diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/PeripheralNames.h b/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/PeripheralNames.h new file mode 100644 index 00000000000..97f5d61cbad --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/PeripheralNames.h @@ -0,0 +1,108 @@ +/* mbed Microcontroller Library + * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PERIPHERALNAMES_H +#define MBED_PERIPHERALNAMES_H + +#include "PinNames.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + SERIAL_0 = 0, + SERIAL_1, + SERIAL_2, + INVALID_SERIAL = (int)NC +} UARTName; + +typedef enum { + ADC_AINA0 = 0, + ADC_AINA1, + ADC_AINA2, + ADC_AINA3, + ADC_AINA4, + ADC_AINA5, + ADC_AINA6, + ADC_AINA7, + ADC_AINA8, + ADC_AINA9, + ADC_AINA10, + ADC_AINA11, + ADC_AINA12, + ADC_AINA13, + ADC_AINA14, + ADC_AINA15, + INVALID_ADC = (int)NC +} ADCName; + +typedef enum { + DAC_A0 = 0, + DAC_A1, + INVALID_DAC = (int)NC +} DACName; + +typedef enum { + SPI_0 = 0, + SPI_1, + INVALID_SPI = (int)NC +} SPIName; + +typedef enum { + I2C_0 = 0, + I2C_1, + I2C_2, + INVALID_I2C = (int)NC +} I2CName; + +typedef enum { + PWM_0 = 0, + PWM_1, + PWM_2, + PWM_3, + PWM_4, + INVALID_PWM = (int)NC +} PWMName; + +typedef enum { + GPIO_IRQ_0 = 0, + GPIO_IRQ_1, + GPIO_IRQ_2, + GPIO_IRQ_3, + GPIO_IRQ_4, + GPIO_IRQ_5, + GPIO_IRQ_6, + GPIO_IRQ_7, + GPIO_IRQ_8, + GPIO_IRQ_9, + GPIO_IRQ_A, + GPIO_IRQ_B, + GPIO_IRQ_C, + GPIO_IRQ_D, + GPIO_IRQ_E, + GPIO_IRQ_F, + INVALID_GPIO_IRQ = (int)NC +} GPIO_IRQName; + +#define STDIO_UART_TX USBTX +#define STDIO_UART_RX USBRX +#define STDIO_UART SERIAL_1 + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/PinNames.h b/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/PinNames.h new file mode 100644 index 00000000000..bd6ad2e6637 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/PinNames.h @@ -0,0 +1,121 @@ +/* mbed Microcontroller Library + * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + PIN_INPUT, + PIN_OUTPUT, + PIN_INOUT +} PinDirection; + +typedef enum { + // TMPM3H6 Pin Names + PA0 = 0 << 3, PA1, PA2, PA3, PA4, PA5, PA6, PA7, + PB0 = 1 << 3, PB1, PB2, PB3, PB4, PB5, PB6, PB7, + PC0 = 2 << 3, PC1, PC2, PC3, PC4, PC5, PC6, + PD0 = 3 << 3, PD1, PD2, PD3, + PE0 = 4 << 3, PE1, PE2, PE3, PE4, PE5, PE6, + PF0 = 5 << 3, PF1, PF2, PF3, PF4, + PG0 = 6 << 3, PG1, + PH0 = 7 << 3, PH1, PH2, PH3, + PJ0 = 8 << 3, PJ1, PJ2, PJ3, PJ4, PJ5, + PK0 = 9 << 3, PK1, PK2, PK3, PK4, PK5, PK6, PK7, + PL0 = 10 << 3, PL1, PL2, PL3, PL4, PL5, PL6, + PM0 = 11 << 3, PM1, PM2, PM3, PM4, PM5, PM6, + PN0 = 12 << 3, PN1, PN2, PN3, PN4,PN5, + PP0 = 13 << 3, PP1, PP2, PP3, + PR0 = 14 << 3, PR1, PR2, PR3, + + // Other mbed Pin Names + LED1 = PB4, + LED2 = PB5, + LED3 = PB6, + LED4 = PB7, + + // external data bus Pin Names + D0 = PL0, + D1 = PL1, + D2 = PJ4, + D3 = PJ3, + D4 = PC4, + D5 = PC3, + D6 = PB3, + D7 = PB2, + D8 = PK1, + D9 = PJ0, + D10 = PL6, + D11 = PP1, + D12 = PP2, + D13 = PP0, + D14 = PA5, + D15 = PA4, + + A0 = PE0, + A1 = PE1, + A2 = PE2, + A3 = PE3, + A4 = PE4, + A5 = PE5, + + DAC0 = PG0, + DAC1 = PG1, + + USBTX = PJ2, + USBRX = PJ1, + + SW1 = PN4, + SW2 = PN3, + SW3 = PN2, + SW4 = PN1, + + // I2C + EEPROM_SDA = PC1, + EEPROM_SCL = PC0, + + // TSPI + MOSI = PP1, + MISO = PP2, + SCLK = PP0, + + // Not connected + NC = (int)0xFFFFFFFF, +} PinName; + +typedef enum { + PullUp = 0, + PullDown, + PullNone, + OpenDrain, + PullDefault +} PinMode; + +typedef enum { + DISABLE = 0, + ENABLE +} FunctionalState; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/PortNames.h b/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/PortNames.h new file mode 100644 index 00000000000..5e91d20ab38 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/PortNames.h @@ -0,0 +1,47 @@ +/* mbed Microcontroller Library + * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PORTNAMES_H +#define MBED_PORTNAMES_H + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + PortA = 0, + PortB, + PortC, + PortD, + PortE, + PortF, + PortG, + PortH, + PortJ, + PortK, + PortL, + PortM, + PortN, + PortP, + PortR, +} PortName; + +#define IS_GPIO_PORT(param) ((param) <= PortR) // parameter checking for port number + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/analogin_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/analogin_api.c new file mode 100644 index 00000000000..a6e354eeee6 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/analogin_api.c @@ -0,0 +1,91 @@ +/* mbed Microcontroller Library + * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "analogin_api.h" +#include "PeripheralNames.h" +#include "pinmap.h" +#include "mbed_wait_api.h" +#include "gpio_include.h" + +static const PinMap PinMap_ADC[] = { + {PD0, ADC_AINA0, PIN_DATA(0, 0)}, + {PD1, ADC_AINA1, PIN_DATA(0, 0)}, + {PD2, ADC_AINA2, PIN_DATA(0, 0)}, + {PD3, ADC_AINA3, PIN_DATA(0, 0)}, + {PE0, ADC_AINA4, PIN_DATA(0, 0)}, + {PE1, ADC_AINA5, PIN_DATA(0, 0)}, + {PE2, ADC_AINA6, PIN_DATA(0, 0)}, + {PE3, ADC_AINA7, PIN_DATA(0, 0)}, + {PE4, ADC_AINA8, PIN_DATA(0, 0)}, + {PE5, ADC_AINA9, PIN_DATA(0, 0)}, + {PE6, ADC_AINA10, PIN_DATA(0, 0)}, + {PF0, ADC_AINA11, PIN_DATA(0, 0)}, + {PF1, ADC_AINA12, PIN_DATA(0, 0)}, + {PF2, ADC_AINA13, PIN_DATA(0, 0)}, + {PF3, ADC_AINA14, PIN_DATA(0, 0)}, + {PF4, ADC_AINA15, PIN_DATA(0, 0)}, + {NC, NC, 0} +}; + +void analogin_init(analogin_t *obj, PinName pin) +{ + // Check that pin belong to ADC module + obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC); + MBED_ASSERT(obj->adc != (ADCName)NC); + + obj->obj = TSB_ADA; + TSB_CG_FSYSENB_IPENB00 = ENABLE; // ADC CG Fsys Enable + pinmap_pinout(pin, PinMap_ADC); // Set pin function as ADC + obj->obj->CLK = ADC_SCLK_1; // Set sample hold time and prescale clock + obj->obj->MOD0 = (ADxMOD0_RCUT_NORMAL | ADxMOD0_DACON_ON); + TSB_CG_SPCLKEN_ADCKEN = ENABLE; // ADC Clock Enable +} + +uint16_t analogin_read_u16(analogin_t *obj) +{ + uint16_t ADCResultValue = 0; + uint32_t ADCResultStored = 0; + + wait_us(3U); // Wait at least 3us to ensure the voltage is stable + obj->obj->CR0 = (ADxCR0_ADEN_DISABLE | ADxCR0_CNT_DISABLE); // Disable Conversion + obj->obj->TSET0 = (ADxTSETn_ENINT_DISABLE | ADxTSETn_TRGS_SGL | obj->adc); // Enable Conversion + obj->obj->CR1 = (ADxCR1_CNTDMEN_DISABLE | ADxCR1_SGLDMEN_DISABLE | + ADxCR1_TRGDMEN_DISABLE | ADxCR1_TRGEN_DISABLE); + obj->obj->CR0 = (ADxCR0_ADEN_ENABLE | ADxCR0_SGL_ENABLE | ADxCR0_CNT_DISABLE); + + while ((obj->obj->ST & ADxST_SNGF_RUN) != ADxST_SNGF_IDLE) { + // Wait until AD conversion complete + } + + wait_us(1U); // Wait for register to update with convert value. + ADCResultStored = obj->obj->REG0; // Convert result + + if ((ADCResultStored & ADxREGn_ADRFn_MASK) == ADxREGn_ADRFn_ON) { + ADCResultValue = (uint16_t)((ADCResultStored & ADxREGn_ADRn_MASK) >> 4); + } + + return ADCResultValue; +} + +float analogin_read(analogin_t *obj) +{ + float result = 0.0; + uint16_t value = 0; + + value = analogin_read_u16(obj); + result = ((float)value * (1.0f / (float)ADC_12BIT_RANGE)); + + return result; +} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/analogout_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/analogout_api.c new file mode 100644 index 00000000000..52f8189666e --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/analogout_api.c @@ -0,0 +1,100 @@ +/* mbed Microcontroller Library + * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "analogout_api.h" +#include "PeripheralNames.h" +#include "pinmap.h" +#include "mbed_wait_api.h" +#include "gpio_include.h" + +static const PinMap PinMap_DAC[] = { + {DAC0, DAC_A0, PIN_DATA(0, 3)}, + {DAC1, DAC_A1, PIN_DATA(0, 3)}, + {NC, NC, 0} +}; + +void analogout_init(dac_t *obj, PinName pin) +{ + obj->dac = (DACName)pinmap_peripheral(pin, PinMap_DAC); // Check that pin belong to DAC module + MBED_ASSERT(obj->dac != (DACName)NC); + + pinmap_pinout(pin, PinMap_DAC); // Set pin function as DAC + TSB_CG_FSYSENA_IPENA06 = ENABLE; + if (obj->dac == DAC_A0) { // Compute handler + obj->handler = TSB_DA0; + TSB_CG_FSYSENB_IPENB01 = ENABLE; + } else { + if (obj->dac == DAC_A1) { + obj->handler = TSB_DA1; + TSB_CG_FSYSENB_IPENB02 = ENABLE; + } else { + obj->handler = NULL; + } + } + obj->handler->CTL = DAC_STOP; +} + +void analogout_free(dac_t *obj) +{ + obj->handler->CTL = DAC_STOP; +} + +void analogout_write(dac_t *obj, float value) +{ + uint8_t outputcode = 0; + + // Enable DAC + obj->handler->CTL = DAC_START; + + if (value < 0.0f) { + value = 0.0f; + } else { + if (value >= 1.0f) { + value = 1.0f; + } + } + + outputcode = (uint8_t)(value * 255.0f); + obj->handler->REG = outputcode; + wait_ms(3); +} + +void analogout_write_u16(dac_t *obj, uint16_t value) +{ + // Enable DAC + obj->handler->CTL = DAC_START; + obj->handler->REG = (uint8_t)(value & 0xFF); + wait_ms(3); +} + +float analogout_read(dac_t *obj) +{ + float result = 0.0; + uint32_t value = 0; + + value = ((obj->handler->REG) & (0xFF)); + result = ((float)value / 255.0f); + + return result; +} + +uint16_t analogout_read_u16(dac_t *obj) +{ + uint16_t value = 0; + + value = (uint16_t)((obj->handler->REG) & (0xFF)); + + return value; +} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/device.h b/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/device.h new file mode 100644 index 00000000000..8c83472d9e4 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/device.h @@ -0,0 +1,23 @@ +/* mbed Microcontroller Library + * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +#define DEVICE_ID_LENGTH 32 + +#include "objects.h" + +#endif diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/device/TMPM3H6.h b/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/device/TMPM3H6.h new file mode 100644 index 00000000000..40a7c8e5388 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/device/TMPM3H6.h @@ -0,0 +1,3145 @@ +/** + ******************************************************************************* + * @file TMPM3H6.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File for the + * TOSHIBA 'TMPM3H6' Device Series + * @version V1.0.9.0 + * $Date:: 2017-12-27 #$ + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved + ******************************************************************************* + */ + +/** @addtogroup TOSHIBA_TXZ_MICROCONTROLLER + * @{ + */ + +/** @addtogroup TMPM3H6 + * @{ + */ + +#ifndef __TMPM3H6_H__ +#define __TMPM3H6_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M3 Processor Exceptions Numbers ***************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ + +/****** TMPM3H6 Specific Interrupt Numbers *******************************************************************/ + INT00_IRQn = 0, /*!< Interrupt Pin0 */ + INT01_IRQn = 1, /*!< Interrupt Pin1 */ + INT02_IRQn = 2, /*!< Interrupt Pin2 */ + INT03_IRQn = 3, /*!< Interrupt Pin3 */ + INT04_IRQn = 4, /*!< Interrupt Pin4 */ + INT05_IRQn = 5, /*!< Interrupt Pin5 */ + INT06_IRQn = 6, /*!< Interrupt Pin6 */ + INT07_IRQn = 7, /*!< Interrupt Pin7 */ + INT08_IRQn = 8, /*!< Interrupt Pin8 */ + INT09_IRQn = 9, /*!< Interrupt Pin9 */ + INT10_IRQn = 10, /*!< Interrupt Pin10 */ + INT11_IRQn = 11, /*!< Interrupt Pin11 */ + INT12_IRQn = 12, /*!< Interrupt Pin12 */ + INT13_IRQn = 13, /*!< Interrupt Pin13 */ + INT14_IRQn = 14, /*!< Interrupt Pin14 */ + INT15_IRQn = 15, /*!< Interrupt Pin15 */ + INTEMG0_IRQn = 16, /*!< PMD0 EMG interrupt */ + INTOVV0_IRQn = 17, /*!< PMD0 OVV interrupt */ + INTPMD0_IRQn = 18, /*!< PMD0 interrupt */ + INTENC00_IRQn = 19, /*!< Encoder 0 interrupt 0 */ + INTENC01_IRQn = 20, /*!< Encoder 0 interrupt 1 */ + INTADAPDA_IRQn = 21, /*!< ADC conversion triggered by PMD is finished A */ + INTADAPDB_IRQn = 22, /*!< ADC conversion triggered by PMD is finished B */ + INTADACP0_IRQn = 23, /*!< ADC conversion monitoring function interrupt 0 */ + INTADACP1_IRQn = 24, /*!< ADC conversion monitoring function interrupt 1 */ + INTADATRG_IRQn = 25, /*!< ADC conversion triggered by General purpose is finished */ + INTADASGL_IRQn = 26, /*!< ADC conversion triggered by Single program is finished */ + INTADACNT_IRQn = 27, /*!< ADC conversion triggered by Continuity program is finished */ + INTT0RX_IRQn = 28, /*!< TSPI/SIO reception (channel 0) */ + INTT0TX_IRQn = 29, /*!< TSPI/SIO transmit (channel 0) */ + INTT0ERR_IRQn = 30, /*!< TSPI/SIO error (channel 0) */ + INTT1RX_IRQn = 31, /*!< TSPI/SIO reception (channel 1) */ + INTT1TX_IRQn = 32, /*!< TSPI/SIO transmit (channel 1) */ + INTT1ERR_IRQn = 33, /*!< TSPI/SIO error (channel 1) */ + INTI2CWUP_IRQn = 34, /*!< Serial bus interface (WakeUp) interrupt (channel 0) */ + INTI2C0_IRQn = 35, /*!< I2C0 transmission and reception interrupt */ + INTI2C0AL_IRQn = 36, /*!< I2C0 arbitration lost interrupt */ + INTI2C0BF_IRQn = 37, /*!< I2C0 bus free interrupt */ + INTI2C0NA_IRQn = 38, /*!< I2C0 no ack interrupt */ + INTI2C1_IRQn = 39, /*!< I2C1 transmission and reception interrupt */ + INTI2C1AL_IRQn = 40, /*!< I2C1 arbitration lost interrupt */ + INTI2C1BF_IRQn = 41, /*!< I2C1 bus free interrupt */ + INTI2C1NA_IRQn = 42, /*!< I2C1 no ack interrupt */ + INTI2C2_IRQn = 43, /*!< I2C2 transmission and reception interrupt */ + INTI2C2AL_IRQn = 44, /*!< I2C2 arbitration lost interrupt */ + INTI2C2BF_IRQn = 45, /*!< I2C2 bus free interrupt */ + INTI2C2NA_IRQn = 46, /*!< I2C2 no ack interrupt */ + INTUART0RX_IRQn = 47, /*!< UART reception (channel 0) */ + INTUART0TX_IRQn = 48, /*!< UART transmit (channel 0) */ + INTUART0ERR_IRQn = 49, /*!< UART error (channel 0) */ + INTUART1RX_IRQn = 50, /*!< UART reception (channel 1) */ + INTUART1TX_IRQn = 51, /*!< UART transmit (channel 1) */ + INTUART1ERR_IRQn = 52, /*!< UART error (channel 1) */ + INTUART2RX_IRQn = 53, /*!< UART reception (channel 2) */ + INTUART2TX_IRQn = 54, /*!< UART transmit (channel 2) */ + INTUART2ERR_IRQn = 55, /*!< UART error (channel 2) */ + INTT32A00A_IRQn = 56, /*!< 32bit T32A00A compare match detection 0 / Over flow / under flow*/ + INTT32A00ACAP0_IRQn = 57, /*!< 32bit T32A00A input capture 0 */ + INTT32A00ACAP1_IRQn = 58, /*!< 32bit T32A00A input capture 1 */ + INTT32A00B_IRQn = 59, /*!< 32bit T32A00B compare match detection 0 / Over flow / under flow*/ + INTT32A00BCAP0_IRQn = 60, /*!< 32bit T32A00B input capture 0 */ + INTT32A00BCAP1_IRQn = 61, /*!< 32bit T32A00B input capture 1 */ + INTT32A00C_IRQn = 62, /*!< 32bit T32A00C compare match detection 0 / Over flow / under flow*/ + INTT32A00CCAP0_IRQn = 63, /*!< 32bit T32A00C input capture 0 */ + INTT32A00CCAP1_IRQn = 64, /*!< 32bit T32A00C input capture 1 */ + INTT32A01A_IRQn = 65, /*!< 32bit T32A01A compare match detection 0 / Over flow / under flow*/ + INTT32A01ACAP0_IRQn = 66, /*!< 32bit T32A01A input capture 0 */ + INTT32A01ACAP1_IRQn = 67, /*!< 32bit T32A01A input capture 1 */ + INTT32A01B_IRQn = 68, /*!< 32bit T32A01B compare match detection 0 / Over flow / under flow*/ + INTT32A01BCAP0_IRQn = 69, /*!< 32bit T32A01B input capture 0 */ + INTT32A01BCAP1_IRQn = 70, /*!< 32bit T32A01B input capture 1 */ + INTT32A01C_IRQn = 71, /*!< 32bit T32A01C compare match detection 0 / Over flow / under flow*/ + INTT32A01CCAP0_IRQn = 72, /*!< 32bit T32A01C input capture 0 */ + INTT32A01CCAP1_IRQn = 73, /*!< 32bit T32A01C input capture 1 */ + INTT32A02A_IRQn = 74, /*!< 32bit T32A02A compare match detection 0 / Over flow / under flow*/ + INTT32A02ACAP0_IRQn = 75, /*!< 32bit T32A02A input capture 0 */ + INTT32A02ACAP1_IRQn = 76, /*!< 32bit T32A02A input capture 1 */ + INTT32A02B_IRQn = 77, /*!< 32bit T32A02B compare match detection 0 / Over flow / under flow*/ + INTT32A02BCAP0_IRQn = 78, /*!< 32bit T32A02B input capture 0 */ + INTT32A02BCAP1_IRQn = 79, /*!< 32bit T32A02B input capture 1 */ + INTT32A02C_IRQn = 80, /*!< 32bit T32A02C compare match detection 0 / Over flow / under flow*/ + INTT32A02CCAP0_IRQn = 81, /*!< 32bit T32A02C input capture 0 */ + INTT32A02CCAP1_IRQn = 82, /*!< 32bit T32A02C input capture 1 */ + INTT32A03A_IRQn = 83, /*!< 32bit T32A03A compare match detection 0 / Over flow / under flow*/ + INTT32A03ACAP0_IRQn = 84, /*!< 32bit T32A03A input capture 0 */ + INTT32A03ACAP1_IRQn = 85, /*!< 32bit T32A03A input capture 1 */ + INTT32A03B_IRQn = 86, /*!< 32bit T32A03B compare match detection 0 / Over flow / under flow*/ + INTT32A03BCAP0_IRQn = 87, /*!< 32bit T32A03B input capture 0 */ + INTT32A03BCAP1_IRQn = 88, /*!< 32bit T32A03B input capture 1 */ + INTT32A03C_IRQn = 89, /*!< 32bit T32A03C compare match detection 0 / Over flow / under flow*/ + INTT32A03CCAP0_IRQn = 90, /*!< 32bit T32A03C input capture 0 */ + INTT32A03CCAP1_IRQn = 91, /*!< 32bit T32A03C input capture 1 */ + INTT32A04A_IRQn = 92, /*!< 32bit T32A04A compare match detection 0 / Over flow / under flow*/ + INTT32A04ACAP0_IRQn = 93, /*!< 32bit T32A04A input capture 0 */ + INTT32A04ACAP1_IRQn = 94, /*!< 32bit T32A04A input capture 1 */ + INTT32A04B_IRQn = 95, /*!< 32bit T32A04B compare match detection 0 / Over flow / under flow*/ + INTT32A04BCAP0_IRQn = 96, /*!< 32bit T32A04B input capture 0 */ + INTT32A04BCAP1_IRQn = 97, /*!< 32bit T32A04B input capture 1 */ + INTT32A04C_IRQn = 98, /*!< 32bit T32A04C compare match detection 0 / Over flow / under flow*/ + INTT32A04CCAP0_IRQn = 99, /*!< 32bit T32A04C input capture 0 */ + INTT32A04CCAP1_IRQn = 100, /*!< 32bit T32A04C input capture 1 */ + INTT32A05A_IRQn = 101, /*!< 32bit T32A05A compare match detection 0 / Over flow / under flow*/ + INTT32A05ACAP0_IRQn = 102, /*!< 32bit T32A05A input capture 0 */ + INTT32A05ACAP1_IRQn = 103, /*!< 32bit T32A05A input capture 1 */ + INTT32A05B_IRQn = 104, /*!< 32bit T32A05B compare match detection 0 / Over flow / under flow*/ + INTT32A05BCAP0_IRQn = 105, /*!< 32bit T32A05B input capture 0 */ + INTT32A05BCAP1_IRQn = 106, /*!< 32bit T32A05B input capture 1 */ + INTT32A05C_IRQn = 107, /*!< 32bit T32A05C compare match detection 0 / Over flow / under flow*/ + INTT32A05CCAP0_IRQn = 108, /*!< 32bit T32A05C input capture 0 */ + INTT32A05CCAP1_IRQn = 109, /*!< 32bit T32A05C input capture 1 */ + INTDMAATC_IRQn = 110, /*!< DMA end of transfer */ + INTDMAAERR_IRQn = 111, /*!< DMA transfer error */ + INTRTC_IRQn = 112, /*!< Real time clock(XHz) interrupt */ + INTRMC0_IRQn = 114, /*!< Remote control reception interrupt */ + INTFLCRDY_IRQn = 115, /*!< Code FLASH Ready interrupt */ + INTFLDRDY_IRQn = 116 /*!< Data FLASH Ready interrupt */ +} IRQn_Type; + +/** Processor and Core Peripheral Section */ + +/* Configuration of the Cortex-M3 Processor and Core Peripherals */ +#define __CM3_REV 0x0201 /*!< Cortex-M3 Core Revision */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 4 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** @} */ /* End of group Configuration_of_CMSIS */ + +#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */ +#include "system_TMPM3H6.h" /* TMPM3Hx System */ + +/** @addtogroup Device_Peripheral_registers + * @{ + */ + +/** Device Specific Peripheral registers structures */ + +/** + * @brief Interrupt control A Register + */ +typedef struct +{ + __IO uint8_t NIC00; /*!< Non makeable Interrupt Control(A) 00 */ + uint8_t RESERVED0[31]; + __IO uint8_t IMC00; /*!< Interrupu Mode Control Register(A) 00 */ + __IO uint8_t IMC01; /*!< Interrupu Mode Control Register(A) 01 */ + __IO uint8_t IMC02; /*!< Interrupu Mode Control Register(A) 02 */ + uint8_t RESERVED1[13]; + __IO uint8_t IMC16; /*!< Interrupu Mode Control Register(A) 16 */ + __IO uint8_t IMC17; /*!< Interrupu Mode Control Register(A) 17 */ +} TSB_IA_TypeDef; + +/** + * @brief Reset LOSC Management register + */ +typedef struct +{ + __IO uint8_t LOSCCR; /*!< Low OSC Control Register */ + __IO uint8_t SHTDNOP; /*!< Power Shut Down Control Register */ + __IO uint8_t RSTFLG0; /*!< Reset flag register 0 */ + __IO uint8_t RSTFLG1; /*!< Reset flag register 1 */ + uint8_t RESERVED0[11]; + __IO uint8_t PROTECT; /*!< Protect Register */ +} TSB_RLM_TypeDef; + +/** + * @brief I2C Wakeup control register + */ +typedef struct +{ + __IO uint8_t WUPCR1; /*!< I2C Wakeup control register1 */ + __IO uint8_t WUPCR2; /*!< I2C Wakeup control register2 */ + __IO uint8_t WUPCR3; /*!< I2C Wakeup control register3 */ + __I uint8_t WUPSL; /*!< I2C Wakeup Status register */ +} TSB_I2CS_TypeDef; + +/** + * @brief LVD0 + */ +typedef struct +{ + __IO uint8_t CR; /*!< LVD Control register */ +} TSB_LVD_TypeDef; + +/** + * @brief DMA Controller + */ +typedef struct +{ + __I uint32_t STATUS; /*!< DMA Status Register */ + __O uint32_t CFG; /*!< DMA Configuration Register */ + __IO uint32_t CTRLBASEPTR; /*!< DMA Control Data Base Pointer Register */ + __I uint32_t ALTCTRLBASEPTR; /*!< DMA Channel Alternate Control Data Base +Pointer Register*/ + uint32_t RESERVED0; + __O uint32_t CHNLSWREQUEST; /*!< DMA Channel Software Request Register */ + __IO uint32_t CHNLUSEBURSTSET; /*!< DMA Channel Useburst Set Register */ + __O uint32_t CHNLUSEBURSTCLR; /*!< DMA Channel Useburst Clear Register */ + __IO uint32_t CHNLREQMASKSET; /*!< DMA Channel Request Mask Set Register */ + __O uint32_t CHNLREQMASKCLR; /*!< DMA Channel Request Mask Clear Register */ + __IO uint32_t CHNLENABLESET; /*!< DMA Channel Enable Set Register */ + __O uint32_t CHNLENABLECLR; /*!< DMA Channel Enable Clear Register */ + __IO uint32_t CHNLPRIALTSET; /*!< DMA Channel Primary-Alternate Set Register */ + __O uint32_t CHNLPRIALTCLR; /*!< DMA Channel Primary-Alternate Clear Register */ + __IO uint32_t CHNLPRIORITYSET; /*!< DMA Channel Priority Set Register */ + __O uint32_t CHNLPRIORITYCLR; /*!< DMA Channel Priority Clear Register */ + uint32_t RESERVED1[3]; + __IO uint32_t ERRCLR; /*!< DMA Bus Error Clear Register */ +} TSB_DMA_TypeDef; + +/** + * @brief Digital analog converter (DAC) + */ +typedef struct +{ + __IO uint32_t CTL; /*!< DAC Control Register */ + __IO uint32_t REG; /*!< DAC output Register */ +} TSB_DA_TypeDef; + +/** + * @brief Serial Interface (TSPI) + */ +typedef struct +{ + __IO uint32_t CR0; /*!< TSPI Control Register 0 */ + __IO uint32_t CR1; /*!< TSPI Control Register 1 */ + __IO uint32_t CR2; /*!< TSPI Control Register 2 */ + __IO uint32_t CR3; /*!< TSPI Control Register 3 */ + __IO uint32_t BR; /*!< TSPI Baud Rate Generator Control Register */ + __IO uint32_t FMTR0; /*!< TSPI Format Control Register 0 */ + __IO uint32_t FMTR1; /*!< TSPI Format Control Register 1 */ + uint32_t RESERVED0[57]; + __IO uint32_t DR; /*!< TSPI Data Register */ + uint32_t RESERVED1[63]; + __IO uint32_t SR; /*!< TSPI Status Register */ + __IO uint32_t ERR; /*!< TSPI Parity Error Flag Register */ +} TSB_TSPI_TypeDef; + +#if defined ( __CC_ARM ) /* RealView Compiler */ +#pragma anon_unions +#elif (defined (__ICCARM__)) /* ICC Compiler */ +#pragma language=extended +#endif + +/** + * @brief I2C + */ +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control Register 1 */ + __IO uint32_t DBR; /*!< I2C Data Buffer Register */ + __IO uint32_t AR; /*!< I2C Bus address Register */ +union { + __O uint32_t CR2; /*!< I2C Control Register 2 */ + __I uint32_t SR; /*!< I2C Status Register */ + }; + __IO uint32_t PRS; /*!< I2C Prescaler clcok setting Register */ + __IO uint32_t IE; /*!< I2C Interrupt Enable Register */ + __IO uint32_t ST; /*!< I2C Interrupt Register */ + __IO uint32_t OP; /*!< I2C Optiononal Function register */ + __I uint32_t PM; /*!< I2C Bus Monitor register */ + __IO uint32_t AR2; /*!< I2C Second Slave address register */ +} TSB_I2C_TypeDef; + +/** + * @brief ADC + */ +typedef struct +{ + __IO uint32_t CR0; /*!< AD Control Register 0 */ + __IO uint32_t CR1; /*!< AD Control Register 1 */ + __I uint32_t ST; /*!< AD Status Register */ + __IO uint32_t CLK; /*!< AD Conversion Clock Setting Register */ + __IO uint32_t MOD0; /*!< AD Mode Control Register 0 */ + __IO uint32_t MOD1; /*!< AD Mode Control Register 1 */ + __IO uint32_t MOD2; /*!< AD Mode Control Register 2 */ + uint32_t RESERVED0; + __IO uint32_t CMPEN; /*!< AD Monitoring interrupt permission register */ + __IO uint32_t CMPCR0; /*!< AD Monitoring Setting Register 0 */ + __IO uint32_t CMPCR1; /*!< AD Monitoring Setting Register 1 */ + __IO uint32_t CMP0; /*!< AD Conversion Result Comparison Register 0 */ + __IO uint32_t CMP1; /*!< AD Conversion Result Comparison Register 1 */ + uint32_t RESERVED1[3]; + __IO uint32_t PSEL0; /*!< AD PMD Trigger Program Number Select Register 0*/ + __IO uint32_t PSEL1; /*!< AD PMD Trigger Program Number Select Register 1*/ + __IO uint32_t PSEL2; /*!< AD PMD Trigger Program Number Select Register 2*/ + __IO uint32_t PSEL3; /*!< AD PMD Trigger Program Number Select Register 3*/ + __IO uint32_t PSEL4; /*!< AD PMD Trigger Program Number Select Register 4*/ + __IO uint32_t PSEL5; /*!< AD PMD Trigger Program Number Select Register 5*/ + __IO uint32_t PSEL6; /*!< AD PMD Trigger Program Number Select Register 6*/ + __IO uint32_t PSEL7; /*!< AD PMD Trigger Program Number Select Register 7*/ + __IO uint32_t PSEL8; /*!< AD PMD Trigger Program Number Select Register 8*/ + __IO uint32_t PSEL9; /*!< AD PMD Trigger Program Number Select Register 9*/ + __IO uint32_t PSEL10; /*!< AD PMD Trigger Program Number Select Register 10*/ + __IO uint32_t PSEL11; /*!< AD PMD Trigger Program Number Select Register 11*/ + __IO uint32_t PINTS0; /*!< AD PMD Trigger Interrupt Select Register 0 */ + __IO uint32_t PINTS1; /*!< AD PMD Trigger Interrupt Select Register 1 */ + __IO uint32_t PINTS2; /*!< AD PMD Trigger Interrupt Select Register 2 */ + __IO uint32_t PINTS3; /*!< AD PMD Trigger Interrupt Select Register 3 */ + __IO uint32_t PINTS4; /*!< AD PMD Trigger Interrupt Select Register 4 */ + __IO uint32_t PINTS5; /*!< AD PMD Trigger Interrupt Select Register 5 */ + __IO uint32_t PINTS6; /*!< AD PMD Trigger Interrupt Select Register 6 */ + __IO uint32_t PINTS7; /*!< AD PMD Trigger Interrupt Select Register 7 */ + __IO uint32_t PREGS; /*!< AD PMD Trigger Conversion Result Storage Select Register*/ + uint32_t RESERVED2[3]; + __IO uint32_t PSET0; /*!< AD PMD Trigger Program Register 0 */ + __IO uint32_t PSET1; /*!< AD PMD Trigger Program Register 1 */ + __IO uint32_t PSET2; /*!< AD PMD Trigger Program Register 2 */ + __IO uint32_t PSET3; /*!< AD PMD Trigger Program Register 3 */ + __IO uint32_t PSET4; /*!< AD PMD Trigger Program Register 4 */ + __IO uint32_t PSET5; /*!< AD PMD Trigger Program Register 5 */ + __IO uint32_t PSET6; /*!< AD PMD Trigger Program Register 6 */ + __IO uint32_t PSET7; /*!< AD PMD Trigger Program Register 7 */ + __IO uint32_t TSET0; /*!< AD General purpose Trigger Program Register 0*/ + __IO uint32_t TSET1; /*!< AD General purpose Trigger Program Register 1*/ + __IO uint32_t TSET2; /*!< AD General purpose Trigger Program Register 2*/ + __IO uint32_t TSET3; /*!< AD General purpose Trigger Program Register 3*/ + __IO uint32_t TSET4; /*!< AD General purpose Trigger Program Register 4*/ + __IO uint32_t TSET5; /*!< AD General purpose Trigger Program Register 5*/ + __IO uint32_t TSET6; /*!< AD General purpose Trigger Program Register 6*/ + __IO uint32_t TSET7; /*!< AD General purpose Trigger Program Register 7*/ + __IO uint32_t TSET8; /*!< AD General purpose Trigger Program Register 8*/ + __IO uint32_t TSET9; /*!< AD General purpose Trigger Program Register 9*/ + __IO uint32_t TSET10; /*!< AD General purpose Trigger Program Register 10*/ + __IO uint32_t TSET11; /*!< AD General purpose Trigger Program Register 11*/ + __IO uint32_t TSET12; /*!< AD General purpose Trigger Program Register 12*/ + __IO uint32_t TSET13; /*!< AD General purpose Trigger Program Register 13*/ + __IO uint32_t TSET14; /*!< AD General purpose Trigger Program Register 14*/ + __IO uint32_t TSET15; /*!< AD General purpose Trigger Program Register 15*/ + __IO uint32_t TSET16; /*!< AD General purpose Trigger Program Register 16*/ + __IO uint32_t TSET17; /*!< AD General purpose Trigger Program Register 17*/ + __IO uint32_t TSET18; /*!< AD General purpose Trigger Program Register 18*/ + __IO uint32_t TSET19; /*!< AD General purpose Trigger Program Register 19*/ + __IO uint32_t TSET20; /*!< AD General purpose Trigger Program Register 20*/ + __IO uint32_t TSET21; /*!< AD General purpose Trigger Program Register 21*/ + __IO uint32_t TSET22; /*!< AD General purpose Trigger Program Register 22*/ + __IO uint32_t TSET23; /*!< AD General purpose Trigger Program Register 23*/ + uint32_t RESERVED3[8]; + __I uint32_t REG0; /*!< AD AD Conversion Result Register 0 */ + __I uint32_t REG1; /*!< AD Conversion Result Register 1 */ + __I uint32_t REG2; /*!< AD Conversion Result Register 2 */ + __I uint32_t REG3; /*!< AD Conversion Result Register 3 */ + __I uint32_t REG4; /*!< AD Conversion Result Register 4 */ + __I uint32_t REG5; /*!< AD Conversion Result Register 5 */ + __I uint32_t REG6; /*!< AD Conversion Result Register 6 */ + __I uint32_t REG7; /*!< AD Conversion Result Register 7 */ + __I uint32_t REG8; /*!< AD Conversion Result Register 8 */ + __I uint32_t REG9; /*!< AD Conversion Result Register 9 */ + __I uint32_t REG10; /*!< AD Conversion Result Register 10 */ + __I uint32_t REG11; /*!< AD Conversion Result Register 11 */ + __I uint32_t REG12; /*!< AD Conversion Result Register 12 */ + __I uint32_t REG13; /*!< AD Conversion Result Register 13 */ + __I uint32_t REG14; /*!< AD Conversion Result Register 14 */ + __I uint32_t REG15; /*!< AD Conversion Result Register 15 */ + __I uint32_t REG16; /*!< AD Conversion Result Register 16 */ + __I uint32_t REG17; /*!< AD Conversion Result Register 17 */ + __I uint32_t REG18; /*!< AD Conversion Result Register 18 */ + __I uint32_t REG19; /*!< AD Conversion Result Register 19 */ + __I uint32_t REG20; /*!< AD Conversion Result Register 20 */ + __I uint32_t REG21; /*!< AD Conversion Result Register 21 */ + __I uint32_t REG22; /*!< AD Conversion Result Register 22 */ + __I uint32_t REG23; /*!< AD Conversion Result Register 23 */ +} TSB_AD_TypeDef; + +/** + * @brief T32A + */ +typedef struct +{ + __IO uint32_t MOD; /*!< T32A Mode Register */ + uint32_t RESERVED0[15]; + __IO uint32_t RUNA; /*!< T32A Run Register A */ + __IO uint32_t CRA; /*!< T32A Counter control Register A */ + __IO uint32_t CAPCRA; /*!< T32A Capture control Register A */ + __IO uint32_t OUTCRA0; /*!< T32A Output control Register A0 */ + __IO uint32_t OUTCRA1; /*!< T32A Output control Register A1 */ + __IO uint32_t STA; /*!< T32A Status Register A */ + __IO uint32_t IMA; /*!< T32A Interrupt mask Register A */ + __I uint32_t TMRA; /*!< T32A Counter capture Register A */ + __IO uint32_t RELDA; /*!< T32A Counter Reload Register A */ + __IO uint32_t RGA0; /*!< T32A Timer Register A0 */ + __IO uint32_t RGA1; /*!< T32A Timer Register A1 */ + __I uint32_t CAPA0; /*!< T32A Timer capturer A0 */ + __I uint32_t CAPA1; /*!< T32A Timer capturer A1 */ + __IO uint32_t DMAA; /*!< T32A DMA Request Enabl eRegister A */ + uint32_t RESERVED1[2]; + __IO uint32_t RUNB; /*!< T32A Run Register B */ + __IO uint32_t CRB; /*!< T32A Counter control Register B */ + __IO uint32_t CAPCRB; /*!< T32A Capture control Register B */ + __IO uint32_t OUTCRB0; /*!< T32A Output control Register B0 */ + __IO uint32_t OUTCRB1; /*!< T32A Output control Register B1 */ + __IO uint32_t STB; /*!< T32A Status Register B */ + __IO uint32_t IMB; /*!< T32A Interrupt mask Register B */ + __I uint32_t TMRB; /*!< T32A Counter capture Register B */ + __IO uint32_t RELDB; /*!< T32A Counter Reload Register B */ + __IO uint32_t RGB0; /*!< T32A Timer Register B0 */ + __IO uint32_t RGB1; /*!< T32A Timer Register B1 */ + __I uint32_t CAPB0; /*!< T32A Timer capturer B0 */ + __I uint32_t CAPB1; /*!< T32A Timer capturer B1 */ + __IO uint32_t DMAB; /*!< T32A DMA Request Enable Register B */ + uint32_t RESERVED2[2]; + __IO uint32_t RUNC; /*!< T32A Run Register C */ + __IO uint32_t CRC; /*!< T32A Counter control Register C */ + __IO uint32_t CAPCRC; /*!< T32A Capture control Register C */ + __IO uint32_t OUTCRC0; /*!< T32A Output control Register C0 */ + __IO uint32_t OUTCRC1; /*!< T32A Output control Register C1 */ + __IO uint32_t STC; /*!< T32A Status Register C */ + __IO uint32_t IMC; /*!< T32A Interrupt mask Register C */ + __I uint32_t TMRC; /*!< T32A Counter capture Register C */ + __IO uint32_t RELDC; /*!< T32A Counter Reload Register C */ + __IO uint32_t RGC0; /*!< T32A Timer Register C0 */ + __IO uint32_t RGC1; /*!< T32A Timer Register C1 */ + __I uint32_t CAPC0; /*!< T32A Timer capturer C0 */ + __I uint32_t CAPC1; /*!< T32A Timer capturer C1 */ + __IO uint32_t DMAC; /*!< T32A DMA Request Enabl eRegister C */ + __IO uint32_t PLSCR; /*!< T32A Pulse count control register */ +} TSB_T32A_TypeDef; + +/** + * @brief UART + */ +typedef struct +{ + __IO uint32_t SWRST; /*!< UART Software reset register */ + __IO uint32_t CR0; /*!< UART Control register 0 */ + __IO uint32_t CR1; /*!< UART Control register 1 */ + __IO uint32_t CLK; /*!< UART Clock Control register */ + __IO uint32_t BRD; /*!< UART Baud rate register */ + __IO uint32_t TRANS; /*!< UART Transfer enable register */ + __IO uint32_t DR; /*!< UART Data register */ + __IO uint32_t SR; /*!< UART Status register */ + __IO uint32_t FIFOCLR; /*!< UART FIFO Clear register */ + __IO uint32_t ERR; /*!< UART Error register */ +} TSB_UART_TypeDef; + +/** + * @brief SIWD + */ +typedef struct +{ + __IO uint32_t PRO; /*!< SIWD Protect register */ + __IO uint32_t EN; /*!< SIWD Enable register */ + __O uint32_t CR; /*!< SIWD Control register */ + __IO uint32_t MOD; /*!< SIWD Mode register */ + __I uint32_t MONI; /*!< SIWD Monitor register */ + __IO uint32_t OSCCR; /*!< SIWD Oscillation control register */ +} TSB_SIWD_TypeDef; + +/** + * @brief DNF + */ +typedef struct +{ + __IO uint32_t CKCR; /*!< DNF clock Control register */ + __IO uint32_t ENCR; /*!< DNF Enable register */ +} TSB_DNF_TypeDef; + +/** + * @brief TRGSEL + */ +typedef struct +{ + __IO uint32_t CR0; /*!< TRGSEL Control register 0 */ + __IO uint32_t CR1; /*!< TRGSEL Control register 1 */ + __IO uint32_t CR2; /*!< TSEL Control register 2 */ + __IO uint32_t CR3; /*!< TRGSEL Control register 3 */ + __IO uint32_t CR4; /*!< TRGSEL Control register 4 */ + __IO uint32_t CR5; /*!< TRGSEL Control register 5 */ + __IO uint32_t CR6; /*!< TRGSEL Control register 6 */ + __IO uint32_t CR7; /*!< TRGSEL Control register 7 */ + __IO uint32_t CR8; /*!< TRGSEL Control register 8 */ + __IO uint32_t CR9; /*!< TRGSEL Control register 9 */ + __IO uint32_t CR10; /*!< TRGSEL Control register 10 */ +} TSB_TSEL_TypeDef; + +/** + * @brief Port A + */ +typedef struct +{ + __IO uint32_t DATA; /*!< PA Data Register */ + __IO uint32_t CR; /*!< PA Control Register */ + __IO uint32_t FR1; /*!< PA Function Register 1 */ + __IO uint32_t FR2; /*!< PA Function Register 2 */ + __IO uint32_t FR3; /*!< PA Function Register 3 */ + __IO uint32_t FR4; /*!< PA Function Register 4 */ + __IO uint32_t FR5; /*!< PA Function Register 5 */ + __IO uint32_t FR6; /*!< PA Function Register 6 */ + uint32_t RESERVED0[2]; + __IO uint32_t OD; /*!< PA Open Drain Control Register */ + __IO uint32_t PUP; /*!< PA Pull-up Control Register */ + __IO uint32_t PDN; /*!< PB Pull-Down Control Register */ + uint32_t RESERVED1; + __IO uint32_t IE; /*!< PA Input Enable Control Register */ +} TSB_PA_TypeDef; + +/** + * @brief Port B + */ +typedef struct +{ + __IO uint32_t DATA; /*!< PB Data Register */ + __IO uint32_t CR; /*!< PB Control Register */ + __IO uint32_t FR1; /*!< PB Function Register 1 */ + __IO uint32_t FR2; /*!< PB Function Register 2 */ + __IO uint32_t FR3; /*!< PB Function Register 3 */ + __IO uint32_t FR4; /*!< PB Function Register 4 */ + __IO uint32_t FR5; /*!< PB Function Register 5 */ + __IO uint32_t FR6; /*!< PB Function Register 6 */ + uint32_t RESERVED0[2]; + __IO uint32_t OD; /*!< PB Open Drain Control Register */ + __IO uint32_t PUP; /*!< PB Pull-up Control Register */ + __IO uint32_t PDN; /*!< PB Pull-Down Control Register */ + uint32_t RESERVED1; + __IO uint32_t IE; /*!< PB Input Enable Control Register */ +} TSB_PB_TypeDef; + +/** + * @brief Port C + */ +typedef struct +{ + __IO uint32_t DATA; /*!< PC Data Register */ + __IO uint32_t CR; /*!< PC Control Register */ + __IO uint32_t FR1; /*!< PC Function Register 1 */ + uint32_t RESERVED0; + __IO uint32_t FR3; /*!< PC Function Register 3 */ + __IO uint32_t FR4; /*!< PC Function Register 4 */ + __IO uint32_t FR5; /*!< PC Function Register 5 */ + uint32_t RESERVED1[3]; + __IO uint32_t OD; /*!< PC Open Drain Control Register */ + __IO uint32_t PUP; /*!< PC Pull-up Control Register */ + __IO uint32_t PDN; /*!< PC Pull-Down Control Register */ + uint32_t RESERVED2; + __IO uint32_t IE; /*!< PC Input Enable Control Register */ +} TSB_PC_TypeDef; + +/** + * @brief Port D + */ +typedef struct +{ + __IO uint32_t DATA; /*!< PD Data Register */ + __IO uint32_t CR; /*!< PD Control Register */ + uint32_t RESERVED0[8]; + __IO uint32_t OD; /*!< PD Open Drain Control Register */ + __IO uint32_t PUP; /*!< PD Pull-up Control Register */ + __IO uint32_t PDN; /*!< PD Pull-Down Control Register */ + uint32_t RESERVED1; + __IO uint32_t IE; /*!< PD Input Enable Control Register */ +} TSB_PD_TypeDef; + +/** + * @brief Port E + */ +typedef struct +{ + __IO uint32_t DATA; /*!< PE Data Register */ + __IO uint32_t CR; /*!< PE Control Register */ + uint32_t RESERVED0[8]; + __IO uint32_t OD; /*!< PE Open Drain Control Register */ + __IO uint32_t PUP; /*!< PE Pull-up Control Register */ + __IO uint32_t PDN; /*!< PE Pull-Down Control Register */ + uint32_t RESERVED1; + __IO uint32_t IE; /*!< PE Input Enable Control Register */ +} TSB_PE_TypeDef; + +/** + * @brief + */ +typedef struct +{ + __IO uint32_t DATA; /*!< PF Data Register */ + __IO uint32_t CR; /*!< PF Control Register */ + uint32_t RESERVED0[8]; + __IO uint32_t OD; /*!< PF Open Drain Control Register */ + __IO uint32_t PUP; /*!< PF Pull-up Control Register */ + __IO uint32_t PDN; /*!< PF Pull-Down Control Register */ + uint32_t RESERVED1; + __IO uint32_t IE; /*!< PF Input Enable Control Register */ +} TSB_PF_TypeDef; + +/** + * @brief + */ +typedef struct +{ + __IO uint32_t DATA; /*!< PG Data Register */ + __IO uint32_t CR; /*!< PG Control Register */ + uint32_t RESERVED0[8]; + __IO uint32_t OD; /*!< PG Open Drain Control Register */ + __IO uint32_t PUP; /*!< PG Pull-up Control Register */ + __IO uint32_t PDN; /*!< PG Pull-Down Control Register */ + uint32_t RESERVED1; + __IO uint32_t IE; /*!< PG Input Enable Control Register */ +} TSB_PG_TypeDef; + +/** + * @brief + */ +typedef struct +{ + __IO uint32_t DATA; /*!< PH Data Register */ + uint32_t RESERVED0[11]; + __IO uint32_t PDN; /*!< PH Pull-Down Control Register */ + uint32_t RESERVED1; + __IO uint32_t IE; /*!< PH Input Enable Control Register */ +} TSB_PH_TypeDef; + +/** + * @brief + */ +typedef struct +{ + __IO uint32_t DATA; /*!< PJ Data Register */ + __IO uint32_t CR; /*!< PJ Control Register */ + __IO uint32_t FR1; /*!< PJ Function Register 1 */ + __IO uint32_t FR2; /*!< PJ Function Register 2 */ + __IO uint32_t FR3; /*!< PJ Function Register 3 */ + __IO uint32_t FR4; /*!< PJ Function Register 4 */ + __IO uint32_t FR5; /*!< PJ Function Register 5 */ + uint32_t RESERVED0[3]; + __IO uint32_t OD; /*!< PJ Open Drain Control Register */ + __IO uint32_t PUP; /*!< PJ Pull-up Control Register */ + __IO uint32_t PDN; /*!< PJ Pull-Down Control Register */ + uint32_t RESERVED1; + __IO uint32_t IE; /*!< PJ Input Enable Control Register */ +} TSB_PJ_TypeDef; + +/** + * @brief + */ +typedef struct +{ + __IO uint32_t DATA; /*!< PK Data Register */ + __IO uint32_t CR; /*!< PK Control Register */ + __IO uint32_t FR1; /*!< PK Function Register 1 */ + __IO uint32_t FR2; /*!< PK Function Register 2 */ + __IO uint32_t FR3; /*!< PK Function Register 3 */ + __IO uint32_t FR4; /*!< PK Function Register 4 */ + __IO uint32_t FR5; /*!< PK Function Register 5 */ + uint32_t RESERVED0[3]; + __IO uint32_t OD; /*!< PK Open Drain Control Register */ + __IO uint32_t PUP; /*!< PK Pull-up Control Register */ + __IO uint32_t PDN; /*!< PK Pull-Down Control Register */ + uint32_t RESERVED1; + __IO uint32_t IE; /*!< PK Input Enable Control Register */ +} TSB_PK_TypeDef; + +/** + * @brief + */ +typedef struct +{ + __IO uint32_t DATA; /*!< PL Data Register */ + __IO uint32_t CR; /*!< PL Control Register */ + __IO uint32_t FR1; /*!< PL Function Register 1 */ + __IO uint32_t FR2; /*!< PL Function Register 2 */ + __IO uint32_t FR3; /*!< PL Function Register 3 */ + uint32_t RESERVED0[5]; + __IO uint32_t OD; /*!< PL Open Drain Control Register */ + __IO uint32_t PUP; /*!< PL Pull-up Control Register */ + __IO uint32_t PDN; /*!< PL Pull-Down Control Register */ + uint32_t RESERVED1; + __IO uint32_t IE; /*!< PL Input Enable Control Register */ +} TSB_PL_TypeDef; + +/** + * @brief + */ +typedef struct +{ + __IO uint32_t DATA; /*!< PM Data Register */ + __IO uint32_t CR; /*!< PM Control Register */ + __IO uint32_t FR1; /*!< PM Function Register 1 */ + __IO uint32_t FR2; /*!< PM Function Register 2 */ + __IO uint32_t FR3; /*!< PM Function Register 3 */ + __IO uint32_t FR4; /*!< PM Function Register 4 */ + __IO uint32_t FR5; /*!< PM Function Register 5 */ + __IO uint32_t FR6; /*!< PM Function Register 6 */ + uint32_t RESERVED0[2]; + __IO uint32_t OD; /*!< PM Open Drain Control Register */ + __IO uint32_t PUP; /*!< PM Pull-up Control Register */ + __IO uint32_t PDN; /*!< PM Pull-Down Control Register */ + uint32_t RESERVED1; + __IO uint32_t IE; /*!< PM Input Enable Control Register */ +} TSB_PM_TypeDef; + +/** + * @brief + */ +typedef struct +{ + __IO uint32_t DATA; /*!< PN Data Register */ + __IO uint32_t CR; /*!< PN Control Register */ + uint32_t RESERVED0[2]; + __IO uint32_t FR3; /*!< PN Function Register 3 */ + __IO uint32_t FR4; /*!< PN Function Register 4 */ + __IO uint32_t FR5; /*!< PN Function Register 5 */ + uint32_t RESERVED1[3]; + __IO uint32_t OD; /*!< PN Open Drain Control Register */ + __IO uint32_t PUP; /*!< PN Pull-up Control Register */ + __IO uint32_t PDN; /*!< PN Pull-Down Control Register */ + uint32_t RESERVED2; + __IO uint32_t IE; /*!< PN Input Enable Control Register */ +} TSB_PN_TypeDef; + +/** + * @brief + */ +typedef struct +{ + __IO uint32_t DATA; /*!< PP Data Register */ + __IO uint32_t CR; /*!< PP Control Register */ + __IO uint32_t FR1; /*!< PP Function Register 1 */ + uint32_t RESERVED0; + __IO uint32_t FR3; /*!< PP Function Register 3 */ + __IO uint32_t FR4; /*!< PP Function Register 4 */ + uint32_t RESERVED1[4]; + __IO uint32_t OD; /*!< PP Open Drain Control Register */ + __IO uint32_t PUP; /*!< PP Pull-up Control Register */ + __IO uint32_t PDN; /*!< PP Pull-Down Control Register */ + uint32_t RESERVED2; + __IO uint32_t IE; /*!< PP Input Enable Control Register */ +} TSB_PP_TypeDef; + +/** + * @brief + */ +typedef struct +{ + __IO uint32_t DATA; /*!< PR Data Register */ + __IO uint32_t CR; /*!< PR Control Register */ + uint32_t RESERVED0[2]; + __IO uint32_t FR3; /*!< PR Function Register 3 */ + __IO uint32_t FR4; /*!< PR Function Register 4 */ + uint32_t RESERVED1[4]; + __IO uint32_t OD; /*!< PR Open Drain Control Register */ + __IO uint32_t PUP; /*!< PR Pull-up Control Register */ + __IO uint32_t PDN; /*!< PR Pull-Down Control Register */ + uint32_t RESERVED2; + __IO uint32_t IE; /*!< PR Input Enable Control Register */ +} TSB_PR_TypeDef; + +/** + * @brief + */ +typedef struct +{ + __IO uint8_t SECR; /*!< RTC Sec setting register */ + __IO uint8_t MINR; /*!< RTC Min settging register */ + __IO uint8_t HOURR; /*!< RTC Hour setting register */ + uint8_t RESERVED0; + __IO uint8_t DAYR; /*!< RTC Day setting register */ + __IO uint8_t DATER; /*!< RTC Date setting register */ + __IO uint8_t MONTHR; /*!< RTC Month settging register PAGE0 */ + __IO uint8_t YEARR; /*!< RTC Year setting register PAGE0 */ + __IO uint8_t PAGER; /*!< RTC Page register */ + uint8_t RESERVED1[3]; + __IO uint8_t RESTR; /*!< RTC Reset register */ + uint8_t RESERVED2; + __IO uint8_t PROTECT; /*!< RTC protect register */ + __IO uint8_t ADJCTL; /*!< RTC clock adjust control register */ + __IO uint8_t ADJDAT; /*!< RTC clock adjust data register */ +} TSB_RTC_TypeDef; + +/** + * @brief + */ +typedef struct +{ + __IO uint32_t EN; /*!< RMC Enable Register */ + __IO uint32_t REN; /*!< RMC Receive Enable Register */ + __I uint32_t RBUF1; /*!< RMC Receive Data Buffer Register 1 */ + __I uint32_t RBUF2; /*!< RMC Receive Data Buffer Register 2 */ + __I uint32_t RBUF3; /*!< RMC Receive Data Buffer Register 3 */ + __IO uint32_t RCR1; /*!< RMC Receive Control Register 1 */ + __IO uint32_t RCR2; /*!< RMC Receive Control Register 2 */ + __IO uint32_t RCR3; /*!< RMC Receive Control Register 3 */ + __IO uint32_t RCR4; /*!< RMC Receive Control Register 4 */ + __I uint32_t RSTAT; /*!< RMC Receive Status Register */ + __IO uint32_t END1; /*!< RMC Receive End Bit Number Register 1 */ + __IO uint32_t END2; /*!< RMC Receive End Bit Number Register 2 */ + __IO uint32_t END3; /*!< RMC Receive End Bit Number Register 3 */ + __IO uint32_t FSSEL; /*!< RMC Frequency Selection Register */ +} TSB_RMC_TypeDef; + +/** + * @brief + */ +typedef struct +{ + __IO uint32_t CR1; /*!< OFD Control Register 1 */ + __IO uint32_t CR2; /*!< OFD Control Register 2 */ + __IO uint32_t MN0; /*!< OFD Lower Detection Frequency Setting Register0*/ + __IO uint32_t MN1; /*!< OFD Lower Detection Frequency Setting Register1*/ + __IO uint32_t MX0; /*!< OFD Higher Detection Frequency Setting Register0*/ + __IO uint32_t MX1; /*!< OFD Higher Detection Frequency Setting Register1*/ + __IO uint32_t RST; /*!< OFD Reset Enable Control Register */ + __I uint32_t STAT; /*!< OFD Status Register */ + __IO uint32_t MON; /*!< OFD External high frequency oscillaion clock monitor register */ +} TSB_OFD_TypeDef; + +/** + * @brief + */ +typedef struct +{ + __IO uint32_t PROTECT; /*!< CG Protect Register */ + __IO uint32_t OSCCR; /*!< CG Oscillation Control Register */ + __IO uint32_t SYSCR; /*!< CG System clock control register */ + __IO uint32_t STBYCR; /*!< CG Standby Control Register */ + __IO uint32_t SCOCR; /*!< CG SCOUT Control Register */ + uint32_t RESERVED0[3]; + __IO uint32_t PLL0SEL; /*!< CG PLL select register for fsys */ + uint32_t RESERVED1[3]; + __IO uint32_t WUPHCR; /*!< CG Warmup register for HOSC */ + __IO uint32_t WUPLCR; /*!< CG Low-speed oscillation warm-up register */ + uint32_t RESERVED2[6]; + __IO uint32_t FSYSENA; /*!< CG output control register A for fsys clock */ + __IO uint32_t FSYSENB; /*!< CG output control register B for fsys clock */ + uint32_t RESERVED3; + __IO uint32_t SPCLKEN; /*!< CG Output control register for ADC AND TRACE CLOCK*/ +} TSB_CG_TypeDef; + +/** + * @brief + */ +typedef struct +{ + __IO uint32_t OSCPRO; /*!< TRM Protect register */ + __IO uint32_t OSCEN; /*!< TRM Enable register */ + __I uint32_t OSCINIT; /*!< TRM Initial trimming level monitor register */ + __IO uint32_t OSCSET; /*!< TRM Trimming level setting register */ +} TSB_TRM_TypeDef; + +/** + * @brief Interrupt control register B + */ +typedef struct +{ + uint8_t RESERVED0[16]; + __IO uint8_t NIC00; /*!< Non makeable Interrupt Control(B) 00 */ + uint8_t RESERVED1[79]; + __IO uint8_t IMC000; /*!< Interrupu Mode Control Register(B) 000 */ + __IO uint8_t IMC001; /*!< Interrupu Mode Control Register(B) 001 */ + __IO uint8_t IMC002; /*!< Interrupu Mode Control Register(B) 002 */ + __IO uint8_t IMC003; /*!< Interrupu Mode Control Register(B) 003 */ + __IO uint8_t IMC004; /*!< Interrupu Mode Control Register(B) 004 */ + __IO uint8_t IMC005; /*!< Interrupu Mode Control Register(B) 005 */ + __IO uint8_t IMC006; /*!< Interrupu Mode Control Register(B) 006 */ + __IO uint8_t IMC007; /*!< Interrupu Mode Control Register(B) 007 */ + __IO uint8_t IMC008; /*!< Interrupu Mode Control Register(B) 008 */ + __IO uint8_t IMC009; /*!< Interrupu Mode Control Register(B) 009 */ + __IO uint8_t IMC010; /*!< Interrupu Mode Control Register(B) 010 */ + __IO uint8_t IMC011; /*!< Interrupu Mode Control Register(B) 011 */ + __IO uint8_t IMC012; /*!< Interrupu Mode Control Register(B) 012 */ + __IO uint8_t IMC013; /*!< Interrupu Mode Control Register(B) 013 */ + __IO uint8_t IMC014; /*!< Interrupu Mode Control Register(B) 014 */ + __IO uint8_t IMC015; /*!< Interrupu Mode Control Register(B) 015 */ + __IO uint8_t IMC016; /*!< Interrupu Mode Control Register(B) 016 */ + __IO uint8_t IMC017; /*!< Interrupu Mode Control Register(B) 017 */ + __IO uint8_t IMC018; /*!< Interrupu Mode Control Register(B) 018 */ + __IO uint8_t IMC019; /*!< Interrupu Mode Control Register(B) 019 */ + __IO uint8_t IMC020; /*!< Interrupu Mode Control Register(B) 020 */ + __IO uint8_t IMC021; /*!< Interrupu Mode Control Register(B) 021 */ + __IO uint8_t IMC022; /*!< Interrupu Mode Control Register(B) 022 */ + __IO uint8_t IMC023; /*!< Interrupu Mode Control Register(B) 023 */ + __IO uint8_t IMC024; /*!< Interrupu Mode Control Register(B) 024 */ + __IO uint8_t IMC025; /*!< Interrupu Mode Control Register(B) 025 */ + __IO uint8_t IMC026; /*!< Interrupu Mode Control Register(B) 026 */ + __IO uint8_t IMC027; /*!< Interrupu Mode Control Register(B) 027 */ + __IO uint8_t IMC028; /*!< Interrupu Mode Control Register(B) 028 */ + __IO uint8_t IMC029; /*!< Interrupu Mode Control Register(B) 029 */ + __IO uint8_t IMC030; /*!< Interrupu Mode Control Register(B) 030 */ + __IO uint8_t IMC031; /*!< Interrupu Mode Control Register(B) 031 */ + __IO uint8_t IMC032; /*!< Interrupu Mode Control Register(B) 032 */ + __IO uint8_t IMC033; /*!< Interrupt Mode Control Register(B) 033 */ + __IO uint8_t IMC034; /*!< Interrupt Mode Control Register(B) 034 */ + __IO uint8_t IMC035; /*!< Interrupt Mode Control Register(B) 035 */ + __IO uint8_t IMC036; /*!< Interrupt Mode Control Register(B) 036 */ + __IO uint8_t IMC037; /*!< Interrupt Mode Control Register(B) 037 */ + __IO uint8_t IMC038; /*!< Interrupt Mode Control Register(B) 038 */ + __IO uint8_t IMC039; /*!< Interrupt Mode Control Register(B) 039 */ + __IO uint8_t IMC040; /*!< Interrupt Mode Control Register(B) 040 */ + __IO uint8_t IMC041; /*!< Interrupt Mode Control Register(B) 041 */ + __IO uint8_t IMC042; /*!< Interrupt Mode Control Register(B) 042 */ + __IO uint8_t IMC043; /*!< Interrupt Mode Control Register(B) 043 */ + __IO uint8_t IMC044; /*!< Interrupt Mode Control Register(B) 044 */ + __IO uint8_t IMC045; /*!< Interrupt Mode Control Register(B) 045 */ + __IO uint8_t IMC046; /*!< Interrupu Mode Control Register(B) 046 */ +} TSB_IB_TypeDef; + +/** + * @brief + */ +typedef struct +{ + __I uint32_t FLGNMI; /*!< Interrupt Monitor Flag 0 */ + __I uint32_t FLG1; /*!< Interrupt Monitor Flag 1 */ + uint32_t RESERVED0; + __I uint32_t FLG3; /*!< Interrupt Monitor Flag 3 */ + __I uint32_t FLG4; /*!< NMI Interrupt Monitor Flag 4 */ +} TSB_IMN_TypeDef; + +/** + * @brief + */ +typedef struct +{ + __IO uint32_t MDEN; /*!< PMD Enable Register */ + __IO uint32_t PORTMD; /*!< PMD Port Output Mode Register */ + __IO uint32_t MDCR; /*!< PMD Control Register */ + __I uint32_t CNTSTA; /*!< PMD PWM Counter Status Register */ + __I uint32_t MDCNT; /*!< PMD PWM Counter Register */ + __IO uint32_t MDPRD; /*!< PMD PWM Period Register */ + __IO uint32_t CMPU; /*!< PMD PWM Compare U Register */ + __IO uint32_t CMPV; /*!< PMD PWM Compare V Register */ + __IO uint32_t CMPW; /*!< PMD PWM Compare W Register */ + uint32_t RESERVED0; + __IO uint32_t MDOUT; /*!< PMD Conduction Control Register */ + __IO uint32_t MDPOT; /*!< PMD Output Setting Register */ + __O uint32_t EMGREL; /*!< PMD EMG Release Register */ + __IO uint32_t EMGCR; /*!< PMD EMG Control Register */ + __I uint32_t EMGSTA; /*!< PMD EMG Status Register */ + __IO uint32_t OVVCR; /*!< PMD OVV Control Register */ + __I uint32_t OVVSTA; /*!< PMD OVV Status Register */ + __IO uint32_t DTR; /*!< PMD Dead Time Register */ + __IO uint32_t TRGCMP0; /*!< PMD Trigger Compare Register 0 */ + __IO uint32_t TRGCMP1; /*!< PMD Trigger Compare Register 1 */ + __IO uint32_t TRGCMP2; /*!< PMD Trigger Compare Register 2 */ + __IO uint32_t TRGCMP3; /*!< PMD Trigger Compare Register 3 */ + __IO uint32_t TRGCR; /*!< PMD Trigger Control Register */ + __IO uint32_t TRGMD; /*!< PMD Trigger Output Mode Setting Register */ + __IO uint32_t TRGSEL; /*!< PMD Trigger Output Select Register */ + __IO uint32_t TRGSYNCR; /*!< PMD Trigger Update Timing Setting Register */ +} TSB_PMD_TypeDef; + +/** + * @brief Encoder Input (ENC) + */ +typedef struct +{ + __IO uint32_t TNCR; /*!< ENC Control Register */ + __IO uint32_t RELOAD; /*!< ENC Reload Compare Register */ + __IO uint32_t INT; /*!< ENC INT Compare Register */ + __IO uint32_t CNT; /*!< ENC Counter/Capture Register */ + __IO uint32_t MCMP; /*!< ENC MCMP Compare Register */ + __IO uint32_t RATE; /*!< ENC Phase Count Rate Register */ + __I uint32_t STS; /*!< ENC Status Register */ + __IO uint32_t INPCR; /*!< ENC Input Process Cntrol Register */ + __IO uint32_t SMPDLY; /*!< ENC Sample Delay Register */ + __I uint32_t INPMON; /*!< ENC Input Moniter Register */ + __IO uint32_t CLKCR; /*!< ENC Sample Clock Control Register */ + __IO uint32_t INTCR; /*!< ENC Interrupt Reqyest Control Register */ + __I uint32_t INTF; /*!< ENC Interrupt Event Flag Register */ +} TSB_EN_TypeDef; + +/** + * @brief + */ +typedef struct +{ + uint32_t RESERVED0[4]; + __IO uint32_t SBMR; /*!< Flash Security Bit Mask Register */ + __IO uint32_t SSR; /*!< Flash Security Status Register */ + __O uint32_t KCR; /*!< Flash Key Code Register */ + uint32_t RESERVED1; + __IO uint32_t SR0; /*!< Flash Status Register 0 */ + uint32_t RESERVED2[3]; + __I uint32_t PSR0; /*!< Flash Protect Status Register 0 */ + __I uint32_t PSR1; /*!< Flash Protect Status Register 1 */ + uint32_t RESERVED3[4]; + __I uint32_t PSR6; /*!< Flash Protect Status Register 6 */ + uint32_t RESERVED4; + __IO uint32_t PMR0; /*!< Flash Protect Mask Register 0 */ + __IO uint32_t PMR1; /*!< Flash Protect Mask Register 1 */ + uint32_t RESERVED5[4]; + __IO uint32_t PMR6; /*!< Flash Protect Mask Register 6 */ + uint32_t RESERVED6[37]; + __I uint32_t SR1; /*!< Flash Status Register 1 */ + __I uint32_t SWPSR; /*!< Flash Memory SWP Status Register */ + uint32_t RESERVED7[14]; + __IO uint32_t AREASEL; /*!< Flash Area Selection Register */ + uint32_t RESERVED8; + __IO uint32_t CR; /*!< Flash Control Register */ + __IO uint32_t STSCLR; /*!< Flash Status Clear Register */ + __IO uint32_t BNKCR; /*!< Flash Bank Change Register */ + uint32_t RESERVED9; + __IO uint32_t BUFDISCLR; /*!< Flash Buffer Disable and Clear Register */ +} TSB_FC_TypeDef; + + +/* Memory map */ +#define FLASH_BASE (0x00000000UL) +#define RAM_BASE (0x20000000UL) +#define PERI_BASE (0x40000000UL) + + +#define TSB_IA_BASE (PERI_BASE + 0x003E000UL) +#define TSB_RLM_BASE (PERI_BASE + 0x003E400UL) +#define TSB_I2CS_BASE (PERI_BASE + 0x003E800UL) +#define TSB_LVD_BASE (PERI_BASE + 0x003EC00UL) +#define TSB_DMAA_BASE (PERI_BASE + 0x004C000UL) +#define TSB_DA0_BASE (PERI_BASE + 0x0054000UL) +#define TSB_DA1_BASE (PERI_BASE + 0x0055000UL) +#define TSB_TSPI0_BASE (PERI_BASE + 0x0098000UL) +#define TSB_TSPI1_BASE (PERI_BASE + 0x0099000UL) +#define TSB_I2C0_BASE (PERI_BASE + 0x00A0000UL) +#define TSB_I2C1_BASE (PERI_BASE + 0x00A1000UL) +#define TSB_I2C2_BASE (PERI_BASE + 0x00A2000UL) +#define TSB_ADA_BASE (PERI_BASE + 0x00B8800UL) +#define TSB_T32A0_BASE (PERI_BASE + 0x00BA000UL) +#define TSB_T32A1_BASE (PERI_BASE + 0x00BA100UL) +#define TSB_T32A2_BASE (PERI_BASE + 0x00BA200UL) +#define TSB_T32A3_BASE (PERI_BASE + 0x00BA300UL) +#define TSB_T32A4_BASE (PERI_BASE + 0x00BA400UL) +#define TSB_T32A5_BASE (PERI_BASE + 0x00BA500UL) +#define TSB_UART0_BASE (PERI_BASE + 0x00BB000UL) +#define TSB_UART1_BASE (PERI_BASE + 0x00BB100UL) +#define TSB_UART2_BASE (PERI_BASE + 0x00BB200UL) +#define TSB_SIWD0_BASE (PERI_BASE + 0x00BB400UL) +#define TSB_DNFA_BASE (PERI_BASE + 0x00BB600UL) +#define TSB_TSEL0_BASE (PERI_BASE + 0x00BB800UL) +#define TSB_PA_BASE (PERI_BASE + 0x00C0000UL) +#define TSB_PB_BASE (PERI_BASE + 0x00C0100UL) +#define TSB_PC_BASE (PERI_BASE + 0x00C0200UL) +#define TSB_PD_BASE (PERI_BASE + 0x00C0300UL) +#define TSB_PE_BASE (PERI_BASE + 0x00C0400UL) +#define TSB_PF_BASE (PERI_BASE + 0x00C0500UL) +#define TSB_PG_BASE (PERI_BASE + 0x00C0600UL) +#define TSB_PH_BASE (PERI_BASE + 0x00C0700UL) +#define TSB_PJ_BASE (PERI_BASE + 0x00C0800UL) +#define TSB_PK_BASE (PERI_BASE + 0x00C0900UL) +#define TSB_PL_BASE (PERI_BASE + 0x00C0A00UL) +#define TSB_PM_BASE (PERI_BASE + 0x00C0B00UL) +#define TSB_PN_BASE (PERI_BASE + 0x00C0C00UL) +#define TSB_PP_BASE (PERI_BASE + 0x00C0D00UL) +#define TSB_PR_BASE (PERI_BASE + 0x00C0E00UL) +#define TSB_RTC_BASE (PERI_BASE + 0x00CC000UL) +#define TSB_RMC0_BASE (PERI_BASE + 0x00E7000UL) +#define TSB_OFD_BASE (PERI_BASE + 0x00F1000UL) +#define TSB_CG_BASE (PERI_BASE + 0x00F3000UL) +#define TSB_TRM_BASE (PERI_BASE + 0x00F3200UL) +#define TSB_IB_BASE (PERI_BASE + 0x00F4E00UL) +#define TSB_IMN_BASE (PERI_BASE + 0x00F4F00UL) +#define TSB_PMD0_BASE (PERI_BASE + 0x00F6000UL) +#define TSB_EN0_BASE (PERI_BASE + 0x00F7000UL) +#define TSB_FC_BASE (PERI_BASE + 0x1DFF0000UL) + + +/* Peripheral declaration */ +#define TSB_IA (( TSB_IA_TypeDef *) TSB_IA_BASE) +#define TSB_RLM (( TSB_RLM_TypeDef *) TSB_RLM_BASE) +#define TSB_I2CS (( TSB_I2CS_TypeDef *) TSB_I2CS_BASE) +#define TSB_LVD (( TSB_LVD_TypeDef *) TSB_LVD_BASE) +#define TSB_DMAA (( TSB_DMA_TypeDef *) TSB_DMAA_BASE) +#define TSB_DA0 (( TSB_DA_TypeDef *) TSB_DA0_BASE) +#define TSB_DA1 (( TSB_DA_TypeDef *) TSB_DA1_BASE) +#define TSB_TSPI0 (( TSB_TSPI_TypeDef *) TSB_TSPI0_BASE) +#define TSB_TSPI1 (( TSB_TSPI_TypeDef *) TSB_TSPI1_BASE) +#define TSB_I2C0 (( TSB_I2C_TypeDef *) TSB_I2C0_BASE) +#define TSB_I2C1 (( TSB_I2C_TypeDef *) TSB_I2C1_BASE) +#define TSB_I2C2 (( TSB_I2C_TypeDef *) TSB_I2C2_BASE) +#define TSB_ADA (( TSB_AD_TypeDef *) TSB_ADA_BASE) +#define TSB_T32A0 (( TSB_T32A_TypeDef *) TSB_T32A0_BASE) +#define TSB_T32A1 (( TSB_T32A_TypeDef *) TSB_T32A1_BASE) +#define TSB_T32A2 (( TSB_T32A_TypeDef *) TSB_T32A2_BASE) +#define TSB_T32A3 (( TSB_T32A_TypeDef *) TSB_T32A3_BASE) +#define TSB_T32A4 (( TSB_T32A_TypeDef *) TSB_T32A4_BASE) +#define TSB_T32A5 (( TSB_T32A_TypeDef *) TSB_T32A5_BASE) +#define TSB_UART0 (( TSB_UART_TypeDef *) TSB_UART0_BASE) +#define TSB_UART1 (( TSB_UART_TypeDef *) TSB_UART1_BASE) +#define TSB_UART2 (( TSB_UART_TypeDef *) TSB_UART2_BASE) +#define TSB_SIWD0 (( TSB_SIWD_TypeDef *) TSB_SIWD0_BASE) +#define TSB_DNFA (( TSB_DNF_TypeDef *) TSB_DNFA_BASE) +#define TSB_TSEL0 (( TSB_TSEL_TypeDef *) TSB_TSEL0_BASE) +#define TSB_PA (( TSB_PA_TypeDef *) TSB_PA_BASE) +#define TSB_PB (( TSB_PB_TypeDef *) TSB_PB_BASE) +#define TSB_PC (( TSB_PC_TypeDef *) TSB_PC_BASE) +#define TSB_PD (( TSB_PD_TypeDef *) TSB_PD_BASE) +#define TSB_PE (( TSB_PE_TypeDef *) TSB_PE_BASE) +#define TSB_PF (( TSB_PF_TypeDef *) TSB_PF_BASE) +#define TSB_PG (( TSB_PG_TypeDef *) TSB_PG_BASE) +#define TSB_PH (( TSB_PH_TypeDef *) TSB_PH_BASE) +#define TSB_PJ (( TSB_PJ_TypeDef *) TSB_PJ_BASE) +#define TSB_PK (( TSB_PK_TypeDef *) TSB_PK_BASE) +#define TSB_PL (( TSB_PL_TypeDef *) TSB_PL_BASE) +#define TSB_PM (( TSB_PM_TypeDef *) TSB_PM_BASE) +#define TSB_PN (( TSB_PN_TypeDef *) TSB_PN_BASE) +#define TSB_PP (( TSB_PP_TypeDef *) TSB_PP_BASE) +#define TSB_PR (( TSB_PR_TypeDef *) TSB_PR_BASE) +#define TSB_RTC (( TSB_RTC_TypeDef *) TSB_RTC_BASE) +#define TSB_RMC0 (( TSB_RMC_TypeDef *) TSB_RMC0_BASE) +#define TSB_OFD (( TSB_OFD_TypeDef *) TSB_OFD_BASE) +#define TSB_CG (( TSB_CG_TypeDef *) TSB_CG_BASE) +#define TSB_TRM (( TSB_TRM_TypeDef *) TSB_TRM_BASE) +#define TSB_IB (( TSB_IB_TypeDef *) TSB_IB_BASE) +#define TSB_IMN (( TSB_IMN_TypeDef *) TSB_IMN_BASE) +#define TSB_PMD0 (( TSB_PMD_TypeDef *) TSB_PMD0_BASE) +#define TSB_EN0 (( TSB_EN_TypeDef *) TSB_EN0_BASE) +#define TSB_FC (( TSB_FC_TypeDef *) TSB_FC_BASE) + + +/* Bit-Band for Device Specific Peripheral Registers */ +#define BITBAND_OFFSET (0x02000000UL) +#define BITBAND_PERI_BASE (PERI_BASE + BITBAND_OFFSET) +#define BITBAND_PERI(addr, bitnum) (BITBAND_PERI_BASE + (((uint32_t)(addr) - PERI_BASE) << 5) + ((uint32_t)(bitnum) << 2)) + + + + + + + +/* DMA Controller */ +#define TSB_DMAA_STATUS_MASTER_ENABLE (*((__I uint32_t *)BITBAND_PERI(&TSB_DMAA->STATUS,0))) +#define TSB_DMAA_CFG_MASTER_ENABLE (*((__O uint32_t *)BITBAND_PERI(&TSB_DMAA->CFG,0))) +#define TSB_DMAA_ERRCLR_ERR_CLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMAA->ERRCLR,0))) + + +/* Digital analog converter (DAC) */ +#define TSB_DA0_CTL_EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_DA0->CTL,0))) + +#define TSB_DA1_CTL_EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_DA1->CTL,0))) + + +/* Serial Interface (TSPI) */ +#define TSB_TSPI0_CR0_TSPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR0,0))) +#define TSB_TSPI0_CR1_MSTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR1,12))) +#define TSB_TSPI0_CR1_TSPIMS (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR1,13))) +#define TSB_TSPI0_CR1_TRXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR1,14))) +#define TSB_TSPI0_CR1_TRGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR1,15))) +#define TSB_TSPI0_CR2_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,0))) +#define TSB_TSPI0_CR2_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,1))) +#define TSB_TSPI0_CR2_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,2))) +#define TSB_TSPI0_CR2_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,4))) +#define TSB_TSPI0_CR2_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,5))) +#define TSB_TSPI0_CR2_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,6))) +#define TSB_TSPI0_CR2_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,7))) +#define TSB_TSPI0_CR2_RXDLY (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,16))) +#define TSB_TSPI0_CR2_TXDEMP (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,21))) +#define TSB_TSPI0_CR3_RFFLLCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR3,0))) +#define TSB_TSPI0_CR3_TFEMPCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR3,1))) +#define TSB_TSPI0_FMTR0_CKPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR0,14))) +#define TSB_TSPI0_FMTR0_CKPHA (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR0,15))) +#define TSB_TSPI0_FMTR0_CS0POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR0,16))) +#define TSB_TSPI0_FMTR0_CS1POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR0,17))) +#define TSB_TSPI0_FMTR0_CS2POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR0,18))) +#define TSB_TSPI0_FMTR0_CS3POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR0,19))) +#define TSB_TSPI0_FMTR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR0,31))) +#define TSB_TSPI0_FMTR1_VPM (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR1,0))) +#define TSB_TSPI0_FMTR1_VPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR1,1))) +#define TSB_TSPI0_SR_RFFLL (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,4))) +#define TSB_TSPI0_SR_INTRXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,5))) +#define TSB_TSPI0_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,6))) +#define TSB_TSPI0_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,7))) +#define TSB_TSPI0_SR_TFEMP (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,20))) +#define TSB_TSPI0_SR_INTTXWF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,21))) +#define TSB_TSPI0_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,22))) +#define TSB_TSPI0_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,23))) +#define TSB_TSPI0_SR_TSPISUE (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,31))) +#define TSB_TSPI0_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->ERR,0))) +#define TSB_TSPI0_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->ERR,1))) +#define TSB_TSPI0_ERR_UDRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->ERR,2))) +#define TSB_TSPI0_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->ERR,3))) + +#define TSB_TSPI1_CR0_TSPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR0,0))) +#define TSB_TSPI1_CR1_MSTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR1,12))) +#define TSB_TSPI1_CR1_TSPIMS (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR1,13))) +#define TSB_TSPI1_CR1_TRXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR1,14))) +#define TSB_TSPI1_CR1_TRGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR1,15))) +#define TSB_TSPI1_CR2_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,0))) +#define TSB_TSPI1_CR2_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,1))) +#define TSB_TSPI1_CR2_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,2))) +#define TSB_TSPI1_CR2_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,4))) +#define TSB_TSPI1_CR2_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,5))) +#define TSB_TSPI1_CR2_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,6))) +#define TSB_TSPI1_CR2_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,7))) +#define TSB_TSPI1_CR2_RXDLY (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,16))) +#define TSB_TSPI1_CR2_TXDEMP (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,21))) +#define TSB_TSPI1_CR3_RFFLLCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR3,0))) +#define TSB_TSPI1_CR3_TFEMPCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR3,1))) +#define TSB_TSPI1_FMTR0_CKPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR0,14))) +#define TSB_TSPI1_FMTR0_CKPHA (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR0,15))) +#define TSB_TSPI1_FMTR0_CS0POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR0,16))) +#define TSB_TSPI1_FMTR0_CS1POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR0,17))) +#define TSB_TSPI1_FMTR0_CS2POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR0,18))) +#define TSB_TSPI1_FMTR0_CS3POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR0,19))) +#define TSB_TSPI1_FMTR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR0,31))) +#define TSB_TSPI1_FMTR1_VPM (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR1,0))) +#define TSB_TSPI1_FMTR1_VPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR1,1))) +#define TSB_TSPI1_SR_RFFLL (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,4))) +#define TSB_TSPI1_SR_INTRXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,5))) +#define TSB_TSPI1_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,6))) +#define TSB_TSPI1_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,7))) +#define TSB_TSPI1_SR_TFEMP (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,20))) +#define TSB_TSPI1_SR_INTTXWF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,21))) +#define TSB_TSPI1_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,22))) +#define TSB_TSPI1_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,23))) +#define TSB_TSPI1_SR_TSPISUE (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,31))) +#define TSB_TSPI1_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->ERR,0))) +#define TSB_TSPI1_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->ERR,1))) +#define TSB_TSPI1_ERR_UDRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->ERR,2))) +#define TSB_TSPI1_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->ERR,3))) + + +/* I2C */ +#define TSB_I2C0_CR1_NOACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->CR1,3))) +#define TSB_I2C0_CR1_ACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->CR1,4))) +#define TSB_I2C0_AR_ALS (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->AR,0))) +#define TSB_I2C0_CR2_I2CM (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C0->CR2,3))) +#define TSB_I2C0_CR2_PIN (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C0->CR2,4))) +#define TSB_I2C0_CR2_BB (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C0->CR2,5))) +#define TSB_I2C0_CR2_TRX (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C0->CR2,6))) +#define TSB_I2C0_CR2_MST (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C0->CR2,7))) +#define TSB_I2C0_SR_LRB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,0))) +#define TSB_I2C0_SR_AD0 (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,1))) +#define TSB_I2C0_SR_AAS (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,2))) +#define TSB_I2C0_SR_AL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,3))) +#define TSB_I2C0_SR_PIN (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,4))) +#define TSB_I2C0_SR_BB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,5))) +#define TSB_I2C0_SR_TRX (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,6))) +#define TSB_I2C0_SR_MST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,7))) +#define TSB_I2C0_IE_INTI2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,0))) +#define TSB_I2C0_IE_INTI2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,1))) +#define TSB_I2C0_IE_INTI2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,2))) +#define TSB_I2C0_IE_INTNACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,3))) +#define TSB_I2C0_IE_DMARI2CRX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,4))) +#define TSB_I2C0_IE_DMARI2CTX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,5))) +#define TSB_I2C0_IE_SELPINCD (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,6))) +#define TSB_I2C0_ST_I2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->ST,0))) +#define TSB_I2C0_ST_I2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->ST,1))) +#define TSB_I2C0_ST_I2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->ST,2))) +#define TSB_I2C0_ST_NACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->ST,3))) +#define TSB_I2C0_OP_MFACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,0))) +#define TSB_I2C0_OP_SREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,1))) +#define TSB_I2C0_OP_GCDI (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,2))) +#define TSB_I2C0_OP_RSTA (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,3))) +#define TSB_I2C0_OP_NFSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,4))) +#define TSB_I2C0_OP_SAST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,5))) +#define TSB_I2C0_OP_SA2ST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,6))) +#define TSB_I2C0_OP_DISAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,7))) +#define TSB_I2C0_PM_SCL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->PM,0))) +#define TSB_I2C0_PM_SDA (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->PM,1))) +#define TSB_I2C0_AR2_SA2EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->AR2,0))) + +#define TSB_I2C1_CR1_NOACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->CR1,3))) +#define TSB_I2C1_CR1_ACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->CR1,4))) +#define TSB_I2C1_AR_ALS (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->AR,0))) +#define TSB_I2C1_CR2_I2CM (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C1->CR2,3))) +#define TSB_I2C1_CR2_PIN (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C1->CR2,4))) +#define TSB_I2C1_CR2_BB (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C1->CR2,5))) +#define TSB_I2C1_CR2_TRX (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C1->CR2,6))) +#define TSB_I2C1_CR2_MST (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C1->CR2,7))) +#define TSB_I2C1_SR_LRB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,0))) +#define TSB_I2C1_SR_AD0 (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,1))) +#define TSB_I2C1_SR_AAS (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,2))) +#define TSB_I2C1_SR_AL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,3))) +#define TSB_I2C1_SR_PIN (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,4))) +#define TSB_I2C1_SR_BB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,5))) +#define TSB_I2C1_SR_TRX (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,6))) +#define TSB_I2C1_SR_MST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,7))) +#define TSB_I2C1_IE_INTI2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,0))) +#define TSB_I2C1_IE_INTI2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,1))) +#define TSB_I2C1_IE_INTI2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,2))) +#define TSB_I2C1_IE_INTNACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,3))) +#define TSB_I2C1_IE_DMARI2CRX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,4))) +#define TSB_I2C1_IE_DMARI2CTX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,5))) +#define TSB_I2C1_IE_SELPINCD (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,6))) +#define TSB_I2C1_ST_I2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->ST,0))) +#define TSB_I2C1_ST_I2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->ST,1))) +#define TSB_I2C1_ST_I2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->ST,2))) +#define TSB_I2C1_ST_NACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->ST,3))) +#define TSB_I2C1_OP_MFACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,0))) +#define TSB_I2C1_OP_SREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,1))) +#define TSB_I2C1_OP_GCDI (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,2))) +#define TSB_I2C1_OP_RSTA (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,3))) +#define TSB_I2C1_OP_NFSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,4))) +#define TSB_I2C1_OP_SAST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,5))) +#define TSB_I2C1_OP_SA2ST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,6))) +#define TSB_I2C1_OP_DISAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,7))) +#define TSB_I2C1_PM_SCL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->PM,0))) +#define TSB_I2C1_PM_SDA (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->PM,1))) +#define TSB_I2C1_AR2_SA2EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->AR2,0))) + +#define TSB_I2C2_CR1_NOACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->CR1,3))) +#define TSB_I2C2_CR1_ACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->CR1,4))) +#define TSB_I2C2_AR_ALS (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->AR,0))) +#define TSB_I2C2_CR2_I2CM (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C2->CR2,3))) +#define TSB_I2C2_CR2_PIN (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C2->CR2,4))) +#define TSB_I2C2_CR2_BB (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C2->CR2,5))) +#define TSB_I2C2_CR2_TRX (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C2->CR2,6))) +#define TSB_I2C2_CR2_MST (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C2->CR2,7))) +#define TSB_I2C2_SR_LRB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->SR,0))) +#define TSB_I2C2_SR_AD0 (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->SR,1))) +#define TSB_I2C2_SR_AAS (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->SR,2))) +#define TSB_I2C2_SR_AL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->SR,3))) +#define TSB_I2C2_SR_PIN (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->SR,4))) +#define TSB_I2C2_SR_BB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->SR,5))) +#define TSB_I2C2_SR_TRX (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->SR,6))) +#define TSB_I2C2_SR_MST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->SR,7))) +#define TSB_I2C2_IE_INTI2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->IE,0))) +#define TSB_I2C2_IE_INTI2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->IE,1))) +#define TSB_I2C2_IE_INTI2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->IE,2))) +#define TSB_I2C2_IE_INTNACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->IE,3))) +#define TSB_I2C2_IE_DMARI2CRX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->IE,4))) +#define TSB_I2C2_IE_DMARI2CTX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->IE,5))) +#define TSB_I2C2_IE_SELPINCD (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->IE,6))) +#define TSB_I2C2_ST_I2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->ST,0))) +#define TSB_I2C2_ST_I2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->ST,1))) +#define TSB_I2C2_ST_I2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->ST,2))) +#define TSB_I2C2_ST_NACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->ST,3))) +#define TSB_I2C2_OP_MFACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->OP,0))) +#define TSB_I2C2_OP_SREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->OP,1))) +#define TSB_I2C2_OP_GCDI (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->OP,2))) +#define TSB_I2C2_OP_RSTA (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->OP,3))) +#define TSB_I2C2_OP_NFSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->OP,4))) +#define TSB_I2C2_OP_SAST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->OP,5))) +#define TSB_I2C2_OP_SA2ST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->OP,6))) +#define TSB_I2C2_OP_DISAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->OP,7))) +#define TSB_I2C2_PM_SCL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->PM,0))) +#define TSB_I2C2_PM_SDA (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->PM,1))) +#define TSB_I2C2_AR2_SA2EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->AR2,0))) + + +/* ADC */ +#define TSB_ADA_CR0_CNT (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CR0,0))) +#define TSB_ADA_CR0_SGL (*((__O uint32_t *)BITBAND_PERI(&TSB_ADA->CR0,1))) +#define TSB_ADA_CR0_ADEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CR0,7))) +#define TSB_ADA_CR1_TRGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CR1,0))) +#define TSB_ADA_CR1_TRGDMEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CR1,4))) +#define TSB_ADA_CR1_SGLDMEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CR1,5))) +#define TSB_ADA_CR1_CNTDMEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CR1,6))) +#define TSB_ADA_ST_PMDF (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->ST,0))) +#define TSB_ADA_ST_TRGF (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->ST,1))) +#define TSB_ADA_ST_SNGF (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->ST,2))) +#define TSB_ADA_ST_CNTF (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->ST,3))) +#define TSB_ADA_ST_ADBF (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->ST,7))) +#define TSB_ADA_MOD0_DACON (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->MOD0,0))) +#define TSB_ADA_MOD0_RCUT (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->MOD0,1))) +#define TSB_ADA_CMPEN_CMP0EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CMPEN,0))) +#define TSB_ADA_CMPEN_CMP1EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CMPEN,1))) +#define TSB_ADA_CMPCR0_ADBIG0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CMPCR0,5))) +#define TSB_ADA_CMPCR0_COMPCND0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CMPCR0,6))) +#define TSB_ADA_CMPCR1_ADBIG1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CMPCR1,5))) +#define TSB_ADA_CMPCR1_COMPCND1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CMPCR1,6))) +#define TSB_ADA_PSEL0_PENS0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSEL0,7))) +#define TSB_ADA_PSEL1_PENS1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSEL1,7))) +#define TSB_ADA_PSEL2_PENS2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSEL2,7))) +#define TSB_ADA_PSEL3_PENS3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSEL3,7))) +#define TSB_ADA_PSEL4_PENS4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSEL4,7))) +#define TSB_ADA_PSEL5_PENS5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSEL5,7))) +#define TSB_ADA_PSEL6_PENS6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSEL6,7))) +#define TSB_ADA_PSEL7_PENS7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSEL7,7))) +#define TSB_ADA_PSEL8_PENS8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSEL8,7))) +#define TSB_ADA_PSEL9_PENS9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSEL9,7))) +#define TSB_ADA_PSEL10_PENS10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSEL10,7))) +#define TSB_ADA_PSEL11_PENS11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSEL11,7))) +#define TSB_ADA_PSET0_ENSP00 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET0,7))) +#define TSB_ADA_PSET0_ENSP01 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET0,15))) +#define TSB_ADA_PSET0_ENSP02 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET0,23))) +#define TSB_ADA_PSET0_ENSP03 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET0,31))) +#define TSB_ADA_PSET1_ENSP10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET1,7))) +#define TSB_ADA_PSET1_ENSP11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET1,15))) +#define TSB_ADA_PSET1_ENSP12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET1,23))) +#define TSB_ADA_PSET1_ENSP13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET1,31))) +#define TSB_ADA_PSET2_ENSP20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET2,7))) +#define TSB_ADA_PSET2_ENSP21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET2,15))) +#define TSB_ADA_PSET2_ENSP22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET2,23))) +#define TSB_ADA_PSET2_ENSP23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET2,31))) +#define TSB_ADA_PSET3_ENSP30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET3,7))) +#define TSB_ADA_PSET3_ENSP31 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET3,15))) +#define TSB_ADA_PSET3_ENSP32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET3,23))) +#define TSB_ADA_PSET3_ENSP33 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET3,31))) +#define TSB_ADA_PSET4_ENSP40 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET4,7))) +#define TSB_ADA_PSET4_ENSP41 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET4,15))) +#define TSB_ADA_PSET4_ENSP42 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET4,23))) +#define TSB_ADA_PSET4_ENSP43 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET4,31))) +#define TSB_ADA_PSET5_ENSP50 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET5,7))) +#define TSB_ADA_PSET5_ENSP51 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET5,15))) +#define TSB_ADA_PSET5_ENSP52 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET5,23))) +#define TSB_ADA_PSET5_ENSP53 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET5,31))) +#define TSB_ADA_PSET6_ENSP60 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET6,7))) +#define TSB_ADA_PSET6_ENSP61 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET6,15))) +#define TSB_ADA_PSET6_ENSP62 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET6,23))) +#define TSB_ADA_PSET6_ENSP63 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET6,31))) +#define TSB_ADA_PSET7_ENSP70 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET7,7))) +#define TSB_ADA_PSET7_ENSP71 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET7,15))) +#define TSB_ADA_PSET7_ENSP72 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET7,23))) +#define TSB_ADA_PSET7_ENSP73 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET7,31))) +#define TSB_ADA_TSET0_ENINT0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET0,7))) +#define TSB_ADA_TSET1_ENINT1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET1,7))) +#define TSB_ADA_TSET2_ENINT2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET2,7))) +#define TSB_ADA_TSET3_ENINT3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET3,7))) +#define TSB_ADA_TSET4_ENINT4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET4,7))) +#define TSB_ADA_TSET5_ENINT5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET5,7))) +#define TSB_ADA_TSET6_ENINT6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET6,7))) +#define TSB_ADA_TSET7_ENINT7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET7,7))) +#define TSB_ADA_TSET8_ENINT8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET8,7))) +#define TSB_ADA_TSET9_ENINT9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET9,7))) +#define TSB_ADA_TSET10_ENINT10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET10,7))) +#define TSB_ADA_TSET11_ENINT11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET11,7))) +#define TSB_ADA_TSET12_ENINT12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET12,7))) +#define TSB_ADA_TSET13_ENINT13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET13,7))) +#define TSB_ADA_TSET14_ENINT14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET14,7))) +#define TSB_ADA_TSET15_ENINT15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET15,7))) +#define TSB_ADA_TSET16_ENINT16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET16,7))) +#define TSB_ADA_TSET17_ENINT17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET17,7))) +#define TSB_ADA_TSET18_ENINT18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET18,7))) +#define TSB_ADA_TSET19_ENINT19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET19,7))) +#define TSB_ADA_TSET20_ENINT20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET20,7))) +#define TSB_ADA_TSET21_ENINT21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET21,7))) +#define TSB_ADA_TSET22_ENINT22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET22,7))) +#define TSB_ADA_TSET23_ENINT23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET23,7))) +#define TSB_ADA_REG0_ADRF0 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG0,0))) +#define TSB_ADA_REG0_ADOVRF0 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG0,1))) +#define TSB_ADA_REG0_ADRF_M0 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG0,28))) +#define TSB_ADA_REG0_ADOVR_M0 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG0,29))) +#define TSB_ADA_REG1_ADRF1 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG1,0))) +#define TSB_ADA_REG1_ADOVRF1 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG1,1))) +#define TSB_ADA_REG1_ADRF_M1 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG1,28))) +#define TSB_ADA_REG1_ADOVR_M1 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG1,29))) +#define TSB_ADA_REG2_ADRF2 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG2,0))) +#define TSB_ADA_REG2_ADOVRF2 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG2,1))) +#define TSB_ADA_REG2_ADRF_M2 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG2,28))) +#define TSB_ADA_REG2_ADOVR_M2 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG2,29))) +#define TSB_ADA_REG3_ADRF3 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG3,0))) +#define TSB_ADA_REG3_ADOVRF3 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG3,1))) +#define TSB_ADA_REG3_ADRF_M3 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG3,28))) +#define TSB_ADA_REG3_ADOVR_M3 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG3,29))) +#define TSB_ADA_REG4_ADRF4 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG4,0))) +#define TSB_ADA_REG4_ADOVRF4 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG4,1))) +#define TSB_ADA_REG4_ADRF_M4 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG4,28))) +#define TSB_ADA_REG4_ADOVR_M4 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG4,29))) +#define TSB_ADA_REG5_ADRF5 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG5,0))) +#define TSB_ADA_REG5_ADOVRF5 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG5,1))) +#define TSB_ADA_REG5_ADRF_M5 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG5,28))) +#define TSB_ADA_REG5_ADOVR_M5 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG5,29))) +#define TSB_ADA_REG6_ADRF6 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG6,0))) +#define TSB_ADA_REG6_ADOVRF6 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG6,1))) +#define TSB_ADA_REG6_ADRF_M6 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG6,28))) +#define TSB_ADA_REG6_ADOVR_M6 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG6,29))) +#define TSB_ADA_REG7_ADRF7 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG7,0))) +#define TSB_ADA_REG7_ADOVRF7 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG7,1))) +#define TSB_ADA_REG7_ADRF_M7 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG7,28))) +#define TSB_ADA_REG7_ADOVR_M7 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG7,29))) +#define TSB_ADA_REG8_ADRF8 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG8,0))) +#define TSB_ADA_REG8_ADOVRF8 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG8,1))) +#define TSB_ADA_REG8_ADRF_M8 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG8,28))) +#define TSB_ADA_REG8_ADOVR_M8 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG8,29))) +#define TSB_ADA_REG9_ADRF9 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG9,0))) +#define TSB_ADA_REG9_ADOVRF9 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG9,1))) +#define TSB_ADA_REG9_ADRF_M9 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG9,28))) +#define TSB_ADA_REG9_ADOVR_M9 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG9,29))) +#define TSB_ADA_REG10_ADRF10 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG10,0))) +#define TSB_ADA_REG10_ADOVRF10 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG10,1))) +#define TSB_ADA_REG10_ADRF_M10 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG10,28))) +#define TSB_ADA_REG10_ADOVR_M10 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG10,29))) +#define TSB_ADA_REG11_ADRF11 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG11,0))) +#define TSB_ADA_REG11_ADOVRF11 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG11,1))) +#define TSB_ADA_REG11_ADRF_M11 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG11,28))) +#define TSB_ADA_REG11_ADOVR_M11 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG11,29))) +#define TSB_ADA_REG12_ADRF12 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG12,0))) +#define TSB_ADA_REG12_ADOVRF12 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG12,1))) +#define TSB_ADA_REG12_ADRF_M12 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG12,28))) +#define TSB_ADA_REG12_ADOVR_M12 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG12,29))) +#define TSB_ADA_REG13_ADRF13 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG13,0))) +#define TSB_ADA_REG13_ADOVRF13 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG13,1))) +#define TSB_ADA_REG13_ADRF_M13 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG13,28))) +#define TSB_ADA_REG13_ADOVR_M13 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG13,29))) +#define TSB_ADA_REG14_ADRF14 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG14,0))) +#define TSB_ADA_REG14_ADOVRF14 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG14,1))) +#define TSB_ADA_REG14_ADRF_M14 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG14,28))) +#define TSB_ADA_REG14_ADOVR_M14 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG14,29))) +#define TSB_ADA_REG15_ADRF15 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG15,0))) +#define TSB_ADA_REG15_ADOVRF15 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG15,1))) +#define TSB_ADA_REG15_ADRF_M15 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG15,28))) +#define TSB_ADA_REG15_ADOVR_M15 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG15,29))) +#define TSB_ADA_REG16_ADRF16 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG16,0))) +#define TSB_ADA_REG16_ADOVRF16 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG16,1))) +#define TSB_ADA_REG16_ADRF_M16 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG16,28))) +#define TSB_ADA_REG16_ADOVR_M16 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG16,29))) +#define TSB_ADA_REG17_ADRF17 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG17,0))) +#define TSB_ADA_REG17_ADOVRF17 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG17,1))) +#define TSB_ADA_REG17_ADRF_M17 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG17,28))) +#define TSB_ADA_REG17_ADOVR_M17 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG17,29))) +#define TSB_ADA_REG18_ADRF18 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG18,0))) +#define TSB_ADA_REG18_ADOVRF18 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG18,1))) +#define TSB_ADA_REG18_ADRF_M18 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG18,28))) +#define TSB_ADA_REG18_ADOVR_M18 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG18,29))) +#define TSB_ADA_REG19_ADRF19 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG19,0))) +#define TSB_ADA_REG19_ADOVRF19 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG19,1))) +#define TSB_ADA_REG19_ADRF_M19 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG19,28))) +#define TSB_ADA_REG19_ADOVR_M19 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG19,29))) +#define TSB_ADA_REG20_ADRF20 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG20,0))) +#define TSB_ADA_REG20_ADOVRF20 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG20,1))) +#define TSB_ADA_REG20_ADRF_M20 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG20,28))) +#define TSB_ADA_REG20_ADOVR_M20 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG20,29))) +#define TSB_ADA_REG21_ADRF21 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG21,0))) +#define TSB_ADA_REG21_ADOVRF21 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG21,1))) +#define TSB_ADA_REG21_ADRF_M21 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG21,28))) +#define TSB_ADA_REG21_ADOVR_M21 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG21,29))) +#define TSB_ADA_REG22_ADRF22 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG22,0))) +#define TSB_ADA_REG22_ADOVRF22 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG22,1))) +#define TSB_ADA_REG22_ADRF_M22 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG22,28))) +#define TSB_ADA_REG22_ADOVR_M22 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG22,29))) +#define TSB_ADA_REG23_ADRF23 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG23,0))) +#define TSB_ADA_REG23_ADOVRF23 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG23,1))) +#define TSB_ADA_REG23_ADRF_M23 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG23,28))) +#define TSB_ADA_REG23_ADOVR_M23 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG23,29))) + + +/* T32A */ +#define TSB_T32A0_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->MOD,0))) +#define TSB_T32A0_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->MOD,1))) +#define TSB_T32A0_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNA,0))) +#define TSB_T32A0_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNA,1))) +#define TSB_T32A0_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNA,2))) +#define TSB_T32A0_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNA,4))) +#define TSB_T32A0_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->CRA,20))) +#define TSB_T32A0_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STA,0))) +#define TSB_T32A0_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STA,1))) +#define TSB_T32A0_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STA,2))) +#define TSB_T32A0_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STA,3))) +#define TSB_T32A0_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMA,0))) +#define TSB_T32A0_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMA,1))) +#define TSB_T32A0_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMA,2))) +#define TSB_T32A0_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMA,3))) +#define TSB_T32A0_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAA,0))) +#define TSB_T32A0_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAA,1))) +#define TSB_T32A0_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAA,2))) +#define TSB_T32A0_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNB,0))) +#define TSB_T32A0_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNB,1))) +#define TSB_T32A0_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNB,2))) +#define TSB_T32A0_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNB,4))) +#define TSB_T32A0_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->CRB,20))) +#define TSB_T32A0_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STB,0))) +#define TSB_T32A0_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STB,1))) +#define TSB_T32A0_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STB,2))) +#define TSB_T32A0_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STB,3))) +#define TSB_T32A0_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMB,0))) +#define TSB_T32A0_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMB,1))) +#define TSB_T32A0_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMB,2))) +#define TSB_T32A0_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMB,3))) +#define TSB_T32A0_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAB,0))) +#define TSB_T32A0_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAB,1))) +#define TSB_T32A0_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAB,2))) +#define TSB_T32A0_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNC,0))) +#define TSB_T32A0_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNC,1))) +#define TSB_T32A0_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNC,2))) +#define TSB_T32A0_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNC,4))) +#define TSB_T32A0_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->CRC,20))) +#define TSB_T32A0_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STC,0))) +#define TSB_T32A0_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STC,1))) +#define TSB_T32A0_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STC,2))) +#define TSB_T32A0_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STC,3))) +#define TSB_T32A0_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STC,4))) +#define TSB_T32A0_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMC,0))) +#define TSB_T32A0_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMC,1))) +#define TSB_T32A0_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMC,2))) +#define TSB_T32A0_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMC,3))) +#define TSB_T32A0_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMC,4))) +#define TSB_T32A0_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAC,0))) +#define TSB_T32A0_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAC,1))) +#define TSB_T32A0_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAC,2))) +#define TSB_T32A0_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->PLSCR,0))) +#define TSB_T32A0_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->PLSCR,1))) + +#define TSB_T32A1_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->MOD,0))) +#define TSB_T32A1_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->MOD,1))) +#define TSB_T32A1_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNA,0))) +#define TSB_T32A1_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNA,1))) +#define TSB_T32A1_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNA,2))) +#define TSB_T32A1_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNA,4))) +#define TSB_T32A1_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->CRA,20))) +#define TSB_T32A1_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STA,0))) +#define TSB_T32A1_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STA,1))) +#define TSB_T32A1_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STA,2))) +#define TSB_T32A1_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STA,3))) +#define TSB_T32A1_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMA,0))) +#define TSB_T32A1_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMA,1))) +#define TSB_T32A1_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMA,2))) +#define TSB_T32A1_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMA,3))) +#define TSB_T32A1_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAA,0))) +#define TSB_T32A1_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAA,1))) +#define TSB_T32A1_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAA,2))) +#define TSB_T32A1_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNB,0))) +#define TSB_T32A1_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNB,1))) +#define TSB_T32A1_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNB,2))) +#define TSB_T32A1_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNB,4))) +#define TSB_T32A1_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->CRB,20))) +#define TSB_T32A1_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STB,0))) +#define TSB_T32A1_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STB,1))) +#define TSB_T32A1_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STB,2))) +#define TSB_T32A1_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STB,3))) +#define TSB_T32A1_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMB,0))) +#define TSB_T32A1_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMB,1))) +#define TSB_T32A1_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMB,2))) +#define TSB_T32A1_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMB,3))) +#define TSB_T32A1_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAB,0))) +#define TSB_T32A1_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAB,1))) +#define TSB_T32A1_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAB,2))) +#define TSB_T32A1_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNC,0))) +#define TSB_T32A1_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNC,1))) +#define TSB_T32A1_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNC,2))) +#define TSB_T32A1_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNC,4))) +#define TSB_T32A1_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->CRC,20))) +#define TSB_T32A1_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STC,0))) +#define TSB_T32A1_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STC,1))) +#define TSB_T32A1_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STC,2))) +#define TSB_T32A1_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STC,3))) +#define TSB_T32A1_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STC,4))) +#define TSB_T32A1_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMC,0))) +#define TSB_T32A1_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMC,1))) +#define TSB_T32A1_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMC,2))) +#define TSB_T32A1_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMC,3))) +#define TSB_T32A1_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMC,4))) +#define TSB_T32A1_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAC,0))) +#define TSB_T32A1_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAC,1))) +#define TSB_T32A1_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAC,2))) +#define TSB_T32A1_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->PLSCR,0))) +#define TSB_T32A1_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->PLSCR,1))) + +#define TSB_T32A2_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->MOD,0))) +#define TSB_T32A2_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->MOD,1))) +#define TSB_T32A2_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNA,0))) +#define TSB_T32A2_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNA,1))) +#define TSB_T32A2_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNA,2))) +#define TSB_T32A2_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNA,4))) +#define TSB_T32A2_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->CRA,20))) +#define TSB_T32A2_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STA,0))) +#define TSB_T32A2_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STA,1))) +#define TSB_T32A2_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STA,2))) +#define TSB_T32A2_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STA,3))) +#define TSB_T32A2_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMA,0))) +#define TSB_T32A2_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMA,1))) +#define TSB_T32A2_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMA,2))) +#define TSB_T32A2_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMA,3))) +#define TSB_T32A2_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAA,0))) +#define TSB_T32A2_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAA,1))) +#define TSB_T32A2_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAA,2))) +#define TSB_T32A2_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNB,0))) +#define TSB_T32A2_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNB,1))) +#define TSB_T32A2_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNB,2))) +#define TSB_T32A2_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNB,4))) +#define TSB_T32A2_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->CRB,20))) +#define TSB_T32A2_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STB,0))) +#define TSB_T32A2_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STB,1))) +#define TSB_T32A2_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STB,2))) +#define TSB_T32A2_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STB,3))) +#define TSB_T32A2_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMB,0))) +#define TSB_T32A2_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMB,1))) +#define TSB_T32A2_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMB,2))) +#define TSB_T32A2_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMB,3))) +#define TSB_T32A2_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAB,0))) +#define TSB_T32A2_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAB,1))) +#define TSB_T32A2_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAB,2))) +#define TSB_T32A2_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNC,0))) +#define TSB_T32A2_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNC,1))) +#define TSB_T32A2_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNC,2))) +#define TSB_T32A2_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNC,4))) +#define TSB_T32A2_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->CRC,20))) +#define TSB_T32A2_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STC,0))) +#define TSB_T32A2_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STC,1))) +#define TSB_T32A2_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STC,2))) +#define TSB_T32A2_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STC,3))) +#define TSB_T32A2_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STC,4))) +#define TSB_T32A2_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMC,0))) +#define TSB_T32A2_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMC,1))) +#define TSB_T32A2_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMC,2))) +#define TSB_T32A2_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMC,3))) +#define TSB_T32A2_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMC,4))) +#define TSB_T32A2_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAC,0))) +#define TSB_T32A2_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAC,1))) +#define TSB_T32A2_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAC,2))) +#define TSB_T32A2_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->PLSCR,0))) +#define TSB_T32A2_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->PLSCR,1))) + +#define TSB_T32A3_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->MOD,0))) +#define TSB_T32A3_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->MOD,1))) +#define TSB_T32A3_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNA,0))) +#define TSB_T32A3_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNA,1))) +#define TSB_T32A3_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNA,2))) +#define TSB_T32A3_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNA,4))) +#define TSB_T32A3_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->CRA,20))) +#define TSB_T32A3_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STA,0))) +#define TSB_T32A3_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STA,1))) +#define TSB_T32A3_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STA,2))) +#define TSB_T32A3_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STA,3))) +#define TSB_T32A3_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMA,0))) +#define TSB_T32A3_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMA,1))) +#define TSB_T32A3_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMA,2))) +#define TSB_T32A3_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMA,3))) +#define TSB_T32A3_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAA,0))) +#define TSB_T32A3_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAA,1))) +#define TSB_T32A3_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAA,2))) +#define TSB_T32A3_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNB,0))) +#define TSB_T32A3_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNB,1))) +#define TSB_T32A3_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNB,2))) +#define TSB_T32A3_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNB,4))) +#define TSB_T32A3_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->CRB,20))) +#define TSB_T32A3_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STB,0))) +#define TSB_T32A3_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STB,1))) +#define TSB_T32A3_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STB,2))) +#define TSB_T32A3_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STB,3))) +#define TSB_T32A3_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMB,0))) +#define TSB_T32A3_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMB,1))) +#define TSB_T32A3_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMB,2))) +#define TSB_T32A3_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMB,3))) +#define TSB_T32A3_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAB,0))) +#define TSB_T32A3_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAB,1))) +#define TSB_T32A3_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAB,2))) +#define TSB_T32A3_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNC,0))) +#define TSB_T32A3_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNC,1))) +#define TSB_T32A3_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNC,2))) +#define TSB_T32A3_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNC,4))) +#define TSB_T32A3_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->CRC,20))) +#define TSB_T32A3_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STC,0))) +#define TSB_T32A3_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STC,1))) +#define TSB_T32A3_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STC,2))) +#define TSB_T32A3_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STC,3))) +#define TSB_T32A3_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STC,4))) +#define TSB_T32A3_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMC,0))) +#define TSB_T32A3_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMC,1))) +#define TSB_T32A3_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMC,2))) +#define TSB_T32A3_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMC,3))) +#define TSB_T32A3_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMC,4))) +#define TSB_T32A3_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAC,0))) +#define TSB_T32A3_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAC,1))) +#define TSB_T32A3_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAC,2))) +#define TSB_T32A3_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->PLSCR,0))) +#define TSB_T32A3_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->PLSCR,1))) + +#define TSB_T32A4_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->MOD,0))) +#define TSB_T32A4_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->MOD,1))) +#define TSB_T32A4_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNA,0))) +#define TSB_T32A4_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNA,1))) +#define TSB_T32A4_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNA,2))) +#define TSB_T32A4_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNA,4))) +#define TSB_T32A4_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->CRA,20))) +#define TSB_T32A4_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STA,0))) +#define TSB_T32A4_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STA,1))) +#define TSB_T32A4_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STA,2))) +#define TSB_T32A4_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STA,3))) +#define TSB_T32A4_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMA,0))) +#define TSB_T32A4_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMA,1))) +#define TSB_T32A4_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMA,2))) +#define TSB_T32A4_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMA,3))) +#define TSB_T32A4_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAA,0))) +#define TSB_T32A4_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAA,1))) +#define TSB_T32A4_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAA,2))) +#define TSB_T32A4_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNB,0))) +#define TSB_T32A4_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNB,1))) +#define TSB_T32A4_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNB,2))) +#define TSB_T32A4_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNB,4))) +#define TSB_T32A4_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->CRB,20))) +#define TSB_T32A4_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STB,0))) +#define TSB_T32A4_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STB,1))) +#define TSB_T32A4_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STB,2))) +#define TSB_T32A4_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STB,3))) +#define TSB_T32A4_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMB,0))) +#define TSB_T32A4_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMB,1))) +#define TSB_T32A4_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMB,2))) +#define TSB_T32A4_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMB,3))) +#define TSB_T32A4_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAB,0))) +#define TSB_T32A4_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAB,1))) +#define TSB_T32A4_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAB,2))) +#define TSB_T32A4_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNC,0))) +#define TSB_T32A4_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNC,1))) +#define TSB_T32A4_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNC,2))) +#define TSB_T32A4_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNC,4))) +#define TSB_T32A4_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->CRC,20))) +#define TSB_T32A4_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STC,0))) +#define TSB_T32A4_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STC,1))) +#define TSB_T32A4_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STC,2))) +#define TSB_T32A4_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STC,3))) +#define TSB_T32A4_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STC,4))) +#define TSB_T32A4_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMC,0))) +#define TSB_T32A4_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMC,1))) +#define TSB_T32A4_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMC,2))) +#define TSB_T32A4_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMC,3))) +#define TSB_T32A4_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMC,4))) +#define TSB_T32A4_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAC,0))) +#define TSB_T32A4_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAC,1))) +#define TSB_T32A4_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAC,2))) +#define TSB_T32A4_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->PLSCR,0))) +#define TSB_T32A4_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->PLSCR,1))) + +#define TSB_T32A5_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->MOD,0))) +#define TSB_T32A5_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->MOD,1))) +#define TSB_T32A5_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNA,0))) +#define TSB_T32A5_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNA,1))) +#define TSB_T32A5_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNA,2))) +#define TSB_T32A5_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNA,4))) +#define TSB_T32A5_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->CRA,20))) +#define TSB_T32A5_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STA,0))) +#define TSB_T32A5_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STA,1))) +#define TSB_T32A5_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STA,2))) +#define TSB_T32A5_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STA,3))) +#define TSB_T32A5_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMA,0))) +#define TSB_T32A5_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMA,1))) +#define TSB_T32A5_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMA,2))) +#define TSB_T32A5_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMA,3))) +#define TSB_T32A5_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAA,0))) +#define TSB_T32A5_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAA,1))) +#define TSB_T32A5_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAA,2))) +#define TSB_T32A5_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNB,0))) +#define TSB_T32A5_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNB,1))) +#define TSB_T32A5_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNB,2))) +#define TSB_T32A5_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNB,4))) +#define TSB_T32A5_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->CRB,20))) +#define TSB_T32A5_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STB,0))) +#define TSB_T32A5_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STB,1))) +#define TSB_T32A5_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STB,2))) +#define TSB_T32A5_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STB,3))) +#define TSB_T32A5_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMB,0))) +#define TSB_T32A5_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMB,1))) +#define TSB_T32A5_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMB,2))) +#define TSB_T32A5_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMB,3))) +#define TSB_T32A5_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAB,0))) +#define TSB_T32A5_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAB,1))) +#define TSB_T32A5_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAB,2))) +#define TSB_T32A5_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNC,0))) +#define TSB_T32A5_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNC,1))) +#define TSB_T32A5_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNC,2))) +#define TSB_T32A5_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNC,4))) +#define TSB_T32A5_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->CRC,20))) +#define TSB_T32A5_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STC,0))) +#define TSB_T32A5_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STC,1))) +#define TSB_T32A5_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STC,2))) +#define TSB_T32A5_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STC,3))) +#define TSB_T32A5_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STC,4))) +#define TSB_T32A5_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMC,0))) +#define TSB_T32A5_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMC,1))) +#define TSB_T32A5_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMC,2))) +#define TSB_T32A5_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMC,3))) +#define TSB_T32A5_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMC,4))) +#define TSB_T32A5_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAC,0))) +#define TSB_T32A5_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAC,1))) +#define TSB_T32A5_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAC,2))) +#define TSB_T32A5_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->PLSCR,0))) +#define TSB_T32A5_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->PLSCR,1))) + + +/* UART */ +#define TSB_UART0_SWRST_SWRSTF (*((__I uint32_t *)BITBAND_PERI(&TSB_UART0->SWRST,7))) +#define TSB_UART0_CR0_PE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,2))) +#define TSB_UART0_CR0_EVEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,3))) +#define TSB_UART0_CR0_SBLEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,4))) +#define TSB_UART0_CR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,5))) +#define TSB_UART0_CR0_IV (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,6))) +#define TSB_UART0_CR0_WU (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,8))) +#define TSB_UART0_CR0_RTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,9))) +#define TSB_UART0_CR0_CTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,10))) +#define TSB_UART0_CR0_LPB (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,15))) +#define TSB_UART0_CR0_HBSEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,16))) +#define TSB_UART0_CR0_HBSMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,17))) +#define TSB_UART0_CR0_HBSST (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,18))) +#define TSB_UART0_CR1_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR1,0))) +#define TSB_UART0_CR1_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR1,1))) +#define TSB_UART0_CR1_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR1,2))) +#define TSB_UART0_CR1_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR1,4))) +#define TSB_UART0_CR1_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR1,5))) +#define TSB_UART0_CR1_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR1,6))) +#define TSB_UART0_CR1_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR1,7))) +#define TSB_UART0_BRD_KEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->BRD,23))) +#define TSB_UART0_TRANS_RXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->TRANS,0))) +#define TSB_UART0_TRANS_TXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->TRANS,1))) +#define TSB_UART0_TRANS_TXTRG (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->TRANS,2))) +#define TSB_UART0_TRANS_BK (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->TRANS,3))) +#define TSB_UART0_DR_BERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART0->DR,16))) +#define TSB_UART0_DR_FERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART0->DR,17))) +#define TSB_UART0_DR_PERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART0->DR,18))) +#define TSB_UART0_SR_RXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->SR,5))) +#define TSB_UART0_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->SR,6))) +#define TSB_UART0_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART0->SR,7))) +#define TSB_UART0_SR_TXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->SR,13))) +#define TSB_UART0_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->SR,14))) +#define TSB_UART0_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART0->SR,15))) +#define TSB_UART0_SR_SUE (*((__I uint32_t *)BITBAND_PERI(&TSB_UART0->SR,31))) +#define TSB_UART0_FIFOCLR_RFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART0->FIFOCLR,0))) +#define TSB_UART0_FIFOCLR_TFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART0->FIFOCLR,1))) +#define TSB_UART0_ERR_BERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->ERR,0))) +#define TSB_UART0_ERR_FERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->ERR,1))) +#define TSB_UART0_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->ERR,2))) +#define TSB_UART0_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->ERR,3))) +#define TSB_UART0_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->ERR,4))) + +#define TSB_UART1_SWRST_SWRSTF (*((__I uint32_t *)BITBAND_PERI(&TSB_UART1->SWRST,7))) +#define TSB_UART1_CR0_PE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,2))) +#define TSB_UART1_CR0_EVEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,3))) +#define TSB_UART1_CR0_SBLEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,4))) +#define TSB_UART1_CR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,5))) +#define TSB_UART1_CR0_IV (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,6))) +#define TSB_UART1_CR0_WU (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,8))) +#define TSB_UART1_CR0_RTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,9))) +#define TSB_UART1_CR0_CTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,10))) +#define TSB_UART1_CR0_LPB (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,15))) +#define TSB_UART1_CR0_HBSEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,16))) +#define TSB_UART1_CR0_HBSMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,17))) +#define TSB_UART1_CR0_HBSST (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,18))) +#define TSB_UART1_CR1_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR1,0))) +#define TSB_UART1_CR1_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR1,1))) +#define TSB_UART1_CR1_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR1,2))) +#define TSB_UART1_CR1_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR1,4))) +#define TSB_UART1_CR1_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR1,5))) +#define TSB_UART1_CR1_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR1,6))) +#define TSB_UART1_CR1_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR1,7))) +#define TSB_UART1_BRD_KEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->BRD,23))) +#define TSB_UART1_TRANS_RXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->TRANS,0))) +#define TSB_UART1_TRANS_TXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->TRANS,1))) +#define TSB_UART1_TRANS_TXTRG (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->TRANS,2))) +#define TSB_UART1_TRANS_BK (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->TRANS,3))) +#define TSB_UART1_DR_BERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART1->DR,16))) +#define TSB_UART1_DR_FERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART1->DR,17))) +#define TSB_UART1_DR_PERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART1->DR,18))) +#define TSB_UART1_SR_RXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->SR,5))) +#define TSB_UART1_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->SR,6))) +#define TSB_UART1_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART1->SR,7))) +#define TSB_UART1_SR_TXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->SR,13))) +#define TSB_UART1_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->SR,14))) +#define TSB_UART1_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART1->SR,15))) +#define TSB_UART1_SR_SUE (*((__I uint32_t *)BITBAND_PERI(&TSB_UART1->SR,31))) +#define TSB_UART1_FIFOCLR_RFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART1->FIFOCLR,0))) +#define TSB_UART1_FIFOCLR_TFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART1->FIFOCLR,1))) +#define TSB_UART1_ERR_BERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->ERR,0))) +#define TSB_UART1_ERR_FERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->ERR,1))) +#define TSB_UART1_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->ERR,2))) +#define TSB_UART1_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->ERR,3))) +#define TSB_UART1_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->ERR,4))) + +#define TSB_UART2_SWRST_SWRSTF (*((__I uint32_t *)BITBAND_PERI(&TSB_UART2->SWRST,7))) +#define TSB_UART2_CR0_PE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,2))) +#define TSB_UART2_CR0_EVEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,3))) +#define TSB_UART2_CR0_SBLEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,4))) +#define TSB_UART2_CR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,5))) +#define TSB_UART2_CR0_IV (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,6))) +#define TSB_UART2_CR0_WU (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,8))) +#define TSB_UART2_CR0_RTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,9))) +#define TSB_UART2_CR0_CTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,10))) +#define TSB_UART2_CR0_LPB (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,15))) +#define TSB_UART2_CR0_HBSEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,16))) +#define TSB_UART2_CR0_HBSMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,17))) +#define TSB_UART2_CR0_HBSST (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,18))) +#define TSB_UART2_CR1_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR1,0))) +#define TSB_UART2_CR1_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR1,1))) +#define TSB_UART2_CR1_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR1,2))) +#define TSB_UART2_CR1_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR1,4))) +#define TSB_UART2_CR1_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR1,5))) +#define TSB_UART2_CR1_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR1,6))) +#define TSB_UART2_CR1_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR1,7))) +#define TSB_UART2_BRD_KEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->BRD,23))) +#define TSB_UART2_TRANS_RXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->TRANS,0))) +#define TSB_UART2_TRANS_TXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->TRANS,1))) +#define TSB_UART2_TRANS_TXTRG (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->TRANS,2))) +#define TSB_UART2_TRANS_BK (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->TRANS,3))) +#define TSB_UART2_DR_BERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART2->DR,16))) +#define TSB_UART2_DR_FERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART2->DR,17))) +#define TSB_UART2_DR_PERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART2->DR,18))) +#define TSB_UART2_SR_RXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->SR,5))) +#define TSB_UART2_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->SR,6))) +#define TSB_UART2_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART2->SR,7))) +#define TSB_UART2_SR_TXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->SR,13))) +#define TSB_UART2_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->SR,14))) +#define TSB_UART2_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART2->SR,15))) +#define TSB_UART2_SR_SUE (*((__I uint32_t *)BITBAND_PERI(&TSB_UART2->SR,31))) +#define TSB_UART2_FIFOCLR_RFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART2->FIFOCLR,0))) +#define TSB_UART2_FIFOCLR_TFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART2->FIFOCLR,1))) +#define TSB_UART2_ERR_BERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->ERR,0))) +#define TSB_UART2_ERR_FERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->ERR,1))) +#define TSB_UART2_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->ERR,2))) +#define TSB_UART2_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->ERR,3))) +#define TSB_UART2_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->ERR,4))) + + +/* SIWD */ +#define TSB_SIWD0_EN_WDTE (*((__IO uint32_t *)BITBAND_PERI(&TSB_SIWD0->EN,0))) +#define TSB_SIWD0_EN_WDTF (*((__I uint32_t *)BITBAND_PERI(&TSB_SIWD0->EN,1))) +#define TSB_SIWD0_MOD_RESCR (*((__IO uint32_t *)BITBAND_PERI(&TSB_SIWD0->MOD,0))) +#define TSB_SIWD0_MOD_INTF (*((__IO uint32_t *)BITBAND_PERI(&TSB_SIWD0->MOD,1))) +#define TSB_SIWD0_OSCCR_OSCPRO (*((__IO uint32_t *)BITBAND_PERI(&TSB_SIWD0->OSCCR,0))) + + +/* DNF */ +#define TSB_DNFA_ENCR_NFEN0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,0))) +#define TSB_DNFA_ENCR_NFEN1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,1))) +#define TSB_DNFA_ENCR_NFEN2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,2))) +#define TSB_DNFA_ENCR_NFEN3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,3))) +#define TSB_DNFA_ENCR_NFEN4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,4))) +#define TSB_DNFA_ENCR_NFEN5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,5))) +#define TSB_DNFA_ENCR_NFEN6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,6))) +#define TSB_DNFA_ENCR_NFEN7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,7))) +#define TSB_DNFA_ENCR_NFEN8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,8))) +#define TSB_DNFA_ENCR_NFEN9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,9))) +#define TSB_DNFA_ENCR_NFEN10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,10))) +#define TSB_DNFA_ENCR_NFEN11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,11))) +#define TSB_DNFA_ENCR_NFEN12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,12))) +#define TSB_DNFA_ENCR_NFEN13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,13))) +#define TSB_DNFA_ENCR_NFEN14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,14))) +#define TSB_DNFA_ENCR_NFEN15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,15))) + + +/* TRGSEL */ +#define TSB_TSEL0_CR0_EN0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,0))) +#define TSB_TSEL0_CR0_OUTSEL0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,1))) +#define TSB_TSEL0_CR0_UPDN0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,2))) +#define TSB_TSEL0_CR0_EN1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,8))) +#define TSB_TSEL0_CR0_OUTSEL1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,9))) +#define TSB_TSEL0_CR0_UPDN1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,10))) +#define TSB_TSEL0_CR0_EN2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,16))) +#define TSB_TSEL0_CR0_OUTSEL2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,17))) +#define TSB_TSEL0_CR0_UPDN2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,18))) +#define TSB_TSEL0_CR0_EN3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,24))) +#define TSB_TSEL0_CR0_OUTSEL3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,25))) +#define TSB_TSEL0_CR0_UPDN3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,26))) +#define TSB_TSEL0_CR1_EN4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,0))) +#define TSB_TSEL0_CR1_OUTSEL4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,1))) +#define TSB_TSEL0_CR1_UPDN4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,2))) +#define TSB_TSEL0_CR1_EN5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,8))) +#define TSB_TSEL0_CR1_OUTSEL5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,9))) +#define TSB_TSEL0_CR1_UPDN5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,10))) +#define TSB_TSEL0_CR1_EN6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,16))) +#define TSB_TSEL0_CR1_OUTSEL6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,17))) +#define TSB_TSEL0_CR1_UPDN6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,18))) +#define TSB_TSEL0_CR1_EN7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,24))) +#define TSB_TSEL0_CR1_OUTSEL7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,25))) +#define TSB_TSEL0_CR1_UPDN7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,26))) +#define TSB_TSEL0_CR2_EN8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,0))) +#define TSB_TSEL0_CR2_OUTSEL8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,1))) +#define TSB_TSEL0_CR2_UPDN8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,2))) +#define TSB_TSEL0_CR2_EN9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,8))) +#define TSB_TSEL0_CR2_OUTSEL9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,9))) +#define TSB_TSEL0_CR2_UPDN9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,10))) +#define TSB_TSEL0_CR2_EN10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,16))) +#define TSB_TSEL0_CR2_OUTSEL10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,17))) +#define TSB_TSEL0_CR2_UPDN10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,18))) +#define TSB_TSEL0_CR2_EN11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,24))) +#define TSB_TSEL0_CR2_OUTSEL11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,25))) +#define TSB_TSEL0_CR2_UPDN11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,26))) +#define TSB_TSEL0_CR3_EN12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,0))) +#define TSB_TSEL0_CR3_OUTSEL12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,1))) +#define TSB_TSEL0_CR3_UPDN12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,2))) +#define TSB_TSEL0_CR3_EN13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,8))) +#define TSB_TSEL0_CR3_OUTSEL13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,9))) +#define TSB_TSEL0_CR3_UPDN13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,10))) +#define TSB_TSEL0_CR3_EN14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,16))) +#define TSB_TSEL0_CR3_OUTSEL14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,17))) +#define TSB_TSEL0_CR3_UPDN14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,18))) +#define TSB_TSEL0_CR3_EN15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,24))) +#define TSB_TSEL0_CR3_OUTSEL15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,25))) +#define TSB_TSEL0_CR3_UPDN15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,26))) +#define TSB_TSEL0_CR4_EN16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,0))) +#define TSB_TSEL0_CR4_OUTSEL16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,1))) +#define TSB_TSEL0_CR4_UPDN16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,2))) +#define TSB_TSEL0_CR4_EN17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,8))) +#define TSB_TSEL0_CR4_OUTSEL17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,9))) +#define TSB_TSEL0_CR4_UPDN17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,10))) +#define TSB_TSEL0_CR4_EN18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,16))) +#define TSB_TSEL0_CR4_OUTSEL18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,17))) +#define TSB_TSEL0_CR4_UPDN18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,18))) +#define TSB_TSEL0_CR4_EN19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,24))) +#define TSB_TSEL0_CR4_OUTSEL19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,25))) +#define TSB_TSEL0_CR4_UPDN19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,26))) +#define TSB_TSEL0_CR5_EN20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,0))) +#define TSB_TSEL0_CR5_OUTSEL20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,1))) +#define TSB_TSEL0_CR5_UPDN20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,2))) +#define TSB_TSEL0_CR5_EN21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,8))) +#define TSB_TSEL0_CR5_OUTSEL21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,9))) +#define TSB_TSEL0_CR5_UPDN21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,10))) +#define TSB_TSEL0_CR5_EN22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,16))) +#define TSB_TSEL0_CR5_OUTSEL22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,17))) +#define TSB_TSEL0_CR5_UPDN22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,18))) +#define TSB_TSEL0_CR5_EN23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,24))) +#define TSB_TSEL0_CR5_OUTSEL23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,25))) +#define TSB_TSEL0_CR5_UPDN23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,26))) +#define TSB_TSEL0_CR6_EN24 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,0))) +#define TSB_TSEL0_CR6_OUTSEL24 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,1))) +#define TSB_TSEL0_CR6_UPDN24 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,2))) +#define TSB_TSEL0_CR6_EN25 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,8))) +#define TSB_TSEL0_CR6_OUTSEL25 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,9))) +#define TSB_TSEL0_CR6_UPDN25 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,10))) +#define TSB_TSEL0_CR6_EN26 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,16))) +#define TSB_TSEL0_CR6_OUTSEL26 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,17))) +#define TSB_TSEL0_CR6_UPDN26 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,18))) +#define TSB_TSEL0_CR6_EN27 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,24))) +#define TSB_TSEL0_CR6_OUTSEL27 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,25))) +#define TSB_TSEL0_CR6_UPDN27 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,26))) +#define TSB_TSEL0_CR7_EN28 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,0))) +#define TSB_TSEL0_CR7_OUTSEL28 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,1))) +#define TSB_TSEL0_CR7_UPDN28 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,2))) +#define TSB_TSEL0_CR7_EN29 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,8))) +#define TSB_TSEL0_CR7_OUTSEL29 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,9))) +#define TSB_TSEL0_CR7_UPDN29 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,10))) +#define TSB_TSEL0_CR7_EN30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,16))) +#define TSB_TSEL0_CR7_OUTSEL30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,17))) +#define TSB_TSEL0_CR7_UPDN30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,18))) +#define TSB_TSEL0_CR7_EN31 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,24))) +#define TSB_TSEL0_CR7_OUTSEL31 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,25))) +#define TSB_TSEL0_CR7_UPDN31 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,26))) +#define TSB_TSEL0_CR8_EN32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,0))) +#define TSB_TSEL0_CR8_OUTSEL32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,1))) +#define TSB_TSEL0_CR8_UPDN32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,2))) +#define TSB_TSEL0_CR8_EN33 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,8))) +#define TSB_TSEL0_CR8_OUTSEL33 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,9))) +#define TSB_TSEL0_CR8_UPDN33 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,10))) +#define TSB_TSEL0_CR8_EN34 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,16))) +#define TSB_TSEL0_CR8_OUTSEL34 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,17))) +#define TSB_TSEL0_CR8_UPDN34 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,18))) +#define TSB_TSEL0_CR8_EN35 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,24))) +#define TSB_TSEL0_CR8_OUTSEL35 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,25))) +#define TSB_TSEL0_CR8_UPDN35 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,26))) +#define TSB_TSEL0_CR9_EN36 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,0))) +#define TSB_TSEL0_CR9_OUTSEL36 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,1))) +#define TSB_TSEL0_CR9_UPDN36 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,2))) +#define TSB_TSEL0_CR9_EN37 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,8))) +#define TSB_TSEL0_CR9_OUTSEL37 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,9))) +#define TSB_TSEL0_CR9_UPDN37 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,10))) +#define TSB_TSEL0_CR9_EN38 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,16))) +#define TSB_TSEL0_CR9_OUTSEL38 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,17))) +#define TSB_TSEL0_CR9_UPDN38 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,18))) +#define TSB_TSEL0_CR9_EN39 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,24))) +#define TSB_TSEL0_CR9_OUTSEL39 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,25))) +#define TSB_TSEL0_CR9_UPDN39 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,26))) +#define TSB_TSEL0_CR10_EN40 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,0))) +#define TSB_TSEL0_CR10_OUTSEL40 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,1))) +#define TSB_TSEL0_CR10_UPDN40 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,2))) + + +/* Port A */ +#define TSB_PA_DATA_PA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,0))) +#define TSB_PA_DATA_PA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,1))) +#define TSB_PA_DATA_PA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,2))) +#define TSB_PA_DATA_PA3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,3))) +#define TSB_PA_DATA_PA4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,4))) +#define TSB_PA_DATA_PA5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,5))) +#define TSB_PA_DATA_PA6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,6))) +#define TSB_PA_DATA_PA7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,7))) +#define TSB_PA_CR_PA0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,0))) +#define TSB_PA_CR_PA1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,1))) +#define TSB_PA_CR_PA2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,2))) +#define TSB_PA_CR_PA3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,3))) +#define TSB_PA_CR_PA4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,4))) +#define TSB_PA_CR_PA5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,5))) +#define TSB_PA_CR_PA6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,6))) +#define TSB_PA_CR_PA7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,7))) +#define TSB_PA_FR1_PA0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR1,0))) +#define TSB_PA_FR1_PA1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR1,1))) +#define TSB_PA_FR1_PA2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR1,2))) +#define TSB_PA_FR1_PA4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR1,4))) +#define TSB_PA_FR1_PA5F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR1,5))) +#define TSB_PA_FR2_PA1F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR2,1))) +#define TSB_PA_FR2_PA2F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR2,2))) +#define TSB_PA_FR2_PA3F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR2,3))) +#define TSB_PA_FR3_PA0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR3,0))) +#define TSB_PA_FR3_PA1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR3,1))) +#define TSB_PA_FR3_PA2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR3,2))) +#define TSB_PA_FR3_PA3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR3,3))) +#define TSB_PA_FR3_PA4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR3,4))) +#define TSB_PA_FR4_PA0F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR4,0))) +#define TSB_PA_FR4_PA1F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR4,1))) +#define TSB_PA_FR4_PA2F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR4,2))) +#define TSB_PA_FR4_PA3F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR4,3))) +#define TSB_PA_FR4_PA4F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR4,4))) +#define TSB_PA_FR4_PA5F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR4,5))) +#define TSB_PA_FR5_PA0F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR5,0))) +#define TSB_PA_FR5_PA1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR5,1))) +#define TSB_PA_FR5_PA2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR5,2))) +#define TSB_PA_FR6_PA0F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR6,0))) +#define TSB_PA_FR6_PA1F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR6,1))) +#define TSB_PA_FR6_PA2F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR6,2))) +#define TSB_PA_FR6_PA3F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR6,3))) +#define TSB_PA_OD_PA0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,0))) +#define TSB_PA_OD_PA1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,1))) +#define TSB_PA_OD_PA2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,2))) +#define TSB_PA_OD_PA3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,3))) +#define TSB_PA_OD_PA4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,4))) +#define TSB_PA_OD_PA5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,5))) +#define TSB_PA_OD_PA6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,6))) +#define TSB_PA_OD_PA7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,7))) +#define TSB_PA_PUP_PA0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,0))) +#define TSB_PA_PUP_PA1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,1))) +#define TSB_PA_PUP_PA2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,2))) +#define TSB_PA_PUP_PA3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,3))) +#define TSB_PA_PUP_PA4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,4))) +#define TSB_PA_PUP_PA5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,5))) +#define TSB_PA_PUP_PA6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,6))) +#define TSB_PA_PUP_PA7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,7))) +#define TSB_PA_PDN_PA0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,0))) +#define TSB_PA_PDN_PA1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,1))) +#define TSB_PA_PDN_PA2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,2))) +#define TSB_PA_PDN_PA3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,3))) +#define TSB_PA_PDN_PA4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,4))) +#define TSB_PA_PDN_PA5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,5))) +#define TSB_PA_PDN_PA6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,6))) +#define TSB_PA_PDN_PA7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,7))) +#define TSB_PA_IE_PA0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,0))) +#define TSB_PA_IE_PA1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,1))) +#define TSB_PA_IE_PA2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,2))) +#define TSB_PA_IE_PA3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,3))) +#define TSB_PA_IE_PA4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,4))) +#define TSB_PA_IE_PA5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,5))) +#define TSB_PA_IE_PA6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,6))) +#define TSB_PA_IE_PA7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,7))) + + +/* Port B */ +#define TSB_PB_DATA_PB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,0))) +#define TSB_PB_DATA_PB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,1))) +#define TSB_PB_DATA_PB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,2))) +#define TSB_PB_DATA_PB3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,3))) +#define TSB_PB_DATA_PB4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,4))) +#define TSB_PB_DATA_PB5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,5))) +#define TSB_PB_DATA_PB6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,6))) +#define TSB_PB_DATA_PB7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,7))) +#define TSB_PB_CR_PB0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,0))) +#define TSB_PB_CR_PB1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,1))) +#define TSB_PB_CR_PB2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,2))) +#define TSB_PB_CR_PB3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,3))) +#define TSB_PB_CR_PB4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,4))) +#define TSB_PB_CR_PB5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,5))) +#define TSB_PB_CR_PB6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,6))) +#define TSB_PB_CR_PB7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,7))) +#define TSB_PB_FR1_PB1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR1,1))) +#define TSB_PB_FR1_PB2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR1,2))) +#define TSB_PB_FR1_PB3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR1,3))) +#define TSB_PB_FR1_PB4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR1,4))) +#define TSB_PB_FR1_PB5F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR1,5))) +#define TSB_PB_FR2_PB2F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR2,2))) +#define TSB_PB_FR2_PB3F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR2,3))) +#define TSB_PB_FR2_PB4F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR2,4))) +#define TSB_PB_FR2_PB5F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR2,5))) +#define TSB_PB_FR3_PB2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR3,2))) +#define TSB_PB_FR3_PB3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR3,3))) +#define TSB_PB_FR3_PB4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR3,4))) +#define TSB_PB_FR3_PB5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR3,5))) +#define TSB_PB_FR3_PB6F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR3,6))) +#define TSB_PB_FR4_PB0F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR4,0))) +#define TSB_PB_FR4_PB1F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR4,1))) +#define TSB_PB_FR4_PB2F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR4,2))) +#define TSB_PB_FR4_PB3F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR4,3))) +#define TSB_PB_FR4_PB4F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR4,4))) +#define TSB_PB_FR4_PB5F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR4,5))) +#define TSB_PB_FR5_PB0F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR5,0))) +#define TSB_PB_FR5_PB1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR5,1))) +#define TSB_PB_FR5_PB2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR5,2))) +#define TSB_PB_FR5_PB5F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR5,5))) +#define TSB_PB_FR6_PB0F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR6,0))) +#define TSB_PB_FR6_PB1F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR6,1))) +#define TSB_PB_OD_PB0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,0))) +#define TSB_PB_OD_PB1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,1))) +#define TSB_PB_OD_PB2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,2))) +#define TSB_PB_OD_PB3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,3))) +#define TSB_PB_OD_PB4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,4))) +#define TSB_PB_OD_PB5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,5))) +#define TSB_PB_OD_PB6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,6))) +#define TSB_PB_OD_PB7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,7))) +#define TSB_PB_PUP_PB0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,0))) +#define TSB_PB_PUP_PB1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,1))) +#define TSB_PB_PUP_PB2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,2))) +#define TSB_PB_PUP_PB3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,3))) +#define TSB_PB_PUP_PB4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,4))) +#define TSB_PB_PUP_PB5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,5))) +#define TSB_PB_PUP_PB6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,6))) +#define TSB_PB_PUP_PB7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,7))) +#define TSB_PB_PDN_PB0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,0))) +#define TSB_PB_PDN_PB1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,1))) +#define TSB_PB_PDN_PB2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,2))) +#define TSB_PB_PDN_PB3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,3))) +#define TSB_PB_PDN_PB4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,4))) +#define TSB_PB_PDN_PB5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,5))) +#define TSB_PB_PDN_PB6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,6))) +#define TSB_PB_PDN_PB7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,7))) +#define TSB_PB_IE_PB1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,1))) +#define TSB_PB_IE_PB2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,2))) +#define TSB_PB_IE_PB3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,3))) +#define TSB_PB_IE_PB4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,4))) +#define TSB_PB_IE_PB5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,5))) +#define TSB_PB_IE_PB6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,6))) +#define TSB_PB_IE_PB7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,7))) + + +/* Port C */ +#define TSB_PC_DATA_PC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,0))) +#define TSB_PC_DATA_PC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,1))) +#define TSB_PC_DATA_PC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,2))) +#define TSB_PC_DATA_PC3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,3))) +#define TSB_PC_DATA_PC4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,4))) +#define TSB_PC_DATA_PC5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,5))) +#define TSB_PC_DATA_PC6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,6))) +#define TSB_PC_CR_PC0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,0))) +#define TSB_PC_CR_PC1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,1))) +#define TSB_PC_CR_PC2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,2))) +#define TSB_PC_CR_PC3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,3))) +#define TSB_PC_CR_PC4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,4))) +#define TSB_PC_CR_PC5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,5))) +#define TSB_PC_CR_PC6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,6))) +#define TSB_PC_FR1_PC0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR1,0))) +#define TSB_PC_FR1_PC1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR1,1))) +#define TSB_PC_FR3_PC0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR3,0))) +#define TSB_PC_FR3_PC1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR3,1))) +#define TSB_PC_FR3_PC2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR3,2))) +#define TSB_PC_FR3_PC3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR3,3))) +#define TSB_PC_FR3_PC4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR3,4))) +#define TSB_PC_FR3_PC5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR3,5))) +#define TSB_PC_FR4_PC0F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR4,0))) +#define TSB_PC_FR4_PC1F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR4,1))) +#define TSB_PC_FR4_PC2F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR4,2))) +#define TSB_PC_FR5_PC2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR5,2))) +#define TSB_PC_OD_PC0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,0))) +#define TSB_PC_OD_PC1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,1))) +#define TSB_PC_OD_PC2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,2))) +#define TSB_PC_OD_PC3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,3))) +#define TSB_PC_OD_PC4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,4))) +#define TSB_PC_OD_PC5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,5))) +#define TSB_PC_OD_PC6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,6))) +#define TSB_PC_PUP_PC0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,0))) +#define TSB_PC_PUP_PC1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,1))) +#define TSB_PC_PUP_PC2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,2))) +#define TSB_PC_PUP_PC3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,3))) +#define TSB_PC_PUP_PC4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,4))) +#define TSB_PC_PUP_PC5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,5))) +#define TSB_PC_PUP_PC6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,6))) +#define TSB_PC_PDN_PC0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,0))) +#define TSB_PC_PDN_PC1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,1))) +#define TSB_PC_PDN_PC2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,2))) +#define TSB_PC_PDN_PC3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,3))) +#define TSB_PC_PDN_PC4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,4))) +#define TSB_PC_PDN_PC5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,5))) +#define TSB_PC_PDN_PC6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,6))) +#define TSB_PC_IE_PC0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,0))) +#define TSB_PC_IE_PC1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,1))) +#define TSB_PC_IE_PC2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,2))) +#define TSB_PC_IE_PC3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,3))) +#define TSB_PC_IE_PC4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,4))) +#define TSB_PC_IE_PC5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,5))) +#define TSB_PC_IE_PC6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,6))) + + +/* Port D */ +#define TSB_PD_DATA_PD0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,0))) +#define TSB_PD_DATA_PD1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,1))) +#define TSB_PD_DATA_PD2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,2))) +#define TSB_PD_DATA_PD3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,3))) +#define TSB_PD_CR_PD0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,0))) +#define TSB_PD_CR_PD1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,1))) +#define TSB_PD_CR_PD2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,2))) +#define TSB_PD_CR_PD3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,3))) +#define TSB_PD_OD_PD0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,0))) +#define TSB_PD_OD_PD1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,1))) +#define TSB_PD_OD_PD2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,2))) +#define TSB_PD_PUP_PD0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,0))) +#define TSB_PD_PUP_PD1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,1))) +#define TSB_PD_PUP_PD2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,2))) +#define TSB_PD_PUP_PD3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,3))) +#define TSB_PD_PDN_PD0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PDN,0))) +#define TSB_PD_PDN_PD1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PDN,1))) +#define TSB_PD_PDN_PD2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PDN,2))) +#define TSB_PD_PDN_PD3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PDN,3))) +#define TSB_PD_IE_PD0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,0))) +#define TSB_PD_IE_PD1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,1))) +#define TSB_PD_IE_PD2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,2))) +#define TSB_PD_IE_PD3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,3))) + + +/* Port E */ +#define TSB_PE_DATA_PE0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,0))) +#define TSB_PE_DATA_PE1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,1))) +#define TSB_PE_DATA_PE2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,2))) +#define TSB_PE_DATA_PE3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,3))) +#define TSB_PE_DATA_PE4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,4))) +#define TSB_PE_DATA_PE5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,5))) +#define TSB_PE_DATA_PE6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,6))) +#define TSB_PE_CR_PE0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,0))) +#define TSB_PE_CR_PE1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,1))) +#define TSB_PE_CR_PE2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,2))) +#define TSB_PE_CR_PE3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,3))) +#define TSB_PE_CR_PE4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,4))) +#define TSB_PE_CR_PE5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,5))) +#define TSB_PE_CR_PE6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,6))) +#define TSB_PE_OD_PE0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,0))) +#define TSB_PE_OD_PE1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,1))) +#define TSB_PE_OD_PE2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,2))) +#define TSB_PE_OD_PE3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,3))) +#define TSB_PE_OD_PE4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,4))) +#define TSB_PE_OD_PE5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,5))) +#define TSB_PE_OD_PE6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,6))) +#define TSB_PE_PUP_PE0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,0))) +#define TSB_PE_PUP_PE1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,1))) +#define TSB_PE_PUP_PE2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,2))) +#define TSB_PE_PUP_PE3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,3))) +#define TSB_PE_PUP_PE4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,4))) +#define TSB_PE_PUP_PE5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,5))) +#define TSB_PE_PUP_PE6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,6))) +#define TSB_PE_PDN_PE0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,0))) +#define TSB_PE_PDN_PE1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,1))) +#define TSB_PE_PDN_PE2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,2))) +#define TSB_PE_PDN_PE3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,3))) +#define TSB_PE_PDN_PE4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,4))) +#define TSB_PE_PDN_PE5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,5))) +#define TSB_PE_PDN_PE6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,6))) +#define TSB_PE_IE_PE0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,0))) +#define TSB_PE_IE_PE1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,1))) +#define TSB_PE_IE_PE2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,2))) +#define TSB_PE_IE_PE3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,3))) +#define TSB_PE_IE_PE4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,4))) +#define TSB_PE_IE_PE5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,5))) +#define TSB_PE_IE_PE6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,6))) + + +/* */ +#define TSB_PF_DATA_PF0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,0))) +#define TSB_PF_DATA_PF1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,1))) +#define TSB_PF_DATA_PF2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,2))) +#define TSB_PF_DATA_PF3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,3))) +#define TSB_PF_DATA_PF4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,4))) +#define TSB_PF_CR_PF0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,0))) +#define TSB_PF_CR_PF1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,1))) +#define TSB_PF_CR_PF2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,2))) +#define TSB_PF_CR_PF3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,3))) +#define TSB_PF_CR_PF4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,4))) +#define TSB_PF_OD_PF0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,0))) +#define TSB_PF_OD_PF1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,1))) +#define TSB_PF_OD_PF2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,2))) +#define TSB_PF_OD_PF3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,3))) +#define TSB_PF_OD_PF4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,4))) +#define TSB_PF_PUP_PF0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,0))) +#define TSB_PF_PUP_PF1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,1))) +#define TSB_PF_PUP_PF2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,2))) +#define TSB_PF_PUP_PF3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,3))) +#define TSB_PF_PUP_PF4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,4))) +#define TSB_PF_PDN_PF0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,0))) +#define TSB_PF_PDN_PF1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,1))) +#define TSB_PF_PDN_PF2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,2))) +#define TSB_PF_PDN_PF3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,3))) +#define TSB_PF_PDN_PF4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,4))) +#define TSB_PF_IE_PF0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,0))) +#define TSB_PF_IE_PF1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,1))) +#define TSB_PF_IE_PF2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,2))) +#define TSB_PF_IE_PF3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,3))) +#define TSB_PF_IE_PF4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,4))) + + +/* */ +#define TSB_PG_DATA_PG0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->DATA,0))) +#define TSB_PG_DATA_PG1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->DATA,1))) +#define TSB_PG_CR_PG0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->CR,0))) +#define TSB_PG_CR_PG1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->CR,1))) +#define TSB_PG_OD_PG0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->OD,0))) +#define TSB_PG_OD_PG1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->OD,1))) +#define TSB_PG_PUP_PG0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PUP,0))) +#define TSB_PG_PUP_PG1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PUP,1))) +#define TSB_PG_PDN_PG0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PDN,0))) +#define TSB_PG_PDN_PG1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PDN,1))) +#define TSB_PG_IE_PG0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->IE,0))) +#define TSB_PG_IE_PG1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->IE,1))) + + +/* */ +#define TSB_PH_DATA_PH0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->DATA,0))) +#define TSB_PH_DATA_PH1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->DATA,1))) +#define TSB_PH_DATA_PH2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->DATA,2))) +#define TSB_PH_DATA_PH3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->DATA,3))) +#define TSB_PH_PDN_PH0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PDN,0))) +#define TSB_PH_PDN_PH1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PDN,1))) +#define TSB_PH_PDN_PH2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PDN,2))) +#define TSB_PH_PDN_PH3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PDN,3))) +#define TSB_PH_IE_PH0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->IE,0))) +#define TSB_PH_IE_PH1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->IE,1))) +#define TSB_PH_IE_PH2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->IE,2))) +#define TSB_PH_IE_PH3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->IE,3))) + + +/* */ +#define TSB_PJ_DATA_PJ0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,0))) +#define TSB_PJ_DATA_PJ1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,1))) +#define TSB_PJ_DATA_PJ2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,2))) +#define TSB_PJ_DATA_PJ3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,3))) +#define TSB_PJ_DATA_PJ4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,4))) +#define TSB_PJ_DATA_PJ5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,5))) +#define TSB_PJ_CR_PJ0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,0))) +#define TSB_PJ_CR_PJ1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,1))) +#define TSB_PJ_CR_PJ2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,2))) +#define TSB_PJ_CR_PJ3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,3))) +#define TSB_PJ_CR_PJ4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,4))) +#define TSB_PJ_CR_PJ5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,5))) +#define TSB_PJ_FR1_PJ0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR1,0))) +#define TSB_PJ_FR1_PJ1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR1,1))) +#define TSB_PJ_FR1_PJ2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR1,2))) +#define TSB_PJ_FR1_PJ3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR1,3))) +#define TSB_PJ_FR1_PJ4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR1,4))) +#define TSB_PJ_FR2_PJ1F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR2,1))) +#define TSB_PJ_FR2_PJ2F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR2,2))) +#define TSB_PJ_FR2_PJ3F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR2,3))) +#define TSB_PJ_FR2_PJ4F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR2,4))) +#define TSB_PJ_FR3_PJ0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR3,0))) +#define TSB_PJ_FR3_PJ1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR3,1))) +#define TSB_PJ_FR3_PJ2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR3,2))) +#define TSB_PJ_FR3_PJ3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR3,3))) +#define TSB_PJ_FR3_PJ4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR3,4))) +#define TSB_PJ_FR3_PJ5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR3,5))) +#define TSB_PJ_FR4_PJ0F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR4,0))) +#define TSB_PJ_FR4_PJ1F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR4,1))) +#define TSB_PJ_FR4_PJ2F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR4,2))) +#define TSB_PJ_FR5_PJ0F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR5,0))) +#define TSB_PJ_FR5_PJ1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR5,1))) +#define TSB_PJ_FR5_PJ2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR5,2))) +#define TSB_PJ_FR5_PJ3F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR5,3))) +#define TSB_PJ_FR5_PJ4F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR5,4))) +#define TSB_PJ_FR5_PJ5F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR5,5))) +#define TSB_PJ_OD_PJ0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,0))) +#define TSB_PJ_OD_PJ1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,1))) +#define TSB_PJ_OD_PJ2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,2))) +#define TSB_PJ_OD_PJ3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,3))) +#define TSB_PJ_OD_PJ4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,4))) +#define TSB_PJ_OD_PJ5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,5))) +#define TSB_PJ_PUP_PJ0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,0))) +#define TSB_PJ_PUP_PJ1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,1))) +#define TSB_PJ_PUP_PJ2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,2))) +#define TSB_PJ_PUP_PJ3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,3))) +#define TSB_PJ_PUP_PJ4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,4))) +#define TSB_PJ_PUP_PJ5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,5))) +#define TSB_PJ_PDN_PJ0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PDN,0))) +#define TSB_PJ_PDN_PJ1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PDN,1))) +#define TSB_PJ_PDN_PJ2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PDN,2))) +#define TSB_PJ_PDN_PJ3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PDN,3))) +#define TSB_PJ_PDN_PJ4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PDN,4))) +#define TSB_PJ_PDN_PJ5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PDN,5))) +#define TSB_PJ_IE_PJ0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,0))) +#define TSB_PJ_IE_PJ1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,1))) +#define TSB_PJ_IE_PJ2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,2))) +#define TSB_PJ_IE_PJ3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,3))) +#define TSB_PJ_IE_PJ4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,4))) +#define TSB_PJ_IE_PJ5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,5))) + + +/* */ +#define TSB_PK_DATA_PK0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->DATA,0))) +#define TSB_PK_DATA_PK1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->DATA,1))) +#define TSB_PK_DATA_PK2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->DATA,2))) +#define TSB_PK_DATA_PK3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->DATA,3))) +#define TSB_PK_DATA_PK4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->DATA,4))) +#define TSB_PK_DATA_PK5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->DATA,5))) +#define TSB_PK_DATA_PK6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->DATA,6))) +#define TSB_PK_DATA_PK7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->DATA,7))) +#define TSB_PK_CR_PK0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->CR,0))) +#define TSB_PK_CR_PK1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->CR,1))) +#define TSB_PK_CR_PK2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->CR,2))) +#define TSB_PK_CR_PK3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->CR,3))) +#define TSB_PK_CR_PK4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->CR,4))) +#define TSB_PK_CR_PK5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->CR,5))) +#define TSB_PK_CR_PK6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->CR,6))) +#define TSB_PK_CR_PK7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->CR,7))) +#define TSB_PK_FR1_PK0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR1,0))) +#define TSB_PK_FR1_PK1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR1,1))) +#define TSB_PK_FR1_PK2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR1,2))) +#define TSB_PK_FR1_PK3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR1,3))) +#define TSB_PK_FR1_PK4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR1,4))) +#define TSB_PK_FR2_PK1F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR2,1))) +#define TSB_PK_FR2_PK2F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR2,2))) +#define TSB_PK_FR2_PK3F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR2,3))) +#define TSB_PK_FR2_PK4F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR2,4))) +#define TSB_PK_FR3_PK2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR3,2))) +#define TSB_PK_FR3_PK3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR3,3))) +#define TSB_PK_FR3_PK4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR3,4))) +#define TSB_PK_FR3_PK5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR3,5))) +#define TSB_PK_FR3_PK6F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR3,6))) +#define TSB_PK_FR3_PK7F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR3,7))) +#define TSB_PK_FR4_PK2F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR4,2))) +#define TSB_PK_FR4_PK3F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR4,3))) +#define TSB_PK_FR4_PK4F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR4,4))) +#define TSB_PK_FR5_PK0F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR5,0))) +#define TSB_PK_FR5_PK1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR5,1))) +#define TSB_PK_FR5_PK2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR5,2))) +#define TSB_PK_FR5_PK3F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR5,3))) +#define TSB_PK_FR5_PK4F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR5,4))) +#define TSB_PK_FR5_PK5F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR5,5))) +#define TSB_PK_FR5_PK6F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR5,6))) +#define TSB_PK_OD_PK0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->OD,0))) +#define TSB_PK_OD_PK1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->OD,1))) +#define TSB_PK_OD_PK2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->OD,2))) +#define TSB_PK_OD_PK3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->OD,3))) +#define TSB_PK_OD_PK4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->OD,4))) +#define TSB_PK_OD_PK5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->OD,5))) +#define TSB_PK_OD_PK6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->OD,6))) +#define TSB_PK_OD_PK7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->OD,7))) +#define TSB_PK_PUP_PK0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PUP,0))) +#define TSB_PK_PUP_PK1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PUP,1))) +#define TSB_PK_PUP_PK2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PUP,2))) +#define TSB_PK_PUP_PK3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PUP,3))) +#define TSB_PK_PUP_PK4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PUP,4))) +#define TSB_PK_PUP_PK5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PUP,5))) +#define TSB_PK_PUP_PK6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PUP,6))) +#define TSB_PK_PUP_PK7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PUP,7))) +#define TSB_PK_PDN_PK0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PDN,0))) +#define TSB_PK_PDN_PK1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PDN,1))) +#define TSB_PK_PDN_PK2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PDN,2))) +#define TSB_PK_PDN_PK3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PDN,3))) +#define TSB_PK_PDN_PK4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PDN,4))) +#define TSB_PK_PDN_PK5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PDN,5))) +#define TSB_PK_PDN_PK6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PDN,6))) +#define TSB_PK_PDN_PK7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PDN,7))) +#define TSB_PK_IE_PK0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->IE,0))) +#define TSB_PK_IE_PK1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->IE,1))) +#define TSB_PK_IE_PK2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->IE,2))) +#define TSB_PK_IE_PK3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->IE,3))) +#define TSB_PK_IE_PK4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->IE,4))) +#define TSB_PK_IE_PK5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->IE,5))) +#define TSB_PK_IE_PK6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->IE,6))) +#define TSB_PK_IE_PK7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->IE,7))) + + +/* */ +#define TSB_PL_DATA_PL0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->DATA,0))) +#define TSB_PL_DATA_PL1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->DATA,1))) +#define TSB_PL_DATA_PL2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->DATA,2))) +#define TSB_PL_DATA_PL3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->DATA,3))) +#define TSB_PL_DATA_PL4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->DATA,4))) +#define TSB_PL_DATA_PL5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->DATA,5))) +#define TSB_PL_DATA_PL6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->DATA,6))) +#define TSB_PL_CR_PL0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->CR,0))) +#define TSB_PL_CR_PL1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->CR,1))) +#define TSB_PL_CR_PL2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->CR,2))) +#define TSB_PL_CR_PL3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->CR,3))) +#define TSB_PL_CR_PL4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->CR,4))) +#define TSB_PL_CR_PL5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->CR,5))) +#define TSB_PL_CR_PL6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->CR,6))) +#define TSB_PL_FR1_PL0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR1,0))) +#define TSB_PL_FR1_PL1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR1,1))) +#define TSB_PL_FR1_PL2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR1,2))) +#define TSB_PL_FR1_PL3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR1,3))) +#define TSB_PL_FR1_PL5F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR1,5))) +#define TSB_PL_FR1_PL6F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR1,6))) +#define TSB_PL_FR2_PL0F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR2,0))) +#define TSB_PL_FR2_PL1F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR2,1))) +#define TSB_PL_FR2_PL2F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR2,2))) +#define TSB_PL_FR2_PL3F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR2,3))) +#define TSB_PL_FR2_PL6F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR2,6))) +#define TSB_PL_FR3_PL0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR3,0))) +#define TSB_PL_FR3_PL1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR3,1))) +#define TSB_PL_OD_PL0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->OD,0))) +#define TSB_PL_OD_PL1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->OD,1))) +#define TSB_PL_OD_PL2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->OD,2))) +#define TSB_PL_OD_PL3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->OD,3))) +#define TSB_PL_OD_PL4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->OD,4))) +#define TSB_PL_OD_PL5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->OD,5))) +#define TSB_PL_OD_PL6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->OD,6))) +#define TSB_PL_PUP_PL0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PUP,0))) +#define TSB_PL_PUP_PL1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PUP,1))) +#define TSB_PL_PUP_PL2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PUP,2))) +#define TSB_PL_PUP_PL3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PUP,3))) +#define TSB_PL_PUP_PL4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PUP,4))) +#define TSB_PL_PUP_PL5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PUP,5))) +#define TSB_PL_PUP_PL6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PUP,6))) +#define TSB_PL_PDN_PL0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PDN,0))) +#define TSB_PL_PDN_PL1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PDN,1))) +#define TSB_PL_PDN_PL2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PDN,2))) +#define TSB_PL_PDN_PL3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PDN,3))) +#define TSB_PL_PDN_PL4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PDN,4))) +#define TSB_PL_PDN_PL5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PDN,5))) +#define TSB_PL_PDN_PL6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PDN,6))) +#define TSB_PL_IE_PL0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->IE,0))) +#define TSB_PL_IE_PL1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->IE,1))) +#define TSB_PL_IE_PL2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->IE,2))) +#define TSB_PL_IE_PL3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->IE,3))) +#define TSB_PL_IE_PL4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->IE,4))) +#define TSB_PL_IE_PL5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->IE,5))) +#define TSB_PL_IE_PL6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->IE,6))) + + +/* */ +#define TSB_PM_DATA_PM0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->DATA,0))) +#define TSB_PM_DATA_PM1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->DATA,1))) +#define TSB_PM_DATA_PM2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->DATA,2))) +#define TSB_PM_DATA_PM3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->DATA,3))) +#define TSB_PM_DATA_PM4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->DATA,4))) +#define TSB_PM_DATA_PM5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->DATA,5))) +#define TSB_PM_DATA_PM6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->DATA,6))) +#define TSB_PM_CR_PM0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->CR,0))) +#define TSB_PM_CR_PM1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->CR,1))) +#define TSB_PM_CR_PM2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->CR,2))) +#define TSB_PM_CR_PM3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->CR,3))) +#define TSB_PM_CR_PM4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->CR,4))) +#define TSB_PM_CR_PM5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->CR,5))) +#define TSB_PM_CR_PM6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->CR,6))) +#define TSB_PM_FR1_PM0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR1,0))) +#define TSB_PM_FR1_PM1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR1,1))) +#define TSB_PM_FR1_PM2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR1,2))) +#define TSB_PM_FR1_PM3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR1,3))) +#define TSB_PM_FR1_PM4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR1,4))) +#define TSB_PM_FR2_PM1F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR2,1))) +#define TSB_PM_FR2_PM2F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR2,2))) +#define TSB_PM_FR2_PM3F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR2,3))) +#define TSB_PM_FR2_PM4F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR2,4))) +#define TSB_PM_FR3_PM0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR3,0))) +#define TSB_PM_FR3_PM1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR3,1))) +#define TSB_PM_FR3_PM2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR3,2))) +#define TSB_PM_FR3_PM3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR3,3))) +#define TSB_PM_FR3_PM4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR3,4))) +#define TSB_PM_FR4_PM0F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR4,0))) +#define TSB_PM_FR4_PM1F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR4,1))) +#define TSB_PM_FR4_PM2F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR4,2))) +#define TSB_PM_FR4_PM3F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR4,3))) +#define TSB_PM_FR4_PM4F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR4,4))) +#define TSB_PM_FR4_PM5F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR4,5))) +#define TSB_PM_FR5_PM0F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR5,0))) +#define TSB_PM_FR5_PM1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR5,1))) +#define TSB_PM_FR5_PM2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR5,2))) +#define TSB_PM_FR5_PM3F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR5,3))) +#define TSB_PM_FR6_PM0F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR6,0))) +#define TSB_PM_FR6_PM1F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR6,1))) +#define TSB_PM_FR6_PM2F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR6,2))) +#define TSB_PM_FR6_PM3F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR6,3))) +#define TSB_PM_FR6_PM4F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR6,4))) +#define TSB_PM_OD_PM0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->OD,0))) +#define TSB_PM_OD_PM1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->OD,1))) +#define TSB_PM_OD_PM2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->OD,2))) +#define TSB_PM_OD_PM3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->OD,3))) +#define TSB_PM_OD_PM4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->OD,4))) +#define TSB_PM_OD_PM5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->OD,5))) +#define TSB_PM_OD_PM6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->OD,6))) +#define TSB_PM_PUP_PM0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PUP,0))) +#define TSB_PM_PUP_PM1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PUP,1))) +#define TSB_PM_PUP_PM2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PUP,2))) +#define TSB_PM_PUP_PM3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PUP,3))) +#define TSB_PM_PUP_PM4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PUP,4))) +#define TSB_PM_PUP_PM5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PUP,5))) +#define TSB_PM_PUP_PM6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PUP,6))) +#define TSB_PM_PDN_PM0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PDN,0))) +#define TSB_PM_PDN_PM1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PDN,1))) +#define TSB_PM_PDN_PM2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PDN,2))) +#define TSB_PM_PDN_PM3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PDN,3))) +#define TSB_PM_PDN_PM4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PDN,4))) +#define TSB_PM_PDN_PM5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PDN,5))) +#define TSB_PM_PDN_PM6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PDN,6))) +#define TSB_PM_IE_PM0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->IE,0))) +#define TSB_PM_IE_PM1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->IE,1))) +#define TSB_PM_IE_PM2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->IE,2))) +#define TSB_PM_IE_PM3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->IE,3))) +#define TSB_PM_IE_PM4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->IE,4))) +#define TSB_PM_IE_PM5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->IE,5))) +#define TSB_PM_IE_PM6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->IE,6))) + + +/* */ +#define TSB_PN_DATA_PN0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->DATA,0))) +#define TSB_PN_DATA_PN1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->DATA,1))) +#define TSB_PN_DATA_PN2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->DATA,2))) +#define TSB_PN_DATA_PN3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->DATA,3))) +#define TSB_PN_DATA_PN4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->DATA,4))) +#define TSB_PN_DATA_PN5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->DATA,5))) +#define TSB_PN_CR_PN0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->CR,0))) +#define TSB_PN_CR_PN1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->CR,1))) +#define TSB_PN_CR_PN2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->CR,2))) +#define TSB_PN_CR_PN3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->CR,3))) +#define TSB_PN_CR_PN4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->CR,4))) +#define TSB_PN_CR_PN5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->CR,5))) +#define TSB_PN_FR3_PN0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR3,0))) +#define TSB_PN_FR3_PN1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR3,1))) +#define TSB_PN_FR3_PN2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR3,2))) +#define TSB_PN_FR3_PN3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR3,3))) +#define TSB_PN_FR3_PN4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR3,4))) +#define TSB_PN_FR3_PN5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR3,5))) +#define TSB_PN_FR4_PN0F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR4,0))) +#define TSB_PN_FR4_PN1F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR4,1))) +#define TSB_PN_FR4_PN2F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR4,2))) +#define TSB_PN_FR5_PN3F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR5,3))) +#define TSB_PN_OD_PN0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->OD,0))) +#define TSB_PN_OD_PN1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->OD,1))) +#define TSB_PN_OD_PN2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->OD,2))) +#define TSB_PN_OD_PN3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->OD,3))) +#define TSB_PN_OD_PN4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->OD,4))) +#define TSB_PN_OD_PN5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->OD,5))) +#define TSB_PN_PUP_PN0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PUP,0))) +#define TSB_PN_PUP_PN1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PUP,1))) +#define TSB_PN_PUP_PN2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PUP,2))) +#define TSB_PN_PUP_PN3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PUP,3))) +#define TSB_PN_PUP_PN4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PUP,4))) +#define TSB_PN_PUP_PN5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PUP,5))) +#define TSB_PN_PDN_PN0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PDN,0))) +#define TSB_PN_PDN_PN1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PDN,1))) +#define TSB_PN_PDN_PN2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PDN,2))) +#define TSB_PN_PDN_PN3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PDN,3))) +#define TSB_PN_PDN_PN4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PDN,4))) +#define TSB_PN_PDN_PN5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PDN,5))) +#define TSB_PN_IE_PN0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->IE,0))) +#define TSB_PN_IE_PN1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->IE,1))) +#define TSB_PN_IE_PN2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->IE,2))) +#define TSB_PN_IE_PN3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->IE,3))) +#define TSB_PN_IE_PN4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->IE,4))) +#define TSB_PN_IE_PN5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->IE,5))) + + +/* */ +#define TSB_PP_DATA_PP0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->DATA,0))) +#define TSB_PP_DATA_PP1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->DATA,1))) +#define TSB_PP_DATA_PP2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->DATA,2))) +#define TSB_PP_DATA_PP3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->DATA,3))) +#define TSB_PP_CR_PP0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->CR,0))) +#define TSB_PP_CR_PP1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->CR,1))) +#define TSB_PP_CR_PP2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->CR,2))) +#define TSB_PP_CR_PP3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->CR,3))) +#define TSB_PP_FR1_PP0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR1,0))) +#define TSB_PP_FR1_PP1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR1,1))) +#define TSB_PP_FR1_PP2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR1,2))) +#define TSB_PP_FR3_PP0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR3,0))) +#define TSB_PP_FR3_PP1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR3,1))) +#define TSB_PP_FR3_PP2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR3,2))) +#define TSB_PP_FR4_PP0F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR4,0))) +#define TSB_PP_FR4_PP1F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR4,1))) +#define TSB_PP_FR4_PP2F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR4,2))) +#define TSB_PP_OD_PP0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->OD,0))) +#define TSB_PP_OD_PP1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->OD,1))) +#define TSB_PP_OD_PP2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->OD,2))) +#define TSB_PP_OD_PP3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->OD,3))) +#define TSB_PP_PUP_PP0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PUP,0))) +#define TSB_PP_PUP_PP1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PUP,1))) +#define TSB_PP_PUP_PP2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PUP,2))) +#define TSB_PP_PUP_PP3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PUP,3))) +#define TSB_PP_PDN_PP0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PDN,0))) +#define TSB_PP_PDN_PP1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PDN,1))) +#define TSB_PP_PDN_PP2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PDN,2))) +#define TSB_PP_PDN_PP3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PDN,3))) +#define TSB_PP_IE_PP0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->IE,0))) +#define TSB_PP_IE_PP1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->IE,1))) +#define TSB_PP_IE_PP2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->IE,2))) +#define TSB_PP_IE_PP3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->IE,3))) + + +/* */ +#define TSB_PR_DATA_PR0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->DATA,0))) +#define TSB_PR_DATA_PR1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->DATA,1))) +#define TSB_PR_DATA_PR2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->DATA,2))) +#define TSB_PR_DATA_PR3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->DATA,3))) +#define TSB_PR_CR_PR0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->CR,0))) +#define TSB_PR_CR_PR1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->CR,1))) +#define TSB_PR_CR_PR2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->CR,2))) +#define TSB_PR_CR_PR3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->CR,3))) +#define TSB_PR_FR3_PR0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR3,0))) +#define TSB_PR_FR3_PR1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR3,1))) +#define TSB_PR_FR3_PR2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR3,2))) +#define TSB_PR_FR4_PR0F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR4,0))) +#define TSB_PR_FR4_PR1F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR4,1))) +#define TSB_PR_FR4_PR2F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR4,2))) +#define TSB_PR_OD_PR0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->OD,0))) +#define TSB_PR_OD_PR1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->OD,1))) +#define TSB_PR_OD_PR2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->OD,2))) +#define TSB_PR_OD_PR3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->OD,3))) +#define TSB_PR_PUP_PR0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PUP,0))) +#define TSB_PR_PUP_PR1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PUP,1))) +#define TSB_PR_PUP_PR2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PUP,2))) +#define TSB_PR_PUP_PR3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PUP,3))) +#define TSB_PR_PDN_PR0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PDN,0))) +#define TSB_PR_PDN_PR1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PDN,1))) +#define TSB_PR_PDN_PR2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PDN,2))) +#define TSB_PR_PDN_PR3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PDN,3))) +#define TSB_PR_IE_PR0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->IE,0))) +#define TSB_PR_IE_PR1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->IE,1))) +#define TSB_PR_IE_PR2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->IE,2))) +#define TSB_PR_IE_PR3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->IE,3))) + + +/* */ +#define TSB_RTC_ADJCTL_AJEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_RTC->ADJCTL,0))) + + +/* */ +#define TSB_RMC0_EN_RMCEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC0->EN,0))) +#define TSB_RMC0_REN_RMCREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC0->REN,0))) +#define TSB_RMC0_RCR2_RMCPHM (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC0->RCR2,24))) +#define TSB_RMC0_RCR2_RMCLD (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC0->RCR2,25))) +#define TSB_RMC0_RCR2_RMCEDIEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC0->RCR2,30))) +#define TSB_RMC0_RCR2_RMCLIEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC0->RCR2,31))) +#define TSB_RMC0_RCR4_RMCPO (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC0->RCR4,7))) +#define TSB_RMC0_RSTAT_RMCRLDR (*((__I uint32_t *)BITBAND_PERI(&TSB_RMC0->RSTAT,7))) +#define TSB_RMC0_RSTAT_RMCEDIF (*((__I uint32_t *)BITBAND_PERI(&TSB_RMC0->RSTAT,12))) +#define TSB_RMC0_RSTAT_RMCDMAXIF (*((__I uint32_t *)BITBAND_PERI(&TSB_RMC0->RSTAT,13))) +#define TSB_RMC0_RSTAT_RMCLOIF (*((__I uint32_t *)BITBAND_PERI(&TSB_RMC0->RSTAT,14))) +#define TSB_RMC0_RSTAT_RMCRLIF (*((__I uint32_t *)BITBAND_PERI(&TSB_RMC0->RSTAT,15))) +#define TSB_RMC0_FSSEL_RMCCLK (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC0->FSSEL,0))) + + +/* */ +#define TSB_OFD_RST_OFDRSTEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_OFD->RST,0))) +#define TSB_OFD_STAT_FRQERR (*((__I uint32_t *)BITBAND_PERI(&TSB_OFD->STAT,0))) +#define TSB_OFD_STAT_OFDBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_OFD->STAT,1))) +#define TSB_OFD_MON_OFDMON (*((__IO uint32_t *)BITBAND_PERI(&TSB_OFD->MON,0))) + + +/* */ +#define TSB_CG_OSCCR_IHOSC1EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->OSCCR,0))) +#define TSB_CG_OSCCR_IHOSC2EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->OSCCR,3))) +#define TSB_CG_OSCCR_OSCSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->OSCCR,8))) +#define TSB_CG_OSCCR_OSCF (*((__I uint32_t *)BITBAND_PERI(&TSB_CG->OSCCR,9))) +#define TSB_CG_OSCCR_IHOSC1F (*((__I uint32_t *)BITBAND_PERI(&TSB_CG->OSCCR,16))) +#define TSB_CG_OSCCR_IHOSC2F (*((__I uint32_t *)BITBAND_PERI(&TSB_CG->OSCCR,19))) +#define TSB_CG_SCOCR_SCOEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->SCOCR,0))) +#define TSB_CG_PLL0SEL_PLL0ON (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->PLL0SEL,0))) +#define TSB_CG_PLL0SEL_PLL0SEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->PLL0SEL,1))) +#define TSB_CG_PLL0SEL_PLL0ST (*((__I uint32_t *)BITBAND_PERI(&TSB_CG->PLL0SEL,2))) +#define TSB_CG_WUPHCR_WUON (*((__O uint32_t *)BITBAND_PERI(&TSB_CG->WUPHCR,0))) +#define TSB_CG_WUPHCR_WUEF (*((__I uint32_t *)BITBAND_PERI(&TSB_CG->WUPHCR,1))) +#define TSB_CG_WUPHCR_WUCLK (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->WUPHCR,8))) +#define TSB_CG_WUPLCR_WULON (*((__O uint32_t *)BITBAND_PERI(&TSB_CG->WUPLCR,0))) +#define TSB_CG_WUPLCR_WULEF (*((__I uint32_t *)BITBAND_PERI(&TSB_CG->WUPLCR,1))) +#define TSB_CG_FSYSENA_IPENA00 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,0))) +#define TSB_CG_FSYSENA_IPENA01 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,1))) +#define TSB_CG_FSYSENA_IPENA02 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,2))) +#define TSB_CG_FSYSENA_IPENA03 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,3))) +#define TSB_CG_FSYSENA_IPENA04 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,4))) +#define TSB_CG_FSYSENA_IPENA05 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,5))) +#define TSB_CG_FSYSENA_IPENA06 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,6))) +#define TSB_CG_FSYSENA_IPENA07 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,7))) +#define TSB_CG_FSYSENA_IPENA08 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,8))) +#define TSB_CG_FSYSENA_IPENA09 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,9))) +#define TSB_CG_FSYSENA_IPENA10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,10))) +#define TSB_CG_FSYSENA_IPENA11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,11))) +#define TSB_CG_FSYSENA_IPENA12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,12))) +#define TSB_CG_FSYSENA_IPENA13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,13))) +#define TSB_CG_FSYSENA_IPENA14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,14))) +#define TSB_CG_FSYSENA_IPENA15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,15))) +#define TSB_CG_FSYSENA_IPENA16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,16))) +#define TSB_CG_FSYSENA_IPENA17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,17))) +#define TSB_CG_FSYSENA_IPENA18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,18))) +#define TSB_CG_FSYSENA_IPENA19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,19))) +#define TSB_CG_FSYSENA_IPENA20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,20))) +#define TSB_CG_FSYSENA_IPENA21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,21))) +#define TSB_CG_FSYSENA_IPENA22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,22))) +#define TSB_CG_FSYSENA_IPENA23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,23))) +#define TSB_CG_FSYSENA_IPENA24 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,24))) +#define TSB_CG_FSYSENA_IPENA25 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,25))) +#define TSB_CG_FSYSENA_IPENA26 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,26))) +#define TSB_CG_FSYSENA_IPENA27 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,27))) +#define TSB_CG_FSYSENA_IPENA28 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,28))) +#define TSB_CG_FSYSENA_IPENA29 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,29))) +#define TSB_CG_FSYSENA_IPENA30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,30))) +#define TSB_CG_FSYSENA_IPENA31 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,31))) +#define TSB_CG_FSYSENB_IPENB00 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,0))) +#define TSB_CG_FSYSENB_IPENB01 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,1))) +#define TSB_CG_FSYSENB_IPENB02 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,2))) +#define TSB_CG_FSYSENB_IPENB03 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,3))) +#define TSB_CG_FSYSENB_IPENB04 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,4))) +#define TSB_CG_FSYSENB_IPENB05 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,5))) +#define TSB_CG_FSYSENB_IPENB06 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,6))) +#define TSB_CG_FSYSENB_IPENB07 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,7))) +#define TSB_CG_FSYSENB_IPENB31 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,31))) +#define TSB_CG_SPCLKEN_TRCKEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->SPCLKEN,0))) +#define TSB_CG_SPCLKEN_ADCKEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->SPCLKEN,16))) + + +/* */ +#define TSB_TRM_OSCEN_TRIMEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TRM->OSCEN,0))) + + + +/* */ +#define TSB_IMN_FLGNMI_INT000FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLGNMI,0))) +#define TSB_IMN_FLGNMI_INT016FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLGNMI,16))) +#define TSB_IMN_FLG1_INT032FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,0))) +#define TSB_IMN_FLG1_INT033FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,1))) +#define TSB_IMN_FLG1_INT034FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,2))) +#define TSB_IMN_FLG1_INT048FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,16))) +#define TSB_IMN_FLG1_INT049FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,17))) +#define TSB_IMN_FLG3_INT096FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,0))) +#define TSB_IMN_FLG3_INT097FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,1))) +#define TSB_IMN_FLG3_INT098FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,2))) +#define TSB_IMN_FLG3_INT099FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,3))) +#define TSB_IMN_FLG3_INT100FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,4))) +#define TSB_IMN_FLG3_INT101FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,5))) +#define TSB_IMN_FLG3_INT102FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,6))) +#define TSB_IMN_FLG3_INT103FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,7))) +#define TSB_IMN_FLG3_INT104FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,8))) +#define TSB_IMN_FLG3_INT105FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,9))) +#define TSB_IMN_FLG3_INT106FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,10))) +#define TSB_IMN_FLG3_INT107FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,11))) +#define TSB_IMN_FLG3_INT108FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,12))) +#define TSB_IMN_FLG3_INT109FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,13))) +#define TSB_IMN_FLG3_INT110FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,14))) +#define TSB_IMN_FLG3_INT111FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,15))) +#define TSB_IMN_FLG3_INT112FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,16))) +#define TSB_IMN_FLG3_INT113FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,17))) +#define TSB_IMN_FLG3_INT114FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,18))) +#define TSB_IMN_FLG3_INT115FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,19))) +#define TSB_IMN_FLG3_INT116FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,20))) +#define TSB_IMN_FLG3_INT117FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,21))) +#define TSB_IMN_FLG3_INT118FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,22))) +#define TSB_IMN_FLG3_INT119FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,23))) +#define TSB_IMN_FLG3_INT120FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,24))) +#define TSB_IMN_FLG3_INT121FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,25))) +#define TSB_IMN_FLG3_INT122FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,26))) +#define TSB_IMN_FLG3_INT123FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,27))) +#define TSB_IMN_FLG3_INT124FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,28))) +#define TSB_IMN_FLG3_INT125FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,29))) +#define TSB_IMN_FLG3_INT126FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,30))) +#define TSB_IMN_FLG3_INT127FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,31))) +#define TSB_IMN_FLG4_INT128FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,0))) +#define TSB_IMN_FLG4_INT129FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,1))) +#define TSB_IMN_FLG4_INT130FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,2))) +#define TSB_IMN_FLG4_INT131FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,3))) +#define TSB_IMN_FLG4_INT132FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,4))) +#define TSB_IMN_FLG4_INT133FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,5))) +#define TSB_IMN_FLG4_INT134FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,6))) +#define TSB_IMN_FLG4_INT135FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,7))) +#define TSB_IMN_FLG4_INT136FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,8))) +#define TSB_IMN_FLG4_INT137FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,9))) +#define TSB_IMN_FLG4_INT138FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,10))) +#define TSB_IMN_FLG4_INT139FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,11))) +#define TSB_IMN_FLG4_INT140FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,12))) +#define TSB_IMN_FLG4_INT141FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,13))) +#define TSB_IMN_FLG4_INT142FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,14))) + + +/* */ +#define TSB_PMD0_MDEN_PWMEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDEN,0))) +#define TSB_PMD0_MDCR_PWMMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDCR,0))) +#define TSB_PMD0_MDCR_PINT (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDCR,3))) +#define TSB_PMD0_MDCR_DTYMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDCR,4))) +#define TSB_PMD0_MDCR_SYNTMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDCR,5))) +#define TSB_PMD0_MDCR_PWMCK (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDCR,6))) +#define TSB_PMD0_MDCR_DTCREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDCR,7))) +#define TSB_PMD0_CNTSTA_UPDWN (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD0->CNTSTA,0))) +#define TSB_PMD0_MDOUT_UPWM (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDOUT,8))) +#define TSB_PMD0_MDOUT_VPWM (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDOUT,9))) +#define TSB_PMD0_MDOUT_WPWM (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDOUT,10))) +#define TSB_PMD0_MDPOT_POLL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDPOT,2))) +#define TSB_PMD0_MDPOT_POLH (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDPOT,3))) +#define TSB_PMD0_EMGCR_EMGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGCR,0))) +#define TSB_PMD0_EMGCR_EMGRS (*((__O uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGCR,1))) +#define TSB_PMD0_EMGCR_INHEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGCR,5))) +#define TSB_PMD0_EMGSTA_EMGST (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGSTA,0))) +#define TSB_PMD0_EMGSTA_EMGI (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGSTA,1))) +#define TSB_PMD0_OVVCR_OVVEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVCR,0))) +#define TSB_PMD0_OVVCR_OVVRS (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVCR,1))) +#define TSB_PMD0_OVVCR_OVVISEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVCR,2))) +#define TSB_PMD0_OVVCR_ADIN0EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVCR,5))) +#define TSB_PMD0_OVVCR_ADIN1EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVCR,6))) +#define TSB_PMD0_OVVSTA_OVVST (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVSTA,0))) +#define TSB_PMD0_OVVSTA_OVVI (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVSTA,1))) +#define TSB_PMD0_TRGCR_TRG0BE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->TRGCR,3))) +#define TSB_PMD0_TRGCR_TRG1BE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->TRGCR,7))) +#define TSB_PMD0_TRGCR_TRG2BE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->TRGCR,11))) +#define TSB_PMD0_TRGCR_TRG3BE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->TRGCR,15))) +#define TSB_PMD0_TRGMD_EMGTGE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->TRGMD,0))) +#define TSB_PMD0_TRGMD_TRGOUT (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->TRGMD,1))) + + +/* Encoder Input (ENC) */ +#define TSB_EN0_TNCR_ENRUN (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->TNCR,6))) +#define TSB_EN0_TNCR_ZEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->TNCR,7))) +#define TSB_EN0_TNCR_ENCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_EN0->TNCR,10))) +#define TSB_EN0_TNCR_SFTCAP (*((__O uint32_t *)BITBAND_PERI(&TSB_EN0->TNCR,11))) +#define TSB_EN0_TNCR_TRGCAPMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->TNCR,12))) +#define TSB_EN0_TNCR_P3EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->TNCR,16))) +#define TSB_EN0_TNCR_SDTEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->TNCR,21))) +#define TSB_EN0_TNCR_MCMPMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->TNCR,24))) +#define TSB_EN0_TNCR_TOVMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->TNCR,25))) +#define TSB_EN0_TNCR_CMPSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->TNCR,28))) +#define TSB_EN0_STS_INERR (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->STS,0))) +#define TSB_EN0_STS_PDERR (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->STS,1))) +#define TSB_EN0_STS_SKPDT (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->STS,2))) +#define TSB_EN0_STS_ZDET (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->STS,12))) +#define TSB_EN0_STS_UD (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->STS,13))) +#define TSB_EN0_STS_REVERR (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->STS,14))) +#define TSB_EN0_INPCR_SYNCSPLEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->INPCR,0))) +#define TSB_EN0_INPCR_SYNCSPLND (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->INPCR,1))) +#define TSB_EN0_INPCR_SYNCNCZEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->INPCR,2))) +#define TSB_EN0_INPCR_PDSTT (*((__O uint32_t *)BITBAND_PERI(&TSB_EN0->INPCR,6))) +#define TSB_EN0_INPCR_PDSTP (*((__O uint32_t *)BITBAND_PERI(&TSB_EN0->INPCR,7))) +#define TSB_EN0_INPMON_SPLMONA (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->INPMON,0))) +#define TSB_EN0_INPMON_SPLMONB (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->INPMON,1))) +#define TSB_EN0_INPMON_SPLMONZ (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->INPMON,2))) +#define TSB_EN0_INPMON_DETMONA (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->INPMON,4))) +#define TSB_EN0_INPMON_DETMONB (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->INPMON,5))) +#define TSB_EN0_INPMON_DETMONZ (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->INPMON,6))) +#define TSB_EN0_INTCR_TPLSIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->INTCR,0))) +#define TSB_EN0_INTCR_CAPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->INTCR,1))) +#define TSB_EN0_INTCR_ERRIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->INTCR,2))) +#define TSB_EN0_INTCR_CMPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->INTCR,3))) +#define TSB_EN0_INTCR_RLDIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->INTCR,4))) +#define TSB_EN0_INTCR_MCMPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->INTCR,5))) +#define TSB_EN0_INTF_TPLSF (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->INTF,0))) +#define TSB_EN0_INTF_CAPF (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->INTF,1))) +#define TSB_EN0_INTF_ERRF (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->INTF,2))) +#define TSB_EN0_INTF_INTCPF (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->INTF,3))) +#define TSB_EN0_INTF_RLDCPF (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->INTF,4))) +#define TSB_EN0_INTF_MCMPF (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->INTF,5))) + +/** @} */ /* End of group Device_Peripheral_registers */ + +#ifdef __cplusplus +} +#endif + +#endif /* __TMPM3H6_H__ */ + +/** @} */ /* End of group TMPM3H6 */ +/** @} */ /* End of group TOSHIBA_TXZ_MICROCONTROLLER */ diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/device/TOOLCHAIN_ARM_STD/startup_TMPM3H6.S b/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/device/TOOLCHAIN_ARM_STD/startup_TMPM3H6.S new file mode 100644 index 00000000000..c987e77da48 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/device/TOOLCHAIN_ARM_STD/startup_TMPM3H6.S @@ -0,0 +1,481 @@ +;/** +; ******************************************************************************* +; * @file startup_TMPM3H6.s +; * @brief CMSIS Cortex-M3 Core Device Startup File for the +; * TOSHIBA 'TMPM3H6' Device Series +; * @version V1.0.0.0 +; * $Date:: #$ +; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +; * +; * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LISENCE AGREEMENT. +; * +; * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved +; ******************************************************************************* +; */ + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__initial_sp EQU 0x20004000 + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD INT00_IRQHandler ; 0: Interrupt Pin0 + DCD INT01_IRQHandler ; 1: Interrupt Pin1 + DCD INT02_IRQHandler ; 2: Interrupt Pin2 + DCD INT03_IRQHandler ; 3: Interrupt Pin3 + DCD INT04_IRQHandler ; 4: Interrupt Pin4 + DCD INT05_IRQHandler ; 5: Interrupt Pin5 + DCD INT06_IRQHandler ; 6: Interrupt Pin6 + DCD INT07_IRQHandler ; 7: Interrupt Pin7 + DCD INT08_IRQHandler ; 8: Interrupt Pin8 + DCD INT09_IRQHandler ; 9: Interrupt Pin9 + DCD INT10_IRQHandler ; 10: Interrupt Pin10 + DCD INT11_IRQHandler ; 11: Interrupt Pin11 + DCD INT12_IRQHandler ; 12: Interrupt Pin12 + DCD INT13_IRQHandler ; 13: Interrupt Pin13 + DCD INT14_IRQHandler ; 14: Interrupt Pin14 + DCD INT15_IRQHandler ; 15: Interrupt Pin15 + DCD INTEMG0_IRQHandler ; 16: PMD0 EMG interrupt + DCD INTOVV0_IRQHandler ; 17: PMD0 OVV interrupt + DCD INTPMD0_IRQHandler ; 18: PMD0 interrupt + DCD INTENC00_IRQHandler ; 19: Encoder 0 interrupt 0 + DCD INTENC01_IRQHandler ; 20: Encoder 0 interrupt 1 + DCD INTADAPDA_IRQHandler ; 21: ADC conversion triggered by PMD is finished A + DCD INTADAPDB_IRQHandler ; 22: ADC conversion triggered by PMD is finished B + DCD INTADACP0_IRQHandler ; 23: ADC conversion monitoring function interrupt 0 + DCD INTADACP1_IRQHandler ; 24: ADC conversion monitoring function interrupt 1 + DCD INTADATRG_IRQHandler ; 25: ADC conversion triggered by General purpose is finished + DCD INTADASGL_IRQHandler ; 26: ADC conversion triggered by Single program is finished + DCD INTADACNT_IRQHandler ; 27: ADC conversion triggered by Continuity program is finished + DCD INTT0RX_IRQHandler ; 28: TSPI/SIO reception (channel 0) + DCD INTT0TX_IRQHandler ; 29: TSPI/SIO transmit (channel 0) + DCD INTT0ERR_IRQHandler ; 30: TSPI/SIO error (channel 0) + DCD INTT1RX_IRQHandler ; 31: TSPI/SIO reception (channel 1) + DCD INTT1TX_IRQHandler ; 32: TSPI/SIO transmit (channel 1) + DCD INTT1ERR_IRQHandler ; 33: TSPI/SIO error (channel 1) + DCD INTI2CWUP_IRQHandler ; 34: Serial bus interface (WakeUp) interrupt (channel 0) + DCD INTI2C0_IRQHandler ; 35: I2C0 transmission and reception interrupt + DCD INTI2C0AL_IRQHandler ; 36: I2C0 arbitration lost interrupt + DCD INTI2C0BF_IRQHandler ; 37: I2C0 bus free interrupt + DCD INTI2C0NA_IRQHandler ; 38: I2C0 no ack interrupt + DCD INTI2C1_IRQHandler ; 39: I2C1 transmission and reception interrupt + DCD INTI2C1AL_IRQHandler ; 40: I2C1 arbitration lost interrupt + DCD INTI2C1BF_IRQHandler ; 41: I2C1 bus free interrupt + DCD INTI2C1NA_IRQHandler ; 42: I2C1 no ack interrupt + DCD INTI2C2_IRQHandler ; 43: I2C2 transmission and reception interrupt + DCD INTI2C2AL_IRQHandler ; 44: I2C2 arbitration lost interrupt + DCD INTI2C2BF_IRQHandler ; 45: I2C2 bus free interrupt + DCD INTI2C2NA_IRQHandler ; 46: I2C2 no ack interrupt + DCD INTUART0RX_IRQHandler ; 47: UART reception (channel 0) + DCD INTUART0TX_IRQHandler ; 48: UART transmit (channel 0) + DCD INTUART0ERR_IRQHandler ; 49: UART error (channel 0) + DCD INTUART1RX_IRQHandler ; 50: UART reception (channel 1) + DCD INTUART1TX_IRQHandler ; 51: UART transmit (channel 1) + DCD INTUART1ERR_IRQHandler ; 52: UART error (channel 1) + DCD INTUART2RX_IRQHandler ; 53: UART reception (channel 2) + DCD INTUART2TX_IRQHandler ; 54: UART transmit (channel 2) + DCD INTUART2ERR_IRQHandler ; 55: UART error (channel 2) + DCD INTT32A00A_IRQHandler ; 56: 32bit T32A00A compare match detection 0 / Over flow / under flow + DCD INTT32A00ACAP0_IRQHandler ; 57: 32bit T32A00A input capture 0 + DCD INTT32A00ACAP1_IRQHandler ; 58: 32bit T32A00A input capture 1 + DCD INTT32A00B_IRQHandler ; 59: 32bit T32A00B compare match detection 0 / Over flow / under flow + DCD INTT32A00BCAP0_IRQHandler ; 60: 32bit T32A00B input capture 0 + DCD INTT32A00BCAP1_IRQHandler ; 61: 32bit T32A00B input capture 1 + DCD INTT32A00C_IRQHandler ; 62: 32bit T32A00C compare match detection 0 / Over flow / under flow + DCD INTT32A00CCAP0_IRQHandler ; 63: 32bit T32A00C input capture 0 + DCD INTT32A00CCAP1_IRQHandler ; 64: 32bit T32A00C input capture 1 + DCD INTT32A01A_IRQHandler ; 65: 32bit T32A01A compare match detection 0 / Over flow / under flow + DCD INTT32A01ACAP0_IRQHandler ; 66: 32bit T32A01A input capture 0 + DCD INTT32A01ACAP1_IRQHandler ; 67: 32bit T32A01A input capture 1 + DCD INTT32A01B_IRQHandler ; 68: 32bit T32A01B compare match detection 0 / Over flow / under flow + DCD INTT32A01BCAP0_IRQHandler ; 69: 32bit T32A01B input capture 0 + DCD INTT32A01BCAP1_IRQHandler ; 70: 32bit T32A01B input capture 1 + DCD INTT32A01C_IRQHandler ; 71: 32bit T32A01C compare match detection 0 / Over flow / under flow + DCD INTT32A01CCAP0_IRQHandler ; 72: 32bit T32A01C input capture 0 + DCD INTT32A01CCAP1_IRQHandler ; 73: 32bit T32A01C input capture 1 + DCD INTT32A02A_IRQHandler ; 74: 32bit T32A02A compare match detection 0 / Over flow / under flow + DCD INTT32A02ACAP0_IRQHandler ; 75: 32bit T32A02A input capture 0 + DCD INTT32A02ACAP1_IRQHandler ; 76: 32bit T32A02A input capture 1 + DCD INTT32A02B_IRQHandler ; 77: 32bit T32A02B compare match detection 0 / Over flow / under flow + DCD INTT32A02BCAP0_IRQHandler ; 78: 32bit T32A02B input capture 0 + DCD INTT32A02BCAP1_IRQHandler ; 79: 32bit T32A02B input capture 1 + DCD INTT32A02C_IRQHandler ; 80: 32bit T32A02C compare match detection 0 / Over flow / under flow + DCD INTT32A02CCAP0_IRQHandler ; 81: 32bit T32A02C input capture 0 + DCD INTT32A02CCAP1_IRQHandler ; 82: 32bit T32A02C input capture 1 + DCD INTT32A03A_IRQHandler ; 83: 32bit T32A03A compare match detection 0 / Over flow / under flow + DCD INTT32A03ACAP0_IRQHandler ; 84: 32bit T32A03A input capture 0 + DCD INTT32A03ACAP1_IRQHandler ; 85: 32bit T32A03A input capture 1 + DCD INTT32A03B_IRQHandler ; 86: 32bit T32A03B compare match detection 0 / Over flow / under flow + DCD INTT32A03BCAP0_IRQHandler ; 87: 32bit T32A03B input capture 0 + DCD INTT32A03BCAP1_IRQHandler ; 88: 32bit T32A03B input capture 1 + DCD INTT32A03C_IRQHandler ; 89: 32bit T32A03C compare match detection 0 / Over flow / under flow + DCD INTT32A03CCAP0_IRQHandler ; 90: 32bit T32A03C input capture 0 + DCD INTT32A03CCAP1_IRQHandler ; 91: 32bit T32A03C input capture 1 + DCD INTT32A04A_IRQHandler ; 92: 32bit T32A04A compare match detection 0 / Over flow / under flow + DCD INTT32A04ACAP0_IRQHandler ; 93: 32bit T32A04A input capture 0 + DCD INTT32A04ACAP1_IRQHandler ; 94: 32bit T32A04A input capture 1 + DCD INTT32A04B_IRQHandler ; 95: 32bit T32A04B compare match detection 0 / Over flow / under flow + DCD INTT32A04BCAP0_IRQHandler ; 96: 32bit T32A04B input capture 0 + DCD INTT32A04BCAP1_IRQHandler ; 97: 32bit T32A04B input capture 1 + DCD INTT32A04C_IRQHandler ; 98: 32bit T32A04C compare match detection 0 / Over flow / under flow + DCD INTT32A04CCAP0_IRQHandler ; 99: 32bit T32A04C input capture 0 + DCD INTT32A04CCAP1_IRQHandler ; 100: 32bit T32A04C input capture 1 + DCD INTT32A05A_IRQHandler ; 101: 32bit T32A05A compare match detection 0 / Over flow / under flow + DCD INTT32A05ACAP0_IRQHandler ; 102: 32bit T32A05A input capture 0 + DCD INTT32A05ACAP1_IRQHandler ; 103: 32bit T32A05A input capture 1 + DCD INTT32A05B_IRQHandler ; 104: 32bit T32A05B compare match detection 0 / Over flow / under flow + DCD INTT32A05BCAP0_IRQHandler ; 105: 32bit T32A05B input capture 0 + DCD INTT32A05BCAP1_IRQHandler ; 106: 32bit T32A05B input capture 1 + DCD INTT32A05C_IRQHandler ; 107: 32bit T32A05C compare match detection 0 / Over flow / under flow + DCD INTT32A05CCAP0_IRQHandler ; 108: 32bit T32A05C input capture 0 + DCD INTT32A05CCAP1_IRQHandler ; 109: 32bit T32A05C input capture 1 + DCD INTDMAATC_IRQHandler ; 110: DMA end of transfer + DCD INTDMAAERR_IRQHandler ; 111: DMA transfer error + DCD INTRTC_IRQHandler ; 112: Real time clock(XHz) interrupt + DCD 0 ; 113: Reserved + DCD INTRMC0_IRQHandler ; 114: Remote control reception interrupt + DCD INTFLCRDY_IRQHandler ; 115: Code FLASH Ready interrupt + DCD INTFLDRDY_IRQHandler ; 116: Data FLASH Ready interrupt + + + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT INT00_IRQHandler [WEAK] + EXPORT INT01_IRQHandler [WEAK] + EXPORT INT02_IRQHandler [WEAK] + EXPORT INT03_IRQHandler [WEAK] + EXPORT INT04_IRQHandler [WEAK] + EXPORT INT05_IRQHandler [WEAK] + EXPORT INT06_IRQHandler [WEAK] + EXPORT INT07_IRQHandler [WEAK] + EXPORT INT08_IRQHandler [WEAK] + EXPORT INT09_IRQHandler [WEAK] + EXPORT INT10_IRQHandler [WEAK] + EXPORT INT11_IRQHandler [WEAK] + EXPORT INT12_IRQHandler [WEAK] + EXPORT INT13_IRQHandler [WEAK] + EXPORT INT14_IRQHandler [WEAK] + EXPORT INT15_IRQHandler [WEAK] + EXPORT INTEMG0_IRQHandler [WEAK] + EXPORT INTOVV0_IRQHandler [WEAK] + EXPORT INTPMD0_IRQHandler [WEAK] + EXPORT INTENC00_IRQHandler [WEAK] + EXPORT INTENC01_IRQHandler [WEAK] + EXPORT INTADAPDA_IRQHandler [WEAK] + EXPORT INTADAPDB_IRQHandler [WEAK] + EXPORT INTADACP0_IRQHandler [WEAK] + EXPORT INTADACP1_IRQHandler [WEAK] + EXPORT INTADATRG_IRQHandler [WEAK] + EXPORT INTADASGL_IRQHandler [WEAK] + EXPORT INTADACNT_IRQHandler [WEAK] + EXPORT INTT0RX_IRQHandler [WEAK] + EXPORT INTT0TX_IRQHandler [WEAK] + EXPORT INTT0ERR_IRQHandler [WEAK] + EXPORT INTT1RX_IRQHandler [WEAK] + EXPORT INTT1TX_IRQHandler [WEAK] + EXPORT INTT1ERR_IRQHandler [WEAK] + EXPORT INTI2CWUP_IRQHandler [WEAK] + EXPORT INTI2C0_IRQHandler [WEAK] + EXPORT INTI2C0AL_IRQHandler [WEAK] + EXPORT INTI2C0BF_IRQHandler [WEAK] + EXPORT INTI2C0NA_IRQHandler [WEAK] + EXPORT INTI2C1_IRQHandler [WEAK] + EXPORT INTI2C1AL_IRQHandler [WEAK] + EXPORT INTI2C1BF_IRQHandler [WEAK] + EXPORT INTI2C1NA_IRQHandler [WEAK] + EXPORT INTI2C2_IRQHandler [WEAK] + EXPORT INTI2C2AL_IRQHandler [WEAK] + EXPORT INTI2C2BF_IRQHandler [WEAK] + EXPORT INTI2C2NA_IRQHandler [WEAK] + EXPORT INTUART0RX_IRQHandler [WEAK] + EXPORT INTUART0TX_IRQHandler [WEAK] + EXPORT INTUART0ERR_IRQHandler [WEAK] + EXPORT INTUART1RX_IRQHandler [WEAK] + EXPORT INTUART1TX_IRQHandler [WEAK] + EXPORT INTUART1ERR_IRQHandler [WEAK] + EXPORT INTUART2RX_IRQHandler [WEAK] + EXPORT INTUART2TX_IRQHandler [WEAK] + EXPORT INTUART2ERR_IRQHandler [WEAK] + EXPORT INTT32A00A_IRQHandler [WEAK] + EXPORT INTT32A00ACAP0_IRQHandler [WEAK] + EXPORT INTT32A00ACAP1_IRQHandler [WEAK] + EXPORT INTT32A00B_IRQHandler [WEAK] + EXPORT INTT32A00BCAP0_IRQHandler [WEAK] + EXPORT INTT32A00BCAP1_IRQHandler [WEAK] + EXPORT INTT32A00C_IRQHandler [WEAK] + EXPORT INTT32A00CCAP0_IRQHandler [WEAK] + EXPORT INTT32A00CCAP1_IRQHandler [WEAK] + EXPORT INTT32A01A_IRQHandler [WEAK] + EXPORT INTT32A01ACAP0_IRQHandler [WEAK] + EXPORT INTT32A01ACAP1_IRQHandler [WEAK] + EXPORT INTT32A01B_IRQHandler [WEAK] + EXPORT INTT32A01BCAP0_IRQHandler [WEAK] + EXPORT INTT32A01BCAP1_IRQHandler [WEAK] + EXPORT INTT32A01C_IRQHandler [WEAK] + EXPORT INTT32A01CCAP0_IRQHandler [WEAK] + EXPORT INTT32A01CCAP1_IRQHandler [WEAK] + EXPORT INTT32A02A_IRQHandler [WEAK] + EXPORT INTT32A02ACAP0_IRQHandler [WEAK] + EXPORT INTT32A02ACAP1_IRQHandler [WEAK] + EXPORT INTT32A02B_IRQHandler [WEAK] + EXPORT INTT32A02BCAP0_IRQHandler [WEAK] + EXPORT INTT32A02BCAP1_IRQHandler [WEAK] + EXPORT INTT32A02C_IRQHandler [WEAK] + EXPORT INTT32A02CCAP0_IRQHandler [WEAK] + EXPORT INTT32A02CCAP1_IRQHandler [WEAK] + EXPORT INTT32A03A_IRQHandler [WEAK] + EXPORT INTT32A03ACAP0_IRQHandler [WEAK] + EXPORT INTT32A03ACAP1_IRQHandler [WEAK] + EXPORT INTT32A03B_IRQHandler [WEAK] + EXPORT INTT32A03BCAP0_IRQHandler [WEAK] + EXPORT INTT32A03BCAP1_IRQHandler [WEAK] + EXPORT INTT32A03C_IRQHandler [WEAK] + EXPORT INTT32A03CCAP0_IRQHandler [WEAK] + EXPORT INTT32A03CCAP1_IRQHandler [WEAK] + EXPORT INTT32A04A_IRQHandler [WEAK] + EXPORT INTT32A04ACAP0_IRQHandler [WEAK] + EXPORT INTT32A04ACAP1_IRQHandler [WEAK] + EXPORT INTT32A04B_IRQHandler [WEAK] + EXPORT INTT32A04BCAP0_IRQHandler [WEAK] + EXPORT INTT32A04BCAP1_IRQHandler [WEAK] + EXPORT INTT32A04C_IRQHandler [WEAK] + EXPORT INTT32A04CCAP0_IRQHandler [WEAK] + EXPORT INTT32A04CCAP1_IRQHandler [WEAK] + EXPORT INTT32A05A_IRQHandler [WEAK] + EXPORT INTT32A05ACAP0_IRQHandler [WEAK] + EXPORT INTT32A05ACAP1_IRQHandler [WEAK] + EXPORT INTT32A05B_IRQHandler [WEAK] + EXPORT INTT32A05BCAP0_IRQHandler [WEAK] + EXPORT INTT32A05BCAP1_IRQHandler [WEAK] + EXPORT INTT32A05C_IRQHandler [WEAK] + EXPORT INTT32A05CCAP0_IRQHandler [WEAK] + EXPORT INTT32A05CCAP1_IRQHandler [WEAK] + EXPORT INTDMAATC_IRQHandler [WEAK] + EXPORT INTDMAAERR_IRQHandler [WEAK] + EXPORT INTRTC_IRQHandler [WEAK] + EXPORT INTRMC0_IRQHandler [WEAK] + EXPORT INTFLCRDY_IRQHandler [WEAK] + EXPORT INTFLDRDY_IRQHandler [WEAK] + +INT00_IRQHandler +INT01_IRQHandler +INT02_IRQHandler +INT03_IRQHandler +INT04_IRQHandler +INT05_IRQHandler +INT06_IRQHandler +INT07_IRQHandler +INT08_IRQHandler +INT09_IRQHandler +INT10_IRQHandler +INT11_IRQHandler +INT12_IRQHandler +INT13_IRQHandler +INT14_IRQHandler +INT15_IRQHandler +INTEMG0_IRQHandler +INTOVV0_IRQHandler +INTPMD0_IRQHandler +INTENC00_IRQHandler +INTENC01_IRQHandler +INTADAPDA_IRQHandler +INTADAPDB_IRQHandler +INTADACP0_IRQHandler +INTADACP1_IRQHandler +INTADATRG_IRQHandler +INTADASGL_IRQHandler +INTADACNT_IRQHandler +INTT0RX_IRQHandler +INTT0TX_IRQHandler +INTT0ERR_IRQHandler +INTT1RX_IRQHandler +INTT1TX_IRQHandler +INTT1ERR_IRQHandler +INTI2CWUP_IRQHandler +INTI2C0_IRQHandler +INTI2C0AL_IRQHandler +INTI2C0BF_IRQHandler +INTI2C0NA_IRQHandler +INTI2C1_IRQHandler +INTI2C1AL_IRQHandler +INTI2C1BF_IRQHandler +INTI2C1NA_IRQHandler +INTI2C2_IRQHandler +INTI2C2AL_IRQHandler +INTI2C2BF_IRQHandler +INTI2C2NA_IRQHandler +INTUART0RX_IRQHandler +INTUART0TX_IRQHandler +INTUART0ERR_IRQHandler +INTUART1RX_IRQHandler +INTUART1TX_IRQHandler +INTUART1ERR_IRQHandler +INTUART2RX_IRQHandler +INTUART2TX_IRQHandler +INTUART2ERR_IRQHandler +INTT32A00A_IRQHandler +INTT32A00ACAP0_IRQHandler +INTT32A00ACAP1_IRQHandler +INTT32A00B_IRQHandler +INTT32A00BCAP0_IRQHandler +INTT32A00BCAP1_IRQHandler +INTT32A00C_IRQHandler +INTT32A00CCAP0_IRQHandler +INTT32A00CCAP1_IRQHandler +INTT32A01A_IRQHandler +INTT32A01ACAP0_IRQHandler +INTT32A01ACAP1_IRQHandler +INTT32A01B_IRQHandler +INTT32A01BCAP0_IRQHandler +INTT32A01BCAP1_IRQHandler +INTT32A01C_IRQHandler +INTT32A01CCAP0_IRQHandler +INTT32A01CCAP1_IRQHandler +INTT32A02A_IRQHandler +INTT32A02ACAP0_IRQHandler +INTT32A02ACAP1_IRQHandler +INTT32A02B_IRQHandler +INTT32A02BCAP0_IRQHandler +INTT32A02BCAP1_IRQHandler +INTT32A02C_IRQHandler +INTT32A02CCAP0_IRQHandler +INTT32A02CCAP1_IRQHandler +INTT32A03A_IRQHandler +INTT32A03ACAP0_IRQHandler +INTT32A03ACAP1_IRQHandler +INTT32A03B_IRQHandler +INTT32A03BCAP0_IRQHandler +INTT32A03BCAP1_IRQHandler +INTT32A03C_IRQHandler +INTT32A03CCAP0_IRQHandler +INTT32A03CCAP1_IRQHandler +INTT32A04A_IRQHandler +INTT32A04ACAP0_IRQHandler +INTT32A04ACAP1_IRQHandler +INTT32A04B_IRQHandler +INTT32A04BCAP0_IRQHandler +INTT32A04BCAP1_IRQHandler +INTT32A04C_IRQHandler +INTT32A04CCAP0_IRQHandler +INTT32A04CCAP1_IRQHandler +INTT32A05A_IRQHandler +INTT32A05ACAP0_IRQHandler +INTT32A05ACAP1_IRQHandler +INTT32A05B_IRQHandler +INTT32A05BCAP0_IRQHandler +INTT32A05BCAP1_IRQHandler +INTT32A05C_IRQHandler +INTT32A05CCAP0_IRQHandler +INTT32A05CCAP1_IRQHandler +INTDMAATC_IRQHandler +INTDMAAERR_IRQHandler +INTRTC_IRQHandler +INTRMC0_IRQHandler +INTFLCRDY_IRQHandler +INTFLDRDY_IRQHandler + + B . + + ENDP + + END diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/device/TOOLCHAIN_ARM_STD/tmpm3h6fwfg.sct b/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/device/TOOLCHAIN_ARM_STD/tmpm3h6fwfg.sct new file mode 100644 index 00000000000..6727537c50f --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/device/TOOLCHAIN_ARM_STD/tmpm3h6fwfg.sct @@ -0,0 +1,29 @@ +;; TMPM3H6FWFG scatter file + +;; Vector table starts at 0 +;; Initial SP == |Image$$ARM_LIB_STACK$$ZI$$Limit| (for two region model) +;; or |Image$$ARM_LIB_STACKHEAP$$ZI$$Limit| (for one region model) +;; Initial PC == &__main (with LSB set to indicate Thumb) +;; These two values are provided by the library +;; Other vectors must be provided by the user +;; Code starts after the last possible vector +;; Data starts at 0x20000000 +;; Heap is positioned by ARM_LIB_HEAB (this is the heap managed by the ARM libraries) +;; Stack is positioned by ARM_LIB_STACK (library will use this to set SP - see above) + +;; Compatible with ISSM model + +LR_IROM1 0x00000000 0x20000 +{ + ER_IROM1 0x00000000 0x20000 + { + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + ; 8_byte_aligned(117 + 16 vect * 4 bytes) = 8_byte_aligned(0x214) = 0x218 + RW_IRAM1 (0x20000000 + 0x218) (0x4000 - 0x218) + { + .ANY (+RW, +ZI) + } +} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/device/TOOLCHAIN_GCC_ARM/startup_TMPM3H6.S b/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/device/TOOLCHAIN_GCC_ARM/startup_TMPM3H6.S new file mode 100644 index 00000000000..cb469a620c2 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/device/TOOLCHAIN_GCC_ARM/startup_TMPM3H6.S @@ -0,0 +1,483 @@ +/** + ******************************************************************************* + * @file startup_TMPM3H6.s + * @brief CMSIS Cortex-M3 Core Device Startup File for the + * TOSHIBA 'TMPM3H6' Device Series + * @version V5.00 + * @date 2016/03/02 + *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ + * + * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved + ******************************************************************************* + */ + +.syntax unified +.arch armv7-m + +.section .stack +.align 3 + +/* +// Stack Configuration +// Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +// +*/ + +#ifdef __STACK_SIZE +.equ Stack_Size, __STACK_SIZE +#else +.equ Stack_Size, 0x400 +#endif +.globl __StackTop +.globl __StackLimit +__StackLimit: +.space Stack_Size +.size __StackLimit, . - __StackLimit +__StackTop: +.size __StackTop, . - __StackTop + +/* +// Heap Configuration +// Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +// +*/ + +.section .heap +.align 3 +#ifdef __HEAP_SIZE +.equ Heap_Size, __HEAP_SIZE +#else +.equ Heap_Size, 0 +#endif +.globl __HeapBase +.globl __HeapLimit +__HeapBase: +.if Heap_Size +.space Heap_Size +.endif +.size __HeapBase, . - __HeapBase +__HeapLimit: +.size __HeapLimit, . - __HeapLimit + + .section .vectors + .align 2 + .globl __Vectors +__Vectors: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long MemManage_Handler /* MPU Fault Handler */ + .long BusFault_Handler /* Bus Fault Handler */ + .long UsageFault_Handler /* Usage Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long DebugMon_Handler /* Debug Monitor Handler */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External interrupts */ + .long INT00_IRQHandler // 0: Interrupt Pin0 + .long INT01_IRQHandler // 1: Interrupt Pin1 + .long INT02_IRQHandler // 2: Interrupt Pin2 + .long INT03_IRQHandler // 3: Interrupt Pin3 + .long INT04_IRQHandler // 4: Interrupt Pin4 + .long INT05_IRQHandler // 5: Interrupt Pin5 + .long INT06_IRQHandler // 6: Interrupt Pin6 + .long INT07_IRQHandler // 7: Interrupt Pin7 + .long INT08_IRQHandler // 8: Interrupt Pin8 + .long INT09_IRQHandler // 9: Interrupt Pin9 + .long INT10_IRQHandler // 10: Interrupt Pin10 + .long INT11_IRQHandler // 11: Interrupt Pin11 + .long INT12_IRQHandler // 12: Interrupt Pin12 + .long INT13_IRQHandler // 13: Interrupt Pin13 + .long INT14_IRQHandler // 14: Interrupt Pin14 + .long INT15_IRQHandler // 15: Interrupt Pin15 + .long INTEMG0_IRQHandler // 16: PMD0 EMG interrupt + .long INTOVV0_IRQHandler // 17: PMD0 OVV interrupt + .long INTPMD0_IRQHandler // 18: PMD0 interrupt + .long INTENC00_IRQHandler // 19: Encoder 0 interrupt 0 + .long INTENC01_IRQHandler // 20: Encoder 0 interrupt 1 + .long INTADAPDA_IRQHandler // 21: ADC conversion triggered by PMD is finished A + .long INTADAPDB_IRQHandler // 22: ADC conversion triggered by PMD is finished B + .long INTADACP0_IRQHandler // 23: ADC conversion monitoring function interrupt A + .long INTADACP1_IRQHandler // 24: ADC conversion monitoring function interrupt B + .long INTADATRG_IRQHandler // 25: ADC conversion triggered by General purpose is finished + .long INTADASGL_IRQHandler // 26: ADC conversion triggered by Single program is finished + .long INTADACNT_IRQHandler // 27: ADC conversion triggered by Continuity program is finished + .long INTT0RX_IRQHandler // 28: TSPI/SIO reception (channel 0) + .long INTT0TX_IRQHandler // 29: TSPI/SIO transmit (channel 0) + .long INTT0ERR_IRQHandler // 30: TSPI/SIO error (channel 0) + .long INTT1RX_IRQHandler // 31: TSPI/SIO reception (channel 1) + .long INTT1TX_IRQHandler // 32: TSPI/SIO transmit (channel 1) + .long INTT1ERR_IRQHandler // 33: TSPI/SIO error (channel 1) + .long INTI2CWUP_IRQHandler // 34: Serial bus interface (WakeUp) interrupt (channel 0) + .long INTI2C0_IRQHandler // 35: I2C0 transmission and reception interrupt + .long INTI2C0AL_IRQHandler // 36: I2C0 arbitration lost interrupt + .long INTI2C0BF_IRQHandler // 37: I2C0 bus free interrupt + .long INTI2C0NA_IRQHandler // 38: I2C0 no ack interrupt + .long INTI2C1_IRQHandler // 39: I2C1 transmission and reception interrupt + .long INTI2C1AL_IRQHandler // 40: I2C1 arbitration lost interrupt + .long INTI2C1BF_IRQHandler // 41: I2C1 bus free interrupt + .long INTI2C1NA_IRQHandler // 42: I2C1 no ack interrupt + .long INTI2C2_IRQHandler // 43: I2C2 transmission and reception interrupt + .long INTI2C2AL_IRQHandler // 44: I2C2 arbitration lost interrupt + .long INTI2C2BF_IRQHandler // 45: I2C2 bus free interrupt + .long INTI2C2NA_IRQHandler // 46: I2C2 no ack interrupt + .long INTUART0RX_IRQHandler // 47: UART reception (channel 0) + .long INTUART0TX_IRQHandler // 48: UART transmit (channel 0) + .long INTUART0ERR_IRQHandler // 49: UART error (channel 0) + .long INTUART1RX_IRQHandler // 50: UART reception (channel 1) + .long INTUART1TX_IRQHandler // 51: UART transmit (channel 1) + .long INTUART1ERR_IRQHandler // 52: UART error (channel 1) + .long INTUART2RX_IRQHandler // 53: UART reception (channel 2) + .long INTUART2TX_IRQHandler // 54: UART transmit (channel 2) + .long INTUART2ERR_IRQHandler // 55: UART error (channel 2) + .long INTT32A00A_IRQHandler // 56: 32bit T32A0A compare match detection 0 / Over flow / under flow + .long INTT32A00ACAP0_IRQHandler // 57: 32bit T32A0A input capture 0 + .long INTT32A00ACAP1_IRQHandler // 58: 32bit T32A0A input capture 1 + .long INTT32A00B_IRQHandler // 59: 32bit T32A0B compare match detection 0 / Over flow / under flow + .long INTT32A00BCAP0_IRQHandler // 60: 32bit T32A0B input capture 0 + .long INTT32A00BCAP1_IRQHandler // 61: 32bit T32A0B input capture 1 + .long INTT32A00C_IRQHandler // 62: 32bit T32A0C compare match detection 0 / Over flow / under flow + .long INTT32A00CCAP0_IRQHandler // 63: 32bit T32A0C input capture 0 + .long INTT32A00CCAP1_IRQHandler // 64: 32bit T32A0C input capture 1 + .long INTT32A01A_IRQHandler // 65: 32bit T32A1A compare match detection 0 / Over flow / under flow + .long INTT32A01ACAP0_IRQHandler // 66: 32bit T32A1A input capture 0 + .long INTT32A01ACAP1_IRQHandler // 67: 32bit T32A1A input capture 1 + .long INTT32A01B_IRQHandler // 68: 32bit T32A1B compare match detection 0 / Over flow / under flow + .long INTT32A01BCAP0_IRQHandler // 69: 32bit T32A1B input capture 0 + .long INTT32A01BCAP1_IRQHandler // 70: 32bit T32A1B input capture 1 + .long INTT32A01C_IRQHandler // 71: 32bit T32A1C compare match detection 0 / Over flow / under flow + .long INTT32A01CCAP0_IRQHandler // 72: 32bit T32A1C input capture 0 + .long INTT32A01CCAP1_IRQHandler // 73: 32bit T32A1C input capture 1 + .long INTT32A02A_IRQHandler // 74: 32bit T32A2A compare match detection 0 / Over flow / under flow + .long INTT32A02ACAP0_IRQHandler // 75: 32bit T32A2A input capture 0 + .long INTT32A02ACAP1_IRQHandler // 76: 32bit T32A2A input capture 1 + .long INTT32A02B_IRQHandler // 77: 32bit T32A2B compare match detection 0 / Over flow / under flow + .long INTT32A02BCAP0_IRQHandler // 78: 32bit T32A2B input capture 0 + .long INTT32A02BCAP1_IRQHandler // 79: 32bit T32A2B input capture 1 + .long INTT32A02C_IRQHandler // 80: 32bit T32A2C compare match detection 0 / Over flow / under flow + .long INTT32A02CCAP0_IRQHandler // 81: 32bit T32A2C input capture 0 + .long INTT32A02CCAP1_IRQHandler // 82: 32bit T32A2C input capture 1 + .long INTT32A03A_IRQHandler // 83: 32bit T32A3A compare match detection 0 / Over flow / under flow + .long INTT32A03ACAP0_IRQHandler // 84: 32bit T32A3A input capture 0 + .long INTT32A03ACAP1_IRQHandler // 85: 32bit T32A3A input capture 1 + .long INTT32A03B_IRQHandler // 86: 32bit T32A3B compare match detection 0 / Over flow / under flow + .long INTT32A03BCAP0_IRQHandler // 87: 32bit T32A3B input capture 0 + .long INTT32A03BCAP1_IRQHandler // 88: 32bit T32A3B input capture 1 + .long INTT32A03C_IRQHandler // 89: 32bit T32A3C compare match detection 0 / Over flow / under flow + .long INTT32A03CCAP0_IRQHandler // 90: 32bit T32A3C input capture 0 + .long INTT32A03CCAP1_IRQHandler // 91: 32bit T32A3C input capture 1 + .long INTT32A04A_IRQHandler // 92: 32bit T32A4A compare match detection 0 / Over flow / under flow + .long INTT32A04ACAP0_IRQHandler // 93: 32bit T32A4A input capture 0 + .long INTT32A04ACAP1_IRQHandler // 94: 32bit T32A4A input capture 1 + .long INTT32A04B_IRQHandler // 95: 32bit T32A4B compare match detection 0 / Over flow / under flow + .long INTT32A04BCAP0_IRQHandler // 96: 32bit T32A4B input capture 0 + .long INTT32A04BCAP1_IRQHandler // 97: 32bit T32A4B input capture 1 + .long INTT32A04C_IRQHandler // 98: 32bit T32A4C compare match detection 0 / Over flow / under flow + .long INTT32A04CCAP0_IRQHandler // 99: 32bit T32A4C input capture 0 + .long INTT32A04CCAP1_IRQHandler // 100: 32bit T32A4C input capture 1 + .long INTT32A05A_IRQHandler // 101: 32bit T32A5A compare match detection 0 / Over flow / under flow + .long INTT32A05ACAP0_IRQHandler // 102: 32bit T32A5A input capture 0 + .long INTT32A05ACAP1_IRQHandler // 103: 32bit T32A5A input capture 1 + .long INTT32A05B_IRQHandler // 104: 32bit T32A5B compare match detection 0 / Over flow / under flow + .long INTT32A05BCAP0_IRQHandler // 105: 32bit T32A5B input capture 0 + .long INTT32A05BCAP1_IRQHandler // 106: 32bit T32A5B input capture 1 + .long INTT32A05C_IRQHandler // 107: 32bit T32A5C compare match detection 0 / Over flow / under flow + .long INTT32A05CCAP0_IRQHandler // 108: 32bit T32A5C input capture 0 + .long INTT32A05CCAP1_IRQHandler // 109: 32bit T32A5C input capture 1 + .long INTDMAATC_IRQHandler // 110: DMA end of transfer + .long INTDMAAERR_IRQHandler // 111: DMA transfer error + .long INTRTC_IRQHandler // 112: Real time clock(XHz) interrupt + .long 0 // 113: Reserved + .long INTRMC0_IRQHandler // 114: Remote control reception interrupt + .long INTFLCRDY_IRQHandler // 115: Code FLASH Ready interrupt + .long INTFLDRDY_IRQHandler // 116: Data FLASH Ready interrupt + + .size __Vectors, . - __Vectors + + .text + .thumb + .thumb_func + .align 2 + .globl Reset_Handler + .type Reset_Handler, %function +Reset_Handler: +/* Firstly it copies data from read only memory to RAM. There are two schemes + * to copy. One can copy more than one sections. Another can only copy + * one section. The former scheme needs more instructions and read-only + * data to implement than the latter. + * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */ + +#ifdef __STARTUP_COPY_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of triplets, each of which specify: + * offset 0: LMA of start of a section to copy from + * offset 4: VMA of start of a section to copy to + * offset 8: size of the section to copy. Must be multiply of 4 + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r4, =__copy_table_start__ + ldr r5, =__copy_table_end__ + +.L_loop0: + cmp r4, r5 + bge .L_loop0_done + ldr r1, [r4] + ldr r2, [r4, #4] + ldr r3, [r4, #8] + +.L_loop0_0: + subs r3, #4 + ittt ge + ldrge r0, [r1, r3] + strge r0, [r2, r3] + bge .L_loop0_0 + + adds r4, #12 + b .L_loop0 + +.L_loop0_done: +#else +/* Single section scheme. + * + * The ranges of copy from/to are specified by following symbols + * __etext: LMA of start of the section to copy from. Usually end of text + * __data_start__: VMA of start of the section to copy to + * __data_end__: VMA of end of the section to copy to + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + +.L_loop1: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt .L_loop1 +#endif /*__STARTUP_COPY_MULTIPLE */ + +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * There are two schemes too. One can clear multiple BSS sections. Another + * can only clear one section. The former is more size expensive than the + * latter. + * + * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. + * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later. + */ +#ifdef __STARTUP_CLEAR_BSS_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of tuples specifying: + * offset 0: Start of a BSS section + * offset 4: Size of this BSS section. Must be multiply of 4 + */ + ldr r3, =__zero_table_start__ + ldr r4, =__zero_table_end__ + +.L_loop2: + cmp r3, r4 + bge .L_loop2_done + ldr r1, [r3] + ldr r2, [r3, #4] + movs r0, 0 + +.L_loop2_0: + subs r2, #4 + itt ge + strge r0, [r1, r2] + bge .L_loop2_0 + + adds r3, #8 + b .L_loop2 +.L_loop2_done: +#elif defined (__STARTUP_CLEAR_BSS) +/* Single BSS section scheme. + * + * The BSS section is specified by following symbols + * __bss_start__: start of the BSS section. + * __bss_end__: end of the BSS section. + * + * Both addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + movs r0, 0 +.L_loop3: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt .L_loop3 +#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */ + +#ifndef __NO_SYSTEM_INIT + bl SystemInit +#endif + +#ifndef __START +#define __START _start +#endif + bl __START + + .pool + .size Reset_Handler, . - Reset_Handler + + .align 1 + .thumb_func + .weak Default_Handler + .type Default_Handler, %function +Default_Handler: + b . + .size Default_Handler, . - Default_Handler + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, Default_Handler + .endm + + def_irq_handler NMI_Handler + def_irq_handler HardFault_Handler + def_irq_handler MemManage_Handler + def_irq_handler BusFault_Handler + def_irq_handler UsageFault_Handler + def_irq_handler SVC_Handler + def_irq_handler DebugMon_Handler + def_irq_handler PendSV_Handler + def_irq_handler SysTick_Handler + + def_irq_handler INT00_IRQHandler + def_irq_handler INT01_IRQHandler + def_irq_handler INT02_IRQHandler + def_irq_handler INT03_IRQHandler + def_irq_handler INT04_IRQHandler + def_irq_handler INT05_IRQHandler + def_irq_handler INT06_IRQHandler + def_irq_handler INT07_IRQHandler + def_irq_handler INT08_IRQHandler + def_irq_handler INT09_IRQHandler + def_irq_handler INT10_IRQHandler + def_irq_handler INT11_IRQHandler + def_irq_handler INT12_IRQHandler + def_irq_handler INT13_IRQHandler + def_irq_handler INT14_IRQHandler + def_irq_handler INT15_IRQHandler + def_irq_handler INTEMG0_IRQHandler + def_irq_handler INTOVV0_IRQHandler + def_irq_handler INTPMD0_IRQHandler + def_irq_handler INTENC00_IRQHandler + def_irq_handler INTENC01_IRQHandler + def_irq_handler INTADAPDA_IRQHandler + def_irq_handler INTADAPDB_IRQHandler + def_irq_handler INTADACP0_IRQHandler + def_irq_handler INTADACP1_IRQHandler + def_irq_handler INTADATRG_IRQHandler + def_irq_handler INTADASGL_IRQHandler + def_irq_handler INTADACNT_IRQHandler + def_irq_handler INTT0RX_IRQHandler + def_irq_handler INTT0TX_IRQHandler + def_irq_handler INTT0ERR_IRQHandler + def_irq_handler INTT1RX_IRQHandler + def_irq_handler INTT1TX_IRQHandler + def_irq_handler INTT1ERR_IRQHandler + def_irq_handler INTI2CWUP_IRQHandler + def_irq_handler INTI2C0_IRQHandler + def_irq_handler INTI2C0AL_IRQHandler + def_irq_handler INTI2C0BF_IRQHandler + def_irq_handler INTI2C0NA_IRQHandler + def_irq_handler INTI2C1_IRQHandler + def_irq_handler INTI2C1AL_IRQHandler + def_irq_handler INTI2C1BF_IRQHandler + def_irq_handler INTI2C1NA_IRQHandler + def_irq_handler INTI2C2_IRQHandler + def_irq_handler INTI2C2AL_IRQHandler + def_irq_handler INTI2C2BF_IRQHandler + def_irq_handler INTI2C2NA_IRQHandler + def_irq_handler INTUART0RX_IRQHandler + def_irq_handler INTUART0TX_IRQHandler + def_irq_handler INTUART0ERR_IRQHandler + def_irq_handler INTUART1RX_IRQHandler + def_irq_handler INTUART1TX_IRQHandler + def_irq_handler INTUART1ERR_IRQHandler + def_irq_handler INTUART2RX_IRQHandler + def_irq_handler INTUART2TX_IRQHandler + def_irq_handler INTUART2ERR_IRQHandler + def_irq_handler INTT32A00A_IRQHandler + def_irq_handler INTT32A00ACAP0_IRQHandler + def_irq_handler INTT32A00ACAP1_IRQHandler + def_irq_handler INTT32A00B_IRQHandler + def_irq_handler INTT32A00BCAP0_IRQHandler + def_irq_handler INTT32A00BCAP1_IRQHandler + def_irq_handler INTT32A00C_IRQHandler + def_irq_handler INTT32A00CCAP0_IRQHandler + def_irq_handler INTT32A00CCAP1_IRQHandler + def_irq_handler INTT32A01A_IRQHandler + def_irq_handler INTT32A01ACAP0_IRQHandler + def_irq_handler INTT32A01ACAP1_IRQHandler + def_irq_handler INTT32A01B_IRQHandler + def_irq_handler INTT32A01BCAP0_IRQHandler + def_irq_handler INTT32A01BCAP1_IRQHandler + def_irq_handler INTT32A01C_IRQHandler + def_irq_handler INTT32A01CCAP0_IRQHandler + def_irq_handler INTT32A01CCAP1_IRQHandler + def_irq_handler INTT32A02A_IRQHandler + def_irq_handler INTT32A02ACAP0_IRQHandler + def_irq_handler INTT32A02ACAP1_IRQHandler + def_irq_handler INTT32A02B_IRQHandler + def_irq_handler INTT32A02BCAP0_IRQHandler + def_irq_handler INTT32A02BCAP1_IRQHandler + def_irq_handler INTT32A02C_IRQHandler + def_irq_handler INTT32A02CCAP0_IRQHandler + def_irq_handler INTT32A02CCAP1_IRQHandler + def_irq_handler INTT32A03A_IRQHandler + def_irq_handler INTT32A03ACAP0_IRQHandler + def_irq_handler INTT32A03ACAP1_IRQHandler + def_irq_handler INTT32A03B_IRQHandler + def_irq_handler INTT32A03BCAP0_IRQHandler + def_irq_handler INTT32A03BCAP1_IRQHandler + def_irq_handler INTT32A03C_IRQHandler + def_irq_handler INTT32A03CCAP0_IRQHandler + def_irq_handler INTT32A03CCAP1_IRQHandler + def_irq_handler INTT32A04A_IRQHandler + def_irq_handler INTT32A04ACAP0_IRQHandler + def_irq_handler INTT32A04ACAP1_IRQHandler + def_irq_handler INTT32A04B_IRQHandler + def_irq_handler INTT32A04BCAP0_IRQHandler + def_irq_handler INTT32A04BCAP1_IRQHandler + def_irq_handler INTT32A04C_IRQHandler + def_irq_handler INTT32A04CCAP0_IRQHandler + def_irq_handler INTT32A04CCAP1_IRQHandler + def_irq_handler INTT32A05A_IRQHandler + def_irq_handler INTT32A05ACAP0_IRQHandler + def_irq_handler INTT32A05ACAP1_IRQHandler + def_irq_handler INTT32A05B_IRQHandler + def_irq_handler INTT32A05BCAP0_IRQHandler + def_irq_handler INTT32A05BCAP1_IRQHandler + def_irq_handler INTT32A05C_IRQHandler + def_irq_handler INTT32A05CCAP0_IRQHandler + def_irq_handler INTT32A05CCAP1_IRQHandler + def_irq_handler INTDMAATC_IRQHandler + def_irq_handler INTDMAAERR_IRQHandler + def_irq_handler INTRTC_IRQHandler + def_irq_handler INTRMC0_IRQHandler + def_irq_handler INTFLCRDY_IRQHandler + def_irq_handler INTFLDRDY_IRQHandler + + .end diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/device/TOOLCHAIN_GCC_ARM/tmpm3h6fwfg.ld b/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/device/TOOLCHAIN_GCC_ARM/tmpm3h6fwfg.ld new file mode 100644 index 00000000000..c43ce8b3f66 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/device/TOOLCHAIN_GCC_ARM/tmpm3h6fwfg.ld @@ -0,0 +1,162 @@ +/* Linker script for Toshiba TMPM3H6 */ + +/* Linker script to configure memory regions. */ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 128K + /* 8_byte_aligned(117 + 16 vect * 4 bytes) = 8_byte_aligned(0x214) = 0x218 */ + RAM (rwx) : ORIGIN = (0x20000000 + 0x218), LENGTH = (16K - 0x218) +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.vectors)) + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + + __etext = .; + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + .heap (COPY): + { + __HeapBase = .; + __end__ = .; + end = __end__; + KEEP(*(.heap*)) + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + KEEP(*(.stack*)) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/device/TOOLCHAIN_IAR/startup_TMPM3H6.S b/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/device/TOOLCHAIN_IAR/startup_TMPM3H6.S new file mode 100644 index 00000000000..61120ca6afe --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/device/TOOLCHAIN_IAR/startup_TMPM3H6.S @@ -0,0 +1,808 @@ +;/** +; ******************************************************************************* +; * @file startup_TMPM3H6.s +; * @brief CMSIS Cortex-M3 Core Device Startup File for the +; * TOSHIBA 'TMPM3H6' Device Series +; * @version V1.0.0.0 +; * $Date:: #$ +; * +; * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LISENCE AGREEMENT. +; * +; * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved +; ******************************************************************************* +; */ +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table DCD sfe(CSTACK) + DCD Reset_Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD INT00_IRQHandler ; 0: Interrupt Pin0 + DCD INT01_IRQHandler ; 1: Interrupt Pin1 + DCD INT02_IRQHandler ; 2: Interrupt Pin2 + DCD INT03_IRQHandler ; 3: Interrupt Pin3 + DCD INT04_IRQHandler ; 4: Interrupt Pin4 + DCD INT05_IRQHandler ; 5: Interrupt Pin5 + DCD INT06_IRQHandler ; 6: Interrupt Pin6 + DCD INT07_IRQHandler ; 7: Interrupt Pin7 + DCD INT08_IRQHandler ; 8: Interrupt Pin8 + DCD INT09_IRQHandler ; 9: Interrupt Pin9 + DCD INT10_IRQHandler ; 10: Interrupt Pin10 + DCD INT11_IRQHandler ; 11: Interrupt Pin11 + DCD INT12_IRQHandler ; 12: Interrupt Pin12 + DCD INT13_IRQHandler ; 13: Interrupt Pin13 + DCD INT14_IRQHandler ; 14: Interrupt Pin14 + DCD INT15_IRQHandler ; 15: Interrupt Pin15 + DCD INTEMG0_IRQHandler ; 16: PMD0 EMG interrupt + DCD INTOVV0_IRQHandler ; 17: PMD0 OVV interrupt + DCD INTPMD0_IRQHandler ; 18: PMD0 interrupt + DCD INTENC00_IRQHandler ; 19: Encoder 0 interrupt 0 + DCD INTENC01_IRQHandler ; 20: Encoder 0 interrupt 1 + DCD INTADAPDA_IRQHandler ; 21: ADC conversion triggered by PMD is finished A + DCD INTADAPDB_IRQHandler ; 22: ADC conversion triggered by PMD is finished B + DCD INTADACP0_IRQHandler ; 23: ADC conversion monitoring function interrupt 0 + DCD INTADACP1_IRQHandler ; 24: ADC conversion monitoring function interrupt 1 + DCD INTADATRG_IRQHandler ; 25: ADC conversion triggered by General purpose is finished + DCD INTADASGL_IRQHandler ; 26: ADC conversion triggered by Single program is finished + DCD INTADACNT_IRQHandler ; 27: ADC conversion triggered by Continuity program is finished + DCD INTT0RX_IRQHandler ; 28: TSPI/SIO reception (channel 0) + DCD INTT0TX_IRQHandler ; 29: TSPI/SIO transmit (channel 0) + DCD INTT0ERR_IRQHandler ; 30: TSPI/SIO error (channel 0) + DCD INTT1RX_IRQHandler ; 31: TSPI/SIO reception (channel 1) + DCD INTT1TX_IRQHandler ; 32: TSPI/SIO transmit (channel 1) + DCD INTT1ERR_IRQHandler ; 33: TSPI/SIO error (channel 1) + DCD INTI2CWUP_IRQHandler ; 34: Serial bus interface (WakeUp) interrupt (channel 0) + DCD INTI2C0_IRQHandler ; 35: I2C0 transmission and reception interrupt + DCD INTI2C0AL_IRQHandler ; 36: I2C0 arbitration lost interrupt + DCD INTI2C0BF_IRQHandler ; 37: I2C0 bus free interrupt + DCD INTI2C0NA_IRQHandler ; 38: I2C0 no ack interrupt + DCD INTI2C1_IRQHandler ; 39: I2C1 transmission and reception interrupt + DCD INTI2C1AL_IRQHandler ; 40: I2C1 arbitration lost interrupt + DCD INTI2C1BF_IRQHandler ; 41: I2C1 bus free interrupt + DCD INTI2C1NA_IRQHandler ; 42: I2C1 no ack interrupt + DCD INTI2C2_IRQHandler ; 43: I2C2 transmission and reception interrupt + DCD INTI2C2AL_IRQHandler ; 44: I2C2 arbitration lost interrupt + DCD INTI2C2BF_IRQHandler ; 45: I2C2 bus free interrupt + DCD INTI2C2NA_IRQHandler ; 46: I2C2 no ack interrupt + DCD INTUART0RX_IRQHandler ; 47: UART reception (channel 0) + DCD INTUART0TX_IRQHandler ; 48: UART transmit (channel 0) + DCD INTUART0ERR_IRQHandler ; 49: UART error (channel 0) + DCD INTUART1RX_IRQHandler ; 50: UART reception (channel 1) + DCD INTUART1TX_IRQHandler ; 51: UART transmit (channel 1) + DCD INTUART1ERR_IRQHandler ; 52: UART error (channel 1) + DCD INTUART2RX_IRQHandler ; 53: UART reception (channel 2) + DCD INTUART2TX_IRQHandler ; 54: UART transmit (channel 2) + DCD INTUART2ERR_IRQHandler ; 55: UART error (channel 2) + DCD INTT32A00A_IRQHandler ; 56: 32bit T32A00A compare match detection 0 / Over flow / under flow + DCD INTT32A00ACAP0_IRQHandler ; 57: 32bit T32A00A input capture 0 + DCD INTT32A00ACAP1_IRQHandler ; 58: 32bit T32A00A input capture 1 + DCD INTT32A00B_IRQHandler ; 59: 32bit T32A00B compare match detection 0 / Over flow / under flow + DCD INTT32A00BCAP0_IRQHandler ; 60: 32bit T32A00B input capture 0 + DCD INTT32A00BCAP1_IRQHandler ; 61: 32bit T32A00B input capture 1 + DCD INTT32A00C_IRQHandler ; 62: 32bit T32A00C compare match detection 0 / Over flow / under flow + DCD INTT32A00CCAP0_IRQHandler ; 63: 32bit T32A00C input capture 0 + DCD INTT32A00CCAP1_IRQHandler ; 64: 32bit T32A00C input capture 1 + DCD INTT32A01A_IRQHandler ; 65: 32bit T32A01A compare match detection 0 / Over flow / under flow + DCD INTT32A01ACAP0_IRQHandler ; 66: 32bit T32A01A input capture 0 + DCD INTT32A01ACAP1_IRQHandler ; 67: 32bit T32A01A input capture 1 + DCD INTT32A01B_IRQHandler ; 68: 32bit T32A01B compare match detection 0 / Over flow / under flow + DCD INTT32A01BCAP0_IRQHandler ; 69: 32bit T32A01B input capture 0 + DCD INTT32A01BCAP1_IRQHandler ; 70: 32bit T32A01B input capture 1 + DCD INTT32A01C_IRQHandler ; 71: 32bit T32A01C compare match detection 0 / Over flow / under flow + DCD INTT32A01CCAP0_IRQHandler ; 72: 32bit T32A01C input capture 0 + DCD INTT32A01CCAP1_IRQHandler ; 73: 32bit T32A01C input capture 1 + DCD INTT32A02A_IRQHandler ; 74: 32bit T32A02A compare match detection 0 / Over flow / under flow + DCD INTT32A02ACAP0_IRQHandler ; 75: 32bit T32A02A input capture 0 + DCD INTT32A02ACAP1_IRQHandler ; 76: 32bit T32A02A input capture 1 + DCD INTT32A02B_IRQHandler ; 77: 32bit T32A02B compare match detection 0 / Over flow / under flow + DCD INTT32A02BCAP0_IRQHandler ; 78: 32bit T32A02B input capture 0 + DCD INTT32A02BCAP1_IRQHandler ; 79: 32bit T32A02B input capture 1 + DCD INTT32A02C_IRQHandler ; 80: 32bit T32A02C compare match detection 0 / Over flow / under flow + DCD INTT32A02CCAP0_IRQHandler ; 81: 32bit T32A02C input capture 0 + DCD INTT32A02CCAP1_IRQHandler ; 82: 32bit T32A02C input capture 1 + DCD INTT32A03A_IRQHandler ; 83: 32bit T32A03A compare match detection 0 / Over flow / under flow + DCD INTT32A03ACAP0_IRQHandler ; 84: 32bit T32A03A input capture 0 + DCD INTT32A03ACAP1_IRQHandler ; 85: 32bit T32A03A input capture 1 + DCD INTT32A03B_IRQHandler ; 86: 32bit T32A03B compare match detection 0 / Over flow / under flow + DCD INTT32A03BCAP0_IRQHandler ; 87: 32bit T32A03B input capture 0 + DCD INTT32A03BCAP1_IRQHandler ; 88: 32bit T32A03B input capture 1 + DCD INTT32A03C_IRQHandler ; 89: 32bit T32A03C compare match detection 0 / Over flow / under flow + DCD INTT32A03CCAP0_IRQHandler ; 90: 32bit T32A03C input capture 0 + DCD INTT32A03CCAP1_IRQHandler ; 91: 32bit T32A03C input capture 1 + DCD INTT32A04A_IRQHandler ; 92: 32bit T32A04A compare match detection 0 / Over flow / under flow + DCD INTT32A04ACAP0_IRQHandler ; 93: 32bit T32A04A input capture 0 + DCD INTT32A04ACAP1_IRQHandler ; 94: 32bit T32A04A input capture 1 + DCD INTT32A04B_IRQHandler ; 95: 32bit T32A04B compare match detection 0 / Over flow / under flow + DCD INTT32A04BCAP0_IRQHandler ; 96: 32bit T32A04B input capture 0 + DCD INTT32A04BCAP1_IRQHandler ; 97: 32bit T32A04B input capture 1 + DCD INTT32A04C_IRQHandler ; 98: 32bit T32A04C compare match detection 0 / Over flow / under flow + DCD INTT32A04CCAP0_IRQHandler ; 99: 32bit T32A04C input capture 0 + DCD INTT32A04CCAP1_IRQHandler ; 100: 32bit T32A04C input capture 1 + DCD INTT32A05A_IRQHandler ; 101: 32bit T32A05A compare match detection 0 / Over flow / under flow + DCD INTT32A05ACAP0_IRQHandler ; 102: 32bit T32A05A input capture 0 + DCD INTT32A05ACAP1_IRQHandler ; 103: 32bit T32A05A input capture 1 + DCD INTT32A05B_IRQHandler ; 104: 32bit T32A05B compare match detection 0 / Over flow / under flow + DCD INTT32A05BCAP0_IRQHandler ; 105: 32bit T32A05B input capture 0 + DCD INTT32A05BCAP1_IRQHandler ; 106: 32bit T32A05B input capture 1 + DCD INTT32A05C_IRQHandler ; 107: 32bit T32A05C compare match detection 0 / Over flow / under flow + DCD INTT32A05CCAP0_IRQHandler ; 108: 32bit T32A05C input capture 0 + DCD INTT32A05CCAP1_IRQHandler ; 109: 32bit T32A05C input capture 1 + DCD INTDMAATC_IRQHandler ; 110: DMA end of transfer + DCD INTDMAAERR_IRQHandler ; 111: DMA transfer error + DCD INTRTC_IRQHandler ; 112: Real time clock(XHz) interrupt + DCD 0 ; 113: Reserved + DCD INTRMC0_IRQHandler ; 114: Remote control reception interrupt + DCD INTFLCRDY_IRQHandler ; 115: Code FLASH Ready interrupt + DCD INTFLDRDY_IRQHandler ; 116: Data FLASH Ready interrupt + THUMB +; Dummy Exception Handlers (infinite loops which can be modified) + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK INT00_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INT00_IRQHandler + B INT00_IRQHandler + + PUBWEAK INT01_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INT01_IRQHandler + B INT01_IRQHandler + + PUBWEAK INT02_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INT02_IRQHandler + B INT02_IRQHandler + + PUBWEAK INT03_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INT03_IRQHandler + B INT03_IRQHandler + + PUBWEAK INT04_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INT04_IRQHandler + B INT04_IRQHandler + + PUBWEAK INT05_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INT05_IRQHandler + B INT05_IRQHandler + + PUBWEAK INT06_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INT06_IRQHandler + B INT06_IRQHandler + + PUBWEAK INT07_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INT07_IRQHandler + B INT07_IRQHandler + + PUBWEAK INT08_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INT08_IRQHandler + B INT08_IRQHandler + + PUBWEAK INT09_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INT09_IRQHandler + B INT09_IRQHandler + + PUBWEAK INT10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INT10_IRQHandler + B INT10_IRQHandler + + PUBWEAK INT11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INT11_IRQHandler + B INT11_IRQHandler + + PUBWEAK INT12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INT12_IRQHandler + B INT12_IRQHandler + + PUBWEAK INT13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INT13_IRQHandler + B INT13_IRQHandler + + PUBWEAK INT14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INT14_IRQHandler + B INT14_IRQHandler + + PUBWEAK INT15_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INT15_IRQHandler + B INT15_IRQHandler + + PUBWEAK INTEMG0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTEMG0_IRQHandler + B INTEMG0_IRQHandler + + PUBWEAK INTOVV0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTOVV0_IRQHandler + B INTOVV0_IRQHandler + + PUBWEAK INTPMD0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTPMD0_IRQHandler + B INTPMD0_IRQHandler + + PUBWEAK INTENC00_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTENC00_IRQHandler + B INTENC00_IRQHandler + + PUBWEAK INTENC01_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTENC01_IRQHandler + B INTENC01_IRQHandler + + PUBWEAK INTADAPDA_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTADAPDA_IRQHandler + B INTADAPDA_IRQHandler + + PUBWEAK INTADAPDB_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTADAPDB_IRQHandler + B INTADAPDB_IRQHandler + + PUBWEAK INTADACP0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTADACP0_IRQHandler + B INTADACP0_IRQHandler + + PUBWEAK INTADACP1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTADACP1_IRQHandler + B INTADACP1_IRQHandler + + PUBWEAK INTADATRG_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTADATRG_IRQHandler + B INTADATRG_IRQHandler + + PUBWEAK INTADASGL_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTADASGL_IRQHandler + B INTADASGL_IRQHandler + + PUBWEAK INTADACNT_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTADACNT_IRQHandler + B INTADACNT_IRQHandler + + PUBWEAK INTT0RX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT0RX_IRQHandler + B INTT0RX_IRQHandler + + PUBWEAK INTT0TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT0TX_IRQHandler + B INTT0TX_IRQHandler + + PUBWEAK INTT0ERR_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT0ERR_IRQHandler + B INTT0ERR_IRQHandler + + PUBWEAK INTT1RX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT1RX_IRQHandler + B INTT1RX_IRQHandler + + PUBWEAK INTT1TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT1TX_IRQHandler + B INTT1TX_IRQHandler + + PUBWEAK INTT1ERR_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT1ERR_IRQHandler + B INTT1ERR_IRQHandler + + PUBWEAK INTI2CWUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTI2CWUP_IRQHandler + B INTI2CWUP_IRQHandler + + PUBWEAK INTI2C0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTI2C0_IRQHandler + B INTI2C0_IRQHandler + + PUBWEAK INTI2C0AL_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTI2C0AL_IRQHandler + B INTI2C0AL_IRQHandler + + PUBWEAK INTI2C0BF_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTI2C0BF_IRQHandler + B INTI2C0BF_IRQHandler + + PUBWEAK INTI2C0NA_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTI2C0NA_IRQHandler + B INTI2C0NA_IRQHandler + + PUBWEAK INTI2C1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTI2C1_IRQHandler + B INTI2C1_IRQHandler + + PUBWEAK INTI2C1AL_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTI2C1AL_IRQHandler + B INTI2C1AL_IRQHandler + + PUBWEAK INTI2C1BF_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTI2C1BF_IRQHandler + B INTI2C1BF_IRQHandler + + PUBWEAK INTI2C1NA_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTI2C1NA_IRQHandler + B INTI2C1NA_IRQHandler + + PUBWEAK INTI2C2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTI2C2_IRQHandler + B INTI2C2_IRQHandler + + PUBWEAK INTI2C2AL_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTI2C2AL_IRQHandler + B INTI2C2AL_IRQHandler + + PUBWEAK INTI2C2BF_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTI2C2BF_IRQHandler + B INTI2C2BF_IRQHandler + + PUBWEAK INTI2C2NA_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTI2C2NA_IRQHandler + B INTI2C2NA_IRQHandler + + PUBWEAK INTUART0RX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTUART0RX_IRQHandler + B INTUART0RX_IRQHandler + + PUBWEAK INTUART0TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTUART0TX_IRQHandler + B INTUART0TX_IRQHandler + + PUBWEAK INTUART0ERR_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTUART0ERR_IRQHandler + B INTUART0ERR_IRQHandler + + PUBWEAK INTUART1RX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTUART1RX_IRQHandler + B INTUART1RX_IRQHandler + + PUBWEAK INTUART1TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTUART1TX_IRQHandler + B INTUART1TX_IRQHandler + + PUBWEAK INTUART1ERR_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTUART1ERR_IRQHandler + B INTUART1ERR_IRQHandler + + PUBWEAK INTUART2RX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTUART2RX_IRQHandler + B INTUART2RX_IRQHandler + + PUBWEAK INTUART2TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTUART2TX_IRQHandler + B INTUART2TX_IRQHandler + + PUBWEAK INTUART2ERR_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTUART2ERR_IRQHandler + B INTUART2ERR_IRQHandler + + PUBWEAK INTT32A00A_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A00A_IRQHandler + B INTT32A00A_IRQHandler + + PUBWEAK INTT32A00ACAP0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A00ACAP0_IRQHandler + B INTT32A00ACAP0_IRQHandler + + PUBWEAK INTT32A00ACAP1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A00ACAP1_IRQHandler + B INTT32A00ACAP1_IRQHandler + + PUBWEAK INTT32A00B_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A00B_IRQHandler + B INTT32A00B_IRQHandler + + PUBWEAK INTT32A00BCAP0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A00BCAP0_IRQHandler + B INTT32A00BCAP0_IRQHandler + + PUBWEAK INTT32A00BCAP1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A00BCAP1_IRQHandler + B INTT32A00BCAP1_IRQHandler + + PUBWEAK INTT32A00C_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A00C_IRQHandler + B INTT32A00C_IRQHandler + + PUBWEAK INTT32A00CCAP0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A00CCAP0_IRQHandler + B INTT32A00CCAP0_IRQHandler + + PUBWEAK INTT32A00CCAP1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A00CCAP1_IRQHandler + B INTT32A00CCAP1_IRQHandler + + PUBWEAK INTT32A01A_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A01A_IRQHandler + B INTT32A01A_IRQHandler + + PUBWEAK INTT32A01ACAP0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A01ACAP0_IRQHandler + B INTT32A01ACAP0_IRQHandler + + PUBWEAK INTT32A01ACAP1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A01ACAP1_IRQHandler + B INTT32A01ACAP1_IRQHandler + + PUBWEAK INTT32A01B_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A01B_IRQHandler + B INTT32A01B_IRQHandler + + PUBWEAK INTT32A01BCAP0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A01BCAP0_IRQHandler + B INTT32A01BCAP0_IRQHandler + + PUBWEAK INTT32A01BCAP1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A01BCAP1_IRQHandler + B INTT32A01BCAP1_IRQHandler + + PUBWEAK INTT32A01C_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A01C_IRQHandler + B INTT32A01C_IRQHandler + + PUBWEAK INTT32A01CCAP0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A01CCAP0_IRQHandler + B INTT32A01CCAP0_IRQHandler + + PUBWEAK INTT32A01CCAP1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A01CCAP1_IRQHandler + B INTT32A01CCAP1_IRQHandler + + PUBWEAK INTT32A02A_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A02A_IRQHandler + B INTT32A02A_IRQHandler + + PUBWEAK INTT32A02ACAP0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A02ACAP0_IRQHandler + B INTT32A02ACAP0_IRQHandler + + PUBWEAK INTT32A02ACAP1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A02ACAP1_IRQHandler + B INTT32A02ACAP1_IRQHandler + + PUBWEAK INTT32A02B_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A02B_IRQHandler + B INTT32A02B_IRQHandler + + PUBWEAK INTT32A02BCAP0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A02BCAP0_IRQHandler + B INTT32A02BCAP0_IRQHandler + + PUBWEAK INTT32A02BCAP1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A02BCAP1_IRQHandler + B INTT32A02BCAP1_IRQHandler + + PUBWEAK INTT32A02C_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A02C_IRQHandler + B INTT32A02C_IRQHandler + + PUBWEAK INTT32A02CCAP0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A02CCAP0_IRQHandler + B INTT32A02CCAP0_IRQHandler + + PUBWEAK INTT32A02CCAP1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A02CCAP1_IRQHandler + B INTT32A02CCAP1_IRQHandler + + PUBWEAK INTT32A03A_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A03A_IRQHandler + B INTT32A03A_IRQHandler + + PUBWEAK INTT32A03ACAP0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A03ACAP0_IRQHandler + B INTT32A03ACAP0_IRQHandler + + PUBWEAK INTT32A03ACAP1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A03ACAP1_IRQHandler + B INTT32A03ACAP1_IRQHandler + + PUBWEAK INTT32A03B_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A03B_IRQHandler + B INTT32A03B_IRQHandler + + PUBWEAK INTT32A03BCAP0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A03BCAP0_IRQHandler + B INTT32A03BCAP0_IRQHandler + + PUBWEAK INTT32A03BCAP1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A03BCAP1_IRQHandler + B INTT32A03BCAP1_IRQHandler + + PUBWEAK INTT32A03C_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A03C_IRQHandler + B INTT32A03C_IRQHandler + + PUBWEAK INTT32A03CCAP0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A03CCAP0_IRQHandler + B INTT32A03CCAP0_IRQHandler + + PUBWEAK INTT32A03CCAP1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A03CCAP1_IRQHandler + B INTT32A03CCAP1_IRQHandler + + PUBWEAK INTT32A04A_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A04A_IRQHandler + B INTT32A04A_IRQHandler + + PUBWEAK INTT32A04ACAP0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A04ACAP0_IRQHandler + B INTT32A04ACAP0_IRQHandler + + PUBWEAK INTT32A04ACAP1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A04ACAP1_IRQHandler + B INTT32A04ACAP1_IRQHandler + + PUBWEAK INTT32A04B_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A04B_IRQHandler + B INTT32A04B_IRQHandler + + PUBWEAK INTT32A04BCAP0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A04BCAP0_IRQHandler + B INTT32A04BCAP0_IRQHandler + + PUBWEAK INTT32A04BCAP1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A04BCAP1_IRQHandler + B INTT32A04BCAP1_IRQHandler + + PUBWEAK INTT32A04C_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A04C_IRQHandler + B INTT32A04C_IRQHandler + + PUBWEAK INTT32A04CCAP0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A04CCAP0_IRQHandler + B INTT32A04CCAP0_IRQHandler + + PUBWEAK INTT32A04CCAP1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A04CCAP1_IRQHandler + B INTT32A04CCAP1_IRQHandler + + PUBWEAK INTT32A05A_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A05A_IRQHandler + B INTT32A05A_IRQHandler + + PUBWEAK INTT32A05ACAP0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A05ACAP0_IRQHandler + B INTT32A05ACAP0_IRQHandler + + PUBWEAK INTT32A05ACAP1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A05ACAP1_IRQHandler + B INTT32A05ACAP1_IRQHandler + + PUBWEAK INTT32A05B_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A05B_IRQHandler + B INTT32A05B_IRQHandler + + PUBWEAK INTT32A05BCAP0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A05BCAP0_IRQHandler + B INTT32A05BCAP0_IRQHandler + + PUBWEAK INTT32A05BCAP1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A05BCAP1_IRQHandler + B INTT32A05BCAP1_IRQHandler + + PUBWEAK INTT32A05C_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A05C_IRQHandler + B INTT32A05C_IRQHandler + + PUBWEAK INTT32A05CCAP0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A05CCAP0_IRQHandler + B INTT32A05CCAP0_IRQHandler + + PUBWEAK INTT32A05CCAP1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A05CCAP1_IRQHandler + B INTT32A05CCAP1_IRQHandler + + PUBWEAK INTDMAATC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTDMAATC_IRQHandler + B INTDMAATC_IRQHandler + + PUBWEAK INTDMAAERR_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTDMAAERR_IRQHandler + B INTDMAAERR_IRQHandler + + PUBWEAK INTRTC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTRTC_IRQHandler + B INTRTC_IRQHandler + + PUBWEAK INTRMC0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTRMC0_IRQHandler + B INTRMC0_IRQHandler + + PUBWEAK INTFLCRDY_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTFLCRDY_IRQHandler + B INTFLCRDY_IRQHandler + + PUBWEAK INTFLDRDY_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTFLDRDY_IRQHandler + B INTFLDRDY_IRQHandler + + END diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/device/TOOLCHAIN_IAR/tmpm3h6fwfg.icf b/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/device/TOOLCHAIN_IAR/tmpm3h6fwfg.icf new file mode 100644 index 00000000000..5445684f1f8 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/device/TOOLCHAIN_IAR/tmpm3h6fwfg.icf @@ -0,0 +1,40 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x0001FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000218; /* 8_byte_aligned(117 + 16 vect * 4 bytes) */ +define symbol __ICFEDIT_region_RAM_end__ = 0x20003FFF; +/* Heap 1/4 of ram and stack 1/8 */ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x1200; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define symbol __BRAM_start__ = 0x20004000; +define symbol __BRAM_end__ = 0x200047FF; +define symbol __DFLASH_start__ = 0x30000000; +define symbol __DFLASH_end__ = 0x30007FFF; +define region BRAM_region = mem:[from __BRAM_start__ to __BRAM_end__ ]; +define region DFLASH_region = mem:[from __DFLASH_start__ to __DFLASH_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; +place in BRAM_region { section .backup_ram }; +place in DFLASH_region { section .data_flash }; diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/device/cmsis.h b/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/device/cmsis.h new file mode 100644 index 00000000000..5a2ec44300c --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/device/cmsis.h @@ -0,0 +1,13 @@ +/* mbed Microcontroller Library - CMSIS for TMPM3H6 + * Copyright (C) 2011 ARM Limited. All rights reserved. + * + * A generic CMSIS include header, pulling in TMPM3Hx specifics + */ + +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "TMPM3H6.h" +#include "cmsis_nvic.h" + +#endif diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/device/cmsis_nvic.h b/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/device/cmsis_nvic.h new file mode 100644 index 00000000000..c112a33ca2a --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/device/cmsis_nvic.h @@ -0,0 +1,15 @@ +/* mbed Microcontroller Library - cmsis_nvic for TMPM3H6 + * Copyright (c) 2011 ARM Limited. All rights reserved. + * + * CMSIS-style functionality to support dynamic vectors + */ + +#ifndef MBED_CMSIS_NVIC_H +#define MBED_CMSIS_NVIC_H + +#define NVIC_FLASH_VECTOR_ADDRESS 0x00000000 +#define NVIC_USER_IRQ_NUMBER 117 +#define NVIC_NUM_VECTORS (16 + 117) // CORE + MCU Peripherals +#define NVIC_RAM_VECTOR_ADDRESS 0x20000000 // Location of vectors in RAM + +#endif diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/device/system_TMPM3H6.c b/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/device/system_TMPM3H6.c new file mode 100644 index 00000000000..8933ce37382 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/device/system_TMPM3H6.c @@ -0,0 +1,311 @@ +/** + ******************************************************************************* + * @file system_TMPM3Hx.c + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Source File for the + * TOSHIBA 'TMPM3Hx' Device Series + * @version V1.0.7.0 + * $Date:: 2017-11-06 #$ + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LISENCE AGREEMENT. + * + * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved + ******************************************************************************* + */ + +#include "TMPM3H6.h" + +/*-------- <<< Start of configuration section >>> ----------------------------*/ + +/* Semi-Independent Watchdog Timer (SIWDT) Configuration */ +#define SIWD_SETUP (1U) /* 1:Disable SIWD, 0:Enable SIWD */ +#define SIWDEN_Val (0x00000000UL) /* SIWD Disable */ +#define SIWDCR_Val (0x000000B1UL) /* SIWD Disable code */ + +/* Clock Generator (CG) Configuration */ +#define CLOCK_SETUP (1U) /* 1:External HOSC, 0: Internal HOSC */ +#define SYSCR_Val (0x00000000UL) + +#define STBYCR_Val (0x00000000UL) + +#define CG_6M_MUL_6_664_FPLL (0x001C7535UL<<8U) /* fPLL = 6MHz * 6.664 */ +#define CG_8M_MUL_5_FPLL (0x00247028UL<<8U) /* fPLL = 8MHz * 5 */ +#define CG_10M_MUL_4_FPLL (0x002E7020UL<<8U) /* fPLL = 10MHz * 4 */ +#define CG_12M_MUL_3_328_FPLL (0x0036FA1AUL<<8U) /* fPLL = 12MHz * 3.328 */ + +#define CG_PLL0SEL_PLL0ON_SET ((uint32_t)0x00000001) +#define CG_PLL0SEL_PLL0ON_CLEAR ((uint32_t)0xFFFFFFFE) +#define CG_PLL0SEL_PLL0SEL_SET ((uint32_t)0x00000002) +#define CG_PLL0SEL_PLL0SEL_CLEAR ((uint32_t)0xFFFFFFFD) + +#define CG_OSCCR_IHOSC1EN_CLEAR ((uint32_t)0xFFFFFFFE) +#define CG_OSCCR_EOSCEN_SET ((uint32_t)0x00000002) +#define CG_OSCCR_OSCSEL_SET ((uint32_t)0x00000100) + +#define CG_WUPHCR_WUON_START_SET ((uint32_t)0x00000001) + +#if (CLOCK_SETUP) + #define CG_WUPHCR_WUCLK_SET ((uint32_t)0x00000100) + #define PLL0SEL_Ready CG_12M_MUL_3_328_FPLL +#else + #define CG_WUPHCR_WUCLK_SET ((uint32_t)0x00000000) + #define PLL0SEL_Ready CG_10M_MUL_4_FPLL +#endif +#define PLL0SEL_Val (PLL0SEL_Ready|0x00000003UL) +#define PLL0SEL_MASK (0xFFFFFF00UL) + +/*-------- <<< End of configuration section >>> ------------------------------*/ + +/*-------- DEFINES -----------------------------------------------------------*/ +/* Define clocks */ +#define EOSC_6M (6000000UL) +#define EOSC_8M (8000000UL) +#define EOSC_10M (10000000UL) +#define EOSC_12M (12000000UL) +#define IOSC_10M (10000000UL) +#define EXTALH EOSC_12M /* External high-speed oscillator freq */ +#define IXTALH IOSC_10M /* Internal high-speed oscillator freq */ +#define EOSC_6M_PLLON (39980000UL) /* 6.00MHz * 53.3125 / 8 */ +#define EOSC_8M_PLLON (40000000UL) /* 8.00MHz * 40.0000 / 8 */ +#define EOSC_10M_PLLON (40000000UL) /* 10.00MHz * 32.0000 / 8 */ +#define EOSC_12M_PLLON (39940000UL) /* 12.00MHz * 26.6250 / 8 */ +#define IOSC_10M_PLLON (40000000UL) /* 10.00MHz * 32.0000 / 8 */ + +/* Configure Warm-up time */ +#define HZ_1M (1000000UL) +#define WU_TIME_EXT (5000UL) /* warm-up time for EXT is 5ms */ +#define INIT_TIME_PLL (100UL) /* Initial time for PLL is 100us */ +#define LOCKUP_TIME_PLL (400UL) /* Lockup time for PLL is 400us */ +#define WUPHCR_WUPT_EXT ((uint32_t)(((((uint64_t)WU_TIME_EXT * EXTALH / HZ_1M) - 16UL) /16UL) << 20U)) /* OSCCR = warm-up time(us) * EXTALH / 16 */ +#if (CLOCK_SETUP) + #define WUPHCR_INIT_PLL ((uint32_t)(((((uint64_t)INIT_TIME_PLL * EXTALH / HZ_1M) - 16UL) /16UL) << 20U)) + #define WUPHCR_LUPT_PLL ((uint32_t)(((((uint64_t)LOCKUP_TIME_PLL * EXTALH / HZ_1M) - 16UL) /16UL) << 20U)) +#else + #define WUPHCR_INIT_PLL ((uint32_t)(((((uint64_t)INIT_TIME_PLL * IXTALH / HZ_1M) - 16UL) /16UL) << 20U)) + #define WUPHCR_LUPT_PLL ((uint32_t)(((((uint64_t)LOCKUP_TIME_PLL * IXTALH / HZ_1M) - 16UL) /16UL) << 20U)) +#endif +/* Determine core clock frequency according to settings */ +/* System clock is high-speed clock*/ +#if (CLOCK_SETUP) + #define CORE_TALH (EXTALH) +#else + #define CORE_TALH (IXTALH) +#endif + +#if ((PLL0SEL_Val & (1U<<1U)) && (PLL0SEL_Val & (1U<<0U))) /* If PLL selected and enabled */ + #if (CORE_TALH == EOSC_6M) /* If input is 6MHz */ + #if ((PLL0SEL_Val & PLL0SEL_MASK) == (CG_6M_MUL_6_664_FPLL)) + #define __CORE_CLK EOSC_6M_PLLON /* output clock is 39.98MHz */ + #else /* fc -> reserved */ + #define __CORE_CLK (0U) + #endif /* End input is 6MHz */ + #elif (CORE_TALH == EOSC_8M) /* If input is 8MHz */ + #if ((PLL0SEL_Val & PLL0SEL_MASK) == (CG_8M_MUL_5_FPLL)) + #define __CORE_CLK EOSC_8M_PLLON /* output clock is 40MHz */ + #else /* fc -> reserved */ + #define __CORE_CLK (0U) + #endif /* End input is 8MHz */ + #elif (CORE_TALH == EOSC_10M) /* If input is 10MHz */ + #if ((PLL0SEL_Val & PLL0SEL_MASK) == CG_10M_MUL_4_FPLL) + #define __CORE_CLK EOSC_10M_PLLON /* output clock is 40MHz */ + #else /* fc -> reserved */ + #define __CORE_CLK (0U) + #endif /* End input is 10MHz */ + #elif (CORE_TALH == EOSC_12M) /* If input is 12MHz */ + #if ((PLL0SEL_Val & PLL0SEL_MASK) == CG_12M_MUL_3_328_FPLL) + #define __CORE_CLK EOSC_12M_PLLON /* output clock is 39.94MHz */ + #else /* fc -> reserved */ + #define __CORE_CLK (0U) + #endif /* End input is 12MHz */ + #elif (CORE_TALH == IOSC_10M) /* If input is 10MHz */ + #if ((PLL0SEL_Val & PLL0SEL_MASK) == CG_10M_MUL_4_FPLL) + #define __CORE_CLK IOSC_10M_PLLON /* output clock is 40MHz */ + #else /* fc -> reserved */ + #define __CORE_CLK (0U) + #endif /* End input is 10MHz */ + #else /* input clock not known */ + #define __CORE_CLK (0U) + #error "Core Oscillator Frequency invalid!" + #endif /* End switch input clock */ +#else + #define __CORE_CLK (CORE_TALH) +#endif + +#if ((SYSCR_Val & 7U) == 0U) /* Gear -> fc */ + #define __CORE_SYS (__CORE_CLK) +#elif ((SYSCR_Val & 7U) == 1U) /* Gear -> fc/2 */ + #define __CORE_SYS (__CORE_CLK / 2U) +#elif ((SYSCR_Val & 7U) == 2U) /* Gear -> fc/4 */ + #define __CORE_SYS (__CORE_CLK / 4U ) +#elif ((SYSCR_Val & 7U) == 3U) /* Gear -> fc/8 */ + #define __CORE_SYS (__CORE_CLK / 8U) +#elif ((SYSCR_Val & 7U) == 4U) /* Gear -> fc/16 */ + #define __CORE_SYS (__CORE_CLK / 16U) +#else /* Gear -> reserved */ + #define __CORE_SYS (0U) +#endif + + +/* Clock Variable definitions */ +uint32_t SystemCoreClock = __CORE_SYS; /*!< System Clock Frequency (Core Clock) */ + + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Update SystemCoreClock according register values. + */ +void SystemCoreClockUpdate(void) +{ /* Get Core Clock Frequency */ + uint32_t CoreClock = 0U; + uint32_t CoreClockInput = 0U; + uint32_t regval = 0U; + uint32_t oscsel = 0U; + uint32_t pll0sel = 0U; + uint32_t pll0on = 0U; + /* Determine clock frequency according to clock register values */ + /* System clock is high-speed clock */ + regval = TSB_CG->OSCCR; + oscsel = regval & CG_OSCCR_OSCSEL_SET; + if (oscsel) { /* If system clock is External high-speed oscillator freq */ + CoreClock = EXTALH; + } else { /* If system clock is Internal high-speed oscillator freq */ + CoreClock = IXTALH; + } + regval = TSB_CG->PLL0SEL; + pll0sel = regval & CG_PLL0SEL_PLL0SEL_SET; + pll0on = regval & CG_PLL0SEL_PLL0ON_SET; + if (pll0sel && pll0on) { /* If PLL enabled */ + if (CoreClock == EOSC_6M) { /* If input is 6MHz */ + if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_6M_MUL_6_664_FPLL) { + CoreClockInput = EOSC_6M_PLLON; /* output clock is 39.98MHz */ + } else { + CoreClockInput = 0U; /* fc -> reserved */ + } + } else if (CoreClock == EOSC_8M) { /* If input is 8MHz */ + if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_8M_MUL_5_FPLL) { + CoreClockInput = EOSC_8M_PLLON; /* output clock is 40MHz */ + } else { + CoreClockInput = 0U; /* fc -> reserved */ + } + } else if (CoreClock == EOSC_10M) { /* If input is 10MHz */ + if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_10M_MUL_4_FPLL) { + CoreClockInput = EOSC_10M_PLLON; /* output clock is 40MHz */ + } else { + CoreClockInput = 0U; /* fc -> reserved */ + } + } else if (CoreClock == EOSC_12M) { /* If input is 12MHz */ + if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_12M_MUL_3_328_FPLL) { + CoreClockInput = EOSC_12M_PLLON; /* output clock is 39.94MHz */ + } else { + CoreClockInput = 0U; /* fc -> reserved */ + } + } else if (CoreClock == IOSC_10M) { /* If input is 10MHz */ + if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_10M_MUL_4_FPLL) { + CoreClockInput = IOSC_10M_PLLON; /* output clock is 40MHz */ + } else { + CoreClockInput = 0U; /* fc -> reserved */ + } + } else { + CoreClockInput = 0U; + } + } else { /* If PLL not used */ + CoreClockInput = CoreClock; + } + + switch (TSB_CG->SYSCR & 7U) { + case 0U: /* Gear -> fc */ + SystemCoreClock = CoreClockInput; + break; + case 1U: /* Gear -> fc/2 */ + SystemCoreClock = CoreClockInput / 2U; + break; + case 2U: /* Gear -> fc/4 */ + SystemCoreClock = CoreClockInput / 4U; + break; + case 3U: /* Gear -> fc/8 */ + if (CoreClockInput >= EOSC_8M) { + SystemCoreClock = CoreClockInput / 8U; + } else { + SystemCoreClock = 0U; + } + break; + case 4U: /* Gear -> fc/16 */ + if (CoreClockInput > EOSC_12M) { + SystemCoreClock = CoreClockInput / 16U; + } else { + SystemCoreClock = 0U; + } + break; + case 5U: + case 6U: + case 7U: + SystemCoreClock = 0U; + break; + default: + SystemCoreClock = 0U; + break; + } +} + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System. + */ +void SystemInit(void) +{ +#if (SIWD_SETUP) /* Watchdog Setup */ + /* SIWD Disable */ + TSB_SIWD0->EN = SIWDEN_Val; + TSB_SIWD0->CR = SIWDCR_Val; +#else + /* SIWD Enable (Setting after a Reset) */ +#endif + +#if (CLOCK_SETUP) /* Clock(external) Setup */ + TSB_CG->SYSCR = SYSCR_Val; + + TSB_CG->WUPHCR = (WUPHCR_WUPT_EXT | CG_WUPHCR_WUCLK_SET); + TSB_CG->OSCCR |= CG_OSCCR_EOSCEN_SET; + TSB_CG->WUPHCR = (WUPHCR_WUPT_EXT | CG_WUPHCR_WUCLK_SET | CG_WUPHCR_WUON_START_SET); + while (TSB_CG_WUPHCR_WUEF) { + ; + } /* Warm-up */ + + TSB_CG->OSCCR |= CG_OSCCR_OSCSEL_SET; + while (!TSB_CG_OSCCR_OSCF) { + ; + } /* Confirm CGOSCCR="1" */ + TSB_CG->OSCCR &= CG_OSCCR_IHOSC1EN_CLEAR ; +#else + /* Internal HOSC Enable (Setting after a Reset) */ +#endif + + TSB_CG->WUPHCR = (WUPHCR_INIT_PLL | CG_WUPHCR_WUCLK_SET); + TSB_CG->PLL0SEL &= CG_PLL0SEL_PLL0SEL_CLEAR; /* PLL-->fOsc */ + TSB_CG->PLL0SEL &= CG_PLL0SEL_PLL0ON_CLEAR; + TSB_CG->PLL0SEL = PLL0SEL_Ready; + TSB_CG->WUPHCR = (WUPHCR_INIT_PLL | CG_WUPHCR_WUCLK_SET | CG_WUPHCR_WUON_START_SET); + while (TSB_CG_WUPHCR_WUEF) { + ; + } /* Warm-up */ + + TSB_CG->WUPHCR = (WUPHCR_LUPT_PLL | CG_WUPHCR_WUCLK_SET); + TSB_CG->PLL0SEL |= CG_PLL0SEL_PLL0ON_SET; /* PLL enabled */ + TSB_CG->STBYCR = STBYCR_Val; + TSB_CG->WUPHCR = (WUPHCR_LUPT_PLL | CG_WUPHCR_WUCLK_SET | CG_WUPHCR_WUON_START_SET); + while (TSB_CG_WUPHCR_WUEF) { + ; + } /* Lockup */ + TSB_CG->PLL0SEL |= CG_PLL0SEL_PLL0SEL_SET; + while (!TSB_CG_PLL0SEL_PLL0ST) { + ; + } /*Confirm CGPLL0SEL = "1" */ +} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/device/system_TMPM3H6.h b/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/device/system_TMPM3H6.h new file mode 100644 index 00000000000..07e40532ed8 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/device/system_TMPM3H6.h @@ -0,0 +1,52 @@ +/** + ***************************************************************************** + * @file system_TMPM3Hx.h + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File for the + * TOSHIBA 'TMPM3Hx' Device Series + * @version V1.0.1.0 + * $Date:: 2017-06-23 13:52:12 #$ + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LISENCE AGREEMENT. + * + * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved + ***************************************************************************** + */ + +#include + +#ifndef __SYSTEM_TMPM3H6_H +#define __SYSTEM_TMPM3H6_H + +#ifdef __cplusplus +extern "C" { +#endif + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +extern void SystemInit (void); + +/** + * Update SystemCoreClock variable + * + * @param none + * @return none + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate (void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/gpio_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/gpio_api.c new file mode 100644 index 00000000000..35bb2b0a14a --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/gpio_api.c @@ -0,0 +1,119 @@ +/* mbed Microcontroller Library + * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "gpio_api.h" +#include "pinmap.h" +#include "mbed_error.h" +#include "gpio_include.h" + +extern const PinMap PinMap_GPIO_IRQ[]; + +void gpio_init(gpio_t *obj, PinName pin) +{ + // Store above pin mask, pin name into GPIO object + obj->pin = pin; + obj->mask = gpio_set(pin); + obj->port = (PortName)(pin >> 3); + TSB_CG->FSYSENA |= (1 << (obj->port)); +} + +void gpio_mode(gpio_t *obj, PinMode mode) +{ + pin_mode(obj->pin, mode); +} + +uint32_t gpio_set(PinName pin) +{ + // Check that pin is valid + MBED_ASSERT(pin != (PinName)NC); + + // Set pin function as GPIO pin + pin_function(pin, GPIO_DATA); + + // Return pin mask + return (1 << (pin & 0x07)); +} + +// Set gpio object pin direction +void gpio_dir(gpio_t *obj, PinDirection direction) +{ + // Set direction + switch (direction) { + case PIN_INPUT: + pin_function(obj->pin, PIN_INPUT); + break; + + case PIN_OUTPUT: + pin_function(obj->pin, PIN_OUTPUT); + break; + + case PIN_INOUT: + pin_function(obj->pin, PIN_INOUT); + break; + + default: + error("Invalid direction\n"); + break; + } +} + +// Write gpio object pin data +void gpio_write(gpio_t *obj, int value) +{ + int port = 0; + uint8_t bit = 0; + uint32_t base = 0; + + // Calculate port and pin position + port = PIN_PORT(obj->pin); + bit = PIN_POS(obj->pin); + + base = BITBAND_PORT_BASE(port); + base = BITBAND_PORT_MODE_BASE(base, GPIO_Mode_DATA); + + if (value == GPIO_PIN_SET) { + BITBAND_PORT_SET(base, bit); + } else if (value == GPIO_PIN_RESET) { + BITBAND_PORT_CLR(base, bit); + } else { + error("Invalid value\n"); + } +} + +// Read gpio object pin data +int gpio_read(gpio_t *obj) +{ + int port = 0; + uint8_t bit = 0; + uint32_t base = 0; + uint32_t val = 0; + int BitValue = 0; + + // Calculate port and pin position + port = PIN_PORT(obj->pin); + bit = PIN_POS(obj->pin); + + base = BITBAND_PORT_BASE(port); + base = BITBAND_PORT_MODE_BASE(base, GPIO_Mode_DATA); + BITBAND_PORT_READ(val, base, bit); + + if (val == GPIO_PIN_RESET) { + BitValue = GPIO_PIN_RESET; + } else { + BitValue = GPIO_PIN_SET; + } + + return (BitValue); +} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/gpio_include.h b/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/gpio_include.h new file mode 100644 index 00000000000..ca6c8cd2b81 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/gpio_include.h @@ -0,0 +1,174 @@ +/* mbed Microcontroller Library + * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef __GPIO_INCLUDE_H +#define __GPIO_INCLUDE_H + +#include +#include +#include "TMPM3H6.h" +#include "objects.h" +#include "serial_api.h" +#include "txz_driver_def.h" + +enum BitMode { + GPIO_PIN_RESET = 0, + GPIO_PIN_SET, +}; + +enum PortFunction { + GPIO_Mode_DATA = 0x0, // 0x0: PxDATA + GPIO_Mode_CR = 0x04, // 0x4: PxCR + GPIO_Mode_FR1 = 0x08, // 0x8: PxFR1 + GPIO_Mode_FR2 = 0x0C, // 0xC: PxFR2 + GPIO_Mode_FR3 = 0x10, // 0x10: PxFR3 + GPIO_Mode_FR4 = 0x14, // 0x14: PxFR4 + GPIO_Mode_FR5 = 0x18, // 0x18: PxFR5 + GPIO_Mode_FR6 = 0x1C, // 0x1C: PxFR6 + GPIO_Mode_OD = 0x28, // 0x28: PxOD + GPIO_Mode_PUP = 0x2C, // 0x2C: PxPUP + GPIO_Mode_PDN = 0x30, // 0x30: PxPDN + GPIO_Mode_IE = 0x38 // 0x38: PxIE +}; + +// GPIO +#define PORT_BASE (0x400C0000UL) // Port Register Base Adress +#define BITBAND_PORT_OFFSET (0x0000100UL) // Port Register Offset Value +#define BITBAND_PORT_BASE(gr) (PORT_BASE + (uint32_t)((BITBAND_PORT_OFFSET) * (gr)) ) // Operational target Port Adress +#define BITBAND_PORT_MODE_BASE(base, pinmode) ((uint32_t)(base) + (uint32_t)(pinmode) ) // Operational target Control Register Adress +#define BITBAND_PORT_SET(base, bitnum) (*((__IO uint32_t *)base) |= (uint32_t)(0x0000001UL<< bitnum)) // Target Pin Bit set +#define BITBAND_PORT_CLR(base, bitnum) (*((__IO uint32_t *)base) &= ~((uint32_t)(0x0000001UL<< bitnum))) // Target Pin Bit clear +#define BITBAND_PORT_READ(val, base, bitnum) val = ((*((__IO uint32_t *)base) & (uint32_t)(0x0000001UL<< bitnum)) >> bitnum) // Target Pin Bit read +#define GPIO_DATA PIN_DATA(0, 2) +#define CHANNEL_NUM 16 +#define PORT_PIN_NUM 8 +#define PIN_PORT(X) (((uint32_t)(X) >> 3) & 0xF) +#define PIN_POS(X) ((uint32_t)(X) & 0x7) +// Pin data, bit 31..16: Pin Function, bit 15..0: Pin Direction +#define PIN_DATA(FUNC, DIR) (int)(((FUNC) << 16)| ((DIR) << 0)) +#define PIN_FUNC(X) (((X) & 0xFFFF0000) >> 16) +#define PIN_DIR(X) ((X) & 0xFFFF) +// SPI +#define TIMEOUT 1000 +#define INITIAL_SPI_FREQ 1000000 +// I2C +#define I2CxCR2_I2CM_ENABLE ((uint32_t)0x00000080) +#define I2CxCR2_SWRES_10 ((uint32_t)0x00000002) +#define I2CxCR2_SWRES_01 ((uint32_t)0x00000001) +#define I2CxCR2_START_CONDITION ((uint32_t)0x000000F8) +#define I2CxCR2_STOP_CONDITION ((uint32_t)0x000000D8) +#define I2CxCR2_INIT ((uint32_t)0x00000008) +#define I2CxCR2_PIN_CLEAR ((uint32_t)0x00000010) +#define I2CxCR2_TRX ((uint32_t)0x00000040) +#define I2CxST_I2C ((uint32_t)0x00000001) +#define I2CxST_CLEAR ((uint32_t)0x0000000F) +#define I2CxCR1_ACK ((uint32_t)0x00000010) +#define I2CxSR_BB ((uint32_t)0x00000020) +#define I2CxSR_LRB ((uint32_t)0x00000001) +#define I2CxOP_RSTA ((uint32_t)0x00000008) +#define I2CxOP_SREN ((uint32_t)0x00000002) +#define I2CxOP_MFACK ((uint32_t)0x00000001) +#define I2CxOP_INIT ((uint32_t)0x00000084) +#define I2CxIE_CLEAR ((uint32_t)0x00000000) +#define I2CxPRS_PRCK ((uint32_t)0x0000000F) +#define I2CxDBR_DB_MASK ((uint32_t)0x000000FF) +#define I2CxOP_SLAVE_INIT ((uint32_t)0x00000084) +#define I2CAR_SA_MASK ((uint32_t)0x000000FE) +#define I2CxSR_TRX ((uint32_t)0x00000040) +#define I2CxOP_SAST ((uint32_t)0x00000020) +#define I2CxIE_INTI2C ((uint32_t)0x00000001) +#define I2C_NO_DATA (0) +#define I2C_READ_ADDRESSED (1) +#define I2C_WRITE_ADDRESSED (3) +#define I2C_ACK (1) +#define I2C_TIMEOUT (100000) +// DAC +#define DAC_START ((uint32_t)0x00000001) +#define DAC_STOP ((uint32_t)0x00000000) +// ADC +#define ADC_12BIT_RANGE 0xFFF +#define ADC_SCLK_1 ((uint32_t)0x00000000) +#define ADxMOD0_RCUT_NORMAL ((uint32_t)0x00000000) +#define ADxMOD0_DACON_ON ((uint32_t)0x00000001) +#define ADxTSETn_ENINT_DISABLE ((uint32_t)0x00000000) +#define ADxTSETn_TRGS_SGL ((uint32_t)0x00000040) +#define ADxCR1_CNTDMEN_DISABLE ((uint32_t)0x00000000) +#define ADxCR1_SGLDMEN_DISABLE ((uint32_t)0x00000000) +#define ADxCR1_TRGDMEN_DISABLE ((uint32_t)0x00000000) +#define ADxCR1_TRGEN_DISABLE ((uint32_t)0x00000000) +#define ADxCR0_ADEN_DISABLE ((uint32_t)0x00000000) +#define ADxCR0_ADEN_ENABLE ((uint32_t)0x00000080) +#define ADxCR0_SGL_ENABLE ((uint32_t)0x00000002) +#define ADxCR0_CNT_DISABLE ((uint32_t)0x00000000) +#define ADxST_SNGF_IDLE ((uint32_t)0x00000000) +#define ADxST_SNGF_RUN ((uint32_t)0x00000004) +#define ADxREGn_ADRFn_MASK ((uint32_t)0x00000001) +#define ADxREGn_ADRFn_ON ((uint32_t)0x00000001) +#define ADxREGn_ADRn_MASK ((uint32_t)0x0000FFF0) +// Timer & PWM +#define T32A_INT_MASK ((uint32_t)0x0000000F) +#define T32A_MODE_32 ((uint32_t)0x00000001) +#define T32A_PRSCLx_32 ((uint32_t)0x30000000) +#define T32A_IMUFx_MASK_REQ ((uint32_t)0x00000008) +#define T32A_IMOFx_MASK_REQ ((uint32_t)0x00000004) +#define T32A_COUNT_STOP ((uint32_t)0x00000004) +#define T32A_COUNT_START ((uint32_t)0x00000002) +#define T32A_RUN_ENABLE ((uint32_t)0x00000001) +#define T32A_DBG_HALT_STOP ((uint32_t)0x00000002) +#define T32A_COUNT_DONT_START ((uint32_t)0x00000000) +#define T32A_RUN_DISABLE ((uint32_t)0x00000000) +#define T32A_WBF_ENABLE ((uint32_t)0x00100000) +#define T32A_RELOAD_TREGx ((uint32_t)0x00000700) +#define T32A_OCRCMPx0_SET ((uint32_t)0x00000001) +#define T32A_OCRCMPx1_CLR ((uint32_t)0x00000008) +#define T32A_OCR_DISABLE ((uint32_t)0x00000000) +#define DEFAULT_PERIOD 0.02f // 20ms +#define DEFAULT_CLOCK_DIVISION 32 +#define MAX_COUNTER_16B 0xFFFF +// UART +#define UART_ENABLE_RX ((uint32_t)0x00000001) +#define UART_ENABLE_TX ((uint32_t)0x00000002) +#define UARTxSWRST_SWRSTF_MASK ((uint32_t)0x00000080) +#define UARTxSWRST_SWRSTF_RUN ((uint32_t)0x00000080) +#define UARTxSWRST_SWRST_10 ((uint32_t)0x00000002) +#define UARTxSWRST_SWRST_01 ((uint32_t)0x00000001) +#define UARTxFIFOCLR_TFCLR_CLEAR ((uint32_t)0x00000002) +#define UARTxFIFOCLR_RFCLR_CLEAR ((uint32_t)0x00000001) +#define UART_PLESCALER_1 ((uint32_t)0x00000000) +#define UART_DIVISION_ENABLE ((uint32_t)0x00800000) +#define UART_TX_INT_ENABLE ((uint32_t)0x00000040) +#define UART_RX_INT_ENABLE ((uint32_t)0x00000010) +#define UART_RX_FIFO_FILL_LEVEL ((uint32_t)0x00000100) +#define UART_RANGE_K_MIN ((uint32_t)0x00000000) +#define UART_RANGE_K_MAX ((uint32_t)0x0000003F) +#define UART_RANGE_N_MIN ((uint32_t)0x00000001) +#define UART_RANGE_N_MAX ((uint32_t)0x0000FFFF) +#define UART_NUM 3 + +typedef struct { + uint32_t ken; // Enable/Disable Division Definition + uint32_t brk; // Division Value K + uint32_t brn; // Division Value N +} uart_boudrate_t; + +// Sleep +#define CG_STBY_MODE_IDLE 0x0 +#define CG_STBY_MODE_STOP1 0x1 +#define EXTERNEL_OSC_MASK 0xFFFFFFF9 +#define IHOSC_CFG_WARM_UP_TIME ((uint64_t)(5000)) +#define IHOSC_CFG_CLOCK ((uint64_t)(10000000)) +#define CGWUPHCR_WUPT_HIGH_MASK ((uint32_t)0xFFF00000) + +#endif // __GPIO_INCLUDE_H diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/gpio_irq_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/gpio_irq_api.c new file mode 100644 index 00000000000..631ee540dca --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/gpio_irq_api.c @@ -0,0 +1,365 @@ +/* mbed Microcontroller Library + * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "gpio_irq_api.h" +#include "mbed_error.h" +#include "PeripheralNames.h" +#include "pinmap.h" +#include "gpio_include.h" +#include "mbed_critical.h" + +const PinMap PinMap_GPIO_IRQ[] = { + {PC0, GPIO_IRQ_0, PIN_DATA(0, 0)}, + {PC1, GPIO_IRQ_1, PIN_DATA(0, 0)}, + {PC2, GPIO_IRQ_2, PIN_DATA(0, 0)}, + {PB1, GPIO_IRQ_3, PIN_DATA(0, 0)}, + {PJ4, GPIO_IRQ_4, PIN_DATA(0, 0)}, + {PK1, GPIO_IRQ_5, PIN_DATA(0, 0)}, + {PH3, GPIO_IRQ_6, PIN_DATA(0, 0)}, + {PA6, GPIO_IRQ_7, PIN_DATA(0, 0)}, + {PL3, GPIO_IRQ_8, PIN_DATA(0, 0)}, + {PM2, GPIO_IRQ_9, PIN_DATA(0, 0)}, + {PN3, GPIO_IRQ_A, PIN_DATA(0, 0)}, + {PA7, GPIO_IRQ_B, PIN_DATA(0, 0)}, + {PL4, GPIO_IRQ_C, PIN_DATA(0, 0)}, + {PK7, GPIO_IRQ_D, PIN_DATA(0, 0)}, + {PP3, GPIO_IRQ_E, PIN_DATA(0, 0)}, + {PM6, GPIO_IRQ_F, PIN_DATA(0, 0)}, + {NC, NC, 0} +}; + +static uint32_t channel_ids[CHANNEL_NUM] = {0}; +static gpio_irq_handler hal_irq_handler[CHANNEL_NUM] = {NULL}; +static void SetSTBYReleaseINTSrc(cg_intsrc, cg_intactivestate, FunctionalState); +static cg_intactivestate CurrentState; +static void INT_IRQHandler(PinName pin, uint32_t index); + +// Initialize gpio IRQ pin +int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) +{ + uint8_t bit = 0; + uint32_t port_base = 0; + + // Get gpio interrupt ID + obj->irq_id = pinmap_peripheral(pin, PinMap_GPIO_IRQ); + + // Disable interrupt by CPU + core_util_critical_section_enter(); + + // Calculate port and pin position + obj->port = (PortName)PIN_PORT(pin); + obj->pin = pin; + bit = PIN_POS(pin); + + port_base = BITBAND_PORT_BASE(obj->port); + port_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_DATA); + BITBAND_PORT_CLR(port_base, bit); + // Enable gpio interrupt function + pinmap_pinout(pin, PinMap_GPIO_IRQ); + + // Get GPIO irq source + switch (obj->irq_id) { + case GPIO_IRQ_0: + obj->irq_src = cg_int_src_0; + break; + case GPIO_IRQ_1: + obj->irq_src = cg_int_src_1; + break; + case GPIO_IRQ_2: + obj->irq_src = cg_int_src_2; + break; + case GPIO_IRQ_3: + obj->irq_src = cg_int_src_3; + break; + case GPIO_IRQ_4: + obj->irq_src = cg_int_src_4; + break; + case GPIO_IRQ_5: + obj->irq_src = cg_int_src_5; + break; + case GPIO_IRQ_6: + obj->irq_src = cg_int_src_6; + break; + case GPIO_IRQ_7: + obj->irq_src = cg_int_src_7; + break; + case GPIO_IRQ_8: + obj->irq_src = cg_int_src_8; + break; + case GPIO_IRQ_9: + obj->irq_src = cg_int_src_9; + break; + case GPIO_IRQ_A: + obj->irq_src = cg_int_src_a; + break; + case GPIO_IRQ_B: + obj->irq_src = cg_int_src_b; + break; + case GPIO_IRQ_C: + obj->irq_src = cg_int_src_c; + break; + case GPIO_IRQ_D: + obj->irq_src = cg_int_src_d; + break; + case GPIO_IRQ_E: + obj->irq_src = cg_int_src_e; + break; + case GPIO_IRQ_F: + obj->irq_src = cg_int_src_f; + break; + default: + break; + } + + // Save irq handler + hal_irq_handler[obj->irq_src] = handler; + + // Save irq id + channel_ids[obj->irq_src] = id; + + // Initialize interrupt event as both edges detection + obj->event = cg_int_active_state_both_edges; + CurrentState = cg_int_active_state_both_edges; + // Set interrupt event and enable INTx clear + SetSTBYReleaseINTSrc(obj->irq_src, (cg_intactivestate)obj->event, ENABLE); + + // Clear gpio pending interrupt + NVIC_ClearPendingIRQ((IRQn_Type) obj->irq_id); + + core_util_critical_section_exit(); + + return 0; +} + +void gpio_irq_free(gpio_irq_t *obj) +{ + // Clear gpio_irq + NVIC_ClearPendingIRQ((IRQn_Type)obj->irq_id); + // Reset interrupt handler + hal_irq_handler[obj->irq_src] = NULL; + // Reset interrupt id + channel_ids[obj->irq_src] = 0; +} + +// Set interrupt event of gpio_irq object +void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) +{ + uint8_t bit = 0; + uint32_t port_base = 0; + + //Disable GPIO interrupt on obj + gpio_irq_disable(obj); + if (enable) { + // Get gpio interrupt event + if (event == IRQ_RISE) { + if ((obj->event == cg_int_active_state_falling) || (obj->event == cg_int_active_state_both_edges)) { + obj->event = cg_int_active_state_both_edges; + } else { + obj->event = cg_int_active_state_rising; + } + } else if (event == IRQ_FALL) { + if ((obj->event == cg_int_active_state_rising) || (obj->event == cg_int_active_state_both_edges)) { + obj->event = cg_int_active_state_both_edges; + } else { + obj->event = cg_int_active_state_falling; + } + } else { + error("Not supported event\n"); + } + } else { + // Get gpio interrupt event + if (event == IRQ_RISE) { + if ((obj->event == cg_int_active_state_rising) || (obj->event == cg_int_active_state_invalid)) { + obj->event = cg_int_active_state_invalid; + } else { + obj->event = cg_int_active_state_falling; + } + } else if (event == IRQ_FALL) { + if ((obj->event == cg_int_active_state_falling) || (obj->event == cg_int_active_state_invalid)) { + obj->event = cg_int_active_state_invalid; + } else { + obj->event = cg_int_active_state_rising; + } + } else { + error("Not supported event\n"); + } + } + CurrentState = obj->event; + // Calculate port and pin position + bit = PIN_POS(obj->pin); + + port_base = BITBAND_PORT_BASE(obj->port); + port_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_DATA); + + if (obj->event != cg_int_active_state_invalid ) { + // Set interrupt event and enable INTx clear + SetSTBYReleaseINTSrc(obj->irq_src, (cg_intactivestate) obj->event, ENABLE); + BITBAND_PORT_CLR(port_base, bit); + } else { + BITBAND_PORT_SET(port_base, bit); + } + //Enable GPIO interrupt on obj + gpio_irq_enable(obj); +} + +// Enable gpio_irq object +void gpio_irq_enable(gpio_irq_t *obj) +{ + // Clear and Enable gpio_irq object + NVIC_ClearPendingIRQ((IRQn_Type)obj->irq_id); + NVIC_EnableIRQ((IRQn_Type)obj->irq_id); +} + +// Disable gpio_irq object +void gpio_irq_disable(gpio_irq_t *obj) +{ + // Disable gpio_irq object + NVIC_DisableIRQ((IRQn_Type)obj->irq_id); +} + +static void INT_IRQHandler(PinName pin, uint32_t index) +{ + int port = 0; + uint8_t bit = 0; + uint32_t data = 0; + uint32_t port_base = 0; + + // Calculate port and pin position + port = PIN_PORT(pin); + bit = PIN_POS(pin); + + // Clear interrupt request + SetSTBYReleaseINTSrc((cg_intsrc)(cg_int_src_0 + index), CurrentState, DISABLE); + + port_base = BITBAND_PORT_BASE(port); + port_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_DATA); + BITBAND_PORT_READ(data, port_base, bit); + + switch (data) { + // Falling edge detection + case 0: + hal_irq_handler[index](channel_ids[index], IRQ_FALL); + break; + // Rising edge detection + case 1: + hal_irq_handler[index](channel_ids[index], IRQ_RISE); + break; + default: + break; + } + // Clear gpio pending interrupt + NVIC_ClearPendingIRQ((IRQn_Type)(cg_int_src_0 + index)); + + // Enable interrupt request + SetSTBYReleaseINTSrc((cg_intsrc)(cg_int_src_0 + index), CurrentState, ENABLE); +} + +void INT00_IRQHandler(void) +{ + INT_IRQHandler(PC0, 0); +} + +void INT01_IRQHandler(void) +{ + INT_IRQHandler(PC1, 1); +} + +void INT02_IRQHandler(void) +{ + INT_IRQHandler(PC2, 2); +} + +void INT03_IRQHandler(void) +{ + INT_IRQHandler(PB1, 3); +} + +void INT04_IRQHandler(void) +{ + INT_IRQHandler(PJ4, 4); +} + +void INT05_IRQHandler(void) +{ + INT_IRQHandler(PK1, 5); +} + +void INT06_IRQHandler(void) +{ + INT_IRQHandler(PH3, 6); +} + +void INT07_IRQHandler(void) +{ + INT_IRQHandler(PA6, 7); +} + +void INT08_IRQHandler(void) +{ + INT_IRQHandler(PL3, 8); +} + +void INT09_IRQHandler(void) +{ + INT_IRQHandler(PM2, 9); +} + +void INT10_IRQHandler(void) +{ + INT_IRQHandler(PN3, 10); +} + +void INT11_IRQHandler(void) +{ + INT_IRQHandler(PA7, 11); +} + +void INT12_IRQHandler(void) +{ + INT_IRQHandler(PL4, 12); +} + +void INT13_IRQHandler(void) +{ + INT_IRQHandler(PK7, 13); +} + +void INT14_IRQHandler(void) +{ + INT_IRQHandler(PP3, 14); +} + +void INT15_IRQHandler(void) +{ + INT_IRQHandler(PM6, 15); +} + +static void SetSTBYReleaseINTSrc(cg_intsrc intsource, cg_intactivestate ActiveState, FunctionalState NewState) +{ + __IO uint8_t *p_imc; + + if (intsource < 3U) { + p_imc = (__IO uint8_t *)(&TSB_IA->IMC00 + (intsource)); + *p_imc = (uint8_t)(0xC0 | ActiveState | NewState); + } else { + intsource -= 3; + p_imc = (__IO uint8_t *)(&TSB_IB->IMC033 + (intsource)); + *p_imc = (uint8_t)(0xC0 | ActiveState | NewState); + } + // Dummy read is need + { + __IO uint8_t imc = *p_imc; + } +} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/gpio_object.h b/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/gpio_object.h new file mode 100644 index 00000000000..ec18793a163 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/gpio_object.h @@ -0,0 +1,81 @@ +/* mbed Microcontroller Library + * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_GPIO_OBJECT_H +#define MBED_GPIO_OBJECT_H + +#include "mbed_assert.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define GPIO_BIT_VALUE_1 ((uint8_t)0x01) +#define GPIO_BIT_VALUE_0 ((uint8_t)0x00) +#define GPIO_BIT_ALL ((uint8_t)0xFF) + +typedef enum { + cg_int_src_0 = 0U, + cg_int_src_1, + cg_int_src_2, + cg_int_src_3, + cg_int_src_4, + cg_int_src_5, + cg_int_src_6, + cg_int_src_7, + cg_int_src_8, + cg_int_src_9, + cg_int_src_a, + cg_int_src_b, + cg_int_src_c, + cg_int_src_d, + cg_int_src_e, + cg_int_src_f +} cg_intsrc; + +typedef enum { + cg_int_active_state_l = 0x00U, + cg_int_active_state_h = 0x02U, + cg_int_active_state_falling = 0x04U, + cg_int_active_state_rising = 0x06U, + cg_int_active_state_both_edges = 0x08U, + cg_int_active_state_invalid = 0x0AU +} cg_intactivestate; + +typedef struct { + PinName pin; + uint32_t mask; + PortName port; +} gpio_t; + +struct gpio_irq_s { + uint32_t mask; + PortName port; + PinName pin; + uint32_t irq_id; + cg_intactivestate event; + cg_intsrc irq_src; +}; + +static inline int gpio_is_connected(const gpio_t *obj) +{ + return (obj->pin != (PinName)NC); +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/i2c_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/i2c_api.c new file mode 100644 index 00000000000..8947fb61fac --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/i2c_api.c @@ -0,0 +1,377 @@ +/* mbed Microcontroller Library + * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "i2c_api.h" +#include "mbed_error.h" +#include "pinmap.h" +#include "gpio_include.h" + +static const PinMap PinMap_I2C_SDA[] = { + {PC1, I2C_0, PIN_DATA(1, 2)}, + {PA5, I2C_1, PIN_DATA(1, 2)}, + {PL1, I2C_2, PIN_DATA(3, 2)}, + {NC, NC, 0} +}; + +static const PinMap PinMap_I2C_SCL[] = { + {PC0, I2C_0, PIN_DATA(1, 2)}, + {PA4, I2C_1, PIN_DATA(1, 2)}, + {PL0, I2C_2, PIN_DATA(3, 2)}, + {NC, NC, 0} +}; + +// Clock setting structure definition +typedef struct { + uint32_t sck; + uint32_t prsck; +} I2C_clock_setting_t; + +// SCK Divider value table +static const uint32_t I2C_SCK_DIVIDER_TBL[8] = { + 20, 24, 32, 48, 80, 144, 272, 528 +}; + +I2C_clock_setting_t clk; +static uint32_t start_flag = 0; + +static int32_t wait_status(i2c_t *p_obj); +static void i2c_start_bit(i2c_t *obj); + +// Initialize the I2C peripheral. It sets the default parameters for I2C +void i2c_init(i2c_t *obj, PinName sda, PinName scl) +{ + MBED_ASSERT(obj != NULL); + + I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA); + I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL); + I2CName i2c_name = (I2CName)pinmap_merge(i2c_sda, i2c_scl); + + MBED_ASSERT((int)i2c_name != NC); + + switch (i2c_name) { + case I2C_0: + TSB_CG_FSYSENA_IPENA20 = ENABLE; + TSB_CG_FSYSENA_IPENA02 = ENABLE; + obj->i2c = TSB_I2C0; + break; + case I2C_1: + TSB_CG_FSYSENA_IPENA21 = ENABLE; + TSB_CG_FSYSENA_IPENA00 = ENABLE; + obj->i2c = TSB_I2C1; + break; + case I2C_2: + TSB_CG_FSYSENA_IPENA22 = ENABLE; + TSB_CG_FSYSENA_IPENA10 = ENABLE; + obj->i2c = TSB_I2C2; + break; + default: + error("I2C is not available"); + break; + } + + pinmap_pinout(sda, PinMap_I2C_SDA); + pin_mode(sda, OpenDrain); + pin_mode(sda, PullUp); + + pinmap_pinout(scl, PinMap_I2C_SCL); + pin_mode(scl, OpenDrain); + pin_mode(scl, PullUp); + + i2c_reset(obj); + i2c_frequency(obj, 100000); + obj->i2c->CR2 = (I2CxCR2_I2CM_ENABLE | I2CxCR2_TRX | I2CxCR2_PIN_CLEAR | + I2CxCR2_INIT); + obj->i2c->OP = I2CxOP_INIT; + obj->i2c->IE = I2CxIE_CLEAR; +} + +// Configure the I2C frequency +void i2c_frequency(i2c_t *obj, int hz) +{ + uint64_t sck; + uint64_t tmp_sck; + uint64_t prsck; + uint64_t tmp_prsck; + uint64_t fscl; + uint64_t tmp_fscl; + uint64_t fx; + + SystemCoreClockUpdate(); + + if (hz <= 1000000) { + sck = tmp_sck = 0; + prsck = tmp_prsck = 1; + fscl = tmp_fscl = 0; + for (prsck = 1; prsck <= 32; prsck++) { + fx = ((uint64_t)SystemCoreClock / prsck); + if ((fx < 20000000U) && (fx > 6666666U)) { + for (sck = 0; sck <= 7; sck++) { + fscl = (fx / (uint64_t)I2C_SCK_DIVIDER_TBL[sck]); + if ((fscl <= (uint64_t)hz) && (fscl > tmp_fscl)) { + tmp_fscl = fscl; + tmp_sck = sck; + tmp_prsck = (prsck < 32) ? prsck : 0; + } + } + } + } + clk.sck = (uint32_t)tmp_sck; + clk.prsck = (tmp_prsck < 32) ? (uint32_t)(tmp_prsck - 1) : 0; + } + + obj->i2c->CR1 = (I2CxCR1_ACK | clk.sck); + obj->i2c->PRS = (I2CxPRS_PRCK & clk.prsck); +} + +int i2c_start(i2c_t *obj) +{ + start_flag = 1; // Start Condition + return 0; +} + +int i2c_stop(i2c_t *obj) +{ + uint32_t timeout = I2C_TIMEOUT; + + obj->i2c->CR2 = I2CxCR2_STOP_CONDITION; + + while ((obj->i2c->SR & I2CxSR_BB) == I2CxSR_BB) { + if (timeout == 0) { + break; + } + timeout--; + } + + return 0; +} + +void i2c_reset(i2c_t *obj) +{ + obj->i2c->CR2 = I2CxCR2_SWRES_10; + obj->i2c->CR2 = I2CxCR2_SWRES_01; +} + +int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) +{ + int32_t result = 0; + int32_t count = 0; + int32_t pdata = 0; + + if (length > 0) { + start_flag = 1; // Start Condition + if (i2c_byte_write(obj, (int32_t)((uint32_t)address | 1U)) == I2C_ACK) { + while (count < length) { + pdata = i2c_byte_read(obj, ((count < (length - 1)) ? 0 : 1)); + if (pdata < 0) { + break; + } + data[count++] = (uint8_t)pdata; + } + result = count; + } else { + stop = 1; + result = I2C_ERROR_NO_SLAVE; + } + + if (stop) { // Stop Condition + i2c_stop(obj); + } + } + + return result; +} + +int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) +{ + int32_t result = 0; + int32_t count = 0; + + start_flag = 1; // Start Condition + + if (i2c_byte_write(obj, address) == I2C_ACK) { + while (count < length) { + if (i2c_byte_write(obj, (int32_t)data[count++]) < I2C_ACK) { + break; + } + } + result = count; + } else { + stop = 1; + result = I2C_ERROR_NO_SLAVE; + } + + if (stop) { // Stop Condition + i2c_stop(obj); + } + + return result; +} + +int i2c_byte_read(i2c_t *obj, int last) +{ + int32_t result = 0; + + obj->i2c->ST = I2CxST_CLEAR; + + if (last) { + obj->i2c->OP |= I2CxOP_MFACK; + } else { + obj->i2c->OP &= ~I2CxOP_MFACK; + } + + obj->i2c->DBR = (0 & I2CxDBR_DB_MASK); + + if (wait_status(obj) < 0) { + result = -1; + } else { + result = (int32_t)(obj->i2c->DBR & I2CxDBR_DB_MASK); + } + + return result; +} + +int i2c_byte_write(i2c_t *obj, int data) +{ + int32_t result = 0; + + obj->i2c->ST = I2CxST_CLEAR; + if (start_flag == 1) { + obj->i2c->DBR = (data & I2CxDBR_DB_MASK); + i2c_start_bit(obj); + start_flag = 0; + } else { + obj->i2c->DBR = (data & I2CxDBR_DB_MASK); + } + + if (wait_status(obj) < 0) { + return -1; + } + + if (!((obj->i2c->SR & I2CxSR_LRB) == I2CxSR_LRB)) { + result = 1; + } else { + result = 0; + } + + return result; +} + +static void i2c_start_bit(i2c_t *obj) // Send START command +{ + uint32_t opreg = 0; + + opreg = obj->i2c->OP; + opreg &= ~(I2CxOP_RSTA | I2CxOP_SREN); + + if ((obj->i2c->SR & I2CxSR_BB)) { + opreg |= I2CxOP_SREN; + } + + obj->i2c->OP = opreg; + obj->i2c->CR2 |= I2CxCR2_START_CONDITION; +} + +static int32_t wait_status(i2c_t *p_obj) +{ + volatile int32_t timeout; + timeout = I2C_TIMEOUT; + + while (!((p_obj->i2c->ST & I2CxST_I2C) == I2CxST_I2C)) { + if ((timeout--) == 0) { + return (-1); + } + } + + return 0; +} + +void i2c_slave_mode(i2c_t *obj, int enable_slave) +{ + if (enable_slave) { + obj->i2c->OP = I2CxOP_SLAVE_INIT; + obj->i2c->CR1 = (I2CxCR1_ACK | clk.sck); + obj->i2c->CR2 = (I2CxCR2_INIT | I2CxCR2_PIN_CLEAR); + obj->i2c->PRS = (I2CxPRS_PRCK & clk.prsck); + obj->i2c->AR = (obj->address & I2CAR_SA_MASK); + obj->i2c->IE = I2CxIE_INTI2C; + } else { + i2c_reset(obj); + obj->i2c->CR2 = (I2CxCR2_I2CM_ENABLE | I2CxCR2_TRX | I2CxCR2_PIN_CLEAR | + I2CxCR2_INIT); + obj->i2c->OP = I2CxOP_INIT; + obj->i2c->CR1 = (I2CxCR1_ACK | clk.sck); + obj->i2c->PRS = (I2CxPRS_PRCK & clk.prsck); + NVIC_DisableIRQ(obj->IRQn); + NVIC_ClearPendingIRQ(obj->IRQn); + obj->i2c->ST = I2CxST_CLEAR; + } +} + +int i2c_slave_receive(i2c_t *obj) +{ + int32_t result = I2C_NO_DATA; + + if ((obj->i2c->ST & I2CxST_I2C) && (obj->i2c->OP & I2CxOP_SAST)) { + if ((obj->i2c->SR & I2CxSR_TRX) == I2CxSR_TRX) { + result = I2C_READ_ADDRESSED; + } else { + result = I2C_WRITE_ADDRESSED; + } + } + + return (result); +} + +int i2c_slave_read(i2c_t *obj, char *data, int length) +{ + int32_t count = 0; + + while (count < length) { + int32_t pdata = i2c_byte_read(obj, ((count < (length - 1)) ? 0 : 1)); + if ((obj->i2c->SR & I2CxSR_TRX)) { + return (count); + } else { + if (pdata < 0) { + break; + } + data[count++] = (uint8_t)pdata; + } + } + + i2c_slave_mode(obj,1); + + return (count); +} + +int i2c_slave_write(i2c_t *obj, const char *data, int length) +{ + int32_t count = 0; + + while (count < length) { + if (i2c_byte_write(obj, (int32_t)data[count++]) < I2C_ACK) { + break; + } + } + + i2c_slave_mode(obj,1); + + return (count); +} + +void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) +{ + obj->address = address & I2CAR_SA_MASK; + i2c_slave_mode(obj,1); +} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/objects.h b/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/objects.h new file mode 100644 index 00000000000..4f5e6254642 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/objects.h @@ -0,0 +1,115 @@ +/* mbed Microcontroller Library + * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_OBJECTS_H +#define MBED_OBJECTS_H + +#include +#include "PortNames.h" +#include "PeripheralNames.h" +#include "txz_tspi.h" +#include "PinNames.h" +#include "TMPM3H6.h" +#include "gpio_include.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct { + uint32_t BaudRate; + uint32_t DataBits; + uint32_t StopBits; + uint32_t Parity; + uint32_t Mode; + uint32_t FlowCtrl; +} uart_inittypedef_t; + +struct port_s { + PortName port; + uint32_t mask; +}; + +typedef struct { + uint8_t PinDATA; + uint8_t PinCR; + uint8_t PinFR[6]; + uint8_t PinOD; + uint8_t PinPUP; + uint8_t PinPDN; + uint8_t PinIE; +} gpio_regtypedef_t; + +typedef struct { + __IO uint32_t DATA; + __IO uint32_t CR; + __IO uint32_t FR[6]; + uint32_t RESERVED0[2]; + __IO uint32_t OD; + __IO uint32_t PUP; + __IO uint32_t PDN; + uint32_t RESERVED1; + __IO uint32_t IE; +} TSB_Port_TypeDef; + +struct serial_s { + PinName pin; + uint32_t index; + TSB_UART_TypeDef *UARTx; + uart_inittypedef_t uart_config; +}; + +struct analogin_s { + PinName pin; + ADCName adc; + TSB_AD_TypeDef *obj; +}; + +struct dac_s { + DACName dac; + TSB_DA_TypeDef *handler; +}; + +struct pwmout_s { + PinName pin; + TSB_T32A_TypeDef *channel; + uint16_t trailing_timing; + uint16_t leading_timing; + uint16_t divisor; + float period; +}; + +struct i2c_s { + uint32_t address; + IRQn_Type IRQn; + TSB_I2C_TypeDef *i2c; +}; + +struct spi_s { + tspi_t p_obj; + SPIName module; + uint8_t bits; +}; + +extern const gpio_regtypedef_t GPIO_SFRs[]; +extern const uint32_t GPIO_Base[]; + +#include "gpio_object.h" + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/periph_driver/txz_driver_def.h b/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/periph_driver/txz_driver_def.h new file mode 100644 index 00000000000..1b3ab6c5dd2 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/periph_driver/txz_driver_def.h @@ -0,0 +1,96 @@ +/** + ******************************************************************************* + * @file txz_driver_def.h + * @brief All common macro and definition for TXZ peripheral drivers + * @version V1.0.0.0 + * $Date:: 2018-01-22 15:26:40 #$ + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved + ******************************************************************************* + */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __TXZ_DRIVER_DEF_H +#define __TXZ_DRIVER_DEF_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup Periph_Driver Peripheral Driver + * @{ + */ + +/** @defgroup TXZ_DRIVER_DEF TXZ DRIVER DEF + * @brief All common macro and definition for TXZ peripheral drivers + * @{ + */ + +/** @defgroup Device_Header_Included Device Header Included + * @brief Include the Device header file of a Target. + * @{ + */ +#include "TMPM3H6.h" /*!< TMPM3H6 Group Header file. */ +/** + * @} + */ /* End of group Device_Header */ + + +/** @defgroup TXZ_Exported_typedef TXZ Exported typedef + * @{ + */ +typedef enum { + TXZ_SUCCESS = 0U, + TXZ_ERROR = 1U +} TXZ_Result; + +typedef enum { + TXZ_BUSY = 0U, + TXZ_DONE = 1U +} TXZ_WorkState; + +typedef enum { + TXZ_DISABLE = 0U, + TXZ_ENABLE = 1U +} TXZ_FunctionalState; +/** + * @} + */ /* End of group TXZ_Exported_typedef */ + +/** @defgroup TXZ_Exported_macro TXZ Exported macro + * @{ + */ +#define IS_TXZ_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +#define IS_POINTER_NOT_NULL(param) ((void*)(param)!=(void*)0) + +/** + * @brief To report the name of the source file and source line number where the + * assert_param error has occurred, "DEBUG" must be defined. And detailed + * definition of assert_failed() is needed to be implemented, which can be + * done, for example, in the main.c file. + */ +#ifdef DEBUG +void assert_failed(char *file, int32_t line); +#define assert_param(expr) ((expr) ? (void)0 : assert_failed((char *)__FILE__, __LINE__)) +#else +#define assert_param(expr) +#endif /* DEBUG */ +/** + * @} + */ /* End of group TXZ_Exported_macro */ + +/** + * @} + */ /* End of group Periph_Driver */ + +/** + * @} + */ /* End of group TXZ_DRIVER_DEF */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __TXZ_DRIVER_DEF_H */ diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/periph_driver/txz_tspi.c b/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/periph_driver/txz_tspi.c new file mode 100644 index 00000000000..f8b408a4b6f --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/periph_driver/txz_tspi.c @@ -0,0 +1,2555 @@ +/** + ******************************************************************************* + * @file txz_tspi.c + * @brief This file provides API functions for TSPI driver. + * @version V1.0.0.9 + * $Date:: 2018-01-22 15:26:40 #$ + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LISENCE AGREEMENT. + * + * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved + ******************************************************************************* + */ + +#ifdef __cplusplus + extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txz_tspi.h" + +#if defined(__TSPI_H) +/** + * @addtogroup Periph_Driver + * @{ + */ + +/** + * @addtogroup TSPI + * @{ + */ + +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup TSPI_Private_define TSPI Private Define + * @{ + */ +/** + * @name TSPI NULL Pointer + * @brief Null Pointer for TSPI + * @{ + */ +#define TSPI_NULL ((void *)0) /*!< NULL pointer. */ +/** + * @} + */ /* End of name TSPI NULL Pointer */ + +/** + * @name Parameter Result + * @brief Whether the parameter is specified or not. + * @{ + */ +#define PARAM_OK ((int32_t)1) /*!< Parameter is valid(specified). */ +#define PARAM_NG ((int32_t)0) /*!< Parameter is invalid(not specified). */ +/** + * @} + */ /* End of name Parameter Result */ + +/** + * @name FIFO Max Num. + * @brief Transfer's/Receive's FIFO Max Num. + * @{ + */ +#define TRANSFER_FIFO_MAX_NUM ((uint32_t)8) /*!< Transfer's FIFO Max Num. */ +#define RECEIVE_FIFO_MAX_NUM ((uint32_t)8) /*!< Receive's FIFO Max Num. */ +/** + * @} + */ /* End of name FIFO Max Num */ + +/** + * @name TSPIxDR_MASK Macro Definition. + * @brief TSPIxDR_MASK Macro Definition. + * @{ + */ +/* DR */ +#define TSPI_DR_8BIT_MASK ((uint32_t)0x000000FF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_9BIT_MASK ((uint32_t)0x000001FF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_10BIT_MASK ((uint32_t)0x000003FF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_11BIT_MASK ((uint32_t)0x000007FF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_12BIT_MASK ((uint32_t)0x00000FFF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_13BIT_MASK ((uint32_t)0x00001FFF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_14BIT_MASK ((uint32_t)0x00003FFF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_15BIT_MASK ((uint32_t)0x00007FFF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_16BIT_MASK ((uint32_t)0x0000FFFF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_17BIT_MASK ((uint32_t)0x0001FFFF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_18BIT_MASK ((uint32_t)0x0003FFFF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_19BIT_MASK ((uint32_t)0x0007FFFF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_20BIT_MASK ((uint32_t)0x000FFFFF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_21BIT_MASK ((uint32_t)0x001FFFFF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_22BIT_MASK ((uint32_t)0x003FFFFF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_23BIT_MASK ((uint32_t)0x007FFFFF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_24BIT_MASK ((uint32_t)0x00FFFFFF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_25BIT_MASK ((uint32_t)0x01FFFFFF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_26BIT_MASK ((uint32_t)0x03FFFFFF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_27BIT_MASK ((uint32_t)0x07FFFFFF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_28BIT_MASK ((uint32_t)0x0FFFFFFF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_29BIT_MASK ((uint32_t)0x1FFFFFFF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_30BIT_MASK ((uint32_t)0x3FFFFFFF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_31BIT_MASK ((uint32_t)0x7FFFFFFF) /*!< DR :Mask for 8bit */ +/** + * @} + */ /* End of name TSPIxDR_MASK Macro Definition */ + +/** + * @name TSPI _DATA_LENGTH Macro Definition. + * @brief TSPI DATA LENGTH Macro Definition. + * @{ + */ +#define DATA_LENGTH_8 ((uint32_t)0x08) /*!< 8 bit */ +#define DATA_LENGTH_9 ((uint32_t)0x09) /*!< 9 bit */ +#define DATA_LENGTH_10 ((uint32_t)0x0a) /*!< 10 bit */ +#define DATA_LENGTH_11 ((uint32_t)0x0b) /*!< 11 bit */ +#define DATA_LENGTH_12 ((uint32_t)0x0c) /*!< 12 bit */ +#define DATA_LENGTH_13 ((uint32_t)0x0d) /*!< 13 bit */ +#define DATA_LENGTH_14 ((uint32_t)0x0e) /*!< 14 bit */ +#define DATA_LENGTH_15 ((uint32_t)0x0f) /*!< 15 bit */ +#define DATA_LENGTH_16 ((uint32_t)0x10) /*!< 16 bit */ +#define DATA_LENGTH_17 ((uint32_t)0x11) /*!< 17 bit */ +#define DATA_LENGTH_18 ((uint32_t)0x12) /*!< 18 bit */ +#define DATA_LENGTH_19 ((uint32_t)0x13) /*!< 19 bit */ +#define DATA_LENGTH_20 ((uint32_t)0x14) /*!< 20 bit */ +#define DATA_LENGTH_21 ((uint32_t)0x15) /*!< 21 bit */ +#define DATA_LENGTH_22 ((uint32_t)0x16) /*!< 22 bit */ +#define DATA_LENGTH_23 ((uint32_t)0x17) /*!< 23 bit */ +#define DATA_LENGTH_24 ((uint32_t)0x18) /*!< 24 bit */ +#define DATA_LENGTH_25 ((uint32_t)0x19) /*!< 25 bit */ +#define DATA_LENGTH_26 ((uint32_t)0x1a) /*!< 26 bit */ +#define DATA_LENGTH_27 ((uint32_t)0x1b) /*!< 27 bit */ +#define DATA_LENGTH_28 ((uint32_t)0x1c) /*!< 28 bit */ +#define DATA_LENGTH_29 ((uint32_t)0x1d) /*!< 29 bit */ +#define DATA_LENGTH_30 ((uint32_t)0x1e) /*!< 30 bit */ +#define DATA_LENGTH_31 ((uint32_t)0x1f) /*!< 31 bit */ +#define DATA_LENGTH_32 ((uint32_t)0x20) /*!< 32 bit */ +/** + * @} + */ /* End of name TSPI _DATA_LENGTH Macro Definition */ +/** + * @} + */ /* End of group TSPI_Private_typedef */ +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup TSPI_Private_define TSPI Private Define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group TSPI_Private_define */ +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup TSPI_Private_typedef TSPI Private Typedef + * @{ + */ +/*----------------------------------*/ +/** + * @brief TSPI mask array. +*/ +/*----------------------------------*/ +static uint32_t mask[32] ={ + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + TSPI_DR_8BIT_MASK, + TSPI_DR_9BIT_MASK, + TSPI_DR_10BIT_MASK, + TSPI_DR_11BIT_MASK, + TSPI_DR_12BIT_MASK, + TSPI_DR_13BIT_MASK, + TSPI_DR_14BIT_MASK, + TSPI_DR_15BIT_MASK, + TSPI_DR_16BIT_MASK, + TSPI_DR_17BIT_MASK, + TSPI_DR_18BIT_MASK, + TSPI_DR_19BIT_MASK, + TSPI_DR_20BIT_MASK, + TSPI_DR_21BIT_MASK, + TSPI_DR_22BIT_MASK, + TSPI_DR_23BIT_MASK, + TSPI_DR_24BIT_MASK, + TSPI_DR_25BIT_MASK, + TSPI_DR_26BIT_MASK, + TSPI_DR_27BIT_MASK, + TSPI_DR_28BIT_MASK, + TSPI_DR_29BIT_MASK, + TSPI_DR_30BIT_MASK, + TSPI_DR_31BIT_MASK +}; + +/** + * @} + */ /* End of group TSPI_Private_typedef */ + +/*------------------------------------------------------------------------------*/ +/* Private Function */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup TSPI_Private_fuctions TSPI Private Fuctions + * @{ + */ + +#ifdef DEBUG + __INLINE static int32_t check_param_transmit_enable(uint32_t param); + __INLINE static int32_t check_param_transmit_tspi_sio(uint32_t param); + __INLINE static int32_t check_param_transmit_master(uint32_t param); + __INLINE static int32_t check_param_transmit_mode(uint32_t param); + __INLINE static int32_t check_param_transmit_sel_select(uint32_t param); + __INLINE static int32_t check_param_frame_range(uint32_t param); + __INLINE static int32_t check_param_idle_imp(uint32_t param); + __INLINE static int32_t check_param_underrun_imp(uint32_t param); + __INLINE static int32_t check_param_tx_fill_level(uint32_t param); + __INLINE static int32_t check_param_rx_fill_level(uint32_t param); + __INLINE static int32_t check_param_tx_fifo_int(uint32_t param); + __INLINE static int32_t check_param_rx_fifo_int(uint32_t param); + __INLINE static int32_t check_param_err_int(uint32_t param); + __INLINE static int32_t check_param_tx_dma_int(uint32_t param); + __INLINE static int32_t check_param_rx_dma_int(uint32_t param); + __INLINE static int32_t check_param_input_clock(uint32_t param); + __INLINE static int32_t check_param_input_divider(uint32_t param); + __INLINE static int32_t check_param_data_direction(uint32_t param); + __INLINE static int32_t check_param_frame_length(uint32_t param); + __INLINE static int32_t check_param_frame_interval(uint32_t param); + __INLINE static int32_t check_param_tspixcs3_imp(uint32_t param); + __INLINE static int32_t check_param_tspixcs2_imp(uint32_t param); + __INLINE static int32_t check_param_tspixcs1_imp(uint32_t param); + __INLINE static int32_t check_param_tspixcs0_imp(uint32_t param); + __INLINE static int32_t check_param_clock_edge_imp(uint32_t param); + __INLINE static int32_t check_param_clock_idle_imp(uint32_t param); + __INLINE static int32_t check_param_min_idle_time(uint32_t param); + __INLINE static int32_t check_param_clock_delay(uint32_t param); + __INLINE static int32_t check_param_negate_delay(uint32_t param); + __INLINE static int32_t check_param_parity_enable(uint32_t param); + __INLINE static int32_t check_param_parity_bit(uint32_t param); +#endif + +#ifdef DEBUG +/*--------------------------------------------------*/ +/** + * @brief Check the Transmit Enable's parameter. + * @param param :Transmit Enable's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_Transmission_Control + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_transmit_enable(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) + { + case TSPI_TRXE_DISABLE: + case TSPI_TRXE_ENABLE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} +/*--------------------------------------------------*/ +/** + * @brief Check the Transmit Mode's parameter. + * @param param :Transmit Mode's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_Transmission_Mode + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_transmit_tspi_sio(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) + { + case TSPI_SPI_MODE: + case TSPI_SIO_MODE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Transmit Master/Slave parameter. + * @param param :Transmit Master/Slave parameter (Only support Master mode) + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_Operation_Select + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_transmit_master(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) + { + case TSPI_MASTER_OPEARTION: + case TSPI_SLAVE_OPERATION: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Transfer Mode's parameter. + * @param param :Transfer Mode's parameter (not support Two Way) + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_Transfer_Mode + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_transmit_mode(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) + { + case TSPI_TWO_WAY: + case TSPI_TX_ONLY: + case TSPI_RX_ONLY: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Transmit Sel Select's parameter. + * @param param :Transmit Sel Select's parameter (not support Two Way) + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_CSSEL_Select + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_transmit_sel_select(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) + { + case TSPI_TSPIxCS0_ENABLE: + case TSPI_TSPIxCS1_ENABLE: + case TSPI_TSPIxCS2_ENABLE: + case TSPI_TSPIxCS3_ENABLE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Transmit Frame Range's parameter. + * @param param :TransmitFrame Range's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_Transfer_Frame_Range + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_frame_range(uint32_t param) + +{ + int32_t result = PARAM_NG; + + if ((TSPI_TRANS_RANGE_SINGLE == param) || (param <= TSPI_TRANS_RANGE_MAX)){ + result = PARAM_OK; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the IDLE Output Value's parameter. + * @param param :IDLE Output Value's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_IDLE_Output_value + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_idle_imp(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) + { + case TSPI_TIDLE_Hiz: + case TSPI_TIDLE_LAST_DATA: + case TSPI_TIDLE_LOW: + case TSPI_TIDLE_HI: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Underrun Occur Output Value's parameter. + * @param param :Underrun Occur Output Value's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_Underrun_Output_value + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_underrun_imp(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) + { + case TSPI_TXDEMP_LOW: + case TSPI_TXDEMP_HI: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Tx Fill Level's parameter. + * @param param :Tx Fill Level's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_TxFillLevel + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_tx_fill_level(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) + { + case TSPI_TX_FILL_LEVEL_0: + case TSPI_TX_FILL_LEVEL_1: + case TSPI_TX_FILL_LEVEL_2: + case TSPI_TX_FILL_LEVEL_3: + case TSPI_TX_FILL_LEVEL_4: + case TSPI_TX_FILL_LEVEL_5: + case TSPI_TX_FILL_LEVEL_6: + case TSPI_TX_FILL_LEVEL_7: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + + +/*--------------------------------------------------*/ +/** + * @brief Check the Rx Fill Level's parameter. + * @param param :Rx Fill Level's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_RxFillLevel + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_rx_fill_level(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) + { + case TSPI_RX_FILL_LEVEL_0: + case TSPI_RX_FILL_LEVEL_1: + case TSPI_RX_FILL_LEVEL_2: + case TSPI_RX_FILL_LEVEL_3: + case TSPI_RX_FILL_LEVEL_4: + case TSPI_RX_FILL_LEVEL_5: + case TSPI_RX_FILL_LEVEL_6: + case TSPI_RX_FILL_LEVEL_7: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Tx FIFO Interrpt's parameter. + * @param param :Tx FIFO Interrpt's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_TxInterrupt + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_tx_fifo_int(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) + { + case TSPI_TX_FIFO_INT_DISABLE: + case TSPI_TX_FIFO_INT_ENABLE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Tx Interrpt's parameter. + * @param param :Tx Interrpt's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_TxInterrupt + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_tx_int(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) + { + case TSPI_TX_INT_DISABLE: + case TSPI_TX_INT_ENABLE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Rx FIFO Interrpt's parameter. + * @param param :Rx FIFO Interrpt's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_RxFIFOInterrupt + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_rx_fifo_int(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) + { + case TSPI_RX_FIFO_INT_DISABLE: + case TSPI_RX_FIFO_INT_ENABLE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Rx Interrpt's parameter. + * @param param :Rx Interrpt's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_RxInterrupt + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_rx_int(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) + { + case TSPI_RX_INT_DISABLE: + case TSPI_RX_INT_ENABLE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Error Interrupt's parameter. + * @param param :Error Interrupt's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_ErrorInterrupt + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_err_int(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) + { + case TSPI_ERR_INT_DISABLE: + case TSPI_ERR_INT_ENABLE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Tx DMA Interrupt's parameter. + * @param param :Tx DMA Interrupt's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_TxDMAInterrupt + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_tx_dma_int(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) + { + case TSPI_TX_DMA_INT_DISABLE: + case TSPI_TX_DMA_INT_ENABLE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Rx DMA Interrupt's parameter. + * @param param :Rx DMA Interrupt's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_RxDMAInterrupt + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_rx_dma_int(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) + { + case TSPI_RX_DMA_INT_DISABLE: + case TSPI_RX_DMA_INT_ENABLE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Input Clock's parameter. + * @param param :Input Clock's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_Baudrate_Clock + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_input_clock(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) + { + case TSPI_BR_CLOCK_0: + case TSPI_BR_CLOCK_1: + case TSPI_BR_CLOCK_2: + case TSPI_BR_CLOCK_4: + case TSPI_BR_CLOCK_8: + case TSPI_BR_CLOCK_16: + case TSPI_BR_CLOCK_32: + case TSPI_BR_CLOCK_64: + case TSPI_BR_CLOCK_128: + case TSPI_BR_CLOCK_256: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Baudrate Divider's parameter. + * @param param :Baudrate Divider's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_Baudrate_Clock + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_input_divider(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) + { + case TSPI_BR_DIVIDER_16: + case TSPI_BR_DIVIDER_1: + case TSPI_BR_DIVIDER_2: + case TSPI_BR_DIVIDER_3: + case TSPI_BR_DIVIDER_4: + case TSPI_BR_DIVIDER_5: + case TSPI_BR_DIVIDER_6: + case TSPI_BR_DIVIDER_7: + case TSPI_BR_DIVIDER_8: + case TSPI_BR_DIVIDER_9: + case TSPI_BR_DIVIDER_10: + case TSPI_BR_DIVIDER_11: + case TSPI_BR_DIVIDER_12: + case TSPI_BR_DIVIDER_13: + case TSPI_BR_DIVIDER_14: + case TSPI_BR_DIVIDER_15: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Data Direction's parameter. + * @param param :Data Direction's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_DataDirection"TSPI_DATA_DIRECTION_xxxx". + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_data_direction(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) + { + case TSPI_DATA_DIRECTION_LSB: + case TSPI_DATA_DIRECTION_MSB: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Data Length's parameter. + * @param param :Data Length's parameter (Only support 8bit DATA) + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_DataLength"TSPI_DATA_LENGTH_xxxx". + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_frame_length(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) + { + case TSPI_DATA_LENGTH_8: + case TSPI_DATA_LENGTH_9: + case TSPI_DATA_LENGTH_10: + case TSPI_DATA_LENGTH_11: + case TSPI_DATA_LENGTH_12: + case TSPI_DATA_LENGTH_13: + case TSPI_DATA_LENGTH_14: + case TSPI_DATA_LENGTH_15: + case TSPI_DATA_LENGTH_16: + case TSPI_DATA_LENGTH_17: + case TSPI_DATA_LENGTH_18: + case TSPI_DATA_LENGTH_19: + case TSPI_DATA_LENGTH_20: + case TSPI_DATA_LENGTH_21: + case TSPI_DATA_LENGTH_22: + case TSPI_DATA_LENGTH_23: + case TSPI_DATA_LENGTH_24: + case TSPI_DATA_LENGTH_25: + case TSPI_DATA_LENGTH_26: + case TSPI_DATA_LENGTH_27: + case TSPI_DATA_LENGTH_28: + case TSPI_DATA_LENGTH_29: + case TSPI_DATA_LENGTH_30: + case TSPI_DATA_LENGTH_31: + case TSPI_DATA_LENGTH_32: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Frame Interval's parameter. + * @param param :Frame Interval's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_Frame_Interval_Time + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_frame_interval(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) + { + case TSPI_INTERVAL_TIME_0: + case TSPI_INTERVAL_TIME_1: + case TSPI_INTERVAL_TIME_2: + case TSPI_INTERVAL_TIME_3: + case TSPI_INTERVAL_TIME_4: + case TSPI_INTERVAL_TIME_5: + case TSPI_INTERVAL_TIME_6: + case TSPI_INTERVAL_TIME_7: + case TSPI_INTERVAL_TIME_8: + case TSPI_INTERVAL_TIME_9: + case TSPI_INTERVAL_TIME_10: + case TSPI_INTERVAL_TIME_11: + case TSPI_INTERVAL_TIME_12: + case TSPI_INTERVAL_TIME_13: + case TSPI_INTERVAL_TIME_14: + case TSPI_INTERVAL_TIME_15: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the TTSPIxCS3 Polarity's parameter. + * @param param :TTSPIxCS3 Polarity's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_TTSPIxCS3_Polarity. + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_tspixcs3_imp(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) + { + case TSPI_TSPIxCS3_NEGATIVE: + case TSPI_TSPIxCS3_POSITIVE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the TTSPIxCS2 Polarity's parameter. + * @param param :TTSPIxCS2 Polarity's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_TTSPIxCS2_Polarity. + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_tspixcs2_imp(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) + { + case TSPI_TSPIxCS2_NEGATIVE: + case TSPI_TSPIxCS2_POSITIVE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the TTSPIxCS1 Polarity's parameter. + * @param param :TTSPIxCS1 Polarity's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_TTSPIxCS1_Polarity. + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_tspixcs1_imp(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) + { + case TSPI_TSPIxCS1_NEGATIVE: + case TSPI_TSPIxCS1_POSITIVE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the TTSPIxCS0 Polarity's parameter. + * @param param :TTSPIxCS0 Polarity's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_TTSPIxCS0_Polarity. + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_tspixcs0_imp(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) + { + case TSPI_TSPIxCS0_NEGATIVE: + case TSPI_TSPIxCS0_POSITIVE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Serial Clock Polarity's parameter. + * @param param :Serial Clock Polarity's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_Serial_Clock_Polarity + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_clock_edge_imp(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) + { + case TSPI_SERIAL_CK_1ST_EDGE: + case TSPI_SERIAL_CK_2ND_EDGE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Serial Clock IDLE Polarity's parameter. + * @param param :Serial Clock IDLE Polarity's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_Serial_Clock_IDLE_Polarity + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_clock_idle_imp(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) + { + case TSPI_SERIAL_CK_IDLE_LOW: + case TSPI_SERIAL_CK_IDLE_HI: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Minimum IDLE Time's parameter. + * @param param :Minimum IDLE Time's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_Minimum_IDLE_Time + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_min_idle_time(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) + { + case TSPI_MIN_IDLE_TIME_1: + case TSPI_MIN_IDLE_TIME_2: + case TSPI_MIN_IDLE_TIME_3: + case TSPI_MIN_IDLE_TIME_4: + case TSPI_MIN_IDLE_TIME_5: + case TSPI_MIN_IDLE_TIME_6: + case TSPI_MIN_IDLE_TIME_7: + case TSPI_MIN_IDLE_TIME_8: + case TSPI_MIN_IDLE_TIME_9: + case TSPI_MIN_IDLE_TIME_10: + case TSPI_MIN_IDLE_TIME_11: + case TSPI_MIN_IDLE_TIME_12: + case TSPI_MIN_IDLE_TIME_13: + case TSPI_MIN_IDLE_TIME_14: + case TSPI_MIN_IDLE_TIME_15: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Serial Clock Delay's parameter. + * @param param :Serial Clock Delay's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_Serial_Clock_Delay + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_clock_delay(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) + { + case TSPI_SERIAL_CK_DELAY_1: + case TSPI_SERIAL_CK_DELAY_2: + case TSPI_SERIAL_CK_DELAY_3: + case TSPI_SERIAL_CK_DELAY_4: + case TSPI_SERIAL_CK_DELAY_5: + case TSPI_SERIAL_CK_DELAY_6: + case TSPI_SERIAL_CK_DELAY_7: + case TSPI_SERIAL_CK_DELAY_8: + case TSPI_SERIAL_CK_DELAY_9: + case TSPI_SERIAL_CK_DELAY_10: + case TSPI_SERIAL_CK_DELAY_11: + case TSPI_SERIAL_CK_DELAY_12: + case TSPI_SERIAL_CK_DELAY_13: + case TSPI_SERIAL_CK_DELAY_14: + case TSPI_SERIAL_CK_DELAY_15: + case TSPI_SERIAL_CK_DELAY_16: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Negate Delay's parameter. + * @param param :Negate Delay's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_Negate_Delay + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_negate_delay(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) + { + case TSPI_NEGATE_1: + case TSPI_NEGATE_2: + case TSPI_NEGATE_3: + case TSPI_NEGATE_4: + case TSPI_NEGATE_5: + case TSPI_NEGATE_6: + case TSPI_NEGATE_7: + case TSPI_NEGATE_8: + case TSPI_NEGATE_9: + case TSPI_NEGATE_10: + case TSPI_NEGATE_11: + case TSPI_NEGATE_12: + case TSPI_NEGATE_13: + case TSPI_NEGATE_14: + case TSPI_NEGATE_15: + case TSPI_NEGATE_16: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Parity Enable's parameter. + * @param param :Parity Enable's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_ParityEnable"TSPI_PARITY_xxxx". + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_parity_enable(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) + { + case TSPI_PARITY_DISABLE: + case TSPI_PARITY_ENABLE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Parity Bit's parameter. + * @param param :Parity Bit's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_ParityBit"TSPI_PARITY_BIT_xxxx". + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_parity_bit(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) + { + case TSPI_PARITY_BIT_ODD: + case TSPI_PARITY_BIT_EVEN: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} +#endif +/** + * @} + */ /* End of group TSPI_Private_functions */ + +/*------------------------------------------------------------------------------*/ +/* Public Function */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup TSPI_Exported_functions + * @{ + */ +/*--------------------------------------------------*/ +/** + * @brief Initialize the TSPI object. + * @param p_obj :TSPI object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, "Failure" is returned. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result tspi_init(tspi_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + /* Check the parameters */ +#ifdef DEBUG + /* Check the NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + /* Check the parameter of TTSPIxCR1. */ + assert_param(check_param_transmit_enable(p_obj->init.cnt1.trxe)); + assert_param(check_param_transmit_tspi_sio(p_obj->init.cnt1.tspims)); + assert_param(check_param_transmit_master(p_obj->init.cnt1.mstr)); + assert_param(check_param_transmit_mode(p_obj->init.cnt1.tmmd)); + assert_param(check_param_transmit_sel_select(p_obj->init.cnt1.cssel)); + assert_param(check_param_frame_range(p_obj->init.cnt1.fc)); + /* Check the parameter of TTSPIxCR2 */ + assert_param(check_param_idle_imp(p_obj->init.cnt2.tidle)); + assert_param(check_param_underrun_imp(p_obj->init.cnt2.txdemp)); + assert_param(check_param_tx_fill_level(p_obj->init.cnt2.til)); + assert_param(check_param_rx_fill_level(p_obj->init.cnt2.ril)); + assert_param(check_param_tx_int(p_obj->init.cnt2.inttxwe)); + assert_param(check_param_rx_int(p_obj->init.cnt2.intrxwe)); + assert_param(check_param_tx_fifo_int(p_obj->init.cnt2.inttxfe)); + assert_param(check_param_rx_fifo_int(p_obj->init.cnt2.intrxfe)); + assert_param(check_param_err_int(p_obj->init.cnt2.interr)); + assert_param(check_param_tx_dma_int(p_obj->init.cnt2.dmate)); + assert_param(check_param_rx_dma_int(p_obj->init.cnt2.dmare)); + /* Check the parameter of TTSPIxBR */ + assert_param(check_param_input_clock(p_obj->init.brd.brck)); + assert_param(check_param_input_divider(p_obj->init.brd.brs)); + /* Check the parameter of TTSPIxFMTR0 */ + assert_param(check_param_data_direction(p_obj->init.fmr0.dir)); + assert_param(check_param_frame_length(p_obj->init.fmr0.fl)); + assert_param(check_param_frame_interval(p_obj->init.fmr0.fint)); + assert_param(check_param_tspixcs3_imp(p_obj->init.fmr0.cs3pol)); + assert_param(check_param_tspixcs2_imp(p_obj->init.fmr0.cs2pol)); + assert_param(check_param_tspixcs1_imp(p_obj->init.fmr0.cs1pol)); + assert_param(check_param_tspixcs0_imp(p_obj->init.fmr0.cs0pol)); + assert_param(check_param_clock_edge_imp(p_obj->init.fmr0.ckpha)); + assert_param(check_param_clock_idle_imp(p_obj->init.fmr0.ckpol)); + assert_param(check_param_min_idle_time(p_obj->init.fmr0.csint)); + assert_param(check_param_clock_delay(p_obj->init.fmr0.cssckdl)); + assert_param(check_param_negate_delay(p_obj->init.fmr0.sckcsdl)); + /* Check the parameter of TTSPIxFMTR1 */ + assert_param(check_param_parity_enable(p_obj->init.fmr1.vpe)); + assert_param(check_param_parity_bit(p_obj->init.fmr1.vpm)); +#endif + + + /* TSPI Software Reset */ + p_obj->p_instance->CR0 = (TSPI_RESET10 | TSPI_ENABLE); + p_obj->p_instance->CR0 = (TSPI_RESET01 | TSPI_ENABLE); + + /* Wait for 2 clocks of reset completion */ + __NOP(); + __NOP(); + + /* Control1 Register1 Set*/ + p_obj->p_instance->CR1 = 0x00001C01U; + p_obj->p_instance->CR1 = (p_obj->init.cnt1.cssel | p_obj->init.cnt1.fc | p_obj->init.cnt1.mstr | p_obj->init.cnt1.tmmd | \ + p_obj->init.cnt1.trxe | p_obj->init.cnt1.tspims| p_obj->init.cnt1.trgen); + /* Control2 Register Set */ + p_obj->p_instance->CR2 = 0x00E10100U; + p_obj->p_instance->CR2 = (p_obj->init.cnt2.tidle | p_obj->init.cnt2.txdemp | p_obj->init.cnt2.rxdly | p_obj->init.cnt2.til | \ + p_obj->init.cnt2.ril | p_obj->init.cnt2.inttxfe | p_obj->init.cnt2.intrxfe |p_obj->init.cnt2.inttxwe | \ + p_obj->init.cnt2.intrxwe | p_obj->init.cnt2.interr | p_obj->init.cnt2.dmate | p_obj->init.cnt2.dmare ); + + /* Control3 Register is FIFO clear, do nothing */ + + /* Baudrate Register Set */ + p_obj->p_instance->BR = 0U; + p_obj->p_instance->BR = (p_obj->init.brd.brck | p_obj->init.brd.brs); + + /* Format control0 Register Set */ + p_obj->p_instance->FMTR0 = 0x8800C400U; + p_obj->p_instance->FMTR0 = (p_obj->init.fmr0.ckpha | p_obj->init.fmr0.ckpol | p_obj->init.fmr0.cs0pol | p_obj->init.fmr0.cs1pol | \ + p_obj->init.fmr0.cs2pol | p_obj->init.fmr0.cs3pol | p_obj->init.fmr0.csint | p_obj->init.fmr0.cssckdl | \ + p_obj->init.fmr0.dir | p_obj->init.fmr0.fint | p_obj->init.fmr0.fl | p_obj->init.fmr0.sckcsdl ); + + /* Format control1 Register Set*/ + p_obj->p_instance->FMTR1 = 0U; + p_obj->p_instance->FMTR1 = (p_obj->init.fmr1.vpm | p_obj->init.fmr1.vpe); + + /* not created */ + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Release the TSPI object. + * @param p_obj :TSPI object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, "Failure" is returned. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result tspi_deinit(tspi_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + /* Check the parameters */ +#ifdef DEBUG + /* Check the NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif + + /* Disable the selected TSPI peripheral */ + p_obj->p_instance->CR0 |= TSPI_DISABLE; + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Transmit data.. + * @param p_obj :TSPI object. + * @param p_info :The information of transmit data. + * @param timeout :Timeout duration. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, "Failure" is returned. + * @note When p_info is NULL, "Failure" is returned. + */ +/*--------------------------------------------------*/ +TXZ_Result tspi_master_write(tspi_t *p_obj, tspi_transmit_t *p_info, uint32_t timeout) +{ + TXZ_Result result = TXZ_SUCCESS; + uint32_t err=0; + uint32_t length = 0; + + /* Check the parameters */ +#ifdef DEBUG + /* Check the NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif + + p_obj->errcode = NOERROR; + + /* Check the Transfer Mode setting */ + if((p_obj->p_instance->CR1 & TSPI_Transfer_Mode_MASK) == TSPI_RX_ONLY) { + p_obj->errcode = TRANSMITMODEERR; + result = TXZ_ERROR; + return (result); + } + + /* Transmit data check*/ + if((p_info->tx8.p_data == TSPI_NULL ) || (p_info->tx8.num == 0)) + { + p_obj->errcode = DATABUFEMPERR; + result = TXZ_ERROR; + return (result); + } + + /* FIFO Cear */ + p_obj->p_instance->CR3 |= TSPI_TX_BUFF_CLR_DONE; + /* Check the Frame length setting */ + length = ((p_obj->p_instance->FMTR0 & TSPI_DATA_LENGTH_MASK) >> 24); + /* Blocking Communication support frame length 8bit (1 byte) only */ + if (length == (TSPI_DATA_LENGTH_8 >> 24)) { + p_obj->transmit.tx_allign = TSPI_DATA_ALLIGN_8; + }else{ + p_obj->errcode = DATALENGTHERR; + result = TXZ_ERROR; + return (result); + } + /* Check if the TSPI is already enabled */ + if((p_obj->p_instance->CR0 & TSPI_ENABLE) != TSPI_ENABLE) + { + p_obj->p_instance->CR0 |= TSPI_ENABLE; + } + + /* Enable TSPI Transmission Control */ + p_obj->p_instance->CR1 |= TSPI_TRXE_ENABLE; + /* Transmit Data write to D ata Register */ + while (p_info->tx8.num > 0) + { + /* Check the current fill level */ + if(((p_obj->p_instance->SR & TSPI_TX_REACH_FILL_LEVEL_MASK) >> 16) <= 7) + { + *((__IO uint8_t*)&p_obj->p_instance->DR) = ((*p_info->tx8.p_data++) & (uint8_t)TSPI_DR_8BIT_MASK); + p_info->tx8.num--; + /* check complete transmit */ + if((p_obj->p_instance->SR & TSPI_TX_DONE_FLAG) != TSPI_TX_DONE) + { + timeout--; + if(timeout == 0) { + p_obj->errcode = TIMEOUTERR; + result = TXZ_ERROR; + return (result); + } + } + else + { + /* Enable TSPI Transmission Control */ + if(p_info->tx8.num==0){ + p_obj->p_instance->CR3 |= TSPI_TX_BUFF_CLR_DONE; + return (result); + } + else { + /* Next transmit data sending */ + p_obj->p_instance->SR |= TSPI_TX_DONE_CLR; + p_obj->p_instance->CR1 |= TSPI_TRXE_ENABLE; + } + + } + }else{ + p_obj->errcode = FIFOFULLERR; + timeout--; + if(timeout == 0) { + p_obj->errcode = TIMEOUTERR; + result = TXZ_ERROR; + return (result); + } + } + + } + /* check complete transmit */ + while((p_obj->p_instance->SR & TSPI_TX_DONE_FLAG) != TSPI_TX_DONE) + { + timeout--; + if(timeout == 0) { + p_obj->errcode = TIMEOUTERR; + result = TXZ_ERROR; + return (result); + } + } + /* Check Error Flag */ + tspi_get_error(p_obj, &err); + if(((err) & TSPI_UNDERRUN_ERR)== TSPI_UNDERRUN_ERR) {p_obj->errcode = UNDERRUNERR;} + else if(((err) & TSPI_OVERRUN_ERR) == TSPI_OVERRUN_ERR) {p_obj->errcode = OVERRUNERR;} + else if(((err) & TSPI_PARITY_ERR) == TSPI_PARITY_ERR) {p_obj->errcode = PARITYERR;} + + if(p_obj->errcode == NOERROR) { + //p_obj->p_instance->SR |= TSPI_TX_DONE_CLR; + p_obj->p_instance->CR3 |= TSPI_TX_BUFF_CLR_DONE; + p_obj->p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK; + return (result); + }else{ + result = TXZ_ERROR; + return (result); + } +} + +/*--------------------------------------------------*/ +/** + * @brief Receive data. Blocking Communication. + * @param p_obj :TSPI object. + * @param p_info :The information of receive buffer. + * @param timeout :Timeout duration. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, "Failure" is returned. + * @note When p_info is NULL, "Failure" is returned. + */ +/*--------------------------------------------------*/ +TXZ_Result tspi_master_read(tspi_t *p_obj, tspi_receive_t *p_info, uint32_t timeout) +{ + TXZ_Result result = TXZ_SUCCESS; + uint32_t err=0; + uint32_t length = 0; + uint32_t count = 0; + uint32_t index = 0; +// uint32_t level = 0; + + /* Check the parameters */ +#ifdef DEBUG + /* Check the NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif + + p_obj->errcode = NOERROR; + + /* Check the Transfer Mode setting */ + if((p_obj->p_instance->CR1 & TSPI_Transfer_Mode_MASK) == TSPI_TX_ONLY) { + p_obj->errcode = TRANSMITMODEERR; + result = TXZ_ERROR; + return (result); + } + if((p_obj->p_instance->CR1 & TSPI_Transfer_Mode_MASK) == TSPI_RX_ONLY) { + /* Enable TSPI Transmission Control */ + p_obj->p_instance->CR1 |= TSPI_TRXE_ENABLE; + } + + /* Transmit data check*/ + if((p_info->rx8.p_data == TSPI_NULL ) || (p_info->rx8.num == 0)) + { + result = TXZ_ERROR; + return (result); + } + count = p_info->rx8.num; + + /* Check the Frame length setting */ + length = ((p_obj->p_instance->FMTR0 & TSPI_DATA_LENGTH_MASK) >> 24U); + /* Blocking Communication support frame length 8bit (1 byte) only */ + if (length == (TSPI_DATA_LENGTH_8 >> 24)) { + p_obj->receive.rx_allign = TSPI_DATA_ALLIGN_8; + }else{ + p_obj->errcode = DATALENGTHERR; + result = TXZ_ERROR; + return (result); + } + + /* Check if the TSPI is already enabled */ + if((p_obj->p_instance->CR0 & TSPI_ENABLE) != TSPI_ENABLE) + { + /* Enable TSPI Transmission Control */ + p_obj->p_instance->CR0 |= TSPI_ENABLE; + } + + while (timeout > 0) + { + /* Wait until Receive Complete Flag is set to receive data */ + if((p_obj->p_instance->SR & TSPI_RX_DONE_FLAG) == TSPI_RX_DONE) + { + while (count > 0) { + /* Check the remain data exist */ + if((p_obj->p_instance->SR & TSPI_RX_REACH_FILL_LEVEL_MASK) != 0){ + p_info->rx8.p_data[index] = (*((__IO uint8_t*)&p_obj->p_instance->DR) & (uint8_t)TSPI_DR_8BIT_MASK); + count--; + index++; + }else{ + p_obj->errcode = FIFOFULLERR; + timeout--; + if(timeout == 0) { + p_obj->errcode = TIMEOUTERR; + result = TXZ_ERROR; + return (result); + } + } + } + /* Receive Complete Flag is clear */ + p_obj->p_instance->SR |= TSPI_RX_DONE_CLR; + /* FIFO Cear */ + p_obj->p_instance->CR2 |= TSPI_RX_BUFF_CLR_DONE; + p_obj->p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK; + return (result); + } + else {timeout--;} + } + /* Timeout management */ + p_obj->errcode = TIMEOUTERR; + + /* Check Error Flag set */ + tspi_get_error(p_obj, &err); + if(((err) & TSPI_UNDERRUN_ERR)== TSPI_UNDERRUN_ERR) {p_obj->errcode = UNDERRUNERR;} + else if(((err) & TSPI_OVERRUN_ERR) == TSPI_OVERRUN_ERR) {p_obj->errcode = OVERRUNERR;} + else if(((err) & TSPI_PARITY_ERR) == TSPI_PARITY_ERR) {p_obj->errcode = PARITYERR;} + + result = TXZ_ERROR; + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Transmit data. Non-Blocking Communication. + * @param p_obj :TSPI object. + * @param p_info :The information of transmit data. + * @retval SUCCESS :Success. + * @retval FAILURE :Failure. + * @note Asynchronous Processing. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result tspi_master_transfer(tspi_t *p_obj, tspi_transmit_t *p_info) +{ + TXZ_Result result = TXZ_SUCCESS; + uint32_t length = 0; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + /* Check the TSPI_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); + assert_param(IS_POINTER_NOT_NULL(p_info)); + /* Check the parameter of transmit. */ + if(p_obj->init.fmr0.fl == TSPI_DATA_LENGTH_8) + { + /* 8 bit */ + assert_param(IS_POINTER_NOT_NULL(p_info->tx8.p_data)); + } + else if ((p_obj->init.fmr0.fl > TSPI_DATA_LENGTH_8) && (p_obj->init.fmr0.fl < TSPI_DATA_LENGTH_17) ) + { + /* 9 - 16 bit */ + assert_param(IS_POINTER_NOT_NULL(p_info->tx16.p_data)); + } + else + { + /* 17 - 32 bit */ + assert_param(IS_POINTER_NOT_NULL(p_info->tx32.p_data)); + } +#endif /* #ifdef DEBUG */ + /*------------------------------*/ + /* Disable Transmit */ + /*------------------------------*/ + /*--- TSPIxTRANS ---*/ + /* Write to TRXE(=0). */ + p_obj->p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK; + p_obj->p_instance->SR |= TSPI_TX_DONE_CLR; + p_obj->p_instance->CR3 |= TSPI_TX_BUFF_CLR_DONE; + /*------------------------------*/ + /* Information Setting */ + /*------------------------------*/ + p_obj->transmit.rp = 0; + length = ((p_obj->p_instance->FMTR0 & TSPI_DATA_LENGTH_MASK) >> 24U); + if(length == DATA_LENGTH_8) + { + /* 8 bit */ + p_obj->transmit.info.tx8.p_data = p_info->tx8.p_data; + p_obj->transmit.info.tx8.num = p_info->tx8.num; + p_obj->transmit.tx_allign = 8; + } + else if ((length > DATA_LENGTH_8) && (length < DATA_LENGTH_17) ) + { + /* 9 - 16 bit */ + p_obj->transmit.info.tx16.p_data = p_info->tx16.p_data; + p_obj->transmit.info.tx16.num = p_info->tx16.num; + p_obj->transmit.tx_allign = 16; + } + else + { + /* 17 - 32 bit */ + p_obj->transmit.info.tx32.p_data = p_info->tx32.p_data; + p_obj->transmit.info.tx32.num = p_info->tx32.num; + p_obj->transmit.tx_allign = 32; + } + /*------------------------------*/ + /* Data Setting */ + /*------------------------------*/ + { + /* transmit data length set */ + + /*--- TSPIxSR ---*/ + /* Read FIFO fill level. */ + /* Read current TLVL. */ + __IO uint32_t tlvl = (p_obj->p_instance->SR & TSPI_TX_REACH_FILL_LEVEL_MASK); + tlvl >>= 8; + /* FIFO Max = TRANSFER_FIFO_MAX_NUM */ + if (tlvl > TRANSFER_FIFO_MAX_NUM) + { + tlvl = TRANSFER_FIFO_MAX_NUM; + } + /* Empty FIFO Num */ + { + __IO uint32_t work = tlvl; + tlvl = (TRANSFER_FIFO_MAX_NUM - work); + } + /*--- TSPIxDR ---*/ + /* Only the empty number of FIFO is a transmission data set. */ + { + uint32_t i = 0; + TXZ_WorkState loopBreak = TXZ_BUSY; + /* Set data to FIFO. */ + for (i=0; (i < tlvl) && (loopBreak == TXZ_BUSY); i++) + { + switch (p_obj->transmit.tx_allign) + { + case 8: + if (p_obj->transmit.info.tx8.num > p_obj->transmit.rp) + { + p_obj->p_instance->DR = ((uint32_t)*(p_obj->transmit.info.tx8.p_data + p_obj->transmit.rp) & (uint8_t)TSPI_DR_8BIT_MASK); + p_obj->transmit.rp += 1; + } + else + { + loopBreak = TXZ_DONE; + } + break; + case 16: + if (p_obj->transmit.info.tx16.num > p_obj->transmit.rp) + { + p_obj->p_instance->DR = ((uint32_t)*(p_obj->transmit.info.tx16.p_data + p_obj->transmit.rp) & mask[length]); + p_obj->transmit.rp += 1; + } + else + { + loopBreak = TXZ_DONE; + } + break; + case 32: + if (p_obj->transmit.info.tx32.num > p_obj->transmit.rp) + { + p_obj->p_instance->DR = ((uint32_t)*(p_obj->transmit.info.tx32.p_data + p_obj->transmit.rp) & mask[length]); + p_obj->transmit.rp += 1; + } + else + { + loopBreak = TXZ_DONE; + } + break; + default: + /* no process */ + break; + } + } + } + } + /*------------------------------*/ + /* Enable Transmit */ + /*------------------------------*/ + /*--- TSPIxTRANS ---*/ + /* Write to TRXE(=1). */ + /* Check if the TSPI is already enabled */ + if((p_obj->p_instance->CR0 & TSPI_ENABLE) != TSPI_ENABLE) + { + p_obj->p_instance->CR0 |= TSPI_ENABLE; + } + + /* Enable TSPI Transmission Control */ + p_obj->p_instance->CR1 |= TSPI_TRXE_ENABLE; + return (result); +} + + + +/*--------------------------------------------------*/ +/** + * @brief Receive data. Non-Blocking Communication. + * @param p_obj :TSPI object. + * @param p_info :The information of receive buffer. + * @retval SUCCESS :Success. + * @retval FAILURE :Failure. + * @note Asynchronous Processing. + * @attention "p_info->rx8(or rx16).num" must be over FIFO max(Refer @ref TSPI_TxReachFillLevel) num. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result tspi_master_receive(tspi_t *p_obj, tspi_receive_t *p_info) +{ + TXZ_Result result = TXZ_SUCCESS; + uint32_t length = 0; + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + /* Check the TSPI_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); + assert_param(IS_POINTER_NOT_NULL(p_info)); + /* Check the parameter of transmit. */ + if(p_obj->init.fmr0.fl == TSPI_DATA_LENGTH_8) + { + /* 8 bit */ + assert_param(IS_POINTER_NOT_NULL(p_info->rx8.p_data)); + } + else if ((p_obj->init.fmr0.fl > TSPI_DATA_LENGTH_8) && (p_obj->init.fmr0.fl < TSPI_DATA_LENGTH_17) ) + { + /* 9 - 16 bit */ + assert_param(IS_POINTER_NOT_NULL(p_info->rx16.p_data)); + } + else + { + /* 17 - 32 bit */ + assert_param(IS_POINTER_NOT_NULL(p_info->rx32.p_data)); + } +#endif /* #ifdef DEBUG */ + /*------------------------------*/ + /* Disable Receive */ + /*------------------------------*/ + /*--- TSPIxTRANS ---*/ + /* Write to TRXE(=0). */ + //p_obj->p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK; + /*------------------------------*/ + /* Information Setting */ + /*------------------------------*/ + length = ((p_obj->p_instance->FMTR0 & TSPI_DATA_LENGTH_MASK) >> 24U); + if(length == DATA_LENGTH_8) + { + /* 8 bit */ + p_obj->receive.info.rx8.p_data = p_info->rx8.p_data; + p_obj->receive.info.rx8.num = p_info->rx8.num; + p_obj->receive.rx_allign = 8; + + } + else if ((length > DATA_LENGTH_8) && (length < DATA_LENGTH_17) ) + { + /* 9 - 16 bit */ + p_obj->receive.info.rx16.p_data = p_info->rx16.p_data; + p_obj->receive.info.rx16.num = p_info->rx16.num; + p_obj->receive.rx_allign = 16; + } + else + { + /* 17 - 32 bit */ + p_obj->receive.info.rx32.p_data = p_info->rx32.p_data; + p_obj->receive.info.rx32.num = p_info->rx32.num; + p_obj->receive.rx_allign = 32; + } + /*------------------------------*/ + /* Enable Receive */ + /*------------------------------*/ + /*--- TSPIxTRANS ---*/ + /* Write to TRXE(=1). */ + /* Check if the TSPI is already enabled */ + if((p_obj->p_instance->CR0 & TSPI_ENABLE) != TSPI_ENABLE) + { + p_obj->p_instance->CR0 |= TSPI_ENABLE; + } + + /* Enable TSPI Transmission Control */ + p_obj->p_instance->CR1 |= TSPI_TRXE_ENABLE; + + return (result); +} +/*--------------------------------------------------*/ +/** + * @brief IRQ Handler for transmit. + * @param p_obj :TSPI object. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +void tspi_irq_handler_transmit(tspi_t *p_obj) +{ + __IO uint32_t status; + + uint32_t length; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + /* Check the TSPI_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef DEBUG */ + /*------------------------------*/ + /* Status Registar Control */ + /*------------------------------*/ + /* Read current TSPIxSR. */ + status = p_obj->p_instance->SR; + /* Clear the transmit's end flag. */ + /* Write to TXEND(=1), and TXFF(=1). */ + //p_obj->p_instance->SR = (TSPI_TX_DONE_CLR | TSPI_TX_FIFO_INT_CLR); + /*------------------------------*/ + /* Data length setting */ + /*------------------------------*/ + length = ((p_obj->p_instance->FMTR0 & TSPI_DATA_LENGTH_MASK) >> 24U); + /*------------------------------*/ + /* Transmit Status Check */ + /*------------------------------*/ + /* Check the transmit's end flag. */ + if (((status & TSPI_TX_DONE_FLAG ) == TSPI_TX_DONE) || + ((status & TSPI_TX_REACH_FILL_LEVEL_MASK) == p_obj->init.cnt2.til)) + { + TXZ_WorkState txDone = TXZ_BUSY; + /* Read FIFO fill level. */ + __IO uint32_t tlvl = (status & TSPI_TX_REACH_FILL_LEVEL_MASK); + tlvl >>= 8; + /* FIFO Max = TRANSFER_FIFO_MAX_NUM */ + if (tlvl > TRANSFER_FIFO_MAX_NUM) + { + tlvl = TRANSFER_FIFO_MAX_NUM; + } + /* Get the empty num in FIFO. */ + { + __IO uint32_t work = tlvl; + tlvl = (TRANSFER_FIFO_MAX_NUM - work); + } + if (tlvl == TRANSFER_FIFO_MAX_NUM) + { + if(length == DATA_LENGTH_8) + { + /* 8 bit */ + p_obj->transmit.tx_allign = 8; + if (p_obj->transmit.info.tx8.num <= p_obj->transmit.rp) + { + txDone = TXZ_DONE; + } + } + else if ((length > DATA_LENGTH_8) && (length < DATA_LENGTH_17) ) + { + /* 9 - 16 bit */ + p_obj->transmit.tx_allign = 16; + if (p_obj->transmit.info.tx16.num <= p_obj->transmit.rp) + { + txDone = TXZ_DONE; + } + } + else + { + /* 17 - 32 bit */ + p_obj->transmit.tx_allign = 32; + if (p_obj->transmit.info.tx32.num <= p_obj->transmit.rp) + { + txDone = TXZ_DONE; + } + } + } + if (txDone == TXZ_DONE) + { + /*=== Transmit Done!! ===*/ + /*--- TSPIxTRANS ---*/ + /* Write to TRXE(=0). */ + p_obj->p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK; + /*------------------------------*/ + /* Call Handler */ + /*------------------------------*/ + if (p_obj->transmit.handler != TSPI_NULL) + { + /* Call the transmit handler with SUCCESS. */ + p_obj->transmit.handler(p_obj->init.id, TXZ_SUCCESS); + } + } + else + { + /*=== Transmit Continue ===*/ + /*------------------------------*/ + /* Data Setting */ + /*------------------------------*/ + /* Only the empty number of FIFO is a transmission data set. */ + uint32_t i = 0; + TXZ_WorkState loopBreak = TXZ_BUSY; + /* Set data to FIFO. */ + for (i=0; (i < tlvl) && (loopBreak == TXZ_BUSY); i++) + { + switch (p_obj->transmit.tx_allign) + { + case 8: + if (p_obj->transmit.info.tx8.num > p_obj->transmit.rp) + { + p_obj->p_instance->DR = ((uint32_t)*(p_obj->transmit.info.tx8.p_data + p_obj->transmit.rp) & (uint8_t)TSPI_DR_8BIT_MASK); + p_obj->transmit.rp += 1; + } + else + { + loopBreak = TXZ_DONE; + } + break; + case 16: + if (p_obj->transmit.info.tx16.num > p_obj->transmit.rp) + { + p_obj->p_instance->DR = ((uint32_t)*(p_obj->transmit.info.tx16.p_data + p_obj->transmit.rp) & mask[length]); + p_obj->transmit.rp += 1; + } + else + { + loopBreak = TXZ_DONE; + } + break; + case 32: + if (p_obj->transmit.info.tx32.num > p_obj->transmit.rp) + { + p_obj->p_instance->DR = ((uint32_t)*(p_obj->transmit.info.tx32.p_data + p_obj->transmit.rp) & mask[length]); + p_obj->transmit.rp += 1; + } + else + { + loopBreak = TXZ_DONE; + } + break; + default: + /* no process */ + break; + } + } + #if 0 + /*------------------------------*/ + /* Enable Transmit */ + /*------------------------------*/ + /*--- TSPIxTRANS ---*/ + /* Write to TRXE(=1). */ + /* Check if the TSPI is already enabled */ + if((p_obj->p_instance->CR0 & TSPI_ENABLE) != TSPI_ENABLE) + { + p_obj->p_instance->CR0 |= TSPI_ENABLE; + } + + /* Enable TSPI Transmission Control */ + p_obj->p_instance->CR1 |= TSPI_TRXE_ENABLE; + #endif + } + } +} +/*--------------------------------------------------*/ +/** + * @brief IRQ Handler for receive. + * @param p_obj :TSPI object. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +void tspi_irq_handler_receive(tspi_t *p_obj) +{ + __IO uint32_t status; + + uint32_t length = 0; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + /* Check the TSPI_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef DEBUG */ + + /*------------------------------*/ + /* Status Registar Control */ + /*------------------------------*/ + /* Read current TSPIxSR. */ + status = p_obj->p_instance->SR; + /* Clear the transmit's end flag. */ + /* Write to RXEND(=1), and RXFF(=1). */ + //p_obj->p_instance->SR = (TSPI_RX_DONE_CLR | TSPI_RX_FIFO_INT_CLR); + /*------------------------------*/ + /* Data length setting */ + /*------------------------------*/ + length = ((p_obj->p_instance->FMTR0 & TSPI_DATA_LENGTH_MASK) >> 24); + if(length == DATA_LENGTH_8) + { + /* 8 bit */ + p_obj->receive.rx_allign = 8; + } + else if ((length > DATA_LENGTH_8) && (length < DATA_LENGTH_17) ) + { + /* 9 - 16 bit */ + p_obj->receive.rx_allign = 16; + } + else + { + /* 17 - 32 bit */ + p_obj->receive.rx_allign = 32; + } + /*------------------------------*/ + /* Receive Status Check */ + /*------------------------------*/ + /* Check the receive's end flag. */ + if (((status & TSPI_RX_DONE_FLAG ) == TSPI_RX_DONE) || + ((status & TSPI_RX_REACH_FILL_LEVEL_MASK) == p_obj->init.cnt2.ril)) + { + /* Read FIFO fill level. */ + __IO uint32_t rlvl = (status & TSPI_RX_REACH_FILL_LEVEL_MASK); + //__IO uint32_t rlvl = 7; + /* FIFO Max = RECEIVE_FIFO_MAX_NUM */ + if (rlvl > RECEIVE_FIFO_MAX_NUM) + { + rlvl = RECEIVE_FIFO_MAX_NUM; + } + /*------------------------------*/ + /* Data Read */ + /*------------------------------*/ + /* Read FIFO data. */ + if (rlvl != 0) + { + uint32_t i; + for (i=0; ireceive.rx_allign) + { + case 8: + *(p_obj->receive.info.rx8.p_data + i) = (uint8_t)(p_obj->p_instance->DR & (uint8_t)TSPI_DR_8BIT_MASK); + break; + case 16: + *(p_obj->receive.info.rx16.p_data + i) = (uint8_t)(p_obj->p_instance->DR & mask[length]); + break; + case 32: + *(p_obj->receive.info.rx32.p_data + i) = (uint8_t)(p_obj->p_instance->DR & mask[length]); + break; + default: + /* no process */ + break; + } + } + /*------------------------------*/ + /* Call Handler */ + /*------------------------------*/ + if (p_obj->receive.handler != TSPI_NULL) + { + tspi_receive_t param; + + switch (p_obj->receive.rx_allign) + { + case 8: + param.rx8.p_data = p_obj->receive.info.rx8.p_data; + param.rx8.num = rlvl; + break; + case 16: + param.rx16.p_data = p_obj->receive.info.rx16.p_data; + param.rx16.num = rlvl; + break; + case 32: + param.rx32.p_data = p_obj->receive.info.rx32.p_data; + param.rx32.num = rlvl; + break; + default: + /* no process */ + break; + } + /* Call the receive handler with SUCCESS. */ + p_obj->receive.handler(p_obj->init.id, TXZ_SUCCESS, ¶m); + } + } + } +} + +/*--------------------------------------------------*/ +/** + * @brief IRQ Handler for error. + * @param p_obj :TSPI object. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +void tspi_error_irq_handler(tspi_t *p_obj) +{ + __IO uint32_t error; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + /* Check the TSPI_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef DEBUG */ + /*------------------------------*/ + /* Error Registar Control */ + /*------------------------------*/ + /* Read current TSPIxERR. */ + error = p_obj->p_instance->ERR; + /* Now, no clear the error flag. */ + /*------------------------------*/ + /* Error Check */ + /*------------------------------*/ + /*--- TSPIxERR ---*/ + /* Check the transmit error. */ + /* TRGERR */ + if ((error & TSPI_TRGERR_MASK) == TSPI_TRGERR_ERR) + { + /*------------------------------*/ + /* Disable Receive */ + /*------------------------------*/ + /*--- TSPIxTRANS ---*/ + /* Write to TRXE(=0). */ + p_obj->p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK; + /*------------------------------*/ + /* Call Handler */ + /*------------------------------*/ + if (p_obj->transmit.handler != TSPI_NULL) + { + /* Call the transmit handler with FAILURE. */ + p_obj->transmit.handler(p_obj->init.id, TXZ_ERROR); + } + } + /* Check the receive error. */ + { + TXZ_Result err = TXZ_SUCCESS; + /* UNDERERR */ + if ((error & TSPI_UNDERRUN_MASK) == TSPI_UNDERRUN_ERR) + { + err = TXZ_ERROR; + } + /* OVRERR */ + if ((error & TSPI_OVERRUN_MASK) == TSPI_OVERRUN_ERR) + { + err = TXZ_ERROR; + } + /* PERR */ + if ((error & TSPI_PARITY_MASK) == TSPI_PARITY_ERR) + { + err = TXZ_ERROR; + } + if (err == TXZ_ERROR) + { + /*------------------------------*/ + /* Receive Check */ + /*------------------------------*/ + /*------------------------------*/ + /* Disable Receive */ + /*------------------------------*/ + /*--- TSPIxTRANS ---*/ + /* Write to TRXE(=0). */ + p_obj->p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK; + /*------------------------------*/ + /* Call Handler */ + /*------------------------------*/ + if (p_obj->receive.handler != TSPI_NULL) + { + /* Call the receive handler with FAILURE. */ + p_obj->receive.handler(p_obj->init.id, TXZ_ERROR, TSPI_NULL); + } + } + } +} + + +/*--------------------------------------------------*/ +/** + * @brief Data Format setting + * @param p_obj :TSPI object. + * @retval - + * @note When p_obj is NULL, no processing. + */ +/*--------------------------------------------------*/ +TXZ_Result tspi_format(tspi_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + /* Check the parameters */ +#ifdef DEBUG + /* Check the NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + /* Check the parameter of TTSPIxFMTR0 */ + assert_param(check_param_data_direction(p_obj->init.fmr0.dir)); + assert_param(check_param_frame_length(p_obj->init.fmr0.fl)); + assert_param(check_param_frame_interval(p_obj->init.fmr0.fint)); + assert_param(check_param_tspixcs3_imp(p_obj->init.fmr0.cs3pol)); + assert_param(check_param_tspixcs2_imp(p_obj->init.fmr0.cs2pol)); + assert_param(check_param_tspixcs1_imp(p_obj->init.fmr0.cs1pol)); + assert_param(check_param_tspixcs0_imp(p_obj->init.fmr0.cs0pol)); + assert_param(check_param_clock_edge_imp(p_obj->init.fmr0.ckpha)); + assert_param(check_param_clock_idle_imp(p_obj->init.fmr0.ckpol)); + assert_param(check_param_min_idle_time(p_obj->init.fmr0.csint)); + assert_param(check_param_clock_delay(p_obj->init.fmr0.cssckdl)); + assert_param(check_param_negate_delay(p_obj->init.fmr0.sckcsdl)); + /* Check the parameter of TTSPIxFMTR1 */ + assert_param(check_param_parity_enable(p_obj->init.fmr1.vpe)); + assert_param(check_param_parity_bit(p_obj->init.fmr1.vpm)); +#endif + + + /* Format control1 Register Set*/ + p_obj->p_instance->FMTR1 = (p_obj->init.fmr1.vpm | p_obj->init.fmr1.vpe); + /* Format control0 Register Set */ + p_obj->p_instance->FMTR0 = (p_obj->init.fmr0.ckpha | p_obj->init.fmr0.ckpol | p_obj->init.fmr0.cs0pol | p_obj->init.fmr0.cs1pol | \ + p_obj->init.fmr0.cs2pol | p_obj->init.fmr0.cs3pol | p_obj->init.fmr0.csint | p_obj->init.fmr0.cssckdl | \ + p_obj->init.fmr0.dir | p_obj->init.fmr0.fint | p_obj->init.fmr0.fl | p_obj->init.fmr0.sckcsdl ); + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Get status. + * @details Status bits. + * | Bit | Bit Symbol | Function | + * | :--- | :--- | :--- | + * | 31 | SUE | Setting Enable Flag. Use @ref TSPI_Status_Setting_flag. | + * | 30-24 | - | - | + * | 23 | TXRUN | Transmitting State Flag. Use @ref TSPI_TxState. | + * | 22 | TXEND | Transmitting Done Flag. Use @ref TSPI_TxDone. | + * | 21 | INTTXWF | Transmitting FIFO Interrpt Flag. Use @ref TSPI_TxFIFOInterruptFlag. | + * | 20 | TFEMP | Transmitting FIFO Empty Flag. Use @ref TSPI_TxFIFOEmptyFlag. | + * | 19-16 | TLVL | Current Transmitting FIFO Level. @ref TSPI_TxReachFillLevel. | + * | 15-8 | - | - | + * | 7 | RXRUN | Receive State Flag. Use @ref TSPI_RxState. | + * | 6 | RXEND | Receive Done Flag. Use @ref TSPI_RxDone. | + * | 5 | INTRXFF | Receiving FIFO Interrpt Flag. Use @ref TSPI_RxFIFOInterruptFlag. | + * | 4 | RXFLL | Receiving FIFO Full Flag. Use @ref TSPI_RxFIFOFullFlag | + * | 3-0 | RLVL | Current Receive FIFO Level. Use @ref TSPI_RxFIFOFullFlag | + * + * @param p_obj :TSPI object. + * @param p_status :Save area for status. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, "Failure" is returned. + * @note When p_status is NULL, "Failure" is returned. + */ +/*--------------------------------------------------*/ +TXZ_Result tspi_get_status(tspi_t *p_obj, uint32_t *p_status) +{ + TXZ_Result result = TXZ_SUCCESS; + /* Check the parameters */ +#ifdef DEBUG + /* Check the NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif + + /* Return TSPI state */ + *p_status = p_obj->p_instance->SR; + if(p_status != TSPI_NULL){ return (result);} + else { + result = TXZ_ERROR; + return (result); + } +} + +/*--------------------------------------------------*/ +/** + * @brief Get error information. + * @details Error bits. + * | Bit | Bit Symbol | Function | + * | :--- | :--- | :--- | + * | 31-3 | - | - | + * | 2 | UDRERR | Overrun Error. Use @ref TSPI_UnderrunErr. | + * | 1 | OVRERR | Overrun Error. Use @ref TSPI_OverrunErr. | + * | 0 | PERR | Parity Error. Use @ref TSPI_ParityErr. | + * + * @param p_obj :TSPI object. + * @param p_error :Save area for error. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, "Failure" is returned. + * @note When p_error is NULL, "Failure" is returned. + */ +/*--------------------------------------------------*/ +TXZ_Result tspi_get_error(tspi_t *p_obj, uint32_t *p_error) +{ + TXZ_Result result = TXZ_SUCCESS; + /* Check the parameters */ +#ifdef DEBUG + /* Check the NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif + + /* Return TSPI ERROR */ + *p_error = p_obj->p_instance->ERR; + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Error information clear. + * @details Error bits. + * | Bit | Bit Symbol | Function | + * | :--- | :--- | :--- | + * | 31-3 | - | - | + * | 3 | TRGERR | Trigger Error. Use @ref TSPI_TRGErr. | + * | 2 | UDRERR | Overrun Error. Use @ref TSPI_UnderrunErr. | + * | 1 | OVRERR | Overrun Error. Use @ref TSPI_OverrunErr. | + * | 0 | PERR | Parity Error. Use @ref TSPI_ParityErr. | + * + * @param p_obj :TSPI object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, "Failure" is returned. + * @note When p_error is NULL, "Failure" is returned. + */ +/*--------------------------------------------------*/ +TXZ_Result tspi_error_clear(tspi_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + /* Check the parameters */ +#ifdef DEBUG + /* Check the NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif + p_obj->p_instance->ERR = (TSPI_TRGERR_ERR | TSPI_UNDERRUN_ERR | TSPI_OVERRUN_ERR | TSPI_PARITY_ERR); + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Discard transmit. + * @param p_obj :TSPI object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note This function clears transmit's fifo, end flag and error info. + * @attention This function is not available in interrupt. + * @attention Use after interrupt is disabled. + */ +/*--------------------------------------------------*/ +TXZ_Result tspi_discard_transmit(tspi_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + /* Check the TSPI_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef DEBUG */ + /*------------------------------*/ + /* Disable Transfer */ + /*------------------------------*/ + /*--- TSPIxTRXE ---*/ + p_obj->p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK; + /*------------------------------*/ + /* Refresh Setting */ + /*------------------------------*/ + /*--- TSPIxSR ---*/ + /* Clear the transmit's end flag. */ + /* Write to TXEND(=1), and TXFF(=1). */ + p_obj->p_instance->SR = (TSPI_TX_DONE_CLR | TSPI_RX_DONE_CLR); + /*--- TSPIxFIFOCLR ---*/ + /* Clear the transmit's FIFO. */ + /* Write to TFCLR(=1). */ + p_obj->p_instance->CR3 = (TSPI_TX_BUFF_CLR_DONE | TSPI_RX_BUFF_CLR_DONE); + /*--- TSPIxERR ---*/ + /* Clear the trigger error flag. */ + /* Write to TRGERR(=1). */ + p_obj->p_instance->ERR = (TSPI_TRGERR_ERR ); + /*------------------------------*/ + /* Enable Transmit */ + /*------------------------------*/ + /*--- TSPIxTRANS ---*/ + /* Write to TRXE(=1). */ + /* Check if the TSPI is already enabled */ + if((p_obj->p_instance->CR0 & TSPI_ENABLE) != TSPI_ENABLE) + { + p_obj->p_instance->CR0 |= TSPI_ENABLE; + } + + /* Enable TSPI Transmission Control */ + p_obj->p_instance->CR1 |= TSPI_TRXE_ENABLE; + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Discard receive. + * @param p_obj :TSPI object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note This function clears receive's fifo, end flag and error info. + * @attention This function is not available in interrupt. + * @attention Use after interrupt is disabled. + */ +/*--------------------------------------------------*/ +TXZ_Result tspi_discard_receive(tspi_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + /* Check the TSPI_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef DEBUG */ + /*------------------------------*/ + /* Disable Transfer */ + /*------------------------------*/ + /*--- TSPIxTRXE ---*/ + p_obj->p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK; + /*------------------------------*/ + /* Refresh Setting */ + /*------------------------------*/ + /*------------------------------*/ + /* Refresh Setting */ + /*------------------------------*/ + /*--- TSPIxSR ---*/ + /* Clear the transmit's end flag. */ + /* Write to TXEND(=1), and TXFF(=1). */ + p_obj->p_instance->SR = (TSPI_TX_DONE_CLR | TSPI_RX_DONE_CLR); + /*--- TSPIxFIFOCLR ---*/ + /* Clear the transmit's FIFO. */ + /* Write to TFCLR(=1). */ + p_obj->p_instance->CR3 = (TSPI_TX_BUFF_CLR_DONE | TSPI_RX_BUFF_CLR_DONE); + /*--- TSPIxERR ---*/ + /* Clear the trigger error flag. */ + /* Write to TRGERR(=1), UDRERR(=1), and OVRERR(=1), PERR(=1) */ + p_obj->p_instance->ERR = (TSPI_TRGERR_ERR | TSPI_UNDERRUN_ERR |TSPI_OVERRUN_ERR | TSPI_PARITY_ERR ); + /*------------------------------*/ + /* Enable Transmit */ + /*------------------------------*/ + /*--- TSPIxTRANS ---*/ + /* Write to TRXE(=1). */ + /* Check if the TSPI is already enabled */ + if((p_obj->p_instance->CR0 & TSPI_ENABLE) != TSPI_ENABLE) + { + p_obj->p_instance->CR0 |= TSPI_ENABLE; + } + + /* Enable TSPI Transmission Control */ + p_obj->p_instance->CR1 |= TSPI_TRXE_ENABLE; + + return (result); +} + + +/** + * @} + */ /* End of group TSPI_Exported_functions */ + +/** + * @} + */ /* End of group TSPI */ + +/** + * @} + */ /* End of group Periph_Driver */ + +#endif /* defined(__TSPI_H) */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/periph_driver/txz_tspi.h b/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/periph_driver/txz_tspi.h new file mode 100644 index 00000000000..0a0e8bd13d8 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/periph_driver/txz_tspi.h @@ -0,0 +1,1320 @@ +/** + ******************************************************************************* + * @file txz_tspi.h + * @brief This file provides all the functions prototypes for TSPI driver. + * @version V1.0.0.7 + * $Date:: 2018-01-22 15:26:40 #$ + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LISENCE AGREEMENT. + * + * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved + ******************************************************************************* + */ +/*------------------------------------------------------------------------------*/ +/* Define to prevent recursive inclusion */ +/*------------------------------------------------------------------------------*/ +#ifndef __TSPI_H +#define __TSPI_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txz_driver_def.h" +/** + * @addtogroup Periph_Driver + * @{ + */ + +/** + * @defgroup TSPI TSPI + * @brief TSPI Driver. + * @{ + */ + + +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup TSPI_Exported_define TSPI Exported Define + * @{ + */ +/** + * @defgroup TSPI_NullPointer Null Pointer + * @brief Null Pointer. + * @{ + */ +#define TSPI_NULL ((void *)0) +/** + * @} + */ /* End of group TSPI_NullPointer */ + +/** + * @defgroup TSPI_ParameterResult Parameter Check Result + * @brief Whether the parameter is specified or not. + * @{ + */ +#define TSPI_PARAM_OK ((int32_t)1) /*!< Parameter is valid(specified). */ +#define TSPI_PARAM_NG ((int32_t)0) /*!< Parameter is invalid(not specified). */ +/** + * @} + */ /* End of group TSPI_ParameterResult */ + +/** + * @defgroup TSPI_Result Result + * @brief TSPI Result Macro Definition. + * @{ + */ +#define TSPI_RESULT_SUCCESS (0) /*!< Success */ +#define TSPI_RESULT_FAILURE (-1) /*!< Failure */ +/** + * @} + */ /* End of group TSPI_Result */ + +/** + * @defgroup TSPI_SW_Reset SW Reset + * @brief Software Rest Macro Definition. + * @{ + */ +#define TSPI_RESET10 ((uint32_t)0x00000080) /*!< RESET Pattarn 10 */ +#define TSPI_RESET01 ((uint32_t)0x00000040) /*!< RESET Pattarn 01 */ +/** + * @} + */ /* End of group TSPI_SW_Reset */ + + +/** + * @defgroup TSPI_Enable TSPI Enable/Disable Control + * @brief Enable/Disable TSPIE Macro Definition. + * @{ + */ +#define TSPI_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define TSPI_ENABLE ((uint32_t)0x00000001) /*!< Enable */ +/** + * @} + */ /* End of group TSPI_Enable */ + +/** + * @defgroup TSPI_Triger_Control Triger Control + * @brief Enable/Disable TRGEN Macro Definition. + * @{ + */ +#define TSPI_TRGEN_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define TSPI_TRGEN_ENABLE ((uint32_t)0x00008000) /*!< Enable */ +/** + * @} + */ /* End of group TSPI_Transmission_Control */ + +/** + * @defgroup TSPI_Transmission_Control Transmission Control + * @brief Enable/Disable TRXE Macro Definition. + * @{ + */ +#define TSPI_TRXE_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define TSPI_TRXE_ENABLE ((uint32_t)0x00004000) /*!< Enable */ +#define TSPI_TRXE_DISABLE_MASK ((uint32_t)0xFFFFBFFF) /*!< Disable MASK*/ +/** + * @} + */ /* End of group TSPI_Transmission_Control */ + +/** + * @defgroup TSPI_Transmission_Mode Transmission Mode + * @brief TSPIIMS Mode Macro Definisiton. + * @{ + */ +#define TSPI_SPI_MODE ((uint32_t)0x00000000) /*!< TSPI MODE */ +#define TSPI_SIO_MODE ((uint32_t)0x00002000) /*!< SIO MODE */ +/** + * @} + */ /* End of group TSPI_Transmission_Mode */ + + +/** + * @defgroup TSPI_Operation_Select Operation Select + * @brief Master/Slave MSTR Operation Macro Definisiton. + * @{ + */ +#define TSPI_MASTER_OPEARTION ((uint32_t)0x00001000) /*!< MASTER MODE */ +#define TSPI_SLAVE_OPERATION ((uint32_t)0x00000000) /*!< SLAVE MODE */ +/** + * @} + */ /* End of group TSPI_Operation_Select */ + + +/** + * @defgroup TSPI_Transfer_Mode Transfer Mode + * @brief Transfer Mode TMMD Macro Definisiton. + * @{ + */ +#define TSPI_TX_ONLY ((uint32_t)0x00000400) /*!< SEND ONLY */ +#define TSPI_RX_ONLY ((uint32_t)0x00000800) /*!< RECEIVE ONLY */ +#define TSPI_TWO_WAY ((uint32_t)0x00000C00) /*!< TWO WAY */ +#define TSPI_Transfer_Mode_MASK ((uint32_t)0x00000C00) /*!< Transfer Mode bit MASK */ +/** + * @} + */ /* End of group TSPI_Transfer_Mode */ + + +/** + * @defgroup TSPI_CSSEL_Select CSSEL Select + * @brief TSPIIxCS0/1/2/3 Select Macro Definisiton. + * @{ + */ +#define TSPI_TSPIxCS0_ENABLE ((uint32_t)0x00000000) /*!< TSPIIxCS0 */ +#define TSPI_TSPIxCS1_ENABLE ((uint32_t)0x00000100) /*!< TSPIIxCS1 */ +#define TSPI_TSPIxCS2_ENABLE ((uint32_t)0x00000200) /*!< TSPIIxCS2 */ +#define TSPI_TSPIxCS3_ENABLE ((uint32_t)0x00000300) /*!< TSPIIxCS3 */ +/** + * @} + */ /* End of group TSPI_CSSEL_Select */ + +/** + * @defgroup TSPI_Transfer_Frame_Range Transfer Frame Range + * @brief Transfer Frame Range Macro Definisiton. + * @{ + */ +#define TSPI_TRANS_RANGE_SINGLE ((uint32_t)0x00000000) /*!< Single Transfer Frame :0 */ +#define TSPI_TRANS_RANGE_MAX ((uint32_t)0x000000FF) /*!< Maximum Transfer Frame Value :=255 */ +/** + * @} + */ /* End of group TSPI_Transfer_Frame_Range */ +/** + * @defgroup TSPI_IDLE_Output_value IDLE Output Value + * @brief IDLE time Output Value TIDLE Macro Definisiton. + * @{ + */ +#define TSPI_TIDLE_Hiz ((uint32_t)0x00000000) /*!< Hi-z */ +#define TSPI_TIDLE_LAST_DATA ((uint32_t)0x00400000) /*!< Last DATA */ +#define TSPI_TIDLE_LOW ((uint32_t)0x00800000) /*!< Low */ +#define TSPI_TIDLE_HI ((uint32_t)0x00C00000) /*!< Hi */ +/** + * @} + */ /* End of group TSPI_IDLE_Output_value */ + +/** + * @defgroup TSPI_RXDLY_value RXDLY Value + * @brief IDLE time Output Value TIDLE Macro Definisiton. + * @{ + */ +#define TSPI_RXDLY_40MHz_OVER ((uint32_t)0x00010000) /*!< fsys > 40MHz */ +#define TSPI_RXDLY_40MHz_OR_LESS ((uint32_t)0x00000000) /*!< fsys <= 40MHz */ +/** + * @} + */ /* End of group TSPI_RXDLY_value*/ + + + /** + * @defgroup TSPI_Underrun_Output_value Underrun Occur Output Value + * @brief In case of Under Run Output Value TXDEMP Macro Definisiton. + * @{ + */ +#define TSPI_TXDEMP_LOW ((uint32_t)0x00000000) /*!< Low */ +#define TSPI_TXDEMP_HI ((uint32_t)0x00200000) /*!< Hi */ +/** + * @} + */ /* End of group TSPI_Underrun_Output_value */ + + +/** + * @defgroup TSPI_TxFillLevel Tx Fill Level + * @brief Transmit Fill Level Macro Definisiton. + * @{ + */ +#define TSPI_TX_FILL_LEVEL_0 ((uint32_t)0x00000000) /*!< 0 */ +#define TSPI_TX_FILL_LEVEL_1 ((uint32_t)0x00001000) /*!< 1 */ +#define TSPI_TX_FILL_LEVEL_2 ((uint32_t)0x00002000) /*!< 2 */ +#define TSPI_TX_FILL_LEVEL_3 ((uint32_t)0x00003000) /*!< 3 */ +#define TSPI_TX_FILL_LEVEL_4 ((uint32_t)0x00004000) /*!< 4 */ +#define TSPI_TX_FILL_LEVEL_5 ((uint32_t)0x00005000) /*!< 5 */ +#define TSPI_TX_FILL_LEVEL_6 ((uint32_t)0x00006000) /*!< 6 */ +#define TSPI_TX_FILL_LEVEL_7 ((uint32_t)0x00007000) /*!< 7 */ +#define TSPI_TX_FILL_LEVEL_MASK ((uint32_t)0x00007000) /*!< MASK */ +/*! + * @} + */ /* End of group TSPI_TxFillLevel */ + + +/** + * @defgroup TSPI_RxFillLevel Rx Fill Level + * @brief Receive Fill Level Macro Definisiton. + * @{ + */ +#define TSPI_RX_FILL_LEVEL_0 ((uint32_t)0x00000000) /*!< 8 */ +#define TSPI_RX_FILL_LEVEL_1 ((uint32_t)0x00000100) /*!< 1 */ +#define TSPI_RX_FILL_LEVEL_2 ((uint32_t)0x00000200) /*!< 2 */ +#define TSPI_RX_FILL_LEVEL_3 ((uint32_t)0x00000300) /*!< 3 */ +#define TSPI_RX_FILL_LEVEL_4 ((uint32_t)0x00000400) /*!< 4 */ +#define TSPI_RX_FILL_LEVEL_5 ((uint32_t)0x00000500) /*!< 5 */ +#define TSPI_RX_FILL_LEVEL_6 ((uint32_t)0x00000600) /*!< 6 */ +#define TSPI_RX_FILL_LEVEL_7 ((uint32_t)0x00000700) /*!< 7 */ +#define TSPI_RX_FILL_LEVEL_MASK ((uint32_t)0x00000700) /*!< MASK */ +/** + * @} + */ /* End of group TSPI_RxFillLevel */ + + +/** + * @defgroup TSPI_TxFIFOInterrupt Tx FIFO Interrpt + * @brief Enable/Disable Transmit FIFO Interrupt Macro Definisiton. + * @{ + */ +#define TSPI_TX_FIFO_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define TSPI_TX_FIFO_INT_ENABLE ((uint32_t)0x00000080) /*!< Enable */ +/** + * @} + */ /* End of group TSPI_TxFIFOInterrupt */ + + +/** + * @defgroup TSPI_TxInterrupt Tx Interrpt + * @brief Enable/Disable Transmit Interrupt Macro Definisiton. + * @{ + */ +#define TSPI_TX_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define TSPI_TX_INT_ENABLE ((uint32_t)0x00000040) /*!< Enable */ +/** + * @} + */ /* End of group TSPI_TxInterrupt */ + + +/** + * @defgroup TSPI_RxFIFOInterrupt Rx FIFO Interrpt + * @brief Enable/Disable Receive FIFO Interrupt Macro Definisiton. + * @{ + */ +#define TSPI_RX_FIFO_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define TSPI_RX_FIFO_INT_ENABLE ((uint32_t)0x00000020) /*!< Enable */ +/** + * @} + */ /* End of group TSPI_RxFIFOInterrupt */ + + +/** + * @defgroup TSPI_RxInterrupt Rx Interrpt + * @brief Enable/Disable Receive Interrupt Macro Definisiton. + * @{ + */ +#define TSPI_RX_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define TSPI_RX_INT_ENABLE ((uint32_t)0x00000010) /*!< Enable */ +/** + * @} + */ /* End of group TSPI_RxInterrupt */ + + +/** + * @defgroup TSPI_ErrorInterrupt Error Interrupt + * @brief Enable/Disable Error Interrupt Macro Definisiton. + * @{ + */ +#define TSPI_ERR_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define TSPI_ERR_INT_ENABLE ((uint32_t)0x00000004) /*!< Enable */ +/** + * @} + */ /* End of group TSPI_ErrorInterrupt */ + + +/** + * @defgroup TSPI_TxDMAInterrupt Tx DMA Interrupt + * @brief Enable/Disable Transmit DMA Interrupt Macro Definisiton. + * @{ + */ +#define TSPI_TX_DMA_INT_MASK ((uint32_t)0x00000002) /*!< Mask Data */ +#define TSPI_TX_DMA_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define TSPI_TX_DMA_INT_ENABLE ((uint32_t)0x00000002) /*!< Enable */ +/** + * @} + */ /* End of group TSPI_TxDMAInterrupt */ + + +/** + * @defgroup TSPI_RxDMAInterrupt Rx DMA Interrupt + * @brief Enable/Disable Receive DMA Interrupt Macro Definisiton. + * @{ + */ +#define TSPI_RX_DMA_INT_MASK ((uint32_t)0x00000001) /*!< Mask Data */ +#define TSPI_RX_DMA_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define TSPI_RX_DMA_INT_ENABLE ((uint32_t)0x00000001) /*!< Enable */ +/** + * @} + */ /* End of group TSPI_RxDMAInterrupt */ + + +/** + * @defgroup TSPI_Tx_Buffer_Clear Tx Buffer Clear + * @brief Tx Buffer Clear Macro Definisiton. + * @{ + */ +#define TSPI_TX_BUFF_CLR_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define TSPI_TX_BUFF_CLR_DONE ((uint32_t)0x00000002) /*!< Clear */ +/** + * @} + */ /* End of group TSPI_Tx_Buffer_Clear */ + + +/** + * @defgroup TSPI_Rx_Buffer_Clear Rx Buffer Clear + * @brief Rx Buffer Clear Macro Definisiton. + * @{ + */ +#define TSPI_RX_BUFF_CLR_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define TSPI_RX_BUFF_CLR_DONE ((uint32_t)0x00000001) /*!< Clear */ +/** + * @} + */ /* End of group TSPI_Rx_Buffer_Clear */ + + +/** + * @defgroup TSPI_Baudrate_Clock Baudrate Input Clock + * @brief Baudrate Input Clock Macro Definisiton. + * @{ + */ +#define TSPI_BR_CLOCK_0 ((uint32_t)0x00000000) /*!< T0 */ +#define TSPI_BR_CLOCK_1 ((uint32_t)0x00000010) /*!< T1 */ +#define TSPI_BR_CLOCK_2 ((uint32_t)0x00000020) /*!< T2 */ +#define TSPI_BR_CLOCK_4 ((uint32_t)0x00000030) /*!< T4 */ +#define TSPI_BR_CLOCK_8 ((uint32_t)0x00000040) /*!< T8 */ +#define TSPI_BR_CLOCK_16 ((uint32_t)0x00000050) /*!< T16 */ +#define TSPI_BR_CLOCK_32 ((uint32_t)0x00000060) /*!< T32 */ +#define TSPI_BR_CLOCK_64 ((uint32_t)0x00000070) /*!< T64 */ +#define TSPI_BR_CLOCK_128 ((uint32_t)0x00000080) /*!< T128 */ +#define TSPI_BR_CLOCK_256 ((uint32_t)0x00000090) /*!< T256 */ +/** + * @} + */ /* End of group TSPI_Baudrate_Clock */ + + +/** + * @defgroup TSPI_Baudrate_Divider Baudrate Divider + * @brief Baudrate IDivider Macro Definisiton. + * @{ + */ +#define TSPI_BR_DIVIDER_16 ((uint32_t)0x00000000) /*!< 1/16 */ +#define TSPI_BR_DIVIDER_1 ((uint32_t)0x00000001) /*!< 1/1 */ +#define TSPI_BR_DIVIDER_2 ((uint32_t)0x00000002) /*!< 1/2 */ +#define TSPI_BR_DIVIDER_3 ((uint32_t)0x00000003) /*!< 1/3 */ +#define TSPI_BR_DIVIDER_4 ((uint32_t)0x00000004) /*!< 1/4 */ +#define TSPI_BR_DIVIDER_5 ((uint32_t)0x00000005) /*!< 1/5 */ +#define TSPI_BR_DIVIDER_6 ((uint32_t)0x00000006) /*!< 1/6 */ +#define TSPI_BR_DIVIDER_7 ((uint32_t)0x00000007) /*!< 1/7 */ +#define TSPI_BR_DIVIDER_8 ((uint32_t)0x00000008) /*!< 1/8 */ +#define TSPI_BR_DIVIDER_9 ((uint32_t)0x00000009) /*!< 1/9 */ +#define TSPI_BR_DIVIDER_10 ((uint32_t)0x0000000a) /*!< 1/10 */ +#define TSPI_BR_DIVIDER_11 ((uint32_t)0x0000000b) /*!< 1/11 */ +#define TSPI_BR_DIVIDER_12 ((uint32_t)0x0000000c) /*!< 1/12 */ +#define TSPI_BR_DIVIDER_13 ((uint32_t)0x0000000d) /*!< 1/13 */ +#define TSPI_BR_DIVIDER_14 ((uint32_t)0x0000000e) /*!< 1/14 */ +#define TSPI_BR_DIVIDER_15 ((uint32_t)0x0000000f) /*!< 1/15 */ +/** + * @} + */ /* End of group TSPI_Baudrate_Divider */ + + +/** + * @defgroup TSPI_DataDirection Data Direction + * @brief Data Direction Macro Definisiton. + * @{ + */ +#define TSPI_DATA_DIRECTION_LSB ((uint32_t)0x00000000) /*!< LSB first */ +#define TSPI_DATA_DIRECTION_MSB ((uint32_t)0x80000000) /*!< MSB first */ +/*! + * @} + */ /* End of group TSPI_DataDirection */ + + +/** + * @defgroup TSPI_DataLength Data Length + * @brief Data Length Macro Definisiton. + * @{ + */ +#define TSPI_DATA_LENGTH_8 ((uint32_t)0x08000000) /*!< 8 bit */ +#define TSPI_DATA_LENGTH_9 ((uint32_t)0x09000000) /*!< 9 bit */ +#define TSPI_DATA_LENGTH_10 ((uint32_t)0x0a000000) /*!< 10 bit */ +#define TSPI_DATA_LENGTH_11 ((uint32_t)0x0b000000) /*!< 11 bit */ +#define TSPI_DATA_LENGTH_12 ((uint32_t)0x0c000000) /*!< 12 bit */ +#define TSPI_DATA_LENGTH_13 ((uint32_t)0x0d000000) /*!< 13 bit */ +#define TSPI_DATA_LENGTH_14 ((uint32_t)0x0e000000) /*!< 14 bit */ +#define TSPI_DATA_LENGTH_15 ((uint32_t)0x0f000000) /*!< 15 bit */ +#define TSPI_DATA_LENGTH_16 ((uint32_t)0x10000000) /*!< 16 bit */ +#define TSPI_DATA_LENGTH_17 ((uint32_t)0x11000000) /*!< 17 bit */ +#define TSPI_DATA_LENGTH_18 ((uint32_t)0x12000000) /*!< 18 bit */ +#define TSPI_DATA_LENGTH_19 ((uint32_t)0x13000000) /*!< 19 bit */ +#define TSPI_DATA_LENGTH_20 ((uint32_t)0x14000000) /*!< 20 bit */ +#define TSPI_DATA_LENGTH_21 ((uint32_t)0x15000000) /*!< 21 bit */ +#define TSPI_DATA_LENGTH_22 ((uint32_t)0x16000000) /*!< 22 bit */ +#define TSPI_DATA_LENGTH_23 ((uint32_t)0x17000000) /*!< 23 bit */ +#define TSPI_DATA_LENGTH_24 ((uint32_t)0x18000000) /*!< 24 bit */ +#define TSPI_DATA_LENGTH_25 ((uint32_t)0x19000000) /*!< 25 bit */ +#define TSPI_DATA_LENGTH_26 ((uint32_t)0x1a000000) /*!< 26 bit */ +#define TSPI_DATA_LENGTH_27 ((uint32_t)0x1b000000) /*!< 27 bit */ +#define TSPI_DATA_LENGTH_28 ((uint32_t)0x1c000000) /*!< 28 bit */ +#define TSPI_DATA_LENGTH_29 ((uint32_t)0x1d000000) /*!< 29 bit */ +#define TSPI_DATA_LENGTH_30 ((uint32_t)0x1e000000) /*!< 30 bit */ +#define TSPI_DATA_LENGTH_31 ((uint32_t)0x1f000000) /*!< 31 bit */ +#define TSPI_DATA_LENGTH_32 ((uint32_t)0x20000000) /*!< 32 bit */ +#define TSPI_DATA_LENGTH_MASK ((uint32_t)0x3F000000) /*!< 32 bit */ +/** + * @} + */ /* End of group TSPI_DataLength */ + + +/** + * @defgroup TSPI_Frame_Interval_Time Frame Interval time + * @brief Frame Interval time Macro Definisiton. + * @{ + */ +#define TSPI_INTERVAL_TIME_0 ((uint32_t)0x00000000) /*!< 0 */ +#define TSPI_INTERVAL_TIME_1 ((uint32_t)0x00100000) /*!< 1 x TSPIIxSCK */ +#define TSPI_INTERVAL_TIME_2 ((uint32_t)0x00200000) /*!< 2 x TSPIIxSCK */ +#define TSPI_INTERVAL_TIME_3 ((uint32_t)0x00300000) /*!< 3 x TSPIIxSCK */ +#define TSPI_INTERVAL_TIME_4 ((uint32_t)0x00400000) /*!< 4 x TSPIIxSCK */ +#define TSPI_INTERVAL_TIME_5 ((uint32_t)0x00500000) /*!< 5 x TSPIIxSCK */ +#define TSPI_INTERVAL_TIME_6 ((uint32_t)0x00600000) /*!< 6 x TSPIIxSCK */ +#define TSPI_INTERVAL_TIME_7 ((uint32_t)0x00700000) /*!< 7 x TSPIIxSCK */ +#define TSPI_INTERVAL_TIME_8 ((uint32_t)0x00800000) /*!< 8 x TSPIIxSCK */ +#define TSPI_INTERVAL_TIME_9 ((uint32_t)0x00900000) /*!< 9 x TSPIIxSCK */ +#define TSPI_INTERVAL_TIME_10 ((uint32_t)0x00a00000) /*!< 10 x TSPIIxSCK */ +#define TSPI_INTERVAL_TIME_11 ((uint32_t)0x00b00000) /*!< 11 x TSPIIxSCK */ +#define TSPI_INTERVAL_TIME_12 ((uint32_t)0x00c00000) /*!< 12 x TSPIIxSCK */ +#define TSPI_INTERVAL_TIME_13 ((uint32_t)0x00d00000) /*!< 13 x TSPIIxSCK */ +#define TSPI_INTERVAL_TIME_14 ((uint32_t)0x00e00000) /*!< 14 x TSPIIxSCK */ +#define TSPI_INTERVAL_TIME_15 ((uint32_t)0x00f00000) /*!< 15 x TSPIIxSCK */ +/** + * @} + */ /* End of group TSPI_Frame_Interval_Time */ + + +/** + * @defgroup TSPI_TSPIxCS3_Polarity TSPIxCS3 Polarity + * @brief TSPIxCS3 Polarity Macro Definisiton. + * @{ + */ +#define TSPI_TSPIxCS3_NEGATIVE ((uint32_t)0x00000000) /*!< negative logic */ +#define TSPI_TSPIxCS3_POSITIVE ((uint32_t)0x00080000) /*!< positive logic */ +/** + * @} + */ /* End of group TSPI_TSPIxCS3_Polarity */ + + +/** + * @defgroup TSPI_TSPIxCS2_Polarity TSPIxCS2 Polarity + * @brief TSPIxCS2 Polarity Macro Definisiton. + * @{ + */ +#define TSPI_TSPIxCS2_NEGATIVE ((uint32_t)0x00000000) /*!< negative logic */ +#define TSPI_TSPIxCS2_POSITIVE ((uint32_t)0x00040000) /*!< positive logic */ +/** + * @} + */ /* End of group TSPI_TSPIxCS2_Polarity */ + + +/** + * @defgroup TSPI_TSPIxCS1_Polarity TSPIxCS1 Polarity + * @brief TSPIxCS1 Polarity Macro Definisiton. + * @{ + */ +#define TSPI_TSPIxCS1_NEGATIVE ((uint32_t)0x00000000) /*!< negative logic */ +#define TSPI_TSPIxCS1_POSITIVE ((uint32_t)0x00020000) /*!< positive logic */ +/** + * @} + */ /* End of group TSPI_TSPIxCS1_Polarity */ + + +/** + * @defgroup TSPI_TSPIxCS0_Polarity TSPIxCS0 Polarity + * @brief TSPIxCS0 Polarity Macro Definisiton. + * @{ + */ +#define TSPI_TSPIxCS0_NEGATIVE ((uint32_t)0x00000000) /*!< negative logic */ +#define TSPI_TSPIxCS0_POSITIVE ((uint32_t)0x00010000) /*!< positive logic */ +/** + * @} + */ /* End of group TSPI_TSPIxCS0_Polarity */ + + +/** + * @defgroup TSPI_Serial_Clock_Polarity Serial Clock Polarity + * @brief Serial Clock Polarity Macro Definisiton. + * @{ + */ +#define TSPI_SERIAL_CK_1ST_EDGE ((uint32_t)0x00000000) /*!< 1st Edge Sampling */ +#define TSPI_SERIAL_CK_2ND_EDGE ((uint32_t)0x00008000) /*!< 2nd Edge Sampling */ +/** + * @} + */ /* End of group Serial Clock Polarity */ + + +/** + * @defgroup TSPI_Serial_Clock_IDLE_Polarity Serial Clock IDLE Polarity + * @brief Serial Clock IDLE Polarity Macro Definisiton. + * @{ + */ +#define TSPI_SERIAL_CK_IDLE_LOW ((uint32_t)0x00000000) /*!< IDLE Term TSPII??SCK LOW */ +#define TSPI_SERIAL_CK_IDLE_HI ((uint32_t)0x00004000) /*!< IDLE Term TSPII??SCK HI */ +/** + * @} + */ /* End of group TSPI_Serial_Clock_IDLE_Polarity */ + + +/** + * @defgroup TSPI_Minimum_IDLE_Time Minimum IDLE Time + * @brief Minimum IDLE Time Macro Definisiton. + * @{ + */ +#define TSPI_MIN_IDLE_TIME_1 ((uint32_t)0x00000400) /*!< 1 x TSPIIxSCK */ +#define TSPI_MIN_IDLE_TIME_2 ((uint32_t)0x00000800) /*!< 2 x TSPIIxSCK */ +#define TSPI_MIN_IDLE_TIME_3 ((uint32_t)0x00000c00) /*!< 3 x TSPIIxSCK */ +#define TSPI_MIN_IDLE_TIME_4 ((uint32_t)0x00001000) /*!< 4 x TSPIIxSCK */ +#define TSPI_MIN_IDLE_TIME_5 ((uint32_t)0x00001400) /*!< 5 x TSPIIxSCK */ +#define TSPI_MIN_IDLE_TIME_6 ((uint32_t)0x00001800) /*!< 6 x TSPIIxSCK */ +#define TSPI_MIN_IDLE_TIME_7 ((uint32_t)0x00001c00) /*!< 7 x TSPIIxSCK */ +#define TSPI_MIN_IDLE_TIME_8 ((uint32_t)0x00002000) /*!< 8 x TSPIIxSCK */ +#define TSPI_MIN_IDLE_TIME_9 ((uint32_t)0x00002400) /*!< 9 x TSPIIxSCK */ +#define TSPI_MIN_IDLE_TIME_10 ((uint32_t)0x00002800) /*!< 10 x TSPIIxSCK */ +#define TSPI_MIN_IDLE_TIME_11 ((uint32_t)0x00002C00) /*!< 11 x TSPIIxSCK */ +#define TSPI_MIN_IDLE_TIME_12 ((uint32_t)0x00003000) /*!< 12 x TSPIIxSCK */ +#define TSPI_MIN_IDLE_TIME_13 ((uint32_t)0x00003400) /*!< 13 x TSPIIxSCK */ +#define TSPI_MIN_IDLE_TIME_14 ((uint32_t)0x00003800) /*!< 14 x TSPIIxSCK */ +#define TSPI_MIN_IDLE_TIME_15 ((uint32_t)0x00003C00) /*!< 15 x TSPIIxSCK */ +/** + * @} + */ /* End of group TSPI_Minimum_IDLE_Time */ + + +/** + * @defgroup TSPI_Serial_Clock_Delay Serial Clock Delay + * @brief Serial Clock Delay Macro Definisiton. + * @{ + */ +#define TSPI_SERIAL_CK_DELAY_1 ((uint32_t)0x00000000) /*!< 1 x TSPIIxSCK */ +#define TSPI_SERIAL_CK_DELAY_2 ((uint32_t)0x00000010) /*!< 2 x TSPIIxSCK */ +#define TSPI_SERIAL_CK_DELAY_3 ((uint32_t)0x00000020) /*!< 3 x TSPIIxSCK */ +#define TSPI_SERIAL_CK_DELAY_4 ((uint32_t)0x00000030) /*!< 4 x TSPIIxSCK */ +#define TSPI_SERIAL_CK_DELAY_5 ((uint32_t)0x00000040) /*!< 5 x TSPIIxSCK */ +#define TSPI_SERIAL_CK_DELAY_6 ((uint32_t)0x00000050) /*!< 6 x TSPIIxSCK */ +#define TSPI_SERIAL_CK_DELAY_7 ((uint32_t)0x00000060) /*!< 7 x TSPIIxSCK */ +#define TSPI_SERIAL_CK_DELAY_8 ((uint32_t)0x00000070) /*!< 8 x TSPIIxSCK */ +#define TSPI_SERIAL_CK_DELAY_9 ((uint32_t)0x00000080) /*!< 9 x TSPIIxSCK */ +#define TSPI_SERIAL_CK_DELAY_10 ((uint32_t)0x00000090) /*!< 10 x TSPIIxSCK */ +#define TSPI_SERIAL_CK_DELAY_11 ((uint32_t)0x000000a0) /*!< 11 x TSPIIxSCK */ +#define TSPI_SERIAL_CK_DELAY_12 ((uint32_t)0x000000b0) /*!< 12 x TSPIIxSCK */ +#define TSPI_SERIAL_CK_DELAY_13 ((uint32_t)0x000000c0) /*!< 13 x TSPIIxSCK */ +#define TSPI_SERIAL_CK_DELAY_14 ((uint32_t)0x000000d0) /*!< 14 x TSPIIxSCK */ +#define TSPI_SERIAL_CK_DELAY_15 ((uint32_t)0x000000e0) /*!< 15 x TSPIIxSCK */ +#define TSPI_SERIAL_CK_DELAY_16 ((uint32_t)0x000000f0) /*!< 16 x TSPIIxSCK */ +/** + * @} + */ /* End of group TSPI_Serial_Clock_Delay */ + + +/** + * @defgroup TSPI_Negate_Delay Negate Delay + * @brief Negate Delay Macro Definisiton. + * @{ + */ +#define TSPI_NEGATE_1 ((uint32_t)0x00000000) /*!< 1 x TSPIIxSCK */ +#define TSPI_NEGATE_2 ((uint32_t)0x00000001) /*!< 2 x TSPIIxSCK */ +#define TSPI_NEGATE_3 ((uint32_t)0x00000002) /*!< 3 x TSPIIxSCK */ +#define TSPI_NEGATE_4 ((uint32_t)0x00000003) /*!< 4 x TSPIIxSCK */ +#define TSPI_NEGATE_5 ((uint32_t)0x00000004) /*!< 5 x TSPIIxSCK */ +#define TSPI_NEGATE_6 ((uint32_t)0x00000005) /*!< 6 x TSPIIxSCK */ +#define TSPI_NEGATE_7 ((uint32_t)0x00000006) /*!< 7 x TSPIIxSCK */ +#define TSPI_NEGATE_8 ((uint32_t)0x00000007) /*!< 8 x TSPIIxSCK */ +#define TSPI_NEGATE_9 ((uint32_t)0x00000008) /*!< 9 x TSPIIxSCK */ +#define TSPI_NEGATE_10 ((uint32_t)0x00000009) /*!< 10 x TSPIIxSCK */ +#define TSPI_NEGATE_11 ((uint32_t)0x0000000a) /*!< 11 x TSPIIxSCK */ +#define TSPI_NEGATE_12 ((uint32_t)0x0000000b) /*!< 12 x TSPIIxSCK */ +#define TSPI_NEGATE_13 ((uint32_t)0x0000000c) /*!< 13 x TSPIIxSCK */ +#define TSPI_NEGATE_14 ((uint32_t)0x0000000d) /*!< 14 x TSPIIxSCK */ +#define TSPI_NEGATE_15 ((uint32_t)0x0000000e) /*!< 15 x TSPIIxSCK */ +#define TSPI_NEGATE_16 ((uint32_t)0x0000000f) /*!< 16 x TSPIIxSCK */ +/** + * @} + */ /* End of group TSPI_Negate_Delay */ + + +/** + * @defgroup TSPI_ParityEnable Parity Enable + * @brief Enable/Disable Parity Macro Definisiton. + * @{ + */ +#define TSPI_PARITY_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define TSPI_PARITY_ENABLE ((uint32_t)0x00000002) /*!< Enable */ +/** + * @} + */ /* End of group TSPI_ParityEnable */ + + +/** + * @defgroup TSPI_ParityBit Parity Bit + * @brief Parity Bit Macro Definisiton. + * @{ + */ +#define TSPI_PARITY_BIT_ODD ((uint32_t)0x00000000) /*!< Odd Parity */ +#define TSPI_PARITY_BIT_EVEN ((uint32_t)0x00000001) /*!< Even Parity */ +/** + * @} + */ /* End of group TSPI_ParityBit */ + + +/** + * @defgroup TSPI_Status_Setting_flag Status Setting Flag + * @brief Enable/Disable Status Setting Flag Macro Definisiton. + * @{ + */ +#define TSPI_STATUS_SETTING_ENABLE ((uint32_t)0x00000000) /*!< Setting Enable */ +#define TSPI_STATUS_SETTING_DISABLE ((uint32_t)0x80000000) /*!< Setting Disable */ +/** + * @} + */ /* End of group TSPI_Status_Setting_flag */ + + +/** + * @defgroup TSPI_TxState Transmitting State Flag + * @brief Transmitting State Flag Macro Definisiton. + * @{ + */ +#define TSPI_TX_FLAG_STOP ((uint32_t)0x00000000) /*!< Not Sending Data */ +#define TSPI_TX_FLAG_ACTIVE ((uint32_t)0x00800000) /*!< Active Sending Data */ +#define TSPI_TX_FLAG_MASK ((uint32_t)0x00800000) /*!< Active Flag Mask */ +/** + * @} + */ /* End of group TSPI_TxState */ + + +/** + * @defgroup TSPI_TxDone Transmitting Complete Flag + * @brief Transmitting Complete Flag Macro Definisiton. + * @{ + */ +#define TSPI_TX_DONE_FLAG ((uint32_t)0x00400000) /*!< Send Data Complete Flag */ +#define TSPI_TX_DONE ((uint32_t)0x00400000) /*!< Send Data Complete */ +#define TSPI_TX_DONE_CLR ((uint32_t)0x00400000) /*!< Send Data Complete Flag Clear */ +/** + * @} + */ /* End of group TSPI_TxDone */ + + +/** + * @defgroup TSPI_TxFIFOInterruptFlag Transmitting FIFO Interrpt Flag + * @brief Transmitting FIFO Interrpt Flag Macro Definisiton. + * @{ + */ +#define TSPI_TX_FIFO_INT_STOP ((uint32_t)0x00000000) /*!< Not active Interrupt */ +#define TSPI_TX_FIFO_INT_ACTIVE ((uint32_t)0x00200000) /*!< Active Interrupt */ +#define TSPI_TX_FIFO_INT_CLR ((uint32_t)0x00200000) /*!< Interrupt Flag Clear */ +/** + * @} + */ /* End of group TSPI_TxFIFOInterruptFlag */ + +/** + * @defgroup TSPI_TxFIFOEmptyFlag Transmitting FIFO Empty Flag + * @brief Transmitting FIFO Empty Flag Macro Definisiton. + * @{ + */ +#define TSPI_TX_FIFO_NOT_EMP ((uint32_t)0x00000000) /*!< Remain Data in FIFO */ +#define TSPI_TX_FIFO_EMP ((uint32_t)0x00100000) /*!< FIFO is empty */ +/** + * @} + */ /* End of group TSPI_TxFIFOEmptyFlag */ + +/** + * @defgroup TSPI_TxReachFillLevel Current Transmitting FIFO Level + * @brief Current Transmitting FIFO Level Macro Definisiton. + * @{ + */ +#define TSPI_TX_REACH_FILL_LEVEL_0 ((uint32_t)0x00000000) /*!< 0 */ +#define TSPI_TX_REACH_FILL_LEVEL_1 ((uint32_t)0x00010000) /*!< 1 */ +#define TSPI_TX_REACH_FILL_LEVEL_2 ((uint32_t)0x00020000) /*!< 2 */ +#define TSPI_TX_REACH_FILL_LEVEL_3 ((uint32_t)0x00030000) /*!< 3 */ +#define TSPI_TX_REACH_FILL_LEVEL_4 ((uint32_t)0x00040000) /*!< 4 */ +#define TSPI_TX_REACH_FILL_LEVEL_5 ((uint32_t)0x00050000) /*!< 5 */ +#define TSPI_TX_REACH_FILL_LEVEL_6 ((uint32_t)0x00060000) /*!< 6 */ +#define TSPI_TX_REACH_FILL_LEVEL_7 ((uint32_t)0x00070000) /*!< 7 */ +#define TSPI_TX_REACH_FILL_LEVEL_MASK ((uint32_t)0x00070000) /*!< TX_REACH_FILL_LEVEL_MASK */ +/** + * @} + */ /* End of group TSPI_TxReachFillLevel */ + + +/** + * @defgroup TSPI_RxState Receive State Flag + * @brief Receive State Flag Macro Definisiton. + * @{ + */ +#define TSPI_RX_FLAG_STOP ((uint32_t)0x00000000) /*!< Not Sending Data */ +#define TSPI_RX_FLAG_ACTIVE ((uint32_t)0x00000080) /*!< Active Sending Data */ +#define TSPI_RX_FLAG_MASK ((uint32_t)0x00000080) /*!< Active Flag Mask */ +/** + * @} + */ /* End of group TSPI_RxState */ + + +/** + * @defgroup TSPI_RxDone Receive Complete Flag + * @brief Receive Complete Flag Macro Definisiton. + * @{ + */ +#define TSPI_RX_DONE_FLAG ((uint32_t)0x00000040) /*!< Receive Data Complete Flag */ +#define TSPI_RX_DONE ((uint32_t)0x00000040) /*!< Send Data Complete */ +#define TSPI_RX_DONE_CLR ((uint32_t)0x00000040) /*!< Receive Data Complete Flag Clear */ +/** + * @} + */ /* End of group TSPI_RxDone */ + + +/** + * @defgroup TSPI_RxFIFOInterruptFlag Receiving FIFO Interrpt Flag + * @brief Rx FIFO Interrpt Flag Macro Definisiton. + * @{ + */ +#define TSPI_RX_FIFO_INT_STOP ((uint32_t)0x00000000) /*!< Not active Interrupt */ +#define TSPI_RX_FIFO_INT_ACTIVE ((uint32_t)0x00000020) /*!< Active Interrupt */ +#define TSPI_RX_FIFO_INT_CLR ((uint32_t)0x00000020) /*!< Interrupt Flag Clear */ +/** + * @} + */ /* End of group TSPI_RxFIFOInterruptFlag */ + +/** + * @defgroup TSPI_RxFIFOFullFlag Receiving FIFO Full Flag + * @brief Receiving FIFO Full Flag Macro Definisiton. + * @{ + */ +#define TSPI_RX_FIFO_NOT_FULL ((uint32_t)0x00000000) /*!< Remain Data in FIFO */ +#define TSPI_RX_FIFO_FULL ((uint32_t)0x00000010) /*!< FIFO is empty */ +/** + * @} + */ /* End of group TSPI_RxFIFOFullFlag */ + + +/** + * @defgroup TSPI_RxReachFillLevel Current Receive FIFO Level + * @brief Current Receive FIFO Level Macro Definisiton. + * @{ + */ +#define TSPI_RX_REACH_FILL_LEVEL_0 ((uint32_t)0x00000000) /*!< 0 */ +#define TSPI_RX_REACH_FILL_LEVEL_1 ((uint32_t)0x00000001) /*!< 1 */ +#define TSPI_RX_REACH_FILL_LEVEL_2 ((uint32_t)0x00000002) /*!< 2 */ +#define TSPI_RX_REACH_FILL_LEVEL_3 ((uint32_t)0x00000003) /*!< 3 */ +#define TSPI_RX_REACH_FILL_LEVEL_4 ((uint32_t)0x00000004) /*!< 4 */ +#define TSPI_RX_REACH_FILL_LEVEL_5 ((uint32_t)0x00000005) /*!< 5 */ +#define TSPI_RX_REACH_FILL_LEVEL_6 ((uint32_t)0x00000006) /*!< 6 */ +#define TSPI_RX_REACH_FILL_LEVEL_7 ((uint32_t)0x00000007) /*!< 7 */ +#define TSPI_RX_REACH_FILL_LEVEL_MASK ((uint32_t)0x0000000F) /*!< TX_REACH_FILL_LEVEL_MASK */ +/** + * @} + */ /* End of group TSPI_RxReachFillLevel */ + + +/** + * @defgroup TSPI_TRGErr Triger Error + * @brief Triger Error Macro Definisiton. + * @{ + */ +#define TSPI_TRGERR_NO_ERR ((uint32_t)0x00000000) /*!< No Error */ +#define TSPI_TRGERR_ERR ((uint32_t)0x00000008) /*!< Error */ +#define TSPI_TRGERR_MASK ((uint32_t)0x00000008) /*!< MASK */ +/** + * @} + */ /* End of group TSPI_TRGErr */ + +/** + * @defgroup TSPI_UnderrunErr Underrun Error + * @brief Underrun Error Macro Definisiton. + * @{ + */ +#define TSPI_UNDERRUN_NO_ERR ((uint32_t)0x00000000) /*!< No Error */ +#define TSPI_UNDERRUN_ERR ((uint32_t)0x00000004) /*!< Error */ +#define TSPI_UNDERRUN_MASK ((uint32_t)0x00000004) /*!< MASK */ +/** + * @} + */ /* End of group TSPI_UnderrunErr */ + +/** + * @defgroup TSPI_OverrunErr Overrun Error + * @brief Overrun Error Macro Definisiton. + * @{ + */ +#define TSPI_OVERRUN_NO_ERR ((uint32_t)0x00000000) /*!< No Error */ +#define TSPI_OVERRUN_ERR ((uint32_t)0x00000002) /*!< Error */ +#define TSPI_OVERRUN_MASK ((uint32_t)0x00000002) /*!< MASK */ +/** + * @} + */ /* End of group TSPI_OverrunErr */ + + +/** + * @defgroup TSPI_ParityErr Parity Error + * @brief Parity Error Macro Definisiton. + * @{ + */ +#define TSPI_PARITY_NO_ERR ((uint32_t)0x00000000) /*!< No Error */ +#define TSPI_PARITY_ERR ((uint32_t)0x00000001) /*!< Error */ +#define TSPI_PARITY_MASK ((uint32_t)0x00000001) /*!< MASK */ +/** + * @} + */ /* End of group TSPI_ParityErr */ + + /** + * @defgroup TSPI_Data_allign Data allign + * @brief Data allign Macro Definisiton. + * @{ + */ +#define TSPI_DATA_ALLIGN_8 ((uint32_t)0x00000000) /*!< Data length byte */ +#define TSPI_DATA_ALLIGN_16 ((uint32_t)0x00000001) /*!< Data length half word */ +#define TSPI_DATA_ALLIGN_32 ((uint32_t)0x00000002) /*!< Data length word */ +/** + * @} + */ /* End of group TSPI_Data_allign */ + + /** + * @defgroup TSPI_FifoMax FIFO MAX + * @brief FIFO MAX LEVEL + * @{ + */ +#define TSPI_FIFO_MAX ((uint32_t)0x00000008) /*!< Data length byte */ +/** + * @} + */ /* End of group TSPI_FifoMax */ + + /** + * @defgroup TSPI_ErrCode Error Code + * @brief Error Code Macro Definisiton. + * @{ + */ +#define NOERROR ((uint32_t)0x00000000) /*!< no error */ +#define TIMEOUTERR ((uint32_t)0x00000001) /*!< transmit/receive timeout error */ +#define DATALENGTHERR ((uint32_t)0x00000002) /*!< frame length setting error */ +#define DATABUFEMPERR ((uint32_t)0x00000003) /*!< transmit data empty error */ +#define DATALACKERR ((uint32_t)0x00000004) /*!< transmit data insufficient error */ +#define FIFOFULLERR ((uint32_t)0x00000005) /*!< FIFO Full error */ +#define TRANSMITMODEERR ((uint32_t)0x00000006) /*!< transmit mode error */ +#define UNDERRUNERR ((uint32_t)0x00000007) /*!< transmit mode error */ +#define OVERRUNERR ((uint32_t)0x00000008) /*!< transmit mode error */ +#define PARITYERR ((uint32_t)0x00000009) /*!< transmit mode error */ +#define INITERR ((uint32_t)0x000000) /*!< transmit mode error */ +/** +* @} + */ /* End of group TSPI_ErrCode */ + + /** + * @defgroup TSPI_Buffer_Size Receive Buffer size + * @brief Error Code Macro Definisiton. + * @{ + */ +#define BUFFSIZE ((uint32_t)0x000000010 /*!< Buffer Size */ +/** +* @} + */ /* End of group TSPI_Buffer_Size */ +/** + * @} + */ /* End of group TSPI_Exported_define */ + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup TSPI_Exported_Typedef TSPI Exported Typedef + * @{ + */ +/* No define */ +/** + * @} + */ /* End of group TSPI_Exported_Typedef */ +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup TSPI_Exported_Typedef TSPI Exported Typedef + * @{ + */ +/*----------------------------------*/ +/** + * @struct tspi_receive8_t + * @brief Receive event information structure definenition. + * @brief When data length definenition is "8bit"( @ref TSPI_DataLength ), use this. +*/ +/*----------------------------------*/ +typedef struct +{ + uint8_t *p_data; /*!< The buffer to receive data. */ + uint32_t num; /*!< The number of receive data. */ +} tspi_receive8_t; + +/*----------------------------------*/ +/** + * @struct tspi_receive16_t + * @brief Receive event information structure definenition. + * @brief When data length definenition is "9 - 16 bit"( @ref TSPI_DataLength ), use this. +*/ +/*----------------------------------*/ +typedef struct +{ + uint16_t *p_data; /*!< The buffer to receive data. */ + uint32_t num; /*!< The number of receive data. */ +} tspi_receive16_t; + +/** + * @struct tspi_receive32_t + * @brief Receive event information structure definenition. + * @brief When data length definenition is "17 - 32 bit"( @ref TSPI_DataLength ), use this. +*/ +/*----------------------------------*/ +typedef struct +{ + uint32_t *p_data; /*!< The buffer to receive data. */ + uint32_t num; /*!< The number of receive data. */ +} tspi_receive32_t; + +/*----------------------------------*/ +/** + * @struct tspi_receive_t + * @brief Receive event information structure definenition. +*/ +/*----------------------------------*/ +typedef union +{ + tspi_receive8_t rx8; /*!< @ref tspi_receive8_t */ + tspi_receive16_t rx16; /*!< @ref tspi_receive16_t */ + tspi_receive32_t rx32; /*!< @ref tspi_receive16_t */ +} tspi_receive_t; + +/*----------------------------------*/ +/** + * @struct tspi_transmit8_t + * @brief Transmit data information structure definenition. + * @brief When data length definenition is "8bit"( @ref TSPI_DataLength ), use this. +*/ +/*----------------------------------*/ +typedef struct +{ + uint8_t *p_data; /*!< The buffer to transmit data. */ + uint32_t num; /*!< The number of transmit data. */ +} tspi_transmit8_t; + +/*----------------------------------*/ +/** + * @struct tspi_transmit16_t + * @brief Transmit data information structure definenition. + * @brief When data length definenition is "9 - 16 bit"( @ref TSPI_DataLength ), use this. +*/ +/*----------------------------------*/ +typedef struct +{ + uint16_t *p_data; /*!< The buffer to transmit data. */ + uint32_t num; /*!< The number of transmit data. */ +} tspi_transmit16_t; +/*----------------------------------*/ +/** + * @struct tspi_transmit32_t + * @brief Transmit data information structure definenition. + * @brief When data length definenition is "17 - 32 bit"( @ref TSPI_DataLength ), use this. +*/ +/*----------------------------------*/ +typedef struct +{ + uint32_t *p_data; /*!< The buffer to transmit data. */ + uint32_t num; /*!< The number of transmit data. */ +} tspi_transmit32_t; + +/*----------------------------------*/ +/** + * @struct tspi_transmit_t + * @brief Transmit data information structure definenition. +*/ +/*----------------------------------*/ +typedef union +{ + tspi_transmit8_t tx8; /*!< @ref tspi_transmit8_t */ + tspi_transmit16_t tx16; /*!< @ref tspi_transmit16_t */ + tspi_transmit32_t tx32; /*!< @ref tspi_transmit16_t */ +} tspi_transmit_t; + +/*----------------------------------*/ +/** + * @struct tspi_control1_t + * @brief Control Setting structure definenition. +*/ +/*----------------------------------*/ +typedef struct +{ + uint32_t trgen; /*!< TRGEN Transmission Triger Control. + : Use @ref TSPI_Triger_Control */ + uint32_t trxe; /*!< TRXE Transmission Control. + : Use @ref TSPI_Transmission_Control */ + uint32_t tspims; /*!< TSPI/SIO Transmission Mode. + : Use @ref TSPI_Transmission_Mode */ + uint32_t mstr; /*!< Master/Slave Operation Select. + : Use @ref TSPI_Operation_Select */ + uint32_t tmmd; /*!< Transfer Mode Select. + : Use @ref TSPI_Transfer_Mode */ + uint32_t cssel; /*!< CSSEL Select. + : Use @ref TSPI_CSSEL_Select */ + uint32_t fc; /*!< Transfer Frame Value. + : Range ( TSPI_TRANS_RANGE_SINGLE <= N =< TSPI_TRANS_RANGE_MAX ) @ref TSPI_Transfer_Frame_Range */ +} tspi_control1_t; + +/*----------------------------------*/ +/** + * @struct tspi_control2_t + * @brief Control Setting structure definenition. +*/ +/*----------------------------------*/ +typedef struct +{ + uint32_t tidle; /*!< IDLE Output Value. + : Use @ref TSPI_IDLE_Output_value */ + uint32_t txdemp; /*!< Under Run Occur Output Value. + : Use @ref TSPI_IDLE_Output_value */ + uint32_t rxdly; /*!< Fsys Select. + : Use @ref TSPI_RXDLY_value */ + uint32_t til; /*!< Transmit Fill Level. + : Use @ref TSPI_TxFillLevel */ + uint32_t ril; /*!< Receive Fill Level. + : Use @ref TSPI_RxFillLevel */ + uint32_t inttxfe; /*!< Enable/Disable Transmit FIFO Interrupt. + : Use @ref TSPI_TxFIFOInterrupt */ + uint32_t inttxwe; /*!< Enable/Disable Transmit Interrupt. + : Use @ref TSPI_TxInterrupt */ + uint32_t intrxfe; /*!< Enable/Disable Receive FIFO Interrupt. + : Use @ref TSPI_RxFIFOInterrupt */ + uint32_t intrxwe; /*!< Enable/Disable Receive Interrupt. + : Use @ref TSPI_RxInterrupt */ + uint32_t interr; /*!< Enable/Disable Error Interrupt. + : Use @ref TSPI_ErrorInterrupt */ + uint32_t dmate; /*!< Enable/Disable Transmit DMA Interrupt. + : Use @ref TSPI_TxDMAInterrupt */ + uint32_t dmare; /*!< Enable/Disable Receive DMA Interrupt. + : Use @ref TSPI_RxDMAInterrupt */ +} tspi_control2_t; + +/*----------------------------------*/ +/** + * @struct tspi_control3_t + * @brief Control Setting structure definenition. +*/ +/*----------------------------------*/ +typedef struct +{ + uint32_t tfempclr; /*!< Transmit Buffer Clear. + : Use @ref TSPI_Tx_Buffer_Clear */ + uint32_t rffllclr; /*!< Receive Buffer Clear. + : Use @ref TSPI_Rx_Buffer_Clear */ +} tspi_control3_t; + +/*----------------------------------*/ +/** + * @struct tspi_baudrate_t + * @brief Clock setting structure definenition. +*/ +/*----------------------------------*/ +typedef struct +{ + uint32_t brck; /*!< Baudrate Input Clock. + : Use @ref TSPI_Baudrate_Clock */ + uint32_t brs; /*!< Baudrate Divider. + : Use @ref TSPI_Baudrate_Divider */ +} tspi_baudrate_t; + +/*----------------------------------*/ +/** + * @struct tspi_fmtr0_t + * @brief Format control0. +*/ +/*----------------------------------*/ +typedef struct +{ + uint32_t dir; /*!< Data Direction. + : Use @ref TSPI_DataDirection */ + uint32_t fl; /*!< Data Length. + : Use @ref TSPI_DataLength */ + uint32_t fint; /*!< Frame Interval time. + : Use @ref TSPI_Frame_Interval_Time */ + uint32_t cs3pol; /*!< TSPIIxCS3 Polarity negative/positive. + : Use @ref TSPI_TSPIxCS3_Polarity */ + uint32_t cs2pol; /*!< TSPIIxCS2 Polarity negative/positive. + : Use @ref TSPI_TSPIxCS2_Polarity */ + uint32_t cs1pol; /*!< TSPIIxCS1 Polarity negative/positive. + : Use @ref TSPI_TSPIxCS1_Polarity */ + uint32_t cs0pol; /*!< TSPIIxCS0 Polarity negative/positive. + : Use @ref TSPI_TSPIxCS0_Polarity */ + uint32_t ckpha; /*!< Serial Clock Polarity 1st/2nd edge. + : Use @ref TSPI_Serial_Clock_Polarity */ + uint32_t ckpol; /*!< Serial Clock IDLE Polarity Hi/Low. + : Use @ref TSPI_Serial_Clock_IDLE_Polarity */ + uint32_t csint; /*!< Minimum IDLE Time. + : Use @ref TSPI_Minimum_IDLE_Time */ + uint32_t cssckdl; /*!< Serial Clock Delay. + : Use @ref TSPI_Serial_Clock_Delay */ + uint32_t sckcsdl; /*!< Negate Delay. + : Use @ref TSPI_Negate_Delay */ +} tspi_fmtr0_t; + +/*----------------------------------*/ +/** + * @struct tspi_fmtr1_t + * @brief Format control1. +*/ +/*----------------------------------*/ +typedef struct +{ + uint32_t reserved; /*!< SIO Slave MOde. + : */ + uint32_t vpe; /*!< Enable/Disable Parity Function. + : Use @ref TSPI_ParityEnable */ + uint32_t vpm; /*!< Odd/Even Parity Bit. + : Use @ref TSPI_ParityBit */ +} tspi_fmtr1_t; + +/*----------------------------------*/ +/** + * @struct tspi_status_t + * @brief Status register. +*/ +/*----------------------------------*/ +typedef struct +{ + uint32_t tspisue; /*!< Enable/Disable Status Setting Flag. + : Use @ref TSPI_Status_Setting_flag */ + uint32_t txrun; /*!< Stop/Active Tx Active Flag. + : Use @ref TSPI_TxState */ + uint32_t txend; /*!< Tx Data Send Complete Flag. + : Use @ref TSPI_TxDone */ + uint32_t inttxwf; /*!< Tx FIFO Interrpt Flag. + : Use @ref TSPI_TxFIFOInterruptFlag */ + uint32_t tfemp; /*!< Tx FIFO Empty Flag. + : Use @ref TSPI_TxFIFOEmptyFlag */ + uint32_t tlvll; /*!< Tx Reach Fill Level + : Use @ref TSPI_TxReachFillLevel */ + uint32_t rxrun; /*!< Stop/Active Rx Active Flag. + : Use @ref TSPI_RxState */ + uint32_t rxend; /*!< Rx Data Receive Complete Flag. + : Use @ref TSPI_RxDone */ + uint32_t intrxff; /*!< Rx FIFO Interrpt Flag + : Use @ref TSPI_RxFIFOInterruptFlag */ + uint32_t rffll; /*!< Rx FIFO Full Flag + : Use @ref TSPI_RxFIFOFullFlag */ + uint32_t rlvl; /*!< Rx Reach Fill Level + : Use @ref TSPI_RxReachFillLevel */ +} tspi_status_t; + +/*----------------------------------*/ +/** + * @struct tspi_error_t + * @brief Error flag. +*/ +/*----------------------------------*/ +typedef struct +{ + uint32_t udrerr; /*!< Underrun Error. + : Use @ref TSPI_UnderrunErr */ + uint32_t ovrerr; /*!< Overrun Error. + : Use @ref TSPI_OverrunErr */ + uint32_t perr; /*!< Parity Error. + : Use @ref TSPI_ParityErr */ +} tspi_error_t; + + +/*----------------------------------*/ +/** + * @struct tspi_initial_setting_t + * @brief Initial setting structure definenition. +*/ +/*----------------------------------*/ +typedef struct +{ + uint32_t id; /*!< ID: User value. */ + tspi_control1_t cnt1; /*!< Control1 setting. + : Use @ref tspi_control1_t */ + tspi_control2_t cnt2; /*!< Control2 setting. + : Use @ref tspi_control2_t */ + tspi_control3_t cnt3; /*!< Control2 setting. + : Use @ref tspi_control2_t */ + tspi_baudrate_t brd; /*!< Baudrate setting. + : Use @ref tspi_baudrate_t */ + tspi_fmtr0_t fmr0; /*!< Format control0 setting. + : Use @ref tspi_fmtr0_t */ + tspi_fmtr1_t fmr1; /*!< Format control1 setting. + : Use @ref tspi_fmtr1_t */ +} tspi_initial_setting_t; + +/*----------------------------------*/ +/** + * @brief TSPI handle structure definenition. +*/ +/*----------------------------------*/ +typedef struct tspi_handle +{ + TSB_TSPI_TypeDef *p_instance; /*!< Registers base address. */ + tspi_initial_setting_t init; /*!< Initial setting. */ + uint32_t errcode; /*!< ErrorCode */ + /*------------------------------------------*/ + /*! + @brief Transmit Informatin. + */ + /*------------------------------------------*/ + struct + { + uint32_t rp; /*!< Num of transmited data. */ + tspi_transmit_t info; /*!< Transmit Data Information. */ + uint8_t tx_allign; /*!< Transmit Data length Information. */ + void (*handler)(uint32_t id, TXZ_Result result); /*!< Transmit Event handler. */ + } transmit; + /*------------------------------------------*/ + /*! + @brief Receive Informatin. + */ + /*------------------------------------------*/ + struct + { + tspi_receive_t info; /*!< Receive Data Information. */ + uint8_t rx_allign; /*!< Receive Data length Information. */ + void (*handler)(uint32_t id, TXZ_Result result, tspi_receive_t *p_info); /*!< Receive Event handler. */ + } receive; +} tspi_t; +/** + * @} + */ /* End of group TSPI_Exported_Typedef */ + + +/*------------------------------------------------------------------------------*/ +/* Functions */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup TSPI_Exported_functions TSPI Exported Functions + * @{ + */ +TXZ_Result tspi_init(tspi_t *p_obj); +TXZ_Result tspi_deinit(tspi_t *p_obj); +TXZ_Result tspi_format(tspi_t *p_obj); +TXZ_Result tspi_master_write(tspi_t *p_obj, tspi_transmit_t *p_info, uint32_t timeout); +TXZ_Result tspi_master_read(tspi_t *p_obj, tspi_receive_t *p_info, uint32_t timeout); +TXZ_Result tspi_master_transfer(tspi_t *p_obj, tspi_transmit_t *p_info); +TXZ_Result tspi_master_receive(tspi_t *p_obj, tspi_receive_t *p_info); +void tspi_irq_handler_transmit(tspi_t *p_obj); +void tspi_irq_handler_receive(tspi_t *p_obj); +void tspi_error_irq_handler(tspi_t *p_obj); +TXZ_Result tspi_get_status(tspi_t *p_obj, uint32_t *p_status); +TXZ_Result tspi_get_error(tspi_t *p_obj, uint32_t *p_error); +TXZ_Result tspi_error_clear(tspi_t *p_obj); +TXZ_Result tspi_discard_transmit(tspi_t *p_obj); +TXZ_Result tspi_discard_receive(tspi_t *p_obj); +/** + * @} + */ /* End of group TSPI_Exported_functions */ +/** + * @} + */ /* End of group TSPI */ +/** + * @} + */ /* End of group Periph_Driver */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __TSPI_H */ + + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/pinmap.c b/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/pinmap.c new file mode 100644 index 00000000000..02554d10c76 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/pinmap.c @@ -0,0 +1,198 @@ +/* mbed Microcontroller Library + * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "mbed_assert.h" +#include "pinmap.h" +#include "gpio_include.h" + +void pin_function(PinName pin, int function) +{ + int port = 0; + uint8_t bit = 0; + uint8_t func = 0; + uint8_t dir = 0; + uint32_t port_base = 0; + uint32_t mode_base = 0; + + // Assert that pin is valid + MBED_ASSERT(pin != NC); + + // Calculate pin function and pin direction + func = PIN_FUNC(function); + dir = PIN_DIR(function); + + // Calculate port and pin position + port = PIN_PORT(pin); + bit = PIN_POS(pin); + + port_base = BITBAND_PORT_BASE(port); + // Initialization PxFR OFF + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR1); + BITBAND_PORT_CLR(mode_base, bit); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR2); + BITBAND_PORT_CLR(mode_base, bit); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR3); + BITBAND_PORT_CLR(mode_base, bit); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR4); + BITBAND_PORT_CLR(mode_base, bit); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR5); + BITBAND_PORT_CLR(mode_base, bit); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR6); + BITBAND_PORT_CLR(mode_base, bit); + + // Initialize Input + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_CLR(mode_base, bit); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_SET(mode_base, bit); + + switch (func) { + case 0: + break; + case 1: + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR1); + break; + case 2: + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR2); + break; + case 3: + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR3); + break; + case 4: + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR4); + break; + case 5: + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR5); + break; + case 6: + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR6); + break; + default: + break; + } + + if (func != 0) { + BITBAND_PORT_SET(mode_base, bit); + } + if (dir == PIN_OUTPUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_CLR(mode_base, bit); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_SET(mode_base, bit); + } else if (dir == PIN_INOUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_SET(mode_base, bit); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_SET(mode_base, bit); + } +} + +void pin_mode(PinName pin, PinMode mode) +{ + int port = 0; + uint8_t bit = 0; + uint8_t val = 0; + + // Assert that pin is valid + MBED_ASSERT(pin != NC); + + // Check if function is in range + if (mode > OpenDrain) { + return; + } + + // Calculate port and pin position + port = PIN_PORT(pin); + bit = PIN_POS(pin); + val = (1 << bit); + + switch (port) { + case PortA: + if (mode == OpenDrain) TSB_PA->OD = val; + else if (mode == PullUp) TSB_PA->PUP = val; + else if (mode == PullDown || mode == PullDefault) TSB_PA->PDN = val; + break; + case PortB: + if (mode == OpenDrain) TSB_PB->OD = val; + else if (mode == PullUp) TSB_PB->PUP = val; + else if (mode == PullDown || mode == PullDefault) TSB_PB->PDN = val; + break; + case PortC: + if (mode == OpenDrain) TSB_PC->OD = val; + else if (mode == PullUp) TSB_PC->PUP = val; + else if (mode == PullDown || mode == PullDefault) TSB_PC->PDN = val; + break; + case PortD: + if (mode == OpenDrain) TSB_PD->OD = val; + else if (mode == PullUp) TSB_PD->PUP = val; + else if (mode == PullDown || mode == PullDefault) TSB_PD->PDN = val; + break; + case PortE: + if (mode == OpenDrain) TSB_PE->OD = val; + else if (mode == PullUp) TSB_PE->PUP = val; + else if (mode == PullDown || mode == PullDefault) TSB_PE->PDN = val; + break; + case PortF: + if (mode == OpenDrain) TSB_PF->OD = val; + else if (mode == PullUp) TSB_PF->PUP = val; + else if (mode == PullDown || mode == PullDefault) TSB_PF->PDN = val; + break; + case PortG: + if (mode == OpenDrain) TSB_PG->OD = val; + else if (mode == PullUp) TSB_PG->PUP = val; + else if (mode == PullDown || mode == PullDefault) TSB_PG->PDN = val; + break; + case PortH: + if (mode == PullDown) TSB_PH->PDN = val; + break; + case PortJ: + if (mode == OpenDrain) TSB_PJ->OD = val; + else if (mode == PullUp) TSB_PJ->PUP = val; + else if (mode == PullDown || mode == PullDefault) TSB_PJ->PDN = val; + break; + case PortK: + if (mode == OpenDrain) TSB_PK->OD = val; + else if (mode == PullUp) TSB_PK->PUP = val; + else if (mode == PullDown || mode == PullDefault) TSB_PK->PDN = val; + break; + case PortL: + if (mode == OpenDrain) TSB_PL->OD = val; + else if (mode == PullUp) TSB_PL->PUP = val; + else if (mode == PullDown || mode == PullDefault) TSB_PL->PDN = val; + break; + case PortM: + if (mode == OpenDrain) TSB_PM->OD = val; + else if (mode == PullUp) TSB_PM->PUP = val; + else if (mode == PullDown || mode == PullDefault) TSB_PM->PDN = val; + break; + case PortN: + if (mode == OpenDrain) TSB_PN->OD = val; + else if (mode == PullUp) TSB_PN->PUP = val; + else if (mode == PullDown || mode == PullDefault) TSB_PN->PDN = val; + break; + case PortP: + if (mode == OpenDrain) TSB_PP->OD = val; + else if (mode == PullUp) TSB_PP->PUP = val; + else if (mode == PullDown || mode == PullDefault) TSB_PP->PDN = val; + break; + case PortR: + if (mode == OpenDrain) TSB_PR->OD = val; + else if (mode == PullUp) TSB_PR->PUP = val; + else if (mode == PullDown || mode == PullDefault) TSB_PR->PDN = val; + break; + default: + break; + } +} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/port_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/port_api.c new file mode 100644 index 00000000000..e4583b9871d --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/port_api.c @@ -0,0 +1,159 @@ +/* mbed Microcontroller Library + * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "port_api.h" +#include "pinmap.h" +#include "gpio_include.h" + +void port_init(port_t *obj, PortName port, int mask, PinDirection dir) +{ + uint8_t i = 0; + + // Assert that port is valid + MBED_ASSERT(port <= PortR); + + // Store port and port mask for future use + obj->port = port; + obj->mask = mask; + + // Enabling Port Clock Supply + TSB_CG->FSYSENA |= (1 << (obj->port)); + + // Set port function and port direction + for (i = 0; i < PORT_PIN_NUM; i++) { + if (obj->mask & (1 << i)) { // If the pin is used + pin_function(port_pin(obj->port, i), dir); + } + } +} + +void port_mode(port_t *obj, PinMode mode) +{ + uint8_t i = 0; + + // Assert that port is valid + MBED_ASSERT(obj->port <= PortR); + + // Set mode for masked pins + for (i = 0; i < PORT_PIN_NUM; i++) { + if (obj->mask & (1 << i)) { // If the pin is used + pin_mode(port_pin(obj->port, i), mode); + } + } +} + +void port_dir(port_t *obj, PinDirection dir) +{ + uint8_t bit = 0; + + // Assert that port is valid + MBED_ASSERT(obj->port <= PortR); + + // Set direction for masked pins + switch (dir) { + case PIN_INPUT: + for (bit = 0; bit < PORT_PIN_NUM; bit++) { + if (((obj->mask >> bit) & 0x01) == 0x01) { + pin_function((PinName)bit, PIN_INPUT); + } + } + break; + case PIN_OUTPUT: + for (bit = 0; bit < PORT_PIN_NUM; bit++) { + if (((obj->mask >> bit) & 0x01) == 0x01) { + pin_function((PinName)bit, PIN_OUTPUT); + } + } + break; + case PIN_INOUT: + for (bit = 0; bit < PORT_PIN_NUM; bit++) { + if (((obj->mask >> bit) & 0x01) == 0x01) { + pin_function((PinName)bit, PIN_INOUT); + } + } + break; + default: + break; + } +} + +void port_write(port_t *obj, int value) +{ + uint8_t port_data = 0; + uint8_t data = 0; + int bit = 0; + uint8_t val = 0; + uint32_t base = 0; + + // Assert that port is valid + MBED_ASSERT(obj->port <= PortR); + + base = BITBAND_PORT_BASE(obj->port); + base = BITBAND_PORT_MODE_BASE(base, GPIO_Mode_DATA); + + // Get current data of port + for (bit = 7; bit >= 0; bit--) { + BITBAND_PORT_READ(val, base, bit); + port_data <<= 1; + port_data |= val; + } + + // Calculate data to write to masked pins + data = (port_data & ~obj->mask) | (value & obj->mask); + + for (bit = 0; bit < PORT_PIN_NUM; bit++) { + if (((obj->mask >> bit) & 0x01) == 0x01) { + if (((data >> bit) & 0x01) == GPIO_PIN_SET) { + BITBAND_PORT_SET(base, bit); + } else { + BITBAND_PORT_CLR(base, bit); + } + } + } +} + +int port_read(port_t *obj) +{ + uint8_t port_data = 0; + uint8_t data = 0; + int bit = 0; + uint8_t val = 0; + uint32_t base = 0; + + // Assert that port is valid + MBED_ASSERT(obj->port <= PortR); + + base = BITBAND_PORT_BASE(obj->port); + base = BITBAND_PORT_MODE_BASE(base, GPIO_Mode_DATA); + + // Get current data of port + for (bit = 7; bit >= 0; bit--) { + BITBAND_PORT_READ(val, base, bit); + port_data <<= 1; + port_data |= val; + } + + // Calculate data of masked pins + data = port_data & obj->mask; + + return data; +} + +PinName port_pin(PortName port, int pin_n) +{ + PinName pin = NC; + pin = (PinName)((port << 3 ) | pin_n); + return pin; +} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/pwmout_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/pwmout_api.c new file mode 100644 index 00000000000..c1263869240 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/pwmout_api.c @@ -0,0 +1,187 @@ +/* mbed Microcontroller Library + * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "pwmout_api.h" +#include "pinmap.h" +#include "gpio_include.h" + +static const PinMap PinMap_PWM[] = { + {PP0, PWM_0, PIN_DATA(4, 1)}, + {PC0, PWM_1, PIN_DATA(4, 1)}, + {PJ0, PWM_2, PIN_DATA(4, 1)}, + {PK2, PWM_3, PIN_DATA(4, 1)}, + {PN0, PWM_4, PIN_DATA(4, 1)}, + {NC, NC, 0} +}; + +static const uint32_t prescale_tbl[] = { + 2, 8, 32, 128, 256, 512, 1024 +}; + +void pwmout_init(pwmout_t* obj, PinName pin) +{ + uint16_t counter = 0; + + PWMName pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM); // Determine the pwm channel + MBED_ASSERT(pwm != (PWMName)NC); + + switch (pwm) { + case PWM_0: + obj->channel = TSB_T32A1; + TSB_CG_FSYSENA_IPENA27 = ENABLE; + TSB_CG_FSYSENA_IPENA13 = ENABLE; + break; + case PWM_1: + obj->channel = TSB_T32A2; + TSB_CG_FSYSENA_IPENA28 = ENABLE; + TSB_CG_FSYSENA_IPENA02 = ENABLE; + break; + case PWM_2: + obj->channel = TSB_T32A3; + TSB_CG_FSYSENA_IPENA29 = ENABLE; + TSB_CG_FSYSENA_IPENA08 = ENABLE; + break; + case PWM_3: + obj->channel = TSB_T32A4; + TSB_CG_FSYSENA_IPENA30 = ENABLE; + TSB_CG_FSYSENA_IPENA09 = ENABLE; + break; + case PWM_4: + obj->channel = TSB_T32A5; + TSB_CG_FSYSENA_IPENA31 = ENABLE; + TSB_CG_FSYSENA_IPENA12 = ENABLE; + break; + default: + obj->channel = NULL; + break; + } + + pinmap_pinout(pin, PinMap_PWM); // Set pin function as PWM + obj->pin = pin; + obj->period = DEFAULT_PERIOD; + obj->divisor = DEFAULT_CLOCK_DIVISION; + obj->channel->MOD = (T32A_MODE_32 | T32A_DBG_HALT_STOP); + obj->channel->RUNC = (T32A_COUNT_STOP | T32A_COUNT_DONT_START | T32A_RUN_DISABLE); + obj->channel->CRC = (T32A_PRSCLx_32 | T32A_WBF_ENABLE | T32A_RELOAD_TREGx); + obj->channel->OUTCRC0 = T32A_OCR_DISABLE; + obj->channel->OUTCRC1 = (T32A_OCRCMPx0_SET | T32A_OCRCMPx1_CLR); + + counter = ((DEFAULT_PERIOD * (SystemCoreClock)) / obj->divisor); + obj->channel->RGC0 = counter; + obj->channel->RGC1 = counter; + obj->trailing_timing = counter; + obj->leading_timing = counter; +} + +void pwmout_free(pwmout_t* obj) +{ + // Stops and clear count operation + obj->channel->RUNC = (T32A_RUN_DISABLE | T32A_COUNT_STOP); + pwmout_write(obj, 0); + obj->pin = NC; + obj->channel = NULL; + obj->trailing_timing = 0; + obj->leading_timing = 0; + obj->divisor = 0; +} + +void pwmout_write(pwmout_t* obj, float value) +{ + obj->channel->RUNC = (T32A_RUN_DISABLE | T32A_COUNT_STOP); // Stop timer for setting clock again + obj->leading_timing = (obj->trailing_timing - + (obj->trailing_timing * value)); // leading_timing value + obj->channel->RGC0 = obj->leading_timing; // Setting TBxRG0 register + obj->channel->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_START); // Start count operation +} + +float pwmout_read(pwmout_t* obj) +{ + float duty_cycle = ((float)(obj->trailing_timing - obj->leading_timing) + / obj->trailing_timing); + return duty_cycle; +} + +void pwmout_period(pwmout_t* obj, float seconds) +{ + pwmout_period_us(obj, (int)(seconds * 1000000.0f)); +} + +void pwmout_period_ms(pwmout_t* obj, int ms) +{ + pwmout_period_us(obj, ms * 1000); +} + +void pwmout_period_us(pwmout_t* obj, int us) +{ + float seconds = 0; + int cycles = 0; + uint32_t clkdiv = 0; + int i = 0; + float duty_cycle = 0; + + seconds = (float)(us / 1000000.0f); + + // Select highest timer resolution + for (i = 0; i < 7; ++i) { + cycles = (int)(((SystemCoreClock) / prescale_tbl[i]) * seconds); + if (cycles <= MAX_COUNTER_16B) { + clkdiv = i + 1; // range 1:7 + clkdiv <<= 28; + break; + } else { + cycles = MAX_COUNTER_16B; + clkdiv = 7; + clkdiv <<= 28; + } + } + + // Stop timer for setting clock again + obj->channel->RUNC = (T32A_RUN_DISABLE | T32A_COUNT_STOP); + // Restore the duty-cycle + duty_cycle = ((float)(obj->trailing_timing - obj->leading_timing) + / obj->trailing_timing); + + obj->trailing_timing = cycles; + obj->leading_timing = (cycles - (cycles * duty_cycle)); + // Change the source clock division and period + obj->channel->MOD = T32A_MODE_32; + obj->channel->CRC = (clkdiv | T32A_WBF_ENABLE | T32A_RELOAD_TREGx); + obj->channel->OUTCRC0 = T32A_OCR_DISABLE; + obj->channel->OUTCRC1 = (T32A_OCRCMPx0_SET | T32A_OCRCMPx1_CLR); + obj->channel->RGC0 = obj->leading_timing; + obj->channel->RGC1 = obj->trailing_timing; + obj->channel->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_START); // Start count operation +} + +void pwmout_pulsewidth(pwmout_t* obj, float seconds) +{ + pwmout_pulsewidth_us(obj, seconds * 1000000.0f); +} + +void pwmout_pulsewidth_ms(pwmout_t* obj, int ms) +{ + pwmout_pulsewidth_us(obj, ms * 1000); +} + +void pwmout_pulsewidth_us(pwmout_t* obj, int us) +{ + float seconds = 0; + float value = 0; + + seconds = (float)(us / 1000000.0f); + value = (((seconds / obj->period) * 100.0f) / 100.0f); + + pwmout_write(obj, value); +} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/serial_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/serial_api.c new file mode 100644 index 00000000000..bd7385278e5 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/serial_api.c @@ -0,0 +1,371 @@ +/* mbed Microcontroller Library + * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include "serial_api.h" +#include "pinmap.h" +#include "mbed_error.h" +#include "gpio_include.h" +#include "objects.h" + +static const PinMap PinMap_UART_TX[] = { + {PA1, SERIAL_0, PIN_DATA(1, 1)}, + {PJ2, SERIAL_1, PIN_DATA(2, 1)}, + {PL1, SERIAL_2, PIN_DATA(2, 1)}, + {NC, NC, 0} +}; + +static const PinMap PinMap_UART_RX[] = { + {PA2, SERIAL_0, PIN_DATA(1, 0)}, + {PJ1, SERIAL_1, PIN_DATA(2, 0)}, + {PL0, SERIAL_2, PIN_DATA(2, 0)}, + {NC, NC, 0} +}; + +static uint32_t serial_irq_ids[UART_NUM] = {0}; +static uart_irq_handler irq_handler; +int stdio_uart_inited = 0; +serial_t stdio_uart; +static void uart_init(TSB_UART_TypeDef *UARTx, uart_inittypedef_t *InitStruct); +static void uart_get_boudrate_setting(uart_boudrate_t *brddiviser, uint32_t boudrate); +static void uart_swreset(TSB_UART_TypeDef *UARTx); + +void serial_init(serial_t *obj, PinName tx, PinName rx) +{ + int is_stdio_uart = 0; + + UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX); + UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX); + UARTName uart_name = (UARTName)pinmap_merge(uart_tx, uart_rx); + MBED_ASSERT((int)uart_name != NC); + + obj->index = uart_name; + switch (uart_name) { + case SERIAL_0: + obj->UARTx = TSB_UART0; + TSB_CG_FSYSENA_IPENA23 = ENABLE; + TSB_CG_FSYSENA_IPENA00 = ENABLE; + break; + case SERIAL_1: + obj->UARTx = TSB_UART1; + TSB_CG_FSYSENA_IPENA24 = ENABLE; + TSB_CG_FSYSENA_IPENA08 = ENABLE; + TSB_CG_FSYSENA_IPENA09 = ENABLE; + break; + case SERIAL_2: + obj->UARTx = TSB_UART2; + TSB_CG_FSYSENA_IPENA25 = ENABLE; + TSB_CG_FSYSENA_IPENA10 = ENABLE; + break; + default: + error("UART is not available"); + break; + } + + pinmap_pinout(tx, PinMap_UART_TX); + pinmap_pinout(rx, PinMap_UART_RX); + + if (tx != NC && rx != NC) { + obj->uart_config.Mode = UART_ENABLE_RX | UART_ENABLE_TX; + } else { + if (tx != NC) { + obj->uart_config.Mode = UART_ENABLE_TX; + } else { + if (rx != NC) { + obj->uart_config.Mode = UART_ENABLE_RX; + } + } + } + + obj->uart_config.BaudRate = 9600; + obj->uart_config.DataBits = 8; + obj->uart_config.StopBits = 0; + obj->uart_config.Parity = ParityNone; + obj->uart_config.FlowCtrl = FlowControlNone; + + uart_init(obj->UARTx, &obj->uart_config); + is_stdio_uart = (uart_name == STDIO_UART) ? (1) : (0); + + if (is_stdio_uart) { + stdio_uart_inited = 1; + memcpy(&stdio_uart, obj, sizeof(serial_t)); + } +} + +void serial_free(serial_t *obj) +{ + obj->UARTx->TRANS = 0; + obj->UARTx->CR0 = 0; + obj->UARTx->CR1 = 0; + + uart_swreset(obj->UARTx); + + obj->uart_config.BaudRate = 0; + obj->uart_config.DataBits = 0; + obj->uart_config.StopBits = 0; + obj->uart_config.Parity = 0; + obj->uart_config.Mode = 0; + obj->uart_config.FlowCtrl = 0; +} + +void serial_baud(serial_t *obj, int baudrate) +{ + obj->uart_config.BaudRate = baudrate; + uart_init(obj->UARTx, &obj->uart_config); +} + +void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) +{ + MBED_ASSERT((stop_bits == 1) || (stop_bits == 2)); // 0: 1 stop bits, 1: 2 stop bits + MBED_ASSERT((parity == ParityNone) || (parity == ParityOdd) || (parity == ParityEven)); + MBED_ASSERT((data_bits > 6) && (data_bits < 10)); // 0: 7 data bits ... 2: 9 data bits + + obj->uart_config.DataBits = data_bits; + obj->uart_config.StopBits = stop_bits; + obj->uart_config.Parity = parity; + uart_init(obj->UARTx, &obj->uart_config); +} + +void INTUART0TX_IRQHandler(void) +{ + irq_handler(serial_irq_ids[SERIAL_0], TxIrq); +} + +void INTUART0RX_IRQHandler(void) +{ + irq_handler(serial_irq_ids[SERIAL_0], RxIrq); +} + +void INTUART1TX_IRQHandler(void) +{ + irq_handler(serial_irq_ids[SERIAL_1], TxIrq); +} + +void INTUART1RX_IRQHandler(void) +{ + irq_handler(serial_irq_ids[SERIAL_1], RxIrq); +} +void INTUART2TX_IRQHandler(void) +{ + irq_handler(serial_irq_ids[SERIAL_2], TxIrq); +} + +void INTUART2RX_IRQHandler(void) +{ + irq_handler(serial_irq_ids[SERIAL_2], RxIrq); +} + +void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) +{ + irq_handler = handler; + serial_irq_ids[obj->index] = id; +} + +void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) +{ + IRQn_Type irq_n = (IRQn_Type)0; + + switch (obj->index) { + case SERIAL_0: + if (irq == RxIrq) { + irq_n = INTUART0RX_IRQn; + } else { + irq_n = INTUART0TX_IRQn; + } + break; + case SERIAL_1: + if (irq == RxIrq) { + irq_n = INTUART1RX_IRQn; + } else { + irq_n = INTUART1TX_IRQn; + } + break; + case SERIAL_2: + if (irq == RxIrq) { + irq_n = INTUART2RX_IRQn; + } else { + irq_n = INTUART2TX_IRQn; + } + break; + default: + break; + } + NVIC_ClearPendingIRQ(irq_n); + if (enable) { + NVIC_EnableIRQ(irq_n); + } else { + NVIC_DisableIRQ(irq_n); + } +} + +int serial_getc(serial_t *obj) +{ + int data = 0; + + while (!serial_readable(obj)) { // Wait until Rx buffer is full + // Do nothing + } + + if (obj->uart_config.Mode & UART_ENABLE_TX) { + obj->UARTx->TRANS &= 0x0D; + } + + data = data | (obj->UARTx->DR & 0xFFU); + + if (obj->uart_config.Mode & UART_ENABLE_TX) { + obj->UARTx->TRANS |= UART_ENABLE_TX; + } + + return data; +} + +void serial_putc(serial_t *obj, int c) +{ + while (!serial_writable(obj)) { + // Do nothing + } + + if (obj->uart_config.Mode & UART_ENABLE_RX) { + obj->UARTx->TRANS &= 0x0E; + } + + obj->UARTx->DR = c & 0xFFU; + + if (obj->uart_config.Mode & UART_ENABLE_RX) { + obj->UARTx->TRANS |= UART_ENABLE_RX; + } +} + +int serial_readable(serial_t *obj) +{ + int ret = 0; + + if ((obj->UARTx->SR & 0x0000000F) != 0) { + ret = 1; + } + + return ret; +} + +int serial_writable(serial_t *obj) +{ + int ret = 0; + + if ((obj->UARTx->SR & 0x8000) == 0) { + ret = 1; + } + + return ret; +} + +void serial_clear(serial_t *obj) +{ + obj->UARTx->FIFOCLR = 0x03; +} + +void serial_pinout_tx(PinName tx) +{ + pinmap_pinout(tx, PinMap_UART_TX); +} + +void serial_break_set(serial_t *obj) +{ + obj->UARTx->TRANS |= 0x08; +} + +void serial_break_clear(serial_t *obj) +{ + obj->UARTx->TRANS &= ~(0x08); +} + +static void uart_swreset(TSB_UART_TypeDef *UARTx) +{ + while (((UARTx->SWRST) & UARTxSWRST_SWRSTF_MASK) == UARTxSWRST_SWRSTF_RUN) { + // No process + } + + UARTx->SWRST = UARTxSWRST_SWRST_10; + UARTx->SWRST = UARTxSWRST_SWRST_01; + + while (((UARTx->SWRST) & UARTxSWRST_SWRSTF_MASK) == UARTxSWRST_SWRSTF_RUN) { + // No process + } +} + +static void uart_get_boudrate_setting(uart_boudrate_t *brddiviser, uint32_t boudrate) +{ + uint32_t clock = 0; + uint32_t k = 0; + uint64_t tx = 0; + uint64_t work = 1; + uint64_t p_range64 = 0; + uint64_t boud64 = 0; + uint64_t tx64 = 0; + uint64_t work64 = 1; + + SystemCoreClockUpdate(); // Get the peripheral I/O clock frequency + clock = SystemCoreClock; + + tx = (uint64_t)((uint64_t)clock << 6); + tx /= work; + tx64 = (uint64_t)((uint64_t)clock << 8); + tx64 /= work64; + work = ((uint64_t)boudrate); + tx /= work; + tx >>= 4; + + boud64 = (64U * boudrate); + p_range64 = ((boud64 / 100) * 3); + + for (k = UART_RANGE_K_MIN; (k <= UART_RANGE_K_MAX); k++) { + work = tx + k; + if (work >= (uint64_t)((uint64_t)1 << 6)) { + work -= (uint64_t)((uint64_t)1 << 6); + work >>= 6; + if ((UART_RANGE_N_MIN <= (uint32_t)work) && ((uint32_t)work <= UART_RANGE_N_MAX)) { + work64 = work <<6; + work64 = (uint64_t)(work64 + (64 - (uint64_t)k)); + work64 = (tx64 / work64); + if (((boud64 - p_range64) <= work64) && (work64 <= (boud64 + p_range64))) { + brddiviser->brn = work; + brddiviser->brk = k; + break; + } + } + } + } +} + +static void uart_init(TSB_UART_TypeDef *UARTx, uart_inittypedef_t *InitStruct) +{ + uart_boudrate_t UTx_brd = {0}; + uint32_t brk = 0; + uint32_t tmp = 0; + uint32_t parity_check = 0; + uint32_t data_length = 0; + + UARTx->CLK = UART_PLESCALER_1; // Register Setting + uart_get_boudrate_setting(&UTx_brd, InitStruct->BaudRate); + UTx_brd.ken = UART_DIVISION_ENABLE; + brk = (UTx_brd.brk << 16); + UARTx->BRD = (UTx_brd.ken | brk | UTx_brd.brn); + parity_check = (InitStruct->Parity == ParityOdd) ? 1 : ((InitStruct->Parity == ParityEven) ? 3 : 0); + data_length = (InitStruct->DataBits) == 8 ? 1 : (((InitStruct->DataBits) == 7) ? 0 : 2); + tmp = (((InitStruct->FlowCtrl) << 9) | ((InitStruct->StopBits) << 4) | (parity_check << 2) | data_length); + UARTx->CR0 = tmp; + UARTx->CR1 = (UART_RX_FIFO_FILL_LEVEL | UART_TX_INT_ENABLE | UART_RX_INT_ENABLE); + UARTx->FIFOCLR = (UARTxFIFOCLR_TFCLR_CLEAR | UARTxFIFOCLR_RFCLR_CLEAR); + UARTx->TRANS = InitStruct->Mode; +} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/sleep.c b/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/sleep.c new file mode 100644 index 00000000000..9cbfbb6ca84 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/sleep.c @@ -0,0 +1,89 @@ +/* mbed Microcontroller Library + * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "sleep_api.h" +#include "gpio_include.h" + +static void warming_up_time(void); + +void hal_sleep(void) +{ + // Set low power consumption mode IDLE + TSB_CG->STBYCR = CG_STBY_MODE_IDLE; + __DSB(); // Enter idle mode + __WFI(); +} + +void hal_deepsleep(void) +{ + uint32_t tmp = 0; + + TSB_CG_FSYSENB_IPENB31 = ENABLE; + + TSB_SIWD0->EN = DISABLE; + TSB_SIWD0->CR = 0xB1; + + while ((TSB_FC->SR0 & 0x01) != 0x01) { + // Flash wait + } + + while (TSB_CG_WUPHCR_WUEF) { + // Wait for end of Warming-up for IHOSC1 + } + + TSB_CG_WUPHCR_WUCLK = DISABLE; + warming_up_time(); + TSB_CG->STBYCR = CG_STBY_MODE_STOP1; + TSB_CG_PLL0SEL_PLL0SEL = DISABLE; + + while (TSB_CG_PLL0SEL_PLL0ST) { + // Wait for PLL status of fsys until off state(fosc=0) + } + + TSB_CG_PLL0SEL_PLL0ON = DISABLE; // Stop PLL of fsys + TSB_CG_OSCCR_IHOSC1EN = ENABLE; + TSB_CG_OSCCR_OSCSEL = DISABLE; + + while (TSB_CG_OSCCR_OSCF) { + // Wait for fosc status until IHOSC1 = 0 + } + + tmp = TSB_CG->OSCCR; + tmp &= EXTERNEL_OSC_MASK; + TSB_CG->OSCCR = tmp; + TSB_CG_OSCCR_IHOSC2EN = DISABLE; + + while (TSB_CG_OSCCR_IHOSC2F) { + // Wait for status of OFD until off "0" + } + + __DSB(); + __WFI(); +} + +static void warming_up_time(void) +{ + uint32_t work = 0; + uint64_t x = 0; + + x = (uint64_t)(IHOSC_CFG_WARM_UP_TIME * IHOSC_CFG_CLOCK); + x = (uint64_t)(x / (uint64_t)(1000000)); + + work = (uint32_t)x; + work &= (uint32_t)(0xFFFFFFF0); + work <<= 16; + work |= (uint32_t)(TSB_CG->WUPHCR & ~CGWUPHCR_WUPT_HIGH_MASK); + TSB_CG->WUPHCR = work; +} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/spi_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/spi_api.c new file mode 100644 index 00000000000..1ac032fdae2 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/spi_api.c @@ -0,0 +1,259 @@ +/* mbed Microcontroller Library + * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "spi_api.h" +#include "mbed_error.h" +#include "pinmap.h" +#include "gpio_include.h" +#include "txz_tspi.h" + +static const PinMap PinMap_SPI_SCLK[] = { + {PM0, SPI_0, PIN_DATA(3, 2)}, + {PP0, SPI_1, PIN_DATA(1, 2)}, + {NC, NC, 0} +}; + +static const PinMap PinMap_SPI_MOSI[] = { + {PM1, SPI_0, PIN_DATA(3, 1)}, + {PP1, SPI_1, PIN_DATA(1, 1)}, + {NC, NC, 0} +}; + +static const PinMap PinMap_SPI_MISO[] = { + {PM2, SPI_0, PIN_DATA(3, 0)}, + {PP2, SPI_1, PIN_DATA(1, 0)}, + {NC, NC, 0} +}; + +static const PinMap PinMap_SPI_SSEL[] = { + {PM3, SPI_0, PIN_DATA(3, 1)}, + {PL6, SPI_1, PIN_DATA(1, 2)}, + {NC, NC, 0} +}; + +void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) +{ + // Check pin parameters + SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI); + SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO); + SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK); + SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL); + SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso); + SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel); + + obj->module = (SPIName)pinmap_merge(spi_data, spi_sclk); + obj->module = (SPIName)pinmap_merge(spi_data, spi_cntl); + MBED_ASSERT((int)obj->module!= NC); + + // Identify SPI module to use + switch ((int)obj->module) { + case SPI_0: + obj->p_obj.p_instance = TSB_TSPI0; + TSB_CG_FSYSENA_IPENA18 = ENABLE; + TSB_CG_FSYSENA_IPENA11 = ENABLE; + break; + case SPI_1: + obj->p_obj.p_instance = TSB_TSPI1; + TSB_CG_FSYSENA_IPENA19 = ENABLE; + TSB_CG_FSYSENA_IPENA13 = ENABLE; + TSB_CG_FSYSENA_IPENA10 = ENABLE; + break; + default: + error("Cannot found SPI module corresponding with input pins."); + break; + } + + // pin out the spi pins + pinmap_pinout(mosi, PinMap_SPI_MOSI); + pinmap_pinout(miso, PinMap_SPI_MISO); + pinmap_pinout(sclk, PinMap_SPI_SCLK); + + if (ssel != NC) { + pinmap_pinout(ssel, PinMap_SPI_SSEL); + } + + //Control 1 configurations + obj->p_obj.init.id = (uint32_t)obj->module; + obj->p_obj.init.cnt1.trgen = TSPI_TRGEN_DISABLE; // Trigger disabled + obj->p_obj.init.cnt1.trxe = TSPI_DISABLE; // Enable Communication + obj->p_obj.init.cnt1.tspims = TSPI_SPI_MODE; // SPI mode + obj->p_obj.init.cnt1.mstr = TSPI_MASTER_OPEARTION; // master mode operation + obj->p_obj.init.cnt1.tmmd = TSPI_TWO_WAY; // Full-duplex mode (Transmit/receive) + obj->p_obj.init.cnt1.cssel = TSPI_TSPIxCS0_ENABLE; // Chip select of pin CS0 is valid + obj->p_obj.init.cnt1.fc = TSPI_TRANS_RANGE_SINGLE; // transfer single frame at a time continuously + + //Control 2 configurations + obj->p_obj.init.cnt2.tidle = TSPI_TIDLE_HI; + obj->p_obj.init.cnt2.txdemp = TSPI_TXDEMP_HI; // when slave underruns TxD fixed to low + obj->p_obj.init.cnt2.rxdly = TSPI_RXDLY_40MHz_OVER; + obj->p_obj.init.cnt2.til = TSPI_TX_FILL_LEVEL_0; // transmit FIFO Level + obj->p_obj.init.cnt2.ril = TSPI_RX_FILL_LEVEL_1; // receive FIFO Level + obj->p_obj.init.cnt2.inttxwe = TSPI_TX_INT_DISABLE; + obj->p_obj.init.cnt2.intrxwe = TSPI_RX_INT_DISABLE; + obj->p_obj.init.cnt2.inttxfe = TSPI_TX_FIFO_INT_DISABLE; + obj->p_obj.init.cnt2.intrxfe = TSPI_RX_FIFO_INT_DISABLE; + obj->p_obj.init.cnt2.interr = TSPI_ERR_INT_DISABLE; + obj->p_obj.init.cnt2.dmate = TSPI_TX_DMA_INT_DISABLE; + obj->p_obj.init.cnt2.dmare = TSPI_RX_DMA_INT_DISABLE; + + //Control 3 configurations + obj->p_obj.init.cnt3.tfempclr = TSPI_TX_BUFF_CLR_DONE; // transmit buffer clear + obj->p_obj.init.cnt3.rffllclr = TSPI_RX_BUFF_CLR_DONE; // receive buffer clear + + //baudrate settings + spi_frequency(obj, (int)INITIAL_SPI_FREQ); + + //Format Control 0 settings + obj->p_obj.init.fmr0.dir = TSPI_DATA_DIRECTION_MSB; // MSB bit first + obj->p_obj.init.fmr0.fl = TSPI_DATA_LENGTH_8; + obj->p_obj.init.fmr0.fint = TSPI_INTERVAL_TIME_0; + + //Special control on polarity of signal and generation timing + obj->p_obj.init.fmr0.cs3pol = TSPI_TSPIxCS3_NEGATIVE; + obj->p_obj.init.fmr0.cs2pol = TSPI_TSPIxCS2_NEGATIVE; + obj->p_obj.init.fmr0.cs1pol = TSPI_TSPIxCS1_NEGATIVE; + obj->p_obj.init.fmr0.cs0pol = TSPI_TSPIxCS0_NEGATIVE; + + obj->p_obj.init.fmr0.ckpha = TSPI_SERIAL_CK_1ST_EDGE; + obj->p_obj.init.fmr0.ckpol = TSPI_SERIAL_CK_IDLE_LOW; + obj->p_obj.init.fmr0.csint = TSPI_MIN_IDLE_TIME_1; + obj->p_obj.init.fmr0.cssckdl = TSPI_SERIAL_CK_DELAY_1; + obj->p_obj.init.fmr0.sckcsdl = TSPI_NEGATE_1; + + //Format Control 1 settings tspi_fmtr1_t + obj->p_obj.init.fmr1.vpe = TSPI_PARITY_DISABLE; + obj->p_obj.init.fmr1.vpm = TSPI_PARITY_BIT_ODD; + + obj->bits = (uint8_t)TSPI_DATA_LENGTH_8; + //initialize SPI + tspi_init(&obj->p_obj); +} + +void spi_free(spi_t *obj) +{ + tspi_deinit(&obj->p_obj); + obj->module = (SPIName)NC; +} + +void spi_format(spi_t *obj, int bits, int mode, int slave) +{ + MBED_ASSERT((slave == 0U) || (slave == 1U)); // 0: master mode, 1: slave mode + MBED_ASSERT((bits >= 8) && (bits <= 32)); + + obj->bits = bits; + obj->p_obj.init.fmr0.fl = (bits << 24); + + if ((mode >> 1) & 0x1) { + obj->p_obj.init.fmr0.ckpol = TSPI_SERIAL_CK_IDLE_HI; + } else { + obj->p_obj.init.fmr0.ckpol = TSPI_SERIAL_CK_IDLE_LOW; + } + + if (mode & 0x1) { + obj->p_obj.init.fmr0.ckpha = TSPI_SERIAL_CK_2ND_EDGE; + } else { + obj->p_obj.init.fmr0.ckpha = TSPI_SERIAL_CK_1ST_EDGE; + } + + tspi_init(&obj->p_obj); +} + +void spi_frequency(spi_t *obj, int hz) +{ + uint8_t brs = 0; + uint8_t brck = 0; + uint16_t prsck = 1; + uint64_t fscl = 0; + uint64_t tmp_fscl = 0; + uint64_t fx = 0; + uint64_t tmpvar = SystemCoreClock; + + SystemCoreClockUpdate(); + + tmpvar = tmpvar / 2; + + for (prsck = 1; prsck <= 512; prsck *= 2) { + fx = ((uint64_t)tmpvar / prsck); + for (brs = 1; brs <= 16; brs++) { + fscl = fx /brs; + if ((fscl <= (uint64_t)hz) && (fscl > tmp_fscl)) { + tmp_fscl = fscl; + obj->p_obj.init.brd.brck = (brck << 4); + if (brs == 16) { + obj->p_obj.init.brd.brs = 0; + } else { + obj->p_obj.init.brd.brs = brs; + } + } + } + brck ++; + } + tspi_init(&obj->p_obj); +} + +int spi_master_write(spi_t *obj, int value) +{ + uint8_t ret_value = 0; + + tspi_transmit_t send_obj; + tspi_receive_t rec_obj; + + // Transmit data + send_obj.tx8.p_data = (uint8_t *)&value; + send_obj.tx8.num = 1; + tspi_master_write(&obj->p_obj, &send_obj, TIMEOUT); + + // Read received data + rec_obj.rx8.p_data = &ret_value; + rec_obj.rx8.num = 1; + tspi_master_read(&obj->p_obj, &rec_obj, TIMEOUT); + + return ret_value; +} + +int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, + char *rx_buffer, int rx_length, char write_fill) +{ + int total = (tx_length > rx_length) ? tx_length : rx_length; + + for (int i = 0; i < total; i++) { + char out = (i < tx_length) ? tx_buffer[i] : write_fill; + char in = spi_master_write(obj, out); + if (i < rx_length) { + rx_buffer[i] = in; + } + } + + return total; +} + +int spi_busy(spi_t *obj) +{ + int ret = 1; + uint32_t status = 0; + + tspi_get_status(&obj->p_obj, &status); + + if ((status & (TSPI_TX_FLAG_ACTIVE | TSPI_RX_FLAG_ACTIVE)) == 0) { + ret = 0; + } + + return ret; +} + +uint8_t spi_get_module(spi_t *obj) +{ + return (uint8_t)(obj->module); +} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/us_ticker.c b/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/us_ticker.c new file mode 100644 index 00000000000..efdf17dc3da --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/us_ticker.c @@ -0,0 +1,85 @@ +/* mbed Microcontroller Library + * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "us_ticker_api.h" +#include "gpio_include.h" + +static bool us_ticker_inited = false; // Is ticker initialized yet? + +const ticker_info_t* us_ticker_get_info() +{ + static const ticker_info_t info = { + 1248125, // (39.94 MHz / 32 ) + 32 // 32 bit counter + }; + return &info; +} + +void us_ticker_init(void) +{ + if (us_ticker_inited) { + us_ticker_disable_interrupt(); + return; + } + us_ticker_inited = true; + + TSB_CG_FSYSENA_IPENA26 = TXZ_ENABLE; + TSB_T32A0->MOD = T32A_MODE_32; + TSB_T32A0->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_STOP); + TSB_T32A0->CRC = T32A_PRSCLx_32; + TSB_T32A0->IMC = (T32A_IMUFx_MASK_REQ | T32A_IMOFx_MASK_REQ); + TSB_T32A0->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_START); + + NVIC_SetVector(INTT32A00C_IRQn, (uint32_t)us_ticker_irq_handler); + NVIC_EnableIRQ(INTT32A00C_IRQn); +} + +uint32_t us_ticker_read(void) +{ + if (!us_ticker_inited) { + us_ticker_init(); + } + + return (TSB_T32A0->TMRC); +} + +void us_ticker_set_interrupt(timestamp_t timestamp) +{ + NVIC_DisableIRQ(INTT32A00C_IRQn); + TSB_T32A0->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_STOP); + TSB_T32A0->RGC1 = timestamp; + NVIC_EnableIRQ(INTT32A00C_IRQn); + TSB_T32A0->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_START); +} + +void us_ticker_fire_interrupt(void) +{ + NVIC_SetPendingIRQ(INTT32A00C_IRQn); + NVIC_EnableIRQ(INTT32A00C_IRQn); +} + +void us_ticker_disable_interrupt(void) +{ + // Disable interrupts by NVIC + TSB_T32A0->STC = T32A_INT_MASK; + NVIC_ClearPendingIRQ(INTT32A00C_IRQn); + NVIC_DisableIRQ(INTT32A00C_IRQn); +} + +void us_ticker_clear_interrupt(void) +{ + TSB_T32A0->STC = T32A_INT_MASK; + NVIC_ClearPendingIRQ(INTT32A00C_IRQn); +} diff --git a/targets/TARGET_TOSHIBA/mbed_rtx.h b/targets/TARGET_TOSHIBA/mbed_rtx.h index 5445f5b3469..8bbb21b69aa 100644 --- a/targets/TARGET_TOSHIBA/mbed_rtx.h +++ b/targets/TARGET_TOSHIBA/mbed_rtx.h @@ -33,4 +33,12 @@ #endif +#if defined(TARGET_TMPM3H6) + +#ifndef INITIAL_SP +#define INITIAL_SP (0x20004000UL) +#endif + +#endif + #endif // MBED_MBED_RTX_H diff --git a/targets/targets.json b/targets/targets.json index 284f3a7d788..33693017cb2 100755 --- a/targets/targets.json +++ b/targets/targets.json @@ -4303,5 +4303,17 @@ "release_versions": ["5"], "device_name": "M2351KIAAEES", "bootloader_supported": true + }, + "TMPM3H6": { + "inherits": ["Target"], + "core": "Cortex-M3", + "is_disk_virtual": true, + "extra_labels": ["TOSHIBA"], + "macros": ["__TMPM3H6__"], + "supported_toolchains": ["GCC_ARM", "ARM", "IAR"], + "device_has": ["USTICKER", "ANALOGIN", "ANALOGOUT", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "I2C", "I2CSLAVE", "STDIO_MESSAGES"], + "device_name": "TMPM3H6FWFG", + "detect_code": ["7012"], + "release_versions": ["5"] } } diff --git a/tools/export/iar/iar_definitions.json b/tools/export/iar/iar_definitions.json index 39631e98f99..e348a8dad60 100644 --- a/tools/export/iar/iar_definitions.json +++ b/tools/export/iar/iar_definitions.json @@ -278,5 +278,10 @@ "OGChipSelectEditMenu": "TMPM46BF10FG\tToshiba TMPM46BF10FG", "GFPUCoreSlave": 21, "GBECoreSlave": 21 + }, + "TMPM3H6FWFG":{ + "OGChipSelectEditMenu": "TMPM3H6FWFG\tToshiba TMPM3H6FWFG", + "GFPUCoreSlave": 24, + "GBECoreSlave": 24 } }