diff --git a/.gitignore b/.gitignore index f21fdf680..6c2cd7917 100644 --- a/.gitignore +++ b/.gitignore @@ -18,9 +18,11 @@ TAGS /build /Bender.lock /Bender.local +golden_reference_design +ref_design golden.src revised.src cadence_conformal -golden_reference_design synopsys_formality questa_autocheck +reports diff --git a/bhv/cv32e40p_instr_trace.svh b/bhv/cv32e40p_instr_trace.svh index a89ed4e45..355bc7382 100644 --- a/bhv/cv32e40p_instr_trace.svh +++ b/bhv/cv32e40p_instr_trace.svh @@ -1,23 +1,37 @@ -// Copyright (c) 2020 OpenHW Group +// Copyright 2020 Silicon Labs, Inc. // -// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at +// This file, and derivatives thereof are licensed under the +// Solderpad License, Version 2.0 (the "License"). // -// https://solderpad.org/licenses/ +// Use of this file means you agree to the terms and conditions +// of the license and are in full compliance with the License. +// +// You may obtain a copy of the License at: +// +// https://solderpad.org/licenses/SHL-2.0/ // // Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// and hardware implementations thereof distributed under the License +// is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS +// OF ANY KIND, EITHER EXPRESSED OR IMPLIED. +// // See the License for the specific language governing permissions and // limitations under the License. -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 -// Tracer data structures and functions -// -// Contributors: Steve Richmond, Silicon Labs -// Pascal Gouedo, Dolphin Design +//////////////////////////////////////////////////////////////////////////////// +// Engineer: Steve Richmond - steve.richmond@silabs.com // +// // +// Design Name: cv32e40p_tracer data structures // +// Project Name: CV32E40P // +// Language: SystemVerilog // +// // +// Description: Moves the class definition for instr_trace_t out of the // +// tracer module for readability and code partitioning // +// // +// Includes various enhancements to make the instr_trace_t // +// class more comprehensive // +// // +//////////////////////////////////////////////////////////////////////////////// typedef struct { logic [5:0] addr; @@ -35,9 +49,13 @@ typedef struct { class instr_trace_t; time simtime; + time stoptime; + bit external_time; int cycles; + int stopcycles; logic [31:0] pc; logic [31:0] instr; + string ctx; //Used to add context in the trace log file (Canceled, debug, interrput,....) bit compressed; bit wb_bypass; bit misaligned; @@ -56,10 +74,15 @@ class instr_trace_t; regs_read = {}; regs_write = {}; mem_access = {}; + external_time = 0; + stoptime = 0; + stopcycles = 0; endfunction function void init(int unsigned cycles, bit [31:0] pc, bit compressed, bit [31:0] instr); - this.simtime = $time; + if(!this.external_time) begin + this.simtime = $time; + end this.cycles = cycles; this.pc = pc; this.compressed = compressed; @@ -308,7 +331,23 @@ class instr_trace_t; begin string insn_str; // Accumulate writes into a single string to enable single $fwrite - insn_str = $sformatf("%t %15d %h %h %-36s", simtime, cycles, pc, instr, str); + if(simtime < 100ns) begin + insn_str = $sformatf(" %t %15d %h %h %-3s %-36s", simtime, cycles, pc, instr, ctx, str); + end else if (simtime < 1us) begin + insn_str = $sformatf(" %t %15d %h %h %-3s %-36s", simtime, cycles, pc, instr, ctx, str); + end else if (simtime < 10us) begin + insn_str = $sformatf(" %t %15d %h %h %-3s %-36s", simtime, cycles, pc, instr, ctx, str); + end else if (simtime < 100us) begin + insn_str = $sformatf(" %t %15d %h %h %-3s %-36s", simtime, cycles, pc, instr, ctx, str); + end else if (simtime < 1ms) begin + insn_str = $sformatf(" %t %15d %h %h %-3s %-36s", simtime, cycles, pc, instr, ctx, str); + end else if (simtime < 10ms) begin + insn_str = $sformatf(" %t %15d %h %h %-3s %-36s", simtime, cycles, pc, instr, ctx, str); + end else if (simtime < 100ms) begin + insn_str = $sformatf(" %t %15d %h %h %-3s %-36s", simtime, cycles, pc, instr, ctx, str); + end else begin + insn_str = $sformatf("%t %15d %h %h %-3s %-36s", simtime, cycles, pc, instr, ctx, str); + end foreach (regs_write[i]) begin if (regs_write[i].addr != 0) @@ -330,6 +369,12 @@ class instr_trace_t; insn_str = $sformatf("%s PA:%08x", insn_str, mem_acc.addr); end + casex (instr) + INSTR_FDIV: insn_str = $sformatf("%s %15d %t", insn_str, stopcycles, stoptime); + INSTR_FSQRT:insn_str = $sformatf("%s %15d %t", insn_str, stopcycles, stoptime); + default: ; + endcase + $fwrite(f, "%s\n", insn_str); end endfunction @@ -489,7 +534,7 @@ class instr_trace_t; begin mnemonic = {compressed ? "c." : "", mnemonic}; regs_read.push_back('{rs1, rs1_value, 0}); - str = $sformatf("%-16s %s, %0d", mnemonic, regAddrToStr(rs1), $signed(imm_sb_type)); + str = $sformatf("%-16s %s, %0d, %0d", mnemonic, regAddrToStr(rs1), $signed(imm_s2_type), $signed(imm_sb_type)); end endfunction // printSBInstr @@ -587,14 +632,14 @@ class instr_trace_t; // immediate post-incremented load regs_read.push_back('{rs1, rs1_value, 0}); regs_write.push_back('{rs1, 'x, 0}); - str = $sformatf("cv.%-13s %s, %0d(x%0d!)", mnemonic, regAddrToStr(rd), $signed(imm_i_type), rs1); + str = $sformatf("cv.%-13s %s, (x%0d), %0d", mnemonic, regAddrToStr(rd), rs1, $signed(imm_i_type)); end else if (instr[6:0] == OPCODE_CUSTOM_1) begin if (instr[27] == 1'b0) begin // reg-reg post-incremented load regs_read.push_back('{rs2, rs2_value, 0}); regs_read.push_back('{rs1, rs1_value, 0}); regs_write.push_back('{rs1, 'x, 0}); - str = $sformatf("cv.%-13s %s, %s(x%0d!)", mnemonic, regAddrToStr(rd), regAddrToStr(rs2), rs1); + str = $sformatf("cv.%-13s %s, (x%0d), %s", mnemonic, regAddrToStr(rd), rs1, regAddrToStr(rs2)); end else begin // reg-reg indexed load regs_read.push_back('{rs2, rs2_value, 0}); @@ -637,7 +682,7 @@ class instr_trace_t; regs_read.push_back('{rs2, rs2_value, 0}); regs_read.push_back('{rs1, rs1_value, 0}); regs_write.push_back('{rs1, 'x, 0}); - str = $sformatf("cv.%-14s %s, %0d(x%0d!)", mnemonic, regAddrToStr(rs2), $signed(imm_s_type), rs1); + str = $sformatf("cv.%-14s %s, (x%0d), %0d", mnemonic, regAddrToStr(rs2), rs1, $signed(imm_s_type)); end else if (instr[31:28] == 4'b0010) begin if (instr[27] == 1'b0) begin // reg-reg post-incremented store @@ -645,7 +690,7 @@ class instr_trace_t; regs_read.push_back('{rs3, rs3_value, 0}); regs_read.push_back('{rs1, rs1_value, 0}); regs_write.push_back('{rs1, 'x, 0}); - str = $sformatf("cv.%-13s %s, %s(x%0d!)", mnemonic, regAddrToStr(rs2), regAddrToStr(rs3), rs1); + str = $sformatf("cv.%-13s %s, (x%0d), %s", mnemonic, regAddrToStr(rs2), rs1, regAddrToStr(rs3)); end else begin // reg-reg indexed store regs_read.push_back('{rs2, rs2_value, 0}); @@ -757,238 +802,429 @@ class instr_trace_t; else str_hb = ".h"; // set mnemonic - case (instr[31:26]) - 6'b000000: begin + case (instr) + INSTR_CVADDH , + INSTR_CVADDSCH , + INSTR_CVADDSCIH, + INSTR_CVADDB , + INSTR_CVADDSCB , + INSTR_CVADDSCIB : begin mnemonic = "cv.add"; str_imm = $sformatf("0x%0h", imm_vs_type); end - 6'b000010: begin + INSTR_CVSUBH , + INSTR_CVSUBSCH , + INSTR_CVSUBSCIH, + INSTR_CVSUBB , + INSTR_CVSUBSCB , + INSTR_CVSUBSCIB : begin mnemonic = "cv.sub"; str_imm = $sformatf("0x%0h", imm_vs_type); end - 6'b000100: begin + INSTR_CVAVGH , + INSTR_CVAVGSCH , + INSTR_CVAVGSCIH , + INSTR_CVAVGB , + INSTR_CVAVGSCB , + INSTR_CVAVGSCIB : begin mnemonic = "cv.avg"; str_imm = $sformatf("0x%0h", imm_vs_type); end - 6'b000110: begin + INSTR_CVAVGUH , + INSTR_CVAVGUSCH , + INSTR_CVAVGUSCIH, + INSTR_CVAVGUB , + INSTR_CVAVGUSCB , + INSTR_CVAVGUSCIB : begin mnemonic = "cv.avgu"; str_imm = $sformatf("0x%0h", imm_vu_type); end - 6'b001000: begin + INSTR_CVMINH , + INSTR_CVMINSCH , + INSTR_CVMINSCIH, + INSTR_CVMINB , + INSTR_CVMINSCB , + INSTR_CVMINSCIB : begin mnemonic = "cv.min"; str_imm = $sformatf("0x%0h", imm_vs_type); end - 6'b001010: begin + INSTR_CVMINUH , + INSTR_CVMINUSCH , + INSTR_CVMINUSCIH, + INSTR_CVMINUB , + INSTR_CVMINUSCB , + INSTR_CVMINUSCIB : begin mnemonic = "cv.minu"; str_imm = $sformatf("0x%0h", imm_vu_type); end - 6'b001100: begin + INSTR_CVMAXH , + INSTR_CVMAXSCH , + INSTR_CVMAXSCIH , + INSTR_CVMAXB , + INSTR_CVMAXSCB , + INSTR_CVMAXSCIB : begin mnemonic = "cv.max"; str_imm = $sformatf("0x%0h", imm_vs_type); end - 6'b001110: begin + INSTR_CVMAXUH , + INSTR_CVMAXUSCH , + INSTR_CVMAXUSCIH , + INSTR_CVMAXUB , + INSTR_CVMAXUSCB , + INSTR_CVMAXUSCIB : begin mnemonic = "cv.maxu"; str_imm = $sformatf("0x%0h", imm_vu_type); end - 6'b010000: begin + INSTR_CVSRLH , + INSTR_CVSRLSCH , + INSTR_CVSRLSCIH , + INSTR_CVSRLB , + INSTR_CVSRLSCB , + INSTR_CVSRLSCIB : begin mnemonic = "cv.srl"; str_imm = $sformatf("0x%0h", imm_vs_type); end - 6'b010010: begin + INSTR_CVSRAH , + INSTR_CVSRASCH , + INSTR_CVSRASCIH, + INSTR_CVSRAB , + INSTR_CVSRASCB , + INSTR_CVSRASCIB : begin mnemonic = "cv.sra"; str_imm = $sformatf("0x%0h", imm_vs_type); end - 6'b010100: begin + INSTR_CVSLLH , + INSTR_CVSLLSCH , + INSTR_CVSLLSCIH, + INSTR_CVSLLB , + INSTR_CVSLLSCB , + INSTR_CVSLLSCIB : begin mnemonic = "cv.sll"; str_imm = $sformatf("0x%0h", imm_vs_type); end - 6'b010110: begin + INSTR_CVORH , + INSTR_CVORSCH , + INSTR_CVORSCIH, + INSTR_CVORB , + INSTR_CVORSCB , + INSTR_CVORSCIB : begin mnemonic = "cv.or"; str_imm = $sformatf("0x%0h", imm_vs_type); end - 6'b011000: begin + INSTR_CVXORH , + INSTR_CVXORSCH , + INSTR_CVXORSCIH , + INSTR_CVXORB , + INSTR_CVXORSCB , + INSTR_CVXORSCIB : begin mnemonic = "cv.xor"; str_imm = $sformatf("0x%0h", imm_vs_type); end - 6'b011010: begin + INSTR_CVANDH , + INSTR_CVANDSCH , + INSTR_CVANDSCIH , + INSTR_CVANDB , + INSTR_CVANDSCB , + INSTR_CVANDSCIB : begin mnemonic = "cv.and"; str_imm = $sformatf("0x%0h", imm_vs_type); end - 6'b011100: begin + INSTR_CVABSH, + INSTR_CVABSB : begin mnemonic = "cv.abs"; str_imm = $sformatf("0x%0h", imm_vs_type); end // dot products - 6'b100000: begin + INSTR_CVDOTUPH , + INSTR_CVDOTUPSCH , + INSTR_CVDOTUPSCIH, + INSTR_CVDOTUPB , + INSTR_CVDOTUPSCB , + INSTR_CVDOTUPSCIB : begin mnemonic = "cv.dotup"; str_imm = $sformatf("0x%0h", imm_vu_type); end - 6'b100010: begin + INSTR_CVDOTUSPH , + INSTR_CVDOTUSPSCH , + INSTR_CVDOTUSPSCIH, + INSTR_CVDOTUSPB , + INSTR_CVDOTUSPSCB , + INSTR_CVDOTUSPSCIB : begin mnemonic = "cv.dotusp"; str_imm = $sformatf("0x%0h", imm_vs_type); end - 6'b100100: begin + INSTR_CVDOTSPH , + INSTR_CVDOTSPSCH , + INSTR_CVDOTSPSCIH, + INSTR_CVDOTSPB , + INSTR_CVDOTSPSCB , + INSTR_CVDOTSPSCIB : begin mnemonic = "cv.dotsp"; str_imm = $sformatf("0x%0h", imm_vs_type); end - 6'b100110: begin + INSTR_CVSDOTUPH , + INSTR_CVSDOTUPSCH , + INSTR_CVSDOTUPSCIH, + INSTR_CVSDOTUPB , + INSTR_CVSDOTUPSCB , + INSTR_CVSDOTUPSCIB : begin mnemonic = "cv.sdotup"; str_imm = $sformatf("0x%0h", imm_vu_type); end - 6'b101000: begin + INSTR_CVSDOTUSPH , + INSTR_CVSDOTUSPSCH , + INSTR_CVSDOTUSPSCIH, + INSTR_CVSDOTUSPB , + INSTR_CVSDOTUSPSCB , + INSTR_CVSDOTUSPSCIB : begin mnemonic = "cv.sdotusp"; str_imm = $sformatf("0x%0h", imm_vs_type); end - 6'b101010: begin + INSTR_CVSDOTSPH , + INSTR_CVSDOTSPSCH , + INSTR_CVSDOTSPSCIH, + INSTR_CVSDOTSPB , + INSTR_CVSDOTSPSCB , + INSTR_CVSDOTSPSCIB : begin mnemonic = "cv.sdotsp"; str_imm = $sformatf("0x%0h", imm_vs_type); end - 6'b101110: begin - case (instr[14:13]) - 2'b00 : begin - mnemonic = "cv.extract"; - str_imm = $sformatf("0x%0h", imm_vs_type); - end - 2'b01 : begin - mnemonic = "cv.extractu"; - str_imm = $sformatf("0x%0h", imm_vu_type); - end - 2'b10 : begin - mnemonic = "cv.insert"; - str_imm = $sformatf("0x%0h", imm_vs_type); - end - endcase - str_sci = ""; + INSTR_CVEXTRACTH, + INSTR_CVEXTRACTB : begin + mnemonic = "cv.extract"; + str_imm = $sformatf("0x%0h", imm_vs_type); + str_sci = ""; + end + INSTR_CVEXTRACTUH, + INSTR_CVEXTRACTUB : begin + mnemonic = "cv.extractu"; + str_imm = $sformatf("0x%0h", imm_vu_type); + str_sci = ""; + end + INSTR_CVINSERTH, + INSTR_CVINSERTB : begin + mnemonic = "cv.insert"; + str_imm = $sformatf("0x%0h", imm_vs_type); + str_sci = ""; end // shuffle/pack - 6'b110000: begin - if (instr[14:12] == 3'b111) begin - mnemonic = "cv.shuffleI0"; - str_imm = $sformatf("0x%8h", imm_shuffle_type); - end else begin + INSTR_CVSHUFFLEH , + INSTR_CVSHUFFLESCIH, + INSTR_CVSHUFFLEB : begin mnemonic = "cv.shuffle"; if (instr[14:12] == 3'b110) begin str_imm = $sformatf("0x%8h", imm_shuffle_type); end - end end - 6'b110010: begin + + INSTR_CVSHUFFLEL0SCIB : begin + mnemonic = "cv.shuffleI0"; + str_imm = $sformatf("0x%8h", imm_shuffle_type); + end + INSTR_CVSHUFFLEL1SCIB : begin mnemonic = "cv.shuffleI1"; str_imm = $sformatf("0x%8h", imm_shuffle_type); end - 6'b110100: begin + INSTR_CVSHUFFLEL2SCIB : begin mnemonic = "cv.shuffleI2"; str_imm = $sformatf("0x%8h", imm_shuffle_type); end - 6'b110110: begin + INSTR_CVSHUFFLEL3SCIB : begin mnemonic = "cv.shuffleI3"; str_imm = $sformatf("0x%8h", imm_shuffle_type); end - 6'b111000: begin + INSTR_CVSHUFFLE2H, + INSTR_CVSHUFFLE2B : begin mnemonic = "cv.shuffle2"; end - 6'b111100: begin + INSTR_CVPACK, + INSTR_CVPACKH : begin mnemonic = "cv.pack"; if (instr[25] == 1'b0) begin str_hb = ""; end end - 6'b111110: begin - mnemonic = instr[25] ? "cv.packhi" : "cv.packlo"; - end + INSTR_CVPACKHIB : mnemonic = "cv.packhi"; + INSTR_CVPACKLOB : mnemonic = "cv.packlo"; // comparisons - 6'b000001: begin + INSTR_CVCMPEQH , + INSTR_CVCMPEQSCH , + INSTR_CVCMPEQSCIH, + INSTR_CVCMPEQB , + INSTR_CVCMPEQSCB , + INSTR_CVCMPEQSCIB : begin mnemonic = "cv.cmpeq"; str_imm = $sformatf("0x%0h", imm_vs_type); end - 6'b000011: begin + INSTR_CVCMPNEH , + INSTR_CVCMPNESCH , + INSTR_CVCMPNESCIH, + INSTR_CVCMPNEB , + INSTR_CVCMPNESCB , + INSTR_CVCMPNESCIB : begin mnemonic = "cv.cmpne"; str_imm = $sformatf("0x%0h", imm_vs_type); end - 6'b000101: begin + INSTR_CVCMPGTH , + INSTR_CVCMPGTSCH , + INSTR_CVCMPGTSCIH, + INSTR_CVCMPGTB , + INSTR_CVCMPGTSCB , + INSTR_CVCMPGTSCIB : begin mnemonic = "cv.cmpgt"; str_imm = $sformatf("0x%0h", imm_vs_type); end - 6'b000111: begin + INSTR_CVCMPGEH , + INSTR_CVCMPGESCH , + INSTR_CVCMPGESCIH, + INSTR_CVCMPGEB , + INSTR_CVCMPGESCB , + INSTR_CVCMPGESCIB : begin mnemonic = "cv.cmpge"; str_imm = $sformatf("0x%0h", imm_vs_type); end - 6'b001001: begin + INSTR_CVCMPLTH , + INSTR_CVCMPLTSCH , + INSTR_CVCMPLTSCIH, + INSTR_CVCMPLTB , + INSTR_CVCMPLTSCB , + INSTR_CVCMPLTSCIB : begin mnemonic = "cv.cmplt"; str_imm = $sformatf("0x%0h", imm_vs_type); end - 6'b001011: begin + INSTR_CVCMPLEH , + INSTR_CVCMPLESCH , + INSTR_CVCMPLESCIH, + INSTR_CVCMPLEB , + INSTR_CVCMPLESCB , + INSTR_CVCMPLESCIB : begin mnemonic = "cv.cmple"; str_imm = $sformatf("0x%0h", imm_vs_type); end - 6'b001101: begin + INSTR_CVCMPGTUH , + INSTR_CVCMPGTUSCH , + INSTR_CVCMPGTUSCIH, + INSTR_CVCMPGTUB , + INSTR_CVCMPGTUSCB , + INSTR_CVCMPGTUSCIB : begin mnemonic = "cv.cmpgtu"; str_imm = $sformatf("0x%0h", imm_vu_type); end - 6'b001111: begin + INSTR_CVCMPGEUH , + INSTR_CVCMPGEUSCH , + INSTR_CVCMPGEUSCIH, + INSTR_CVCMPGEUB , + INSTR_CVCMPGEUSCB , + INSTR_CVCMPGEUSCIB : begin mnemonic = "cv.cmpgeu"; str_imm = $sformatf("0x%0h", imm_vu_type); end - 6'b010001: begin + INSTR_CVCMPLTUH , + INSTR_CVCMPLTUSCH , + INSTR_CVCMPLTUSCIH, + INSTR_CVCMPLTUB , + INSTR_CVCMPLTUSCB , + INSTR_CVCMPLTUSCIB : begin mnemonic = "cv.cmpltu"; str_imm = $sformatf("0x%0h", imm_vu_type); end - 6'b010011: begin + INSTR_CVCMPLEUH , + INSTR_CVCMPLEUSCH , + INSTR_CVCMPLEUSCIH, + INSTR_CVCMPLEUB , + INSTR_CVCMPLEUSCB , + INSTR_CVCMPLEUSCIB : begin mnemonic = "cv.cmpleu"; str_imm = $sformatf("0x%0h", imm_vu_type); end - 6'b010101: begin - unique case (instr[14:13]) - 2'b00: mnemonic = instr[25] == 1'b0 ? "cv.cplxmul.r" : "cv.cplxmul.i"; - 2'b01: mnemonic = instr[25] == 1'b0 ? "cv.cplxmul.r.div2" : "cv.cplxmul.i.div2"; - 2'b10: mnemonic = instr[25] == 1'b0 ? "cv.cplxmul.r.div4" : "cv.cplxmul.i.div4"; - 2'b11: mnemonic = instr[25] == 1'b0 ? "cv.cplxmul.r.div8" : "cv.cplxmul.i.div8"; - endcase + INSTR_CVCPLXMULR, + INSTR_CVCPLXMULI : begin + mnemonic = instr[25] == 1'b0 ? "cv.cplxmul.r" : "cv.cplxmul.i"; str_sci = ""; str_hb = ""; end - - 6'b010111: begin - mnemonic = "cv.cplxconj"; - str_sci = ""; + INSTR_CVCPLXMULRDIV2, + INSTR_CVCPLXMULIDIV2 : begin + mnemonic = instr[25] == 1'b0 ? "cv.cplxmul.r.div2" : "cv.cplxmul.i.div2"; + str_sci = ""; str_hb = ""; end - - 6'b011001: begin - unique case (instr[14:13]) - 2'b00: mnemonic = "cv.subrotmj"; - 2'b01: mnemonic = "cv.subrotmj.div2"; - 2'b10: mnemonic = "cv.subrotmj.div4"; - 2'b11: mnemonic = "cv.subrotmj.div8"; - endcase + INSTR_CVCPLXMULRDIV4, + INSTR_CVCPLXMULIDIV4 : begin + mnemonic = instr[25] == 1'b0 ? "cv.cplxmul.r.div4" : "cv.cplxmul.i.div4"; str_sci = ""; str_hb = ""; end - - 6'b011011: begin - unique case (instr[14:13]) - 2'b01: mnemonic = "cv.add.div2"; - 2'b10: mnemonic = "cv.add.div4"; - 2'b11: mnemonic = "cv.add.div8"; - endcase + INSTR_CVCPLXMULRDIV8, + INSTR_CVCPLXMULIDIV8 : begin + mnemonic = instr[25] == 1'b0 ? "cv.cplxmul.r.div8" : "cv.cplxmul.i.div8"; str_sci = ""; str_hb = ""; end - 6'b011101: begin - unique case (instr[14:13]) - 2'b01: mnemonic = "cv.sub.div2"; - 2'b10: mnemonic = "cv.sub.div4"; - 2'b11: mnemonic = "cv.sub.div8"; - endcase - str_sci = ""; + INSTR_CVCPLXCONJ : begin + mnemonic = "cv.cplxconj"; + str_sci = ""; str_hb = ""; end + INSTR_CVSUBROTMJ : begin + mnemonic = "cv.subrotmj"; + str_sci = ""; + str_hb = ""; + end + INSTR_CVSUBROTMJDIV2 : begin + mnemonic = "cv.subrotmj.div2"; + str_sci = ""; + str_hb = ""; + end + INSTR_CVSUBROTMJDIV4 : begin + mnemonic = "cv.subrotmj.div4"; + str_sci = ""; + str_hb = ""; + end + INSTR_CVSUBROTMJDIV8 : begin + mnemonic = "cv.subrotmj.div8"; + str_sci = ""; + str_hb = ""; + end + + INSTR_CVADDIV2 : begin + mnemonic = "cv.add.div2"; + str_sci = ""; + str_hb = ""; + end + INSTR_CVADDIV4 : begin + mnemonic = "cv.add.div4"; + str_sci = ""; + str_hb = ""; + end + INSTR_CVADDIV8 : begin + mnemonic = "cv.add.div8"; + str_sci = ""; + str_hb = ""; + end + + INSTR_CVSUBIV2 : begin + mnemonic = "cv.sub.div2"; + str_sci = ""; + str_hb = ""; + end + INSTR_CVSUBIV4 : begin + mnemonic = "cv.sub.div4"; + str_sci = ""; + str_hb = ""; + end + INSTR_CVSUBIV8 : begin + mnemonic = "cv.sub.div8"; + str_sci = ""; + str_hb = ""; + end + default: begin printMnemonic("INVALID"); return; diff --git a/bhv/cv32e40p_rvfi.sv b/bhv/cv32e40p_rvfi.sv index 13a5beb00..99429d90d 100644 --- a/bhv/cv32e40p_rvfi.sv +++ b/bhv/cv32e40p_rvfi.sv @@ -1,24 +1,28 @@ -// Copyright (c) 2020 OpenHW Group +// Copyright 2024 Dolphin Design +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 // -// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. +// Licensed under the Solderpad Hardware License v 2.1 (the "License"); +// you may not use this file except in compliance with the License, or, +// at your option, the Apache License version 2.0. // You may obtain a copy of the License at // -// https://solderpad.org/licenses/ +// https://solderpad.org/licenses/SHL-2.1/ // -// Unless required by applicable law or agreed to in writing, software +// Unless required by applicable law or agreed to in writing, any work // distributed under the License is distributed on an "AS IS" BASIS, // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 -// CV32E40P RVFI interface -// -// Contributors: Davide Schiavone, OpenHW Group -// Halfdan Bechmann, Silicon Labs -// Yoann Pruvost, Dolphin Design +//////////////////////////////////////////////////////////////////////////////////// +// // +// Contributors: Davide Schiavone, OpenHW Group // +// Halfdan Bechmann, Silicon Labs // +// Yoann Pruvost, Dolphin Design // +// // +// Description: CV32E40P RVFI interface // +// // +//////////////////////////////////////////////////////////////////////////////////// `include "cv32e40p_rvfi_pkg.sv" @@ -27,7 +31,8 @@ module cv32e40p_rvfi import cv32e40p_rvfi_pkg::*; #( parameter FPU = 0, - parameter ZFINX = 0 + parameter ZFINX = 0, + parameter NUM_MHPMCOUNTERS = 1 ) ( input logic clk_i, input logic rst_ni, @@ -290,7 +295,7 @@ module cv32e40p_rvfi // performance counters // cycle, instret, hpcounter, cycleh, instreth, hpcounterh // mcycle, minstret, mhpcounter, mcycleh, minstreth, mhpcounterh - input logic [31:0][MHPMCOUNTER_WIDTH-1:0] csr_mhpmcounter_q_i, + input logic [63:0][MHPMCOUNTER_WIDTH-1:0] csr_mhpmcounter_q_i, input logic [31:0] csr_mhpmcounter_write_lower_i, input logic [31:0] csr_mhpmcounter_write_upper_i, @@ -327,6 +332,10 @@ module cv32e40p_rvfi // the convention of RISC-V Formal Interface Specification. output logic [ 0:0] rvfi_valid, output logic [63:0] rvfi_order, + output integer rvfi_start_cycle, + output time rvfi_start_time, + output integer rvfi_stop_cycle, + output time rvfi_stop_time, output logic [31:0] rvfi_insn, output rvfi_trap_t rvfi_trap, output logic [ 0:0] rvfi_halt, @@ -346,6 +355,7 @@ module cv32e40p_rvfi output logic rvfi_frd_wvalid [1:0], output logic [ 4:0] rvfi_frd_addr [1:0], output logic [31:0] rvfi_frd_wdata [1:0], + output logic rvfi_2_rd, output logic [ 4:0] rvfi_rs1_addr, output logic [ 4:0] rvfi_rs2_addr, output logic [ 4:0] rvfi_rs3_addr, @@ -366,8 +376,8 @@ module cv32e40p_rvfi output logic [31:0] rvfi_pc_wdata, output logic [31:0] rvfi_mem_addr, - output logic [ 3:0] rvfi_mem_rmask, - output logic [ 3:0] rvfi_mem_wmask, + output logic [31:0] rvfi_mem_rmask, + output logic [31:0] rvfi_mem_wmask, output logic [31:0] rvfi_mem_rdata, output logic [31:0] rvfi_mem_wdata, @@ -618,6 +628,13 @@ module cv32e40p_rvfi bit clk_i_d; assign #0.01 clk_i_d = clk_i; + integer cycles; + // cycle counter + always_ff @(posedge clk_i_d, negedge rst_ni) begin + if (rst_ni == 1'b0) cycles <= 0; + else cycles <= cycles + 1; + end + logic pc_mux_debug; logic pc_mux_dret; logic pc_mux_exception; @@ -626,6 +643,9 @@ module cv32e40p_rvfi logic pc_mux_nmi; localparam logic [31:0] MSTATUS_WRITE_MASK = 32'h0000_6088; + localparam logic [31:0] MCOUNTINHIBIT_WRITE_MASK = {{(29-NUM_MHPMCOUNTERS){1'b0}}, {(NUM_MHPMCOUNTERS){1'b1}}, 3'b101}; + localparam NUM_HPM_EVENTS = 16; + localparam logic [31:0] MHPMEVENT_WRITE_MASK = {{(31-NUM_HPM_EVENTS){1'b0}}, {(NUM_HPM_EVENTS){1'b1}}}; `include "pipe_freeze_trace.sv" @@ -747,6 +767,10 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb; end rvfi_order = new_rvfi_trace.m_order; + rvfi_start_cycle = new_rvfi_trace.m_start_cycle; + rvfi_start_time = new_rvfi_trace.m_start_time; + rvfi_stop_cycle = new_rvfi_trace.m_stop_cycle; + rvfi_stop_time = new_rvfi_trace.m_stop_time; rvfi_pc_rdata = new_rvfi_trace.m_pc_rdata; rvfi_insn = new_rvfi_trace.m_insn; @@ -801,6 +825,7 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb; rvfi_frd_addr[1] = '0; rvfi_frd_wdata[1] = '0; + rvfi_2_rd = new_rvfi_trace.m_2_rd_insn; if (new_rvfi_trace.m_rd_addr[0][5] == 1'b0) begin rvfi_rd_addr[0] = new_rvfi_trace.m_rd_addr[0][4:0]; rvfi_rd_wdata[0] = new_rvfi_trace.m_rd_wdata[0]; @@ -905,15 +930,50 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb; `SET_RVFI_CSR_FROM_INSN(misa) `SET_RVFI_CSR_FROM_INSN(mie) `SET_RVFI_CSR_FROM_INSN(mtvec) - `SET_RVFI_CSR_FROM_INSN(mcountinhibit) + + rvfi_csr_mcountinhibit_rdata = new_rvfi_trace.m_csr.mcountinhibit_rdata; + rvfi_csr_mcountinhibit_rmask = new_rvfi_trace.m_csr.mcountinhibit_rmask; + rvfi_csr_mcountinhibit_wdata = new_rvfi_trace.m_csr.mcountinhibit_wdata; + rvfi_csr_mcountinhibit_wmask = new_rvfi_trace.m_csr.mcountinhibit_wmask & MCOUNTINHIBIT_WRITE_MASK; + `SET_RVFI_CSR_FROM_INSN(mscratch) `SET_RVFI_CSR_FROM_INSN(mepc) `SET_RVFI_CSR_FROM_INSN(mcause) + `SET_RVFI_CSR_FROM_INSN(mcycle) `SET_RVFI_CSR_FROM_INSN(minstret) + `SET_RVFI_CSR_FROM_INSN(minstreth) + + // `SET_RVFI_CSR_FROM_INSN(cycle) + // `SET_RVFI_CSR_FROM_INSN(instret) + rvfi_csr_instret_rdata = new_rvfi_trace.m_csr.minstret_rdata; + rvfi_csr_instret_rmask = new_rvfi_trace.m_csr.minstret_rmask; + rvfi_csr_instret_wdata = new_rvfi_trace.m_csr.minstret_wdata; + rvfi_csr_instret_wmask = new_rvfi_trace.m_csr.minstret_wmask; + + for(int idx=3; idx<32; idx++) begin + rvfi_csr_mhpmcounter_rmask[idx] = new_rvfi_trace.m_csr.mhpmcounter_rmask[idx][31:0]; + rvfi_csr_mhpmcounter_wmask[idx] = new_rvfi_trace.m_csr.mhpmcounter_wmask[idx][31:0]; + rvfi_csr_mhpmcounter_rdata[idx] = new_rvfi_trace.m_csr.mhpmcounter_rdata[idx][31:0]; + rvfi_csr_mhpmcounter_wdata[idx] = new_rvfi_trace.m_csr.mhpmcounter_wdata[idx][31:0]; + + rvfi_csr_mhpmcounterh_rmask[idx] = new_rvfi_trace.m_csr.mhpmcounter_rmask[idx][63:32]; + rvfi_csr_mhpmcounterh_wmask[idx] = new_rvfi_trace.m_csr.mhpmcounter_wmask[idx][63:32]; + rvfi_csr_mhpmcounterh_rdata[idx] = new_rvfi_trace.m_csr.mhpmcounter_rdata[idx][63:32]; + rvfi_csr_mhpmcounterh_wdata[idx] = new_rvfi_trace.m_csr.mhpmcounter_wdata[idx][63:32]; + + rvfi_csr_mhpmevent_rmask[idx] = new_rvfi_trace.m_csr.mhpmevent_rmask[idx]; + rvfi_csr_mhpmevent_wmask[idx] = new_rvfi_trace.m_csr.mhpmevent_wmask[idx] & MHPMEVENT_WRITE_MASK; + rvfi_csr_mhpmevent_rdata[idx] = new_rvfi_trace.m_csr.mhpmevent_rdata[idx]; + rvfi_csr_mhpmevent_wdata[idx] = new_rvfi_trace.m_csr.mhpmevent_wdata[idx]; + end + // `SET_RVFI_CSR_FROM_INSN(instreth) + rvfi_csr_instreth_rdata = new_rvfi_trace.m_csr.minstreth_rdata; + rvfi_csr_instreth_rmask = new_rvfi_trace.m_csr.minstreth_rmask; + rvfi_csr_instreth_wdata = new_rvfi_trace.m_csr.minstreth_wdata; + rvfi_csr_instreth_wmask = new_rvfi_trace.m_csr.minstreth_wmask; + `SET_RVFI_CSR_FROM_INSN(mip) - // if(rvfi_order == 64'h00000000_00000167) begin - // rvfi_csr_mip_rdata = 32'h0010_0000; - // end + rvfi_csr_tdata_rdata[0] = 'Z; rvfi_csr_tdata_rmask[0] = '0; // Does not exist rvfi_csr_tdata_wdata[0] = 'Z; // Does not exist @@ -959,36 +1019,134 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb; endfunction // set_rvfi - function void minstret_to_id(); - trace_id.m_csr.minstret_we = r_pipe_freeze_trace.csr.mhpmcounter_write_lower[2]; - trace_id.m_csr.minstret_rdata = r_pipe_freeze_trace.csr.mhpmcounter_q[2]; - trace_id.m_csr.minstret_rmask = '1; - trace_id.m_csr.minstret_wdata = r_pipe_freeze_trace.csr.mhpmcounter_q; - trace_id.m_csr.minstret_wmask = r_pipe_freeze_trace.csr.mhpmcounter_write_lower[2] ? '1 : '0; + function void sample_perf_counter_to_id(int idx); + trace_id.m_csr.mhpmcounter_rdata[idx][31:0] = r_pipe_freeze_trace.csr.mhpmcounter_q[idx][31:0]; + trace_id.m_csr.mhpmcounter_rmask[idx][31:0] = '1; + endfunction + + function void perf_counter_to_id(int idx); + if(!trace_id.m_csr.mhpmcounter_we[idx][0]) begin + trace_id.m_csr.mhpmcounter_wdata[idx][31:0] = r_pipe_freeze_trace.csr.wdata_int; + end + if(r_pipe_freeze_trace.csr.mhpmcounter_write_lower[idx]) begin + trace_id.m_csr.mhpmcounter_we[idx][0] = r_pipe_freeze_trace.csr.mhpmcounter_write_lower[idx]; + trace_id.m_csr.mhpmcounter_wdata[idx][31:0] = r_pipe_freeze_trace.csr.wdata_int; + trace_id.m_csr.mhpmcounter_wmask[idx][31:0] = r_pipe_freeze_trace.csr.mhpmcounter_write_lower[idx] ? '1 : '0; + end + sample_perf_counter_to_id(idx); + endfunction + + function void sample_perf_event_to_trace(int idx, insn_trace_t m_trace); + m_trace.m_csr.mhpmevent_rdata[idx] = r_pipe_freeze_trace.csr.mhpmevent_q[idx]; + m_trace.m_csr.mhpmevent_rmask[idx] = '1; + endfunction + + function void perf_event_to_trace(int idx, insn_trace_t m_trace); + if(!m_trace.m_csr.mhpmevent_we[idx]) begin + m_trace.m_csr.mhpmevent_wdata[idx] = r_pipe_freeze_trace.csr.wdata_int; + end + if(r_pipe_freeze_trace.csr.mhpmevent_we[idx]) begin + m_trace.m_csr.mhpmevent_we[idx] = r_pipe_freeze_trace.csr.mhpmevent_we[idx]; + m_trace.m_csr.mhpmevent_wdata[idx] = r_pipe_freeze_trace.csr.wdata_int; + m_trace.m_csr.mhpmevent_wmask[idx] = r_pipe_freeze_trace.csr.mhpmevent_we[idx] ? '1 : '0; + end + sample_perf_event_to_trace(idx, m_trace); + endfunction + + function void sample_minstret_to_trace(insn_trace_t m_trace); + m_trace.m_csr.minstret_rdata = r_pipe_freeze_trace.csr.mhpmcounter_q[2][31:0]; + m_trace.m_csr.minstret_rmask = '1; + endfunction + + function void minstret_to_trace(insn_trace_t m_trace); + if(!m_trace.m_csr.minstret_we) begin + m_trace.m_csr.minstret_wdata = r_pipe_freeze_trace.csr.wdata_int; + end + if(r_pipe_freeze_trace.csr.mhpmcounter_write_lower[2]) begin + m_trace.m_csr.minstret_we = r_pipe_freeze_trace.csr.mhpmcounter_write_lower[2]; + m_trace.m_csr.minstret_wdata = r_pipe_freeze_trace.csr.wdata_int; + m_trace.m_csr.minstret_wmask = r_pipe_freeze_trace.csr.mhpmcounter_write_lower[2] ? '1 : '0; + end + sample_minstret_to_trace(m_trace); + endfunction + + function void sample_perf_counter_h_to_id(int idx); + trace_id.m_csr.mhpmcounter_rdata[idx][63:32] = r_pipe_freeze_trace.csr.mhpmcounter_q[idx][63:0]; + trace_id.m_csr.mhpmcounter_rmask[idx][63:32] = '1; + endfunction + + function void perf_counter_h_to_id(int idx); + if(!trace_id.m_csr.mhpmcounter_we[idx][1]) begin + trace_id.m_csr.mhpmcounter_wdata[idx][63:32] = r_pipe_freeze_trace.csr.wdata_int; + end + if(r_pipe_freeze_trace.csr.mhpmcounter_write_lower[idx]) begin + trace_id.m_csr.mhpmcounter_we[idx][1] = r_pipe_freeze_trace.csr.mhpmcounter_write_lower[idx]; + trace_id.m_csr.mhpmcounter_wdata[idx][63:32] = r_pipe_freeze_trace.csr.wdata_int; + trace_id.m_csr.mhpmcounter_wmask[idx][63:32] = r_pipe_freeze_trace.csr.mhpmcounter_write_lower[idx] ? '1 : '0; + end + sample_perf_counter_h_to_id(idx); + endfunction + + function void sample_minstreth_to_trace(insn_trace_t m_trace); + m_trace.m_csr.minstreth_rdata = r_pipe_freeze_trace.csr.mhpmcounter_q[2][63:32]; + m_trace.m_csr.minstreth_rmask = '1; endfunction - function void minstret_to_ex(); - trace_ex.m_csr.minstret_we = r_pipe_freeze_trace.csr.mhpmcounter_write_lower[2]; - trace_ex.m_csr.minstret_rdata = r_pipe_freeze_trace.csr.mhpmcounter_q[2]; - trace_ex.m_csr.minstret_rmask = '1; - trace_ex.m_csr.minstret_wdata = r_pipe_freeze_trace.csr.mhpmcounter_q; - trace_ex.m_csr.minstret_wmask = r_pipe_freeze_trace.csr.mhpmcounter_write_lower[2] ? '1 : '0; + function void sample_mcycle_to_trace(insn_trace_t m_trace); + m_trace.m_csr.mcycle_we = r_pipe_freeze_trace.csr.mhpmcounter_write_lower[0]; + m_trace.m_csr.mcycle_rdata = r_pipe_freeze_trace.csr.mhpmcounter_q[0][31:0]; + m_trace.m_csr.mcycle_rmask = '1; + m_trace.m_csr.mcycle_wdata = r_pipe_freeze_trace.csr.mhpmcounter_q[31:0]; + m_trace.m_csr.mcycle_wmask = r_pipe_freeze_trace.csr.mhpmcounter_write_lower[0] ? '1 : '0; endfunction - function void tinfo_to_id(); - trace_id.m_csr.tinfo_we = '0; // READ ONLY csr_tinfo_we_i; - trace_id.m_csr.tinfo_rdata = r_pipe_freeze_trace.csr.tinfo_q; - trace_id.m_csr.tinfo_rmask = '1; - trace_id.m_csr.tinfo_wdata = r_pipe_freeze_trace.csr.tinfo_n; - trace_id.m_csr.tinfo_wmask = '0; + function void minstreth_to_trace(insn_trace_t m_trace); + if(!m_trace.m_csr.minstreth_we) begin + m_trace.m_csr.minstreth_wdata = r_pipe_freeze_trace.csr.wdata_int; + end + if(r_pipe_freeze_trace.csr.mhpmcounter_write_upper[2]) begin + m_trace.m_csr.minstreth_we = r_pipe_freeze_trace.csr.mhpmcounter_write_upper[2]; + m_trace.m_csr.minstreth_wdata = r_pipe_freeze_trace.csr.wdata_int; + m_trace.m_csr.minstreth_wmask = r_pipe_freeze_trace.csr.mhpmcounter_write_upper[2] ? '1 : '0; + end + sample_minstreth_to_trace(m_trace); endfunction - function void tinfo_to_ex(); - trace_ex.m_csr.tinfo_we = '0; // READ ONLY csr_tinfo_we_i; - trace_ex.m_csr.tinfo_rdata = r_pipe_freeze_trace.csr.tinfo_q; - trace_ex.m_csr.tinfo_rmask = '1; - trace_ex.m_csr.tinfo_wdata = r_pipe_freeze_trace.csr.tinfo_n; - trace_ex.m_csr.tinfo_wmask = '0; + function void sample_perf_counter_to_trace(insn_trace_t m_trace); + sample_minstret_to_trace(m_trace); + sample_minstreth_to_trace(m_trace); + sample_mcycle_to_trace(m_trace); + for(int idx=3; idx<32; idx++)begin + sample_perf_event_to_trace(idx, m_trace); //TO CHANGE + end + endfunction + + function void perf_counter_to_trace(insn_trace_t m_trace); + if(r_pipe_freeze_trace.csr.mhpmcounter_write_lower[2]) begin + minstret_to_trace(m_trace); + end + if(r_pipe_freeze_trace.csr.mhpmcounter_write_upper[2]) begin + minstreth_to_trace(m_trace); + end + for(int idx=3; idx<32; idx++) begin + if(r_pipe_freeze_trace.csr.mhpmcounter_write_lower[idx]) begin + perf_counter_to_id(idx); + end + if(r_pipe_freeze_trace.csr.mhpmcounter_write_upper[idx]) begin + perf_counter_h_to_id(idx); + end + if(r_pipe_freeze_trace.csr.mhpmevent_we[idx]) begin + perf_event_to_trace(idx, m_trace); + end + end + endfunction + + function void tinfo_to_trace(insn_trace_t m_trace); + m_trace.m_csr.tinfo_we = '0; // READ ONLY csr_tinfo_we_i; + m_trace.m_csr.tinfo_rdata = r_pipe_freeze_trace.csr.tinfo_q; + m_trace.m_csr.tinfo_rmask = '1; + m_trace.m_csr.tinfo_wdata = r_pipe_freeze_trace.csr.tinfo_n; + m_trace.m_csr.tinfo_wmask = '0; endfunction function void mtvec_to_id(); @@ -1083,8 +1241,6 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb; lpcount1_to_id(); lpend1_to_id(); lpstart1_to_id(); - - endfunction bit s_was_flush; //debug exception is flagged as trap only if preceed by a flush @@ -1257,6 +1413,9 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb; end end csr_to_apu_resp(); + + trace_apu_resp.m_stop_cycle = cycles; + trace_apu_resp.m_stop_time = $time; send_rvfi(trace_apu_resp); ->e_send_rvfi_trace_apu_resp; end @@ -1275,7 +1434,7 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb; `CSR_FROM_PIPE(id, misa) `CSR_FROM_PIPE(id, tdata1) `CSR_FROM_PIPE(id, tdata2) - tinfo_to_id(); + tinfo_to_trace(trace_id); `CSR_FROM_PIPE(id, mip) send_rvfi(trace_id); end @@ -1291,15 +1450,28 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb; function logic [31:0] be_to_mask(logic [3:0] be); logic [31:0] mask; - mask[7:0] = be[0] ? 8'hFF : 8'h00; - mask[15:8] = be[0] ? 8'hFF : 8'h00; - mask[23:16] = be[0] ? 8'hFF : 8'h00; - mask[31:24] = be[0] ? 8'hFF : 8'h00; + mask[7:0] = (be[0] == 1'b1) ? 8'hFF : 8'h00; + mask[15:8] = (be[1] == 1'b1) ? 8'hFF : 8'h00; + mask[23:16] = (be[2] == 1'b1) ? 8'hFF : 8'h00; + mask[31:24] = (be[3] == 1'b1) ? 8'hFF : 8'h00; be_to_mask = mask; return mask; endfunction + function void commit_rf_to_trace(insn_trace_t m_trace); + if (m_trace.m_got_ex_reg) begin + m_trace.m_rd_addr[1] = r_pipe_freeze_trace.rf_addr_wb; + m_trace.m_rd_wdata[1] = r_pipe_freeze_trace.rf_wdata_wb; + m_trace.m_2_rd_insn = 1'b1; + m_trace.m_got_first_data = 1'b1; + end else begin + m_trace.m_rd_addr[0] = r_pipe_freeze_trace.rf_addr_wb; + m_trace.m_rd_wdata[0] = r_pipe_freeze_trace.rf_wdata_wb; + m_trace.m_got_first_data = 1'b1; + end + endfunction + task compute_pipeline(); bit s_new_valid_insn; bit s_ex_valid_adjusted; @@ -1375,7 +1547,7 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb; `CSR_FROM_PIPE(id, misa) `CSR_FROM_PIPE(id, tdata1) `CSR_FROM_PIPE(id, tdata2) - tinfo_to_id(); + tinfo_to_trace(trace_id); `CSR_FROM_PIPE(id, mip) end end @@ -1409,7 +1581,7 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb; if (trace_ex.m_valid & s_wb_valid_adjusted) begin // Used flopped values in case write happened before wb_valid - minstret_to_ex(); + sample_perf_counter_to_trace(trace_ex); trace_ex.m_csr.got_minstret = '1; end @@ -1486,14 +1658,14 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb; if (trace_ex.m_valid) begin if(trace_ex.m_instret_smaple_trigger == 1) begin //time to sample instret - minstret_to_ex(); + sample_perf_counter_to_trace(trace_ex); end trace_ex.m_instret_smaple_trigger = trace_ex.m_instret_smaple_trigger + 1; `CSR_FROM_PIPE(ex, misa) `CSR_FROM_PIPE(ex, tdata1) `CSR_FROM_PIPE(ex, tdata2) - tinfo_to_ex(); + tinfo_to_trace(trace_ex); if (s_rf_we_wb_adjusted) begin ->e_dev_commit_rf_to_ex_4; @@ -1519,18 +1691,9 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb; if (s_rf_we_wb_adjusted) begin ->e_dev_commit_rf_to_ex_1; - if (trace_ex.m_got_ex_reg) begin - trace_ex.m_rd_addr[1] = r_pipe_freeze_trace.rf_addr_wb; - trace_ex.m_rd_wdata[1] = r_pipe_freeze_trace.rf_wdata_wb; - trace_ex.m_2_rd_insn = 1'b1; - trace_ex.m_got_first_data = 1'b1; - end else begin - trace_ex.m_rd_addr[0] = r_pipe_freeze_trace.rf_addr_wb; - trace_ex.m_rd_wdata[0] = r_pipe_freeze_trace.rf_wdata_wb; - trace_ex.m_got_first_data = 1'b1; - end + commit_rf_to_trace(trace_ex); - if (r_pipe_freeze_trace.csr.fregs_we && !r_pipe_freeze_trace.apu_rvalid) begin //Catching mstatus_fs updates caused by flw + if (r_pipe_freeze_trace.csr.fregs_we && (r_pipe_freeze_trace.rf_we_wb && r_pipe_freeze_trace.rf_addr_wb[5])) begin //Catching mstatus_fs updates caused by flw `CSR_FROM_PIPE(ex, mstatus_fs) trace_ex.m_csr.mstatus_fs_we = 1'b1; trace_ex.m_csr.mstatus_fs_wmask = '1; @@ -1559,16 +1722,7 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb; end end else if (s_rf_we_wb_adjusted && !s_was_flush) begin ->e_dev_commit_rf_to_ex_2; - if (trace_ex.m_got_ex_reg) begin - trace_ex.m_rd_addr[1] = r_pipe_freeze_trace.rf_addr_wb; - trace_ex.m_rd_wdata[1] = r_pipe_freeze_trace.rf_wdata_wb; - trace_ex.m_2_rd_insn = 1'b1; - trace_ex.m_got_first_data = 1'b1; - end else begin - trace_ex.m_rd_addr[0] = r_pipe_freeze_trace.rf_addr_wb; - trace_ex.m_rd_wdata[0] = r_pipe_freeze_trace.rf_wdata_wb; - trace_ex.m_got_first_data = 1'b1; - end + commit_rf_to_trace(trace_ex); end end @@ -1578,7 +1732,12 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb; if (trace_id.m_valid) begin if(trace_id.m_instret_smaple_trigger == 1) begin //time to sample instret - minstret_to_id(); + sample_perf_counter_to_trace(trace_id); + for(int idx=3; idx<32; idx++) begin + sample_perf_counter_to_id(idx); + sample_perf_counter_h_to_id(idx); + sample_perf_event_to_trace(idx, trace_id); + end end trace_id.m_instret_smaple_trigger = trace_id.m_instret_smaple_trigger + 1; @@ -1594,6 +1753,10 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb; if(r_pipe_freeze_trace.csr.we && (r_pipe_freeze_trace.csr.addr == CSR_DPC)) begin `CSR_FROM_PIPE(id, dpc) end + + `CSR_FROM_PIPE(id, mcountinhibit) + + perf_counter_to_trace(trace_id); ->e_csr_in_ex; end @@ -1634,7 +1797,7 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb; trace_ex.m_csr.fcsr_wmask = '0; if(r_pipe_freeze_trace.ctrl_fsm_cs == XRET_JUMP) begin //xret exit pipeline - tinfo_to_id(); + tinfo_to_trace(trace_id); `CSR_FROM_PIPE(id, tdata1) `CSR_FROM_PIPE(id, tdata2) send_rvfi(trace_id); diff --git a/bhv/cv32e40p_rvfi_trace.sv b/bhv/cv32e40p_rvfi_trace.sv index 417f562a2..adf851759 100644 --- a/bhv/cv32e40p_rvfi_trace.sv +++ b/bhv/cv32e40p_rvfi_trace.sv @@ -1,26 +1,31 @@ -// Copyright (c) 2020 OpenHW Group +// Copyright 2024 Dolphin Design +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 // -// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. +// Licensed under the Solderpad Hardware License v 2.1 (the "License"); +// you may not use this file except in compliance with the License, or, +// at your option, the Apache License version 2.0. // You may obtain a copy of the License at // -// https://solderpad.org/licenses/ +// https://solderpad.org/licenses/SHL-2.1/ // -// Unless required by applicable law or agreed to in writing, software +// Unless required by applicable law or agreed to in writing, any work // distributed under the License is distributed on an "AS IS" BASIS, // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 -// CV32E40P RVFI interface -// -// Contributors: Halfdan Bechmann, Silicon Labs -// Yoann Pruvost, Dolphin Design +//////////////////////////////////////////////////////////////////////////////////// +// // +// Contributors: Halfdan Bechmann, Silicon Labs // +// Yoann Pruvost, Dolphin Design // +// // +// Description: CV32E40P RVFI tracer // +// // +//////////////////////////////////////////////////////////////////////////////////// module cv32e40p_rvfi_trace import cv32e40p_pkg::*; + import cv32e40p_rvfi_pkg::*; #( parameter FPU = 0, parameter ZFINX = 0 @@ -32,9 +37,14 @@ module cv32e40p_rvfi_trace input logic [31:0] imm_s3_type, - input logic rvfi_valid, - input logic [31:0] rvfi_insn, - input logic [31:0] rvfi_pc_rdata, + input logic rvfi_valid, + input logic [31:0] rvfi_insn, + input integer rvfi_start_cycle, + input time rvfi_start_time, + input integer rvfi_stop_cycle, + input time rvfi_stop_time, + input logic [31:0] rvfi_pc_rdata, + input rvfi_trap_t rvfi_trap, input logic [ 4:0] rvfi_rd_addr [1:0], input logic [31:0] rvfi_rd_wdata[1:0], @@ -42,6 +52,7 @@ module cv32e40p_rvfi_trace input logic rvfi_frd_wvalid[1:0], input logic [ 4:0] rvfi_frd_addr [1:0], input logic [31:0] rvfi_frd_wdata [1:0], + input logic rvfi_2_rd, input logic [ 4:0] rvfi_rs1_addr, input logic [ 4:0] rvfi_rs2_addr, @@ -61,8 +72,8 @@ module cv32e40p_rvfi_trace input logic [31:0] rvfi_frs3_rdata, input logic [31:0] rvfi_mem_addr, - input logic [ 3:0] rvfi_mem_rmask, - input logic [ 3:0] rvfi_mem_wmask, + input logic [31:0] rvfi_mem_rmask, + input logic [31:0] rvfi_mem_wmask, input logic [31:0] rvfi_mem_rdata, input logic [31:0] rvfi_mem_wdata ); @@ -74,7 +85,7 @@ module cv32e40p_rvfi_trace integer f; //file pointer string fn; - integer cycles; + // integer cycles; string info_tag; logic is_compressed; @@ -125,7 +136,13 @@ module cv32e40p_rvfi_trace rs3_value = rvfi_rs3_rdata; end - if (rvfi_frd_wvalid[0]) begin + if (rvfi_2_rd) begin + if (rvfi_frd_wvalid[1]) begin + rd = {1'b1, rvfi_frd_addr[1]}; + end else begin + rd = {1'b0, rvfi_rd_addr[1]}; + end + end else if (rvfi_frd_wvalid[0]) begin rd = {1'b1, rvfi_frd_addr[0]}; end else begin rd = {1'b0, rvfi_rd_addr[0]}; @@ -134,57 +151,69 @@ module cv32e40p_rvfi_trace assign rs4 = rs3; - assign imm_i_type = {{20{rvfi_insn[31]}}, rvfi_insn[31:20]}; - assign imm_iz_type = {20'b0, rvfi_insn[31:20]}; - assign imm_s_type = {{20{rvfi_insn[31]}}, rvfi_insn[31:25], rvfi_insn[11:7]}; + cv32e40p_compressed_decoder #( + .FPU(FPU) + ) rvfi_trace_decompress_i ( + .instr_i(rvfi_insn), + .instr_o(decomp_insn), + .is_compressed_o(is_compressed) + ); + + assign imm_i_type = {{20{decomp_insn[31]}}, decomp_insn[31:20]}; + assign imm_iz_type = {20'b0, decomp_insn[31:20]}; + assign imm_s_type = {{20{decomp_insn[31]}}, decomp_insn[31:25], decomp_insn[11:7]}; assign imm_sb_type = { - {19{rvfi_insn[31]}}, rvfi_insn[31], rvfi_insn[7], rvfi_insn[30:25], rvfi_insn[11:8], 1'b0 + {19{decomp_insn[31]}}, + decomp_insn[31], + decomp_insn[7], + decomp_insn[30:25], + decomp_insn[11:8], + 1'b0 }; - assign imm_u_type = {rvfi_insn[31:12], 12'b0}; + assign imm_u_type = {decomp_insn[31:12], 12'b0}; assign imm_uj_type = { - {12{rvfi_insn[31]}}, rvfi_insn[19:12], rvfi_insn[20], rvfi_insn[30:21], 1'b0 + {12{decomp_insn[31]}}, decomp_insn[19:12], decomp_insn[20], decomp_insn[30:21], 1'b0 }; - assign imm_z_type = '0; //{27'b0, rvfi_insn[REG_S1_MSB:REG_S1_LSB]}; + assign imm_z_type = '0; //{27'b0, decomp_insn[REG_S1_MSB:REG_S1_LSB]}; - assign imm_s2_type = {27'b0, rvfi_insn[24:20]}; + assign imm_s2_type = {27'b0, decomp_insn[24:20]}; assign imm_vs_type = '0; assign imm_vu_type = '0; assign imm_shuffle_type = '0; assign imm_clip_type = '0; - cv32e40p_compressed_decoder #( - .FPU(FPU) - ) rvfi_trace_decompress_i ( - .instr_i(rvfi_insn), - .instr_o(decomp_insn), - .is_compressed_o(is_compressed) - ); - `include "cv32e40p_instr_trace.svh" instr_trace_t trace_retire; function instr_trace_t trace_new_instr(); instr_trace_t trace; trace = new(); - trace.init(.cycles(cycles), .pc(rvfi_pc_rdata), .compressed(is_compressed), + trace.external_time = 1; + trace.simtime = rvfi_start_time - 1ns; + trace.stoptime = rvfi_stop_time; + trace.stopcycles = rvfi_stop_cycle; + trace.ctx = (rvfi_trap.trap) ? "(C)" : ""; + trace.init(.cycles(rvfi_start_cycle), .pc(rvfi_pc_rdata), .compressed(is_compressed), .instr(decomp_insn)); return trace; endfunction : trace_new_instr function void apply_reg_write(); foreach (trace_retire.regs_write[i]) begin - if (rvfi_frd_wvalid[0] && (trace_retire.regs_write[i].addr == {1'b1, rvfi_frd_addr[0]})) begin - trace_retire.regs_write[i].value = rvfi_frd_wdata[0]; - end else if (trace_retire.regs_write[i].addr == rvfi_rd_addr[0]) begin - trace_retire.regs_write[i].value = rvfi_rd_wdata[0]; - end if (rvfi_frd_wvalid[1] && (trace_retire.regs_write[i].addr == {1'b1, rvfi_frd_addr[1]})) begin trace_retire.regs_write[i].value = rvfi_frd_wdata[1]; end else if (trace_retire.regs_write[i].addr == rvfi_rd_addr[1]) begin trace_retire.regs_write[i].value = rvfi_rd_wdata[1]; end end + foreach (trace_retire.regs_write[i]) begin + if (rvfi_frd_wvalid[0] && (trace_retire.regs_write[i].addr == {1'b1, rvfi_frd_addr[0]})) begin + trace_retire.regs_write[i].value = rvfi_frd_wdata[0]; + end else if (trace_retire.regs_write[i].addr == rvfi_rd_addr[0]) begin + trace_retire.regs_write[i].value = rvfi_rd_wdata[0]; + end + end endfunction : apply_reg_write function void apply_mem_access(); @@ -202,11 +231,9 @@ instr_trace_t trace_retire; end endfunction : apply_mem_access - // cycle counter - always_ff @(posedge clk_i, negedge rst_ni) begin - if (rst_ni == 1'b0) cycles <= 0; - else cycles <= cycles + 1; - end + string insn_disas; + logic [31:0] insn_pc; + logic [31:0] insn_val; always @(posedge clk_i) begin if (rvfi_valid) begin @@ -214,6 +241,9 @@ instr_trace_t trace_retire; apply_reg_write(); apply_mem_access(); trace_retire.printInstrTrace(); + insn_disas = trace_retire.str; + insn_pc = trace_retire.pc; + insn_val = trace_retire.instr; end end @@ -223,7 +253,8 @@ instr_trace_t trace_retire; $sformat(info_tag, "CORE_TRACER %2d", hart_id_i); $display("[%s] Output filename is: %s", info_tag, fn); f = $fopen(fn, "w"); - $fwrite(f, "Time\tCycle\tPC\tInstr\tDecoded instruction\tRegister and memory contents\n"); + $fwrite(f, + " Time Cycle PC Instr Ctx Decoded instruction Register and memory contents Stop cycle Stop time\n"); end diff --git a/bhv/cv32e40p_tb_wrapper.sv b/bhv/cv32e40p_tb_wrapper.sv index ca703682a..25245407e 100644 --- a/bhv/cv32e40p_tb_wrapper.sv +++ b/bhv/cv32e40p_tb_wrapper.sv @@ -1,23 +1,27 @@ -// Copyright (c) 2020 OpenHW Group +// Copyright 2024 Dolphin Design +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 // -// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. +// Licensed under the Solderpad Hardware License v 2.1 (the "License"); +// you may not use this file except in compliance with the License, or, +// at your option, the Apache License version 2.0. // You may obtain a copy of the License at // -// https://solderpad.org/licenses/ +// https://solderpad.org/licenses/SHL-2.1/ // -// Unless required by applicable law or agreed to in writing, software +// Unless required by applicable law or agreed to in writing, any work // distributed under the License is distributed on an "AS IS" BASIS, // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 -// Wrapper for a cv32e40p, containing cv32e40p_top, and rvfi_tracer -// -// Contributors: Davide Schiavone, OpenHW Group -// Yoann Pruvost, Dolphin Design +//////////////////////////////////////////////////////////////////////////////////// +// // +// Contributors: Davide Schiavone, OpenHW Group // +// Yoann Pruvost, Dolphin Design // +// // +// Description: Test-bench wrapper for cv32e40p_top, tracer and and rvfi_tracer // +// // +//////////////////////////////////////////////////////////////////////////////////// `ifdef CV32E40P_ASSERT_ON `include "cv32e40p_prefetch_controller_sva.sv" @@ -234,8 +238,9 @@ module cv32e40p_tb_wrapper endgenerate cv32e40p_rvfi #( - .FPU (FPU), - .ZFINX(ZFINX) + .FPU(FPU), + .ZFINX(ZFINX), + .NUM_MHPMCOUNTERS(NUM_MHPMCOUNTERS) ) rvfi_i ( .clk_i (cv32e40p_top_i.core_i.clk_i), .rst_ni(cv32e40p_top_i.core_i.rst_ni), @@ -399,6 +404,9 @@ module cv32e40p_tb_wrapper .csr_mcountinhibit_n_i (cv32e40p_top_i.core_i.cs_registers_i.mcountinhibit_n), .csr_mcountinhibit_we_i(cv32e40p_top_i.core_i.cs_registers_i.mcountinhibit_we), + .csr_mhpmevent_n_i(cv32e40p_top_i.core_i.cs_registers_i.mhpmevent_n), + .csr_mhpmevent_q_i(cv32e40p_top_i.core_i.cs_registers_i.mhpmevent_q), + .csr_mhpmevent_we_i(cv32e40p_top_i.core_i.cs_registers_i.mhpmevent_we), .csr_mscratch_q_i(cv32e40p_top_i.core_i.cs_registers_i.mscratch_q), .csr_mscratch_n_i(cv32e40p_top_i.core_i.cs_registers_i.mscratch_n), .csr_mepc_q_i(cv32e40p_top_i.core_i.cs_registers_i.mepc_q), @@ -454,12 +462,18 @@ module cv32e40p_tb_wrapper .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), + .rvfi_start_cycle(rvfi_start_cycle), + .rvfi_start_time(rvfi_start_time), + .rvfi_stop_cycle(rvfi_stop_cycle), + .rvfi_stop_time(rvfi_stop_time), .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_trap(rvfi_trap), .rvfi_rd_addr(rvfi_rd_addr), .rvfi_rd_wdata(rvfi_rd_wdata), .rvfi_frd_wvalid(rvfi_frd_wvalid), .rvfi_frd_addr(rvfi_frd_addr), .rvfi_frd_wdata(rvfi_frd_wdata), + .rvfi_2_rd(rvfi_2_rd), .rvfi_rs1_addr(rvfi_rs1_addr), .rvfi_rs2_addr(rvfi_rs2_addr), .rvfi_rs3_addr(rvfi_rs3_addr), diff --git a/bhv/cv32e40p_tracer.sv b/bhv/cv32e40p_tracer.sv index 8208f2e61..59ed6fd7c 100644 --- a/bhv/cv32e40p_tracer.sv +++ b/bhv/cv32e40p_tracer.sv @@ -1,24 +1,26 @@ -// Copyright (c) 2020 OpenHW Group -// -// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// https://solderpad.org/licenses/ -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 - -// Traces the executed instructions -// -// Contributors: Andreas Traber, ETHZ -// Davide Schiavone, OpenHW Group -// Pascal Gouedo, Dolphin Design +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +//////////////////////////////////////////////////////////////////////////////// +// Engineer: Andreas Traber - atraber@iis.ee.ethz.ch // +// // +// Additional contributions by: // +// Davide Schiavone - pschiavo@iis.ee.ethz.ch // +// // +// Design Name: RISC-V Tracer // +// Project Name: RI5CY // +// Language: SystemVerilog // +// // +// Description: Traces the executed instructions // +// // +//////////////////////////////////////////////////////////////////////////////// `ifdef CV32E40P_TRACE_EXECUTION @@ -183,7 +185,8 @@ module cv32e40p_tracer $sformat(info_tag, "CORE_TRACER %2d", hart_id_i); $display("[%s] Output filename is: %s", info_tag, fn); f = $fopen(fn, "w"); - $fwrite(f, "Time\tCycle\tPC\tInstr\tDecoded instruction\tRegister and memory contents\n"); + $fwrite(f, + " Time Cycle PC Instr Ctx Decoded instruction Register and memory contents\n"); end //initial begin diff --git a/bhv/include/cv32e40p_rvfi_pkg.sv b/bhv/include/cv32e40p_rvfi_pkg.sv index 688795690..f4044e6ec 100644 --- a/bhv/include/cv32e40p_rvfi_pkg.sv +++ b/bhv/include/cv32e40p_rvfi_pkg.sv @@ -1,24 +1,28 @@ -// Copyright (c) 2020 OpenHW Group +// Copyright 2024 Dolphin Design +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 // -// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. +// Licensed under the Solderpad Hardware License v 2.1 (the "License"); +// you may not use this file except in compliance with the License, or, +// at your option, the Apache License version 2.0. // You may obtain a copy of the License at // -// https://solderpad.org/licenses/ +// https://solderpad.org/licenses/SHL-2.1/ // -// Unless required by applicable law or agreed to in writing, software +// Unless required by applicable law or agreed to in writing, any work // distributed under the License is distributed on an "AS IS" BASIS, // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 -// Includes to print info about the RVFI output -// -// Contributors: Davide Schiavone, OpenHW Group -// Halfdan Bechmann, Silicon Labs -// Yoann Pruvost, Dolphin Design +//////////////////////////////////////////////////////////////////////////////////// +// // +// Contributors: Davide Schiavone, OpenHW Group // +// Halfdan Bechmann, Silicon Labs // +// Yoann Pruvost, Dolphin Design // +// // +// Description: Package to print info on RVFI interface // +// // +//////////////////////////////////////////////////////////////////////////////////// package cv32e40p_rvfi_pkg; import cv32e40p_pkg::*; diff --git a/bhv/include/cv32e40p_tracer_pkg.sv b/bhv/include/cv32e40p_tracer_pkg.sv index d026c4aad..b9ce57df4 100644 --- a/bhv/include/cv32e40p_tracer_pkg.sv +++ b/bhv/include/cv32e40p_tracer_pkg.sv @@ -1,23 +1,13 @@ -// Copyright (c) 2020 OpenHW Group -// -// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// https://solderpad.org/licenses/ -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 - -// Tracer package -// -// Contributors: Steve Richmond, Silicon Labs -// Pascal Gouedo, Dolphin Design +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + package cv32e40p_tracer_pkg; import cv32e40p_pkg::*; diff --git a/bhv/insn_trace.sv b/bhv/insn_trace.sv index 71cbaaff4..8cdc06d9e 100644 --- a/bhv/insn_trace.sv +++ b/bhv/insn_trace.sv @@ -1,5 +1,26 @@ -// Copyright 2022 Dolphin Design -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +// Copyright 2024 OpenHW Group and Dolphin Design +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the "License"); +// you may not use this file except in compliance with the License, or, +// at your option, the Apache License version 2.0. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +//////////////////////////////////////////////////////////////////////////////////// +// // +// Contributors: Yoann Pruvost, Dolphin Design // +// // +// Description: Macros and Functions to print information on RVFI interface // +// // +//////////////////////////////////////////////////////////////////////////////////// `define DEFINE_CSR(CSR_NAME) \ logic ``CSR_NAME``_we; \ @@ -23,6 +44,10 @@ class insn_trace_t; bit m_valid; logic [63:0] m_order; + integer m_start_cycle; + integer m_stop_cycle; + time m_start_time; + time m_stop_time; bit m_skip_order; //next order was used by trap; logic [31:0] m_pc_rdata; logic [31:0] m_insn; @@ -71,9 +96,9 @@ struct { logic [31:0] addr ; - logic [ 3:0] rmask; + logic [31:0] rmask; logic [31:0] rdata; - logic [ 3:0] wmask; + logic [31:0] wmask; logic [31:0] wdata; } m_mem; @@ -103,9 +128,28 @@ `DEFINE_CSR(mscratch) `DEFINE_CSR(mepc) `DEFINE_CSR(mcause) + `DEFINE_CSR(mcycle) `DEFINE_CSR(minstret) bit got_minstret; - + `DEFINE_CSR(mcycleh) + `DEFINE_CSR(minstreth) + `DEFINE_CSR(cycle) + `DEFINE_CSR(instret) + // bit got_minstret; + `DEFINE_CSR(cycleh) + `DEFINE_CSR(instreth) + + logic [31:0][ 1:0] mhpmcounter_we; + logic [31:0][63:0] mhpmcounter_rdata; + logic [31:0][63:0] mhpmcounter_rmask; + logic [31:0][63:0] mhpmcounter_wdata; + logic [31:0][63:0] mhpmcounter_wmask; + + logic [31:0] mhpmevent_we; + logic [31:0][31:0] mhpmevent_rdata; + logic [31:0][31:0] mhpmevent_rmask; + logic [31:0][31:0] mhpmevent_wdata; + logic [31:0][31:0] mhpmevent_wmask; `DEFINE_CSR(mip) //mnxti //mintstatus @@ -149,6 +193,10 @@ function new(); this.m_order = 0; + this.m_start_cycle = 0; + this.m_stop_cycle = 0; + this.m_start_time = 0; + this.m_stop_time = 0; this.m_skip_order = 1'b0; this.m_valid = 1'b0; this.m_move_down_pipe = 1'b0; @@ -615,12 +663,12 @@ INSTR_CVCMPLEB : this.m_mnemonic = "cv.cmple.b"; INSTR_CVCMPLESCB : this.m_mnemonic = "cv.cmple.sc.b"; INSTR_CVCMPLESCIB : this.m_mnemonic = "cv.cmple.sci.b"; - INSTR_CVCMPGTUH : this.m_mnemonic = "cv.cmptu.h"; - INSTR_CVCMPGTUSCH : this.m_mnemonic = "cv.cmptu.sc.h"; - INSTR_CVCMPGTUSCIH : this.m_mnemonic = "cv.cmptu.sci.h"; - INSTR_CVCMPGTUB : this.m_mnemonic = "cv.cmptu.b"; - INSTR_CVCMPGTUSCB : this.m_mnemonic = "cv.cmptu.sc.b"; - INSTR_CVCMPGTUSCIB : this.m_mnemonic = "cv.cmptu.sci.b"; + INSTR_CVCMPGTUH : this.m_mnemonic = "cv.cmpgtu.h"; + INSTR_CVCMPGTUSCH : this.m_mnemonic = "cv.cmpgtu.sc.h"; + INSTR_CVCMPGTUSCIH : this.m_mnemonic = "cv.cmpgtu.sci.h"; + INSTR_CVCMPGTUB : this.m_mnemonic = "cv.cmpgtu.b"; + INSTR_CVCMPGTUSCB : this.m_mnemonic = "cv.cmpgtu.sc.b"; + INSTR_CVCMPGTUSCIB : this.m_mnemonic = "cv.cmpgtu.sci.b"; INSTR_CVCMPGEUH : this.m_mnemonic = "cv.cmpgeu.h"; INSTR_CVCMPGEUSCH : this.m_mnemonic = "cv.cmpgeu.sc.h"; INSTR_CVCMPGEUSCIH : this.m_mnemonic = "cv.cmpgeu.sci.h"; @@ -849,7 +897,18 @@ `INIT_CSR(mscratch) `INIT_CSR(mepc) `INIT_CSR(mcause) + `INIT_CSR(mcycle) `INIT_CSR(minstret) + `INIT_CSR(mcycleh) + `INIT_CSR(minstreth) + `INIT_CSR(cycle) + `INIT_CSR(instret) + `INIT_CSR(cycleh) + `INIT_CSR(instreth) + this.m_csr.mhpmcounter_we = '0; + this.m_csr.mhpmcounter_wmask = '0; + this.m_csr.mhpmevent_we = '0; + this.m_csr.mhpmevent_wmask = '0; `INIT_CSR(mip) `INIT_CSR(tdata1) `INIT_CSR(tdata2) @@ -877,6 +936,10 @@ this.m_valid = 1'b1; this.m_stage = ID; this.m_order = this.m_order + 64'h1; + this.m_start_cycle = cycles; + this.m_stop_cycle = 0; + this.m_start_time = $time; + this.m_stop_time = 0; if(this.m_skip_order) begin this.m_order = this.m_order + 64'h1; end @@ -954,6 +1017,10 @@ this.m_valid = m_source.m_valid; this.m_stage = m_source.m_stage; this.m_order = m_source.m_order; + this.m_start_cycle = m_source.m_start_cycle; + this.m_stop_cycle = m_source.m_stop_cycle; + this.m_start_time = m_source.m_start_time; + this.m_stop_time = m_source.m_stop_time; this.m_pc_rdata = m_source.m_pc_rdata; this.m_insn = m_source.m_insn; this.m_mnemonic = m_source.m_mnemonic; @@ -1004,8 +1071,26 @@ `ASSIGN_CSR(mscratch) `ASSIGN_CSR(mepc) `ASSIGN_CSR(mcause) + `ASSIGN_CSR(mcycle) `ASSIGN_CSR(minstret) this.m_csr.got_minstret = m_source.m_csr.got_minstret; + `ASSIGN_CSR(mcycleh) + `ASSIGN_CSR(minstreth) + `ASSIGN_CSR(cycle) + `ASSIGN_CSR(instret) + // this.m_csr.got_minstret = m_source.m_csr.got_minstret; + `ASSIGN_CSR(cycleh) + `ASSIGN_CSR(instreth) + this.m_csr.mhpmcounter_we = m_source.m_csr.mhpmcounter_we; + this.m_csr.mhpmcounter_rdata = m_source.m_csr.mhpmcounter_rdata; + this.m_csr.mhpmcounter_rmask = m_source.m_csr.mhpmcounter_rmask; + this.m_csr.mhpmcounter_wdata = m_source.m_csr.mhpmcounter_wdata; + this.m_csr.mhpmcounter_wmask = m_source.m_csr.mhpmcounter_wmask; + this.m_csr.mhpmevent_we = m_source.m_csr.mhpmevent_we; + this.m_csr.mhpmevent_rdata = m_source.m_csr.mhpmevent_rdata; + this.m_csr.mhpmevent_rmask = m_source.m_csr.mhpmevent_rmask; + this.m_csr.mhpmevent_wdata = m_source.m_csr.mhpmevent_wdata; + this.m_csr.mhpmevent_wmask = m_source.m_csr.mhpmevent_wmask; `ASSIGN_CSR(mip) `ASSIGN_CSR(tdata1) `ASSIGN_CSR(tdata2) diff --git a/bhv/pipe_freeze_trace.sv b/bhv/pipe_freeze_trace.sv index 88d65d0b0..39a16fa62 100644 --- a/bhv/pipe_freeze_trace.sv +++ b/bhv/pipe_freeze_trace.sv @@ -1,27 +1,29 @@ -// Copyright (c) 2023 OpenHW Group +// Copyright 2024 OpenHW Group and Dolphin Design +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 // -// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. +// Licensed under the Solderpad Hardware License v 2.1 (the "License"); +// you may not use this file except in compliance with the License, or, +// at your option, the Apache License version 2.0. // You may obtain a copy of the License at // -// https://solderpad.org/licenses/ +// https://solderpad.org/licenses/SHL-2.1/ // -// Unless required by applicable law or agreed to in writing, software +// Unless required by applicable law or agreed to in writing, any work // distributed under the License is distributed on an "AS IS" BASIS, // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 -// CV32E40P -// -// Contributors: Yoann Pruvost, Dolphin Design +//////////////////////////////////////////////////////////////////////////////////// +// // +// Contributors: Yoann Pruvost, Dolphin Design // +// // +// Description: Structures, Functions and Task used to store all information // +// coming from the core pipeline at every posedge. // +// Those information will then be processed by RVFI. // +// // +//////////////////////////////////////////////////////////////////////////////////// -/* - * This struct is used to store all information comming from the core at every posedge - * The information will then be processed - */ typedef struct { logic is_decoding; logic is_illegal; @@ -349,6 +351,7 @@ function compute_csr_we(); r_pipe_freeze_trace.csr.fflags_we = 1'b0; r_pipe_freeze_trace.csr.frm_we = 1'b0; r_pipe_freeze_trace.csr.fcsr_we = 1'b0; + r_pipe_freeze_trace.csr.mhpmevent_we = '0; r_pipe_freeze_trace.csr.dpc_we = csr_dpc_we_i; if (r_pipe_freeze_trace.csr.we) begin case (r_pipe_freeze_trace.csr.addr) @@ -366,7 +369,10 @@ function compute_csr_we(); r_pipe_freeze_trace.csr.fflags_we = 1'b1; r_pipe_freeze_trace.csr.mstatus_fs_we = 1'b1; end - CSR_FRM: r_pipe_freeze_trace.csr.frm_we = 1'b1; + CSR_FRM: begin + r_pipe_freeze_trace.csr.frm_we = 1'b1; + r_pipe_freeze_trace.csr.mstatus_fs_we = 1'b1; + end CSR_FCSR: begin r_pipe_freeze_trace.csr.fcsr_we = 1'b1; r_pipe_freeze_trace.csr.mstatus_fs_we = 1'b1; @@ -376,6 +382,10 @@ function compute_csr_we(); CSR_DSCRATCH1: r_pipe_freeze_trace.csr.dscratch1_we = 1'b1; endcase end + + if (csr_mhpmevent_we_i) begin + r_pipe_freeze_trace.csr.mhpmevent_we[r_pipe_freeze_trace.csr.addr[4:0]] = 1'b1; + end // CSR_MCAUSE: r_pipe_freeze_trace.csr.mcause_we = r_pipe_freeze_trace.csr.mcause_n != r_pipe_freeze_trace.csr.mcause_q; //for debug purpose endfunction /* @@ -573,7 +583,6 @@ task monitor_pipeline(); r_pipe_freeze_trace.csr.mcountinhibit_we = csr_mcountinhibit_we_i; r_pipe_freeze_trace.csr.mhpmevent_n = csr_mhpmevent_n_i; r_pipe_freeze_trace.csr.mhpmevent_q = csr_mhpmevent_q_i; - r_pipe_freeze_trace.csr.mhpmevent_we = csr_mhpmevent_we_i; r_pipe_freeze_trace.csr.mscratch_n = csr_mscratch_n_i; r_pipe_freeze_trace.csr.mscratch_q = csr_mscratch_q_i; r_pipe_freeze_trace.csr.mepc_n = csr_mepc_n_i; diff --git a/docs/images/ImperasDV_diagram_May_2023-reduced.jpg b/docs/images/ImperasDV_diagram_May_2023-reduced.jpg new file mode 100755 index 000000000..5e45af889 Binary files /dev/null and b/docs/images/ImperasDV_diagram_May_2023-reduced.jpg differ diff --git a/docs/images/openhw-landscape.png b/docs/images/openhw-landscape.png new file mode 100755 index 000000000..fab0f7e71 Binary files /dev/null and b/docs/images/openhw-landscape.png differ diff --git a/docs/source/_static/css/custom.css b/docs/source/_static/css/custom.css index 3ae7d9ae9..34a579c86 100644 --- a/docs/source/_static/css/custom.css +++ b/docs/source/_static/css/custom.css @@ -1,3 +1,9 @@ .no-scrollbar-table td { white-space: normal !important; } +.wy-side-nav-search>div.version { + color:black +} +.wy-side-nav-search>a.icon.icon-home { + color:black +} diff --git a/docs/source/conf.py b/docs/source/conf.py index dbb7b0203..3e24854b3 100644 --- a/docs/source/conf.py +++ b/docs/source/conf.py @@ -1,20 +1,20 @@ # -*- coding: utf-8 -*- # -# Copyright (c) 2020 OpenHW Group -# -# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. +# Copyright 2024 OpenHW Group and Dolphin Design +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +# +# Licensed under the Solderpad Hardware License v 2.1 (the "License"); +# you may not use this file except in compliance with the License, or, +# at your option, the Apache License version 2.0. # You may obtain a copy of the License at # -# https://solderpad.org/licenses/ +# https://solderpad.org/licenses/SHL-2.1/ # -# Unless required by applicable law or agreed to in writing, software +# Unless required by applicable law or agreed to in writing, any work # distributed under the License is distributed on an "AS IS" BASIS, # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. # See the License for the specific language governing permissions and # limitations under the License. -# -# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 # ############################################################################### # @@ -38,13 +38,13 @@ # -- Project information ----------------------------------------------------- project = u'CORE-V CV32E40P User Manual' -copyright = u'2023, OpenHW Group' +copyright = u'2024, OpenHW Group' author = u'PULP Platform and OpenHW Group' # The short X.Y version version = u'' # The full version, including alpha/beta/rc tags -release = u'' +release = u'v1.8.0' # -- General configuration --------------------------------------------------- @@ -98,6 +98,9 @@ # The name of the Pygments (syntax highlighting) style to use. pygments_style = None +# Tags for conditional text +#tags.add('USER') +#tags.add('PMP') # -- Options for HTML output ------------------------------------------------- @@ -111,8 +114,10 @@ # further. For a list of options available for each theme, see the # documentation. # -html_theme_options = {'style_nav_header_background': '#DDDDDD'} +html_theme_options = {'style_nav_header_background': '#DDDDDD', 'prev_next_buttons_location': 'both'} html_logo = '../images/openhw-landscape.svg' +html_show_sphinx = False +html_show_sourcelink = False # Add any paths that contain custom static files (such as style sheets) here, # relative to this directory. They are copied after the builtin static files, @@ -143,6 +148,8 @@ # -- Options for LaTeX output ------------------------------------------------ +latex_logo = '../images/openhw-landscape.png' + latex_elements = { # The paper size ('letterpaper' or 'a4paper'). # @@ -159,6 +166,7 @@ # Latex figure (float) alignment # # 'figure_align': 'htbp', + 'figure_align': 'H', } # Grouping the document tree into LaTeX files. List of tuples diff --git a/docs/source/control_status_registers.rst b/docs/source/control_status_registers.rst index 28f3d2fe6..7eee4b64d 100644 --- a/docs/source/control_status_registers.rst +++ b/docs/source/control_status_registers.rst @@ -1,20 +1,20 @@ .. - Copyright (c) 2023 OpenHW Group - - Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. + Copyright 2024 OpenHW Group and Dolphin Design + SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + + Licensed under the Solderpad Hardware License v 2.1 (the "License"); + you may not use this file except in compliance with the License, or, + at your option, the Apache License version 2.0. You may obtain a copy of the License at - - https://solderpad.org/licenses/ - - Unless required by applicable law or agreed to in writing, software + + https://solderpad.org/licenses/SHL-2.1/ + + Unless required by applicable law or agreed to in writing, any work distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License. - SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 - .. _cs-registers: Control and Status Registers diff --git a/docs/source/core_versions.rst b/docs/source/core_versions.rst index c23169985..83dbb56f6 100644 --- a/docs/source/core_versions.rst +++ b/docs/source/core_versions.rst @@ -1,19 +1,19 @@ .. - Copyright (c) 2020 OpenHW Group - - Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. + Copyright 2024 OpenHW Group and Dolphin Design + SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + + Licensed under the Solderpad Hardware License v 2.1 (the "License"); + you may not use this file except in compliance with the License, or, + at your option, the Apache License version 2.0. You may obtain a copy of the License at - https://solderpad.org/licenses/ + https://solderpad.org/licenses/SHL-2.1/ - Unless required by applicable law or agreed to in writing, software + Unless required by applicable law or agreed to in writing, any work distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License. - - SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 .. _core_versions: diff --git a/docs/source/corev_hw_loop.rst b/docs/source/corev_hw_loop.rst index e51b0fe8f..6653ce1f5 100644 --- a/docs/source/corev_hw_loop.rst +++ b/docs/source/corev_hw_loop.rst @@ -1,19 +1,19 @@ .. - Copyright (c) 2023 OpenHW Group - - Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. + Copyright 2024 OpenHW Group and Dolphin Design + SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + + Licensed under the Solderpad Hardware License v 2.1 (the "License"); + you may not use this file except in compliance with the License, or, + at your option, the Apache License version 2.0. You may obtain a copy of the License at - https://solderpad.org/licenses/ + https://solderpad.org/licenses/SHL-2.1/ - Unless required by applicable law or agreed to in writing, software + Unless required by applicable law or agreed to in writing, any work distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License. - - SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 .. _hwloop-specs: @@ -51,7 +51,7 @@ Those constraint checks could be done only for each instruction in the hardware The HWLoop constraints are: -- HWLoop start, end and setup instructions addresses must be 32-bit aligned (short or long commands). +- HWLoop starti, endi, setupi and setup instructions addresses must be 32-bit aligned (PC-related instructions). - Start and End addresses of an HWLoop body must be 32-bit aligned. @@ -63,9 +63,12 @@ The HWLoop constraints are: - HWLoop body must contain at least 3 instructions. -- When both loops are nested, the End address of the outermost HWLoop (must be #1) must be at least 2 - instructions further than the End address of the innermost HWLoop (must be #0), - i.e. HWLoop[1].endaddress >= HWLoop[0].endaddress + 8. +- When both loops are nested, at least 1 instruction should be present between last innermost HWLoop (must be #0) instruction and + last outermost HWLoop (must be #1) instruction. In other words the End address of the outermost HWLoop must be at least 8 + bytes further than the End address of the innermost HWLoop (HWLoop[1].endaddress >= HWLoop[0].endaddress + 8). + + In the example below the first "addi %[j], %[j], 2;" instruction is the one added due to this constraint. + The code could have been simpler by using only one "addi %[j], %[j], 4;" instruction but to respect this constraint it has been split in two instructions. - HWLoop must always be entered from its start location (no branch/jump to a location inside a HWLoop body). @@ -139,13 +142,13 @@ At the end of the loop, the register %[i] contains 300 and the register %[j] con .. _hwloop-exceptions_handlers: -Hardware loops impact on application, exceptions handlers and debugger -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +Hardware loops impact on application, exception handlers and debug program +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ Application and ebreak/ecall exception handlers ----------------------------------------------- -When an ebreak or an ecall instruction is used in an application, special care should be given for those instruction handlers in case they are placed as the last instruction of an HWLoop. +When an ebreak or an ecall instruction is used in an application, special care should be given for their respective exception handler in case those instructions are the last one of an HWLoop. Those handlers should manage MEPC and lpcountX CSRs updates because an hw loop early-exit could happen if not done. At the end of the handlers after restoring the context/CSRs, a piece of smart code should be added with following highest to lowest order of priority: @@ -164,9 +167,7 @@ Interrupt handlers ------------------ When an interrupt is happening on the last HWLoop instruction, its execution is cancelled, its address is saved in MEPC and its execution will be resumed when returning from interrupt handler. -There is nothing special to be done in those interrupt handlers with respect to MEPC and lpcountX updates, they will be correctly managed by design when executing this last HWLoop instruction after interrupt handler execution. - -Moreover since hardware loop could be used in interrupt routine, the registers have to be saved (resp. restored) at the beginning (resp. end) of the interrupt routine together with the general purpose registers. +There is nothing special to be done in those interrupt handlers with respect to MEPC and lpcountX updates (except HWloop CSRs save/restore mentioned below), they will be correctly managed by design when executing this last HWLoop instruction after interrupt handler execution. Illegal instruction exception handler ------------------------------------- @@ -176,11 +177,17 @@ Depending if an application is going to resume or not after Illegal instruction Debugger -------- -If ebreak is used to enter in Debug Mode (:ref:`ebreak_scenario_2`) and put at the last instruction location of an HWLoop (not very likely to happen), same management than above should be done but on DPC rather than on MEPC. +If ebreak is used to enter in Debug Mode (:ref:`ebreak_scenario_2`) and put at the last instruction location of an HWLoop, same management than above should be done but on DPC rather than on MEPC. When ebreak instruction is used as Software Breakpoint by a debugger when in debug mode and is placed at the last instruction location of an HWLoop in instruction memory, no special management is foreseen. When executing the Software Breakpoint/ebreak instruction, control is given back to the debugger which will manage the different cases. For instance in Single-Step case, original instruction is put back in instruction memory, a Single-Step command is executed on this last instruction (with desgin updating PC and lpcountX to correct values) and Software Breakpoint/ebreak is put back by the debugger in memory. -When ecall instruction is used by a debugger to execute System Calls and is placed at the last instruction location of an HWLoop in instruction memory, debugger ecall handler in debug rom should do the same than described above for application case. +When ecall instruction is used by a debugger to execute System Calls and is placed at the last instruction location of an HWLoop in instruction memory, debugger ecall handler in debug program should do the same than described above for application case. + +HWloop CSRs save and restore +---------------------------- + +As synchronous/asynchronous exception or a debug event happening during HWloop execution is interrupting the normal HWloop execution, special care should be given to HWloop CSRs in case any exception handler or debug program is going to use HWloop feature (or even just call functions using them like memmove, memcpy...). +So HWloop CSRs save/restore should be added together with the general purpose registers to exception handlers or debug program. diff --git a/docs/source/debug.rst b/docs/source/debug.rst index b18da9699..c7e35e126 100644 --- a/docs/source/debug.rst +++ b/docs/source/debug.rst @@ -1,19 +1,19 @@ .. - Copyright (c) 2023 OpenHW Group - - Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. + Copyright 2024 OpenHW Group and Dolphin Design + SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + + Licensed under the Solderpad Hardware License v 2.1 (the "License"); + you may not use this file except in compliance with the License, or, + at your option, the Apache License version 2.0. You may obtain a copy of the License at - https://solderpad.org/licenses/ + https://solderpad.org/licenses/SHL-2.1/ - Unless required by applicable law or agreed to in writing, software + Unless required by applicable law or agreed to in writing, any work distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License. - - SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 .. _debug-support: diff --git a/docs/source/exceptions_interrupts.rst b/docs/source/exceptions_interrupts.rst index 086ce723a..91489ef09 100644 --- a/docs/source/exceptions_interrupts.rst +++ b/docs/source/exceptions_interrupts.rst @@ -1,19 +1,19 @@ .. - Copyright (c) 2023 OpenHW Group - - Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. + Copyright 2024 OpenHW Group and Dolphin Design + SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + + Licensed under the Solderpad Hardware License v 2.1 (the "License"); + you may not use this file except in compliance with the License, or, + at your option, the Apache License version 2.0. You may obtain a copy of the License at - https://solderpad.org/licenses/ + https://solderpad.org/licenses/SHL-2.1/ - Unless required by applicable law or agreed to in writing, software + Unless required by applicable law or agreed to in writing, any work distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License. - - SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 .. _exceptions-interrupts: diff --git a/docs/source/fpu.rst b/docs/source/fpu.rst index 019630a35..23245a970 100644 --- a/docs/source/fpu.rst +++ b/docs/source/fpu.rst @@ -1,18 +1,19 @@ .. - Copyright (c) 2023 OpenHW Group - - Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. + Copyright 2024 OpenHW Group and Dolphin Design + SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + + Licensed under the Solderpad Hardware License v 2.1 (the "License"); + you may not use this file except in compliance with the License, or, + at your option, the Apache License version 2.0. You may obtain a copy of the License at - https://solderpad.org/licenses/ + https://solderpad.org/licenses/SHL-2.1/ - Unless required by applicable law or agreed to in writing, software + Unless required by applicable law or agreed to in writing, any work distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License. - SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 .. _fpu: diff --git a/docs/source/glossary.rst b/docs/source/glossary.rst index 7269f96a9..effecfa33 100644 --- a/docs/source/glossary.rst +++ b/docs/source/glossary.rst @@ -1,19 +1,19 @@ .. - Copyright (c) 2020 OpenHW Group - - Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. + Copyright 2024 OpenHW Group and Dolphin Design + SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + + Licensed under the Solderpad Hardware License v 2.1 (the "License"); + you may not use this file except in compliance with the License, or, + at your option, the Apache License version 2.0. You may obtain a copy of the License at - https://solderpad.org/licenses/ + https://solderpad.org/licenses/SHL-2.1/ - Unless required by applicable law or agreed to in writing, software + Unless required by applicable law or agreed to in writing, any work distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License. - - SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 .. _glossary: diff --git a/docs/source/index.rst b/docs/source/index.rst index 88a1283cb..a8848922a 100644 --- a/docs/source/index.rst +++ b/docs/source/index.rst @@ -1,19 +1,19 @@ .. - Copyright (c) 2023 OpenHW Group - - Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. + Copyright 2024 OpenHW Group and Dolphin Design + SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + + Licensed under the Solderpad Hardware License v 2.1 (the "License"); + you may not use this file except in compliance with the License, or, + at your option, the Apache License version 2.0. You may obtain a copy of the License at - https://solderpad.org/licenses/ + https://solderpad.org/licenses/SHL-2.1/ - Unless required by applicable law or agreed to in writing, software + Unless required by applicable law or agreed to in writing, any work distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License. - - SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 OpenHW Group CV32E40P User Manual ================================= diff --git a/docs/source/instruction_fetch.rst b/docs/source/instruction_fetch.rst index 2e5f77083..9624498cc 100644 --- a/docs/source/instruction_fetch.rst +++ b/docs/source/instruction_fetch.rst @@ -1,19 +1,19 @@ .. - Copyright (c) 2023 OpenHW Group - - Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. + Copyright 2024 OpenHW Group and Dolphin Design + SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + + Licensed under the Solderpad Hardware License v 2.1 (the "License"); + you may not use this file except in compliance with the License, or, + at your option, the Apache License version 2.0. You may obtain a copy of the License at - https://solderpad.org/licenses/ + https://solderpad.org/licenses/SHL-2.1/ - Unless required by applicable law or agreed to in writing, software + Unless required by applicable law or agreed to in writing, any work distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License. - - SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 .. _instruction-fetch: diff --git a/docs/source/instruction_set_extensions.rst b/docs/source/instruction_set_extensions.rst index de3dc3ea8..03dca5191 100644 --- a/docs/source/instruction_set_extensions.rst +++ b/docs/source/instruction_set_extensions.rst @@ -1,19 +1,19 @@ .. - Copyright (c) 2023 OpenHW Group - - Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. + Copyright 2024 OpenHW Group and Dolphin Design + SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + + Licensed under the Solderpad Hardware License v 2.1 (the "License"); + you may not use this file except in compliance with the License, or, + at your option, the Apache License version 2.0. You may obtain a copy of the License at - https://solderpad.org/licenses/ + https://solderpad.org/licenses/SHL-2.1/ - Unless required by applicable law or agreed to in writing, software + Unless required by applicable law or agreed to in writing, any work distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License. - - SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 .. _custom-isa-extensions: @@ -783,21 +783,21 @@ General ALU operations | | | | | Note: If Is2 is equal to 0, (2^(Is2-1)-1) is equivalent to 0. | +-------------------------------------------+------------------------------------------------------------------------+ - | **cv.clipr rD, rs1, rs2** | if rs1 <= -(rs2+1), rD = -(rs2+1), | + | **cv.clipr rD, rs1, rs2** | rs2' = rs2 & 0x7FFFFFFF | | | | - | | else if rs1 >=rs2, rD = rs2, | + | | if rs1 <= -(rs2'+1), rD = -(rs2'+1), | | | | - | | else rD = rs1 | + | | else if rs1 >=rs2', rD = rs2', | | | | - | | Note: rs2 is unsigned. | + | | else rD = rs1 | +-------------------------------------------+------------------------------------------------------------------------+ - | **cv.clipur rD, rs1, rs2** | if rs1 <= 0, rD = 0, | + | **cv.clipur rD, rs1, rs2** | rs2' = rs2 & 0x7FFFFFFF | | | | - | | else if rs1 >= rs2, rD = rs2, | + | | if rs1 <= 0, rD = 0, | | | | - | | else rD = rs1 | + | | else if rs1 >= rs2', rD = rs2', | | | | - | | Note: rs2 is unsigned. | + | | else rD = rs1 | +-------------------------------------------+------------------------------------------------------------------------+ | **cv.addN rD, rs1, rs2, Is3** | rD = (rs1 + rs2) >>> Is3 | | | | @@ -1019,7 +1019,7 @@ Immediate Branching Encoding ^^^^^^^^^^^^^^^^^^^^^^^^^^^^ .. table:: Immediate Branching encoding - :name: General ALU operations encoding + :name: Immediate Branching encoding :widths: 13 14 8 6 8 12 12 11 16 :class: no-scrollbar-table @@ -1046,8 +1046,8 @@ The custom multiply-accumulate extensions are only supported if ``COREV_PULP`` = 16-Bit x 16-Bit Multiplication operations ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -.. table:: 16-Bit Multiplication operations - :name: 16-Bit Multiplication operations +.. table:: 16-Bit x 16-Bit Multiplication operations + :name: 16-Bit x 16-Bit Multiplication operations :widths: 30 70 :class: no-scrollbar-table @@ -1099,8 +1099,8 @@ The custom multiply-accumulate extensions are only supported if ``COREV_PULP`` = 16-Bit x 16-Bit Multiplication pseudo-instructions ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -.. table:: 16-Bit Multiplication pseudo-instructions - :name: 16-Bit Multiplication pseudo-instructions +.. table:: 16-Bit x 16-Bit Multiplication pseudo-instructions + :name: 16-Bit x 16-Bit Multiplication pseudo-instructions :widths: 23 27 50 :class: no-scrollbar-table @@ -1127,8 +1127,8 @@ The custom multiply-accumulate extensions are only supported if ``COREV_PULP`` = 16-Bit x 16-Bit Multiply-Accumulate operations ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -.. table:: 16-Bit Multiply-Accumulate operations - :name: 16-Bit Multiply-Accumulate operations +.. table:: 16-Bit x 16-Bit Multiply-Accumulate operations + :name: 16-Bit x 16-Bit Multiply-Accumulate operations :widths: 30 70 :class: no-scrollbar-table @@ -1179,8 +1179,8 @@ The custom multiply-accumulate extensions are only supported if ``COREV_PULP`` = 32-Bit x 32-Bit Multiply-Accumulate operations ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -.. table:: 32-Bit Multiply-Accumulate operations - :name: 32-Bit Multiply-Accumulate operations +.. table:: 32-Bit x 32-Bit Multiply-Accumulate operations + :name: 32-Bit x 32-Bit Multiply-Accumulate operations :widths: 30 70 :class: no-scrollbar-table @@ -1195,8 +1195,8 @@ The custom multiply-accumulate extensions are only supported if ``COREV_PULP`` = Encoding ^^^^^^^^ -.. table:: 16-Bit Multiplication operations - :name: 16-Bit Multiplication operations +.. table:: 16-Bit x 16-Bit Multiplication encoding + :name: 16-Bit x 16-Bit Multiplication encoding :widths: 5 16 6 6 9 6 11 39 :class: no-scrollbar-table @@ -1222,8 +1222,8 @@ Encoding | 11 | Luimm5[4:0] | src2 | src1 | 100 | dest | 101 1011 | **cv.mulhhsRN rD, rs1, rs2, Is3** | +--------+---------------+---------+---------+------------+--------+------------+------------------------------------+ -.. table:: 16-Bit Multiply-Accumulate operations - :name: 16-Bit Multiply-Accumulate operations +.. table:: 16-Bit x 16-Bit Multiply-Accumulate encoding + :name: 16-Bit x 16-Bit Multiply-Accumulate encoding :widths: 5 16 6 6 9 6 11 39 :class: no-scrollbar-table @@ -1249,8 +1249,8 @@ Encoding | 11 | Luimm5[4:0] | src2 | src1 | 110 | dest | 101 1011 | **cv.machhsRN rD, rs1, rs2, Is3** | +--------+---------------+---------+---------+------------+--------+------------+------------------------------------+ -.. table:: 32-Bit Multiply-Accumulate operations - :name: 32-Bit Multiply-Accumulate operations +.. table:: 32-Bit x 32-Bit Multiply-Accumulate encoding + :name: 32-Bit x 32-Bit Multiply-Accumulate encoding :widths: 21 6 6 9 6 11 39 :class: no-scrollbar-table @@ -1384,7 +1384,7 @@ SIMD ALU operations | | Only Imm6[3:0] and rs2[3:0] are used for .h instruction and | | | Imm6[2:0] and rs2[2:0] for .b instruction. | | | | - | | Other bits are not used and must be set to 0. | + | | In .sci case, unused Imm6 bits must be set to 0. | +------------------------------------------------------------+------------------------------------------------------------------+ | **cv.sra[.sc,.sci]{.h,.b} rD, rs1, [rs2, Imm6]** | rD[i] = rs1[i] >>> op2[i] | | | | @@ -1393,7 +1393,7 @@ SIMD ALU operations | | Only Imm6[3:0] and rs2[3:0] are used for .h instruction and | | | Imm6[2:0] and rs2[2:0] for .b instruction. | | | | - | | Other bits are not used and must be set to 0. | + | | In .sci case, unused Imm6 bits must be set to 0. | +------------------------------------------------------------+------------------------------------------------------------------+ | **cv.sll[.sc,.sci]{.h,.b} rD, rs1, [rs2, Imm6]** | rD[i] = rs1[i] << op2[i] | | | | @@ -1402,7 +1402,7 @@ SIMD ALU operations | | Only Imm6[3:0] and rs2[3:0] are used for .h instruction and | | | Imm6[2:0] and rs2[2:0] for .b instruction. | | | | - | | Other bits are not used and must be set to 0. | + | | In .sci case, unused Imm6 bits must be set to 0. | +------------------------------------------------------------+------------------------------------------------------------------+ | **cv.or[.sc,.sci]{.h,.b} rD, rs1, [rs2, Imm6]** | rD[i] = rs1[i] \| op2[i] | +------------------------------------------------------------+------------------------------------------------------------------+ @@ -1425,20 +1425,32 @@ SIMD Bit Manipulation operations | **Mnemonic** | **Description** | +=======================================+=======================================================================================+ | **cv.extract.h rD, rs1, Imm6** | rD = Sext(rs1[I0\*16+15:I0\*16]) | + | | | + | | Note: Only Imm6[0] bit is used and other Imm6 bits must be set to 0. | +---------------------------------------+---------------------------------------------------------------------------------------+ | **cv.extract.b rD, rs1, Imm6** | rD = Sext(rs1[(I1:I0)\*8+7:(I1:I0)\*8]) | + | | | + | | Note: Only Imm6[1:0] bits are used and other Imm6 bits must be set to 0. | +---------------------------------------+---------------------------------------------------------------------------------------+ | **cv.extractu.h rD, rs1, Imm6** | rD = Zext(rs1[I0\*16+15:I0\*16]) | + | | | + | | Note: Only Imm6[0] bit is used and other Imm6 bits must be set to 0. | +---------------------------------------+---------------------------------------------------------------------------------------+ | **cv.extractu.b rD, rs1, Imm6** | rD = Zext(rs1[(I1:I0)\*8+7:(I1:I0)\*8]) | + | | | + | | Note: Only Imm6[1:0] bits are used and other Imm6 bits must be set to 0. | +---------------------------------------+---------------------------------------------------------------------------------------+ | **cv.insert.h rD, rs1, Imm6** | rD[I0\*16+15:I0\*16] = rs1[15:0] | | | | | | Note: The rest of the bits of rD are untouched and keep their previous value. | + | | | + | | Only Imm6[0] bit is used and other Imm6 bits must be set to 0. | +---------------------------------------+---------------------------------------------------------------------------------------+ | **cv.insert.b rD, rs1, Imm6** | rD[(I1:I0)\*8+7:(I1:I0)\*8] = rs1[7:0] | | | | | | Note: The rest of the bits of rD are untouched and keep their previous value. | + | | | + | | Only Imm6[1:0] bits are used and other Imm6 bits must be set to 0. | +---------------------------------------+---------------------------------------------------------------------------------------+ SIMD Dot Product operations @@ -1531,6 +1543,8 @@ SIMD Shuffle and Pack operations | **cv.shuffle.sci.h rD, rs1, Imm6** | rD[31:16] = rs1[I1\*16+15:I1\*16] | | | | | | rD[15:0] = rs1[I0\*16+15:I0\*16] | + | | | + | | Note: Only Imm6[1:0] bits are used and other Imm6 bits must be set to 0. | +---------------------------------------+---------------------------------------------------------------------------------------+ | **cv.shuffle.b rD, rs1, rs2** | rD[31:24] = rs1[rs2[25:24]\*8+7:rs2[25:24]\*8] | | | | @@ -1610,296 +1624,296 @@ SIMD ALU Encoding .. table:: SIMD ALU encoding :name: SIMD ALU encoding - :widths: 11 4 4 9 7 8 8 13 36 + :widths: 11 4 4 13 7 8 8 13 32 :class: no-scrollbar-table - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 31 : 27 | 26 | 25 | 24 : 20 | 19 : 15 | 14 : 12 | 11 : 7 | 6 : 0 | | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | **funct5** | **F** | | **rs2** | **rs1** | **funct3** | **rD** | **opcode** | | - +============+=======+====+=========+=========+============+==========+============+======================================+ - | 0 0000 | 0 | 0 | src2 | src1 | 000 | dest | 111 1011 | **cv.add.h rD, rs1, rs2** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 0 0000 | 0 | 0 | src2 | src1 | 100 | dest | 111 1011 | **cv.add.sc.h rD, rs1, rs2** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 0 0000 | 0 | Imm6[0\|5:1] | src1 | 110 | dest | 111 1011 | **cv.add.sci.h rD, rs1, Imm6** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 0 0000 | 0 | 0 | src2 | src1 | 001 | dest | 111 1011 | **cv.add.b rD, rs1, rs2** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 0 0000 | 0 | 0 | src2 | src1 | 101 | dest | 111 1011 | **cv.add.sc.b rD, rs1, rs2** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 0 0000 | 0 | Imm6[0\|5:1] | src1 | 111 | dest | 111 1011 | **cv.add.sci.b rD, rs1, Imm6** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 0 0001 | 0 | 0 | src2 | src1 | 000 | dest | 111 1011 | **cv.sub.h rD, rs1, rs2** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 0 0001 | 0 | 0 | src2 | src1 | 100 | dest | 111 1011 | **cv.sub.sc.h rD, rs1, rs2** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 0 0001 | 0 | Imm6[0\|5:1] | src1 | 110 | dest | 111 1011 | **cv.sub.sci.h rD, rs1, Imm6** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 0 0001 | 0 | 0 | src2 | src1 | 001 | dest | 111 1011 | **cv.sub.b rD, rs1, rs2** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 0 0001 | 0 | 0 | src2 | src1 | 101 | dest | 111 1011 | **cv.sub.sc.b rD, rs1, rs2** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 0 0001 | 0 | Imm6[0\|5:1] | src1 | 111 | dest | 111 1011 | **cv.sub.sci.b rD, rs1, Imm6** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 0 0010 | 0 | 0 | src2 | src1 | 000 | dest | 111 1011 | **cv.avg.h rD, rs1, rs2** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 0 0010 | 0 | 0 | src2 | src1 | 100 | dest | 111 1011 | **cv.avg.sc.h rD, rs1, rs2** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 0 0010 | 0 | Imm6[0\|5:1] | src1 | 110 | dest | 111 1011 | **cv.avg.sci.h rD, rs1, Imm6** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 0 0010 | 0 | 0 | src2 | src1 | 001 | dest | 111 1011 | **cv.avg.b rD, rs1, rs2** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 0 0010 | 0 | 0 | src2 | src1 | 101 | dest | 111 1011 | **cv.avg.sc.b rD, rs1, rs2** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 0 0010 | 0 | Imm6[0\|5:1] | src1 | 111 | dest | 111 1011 | **cv.avg.sci.b rD, rs1, Imm6** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 0 0011 | 0 | 0 | src2 | src1 | 000 | dest | 111 1011 | **cv.avgu.h rD, rs1, rs2** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 0 0011 | 0 | 0 | src2 | src1 | 100 | dest | 111 1011 | **cv.avgu.sc.h rD, rs1, rs2** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 0 0011 | 0 | Imm6[0\|5:1] | src1 | 110 | dest | 111 1011 | **cv.avgu.sci.h rD, rs1, Imm6** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 0 0011 | 0 | 0 | src2 | src1 | 001 | dest | 111 1011 | **cv.avgu.b rD, rs1, rs2** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 0 0011 | 0 | 0 | src2 | src1 | 101 | dest | 111 1011 | **cv.avgu.sc.b rD, rs1, rs2** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 0 0011 | 0 | Imm6[0\|5:1] | src1 | 111 | dest | 111 1011 | **cv.avgu.sci.b rD, rs1, Imm6** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 0 0100 | 0 | 0 | src2 | src1 | 000 | dest | 111 1011 | **cv.min.h rD, rs1, rs2** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 0 0100 | 0 | 0 | src2 | src1 | 100 | dest | 111 1011 | **cv.min.sc.h rD, rs1, rs2** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 0 0100 | 0 | Imm6[0\|5:1] | src1 | 110 | dest | 111 1011 | **cv.min.sci.h rD, rs1, Imm6** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 0 0100 | 0 | 0 | src2 | src1 | 001 | dest | 111 1011 | **cv.min.b rD, rs1, rs2** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 0 0100 | 0 | 0 | src2 | src1 | 101 | dest | 111 1011 | **cv.min.sc.b rD, rs1, rs2** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 0 0100 | 0 | Imm6[0\|5:1] | src1 | 111 | dest | 111 1011 | **cv.min.sci.b rD, rs1, Imm6** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 0 0101 | 0 | 0 | src2 | src1 | 000 | dest | 111 1011 | **cv.minu.h rD, rs1, rs2** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 0 0101 | 0 | 0 | src2 | src1 | 100 | dest | 111 1011 | **cv.minu.sc.h rD, rs1, rs2** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 0 0101 | 0 | Imm6[0\|5:1] | src1 | 110 | dest | 111 1011 | **cv.minu.sci.h rD, rs1, Imm6** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 0 0101 | 0 | 0 | src2 | src1 | 001 | dest | 111 1011 | **cv.minu.b rD, rs1, rs2** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 0 0101 | 0 | 0 | src2 | src1 | 101 | dest | 111 1011 | **cv.minu.sc.b rD, rs1, rs2** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 0 0101 | 0 | Imm6[0\|5:1] | src1 | 111 | dest | 111 1011 | **cv.minu.sci.b rD, rs1, Imm6** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 0 0110 | 0 | 0 | src2 | src1 | 000 | dest | 111 1011 | **cv.max.h rD, rs1, rs2** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 0 0110 | 0 | 0 | src2 | src1 | 100 | dest | 111 1011 | **cv.max.sc.h rD, rs1, rs2** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 0 0110 | 0 | Imm6[0\|5:1] | src1 | 110 | dest | 111 1011 | **cv.max.sci.h rD, rs1, Imm6** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 0 0110 | 0 | 0 | src2 | src1 | 001 | dest | 111 1011 | **cv.max.b rD, rs1, rs2** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 0 0110 | 0 | 0 | src2 | src1 | 101 | dest | 111 1011 | **cv.max.sc.b rD, rs1, rs2** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 0 0110 | 0 | Imm6[0\|5:1] | src1 | 111 | dest | 111 1011 | **cv.max.sci.b rD, rs1, Imm6** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 0 0111 | 0 | 0 | src2 | src1 | 000 | dest | 111 1011 | **cv.maxu.h rD, rs1, rs2** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 0 0111 | 0 | 0 | src2 | src1 | 100 | dest | 111 1011 | **cv.maxu.sc.h rD, rs1, rs2** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 0 0111 | 0 | Imm6[0\|5:1] | src1 | 110 | dest | 111 1011 | **cv.maxu.sci.h rD, rs1, Imm6** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 0 0111 | 0 | 0 | src2 | src1 | 001 | dest | 111 1011 | **cv.maxu.b rD, rs1, rs2** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 0 0111 | 0 | 0 | src2 | src1 | 101 | dest | 111 1011 | **cv.maxu.sc.b rD, rs1, rs2** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 0 0111 | 0 | Imm6[0\|5:1] | src1 | 111 | dest | 111 1011 | **cv.maxu.sci.b rD, rs1, Imm6** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 0 1000 | 0 | 0 | src2 | src1 | 000 | dest | 111 1011 | **cv.srl.h rD, rs1, rs2** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 0 1000 | 0 | 0 | src2 | src1 | 100 | dest | 111 1011 | **cv.srl.sc.h rD, rs1, rs2** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 0 1000 | 0 | Imm6[0\|5:1] | src1 | 110 | dest | 111 1011 | **cv.srl.sci.h rD, rs1, Imm6** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 0 1000 | 0 | 0 | src2 | src1 | 001 | dest | 111 1011 | **cv.srl.b rD, rs1, rs2** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 0 1000 | 0 | 0 | src2 | src1 | 101 | dest | 111 1011 | **cv.srl.sc.b rD, rs1, rs2** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 0 1000 | 0 | Imm6[0\|5:1] | src1 | 111 | dest | 111 1011 | **cv.srl.sci.b rD, rs1, Imm6** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 0 1001 | 0 | 0 | src2 | src1 | 000 | dest | 111 1011 | **cv.sra.h rD, rs1, rs2** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 0 1001 | 0 | 0 | src2 | src1 | 100 | dest | 111 1011 | **cv.sra.sc.h rD, rs1, rs2** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 0 1001 | 0 | Imm6[0\|5:1] | src1 | 110 | dest | 111 1011 | **cv.sra.sci.h rD, rs1, Imm6** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 0 1001 | 0 | 0 | src2 | src1 | 001 | dest | 111 1011 | **cv.sra.b rD, rs1, rs2** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 0 1001 | 0 | 0 | src2 | src1 | 101 | dest | 111 1011 | **cv.sra.sc.b rD, rs1, rs2** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 0 1001 | 0 | Imm6[0\|5:1] | src1 | 111 | dest | 111 1011 | **cv.sra.sci.b rD, rs1, Imm6** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 0 1010 | 0 | 0 | src2 | src1 | 000 | dest | 111 1011 | **cv.sll.h rD, rs1, rs2** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 0 1010 | 0 | 0 | src2 | src1 | 100 | dest | 111 1011 | **cv.sll.sc.h rD, rs1, rs2** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 0 1010 | 0 | Imm6[0\|5:1] | src1 | 110 | dest | 111 1011 | **cv.sll.sci.h rD, rs1, Imm6** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 0 1010 | 0 | 0 | src2 | src1 | 001 | dest | 111 1011 | **cv.sll.b rD, rs1, rs2** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 0 1010 | 0 | 0 | src2 | src1 | 101 | dest | 111 1011 | **cv.sll.sc.b rD, rs1, rs2** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 0 1010 | 0 | Imm6[0\|5:1] | src1 | 111 | dest | 111 1011 | **cv.sll.sci.b rD, rs1, Imm6** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 0 1011 | 0 | 0 | src2 | src1 | 000 | dest | 111 1011 | **cv.or.h rD, rs1, rs2** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 0 1011 | 0 | 0 | src2 | src1 | 100 | dest | 111 1011 | **cv.or.sc.h rD, rs1, rs2** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 0 1011 | 0 | Imm6[0\|5:1] | src1 | 110 | dest | 111 1011 | **cv.or.sci.h rD, rs1, Imm6** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 0 1011 | 0 | 0 | src2 | src1 | 001 | dest | 111 1011 | **cv.or.b rD, rs1, rs2** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 0 1011 | 0 | 0 | src2 | src1 | 101 | dest | 111 1011 | **cv.or.sc.b rD, rs1, rs2** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 0 1011 | 0 | Imm6[0\|5:1] | src1 | 111 | dest | 111 1011 | **cv.or.sci.b rD, rs1, Imm6** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 0 1100 | 0 | 0 | src2 | src1 | 000 | dest | 111 1011 | **cv.xor.h rD, rs1, rs2** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 0 1100 | 0 | 0 | src2 | src1 | 100 | dest | 111 1011 | **cv.xor.sc.h rD, rs1, rs2** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 0 1100 | 0 | Imm6[0\|5:1] | src1 | 110 | dest | 111 1011 | **cv.xor.sci.h rD, rs1, Imm6** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 0 1100 | 0 | 0 | src2 | src1 | 001 | dest | 111 1011 | **cv.xor.b rD, rs1, rs2** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 0 1100 | 0 | 0 | src2 | src1 | 101 | dest | 111 1011 | **cv.xor.sc.b rD, rs1, rs2** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 0 1100 | 0 | Imm6[0\|5:1] | src1 | 111 | dest | 111 1011 | **cv.xor.sci.b rD, rs1, Imm6** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 0 1101 | 0 | 0 | src2 | src1 | 000 | dest | 111 1011 | **cv.and.h rD, rs1, rs2** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 0 1101 | 0 | 0 | src2 | src1 | 100 | dest | 111 1011 | **cv.and.sc.h rD, rs1, rs2** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 0 1101 | 0 | Imm6[0\|5:1] | src1 | 110 | dest | 111 1011 | **cv.and.sci.h rD, rs1, Imm6** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 0 1101 | 0 | 0 | src2 | src1 | 001 | dest | 111 1011 | **cv.and.b rD, rs1, rs2** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 0 1101 | 0 | 0 | src2 | src1 | 101 | dest | 111 1011 | **cv.and.sc.b rD, rs1, rs2** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 0 1101 | 0 | Imm6[0\|5:1] | src1 | 111 | dest | 111 1011 | **cv.and.sci.b rD, rs1, Imm6** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 0 1110 | 0 | 0 | 0 | src1 | 000 | dest | 111 1011 | **cv.abs.h rD, rs1** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 0 1110 | 0 | 0 | 0 | src1 | 001 | dest | 111 1011 | **cv.abs.b rD, rs1** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 1 0111 | 0 | Imm6[0\|5:1] | src1 | 000 | dest | 111 1011 | **cv.extract.h rD, rs1, Imm6** | - +------------+-------+--------------+---------+------------+----------+------------+--------------------------------------+ - | 1 0111 | 0 | Imm6[0\|5:1] | src1 | 001 | dest | 111 1011 | **cv.extract.b rD, rs1, Imm6** | - +------------+-------+--------------+---------+------------+----------+------------+--------------------------------------+ - | 1 0111 | 0 | Imm6[0\|5:1] | src1 | 010 | dest | 111 1011 | **cv.extractu.h rD, rs1, Imm6** | - +------------+-------+--------------+---------+------------+----------+------------+--------------------------------------+ - | 1 0111 | 0 | Imm6[0\|5:1] | src1 | 011 | dest | 111 1011 | **cv.extractu.b rD, rs1, Imm6** | - +------------+-------+--------------+---------+------------+----------+------------+--------------------------------------+ - | 1 0111 | 0 | Imm6[0\|5:1] | src1 | 100 | dest | 111 1011 | **cv.insert.h rD, rs1, Imm6** | - +------------+-------+--------------+---------+------------+----------+------------+--------------------------------------+ - | 1 0111 | 0 | Imm6[0\|5:1] | src1 | 101 | dest | 111 1011 | **cv.insert.b rD, rs1, Imm6** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 1 0000 | 0 | 0 | src2 | src1 | 000 | dest | 111 1011 | **cv.dotup.h rD, rs1, rs2** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 1 0000 | 0 | 0 | src2 | src1 | 100 | dest | 111 1011 | **cv.dotup.sc.h rD, rs1, rs2** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 1 0000 | 0 | Imm6[0\|5:1] | src1 | 110 | dest | 111 1011 | **cv.dotup.sci.h rD, rs1, Imm6** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 1 0000 | 0 | 0 | src2 | src1 | 001 | dest | 111 1011 | **cv.dotup.b rD, rs1, rs2** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 1 0000 | 0 | 0 | src2 | src1 | 101 | dest | 111 1011 | **cv.dotup.sc.b rD, rs1, rs2** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 1 0000 | 0 | Imm6[0\|5:1] | src1 | 111 | dest | 111 1011 | **cv.dotup.sci.b rD, rs1, Imm6** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 1 0001 | 0 | 0 | src2 | src1 | 000 | dest | 111 1011 | **cv.dotusp.h rD, rs1, rs2** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 1 0001 | 0 | 0 | src2 | src1 | 100 | dest | 111 1011 | **cv.dotusp.sc.h rD, rs1, rs2** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 1 0001 | 0 | Imm6[0\|5:1] | src1 | 110 | dest | 111 1011 | **cv.dotusp.sci.h rD, rs1, Imm6** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 1 0001 | 0 | 0 | src2 | src1 | 001 | dest | 111 1011 | **cv.dotusp.b rD, rs1, rs2** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 1 0001 | 0 | 0 | src2 | src1 | 101 | dest | 111 1011 | **cv.dotusp.sc.b rD, rs1, rs2** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 1 0001 | 0 | Imm6[0\|5:1] | src1 | 111 | dest | 111 1011 | **cv.dotusp.sci.b rD, rs1, Imm6** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 1 0010 | 0 | 0 | src2 | src1 | 000 | dest | 111 1011 | **cv.dotsp.h rD, rs1, rs2** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 1 0010 | 0 | 0 | src2 | src1 | 100 | dest | 111 1011 | **cv.dotsp.sc.h rD, rs1, rs2** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 1 0010 | 0 | Imm6[0\|5:1] | src1 | 110 | dest | 111 1011 | **cv.dotsp.sci.h rD, rs1, Imm6** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 1 0010 | 0 | 0 | src2 | src1 | 001 | dest | 111 1011 | **cv.dotsp.b rD, rs1, rs2** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 1 0010 | 0 | 0 | src2 | src1 | 101 | dest | 111 1011 | **cv.dotsp.sc.b rD, rs1, rs2** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 1 0010 | 0 | Imm6[0\|5:1] | src1 | 111 | dest | 111 1011 | **cv.dotsp.sci.b rD, rs1, Imm6** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 1 0011 | 0 | 0 | src2 | src1 | 000 | dest | 111 1011 | **cv.sdotup.h rD, rs1, rs2** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 1 0011 | 0 | 0 | src2 | src1 | 100 | dest | 111 1011 | **cv.sdotup.sc.h rD, rs1, rs2** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 1 0011 | 0 | Imm6[0\|5:1] | src1 | 110 | dest | 111 1011 | **cv.sdotup.sci.h rD, rs1, Imm6** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 1 0011 | 0 | 0 | src2 | src1 | 001 | dest | 111 1011 | **cv.sdotup.b rD, rs1, rs2** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 1 0011 | 0 | 0 | src2 | src1 | 101 | dest | 111 1011 | **cv.sdotup.sc.b rD, rs1, rs2** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 1 0011 | 0 | Imm6[0\|5:1] | src1 | 111 | dest | 111 1011 | **cv.sdotup.sci.b rD, rs1, Imm6** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 1 0100 | 0 | 0 | src2 | src1 | 000 | dest | 111 1011 | **cv.sdotusp.h rD, rs1, rs2** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 1 0100 | 0 | 0 | src2 | src1 | 100 | dest | 111 1011 | **cv.sdotusp.sc.h rD, rs1, rs2** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 1 0100 | 0 | Imm6[0\|5:1] | src1 | 110 | dest | 111 1011 | **cv.sdotusp.sci.h rD, rs1, Imm6** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 1 0100 | 0 | 0 | src2 | src1 | 001 | dest | 111 1011 | **cv.sdotusp.b rD, rs1, rs2** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 1 0100 | 0 | 0 | src2 | src1 | 101 | dest | 111 1011 | **cv.sdotusp.sc.b rD, rs1, rs2** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 1 0100 | 0 | Imm6[0\|5:1] | src1 | 111 | dest | 111 1011 | **cv.sdotusp.sci.b rD, rs1, Imm6** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 1 0101 | 0 | 0 | src2 | src1 | 000 | dest | 111 1011 | **cv.sdotsp.h rD, rs1, rs2** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 1 0101 | 0 | 0 | src2 | src1 | 100 | dest | 111 1011 | **cv.sdotsp.sc.h rD, rs1, rs2** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 1 0101 | 0 | Imm6[0\|5:1] | src1 | 110 | dest | 111 1011 | **cv.sdotsp.sci.h rD, rs1, Imm6** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 1 0101 | 0 | 0 | src2 | src1 | 001 | dest | 111 1011 | **cv.sdotsp.b rD, rs1, rs2** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 1 0101 | 0 | 0 | src2 | src1 | 101 | dest | 111 1011 | **cv.sdotsp.sc.b rD, rs1, rs2** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 1 0101 | 0 | Imm6[0\|5:1] | src1 | 111 | dest | 111 1011 | **cv.sdotsp.sci.b rD, rs1, Imm6** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 1 1000 | 0 | 0 | src2 | src1 | 000 | dest | 111 1011 | **cv.shuffle.h rD, rs1, rs2** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 1 1000 | 0 | Imm6[0\|5:1] | src1 | 110 | dest | 111 1011 | **cv.shuffle.sci.h rD, rs1, Imm6** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 1 1000 | 0 | 0 | src2 | src1 | 001 | dest | 111 1011 | **cv.shuffle.b rD, rs1, rs2** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 1 1000 | 0 | Imm6[0\|5:1] | src1 | 111 | dest | 111 1011 | **cv.shuffleI0.sci.b rD, rs1, Imm6** | - +------------+-------+--------------+---------+------------+----------+------------+--------------------------------------+ - | 1 1001 | 0 | Imm6[0\|5:1] | src1 | 111 | dest | 111 1011 | **cv.shuffleI1.sci.b rD, rs1, Imm6** | - +------------+-------+--------------+---------+------------+----------+------------+--------------------------------------+ - | 1 1010 | 0 | Imm6[0\|5:1] | src1 | 111 | dest | 111 1011 | **cv.shuffleI2.sci.b rD, rs1, Imm6** | - +------------+-------+--------------+---------+------------+----------+------------+--------------------------------------+ - | 1 1011 | 0 | Imm6[0\|5:1] | src1 | 111 | dest | 111 1011 | **cv.shuffleI3.sci.b rD, rs1, Imm6** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 1 1100 | 0 | 0 | src2 | src1 | 000 | dest | 111 1011 | **cv.shuffle2.h rD, rs1, rs2** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 1 1100 | 0 | 0 | src2 | src1 | 001 | dest | 111 1011 | **cv.shuffle2.b rD, rs1, rs2** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 1 1110 | 0 | 0 | src2 | src1 | 000 | dest | 111 1011 | **cv.pack rD, rs1, rs2** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 1 1110 | 0 | 1 | src2 | src1 | 000 | dest | 111 1011 | **cv.pack.h rD, rs1, rs2** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 1 1111 | 0 | 1 | src2 | src1 | 001 | dest | 111 1011 | **cv.packhi.b rD, rs1, rs2** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ - | 1 1111 | 0 | 0 | src2 | src1 | 001 | dest | 111 1011 | **cv.packlo.b rD, rs1, rs2** | - +------------+-------+----+---------+---------+------------+----------+------------+--------------------------------------+ + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 31 : 27 | 26 | 25 | 24 : 20 | 19 : 15 | 14 : 12 | 11 : 7 | 6 : 0 | | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | **funct5** | **F** | | **rs2** | **rs1** | **funct3** | **rD** | **opcode** | | + +============+=======+====+==================+=========+============+==========+============+======================================+ + | 0 0000 | 0 | 0 | src2 | src1 | 000 | dest | 111 1011 | **cv.add.h rD, rs1, rs2** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 0 0000 | 0 | 0 | src2 | src1 | 100 | dest | 111 1011 | **cv.add.sc.h rD, rs1, rs2** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 0 0000 | 0 | Imm6[0\|5:1] | src1 | 110 | dest | 111 1011 | **cv.add.sci.h rD, rs1, Imm6** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 0 0000 | 0 | 0 | src2 | src1 | 001 | dest | 111 1011 | **cv.add.b rD, rs1, rs2** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 0 0000 | 0 | 0 | src2 | src1 | 101 | dest | 111 1011 | **cv.add.sc.b rD, rs1, rs2** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 0 0000 | 0 | Imm6[0\|5:1] | src1 | 111 | dest | 111 1011 | **cv.add.sci.b rD, rs1, Imm6** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 0 0001 | 0 | 0 | src2 | src1 | 000 | dest | 111 1011 | **cv.sub.h rD, rs1, rs2** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 0 0001 | 0 | 0 | src2 | src1 | 100 | dest | 111 1011 | **cv.sub.sc.h rD, rs1, rs2** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 0 0001 | 0 | Imm6[0\|5:1] | src1 | 110 | dest | 111 1011 | **cv.sub.sci.h rD, rs1, Imm6** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 0 0001 | 0 | 0 | src2 | src1 | 001 | dest | 111 1011 | **cv.sub.b rD, rs1, rs2** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 0 0001 | 0 | 0 | src2 | src1 | 101 | dest | 111 1011 | **cv.sub.sc.b rD, rs1, rs2** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 0 0001 | 0 | Imm6[0\|5:1] | src1 | 111 | dest | 111 1011 | **cv.sub.sci.b rD, rs1, Imm6** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 0 0010 | 0 | 0 | src2 | src1 | 000 | dest | 111 1011 | **cv.avg.h rD, rs1, rs2** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 0 0010 | 0 | 0 | src2 | src1 | 100 | dest | 111 1011 | **cv.avg.sc.h rD, rs1, rs2** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 0 0010 | 0 | Imm6[0\|5:1] | src1 | 110 | dest | 111 1011 | **cv.avg.sci.h rD, rs1, Imm6** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 0 0010 | 0 | 0 | src2 | src1 | 001 | dest | 111 1011 | **cv.avg.b rD, rs1, rs2** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 0 0010 | 0 | 0 | src2 | src1 | 101 | dest | 111 1011 | **cv.avg.sc.b rD, rs1, rs2** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 0 0010 | 0 | Imm6[0\|5:1] | src1 | 111 | dest | 111 1011 | **cv.avg.sci.b rD, rs1, Imm6** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 0 0011 | 0 | 0 | src2 | src1 | 000 | dest | 111 1011 | **cv.avgu.h rD, rs1, rs2** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 0 0011 | 0 | 0 | src2 | src1 | 100 | dest | 111 1011 | **cv.avgu.sc.h rD, rs1, rs2** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 0 0011 | 0 | Imm6[0\|5:1] | src1 | 110 | dest | 111 1011 | **cv.avgu.sci.h rD, rs1, Imm6** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 0 0011 | 0 | 0 | src2 | src1 | 001 | dest | 111 1011 | **cv.avgu.b rD, rs1, rs2** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 0 0011 | 0 | 0 | src2 | src1 | 101 | dest | 111 1011 | **cv.avgu.sc.b rD, rs1, rs2** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 0 0011 | 0 | Imm6[0\|5:1] | src1 | 111 | dest | 111 1011 | **cv.avgu.sci.b rD, rs1, Imm6** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 0 0100 | 0 | 0 | src2 | src1 | 000 | dest | 111 1011 | **cv.min.h rD, rs1, rs2** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 0 0100 | 0 | 0 | src2 | src1 | 100 | dest | 111 1011 | **cv.min.sc.h rD, rs1, rs2** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 0 0100 | 0 | Imm6[0\|5:1] | src1 | 110 | dest | 111 1011 | **cv.min.sci.h rD, rs1, Imm6** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 0 0100 | 0 | 0 | src2 | src1 | 001 | dest | 111 1011 | **cv.min.b rD, rs1, rs2** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 0 0100 | 0 | 0 | src2 | src1 | 101 | dest | 111 1011 | **cv.min.sc.b rD, rs1, rs2** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 0 0100 | 0 | Imm6[0\|5:1] | src1 | 111 | dest | 111 1011 | **cv.min.sci.b rD, rs1, Imm6** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 0 0101 | 0 | 0 | src2 | src1 | 000 | dest | 111 1011 | **cv.minu.h rD, rs1, rs2** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 0 0101 | 0 | 0 | src2 | src1 | 100 | dest | 111 1011 | **cv.minu.sc.h rD, rs1, rs2** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 0 0101 | 0 | Imm6[0\|5:1] | src1 | 110 | dest | 111 1011 | **cv.minu.sci.h rD, rs1, Imm6** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 0 0101 | 0 | 0 | src2 | src1 | 001 | dest | 111 1011 | **cv.minu.b rD, rs1, rs2** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 0 0101 | 0 | 0 | src2 | src1 | 101 | dest | 111 1011 | **cv.minu.sc.b rD, rs1, rs2** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 0 0101 | 0 | Imm6[0\|5:1] | src1 | 111 | dest | 111 1011 | **cv.minu.sci.b rD, rs1, Imm6** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 0 0110 | 0 | 0 | src2 | src1 | 000 | dest | 111 1011 | **cv.max.h rD, rs1, rs2** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 0 0110 | 0 | 0 | src2 | src1 | 100 | dest | 111 1011 | **cv.max.sc.h rD, rs1, rs2** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 0 0110 | 0 | Imm6[0\|5:1] | src1 | 110 | dest | 111 1011 | **cv.max.sci.h rD, rs1, Imm6** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 0 0110 | 0 | 0 | src2 | src1 | 001 | dest | 111 1011 | **cv.max.b rD, rs1, rs2** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 0 0110 | 0 | 0 | src2 | src1 | 101 | dest | 111 1011 | **cv.max.sc.b rD, rs1, rs2** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 0 0110 | 0 | Imm6[0\|5:1] | src1 | 111 | dest | 111 1011 | **cv.max.sci.b rD, rs1, Imm6** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 0 0111 | 0 | 0 | src2 | src1 | 000 | dest | 111 1011 | **cv.maxu.h rD, rs1, rs2** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 0 0111 | 0 | 0 | src2 | src1 | 100 | dest | 111 1011 | **cv.maxu.sc.h rD, rs1, rs2** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 0 0111 | 0 | Imm6[0\|5:1] | src1 | 110 | dest | 111 1011 | **cv.maxu.sci.h rD, rs1, Imm6** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 0 0111 | 0 | 0 | src2 | src1 | 001 | dest | 111 1011 | **cv.maxu.b rD, rs1, rs2** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 0 0111 | 0 | 0 | src2 | src1 | 101 | dest | 111 1011 | **cv.maxu.sc.b rD, rs1, rs2** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 0 0111 | 0 | Imm6[0\|5:1] | src1 | 111 | dest | 111 1011 | **cv.maxu.sci.b rD, rs1, Imm6** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 0 1000 | 0 | 0 | src2 | src1 | 000 | dest | 111 1011 | **cv.srl.h rD, rs1, rs2** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 0 1000 | 0 | 0 | src2 | src1 | 100 | dest | 111 1011 | **cv.srl.sc.h rD, rs1, rs2** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 0 1000 | 0 | Imm6[0] 00 Imm6[3:1] | src1 | 110 | dest | 111 1011 | **cv.srl.sci.h rD, rs1, Imm6** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 0 1000 | 0 | 0 | src2 | src1 | 001 | dest | 111 1011 | **cv.srl.b rD, rs1, rs2** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 0 1000 | 0 | 0 | src2 | src1 | 101 | dest | 111 1011 | **cv.srl.sc.b rD, rs1, rs2** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 0 1000 | 0 | Imm6[0] 000 Imm6[2:1] | src1 | 111 | dest | 111 1011 | **cv.srl.sci.b rD, rs1, Imm6** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 0 1001 | 0 | 0 | src2 | src1 | 000 | dest | 111 1011 | **cv.sra.h rD, rs1, rs2** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 0 1001 | 0 | 0 | src2 | src1 | 100 | dest | 111 1011 | **cv.sra.sc.h rD, rs1, rs2** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 0 1001 | 0 | Imm6[0] 00 Imm6[3:1] | src1 | 110 | dest | 111 1011 | **cv.sra.sci.h rD, rs1, Imm6** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 0 1001 | 0 | 0 | src2 | src1 | 001 | dest | 111 1011 | **cv.sra.b rD, rs1, rs2** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 0 1001 | 0 | 0 | src2 | src1 | 101 | dest | 111 1011 | **cv.sra.sc.b rD, rs1, rs2** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 0 1001 | 0 | Imm6[0] 000 Imm6[2:1] | src1 | 111 | dest | 111 1011 | **cv.sra.sci.b rD, rs1, Imm6** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 0 1010 | 0 | 0 | src2 | src1 | 000 | dest | 111 1011 | **cv.sll.h rD, rs1, rs2** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 0 1010 | 0 | 0 | src2 | src1 | 100 | dest | 111 1011 | **cv.sll.sc.h rD, rs1, rs2** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 0 1010 | 0 | Imm6[0] 00 Imm6[3:1] | src1 | 110 | dest | 111 1011 | **cv.sll.sci.h rD, rs1, Imm6** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 0 1010 | 0 | 0 | src2 | src1 | 001 | dest | 111 1011 | **cv.sll.b rD, rs1, rs2** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 0 1010 | 0 | 0 | src2 | src1 | 101 | dest | 111 1011 | **cv.sll.sc.b rD, rs1, rs2** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 0 1010 | 0 | Imm6[0] 000 Imm6[2:1] | src1 | 111 | dest | 111 1011 | **cv.sll.sci.b rD, rs1, Imm6** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 0 1011 | 0 | 0 | src2 | src1 | 000 | dest | 111 1011 | **cv.or.h rD, rs1, rs2** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 0 1011 | 0 | 0 | src2 | src1 | 100 | dest | 111 1011 | **cv.or.sc.h rD, rs1, rs2** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 0 1011 | 0 | Imm6[0\|5:1] | src1 | 110 | dest | 111 1011 | **cv.or.sci.h rD, rs1, Imm6** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 0 1011 | 0 | 0 | src2 | src1 | 001 | dest | 111 1011 | **cv.or.b rD, rs1, rs2** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 0 1011 | 0 | 0 | src2 | src1 | 101 | dest | 111 1011 | **cv.or.sc.b rD, rs1, rs2** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 0 1011 | 0 | Imm6[0\|5:1] | src1 | 111 | dest | 111 1011 | **cv.or.sci.b rD, rs1, Imm6** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 0 1100 | 0 | 0 | src2 | src1 | 000 | dest | 111 1011 | **cv.xor.h rD, rs1, rs2** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 0 1100 | 0 | 0 | src2 | src1 | 100 | dest | 111 1011 | **cv.xor.sc.h rD, rs1, rs2** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 0 1100 | 0 | Imm6[0\|5:1] | src1 | 110 | dest | 111 1011 | **cv.xor.sci.h rD, rs1, Imm6** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 0 1100 | 0 | 0 | src2 | src1 | 001 | dest | 111 1011 | **cv.xor.b rD, rs1, rs2** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 0 1100 | 0 | 0 | src2 | src1 | 101 | dest | 111 1011 | **cv.xor.sc.b rD, rs1, rs2** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 0 1100 | 0 | Imm6[0\|5:1] | src1 | 111 | dest | 111 1011 | **cv.xor.sci.b rD, rs1, Imm6** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 0 1101 | 0 | 0 | src2 | src1 | 000 | dest | 111 1011 | **cv.and.h rD, rs1, rs2** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 0 1101 | 0 | 0 | src2 | src1 | 100 | dest | 111 1011 | **cv.and.sc.h rD, rs1, rs2** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 0 1101 | 0 | Imm6[0\|5:1] | src1 | 110 | dest | 111 1011 | **cv.and.sci.h rD, rs1, Imm6** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 0 1101 | 0 | 0 | src2 | src1 | 001 | dest | 111 1011 | **cv.and.b rD, rs1, rs2** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 0 1101 | 0 | 0 | src2 | src1 | 101 | dest | 111 1011 | **cv.and.sc.b rD, rs1, rs2** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 0 1101 | 0 | Imm6[0\|5:1] | src1 | 111 | dest | 111 1011 | **cv.and.sci.b rD, rs1, Imm6** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 0 1110 | 0 | 0 | 0 | src1 | 000 | dest | 111 1011 | **cv.abs.h rD, rs1** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 0 1110 | 0 | 0 | 0 | src1 | 001 | dest | 111 1011 | **cv.abs.b rD, rs1** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 1 0111 | 0 | Imm6[0] 00000 | src1 | 000 | dest | 111 1011 | **cv.extract.h rD, rs1, Imm6** | + +------------+-------+-----------------------+---------+------------+----------+------------+--------------------------------------+ + | 1 0111 | 0 | Imm6[0] 0000 Imm6[1] | src1 | 001 | dest | 111 1011 | **cv.extract.b rD, rs1, Imm6** | + +------------+-------+-----------------------+---------+------------+----------+------------+--------------------------------------+ + | 1 0111 | 0 | Imm6[0] 00000 | src1 | 010 | dest | 111 1011 | **cv.extractu.h rD, rs1, Imm6** | + +------------+-------+-----------------------+---------+------------+----------+------------+--------------------------------------+ + | 1 0111 | 0 | Imm6[0] 0000 Imm6[1] | src1 | 011 | dest | 111 1011 | **cv.extractu.b rD, rs1, Imm6** | + +------------+-------+-----------------------+---------+------------+----------+------------+--------------------------------------+ + | 1 0111 | 0 | Imm6[0] 00000 | src1 | 100 | dest | 111 1011 | **cv.insert.h rD, rs1, Imm6** | + +------------+-------+-----------------------+---------+------------+----------+------------+--------------------------------------+ + | 1 0111 | 0 | Imm6[0] 0000 Imm6[1] | src1 | 101 | dest | 111 1011 | **cv.insert.b rD, rs1, Imm6** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 1 0000 | 0 | 0 | src2 | src1 | 000 | dest | 111 1011 | **cv.dotup.h rD, rs1, rs2** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 1 0000 | 0 | 0 | src2 | src1 | 100 | dest | 111 1011 | **cv.dotup.sc.h rD, rs1, rs2** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 1 0000 | 0 | Imm6[0\|5:1] | src1 | 110 | dest | 111 1011 | **cv.dotup.sci.h rD, rs1, Imm6** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 1 0000 | 0 | 0 | src2 | src1 | 001 | dest | 111 1011 | **cv.dotup.b rD, rs1, rs2** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 1 0000 | 0 | 0 | src2 | src1 | 101 | dest | 111 1011 | **cv.dotup.sc.b rD, rs1, rs2** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 1 0000 | 0 | Imm6[0\|5:1] | src1 | 111 | dest | 111 1011 | **cv.dotup.sci.b rD, rs1, Imm6** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 1 0001 | 0 | 0 | src2 | src1 | 000 | dest | 111 1011 | **cv.dotusp.h rD, rs1, rs2** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 1 0001 | 0 | 0 | src2 | src1 | 100 | dest | 111 1011 | **cv.dotusp.sc.h rD, rs1, rs2** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 1 0001 | 0 | Imm6[0\|5:1] | src1 | 110 | dest | 111 1011 | **cv.dotusp.sci.h rD, rs1, Imm6** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 1 0001 | 0 | 0 | src2 | src1 | 001 | dest | 111 1011 | **cv.dotusp.b rD, rs1, rs2** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 1 0001 | 0 | 0 | src2 | src1 | 101 | dest | 111 1011 | **cv.dotusp.sc.b rD, rs1, rs2** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 1 0001 | 0 | Imm6[0\|5:1] | src1 | 111 | dest | 111 1011 | **cv.dotusp.sci.b rD, rs1, Imm6** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 1 0010 | 0 | 0 | src2 | src1 | 000 | dest | 111 1011 | **cv.dotsp.h rD, rs1, rs2** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 1 0010 | 0 | 0 | src2 | src1 | 100 | dest | 111 1011 | **cv.dotsp.sc.h rD, rs1, rs2** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 1 0010 | 0 | Imm6[0\|5:1] | src1 | 110 | dest | 111 1011 | **cv.dotsp.sci.h rD, rs1, Imm6** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 1 0010 | 0 | 0 | src2 | src1 | 001 | dest | 111 1011 | **cv.dotsp.b rD, rs1, rs2** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 1 0010 | 0 | 0 | src2 | src1 | 101 | dest | 111 1011 | **cv.dotsp.sc.b rD, rs1, rs2** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 1 0010 | 0 | Imm6[0\|5:1] | src1 | 111 | dest | 111 1011 | **cv.dotsp.sci.b rD, rs1, Imm6** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 1 0011 | 0 | 0 | src2 | src1 | 000 | dest | 111 1011 | **cv.sdotup.h rD, rs1, rs2** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 1 0011 | 0 | 0 | src2 | src1 | 100 | dest | 111 1011 | **cv.sdotup.sc.h rD, rs1, rs2** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 1 0011 | 0 | Imm6[0\|5:1] | src1 | 110 | dest | 111 1011 | **cv.sdotup.sci.h rD, rs1, Imm6** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 1 0011 | 0 | 0 | src2 | src1 | 001 | dest | 111 1011 | **cv.sdotup.b rD, rs1, rs2** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 1 0011 | 0 | 0 | src2 | src1 | 101 | dest | 111 1011 | **cv.sdotup.sc.b rD, rs1, rs2** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 1 0011 | 0 | Imm6[0\|5:1] | src1 | 111 | dest | 111 1011 | **cv.sdotup.sci.b rD, rs1, Imm6** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 1 0100 | 0 | 0 | src2 | src1 | 000 | dest | 111 1011 | **cv.sdotusp.h rD, rs1, rs2** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 1 0100 | 0 | 0 | src2 | src1 | 100 | dest | 111 1011 | **cv.sdotusp.sc.h rD, rs1, rs2** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 1 0100 | 0 | Imm6[0\|5:1] | src1 | 110 | dest | 111 1011 | **cv.sdotusp.sci.h rD, rs1, Imm6** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 1 0100 | 0 | 0 | src2 | src1 | 001 | dest | 111 1011 | **cv.sdotusp.b rD, rs1, rs2** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 1 0100 | 0 | 0 | src2 | src1 | 101 | dest | 111 1011 | **cv.sdotusp.sc.b rD, rs1, rs2** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 1 0100 | 0 | Imm6[0\|5:1] | src1 | 111 | dest | 111 1011 | **cv.sdotusp.sci.b rD, rs1, Imm6** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 1 0101 | 0 | 0 | src2 | src1 | 000 | dest | 111 1011 | **cv.sdotsp.h rD, rs1, rs2** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 1 0101 | 0 | 0 | src2 | src1 | 100 | dest | 111 1011 | **cv.sdotsp.sc.h rD, rs1, rs2** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 1 0101 | 0 | Imm6[0\|5:1] | src1 | 110 | dest | 111 1011 | **cv.sdotsp.sci.h rD, rs1, Imm6** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 1 0101 | 0 | 0 | src2 | src1 | 001 | dest | 111 1011 | **cv.sdotsp.b rD, rs1, rs2** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 1 0101 | 0 | 0 | src2 | src1 | 101 | dest | 111 1011 | **cv.sdotsp.sc.b rD, rs1, rs2** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 1 0101 | 0 | Imm6[0\|5:1] | src1 | 111 | dest | 111 1011 | **cv.sdotsp.sci.b rD, rs1, Imm6** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 1 1000 | 0 | 0 | src2 | src1 | 000 | dest | 111 1011 | **cv.shuffle.h rD, rs1, rs2** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 1 1000 | 0 | Imm6[0] 0000 Imm6[1] | src1 | 110 | dest | 111 1011 | **cv.shuffle.sci.h rD, rs1, Imm6** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 1 1000 | 0 | 0 | src2 | src1 | 001 | dest | 111 1011 | **cv.shuffle.b rD, rs1, rs2** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 1 1000 | 0 | Imm6[0\|5:1] | src1 | 111 | dest | 111 1011 | **cv.shuffleI0.sci.b rD, rs1, Imm6** | + +------------+-------+-----------------------+---------+------------+----------+------------+--------------------------------------+ + | 1 1001 | 0 | Imm6[0\|5:1] | src1 | 111 | dest | 111 1011 | **cv.shuffleI1.sci.b rD, rs1, Imm6** | + +------------+-------+-----------------------+---------+------------+----------+------------+--------------------------------------+ + | 1 1010 | 0 | Imm6[0\|5:1] | src1 | 111 | dest | 111 1011 | **cv.shuffleI2.sci.b rD, rs1, Imm6** | + +------------+-------+-----------------------+---------+------------+----------+------------+--------------------------------------+ + | 1 1011 | 0 | Imm6[0\|5:1] | src1 | 111 | dest | 111 1011 | **cv.shuffleI3.sci.b rD, rs1, Imm6** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 1 1100 | 0 | 0 | src2 | src1 | 000 | dest | 111 1011 | **cv.shuffle2.h rD, rs1, rs2** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 1 1100 | 0 | 0 | src2 | src1 | 001 | dest | 111 1011 | **cv.shuffle2.b rD, rs1, rs2** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 1 1110 | 0 | 0 | src2 | src1 | 000 | dest | 111 1011 | **cv.pack rD, rs1, rs2** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 1 1110 | 0 | 1 | src2 | src1 | 000 | dest | 111 1011 | **cv.pack.h rD, rs1, rs2** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 1 1111 | 0 | 1 | src2 | src1 | 001 | dest | 111 1011 | **cv.packhi.b rD, rs1, rs2** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ + | 1 1111 | 0 | 0 | src2 | src1 | 001 | dest | 111 1011 | **cv.packlo.b rD, rs1, rs2** | + +------------+-------+----+------------------+---------+------------+----------+------------+--------------------------------------+ SIMD Comparison operations diff --git a/docs/source/integration.rst b/docs/source/integration.rst index d2fa3eac8..f98e29fcd 100644 --- a/docs/source/integration.rst +++ b/docs/source/integration.rst @@ -1,19 +1,19 @@ .. - Copyright (c) 2023 OpenHW Group - - Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. + Copyright 2024 OpenHW Group and Dolphin Design + SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + + Licensed under the Solderpad Hardware License v 2.1 (the "License"); + you may not use this file except in compliance with the License, or, + at your option, the Apache License version 2.0. You may obtain a copy of the License at - https://solderpad.org/licenses/ + https://solderpad.org/licenses/SHL-2.1/ - Unless required by applicable law or agreed to in writing, software + Unless required by applicable law or agreed to in writing, any work distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License. - - SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 .. _core-integration: @@ -259,21 +259,27 @@ be provided. FPGA Synthesis ^^^^^^^^^^^^^^^ -FPGA synthesis is only supported for CV32E40P. -The user needs to provide a technology specific implementation of a clock gating cell as described -in :ref:`clock-gating-cell`. +FPGA synthesis is supported for CV32E40P and it has been successfully implemented using both AMD® Vivado® and Intel® Quartus® Prime Pro Edition tools. + +Due to some advanced System Verilog features used by CV32E40P RTL design, Intel® Quartus® Prime Standard Edition isn't able to parse some CV32E40P System Verilog files. + +The user needs to provide a technology specific implementation of a clock gating cell as described in :ref:`clock-gating-cell`. .. _synthesis_with_fpu: Synthesizing with the FPU ^^^^^^^^^^^^^^^^^^^^^^^^^ -By default the pipeline of the FPU is purely combinatorial (FPU_*_LAT = 0). In this case FPU instructions latency is the same than simple ALU operations (except FP multicycle DIV/SQRT ones). +By default the pipeline of the FPU is purely combinatorial (FPU_*_LAT = 0). In this case FPU instructions latency is the same than simple ALU operations (except multicycle FDIV/FSQRT ones). But as FPU operations are much more complex than ALU ones, maximum achievable frequency is much lower than ALU one when FPU is enabled. + If this can be fine for low frequency systems, it is possible to indicate how many pipeline registers are instantiated in the FPU to reach higher target frequency. -This is done with FPU_*_LAT CV32E40P parameters setting to perfectly fit target frequency. +This is done by adjusting FPU_*_LAT CV32E40P parameters setting to perfectly fit target frequency. + It should be noted that any additional pipeline register is impacting FPU instructions latency and could cause performances degradation depending of applications using Floating-Point operations. + Those pipeline registers are all added at the end of the FPU pipeline with all operators before them. Optimal frequency is only achievable using automatic retiming commands in implementation tools. -This can be achieved with the following command for Synopsys Design Compiler: +As an exemple, this can be done for Synopsys® Design Compiler with the following command: + “set_optimize_registers true -designs [get_object_name [get_designs "\*cv32e40p_fp_wrapper\*"]]”. diff --git a/docs/source/intro.rst b/docs/source/intro.rst index 853ef357c..4db1c51b0 100644 --- a/docs/source/intro.rst +++ b/docs/source/intro.rst @@ -1,20 +1,20 @@ .. - Copyright (c) 2023 OpenHW Group - - Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. + Copyright 2024 OpenHW Group and Dolphin Design + SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + + Licensed under the Solderpad Hardware License v 2.1 (the "License"); + you may not use this file except in compliance with the License, or, + at your option, the Apache License version 2.0. You may obtain a copy of the License at - - https://solderpad.org/licenses/ - - Unless required by applicable law or agreed to in writing, software + + https://solderpad.org/licenses/SHL-2.1/ + + Unless required by applicable law or agreed to in writing, any work distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License. - SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 - Introduction ============= diff --git a/docs/source/load_store_unit.rst b/docs/source/load_store_unit.rst index ebaf837cc..34b683377 100644 --- a/docs/source/load_store_unit.rst +++ b/docs/source/load_store_unit.rst @@ -1,19 +1,19 @@ .. - Copyright (c) 2023 OpenHW Group - - Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. + Copyright 2024 OpenHW Group and Dolphin Design + SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + + Licensed under the Solderpad Hardware License v 2.1 (the "License"); + you may not use this file except in compliance with the License, or, + at your option, the Apache License version 2.0. You may obtain a copy of the License at - https://solderpad.org/licenses/ + https://solderpad.org/licenses/SHL-2.1/ - Unless required by applicable law or agreed to in writing, software + Unless required by applicable law or agreed to in writing, any work distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License. - - SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 .. _load-store-unit: diff --git a/docs/source/perf_counters.rst b/docs/source/perf_counters.rst index bbed0c545..81e0f21f7 100644 --- a/docs/source/perf_counters.rst +++ b/docs/source/perf_counters.rst @@ -1,19 +1,19 @@ .. - Copyright (c) 2023 OpenHW Group - - Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. + Copyright 2024 OpenHW Group and Dolphin Design + SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + + Licensed under the Solderpad Hardware License v 2.1 (the "License"); + you may not use this file except in compliance with the License, or, + at your option, the Apache License version 2.0. You may obtain a copy of the License at - https://solderpad.org/licenses/ + https://solderpad.org/licenses/SHL-2.1/ - Unless required by applicable law or agreed to in writing, software + Unless required by applicable law or agreed to in writing, any work distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License. - - SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 .. _performance-counters: diff --git a/docs/source/pipeline.rst b/docs/source/pipeline.rst index 971a0a9e1..8b5501e37 100644 --- a/docs/source/pipeline.rst +++ b/docs/source/pipeline.rst @@ -1,19 +1,19 @@ .. - Copyright (c) 2023 OpenHW Group - - Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. + Copyright 2024 OpenHW Group and Dolphin Design + SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + + Licensed under the Solderpad Hardware License v 2.1 (the "License"); + you may not use this file except in compliance with the License, or, + at your option, the Apache License version 2.0. You may obtain a copy of the License at - https://solderpad.org/licenses/ + https://solderpad.org/licenses/SHL-2.1/ - Unless required by applicable law or agreed to in writing, software + Unless required by applicable law or agreed to in writing, any work distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License. - - SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 .. _pipeline-details: @@ -47,6 +47,7 @@ Execute (EX) * There is a multi-cycle MULH in EX. * There is a Misaligned LOAD/STORE in EX. * There is a Post-Increment LOAD/STORE in EX. + In those 3 exceptions, EX will not be stalled, FPU result (and flags) are memorized and will be written back in the register file (and FPU CSR) as soon as there is no conflict anymore. Writeback (WB) @@ -150,7 +151,7 @@ The cycle counts assume zero stall on the instruction-side interface and zero st | Comparison, Conversion | | If there are enough instructions between FPU one and | | or Classify | | the instruction using the result then cycle number is 1. | +------------------------+--------------------------------------+ "Enough instruction" number is either FPU_ADDMUL_LAT, | - | Single Precision | 1..19 | FPU_OTHERS_LAT or 11. | + | Single Precision | 1..19 | FPU_OTHERS_LAT or 19. | | Floating-Point | | If there are no instruction in between then cycle number is | | Division and | | the maximum value for each category. | | Square-Root | | | diff --git a/docs/source/preface.rst b/docs/source/preface.rst index f6b516214..daa3446d4 100644 --- a/docs/source/preface.rst +++ b/docs/source/preface.rst @@ -1,3 +1,20 @@ +.. + Copyright 2024 OpenHW Group and Dolphin Design + SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + + Licensed under the Solderpad Hardware License v 2.1 (the "License"); + you may not use this file except in compliance with the License, or, + at your option, the Apache License version 2.0. + You may obtain a copy of the License at + + https://solderpad.org/licenses/SHL-2.1/ + + Unless required by applicable law or agreed to in writing, any work + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + Changelog ========= diff --git a/docs/source/register_file.rst b/docs/source/register_file.rst index 2c16e90e7..662c2882a 100644 --- a/docs/source/register_file.rst +++ b/docs/source/register_file.rst @@ -1,19 +1,19 @@ .. - Copyright (c) 2023 OpenHW Group - - Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. + Copyright 2024 OpenHW Group and Dolphin Design + SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + + Licensed under the Solderpad Hardware License v 2.1 (the "License"); + you may not use this file except in compliance with the License, or, + at your option, the Apache License version 2.0. You may obtain a copy of the License at - https://solderpad.org/licenses/ + https://solderpad.org/licenses/SHL-2.1/ - Unless required by applicable law or agreed to in writing, software + Unless required by applicable law or agreed to in writing, any work distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License. - - SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 .. _register-file: diff --git a/docs/source/sleep.rst b/docs/source/sleep.rst index cc01f4c65..0a4b793a5 100644 --- a/docs/source/sleep.rst +++ b/docs/source/sleep.rst @@ -1,19 +1,19 @@ .. - Copyright (c) 2023 OpenHW Group - - Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. + Copyright 2024 OpenHW Group and Dolphin Design + SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + + Licensed under the Solderpad Hardware License v 2.1 (the "License"); + you may not use this file except in compliance with the License, or, + at your option, the Apache License version 2.0. You may obtain a copy of the License at - https://solderpad.org/licenses/ + https://solderpad.org/licenses/SHL-2.1/ - Unless required by applicable law or agreed to in writing, software + Unless required by applicable law or agreed to in writing, any work distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License. - - SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 .. _sleep_unit: diff --git a/docs/source/verification.rst b/docs/source/verification.rst index afc645886..3b0de4bd8 100644 --- a/docs/source/verification.rst +++ b/docs/source/verification.rst @@ -1,19 +1,19 @@ .. - Copyright (c) 2023 OpenHW Group - - Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. + Copyright 2024 OpenHW Group and Dolphin Design + SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + + Licensed under the Solderpad Hardware License v 2.1 (the "License"); + you may not use this file except in compliance with the License, or, + at your option, the Apache License version 2.0. You may obtain a copy of the License at - https://solderpad.org/licenses/ + https://solderpad.org/licenses/SHL-2.1/ - Unless required by applicable law or agreed to in writing, software + Unless required by applicable law or agreed to in writing, any work distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License. - - SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 .. _verification: @@ -29,8 +29,8 @@ v1.0.0 verification ------------------- In early 2021 the CV32E40P achieved Functional RTL Freeze (released with cv32e40p_v1.0.0 version), meaning that is has been fully verified as per its -`Verification Plan `_. -Final functional, code and test coverage reports can be found `here `_. +`Verification Plan `_. +Final functional, code and test coverage reports can be found `here `_. The unofficial start date for the CV32E40P verification effort is 2020-02-27, which is the date the core-v-verif environment "went live". Between then and @@ -97,62 +97,127 @@ A classification of the issues themselves: | Invalid | 1 | | +------------------------------+-----------+----------------------------------------------------------------------------------------+ -Additional details are available as part of the `CV32E40P v1.0.0 Report `_. +Additional details are available as part of the `CV32E40P v1.0.0 Report `_. .. [1] It is a testament on the quality of the work done by the PULP platform team - that it took a team of professonal verification engineers more than 9 months + that it took a team of professional verification engineers more than 9 months to find all these issues. +.. raw:: latex + + \newpage + v2.0.0 verification ------------------- -The table below lists the 9 configurations with ``cv32e40p_top`` parameters values verified in the scope of CV32E40Pv2 project using both Formal-based and Simulation-based methodologies. +The table below lists the 7 configurations with ``cv32e40p_top`` parameters values verified in the scope of CV32E40Pv2 project using both Formal-based and Simulation-based methodologies. .. table:: Verified configurations :name: Verified configurations :align: center + :widths: 23 11 11 11 11 11 11 11 :class: no-scrollbar-table - +--------------------+-----------------------------------+ - | **Top Parameters** | **Verified Configurations** | - +====================+===+===+===+===+===+===+===+===+===+ - | COREV_PULP | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | - +--------------------+---+---+---+---+---+---+---+---+---+ - | COREV_CLUSTER | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | - +--------------------+---+---+---+---+---+---+---+---+---+ - | FPU | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | - +--------------------+---+---+---+---+---+---+---+---+---+ - | ZFINX | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | 1 | - +--------------------+---+---+---+---+---+---+---+---+---+ - | FPU_ADDMUL_LAT | 0 | 0 | 1 | 2 | 0 | 1 | 2 | 0 | 2 | - +--------------------+---+---+---+---+---+---+---+---+---+ - | FPU_OTHERS_LAT | 0 | 0 | 1 | 2 | 0 | 1 | 2 | 0 | 2 | - +--------------------+---+---+---+---+---+---+---+---+---+ - -A total of resp. 30 and xx RTL issues were identified by resp. Formal Verification and Simulation methodologies, all have been resolved. + +--------------------+-------------------------------------------------------------------------+ + | | **Verified Configurations (CFG_"config name")** | + +====================+=======+==========+==========+==========+==========+==========+==========+ + | **Top Parameters** | **P** | **P_F0** | **P_F1** | **P_F2** | **P_Z0** | **P_Z1** | **P_Z2** | + +--------------------+-------+----------+----------+----------+----------+----------+----------+ + | COREV_PULP | 1 | 1 | 1 | 1 | 1 | 1 | 1 | + +--------------------+-------+----------+----------+----------+----------+----------+----------+ + | COREV_CLUSTER | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + +--------------------+-------+----------+----------+----------+----------+----------+----------+ + | FPU | 0 | 1 | 1 | 1 | 1 | 1 | 1 | + +--------------------+-------+----------+----------+----------+----------+----------+----------+ + | ZFINX | 0 | 0 | 0 | 0 | 1 | 1 | 1 | + +--------------------+-------+----------+----------+----------+----------+----------+----------+ + | FPU_ADDMUL_LAT | 0 | 0 | 1 | 2 | 0 | 1 | 2 | + +--------------------+-------+----------+----------+----------+----------+----------+----------+ + | FPU_OTHERS_LAT | 0 | 0 | 1 | 2 | 0 | 1 | 2 | + +--------------------+-------+----------+----------+----------+----------+----------+----------+ + +Verification environment is described in `CORE-V Verification Strategy `_ and used the so-called `Step-and-Compare 2.0 `_ methodology. It is using an Imperas® model connected in the test-bench through an RVVI interface as shown by following figure: + +.. figure:: ../images/ImperasDV_diagram_May_2023-reduced.jpg + :name: ImperasDV framework + :align: center -A breakdown of the RTL issues is as follows: + ImperasDV framework + +CV32E40Pv2 achieved RTL Freeze (released with cv32e40p_v1.8.0 version) mid-April 2024, meaning that is has been fully verified as per its +`Verification Plan `_. +Summary and all reports links (RTL code, functional, tests) can be found here: `CV32E40P v2.0.0 Summary and Reports `_. + +It is to be mentioned that CV32E40Pv2 has successfully executed `RISCOF (RISC-V COmpatibility Framework) `_ for RV32IMCF extensions . +The official RISCOF reports can be found following the link mentioned above. + +RISC-V ISA Formal verification +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +To accelerate the verification of more than 300 XPULP instructions, RISC-V ISA Formal Verification methodology has been used with Siemens EDA Onespin tool and its RISC-V ISA Processor Verification app. + +The XPULP instructions pseudo-code description using Sail language have been added to the RISC-V ISA app to successfully formally verify all the CV32E40P instructions, including the previously verified standard IMC together with the new F, Zfinx and XPULP extensions and all additional custom CSRs. + +Example: -.. table:: How RTL Issues Were Found in v2.0.0 - :name: How RTL Issues Were Found in v2.0.0 +.. code-block:: text + + { + "name": "CV.SDOTUP.B", + "disassembly": "cv.sdotup.b {rd},{rs1},{rs2}", + "decoding": "1001100 rs2 rs1 001 rd/rs3 1111011", + "restrictions": "", + "execution": "X(rd) = X(rs3) + EXTZ(mul(X(rs1)[7..0],X(rs2)[7..0])) + + EXTZ(mul(X(rs1)[15..8],X(rs2)[15..8])) + + EXTZ(mul(X(rs1)[23..16],X(rs2)[23..16])) + + EXTZ(mul(X(rs1)[31..24],X(rs2)[31..24]))" + }, + +Those SAIL instructions description are then used to automatically generate 277 assertions and 29 CSRs descriptions. +Those assertions have been applied on the 7 different configurations listed in :ref:`Verified configurations` table on intermediate RTL version and were proven as correct. + +RTL code coverage is generated using Siemens EDA Onespin Quantify tool which uses RTL mutation to check assertions quality and can produce standard UCDB database that can be merged with simulation one afterwards. + +Simulation verification +^^^^^^^^^^^^^^^^^^^^^^^ + +core-v-verif verification environment for v1.0.0 was using a *step&compare* methodology with an instruction set simulator (ISS) from Imperas Software as the reference model. +This strategy was successful, but inefficient because the *step&compare* logic in the testbench must compensate for the cycle-time effects of events that are asynchronous to the instruction stream such as interrupts, debug resets plus bus errors and random delays on instruction fetch and load/store memory buses. +For verification of v2.0.0 release of the CV32E40P core, the step-and-compare and the ISS have been replaced by a true reference model (RM) called ImperasDV. In addition, the Imperas Reference Model has been extended to support the v2 XPULP instructions specification. + +Another innovation for v2.0.0 was the adoption of a standardized tracer interface to the DUT and RM, based on the open-source RISC-V Verification Interface (RVVI). The use of well documented, standardized interfaces greatly simplifies the integration of the DUT with the RM. + +Results summary +^^^^^^^^^^^^^^^ + +RISC-V ISA Formal Verification has been successfully launched on intermediate RTL versions of the 7 different configurations. +But on v1.8.0 RTL tag, only PULP configuration (CFG_P) was fully proven, run-time of more than a month on configurations including the Floating-Point unit prevented to have full results. +Properties status can be found in `CV32E40P v2.0.0 Report `_. + +30 issues were identified by Formal Verification, 20 by Simulation methodologies and 4 by Lint/RTL code review, all have been resolved except 1 about Lint warnings. + +Here is the breakdown of all the issues: + +.. table:: How Issues Were Found in v2.0.0 + :name: How Issues Were Found in v2.0.0 :widths: 27 9 64 :class: no-scrollbar-table - +---------------------+-----------+---------------------------------------------------------------+ - | **"Found By"** | **Count** | **Note** | - +=====================+===========+===============================================================+ - | Formal Verification | 30 | All related to features enabled by ``COREV_PULP`` or ``FPU``. | - +---------------------+-----------+---------------------------------------------------------------+ - | Simulation | | | - +---------------------+-----------+---------------------------------------------------------------+ - | Lint | | | - +---------------------+-----------+---------------------------------------------------------------+ + +--------------------------------+-----------+---------------------------------------------------------------+ + | **"Found By"** | **Count** | **Note** | + +================================+===========+===============================================================+ + | RISC-V ISA Formal Verification | 30 | All related to features enabled by ``COREV_PULP`` or ``FPU``. | + +--------------------------------+-----------+---------------------------------------------------------------+ + | Simulation | 20 | Details below | + +--------------------------------+-----------+---------------------------------------------------------------+ + | Lint/RTL Code review | 4 | | + +--------------------------------+-----------+---------------------------------------------------------------+ -A classification of the Formal Verification issues by type and their description are listed in the two following tables: +A classification of the RISC-V ISA Formal Verification issues by type and their description are listed in the following tables: -.. table:: Breakdown of Issues found by Formal Verification in v2.0.0 - :name: Breakdown of Issues found by Formal Verification in v2.0.0 +.. table:: Breakdown of Issues found by RISC-V ISA Formal Verification in v2.0.0 + :name: Breakdown of Issues found by RISC-V ISA Formal Verification in v2.0.0 :widths: 27 9 64 :class: no-scrollbar-table @@ -161,11 +226,11 @@ A classification of the Formal Verification issues by type and their description +==============================+===========+========================================================================================+ | User Manual | 12 | Instructions description leading to mis-interpretation | +------------------------------+-----------+----------------------------------------------------------------------------------------+ - | RTL bugs | 18 | See classification below | + | RTL bugs | 18 | Details below | +------------------------------+-----------+----------------------------------------------------------------------------------------+ -.. table:: Formal Verification Issues Classification in v2.0.0 - :name: Formal Verification Issues Classification in v2.0.0 +.. table:: RISC-V ISA Formal Verification Issues Classification in v2.0.0 + :name: RISC-V ISA Formal Verification Issues Classification in v2.0.0 :widths: 27 9 64 :class: no-scrollbar-table @@ -186,7 +251,7 @@ A classification of the Formal Verification issues by type and their description | F instructions result or flags | 5 | F result or flags computations is incorrect with respect to IEEE 754-2008 standard. | +--------------------------------+-----------+---------------------------------------------------------------------------------------+ -A classification of the simulation issues by method used to identify them is informative: +A classification of the Simulation issues by type and their description are listed in the following tables: .. table:: Breakdown of Issues found by Simulation in v2.0.0 :name: Breakdown of Issues found by Simulation in v2.0.0 @@ -194,92 +259,46 @@ A classification of the simulation issues by method used to identify them is inf :class: no-scrollbar-table +------------------------------+-----------+----------------------------------------------------------------------------------------+ - | **Simulation Method** | **Count** | **Note** | + | **Type** | **Count** | **Note** | +==============================+===========+========================================================================================+ - | Directed, self-checking test | | Many test supplied by Design team and a couple from the Open Source Community at large | - +------------------------------+-----------+----------------------------------------------------------------------------------------+ - | RVFI/RVVI | | Issues directly attributed to comparison against Reference Model | - +------------------------------+-----------+----------------------------------------------------------------------------------------+ - | Constrained-Random | | Test generated by corev-dv (extension of riscv-dv) | + | RTL bugs | 20 | See classification below | +------------------------------+-----------+----------------------------------------------------------------------------------------+ - -A classification of the Simulation issues themselves: - -.. table:: Simulation Issue Classification in v2.0.0 - :name: Simulation Issue Classification in v2.0.0 - :widths: 27 9 64 +.. table:: Simulation Issues Classification in v2.0.0 + :name: Simulation Issues Classification in v2.0.0 + :widths: 38 9 53 :class: no-scrollbar-table - +------------------------------+-----------+----------------------------------------------------------------------------------------+ - | **Issue Type** | **Count** | **Note** | - +==============================+===========+========================================================================================+ - | RTL Functional bug | | | - +------------------------------+-----------+----------------------------------------------------------------------------------------+ - | | | | - +------------------------------+-----------+----------------------------------------------------------------------------------------+ - -Formal verification -^^^^^^^^^^^^^^^^^^^ - -To accelerate the verification of more than 300 Xpulp instructions, Formal Verification methodology has been used with Siemens EDA Onespin tools and its RISC-V ISA Processor Verification app. - -The Xpulp instructions pseudo-code description using Sail language have been added to the RISC-V ISA app to successfully formally verify all the CV32E40P instructions, including the previously verified standard IMC together with the new F, Zfinx and Xpulp extensions and all additional custom CSRs. - -Example: - -.. code-block:: text - - { - "name": "CV.SDOTUP.B", - "disassembly": "cv.sdotup.b {rd},{rs1},{rs2}", - "decoding": "1001100 rs2 rs1 001 rd/rs3 1111011", - "restrictions": "", - "execution": "X(rd) = X(rs3) + EXTZ(mul(X(rs1)[7..0],X(rs2)[7..0])) + - EXTZ(mul(X(rs1)[15..8],X(rs2)[15..8])) + - EXTZ(mul(X(rs1)[23..16],X(rs2)[23..16])) + - EXTZ(mul(X(rs1)[31..24],X(rs2)[31..24]))" - }, - -Those SAIL instructions description are then used to automatically generate more than 430 assertions and 29 CSRs descriptions. -Those assertions have been applied on the 9 different configurations listed in :ref:`Verified configurations` table. - -RTL code coverage is generated using Siemens EDA Onespin Quantify tool which uses RTL mutation to check assertions quality and can produce standard UCDB database that can be merged with simulation one afterwards. - -WIP... - -.. ADD PLANS AND REPORTS LINKS - -.. Formal Verification assertions and RTL code coverage reports can be found `here `_. - -.. TO DEVELOP ... - -Simulation verification -^^^^^^^^^^^^^^^^^^^^^^^ - -core-v-verif verification environment for v1.0.0 was using a *step&compare* methodology with an instruction set simulator (ISS) from Imperas Software as the reference model. -This strategy was successful, but inefficient because the *step&compare* logic in the testbench must compensate for the cycle-time effects of events that are asynchronous to the instruction stream such as interrupts, debug resets plus bus errors and random delays on instruction fetch and load/store memory buses. -For verification of v2.0.0 release of the CV32E40P core, the step-and-compare and the ISS have been replaced by a true reference model (RM) called ImperasDV. In addition, the Imperas Reference Model has been extended to support the v2 Xpulp instructions specification. - -Another innovation for v2.0.0 was the adoption of a standardized tracer interface to the DUT and RM, based on the open-source RISC-V Verification Interface (RVVI). The use of well documented, standardized interfaces greatly simplifies the integration of the DUT with the RM. - -Additionaly to V1 Verification plans, `Verification Plan `_ contains a `new section `_ related to F and XPULP verification. - -WIP... - -.. ADD REPORTS LINKS - -.. TO DEVELOP ... - -Reports -^^^^^^^ - -WIP... - -.. ADD BUG LIST LINK AND TABLE LIKE ABOVE - -.. ADD MERGED RTL CODE COVERAGE GENERATED REPORTS LINK - + +------------------------------------------+-----------+---------------------------------------------------------------------------------------+ + | **Issue Type** | **Count** | **Note** | + +==========================================+===========+=======================================================================================+ + | Multi-cycle F instructions | 5 | Data forward violation between XPULP instructions and muticycle F instructions. | + +------------------------------------------+-----------+---------------------------------------------------------------------------------------+ + | Hardware Loops | 4 | Conflict between CSR write and cv.lp* instructions. | + | | | | + | | | Incorrect behavior when count programmed with 0 value. | + | | | | + | | | lpcountX not decremented to 0 at the end of HWloop execution. | + | | | | + | | | lpcountX not updated after a pipeline flush due to a CSR access. | + +------------------------------------------+-----------+---------------------------------------------------------------------------------------+ + | Illegal instructions exception | 3 | Illegal immediates values | + +------------------------------------------+-----------+---------------------------------------------------------------------------------------+ + | Incorrect Register file control | 1 | ZFINX = 1 case | + +------------------------------------------+-----------+---------------------------------------------------------------------------------------+ + | MIMPID incorrect value | 1 | Value depending of FPU, COREV_PULP and COREV_CLUSTER paremeters. | + +------------------------------------------+-----------+---------------------------------------------------------------------------------------+ + | Deadlock | 1 | Bug resolution for multicycle F instructions created a deadlock when conflicting | + | | | Register File write between ALU and FPU. | + +------------------------------------------+-----------+---------------------------------------------------------------------------------------+ + | MSTATUS.FS incorrect value | 1 | FS was not updated following any Floating Point Load instruction. | + +------------------------------------------+-----------+---------------------------------------------------------------------------------------+ + | Unnecessary multiple Register File write | 1 | Removed redundant Register File writes. | + +------------------------------------------+-----------+---------------------------------------------------------------------------------------+ + | Missing or unreacheable case defaults | 2 | Found with RTL Code coverage holes analysis. | + +------------------------------------------+-----------+---------------------------------------------------------------------------------------+ + | FPU unnecessary clock enable | 1 | Finer grain clock gating generation. | + +------------------------------------------+-----------+---------------------------------------------------------------------------------------+ Tracer ------ @@ -292,7 +311,7 @@ Output file ^^^^^^^^^^^ All traced instructions are written to a log file. -The log file is named ``trace_core_.log``, with ```` being the 32 digit hart ID of the core being traced. +The log file is named ``trace_core.log``. Trace output format ^^^^^^^^^^^^^^^^^^^ @@ -309,7 +328,7 @@ The trace output is in tab-separated columns. - Numeric register names are used (e.g. ``x1``). - Symbolic CSR names are used. - Jump/branch targets are given as absolute address if possible (PC + immediate). -6. **Register and memory contents**: For all accessed registers, the value before and after the instruction execution is given. Writes to registers are indicated as ``registername=value``, reads as ``registername:value``. For memory accesses, the physical address (PA), the loaded and stored data are given. +6. **Register and memory contents**: For all accessed registers, the value before and after the instruction execution is given. Writes to registers are indicated as ``registername=value``, reads as ``registername:value``. For memory accesses, the physical address (PA) of the loaded or stored data is reported as well. diff --git a/rtl/cv32e40p_controller.sv b/rtl/cv32e40p_controller.sv index d2d7b2fe9..d1c86d6c8 100644 --- a/rtl/cv32e40p_controller.sv +++ b/rtl/cv32e40p_controller.sv @@ -597,7 +597,17 @@ module cv32e40p_controller import cv32e40p_pkg::*; csr_status_i: begin halt_if_o = 1'b1; - ctrl_fsm_ns = id_ready_i ? FLUSH_EX : DECODE; + if (~id_ready_i) begin + ctrl_fsm_ns = DECODE; + end else begin + ctrl_fsm_ns = FLUSH_EX; + if (hwlp_end0_eq_pc) begin + hwlp_dec_cnt_o[0] = 1'b1; + end + if (hwlp_end1_eq_pc) begin + hwlp_dec_cnt_o[1] = 1'b1; + end + end end data_load_event_i: begin @@ -617,7 +627,7 @@ module cv32e40p_controller import cv32e40p_pkg::*; ctrl_fsm_ns = hwlp_end0_eq_pc_plus4 || hwlp_end1_eq_pc_plus4 ? DECODE : DECODE_HWLOOP; // we can be at the end of HWloop due to a return from interrupt or ecall or ebreak or exceptions - if(hwlp_end0_eq_pc && hwlp_counter0_gt_1) begin + if (hwlp_end0_eq_pc && hwlp_counter0_gt_1) begin pc_mux_o = PC_HWLOOP; if (~jump_done_q) begin pc_set_o = 1'b1; @@ -791,7 +801,17 @@ module cv32e40p_controller import cv32e40p_pkg::*; csr_status_i: begin halt_if_o = 1'b1; - ctrl_fsm_ns = id_ready_i ? FLUSH_EX : DECODE_HWLOOP; + if (~id_ready_i) begin + ctrl_fsm_ns = DECODE_HWLOOP; + end else begin + ctrl_fsm_ns = FLUSH_EX; + if (hwlp_end0_eq_pc) begin + hwlp_dec_cnt_o[0] = 1'b1; + end + if (hwlp_end1_eq_pc) begin + hwlp_dec_cnt_o[1] = 1'b1; + end + end end data_load_event_i: begin @@ -1067,16 +1087,10 @@ module cv32e40p_controller import cv32e40p_pkg::*; end csr_status_i: begin - - if(hwlp_end0_eq_pc && hwlp_counter0_gt_1) begin - pc_mux_o = PC_HWLOOP; - pc_set_o = 1'b1; - hwlp_dec_cnt_o[0] = 1'b1; - end - if(hwlp_end1_eq_pc && hwlp_counter1_gt_1) begin - pc_mux_o = PC_HWLOOP; - pc_set_o = 1'b1; - hwlp_dec_cnt_o[1] = 1'b1; + if ((hwlp_end0_eq_pc && !hwlp_counter0_eq_0) || + (hwlp_end1_eq_pc && !hwlp_counter1_eq_0)) begin + pc_mux_o = PC_HWLOOP; + pc_set_o = 1'b1; end end @@ -1561,7 +1575,7 @@ endgenerate // HWLoop 0 and 1 having target address constraints property p_hwlp_same_target_address; - @(posedge clk) (hwlp_counter_i[1] > 1 && hwlp_counter_i[0] > 1) |-> ( hwlp_end_addr_i[1] - 4 >= hwlp_end_addr_i[0] - 4 + 8 ); + @(posedge clk) (hwlp_counter_i[1] > 1 && hwlp_counter_i[0] > 1 && pc_id_i >= hwlp_start_addr_i[0] && pc_id_i <= hwlp_end_addr_i[0] - 4) |-> ( hwlp_end_addr_i[1] - 4 >= hwlp_end_addr_i[0] - 4 + 8 ); endproperty a_hwlp_same_target_address : assert property(p_hwlp_same_target_address) else $warning("%t, HWLoops target address do not respect constraints", $time); diff --git a/rtl/cv32e40p_core.sv b/rtl/cv32e40p_core.sv index 7d83e548b..4275cf9c1 100644 --- a/rtl/cv32e40p_core.sv +++ b/rtl/cv32e40p_core.sv @@ -70,7 +70,8 @@ module cv32e40p_core output logic [31:0] data_wdata_o, input logic [31:0] data_rdata_i, - // apu-interconnect + // CVFPU interface + output logic apu_busy_o, // handshake signals output logic apu_req_o, input logic apu_gnt_i, @@ -163,7 +164,6 @@ module cv32e40p_core logic ctrl_busy; logic if_busy; logic lsu_busy; - logic apu_busy; logic [31:0] pc_ex; // PC of last executed branch or cv.elw @@ -399,7 +399,7 @@ module cv32e40p_core .if_busy_i (if_busy), .ctrl_busy_i(ctrl_busy), .lsu_busy_i (lsu_busy), - .apu_busy_i (apu_busy), + .apu_busy_i (apu_busy_o), // PULP cluster .pulp_clock_en_i (pulp_clock_en_i), @@ -634,7 +634,7 @@ module cv32e40p_core .apu_write_regs_valid_o (apu_write_regs_valid), .apu_write_dep_i (apu_write_dep), .apu_perf_dep_o (perf_apu_dep), - .apu_busy_i (apu_busy), + .apu_busy_i (apu_busy_o), // CSR ID/EX .csr_access_ex_o (csr_access_ex), @@ -818,9 +818,9 @@ module cv32e40p_core .apu_perf_cont_o(perf_apu_cont), .apu_perf_wb_o (perf_apu_wb), .apu_ready_wb_o (apu_ready_wb), - .apu_busy_o (apu_busy), + .apu_busy_o (apu_busy_o), - // apu-interconnect + // CVFPU interface // handshake signals .apu_req_o (apu_req_o), .apu_gnt_i (apu_gnt_i), @@ -1057,9 +1057,9 @@ module cv32e40p_core assign csr_addr_int = csr_num_e'(csr_access_ex ? alu_operand_b_ex[11:0] : '0); // Floating-Point registers write - assign fregs_we = (FPU & !ZFINX) ? ((regfile_alu_we_fw && regfile_alu_waddr_fw[5]) || - (regfile_we_wb && regfile_waddr_fw_wb_o[5])) - : 1'b0; + assign fregs_we = (FPU == 1 & ZFINX == 0) ? ((regfile_alu_we_fw && regfile_alu_waddr_fw[5]) || + (regfile_we_wb && regfile_waddr_fw_wb_o[5])) + : 1'b0; /////////////////////////// // ____ __ __ ____ // diff --git a/rtl/cv32e40p_cs_registers.sv b/rtl/cv32e40p_cs_registers.sv index 609662830..d543179f5 100644 --- a/rtl/cv32e40p_cs_registers.sv +++ b/rtl/cv32e40p_cs_registers.sv @@ -509,7 +509,7 @@ module cv32e40p_cs_registers // mimpid, Machine Implementation ID CSR_MIMPID: begin - csr_rdata_int = (FPU || COREV_PULP || COREV_CLUSTER) ? 32'h1 : 'b0; + csr_rdata_int = (FPU == 1 || COREV_PULP == 1 || COREV_CLUSTER == 1) ? 32'h1 : 'b0; end // unimplemented, read 0 CSRs diff --git a/rtl/cv32e40p_decoder.sv b/rtl/cv32e40p_decoder.sv index d03027bae..c1608eb4a 100644 --- a/rtl/cv32e40p_decoder.sv +++ b/rtl/cv32e40p_decoder.sv @@ -1057,7 +1057,6 @@ module cv32e40p_decoder 5'b00000: begin fpu_op = cv32e40p_fpu_pkg::ADD; fp_op_group = ADDMUL; - apu_op_o = 2'b0; alu_op_b_mux_sel_o = OP_B_REGA_OR_FWD; alu_op_c_mux_sel_o = OP_C_REGB_OR_FWD; end @@ -1066,7 +1065,6 @@ module cv32e40p_decoder fpu_op = cv32e40p_fpu_pkg::ADD; fpu_op_mod = 1'b1; fp_op_group = ADDMUL; - apu_op_o = 2'b1; alu_op_b_mux_sel_o = OP_B_REGA_OR_FWD; alu_op_c_mux_sel_o = OP_C_REGB_OR_FWD; end @@ -1085,7 +1083,6 @@ module cv32e40p_decoder regb_used_o = 1'b0; fpu_op = cv32e40p_fpu_pkg::SQRT; fp_op_group = DIVSQRT; - apu_op_o = 1'b1; // rs2 must be zero if (instr_rdata_i[24:20] != 5'b00000) illegal_insn_o = 1'b1; end @@ -1213,7 +1210,6 @@ module cv32e40p_decoder fpu_op = cv32e40p_fpu_pkg::F2I; fp_op_group = CONV; fpu_op_mod = instr_rdata_i[20]; // signed/unsigned switch - apu_op_o = 2'b1; unique case (instr_rdata_i[26:25]) //fix for casting to different formats other than FP32 2'b00: begin @@ -1249,7 +1245,6 @@ module cv32e40p_decoder fpu_op = cv32e40p_fpu_pkg::I2F; fp_op_group = CONV; fpu_op_mod = instr_rdata_i[20]; // signed/unsigned switch - apu_op_o = 2'b0; // bits [21:20] used, other bits must be 0 if (instr_rdata_i[24:21]) illegal_insn_o = 1'b1; // in RV32, no casts to L allowed. end @@ -1323,20 +1318,20 @@ module cv32e40p_decoder // check rounding mode if (check_fprm) begin unique case (instr_rdata_i[14:12]) inside - [3'b000:3'b100]: ; //legal rounding modes + 3'b000, 3'b001, 3'b010, 3'b011, 3'b100: ; //legal rounding modes 3'b101: begin // Alternative Half-Precsision encded as fmt=10 and rm=101 if (~C_XF16ALT || fpu_dst_fmt_o != cv32e40p_fpu_pkg::FP16ALT) illegal_insn_o = 1'b1; // actual rounding mode from frm csr unique case (frm_i) inside - [3'b000:3'b100] : fp_rnd_mode_o = frm_i; //legal rounding modes - default : illegal_insn_o = 1'b1; + 3'b000, 3'b001, 3'b010, 3'b011, 3'b100 : fp_rnd_mode_o = frm_i; //legal rounding modes + default : illegal_insn_o = 1'b1; endcase end 3'b111: begin // rounding mode from frm csr unique case (frm_i) inside - [3'b000:3'b100] : fp_rnd_mode_o = frm_i; //legal rounding modes - default : illegal_insn_o = 1'b1; + 3'b000, 3'b001, 3'b010, 3'b011, 3'b100 : fp_rnd_mode_o = frm_i; //legal rounding modes + default : illegal_insn_o = 1'b1; endcase end default : illegal_insn_o = 1'b1; @@ -1364,6 +1359,7 @@ module cv32e40p_decoder NONCOMP : apu_lat_o = (FPU_OTHERS_LAT<2) ? FPU_OTHERS_LAT+1 : 2'h3; // CONV uses the same latency for all formats CONV : apu_lat_o = (FPU_OTHERS_LAT<2) ? FPU_OTHERS_LAT+1 : 2'h3; + default: ; endcase // Set FPnew OP and OPMOD as the APU op @@ -1425,25 +1421,21 @@ module cv32e40p_decoder unique case (instr_rdata_i[6:0]) // fmadd.fmt - FP Fused multiply-add OPCODE_OP_FMADD : begin - fpu_op = cv32e40p_fpu_pkg::FMADD; - apu_op_o = 2'b00; + fpu_op = cv32e40p_fpu_pkg::FMADD; end // fmsub.fmt - FP Fused multiply-subtract OPCODE_OP_FMSUB : begin - fpu_op = cv32e40p_fpu_pkg::FMADD; - fpu_op_mod = 1'b1; - apu_op_o = 2'b01; + fpu_op = cv32e40p_fpu_pkg::FMADD; + fpu_op_mod = 1'b1; end // fnmsub.fmt - FP Negated fused multiply-subtract OPCODE_OP_FNMSUB : begin - fpu_op = cv32e40p_fpu_pkg::FNMSUB; - apu_op_o = 2'b10; + fpu_op = cv32e40p_fpu_pkg::FNMSUB; end // fnmadd.fmt - FP Negated fused multiply-add OPCODE_OP_FNMADD : begin - fpu_op = cv32e40p_fpu_pkg::FNMSUB; - fpu_op_mod = 1'b1; - apu_op_o = 2'b11; + fpu_op = cv32e40p_fpu_pkg::FNMSUB; + fpu_op_mod = 1'b1; end default : ; endcase @@ -1459,19 +1451,19 @@ module cv32e40p_decoder // check rounding mode unique case (instr_rdata_i[14:12]) inside - [3'b000:3'b100]: ; //legal rounding modes + 3'b000, 3'b001, 3'b010, 3'b011, 3'b100: ; //legal rounding modes 3'b101: begin // Alternative Half-Precsision encded as fmt=10 and rm=101 if (~C_XF16ALT || fpu_dst_fmt_o != cv32e40p_fpu_pkg::FP16ALT) illegal_insn_o = 1'b1; // actual rounding mode from frm csr unique case (frm_i) inside - [3'b000:3'b100] : fp_rnd_mode_o = frm_i; //legal rounding modes + 3'b000, 3'b001, 3'b010, 3'b011, 3'b100 : fp_rnd_mode_o = frm_i; //legal rounding modes default : illegal_insn_o = 1'b1; endcase end 3'b111: begin // rounding mode from frm csr unique case (frm_i) inside - [3'b000:3'b100] : fp_rnd_mode_o = frm_i; //legal rounding modes + 3'b000, 3'b001, 3'b010, 3'b011, 3'b100 : fp_rnd_mode_o = frm_i; //legal rounding modes default : illegal_insn_o = 1'b1; endcase end @@ -1493,6 +1485,7 @@ module cv32e40p_decoder // Set FPnew OP and OPMOD as the APU op apu_op_o = {fpu_vec_op, fpu_op_mod, fpu_op}; + // No FPU or (ZFINX == 0 && MSTATUS.FS == FS_OFF) end else begin illegal_insn_o = 1'b1; @@ -1900,15 +1893,14 @@ module cv32e40p_decoder alu_op_b_mux_sel_o = OP_B_REGA_OR_FWD; unique case (instr_rdata_i[27:25]) - 3'b000: alu_operator_o = ALU_ADD; // cv.addNr - 3'b001: alu_operator_o = ALU_ADDU; // cv.adduNr - 3'b010: alu_operator_o = ALU_ADDR; // cv.addRNr - 3'b011: alu_operator_o = ALU_ADDUR; // cv.adduRNr - 3'b100: alu_operator_o = ALU_SUB; // cv.subNr - 3'b101: alu_operator_o = ALU_SUBU; // cv.subuNr - 3'b110: alu_operator_o = ALU_SUBR; // cv.subRNr - 3'b111: alu_operator_o = ALU_SUBUR; // cv.subuRNr - default: alu_operator_o = ALU_ADD; + 3'b001: alu_operator_o = ALU_ADDU; // cv.adduNr + 3'b010: alu_operator_o = ALU_ADDR; // cv.addRNr + 3'b011: alu_operator_o = ALU_ADDUR; // cv.adduRNr + 3'b100: alu_operator_o = ALU_SUB; // cv.subNr + 3'b101: alu_operator_o = ALU_SUBU; // cv.subuNr + 3'b110: alu_operator_o = ALU_SUBR; // cv.subRNr + 3'b111: alu_operator_o = ALU_SUBUR; // cv.subuRNr + default: alu_operator_o = ALU_ADD; // cv.addNr endcase end @@ -2085,7 +2077,6 @@ module cv32e40p_decoder // decide between using unsigned and rounding, and combinations unique case ({instr_rdata_i[31:30], instr_rdata_i[12]}) - {2'b00, 1'b0}: alu_operator_o = ALU_ADD; // cv.addN {2'b01, 1'b0}: alu_operator_o = ALU_ADDU; // cv.adduN {2'b10, 1'b0}: alu_operator_o = ALU_ADDR; // cv.addRN {2'b11, 1'b0}: alu_operator_o = ALU_ADDUR; // cv.adduRN @@ -2093,12 +2084,12 @@ module cv32e40p_decoder {2'b01, 1'b1}: alu_operator_o = ALU_SUBU; // cv.subuN {2'b10, 1'b1}: alu_operator_o = ALU_SUBR; // cv.subRN {2'b11, 1'b1}: alu_operator_o = ALU_SUBUR; // cv.subuRN - default : alu_operator_o = ALU_ADD; + default : alu_operator_o = ALU_ADD; // cv.addN endcase end - 2'b10, 2'b11: begin + default: begin // MUL/MAC with subword selection alu_en = 1'b0; mult_int_en = 1'b1; @@ -2126,7 +2117,6 @@ module cv32e40p_decoder mult_operator_o = MUL_I; end end - default: illegal_insn_o = 1'b1; endcase end else begin illegal_insn_o = 1'b1; @@ -2267,6 +2257,11 @@ module cv32e40p_decoder instr_rdata_i[25] != 1'b0) begin illegal_insn_o = 1'b1; end + // Imm6 restrictions + if ((instr_rdata_i[14:12] == 3'b110 && instr_rdata_i[24:23] != 2'b0) || + (instr_rdata_i[14:12] == 3'b111 && instr_rdata_i[24:22] != 3'b0)) begin + illegal_insn_o = 1'b1; + end end 6'b01001_0: begin // cv.sra alu_operator_o = ALU_SRA; @@ -2278,6 +2273,11 @@ module cv32e40p_decoder instr_rdata_i[25] != 1'b0) begin illegal_insn_o = 1'b1; end + // Imm6 restrictions + if ((instr_rdata_i[14:12] == 3'b110 && instr_rdata_i[24:23] != 2'b0) || + (instr_rdata_i[14:12] == 3'b111 && instr_rdata_i[24:22] != 3'b0)) begin + illegal_insn_o = 1'b1; + end end 6'b01010_0: begin // cv.sll alu_operator_o = ALU_SLL; @@ -2289,6 +2289,11 @@ module cv32e40p_decoder instr_rdata_i[25] != 1'b0) begin illegal_insn_o = 1'b1; end + // Imm6 restrictions + if ((instr_rdata_i[14:12] == 3'b110 && instr_rdata_i[24:23] != 2'b0) || + (instr_rdata_i[14:12] == 3'b111 && instr_rdata_i[24:22] != 3'b0)) begin + illegal_insn_o = 1'b1; + end end 6'b01011_0: begin // cv.or alu_operator_o = ALU_OR; @@ -2425,6 +2430,11 @@ module cv32e40p_decoder end default: illegal_insn_o = 1'b1; endcase + // Imm6 restrictions + if ((instr_rdata_i[12] == 1'b0 && instr_rdata_i[24:20] != 5'b0) || + (instr_rdata_i[12] == 1'b1 && instr_rdata_i[24:21] != 4'b0)) begin + illegal_insn_o = 1'b1; + end end 6'b11000_0: begin // cv.shuffle, cv.shuffleI0 alu_operator_o = ALU_SHUF; @@ -2439,6 +2449,10 @@ module cv32e40p_decoder instr_rdata_i[25] != 1'b0) begin illegal_insn_o = 1'b1; end + // Imm6 restriction + if (instr_rdata_i[14:12] == 3'b110 && instr_rdata_i[24:21] != 4'b0) begin + illegal_insn_o = 1'b1; + end end 6'b11001_0, 6'b11010_0, diff --git a/rtl/cv32e40p_ex_stage.sv b/rtl/cv32e40p_ex_stage.sv index 4d870a969..488a83dc2 100644 --- a/rtl/cv32e40p_ex_stage.sv +++ b/rtl/cv32e40p_ex_stage.sv @@ -213,9 +213,9 @@ module cv32e40p_ex_stage end end else begin regfile_alu_we_fw_o = regfile_alu_we_i & ~apu_en_i; - regfile_alu_we_fw_power_o = !COREV_PULP ? regfile_alu_we_i & ~apu_en_i : - regfile_alu_we_i & ~apu_en_i & - mult_ready & alu_ready & lsu_ready_ex_i; + regfile_alu_we_fw_power_o = (COREV_PULP == 0) ? regfile_alu_we_i & ~apu_en_i : + regfile_alu_we_i & ~apu_en_i & + mult_ready & alu_ready & lsu_ready_ex_i; regfile_alu_waddr_fw_o = regfile_alu_waddr_i; if (alu_en_i) regfile_alu_wdata_fw_o = alu_result; if (mult_en_i) regfile_alu_wdata_fw_o = mult_result; @@ -233,7 +233,7 @@ module cv32e40p_ex_stage if (regfile_we_lsu) begin regfile_we_wb_o = 1'b1; - regfile_we_wb_power_o = !COREV_PULP ? 1'b1 : ~data_misaligned_ex_i & wb_ready_i; + regfile_we_wb_power_o = (COREV_PULP == 0) ? 1'b1 : ~data_misaligned_ex_i & wb_ready_i; if (apu_valid & (!apu_singlecycle & !apu_multicycle)) begin wb_contention_lsu = 1'b1; end diff --git a/rtl/cv32e40p_fp_wrapper.sv b/rtl/cv32e40p_fp_wrapper.sv index 62ec46c2f..839d58aae 100644 --- a/rtl/cv32e40p_fp_wrapper.sv +++ b/rtl/cv32e40p_fp_wrapper.sv @@ -14,7 +14,7 @@ module cv32e40p_fp_wrapper import cv32e40p_apu_core_pkg::*; #( - parameter FPU_ADDMUL_LAT = 0, // Floating-Point ADDition/MULtiplication computing lane pipeline registers number + parameter FPU_ADDMUL_LAT = 0, // Floating-Point ADDition/MULtiplication computing lane pipeline registers number parameter FPU_OTHERS_LAT = 0 // Floating-Point COMParison/CONVersion computing lanes pipeline registers number ) ( // Clock and Reset diff --git a/rtl/cv32e40p_id_stage.sv b/rtl/cv32e40p_id_stage.sv index 93bb13803..f323cbe5f 100644 --- a/rtl/cv32e40p_id_stage.sv +++ b/rtl/cv32e40p_id_stage.sv @@ -1514,9 +1514,13 @@ module cv32e40p_id_stage if (id_valid_o) begin // unstall the whole pipeline alu_en_ex_o <= alu_en; if (alu_en) begin - alu_operator_ex_o <= alu_operator; - alu_operand_a_ex_o <= alu_operand_a; - alu_operand_b_ex_o <= alu_operand_b; + alu_operator_ex_o <= alu_operator; + alu_operand_a_ex_o <= alu_operand_a; + if (alu_op_b_mux_sel == OP_B_REGB_OR_FWD && (alu_operator == ALU_CLIP || alu_operator == ALU_CLIPU)) begin + alu_operand_b_ex_o <= {1'b0, alu_operand_b[30:0]}; + end else begin + alu_operand_b_ex_o <= alu_operand_b; + end alu_operand_c_ex_o <= alu_operand_c; bmask_a_ex_o <= bmask_a_id; bmask_b_ex_o <= bmask_b_id; diff --git a/rtl/cv32e40p_load_store_unit.sv b/rtl/cv32e40p_load_store_unit.sv index 7c08ffe11..f9c4db4a8 100644 --- a/rtl/cv32e40p_load_store_unit.sv +++ b/rtl/cv32e40p_load_store_unit.sv @@ -121,18 +121,18 @@ module cv32e40p_load_store_unit #( 2'b00: begin // Writing a word if (misaligned_st == 1'b0) begin // non-misaligned case case (data_addr_int[1:0]) - 2'b00: data_be = 4'b1111; - 2'b01: data_be = 4'b1110; - 2'b10: data_be = 4'b1100; - 2'b11: data_be = 4'b1000; + 2'b00: data_be = 4'b1111; + 2'b01: data_be = 4'b1110; + 2'b10: data_be = 4'b1100; + default: data_be = 4'b1000; endcase ; // case (data_addr_int[1:0]) end else begin // misaligned case case (data_addr_int[1:0]) - 2'b00: data_be = 4'b0000; // this is not used, but included for completeness - 2'b01: data_be = 4'b0001; - 2'b10: data_be = 4'b0011; - 2'b11: data_be = 4'b0111; + 2'b01: data_be = 4'b0001; + 2'b10: data_be = 4'b0011; + 2'b11: data_be = 4'b0111; + default: data_be = 4'b0000; // this is not used, but included for completeness endcase ; // case (data_addr_int[1:0]) end @@ -141,10 +141,10 @@ module cv32e40p_load_store_unit #( 2'b01: begin // Writing a half word if (misaligned_st == 1'b0) begin // non-misaligned case case (data_addr_int[1:0]) - 2'b00: data_be = 4'b0011; - 2'b01: data_be = 4'b0110; - 2'b10: data_be = 4'b1100; - 2'b11: data_be = 4'b1000; + 2'b00: data_be = 4'b0011; + 2'b01: data_be = 4'b0110; + 2'b10: data_be = 4'b1100; + default: data_be = 4'b1000; endcase ; // case (data_addr_int[1:0]) end else begin // misaligned case @@ -154,10 +154,10 @@ module cv32e40p_load_store_unit #( 2'b10, 2'b11: begin // Writing a byte case (data_addr_int[1:0]) - 2'b00: data_be = 4'b0001; - 2'b01: data_be = 4'b0010; - 2'b10: data_be = 4'b0100; - 2'b11: data_be = 4'b1000; + 2'b00: data_be = 4'b0001; + 2'b01: data_be = 4'b0010; + 2'b10: data_be = 4'b0100; + default: data_be = 4'b1000; endcase ; // case (data_addr_int[1:0]) end diff --git a/rtl/cv32e40p_register_file_latch.sv b/rtl/cv32e40p_register_file_latch.sv index d8e2f4aa0..57383e6a5 100644 --- a/rtl/cv32e40p_register_file_latch.sv +++ b/rtl/cv32e40p_register_file_latch.sv @@ -172,8 +172,8 @@ module cv32e40p_register_file #( mem[0] = '0; for (k = 1; k < NUM_WORDS; k++) begin : w_WordIter - if (~rst_n) mem[k] = '0; - else if (mem_clocks[k] == 1'b1) mem[k] = waddr_onehot_b_q[k] ? wdata_b_q : wdata_a_q; + if (~rst_n) mem[k] <= '0; + else if (mem_clocks[k] == 1'b1) mem[k] <= waddr_onehot_b_q[k] ? wdata_b_q : wdata_a_q; end end @@ -182,9 +182,9 @@ module cv32e40p_register_file #( always_latch begin : latch_wdata_fp if (FPU == 1) begin for (l = 0; l < NUM_FP_WORDS; l++) begin : w_WordIter - if (~rst_n) mem_fp[l] = '0; + if (~rst_n) mem_fp[l] <= '0; else if (mem_clocks[l+NUM_WORDS] == 1'b1) - mem_fp[l] = waddr_onehot_b_q[l+NUM_WORDS] ? wdata_b_q : wdata_a_q; + mem_fp[l] <= waddr_onehot_b_q[l+NUM_WORDS] ? wdata_b_q : wdata_a_q; end end end diff --git a/rtl/cv32e40p_top.sv b/rtl/cv32e40p_top.sv index 7ddd2d5a2..43eee77bd 100644 --- a/rtl/cv32e40p_top.sv +++ b/rtl/cv32e40p_top.sv @@ -1,15 +1,27 @@ -// Copyright 2018 ETH Zurich and University of Bologna. -// Copyright and related rights are licensed under the Solderpad Hardware -// License, Version 0.51 (the "License"); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law -// or agreed to in writing, software, hardware and materials distributed under -// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR -// CONDITIONS OF ANY KIND, either express or implied. See the License for the -// specific language governing permissions and limitations under the License. - -// Top file instantiating a CV32E40P core and an optional FPU -// Contributor: Davide Schiavone +// Copyright 2024 Dolphin Design +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the "License"); +// you may not use this file except in compliance with the License, or, +// at your option, the Apache License version 2.0. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +///////////////////////////////////////////////////////////////////////////// +// // +// Contributors: Pascal Gouedo, Dolphin Design // +// // +// Description: Top level module of CV32E40P instantiating the Core and // +// an optional CVFPU with its clock gating cell. // +// // +///////////////////////////////////////////////////////////////////////////// module cv32e40p_top #( parameter COREV_PULP = 0, // PULP ISA Extension (incl. custom CSRs and hardware loop, excl. cv.elw) @@ -70,7 +82,7 @@ module cv32e40p_top #( import cv32e40p_apu_core_pkg::*; // Core to FPU - logic clk; + logic apu_busy; logic apu_req; logic [ APU_NARGS_CPU-1:0][31:0] apu_operands; logic [ APU_WOP_CPU-1:0] apu_op; @@ -82,6 +94,8 @@ module cv32e40p_top #( logic [ 31:0] apu_rdata; logic [APU_NUSFLAGS_CPU-1:0] apu_rflags; + logic apu_clk_en, apu_clk; + // Instantiate the Core cv32e40p_core #( .COREV_PULP (COREV_PULP), @@ -119,6 +133,7 @@ module cv32e40p_top #( .data_wdata_o (data_wdata_o), .data_rdata_i (data_rdata_i), + .apu_busy_o (apu_busy), .apu_req_o (apu_req), .apu_gnt_i (apu_gnt), .apu_operands_o(apu_operands), @@ -143,12 +158,15 @@ module cv32e40p_top #( generate if (FPU) begin : fpu_gen + + assign apu_clk_en = apu_req | apu_busy; + // FPU clock gate cv32e40p_clock_gate core_clock_gate_i ( .clk_i (clk_i), - .en_i (!core_sleep_o), + .en_i (apu_clk_en), .scan_cg_en_i(scan_cg_en_i), - .clk_o (clk) + .clk_o (apu_clk) ); // Instantiate the FPU wrapper @@ -156,7 +174,7 @@ module cv32e40p_top #( .FPU_ADDMUL_LAT(FPU_ADDMUL_LAT), .FPU_OTHERS_LAT(FPU_OTHERS_LAT) ) fp_wrapper_i ( - .clk_i (clk), + .clk_i (apu_clk), .rst_ni (rst_ni), .apu_req_i (apu_req), .apu_gnt_o (apu_gnt), diff --git a/rtl/vendor/pulp_platform_fpu_div_sqrt_mvp.lock.hjson b/rtl/vendor/pulp_platform_fpu_div_sqrt_mvp.lock.hjson deleted file mode 100644 index f9ec4482c..000000000 --- a/rtl/vendor/pulp_platform_fpu_div_sqrt_mvp.lock.hjson +++ /dev/null @@ -1,14 +0,0 @@ -// Copyright lowRISC contributors. -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 - -// This file is generated by the util/vendor script. Please do not modify it -// manually. - -{ - upstream: - { - url: https://github.com/pulp-platform/fpu_div_sqrt_mvp.git - rev: 86e1f558b3c95e91577c41b2fc452c86b04e85ac - } -} diff --git a/rtl/vendor/pulp_platform_fpu_div_sqrt_mvp.vendor.hjson b/rtl/vendor/pulp_platform_fpu_div_sqrt_mvp.vendor.hjson deleted file mode 100644 index 4e10e4e1a..000000000 --- a/rtl/vendor/pulp_platform_fpu_div_sqrt_mvp.vendor.hjson +++ /dev/null @@ -1,19 +0,0 @@ -// Copyright 2022 OpenHW Group -// Solderpad Hardware License, Version 2.1, see LICENSE.md for details. -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -{ - name: "pulp_platform_fpu_div_sqrt_mvp", - target_dir: "pulp_platform_fpu_div_sqrt_mvp", - - upstream: { - url: "https://github.com/pulp-platform/fpu_div_sqrt_mvp.git", - rev: "86e1f558b3c95e91577c41b2fc452c86b04e85ac", - }, - - exclude_from_upstream: [ - "CHANGELOG.md", - "Bender.yml", - "src_files.yml", - "document" - ] -} diff --git a/rtl/vendor/pulp_platform_fpu_div_sqrt_mvp/LICENSE b/rtl/vendor/pulp_platform_fpu_div_sqrt_mvp/LICENSE deleted file mode 100644 index 18e4f6769..000000000 --- a/rtl/vendor/pulp_platform_fpu_div_sqrt_mvp/LICENSE +++ /dev/null @@ -1,176 +0,0 @@ -SOLDERPAD HARDWARE LICENSE version 0.51 - -This license is based closely on the Apache License Version 2.0, but is not -approved or endorsed by the Apache Foundation. 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You may obtain a copy of the License at -// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law -// or agreed to in writing, software, hardware and materials distributed under -// this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR -// CONDITIONS OF ANY KIND, either express or implied. See the License for the -// specific language governing permissions and limitations under the License. - -//////////////////////////////////////////////////////////////////////////////// -// Company: IIS @ ETHZ - Federal Institute of Technology // -// // -// Engineers: Lei Li lile@iis.ee.ethz.ch // -// // -// Additional contributions by: // -// // -// // -// // -// Create Date: 04/03/2018 // -// Design Name: FPU // -// Module Name: control_mvp.sv // -// Project Name: Private FPU // -// Language: SystemVerilog // -// // -// Description: the control logic of div and sqrt // -// // -// Revision Date: 12/04/2018 // -// Lei Li // -// To address some requirements by Stefan and add low power // -// control for special cases // -// Revision Date: 13/04/2018 // -// Lei Li // -// To fix some bug found in Control FSM // -// when Iteration_unit_num_S = 2'b10 // -// // -// // -// // -//////////////////////////////////////////////////////////////////////////////// - -import defs_div_sqrt_mvp::*; - -module control_mvp - - (//Input - input logic Clk_CI, - input logic Rst_RBI, - input logic Div_start_SI , - input logic Sqrt_start_SI, - input logic Start_SI, - input logic Kill_SI, - input logic Special_case_SBI, - input logic Special_case_dly_SBI, - input logic [C_PC-1:0] Precision_ctl_SI, - input logic [1:0] Format_sel_SI, - input logic [C_MANT_FP64:0] Numerator_DI, - input logic [C_EXP_FP64:0] Exp_num_DI, - input logic [C_MANT_FP64:0] Denominator_DI, - input logic [C_EXP_FP64:0] Exp_den_DI, - - - output logic Div_start_dly_SO , - output logic Sqrt_start_dly_SO, - output logic Div_enable_SO, - output logic Sqrt_enable_SO, - - - //To next stage - output logic Full_precision_SO, - output logic FP32_SO, - output logic FP64_SO, - output logic FP16_SO, - output logic FP16ALT_SO, - - output logic Ready_SO, - output logic Done_SO, - - output logic [C_MANT_FP64+4:0] Mant_result_prenorm_DO, - // output logic [3:0] Round_bit_DO, - output logic [C_EXP_FP64+1:0] Exp_result_prenorm_DO - ); - - logic [C_MANT_FP64+1+4:0] Partial_remainder_DN,Partial_remainder_DP; //58bits,r=q+2 - logic [C_MANT_FP64+4:0] Quotient_DP; //57bits - ///////////////////////////////////////////////////////////////////////////// - // Assign Inputs // - ///////////////////////////////////////////////////////////////////////////// - logic [C_MANT_FP64+1:0] Numerator_se_D; //sign extension and hidden bit - logic [C_MANT_FP64+1:0] Denominator_se_D; //signa extension and hidden bit - logic [C_MANT_FP64+1:0] Denominator_se_DB; //1's complement - - assign Numerator_se_D={1'b0,Numerator_DI}; - - assign Denominator_se_D={1'b0,Denominator_DI}; - - always_comb - begin - if(FP32_SO) - begin - Denominator_se_DB={~Denominator_se_D[C_MANT_FP64+1:C_MANT_FP64-C_MANT_FP32], {(C_MANT_FP64-C_MANT_FP32){1'b0}} }; - end - else if(FP64_SO) begin - Denominator_se_DB=~Denominator_se_D; - end - else if(FP16_SO) begin - Denominator_se_DB={~Denominator_se_D[C_MANT_FP64+1:C_MANT_FP64-C_MANT_FP16], {(C_MANT_FP64-C_MANT_FP16){1'b0}} }; - end - else begin - Denominator_se_DB={~Denominator_se_D[C_MANT_FP64+1:C_MANT_FP64-C_MANT_FP16ALT], {(C_MANT_FP64-C_MANT_FP16ALT){1'b0}} }; - end - end - - - logic [C_MANT_FP64+1:0] Mant_D_sqrt_Norm; - - assign Mant_D_sqrt_Norm=Exp_num_DI[0]?{1'b0,Numerator_DI}:{Numerator_DI,1'b0}; //for sqrt - - ///////////////////////////////////////////////////////////////////////////// - // Format Selection // - ///////////////////////////////////////////////////////////////////////////// - logic [1:0] Format_sel_S; - - always_ff @(posedge Clk_CI, negedge Rst_RBI) - begin - if(~Rst_RBI) - begin - Format_sel_S<='b0; - end - else if(Start_SI&&Ready_SO) - begin - Format_sel_S<=Format_sel_SI; - end - else - begin - Format_sel_S<=Format_sel_S; - end - end - - assign FP32_SO = (Format_sel_S==2'b00); - assign FP64_SO = (Format_sel_S==2'b01); - assign FP16_SO = (Format_sel_S==2'b10); - assign FP16ALT_SO = (Format_sel_S==2'b11); - - - - ///////////////////////////////////////////////////////////////////////////// - // Precision Control // - ///////////////////////////////////////////////////////////////////////////// - - logic [C_PC-1:0] Precision_ctl_S; - always_ff @(posedge Clk_CI, negedge Rst_RBI) - begin - if(~Rst_RBI) - begin - Precision_ctl_S<='b0; - end - else if(Start_SI&&Ready_SO) - begin - Precision_ctl_S<=Precision_ctl_SI; - end - else - begin - Precision_ctl_S<=Precision_ctl_S; - end - end - assign Full_precision_SO = (Precision_ctl_S==6'h00); - - - - logic [5:0] State_ctl_S; - logic [5:0] State_Two_iteration_unit_S; - logic [5:0] State_Four_iteration_unit_S; - - assign State_Two_iteration_unit_S = Precision_ctl_S[C_PC-1:1]; //Two iteration units - assign State_Four_iteration_unit_S = Precision_ctl_S[C_PC-1:2]; //Four iteration units - always_comb - begin - case(Iteration_unit_num_S) -//////////////////////one iteration unit, start/////////////////////////////////////// - 2'b00: //one iteration unit - begin - case(Format_sel_S) - 2'b00: //FP32 - begin - if(Full_precision_SO) - begin - State_ctl_S = 6'h1b; //24+4 more iterations for rounding bits - end - else - begin - State_ctl_S = Precision_ctl_S; - end - end - 2'b01: //FP64 - begin - if(Full_precision_SO) - begin - State_ctl_S = 6'h38; //53+4 more iterations for rounding bits - end - else - begin - State_ctl_S = Precision_ctl_S; - end - end - 2'b10: //FP16 - begin - if(Full_precision_SO) - begin - State_ctl_S = 6'h0e; //11+4 more iterations for rounding bits - end - else - begin - State_ctl_S = Precision_ctl_S; - end - end - 2'b11: //FP16ALT - begin - if(Full_precision_SO) - begin - State_ctl_S = 6'h0b; //8+4 more iterations for rounding bits - end - else - begin - State_ctl_S = Precision_ctl_S; - end - end - endcase - end -//////////////////////one iteration unit, end/////////////////////////////////////// - -//////////////////////two iteration units, start/////////////////////////////////////// - 2'b01: //two iteration units - begin - case(Format_sel_S) - 2'b00: //FP32 - begin - if(Full_precision_SO) - begin - State_ctl_S = 6'h0d; //24+4 more iterations for rounding bits - end - else - begin - State_ctl_S = State_Two_iteration_unit_S; - end - end - 2'b01: //FP64 - begin - if(Full_precision_SO) - begin - State_ctl_S = 6'h1b; //53+3 more iterations for rounding bits - end - else - begin - State_ctl_S = State_Two_iteration_unit_S; - end - end - 2'b10: //FP16 - begin - if(Full_precision_SO) - begin - State_ctl_S = 6'h06; //11+3 more iterations for rounding bits - end - else - begin - State_ctl_S = State_Two_iteration_unit_S; - end - end - 2'b11: //FP16ALT - begin - if(Full_precision_SO) - begin - State_ctl_S = 6'h05; //8+4 more iterations for rounding bits - end - else - begin - State_ctl_S = State_Two_iteration_unit_S; - end - end - endcase - end -//////////////////////two iteration units, end/////////////////////////////////////// - -//////////////////////three iteration units, start/////////////////////////////////////// - 2'b10: //three iteration units - begin - case(Format_sel_S) - 2'b00: //FP32 - begin - case(Precision_ctl_S) - 6'h00: - begin - State_ctl_S = 6'h08; //24+3 more iterations for rounding bits - end - 6'h06,6'h07,6'h08: - begin - State_ctl_S = 6'h02; - end - 6'h09,6'h0a,6'h0b: - begin - State_ctl_S = 6'h03; - end - 6'h0c,6'h0d,6'h0e: - begin - State_ctl_S = 6'h04; - end - 6'h0f,6'h10,6'h11: - begin - State_ctl_S = 6'h05; - end - 6'h12,6'h13,6'h14: - begin - State_ctl_S = 6'h06; - end - 6'h15,6'h16,6'h17: - begin - State_ctl_S = 6'h07; - end - default: - begin - State_ctl_S = 6'h08; //24+3 more iterations for rounding bits - end - endcase - end - 2'b01: //FP64 - begin - case(Precision_ctl_S) - 6'h00: - begin - State_ctl_S = 6'h12; //53+4 more iterations for rounding bits - end - 6'h06,6'h07,6'h08: - begin - State_ctl_S = 6'h02; - end - 6'h09,6'h0a,6'h0b: - begin - State_ctl_S = 6'h03; - end - 6'h0c,6'h0d,6'h0e: - begin - State_ctl_S = 6'h04; - end - 6'h0f,6'h10,6'h11: - begin - State_ctl_S = 6'h05; - end - 6'h12,6'h13,6'h14: - begin - State_ctl_S = 6'h06; - end - 6'h15,6'h16,6'h17: - begin - State_ctl_S = 6'h07; - end - 6'h18,6'h19,6'h1a: - begin - State_ctl_S = 6'h08; - end - 6'h1b,6'h1c,6'h1d: - begin - State_ctl_S = 6'h09; - end - 6'h1e,6'h1f,6'h20: - begin - State_ctl_S = 6'h0a; - end - 6'h21,6'h22,6'h23: - begin - State_ctl_S = 6'h0b; - end - 6'h24,6'h25,6'h26: - begin - State_ctl_S = 6'h0c; - end - 6'h27,6'h28,6'h29: - begin - State_ctl_S = 6'h0d; - end - 6'h2a,6'h2b,6'h2c: - begin - State_ctl_S = 6'h0e; - end - 6'h2d,6'h2e,6'h2f: - begin - State_ctl_S = 6'h0f; - end - 6'h30,6'h31,6'h32: - begin - State_ctl_S = 6'h10; - end - 6'h33,6'h34,6'h35: - begin - State_ctl_S = 6'h11; - end - default: - begin - State_ctl_S = 6'h12; //53+4 more iterations for rounding bits - end - endcase - end - 2'b10: //FP16 - begin - case(Precision_ctl_S) - 6'h00: - begin - State_ctl_S = 6'h04; //12+3 more iterations for rounding bits - end - 6'h06,6'h07,6'h08: - begin - State_ctl_S = 6'h02; - end - 6'h09,6'h0a,6'h0b: - begin - State_ctl_S = 6'h03; - end - default: - begin - State_ctl_S = 6'h04; //12+3 more iterations for rounding bits - end - endcase - end - 2'b11: //FP16ALT - begin - case(Precision_ctl_S) - 6'h00: - begin - State_ctl_S = 6'h03; //8+4 more iterations for rounding bits - end - 6'h06,6'h07,6'h08: - begin - State_ctl_S = 6'h02; - end - default: - begin - State_ctl_S = 6'h03; //8+4 more iterations for rounding bits - end - endcase - end - endcase - end -//////////////////////three iteration units, end/////////////////////////////////////// - -//////////////////////four iteration units, start/////////////////////////////////////// - 2'b11: //four iteration units - begin - case(Format_sel_S) - 2'b00: //FP32 - begin - if(Full_precision_SO) - begin - State_ctl_S = 6'h06; //24+4 more iterations for rounding bits - end - else - begin - State_ctl_S = State_Four_iteration_unit_S; - end - end - 2'b01: //FP64 - begin - if(Full_precision_SO) - begin - State_ctl_S = 6'h0d; //53+3 more iterations for rounding bits - end - else - begin - State_ctl_S = State_Four_iteration_unit_S; - end - end - 2'b10: //FP16 - begin - if(Full_precision_SO) - begin - State_ctl_S = 6'h03; //11+4 more iterations for rounding bits - end - else - begin - State_ctl_S = State_Four_iteration_unit_S; - end - end - 2'b11: //FP16ALT - begin - if(Full_precision_SO) - begin - State_ctl_S = 6'h02; //8+4 more iterations for rounding bits - end - else - begin - State_ctl_S = State_Four_iteration_unit_S; - end - end - endcase - end -//////////////////////four iteration units, end/////////////////////////////////////// - - endcase - end - - - ///////////////////////////////////////////////////////////////////////////// - // control logic // - ///////////////////////////////////////////////////////////////////////////// - - logic Div_start_dly_S; - - always_ff @(posedge Clk_CI, negedge Rst_RBI) // generate Div_start_dly_S signal - begin - if(~Rst_RBI) - begin - Div_start_dly_S<=1'b0; - end - else if(Div_start_SI&&Ready_SO) - begin - Div_start_dly_S<=1'b1; - end - else - begin - Div_start_dly_S<=1'b0; - end - end - - assign Div_start_dly_SO=Div_start_dly_S; - - always_ff @(posedge Clk_CI, negedge Rst_RBI) begin // generate Div_enable_SO signal - if(~Rst_RBI) - Div_enable_SO<=1'b0; - // Synchronous reset with Flush - else if (Kill_SI) - Div_enable_SO <= 1'b0; - else if(Div_start_SI&&Ready_SO) - Div_enable_SO<=1'b1; - else if(Done_SO) - Div_enable_SO<=1'b0; - else - Div_enable_SO<=Div_enable_SO; - end - - logic Sqrt_start_dly_S; - - always_ff @(posedge Clk_CI, negedge Rst_RBI) // generate Sqrt_start_dly_SI signal - begin - if(~Rst_RBI) - begin - Sqrt_start_dly_S<=1'b0; - end - else if(Sqrt_start_SI&&Ready_SO) - begin - Sqrt_start_dly_S<=1'b1; - end - else - begin - Sqrt_start_dly_S<=1'b0; - end - end - assign Sqrt_start_dly_SO=Sqrt_start_dly_S; - - always_ff @(posedge Clk_CI, negedge Rst_RBI) begin // generate Sqrt_enable_SO signal - if(~Rst_RBI) - Sqrt_enable_SO<=1'b0; - else if (Kill_SI) - Sqrt_enable_SO <= 1'b0; - else if(Sqrt_start_SI&&Ready_SO) - Sqrt_enable_SO<=1'b1; - else if(Done_SO) - Sqrt_enable_SO<=1'b0; - else - Sqrt_enable_SO<=Sqrt_enable_SO; - end - - logic [5:0] Crtl_cnt_S; - logic Start_dly_S; - - assign Start_dly_S=Div_start_dly_S |Sqrt_start_dly_S; - - logic Fsm_enable_S; - assign Fsm_enable_S=( (Start_dly_S | (| Crtl_cnt_S)) && (~Kill_SI) && Special_case_dly_SBI); - - logic Final_state_S; - assign Final_state_S= (Crtl_cnt_S==State_ctl_S); - - - always_ff @(posedge Clk_CI, negedge Rst_RBI) //control_FSM - begin - if (~Rst_RBI) - begin - Crtl_cnt_S <= '0; - end - else if (Final_state_S | Kill_SI) - begin - Crtl_cnt_S <= '0; - end - else if(Fsm_enable_S) // one cycle Start_SI - begin - Crtl_cnt_S <= Crtl_cnt_S+1; - end - else - begin - Crtl_cnt_S <= '0; - end - end // always_ff - - - - always_ff @(posedge Clk_CI, negedge Rst_RBI) //Generate Done_SO, they can share this Done_SO. - begin - if(~Rst_RBI) - begin - Done_SO<=1'b0; - end - else if(Start_SI&&Ready_SO) - begin - if(~Special_case_SBI) - begin - Done_SO<=1'b1; - end - else - begin - Done_SO<=1'b0; - end - end - else if(Final_state_S) - begin - Done_SO<=1'b1; - end - else - begin - Done_SO<=1'b0; - end - end - - - - - always_ff @(posedge Clk_CI, negedge Rst_RBI) //Generate Ready_SO - begin - if(~Rst_RBI) - begin - Ready_SO<=1'b1; - end - - else if(Start_SI&&Ready_SO) - begin - if(~Special_case_SBI) - begin - Ready_SO<=1'b1; - end - else - begin - Ready_SO<=1'b0; - end - end - else if(Final_state_S | Kill_SI) - begin - Ready_SO<=1'b1; - end - else - begin - Ready_SO<=Ready_SO; - end - end - - - ///////////////////////////////////////////////////////////////////////////// - // Declarations for square root when Iteration_unit_num_S = 2'b00, start // - //////////////////////////////////////////////////////////////////////////// - - logic Qcnt_one_0; - logic Qcnt_one_1; - logic [1:0] Qcnt_one_2; - logic [2:0] Qcnt_one_3; - logic [3:0] Qcnt_one_4; - logic [4:0] Qcnt_one_5; - logic [5:0] Qcnt_one_6; - logic [6:0] Qcnt_one_7; - logic [7:0] Qcnt_one_8; - logic [8:0] Qcnt_one_9; - logic [9:0] Qcnt_one_10; - logic [10:0] Qcnt_one_11; - logic [11:0] Qcnt_one_12; - logic [12:0] Qcnt_one_13; - logic [13:0] Qcnt_one_14; - logic [14:0] Qcnt_one_15; - logic [15:0] Qcnt_one_16; - logic [16:0] Qcnt_one_17; - logic [17:0] Qcnt_one_18; - logic [18:0] Qcnt_one_19; - logic [19:0] Qcnt_one_20; - logic [20:0] Qcnt_one_21; - logic [21:0] Qcnt_one_22; - logic [22:0] Qcnt_one_23; - logic [23:0] Qcnt_one_24; - logic [24:0] Qcnt_one_25; - logic [25:0] Qcnt_one_26; - logic [26:0] Qcnt_one_27; - logic [27:0] Qcnt_one_28; - logic [28:0] Qcnt_one_29; - logic [29:0] Qcnt_one_30; - logic [30:0] Qcnt_one_31; - logic [31:0] Qcnt_one_32; - logic [32:0] Qcnt_one_33; - logic [33:0] Qcnt_one_34; - logic [34:0] Qcnt_one_35; - logic [35:0] Qcnt_one_36; - logic [36:0] Qcnt_one_37; - logic [37:0] Qcnt_one_38; - logic [38:0] Qcnt_one_39; - logic [39:0] Qcnt_one_40; - logic [40:0] Qcnt_one_41; - logic [41:0] Qcnt_one_42; - logic [42:0] Qcnt_one_43; - logic [43:0] Qcnt_one_44; - logic [44:0] Qcnt_one_45; - logic [45:0] Qcnt_one_46; - logic [46:0] Qcnt_one_47; - logic [47:0] Qcnt_one_48; - logic [48:0] Qcnt_one_49; - logic [49:0] Qcnt_one_50; - logic [50:0] Qcnt_one_51; - logic [51:0] Qcnt_one_52; - logic [52:0] Qcnt_one_53; - logic [53:0] Qcnt_one_54; - logic [54:0] Qcnt_one_55; - logic [55:0] Qcnt_one_56; - logic [56:0] Qcnt_one_57; - logic [57:0] Qcnt_one_58; - logic [58:0] Qcnt_one_59; - logic [59:0] Qcnt_one_60; - - ///////////////////////////////////////////////////////////////////////////// - // Declarations for square root when Iteration_unit_num_S = 2'b00, end // - //////////////////////////////////////////////////////////////////////////// - - - - ///////////////////////////////////////////////////////////////////////////// - // Declarations for square root when Iteration_unit_num_S = 2'b01, start // - //////////////////////////////////////////////////////////////////////////// - logic [1:0] Qcnt_two_0; - logic [2:0] Qcnt_two_1; - logic [4:0] Qcnt_two_2; - logic [6:0] Qcnt_two_3; - logic [8:0] Qcnt_two_4; - logic [10:0] Qcnt_two_5; - logic [12:0] Qcnt_two_6; - logic [14:0] Qcnt_two_7; - logic [16:0] Qcnt_two_8; - logic [18:0] Qcnt_two_9; - logic [20:0] Qcnt_two_10; - logic [22:0] Qcnt_two_11; - logic [24:0] Qcnt_two_12; - logic [26:0] Qcnt_two_13; - logic [28:0] Qcnt_two_14; - logic [30:0] Qcnt_two_15; - logic [32:0] Qcnt_two_16; - logic [34:0] Qcnt_two_17; - logic [36:0] Qcnt_two_18; - logic [38:0] Qcnt_two_19; - logic [40:0] Qcnt_two_20; - logic [42:0] Qcnt_two_21; - logic [44:0] Qcnt_two_22; - logic [46:0] Qcnt_two_23; - logic [48:0] Qcnt_two_24; - logic [50:0] Qcnt_two_25; - logic [52:0] Qcnt_two_26; - logic [54:0] Qcnt_two_27; - logic [56:0] Qcnt_two_28; - ///////////////////////////////////////////////////////////////////////////// - // Declarations for square root when Iteration_unit_num_S = 2'b01, end // - //////////////////////////////////////////////////////////////////////////// - - - ///////////////////////////////////////////////////////////////////////////// - // Declarations for square root when Iteration_unit_num_S = 2'b10, start // - //////////////////////////////////////////////////////////////////////////// - logic [2:0] Qcnt_three_0; - logic [4:0] Qcnt_three_1; - logic [7:0] Qcnt_three_2; - logic [10:0] Qcnt_three_3; - logic [13:0] Qcnt_three_4; - logic [16:0] Qcnt_three_5; - logic [19:0] Qcnt_three_6; - logic [22:0] Qcnt_three_7; - logic [25:0] Qcnt_three_8; - logic [28:0] Qcnt_three_9; - logic [31:0] Qcnt_three_10; - logic [34:0] Qcnt_three_11; - logic [37:0] Qcnt_three_12; - logic [40:0] Qcnt_three_13; - logic [43:0] Qcnt_three_14; - logic [46:0] Qcnt_three_15; - logic [49:0] Qcnt_three_16; - logic [52:0] Qcnt_three_17; - logic [55:0] Qcnt_three_18; - logic [58:0] Qcnt_three_19; - logic [61:0] Qcnt_three_20; - ///////////////////////////////////////////////////////////////////////////// - // Declarations for square root when Iteration_unit_num_S = 2'b10, end // - //////////////////////////////////////////////////////////////////////////// - - - ///////////////////////////////////////////////////////////////////////////// - // Declarations for square root when Iteration_unit_num_S = 2'b11, start // - //////////////////////////////////////////////////////////////////////////// - logic [3:0] Qcnt_four_0; - logic [6:0] Qcnt_four_1; - logic [10:0] Qcnt_four_2; - logic [14:0] Qcnt_four_3; - logic [18:0] Qcnt_four_4; - logic [22:0] Qcnt_four_5; - logic [26:0] Qcnt_four_6; - logic [30:0] Qcnt_four_7; - logic [34:0] Qcnt_four_8; - logic [38:0] Qcnt_four_9; - logic [42:0] Qcnt_four_10; - logic [46:0] Qcnt_four_11; - logic [50:0] Qcnt_four_12; - logic [54:0] Qcnt_four_13; - logic [58:0] Qcnt_four_14; - - ///////////////////////////////////////////////////////////////////////////// - // Declarations for square root when Iteration_unit_num_S = 2'b11, end // - //////////////////////////////////////////////////////////////////////////// - - - - logic [C_MANT_FP64+1+4:0] Sqrt_R0,Sqrt_Q0,Q_sqrt0,Q_sqrt_com_0; - logic [C_MANT_FP64+1+4:0] Sqrt_R1,Sqrt_Q1,Q_sqrt1,Q_sqrt_com_1; - logic [C_MANT_FP64+1+4:0] Sqrt_R2,Sqrt_Q2,Q_sqrt2,Q_sqrt_com_2; - logic [C_MANT_FP64+1+4:0] Sqrt_R3,Sqrt_Q3,Q_sqrt3,Q_sqrt_com_3,Sqrt_R4; //Sqrt_Q4; - - - logic [1:0] Sqrt_DI [3:0]; - logic [1:0] Sqrt_DO [3:0]; - logic Sqrt_carry_DO; - - - logic [C_MANT_FP64+1+4:0] Iteration_cell_a_D [3:0]; - logic [C_MANT_FP64+1+4:0] Iteration_cell_b_D [3:0]; - logic [C_MANT_FP64+1+4:0] Iteration_cell_a_BMASK_D [3:0]; - logic [C_MANT_FP64+1+4:0] Iteration_cell_b_BMASK_D [3:0]; - logic Iteration_cell_carry_D [3:0]; - logic [C_MANT_FP64+1+4:0] Iteration_cell_sum_D [3:0]; - logic [C_MANT_FP64+1+4:0] Iteration_cell_sum_AMASK_D [3:0]; - - - logic [3:0] Sqrt_quotinent_S; - - - always_comb - begin // - case (Format_sel_S) - 2'b00: - begin - Sqrt_quotinent_S = {(~Iteration_cell_sum_AMASK_D[0][C_MANT_FP32+5]),(~Iteration_cell_sum_AMASK_D[1][C_MANT_FP32+5]),(~Iteration_cell_sum_AMASK_D[2][C_MANT_FP32+5]),(~Iteration_cell_sum_AMASK_D[3][C_MANT_FP32+5])}; - Q_sqrt_com_0 ={ {(C_MANT_FP64-C_MANT_FP32){1'b0}},~Q_sqrt0[C_MANT_FP32+5:0] }; - Q_sqrt_com_1 ={ {(C_MANT_FP64-C_MANT_FP32){1'b0}},~Q_sqrt1[C_MANT_FP32+5:0] }; - Q_sqrt_com_2 ={ {(C_MANT_FP64-C_MANT_FP32){1'b0}},~Q_sqrt2[C_MANT_FP32+5:0] }; - Q_sqrt_com_3 ={ {(C_MANT_FP64-C_MANT_FP32){1'b0}},~Q_sqrt3[C_MANT_FP32+5:0] }; - end - 2'b01: - begin - Sqrt_quotinent_S = {Iteration_cell_carry_D[0],Iteration_cell_carry_D[1],Iteration_cell_carry_D[2],Iteration_cell_carry_D[3]}; - Q_sqrt_com_0=~Q_sqrt0; - Q_sqrt_com_1=~Q_sqrt1; - Q_sqrt_com_2=~Q_sqrt2; - Q_sqrt_com_3=~Q_sqrt3; - end - 2'b10: - begin - Sqrt_quotinent_S = {(~Iteration_cell_sum_AMASK_D[0][C_MANT_FP16+5]),(~Iteration_cell_sum_AMASK_D[1][C_MANT_FP16+5]),(~Iteration_cell_sum_AMASK_D[2][C_MANT_FP16+5]),(~Iteration_cell_sum_AMASK_D[3][C_MANT_FP16+5])}; - Q_sqrt_com_0 ={ {(C_MANT_FP64-C_MANT_FP16){1'b0}},~Q_sqrt0[C_MANT_FP16+5:0] }; - Q_sqrt_com_1 ={ {(C_MANT_FP64-C_MANT_FP16){1'b0}},~Q_sqrt1[C_MANT_FP16+5:0] }; - Q_sqrt_com_2 ={ {(C_MANT_FP64-C_MANT_FP16){1'b0}},~Q_sqrt2[C_MANT_FP16+5:0] }; - Q_sqrt_com_3 ={ {(C_MANT_FP64-C_MANT_FP16){1'b0}},~Q_sqrt3[C_MANT_FP16+5:0] }; - end - 2'b11: - begin - Sqrt_quotinent_S = {(~Iteration_cell_sum_AMASK_D[0][C_MANT_FP16ALT+5]),(~Iteration_cell_sum_AMASK_D[1][C_MANT_FP16ALT+5]),(~Iteration_cell_sum_AMASK_D[2][C_MANT_FP16ALT+5]),(~Iteration_cell_sum_AMASK_D[3][C_MANT_FP16ALT+5])}; - Q_sqrt_com_0 ={ {(C_MANT_FP64-C_MANT_FP16ALT){1'b0}},~Q_sqrt0[C_MANT_FP16ALT+5:0] }; - Q_sqrt_com_1 ={ {(C_MANT_FP64-C_MANT_FP16ALT){1'b0}},~Q_sqrt1[C_MANT_FP16ALT+5:0] }; - Q_sqrt_com_2 ={ {(C_MANT_FP64-C_MANT_FP16ALT){1'b0}},~Q_sqrt2[C_MANT_FP16ALT+5:0] }; - Q_sqrt_com_3 ={ {(C_MANT_FP64-C_MANT_FP16ALT){1'b0}},~Q_sqrt3[C_MANT_FP16ALT+5:0] }; - end - endcase - end - - - - assign Qcnt_one_0= {1'b0}; //qk for each feedback - assign Qcnt_one_1= {Quotient_DP[0]}; - assign Qcnt_one_2= {Quotient_DP[1:0]}; - assign Qcnt_one_3= {Quotient_DP[2:0]}; - assign Qcnt_one_4= {Quotient_DP[3:0]}; - assign Qcnt_one_5= {Quotient_DP[4:0]}; - assign Qcnt_one_6= {Quotient_DP[5:0]}; - assign Qcnt_one_7= {Quotient_DP[6:0]}; - assign Qcnt_one_8= {Quotient_DP[7:0]}; - assign Qcnt_one_9= {Quotient_DP[8:0]}; - assign Qcnt_one_10= {Quotient_DP[9:0]}; - assign Qcnt_one_11= {Quotient_DP[10:0]}; - assign Qcnt_one_12= {Quotient_DP[11:0]}; - assign Qcnt_one_13= {Quotient_DP[12:0]}; - assign Qcnt_one_14= {Quotient_DP[13:0]}; - assign Qcnt_one_15= {Quotient_DP[14:0]}; - assign Qcnt_one_16= {Quotient_DP[15:0]}; - assign Qcnt_one_17= {Quotient_DP[16:0]}; - assign Qcnt_one_18= {Quotient_DP[17:0]}; - assign Qcnt_one_19= {Quotient_DP[18:0]}; - assign Qcnt_one_20= {Quotient_DP[19:0]}; - assign Qcnt_one_21= {Quotient_DP[20:0]}; - assign Qcnt_one_22= {Quotient_DP[21:0]}; - assign Qcnt_one_23= {Quotient_DP[22:0]}; - assign Qcnt_one_24= {Quotient_DP[23:0]}; - assign Qcnt_one_25= {Quotient_DP[24:0]}; - assign Qcnt_one_26= {Quotient_DP[25:0]}; - assign Qcnt_one_27= {Quotient_DP[26:0]}; - assign Qcnt_one_28= {Quotient_DP[27:0]}; - assign Qcnt_one_29= {Quotient_DP[28:0]}; - assign Qcnt_one_30= {Quotient_DP[29:0]}; - assign Qcnt_one_31= {Quotient_DP[30:0]}; - assign Qcnt_one_32= {Quotient_DP[31:0]}; - assign Qcnt_one_33= {Quotient_DP[32:0]}; - assign Qcnt_one_34= {Quotient_DP[33:0]}; - assign Qcnt_one_35= {Quotient_DP[34:0]}; - assign Qcnt_one_36= {Quotient_DP[35:0]}; - assign Qcnt_one_37= {Quotient_DP[36:0]}; - assign Qcnt_one_38= {Quotient_DP[37:0]}; - assign Qcnt_one_39= {Quotient_DP[38:0]}; - assign Qcnt_one_40= {Quotient_DP[39:0]}; - assign Qcnt_one_41= {Quotient_DP[40:0]}; - assign Qcnt_one_42= {Quotient_DP[41:0]}; - assign Qcnt_one_43= {Quotient_DP[42:0]}; - assign Qcnt_one_44= {Quotient_DP[43:0]}; - assign Qcnt_one_45= {Quotient_DP[44:0]}; - assign Qcnt_one_46= {Quotient_DP[45:0]}; - assign Qcnt_one_47= {Quotient_DP[46:0]}; - assign Qcnt_one_48= {Quotient_DP[47:0]}; - assign Qcnt_one_49= {Quotient_DP[48:0]}; - assign Qcnt_one_50= {Quotient_DP[49:0]}; - assign Qcnt_one_51= {Quotient_DP[50:0]}; - assign Qcnt_one_52= {Quotient_DP[51:0]}; - assign Qcnt_one_53= {Quotient_DP[52:0]}; - assign Qcnt_one_54= {Quotient_DP[53:0]}; - assign Qcnt_one_55= {Quotient_DP[54:0]}; - assign Qcnt_one_56= {Quotient_DP[55:0]}; - assign Qcnt_one_57= {Quotient_DP[56:0]}; - - - assign Qcnt_two_0 = {1'b0, Sqrt_quotinent_S[3]}; //qk for each feedback - assign Qcnt_two_1 = {Quotient_DP[1:0],Sqrt_quotinent_S[3]}; - assign Qcnt_two_2 = {Quotient_DP[3:0],Sqrt_quotinent_S[3]}; - assign Qcnt_two_3 = {Quotient_DP[5:0],Sqrt_quotinent_S[3]}; - assign Qcnt_two_4 = {Quotient_DP[7:0],Sqrt_quotinent_S[3]}; - assign Qcnt_two_5 = {Quotient_DP[9:0],Sqrt_quotinent_S[3]}; - assign Qcnt_two_6 = {Quotient_DP[11:0],Sqrt_quotinent_S[3]}; - assign Qcnt_two_7 = {Quotient_DP[13:0],Sqrt_quotinent_S[3]}; - assign Qcnt_two_8 = {Quotient_DP[15:0],Sqrt_quotinent_S[3]}; - assign Qcnt_two_9 = {Quotient_DP[17:0],Sqrt_quotinent_S[3]}; - assign Qcnt_two_10 = {Quotient_DP[19:0],Sqrt_quotinent_S[3]}; - assign Qcnt_two_11 = {Quotient_DP[21:0],Sqrt_quotinent_S[3]}; - assign Qcnt_two_12 = {Quotient_DP[23:0],Sqrt_quotinent_S[3]}; - assign Qcnt_two_13 = {Quotient_DP[25:0],Sqrt_quotinent_S[3]}; - assign Qcnt_two_14 = {Quotient_DP[27:0],Sqrt_quotinent_S[3]}; - assign Qcnt_two_15 = {Quotient_DP[29:0],Sqrt_quotinent_S[3]}; - assign Qcnt_two_16 = {Quotient_DP[31:0],Sqrt_quotinent_S[3]}; - assign Qcnt_two_17 = {Quotient_DP[33:0],Sqrt_quotinent_S[3]}; - assign Qcnt_two_18 = {Quotient_DP[35:0],Sqrt_quotinent_S[3]}; - assign Qcnt_two_19 = {Quotient_DP[37:0],Sqrt_quotinent_S[3]}; - assign Qcnt_two_20 = {Quotient_DP[39:0],Sqrt_quotinent_S[3]}; - assign Qcnt_two_21 = {Quotient_DP[41:0],Sqrt_quotinent_S[3]}; - assign Qcnt_two_22 = {Quotient_DP[43:0],Sqrt_quotinent_S[3]}; - assign Qcnt_two_23 = {Quotient_DP[45:0],Sqrt_quotinent_S[3]}; - assign Qcnt_two_24 = {Quotient_DP[47:0],Sqrt_quotinent_S[3]}; - assign Qcnt_two_25 = {Quotient_DP[49:0],Sqrt_quotinent_S[3]}; - assign Qcnt_two_26 = {Quotient_DP[51:0],Sqrt_quotinent_S[3]}; - assign Qcnt_two_27 = {Quotient_DP[53:0],Sqrt_quotinent_S[3]}; - assign Qcnt_two_28 = {Quotient_DP[55:0],Sqrt_quotinent_S[3]}; - - - assign Qcnt_three_0 = {1'b0, Sqrt_quotinent_S[3],Sqrt_quotinent_S[2]}; //qk for each feedback - assign Qcnt_three_1 = {Quotient_DP[2:0],Sqrt_quotinent_S[3],Sqrt_quotinent_S[2]}; - assign Qcnt_three_2 = {Quotient_DP[5:0],Sqrt_quotinent_S[3],Sqrt_quotinent_S[2]}; - assign Qcnt_three_3 = {Quotient_DP[8:0],Sqrt_quotinent_S[3],Sqrt_quotinent_S[2]}; - assign Qcnt_three_4 = {Quotient_DP[11:0],Sqrt_quotinent_S[3],Sqrt_quotinent_S[2]}; - assign Qcnt_three_5 = {Quotient_DP[14:0],Sqrt_quotinent_S[3],Sqrt_quotinent_S[2]}; - assign Qcnt_three_6 = {Quotient_DP[17:0],Sqrt_quotinent_S[3],Sqrt_quotinent_S[2]}; - assign Qcnt_three_7 = {Quotient_DP[20:0],Sqrt_quotinent_S[3],Sqrt_quotinent_S[2]}; - assign Qcnt_three_8 = {Quotient_DP[23:0],Sqrt_quotinent_S[3],Sqrt_quotinent_S[2]}; - assign Qcnt_three_9 = {Quotient_DP[26:0],Sqrt_quotinent_S[3],Sqrt_quotinent_S[2]}; - assign Qcnt_three_10 = {Quotient_DP[29:0],Sqrt_quotinent_S[3],Sqrt_quotinent_S[2]}; - assign Qcnt_three_11 = {Quotient_DP[32:0],Sqrt_quotinent_S[3],Sqrt_quotinent_S[2]}; - assign Qcnt_three_12 = {Quotient_DP[35:0],Sqrt_quotinent_S[3],Sqrt_quotinent_S[2]}; - assign Qcnt_three_13 = {Quotient_DP[38:0],Sqrt_quotinent_S[3],Sqrt_quotinent_S[2]}; - assign Qcnt_three_14 = {Quotient_DP[41:0],Sqrt_quotinent_S[3],Sqrt_quotinent_S[2]}; - assign Qcnt_three_15 = {Quotient_DP[44:0],Sqrt_quotinent_S[3],Sqrt_quotinent_S[2]}; - assign Qcnt_three_16 = {Quotient_DP[47:0],Sqrt_quotinent_S[3],Sqrt_quotinent_S[2]}; - assign Qcnt_three_17 = {Quotient_DP[50:0],Sqrt_quotinent_S[3],Sqrt_quotinent_S[2]}; - assign Qcnt_three_18 = {Quotient_DP[53:0],Sqrt_quotinent_S[3],Sqrt_quotinent_S[2]}; - assign Qcnt_three_19 = {Quotient_DP[56:0],Sqrt_quotinent_S[3],Sqrt_quotinent_S[2]}; - - - assign Qcnt_four_0 = {1'b0, Sqrt_quotinent_S[3],Sqrt_quotinent_S[2],Sqrt_quotinent_S[1]}; - assign Qcnt_four_1 = {Quotient_DP[3:0],Sqrt_quotinent_S[3],Sqrt_quotinent_S[2],Sqrt_quotinent_S[1]}; - assign Qcnt_four_2 = {Quotient_DP[7:0],Sqrt_quotinent_S[3],Sqrt_quotinent_S[2],Sqrt_quotinent_S[1]}; - assign Qcnt_four_3 = {Quotient_DP[11:0],Sqrt_quotinent_S[3],Sqrt_quotinent_S[2],Sqrt_quotinent_S[1]}; - assign Qcnt_four_4 = {Quotient_DP[15:0],Sqrt_quotinent_S[3],Sqrt_quotinent_S[2],Sqrt_quotinent_S[1]}; - assign Qcnt_four_5 = {Quotient_DP[19:0],Sqrt_quotinent_S[3],Sqrt_quotinent_S[2],Sqrt_quotinent_S[1]}; - assign Qcnt_four_6 = {Quotient_DP[23:0],Sqrt_quotinent_S[3],Sqrt_quotinent_S[2],Sqrt_quotinent_S[1]}; - assign Qcnt_four_7 = {Quotient_DP[27:0],Sqrt_quotinent_S[3],Sqrt_quotinent_S[2],Sqrt_quotinent_S[1]}; - assign Qcnt_four_8 = {Quotient_DP[31:0],Sqrt_quotinent_S[3],Sqrt_quotinent_S[2],Sqrt_quotinent_S[1]}; - assign Qcnt_four_9 = {Quotient_DP[35:0],Sqrt_quotinent_S[3],Sqrt_quotinent_S[2],Sqrt_quotinent_S[1]}; - assign Qcnt_four_10 = {Quotient_DP[39:0],Sqrt_quotinent_S[3],Sqrt_quotinent_S[2],Sqrt_quotinent_S[1]}; - assign Qcnt_four_11 = {Quotient_DP[43:0],Sqrt_quotinent_S[3],Sqrt_quotinent_S[2],Sqrt_quotinent_S[1]}; - assign Qcnt_four_12 = {Quotient_DP[47:0],Sqrt_quotinent_S[3],Sqrt_quotinent_S[2],Sqrt_quotinent_S[1]}; - assign Qcnt_four_13 = {Quotient_DP[51:0],Sqrt_quotinent_S[3],Sqrt_quotinent_S[2],Sqrt_quotinent_S[1]}; - assign Qcnt_four_14 = {Quotient_DP[55:0],Sqrt_quotinent_S[3],Sqrt_quotinent_S[2],Sqrt_quotinent_S[1]}; - - - - - always_comb begin // the intermediate operands for sqrt - - case(Iteration_unit_num_S) - 2'b00: - begin - - ///////////////////////////////////////////////////////////////////////////// - // Operands for square root when Iteration_unit_num_S = 2'b00, start // - ///////////////////////////////////////////////////////////////////////////// - - - - - case(Crtl_cnt_S) - - 6'b000000: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64+1:C_MANT_FP64]; - Q_sqrt0={{(C_MANT_FP64+5){1'b0}},Qcnt_one_0}; - Sqrt_Q0=Q_sqrt_com_0; - end - 6'b000001: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-1:C_MANT_FP64-2]; - Q_sqrt0={{(C_MANT_FP64+5){1'b0}},Qcnt_one_1}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - end - 6'b000010: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-3:C_MANT_FP64-4]; - Q_sqrt0={{(C_MANT_FP64+4){1'b0}},Qcnt_one_2}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - end - 6'b000011: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-5:C_MANT_FP64-6]; - Q_sqrt0={{(C_MANT_FP64+3){1'b0}},Qcnt_one_3}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - end - 6'b000100: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-7:C_MANT_FP64-8]; - Q_sqrt0={{(C_MANT_FP64+2){1'b0}},Qcnt_one_4}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - end - 6'b000101: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-9:C_MANT_FP64-10]; - Q_sqrt0={{(C_MANT_FP64+1){1'b0}},Qcnt_one_5}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - end - 6'b000110: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-11:C_MANT_FP64-12]; - Q_sqrt0={{(C_MANT_FP64){1'b0}},Qcnt_one_6}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - end - 6'b000111: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-13:C_MANT_FP64-14]; - Q_sqrt0={{(C_MANT_FP64-1){1'b0}},Qcnt_one_7}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - end - 6'b001000: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-15:C_MANT_FP64-16]; - Q_sqrt0={{(C_MANT_FP64-2){1'b0}},Qcnt_one_8}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - end - 6'b001001: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-17:C_MANT_FP64-18]; - Q_sqrt0={{(C_MANT_FP64-3){1'b0}},Qcnt_one_9}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - end - 6'b001010: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-19:C_MANT_FP64-20]; - Q_sqrt0={{(C_MANT_FP64-4){1'b0}},Qcnt_one_10}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - end - 6'b001011: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-21:C_MANT_FP64-22]; - Q_sqrt0={{(C_MANT_FP64-5){1'b0}},Qcnt_one_11}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - end - 6'b001100: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-23:C_MANT_FP64-24]; - Q_sqrt0={{(C_MANT_FP64-6){1'b0}},Qcnt_one_12}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - end - 6'b001101: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-25:C_MANT_FP64-26]; - Q_sqrt0={{(C_MANT_FP64-7){1'b0}},Qcnt_one_13}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - end - 6'b001110: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-27:C_MANT_FP64-28]; - Q_sqrt0={{(C_MANT_FP64-8){1'b0}},Qcnt_one_14}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - end - 6'b001111: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-29:C_MANT_FP64-30]; - Q_sqrt0={{(C_MANT_FP64-9){1'b0}},Qcnt_one_15}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - end - 6'b010000: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-31:C_MANT_FP64-32]; - Q_sqrt0={{(C_MANT_FP64-10){1'b0}},Qcnt_one_16}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - end - 6'b010001: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-33:C_MANT_FP64-34]; - Q_sqrt0={{(C_MANT_FP64-11){1'b0}},Qcnt_one_17}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - end - 6'b010010: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-35:C_MANT_FP64-36]; - Q_sqrt0={{(C_MANT_FP64-12){1'b0}},Qcnt_one_18}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - end - 6'b010011: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-37:C_MANT_FP64-38]; - Q_sqrt0={{(C_MANT_FP64-13){1'b0}},Qcnt_one_19}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - end - 6'b010100: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-39:C_MANT_FP64-40]; - Q_sqrt0={{(C_MANT_FP64-14){1'b0}},Qcnt_one_20}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - end - 6'b010101: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-41:C_MANT_FP64-42]; - Q_sqrt0={{(C_MANT_FP64-15){1'b0}},Qcnt_one_21}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - end - 6'b010110: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-43:C_MANT_FP64-44]; - Q_sqrt0={{(C_MANT_FP64-16){1'b0}},Qcnt_one_22}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - end - 6'b010111: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-45:C_MANT_FP64-46]; - Q_sqrt0={{(C_MANT_FP64-17){1'b0}},Qcnt_one_23}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - end - 6'b011000: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-47:C_MANT_FP64-48]; - Q_sqrt0={{(C_MANT_FP64-18){1'b0}},Qcnt_one_24}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - end - 6'b011001: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-49:C_MANT_FP64-50]; - Q_sqrt0={{(C_MANT_FP64-19){1'b0}},Qcnt_one_25}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - end - 6'b011010: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-51:C_MANT_FP64-52]; - Q_sqrt0={{(C_MANT_FP64-20){1'b0}},Qcnt_one_26}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - end - 6'b011011: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-21){1'b0}},Qcnt_one_27}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - end - 6'b011100: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-22){1'b0}},Qcnt_one_28}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - end - 6'b011101: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-23){1'b0}},Qcnt_one_29}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - end - 6'b011110: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-24){1'b0}},Qcnt_one_30}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - end - 6'b011111: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-25){1'b0}},Qcnt_one_31}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - end - 6'b100000: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-26){1'b0}},Qcnt_one_32}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - end - 6'b100001: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-27){1'b0}},Qcnt_one_33}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - end - 6'b100010: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-28){1'b0}},Qcnt_one_34}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - end - 6'b100011: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-29){1'b0}},Qcnt_one_35}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - end - 6'b100100: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-30){1'b0}},Qcnt_one_36}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - end - 6'b100101: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-31){1'b0}},Qcnt_one_37}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - end - 6'b100110: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-32){1'b0}},Qcnt_one_38}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - end - 6'b100111: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-33){1'b0}},Qcnt_one_39}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - end - 6'b101000: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-34){1'b0}},Qcnt_one_40}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - end - 6'b101001: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-35){1'b0}},Qcnt_one_41}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - end - 6'b101010: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-36){1'b0}},Qcnt_one_42}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - end - 6'b101011: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-37){1'b0}},Qcnt_one_43}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - end - 6'b101100: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-38){1'b0}},Qcnt_one_44}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - end - 6'b101101: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-39){1'b0}},Qcnt_one_45}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - end - 6'b101110: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-40){1'b0}},Qcnt_one_46}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - end - 6'b101111: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-41){1'b0}},Qcnt_one_47}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - end - 6'b110000: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-42){1'b0}},Qcnt_one_48}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - end - 6'b110001: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-43){1'b0}},Qcnt_one_49}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - end - 6'b110010: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-44){1'b0}},Qcnt_one_50}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - end - 6'b110011: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-45){1'b0}},Qcnt_one_51}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - end - 6'b110100: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-46){1'b0}},Qcnt_one_52}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - end - 6'b110101: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-47){1'b0}},Qcnt_one_53}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - end - 6'b110110: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-48){1'b0}},Qcnt_one_54}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - end - 6'b110111: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-49){1'b0}},Qcnt_one_55}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - end - 6'b111000: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-50){1'b0}},Qcnt_one_56}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - end - - default: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0='0; - Sqrt_Q0='0; - end - endcase - end - - - ///////////////////////////////////////////////////////////////////////////// - // Operands for square root when Iteration_unit_num_S = 2'b00, end // - ///////////////////////////////////////////////////////////////////////////// - - - 2'b01: - begin - ///////////////////////////////////////////////////////////////////////////// - // Operands for square root when Iteration_unit_num_S = 2'b01, start // - ///////////////////////////////////////////////////////////////////////////// - case(Crtl_cnt_S) - - 6'b000000: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64+1:C_MANT_FP64]; - Q_sqrt0={{(C_MANT_FP64+5){1'b0}},Qcnt_two_0[1]}; - Sqrt_Q0=Q_sqrt_com_0; - Sqrt_DI[1]=Mant_D_sqrt_Norm[C_MANT_FP64-1:C_MANT_FP64-2]; - Q_sqrt1={{(C_MANT_FP64+4){1'b0}},Qcnt_two_0[1:0]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - end - - 6'b000001: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-3:C_MANT_FP64-4]; - Q_sqrt0={{(C_MANT_FP64+4){1'b0}},Qcnt_two_1[2:1]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=Mant_D_sqrt_Norm[C_MANT_FP64-5:C_MANT_FP64-6]; - Q_sqrt1={{(C_MANT_FP64+3){1'b0}},Qcnt_two_1[2:0]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - end - - 6'b000010: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-7:C_MANT_FP64-8]; - Q_sqrt0={{(C_MANT_FP64+2){1'b0}},Qcnt_two_2[4:1]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=Mant_D_sqrt_Norm[C_MANT_FP64-9:C_MANT_FP64-10]; - Q_sqrt1={{(C_MANT_FP64+1){1'b0}},Qcnt_two_2[4:0]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - end - - 6'b000011: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-11:C_MANT_FP64-12]; - Q_sqrt0={{(C_MANT_FP64){1'b0}},Qcnt_two_3[6:1]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=Mant_D_sqrt_Norm[C_MANT_FP64-13:C_MANT_FP64-14]; - Q_sqrt1={{(C_MANT_FP64-1){1'b0}},Qcnt_two_3[6:0]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - end - - 6'b000100: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-15:C_MANT_FP64-16]; - Q_sqrt0={{(C_MANT_FP64-2){1'b0}},Qcnt_two_4[8:1]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=Mant_D_sqrt_Norm[C_MANT_FP64-17:C_MANT_FP64-18]; - Q_sqrt1={{(C_MANT_FP64-3){1'b0}},Qcnt_two_4[8:0]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - end - - 6'b000101: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-19:C_MANT_FP64-20]; - Q_sqrt0={{(C_MANT_FP64-4){1'b0}},Qcnt_two_5[10:1]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=Mant_D_sqrt_Norm[C_MANT_FP64-21:C_MANT_FP64-22]; - Q_sqrt1={{(C_MANT_FP64-5){1'b0}},Qcnt_two_5[10:0]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - end - - 6'b000110: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-23:C_MANT_FP64-24]; - Q_sqrt0={{(C_MANT_FP64-6){1'b0}},Qcnt_two_6[12:1]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=Mant_D_sqrt_Norm[C_MANT_FP64-25:C_MANT_FP64-26]; - Q_sqrt1={{(C_MANT_FP64-7){1'b0}},Qcnt_two_6[12:0]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - end - - 6'b000111: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-27:C_MANT_FP64-28]; - Q_sqrt0={{(C_MANT_FP64-8){1'b0}},Qcnt_two_7[14:1]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=Mant_D_sqrt_Norm[C_MANT_FP64-29:C_MANT_FP64-30]; - Q_sqrt1={{(C_MANT_FP64-9){1'b0}},Qcnt_two_7[14:0]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - end - - 6'b001000: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-31:C_MANT_FP64-32]; - Q_sqrt0={{(C_MANT_FP64-10){1'b0}},Qcnt_two_8[16:1]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=Mant_D_sqrt_Norm[C_MANT_FP64-33:C_MANT_FP64-34]; - Q_sqrt1={{(C_MANT_FP64-11){1'b0}},Qcnt_two_8[16:0]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - end - - 6'b001001: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-35:C_MANT_FP64-36]; - Q_sqrt0={{(C_MANT_FP64-12){1'b0}},Qcnt_two_9[18:1]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=Mant_D_sqrt_Norm[C_MANT_FP64-37:C_MANT_FP64-38]; - Q_sqrt1={{(C_MANT_FP64-13){1'b0}},Qcnt_two_9[18:0]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - end - - 6'b001010: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-39:C_MANT_FP64-40]; - Q_sqrt0={{(C_MANT_FP64-14){1'b0}},Qcnt_two_10[20:1]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=Mant_D_sqrt_Norm[C_MANT_FP64-41:C_MANT_FP64-42]; - Q_sqrt1={{(C_MANT_FP64-15){1'b0}},Qcnt_two_10[20:0]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - end - - 6'b001011: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-43:C_MANT_FP64-44]; - Q_sqrt0={{(C_MANT_FP64-16){1'b0}},Qcnt_two_11[22:1]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=Mant_D_sqrt_Norm[C_MANT_FP64-45:C_MANT_FP64-46]; - Q_sqrt1={{(C_MANT_FP64-17){1'b0}},Qcnt_two_11[22:0]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - end - - 6'b001100: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-47:C_MANT_FP64-48]; - Q_sqrt0={{(C_MANT_FP64-18){1'b0}},Qcnt_two_12[24:1]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=Mant_D_sqrt_Norm[C_MANT_FP64-49:C_MANT_FP64-50]; - Q_sqrt1={{(C_MANT_FP64-19){1'b0}},Qcnt_two_12[24:0]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - end - - 6'b001101: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-51:C_MANT_FP64-52]; - Q_sqrt0={{(C_MANT_FP64-20){1'b0}},Qcnt_two_13[26:1]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=2'b00; - Q_sqrt1={{(C_MANT_FP64-21){1'b0}},Qcnt_two_13[26:0]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - end - - 6'b001110: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-22){1'b0}},Qcnt_two_14[28:1]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=2'b00; - Q_sqrt1={{(C_MANT_FP64-23){1'b0}},Qcnt_two_14[28:0]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - end - - 6'b001111: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-24){1'b0}},Qcnt_two_15[30:1]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=2'b00; - Q_sqrt1={{(C_MANT_FP64-25){1'b0}},Qcnt_two_15[30:0]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - end - - 6'b010000: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-26){1'b0}},Qcnt_two_16[32:1]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=2'b00; - Q_sqrt1={{(C_MANT_FP64-27){1'b0}},Qcnt_two_16[32:0]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - end - - 6'b010001: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-28){1'b0}},Qcnt_two_17[34:1]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=2'b00; - Q_sqrt1={{(C_MANT_FP64-29){1'b0}},Qcnt_two_17[34:0]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - end - - 6'b010010: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-30){1'b0}},Qcnt_two_18[36:1]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=2'b00; - Q_sqrt1={{(C_MANT_FP64-31){1'b0}},Qcnt_two_18[36:0]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - end - - 6'b010011: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-32){1'b0}},Qcnt_two_19[38:1]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=2'b00; - Q_sqrt1={{(C_MANT_FP64-33){1'b0}},Qcnt_two_19[38:0]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - end - - 6'b010100: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-34){1'b0}},Qcnt_two_20[40:1]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=2'b00; - Q_sqrt1={{(C_MANT_FP64-35){1'b0}},Qcnt_two_20[40:0]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - end - - 6'b010101: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-36){1'b0}},Qcnt_two_21[42:1]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=2'b00; - Q_sqrt1={{(C_MANT_FP64-37){1'b0}},Qcnt_two_21[42:0]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - end - - 6'b010110: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-38){1'b0}},Qcnt_two_22[44:1]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=2'b00; - Q_sqrt1={{(C_MANT_FP64-39){1'b0}},Qcnt_two_22[44:0]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - end - - 6'b010111: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-40){1'b0}},Qcnt_two_23[46:1]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=2'b00; - Q_sqrt1={{(C_MANT_FP64-41){1'b0}},Qcnt_two_23[46:0]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - end - - 6'b011000: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-42){1'b0}},Qcnt_two_24[48:1]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=2'b00; - Q_sqrt1={{(C_MANT_FP64-43){1'b0}},Qcnt_two_24[48:0]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - end - - 6'b011001: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-44){1'b0}},Qcnt_two_25[50:1]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=2'b00; - Q_sqrt1={{(C_MANT_FP64-45){1'b0}},Qcnt_two_25[50:0]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - end - - 6'b011010: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-46){1'b0}},Qcnt_two_26[52:1]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=2'b00; - Q_sqrt1={{(C_MANT_FP64-47){1'b0}},Qcnt_two_26[52:0]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - end - - 6'b011011: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-48){1'b0}},Qcnt_two_27[54:1]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=2'b00; - Q_sqrt1={{(C_MANT_FP64-49){1'b0}},Qcnt_two_27[54:0]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - end - - 6'b011100: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-50){1'b0}},Qcnt_two_28[56:1]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=2'b00; - Q_sqrt1={{(C_MANT_FP64-51){1'b0}},Qcnt_two_28[56:0]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - end - - default: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64+1:C_MANT_FP64]; - Q_sqrt0={{(C_MANT_FP64+5){1'b0}},Qcnt_two_0[1]}; - Sqrt_Q0=Q_sqrt_com_0; - Sqrt_DI[1]=Mant_D_sqrt_Norm[C_MANT_FP64-1:C_MANT_FP64-2]; - Q_sqrt1={{(C_MANT_FP64+4){1'b0}},Qcnt_two_0[1:0]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - end - - endcase - end - - ///////////////////////////////////////////////////////////////////////////// - // Operands for square root when Iteration_unit_num_S = 2'b01, end // - ///////////////////////////////////////////////////////////////////////////// - - - 2'b10: - begin - ///////////////////////////////////////////////////////////////////////////// - // Operands for square root when Iteration_unit_num_S = 2'b10, start // - ///////////////////////////////////////////////////////////////////////////// - - case(Crtl_cnt_S) - 6'b000000: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64+1:C_MANT_FP64]; - Q_sqrt0={{(C_MANT_FP64+5){1'b0}},Qcnt_three_0[2]}; - Sqrt_Q0=Q_sqrt_com_0; - Sqrt_DI[1]=Mant_D_sqrt_Norm[C_MANT_FP64-1:C_MANT_FP64-2]; - Q_sqrt1={{(C_MANT_FP64+4){1'b0}},Qcnt_three_0[2:1]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - Sqrt_DI[2]=Mant_D_sqrt_Norm[C_MANT_FP64-3:C_MANT_FP64-4]; - Q_sqrt2={{(C_MANT_FP64+3){1'b0}},Qcnt_three_0[2:0]}; - Sqrt_Q2=Sqrt_quotinent_S[2]?Q_sqrt_com_2:Q_sqrt2; - end - - 6'b000001: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-5:C_MANT_FP64-6]; - Q_sqrt0={{(C_MANT_FP64+2){1'b0}},Qcnt_three_1[4:2]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=Mant_D_sqrt_Norm[C_MANT_FP64-7:C_MANT_FP64-8]; - Q_sqrt1={{(C_MANT_FP64+1){1'b0}},Qcnt_three_1[4:1]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - Sqrt_DI[2]=Mant_D_sqrt_Norm[C_MANT_FP64-9:C_MANT_FP64-10]; - Q_sqrt2={{(C_MANT_FP64){1'b0}},Qcnt_three_1[4:0]}; - Sqrt_Q2=Sqrt_quotinent_S[2]?Q_sqrt_com_2:Q_sqrt2; - end - - 6'b000010: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-11:C_MANT_FP64-12]; - Q_sqrt0={{(C_MANT_FP64-1){1'b0}},Qcnt_three_2[7:2]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=Mant_D_sqrt_Norm[C_MANT_FP64-13:C_MANT_FP64-14]; - Q_sqrt1={{(C_MANT_FP64-2){1'b0}},Qcnt_three_2[7:1]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - Sqrt_DI[2]=Mant_D_sqrt_Norm[C_MANT_FP64-15:C_MANT_FP64-16]; - Q_sqrt2={{(C_MANT_FP64-3){1'b0}},Qcnt_three_2[7:0]}; - Sqrt_Q2=Sqrt_quotinent_S[2]?Q_sqrt_com_2:Q_sqrt2; - end - - 6'b000011: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-17:C_MANT_FP64-18]; - Q_sqrt0={{(C_MANT_FP64-4){1'b0}},Qcnt_three_3[10:2]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=Mant_D_sqrt_Norm[C_MANT_FP64-19:C_MANT_FP64-20]; - Q_sqrt1={{(C_MANT_FP64-5){1'b0}},Qcnt_three_3[10:1]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - Sqrt_DI[2]=Mant_D_sqrt_Norm[C_MANT_FP64-21:C_MANT_FP64-22]; - Q_sqrt2={{(C_MANT_FP64-6){1'b0}},Qcnt_three_3[10:0]}; - Sqrt_Q2=Sqrt_quotinent_S[2]?Q_sqrt_com_2:Q_sqrt2; - end - - 6'b000100: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-23:C_MANT_FP64-24]; - Q_sqrt0={{(C_MANT_FP64-7){1'b0}},Qcnt_three_4[13:2]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=Mant_D_sqrt_Norm[C_MANT_FP64-25:C_MANT_FP64-26]; - Q_sqrt1={{(C_MANT_FP64-8){1'b0}},Qcnt_three_4[13:1]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - Sqrt_DI[2]=Mant_D_sqrt_Norm[C_MANT_FP64-27:C_MANT_FP64-28]; - Q_sqrt2={{(C_MANT_FP64-9){1'b0}},Qcnt_three_4[13:0]}; - Sqrt_Q2=Sqrt_quotinent_S[2]?Q_sqrt_com_2:Q_sqrt2; - end - - 6'b000101: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-29:C_MANT_FP64-30]; - Q_sqrt0={{(C_MANT_FP64-10){1'b0}},Qcnt_three_5[16:2]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=Mant_D_sqrt_Norm[C_MANT_FP64-31:C_MANT_FP64-32]; - Q_sqrt1={{(C_MANT_FP64-11){1'b0}},Qcnt_three_5[16:1]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - Sqrt_DI[2]=Mant_D_sqrt_Norm[C_MANT_FP64-33:C_MANT_FP64-34]; - Q_sqrt2={{(C_MANT_FP64-12){1'b0}},Qcnt_three_5[16:0]}; - Sqrt_Q2=Sqrt_quotinent_S[2]?Q_sqrt_com_2:Q_sqrt2; - end - - 6'b000110: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-35:C_MANT_FP64-36]; - Q_sqrt0={{(C_MANT_FP64-13){1'b0}},Qcnt_three_6[19:2]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=Mant_D_sqrt_Norm[C_MANT_FP64-37:C_MANT_FP64-38]; - Q_sqrt1={{(C_MANT_FP64-14){1'b0}},Qcnt_three_6[19:1]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - Sqrt_DI[2]=Mant_D_sqrt_Norm[C_MANT_FP64-39:C_MANT_FP64-40]; - Q_sqrt2={{(C_MANT_FP64-15){1'b0}},Qcnt_three_6[19:0]}; - Sqrt_Q2=Sqrt_quotinent_S[2]?Q_sqrt_com_2:Q_sqrt2; - end - - 6'b000111: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-41:C_MANT_FP64-42]; - Q_sqrt0={{(C_MANT_FP64-16){1'b0}},Qcnt_three_7[22:2]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=Mant_D_sqrt_Norm[C_MANT_FP64-43:C_MANT_FP64-44]; - Q_sqrt1={{(C_MANT_FP64-17){1'b0}},Qcnt_three_7[22:1]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - Sqrt_DI[2]=Mant_D_sqrt_Norm[C_MANT_FP64-45:C_MANT_FP64-46]; - Q_sqrt2={{(C_MANT_FP64-18){1'b0}},Qcnt_three_7[22:0]}; - Sqrt_Q2=Sqrt_quotinent_S[2]?Q_sqrt_com_2:Q_sqrt2; - end - - 6'b001000: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-47:C_MANT_FP64-48]; - Q_sqrt0={{(C_MANT_FP64-19){1'b0}},Qcnt_three_8[25:2]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=Mant_D_sqrt_Norm[C_MANT_FP64-49:C_MANT_FP64-50]; - Q_sqrt1={{(C_MANT_FP64-20){1'b0}},Qcnt_three_8[25:1]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - Sqrt_DI[2]=Mant_D_sqrt_Norm[C_MANT_FP64-51:C_MANT_FP64-52]; - Q_sqrt2={{(C_MANT_FP64-21){1'b0}},Qcnt_three_8[25:0]}; - Sqrt_Q2=Sqrt_quotinent_S[2]?Q_sqrt_com_2:Q_sqrt2; - end - - 6'b001001: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-22){1'b0}},Qcnt_three_9[28:2]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=2'b00; - Q_sqrt1={{(C_MANT_FP64-23){1'b0}},Qcnt_three_9[28:1]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - Sqrt_DI[2]=2'b00; - Q_sqrt2={{(C_MANT_FP64-24){1'b0}},Qcnt_three_9[28:0]}; - Sqrt_Q2=Sqrt_quotinent_S[2]?Q_sqrt_com_2:Q_sqrt2; - end - - 6'b001010: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-25){1'b0}},Qcnt_three_10[31:2]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=2'b00; - Q_sqrt1={{(C_MANT_FP64-26){1'b0}},Qcnt_three_10[31:1]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - Sqrt_DI[2]=2'b00; - Q_sqrt2={{(C_MANT_FP64-27){1'b0}},Qcnt_three_10[31:0]}; - Sqrt_Q2=Sqrt_quotinent_S[2]?Q_sqrt_com_2:Q_sqrt2; - end - - 6'b001011: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-28){1'b0}},Qcnt_three_11[34:2]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=2'b00; - Q_sqrt1={{(C_MANT_FP64-29){1'b0}},Qcnt_three_11[34:1]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - Sqrt_DI[2]=2'b00; - Q_sqrt2={{(C_MANT_FP64-30){1'b0}},Qcnt_three_11[34:0]}; - Sqrt_Q2=Sqrt_quotinent_S[2]?Q_sqrt_com_2:Q_sqrt2; - end - - 6'b001100: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-31){1'b0}},Qcnt_three_12[37:2]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=2'b00; - Q_sqrt1={{(C_MANT_FP64-32){1'b0}},Qcnt_three_12[37:1]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - Sqrt_DI[2]=2'b00; - Q_sqrt2={{(C_MANT_FP64-33){1'b0}},Qcnt_three_12[37:0]}; - Sqrt_Q2=Sqrt_quotinent_S[2]?Q_sqrt_com_2:Q_sqrt2; - end - - 6'b001101: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-34){1'b0}},Qcnt_three_13[40:2]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=2'b00; - Q_sqrt1={{(C_MANT_FP64-35){1'b0}},Qcnt_three_13[40:1]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - Sqrt_DI[2]=2'b00; - Q_sqrt2={{(C_MANT_FP64-36){1'b0}},Qcnt_three_13[40:0]}; - Sqrt_Q2=Sqrt_quotinent_S[2]?Q_sqrt_com_2:Q_sqrt2; - end - - 6'b001110: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-37){1'b0}},Qcnt_three_14[43:2]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=2'b00; - Q_sqrt1={{(C_MANT_FP64-38){1'b0}},Qcnt_three_14[43:1]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - Sqrt_DI[2]=2'b00; - Q_sqrt2={{(C_MANT_FP64-39){1'b0}},Qcnt_three_14[43:0]}; - Sqrt_Q2=Sqrt_quotinent_S[2]?Q_sqrt_com_2:Q_sqrt2; - end - - 6'b001111: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-40){1'b0}},Qcnt_three_15[46:2]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=2'b00; - Q_sqrt1={{(C_MANT_FP64-41){1'b0}},Qcnt_three_15[46:1]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - Sqrt_DI[2]=2'b00; - Q_sqrt2={{(C_MANT_FP64-42){1'b0}},Qcnt_three_15[46:0]}; - Sqrt_Q2=Sqrt_quotinent_S[2]?Q_sqrt_com_2:Q_sqrt2; - end - - 6'b010000: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-43){1'b0}},Qcnt_three_16[49:2]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=2'b00; - Q_sqrt1={{(C_MANT_FP64-44){1'b0}},Qcnt_three_16[49:1]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - Sqrt_DI[2]=2'b00; - Q_sqrt2={{(C_MANT_FP64-45){1'b0}},Qcnt_three_16[49:0]}; - Sqrt_Q2=Sqrt_quotinent_S[2]?Q_sqrt_com_2:Q_sqrt2; - end - - 6'b010001: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-46){1'b0}},Qcnt_three_17[52:2]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=2'b00; - Q_sqrt1={{(C_MANT_FP64-47){1'b0}},Qcnt_three_17[52:1]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - Sqrt_DI[2]=2'b00; - Q_sqrt2={{(C_MANT_FP64-48){1'b0}},Qcnt_three_17[52:0]}; - Sqrt_Q2=Sqrt_quotinent_S[2]?Q_sqrt_com_2:Q_sqrt2; - end - - 6'b010010: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-49){1'b0}},Qcnt_three_18[55:2]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=2'b00; - Q_sqrt1={{(C_MANT_FP64-50){1'b0}},Qcnt_three_18[55:1]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - Sqrt_DI[2]=2'b00; - Q_sqrt2={{(C_MANT_FP64-51){1'b0}},Qcnt_three_18[55:0]}; - Sqrt_Q2=Sqrt_quotinent_S[2]?Q_sqrt_com_2:Q_sqrt2; - end - - default : - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64+1:C_MANT_FP64]; - Q_sqrt0={{(C_MANT_FP64+5){1'b0}},Qcnt_three_0[2]}; - Sqrt_Q0=Q_sqrt_com_0; - Sqrt_DI[1]=Mant_D_sqrt_Norm[C_MANT_FP64-1:C_MANT_FP64-2]; - Q_sqrt1={{(C_MANT_FP64+4){1'b0}},Qcnt_three_0[2:1]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - Sqrt_DI[2]=Mant_D_sqrt_Norm[C_MANT_FP64-3:C_MANT_FP64-4]; - Q_sqrt2={{(C_MANT_FP64+3){1'b0}},Qcnt_three_0[2:0]}; - Sqrt_Q2=Sqrt_quotinent_S[2]?Q_sqrt_com_2:Q_sqrt2; - end - endcase - - end - ///////////////////////////////////////////////////////////////////////////// - // Operands for square root when Iteration_unit_num_S = 2'b10, end // - ///////////////////////////////////////////////////////////////////////////// - - - 2'b11: - begin - ///////////////////////////////////////////////////////////////////////////// - // Operands for square root when Iteration_unit_num_S = 2'b11, start // - ///////////////////////////////////////////////////////////////////////////// - - case(Crtl_cnt_S) - - 6'b000000: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64+1:C_MANT_FP64]; - Q_sqrt0={{(C_MANT_FP64+5){1'b0}},Qcnt_four_0[3]}; - Sqrt_Q0=Q_sqrt_com_0; - Sqrt_DI[1]=Mant_D_sqrt_Norm[C_MANT_FP64-1:C_MANT_FP64-2]; - Q_sqrt1={{(C_MANT_FP64+4){1'b0}},Qcnt_four_0[3:2]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - Sqrt_DI[2]=Mant_D_sqrt_Norm[C_MANT_FP64-3:C_MANT_FP64-4]; - Q_sqrt2={{(C_MANT_FP64+3){1'b0}},Qcnt_four_0[3:1]}; - Sqrt_Q2=Sqrt_quotinent_S[2]?Q_sqrt_com_2:Q_sqrt2; - Sqrt_DI[3]=Mant_D_sqrt_Norm[C_MANT_FP64-5:C_MANT_FP64-6]; - Q_sqrt3={{(C_MANT_FP64+2){1'b0}},Qcnt_four_0[3:0]}; - Sqrt_Q3=Sqrt_quotinent_S[1]?Q_sqrt_com_3:Q_sqrt3; - end - - 6'b000001: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-7:C_MANT_FP64-8]; - Q_sqrt0={{(C_MANT_FP64+1){1'b0}},Qcnt_four_1[6:3]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=Mant_D_sqrt_Norm[C_MANT_FP64-9:C_MANT_FP64-10]; - Q_sqrt1={{(C_MANT_FP64){1'b0}},Qcnt_four_1[6:2]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - Sqrt_DI[2]=Mant_D_sqrt_Norm[C_MANT_FP64-11:C_MANT_FP64-12]; - Q_sqrt2={{(C_MANT_FP64-1){1'b0}},Qcnt_four_1[6:1]}; - Sqrt_Q2=Sqrt_quotinent_S[2]?Q_sqrt_com_2:Q_sqrt2; - Sqrt_DI[3]=Mant_D_sqrt_Norm[C_MANT_FP64-13:C_MANT_FP64-14]; - Q_sqrt3={{(C_MANT_FP64-2){1'b0}},Qcnt_four_1[6:0]}; - Sqrt_Q3=Sqrt_quotinent_S[1]?Q_sqrt_com_3:Q_sqrt3; - end - - 6'b000010: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-15:C_MANT_FP64-16]; - Q_sqrt0={{(C_MANT_FP64-3){1'b0}},Qcnt_four_2[10:3]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=Mant_D_sqrt_Norm[C_MANT_FP64-17:C_MANT_FP64-18]; - Q_sqrt1={{(C_MANT_FP64-4){1'b0}},Qcnt_four_2[10:2]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - Sqrt_DI[2]=Mant_D_sqrt_Norm[C_MANT_FP64-19:C_MANT_FP64-20]; - Q_sqrt2={{(C_MANT_FP64-5){1'b0}},Qcnt_four_2[10:1]}; - Sqrt_Q2=Sqrt_quotinent_S[2]?Q_sqrt_com_2:Q_sqrt2; - Sqrt_DI[3]=Mant_D_sqrt_Norm[C_MANT_FP64-21:C_MANT_FP64-22]; - Q_sqrt3={{(C_MANT_FP64-6){1'b0}},Qcnt_four_2[10:0]}; - Sqrt_Q3=Sqrt_quotinent_S[1]?Q_sqrt_com_3:Q_sqrt3; - end - - 6'b000011: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-23:C_MANT_FP64-24]; - Q_sqrt0={{(C_MANT_FP64-7){1'b0}},Qcnt_four_3[14:3]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=Mant_D_sqrt_Norm[C_MANT_FP64-25:C_MANT_FP64-26]; - Q_sqrt1={{(C_MANT_FP64-8){1'b0}},Qcnt_four_3[14:2]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - Sqrt_DI[2]=Mant_D_sqrt_Norm[C_MANT_FP64-27:C_MANT_FP64-28]; - Q_sqrt2={{(C_MANT_FP64-9){1'b0}},Qcnt_four_3[14:1]}; - Sqrt_Q2=Sqrt_quotinent_S[2]?Q_sqrt_com_2:Q_sqrt2; - Sqrt_DI[3]=Mant_D_sqrt_Norm[C_MANT_FP64-29:C_MANT_FP64-30]; - Q_sqrt3={{(C_MANT_FP64-10){1'b0}},Qcnt_four_3[14:0]}; - Sqrt_Q3=Sqrt_quotinent_S[1]?Q_sqrt_com_3:Q_sqrt3; - end - - 6'b000100: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-31:C_MANT_FP64-32]; - Q_sqrt0={{(C_MANT_FP64-11){1'b0}},Qcnt_four_4[18:3]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=Mant_D_sqrt_Norm[C_MANT_FP64-33:C_MANT_FP64-34]; - Q_sqrt1={{(C_MANT_FP64-12){1'b0}},Qcnt_four_4[18:2]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - Sqrt_DI[2]=Mant_D_sqrt_Norm[C_MANT_FP64-35:C_MANT_FP64-36]; - Q_sqrt2={{(C_MANT_FP64-13){1'b0}},Qcnt_four_4[18:1]}; - Sqrt_Q2=Sqrt_quotinent_S[2]?Q_sqrt_com_2:Q_sqrt2; - Sqrt_DI[3]=Mant_D_sqrt_Norm[C_MANT_FP64-37:C_MANT_FP64-38]; - Q_sqrt3={{(C_MANT_FP64-14){1'b0}},Qcnt_four_4[18:0]}; - Sqrt_Q3=Sqrt_quotinent_S[1]?Q_sqrt_com_3:Q_sqrt3; - end - - 6'b000101: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-39:C_MANT_FP64-40]; - Q_sqrt0={{(C_MANT_FP64-15){1'b0}},Qcnt_four_5[22:3]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=Mant_D_sqrt_Norm[C_MANT_FP64-41:C_MANT_FP64-42]; - Q_sqrt1={{(C_MANT_FP64-16){1'b0}},Qcnt_four_5[22:2]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - Sqrt_DI[2]=Mant_D_sqrt_Norm[C_MANT_FP64-43:C_MANT_FP64-44]; - Q_sqrt2={{(C_MANT_FP64-17){1'b0}},Qcnt_four_5[22:1]}; - Sqrt_Q2=Sqrt_quotinent_S[2]?Q_sqrt_com_2:Q_sqrt2; - Sqrt_DI[3]=Mant_D_sqrt_Norm[C_MANT_FP64-45:C_MANT_FP64-46]; - Q_sqrt3={{(C_MANT_FP64-18){1'b0}},Qcnt_four_5[22:0]}; - Sqrt_Q3=Sqrt_quotinent_S[1]?Q_sqrt_com_3:Q_sqrt3; - end - - 6'b000110: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-47:C_MANT_FP64-48]; - Q_sqrt0={{(C_MANT_FP64-19){1'b0}},Qcnt_four_6[26:3]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=Mant_D_sqrt_Norm[C_MANT_FP64-49:C_MANT_FP64-50]; - Q_sqrt1={{(C_MANT_FP64-20){1'b0}},Qcnt_four_6[26:2]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - Sqrt_DI[2]=Mant_D_sqrt_Norm[C_MANT_FP64-51:C_MANT_FP64-52]; - Q_sqrt2={{(C_MANT_FP64-21){1'b0}},Qcnt_four_6[26:1]}; - Sqrt_Q2=Sqrt_quotinent_S[2]?Q_sqrt_com_2:Q_sqrt2; - Sqrt_DI[3]=2'b00; - Q_sqrt3={{(C_MANT_FP64-22){1'b0}},Qcnt_four_6[26:0]}; - Sqrt_Q3=Sqrt_quotinent_S[1]?Q_sqrt_com_3:Q_sqrt3; - end - - 6'b000111: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-23){1'b0}},Qcnt_four_7[30:3]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=2'b00; - Q_sqrt1={{(C_MANT_FP64-24){1'b0}},Qcnt_four_7[30:2]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - Sqrt_DI[2]=2'b00; - Q_sqrt2={{(C_MANT_FP64-25){1'b0}},Qcnt_four_7[30:1]}; - Sqrt_Q2=Sqrt_quotinent_S[2]?Q_sqrt_com_2:Q_sqrt2; - Sqrt_DI[3]=2'b00; - Q_sqrt3={{(C_MANT_FP64-26){1'b0}},Qcnt_four_7[30:0]}; - Sqrt_Q3=Sqrt_quotinent_S[1]?Q_sqrt_com_3:Q_sqrt3; - end - - 6'b001000: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-27){1'b0}},Qcnt_four_8[34:3]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=2'b00; - Q_sqrt1={{(C_MANT_FP64-28){1'b0}},Qcnt_four_8[34:2]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - Sqrt_DI[2]=2'b00; - Q_sqrt2={{(C_MANT_FP64-29){1'b0}},Qcnt_four_8[34:1]}; - Sqrt_Q2=Sqrt_quotinent_S[2]?Q_sqrt_com_2:Q_sqrt2; - Sqrt_DI[3]=2'b00; - Q_sqrt3={{(C_MANT_FP64-30){1'b0}},Qcnt_four_8[34:0]}; - Sqrt_Q3=Sqrt_quotinent_S[1]?Q_sqrt_com_3:Q_sqrt3; - end - - 6'b001001: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-31){1'b0}},Qcnt_four_9[38:3]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=2'b00; - Q_sqrt1={{(C_MANT_FP64-32){1'b0}},Qcnt_four_9[38:2]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - Sqrt_DI[2]=2'b00; - Q_sqrt2={{(C_MANT_FP64-33){1'b0}},Qcnt_four_9[38:1]}; - Sqrt_Q2=Sqrt_quotinent_S[2]?Q_sqrt_com_2:Q_sqrt2; - Sqrt_DI[3]=2'b00; - Q_sqrt3={{(C_MANT_FP64-34){1'b0}},Qcnt_four_9[38:0]}; - Sqrt_Q3=Sqrt_quotinent_S[1]?Q_sqrt_com_3:Q_sqrt3; - end - - 6'b001010: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-35){1'b0}},Qcnt_four_10[42:3]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=2'b00; - Q_sqrt1={{(C_MANT_FP64-36){1'b0}},Qcnt_four_10[42:2]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - Sqrt_DI[2]=2'b00; - Q_sqrt2={{(C_MANT_FP64-37){1'b0}},Qcnt_four_10[42:1]}; - Sqrt_Q2=Sqrt_quotinent_S[2]?Q_sqrt_com_2:Q_sqrt2; - Sqrt_DI[3]=2'b00; - Q_sqrt3={{(C_MANT_FP64-38){1'b0}},Qcnt_four_10[42:0]}; - Sqrt_Q3=Sqrt_quotinent_S[1]?Q_sqrt_com_3:Q_sqrt3; - end - - 6'b001011: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-39){1'b0}},Qcnt_four_11[46:3]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=2'b00; - Q_sqrt1={{(C_MANT_FP64-40){1'b0}},Qcnt_four_11[46:2]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - Sqrt_DI[2]=2'b00; - Q_sqrt2={{(C_MANT_FP64-41){1'b0}},Qcnt_four_11[46:1]}; - Sqrt_Q2=Sqrt_quotinent_S[2]?Q_sqrt_com_2:Q_sqrt2; - Sqrt_DI[3]=2'b00; - Q_sqrt3={{(C_MANT_FP64-42){1'b0}},Qcnt_four_11[46:0]}; - Sqrt_Q3=Sqrt_quotinent_S[1]?Q_sqrt_com_3:Q_sqrt3; - end - - 6'b001100: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-43){1'b0}},Qcnt_four_12[50:3]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=2'b00; - Q_sqrt1={{(C_MANT_FP64-44){1'b0}},Qcnt_four_12[50:2]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - Sqrt_DI[2]=2'b00; - Q_sqrt2={{(C_MANT_FP64-45){1'b0}},Qcnt_four_12[50:1]}; - Sqrt_Q2=Sqrt_quotinent_S[2]?Q_sqrt_com_2:Q_sqrt2; - Sqrt_DI[3]=2'b00; - Q_sqrt3={{(C_MANT_FP64-46){1'b0}},Qcnt_four_12[50:0]}; - Sqrt_Q3=Sqrt_quotinent_S[1]?Q_sqrt_com_3:Q_sqrt3; - end - - 6'b001101: - begin - Sqrt_DI[0]=2'b00; - Q_sqrt0={{(C_MANT_FP64-47){1'b0}},Qcnt_four_13[54:3]}; - Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; - Sqrt_DI[1]=2'b00; - Q_sqrt1={{(C_MANT_FP64-48){1'b0}},Qcnt_four_13[54:2]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - Sqrt_DI[2]=2'b00; - Q_sqrt2={{(C_MANT_FP64-49){1'b0}},Qcnt_four_13[54:1]}; - Sqrt_Q2=Sqrt_quotinent_S[2]?Q_sqrt_com_2:Q_sqrt2; - Sqrt_DI[3]=2'b00; - Q_sqrt3={{(C_MANT_FP64-50){1'b0}},Qcnt_four_13[54:0]}; - Sqrt_Q3=Sqrt_quotinent_S[1]?Q_sqrt_com_3:Q_sqrt3; - end - - default: - begin - Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64+1:C_MANT_FP64]; - Q_sqrt0={{(C_MANT_FP64+5){1'b0}},Qcnt_four_0[3]}; - Sqrt_Q0=Q_sqrt_com_0; - Sqrt_DI[1]=Mant_D_sqrt_Norm[C_MANT_FP64-1:C_MANT_FP64-2]; - Q_sqrt1={{(C_MANT_FP64+4){1'b0}},Qcnt_four_0[3:2]}; - Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; - Sqrt_DI[2]=Mant_D_sqrt_Norm[C_MANT_FP64-3:C_MANT_FP64-4]; - Q_sqrt2={{(C_MANT_FP64+3){1'b0}},Qcnt_four_0[3:1]}; - Sqrt_Q2=Sqrt_quotinent_S[2]?Q_sqrt_com_2:Q_sqrt2; - Sqrt_DI[3]=Mant_D_sqrt_Norm[C_MANT_FP64-5:C_MANT_FP64-6]; - Q_sqrt3={{(C_MANT_FP64+2){1'b0}},Qcnt_four_0[3:0]}; - Sqrt_Q3=Sqrt_quotinent_S[1]?Q_sqrt_com_3:Q_sqrt3; - end - endcase - end - endcase - ///////////////////////////////////////////////////////////////////////////// - // Operands for square root when Iteration_unit_num_S = 2'b11, end // - ///////////////////////////////////////////////////////////////////////////// - end - - - - assign Sqrt_R0= ((Sqrt_start_dly_S)?'0:{Partial_remainder_DP[C_MANT_FP64+5:0]}); - assign Sqrt_R1= {Iteration_cell_sum_AMASK_D[0][C_MANT_FP64+5],Iteration_cell_sum_AMASK_D[0][C_MANT_FP64+2:0],Sqrt_DO[0]} ; - assign Sqrt_R2= {Iteration_cell_sum_AMASK_D[1][C_MANT_FP64+5],Iteration_cell_sum_AMASK_D[1][C_MANT_FP64+2:0],Sqrt_DO[1]}; - assign Sqrt_R3= {Iteration_cell_sum_AMASK_D[2][C_MANT_FP64+5],Iteration_cell_sum_AMASK_D[2][C_MANT_FP64+2:0],Sqrt_DO[2]}; - assign Sqrt_R4= {Iteration_cell_sum_AMASK_D[3][C_MANT_FP64+5],Iteration_cell_sum_AMASK_D[3][C_MANT_FP64+2:0],Sqrt_DO[3]}; - - logic [C_MANT_FP64+5:0] Denominator_se_format_DB; // - - assign Denominator_se_format_DB={Denominator_se_DB[C_MANT_FP64+1:C_MANT_FP64-C_MANT_FP16ALT],{FP16ALT_SO?FP16ALT_SO:Denominator_se_DB[C_MANT_FP64-C_MANT_FP16ALT-1]}, - Denominator_se_DB[C_MANT_FP64-C_MANT_FP16ALT-2:C_MANT_FP64-C_MANT_FP16],{FP16_SO?FP16_SO:Denominator_se_DB[C_MANT_FP64-C_MANT_FP16-1]}, - Denominator_se_DB[C_MANT_FP64-C_MANT_FP16-2:C_MANT_FP64-C_MANT_FP32],{FP32_SO?FP32_SO:Denominator_se_DB[C_MANT_FP64-C_MANT_FP32-1]}, - Denominator_se_DB[C_MANT_FP64-C_MANT_FP32-2:C_MANT_FP64-C_MANT_FP64],FP64_SO,3'b0} ; - // for iteration cell_U0 - logic [C_MANT_FP64+5:0] First_iteration_cell_div_a_D,First_iteration_cell_div_b_D; - logic Sel_b_for_first_S; - - - assign First_iteration_cell_div_a_D=(Div_start_dly_S)?{Numerator_se_D[C_MANT_FP64+1:C_MANT_FP64-C_MANT_FP16ALT],{FP16ALT_SO?FP16ALT_SO:Numerator_se_D[C_MANT_FP64-C_MANT_FP16ALT-1]}, - Numerator_se_D[C_MANT_FP64-C_MANT_FP16ALT-2:C_MANT_FP64-C_MANT_FP16],{FP16_SO?FP16_SO:Numerator_se_D[C_MANT_FP64-C_MANT_FP16-1]}, - Numerator_se_D[C_MANT_FP64-C_MANT_FP16-2:C_MANT_FP64-C_MANT_FP32],{FP32_SO?FP32_SO:Numerator_se_D[C_MANT_FP64-C_MANT_FP32-1]}, - Numerator_se_D[C_MANT_FP64-C_MANT_FP32-2:C_MANT_FP64-C_MANT_FP64],FP64_SO,3'b0} - :{Partial_remainder_DP[C_MANT_FP64+4:C_MANT_FP64-C_MANT_FP16ALT+3],{FP16ALT_SO?Quotient_DP[0]:Partial_remainder_DP[C_MANT_FP64-C_MANT_FP16ALT+2]}, - Partial_remainder_DP[C_MANT_FP64-C_MANT_FP16ALT+1:C_MANT_FP64-C_MANT_FP16+3],{FP16_SO?Quotient_DP[0]:Partial_remainder_DP[C_MANT_FP64-C_MANT_FP16+2]}, - Partial_remainder_DP[C_MANT_FP64-C_MANT_FP16+1:C_MANT_FP64-C_MANT_FP32+3],{FP32_SO?Quotient_DP[0]:Partial_remainder_DP[C_MANT_FP64-C_MANT_FP32+2]}, - Partial_remainder_DP[C_MANT_FP64-C_MANT_FP32+1:C_MANT_FP64-C_MANT_FP64+3],FP64_SO&&Quotient_DP[0],3'b0}; - assign Sel_b_for_first_S=(Div_start_dly_S)?1:Quotient_DP[0]; - assign First_iteration_cell_div_b_D=Sel_b_for_first_S?Denominator_se_format_DB:{Denominator_se_D,4'b0}; - assign Iteration_cell_a_BMASK_D[0]=Sqrt_enable_SO?Sqrt_R0:{First_iteration_cell_div_a_D}; - assign Iteration_cell_b_BMASK_D[0]=Sqrt_enable_SO?Sqrt_Q0:{First_iteration_cell_div_b_D}; - - - - // for iteration cell_U1 - logic [C_MANT_FP64+5:0] Sec_iteration_cell_div_a_D,Sec_iteration_cell_div_b_D; - logic Sel_b_for_sec_S; - generate - if(|Iteration_unit_num_S) - begin - assign Sel_b_for_sec_S=~Iteration_cell_sum_AMASK_D[0][C_MANT_FP64+5]; - assign Sec_iteration_cell_div_a_D={Iteration_cell_sum_AMASK_D[0][C_MANT_FP64+4:C_MANT_FP64-C_MANT_FP16ALT+3],{FP16ALT_SO?Sel_b_for_sec_S:Iteration_cell_sum_AMASK_D[0][C_MANT_FP64-C_MANT_FP16ALT+2]}, - Iteration_cell_sum_AMASK_D[0][C_MANT_FP64-C_MANT_FP16ALT+1:C_MANT_FP64-C_MANT_FP16+3],{FP16_SO?Sel_b_for_sec_S:Iteration_cell_sum_AMASK_D[0][C_MANT_FP64-C_MANT_FP16+2]}, - Iteration_cell_sum_AMASK_D[0][C_MANT_FP64-C_MANT_FP16+1:C_MANT_FP64-C_MANT_FP32+3],{FP32_SO?Sel_b_for_sec_S:Iteration_cell_sum_AMASK_D[0][C_MANT_FP64-C_MANT_FP32+2]}, - Iteration_cell_sum_AMASK_D[0][C_MANT_FP64-C_MANT_FP32+1:C_MANT_FP64-C_MANT_FP64+3],FP64_SO&&Sel_b_for_sec_S,3'b0}; - assign Sec_iteration_cell_div_b_D=Sel_b_for_sec_S?Denominator_se_format_DB:{Denominator_se_D,4'b0}; - assign Iteration_cell_a_BMASK_D[1]=Sqrt_enable_SO?Sqrt_R1:{Sec_iteration_cell_div_a_D}; - assign Iteration_cell_b_BMASK_D[1]=Sqrt_enable_SO?Sqrt_Q1:{Sec_iteration_cell_div_b_D}; - end - endgenerate - - // for iteration cell_U2 - logic [C_MANT_FP64+5:0] Thi_iteration_cell_div_a_D,Thi_iteration_cell_div_b_D; - logic Sel_b_for_thi_S; - generate - if((Iteration_unit_num_S==2'b10) | (Iteration_unit_num_S==2'b11)) - begin - assign Sel_b_for_thi_S=~Iteration_cell_sum_AMASK_D[1][C_MANT_FP64+5]; - assign Thi_iteration_cell_div_a_D={Iteration_cell_sum_AMASK_D[1][C_MANT_FP64+4:C_MANT_FP64-C_MANT_FP16ALT+3],{FP16ALT_SO?Sel_b_for_thi_S:Iteration_cell_sum_AMASK_D[1][C_MANT_FP64-C_MANT_FP16ALT+2]}, - Iteration_cell_sum_AMASK_D[1][C_MANT_FP64-C_MANT_FP16ALT+1:C_MANT_FP64-C_MANT_FP16+3],{FP16_SO?Sel_b_for_thi_S:Iteration_cell_sum_AMASK_D[1][C_MANT_FP64-C_MANT_FP16+2]}, - Iteration_cell_sum_AMASK_D[1][C_MANT_FP64-C_MANT_FP16+1:C_MANT_FP64-C_MANT_FP32+3],{FP32_SO?Sel_b_for_thi_S:Iteration_cell_sum_AMASK_D[1][C_MANT_FP64-C_MANT_FP32+2]}, - Iteration_cell_sum_AMASK_D[1][C_MANT_FP64-C_MANT_FP32+1:C_MANT_FP64-C_MANT_FP64+3],FP64_SO&&Sel_b_for_thi_S,3'b0}; - assign Thi_iteration_cell_div_b_D=Sel_b_for_thi_S?Denominator_se_format_DB:{Denominator_se_D,4'b0}; - assign Iteration_cell_a_BMASK_D[2]=Sqrt_enable_SO?Sqrt_R2:{Thi_iteration_cell_div_a_D}; - assign Iteration_cell_b_BMASK_D[2]=Sqrt_enable_SO?Sqrt_Q2:{Thi_iteration_cell_div_b_D}; - end - endgenerate - - // for iteration cell_U3 - logic [C_MANT_FP64+5:0] Fou_iteration_cell_div_a_D,Fou_iteration_cell_div_b_D; - logic Sel_b_for_fou_S; - - generate - if(Iteration_unit_num_S==2'b11) - begin - assign Sel_b_for_fou_S=~Iteration_cell_sum_AMASK_D[2][C_MANT_FP64+5]; - assign Fou_iteration_cell_div_a_D={Iteration_cell_sum_AMASK_D[2][C_MANT_FP64+4:C_MANT_FP64-C_MANT_FP16ALT+3],{FP16ALT_SO?Sel_b_for_fou_S:Iteration_cell_sum_AMASK_D[2][C_MANT_FP64-C_MANT_FP16ALT+2]}, - Iteration_cell_sum_AMASK_D[2][C_MANT_FP64-C_MANT_FP16ALT+1:C_MANT_FP64-C_MANT_FP16+3],{FP16_SO?Sel_b_for_fou_S:Iteration_cell_sum_AMASK_D[2][C_MANT_FP64-C_MANT_FP16+2]}, - Iteration_cell_sum_AMASK_D[2][C_MANT_FP64-C_MANT_FP16+1:C_MANT_FP64-C_MANT_FP32+3],{FP32_SO?Sel_b_for_fou_S:Iteration_cell_sum_AMASK_D[2][C_MANT_FP64-C_MANT_FP32+2]}, - Iteration_cell_sum_AMASK_D[2][C_MANT_FP64-C_MANT_FP32+1:C_MANT_FP64-C_MANT_FP64+3],FP64_SO&&Sel_b_for_fou_S,3'b0}; - assign Fou_iteration_cell_div_b_D=Sel_b_for_fou_S?Denominator_se_format_DB:{Denominator_se_D,4'b0}; - assign Iteration_cell_a_BMASK_D[3]=Sqrt_enable_SO?Sqrt_R3:{Fou_iteration_cell_div_a_D}; - assign Iteration_cell_b_BMASK_D[3]=Sqrt_enable_SO?Sqrt_Q3:{Fou_iteration_cell_div_b_D}; - end - endgenerate - - ///////////////////////////////////////////////////////////////////////////// - // Masking Contrl // - ///////////////////////////////////////////////////////////////////////////// - - - logic [C_MANT_FP64+1+4:0] Mask_bits_ctl_S; //For extension - - assign Mask_bits_ctl_S =58'h3ff_ffff_ffff_ffff; //It is not needed. The corresponding process is handled the above codes - - ///////////////////////////////////////////////////////////////////////////// - // Iteration Instances with masking control // - ///////////////////////////////////////////////////////////////////////////// - - - logic Div_enable_SI [3:0]; - logic Div_start_dly_SI [3:0]; - logic Sqrt_enable_SI [3:0]; - generate - genvar i,j; - for (i=0; i <= Iteration_unit_num_S ; i++) - begin - for (j = 0; j <= C_MANT_FP64+5; j++) begin - assign Iteration_cell_a_D[i][j] = Mask_bits_ctl_S[j] && Iteration_cell_a_BMASK_D[i][j]; - assign Iteration_cell_b_D[i][j] = Mask_bits_ctl_S[j] && Iteration_cell_b_BMASK_D[i][j]; - assign Iteration_cell_sum_AMASK_D[i][j] = Mask_bits_ctl_S[j] && Iteration_cell_sum_D[i][j]; - end - - assign Div_enable_SI[i] = Div_enable_SO; - assign Div_start_dly_SI[i] = Div_start_dly_S; - assign Sqrt_enable_SI[i] = Sqrt_enable_SO; - iteration_div_sqrt_mvp #(C_MANT_FP64+6) iteration_div_sqrt - ( - .A_DI (Iteration_cell_a_D[i] ), - .B_DI (Iteration_cell_b_D[i] ), - .Div_enable_SI (Div_enable_SI[i] ), - .Div_start_dly_SI (Div_start_dly_SI[i] ), - .Sqrt_enable_SI (Sqrt_enable_SI[i] ), - .D_DI (Sqrt_DI[i] ), - .D_DO (Sqrt_DO[i] ), - .Sum_DO (Iteration_cell_sum_D[i] ), - .Carry_out_DO (Iteration_cell_carry_D[i] ) - ); - - end - - endgenerate - - - - always_comb - begin - case (Iteration_unit_num_S) - 2'b00: - begin - if(Fsm_enable_S) - Partial_remainder_DN = Sqrt_enable_SO?Sqrt_R1:Iteration_cell_sum_AMASK_D[0]; - else - Partial_remainder_DN = Partial_remainder_DP; - end - 2'b01: - begin - if(Fsm_enable_S) - Partial_remainder_DN = Sqrt_enable_SO?Sqrt_R2:Iteration_cell_sum_AMASK_D[1]; - else - Partial_remainder_DN = Partial_remainder_DP; - end - 2'b10: - begin - if(Fsm_enable_S) - Partial_remainder_DN = Sqrt_enable_SO?Sqrt_R3:Iteration_cell_sum_AMASK_D[2]; - else - Partial_remainder_DN = Partial_remainder_DP; - end - 2'b11: - begin - if(Fsm_enable_S) - Partial_remainder_DN = Sqrt_enable_SO?Sqrt_R4:Iteration_cell_sum_AMASK_D[3]; - else - Partial_remainder_DN = Partial_remainder_DP; - end - endcase - end - - - - always_ff @(posedge Clk_CI, negedge Rst_RBI) // partial_remainder - begin - if(~Rst_RBI) - begin - Partial_remainder_DP <= '0; - end - else - begin - Partial_remainder_DP <= Partial_remainder_DN; - end - end - - logic [C_MANT_FP64+4:0] Quotient_DN; - - always_comb // Can choosen the different carry-outs based on different operations - begin - case (Iteration_unit_num_S) - 2'b00: - begin - if(Fsm_enable_S) - Quotient_DN= Sqrt_enable_SO ? {Quotient_DP[C_MANT_FP64+3:0],Sqrt_quotinent_S[3]} :{Quotient_DP[C_MANT_FP64+3:0],Iteration_cell_carry_D[0]}; - else - Quotient_DN= Quotient_DP; - end - 2'b01: - begin - if(Fsm_enable_S) - Quotient_DN= Sqrt_enable_SO ? {Quotient_DP[C_MANT_FP64+2:0],Sqrt_quotinent_S[3:2]} :{Quotient_DP[C_MANT_FP64+2:0],Iteration_cell_carry_D[0],Iteration_cell_carry_D[1]}; - else - Quotient_DN= Quotient_DP; - end - 2'b10: - begin - if(Fsm_enable_S) - Quotient_DN= Sqrt_enable_SO ? {Quotient_DP[C_MANT_FP64+1:0],Sqrt_quotinent_S[3:1]} : {Quotient_DP[C_MANT_FP64+1:0],Iteration_cell_carry_D[0],Iteration_cell_carry_D[1],Iteration_cell_carry_D[2]}; - else - Quotient_DN= Quotient_DP; - end - 2'b11: - begin - if(Fsm_enable_S) - Quotient_DN= Sqrt_enable_SO ? {Quotient_DP[C_MANT_FP64:0],Sqrt_quotinent_S } : {Quotient_DP[C_MANT_FP64:0],Iteration_cell_carry_D[0],Iteration_cell_carry_D[1],Iteration_cell_carry_D[2],Iteration_cell_carry_D[3]}; - else - Quotient_DN= Quotient_DP; - end - endcase - end - - always_ff @(posedge Clk_CI, negedge Rst_RBI) // Quotient - begin - if(~Rst_RBI) - begin - Quotient_DP <= '0; - end - else - Quotient_DP <= Quotient_DN; - end - - - ///////////////////////////////////////////////////////////////////////////// - // Precision Control for outputs // - ///////////////////////////////////////////////////////////////////////////// - - -//////////////////////one iteration unit, start/////////////////////////////////////// - generate - if(Iteration_unit_num_S==2'b00) - begin - always_comb - begin - case (Format_sel_S) - 2'b00: - begin - case (Precision_ctl_S) - 6'h00: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32+4:0],{(C_MANT_FP64-C_MANT_FP32){1'b0}}}; //+4 - end - 6'h17: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32:0],{(C_MANT_FP64-C_MANT_FP32+4){1'b0}}}; //Precision_ctl_S+1 - end - 6'h16: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32-1:0],{(C_MANT_FP64-C_MANT_FP32+4+1){1'b0}}}; //Precision_ctl_S+1 - end - 6'h15: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32-2:0],{(C_MANT_FP64-C_MANT_FP32+4+2){1'b0}}}; //Precision_ctl_S+1 - end - 6'h14: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32-3:0],{(C_MANT_FP64-C_MANT_FP32+4+3){1'b0}}}; //Precision_ctl_S+1 - end - 6'h13: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32-4:0],{(C_MANT_FP64-C_MANT_FP32+4+4){1'b0}}}; //Precision_ctl_S+1 - end - 6'h12: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32-5:0],{(C_MANT_FP64-C_MANT_FP32+4+5){1'b0}}}; //Precision_ctl_S+1 - end - 6'h11: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32-6:0],{(C_MANT_FP64-C_MANT_FP32+4+6){1'b0}}}; //Precision_ctl_S+1 - end - 6'h10: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32-7:0],{(C_MANT_FP64-C_MANT_FP32+4+7){1'b0}}}; //Precision_ctl_S+1 - end - 6'h0f: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32-8:0],{(C_MANT_FP64-C_MANT_FP32+4+8){1'b0}}}; //Precision_ctl_S+1 - end - 6'h0e: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32-9:0],{(C_MANT_FP64-C_MANT_FP32+4+9){1'b0}}}; //Precision_ctl_S+1 - end - 6'h0d: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32-10:0],{(C_MANT_FP64-C_MANT_FP32+4+10){1'b0}}}; //Precision_ctl_S+1 - end - 6'h0c: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32-11:0],{(C_MANT_FP64-C_MANT_FP32+4+11){1'b0}}}; //Precision_ctl_S+1 - end - 6'h0b: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32-12:0],{(C_MANT_FP64-C_MANT_FP32+4+12){1'b0}}}; //Precision_ctl_S+1 - end - 6'h0a: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32-13:0],{(C_MANT_FP64-C_MANT_FP32+4+13){1'b0}}}; //Precision_ctl_S+1 - end - 6'h09: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32-14:0],{(C_MANT_FP64-C_MANT_FP32+4+14){1'b0}}}; //Precision_ctl_S+1 - end - 6'h08: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32-15:0],{(C_MANT_FP64-C_MANT_FP32+4+15){1'b0}}}; //Precision_ctl_S+1 - end - 6'h07: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32-16:0],{(C_MANT_FP64-C_MANT_FP32+4+16){1'b0}}}; //Precision_ctl_S+1 - end - default : - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32+4:0],{(C_MANT_FP64-C_MANT_FP32){1'b0}}}; //+4 - end - endcase - end - - 2'b01: - begin - case (Precision_ctl_S) - 6'h00: - begin - Mant_result_prenorm_DO = Quotient_DP[C_MANT_FP64+4:0]; //+4 - end - 6'h34: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64:0],{(4){1'b0}}}; //Precision_ctl_S+1 - end - 6'h33: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-1:0],{(4+1){1'b0}}}; //Precision_ctl_S+1 - end - 6'h32: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-2:0],{(4+2){1'b0}}}; //Precision_ctl_S+1 - end - 6'h31: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-3:0],{(4+3){1'b0}}}; //Precision_ctl_S+1 - end - 6'h30: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-4:0],{(4+4){1'b0}}}; //Precision_ctl_S+1 - end - 6'h2f: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-5:0],{(4+5){1'b0}}}; //Precision_ctl_S+1 - end - 6'h2e: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-6:0],{(4+6){1'b0}}}; //Precision_ctl_S+1 - end - 6'h2d: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-7:0],{(4+7){1'b0}}}; //Precision_ctl_S+1 - end - 6'h2c: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-8:0],{(4+8){1'b0}}}; //Precision_ctl_S+1 - end - 6'h2b: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-9:0],{(4+9){1'b0}}}; //Precision_ctl_S+1 - end - 6'h2a: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-10:0],{(4+10){1'b0}}}; //Precision_ctl_S+1 - end - 6'h29: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-11:0],{(4+11){1'b0}}}; //Precision_ctl_S+1 - end - 6'h28: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-12:0],{(4+12){1'b0}}}; //Precision_ctl_S+1 - end - 6'h27: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-13:0],{(4+13){1'b0}}}; //Precision_ctl_S+1 - end - 6'h26: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-14:0],{(4+14){1'b0}}}; //Precision_ctl_S+1 - end - 6'h25: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-15:0],{(4+15){1'b0}}}; //Precision_ctl_S+1 - end - 6'h24: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-16:0],{(4+16){1'b0}}}; //Precision_ctl_S+1 - end - 6'h23: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-17:0],{(4+17){1'b0}}}; //Precision_ctl_S+1 - end - 6'h22: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-18:0],{(4+18){1'b0}}}; //Precision_ctl_S+1 - end - 6'h21: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-19:0],{(4+19){1'b0}}}; //Precision_ctl_S+1 - end - 6'h20: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-20:0],{(4+20){1'b0}}}; //Precision_ctl_S+1 - end - 6'h1f: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-21:0],{(4+21){1'b0}}}; //Precision_ctl_S+1 - end - 6'h1e: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-22:0],{(4+22){1'b0}}}; //Precision_ctl_S+1 - end - 6'h1d: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-23:0],{(4+23){1'b0}}}; //Precision_ctl_S+1 - end - 6'h1c: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-24:0],{(4+24){1'b0}}}; //Precision_ctl_S+1 - end - 6'h1b: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-25:0],{(4+25){1'b0}}}; //Precision_ctl_S+1 - end - 6'h1a: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-26:0],{(4+26){1'b0}}}; //Precision_ctl_S+1 - end - 6'h19: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-27:0],{(4+27){1'b0}}}; //Precision_ctl_S+1 - end - 6'h18: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-28:0],{(4+28){1'b0}}}; //Precision_ctl_S+1 - end - 6'h17: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-29:0],{(4+29){1'b0}}}; //Precision_ctl_S+1 - end - 6'h16: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-30:0],{(4+30){1'b0}}}; //Precision_ctl_S+1 - end - 6'h15: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-31:0],{(4+31){1'b0}}}; //Precision_ctl_S+1 - end - 6'h14: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-32:0],{(4+32){1'b0}}}; //Precision_ctl_S+1 - end - 6'h13: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-33:0],{(4+33){1'b0}}}; //Precision_ctl_S+1 - end - 6'h12: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-34:0],{(4+34){1'b0}}}; //Precision_ctl_S+1 - end - 6'h11: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-35:0],{(4+35){1'b0}}}; //Precision_ctl_S+1 - end - 6'h10: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-36:0],{(4+36){1'b0}}}; //Precision_ctl_S+1 - end - 6'h0f: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-37:0],{(4+37){1'b0}}}; //Precision_ctl_S+1 - end - 6'h0e: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-38:0],{(4+38){1'b0}}}; //Precision_ctl_S+1 - end - 6'h0d: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-39:0],{(4+39){1'b0}}}; //Precision_ctl_S+1 - end - 6'h0c: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-40:0],{(4+40){1'b0}}}; //Precision_ctl_S+1 - end - 6'h0b: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-41:0],{(4+41){1'b0}}}; //Precision_ctl_S+1 - end - 6'h0a: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-42:0],{(4+42){1'b0}}}; //Precision_ctl_S+1 - end - 6'h09: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-43:0],{(4+43){1'b0}}}; //Precision_ctl_S+1 - end - 6'h08: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-44:0],{(4+44){1'b0}}}; //Precision_ctl_S+1 - end - 6'h07: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-45:0],{(4+45){1'b0}}}; //Precision_ctl_S+1 - end - default: - begin - Mant_result_prenorm_DO = Quotient_DP[C_MANT_FP64+4:0]; //+4 - end - endcase - end - - 2'b10: - begin - case (Precision_ctl_S) - 6'b00: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP16+4:0],{(C_MANT_FP64-C_MANT_FP16){1'b0}}}; //+4 - end - 6'h0a: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP16:0],{(C_MANT_FP64-C_MANT_FP16+4){1'b0}}}; //Precision_ctl_S+1 - end - 6'h09: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP16-1:0],{(C_MANT_FP64-C_MANT_FP16+4+1){1'b0}}}; //Precision_ctl_S+1 - end - 6'h08: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP16-2:0],{(C_MANT_FP64-C_MANT_FP16+4+2){1'b0}}}; //Precision_ctl_S+1 - end - 6'h07: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP16-3:0],{(C_MANT_FP64-C_MANT_FP16+4+3){1'b0}}}; //Precision_ctl_S+1 - end - default : - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP16+4:0],{(C_MANT_FP64-C_MANT_FP16){1'b0}}}; //+4 - end - endcase - end - - 2'b11: - begin - - case (Precision_ctl_S) - 6'b00: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP16ALT+4:0],{(C_MANT_FP64-C_MANT_FP16ALT){1'b0}}}; //+4 - end - 6'h07: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP16ALT:0],{(C_MANT_FP64-C_MANT_FP16ALT+4){1'b0}}}; //Precision_ctl_S+1 - end - default : - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP16ALT+4:0],{(C_MANT_FP64-C_MANT_FP16ALT){1'b0}}}; //+4 - end - endcase - end - endcase - end - end - endgenerate -//////////////////////one iteration unit, end////////////////////////////////////////// - -//////////////////////two iteration units, start/////////////////////////////////////// - generate - if(Iteration_unit_num_S==2'b01) - begin - always_comb - begin - case (Format_sel_S) - 2'b00: - begin - case (Precision_ctl_S) - 6'h00: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32+4:0],{(C_MANT_FP64-C_MANT_FP32){1'b0}}}; //+4 - end - 6'h17,6'h16: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32:0],{(C_MANT_FP64-C_MANT_FP32+4){1'b0}}}; //Precision_ctl_S+1 - end - 6'h15,6'h14: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32-2:0],{(C_MANT_FP64-C_MANT_FP32+4+2){1'b0}}}; //Precision_ctl_S+1 - end - 6'h13,6'h12: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32-4:0],{(C_MANT_FP64-C_MANT_FP32+4+4){1'b0}}}; //Precision_ctl_S+1 - end - 6'h11,6'h10: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32-6:0],{(C_MANT_FP64-C_MANT_FP32+4+6){1'b0}}}; //Precision_ctl_S+1 - end - 6'h0f,6'h0e: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32-8:0],{(C_MANT_FP64-C_MANT_FP32+4+8){1'b0}}}; //Precision_ctl_S+1 - end - 6'h0d,6'h0c: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32-10:0],{(C_MANT_FP64-C_MANT_FP32+4+10){1'b0}}}; //Precision_ctl_S+1 - end - 6'h0b,6'h0a: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32-12:0],{(C_MANT_FP64-C_MANT_FP32+4+12){1'b0}}}; //Precision_ctl_S+1 - end - 6'h09,6'h08: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32-14:0],{(C_MANT_FP64-C_MANT_FP32+4+14){1'b0}}}; //Precision_ctl_S+1 - end - 6'h07,6'h06: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32-16:0],{(C_MANT_FP64-C_MANT_FP32+4+16){1'b0}}}; //Precision_ctl_S+1 - end - default: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32+4:0],{(C_MANT_FP64-C_MANT_FP32){1'b0}}}; //+4 - end - endcase - end - 2'b01: - begin - case (Precision_ctl_S) - 6'h00: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64+3:0],1'b0}; //+3 - end - 6'h34: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64+1:1],{(4){1'b0}} }; //Precision_ctl_S+1 - end - 6'h33,6'h32: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-1:0],{(4+1){1'b0}} }; //Precision_ctl_S+1 - end - 6'h31,6'h30: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-3:0],{(4+3){1'b0}} }; //Precision_ctl_S+1 - end - 6'h2f,6'h2e: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-5:0],{(4+5){1'b0}} }; //Precision_ctl_S+1 - end - 6'h2d,6'h2c: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-7:0],{(4+7){1'b0}} }; //Precision_ctl_S+1 - end - 6'h2b,6'h2a: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-9:0],{(4+9){1'b0}} }; //Precision_ctl_S+1 - end - 6'h29,6'h28: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-11:0],{(4+11){1'b0}} }; //Precision_ctl_S+1 - end - 6'h27,6'h26: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-13:0],{(4+13){1'b0}} }; //Precision_ctl_S+1 - end - 6'h25,6'h24: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-15:0],{(4+15){1'b0}} }; //Precision_ctl_S+1 - end - 6'h23,6'h22: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-17:0],{(4+17){1'b0}} }; //Precision_ctl_S+1 - end - 6'h21,6'h20: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-19:0],{(4+19){1'b0}} }; //Precision_ctl_S+1 - end - 6'h1f,6'h1e: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-21:0],{(4+21){1'b0}} }; //Precision_ctl_S+1 - end - 6'h1d,6'h1c: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-23:0],{(4+23){1'b0}} }; //Precision_ctl_S+1 - end - 6'h1b,6'h1a: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-25:0],{(4+25){1'b0}} }; //Precision_ctl_S+1 - end - 6'h19,6'h18: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-27:0],{(4+27){1'b0}} }; //Precision_ctl_S+1 - end - 6'h17,6'h16: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-29:0],{(4+29){1'b0}} }; //Precision_ctl_S+1 - end - 6'h15,6'h14: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-31:0],{(4+31){1'b0}} }; //Precision_ctl_S+1 - end - 6'h13,6'h12: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-33:0],{(4+33){1'b0}} }; //Precision_ctl_S+1 - end - 6'h11,6'h10: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-35:0],{(4+35){1'b0}} }; //Precision_ctl_S+1 - end - 6'h0f,6'h0e: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-37:0],{(4+37){1'b0}} }; //Precision_ctl_S+1 - end - 6'h0d,6'h0c: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-39:0],{(4+39){1'b0}} }; //Precision_ctl_S+1 - end - 6'h0b,6'h0a: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-41:0],{(4+41){1'b0}} }; //Precision_ctl_S+1 - end - 6'h09,6'h08: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-43:0],{(4+43){1'b0}} }; //Precision_ctl_S+1 - end - 6'h07: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-45:0],{(4+45){1'b0}} }; //Precision_ctl_S+1 - end - default: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64+3:0],1'b0}; //+3 - end - endcase - end - - 2'b10: - begin - case (Precision_ctl_S) - 6'b00: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP16+3:0],{(C_MANT_FP64-C_MANT_FP16+1){1'b0}} }; //+3 - end - 6'h0a: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP16+1:1],{(C_MANT_FP64-C_MANT_FP16+4){1'b0}} }; //Precision_ctl_S+1 - end - 6'h09,6'h08: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP16-1:0],{(C_MANT_FP64-C_MANT_FP16+4+1){1'b0}} }; //Precision_ctl_S+1 - end - 6'h07: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP16-3:0],{(C_MANT_FP64-C_MANT_FP16+4+3){1'b0}} }; //Precision_ctl_S+1 - end - default : - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP16+4:0],{(C_MANT_FP64-C_MANT_FP16){1'b0}} }; //+4 - end - endcase - end - - 2'b11: - begin - - case (Precision_ctl_S) - 6'b00: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP16ALT+4:0],{(C_MANT_FP64-C_MANT_FP16ALT){1'b0}} }; //+4 - end - 6'h07: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP16ALT:0],{(C_MANT_FP64-C_MANT_FP16ALT+4){1'b0}} }; //Precision_ctl_S+1 - end - default : - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP16ALT+4:0],{(C_MANT_FP64-C_MANT_FP16ALT){1'b0}} }; //+4 - end - endcase - end - endcase - end - end - endgenerate -//////////////////////two iteration units, end////////////////////////////////////////// - -//////////////////////three iteration units, start/////////////////////////////////////// - generate - if(Iteration_unit_num_S==2'b10) - begin - always_comb - begin - case (Format_sel_S) - 2'b00: - begin - case (Precision_ctl_S) - 6'h00: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32+3:0],{(C_MANT_FP64-C_MANT_FP32+1){1'b0}}}; //+3 - end - 6'h17,6'h16,6'h15: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32:0],{(C_MANT_FP64-C_MANT_FP32+4){1'b0}}}; //Precision_ctl_S+1 - end - 6'h14,6'h13,6'h12: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32-3:0],{(C_MANT_FP64-C_MANT_FP32+4+3){1'b0}}}; //Precision_ctl_S+1 - end - 6'h11,6'h10,6'h0f: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32-6:0],{(C_MANT_FP64-C_MANT_FP32+4+6){1'b0}}}; //Precision_ctl_S+1 - end - 6'h0e,6'h0d,6'h0c: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32-9:0],{(C_MANT_FP64-C_MANT_FP32+4+9){1'b0}}}; //Precision_ctl_S+1 - end - 6'h0b,6'h0a,6'h09: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32-12:0],{(C_MANT_FP64-C_MANT_FP32+4+12){1'b0}}}; //Precision_ctl_S+1 - end - 6'h08,6'h07,6'h06: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32-15:0],{(C_MANT_FP64-C_MANT_FP32+4+15){1'b0}}}; //Precision_ctl_S+1 - end - default: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32+3:0],{(C_MANT_FP64-C_MANT_FP32+1){1'b0}}}; //+3 - end - endcase - end - - 2'b01: - begin - case (Precision_ctl_S) - 6'h00: - begin - Mant_result_prenorm_DO = Quotient_DP[C_MANT_FP64+4:0]; //+4 - end - 6'h34,6'h33: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64+1:1],{(4){1'b0}} }; //Precision_ctl_S+1 - end - 6'h32,6'h31,6'h30: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-2:0],{(4+2){1'b0}} }; //Precision_ctl_S+1 - end - 6'h2f,6'h2e,6'h2d: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-5:0],{(4+5){1'b0}} }; //Precision_ctl_S+1 - end - 6'h2c,6'h2b,6'h2a: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-8:0],{(4+8){1'b0}} }; //Precision_ctl_S+1 - end - 6'h29,6'h28,6'h27: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-11:0],{(4+11){1'b0}} }; //Precision_ctl_S+1 - end - 6'h26,6'h25,6'h24: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-14:0],{(4+14){1'b0}} }; //Precision_ctl_S+1 - end - 6'h23,6'h22,6'h21: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-17:0],{(4+17){1'b0}} }; //Precision_ctl_S+1 - end - 6'h20,6'h1f,6'h1e: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-20:0],{(4+20){1'b0}} }; //Precision_ctl_S+1 - end - 6'h1d,6'h1c,6'h1b: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-23:0],{(4+23){1'b0}} }; //Precision_ctl_S+1 - end - 6'h1a,6'h19,6'h18: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-26:0],{(4+26){1'b0}} }; //Precision_ctl_S+1 - end - 6'h17,6'h16,6'h15: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-29:0],{(4+29){1'b0}} }; //Precision_ctl_S+1 - end - 6'h14,6'h13,6'h12: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-32:0],{(4+32){1'b0}} }; //Precision_ctl_S+1 - end - 6'h11,6'h10,6'h0f: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-35:0],{(4+35){1'b0}} }; //Precision_ctl_S+1 - end - 6'h0e,6'h0d,6'h0c: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-38:0],{(4+38){1'b0}} }; //Precision_ctl_S+1 - end - 6'h0b,6'h0a,6'h09: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-41:0],{(4+41){1'b0}} }; //Precision_ctl_S+1 - end - 6'h08,6'h07,6'h06: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-44:0],{(4+44){1'b0}} }; //Precision_ctl_S+1 - end - default: - begin - Mant_result_prenorm_DO = Quotient_DP[C_MANT_FP64+4:0]; //+4 - end - endcase - end - - 2'b10: - begin - case (Precision_ctl_S) - 6'b00: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP16+4:0],{(C_MANT_FP64-C_MANT_FP16){1'b0}} }; //+4 - end - 6'h0a,6'h09: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP16+1:1],{(C_MANT_FP64-C_MANT_FP16+4){1'b0}} }; //Precision_ctl_S+1 - end - 6'h08,6'h07,6'h06: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP16-2:0],{(C_MANT_FP64-C_MANT_FP16+4+2){1'b0}} }; //Precision_ctl_S+1 - end - default : - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP16+4:0],{(C_MANT_FP64-C_MANT_FP16){1'b0}} }; //+4 - end - endcase - end - - 2'b11: - begin - - case (Precision_ctl_S) - 6'b00: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP16ALT+4:0],{(C_MANT_FP64-C_MANT_FP16ALT){1'b0}} }; //+4 - end - 6'h07,6'h06: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP16ALT+1:1],{(C_MANT_FP64-C_MANT_FP16ALT+4){1'b0}} }; //Precision_ctl_S+1 - end - default : - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP16ALT+4:0],{(C_MANT_FP64-C_MANT_FP16ALT){1'b0}} }; //+4 - end - endcase - end - endcase - end - end - endgenerate -//////////////////////three iteration units, end////////////////////////////////////////// - -//////////////////////four iteration units, start/////////////////////////////////////// - generate - if(Iteration_unit_num_S==2'b11) - begin - always_comb - begin - case (Format_sel_S) - 2'b00: - begin - case (Precision_ctl_S) - 6'h00: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32+4:0],{(C_MANT_FP64-C_MANT_FP32){1'b0}}}; //+4 - end - 6'h17,6'h16,6'h15,6'h14: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32:0],{(C_MANT_FP64-C_MANT_FP32+4){1'b0}}}; //Precision_ctl_S+1 - end - 6'h13,6'h12,6'h11,6'h10: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32-4:0],{(C_MANT_FP64-C_MANT_FP32+4+4){1'b0}}}; //Precision_ctl_S+1 - end - 6'h0f,6'h0e,6'h0d,6'h0c: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32-8:0],{(C_MANT_FP64-C_MANT_FP32+4+8){1'b0}}}; //Precision_ctl_S+1 - end - 6'h0b,6'h0a,6'h09,6'h08: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32-12:0],{(C_MANT_FP64-C_MANT_FP32+4+12){1'b0}}}; //Precision_ctl_S+1 - end - 6'h07,6'h06: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32-16:0],{(C_MANT_FP64-C_MANT_FP32+4+16){1'b0}}}; //Precision_ctl_S+1 - end - default: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32+4:0],{(C_MANT_FP64-C_MANT_FP32){1'b0}}}; //+4 - end - endcase - end - - 2'b01: - begin - case (Precision_ctl_S) - 6'h00: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64+3:0],{(1){1'b0}}}; //+3 - end - 6'h34: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64+3:0],{(1){1'b0}} }; //Precision_ctl_S+1 - end - 6'h33,6'h32,6'h31,6'h30: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-1:0],{(5){1'b0}} }; //Precision_ctl_S+1 - end - 6'h2f,6'h2e,6'h2d,6'h2c: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-5:0],{(9){1'b0}} }; //Precision_ctl_S+1 - end - 6'h2b,6'h2a,6'h29,6'h28: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-9:0],{(13){1'b0}} }; //Precision_ctl_S+1 - end - 6'h27,6'h26,6'h25,6'h24: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-13:0],{(17){1'b0}} }; //Precision_ctl_S+1 - end - 6'h23,6'h22,6'h21,6'h20: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-17:0],{(21){1'b0}} }; //Precision_ctl_S+1 - end - 6'h1f,6'h1e,6'h1d,6'h1c: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-21:0],{(25){1'b0}} }; //Precision_ctl_S+1 - end - 6'h1b,6'h1a,6'h19,6'h18: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-25:0],{(29){1'b0}} }; //Precision_ctl_S+1 - end - 6'h17,6'h16,6'h15,6'h14: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-29:0],{(33){1'b0}} }; //Precision_ctl_S+1 - end - 6'h13,6'h12,6'h11,6'h10: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-33:0],{(37){1'b0}} }; //Precision_ctl_S+1 - end - 6'h0f,6'h0e,6'h0d,6'h0c: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-37:0],{(41){1'b0}} }; //Precision_ctl_S+1 - end - 6'h0b,6'h0a,6'h09,6'h08: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-41:0],{(45){1'b0}} }; //Precision_ctl_S+1 - end - 6'h07,6'h06: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-45:0],{(49){1'b0}} }; //Precision_ctl_S+1 - end - default: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64+3:0],{(1){1'b0}}}; //+3 - end - endcase - end - - 2'b10: - begin - case (Precision_ctl_S) - 6'b00: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP16+5:0],{(C_MANT_FP64-C_MANT_FP16-1){1'b0}} }; //+5 - end - 6'h0a,6'h09,6'h08: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP16+1:1],{(C_MANT_FP64-C_MANT_FP16+4){1'b0}} }; //Precision_ctl_S+1 - end - 6'h07,6'h06: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP16+1-4:0],{(C_MANT_FP64-C_MANT_FP16+4+3){1'b0}} }; //Precision_ctl_S+1 - end - default : - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP16+5:0],{(C_MANT_FP64-C_MANT_FP16-1){1'b0}} }; //+5 - end - endcase - end - - 2'b11: - begin - - case (Precision_ctl_S) - 6'b00: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP16ALT+4:0],{(C_MANT_FP64-C_MANT_FP16ALT){1'b0}} }; //+4 - end - 6'h07,6'h06: - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP16ALT:0],{(C_MANT_FP64-C_MANT_FP16ALT+4){1'b0}} }; //Precision_ctl_S+1 - end - default : - begin - Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP16ALT+4:0],{(C_MANT_FP64-C_MANT_FP16ALT){1'b0}} }; //+4 - end - endcase - end - endcase - end - end - endgenerate -//////////////////////four iteration units, end/////////////////////////////////////// - - - - - -// resultant exponent - logic [C_EXP_FP64+1:0] Exp_result_prenorm_DN,Exp_result_prenorm_DP; - - logic [C_EXP_FP64+1:0] Exp_add_a_D; - logic [C_EXP_FP64+1:0] Exp_add_b_D; - logic [C_EXP_FP64+1:0] Exp_add_c_D; - - integer C_BIAS_AONE, C_HALF_BIAS; - always_comb - begin // - case (Format_sel_S) - 2'b00: - begin - C_BIAS_AONE =C_BIAS_AONE_FP32; - C_HALF_BIAS =C_HALF_BIAS_FP32; - end - 2'b01: - begin - C_BIAS_AONE =C_BIAS_AONE_FP64; - C_HALF_BIAS =C_HALF_BIAS_FP64; - end - 2'b10: - begin - C_BIAS_AONE =C_BIAS_AONE_FP16; - C_HALF_BIAS =C_HALF_BIAS_FP16; - end - 2'b11: - begin - C_BIAS_AONE =C_BIAS_AONE_FP16ALT; - C_HALF_BIAS =C_HALF_BIAS_FP16ALT; - end - endcase - end - -//For division, exponent=(Exp_a_D-LZ1)-(Exp_b_D-LZ2)+BIAS -//For square root, exponent=(Exp_a_D-LZ1)/2+(Exp_a_D-LZ1)%2+C_HALF_BIAS -//For exponent, in preprorces module, (Exp_a_D-LZ1) and (Exp_b_D-LZ2) have been processed with the corresponding process for denormal numbers. - - assign Exp_add_a_D = {Sqrt_start_dly_S?{Exp_num_DI[C_EXP_FP64],Exp_num_DI[C_EXP_FP64],Exp_num_DI[C_EXP_FP64],Exp_num_DI[C_EXP_FP64:1]}:{Exp_num_DI[C_EXP_FP64],Exp_num_DI[C_EXP_FP64],Exp_num_DI}}; - assign Exp_add_b_D = {Sqrt_start_dly_S?{1'b0,{C_EXP_ZERO_FP64},Exp_num_DI[0]}:{~Exp_den_DI[C_EXP_FP64],~Exp_den_DI[C_EXP_FP64],~Exp_den_DI}}; - assign Exp_add_c_D = {Div_start_dly_S?{{C_BIAS_AONE}}:{{C_HALF_BIAS}}}; - assign Exp_result_prenorm_DN = (Start_dly_S)?{Exp_add_a_D + Exp_add_b_D + Exp_add_c_D}:Exp_result_prenorm_DP; - - - always_ff @(posedge Clk_CI, negedge Rst_RBI) - begin - if(~Rst_RBI) - begin - Exp_result_prenorm_DP <= '0; - end - else - begin - Exp_result_prenorm_DP<= Exp_result_prenorm_DN; - end - end - - assign Exp_result_prenorm_DO = Exp_result_prenorm_DP; - -endmodule diff --git a/rtl/vendor/pulp_platform_fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv b/rtl/vendor/pulp_platform_fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv deleted file mode 100644 index b3f41fec6..000000000 --- a/rtl/vendor/pulp_platform_fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv +++ /dev/null @@ -1,83 +0,0 @@ -// Copyright 2018 ETH Zurich and University of Bologna. -// Copyright and related rights are licensed under the Solderpad Hardware -// License, Version 0.51 (the “License”); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law -// or agreed to in writing, software, hardware and materials distributed under -// this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR -// CONDITIONS OF ANY KIND, either express or implied. See the License for the -// specific language governing permissions and limitations under the License. -// -// This file contains all div_sqrt_top_mvp parameters -// Authors : Lei Li (lile@iis.ee.ethz.ch) - -package defs_div_sqrt_mvp; - - // op command - localparam C_RM = 3; - localparam C_RM_NEAREST = 3'h0; - localparam C_RM_TRUNC = 3'h1; - localparam C_RM_PLUSINF = 3'h2; - localparam C_RM_MINUSINF = 3'h3; - localparam C_PC = 6; // Precision Control - localparam C_FS = 2; // Format Selection - localparam C_IUNC = 2; // Iteration Unit Number Control - localparam Iteration_unit_num_S = 2'b10; - - // FP64 - localparam C_OP_FP64 = 64; - localparam C_MANT_FP64 = 52; - localparam C_EXP_FP64 = 11; - localparam C_BIAS_FP64 = 1023; - localparam C_BIAS_AONE_FP64 = 11'h400; - localparam C_HALF_BIAS_FP64 = 511; - localparam C_EXP_ZERO_FP64 = 11'h000; - localparam C_EXP_ONE_FP64 = 13'h001; // Bit width is in agreement with in norm - localparam C_EXP_INF_FP64 = 11'h7FF; - localparam C_MANT_ZERO_FP64 = 52'h0; - localparam C_MANT_NAN_FP64 = 52'h8_0000_0000_0000; - localparam C_PZERO_FP64 = 64'h0000_0000_0000_0000; - localparam C_MZERO_FP64 = 64'h8000_0000_0000_0000; - localparam C_QNAN_FP64 = 64'h7FF8_0000_0000_0000; - - // FP32 - localparam C_OP_FP32 = 32; - localparam C_MANT_FP32 = 23; - localparam C_EXP_FP32 = 8; - localparam C_BIAS_FP32 = 127; - localparam C_BIAS_AONE_FP32 = 8'h80; - localparam C_HALF_BIAS_FP32 = 63; - localparam C_EXP_ZERO_FP32 = 8'h00; - localparam C_EXP_INF_FP32 = 8'hFF; - localparam C_MANT_ZERO_FP32 = 23'h0; - localparam C_PZERO_FP32 = 32'h0000_0000; - localparam C_MZERO_FP32 = 32'h8000_0000; - localparam C_QNAN_FP32 = 32'h7FC0_0000; - - // FP16 - localparam C_OP_FP16 = 16; - localparam C_MANT_FP16 = 10; - localparam C_EXP_FP16 = 5; - localparam C_BIAS_FP16 = 15; - localparam C_BIAS_AONE_FP16 = 5'h10; - localparam C_HALF_BIAS_FP16 = 7; - localparam C_EXP_ZERO_FP16 = 5'h00; - localparam C_EXP_INF_FP16 = 5'h1F; - localparam C_MANT_ZERO_FP16 = 10'h0; - localparam C_PZERO_FP16 = 16'h0000; - localparam C_MZERO_FP16 = 16'h8000; - localparam C_QNAN_FP16 = 16'h7E00; - - // FP16alt - localparam C_OP_FP16ALT = 16; - localparam C_MANT_FP16ALT = 7; - localparam C_EXP_FP16ALT = 8; - localparam C_BIAS_FP16ALT = 127; - localparam C_BIAS_AONE_FP16ALT = 8'h80; - localparam C_HALF_BIAS_FP16ALT = 63; - localparam C_EXP_ZERO_FP16ALT = 8'h00; - localparam C_EXP_INF_FP16ALT = 8'hFF; - localparam C_MANT_ZERO_FP16ALT = 7'h0; - localparam C_QNAN_FP16ALT = 16'h7FC0; - -endpackage : defs_div_sqrt_mvp diff --git a/rtl/vendor/pulp_platform_fpu_div_sqrt_mvp/hdl/div_sqrt_mvp_wrapper.sv b/rtl/vendor/pulp_platform_fpu_div_sqrt_mvp/hdl/div_sqrt_mvp_wrapper.sv deleted file mode 100644 index 051bcc3ad..000000000 --- a/rtl/vendor/pulp_platform_fpu_div_sqrt_mvp/hdl/div_sqrt_mvp_wrapper.sv +++ /dev/null @@ -1,232 +0,0 @@ -// Copyright 2018 ETH Zurich and University of Bologna. -// Copyright and related rights are licensed under the Solderpad Hardware -// License, Version 0.51 (the “License”); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law -// or agreed to in writing, software, hardware and materials distributed under -// this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR -// CONDITIONS OF ANY KIND, either express or implied. See the License for the -// specific language governing permissions and limitations under the License. -//////////////////////////////////////////////////////////////////////////////// -// Company: IIS @ ETHZ - Federal Institute of Technology // -// // -// Engineers: Lei Li -- lile@iis.ee.ethz.ch // -// // -// Additional contributions by: // -// // -// // -// // -// Create Date: 20/04/2018 // -// Design Name: FPU // -// Module Name: div_sqrt_mvp_wrapper.sv // -// Project Name: The shared divisor and square root // -// Language: SystemVerilog // -// // -// Description: The wrapper of div_sqrt_top_mvp // -// // -// // -// // -// // -// // -// // -// // -// // -// // -// // -// // -//////////////////////////////////////////////////////////////////////////////// - -import defs_div_sqrt_mvp::*; - -module div_sqrt_mvp_wrapper -#( - parameter PrePipeline_depth_S = 0, // If you want to add a flip/flop stage before preprocess, set it to 1. - parameter PostPipeline_depth_S = 2 // The output delay stages -) - (//Input - input logic Clk_CI, - input logic Rst_RBI, - input logic Div_start_SI, - input logic Sqrt_start_SI, - - //Input Operands - input logic [C_OP_FP64-1:0] Operand_a_DI, - input logic [C_OP_FP64-1:0] Operand_b_DI, - - // Input Control - input logic [C_RM-1:0] RM_SI, //Rounding Mode - input logic [C_PC-1:0] Precision_ctl_SI, // Precision Control - input logic [C_FS-1:0] Format_sel_SI, // Format Selection, - input logic Kill_SI, - - //Output Result - output logic [C_OP_FP64-1:0] Result_DO, - - //Output-Flags - output logic [4:0] Fflags_SO, - output logic Ready_SO, - output logic Done_SO - ); - - - logic Div_start_S_S,Sqrt_start_S_S; - logic [C_OP_FP64-1:0] Operand_a_S_D; - logic [C_OP_FP64-1:0] Operand_b_S_D; - - // Input Control - logic [C_RM-1:0] RM_S_S; //Rounding Mode - logic [C_PC-1:0] Precision_ctl_S_S; // Precision Control - logic [C_FS-1:0] Format_sel_S_S; // Format Selection, - logic Kill_S_S; - - - logic [C_OP_FP64-1:0] Result_D; - logic Ready_S; - logic Done_S; - logic [4:0] Fflags_S; - - - generate - if(PrePipeline_depth_S==1) - begin - - div_sqrt_top_mvp div_top_U0 //for RTL - - (//Input - .Clk_CI (Clk_CI), - .Rst_RBI (Rst_RBI), - .Div_start_SI (Div_start_S_S), - .Sqrt_start_SI (Sqrt_start_S_S), - //Input Operands - .Operand_a_DI (Operand_a_S_D), - .Operand_b_DI (Operand_b_S_D), - .RM_SI (RM_S_S), //Rounding Mode - .Precision_ctl_SI (Precision_ctl_S_S), - .Format_sel_SI (Format_sel_S_S), - .Kill_SI (Kill_S_S), - .Result_DO (Result_D), - .Fflags_SO (Fflags_S), - .Ready_SO (Ready_S), - .Done_SO (Done_S) - ); - - always_ff @(posedge Clk_CI, negedge Rst_RBI) - begin - if(~Rst_RBI) - begin - Div_start_S_S<='0; - Sqrt_start_S_S<=1'b0; - Operand_a_S_D<='0; - Operand_b_S_D<='0; - RM_S_S <=1'b0; - Precision_ctl_S_S<='0; - Format_sel_S_S<='0; - Kill_S_S<='0; - end - else - begin - Div_start_S_S<=Div_start_SI; - Sqrt_start_S_S<=Sqrt_start_SI; - Operand_a_S_D<=Operand_a_DI; - Operand_b_S_D<=Operand_b_DI; - RM_S_S <=RM_SI; - Precision_ctl_S_S<=Precision_ctl_SI; - Format_sel_S_S<=Format_sel_SI; - Kill_S_S<=Kill_SI; - end - end - end - - else - begin - div_sqrt_top_mvp div_top_U0 //for RTL - (//Input - .Clk_CI (Clk_CI), - .Rst_RBI (Rst_RBI), - .Div_start_SI (Div_start_SI), - .Sqrt_start_SI (Sqrt_start_SI), - //Input Operands - .Operand_a_DI (Operand_a_DI), - .Operand_b_DI (Operand_b_DI), - .RM_SI (RM_SI), //Rounding Mode - .Precision_ctl_SI (Precision_ctl_SI), - .Format_sel_SI (Format_sel_SI), - .Kill_SI (Kill_SI), - .Result_DO (Result_D), - .Fflags_SO (Fflags_S), - .Ready_SO (Ready_S), - .Done_SO (Done_S) - ); - end - endgenerate - - ///////////////////////////////////////////////////////////////////////////// - // First Stage of Outputs - ///////////////////////////////////////////////////////////////////////////// - logic [C_OP_FP64-1:0] Result_dly_S_D; - logic Ready_dly_S_S; - logic Done_dly_S_S; - logic [4:0] Fflags_dly_S_S; - always_ff @(posedge Clk_CI, negedge Rst_RBI) - begin - if(~Rst_RBI) - begin - Result_dly_S_D<='0; - Ready_dly_S_S<=1'b0; - Done_dly_S_S<=1'b0; - Fflags_dly_S_S<=1'b0; - end - else - begin - Result_dly_S_D<=Result_D; - Ready_dly_S_S<=Ready_S; - Done_dly_S_S<=Done_S; - Fflags_dly_S_S<=Fflags_S; - end - end - - ///////////////////////////////////////////////////////////////////////////// - // Second Stage of Outputs - ///////////////////////////////////////////////////////////////////////////// - - logic [C_OP_FP64-1:0] Result_dly_D_D; - logic Ready_dly_D_S; - logic Done_dly_D_S; - logic [4:0] Fflags_dly_D_S; - generate - if(PostPipeline_depth_S==2) - begin - always_ff @(posedge Clk_CI, negedge Rst_RBI) - begin - if(~Rst_RBI) - begin - Result_dly_D_D<='0; - Ready_dly_D_S<=1'b0; - Done_dly_D_S<=1'b0; - Fflags_dly_D_S<=1'b0; - end - else - begin - Result_dly_D_D<=Result_dly_S_D; - Ready_dly_D_S<=Ready_dly_S_S; - Done_dly_D_S<=Done_dly_S_S; - Fflags_dly_D_S<=Fflags_dly_S_S; - end - end - assign Result_DO = Result_dly_D_D; - assign Ready_SO = Ready_dly_D_S; - assign Done_SO = Done_dly_D_S; - assign Fflags_SO=Fflags_dly_D_S; - end - - else - begin - assign Result_DO = Result_dly_S_D; - assign Ready_SO = Ready_dly_S_S; - assign Done_SO = Done_dly_S_S; - assign Fflags_SO = Fflags_dly_S_S; - end - - endgenerate - -endmodule // diff --git a/rtl/vendor/pulp_platform_fpu_div_sqrt_mvp/hdl/div_sqrt_top_mvp.sv b/rtl/vendor/pulp_platform_fpu_div_sqrt_mvp/hdl/div_sqrt_top_mvp.sv deleted file mode 100644 index 3af6081b7..000000000 --- a/rtl/vendor/pulp_platform_fpu_div_sqrt_mvp/hdl/div_sqrt_top_mvp.sv +++ /dev/null @@ -1,180 +0,0 @@ -// Copyright 2018 ETH Zurich and University of Bologna. -// Copyright and related rights are licensed under the Solderpad Hardware -// License, Version 0.51 (the “License”); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law -// or agreed to in writing, software, hardware and materials distributed under -// this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR -// CONDITIONS OF ANY KIND, either express or implied. See the License for the -// specific language governing permissions and limitations under the License. - -//////////////////////////////////////////////////////////////////////////////// -// Company: IIS @ ETHZ - Federal Institute of Technology // -// // -// Engineers: Lei Li -- lile@iis.ee.ethz.ch // -// // -// Additional contributions by: // -// // -// // -// // -// Create Date: 03/03/2018 // -// Design Name: div_sqrt_top_mvp // -// Module Name: div_sqrt_top_mvp.sv // -// Project Name: The shared divisor and square root // -// Language: SystemVerilog // -// // -// Description: The top of div and sqrt // -// // -// // -// Revision Date: 12/04/2018 // -// Lei Li // -// To address some requirements by Stefan and add low power // -// control for special cases // -//////////////////////////////////////////////////////////////////////////////// - -import defs_div_sqrt_mvp::*; - -module div_sqrt_top_mvp - - (//Input - input logic Clk_CI, - input logic Rst_RBI, - input logic Div_start_SI, - input logic Sqrt_start_SI, - - //Input Operands - input logic [C_OP_FP64-1:0] Operand_a_DI, - input logic [C_OP_FP64-1:0] Operand_b_DI, - - // Input Control - input logic [C_RM-1:0] RM_SI, //Rounding Mode - input logic [C_PC-1:0] Precision_ctl_SI, // Precision Control - input logic [C_FS-1:0] Format_sel_SI, // Format Selection, - input logic Kill_SI, - - //Output Result - output logic [C_OP_FP64-1:0] Result_DO, - - //Output-Flags - output logic [4:0] Fflags_SO, - output logic Ready_SO, - output logic Done_SO - ); - - - - - - //Operand components - logic [C_EXP_FP64:0] Exp_a_D; - logic [C_EXP_FP64:0] Exp_b_D; - logic [C_MANT_FP64:0] Mant_a_D; - logic [C_MANT_FP64:0] Mant_b_D; - - logic [C_EXP_FP64+1:0] Exp_z_D; - logic [C_MANT_FP64+4:0] Mant_z_D; - logic Sign_z_D; - logic Start_S; - logic [C_RM-1:0] RM_dly_S; - logic Div_enable_S; - logic Sqrt_enable_S; - logic Inf_a_S; - logic Inf_b_S; - logic Zero_a_S; - logic Zero_b_S; - logic NaN_a_S; - logic NaN_b_S; - logic SNaN_S; - logic Special_case_SB,Special_case_dly_SB; - - logic Full_precision_S; - logic FP32_S; - logic FP64_S; - logic FP16_S; - logic FP16ALT_S; - - - preprocess_mvp preprocess_U0 - ( - .Clk_CI (Clk_CI ), - .Rst_RBI (Rst_RBI ), - .Div_start_SI (Div_start_SI ), - .Sqrt_start_SI (Sqrt_start_SI ), - .Ready_SI (Ready_SO ), - .Operand_a_DI (Operand_a_DI ), - .Operand_b_DI (Operand_b_DI ), - .RM_SI (RM_SI ), - .Format_sel_SI (Format_sel_SI ), - .Start_SO (Start_S ), - .Exp_a_DO_norm (Exp_a_D ), - .Exp_b_DO_norm (Exp_b_D ), - .Mant_a_DO_norm (Mant_a_D ), - .Mant_b_DO_norm (Mant_b_D ), - .RM_dly_SO (RM_dly_S ), - .Sign_z_DO (Sign_z_D ), - .Inf_a_SO (Inf_a_S ), - .Inf_b_SO (Inf_b_S ), - .Zero_a_SO (Zero_a_S ), - .Zero_b_SO (Zero_b_S ), - .NaN_a_SO (NaN_a_S ), - .NaN_b_SO (NaN_b_S ), - .SNaN_SO (SNaN_S ), - .Special_case_SBO (Special_case_SB ), - .Special_case_dly_SBO (Special_case_dly_SB) - ); - - nrbd_nrsc_mvp nrbd_nrsc_U0 - ( - .Clk_CI (Clk_CI ), - .Rst_RBI (Rst_RBI ), - .Div_start_SI (Div_start_SI ) , - .Sqrt_start_SI (Sqrt_start_SI ), - .Start_SI (Start_S ), - .Kill_SI (Kill_SI ), - .Special_case_SBI (Special_case_SB ), - .Special_case_dly_SBI (Special_case_dly_SB), - .Div_enable_SO (Div_enable_S ), - .Sqrt_enable_SO (Sqrt_enable_S ), - .Precision_ctl_SI (Precision_ctl_SI ), - .Format_sel_SI (Format_sel_SI ), - .Exp_a_DI (Exp_a_D ), - .Exp_b_DI (Exp_b_D ), - .Mant_a_DI (Mant_a_D ), - .Mant_b_DI (Mant_b_D ), - .Full_precision_SO (Full_precision_S ), - .FP32_SO (FP32_S ), - .FP64_SO (FP64_S ), - .FP16_SO (FP16_S ), - .FP16ALT_SO (FP16ALT_S ), - .Ready_SO (Ready_SO ), - .Done_SO (Done_SO ), - .Exp_z_DO (Exp_z_D ), - .Mant_z_DO (Mant_z_D ) - ); - - - norm_div_sqrt_mvp fpu_norm_U0 - ( - .Mant_in_DI (Mant_z_D ), - .Exp_in_DI (Exp_z_D ), - .Sign_in_DI (Sign_z_D ), - .Div_enable_SI (Div_enable_S ), - .Sqrt_enable_SI (Sqrt_enable_S ), - .Inf_a_SI (Inf_a_S ), - .Inf_b_SI (Inf_b_S ), - .Zero_a_SI (Zero_a_S ), - .Zero_b_SI (Zero_b_S ), - .NaN_a_SI (NaN_a_S ), - .NaN_b_SI (NaN_b_S ), - .SNaN_SI (SNaN_S ), - .RM_SI (RM_dly_S ), - .Full_precision_SI (Full_precision_S ), - .FP32_SI (FP32_S ), - .FP64_SI (FP64_S ), - .FP16_SI (FP16_S ), - .FP16ALT_SI (FP16ALT_S ), - .Result_DO (Result_DO ), - .Fflags_SO (Fflags_SO ) //{NV,DZ,OF,UF,NX} - ); - -endmodule diff --git a/rtl/vendor/pulp_platform_fpu_div_sqrt_mvp/hdl/iteration_div_sqrt_mvp.sv b/rtl/vendor/pulp_platform_fpu_div_sqrt_mvp/hdl/iteration_div_sqrt_mvp.sv deleted file mode 100644 index 0c645e6eb..000000000 --- a/rtl/vendor/pulp_platform_fpu_div_sqrt_mvp/hdl/iteration_div_sqrt_mvp.sv +++ /dev/null @@ -1,61 +0,0 @@ -// Copyright 2018 ETH Zurich and University of Bologna. -// Copyright and related rights are licensed under the Solderpad Hardware -// License, Version 0.51 (the “License”); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law -// or agreed to in writing, software, hardware and materials distributed under -// this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR -// CONDITIONS OF ANY KIND, either express or implied. See the License for the -// specific language governing permissions and limitations under the License. -//////////////////////////////////////////////////////////////////////////////// -// Company: IIS @ ETHZ - Federal Institute of Technology // -// // -// Engineers: Lei Li lile@iis.ee.ethz.ch // -// // -// Additional contributions by: // -// // -// // -// // -// Create Date: 12/01/2017 // -// Design Name: FPU // -// Module Name: iteration_div_sqrt_mvp // -// Project Name: Private FPU // -// Language: SystemVerilog // -// // -// Description: iteration unit for div and sqrt // -// // -// // -// Revision: 03/14/2018 // -// For div_sqrt_mvp // -//////////////////////////////////////////////////////////////////////////////// - -module iteration_div_sqrt_mvp -#( - parameter WIDTH=25 -) - (//Input - - input logic [WIDTH-1:0] A_DI, - input logic [WIDTH-1:0] B_DI, - input logic Div_enable_SI, - input logic Div_start_dly_SI, - input logic Sqrt_enable_SI, - input logic [1:0] D_DI, - - output logic [1:0] D_DO, - output logic [WIDTH-1:0] Sum_DO, - output logic Carry_out_DO - ); - - logic D_carry_D; - logic Sqrt_cin_D; - logic Cin_D; - - assign D_DO[0]=~D_DI[0]; - assign D_DO[1]=~(D_DI[1] ^ D_DI[0]); - assign D_carry_D=D_DI[1] | D_DI[0]; - assign Sqrt_cin_D=Sqrt_enable_SI&&D_carry_D; - assign Cin_D=Div_enable_SI?1'b0:Sqrt_cin_D; - assign {Carry_out_DO,Sum_DO}=A_DI+B_DI+Cin_D; - -endmodule diff --git a/rtl/vendor/pulp_platform_fpu_div_sqrt_mvp/hdl/norm_div_sqrt_mvp.sv b/rtl/vendor/pulp_platform_fpu_div_sqrt_mvp/hdl/norm_div_sqrt_mvp.sv deleted file mode 100644 index 590abe969..000000000 --- a/rtl/vendor/pulp_platform_fpu_div_sqrt_mvp/hdl/norm_div_sqrt_mvp.sv +++ /dev/null @@ -1,470 +0,0 @@ -// Copyright 2018 ETH Zurich and University of Bologna. -// Copyright and related rights are licensed under the Solderpad Hardware -// License, Version 0.51 (the “License”); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law -// or agreed to in writing, software, hardware and materials distributed under -// this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR -// CONDITIONS OF ANY KIND, either express or implied. See the License for the -// specific language governing permissions and limitations under the License. - -//////////////////////////////////////////////////////////////////////////////// -// Company: IIS @ ETHZ - Federal Institute of Technology // -// // -// Engineers: Lei Li lile@iis.ee.ethz.ch // -// // -// Additional contributions by: // -// // -// // -// // -// Create Date: 09/03/2018 // -// Design Name: FPU // -// Module Name: norm_div_sqrt_mvp.sv // -// Project Name: // -// Language: SystemVerilog // -// // -// Description: Floating point Normalizer/Rounding unit // -// Since this module is design as a combinatinal logic, it can// -// be added arbinary register stages for different frequency // -// in the wrapper module. // -// // -// // -// // -// Revision Date: 12/04/2018 // -// Lei Li // -// To address some requirements by Stefan // -// // -// // -// // -// // -// // -// // -//////////////////////////////////////////////////////////////////////////////// - -import defs_div_sqrt_mvp::*; - -module norm_div_sqrt_mvp - (//Inputs - input logic [C_MANT_FP64+4:0] Mant_in_DI, // Include the needed 4-bit for rounding and hidden bit - input logic signed [C_EXP_FP64+1:0] Exp_in_DI, - input logic Sign_in_DI, - input logic Div_enable_SI, - input logic Sqrt_enable_SI, - input logic Inf_a_SI, - input logic Inf_b_SI, - input logic Zero_a_SI, - input logic Zero_b_SI, - input logic NaN_a_SI, - input logic NaN_b_SI, - input logic SNaN_SI, - input logic [C_RM-1:0] RM_SI, - input logic Full_precision_SI, - input logic FP32_SI, - input logic FP64_SI, - input logic FP16_SI, - input logic FP16ALT_SI, - //Outputs - output logic [C_EXP_FP64+C_MANT_FP64:0] Result_DO, - output logic [4:0] Fflags_SO //{NV,DZ,OF,UF,NX} - ); - - - logic Sign_res_D; - - logic NV_OP_S; - logic Exp_OF_S; - logic Exp_UF_S; - logic Div_Zero_S; - logic In_Exact_S; - - ///////////////////////////////////////////////////////////////////////////// - // Normalization // - ///////////////////////////////////////////////////////////////////////////// - logic [C_MANT_FP64:0] Mant_res_norm_D; - logic [C_EXP_FP64-1:0] Exp_res_norm_D; - - ///////////////////////////////////////////////////////////////////////////// - // Right shift operations for negtive exponents // - ///////////////////////////////////////////////////////////////////////////// - - logic [C_EXP_FP64+1:0] Exp_Max_RS_FP64_D; - logic [C_EXP_FP32+1:0] Exp_Max_RS_FP32_D; - logic [C_EXP_FP16+1:0] Exp_Max_RS_FP16_D; - logic [C_EXP_FP16ALT+1:0] Exp_Max_RS_FP16ALT_D; - // - assign Exp_Max_RS_FP64_D=Exp_in_DI[C_EXP_FP64:0]+C_MANT_FP64+1; // to check exponent after (C_MANT_FP64+1)-bit >> when Exp_in_DI is negative - assign Exp_Max_RS_FP32_D=Exp_in_DI[C_EXP_FP32:0]+C_MANT_FP32+1; // to check exponent after (C_MANT_FP32+1)-bit >> when Exp_in_DI is negative - assign Exp_Max_RS_FP16_D=Exp_in_DI[C_EXP_FP16:0]+C_MANT_FP16+1; // to check exponent after (C_MANT_FP16+1)-bit >> when Exp_in_DI is negative - assign Exp_Max_RS_FP16ALT_D=Exp_in_DI[C_EXP_FP16ALT:0]+C_MANT_FP16ALT+1; // to check exponent after (C_MANT_FP16ALT+1)-bit >> when Exp_in_DI is negative - logic [C_EXP_FP64+1:0] Num_RS_D; - assign Num_RS_D=~Exp_in_DI+1+1; // How many right shifts(RS) are needed to generate a denormal number? >> is need only when Exp_in_DI is negative - logic [C_MANT_FP64:0] Mant_RS_D; - logic [C_MANT_FP64+4:0] Mant_forsticky_D; - assign {Mant_RS_D,Mant_forsticky_D} ={Mant_in_DI,{(C_MANT_FP64+1){1'b0}} } >>(Num_RS_D); // -// - logic [C_EXP_FP64+1:0] Exp_subOne_D; - assign Exp_subOne_D = Exp_in_DI -1; - - //normalization - logic [1:0] Mant_lower_D; - logic Mant_sticky_bit_D; - logic [C_MANT_FP64+4:0] Mant_forround_D; - - always_comb - begin - - if(NaN_a_SI) // if a is NaN, return NaN - begin - Div_Zero_S=1'b0; - Exp_OF_S=1'b0; - Exp_UF_S=1'b0; - Mant_res_norm_D={1'b0,C_MANT_NAN_FP64}; - Exp_res_norm_D='1; - Mant_forround_D='0; - Sign_res_D=1'b0; - NV_OP_S = SNaN_SI; - end - - else if(NaN_b_SI) //if b is NaN, return NaN - begin - Div_Zero_S=1'b0; - Exp_OF_S=1'b0; - Exp_UF_S=1'b0; - Mant_res_norm_D={1'b0,C_MANT_NAN_FP64}; - Exp_res_norm_D='1; - Mant_forround_D='0; - Sign_res_D=1'b0; - NV_OP_S = SNaN_SI; - end - - else if(Inf_a_SI) - begin - if(Div_enable_SI&&Inf_b_SI) //Inf/Inf, retrurn NaN - begin - Div_Zero_S=1'b0; - Exp_OF_S=1'b0; - Exp_UF_S=1'b0; - Mant_res_norm_D={1'b0,C_MANT_NAN_FP64}; - Exp_res_norm_D='1; - Mant_forround_D='0; - Sign_res_D=1'b0; - NV_OP_S = 1'b1; - end - else if (Sqrt_enable_SI && Sign_in_DI) begin // catch sqrt(-inf) - Div_Zero_S=1'b0; - Exp_OF_S=1'b0; - Exp_UF_S=1'b0; - Mant_res_norm_D={1'b0,C_MANT_NAN_FP64}; - Exp_res_norm_D='1; - Mant_forround_D='0; - Sign_res_D=1'b0; - NV_OP_S = 1'b1; - end else begin - Div_Zero_S=1'b0; - Exp_OF_S=1'b1; - Exp_UF_S=1'b0; - Mant_res_norm_D= '0; - Exp_res_norm_D='1; - Mant_forround_D='0; - Sign_res_D=Sign_in_DI; - NV_OP_S = 1'b0; - end - end - - else if(Div_enable_SI&&Inf_b_SI) - begin - Div_Zero_S=1'b0; - Exp_OF_S=1'b1; - Exp_UF_S=1'b0; - Mant_res_norm_D= '0; - Exp_res_norm_D='0; - Mant_forround_D='0; - Sign_res_D=Sign_in_DI; - NV_OP_S = 1'b0; - end - - else if(Zero_a_SI) - begin - if(Div_enable_SI&&Zero_b_SI) - begin - Div_Zero_S=1'b1; - Exp_OF_S=1'b0; - Exp_UF_S=1'b0; - Mant_res_norm_D={1'b0,C_MANT_NAN_FP64}; - Exp_res_norm_D='1; - Mant_forround_D='0; - Sign_res_D=1'b0; - NV_OP_S = 1'b1; - end - else - begin - Div_Zero_S=1'b0; - Exp_OF_S=1'b0; - Exp_UF_S=1'b0; - Mant_res_norm_D='0; - Exp_res_norm_D='0; - Mant_forround_D='0; - Sign_res_D=Sign_in_DI; - NV_OP_S = 1'b0; - end - end - - else if(Div_enable_SI&&(Zero_b_SI)) //div Zero - begin - Div_Zero_S=1'b1; - Exp_OF_S=1'b0; - Exp_UF_S=1'b0; - Mant_res_norm_D='0; - Exp_res_norm_D='1; - Mant_forround_D='0; - Sign_res_D=Sign_in_DI; - NV_OP_S = 1'b0; - end - - else if(Sign_in_DI&&Sqrt_enable_SI) //sqrt(-a) - begin - Div_Zero_S=1'b0; - Exp_OF_S=1'b0; - Exp_UF_S=1'b0; - Mant_res_norm_D={1'b0,C_MANT_NAN_FP64}; - Exp_res_norm_D='1; - Mant_forround_D='0; - Sign_res_D=1'b0; - NV_OP_S = 1'b1; - end - - else if((Exp_in_DI[C_EXP_FP64:0]=='0)) - begin - if(Mant_in_DI!='0) //Exp=0, Mant!=0, it is denormal - begin - Div_Zero_S=1'b0; - Exp_OF_S=1'b0; - Exp_UF_S=1'b1; - Mant_res_norm_D={1'b0,Mant_in_DI[C_MANT_FP64+4:5]}; - Exp_res_norm_D='0; - Mant_forround_D={Mant_in_DI[4:0],{(C_MANT_FP64){1'b0}} }; - Sign_res_D=Sign_in_DI; - NV_OP_S = 1'b0; - end - else // Zero - begin - Div_Zero_S=1'b0; - Exp_OF_S=1'b0; - Exp_UF_S=1'b0; - Mant_res_norm_D='0; - Exp_res_norm_D='0; - Mant_forround_D='0; - Sign_res_D=Sign_in_DI; - NV_OP_S = 1'b0; - end - end - - else if((Exp_in_DI[C_EXP_FP64:0]==C_EXP_ONE_FP64)&&(~Mant_in_DI[C_MANT_FP64+4])) //denormal - begin - Div_Zero_S=1'b0; - Exp_OF_S=1'b0; - Exp_UF_S=1'b1; - Mant_res_norm_D=Mant_in_DI[C_MANT_FP64+4:4]; - Exp_res_norm_D='0; - Mant_forround_D={Mant_in_DI[3:0],{(C_MANT_FP64+1){1'b0}}}; - Sign_res_D=Sign_in_DI; - NV_OP_S = 1'b0; - end - - else if(Exp_in_DI[C_EXP_FP64+1]) //minus //consider format - begin - Div_Zero_S=1'b0; - Exp_OF_S=1'b0; - Exp_UF_S=1'b1; - Mant_res_norm_D={Mant_RS_D[C_MANT_FP64:0]}; - Exp_res_norm_D='0; - Mant_forround_D={Mant_forsticky_D[C_MANT_FP64+4:0]}; //?? - Sign_res_D=Sign_in_DI; - NV_OP_S = 1'b0; - end - - else if( (Exp_in_DI[C_EXP_FP32]&&FP32_SI) | (Exp_in_DI[C_EXP_FP64]&&FP64_SI) | (Exp_in_DI[C_EXP_FP16]&&FP16_SI) | (Exp_in_DI[C_EXP_FP16ALT]&&FP16ALT_SI) ) //OF - begin - Div_Zero_S=1'b0; - Exp_OF_S=1'b1; - Exp_UF_S=1'b0; - Mant_res_norm_D='0; - Exp_res_norm_D='1; - Mant_forround_D='0; - Sign_res_D=Sign_in_DI; - NV_OP_S = 1'b0; - end - - else if( ((Exp_in_DI[C_EXP_FP32-1:0]=='1)&&FP32_SI) | ((Exp_in_DI[C_EXP_FP64-1:0]=='1)&&FP64_SI) | ((Exp_in_DI[C_EXP_FP16-1:0]=='1)&&FP16_SI) | ((Exp_in_DI[C_EXP_FP16ALT-1:0]=='1)&&FP16ALT_SI) )//255 - begin - if(~Mant_in_DI[C_MANT_FP64+4]) // MSB=0 - begin - Div_Zero_S=1'b0; - Exp_OF_S=1'b0; - Exp_UF_S=1'b0; - Mant_res_norm_D=Mant_in_DI[C_MANT_FP64+3:3]; - Exp_res_norm_D=Exp_subOne_D; - Mant_forround_D={Mant_in_DI[2:0],{(C_MANT_FP64+2){1'b0}}}; - Sign_res_D=Sign_in_DI; - NV_OP_S = 1'b0; - end - else if(Mant_in_DI!='0) //NaN - begin - Div_Zero_S=1'b0; - Exp_OF_S=1'b1; - Exp_UF_S=1'b0; - Mant_res_norm_D= '0; - Exp_res_norm_D='1; - Mant_forround_D='0; - Sign_res_D=Sign_in_DI; - NV_OP_S = 1'b0; - end - else //infinity - begin - Div_Zero_S=1'b0; - Exp_OF_S=1'b1; - Exp_UF_S=1'b0; - Mant_res_norm_D= '0; - Exp_res_norm_D='1; - Mant_forround_D='0; - Sign_res_D=Sign_in_DI; - NV_OP_S = 1'b0; - end - end - - else if(Mant_in_DI[C_MANT_FP64+4]) //normal numbers with 1.XXX - begin - Div_Zero_S=1'b0; - Exp_OF_S=1'b0; - Exp_UF_S=1'b0; - Mant_res_norm_D= Mant_in_DI[C_MANT_FP64+4:4]; - Exp_res_norm_D=Exp_in_DI[C_EXP_FP64-1:0]; - Mant_forround_D={Mant_in_DI[3:0],{(C_MANT_FP64+1){1'b0}}}; - Sign_res_D=Sign_in_DI; - NV_OP_S = 1'b0; - end - - else //normal numbers with 0.1XX - begin - Div_Zero_S=1'b0; - Exp_OF_S=1'b0; - Exp_UF_S=1'b0; - Mant_res_norm_D=Mant_in_DI[C_MANT_FP64+3:3]; - Exp_res_norm_D=Exp_subOne_D; - Mant_forround_D={Mant_in_DI[2:0],{(C_MANT_FP64+2){1'b0}}}; - Sign_res_D=Sign_in_DI; - NV_OP_S = 1'b0; - end - - end - - ///////////////////////////////////////////////////////////////////////////// - // Rounding enable only for full precision (Full_precision_SI==1'b1) // - ///////////////////////////////////////////////////////////////////////////// - - logic [C_MANT_FP64:0] Mant_upper_D; - logic [C_MANT_FP64+1:0] Mant_upperRounded_D; - logic Mant_roundUp_S; - logic Mant_rounded_S; - - always_comb //determine which bits for Mant_lower_D and Mant_sticky_bit_D - begin - if(FP32_SI) - begin - Mant_upper_D = {Mant_res_norm_D[C_MANT_FP64:C_MANT_FP64-C_MANT_FP32], {(C_MANT_FP64-C_MANT_FP32){1'b0}} }; - Mant_lower_D = Mant_res_norm_D[C_MANT_FP64-C_MANT_FP32-1:C_MANT_FP64-C_MANT_FP32-2]; - Mant_sticky_bit_D = | Mant_res_norm_D[C_MANT_FP64-C_MANT_FP32-3:0]; - end - else if(FP64_SI) - begin - Mant_upper_D = Mant_res_norm_D[C_MANT_FP64:0]; - Mant_lower_D = Mant_forround_D[C_MANT_FP64+4:C_MANT_FP64+3]; - Mant_sticky_bit_D = | Mant_forround_D[C_MANT_FP64+3:0]; - end - else if(FP16_SI) - begin - Mant_upper_D = {Mant_res_norm_D[C_MANT_FP64:C_MANT_FP64-C_MANT_FP16], {(C_MANT_FP64-C_MANT_FP16){1'b0}} }; - Mant_lower_D = Mant_res_norm_D[C_MANT_FP64-C_MANT_FP16-1:C_MANT_FP64-C_MANT_FP16-2]; - Mant_sticky_bit_D = | Mant_res_norm_D[C_MANT_FP64-C_MANT_FP16-3:30]; - end - else //FP16ALT - begin - Mant_upper_D = {Mant_res_norm_D[C_MANT_FP64:C_MANT_FP64-C_MANT_FP16ALT], {(C_MANT_FP64-C_MANT_FP16ALT){1'b0}} }; - Mant_lower_D = Mant_res_norm_D[C_MANT_FP64-C_MANT_FP16ALT-1:C_MANT_FP64-C_MANT_FP16ALT-2]; - Mant_sticky_bit_D = | Mant_res_norm_D[C_MANT_FP64-C_MANT_FP16ALT-3:30]; - end - end - - assign Mant_rounded_S = (|(Mant_lower_D))| Mant_sticky_bit_D; - - - - - always_comb //determine whether to round up or not - begin - Mant_roundUp_S = 1'b0; - case (RM_SI) - C_RM_NEAREST : - Mant_roundUp_S = Mant_lower_D[1] && ((Mant_lower_D[0] | Mant_sticky_bit_D )| ( (FP32_SI&&Mant_upper_D[C_MANT_FP64-C_MANT_FP32]) | (FP64_SI&&Mant_upper_D[0]) | (FP16_SI&&Mant_upper_D[C_MANT_FP64-C_MANT_FP16]) | (FP16ALT_SI&&Mant_upper_D[C_MANT_FP64-C_MANT_FP16ALT]) ) ); - C_RM_TRUNC : - Mant_roundUp_S = 0; - C_RM_PLUSINF : - Mant_roundUp_S = Mant_rounded_S & ~Sign_in_DI; - C_RM_MINUSINF: - Mant_roundUp_S = Mant_rounded_S & Sign_in_DI; - default : - Mant_roundUp_S = 0; - endcase // case (RM_DI) - end // always_comb begin - - logic Mant_renorm_S; - logic [C_MANT_FP64:0] Mant_roundUp_Vector_S; // for all the formats - - assign Mant_roundUp_Vector_S={7'h0,(FP16ALT_SI&&Mant_roundUp_S),2'h0,(FP16_SI&&Mant_roundUp_S),12'h0,(FP32_SI&&Mant_roundUp_S),28'h0,(FP64_SI&&Mant_roundUp_S)}; - - - assign Mant_upperRounded_D = Mant_upper_D + Mant_roundUp_Vector_S; - assign Mant_renorm_S = Mant_upperRounded_D[C_MANT_FP64+1]; - - ///////////////////////////////////////////////////////////////////////////// - // Renormalization for Rounding // - ///////////////////////////////////////////////////////////////////////////// - logic [C_MANT_FP64-1:0] Mant_res_round_D; - logic [C_EXP_FP64-1:0] Exp_res_round_D; - - - assign Mant_res_round_D = (Mant_renorm_S)?Mant_upperRounded_D[C_MANT_FP64:1]:Mant_upperRounded_D[C_MANT_FP64-1:0]; // including the process of the hidden bit - assign Exp_res_round_D = Exp_res_norm_D+Mant_renorm_S; - - ///////////////////////////////////////////////////////////////////////////// - // Output Assignments // - ///////////////////////////////////////////////////////////////////////////// - logic [C_MANT_FP64-1:0] Mant_before_format_ctl_D; - logic [C_EXP_FP64-1:0] Exp_before_format_ctl_D; - assign Mant_before_format_ctl_D = Full_precision_SI ? Mant_res_round_D : Mant_res_norm_D; - assign Exp_before_format_ctl_D = Full_precision_SI ? Exp_res_round_D : Exp_res_norm_D; - - always_comb //NaN Boxing - begin // - if(FP32_SI) - begin - Result_DO ={32'hffff_ffff,Sign_res_D,Exp_before_format_ctl_D[C_EXP_FP32-1:0],Mant_before_format_ctl_D[C_MANT_FP64-1:C_MANT_FP64-C_MANT_FP32]}; - end - else if(FP64_SI) - begin - Result_DO ={Sign_res_D,Exp_before_format_ctl_D[C_EXP_FP64-1:0],Mant_before_format_ctl_D[C_MANT_FP64-1:0]}; - end - else if(FP16_SI) - begin - Result_DO ={48'hffff_ffff_ffff,Sign_res_D,Exp_before_format_ctl_D[C_EXP_FP16-1:0],Mant_before_format_ctl_D[C_MANT_FP64-1:C_MANT_FP64-C_MANT_FP16]}; - end - else - begin - Result_DO ={48'hffff_ffff_ffff,Sign_res_D,Exp_before_format_ctl_D[C_EXP_FP16ALT-1:0],Mant_before_format_ctl_D[C_MANT_FP64-1:C_MANT_FP64-C_MANT_FP16ALT]}; - end - end - -assign In_Exact_S = (~Full_precision_SI) | Mant_rounded_S; -assign Fflags_SO = {NV_OP_S,Div_Zero_S,Exp_OF_S,Exp_UF_S,In_Exact_S}; //{NV,DZ,OF,UF,NX} - -endmodule // norm_div_sqrt_mvp diff --git a/rtl/vendor/pulp_platform_fpu_div_sqrt_mvp/hdl/nrbd_nrsc_mvp.sv b/rtl/vendor/pulp_platform_fpu_div_sqrt_mvp/hdl/nrbd_nrsc_mvp.sv deleted file mode 100644 index 62bd147f6..000000000 --- a/rtl/vendor/pulp_platform_fpu_div_sqrt_mvp/hdl/nrbd_nrsc_mvp.sv +++ /dev/null @@ -1,104 +0,0 @@ -// Copyright 2018 ETH Zurich and University of Bologna. -// Copyright and related rights are licensed under the Solderpad Hardware -// License, Version 0.51 (the “License”); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law -// or agreed to in writing, software, hardware and materials distributed under -// this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR -// CONDITIONS OF ANY KIND, either express or implied. See the License for the -// specific language governing permissions and limitations under the License. -//////////////////////////////////////////////////////////////////////////////// -// Company: IIS @ ETHZ - Federal Institute of Technology // -// // -// Engineers: Lei Li lile@iis.ee.ethz.ch // -// // -// Additional contributions by: // -// // -// // -// // -// Create Date: 10/04/2018 // -// Design Name: FPU // -// Module Name: nrbd_nrsc_mvp.sv // -// Project Name: Private FPU // -// Language: SystemVerilog // -// // -// Description: non restroring binary divisior/ square root // -// // -// Revision Date: 12/04/2018 // -// Lei Li // -// To address some requirements by Stefan and add low power // -// control for special cases // -// // -//////////////////////////////////////////////////////////////////////////////// - -import defs_div_sqrt_mvp::*; - -module nrbd_nrsc_mvp - - (//Input - input logic Clk_CI, - input logic Rst_RBI, - input logic Div_start_SI, - input logic Sqrt_start_SI, - input logic Start_SI, - input logic Kill_SI, - input logic Special_case_SBI, - input logic Special_case_dly_SBI, - input logic [C_PC-1:0] Precision_ctl_SI, - input logic [1:0] Format_sel_SI, - input logic [C_MANT_FP64:0] Mant_a_DI, - input logic [C_MANT_FP64:0] Mant_b_DI, - input logic [C_EXP_FP64:0] Exp_a_DI, - input logic [C_EXP_FP64:0] Exp_b_DI, - //output - output logic Div_enable_SO, - output logic Sqrt_enable_SO, - - output logic Full_precision_SO, - output logic FP32_SO, - output logic FP64_SO, - output logic FP16_SO, - output logic FP16ALT_SO, - output logic Ready_SO, - output logic Done_SO, - output logic [C_MANT_FP64+4:0] Mant_z_DO, - output logic [C_EXP_FP64+1:0] Exp_z_DO - ); - - - logic Div_start_dly_S,Sqrt_start_dly_S; - - -control_mvp control_U0 -( .Clk_CI (Clk_CI ), - .Rst_RBI (Rst_RBI ), - .Div_start_SI (Div_start_SI ), - .Sqrt_start_SI (Sqrt_start_SI ), - .Start_SI (Start_SI ), - .Kill_SI (Kill_SI ), - .Special_case_SBI (Special_case_SBI ), - .Special_case_dly_SBI (Special_case_dly_SBI ), - .Precision_ctl_SI (Precision_ctl_SI ), - .Format_sel_SI (Format_sel_SI ), - .Numerator_DI (Mant_a_DI ), - .Exp_num_DI (Exp_a_DI ), - .Denominator_DI (Mant_b_DI ), - .Exp_den_DI (Exp_b_DI ), - .Div_start_dly_SO (Div_start_dly_S ), - .Sqrt_start_dly_SO (Sqrt_start_dly_S ), - .Div_enable_SO (Div_enable_SO ), - .Sqrt_enable_SO (Sqrt_enable_SO ), - .Full_precision_SO (Full_precision_SO ), - .FP32_SO (FP32_SO ), - .FP64_SO (FP64_SO ), - .FP16_SO (FP16_SO ), - .FP16ALT_SO (FP16ALT_SO ), - .Ready_SO (Ready_SO ), - .Done_SO (Done_SO ), - .Mant_result_prenorm_DO (Mant_z_DO ), - .Exp_result_prenorm_DO (Exp_z_DO ) -); - - - -endmodule diff --git a/rtl/vendor/pulp_platform_fpu_div_sqrt_mvp/hdl/preprocess_mvp.sv b/rtl/vendor/pulp_platform_fpu_div_sqrt_mvp/hdl/preprocess_mvp.sv deleted file mode 100644 index 9e0d25f38..000000000 --- a/rtl/vendor/pulp_platform_fpu_div_sqrt_mvp/hdl/preprocess_mvp.sv +++ /dev/null @@ -1,425 +0,0 @@ -// Copyright 2018 ETH Zurich and University of Bologna. -// Copyright and related rights are licensed under the Solderpad Hardware -// License, Version 0.51 (the “License”); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law -// or agreed to in writing, software, hardware and materials distributed under -// this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR -// CONDITIONS OF ANY KIND, either express or implied. See the License for the -// specific language governing permissions and limitations under the License. -//////////////////////////////////////////////////////////////////////////////// -// Company: IIS @ ETHZ - Federal Institute of Technology // -// // -// Engineers: Lei Li //lile@iis.ee.ethz.ch // -// // -// Additional contributions by: // -// // -// // -// // -// Create Date: 01/03/2018 // -// Design Name: FPU // -// Module Name: preprocess_mvp.sv // -// Project Name: Private FPU // -// Language: SystemVerilog // -// // -// Description: decode and data preparation // -// // -// Revision Date: 12/04/2018 // -// Lei Li // -// To address some requirements by Stefan and add low power // -// control for special cases // -// // -// // -//////////////////////////////////////////////////////////////////////////////// - -import defs_div_sqrt_mvp::*; - -module preprocess_mvp - ( - input logic Clk_CI, - input logic Rst_RBI, - input logic Div_start_SI, - input logic Sqrt_start_SI, - input logic Ready_SI, - //Input Operands - input logic [C_OP_FP64-1:0] Operand_a_DI, - input logic [C_OP_FP64-1:0] Operand_b_DI, - input logic [C_RM-1:0] RM_SI, //Rounding Mode - input logic [C_FS-1:0] Format_sel_SI, // Format Selection - - // to control - output logic Start_SO, - output logic [C_EXP_FP64:0] Exp_a_DO_norm, - output logic [C_EXP_FP64:0] Exp_b_DO_norm, - output logic [C_MANT_FP64:0] Mant_a_DO_norm, - output logic [C_MANT_FP64:0] Mant_b_DO_norm, - - output logic [C_RM-1:0] RM_dly_SO, - - output logic Sign_z_DO, - output logic Inf_a_SO, - output logic Inf_b_SO, - output logic Zero_a_SO, - output logic Zero_b_SO, - output logic NaN_a_SO, - output logic NaN_b_SO, - output logic SNaN_SO, - output logic Special_case_SBO, - output logic Special_case_dly_SBO - ); - - //Hidden Bits - logic Hb_a_D; - logic Hb_b_D; - - logic [C_EXP_FP64-1:0] Exp_a_D; - logic [C_EXP_FP64-1:0] Exp_b_D; - logic [C_MANT_FP64-1:0] Mant_a_NonH_D; - logic [C_MANT_FP64-1:0] Mant_b_NonH_D; - logic [C_MANT_FP64:0] Mant_a_D; - logic [C_MANT_FP64:0] Mant_b_D; - - ///////////////////////////////////////////////////////////////////////////// - // Disassemble operands - ///////////////////////////////////////////////////////////////////////////// - logic Sign_a_D,Sign_b_D; - logic Start_S; - - always_comb - begin - case(Format_sel_SI) - 2'b00: - begin - Sign_a_D = Operand_a_DI[C_OP_FP32-1]; - Sign_b_D = Operand_b_DI[C_OP_FP32-1]; - Exp_a_D = {3'h0, Operand_a_DI[C_OP_FP32-2:C_MANT_FP32]}; - Exp_b_D = {3'h0, Operand_b_DI[C_OP_FP32-2:C_MANT_FP32]}; - Mant_a_NonH_D = {Operand_a_DI[C_MANT_FP32-1:0],29'h0}; - Mant_b_NonH_D = {Operand_b_DI[C_MANT_FP32-1:0],29'h0}; - end - 2'b01: - begin - Sign_a_D = Operand_a_DI[C_OP_FP64-1]; - Sign_b_D = Operand_b_DI[C_OP_FP64-1]; - Exp_a_D = Operand_a_DI[C_OP_FP64-2:C_MANT_FP64]; - Exp_b_D = Operand_b_DI[C_OP_FP64-2:C_MANT_FP64]; - Mant_a_NonH_D = Operand_a_DI[C_MANT_FP64-1:0]; - Mant_b_NonH_D = Operand_b_DI[C_MANT_FP64-1:0]; - end - 2'b10: - begin - Sign_a_D = Operand_a_DI[C_OP_FP16-1]; - Sign_b_D = Operand_b_DI[C_OP_FP16-1]; - Exp_a_D = {6'h00, Operand_a_DI[C_OP_FP16-2:C_MANT_FP16]}; - Exp_b_D = {6'h00, Operand_b_DI[C_OP_FP16-2:C_MANT_FP16]}; - Mant_a_NonH_D = {Operand_a_DI[C_MANT_FP16-1:0],42'h0}; - Mant_b_NonH_D = {Operand_b_DI[C_MANT_FP16-1:0],42'h0}; - end - 2'b11: - begin - Sign_a_D = Operand_a_DI[C_OP_FP16ALT-1]; - Sign_b_D = Operand_b_DI[C_OP_FP16ALT-1]; - Exp_a_D = {3'h0, Operand_a_DI[C_OP_FP16ALT-2:C_MANT_FP16ALT]}; - Exp_b_D = {3'h0, Operand_b_DI[C_OP_FP16ALT-2:C_MANT_FP16ALT]}; - Mant_a_NonH_D = {Operand_a_DI[C_MANT_FP16ALT-1:0],45'h0}; - Mant_b_NonH_D = {Operand_b_DI[C_MANT_FP16ALT-1:0],45'h0}; - end - endcase - end - - - assign Mant_a_D = {Hb_a_D,Mant_a_NonH_D}; - assign Mant_b_D = {Hb_b_D,Mant_b_NonH_D}; - - assign Hb_a_D = | Exp_a_D; // hidden bit - assign Hb_b_D = | Exp_b_D; // hidden bit - - assign Start_S= Div_start_SI | Sqrt_start_SI; - - - - ///////////////////////////////////////////////////////////////////////////// - // preliminary checks for infinite/zero/NaN operands // - ///////////////////////////////////////////////////////////////////////////// - - logic Mant_a_prenorm_zero_S; - logic Mant_b_prenorm_zero_S; - - logic Exp_a_prenorm_zero_S; - logic Exp_b_prenorm_zero_S; - assign Exp_a_prenorm_zero_S = ~Hb_a_D; - assign Exp_b_prenorm_zero_S = ~Hb_b_D; - - logic Exp_a_prenorm_Inf_NaN_S; - logic Exp_b_prenorm_Inf_NaN_S; - - logic Mant_a_prenorm_QNaN_S; - logic Mant_a_prenorm_SNaN_S; - logic Mant_b_prenorm_QNaN_S; - logic Mant_b_prenorm_SNaN_S; - - assign Mant_a_prenorm_QNaN_S=Mant_a_NonH_D[C_MANT_FP64-1]&&(~(|Mant_a_NonH_D[C_MANT_FP64-2:0])); - assign Mant_a_prenorm_SNaN_S=(~Mant_a_NonH_D[C_MANT_FP64-1])&&((|Mant_a_NonH_D[C_MANT_FP64-2:0])); - assign Mant_b_prenorm_QNaN_S=Mant_b_NonH_D[C_MANT_FP64-1]&&(~(|Mant_b_NonH_D[C_MANT_FP64-2:0])); - assign Mant_b_prenorm_SNaN_S=(~Mant_b_NonH_D[C_MANT_FP64-1])&&((|Mant_b_NonH_D[C_MANT_FP64-2:0])); - - always_comb - begin - case(Format_sel_SI) - 2'b00: - begin - Mant_a_prenorm_zero_S=(Operand_a_DI[C_MANT_FP32-1:0] == C_MANT_ZERO_FP32); - Mant_b_prenorm_zero_S=(Operand_b_DI[C_MANT_FP32-1:0] == C_MANT_ZERO_FP32); - Exp_a_prenorm_Inf_NaN_S=(Operand_a_DI[C_OP_FP32-2:C_MANT_FP32] == C_EXP_INF_FP32); - Exp_b_prenorm_Inf_NaN_S=(Operand_b_DI[C_OP_FP32-2:C_MANT_FP32] == C_EXP_INF_FP32); - end - 2'b01: - begin - Mant_a_prenorm_zero_S=(Operand_a_DI[C_MANT_FP64-1:0] == C_MANT_ZERO_FP64); - Mant_b_prenorm_zero_S=(Operand_b_DI[C_MANT_FP64-1:0] == C_MANT_ZERO_FP64); - Exp_a_prenorm_Inf_NaN_S=(Operand_a_DI[C_OP_FP64-2:C_MANT_FP64] == C_EXP_INF_FP64); - Exp_b_prenorm_Inf_NaN_S=(Operand_b_DI[C_OP_FP64-2:C_MANT_FP64] == C_EXP_INF_FP64); - end - 2'b10: - begin - Mant_a_prenorm_zero_S=(Operand_a_DI[C_MANT_FP16-1:0] == C_MANT_ZERO_FP16); - Mant_b_prenorm_zero_S=(Operand_b_DI[C_MANT_FP16-1:0] == C_MANT_ZERO_FP16); - Exp_a_prenorm_Inf_NaN_S=(Operand_a_DI[C_OP_FP16-2:C_MANT_FP16] == C_EXP_INF_FP16); - Exp_b_prenorm_Inf_NaN_S=(Operand_b_DI[C_OP_FP16-2:C_MANT_FP16] == C_EXP_INF_FP16); - end - 2'b11: - begin - Mant_a_prenorm_zero_S=(Operand_a_DI[C_MANT_FP16ALT-1:0] == C_MANT_ZERO_FP16ALT); - Mant_b_prenorm_zero_S=(Operand_b_DI[C_MANT_FP16ALT-1:0] == C_MANT_ZERO_FP16ALT); - Exp_a_prenorm_Inf_NaN_S=(Operand_a_DI[C_OP_FP16ALT-2:C_MANT_FP16ALT] == C_EXP_INF_FP16ALT); - Exp_b_prenorm_Inf_NaN_S=(Operand_b_DI[C_OP_FP16ALT-2:C_MANT_FP16ALT] == C_EXP_INF_FP16ALT); - end - endcase - end - - - - - logic Zero_a_SN,Zero_a_SP; - logic Zero_b_SN,Zero_b_SP; - logic Inf_a_SN,Inf_a_SP; - logic Inf_b_SN,Inf_b_SP; - logic NaN_a_SN,NaN_a_SP; - logic NaN_b_SN,NaN_b_SP; - logic SNaN_SN,SNaN_SP; - - assign Zero_a_SN = (Start_S&&Ready_SI)?(Exp_a_prenorm_zero_S&&Mant_a_prenorm_zero_S):Zero_a_SP; - assign Zero_b_SN = (Start_S&&Ready_SI)?(Exp_b_prenorm_zero_S&&Mant_b_prenorm_zero_S):Zero_b_SP; - assign Inf_a_SN = (Start_S&&Ready_SI)?(Exp_a_prenorm_Inf_NaN_S&&Mant_a_prenorm_zero_S):Inf_a_SP; - assign Inf_b_SN = (Start_S&&Ready_SI)?(Exp_b_prenorm_Inf_NaN_S&&Mant_b_prenorm_zero_S):Inf_b_SP; - assign NaN_a_SN = (Start_S&&Ready_SI)?(Exp_a_prenorm_Inf_NaN_S&&(~Mant_a_prenorm_zero_S)):NaN_a_SP; - assign NaN_b_SN = (Start_S&&Ready_SI)?(Exp_b_prenorm_Inf_NaN_S&&(~Mant_b_prenorm_zero_S)):NaN_b_SP; - assign SNaN_SN = (Start_S&&Ready_SI) ? ((Mant_a_prenorm_SNaN_S&&NaN_a_SN) | (Mant_b_prenorm_SNaN_S&&NaN_b_SN)) : SNaN_SP; - - always_ff @(posedge Clk_CI, negedge Rst_RBI) - begin - if(~Rst_RBI) - begin - Zero_a_SP <='0; - Zero_b_SP <='0; - Inf_a_SP <='0; - Inf_b_SP <='0; - NaN_a_SP <='0; - NaN_b_SP <='0; - SNaN_SP <= '0; - end - else - begin - Inf_a_SP <=Inf_a_SN; - Inf_b_SP <=Inf_b_SN; - Zero_a_SP <=Zero_a_SN; - Zero_b_SP <=Zero_b_SN; - NaN_a_SP <=NaN_a_SN; - NaN_b_SP <=NaN_b_SN; - SNaN_SP <= SNaN_SN; - end - end - - ///////////////////////////////////////////////////////////////////////////// - // Low power control - ///////////////////////////////////////////////////////////////////////////// - - assign Special_case_SBO=(~{(Div_start_SI)?(Zero_a_SN | Zero_b_SN | Inf_a_SN | Inf_b_SN | NaN_a_SN | NaN_b_SN): (Zero_a_SN | Inf_a_SN | NaN_a_SN | Sign_a_D) })&&(Start_S&&Ready_SI); - - - always_ff @(posedge Clk_CI, negedge Rst_RBI) - begin - if(~Rst_RBI) - begin - Special_case_dly_SBO <= '0; - end - else if((Start_S&&Ready_SI)) - begin - Special_case_dly_SBO <= Special_case_SBO; - end - else if(Special_case_dly_SBO) - begin - Special_case_dly_SBO <= 1'b1; - end - else - begin - Special_case_dly_SBO <= '0; - end - end - - ///////////////////////////////////////////////////////////////////////////// - // Delay sign for normalization and round // - ///////////////////////////////////////////////////////////////////////////// - - logic Sign_z_DN; - logic Sign_z_DP; - - always_comb - begin - if(Div_start_SI&&Ready_SI) - Sign_z_DN = Sign_a_D ^ Sign_b_D; - else if(Sqrt_start_SI&&Ready_SI) - Sign_z_DN = Sign_a_D; - else - Sign_z_DN = Sign_z_DP; - end - - always_ff @(posedge Clk_CI, negedge Rst_RBI) - begin - if(~Rst_RBI) - begin - Sign_z_DP <= '0; - end - else - begin - Sign_z_DP <= Sign_z_DN; - end - end - - logic [C_RM-1:0] RM_DN; - logic [C_RM-1:0] RM_DP; - - always_comb - begin - if(Start_S&&Ready_SI) - RM_DN = RM_SI; - else - RM_DN = RM_DP; - end - - always_ff @(posedge Clk_CI, negedge Rst_RBI) - begin - if(~Rst_RBI) - begin - RM_DP <= '0; - end - else - begin - RM_DP <= RM_DN; - end - end - assign RM_dly_SO = RM_DP; - - logic [5:0] Mant_leadingOne_a, Mant_leadingOne_b; - logic Mant_zero_S_a,Mant_zero_S_b; - - lzc #( - .WIDTH ( C_MANT_FP64+1 ), - .MODE ( 1 ) - ) LOD_Ua ( - .in_i ( Mant_a_D ), - .cnt_o ( Mant_leadingOne_a ), - .empty_o ( Mant_zero_S_a ) - ); - - logic [C_MANT_FP64:0] Mant_a_norm_DN,Mant_a_norm_DP; - - assign Mant_a_norm_DN = ((Start_S&&Ready_SI))?(Mant_a_D<<(Mant_leadingOne_a)):Mant_a_norm_DP; - - always_ff @(posedge Clk_CI, negedge Rst_RBI) - begin - if(~Rst_RBI) - begin - Mant_a_norm_DP <= '0; - end - else - begin - Mant_a_norm_DP<=Mant_a_norm_DN; - end - end - - logic [C_EXP_FP64:0] Exp_a_norm_DN,Exp_a_norm_DP; - assign Exp_a_norm_DN = ((Start_S&&Ready_SI))?(Exp_a_D-Mant_leadingOne_a+(|Mant_leadingOne_a)):Exp_a_norm_DP; //Covering the process of denormal numbers - - always_ff @(posedge Clk_CI, negedge Rst_RBI) - begin - if(~Rst_RBI) - begin - Exp_a_norm_DP <= '0; - end - else - begin - Exp_a_norm_DP<=Exp_a_norm_DN; - end - end - - lzc #( - .WIDTH ( C_MANT_FP64+1 ), - .MODE ( 1 ) - ) LOD_Ub ( - .in_i ( Mant_b_D ), - .cnt_o ( Mant_leadingOne_b ), - .empty_o ( Mant_zero_S_b ) - ); - - - logic [C_MANT_FP64:0] Mant_b_norm_DN,Mant_b_norm_DP; - - assign Mant_b_norm_DN = ((Start_S&&Ready_SI))?(Mant_b_D<<(Mant_leadingOne_b)):Mant_b_norm_DP; - - always_ff @(posedge Clk_CI, negedge Rst_RBI) - begin - if(~Rst_RBI) - begin - Mant_b_norm_DP <= '0; - end - else - begin - Mant_b_norm_DP<=Mant_b_norm_DN; - end - end - - logic [C_EXP_FP64:0] Exp_b_norm_DN,Exp_b_norm_DP; - assign Exp_b_norm_DN = ((Start_S&&Ready_SI))?(Exp_b_D-Mant_leadingOne_b+(|Mant_leadingOne_b)):Exp_b_norm_DP; //Covering the process of denormal numbers - - always_ff @(posedge Clk_CI, negedge Rst_RBI) - begin - if(~Rst_RBI) - begin - Exp_b_norm_DP <= '0; - end - else - begin - Exp_b_norm_DP<=Exp_b_norm_DN; - end - end - - ///////////////////////////////////////////////////////////////////////////// - // Output assignments // - ///////////////////////////////////////////////////////////////////////////// - - assign Start_SO=Start_S; - assign Exp_a_DO_norm=Exp_a_norm_DP; - assign Exp_b_DO_norm=Exp_b_norm_DP; - assign Mant_a_DO_norm=Mant_a_norm_DP; - assign Mant_b_DO_norm=Mant_b_norm_DP; - assign Sign_z_DO=Sign_z_DP; - assign Inf_a_SO=Inf_a_SP; - assign Inf_b_SO=Inf_b_SP; - assign Zero_a_SO=Zero_a_SP; - assign Zero_b_SO=Zero_b_SP; - assign NaN_a_SO=NaN_a_SP; - assign NaN_b_SO=NaN_b_SP; - assign SNaN_SO=SNaN_SP; - -endmodule diff --git a/scripts/formal/Makefile b/scripts/formal/Makefile new file mode 100644 index 000000000..bff46da6f --- /dev/null +++ b/scripts/formal/Makefile @@ -0,0 +1,54 @@ +# Copyright 2024 Dolphin Design +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +# +# Licensed under the Solderpad Hardware License v 2.1 (the "License"); +# you may not use this file except in compliance with the License, or, +# at your option, the Apache License version 2.0. +# You may obtain a copy of the License at +# +# https://solderpad.org/licenses/SHL-2.1/ +# +# Unless required by applicable law or agreed to in writing, any work +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +################################################################################## +# # +# Contributors: Yoann Pruvost, Dolphin Design # +# # +# Description: Makefile for CV32E40P Formal code analysis # +# # +################################################################################## + +export DESIGN_RTL_DIR = ../../rtl + +create_lib: + rm -rf work + vlib work + +compile_design: create_lib + vlog -sv -f ../../cv32e40p_fpu_manifest.flist + vlog -sv -mfcu -cuname cv32e40p_bind -f cv32e40p_formal.flist + +compile_design_pulp: create_lib + vlog -sv +define+PULP -f ../../cv32e40p_fpu_manifest.flist + vlog -sv +define+PULP -mfcu -cuname cv32e40p_bind -f cv32e40p_formal.flist + +compile_design_pulp_f0: create_lib + vlog -sv +define+PULP_F0 -f ../../cv32e40p_fpu_manifest.flist + vlog -sv +define+PULP_F0 -mfcu -cuname cv32e40p_bind -f cv32e40p_formal.flist + +run: compile_design + qverify -c -do formal.do + +run_pulp: compile_design_pulp + qverify -c -do formal.do + +run_pulp_F0: compile_design_pulp_f0 + qverify -c -do formal.do + +clean: + qverify_clean + rm -rf work \ No newline at end of file diff --git a/scripts/formal/README.md b/scripts/formal/README.md new file mode 100644 index 000000000..aa91fab6a --- /dev/null +++ b/scripts/formal/README.md @@ -0,0 +1,24 @@ +## CV32E40P Formal + + This folder contains the source and scripts used in the effort to justify waived code coverage holes using formal tools. + + Disclaimer: This has been developped and tested with Siemens Questa formal and the Makefile only support this tool. Porting to other tools should be straightforward as all source files are standard sva. + +### Introduction + To assist code coverage analysis we formally proved that some code was in our case unreachable. Each assertion correspond to one coverage holes. We tried to keep the constraints as minimal as possible. The only constraints we are using are: + - OBI protocol constraints on both instructions and data interfaces + - Disabling scan + + +### How to use + +Inside this folder, with ```vlog``` and ```qverify``` available in your PATH, run one of the following command. + +| Command | Description | +|-----------------|-----------------------------------------------| +|make run | Run default config (no corev_pulp, no FPU) | +|make run_pulp | Run config corev_pulp withou FPU | +|make run_pulp_F0 | Run config corev_pulp with FPU with latency 0 | +|make clean | Remove all temporary file | + +All runs are in batch. At the end of the run, use ```qverify ``` to open the results in GUI. \ No newline at end of file diff --git a/scripts/formal/cv32e40p_formal.flist b/scripts/formal/cv32e40p_formal.flist new file mode 100644 index 000000000..e3c5f1f2a --- /dev/null +++ b/scripts/formal/cv32e40p_formal.flist @@ -0,0 +1,33 @@ +// Copyright 2024 Dolphin Design +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the "License"); +// you may not use this file except in compliance with the License, or, +// at your option, the Apache License version 2.0. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +//////////////////////////////////////////////////////////////////////////////////// +// // +// Contributors: Yoann Pruvost, Dolphin Design // +// // +// Description: Filelist for CV32E40P formal code analysis // +// // +//////////////////////////////////////////////////////////////////////////////////// + ++incdir+./src +src/insn_assert.sv +src/data_assert.sv +src/cv32e40p_assert.sv +src/cv32e40p_ID_assert.sv +src/cv32e40p_EX_assert.sv +src/fpnew_divsqrt_th_32_assert.sv +src/cv32e40p_formal_top.sv +src/cv32e40p_bind.sv \ No newline at end of file diff --git a/scripts/formal/formal.do b/scripts/formal/formal.do new file mode 100644 index 000000000..8e0be6031 --- /dev/null +++ b/scripts/formal/formal.do @@ -0,0 +1,37 @@ +// Copyright 2024 Dolphin Design +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the "License"); +// you may not use this file except in compliance with the License, or, +// at your option, the Apache License version 2.0. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +//////////////////////////////////////////////////////////////////////////////////// +// // +// Contributors: Yoann Pruvost, Dolphin Design // +// // +// Description: Formal script for CV32E40P // +// // +//////////////////////////////////////////////////////////////////////////////////// + +set top cv32e40p_formal_top + +#netlist clock clk_i -period 50 + +#netlist constraint rst_ni -value 1'b1 -after_init + +#netlist port domain i_lint_grnt -clock i_clk + +formal compile -d cv32e40p_formal_top -cuname cv32e40p_bind + +formal verify -timeout 100m -jobs 4 -sanity_waveforms + +#exit diff --git a/scripts/formal/src/cv32e40p_EX_assert.sv b/scripts/formal/src/cv32e40p_EX_assert.sv new file mode 100644 index 000000000..6a04b7629 --- /dev/null +++ b/scripts/formal/src/cv32e40p_EX_assert.sv @@ -0,0 +1,74 @@ +// Copyright 2024 Dolphin Design +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the "License"); +// you may not use this file except in compliance with the License, or, +// at your option, the Apache License version 2.0. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +//////////////////////////////////////////////////////////////////////////////////// +// // +// Contributors: Yoann Pruvost, Dolphin Design // +// // +// Description: Assertion for unreachable code in CV32E40P EX stage // +// // +//////////////////////////////////////////////////////////////////////////////////// + +module cv32e40p_EX_assert import cv32e40p_pkg::*; +( + input logic clk_i, + input logic rst_ni, + + input logic apu_valid , + input logic apu_singlecycle , + input logic apu_multicycle , + input logic regfile_alu_we_i, + input logic apu_en_i , + input logic regfile_we_lsu , + input logic apu_rvalid_i , + input logic apu_rvalid_q , + + input logic data_misaligned_i , + input logic data_misaligned_ex_i , + input logic data_req_i , + input logic data_rvalid_i , + input logic mulh_active , + input mul_opcode_e mult_operator_i , + input logic [ 1:0] ctrl_transfer_insn_in_dec_i, + input logic apu_read_dep_for_jalr_o +); + + property unreachable_ex_211; + @(posedge clk_i) disable iff(!rst_ni) + (apu_valid & (apu_singlecycle | apu_multicycle)) |-> !(apu_en_i & regfile_alu_we_i); + endproperty + + property unreachable_ex_237; + @(posedge clk_i) disable iff(!rst_ni) + regfile_we_lsu |-> !(~apu_valid & (!apu_singlecycle & !apu_multicycle)); + endproperty + + property unreachable_ex_387; + @(posedge clk_i) disable iff(!rst_ni) + ((apu_rvalid_i && apu_multicycle) && ~(((ctrl_transfer_insn_in_dec_i == 2) && regfile_alu_we_i) && ~apu_read_dep_for_jalr_o) && ~((data_misaligned_i || data_misaligned_ex_i) || ((data_req_i || data_rvalid_i) && regfile_alu_we_i)) && mulh_active)|-> mult_operator_i == MUL_H; + endproperty + + property unreachable_ex_396; + @(posedge clk_i) disable iff(!rst_ni) + (apu_rvalid_q && ~(( ~apu_read_dep_for_jalr_o && (ctrl_transfer_insn_in_dec_i==2)) && regfile_alu_we_i) && ~((data_misaligned_i || data_misaligned_ex_i) || ((data_req_i || data_rvalid_i) && regfile_alu_we_i)) && mulh_active) |-> mult_operator_i == MUL_H; + endproperty + + assert_unreachable_ex_211: assert property(unreachable_ex_211); + assert_unreachable_ex_237: assert property(unreachable_ex_237); + assert_unreachable_ex_387: assert property(unreachable_ex_387); + assert_unreachable_ex_396: assert property(unreachable_ex_396); + +endmodule \ No newline at end of file diff --git a/scripts/formal/src/cv32e40p_ID_assert.sv b/scripts/formal/src/cv32e40p_ID_assert.sv new file mode 100644 index 000000000..1a6b58cf3 --- /dev/null +++ b/scripts/formal/src/cv32e40p_ID_assert.sv @@ -0,0 +1,46 @@ +// Copyright 2024 Dolphin Design +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the "License"); +// you may not use this file except in compliance with the License, or, +// at your option, the Apache License version 2.0. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +//////////////////////////////////////////////////////////////////////////////////// +// // +// Contributors: Yoann Pruvost, Dolphin Design // +// // +// Description: Assertion for unreachable code in CV32E40P ID stage // +// // +//////////////////////////////////////////////////////////////////////////////////// + +module cv32e40p_ID_assert import cv32e40p_pkg::*; +( + input logic clk_i, + input logic rst_ni, + + input logic [31:0] instr_rdata_i, + input logic is_compressed_id_i, + + input logic [ 2:0] alu_op_a_mux_sel, + input logic [ 2:0] alu_op_b_mux_sel, + input logic [ 1:0] alu_op_c_mux_sel, + input logic alu_bmask_b_mux_sel, + input logic [ 1:0] ctrl_transfer_target_mux_sel +); + + property unreachable_id_872; + @(posedge clk_i) disable iff(!rst_ni) + (alu_op_c_mux_sel == OP_C_REGC_OR_FWD) && (~(alu_op_b_mux_sel == OP_B_BMASK) && ((alu_op_a_mux_sel != OP_A_REGC_OR_FWD) && (ctrl_transfer_target_mux_sel != JT_JALR)) && ~alu_bmask_b_mux_sel) |-> alu_op_b_mux_sel == OP_B_IMM; + endproperty + + assert_unreachable_id_872: assert property(unreachable_id_872); +endmodule \ No newline at end of file diff --git a/scripts/formal/src/cv32e40p_assert.sv b/scripts/formal/src/cv32e40p_assert.sv new file mode 100644 index 000000000..610ad3940 --- /dev/null +++ b/scripts/formal/src/cv32e40p_assert.sv @@ -0,0 +1,124 @@ +// Copyright 2024 Dolphin Design +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the "License"); +// you may not use this file except in compliance with the License, or, +// at your option, the Apache License version 2.0. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +//////////////////////////////////////////////////////////////////////////////////// +// // +// Contributors: Yoann Pruvost, Dolphin Design // +// Pascal Gouedo, Dolphin Design // +// // +// Description: GLobal assume and assert for CV32E40P formal code analysis // +// // +//////////////////////////////////////////////////////////////////////////////////// + + +module cv32e40p_assert import cv32e40p_pkg::*; +( + input logic clk_i, + input logic rst_ni, + input logic scan_cg_en_i, + + input logic [31:0] boot_addr_i, + input logic [31:0] mtvec_addr_i, + input logic [31:0] hart_id_i, + input logic [31:0] dm_halt_addr_i, + input logic [31:0] dm_exception_addr_i, + + input logic [1:0] data_type_ex_i, + + input logic [31:0] pc_id_i, + + // Taken from controller + input ctrl_state_e ctrl_fsm_cs, + input logic is_hwlp_body, + input logic hwlp_end0_eq_pc, + input logic hwlp_counter0_gt_1, + input logic hwlp_end1_eq_pc, + input logic hwlp_counter1_gt_1, + input logic jump_done_q +); + import cv32e40p_tracer_pkg::*; + + /********** + * Assume * + **********/ + property no_scan; + @(posedge clk_i) disable iff(!rst_ni) + scan_cg_en_i == '0; + endproperty + + property hart_id_0; + @(posedge clk_i) disable iff(!rst_ni) + hart_id_i == '0; + endproperty + + property aligned_boot_address; + @(posedge clk_i) disable iff(!rst_ni) + boot_addr_i == 32'h1000_0000; + endproperty + + property aligned_mtvec_address; + @(posedge clk_i) disable iff(!rst_ni) + mtvec_addr_i == 32'h2000_0000; + endproperty + + property aligned_halt_address; + @(posedge clk_i) disable iff(!rst_ni) + dm_halt_addr_i == 32'h3000_0000; + endproperty + + property aligned_exception_address; + @(posedge clk_i) disable iff(!rst_ni) + dm_exception_addr_i == 32'h4000_0000; + endproperty + + /********** + * Assert * + **********/ + property data_type_ex_never_11; + @(posedge clk_i) disable iff(!rst_ni) + data_type_ex_i != 2'b11; + endproperty + + property never_jump_done_q_when_hwlp_body_and_hwlp_end0_eq_pc_and_hwlp_counter0_gt_1; + @(posedge clk_i) disable iff(!rst_ni) + (ctrl_fsm_cs == DECODE) & is_hwlp_body & hwlp_end0_eq_pc & hwlp_counter0_gt_1 |-> ~jump_done_q; + endproperty + + property never_ret_from_int_ecall_ebreak_exceptions_on_HWLoop1_last_inst_with_HWLoop1_counter_not_gt1; + @(posedge clk_i) disable iff(!rst_ni) + (ctrl_fsm_cs == DECODE) & is_hwlp_body |-> ~(hwlp_end1_eq_pc & hwlp_counter1_gt_1); + endproperty + + property pc_id_aligned; + @(posedge clk_i) disable iff(!rst_ni) + pc_id_i[2:0] != 2'b00; + endproperty + + + + assume_no_scan: assume property(no_scan); + // assume_hart_id_0: assume property(hart_id_0); + // assume_aligned_boot_address: assume property(aligned_boot_address); + // asuume_aligned_mtvec_address: assume property(aligned_mtvec_address); + // assume_aligned_halt_address: assume property(aligned_halt_address); + // assume_aligned_exception_address: assume property(aligned_exception_address); + + assert_data_type_ex_never_11: assert property(data_type_ex_never_11); + // assert_never_jump_done_q_when_hwlp_body_and_hwlp_end0_eq_pc_and_hwlp_counter0_gt_1: assert property(never_jump_done_q_when_hwlp_body_and_hwlp_end0_eq_pc_and_hwlp_counter0_gt_1); + // assert_never_ret_from_int_ecall_ebreak_exceptions_on_HWLoop1_last_inst_with_HWLoop1_counter_not_gt1: assert property(never_ret_from_int_ecall_ebreak_exceptions_on_HWLoop1_last_inst_with_HWLoop1_counter_not_gt1); + // assert_pc_id_aligned: assert property(pc_id_aligned); + +endmodule \ No newline at end of file diff --git a/scripts/formal/src/cv32e40p_bind.sv b/scripts/formal/src/cv32e40p_bind.sv new file mode 100644 index 000000000..38d51941a --- /dev/null +++ b/scripts/formal/src/cv32e40p_bind.sv @@ -0,0 +1,117 @@ +// Copyright 2024 Dolphin Design +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the "License"); +// you may not use this file except in compliance with the License, or, +// at your option, the Apache License version 2.0. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +//////////////////////////////////////////////////////////////////////////////////// +// // +// Contributors: Yoann Pruvost, Dolphin Design // +// Pascal Gouedo, Dolphin Design // +// // +// Description: CV32E40P binding for formal code analysis // +// // +//////////////////////////////////////////////////////////////////////////////////// + +bind cv32e40p_formal_top insn_assert u_insn_assert ( + .clk_i(clk_i), + .rst_ni(rst_ni), + + .instr_req_o (instr_req_o), + .instr_gnt_i (instr_gnt_i), + .instr_rvalid_i(instr_rvalid_i), + .instr_addr_o (instr_addr_o), + .instr_rdata_i (instr_rdata_i) +); + +bind cv32e40p_formal_top data_assert u_data_assert ( + .clk_i(clk_i), + .rst_ni(rst_ni), + + .data_req_o (data_req_o ), + .data_gnt_i (data_gnt_i ), + .data_rvalid_i(data_rvalid_i), + .data_we_o (data_we_o ), + .data_be_o (data_be_o ), + .data_addr_o (data_addr_o ), + .data_wdata_o (data_wdata_o ), + .data_rdata_i (data_rdata_i ) +); + +bind cv32e40p_formal_top cv32e40p_assert u_cv32e40p_assert ( + .clk_i(clk_i), + .rst_ni(rst_ni), + .scan_cg_en_i(scan_cg_en_i), + + .boot_addr_i (boot_addr_i ), + .mtvec_addr_i (mtvec_addr_i ), + .hart_id_i (hart_id_i ), + .dm_halt_addr_i (dm_halt_addr_i ), + .dm_exception_addr_i(dm_exception_addr_i), + + .data_type_ex_i(u_cv32e40p_top.core_i.data_type_ex), + + .pc_id_i(u_cv32e40p_top.core_i.pc_id), + + //From controller + .ctrl_fsm_cs (u_cv32e40p_top.core_i.id_stage_i.controller_i.ctrl_fsm_cs ), + .is_hwlp_body (u_cv32e40p_top.core_i.id_stage_i.controller_i.is_hwlp_body ), + .hwlp_end0_eq_pc (u_cv32e40p_top.core_i.id_stage_i.controller_i.hwlp_end0_eq_pc ), + .hwlp_counter0_gt_1(u_cv32e40p_top.core_i.id_stage_i.controller_i.hwlp_counter0_gt_1), + .hwlp_end1_eq_pc (u_cv32e40p_top.core_i.id_stage_i.controller_i.hwlp_end1_eq_pc ), + .hwlp_counter1_gt_1(u_cv32e40p_top.core_i.id_stage_i.controller_i.hwlp_counter1_gt_1), + .jump_done_q (u_cv32e40p_top.core_i.id_stage_i.controller_i.jump_done_q ) +); + +bind cv32e40p_id_stage cv32e40p_ID_assert u_cv32e40p_ID_assert ( + .clk_i(clk), + .rst_ni(rst_n), + + .alu_op_a_mux_sel (alu_op_a_mux_sel ), + .alu_op_b_mux_sel (alu_op_b_mux_sel ), + .alu_op_c_mux_sel (alu_op_c_mux_sel ), + .alu_bmask_b_mux_sel (alu_bmask_b_mux_sel ), + .ctrl_transfer_target_mux_sel(ctrl_transfer_target_mux_sel) +); + +bind cv32e40p_ex_stage cv32e40p_EX_assert u_cv32e40p_EX_assert ( + .clk_i(clk), + .rst_ni(rst_n), + + .apu_valid (apu_valid ), + .apu_singlecycle (apu_singlecycle ), + .apu_multicycle (apu_multicycle ), + .regfile_alu_we_i(regfile_alu_we_i), + .apu_en_i (apu_en_i ), + .regfile_we_lsu (regfile_we_lsu ), + .apu_rvalid_i (apu_rvalid_i ), + .apu_rvalid_q (apu_rvalid_q ), + .data_misaligned_i (data_misaligned_i ), + .data_misaligned_ex_i (data_misaligned_ex_i ), + .data_req_i (data_req_i ), + .data_rvalid_i (data_rvalid_i ), + .mulh_active (mulh_active ), + .mult_operator_i (mult_operator_i ), + .ctrl_transfer_insn_in_dec_i(ctrl_transfer_insn_in_dec_i), + .apu_read_dep_for_jalr_o (apu_read_dep_for_jalr_o ) +); + +bind fpnew_divsqrt_th_32 fpnew_divsqrt_th_32_assert u_fpnew_divsqrt_th_32_assert ( + .clk_i (clk_i), + .rst_ni(rst_ni), + + .op_starting (op_starting ), + .unit_ready_q (unit_ready_q ), + .ex2_inst_wb (ex2_inst_wb ), + .ex2_inst_wb_vld_q(ex2_inst_wb_vld_q) +); diff --git a/scripts/formal/src/cv32e40p_formal_top.sv b/scripts/formal/src/cv32e40p_formal_top.sv new file mode 100644 index 000000000..5148cd76d --- /dev/null +++ b/scripts/formal/src/cv32e40p_formal_top.sv @@ -0,0 +1,93 @@ +// Copyright 2024 Dolphin Design +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the "License"); +// you may not use this file except in compliance with the License, or, +// at your option, the Apache License version 2.0. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +//////////////////////////////////////////////////////////////////////////////////// +// // +// Contributors: Yoann Pruvost, Dolphin Design // +// // +// Description: Formal testbench for CV32E40P // +// // +//////////////////////////////////////////////////////////////////////////////////// + +module cv32e40p_formal_top ( + // Clock and Reset + input logic clk_i, + input logic rst_ni, + + input logic pulp_clock_en_i, // PULP clock enable (only used if COREV_CLUSTER = 1) + input logic scan_cg_en_i, // Enable all clock gates for testing + + // Core ID, Cluster ID, debug mode halt address and boot address are considered more or less static + input logic [31:0] boot_addr_i, + input logic [31:0] mtvec_addr_i, + input logic [31:0] dm_halt_addr_i, + input logic [31:0] hart_id_i, + input logic [31:0] dm_exception_addr_i, + + // Instruction memory interface + output logic instr_req_o, + input logic instr_gnt_i, + input logic instr_rvalid_i, + output logic [31:0] instr_addr_o, + input logic [31:0] instr_rdata_i, + + // Data memory interface + output logic data_req_o, + input logic data_gnt_i, + input logic data_rvalid_i, + output logic data_we_o, + output logic [ 3:0] data_be_o, + output logic [31:0] data_addr_o, + output logic [31:0] data_wdata_o, + input logic [31:0] data_rdata_i, + + // Interrupt inputs + input logic [31:0] irq_i, // CLINT interrupts + CLINT extension interrupts + output logic irq_ack_o, + output logic [ 4:0] irq_id_o, + + // Debug Interface + input logic debug_req_i, + output logic debug_havereset_o, + output logic debug_running_o, + output logic debug_halted_o, + + // CPU Control Signals + input logic fetch_enable_i, + output logic core_sleep_o +); + + `ifdef PULP_F0 + parameter COREV_PULP = 1; + parameter FPU = 1; + `elsif PULP + parameter COREV_PULP = 1; + parameter FPU = 0; + `else + parameter COREV_PULP = 0; + parameter FPU = 0; + `endif + + cv32e40p_top #( + .COREV_PULP(COREV_PULP), + .FPU(FPU) + + ) u_cv32e40p_top ( + .* + ); + + +endmodule \ No newline at end of file diff --git a/scripts/formal/src/data_assert.sv b/scripts/formal/src/data_assert.sv new file mode 100644 index 000000000..1b70b660b --- /dev/null +++ b/scripts/formal/src/data_assert.sv @@ -0,0 +1,74 @@ +// Copyright 2024 Dolphin Design +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the "License"); +// you may not use this file except in compliance with the License, or, +// at your option, the Apache License version 2.0. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +//////////////////////////////////////////////////////////////////////////////////// +// // +// Contributors: Yoann Pruvost, Dolphin Design // +// Pascal Gouedo, Dolphin Design // +// // +// Description: OBI protocol emulation for CV32E40P data interface // +// // +//////////////////////////////////////////////////////////////////////////////////// + +module data_assert ( + input logic clk_i, + input logic rst_ni, + + // Data memory interface + input logic data_req_o, + input logic data_gnt_i, + input logic data_rvalid_i, + input logic data_we_o, + input logic [ 3:0] data_be_o, + input logic [31:0] data_addr_o, + input logic [31:0] data_wdata_o, + input logic [31:0] data_rdata_i +); + + /***************** + * Helpers logic * + *****************/ + int s_outstanding_cnt; + + always_ff @(posedge clk_i or negedge rst_ni) begin + if(!rst_ni) begin + s_outstanding_cnt <= 0; + end else if (data_req_o & data_gnt_i & data_rvalid_i) begin + s_outstanding_cnt <= s_outstanding_cnt; + end else if (data_req_o & data_gnt_i) begin + s_outstanding_cnt <= s_outstanding_cnt + 1; + end else if (data_rvalid_i) begin + s_outstanding_cnt <= s_outstanding_cnt - 1; + end + end + + /********** + * Assume * + **********/ + // Concerning lint_grnt + property no_grnt_when_no_req; + @(posedge clk_i) disable iff(!rst_ni) + !data_req_o |-> !data_gnt_i; + endproperty + + property no_rvalid_if_no_pending_req; + @(posedge clk_i) disable iff(!rst_ni) + s_outstanding_cnt < 1 |-> !data_rvalid_i; + endproperty + + assume_no_grnt_when_no_req: assume property(no_grnt_when_no_req); + assume_no_rvalid_if_no_pending_req: assume property(no_rvalid_if_no_pending_req); +endmodule diff --git a/scripts/formal/src/debug_assert.sv b/scripts/formal/src/debug_assert.sv new file mode 100644 index 000000000..0c6c6bd8c --- /dev/null +++ b/scripts/formal/src/debug_assert.sv @@ -0,0 +1,46 @@ +// Copyright 2024 Dolphin Design +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the "License"); +// you may not use this file except in compliance with the License, or, +// at your option, the Apache License version 2.0. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +//////////////////////////////////////////////////////////////////////////////////// +// // +// Contributors: Yoann Pruvost, Dolphin Design // +// // +// Description: Debug interface constraints // +// // +//////////////////////////////////////////////////////////////////////////////////// + +module debug_assert ( + input logic clk_i, + input logic rst_ni, + // Debug Interface + input logic debug_req_i, + input logic debug_havereset_o, + input logic debug_running_o, + input logic debug_halted_o +); + + /********** + * Assume * + **********/ + property no_debug; + @(posedge clk_i) disable iff(!rst_ni) + debug_req_i == '0; + endproperty + + // Uncomment this line to disable debug interface + // assume_no_debug: assume property(no_debug); + +endmodule \ No newline at end of file diff --git a/scripts/formal/src/fpnew_divsqrt_th_32_assert.sv b/scripts/formal/src/fpnew_divsqrt_th_32_assert.sv new file mode 100644 index 000000000..d66e15df6 --- /dev/null +++ b/scripts/formal/src/fpnew_divsqrt_th_32_assert.sv @@ -0,0 +1,42 @@ +// Copyright 2024 Dolphin Design +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the "License"); +// you may not use this file except in compliance with the License, or, +// at your option, the Apache License version 2.0. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +//////////////////////////////////////////////////////////////////////////////////// +// // +// Contributors: Yoann Pruvost, Dolphin Design // +// // +// Description: Assertion for unreachable code in CV32E40P div sqrt unit // +// // +//////////////////////////////////////////////////////////////////////////////////// + +module fpnew_divsqrt_th_32_assert ( + input logic clk_i, + input logic rst_ni, + + input logic op_starting , + input logic unit_ready_q , + input logic ex2_inst_wb , + input logic ex2_inst_wb_vld_q +); + + property unreachable_divsqrt_th_288; + @(posedge clk_i) disable iff(!rst_ni) + (op_starting && unit_ready_q) |-> !(ex2_inst_wb && ex2_inst_wb_vld_q); + endproperty + + assert_unreachable_divsqrt_th_288: assert property(unreachable_divsqrt_th_288); + +endmodule \ No newline at end of file diff --git a/scripts/formal/src/insn_assert.sv b/scripts/formal/src/insn_assert.sv new file mode 100644 index 000000000..ca3acdc5f --- /dev/null +++ b/scripts/formal/src/insn_assert.sv @@ -0,0 +1,165 @@ +// Copyright 2024 Dolphin Design +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the "License"); +// you may not use this file except in compliance with the License, or, +// at your option, the Apache License version 2.0. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +//////////////////////////////////////////////////////////////////////////////////// +// // +// Contributors: Yoann Pruvost, Dolphin Design // +// // +// Description: OBI protocol emulation for CV32E40P instruction interface // +// // +//////////////////////////////////////////////////////////////////////////////////// + +module insn_assert ( + input logic clk_i, + input logic rst_ni, + // Instruction memory interface + input logic instr_req_o, + input logic instr_gnt_i, + input logic instr_rvalid_i, + input logic [31:0] instr_addr_o, + input logic [31:0] instr_rdata_i +); + + import cv32e40p_pkg::*; + import cv32e40p_tracer_pkg::*; + + /***************** + * Helpers logic * + *****************/ + int s_outstanding_cnt; + + always_ff @(posedge clk_i or negedge rst_ni) begin + if(!rst_ni) begin + s_outstanding_cnt <= 0; + end else if (instr_req_o & instr_gnt_i & instr_rvalid_i) begin + s_outstanding_cnt <= s_outstanding_cnt; + end else if (instr_req_o & instr_gnt_i) begin + s_outstanding_cnt <= s_outstanding_cnt + 1; + end else if (instr_rvalid_i) begin + s_outstanding_cnt <= s_outstanding_cnt - 1; + end + end + + logic [31:0] s_prev_insn; + always_ff @(posedge clk_i or negedge rst_ni) begin + if(!rst_ni) begin + s_prev_insn <= '0; + end else if (instr_rvalid_i) begin + s_prev_insn <= instr_rdata_i; + end + end + + /********** + * Assume * + **********/ + // Concerning lint_grnt + property no_grnt_when_no_req; + @(posedge clk_i) disable iff(!rst_ni) + !instr_req_o |-> !instr_gnt_i; + endproperty + + property no_rvalid_if_no_pending_req; + @(posedge clk_i) disable iff(!rst_ni) + s_outstanding_cnt < 1 |-> !instr_rvalid_i; + endproperty + + property no_compressed; + @(posedge clk_i) disable iff(!rst_ni) + instr_rdata_i[1:0] == 2'b11; + endproperty + + property no_jump; + @(posedge clk_i) disable iff(!rst_ni) + (instr_rdata_i[6:0] != OPCODE_JAL) & (instr_rdata_i[6:0] != OPCODE_JALR); + endproperty + + property no_branch; + @(posedge clk_i) disable iff(!rst_ni) + instr_rdata_i[6:0] != OPCODE_BRANCH; + endproperty + + property no_custom0; + @(posedge clk_i) disable iff(!rst_ni) + instr_rdata_i[6:0] != OPCODE_CUSTOM_0; + endproperty + + property cvend0_only_after_cvstart0; + @(posedge clk_i) disable iff(!rst_ni) + (s_prev_insn != INSTR_CVSTARTI0) & (s_prev_insn != INSTR_CVSTARTI0) |-> (instr_rdata_i != INSTR_CVSENDI0) & (instr_rdata_i != INSTR_CVEND0); + endproperty + + property cvcount0_only_after_cvend0; + @(posedge clk_i) disable iff(!rst_ni) + (s_prev_insn != INSTR_CVSENDI0) & (s_prev_insn != INSTR_CVEND0) |-> (instr_rdata_i != INSTR_CVCOUNTI0) & (instr_rdata_i != INSTR_CVCOUNT0); + endproperty + + property no_cvsetup0; + @(posedge clk_i) disable iff(!rst_ni) + (instr_rdata_i != INSTR_CVSETUPI0) & (instr_rdata_i != INSTR_CVSETUP0); + endproperty + + property no_cvstart0; + @(posedge clk_i) disable iff(!rst_ni) + (instr_rdata_i != INSTR_CVSTARTI0) & (instr_rdata_i != INSTR_CVSTART0); + endproperty + + property cvend1_only_after_cvstart1; + @(posedge clk_i) disable iff(!rst_ni) + (s_prev_insn != INSTR_CVSTARTI1) & (s_prev_insn != INSTR_CVSTARTI1) |-> (instr_rdata_i != INSTR_CVSENDI1) & (instr_rdata_i != INSTR_CVEND1); + endproperty + + property cvcount1_only_after_cvend1; + @(posedge clk_i) disable iff(!rst_ni) + (s_prev_insn != INSTR_CVSENDI1) & (s_prev_insn != INSTR_CVEND1) |-> (instr_rdata_i != INSTR_CVCOUNTI1) & (instr_rdata_i != INSTR_CVCOUNT1); + endproperty + + property no_cvsetup1; + @(posedge clk_i) disable iff(!rst_ni) + (instr_rdata_i != INSTR_CVSETUPI1) & (instr_rdata_i != INSTR_CVSETUP1); + endproperty + + property no_cvstart1; + @(posedge clk_i) disable iff(!rst_ni) + (instr_rdata_i != INSTR_CVSTARTI1) & (instr_rdata_i != INSTR_CVSTART1); + endproperty + + property no_csr_write_to_hwloop; + @(posedge clk_i) disable iff(!rst_ni) + instr_rdata_i[6:0] == OPCODE_SYSTEM |-> (instr_rdata_i[31:20] != 12'hCC0) & (instr_rdata_i[31:20] != 12'hCC1) & (instr_rdata_i[31:20] != 12'hCC2) & (instr_rdata_i[31:20] != 12'hCC4) & (instr_rdata_i[31:20] != 12'hCC5) & (instr_rdata_i[31:20] != 12'hCC6); + endproperty + + assume_no_grnt_when_no_req: assume property(no_grnt_when_no_req); + assume_no_rvalid_if_no_pending_req: assume property(no_rvalid_if_no_pending_req); + // assume_no_compressed: assume property(no_compressed); + // assume_no_jump: assume property(no_jump); + // assume_no_branch: assume property(no_branch); + + // assume_no_custom0: assume property(no_custom0); + + //hwloop 0 constraints + // assume_cvend0_only_after_cvstart0: assume property(cvend0_only_after_cvstart0); + // assume_cvcount0_only_after_cvend0: assume property(cvcount0_only_after_cvend0); + // assume_no_cvsetup0: assume property(no_cvsetup0); + // assume_no_cvstart0: assume property(no_cvstart0); //This one disables all hwloop0 + //hwloop 1 constraints + // assume_cvend1_only_after_cvstart1: assume property(cvend1_only_after_cvstart1); + // assume_cvcount1_only_after_cvend1: assume property(cvcount1_only_after_cvend1); + // assume_no_cvsetup1: assume property(no_cvsetup1); + // assume_no_cvstart1: assume property(no_cvstart1); //This one disables all hwloop1 + + assume_no_csr_write_to_hwloop: assume property(no_csr_write_to_hwloop); + +endmodule \ No newline at end of file diff --git a/scripts/formal/src/interrupt_assert.sv b/scripts/formal/src/interrupt_assert.sv new file mode 100644 index 000000000..0f0e67492 --- /dev/null +++ b/scripts/formal/src/interrupt_assert.sv @@ -0,0 +1,46 @@ +// Copyright 2024 Dolphin Design +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the "License"); +// you may not use this file except in compliance with the License, or, +// at your option, the Apache License version 2.0. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +//////////////////////////////////////////////////////////////////////////////////// +// // +// Contributors: Yoann Pruvost, Dolphin Design // +// // +// Description: Debug interface constraints // +// // +//////////////////////////////////////////////////////////////////////////////////// + +module interrput_assert ( + input logic clk_i, + input logic rst_ni, + // Interrupt inputs + input logic [31:0] irq_i, + input logic irq_ack_o, + input logic [ 4:0] irq_id_o +); + + /********** + * Assume * + **********/ + property no_interrupt; + @(posedge clk_i) disable iff(!rst_ni) + irq_i == '0; + endproperty + + // Uncomment to disable interrupt interface + // assume_no_interrupt: assume property(no_interrupt); + + +endmodule \ No newline at end of file diff --git a/scripts/lec/README.md b/scripts/lec/README.md deleted file mode 100644 index 51befbc2f..000000000 --- a/scripts/lec/README.md +++ /dev/null @@ -1,51 +0,0 @@ -# Logic Equivalence Checking (LEC) - -This folder contains a LEC script that runs on both -Synopsys Formality and Cadence Design Systems Conformal. - -This script allows to catch non-logical equivalent changes on the RTL which are forbidden -on the verified paramter set. - -Please have a look at: https://cv32e40p.readthedocs.io/en/latest/core_versions/ - -The `cv32e40p_v1.0.0` tag refers to the frozen RTL. The RTL has been verified and frozen on a given value of the input parameter of the design. Unless a bug is found, it is forbidden to change the RTL -in a non-logical equivalent manner for PPA optimizations of any other change. -Instead, it is possible to change the RTL on a different value of the parameter set, which has not been verified yet. -For example, it is possible to change the RTL design when the `FPU` parameter is set to 1 as this configuration has not been verified yet. However, the design must be logically equivalent when the parameter is set back to 0. -It is possible to change the `apu` interface and the `pulp_clock_en_i` signal on the frozen parameter set as these -signals are not used when the parameter `FPU` and `PULP_CLUSTER` are set to 0, respectively. - -The current scripts have been tried on Synopsys Formality `2021.06-SP5` and Cadence Design Systems Conformal `20.20` on a 64 bit executable. - -### Running the script - -From a bash shell, please execute: - -``` -./lec.sh synopsys -``` - or - -``` -./lec.sh cadence -``` - -to use one of the tools. synopsys is used by default if no tool is specified,. - -Use `sh ./les.sh {synopsys, cadence}` if you run it from a tcsh shell. - -The script clones the `cv32e40p_v1.0.0` tag of the core as a golden reference, and uses the current repository's `rtl` as revised version. - -If you want to use another golden reference rtl, Set the `GOLDEN_RTL` enviromental variable to the new rtl before calling the `lec.sh` script. - -``` -export GOLDEN_RTL=YOUR_GOLDEN_CORE_RTL_PATH -``` -or - -``` -setenv GOLDEN_RTL YOUR_GOLDEN_CORE_RTL_PATH -``` -If the script succeeds, it returns 0, otherwise -1. - -The `check_lec.tcl` scripts in the tool specific folders are executed on the tools to perform `RTL to RTL` logic equivalence checking. diff --git a/scripts/lec/cadence_conformal/check_lec.tcl b/scripts/lec/cadence_conformal/check_lec.tcl deleted file mode 100644 index d8b918a36..000000000 --- a/scripts/lec/cadence_conformal/check_lec.tcl +++ /dev/null @@ -1,38 +0,0 @@ -// Copyright 2021 OpenHW Group -// -// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// https://solderpad.org/licenses/ -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - -read_design -SV -replace -noelaborate -golden -File ../golden.src - -elaborate_design -golden - -read_design -SV -replace -noelaborate -revised -File ../revised.src - -elaborate_design -revised - -report_design_data > ./reports/report_design.log - -add_ignored_outputs apu_req_o -Both -add_ignored_outputs apu_operands_o* -Both -add_ignored_outputs apu_op_o* -Both -add_ignored_outputs apu_flags_o* -Both - -write_hier_compare_dofile hier_compare_r2r.do -constraint -replace - -run_hier_compare hier_compare_r2r.do -ROOT_module cv32e40p_core cv32e40p_core - -report_hier_compare_result -all -usage > ./reports/result.rpt -report_hier_compare_result -NONEQuivalent -usage > ./reports/result_noneq.rpt -report_verification -verbose -hier > ./reports/result_verfication.rpt - -exit 0 diff --git a/scripts/lec/clone_reference.sh b/scripts/lec/clone_reference.sh deleted file mode 100755 index 76a7510eb..000000000 --- a/scripts/lec/clone_reference.sh +++ /dev/null @@ -1,22 +0,0 @@ -#!/bin/bash - -# Copyright 2021 OpenHW Group -# -# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# https://solderpad.org/licenses/ -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. - -if [ ! -d "./golden_reference_design" ]; then - mkdir -p ./golden_reference_design - cd ./golden_reference_design - git clone https://github.com/openhwgroup/cv32e40p.git --branch cv32e40p_v1.0.0 - cd ../ -fi diff --git a/scripts/lec/lec.sh b/scripts/lec/lec.sh deleted file mode 100755 index 5e9f7387f..000000000 --- a/scripts/lec/lec.sh +++ /dev/null @@ -1,98 +0,0 @@ -#!/bin/bash - -# Copyright 2021 OpenHW Group -# -# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# https://solderpad.org/licenses/ -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. - -if [[ -z "${GOLDEN_RTL}" ]]; then - echo "The env variable GOLDEN_RTL is empty." - echo "Cloning Golden Design...." - sh clone_reference.sh - export GOLDEN_RTL=$(pwd)/golden_reference_design/cv32e40p/rtl -else - echo "Using ${GOLDEN_RTL} as reference design" -fi - -REVISED_RTL=$(pwd)/../../rtl - - -var_golden_rtl=$(awk '{ if ($0 ~ "sv" && $0 !~ "incdir" && $0 !~ "wrapper" && $0 !~ "tracer") print $0 }' $GOLDEN_RTL/../cv32e40p_manifest.flist | awk -v rtlpath=$GOLDEN_RTL -F "/" '{$1=rtlpath} OFS="/"') - -var_revised_rtl=$(awk '{ if ($0 ~ "sv" && $0 !~ "incdir" && $0 !~ "wrapper" && $0 !~ "_top" && $0 !~ "tracer") print $0 }' $REVISED_RTL/../cv32e40p_manifest.flist | awk -v rtlpath=$REVISED_RTL -F "/" '{$1=rtlpath} OFS="/"') - -echo $var_golden_rtl > golden.src -echo $var_revised_rtl > revised.src - -if [[ $# -gt 0 ]]; then - if [[ $1 == "cadence" ]]; then - echo "Using Cadence Conformal" - if [[ -d ./cadence_conformal/reports ]]; then - rm -rf ./cadence_conformal/reports - mkdir ./cadence_conformal/reports - else - mkdir ./cadence_conformal/reports - fi - else - echo "Using Synopsys Formality" - if [[ -d ./synopsys_formality/reports ]]; then - rm -rf ./synopsys_formality/reports - mkdir ./synopsys_formality/reports - else - mkdir ./synopsys_formality/reports - fi - fi -else - echo "No tool specified...." - echo "Using Synopsys Formality" - if [[ -d ./synopsys_formality/reports ]]; then - rm -rf ./synopsys_formality/reports - mkdir ./synopsys_formality/reports - else - mkdir ./synopsys_formality/reports - fi -fi - -if [[ $1 == "cadence" ]]; then - echo "Running Cadence Conformal" - cd ./cadence_conformal - lec -Dofile check_lec.tcl -TclMode -LOGfile cv32e40p_lec_log.log -NoGUI -xl - if [ -f "./reports/result.rpt" ]; then - NonLec=$(awk '{ if ($0 ~ "Hierarchical compare : Equivalent") print "0"}' ./reports/result.rpt) - else - echo "FATAL: could not find reports..." - NonLec="-1" - fi - cd ../ -else - echo "Running Synopsys Formality" - cd ./synopsys_formality - fm_shell -f check_lec.tcl |& tee cv32e40p_lec_log.log - if [ -f "./reports/verify.rpt" ]; then - NonLec=$(awk '{ if ($0 ~ "Verification SUCCEEDED") print "0"}' ./reports/verify.rpt) - else - echo "FATAL: could not find reports..." - NonLec="-1" - fi - cd ../ -fi - -if [[ $NonLec == "0" ]]; then - echo "The DESIGN IS LOGICALLY EQUIVALENT" -else - NonLec="-1" - echo "The DESIGN IS NOT LOGICALLY EQUIVALENT" -fi - -echo "$0 returns $NonLec" - -exit $NonLec diff --git a/scripts/lec/synopsys_formality/check_lec.tcl b/scripts/lec/synopsys_formality/check_lec.tcl deleted file mode 100644 index 612aba257..000000000 --- a/scripts/lec/synopsys_formality/check_lec.tcl +++ /dev/null @@ -1,22 +0,0 @@ -set synopsys_auto_setup true - -read_sverilog -container r -libname WORK -12 -f ../golden.src -set_top r:/WORK/cv32e40p_core - -read_sverilog -container i -libname WORK -12 -f ../revised.src -set_top i:/WORK/cv32e40p_core - -match > ./reports/match.rpt - -set_dont_verify_point -type port i:WORK/cv32e40p_core/apu_req_o -set_dont_verify_point -type port i:WORK/cv32e40p_core/apu_operands_o* -set_dont_verify_point -type port i:WORK/cv32e40p_core/apu_op_o* -set_dont_verify_point -type port i:WORK/cv32e40p_core/apu_flags_o* - -verify > ./reports/verify.rpt - -report_aborted_points > ./reports/aborted_points.rpt -report_failing_points > ./reports/failing_points.rpt -analyze_points -failing > ./reports/analyze.rpt - -exit diff --git a/scripts/lint/README.md b/scripts/lint/README.md new file mode 100644 index 000000000..8aade066c --- /dev/null +++ b/scripts/lint/README.md @@ -0,0 +1,28 @@ +# RTL source Lint + +This folder contains LINT scripts that runs using SiemensEDA Questa AutoCheck tool. It requires SiemensEDA QuestaSim to first compile the design. + +Those scripts allow to check RTL coding quality using common guidelines and rules. It can find syntax errors or issues leading to bad/incorrect synthesis (like latches in combinational process). +Common practice is to launch LINT check prior to committing RTL sources to git repository. + +As cv32e40p\_top has 5 parameters and to be able to check different parameters values, a new top level module (cv32e40p\_wrapper) has been created together with some predefined configuration packages (in config\_?p\_?f\_?z\_?lat\_??c directories). + +Configuration directory naming style is: +- \_?p : PULP enabled or not (0 or 1) +- \_?f : FPU enabled or not (0 or 1) +- \_?z : ZFINX enabled or not (0 or 1) +- \_?lat : FPU instructions latency (0, 1 or 2) +- \_?c : PULP\_CLUSTER enabled or not (0 or 1) + +### Running the script + +From a shell, please execute: + +``` +./lint.sh 1p_0f_0z_0lat_0c +``` + +The script uses `../../rtl` as design sources to check. + +Intermediate logs are visible in `questa_autocheck/config_?p_?f_?z_?lat_?c` and `questa_autocheck/config_?p_?f_?z_?lat_?c/formal_lint_out` and final lint report in `questa_autocheck/config_?p_?f_?z_?lat_?c/formal_lint.rpt` + diff --git a/scripts/lint/autocheck_common_rules.do b/scripts/lint/autocheck_common_rules.do new file mode 100644 index 000000000..f977f2cd7 --- /dev/null +++ b/scripts/lint/autocheck_common_rules.do @@ -0,0 +1,14 @@ +autocheck enable +autocheck disable -type ARITH_OVERFLOW_SUB +autocheck disable -type ARITH_OVERFLOW_VAL +autocheck disable -type CASE_DEFAULT +autocheck disable -type DECLARATION_UNUSED_UNDRIVEN +autocheck disable -type FUNCTION_INCOMPLETE_ASSIGN +autocheck disable -type INDEX_UNREACHABLE +autocheck disable -type INIT_X_OPTIMISM +autocheck disable -type INIT_X_PESSIMISM +autocheck disable -type INIT_X_UNRESOLVED +autocheck disable -type INIT_X_UNRESOLVED_MEM +autocheck disable -type REG_RACE +autocheck disable -type REG_STUCK_AT +configure message severity fatal -id elaboration-835 diff --git a/scripts/lint/config_0p_0f_0z_0lat_0c/cv32e40p_config_pkg.sv b/scripts/lint/config_0p_0f_0z_0lat_0c/cv32e40p_config_pkg.sv new file mode 100644 index 000000000..aeb194c04 --- /dev/null +++ b/scripts/lint/config_0p_0f_0z_0lat_0c/cv32e40p_config_pkg.sv @@ -0,0 +1,19 @@ +`ifndef CV32E40P_CONFIG_PKG +`define CV32E40P_CONFIG_PKG + +package cv32e40p_config_pkg; + + parameter bit COREV_PULP = 0; + parameter bit COREV_CLUSTER = 0; + parameter bit FPU = 0; + parameter int FPU_ADDMUL_LAT = 0; + parameter int FPU_OTHERS_LAT = 0; + parameter bit ZFINX = 0; + parameter int INSTR_ADDR_MEM_WIDTH = 13; + parameter int DATA_ADDR_MEM_WIDTH = 13; + +endpackage + +`endif + + diff --git a/scripts/lint/config_1p_0f_0z_0lat_0c/cv32e40p_config_pkg.sv b/scripts/lint/config_1p_0f_0z_0lat_0c/cv32e40p_config_pkg.sv new file mode 100644 index 000000000..03894df90 --- /dev/null +++ b/scripts/lint/config_1p_0f_0z_0lat_0c/cv32e40p_config_pkg.sv @@ -0,0 +1,19 @@ +`ifndef CV32E40P_CONFIG_PKG +`define CV32E40P_CONFIG_PKG + +package cv32e40p_config_pkg; + + parameter bit COREV_PULP = 1; + parameter bit COREV_CLUSTER = 0; + parameter bit FPU = 0; + parameter int FPU_ADDMUL_LAT = 0; + parameter int FPU_OTHERS_LAT = 0; + parameter bit ZFINX = 0; + parameter int INSTR_ADDR_MEM_WIDTH = 13; + parameter int DATA_ADDR_MEM_WIDTH = 13; + +endpackage + +`endif + + diff --git a/scripts/lint/config_1p_1f_0z_0lat_0c/cv32e40p_config_pkg.sv b/scripts/lint/config_1p_1f_0z_0lat_0c/cv32e40p_config_pkg.sv new file mode 100644 index 000000000..fc7ba9e7c --- /dev/null +++ b/scripts/lint/config_1p_1f_0z_0lat_0c/cv32e40p_config_pkg.sv @@ -0,0 +1,19 @@ +`ifndef CV32E40P_CONFIG_PKG +`define CV32E40P_CONFIG_PKG + +package cv32e40p_config_pkg; + + parameter bit COREV_PULP = 1; + parameter bit COREV_CLUSTER = 0; + parameter bit FPU = 1; + parameter int FPU_ADDMUL_LAT = 0; + parameter int FPU_OTHERS_LAT = 0; + parameter bit ZFINX = 0; + parameter int INSTR_ADDR_MEM_WIDTH = 13; + parameter int DATA_ADDR_MEM_WIDTH = 13; + +endpackage + +`endif + + diff --git a/scripts/lint/config_1p_1f_0z_1lat_0c/cv32e40p_config_pkg.sv b/scripts/lint/config_1p_1f_0z_1lat_0c/cv32e40p_config_pkg.sv new file mode 100644 index 000000000..c74225582 --- /dev/null +++ b/scripts/lint/config_1p_1f_0z_1lat_0c/cv32e40p_config_pkg.sv @@ -0,0 +1,19 @@ +`ifndef CV32E40P_CONFIG_PKG +`define CV32E40P_CONFIG_PKG + +package cv32e40p_config_pkg; + + parameter bit COREV_PULP = 1; + parameter bit COREV_CLUSTER = 0; + parameter bit FPU = 1; + parameter int FPU_ADDMUL_LAT = 1; + parameter int FPU_OTHERS_LAT = 1; + parameter bit ZFINX = 0; + parameter int INSTR_ADDR_MEM_WIDTH = 13; + parameter int DATA_ADDR_MEM_WIDTH = 13; + +endpackage + +`endif + + diff --git a/scripts/lint/config_1p_1f_0z_2lat_0c/cv32e40p_config_pkg.sv b/scripts/lint/config_1p_1f_0z_2lat_0c/cv32e40p_config_pkg.sv new file mode 100644 index 000000000..e17cc8b70 --- /dev/null +++ b/scripts/lint/config_1p_1f_0z_2lat_0c/cv32e40p_config_pkg.sv @@ -0,0 +1,19 @@ +`ifndef CV32E40P_CONFIG_PKG +`define CV32E40P_CONFIG_PKG + +package cv32e40p_config_pkg; + + parameter bit COREV_PULP = 1; + parameter bit COREV_CLUSTER = 0; + parameter bit FPU = 1; + parameter int FPU_ADDMUL_LAT = 2; + parameter int FPU_OTHERS_LAT = 2; + parameter bit ZFINX = 0; + parameter int INSTR_ADDR_MEM_WIDTH = 13; + parameter int DATA_ADDR_MEM_WIDTH = 13; + +endpackage + +`endif + + diff --git a/scripts/lint/config_1p_1f_1z_0lat_0c/cv32e40p_config_pkg.sv b/scripts/lint/config_1p_1f_1z_0lat_0c/cv32e40p_config_pkg.sv new file mode 100644 index 000000000..0d28e20ef --- /dev/null +++ b/scripts/lint/config_1p_1f_1z_0lat_0c/cv32e40p_config_pkg.sv @@ -0,0 +1,19 @@ +`ifndef CV32E40P_CONFIG_PKG +`define CV32E40P_CONFIG_PKG + +package cv32e40p_config_pkg; + + parameter bit COREV_PULP = 1; + parameter bit COREV_CLUSTER = 0; + parameter bit FPU = 1; + parameter int FPU_ADDMUL_LAT = 0; + parameter int FPU_OTHERS_LAT = 0; + parameter bit ZFINX = 1; + parameter int INSTR_ADDR_MEM_WIDTH = 13; + parameter int DATA_ADDR_MEM_WIDTH = 13; + +endpackage + +`endif + + diff --git a/scripts/lint/config_1p_1f_1z_1lat_0c/cv32e40p_config_pkg.sv b/scripts/lint/config_1p_1f_1z_1lat_0c/cv32e40p_config_pkg.sv new file mode 100644 index 000000000..e47e861c1 --- /dev/null +++ b/scripts/lint/config_1p_1f_1z_1lat_0c/cv32e40p_config_pkg.sv @@ -0,0 +1,19 @@ +`ifndef CV32E40P_CONFIG_PKG +`define CV32E40P_CONFIG_PKG + +package cv32e40p_config_pkg; + + parameter bit COREV_PULP = 1; + parameter bit COREV_CLUSTER = 0; + parameter bit FPU = 1; + parameter int FPU_ADDMUL_LAT = 1; + parameter int FPU_OTHERS_LAT = 1; + parameter bit ZFINX = 1; + parameter int INSTR_ADDR_MEM_WIDTH = 13; + parameter int DATA_ADDR_MEM_WIDTH = 13; + +endpackage + +`endif + + diff --git a/scripts/lint/config_1p_1f_1z_2lat_0c/cv32e40p_config_pkg.sv b/scripts/lint/config_1p_1f_1z_2lat_0c/cv32e40p_config_pkg.sv new file mode 100644 index 000000000..af5b4b732 --- /dev/null +++ b/scripts/lint/config_1p_1f_1z_2lat_0c/cv32e40p_config_pkg.sv @@ -0,0 +1,19 @@ +`ifndef CV32E40P_CONFIG_PKG +`define CV32E40P_CONFIG_PKG + +package cv32e40p_config_pkg; + + parameter bit COREV_PULP = 1; + parameter bit COREV_CLUSTER = 0; + parameter bit FPU = 1; + parameter int FPU_ADDMUL_LAT = 2; + parameter int FPU_OTHERS_LAT = 2; + parameter bit ZFINX = 1; + parameter int INSTR_ADDR_MEM_WIDTH = 13; + parameter int DATA_ADDR_MEM_WIDTH = 13; + +endpackage + +`endif + + diff --git a/scripts/lint/config_1p_1f_1z_2lat_1c/cv32e40p_config_pkg.sv b/scripts/lint/config_1p_1f_1z_2lat_1c/cv32e40p_config_pkg.sv new file mode 100644 index 000000000..f0a16fe74 --- /dev/null +++ b/scripts/lint/config_1p_1f_1z_2lat_1c/cv32e40p_config_pkg.sv @@ -0,0 +1,19 @@ +`ifndef CV32E40P_CONFIG_PKG +`define CV32E40P_CONFIG_PKG + +package cv32e40p_config_pkg; + + parameter bit COREV_PULP = 1; + parameter bit COREV_CLUSTER = 1; + parameter bit FPU = 1; + parameter int FPU_ADDMUL_LAT = 2; + parameter int FPU_OTHERS_LAT = 2; + parameter bit ZFINX = 1; + parameter int INSTR_ADDR_MEM_WIDTH = 13; + parameter int DATA_ADDR_MEM_WIDTH = 13; + +endpackage + +`endif + + diff --git a/scripts/lint/cv32e40p_wrapper.sv b/scripts/lint/cv32e40p_wrapper.sv new file mode 100644 index 000000000..135ee4fa9 --- /dev/null +++ b/scripts/lint/cv32e40p_wrapper.sv @@ -0,0 +1,123 @@ +// Copyright 2024 OpenHW Group and Dolphin Design +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + +// Contributor(s): Pascal Gouedo, Dolphin Design +// +// Design Name: CV32E40P RTL Lint wrapper +// +// Description: Wrapper file instantiating CV32E40P top and importing +// a configuration package to be used for RTL LINT checks. + +module cv32e40p_wrapper ( + // Clock and Reset + input logic clk_i, + input logic rst_ni, + + input logic pulp_clock_en_i, + input logic scan_cg_en_i, + + input logic [31:0] boot_addr_i, + input logic [31:0] mtvec_addr_i, + input logic [31:0] dm_halt_addr_i, + input logic [31:0] hart_id_i, + input logic [31:0] dm_exception_addr_i, + + // Instruction memory interface + output logic instr_req_o, + input logic instr_gnt_i, + input logic instr_rvalid_i, + output logic [31:0] instr_addr_o, + input logic [31:0] instr_rdata_i, + + // Data memory interface + output logic data_req_o, + input logic data_gnt_i, + input logic data_rvalid_i, + output logic data_we_o, + output logic [ 3:0] data_be_o, + output logic [31:0] data_addr_o, + output logic [31:0] data_wdata_o, + input logic [31:0] data_rdata_i, + + // Interrupt inputs + input logic [31:0] irq_i, + output logic irq_ack_o, + output logic [ 4:0] irq_id_o, + + // Debug Interface + input logic debug_req_i, + output logic debug_havereset_o, + output logic debug_running_o, + output logic debug_halted_o, + + // CPU Control Signals + input logic fetch_enable_i, + output logic core_sleep_o +); + + import cv32e40p_config_pkg::*; + + // Instantiate the Core + cv32e40p_top #( + .COREV_PULP (COREV_PULP), + .COREV_CLUSTER (COREV_CLUSTER), + .FPU (FPU), + .FPU_ADDMUL_LAT (FPU_ADDMUL_LAT), + .FPU_OTHERS_LAT (FPU_OTHERS_LAT), + .ZFINX (ZFINX), + .NUM_MHPMCOUNTERS(1) + ) top_i ( + .clk_i (clk_i), + .rst_ni(rst_ni), + + .pulp_clock_en_i(pulp_clock_en_i), + .scan_cg_en_i (scan_cg_en_i), + + .boot_addr_i (boot_addr_i), + .mtvec_addr_i (mtvec_addr_i), + .dm_halt_addr_i (dm_halt_addr_i), + .hart_id_i (hart_id_i), + .dm_exception_addr_i(dm_exception_addr_i), + + .instr_req_o (instr_req_o), + .instr_gnt_i (instr_gnt_i), + .instr_rvalid_i(instr_rvalid_i), + .instr_addr_o (instr_addr_o), + .instr_rdata_i (instr_rdata_i), + + .data_req_o (data_req_o), + .data_gnt_i (data_gnt_i), + .data_rvalid_i(data_rvalid_i), + .data_we_o (data_we_o), + .data_be_o (data_be_o), + .data_addr_o (data_addr_o), + .data_wdata_o (data_wdata_o), + .data_rdata_i (data_rdata_i), + + .irq_i (irq_i), + .irq_ack_o(irq_ack_o), + .irq_id_o (irq_id_o), + + .debug_req_i (debug_req_i), + .debug_havereset_o(debug_havereset_o), + .debug_running_o (debug_running_o), + .debug_halted_o (debug_halted_o), + + .fetch_enable_i(fetch_enable_i), + .core_sleep_o (core_sleep_o) + ); + +endmodule diff --git a/scripts/lint/formal_lint_rules.do b/scripts/lint/formal_lint_rules.do new file mode 100644 index 000000000..a52229177 --- /dev/null +++ b/scripts/lint/formal_lint_rules.do @@ -0,0 +1,16 @@ +# define all clocks +netlist clock clk_i -period 100 -waveform 0 50 + +# define all reset +netlist reset rst_ni -active_low -async + +# define clock domain for reset +netlist port domain rst_ni -clock clk_i + +# define special case +netlist constant scan_cg_en_i 1'b0 +netlist constant pulp_clock_en_i 1'b0 + +# disable rules +autocheck disable -type FSM_DEADLOCK_STATE FSM_LOCKOUT_STATE + diff --git a/scripts/lint/lint.sh b/scripts/lint/lint.sh new file mode 100755 index 000000000..259f9dae6 --- /dev/null +++ b/scripts/lint/lint.sh @@ -0,0 +1,60 @@ +#!/usr/bin/env bash + +# Copyright 2023 OpenHW Group +# Copyright 2023 Dolphin Design +# +# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# https://solderpad.org/licenses/ +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# Contributor: Pascal Gouedo + +if [[ $# -eq 0 ]]; then + CONFIG=config_0p_0f_0z_0lat_0c +else + CONFIG=config_$1 + if [[ ! -d $CONFIG ]]; then + echo "Config $CONFIG does not exists." + exit + fi +fi +echo "Lint of $CONFIG" + +if [[ -d questa_autocheck/$CONFIG ]]; then + rm -rf questa_autocheck/$CONFIG +fi +mkdir -p questa_autocheck/$CONFIG + +# Creating RTL file list +if [[ $CONFIG == *1f* ]]; then + MANIFEST=cv32e40p_fpu_manifest +else + MANIFEST=cv32e40p_manifest +fi + +UPSTREAM_DIR=$(pwd)/../../rtl +echo "$upstream_dir" +sed -n '/^+incdir+/s:${DESIGN_RTL_DIR}:'"$UPSTREAM_DIR"':p' ../../$MANIFEST.flist > questa_autocheck/$CONFIG/inc_design.f +sed -n '1,/cv32e40p_sim_clock_gate/{s:^${DESIGN_RTL_DIR}:'"$UPSTREAM_DIR"':p}' ../../$MANIFEST.flist > questa_autocheck/$CONFIG/src_design.f +echo "$(pwd)/$CONFIG/cv32e40p_config_pkg.sv" >> questa_autocheck/$CONFIG/src_design.f +echo "$(pwd)/cv32e40p_wrapper.sv" >> questa_autocheck/$CONFIG/src_design.f + +cd questa_autocheck/$CONFIG + +# Compiling Verilog / SystemVerilog RTL files +vlog -64 -nologo -source -timescale "1 ns / 1 ps" -sv -f inc_design.f -f src_design.f -assertdebug -work design_lib |& tee compile_design.log + +# Launching formal lint analysis +qverify -licq -c -od formal_lint_out -do ../../qverify_analysis.do |& tee formal_lint.log + +# Launching formal lint AutoCheck Summary +qverify -licq -c -od formal_lint_out -do ../../qverify_autocheck.do + diff --git a/scripts/lint/proc_dumpAutoCheckSummary.tcl b/scripts/lint/proc_dumpAutoCheckSummary.tcl new file mode 100644 index 000000000..3c3f2f710 --- /dev/null +++ b/scripts/lint/proc_dumpAutoCheckSummary.tcl @@ -0,0 +1,74 @@ +proc dumpAutoCheckSummary { filename } { + namespace import -force Autocheck::* + if { [catch { set fp [open $filename a] } msg] } { + puts "Unable to open $filename : $msg" + exit 1 + } + + set typecnt 0 + #--------- Find types --------------------------------------- + set checks [GetChecks] + while { [set check [GetNext $checks]] != "" } { + set type [GetType $check] + set severity($type) [GetSeverity $check] + lappend types $type + } + set types [lsort [lrmdups $types]] + #--------- Collect data for each type ----------------------- + foreach type $types { + set cnt 0 + set cnt_waiv 0 + set cnt_viol 0 + set cnt_caut 0 + set cnt_inconcl 0 + set cnt_info 0 + set cnt_eval 0 + set cnt_off 0 + set cnt_def 0 + set checks [GetChecks] + while { [set check [GetNext $checks]] != "" } { + if {[GetType $check] == $type} { +# debug +#puts $fp "[GetType $check]" +#puts $fp "[GetStatus $check]" +#puts $fp "[GetSeverity $check]" + ### DM ### increment different counters depending of status + if {[GetStatus $check] == "Waived"} { + incr cnt_waiv + } else { + set Severity [GetSeverity $check] + switch $Severity { + Violation {incr cnt_viol} + Caution {incr cnt_caut} + Inconclusive {incr cnt_inconcl} + } + ### DM ### add other (off, ...) if needed + } + } + } + + ### DM ### only prints when waived exist / or when violation or inconclusive + if {$cnt_waiv != 0} { + puts $fp "# ** Waived:\t$type ($cnt_waiv)" + puts "# ** Waived:\t$type ($cnt_waiv)" + } + if {$cnt_viol != 0} { + puts $fp "# ** Violation:\t$type ($cnt_viol)" + puts "# ** Violation:\t$type ($cnt_viol)" + } + if {$cnt_caut != 0} { + puts $fp "# ** Caution:\t$type ($cnt_caut)" + puts "# ** Caution:\t$type ($cnt_caut)" + } + if {$cnt_inconcl != 0} { + puts $fp "# ** Inconclusive:\t$type ($cnt_inconcl)" + puts "# ** Inconclusive:\t$type ($cnt_inconcl)" + } + ### DM ### add other (caution, off, ...) if needed + + } + puts $fp "==============================================" + puts $fp " [llength $types] Types; [GetCount $checks] Checks" + close $fp +} + diff --git a/scripts/lint/qverify_analysis.do b/scripts/lint/qverify_analysis.do new file mode 100644 index 000000000..e66554992 --- /dev/null +++ b/scripts/lint/qverify_analysis.do @@ -0,0 +1,8 @@ +set top cv32e40p_wrapper +source ../../autocheck_common_rules.do +source ../../formal_lint_rules.do +autocheck report inconclusives +autocheck compile -work design_lib -d cv32e40p_wrapper -L design_lib -L work +autocheck verify -jobs 1 +exit + diff --git a/scripts/lint/qverify_autocheck.do b/scripts/lint/qverify_autocheck.do new file mode 100644 index 000000000..9bbcc18a4 --- /dev/null +++ b/scripts/lint/qverify_autocheck.do @@ -0,0 +1,4 @@ +autocheck load db formal_lint_out/autocheck_verify.db +source ../../proc_dumpAutoCheckSummary.tcl +dumpAutoCheckSummary formal_lint.rpt +exit diff --git a/scripts/slec/README.md b/scripts/slec/README.md new file mode 100644 index 000000000..6249563cc --- /dev/null +++ b/scripts/slec/README.md @@ -0,0 +1,79 @@ +# Sequential Logic Equivalence Checking (SLEC) + +This folder contains a SLEC script that runs: + +- LEC: Synopsys Formality and Cadence Design Systems Conformal. +- SEC: Siemens SLEC App + +Please have a look at: https://cv32e40p.readthedocs.io/en/latest/core_versions/ + +The `cv32e40p_v1.0.0` tag refers to the frozen RTL. The RTL has been verified +and frozen on a given value of the input parameter of the design. Unless a bug +is found, it is forbidden to change the RTL in a non-logical equivalent manner +for PPA optimizations of any other change. +Instead, it is possible to change the RTL on a different value of the parameter +set, which has not been verified yet. +For example, it is possible to change the RTL design when the `FPU` parameter is +set to 1 as this configuration has not been verified yet. However, the design +must be logically equivalent when the parameter is set back to 0. +It is possible to change the `apu` interface and the `pulp_clock_en_i` signal on +the frozen parameter set as these signals are not used when the parameter `FPU` +and `PULP_CLUSTER` are set to 0, respectively. + +The current scripts have been tried on Synopsys Formality `2021.06-SP5` , +Cadence Design Systems Conformal `20.20` and Siemens SLEC App `2023.4`. + +### Running the script + +From a bash shell using LEC, please execute: + +``` +./run.sh -t synopsys -p lec +``` + or + + ``` + ./run.sh -t cadence -p lec + ``` + + From a bash shell to use SEC, please execute: + ``` + ./run.sh -t siemens -p sec + ``` + + By default `cv32e40p_core` is used as a top module, if you want to use + another one set the `TOP_MODULE` environment variable. + + The script clones the `cv32e40p_v1.0.0` tag of the core as a golden reference, + and uses the current repository's `rtl` as revised version. + + If you want to use another golden reference RTL, set the `GOLDEN_RTL` + environmental variable to the new RTL before calling the `run.sh` script. + + ``` + export GOLDEN_RTL=YOUR_GOLDEN_CORE_RTL_PATH + ``` + or + + ``` + setenv GOLDEN_RTL YOUR_GOLDEN_CORE_RTL_PATH + ``` + +### Additional improvements for v2 + +To be able to make LEC checks between v2 versions, the scripts have been augmented with additional optional switches: +* for RTL version : -v v1 or v2 +* for PULP instructions selection : -x 0 or 1 +* for FPU instructions selection : -f 0 or 1 +* for ZFINX selection : -z 0 or 1 + +When those options are not used, present behavior is happenning, meaning verifying local RTL files with `cv32e40p_v1.0.0` tag. +When v2 option is selected, `cv32e40p_top` is used as a top module, including both `cv32e40p_core` and `CVFPU`. +CAUTION : Right now dev branch is cloned as a golden reference when v2 version is used. It will have to be changed to `cv32e40p_v2.0.0` tag after CV32E40Pv2 RTL freeze. + +From a bash shell using LEC, please execute: + +``` +./run.sh -t synopsys -p lec -v v2 -x 1 -f 1 +``` + diff --git a/scripts/slec/cadence/lec.tcl b/scripts/slec/cadence/lec.tcl new file mode 100644 index 000000000..dcc241e63 --- /dev/null +++ b/scripts/slec/cadence/lec.tcl @@ -0,0 +1,57 @@ +# Copyright 2024 OpenHW Group and Dolphin Design +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +# +# Licensed under the Solderpad Hardware License v 2.1 (the “License”); +# you may not use this file except in compliance with the License, or, +# at your option, the Apache License version 2.0. +# You may obtain a copy of the License at +# +# https://solderpad.org/licenses/SHL-2.1/ +# +# Unless required by applicable law or agreed to in writing, any work +# distributed under the License is distributed on an “AS IS” BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +set summary_log $::env(summary_log) +set top_module $::env(top_module) +set version $::env(version) +set pulp_cfg $::env(pulp_cfg) +set fpu_cfg $::env(fpu_cfg) +set zfinx_cfg $::env(zfinx_cfg) +set latency_cfg $::env(latency_cfg) + +if {"$version" == "v1"} { + set golden_parameter_list "-parameter PULP_XPULP 0 -parameter FPU 0 -parameter PULP_ZFINX 0" +} else { + set golden_parameter_list "-parameter COREV_PULP $pulp_cfg -parameter FPU $fpu_cfg -parameter ZFINX $zfinx_cfg -parameter FPU_ADDMUL_LAT $latency_cfg -parameter FPU_OTHERS_LAT $latency_cfg" +} + +read_design -SV09 -replace -noelaborate -golden -File ./golden.src + +elaborate_design -golden -root $top_module $golden_parameter_list + +read_design -SV09 -replace -noelaborate -revised -File ./revised.src + +elaborate_design -revised -root $top_module -parameter COREV_PULP $pulp_cfg -parameter FPU $fpu_cfg -parameter ZFINX $zfinx_cfg -parameter FPU_ADDMUL_LAT $latency_cfg -parameter FPU_OTHERS_LAT $latency_cfg + +report_design_data + +if {"$top_module" == "cv32e40p_core"} { + add_ignored_outputs apu_req_o -Both + add_ignored_outputs apu_operands_o* -Both + add_ignored_outputs apu_op_o* -Both + add_ignored_outputs apu_flags_o* -Both + add_ignored_outputs apu_busy_o -Revised +} + +write_hier_compare_dofile hier_compare_r2r.do -constraint -replace + +run_hier_compare hier_compare_r2r.do -ROOT_module $top_module $top_module + +report_hier_compare_result -all -usage > $summary_log +report_verification -verbose -hier >> $summary_log +report_hier_compare_result -NONEQuivalent -usage > $summary_log.noneq.rpt + +exit 0 diff --git a/scripts/slec/cadence/sec.tcl b/scripts/slec/cadence/sec.tcl new file mode 100644 index 000000000..7107eb9e3 --- /dev/null +++ b/scripts/slec/cadence/sec.tcl @@ -0,0 +1,40 @@ +# Copyright 2021 OpenHW Group +# +# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# https://solderpad.org/licenses/ +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +set summary_log $::env(summary_log) +set top_module $::env(top_module) + +check_sec -setup -spec_top $top_module -imp_top $top_module \ + -spec_analyze "-sv -f ./golden.src" \ + -imp_analyze "-sv -f ./revised.src"\ + -auto_map_reset_x_values + + +clock clk_i +reset ~rst_ni + +check_sec -map -auto + +if {"$top_module" == "cv32e40p_core"} { + check_sec -waive -waive_signals ex_stage_i.alu_i.ff_one_i.sel_nodes + check_sec -waive -waive_signals cv32e40p_core_imp.ex_stage_i.alu_i.ff_one_i.sel_nodes + + check_sec -waive -waive_signals ex_stage_i.alu_i.ff_one_i.index_nodes + check_sec -waive -waive_signals cv32e40p_core_imp.ex_stage_i.alu_i.ff_one_i.index_nodes +} + +check_sec -prove + +check_sec -signoff -get_valid_status -summary -file $summary_log + +exit 0 diff --git a/scripts/slec/run.sh b/scripts/slec/run.sh new file mode 100755 index 000000000..01bb1b126 --- /dev/null +++ b/scripts/slec/run.sh @@ -0,0 +1,245 @@ +#!/bin/bash + +# Copyright 2024 OpenHW Group and Dolphin Design +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +# +# Licensed under the Solderpad Hardware License v 2.1 (the “License”); +# you may not use this file except in compliance with the License, or, +# at your option, the Apache License version 2.0. +# You may obtain a copy of the License at +# +# https://solderpad.org/licenses/SHL-2.1/ +# +# Unless required by applicable law or agreed to in writing, any work +# distributed under the License is distributed on an “AS IS” BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +usage() { # Function: Print a help message. + echo "Usage: $0 -t {cadence,synopsys,siemens} -p {sec,lec} [-v {v1,v2}] [-x {0,1}] [-f {0,1}] [-z {0,1}] [-l {0,1,2}]]" 1>&2 + echo "For v2 : if f or z is 1 then p must be 1" 1>&2 + echo " if z is 1 then f must be 1" 1>&2 + echo " l only 1 or 2 if f is 1" 1>&2 +} + +exit_abnormal() { # Function: Exit with error. + usage + exit 1 +} + +not_implemented() { + echo "$1 does not have yet $2 implemented" + exit 1 +} + +print_log() { + echo "[LOG] $1" +} + +VERSION=v1 +PULP_CFG=0 +FPU_CFG=0 +ZFINX_CFG=0 +LATENCY_CFG=0 + +while getopts "t:p:v:x:f:z:l:" flag +do + case "${flag}" in + t) + target_tool=${OPTARG} + ;; + p) + target_process=${OPTARG} + ;; + v) + VERSION=${OPTARG} + ;; + x) + PULP_CFG=${OPTARG} + ;; + f) + FPU_CFG=${OPTARG} + ;; + z) + ZFINX_CFG=${OPTARG} + ;; + l) + LATENCY_CFG=${OPTARG} + ;; + :) + exit_abnormal + ;; + *) + exit_abnormal + ;; + ?) + exit_abnormal + ;; + esac +done + +if [[ "${target_tool}" != "cadence" && "${target_tool}" != "synopsys" && "${target_tool}" != "siemens" ]]; then + exit_abnormal +fi + +if [[ "${target_process}" != "sec" && "${target_process}" != "lec" ]]; then + exit_abnormal +fi + +if [[ "${VERSION}" != "v1" && "${VERSION}" != "v2" ]]; then + exit_abnormal +elif [[ "${VERSION}" == "v1" && ("${PULP_CFG}" != "0" || "${FPU_CFG}" != "0" || "${ZFINX_CFG}" != "0") ]]; then + exit_abnormal +fi + +if [[ "${PULP_CFG}" != 0 && "${PULP_CFG}" != 1 ]]; then + exit_abnormal +fi + +if [[ "${FPU_CFG}" != 0 && "${FPU_CFG}" != 1 ]]; then + exit_abnormal +fi + +if [[ "${ZFINX_CFG}" != 0 && "${ZFINX_CFG}" != 1 ]]; then + exit_abnormal +fi + +if [[ (("${PULP_CFG}" == 0 && ("${FPU_CFG}" == 1 || "${ZFINX_CFG}" == 1)) || ("${PULP_CFG}" == 1 && "${FPU_CFG}" == 0 && "${ZFINX_CFG}" == 1)) ]]; then + exit_abnormal +fi + +if [[ ("${FPU_CFG}" == 0 && ("${LATENCY_CFG}" == 1 || "${LATENCY_CFG}" == 2)) ]]; then + exit_abnormal +fi + +if [[ "${VERSION}" == "v1" ]]; then + REF_BRANCH=cv32e40p_v1.0.0 + TOP_MODULE=cv32e40p_core +else + REF_BRANCH=dev + TOP_MODULE=cv32e40p_top +fi + +export top_module=${TOP_MODULE} +export version=${VERSION} +export pulp_cfg=${PULP_CFG} +export fpu_cfg=${FPU_CFG} +export zfinx_cfg=${ZFINX_CFG} +export latency_cfg=${LATENCY_CFG} + +if [ -z "${REF_REPO}" ]; then + print_log "Empty REF_REPO env variable" + REF_REPO=https://github.com/openhwgroup/cv32e40p.git + REF_FOLDER=ref_design + print_log " * Setting REF_REPO ${REF_REPO}" + print_log " * Setting REF_FOLDER ${REF_FOLDER}" + print_log " * Setting REF_BRANCH ${REF_BRANCH}" + print_log " * Setting TOP_MODULE ${TOP_MODULE}" +fi + +RTL_FOLDER=$(readlink -f ../..) + +if [[ "${PULP_CFG}" == 0 && "${ZFINX_CFG}" == 0 ]]; then + FLIST=cv32e40p_manifest.flist +else + FLIST=cv32e40p_fpu_manifest.flist +fi + +if [[ -z "${TOP_MODULE}" ]]; then + print_log "Empty TOP_MODULE env variable" + print_log " * Setting TOP_MODULE ${TOP_MODULE}" +fi + +if [ ! -d ./reports/ ]; then + mkdir -p ./reports/ +fi + +if [[ -z "${GOLDEN_RTL}" ]]; then + print_log "The env variable GOLDEN_RTL is empty." + \rm -rf "./${REF_FOLDER}" + print_log " * Cloning Golden Design...." + git clone $REF_REPO --single-branch -b $REF_BRANCH $REF_FOLDER; + git -C ${REF_FOLDER} checkout $REF_COMMIT + export GOLDEN_RTL=$(pwd)/${REF_FOLDER}/rtl +else + print_log "${target_process^^}: Using ${GOLDEN_RTL} as reference design" +fi + +REVISED_DIR=$RTL_FOLDER +REVISED_FLIST=$(pwd)/revised.src + +GOLDEN_DIR=$(readlink -f ./${REF_FOLDER}/) +GOLDEN_FLIST=$(pwd)/golden.src + +var_golden_rtl=$(awk '{ if ($0 ~ "{DESIGN_RTL_DIR}" && $0 !~ "#" && $0 !~ "tracer" && $0 !~ "tb_wrapper" && $0 !~ "cv32e40p_wrapper") print $0 }' ${GOLDEN_DIR}/$FLIST | sed 's|${DESIGN_RTL_DIR}|'"${GOLDEN_DIR}"'/rtl/|') + +if [[ "${VERSION}" == "v1" ]]; then + var_revised_rtl=$(awk '{ if ($0 ~ "{DESIGN_RTL_DIR}" && $0 !~ "#" && $0 !~ "tracer" && $0 !~ "tb_wrapper" && $0 !~ "cv32e40p_wrapper" && $0 !~ "top") print $0 }' ${REVISED_DIR}/$FLIST | sed 's|${DESIGN_RTL_DIR}|'"${REVISED_DIR}"'/rtl/|') +else + var_revised_rtl=$(awk '{ if ($0 ~ "{DESIGN_RTL_DIR}" && $0 !~ "#" && $0 !~ "tracer" && $0 !~ "tb_wrapper") print $0 }' ${REVISED_DIR}/$FLIST | sed 's|${DESIGN_RTL_DIR}|'"${REVISED_DIR}"'/rtl/|') +fi + +print_log "Generating GOLDEN flist in path: ${GOLDEN_FLIST}" +echo $var_golden_rtl > ${GOLDEN_FLIST} +print_log "Generating REVISED flist in path: ${REVISED_FLIST}" +echo $var_revised_rtl > ${REVISED_FLIST} + +export report_dir=$(readlink -f $(dirname "${BASH_SOURCE[0]}"))/reports/${target_tool}/$(date +%Y-%m-%d-%Hh%Mm%Ss) + +if [[ -d ${report_dir} ]]; then + rm -rf ${report_dir} +fi +mkdir -p ${report_dir} + +export tcl_script=$(readlink -f $(dirname "${BASH_SOURCE[0]}"))/${target_tool}/${target_process}.tcl +export output_log=${report_dir}/output.${target_tool}-${target_process}.log +export summary_log=${report_dir}/summary.${target_tool}-${target_process}.log + +export expected_grep_exit_code=1 + +if [[ "${target_tool}" == "cadence" ]]; then + + if [[ "${target_process}" == "lec" ]]; then + lec -Dofile ${tcl_script} -TclMode -NoGUI -xl | tee ${output_log} + regex_string="Hierarchical compare : Equivalent" + elif [[ "${target_process}" == "sec" ]]; then + jg -sec -proj ${report_dir} -batch -tcl ${tcl_script} -define report_dir ${report_dir} | tee ${output_log} + regex_string="Overall SEC status[ ]+- Complete" + fi + +elif [[ "${target_tool}" == "synopsys" ]]; then + + if [[ "${target_process}" == "lec" ]]; then + fm_shell -work_path ${report_dir} -f ${tcl_script} | tee ${output_log} + regex_string="Verification SUCCEEDED" + elif [[ "${target_process}" == "sec" ]]; then + not_implemented ${target_tool} ${target_process} + fi + +elif [[ "${target_tool}" == "siemens" ]]; then + + if [[ "${target_process}" == "lec" ]]; then + not_implemented ${target_tool} ${target_process} + elif [[ "${target_process}" == "sec" ]]; then + make -C siemens/ run_sec_vl SPEC_FLIST=${GOLDEN_FLIST} IMPL_FLIST=${REVISED_FLIST} TOP_MODULE=${TOP_MODULE} SUMMARY_LOG=${summary_log} | tee ${output_log} + regex_string="^Fired" + expected_grep_exit_code=0 + fi + +fi + +if [[ ! -f ${output_log} || ! -f ${summary_log} ]]; then + print_log "Something went wrong during the process" + exit 1 +fi + +grep -Eq "${regex_string}" ${summary_log}; grep_exit_code=$? + +if [[ ${grep_exit_code} != ${expected_grep_exit_code} ]]; then + print_log "${target_process^^}: THE DESIGN IS EQUIVALENT" +else + print_log "${target_process^^}: THE DESIGN IS NOT EQUIVALENT" +fi + +exit ${exit_code} diff --git a/scripts/slec/siemens/Makefile b/scripts/slec/siemens/Makefile new file mode 100755 index 000000000..15e281f93 --- /dev/null +++ b/scripts/slec/siemens/Makefile @@ -0,0 +1,41 @@ +############################################################################## +# Copyright 2006-Mentor Graphics Corporation +# +# THIS SOFTWARE AND RELATED DOCUMENTATION +# ARE PROPRIETARY AND CONFIDENTIAL TO SIEMENS. +# © 2023 Siemens + +INSTALL := $(shell qverify -install_path) +VLIB = $(INSTALL)/modeltech/linux_x86_64/vlib +VMAP = $(INSTALL)/modeltech/linux_x86_64/vmap +VLOG = $(INSTALL)/modeltech/linux_x86_64/vlog +VCOM = $(INSTALL)/modeltech/linux_x86_64/vcom + +run_sec_vl: clean run_sec + +run_sec: + $(VLIB) work_ip_orig + $(VLIB) work_ip_mod + $(VMAP) work_spec work_ip_orig + $(VMAP) work_impl work_ip_mod + $(VLOG) -sv -f $(SPEC_FLIST) -work work_spec + $(VLOG) -sv -f $(IMPL_FLIST) -work work_impl + + qverify -c -od log -do " \ + onerror { exit 1 }; \ + slec configure -spec -d $(TOP_MODULE) -work work_spec; \ + slec configure -impl -d $(TOP_MODULE) -work work_impl; \ + slec compile; \ + slec verify -timeout 10m; \ + exit" + @cp log/slec_verify.log $(SUMMARY_LOG) + + +debug: + qverify log/slec.db + +clean: + qverify_clean + rm -rf log* work* *.rpt modelsim.ini .visualizer visualizer* + + diff --git a/scripts/slec/synopsys/lec.tcl b/scripts/slec/synopsys/lec.tcl new file mode 100644 index 000000000..e3c09e997 --- /dev/null +++ b/scripts/slec/synopsys/lec.tcl @@ -0,0 +1,64 @@ +# Copyright 2024 OpenHW Group and Dolphin Design +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +# +# Licensed under the Solderpad Hardware License v 2.1 (the “License”); +# you may not use this file except in compliance with the License, or, +# at your option, the Apache License version 2.0. +# You may obtain a copy of the License at +# +# https://solderpad.org/licenses/SHL-2.1/ +# +# Unless required by applicable law or agreed to in writing, any work +# distributed under the License is distributed on an “AS IS” BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +set synopsys_auto_setup true +set verification_failing_point_limit 0 + +set summary_log $::env(summary_log) +set top_module $::env(top_module) +set version $::env(version) +set pulp_cfg $::env(pulp_cfg) +set fpu_cfg $::env(fpu_cfg) +set zfinx_cfg $::env(zfinx_cfg) +set latency_cfg $::env(latency_cfg) + +set core_impl_name cv32e40p_core_COREV_PULP${pulp_cfg}_FPU${fpu_cfg}_FPU_ADDMUL_LAT${latency_cfg}_FPU_OTHERS_LAT${latency_cfg}_ZFINX${zfinx_cfg} + +if {"$version" == "v1"} { + set golden_parameter_list "PULP_XPULP = 0, FPU = 0, PULP_ZFINX = 0" + set core_ref_name cv32e40p_core_PULP_XPULP0_FPU0_PULP_ZFINX0 +} else { + set golden_parameter_list "COREV_PULP = $pulp_cfg, FPU = $fpu_cfg, ZFINX = $zfinx_cfg, FPU_ADDMUL_LAT = $latency_cfg, FPU_OTHERS_LAT = $latency_cfg" + set core_ref_name $core_impl_name +} + +read_sverilog -container r -libname WORK -12 -f golden.src +set_top r:/WORK/$top_module -parameter $golden_parameter_list + +read_sverilog -container i -libname WORK -12 -f revised.src +set_top i:/WORK/$top_module -parameter "COREV_PULP = $pulp_cfg, FPU = $fpu_cfg, ZFINX = $zfinx_cfg, FPU_ADDMUL_LAT = $latency_cfg, FPU_OTHERS_LAT = $latency_cfg" + +match > $summary_log.match.rpt + +if {"$top_module" == "cv32e40p_core"} { + set_dont_verify_point -type port r:/WORK/$core_ref_name/apu_req_o + set_dont_verify_point -type port r:/WORK/$core_ref_name/apu_operands_o* + set_dont_verify_point -type port r:/WORK/$core_ref_name/apu_op_o* + set_dont_verify_point -type port r:/WORK/$core_ref_name/apu_flags_o* + set_dont_verify_point -type port i:/WORK/$core_impl_name/apu_req_o + set_dont_verify_point -type port i:/WORK/$core_impl_name/apu_operands_o* + set_dont_verify_point -type port i:/WORK/$core_impl_name/apu_op_o* + set_dont_verify_point -type port i:/WORK/$core_impl_name/apu_flags_o* + set_dont_verify_point -type port i:/WORK/$core_impl_name/apu_busy_o +} + +verify > $summary_log + +report_passing_points > $summary_log.passing_points.rpt +report_aborted_points > $summary_log.aborted_points.rpt +report_failing_points > $summary_log.failing_points.rpt + +exit