diff --git a/docs/flow/dsl.md b/docs/flow/dsl.md
index d6e0e58..be6e6b3 100644
--- a/docs/flow/dsl.md
+++ b/docs/flow/dsl.md
@@ -1,28 +1,30 @@
 ### HCL
-- [HeteroCL](https://github.com/cornell-zhang/heterocl) (Cornell, UCLA), under [Apache License 2.0](https://github.com/cornell-zhang/heterocl/blob/master/LICENSE)
++ [HeteroCL](https://github.com/cornell-zhang/heterocl) (Cornell, UCLA), under [Apache License 2.0](https://github.com/cornell-zhang/heterocl/blob/master/LICENSE)
   - A Multi-Paradigm Programming Infrastructure for Software-Defined Reconfigurable Computing.
-- [Chisel](https://www.chisel-lang.org/) (Berkeley), under [BSD 3-Clause License](https://github.com/freechipsproject/chisel3/blob/master/src/LICENSE.txt)
++ [Chisel](https://www.chisel-lang.org/) (Berkeley), under [BSD 3-Clause License](https://github.com/freechipsproject/chisel3/blob/master/src/LICENSE.txt)
   - A hardware construction language that supports advanced hardware design using highly parameterized generators and layered domain-specific hardware languages.
-- [PyHCL](https://github.com/scutdig/PyChip-py-hcl) (SCUT), under [MIT License](https://github.com/scutdig/PyChip-py-hcl/blob/master/LICENSE)
++ [Genesis2](https://github.com/StanfordVLSI/Genesis2), under [BSD 2-Clause License](https://github.com/StanfordVLSI/Genesis2/blob/master/Genesis2Tools/LICENSE.txt)
+  - A design system and meta-programming language for automatically producing custom hardware.
++ [PyHCL](https://github.com/scutdig/PyChip-py-hcl) (SCUT), under [MIT License](https://github.com/scutdig/PyChip-py-hcl/blob/master/LICENSE)
   - PyHCL is a hardware construct language like Chisel but more lightweight and more relaxed to use.
-- [SpinalHDL](https://github.com/SpinalHDL/SpinalHDL), under [LGPL License and MIT License](https://github.com/SpinalHDL/SpinalHDL/blob/dev/LICENSE)
++ [SpinalHDL](https://github.com/SpinalHDL/SpinalHDL), under [LGPL License and MIT License](https://github.com/SpinalHDL/SpinalHDL/blob/dev/LICENSE)
   - A language to describe digital hardware.
-- [PyMTL3](https://github.com/pymtl/pymtl3) (Cornell), under [BSD 3-Clause License](https://github.com/pymtl/pymtl3/blob/master/LICENSE)
++ [PyMTL3](https://github.com/pymtl/pymtl3) (Cornell), under [BSD 3-Clause License](https://github.com/pymtl/pymtl3/blob/master/LICENSE)
   - PyMTL 3 (Mamba) is the latest version of PyMTL, an open-source Python-based hardware generation, simulation, and verification framework with multi-level hardware modeling support.
-- [PyGears](https://github.com/bogdanvuk/pygears) (University of Novi Sad), under [MIT License](https://github.com/bogdanvuk/pygears/blob/master/LICENSE)
++ [PyGears](https://github.com/bogdanvuk/pygears) (University of Novi Sad), under [MIT License](https://github.com/bogdanvuk/pygears/blob/master/LICENSE)
   - PyGears is a free framework that lets you design hardware using high-level Python constructs and compile it to synthesizable SystemVerilog or Verilog code.
-- [ActiveCore](https://github.com/AntonovAlexander/activecore) (ITMO)
++ [ActiveCore](https://github.com/AntonovAlexander/activecore) (ITMO)
   - A framework that demonstrates original hardware designing concept based on "Micro-Language IP" (MLIP) cores.
-- [Hardcaml](https://github.com/janestreet/hardcaml) (Jane Street)
++ [Hardcaml](https://github.com/janestreet/hardcaml) (Jane Street)
   - An OCaml library for designing hardware.
-- [Kiwi](https://www.cl.cam.ac.uk/~djg11/kiwi/) (Cambridge)
++ [Kiwi](https://www.cl.cam.ac.uk/~djg11/kiwi/) (Cambridge)
   - Aims to make reconfigurable computing technology like Field Programmable Gate Arrays (FPGAs) more accessible to mainstream programmers.
-- [Kratos](https://github.com/Kuree/kratos) (Stanford), under [BSD 2-Clause "Simplified" License](https://github.com/Kuree/kratos/blob/master/LICENSE)
++ [Kratos](https://github.com/Kuree/kratos) (Stanford), under [BSD 2-Clause "Simplified" License](https://github.com/Kuree/kratos/blob/master/LICENSE)
   - Kratos is a hardware design language written in C++/Python.
-- [ScalaHDL](https://github.com/lastland/ScalaHDL) (SJTU, Morgan Staneley)
++ [ScalaHDL](https://github.com/lastland/ScalaHDL) (SJTU, Morgan Staneley)
   - An open-source domain-specific language (DSL) that enables designers to describe algorithms using a multi-paradigm programming language, and generate the required
 Verilog code to implement such systems.
-- [VeriScala](https://github.com/VeriScala/VeriScala) (SJTU)
++ [VeriScala](https://github.com/VeriScala/VeriScala) (SJTU)
   - A new open-source Domain-Specific Language (DSL) based framework that supports highly abstracted object-oriented hardware defining, programmatical testing, and interactive on-chip debugging.
 
 ### IR