Perform a batch update

docs/flow/index.md

@@ -1,2 +1,2 @@
-本栏目将覆盖[ASIC流程](asic.md)、[FPGA流程](fpga.md)、[AMS流程](ams.md)、[标准格式](standard.md)、[DSL&IR](dsl.md)及[开发环境](ide.md)等流程工具。
+本栏目将覆盖[ASIC流程](asic.md)、[FPGA流程](fpga.md)、[AMS流程](ams.md)、[标准格式](standard.md)、[中间表示](ir.md)及[开发环境](ide.md)等流程工具。
 

docs/flow/ir.md

@@ -0,0 +1,27 @@
+### Intermediate Representation (IR)
+ - [FIRRTL](https://github.com/freechipsproject/firrtl) (Berkeley)
+   - An intermediate representation (IR) for digital circuits designed as a platform for writing circuit-level transformations.
+ - [LiveHD](https://github.com/masc-ucsc/livehd) (UCSC)
+   - An infrastructure designed for Live Hardware Development.
+   - Including Live Graph ([LGraph](https://github.com/masc-ucsc/livehd/blob/master/core/lgraph.hpp)), Language Neutral AST ([LNAST](https://github.com/masc-ucsc/livehd/blob/master/elab/lnast.hpp)), integrated 3rd-party tools, code generation, and "live" techniques.
++ [CIRCT](https://github.com/llvm/circt), under [Apache License](https://github.com/llvm/circt/blob/main/LICENSE)
+  - "CIRCT" stands for "Circuit IR Compilers and Tools".
+- [CoreIR](https://github.com/rdaly525/coreir)
+   - An LLVM-style hardware compiler with first class support for generators
+ - [LLHD](http://www.llhd.io/)
+   - An intermediate representation for digital circuit descriptions.
+   - Together with an accompanying simulator and SystemVerilog/VHDL compiler.
+ - [LLHDL](https://github.com/errordeveloper/llhdl) (archived)
+   - A logic synthesis and manipulation infrastructure for FPGAs.
+ - [netlistDB](https://github.com/HardwareIR/netlistDB)
+   - Intermediate format for digital hardware representation with graph database API.
+ - [nMigen](https://github.com/m-labs/nmigen)
+   - A refreshed Python toolbox for building complex digital hardware.
+ - [RTLIL](https://github.com/YosysHQ/yosys/blob/master/kernel/rtlil.h)
+   - Verilog AST like IR in Yosys.
+ - [spydrnet](https://byuccl.github.io/spydrnet/)
+   - A flexible framework for analyzing and transforming FPGA netlists.
+ - [fircpp](https://github.com/easysoc/fircpp)
+   - fircpp is a C++ Firrtl parser based on antlr4.
+ - [SDF3](http://www.es.ele.tue.nl/sdf3/) (Electronic Systems Group), under [GNU General Public License and the SDF3 Proprietary License](http://www.es.ele.tue.nl/sdf3/license/)
+   - Offers many SDFG transformation and analysis algorithms.

docs/sip/lib.md

@@ -0,0 +1,25 @@
+### Standard Cell Libraries
+- [DesignStart Physical IP](https://developer.arm.com/ip-products/designstart/physical-ip) (ARM)
+  - The most comprehensive physical IP with no upfront fees – for companies to produce commercial silicon or for universities to research
+- [Open-Cell](http://www.si2.org/open-cell-library/) (Si2)
+  - Silvaco's 15nm Open-Cell Library
+  - No charge for universities and Si2 members
+- [LibreCell](https://codeberg.org/tok/librecell), under [GNU General Public License v3.0](https://codeberg.org/tok/librecell/src/branch/master/librecell-common/LICENSE), [CERN Open Hardware Licence v2.0](https://codeberg.org/tok/librecell/src/branch/master/librecell-layout/LICENCE), and [GNU Affero General Public License v3.0](https://codeberg.org/tok/librecell/src/branch/master/librecell-lib/LICENSE)
+  - Aims to be a toolbox for automated synthesis of CMOS logic cells.
+
+### Hardware Functional Libraries
++ [FP-Gen](https://github.com/StanfordVLSI/FP-Gen) (Stanford), under [BSD 3-Clause "New" or "Revised" License](https://github.com/StanfordVLSI/FP-Gen/blob/master/LICENSE)
+  - A Floating Point Adder/Multiplier/Multiply-Accumulate generator and testbench.
++ [FloPoCo](http://flopoco.gforge.inria.fr/)
+  - A generator of arithmetic cores (Floating-Point Cores, but not only) for FPGAs (but not only).
++ [GenMul](https://github.com/amahzoon/genmul) (Univ. of Bremen)
+  - GenMul is a multiplier generator which outputs multiplier circuits in Verilog.
++ [muIR](https://github.com/sfu-arch/muir-lib) (SFU), under [BSD 3-Clause License](https://github.com/sfu-arch/muir-lib/blob/master/LICENSE)
+  - muIR is a library of hardware components for auto generating highly configurable parallel dataflow accelerator.
++ [HLSLibs](https://hlslibs.org/) (Mentor)
+  - A free and open set of libraries implemented in standard C++ for bit-accurate hardware and software design.
++ [MatchLib](https://github.com/NVlabs/matchlib) (NVIDIA)
+  - MatchLib is a SystemC/C++ library of commonly-used hardware functions and components that can be synthesized by most commercially-available HLS tools into RTL.
++ [HiFlipVX](https://github.com/TUD-ADS/HiFlipVX)
+  - Open Source High-Level Synthesis FPGA Library for Image Processing.
+

docs/sip/pdk.md

@@ -10,29 +10,6 @@
 + [FreePDK15_TFET](https://github.com/SJTU-YONGFU-RESEARCH-GRP/FreePDK15_TFET) (SJTU), under [GNU General Public License v3.0](https://github.com/SJTU-YONGFU-RESEARCH-GRP/FreePDK15_TFET/blob/main/LICENSE)
   - FreePDK15(TM) Predictive Process Design Kit with TFET devices
 
-### Standard Cell Libraries
-- [DesignStart Physical IP](https://developer.arm.com/ip-products/designstart/physical-ip) (ARM)
-  - The most comprehensive physical IP with no upfront fees – for companies to produce commercial silicon or for universities to research
-- [Open-Cell](http://www.si2.org/open-cell-library/) (Si2)
-  - Silvaco's 15nm Open-Cell Library
-  - No charge for universities and Si2 members
-- [LibreCell](https://codeberg.org/tok/librecell), under [GNU General Public License v3.0](https://codeberg.org/tok/librecell/src/branch/master/librecell-common/LICENSE), [CERN Open Hardware Licence v2.0](https://codeberg.org/tok/librecell/src/branch/master/librecell-layout/LICENCE), and [GNU Affero General Public License v3.0](https://codeberg.org/tok/librecell/src/branch/master/librecell-lib/LICENSE)
-  - Aims to be a toolbox for automated synthesis of CMOS logic cells.
-
-### Hardware Functional Libraries
-+ [FP-Gen](https://github.com/StanfordVLSI/FP-Gen) (Stanford), under [BSD 3-Clause "New" or "Revised" License](https://github.com/StanfordVLSI/FP-Gen/blob/master/LICENSE)
-  - A Floating Point Adder/Multiplier/Multiply-Accumulate generator and testbench.
-+ [FloPoCo](http://flopoco.gforge.inria.fr/)
-  - A generator of arithmetic cores (Floating-Point Cores, but not only) for FPGAs (but not only).
-+ [GenMul](https://github.com/amahzoon/genmul) (Univ. of Bremen)
-  - GenMul is a multiplier generator which outputs multiplier circuits in Verilog.
-+ [HLSLibs](https://hlslibs.org/) (Mentor)
-  - A free and open set of libraries implemented in standard C++ for bit-accurate hardware and software design.
-+ [MatchLib](https://github.com/NVlabs/matchlib) (NVIDIA)
-  - MatchLib is a SystemC/C++ library of commonly-used hardware functions and components that can be synthesized by most commercially-available HLS tools into RTL.
-+ [HiFlipVX](https://github.com/TUD-ADS/HiFlipVX)
-  - Open Source High-Level Synthesis FPGA Library for Image Processing.
-
 ### PDK for CNTFET
 - Variation-Aware [Nanosystem Design Kit (NDK)](https://nanohub.org/resources/22582) (Stanford)
   - A framework that quickly evaluates the impact of CNT variations on circuit delay and noise margin, and systematically explores the large space of CNT processing options to derive optimized CNT processing and CNFET circuit design guidelines.

docs/synthesis/behavior.md

@@ -18,15 +18,6 @@
 - [CAPH](https://github.com/jserot/caph) (INSA Rennes), under [Q Public License v1.0](https://github.com/jserot/caph/blob/master/LICENSE) and [GNU Library General Public License v2.0](https://github.com/jserot/caph/blob/master/LICENSE)
   - CAPH is a domain-specific  language for describing and implementing stream-processing applications on reconfigurable hardware, such as FPGAs.
 
-### Hardware Generation
-- [muIR](https://github.com/sfu-arch/muir-lib) (SFU), under [BSD 3-Clause License](https://github.com/sfu-arch/muir-lib/blob/master/LICENSE)
-  - muIR is a library of hardware components for auto generating highly configurable parallel dataflow accelerator.
-- [Bluespec Compiler](https://github.com/B-Lang-org/bsc) (Bluespec), most under [BSD-3-Clause License](https://github.com/B-Lang-org/bsc/blob/main/COPYING)
-  - Compiler, simulator, and tools for the Bluespec Hardware Description Language.
-- [CBG-BSV Toy Bluespec Compiler](https://www.cl.cam.ac.uk/~djg11//wwwhpr/toy-bluespec-compiler.html) (Cambridge)
-  - "For compiler writers like myself, the best way to learn a new language was to write a toy compiler for it."
-- other tools for [DSL/IR](../flow/dsl.md)
-
 ### HLS Passes
 - [EDS Scheduling](https://github.com/chhzh123/Entropy-directed-scheduling) (SYSU), under [MIT License](https://github.com/chhzh123/Entropy-directed-scheduling/blob/master/LICENSE)
   - The implementation of Entropy-Directed Scheduling (EDS) algorithm for FPGA high-level synthesis (HLS).

docs/flow/dsl.md → docs/synthesis/hcl.md

@@ -1,16 +1,22 @@
-### HCL
+### Hardware Construction Language (HCL)
 + [HeteroCL](https://github.com/cornell-zhang/heterocl) (Cornell, UCLA), under [Apache License 2.0](https://github.com/cornell-zhang/heterocl/blob/master/LICENSE)
   - A Multi-Paradigm Programming Infrastructure for Software-Defined Reconfigurable Computing.
++ [BSV/BH](https://github.com/BSVLang/Main) (Bluespec, Sandburst, MIT), under [MIT License](https://github.com/BSVLang/Main/blob/master/LICENSE)
+  - Bluespec SystemVerilog (BSV) and Bluespec Haskell (BH or Bluespec Classic), a high-level hardware description language.
+  - [Bluespec Compiler](https://github.com/B-Lang-org/bsc) (Bluespec), most under [BSD-3-Clause License](https://github.com/B-Lang-org/bsc/blob/main/COPYING)
+    * Compiler, simulator, and tools for the Bluespec Hardware Description Language.
+  - [CBG-BSV Toy Bluespec Compiler](https://www.cl.cam.ac.uk/~djg11//wwwhpr/toy-bluespec-compiler.html) (Cambridge)
+    * "For compiler writers like myself, the best way to learn a new language was to write a toy compiler for it."
 + [Chisel](https://www.chisel-lang.org/) (Berkeley), under [BSD 3-Clause License](https://github.com/freechipsproject/chisel3/blob/master/src/LICENSE.txt)
   - A hardware construction language that supports advanced hardware design using highly parameterized generators and layered domain-specific hardware languages.
-+ [Genesis2](https://github.com/StanfordVLSI/Genesis2), under [BSD 2-Clause License](https://github.com/StanfordVLSI/Genesis2/blob/master/Genesis2Tools/LICENSE.txt)
-  - A design system and meta-programming language for automatically producing custom hardware.
-+ [PyHCL](https://github.com/scutdig/PyChip-py-hcl) (SCUT), under [MIT License](https://github.com/scutdig/PyChip-py-hcl/blob/master/LICENSE)
-  - PyHCL is a hardware construct language like Chisel but more lightweight and more relaxed to use.
 + [SpinalHDL](https://github.com/SpinalHDL/SpinalHDL), under [LGPL License and MIT License](https://github.com/SpinalHDL/SpinalHDL/blob/dev/LICENSE)
   - A language to describe digital hardware.
 + [PyMTL3](https://github.com/pymtl/pymtl3) (Cornell), under [BSD 3-Clause License](https://github.com/pymtl/pymtl3/blob/master/LICENSE)
   - PyMTL 3 (Mamba) is the latest version of PyMTL, an open-source Python-based hardware generation, simulation, and verification framework with multi-level hardware modeling support.
++ [Genesis2](https://github.com/StanfordVLSI/Genesis2), under [BSD 2-Clause License](https://github.com/StanfordVLSI/Genesis2/blob/master/Genesis2Tools/LICENSE.txt)
+  - A design system and meta-programming language for automatically producing custom hardware.
++ [PyHCL](https://github.com/scutdig/PyChip-py-hcl) (SCUT), under [MIT License](https://github.com/scutdig/PyChip-py-hcl/blob/master/LICENSE)
+  - PyHCL is a hardware construct language like Chisel but more lightweight and more relaxed to use.
 + [PyGears](https://github.com/bogdanvuk/pygears) (University of Novi Sad), under [MIT License](https://github.com/bogdanvuk/pygears/blob/master/LICENSE)
   - PyGears is a free framework that lets you design hardware using high-level Python constructs and compile it to synthesizable SystemVerilog or Verilog code.
 + [ActiveCore](https://github.com/AntonovAlexander/activecore) (ITMO)
@@ -27,30 +33,4 @@ Verilog code to implement such systems.
 + [VeriScala](https://github.com/VeriScala/VeriScala) (SJTU)
   - A new open-source Domain-Specific Language (DSL) based framework that supports highly abstracted object-oriented hardware defining, programmatical testing, and interactive on-chip debugging.
 
-### IR
- - [FIRRTL](https://github.com/freechipsproject/firrtl) (Berkeley)
-   - An intermediate representation (IR) for digital circuits designed as a platform for writing circuit-level transformations.
- - [LiveHD](https://github.com/masc-ucsc/livehd) (UCSC)
-   - An infrastructure designed for Live Hardware Development.
-   - Including Live Graph ([LGraph](https://github.com/masc-ucsc/livehd/blob/master/core/lgraph.hpp)), Language Neutral AST ([LNAST](https://github.com/masc-ucsc/livehd/blob/master/elab/lnast.hpp)), integrated 3rd-party tools, code generation, and "live" techniques.
-+ [CIRCT](https://github.com/llvm/circt), under [Apache License](https://github.com/llvm/circt/blob/main/LICENSE)
-  - "CIRCT" stands for "Circuit IR Compilers and Tools".
-- [CoreIR](https://github.com/rdaly525/coreir)
-   - An LLVM-style hardware compiler with first class support for generators
- - [LLHD](http://www.llhd.io/)
-   - An intermediate representation for digital circuit descriptions.
-   - Together with an accompanying simulator and SystemVerilog/VHDL compiler.
- - [LLHDL](https://github.com/errordeveloper/llhdl) (archived)
-   - A logic synthesis and manipulation infrastructure for FPGAs.
- - [netlistDB](https://github.com/HardwareIR/netlistDB)
-   - Intermediate format for digital hardware representation with graph database API.
- - [nMigen](https://github.com/m-labs/nmigen)
-   - A refreshed Python toolbox for building complex digital hardware.
- - [RTLIL](https://github.com/YosysHQ/yosys/blob/master/kernel/rtlil.h)
-   - Verilog AST like IR in Yosys.
- - [spydrnet](https://byuccl.github.io/spydrnet/)
-   - A flexible framework for analyzing and transforming FPGA netlists.
- - [fircpp](https://github.com/easysoc/fircpp)
-   - fircpp is a C++ Firrtl parser based on antlr4.
- - [SDF3](http://www.es.ele.tue.nl/sdf3/) (Electronic Systems Group), under [GNU General Public License and the SDF3 Proprietary License](http://www.es.ele.tue.nl/sdf3/license/)
-   - Offers many SDFG transformation and analysis algorithms.
+

docs/synthesis/index.md

@@ -1,2 +1,2 @@
-本栏目将覆盖[高层综合](behavior.md)、[逻辑综合](logic.md)、[布局器](place.md)、[电网综合](power.md)、[时钟综合](clock.md)、[物理优化](opt.md)、[布线器](route.md)、以及[版图综合](layout.md)等设计自动综合工具。
+本栏目将覆盖[高层综合](behavior.md)、[硬件构建](hcl.md)、[逻辑综合](logic.md)、[布局器](place.md)、[电网综合](power.md)、[时钟综合](clock.md)、[物理优化](opt.md)、[布线器](route.md)、以及[版图综合](layout.md)等设计自动综合工具。
 

mkdocs.yml

@@ -11,7 +11,7 @@ repo_url: 'https://github.com/pkuzjx/EDA-wiki'
 edit_uri: 'blob/master/docs/'
 
 # Copyright
-copyright: 'ICP备案号：<a href="http://www.beian.gov.cn">京ICP备19041147号</a> <br> Copyright &copy; 2019 - 2020 EDA Wiki Team'
+copyright: 'ICP备案号：<a href="http://www.beian.gov.cn">京ICP备19041147号</a> <br> Copyright &copy; 2019 - 2021 EDA Wiki Team'
 google_analytics:
   - ''
   - 'auto'
@@ -31,12 +31,13 @@ nav:
     - FPGA流程: flow/fpga.md
     - AMS流程: flow/ams.md
     - 标准格式: flow/standard.md
-    - DSL & IR: flow/dsl.md
+    - 中间表示: flow/ir.md
     - 开发环境: flow/ide.md
 
   - 设计综合:
     - 设计综合简介: synthesis/index.md
     - 高层综合: synthesis/behavior.md
+    - 硬件构建: synthesis/hcl.md
     - 逻辑综合: synthesis/logic.md
     - 布局器: synthesis/place.md
     - 电网综合: synthesis/power.md
@@ -61,7 +62,8 @@ nav:
 
   - 硅知产:
     - 硅知产简介: sip/index.md
-    - PDK与单元库: sip/pdk.md
+    - 工艺设计套件: sip/pdk.md
+    - 单元库: sip/lib.md
     - 存储单元: sip/mem.md
     - 通用计算: sip/general.md
     - 专用计算: sip/special.md

requirements.txt

@@ -1,4 +1,4 @@
 mkdocs>=1
-mkdocs-material
+mkdocs-material<4
 pymdown-extensions
 mdx_truly_sane_lists