From 14e1677736ae10d1689401a69e6f162df29afdbe Mon Sep 17 00:00:00 2001 From: Michael Rogenmoser Date: Wed, 23 Jul 2025 14:42:20 +0200 Subject: [PATCH 1/3] Add make targets to run simulation with VCS --- Makefile | 20 +++++++++++++++++++- README.md | 4 ++++ rtl/tb_croc_soc.sv | 2 +- rtl/user_pkg.sv | 2 +- vcs/.gitignore | 11 +++++++++++ 5 files changed, 36 insertions(+), 3 deletions(-) create mode 100644 vcs/.gitignore diff --git a/Makefile b/Makefile index 1d092128..427cf1d3 100644 --- a/Makefile +++ b/Makefile @@ -13,6 +13,8 @@ YOSYS ?= yosys OPENROAD ?= openroad KLAYOUT ?= klayout VSIM ?= vsim +VLOGAN ?= vlogan +VCS ?= vcs REGGEN ?= $(PYTHON3) $(shell $(BENDER) path register_interface)/vendor/lowrisc_opentitan/util/regtool.py # Directories @@ -108,7 +110,23 @@ verilator/obj_dir/Vtb_croc_soc: verilator/croc.f $(SW_HEX) verilator: verilator/obj_dir/Vtb_croc_soc cd verilator; obj_dir/Vtb_croc_soc +binary="$(realpath $(SW_HEX))" -.PHONY: verilator vsim vsim-yosys +# VCS +VCS_SCRIPT_ARGS = -assert svaext +v2k -kdb -override_timescale=1ns/10ps -debug_access+all +VCS_COMPILE_ARGS = -kdb -lca -sverilog -full64 -j8 -l compile.log +vcs+fsdbon -debug_access+all +lint=TFIPC-L +lint=PCWM +warn=noCWUC +warn=noUII-L -override_timescale=1ns/10ps +vcs/compile_rtl.sh: Bender.lock Bender.yml + $(BENDER) script vcs -t rtl -t vcs -t simulation -t verilator -DSYNTHESIS -DSIMULATION --vlog-arg="$(VCS_SCRIPT_ARGS)" --vlogan-bin="$(VLOGAN)" > $@ + chmod +x $@ + +vcs/%.sim: vcs/compile_rtl.sh + rm -rf vcs/work + cd vcs; ./compile_rtl.sh + cd vcs; $(VCS) $(VCS_COMPILE_ARGS) -o $*.sim $* + +## Simulate RTL using VCS +vcs: vcs/tb_croc_soc.sim $(SW_HEX) + cd vcs; ./tb_croc_soc.sim +fsdb+all=on +binary="$(realpath $(SW_HEX))" -l transcript.log + +.PHONY: verilator vsim vsim-yosys vcs #################### diff --git a/README.md b/README.md index 61104a8a..6b945ece 100644 --- a/README.md +++ b/README.md @@ -175,6 +175,10 @@ If you have Questasim/Modelsim, you can also run: make vsim ``` +If you have VCS, you can also run: +```sh +make vcs +``` The most important make targets are documented, you can list them with: ```sh diff --git a/rtl/tb_croc_soc.sv b/rtl/tb_croc_soc.sv index 71782388..479f13c6 100644 --- a/rtl/tb_croc_soc.sv +++ b/rtl/tb_croc_soc.sv @@ -377,7 +377,7 @@ module tb_croc_soc #( if (uart_read_buf.size() > 0) begin automatic string uart_str = ""; foreach (uart_read_buf[i]) begin - uart_str = {uart_str, uart_read_buf[i]}; + uart_str = {uart_str, string'(uart_read_buf[i])}; end $display("@%t | [UART] %s", $time, uart_str); diff --git a/rtl/user_pkg.sv b/rtl/user_pkg.sv index 8d8d10f1..a59f3461 100644 --- a/rtl/user_pkg.sv +++ b/rtl/user_pkg.sv @@ -26,7 +26,7 @@ package user_pkg; localparam bit [31:0] UserRomAddrOffset = croc_pkg::UserBaseAddr; // 32'h2000_0000; localparam bit [31:0] UserRomAddrRange = 32'h0000_1000; // every subordinate has at least 4KB - localparam int unsigned NumDemuxSbrRules = NumUserDomainSubordinates; // number of address rules in the decoder + localparam int unsigned NumDemuxSbrRules = NumUserDomainSubordinates > 0 ? NumUserDomainSubordinates : 1; // number of address rules in the decoder localparam int unsigned NumDemuxSbr = NumDemuxSbrRules + 1; // additional OBI error, used for signal arrays // Enum for bus indices diff --git a/vcs/.gitignore b/vcs/.gitignore new file mode 100644 index 00000000..64fe0bd5 --- /dev/null +++ b/vcs/.gitignore @@ -0,0 +1,11 @@ +AN.DB +work.lib++ +tb_croc_soc.sim* +vc_hdrs.h +csrc +compile_rtl.sh +ucli.key +croc.fst +compile.log +novas* +transcript.log From 14f4f021bc19479137ed63ccb281163392d12da8 Mon Sep 17 00:00:00 2001 From: Michael Rogenmoser Date: Wed, 23 Jul 2025 16:13:54 +0200 Subject: [PATCH 2/3] Add VCS yosys flow --- Makefile | 17 ++++++++++++++--- vcs/.gitignore | 5 +++-- vcs/compile_tech.sh | 14 ++++++++++++++ vsim/compile_tech.tcl | 5 ++--- 4 files changed, 33 insertions(+), 8 deletions(-) create mode 100755 vcs/compile_tech.sh diff --git a/Makefile b/Makefile index 427cf1d3..c291615c 100644 --- a/Makefile +++ b/Makefile @@ -117,15 +117,26 @@ vcs/compile_rtl.sh: Bender.lock Bender.yml $(BENDER) script vcs -t rtl -t vcs -t simulation -t verilator -DSYNTHESIS -DSIMULATION --vlog-arg="$(VCS_SCRIPT_ARGS)" --vlogan-bin="$(VLOGAN)" > $@ chmod +x $@ -vcs/%.sim: vcs/compile_rtl.sh - rm -rf vcs/work +vcs/compile_netlist.sh: Bender.lock Bender.yml + $(BENDER) script vcs -t ihp13 -t vcs -t simulation -t verilator -t netlist_yosys -DSYNTHESIS -DSIMULATION --vlog-arg="$(VCS_SCRIPT_ARGS)" --vlogan-bin="$(VLOGAN)" > $@ + cat vcs/compile_tech.sh >> $@ + chmod +x $@ + +vcs/tb_croc_soc.sim: vcs/compile_rtl.sh cd vcs; ./compile_rtl.sh - cd vcs; $(VCS) $(VCS_COMPILE_ARGS) -o $*.sim $* + cd vcs; $(VCS) $(VCS_COMPILE_ARGS) -o tb_croc_soc.sim tb_croc_soc + +vcs/tb_croc_soc_yosys.sim: vcs/compile_netlist.sh yosys/out/croc_chip_yosys_debug.v + cd vcs; ./compile_netlist.sh + cd vcs; $(VCS) $(VCS_COMPILE_ARGS) -o tb_croc_soc_yosys.sim tb_croc_soc ## Simulate RTL using VCS vcs: vcs/tb_croc_soc.sim $(SW_HEX) cd vcs; ./tb_croc_soc.sim +fsdb+all=on +binary="$(realpath $(SW_HEX))" -l transcript.log +vcs-yosys: vcs/tb_croc_soc_yosys.sim $(SW_HEX) + cd vcs; ./tb_croc_soc_yosys.sim +fsdb+all=on +binary="$(realpath $(SW_HEX))" -l transcript.log + .PHONY: verilator vsim vsim-yosys vcs diff --git a/vcs/.gitignore b/vcs/.gitignore index 64fe0bd5..9d596de4 100644 --- a/vcs/.gitignore +++ b/vcs/.gitignore @@ -1,11 +1,12 @@ AN.DB work.lib++ -tb_croc_soc.sim* +tb_croc_soc* vc_hdrs.h csrc -compile_rtl.sh ucli.key croc.fst +compile_rtl.sh +compile_netlist.sh compile.log novas* transcript.log diff --git a/vcs/compile_tech.sh b/vcs/compile_tech.sh new file mode 100755 index 00000000..7f50a04a --- /dev/null +++ b/vcs/compile_tech.sh @@ -0,0 +1,14 @@ +$VLOGAN -sverilog \ + -full64 \ + -assert svaext +v2k -kdb -override_timescale=1ns/10ps -debug_access+all \ + "+define+FUNCTIONAL" \ + "$ROOT/ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_stdcell/verilog/sg13g2_stdcell.v" \ + "$ROOT/ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_core_behavioral_bm_bist.v" \ + "$ROOT/ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_64x64_c2_bm_bist.v" \ + "$ROOT/ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_256x64_c2_bm_bist.v" \ + "$ROOT/ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_512x64_c2_bm_bist.v" \ + "$ROOT/ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_1024x64_c2_bm_bist.v" \ + "$ROOT/ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_2048x64_c2_bm_bist.v" \ + "$ROOT/ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_256x48_c2_bm_bist.v" \ + "$ROOT/ihp13/tc_sram_impl.sv" \ + "$ROOT/ihp13/tc_clk.sv" diff --git a/vsim/compile_tech.tcl b/vsim/compile_tech.tcl index 01e865b3..0ab1a270 100644 --- a/vsim/compile_tech.tcl +++ b/vsim/compile_tech.tcl @@ -15,7 +15,6 @@ if {[catch { vlog -incr -sv \ "$ROOT/ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_1024x64_c2_bm_bist.v" \ "$ROOT/ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_2048x64_c2_bm_bist.v" \ "$ROOT/ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_256x48_c2_bm_bist.v" \ - "$ROOT/ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_256x48_c2_bm_bist.v" \ - "$ROOT/ihp13/tc_sram.sv" \ - "$ROOT/ihp13/tc_clk.s_implv" \ + "$ROOT/ihp13/tc_sram_impl.sv" \ + "$ROOT/ihp13/tc_clk.sv" \ }]} {return 1} From f66e251cb4ce274edf44c92abda64ee6af4df969 Mon Sep 17 00:00:00 2001 From: Michael Rogenmoser Date: Wed, 23 Jul 2025 16:33:44 +0200 Subject: [PATCH 3/3] Add VCS openroad flow --- Bender.yml | 13 +++++++++---- Makefile | 20 ++++++++++++++++---- vcs/.gitignore | 2 +- 3 files changed, 26 insertions(+), 9 deletions(-) diff --git a/Bender.yml b/Bender.yml index 97468f09..41bafeff 100644 --- a/Bender.yml +++ b/Bender.yml @@ -35,7 +35,7 @@ sources: # add your design files containing anything but modules (packages) here # RTL - - target: not(netlist_yosys) + - target: not(any(netlist_yosys, netlist_openroad)) files: # Level 1 - rtl/core_wrap.sv @@ -49,16 +49,21 @@ sources: # Level 3 - rtl/croc_soc.sv - - target: not(fpga) + - target: not(any(fpga, netlist_yosys, netlist_openroad)) files: # Level 0 - rtl/croc_chip.sv - # netlist for simulation + # yosys netlist for simulation - target: netlist_yosys files: - yosys/out/croc_chip_yosys_debug.v + # openroad netlist for simulation + - target: netlist_openroad + files: + - openroad/out/croc.v + - target: any(simulation, verilator) files: - rtl/tb_croc_soc.sv @@ -187,4 +192,4 @@ vendor_package: - { from: 'rtl/', to: '', patch_dir: 'rtl/' } - { from: 'README.md', to: 'README.md', patch_dir: '' } - { from: 'doc/03_reference/images/blockdiagram.svg', to: 'blockdiagram.svg', patch_dir: '' } - - { from: 'vendor/lowrisc_ip/ip/prim/rtl/', to: 'include/lowrisc_prim/', patch_dir: 'lowrisc_prim/' } \ No newline at end of file + - { from: 'vendor/lowrisc_ip/ip/prim/rtl/', to: 'include/lowrisc_prim/', patch_dir: 'lowrisc_prim/' } diff --git a/Makefile b/Makefile index c291615c..51d562d7 100644 --- a/Makefile +++ b/Makefile @@ -117,19 +117,28 @@ vcs/compile_rtl.sh: Bender.lock Bender.yml $(BENDER) script vcs -t rtl -t vcs -t simulation -t verilator -DSYNTHESIS -DSIMULATION --vlog-arg="$(VCS_SCRIPT_ARGS)" --vlogan-bin="$(VLOGAN)" > $@ chmod +x $@ -vcs/compile_netlist.sh: Bender.lock Bender.yml +vcs/compile_netlist_yosys.sh: Bender.lock Bender.yml $(BENDER) script vcs -t ihp13 -t vcs -t simulation -t verilator -t netlist_yosys -DSYNTHESIS -DSIMULATION --vlog-arg="$(VCS_SCRIPT_ARGS)" --vlogan-bin="$(VLOGAN)" > $@ cat vcs/compile_tech.sh >> $@ chmod +x $@ +vcs/compile_netlist_openroad.sh: Bender.lock Bender.yml + $(BENDER) script vcs -t ihp13 -t vcs -t simulation -t verilator -t netlist_openroad -DSYNTHESIS -DSIMULATION --vlog-arg="$(VCS_SCRIPT_ARGS)" --vlogan-bin="$(VLOGAN)" > $@ + cat vcs/compile_tech.sh >> $@ + chmod +x $@ + vcs/tb_croc_soc.sim: vcs/compile_rtl.sh cd vcs; ./compile_rtl.sh cd vcs; $(VCS) $(VCS_COMPILE_ARGS) -o tb_croc_soc.sim tb_croc_soc -vcs/tb_croc_soc_yosys.sim: vcs/compile_netlist.sh yosys/out/croc_chip_yosys_debug.v - cd vcs; ./compile_netlist.sh +vcs/tb_croc_soc_yosys.sim: vcs/compile_netlist_yosys.sh yosys/out/croc_chip_yosys_debug.v + cd vcs; ./compile_netlist_yosys.sh cd vcs; $(VCS) $(VCS_COMPILE_ARGS) -o tb_croc_soc_yosys.sim tb_croc_soc +vcs/tb_croc_soc_openroad.sim: vcs/compile_netlist_openroad.sh openroad/out/croc.v + cd vcs; ./compile_netlist_openroad.sh + cd vcs; $(VCS) $(VCS_COMPILE_ARGS) -o tb_croc_soc_openroad.sim tb_croc_soc + ## Simulate RTL using VCS vcs: vcs/tb_croc_soc.sim $(SW_HEX) cd vcs; ./tb_croc_soc.sim +fsdb+all=on +binary="$(realpath $(SW_HEX))" -l transcript.log @@ -137,7 +146,10 @@ vcs: vcs/tb_croc_soc.sim $(SW_HEX) vcs-yosys: vcs/tb_croc_soc_yosys.sim $(SW_HEX) cd vcs; ./tb_croc_soc_yosys.sim +fsdb+all=on +binary="$(realpath $(SW_HEX))" -l transcript.log -.PHONY: verilator vsim vsim-yosys vcs +vcs-openroad: vcs/tb_croc_soc_openroad.sim $(SW_HEX) + cd vcs; ./tb_croc_soc_openroad.sim +fsdb+all=on +binary="$(realpath $(SW_HEX))" -l transcript.log + +.PHONY: verilator vsim vsim-yosys vcs vcs-yosys vcs-openroad #################### diff --git a/vcs/.gitignore b/vcs/.gitignore index 9d596de4..ded2ecc6 100644 --- a/vcs/.gitignore +++ b/vcs/.gitignore @@ -6,7 +6,7 @@ csrc ucli.key croc.fst compile_rtl.sh -compile_netlist.sh +compile_netlist* compile.log novas* transcript.log