diff --git a/latch_scm/register_file_1r_1w.sv b/latch_scm/register_file_1r_1w.sv
index f6247e1..07a5fcd 100644
--- a/latch_scm/register_file_1r_1w.sv
+++ b/latch_scm/register_file_1r_1w.sv
@@ -57,7 +57,6 @@ module register_file_1r_1w
 
     // Read address register, located at the input of the address decoder
     logic [ADDR_WIDTH-1:0]                        RAddrRegxDP; 
-    logic [NUM_WORDS-1:0]                         RAddrOneHotxD;
 
 
     logic [DATA_WIDTH-1:0]                        MemContentxDP[NUM_WORDS];
@@ -98,11 +97,6 @@ module register_file_1r_1w
     //-----------------------------------------------------------------------------
     //-- READ : Read address decoder RAD
     //-----------------------------------------------------------------------------  
-    always_comb
-    begin : p_RAD
-        RAddrOneHotxD = '0;
-        RAddrOneHotxD[RAddrRegxDP] = 1'b1;
-    end
     assign ReadData = MemContentxDP[RAddrRegxDP];
 
 
diff --git a/latch_scm/register_file_1r_1w_all.sv b/latch_scm/register_file_1r_1w_all.sv
index 9e5b568..3dd7d09 100644
--- a/latch_scm/register_file_1r_1w_all.sv
+++ b/latch_scm/register_file_1r_1w_all.sv
@@ -36,7 +36,6 @@ module register_file_1r_1w_all
 
    // Read address register, located at the input of the address decoder
    logic [ADDR_WIDTH-1:0]                       RAddrRegxDP;
-   logic [NUM_WORDS-1:0]                        RAddrOneHotxD;
 
    logic [NUM_BYTE-1:0][7:0]                    MemContentxDP[NUM_WORDS];
 
@@ -77,11 +76,6 @@ module register_file_1r_1w_all
    //-----------------------------------------------------------------------------
    //-- READ : Read address decoder RAD
    //-----------------------------------------------------------------------------
-   always_comb
-     begin : p_RAD
-        RAddrOneHotxD = '0;
-        RAddrOneHotxD[RAddrRegxDP] = 1'b1;
-     end
    assign ReadData = MemContentxDP[RAddrRegxDP];
 
 
diff --git a/latch_scm/register_file_1r_1w_be.sv b/latch_scm/register_file_1r_1w_be.sv
index e3b2d1b..8bac512 100644
--- a/latch_scm/register_file_1r_1w_be.sv
+++ b/latch_scm/register_file_1r_1w_be.sv
@@ -33,7 +33,6 @@ module register_file_1r_1w_be
 
     // Read address register, located at the input of the address decoder
     logic [ADDR_WIDTH-1:0]                         RAddrRegxDP;
-    logic [NUM_WORDS-1:0]                          RAddrOneHotxD;
 
     logic [NUM_BYTE-1:0][7:0]                      MemContentxDP[NUM_WORDS];
 
@@ -74,11 +73,6 @@ module register_file_1r_1w_be
     //-----------------------------------------------------------------------------
     //-- READ : Read address decoder RAD
     //-----------------------------------------------------------------------------  
-    always_comb
-    begin : p_RAD
-      RAddrOneHotxD = '0;
-      RAddrOneHotxD[RAddrRegxDP] = 1'b1;
-    end
     assign ReadData = MemContentxDP[RAddrRegxDP];