Improve FP6-LLM 2+4bit weight splitting + user API #279
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Address #208
2+4bit weight splitting
Port https://github.com/pytorch/ao/blob/4ca3985be603e6496da7ec57adf1942c8b32a78e/torchao/csrc/fp6_llm/weight_prepacking.cpp to pure PyTorch.
FP16 weight, (8192, 8192). Ryzen 5600, 4070Ti SUPER
Note:
original 2+4bit splitting
only works on CPU. Thus, for the 2nd last row, FP16->FP6 is done on GPU, but 2+4bit splitting is done on CPU.User API
I opt for custom linear module instead of tensor subclass mainly because it's easier to implement.
Note:
Fp6LlmLinear
will cast input to FP16 and cast output to original dtype.