From cec6fa988eb165a1806c027da5cf0a1286691e10 Mon Sep 17 00:00:00 2001 From: Mariappan Ramasamy <947300+Mariappan@users.noreply.github.com> Date: Tue, 8 Mar 2022 18:56:22 +0800 Subject: [PATCH 01/20] Add STeMCell controller board config --- builddefs/build_keyboard.mk | 18 + builddefs/common_features.mk | 1 - lib/chibios | 2 +- lib/chibios-contrib | 2 +- .../chibios/boards/STEMCELL/board/board.c | 266 ++++ .../chibios/boards/STEMCELL/board/board.h | 1365 +++++++++++++++++ .../chibios/boards/STEMCELL/board/board.mk | 9 + .../chibios/boards/STEMCELL/configs/board.h | 20 + .../boards/STEMCELL/configs/bootloader_defs.h | 5 + .../chibios/boards/STEMCELL/configs/chconf.h | 6 + .../chibios/boards/STEMCELL/configs/config.h | 25 + .../chibios/boards/STEMCELL/configs/halconf.h | 27 + .../chibios/boards/STEMCELL/configs/mcuconf.h | 244 +++ .../boards/STEMCELL/convert_to_stemcell.mk | 12 + .../boards/STEMCELL/ld/STEMCELL_tinyuf2.ld | 88 ++ .../boards/STEMCELL/ld/STM32F401xC_tinyuf2.ld | 88 ++ platforms/chibios/pin_defs.h | 57 + 17 files changed, 2232 insertions(+), 3 deletions(-) create mode 100644 platforms/chibios/boards/STEMCELL/board/board.c create mode 100644 platforms/chibios/boards/STEMCELL/board/board.h create mode 100644 platforms/chibios/boards/STEMCELL/board/board.mk create mode 100644 platforms/chibios/boards/STEMCELL/configs/board.h create mode 100644 platforms/chibios/boards/STEMCELL/configs/bootloader_defs.h create mode 100644 platforms/chibios/boards/STEMCELL/configs/chconf.h create mode 100644 platforms/chibios/boards/STEMCELL/configs/config.h create mode 100644 platforms/chibios/boards/STEMCELL/configs/halconf.h create mode 100644 platforms/chibios/boards/STEMCELL/configs/mcuconf.h create mode 100644 platforms/chibios/boards/STEMCELL/convert_to_stemcell.mk create mode 100644 platforms/chibios/boards/STEMCELL/ld/STEMCELL_tinyuf2.ld create mode 100644 platforms/chibios/boards/STEMCELL/ld/STM32F401xC_tinyuf2.ld diff --git a/builddefs/build_keyboard.mk b/builddefs/build_keyboard.mk index d5efcb4193a1..32aa277446b3 100644 --- a/builddefs/build_keyboard.mk +++ b/builddefs/build_keyboard.mk @@ -176,6 +176,24 @@ ifeq ($(strip $(CONVERT_TO_PROTON_C)), yes) include platforms/chibios/boards/QMK_PROTON_C/convert_to_proton_c.mk endif +ifeq ($(strip $(STMC)), yes) + CONVERT_TO_STEMCELL=yes +endif + +ifeq ($(strip $(STMC_US)), yes) + CONVERT_TO_STEMCELL_UART_SWAP=yes + OPT_DEFS += -DCONVERT_TO_STEMCELL_UART_SWAP +endif + +ifeq ($(strip $(STMC_IS)), yes) + CONVERT_TO_STEMCELL_I2C_SWAP=yes + OPT_DEFS += -DCONVERT_TO_STEMCELL_I2C_SWAP +endif + +ifeq ($(strip $(CONVERT_TO_STEMCELL)), yes) + include platforms/chibios/boards/STEMCELL/convert_to_stemcell.mk +endif + include $(BUILDDEFS_PATH)/mcu_selection.mk # Find all the C source files to be compiled in subfolders. diff --git a/builddefs/common_features.mk b/builddefs/common_features.mk index 08d186d656c7..66f416b5f137 100644 --- a/builddefs/common_features.mk +++ b/builddefs/common_features.mk @@ -184,7 +184,6 @@ else # Automatically provided by avr-libc, nothing required else ifeq ($(PLATFORM),CHIBIOS) ifneq ($(filter STM32F3xx_% STM32F1xx_% %_STM32F401xC %_STM32F401xE %_STM32F405xG %_STM32F411xE %_STM32F072xB %_STM32F042x6 %_GD32VF103xB %_GD32VF103x8, $(MCU_SERIES)_$(MCU_LDSCRIPT)),) - # Emulated EEPROM OPT_DEFS += -DEEPROM_DRIVER -DEEPROM_STM32_FLASH_EMULATED COMMON_VPATH += $(DRIVER_PATH)/eeprom SRC += eeprom_driver.c diff --git a/lib/chibios b/lib/chibios index 257302333c31..d7b9d1c87f72 160000 --- a/lib/chibios +++ b/lib/chibios @@ -1 +1 @@ -Subproject commit 257302333c31f1f710800c2b97acf3550de043e1 +Subproject commit d7b9d1c87f724bd7c8cd1486d6d0dc3ba52e0d52 diff --git a/lib/chibios-contrib b/lib/chibios-contrib index ff1c6ec90cfc..d1c2126d1cd8 160000 --- a/lib/chibios-contrib +++ b/lib/chibios-contrib @@ -1 +1 @@ -Subproject commit ff1c6ec90cfc250d81e6f29a0d60a4faf2afb46d +Subproject commit d1c2126d1cd867c50127da84425805e225df8555 diff --git a/platforms/chibios/boards/STEMCELL/board/board.c b/platforms/chibios/boards/STEMCELL/board/board.c new file mode 100644 index 000000000000..9ff3f758c123 --- /dev/null +++ b/platforms/chibios/boards/STEMCELL/board/board.c @@ -0,0 +1,266 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * This file has been automatically generated using ChibiStudio board + * generator plugin. Do not edit manually. + */ + +#include "hal.h" +#include "stm32_gpio.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/** + * @brief Type of STM32 GPIO port setup. + */ +typedef struct { + uint32_t moder; + uint32_t otyper; + uint32_t ospeedr; + uint32_t pupdr; + uint32_t odr; + uint32_t afrl; + uint32_t afrh; +} gpio_setup_t; + +/** + * @brief Type of STM32 GPIO initialization data. + */ +typedef struct { +#if STM32_HAS_GPIOA || defined(__DOXYGEN__) + gpio_setup_t PAData; +#endif +#if STM32_HAS_GPIOB || defined(__DOXYGEN__) + gpio_setup_t PBData; +#endif +#if STM32_HAS_GPIOC || defined(__DOXYGEN__) + gpio_setup_t PCData; +#endif +#if STM32_HAS_GPIOD || defined(__DOXYGEN__) + gpio_setup_t PDData; +#endif +#if STM32_HAS_GPIOE || defined(__DOXYGEN__) + gpio_setup_t PEData; +#endif +#if STM32_HAS_GPIOF || defined(__DOXYGEN__) + gpio_setup_t PFData; +#endif +#if STM32_HAS_GPIOG || defined(__DOXYGEN__) + gpio_setup_t PGData; +#endif +#if STM32_HAS_GPIOH || defined(__DOXYGEN__) + gpio_setup_t PHData; +#endif +#if STM32_HAS_GPIOI || defined(__DOXYGEN__) + gpio_setup_t PIData; +#endif +#if STM32_HAS_GPIOJ || defined(__DOXYGEN__) + gpio_setup_t PJData; +#endif +#if STM32_HAS_GPIOK || defined(__DOXYGEN__) + gpio_setup_t PKData; +#endif +} gpio_config_t; + +/** + * @brief STM32 GPIO static initialization data. + */ +static const gpio_config_t gpio_default_config = { +#if STM32_HAS_GPIOA + {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, + VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH}, +#endif +#if STM32_HAS_GPIOB + {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, + VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH}, +#endif +#if STM32_HAS_GPIOC + {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, + VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH}, +#endif +#if STM32_HAS_GPIOD + {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, + VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH}, +#endif +#if STM32_HAS_GPIOE + {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, + VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH}, +#endif +#if STM32_HAS_GPIOF + {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, + VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH}, +#endif +#if STM32_HAS_GPIOG + {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR, + VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH}, +#endif +#if STM32_HAS_GPIOH + {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, + VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH}, +#endif +#if STM32_HAS_GPIOI + {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR, + VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH}, +#endif +#if STM32_HAS_GPIOJ + {VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR, + VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH}, +#endif +#if STM32_HAS_GPIOK + {VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR, + VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH} +#endif +}; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) { + + gpiop->OTYPER = config->otyper; + gpiop->OSPEEDR = config->ospeedr; + gpiop->PUPDR = config->pupdr; + gpiop->ODR = config->odr; + gpiop->AFRL = config->afrl; + gpiop->AFRH = config->afrh; + gpiop->MODER = config->moder; +} + +static void stm32_gpio_init(void) { + + /* Enabling GPIO-related clocks, the mask comes from the + registry header file.*/ + rccResetAHB1(STM32_GPIO_EN_MASK); + rccEnableAHB1(STM32_GPIO_EN_MASK, true); + + /* Initializing all the defined GPIO ports.*/ +#if STM32_HAS_GPIOA + gpio_init(GPIOA, &gpio_default_config.PAData); +#endif +#if STM32_HAS_GPIOB + gpio_init(GPIOB, &gpio_default_config.PBData); +#endif +#if STM32_HAS_GPIOC + gpio_init(GPIOC, &gpio_default_config.PCData); +#endif +#if STM32_HAS_GPIOD + gpio_init(GPIOD, &gpio_default_config.PDData); +#endif +#if STM32_HAS_GPIOE + gpio_init(GPIOE, &gpio_default_config.PEData); +#endif +#if STM32_HAS_GPIOF + gpio_init(GPIOF, &gpio_default_config.PFData); +#endif +#if STM32_HAS_GPIOG + gpio_init(GPIOG, &gpio_default_config.PGData); +#endif +#if STM32_HAS_GPIOH + gpio_init(GPIOH, &gpio_default_config.PHData); +#endif +#if STM32_HAS_GPIOI + gpio_init(GPIOI, &gpio_default_config.PIData); +#endif +#if STM32_HAS_GPIOJ + gpio_init(GPIOJ, &gpio_default_config.PJData); +#endif +#if STM32_HAS_GPIOK + gpio_init(GPIOK, &gpio_default_config.PKData); +#endif +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Early initialization code. + * @details GPIO ports and system clocks are initialized before everything + * else. + */ +void __early_init(void) { + + stm32_gpio_init(); + stm32_clock_init(); +} + +#if HAL_USE_SDC || defined(__DOXYGEN__) +/** + * @brief SDC card detection. + */ +bool sdc_lld_is_card_inserted(SDCDriver *sdcp) { + + (void)sdcp; + /* CHTODO: Fill the implementation.*/ + return true; +} + +/** + * @brief SDC card write protection detection. + */ +bool sdc_lld_is_write_protected(SDCDriver *sdcp) { + + (void)sdcp; + /* CHTODO: Fill the implementation.*/ + return false; +} +#endif /* HAL_USE_SDC */ + +#if HAL_USE_MMC_SPI || defined(__DOXYGEN__) +/** + * @brief MMC_SPI card detection. + */ +bool mmc_lld_is_card_inserted(MMCDriver *mmcp) { + + (void)mmcp; + /* CHTODO: Fill the implementation.*/ + return true; +} + +/** + * @brief MMC_SPI card write protection detection. + */ +bool mmc_lld_is_write_protected(MMCDriver *mmcp) { + + (void)mmcp; + /* CHTODO: Fill the implementation.*/ + return false; +} +#endif + +/** + * @brief Board-specific initialization code. + * @note You can add your board-specific code here. + */ +void boardInit(void) { + +} diff --git a/platforms/chibios/boards/STEMCELL/board/board.h b/platforms/chibios/boards/STEMCELL/board/board.h new file mode 100644 index 000000000000..b8be7c18eeca --- /dev/null +++ b/platforms/chibios/boards/STEMCELL/board/board.h @@ -0,0 +1,1365 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * This file has been automatically generated using ChibiStudio board + * generator plugin. Do not edit manually. + */ + +#ifndef BOARD_H +#define BOARD_H + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/* + * Setup for STMicroelectronics STM32F401C-Discovery board. + */ + +/* + * Board identifier. + */ +#define BOARD_ST_STM32F401C_DISCOVERY +#define BOARD_NAME "STMicroelectronics STM32F401C-Discovery" + +/* + * Board oscillators-related settings. + * NOTE: LSE not fitted. + */ +#if !defined(STM32_LSECLK) +#define STM32_LSECLK 0U +#endif + +#if !defined(STM32_HSECLK) +#define STM32_HSECLK 8000000U +#endif + +/* + * Board voltages. + * Required for performance limits calculation. + */ +#define STM32_VDD 300U + +/* + * MCU type as defined in the ST header. + */ +#define STM32F401xC + +/* + * IO pins assignments. + */ +#define GPIOA_BUTTON 0U +#define GPIOA_PIN1 1U +#define GPIOA_PIN2 2U +#define GPIOA_PIN3 3U +#define GPIOA_CS43L22_LRCK 4U +#define GPIOA_L3GD20_SCL 5U +#define GPIOA_L3GD20_SD0 6U +#define GPIOA_L3GD20_SDI 7U +#define GPIOA_LED 8U +#define GPIOA_VBUS_FS 9U +#define GPIOA_OTG_FS_ID 10U +#define GPIOA_OTG_FS_DM 11U +#define GPIOA_OTG_FS_DP 12U +#define GPIOA_SWDIO 13U +#define GPIOA_SWCLK 14U +#define GPIOA_PIN15 15U + +#define GPIOB_PIN0 0U +#define GPIOB_PIN1 1U +#define GPIOB_PIN2 2U +#define GPIOB_SWO 3U +#define GPIOB_PIN4 4U +#define GPIOB_PIN5 5U +#define GPIOB_LSM303DLHC_SCL 6U +#define GPIOB_PIN7 7U +#define GPIOB_PIN8 8U +#define GPIOB_LSM303DLHC_SDA 9U +#define GPIOB_MP45DT02_CLK_IN 10U +#define GPIOB_PIN11 11U +#define GPIOB_PIN12 12U +#define GPIOB_PIN13 13U +#define GPIOB_PIN14 14U +#define GPIOB_PIN15 15U + +#define GPIOC_OTG_FS_POWER_ON 0U +#define GPIOC_PIN1 1U +#define GPIOC_PIN2 2U +#define GPIOC_CS43L22_AIN4x 3U +#define GPIOC_MP45DT02_PDM_OUT 3U +#define GPIOC_PIN4 4U +#define GPIOC_PIN5 5U +#define GPIOC_PIN6 6U +#define GPIOC_CS43L22_MCLK 7U +#define GPIOC_PIN8 8U +#define GPIOC_PIN9 9U +#define GPIOC_CS43L22_SCLK 10U +#define GPIOC_PIN11 11U +#define GPIOC_CS43L22_SDIN 12U +#define GPIOC_PIN13 13U +#define GPIOC_OSC32_IN 14U +#define GPIOC_OSC32_OUT 15U + +#define GPIOD_PIN0 0U +#define GPIOD_PIN1 1U +#define GPIOD_PIN2 2U +#define GPIOD_PIN3 3U +#define GPIOD_CS43L22_RESET 4U +#define GPIOD_OverCurrent 5U +#define GPIOD_PIN6 6U +#define GPIOD_PIN7 7U +#define GPIOD_PIN8 8U +#define GPIOD_PIN9 9U +#define GPIOD_PIN10 10U +#define GPIOD_PIN11 11U +#define GPIOD_LED4 12U +#define GPIOD_LED3 13U +#define GPIOD_LED5 14U +#define GPIOD_LED6 15U + +#define GPIOE_L3GD20_INT1 0U +#define GPIOE_L3GD20_INT2 1U +#define GPIOE_LSM303DLHC_DRDY 2U +#define GPIOE_L3GD20_CS 3U +#define GPIOE_LSM303DLHC_INT1 4U +#define GPIOE_LSM303DLHC_INT2 5U +#define GPIOE_PIN6 6U +#define GPIOE_PIN7 7U +#define GPIOE_PIN8 8U +#define GPIOE_PIN9 9U +#define GPIOE_PIN10 10U +#define GPIOE_PIN11 11U +#define GPIOE_PIN12 12U +#define GPIOE_PIN13 13U +#define GPIOE_PIN14 14U +#define GPIOE_PIN15 15U + +#define GPIOF_PIN0 0U +#define GPIOF_PIN1 1U +#define GPIOF_PIN2 2U +#define GPIOF_PIN3 3U +#define GPIOF_PIN4 4U +#define GPIOF_PIN5 5U +#define GPIOF_PIN6 6U +#define GPIOF_PIN7 7U +#define GPIOF_PIN8 8U +#define GPIOF_PIN9 9U +#define GPIOF_PIN10 10U +#define GPIOF_PIN11 11U +#define GPIOF_PIN12 12U +#define GPIOF_PIN13 13U +#define GPIOF_PIN14 14U +#define GPIOF_PIN15 15U + +#define GPIOG_PIN0 0U +#define GPIOG_PIN1 1U +#define GPIOG_PIN2 2U +#define GPIOG_PIN3 3U +#define GPIOG_PIN4 4U +#define GPIOG_PIN5 5U +#define GPIOG_PIN6 6U +#define GPIOG_PIN7 7U +#define GPIOG_PIN8 8U +#define GPIOG_PIN9 9U +#define GPIOG_PIN10 10U +#define GPIOG_PIN11 11U +#define GPIOG_PIN12 12U +#define GPIOG_PIN13 13U +#define GPIOG_PIN14 14U +#define GPIOG_PIN15 15U + +#define GPIOH_OSC_IN 0U +#define GPIOH_OSC_OUT 1U +#define GPIOH_PIN2 2U +#define GPIOH_PIN3 3U +#define GPIOH_PIN4 4U +#define GPIOH_PIN5 5U +#define GPIOH_PIN6 6U +#define GPIOH_PIN7 7U +#define GPIOH_PIN8 8U +#define GPIOH_PIN9 9U +#define GPIOH_PIN10 10U +#define GPIOH_PIN11 11U +#define GPIOH_PIN12 12U +#define GPIOH_PIN13 13U +#define GPIOH_PIN14 14U +#define GPIOH_PIN15 15U + +#define GPIOI_PIN0 0U +#define GPIOI_PIN1 1U +#define GPIOI_PIN2 2U +#define GPIOI_PIN3 3U +#define GPIOI_PIN4 4U +#define GPIOI_PIN5 5U +#define GPIOI_PIN6 6U +#define GPIOI_PIN7 7U +#define GPIOI_PIN8 8U +#define GPIOI_PIN9 9U +#define GPIOI_PIN10 10U +#define GPIOI_PIN11 11U +#define GPIOI_PIN12 12U +#define GPIOI_PIN13 13U +#define GPIOI_PIN14 14U +#define GPIOI_PIN15 15U + +/* + * IO lines assignments. + */ +#define LINE_BUTTON PAL_LINE(GPIOA, 0U) +#define LINE_CS43L22_LRCK PAL_LINE(GPIOA, 4U) +#define LINE_L3GD20_SCL PAL_LINE(GPIOA, 5U) +#define LINE_L3GD20_SD0 PAL_LINE(GPIOA, 6U) +#define LINE_L3GD20_SDI PAL_LINE(GPIOA, 7U) +#define LINE_VBUS_FS PAL_LINE(GPIOA, 9U) +#define LINE_OTG_FS_ID PAL_LINE(GPIOA, 10U) +#define LINE_OTG_FS_DM PAL_LINE(GPIOA, 11U) +#define LINE_OTG_FS_DP PAL_LINE(GPIOA, 12U) +#define LINE_SWDIO PAL_LINE(GPIOA, 13U) +#define LINE_SWCLK PAL_LINE(GPIOA, 14U) +#define LINE_SWO PAL_LINE(GPIOB, 3U) +#define LINE_LSM303DLHC_SCL PAL_LINE(GPIOB, 6U) +#define LINE_LSM303DLHC_SDA PAL_LINE(GPIOB, 9U) +#define LINE_MP45DT02_CLK_IN PAL_LINE(GPIOB, 10U) +#define LINE_OTG_FS_POWER_ON PAL_LINE(GPIOC, 0U) +#define LINE_CS43L22_AIN4x PAL_LINE(GPIOC, 3U) +#define LINE_MP45DT02_PDM_OUT PAL_LINE(GPIOC, 3U) +#define LINE_CS43L22_MCLK PAL_LINE(GPIOC, 7U) +#define LINE_CS43L22_SCLK PAL_LINE(GPIOC, 10U) +#define LINE_CS43L22_SDIN PAL_LINE(GPIOC, 12U) +#define LINE_OSC32_IN PAL_LINE(GPIOC, 14U) +#define LINE_OSC32_OUT PAL_LINE(GPIOC, 15U) +#define LINE_CS43L22_RESET PAL_LINE(GPIOD, 4U) +#define LINE_OverCurrent PAL_LINE(GPIOD, 5U) +#define LINE_LED4 PAL_LINE(GPIOD, 12U) +#define LINE_LED3 PAL_LINE(GPIOD, 13U) +#define LINE_LED5 PAL_LINE(GPIOD, 14U) +#define LINE_LED6 PAL_LINE(GPIOD, 15U) +#define LINE_L3GD20_INT1 PAL_LINE(GPIOE, 0U) +#define LINE_L3GD20_INT2 PAL_LINE(GPIOE, 1U) +#define LINE_LSM303DLHC_DRDY PAL_LINE(GPIOE, 2U) +#define LINE_L3GD20_CS PAL_LINE(GPIOE, 3U) +#define LINE_LSM303DLHC_INT1 PAL_LINE(GPIOE, 4U) +#define LINE_LSM303DLHC_INT2 PAL_LINE(GPIOE, 5U) +#define LINE_OSC_IN PAL_LINE(GPIOH, 0U) +#define LINE_OSC_OUT PAL_LINE(GPIOH, 1U) + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/* + * I/O ports initial setup, this configuration is established soon after reset + * in the initialization code. + * Please refer to the STM32 Reference Manual for details. + */ +#define PIN_MODE_INPUT(n) (0U << ((n) * 2U)) +#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2U)) +#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2U)) +#define PIN_MODE_ANALOG(n) (3U << ((n) * 2U)) +#define PIN_ODR_LOW(n) (0U << (n)) +#define PIN_ODR_HIGH(n) (1U << (n)) +#define PIN_OTYPE_PUSHPULL(n) (0U << (n)) +#define PIN_OTYPE_OPENDRAIN(n) (1U << (n)) +#define PIN_OSPEED_VERYLOW(n) (0U << ((n) * 2U)) +#define PIN_OSPEED_LOW(n) (1U << ((n) * 2U)) +#define PIN_OSPEED_MEDIUM(n) (2U << ((n) * 2U)) +#define PIN_OSPEED_HIGH(n) (3U << ((n) * 2U)) +#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2U)) +#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2U)) +#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2U)) +#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U)) + +/* + * GPIOA setup: + * + * PA0 - BUTTON (input floating). + * PA1 - PIN1 (input pullup). + * PA2 - PIN2 (input pullup). + * PA3 - PIN3 (input pullup). + * PA4 - CS43L22_LRCK (alternate 6). + * PA5 - L3GD20_SCL (alternate 5). + * PA6 - L3GD20_SD0 (alternate 5). + * PA7 - L3GD20_SDI (alternate 5). + * PA8 - LED (output pushpull maximum). + * PA9 - VBUS_FS (input floating). + * PA10 - OTG_FS_ID (alternate 10). + * PA11 - OTG_FS_DM (alternate 10). + * PA12 - OTG_FS_DP (alternate 10). + * PA13 - SWDIO (alternate 0). + * PA14 - SWCLK (alternate 0). + * PA15 - PIN15 (input pullup). + */ +#define VAL_GPIOA_MODER (PIN_MODE_INPUT(GPIOA_BUTTON) | \ + PIN_MODE_INPUT(GPIOA_PIN1) | \ + PIN_MODE_INPUT(GPIOA_PIN2) | \ + PIN_MODE_INPUT(GPIOA_PIN3) | \ + PIN_MODE_ALTERNATE(GPIOA_CS43L22_LRCK) |\ + PIN_MODE_ALTERNATE(GPIOA_L3GD20_SCL) | \ + PIN_MODE_ALTERNATE(GPIOA_L3GD20_SD0) | \ + PIN_MODE_ALTERNATE(GPIOA_L3GD20_SDI) | \ + PIN_MODE_OUTPUT(GPIOA_LED)| \ + PIN_MODE_INPUT(GPIOA_VBUS_FS) | \ + PIN_MODE_ALTERNATE(GPIOA_OTG_FS_ID) | \ + PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DM) | \ + PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DP) | \ + PIN_MODE_ALTERNATE(GPIOA_SWDIO) | \ + PIN_MODE_ALTERNATE(GPIOA_SWCLK) | \ + PIN_MODE_INPUT(GPIOA_PIN15)) +#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_BUTTON) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOA_CS43L22_LRCK) |\ + PIN_OTYPE_PUSHPULL(GPIOA_L3GD20_SCL) | \ + PIN_OTYPE_PUSHPULL(GPIOA_L3GD20_SD0) | \ + PIN_OTYPE_PUSHPULL(GPIOA_L3GD20_SDI) | \ + PIN_OTYPE_PUSHPULL(GPIOA_LED) | \ + PIN_OTYPE_PUSHPULL(GPIOA_VBUS_FS) | \ + PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_ID) | \ + PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_DM) | \ + PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_DP) | \ + PIN_OTYPE_PUSHPULL(GPIOA_SWDIO) | \ + PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN15)) +#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_HIGH(GPIOA_BUTTON) | \ + PIN_OSPEED_HIGH(GPIOA_PIN1) | \ + PIN_OSPEED_HIGH(GPIOA_PIN2) | \ + PIN_OSPEED_HIGH(GPIOA_PIN3) | \ + PIN_OSPEED_HIGH(GPIOA_CS43L22_LRCK) | \ + PIN_OSPEED_HIGH(GPIOA_L3GD20_SCL) | \ + PIN_OSPEED_HIGH(GPIOA_L3GD20_SD0) | \ + PIN_OSPEED_HIGH(GPIOA_L3GD20_SDI) | \ + PIN_OSPEED_HIGH(GPIOA_LED) | \ + PIN_OSPEED_HIGH(GPIOA_VBUS_FS) | \ + PIN_OSPEED_HIGH(GPIOA_OTG_FS_ID) | \ + PIN_OSPEED_HIGH(GPIOA_OTG_FS_DM) | \ + PIN_OSPEED_HIGH(GPIOA_OTG_FS_DP) | \ + PIN_OSPEED_HIGH(GPIOA_SWDIO) | \ + PIN_OSPEED_HIGH(GPIOA_SWCLK) | \ + PIN_OSPEED_HIGH(GPIOA_PIN15)) +#define VAL_GPIOA_PUPDR (PIN_PUPDR_FLOATING(GPIOA_BUTTON) | \ + PIN_PUPDR_PULLUP(GPIOA_PIN1) | \ + PIN_PUPDR_PULLUP(GPIOA_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOA_PIN3) | \ + PIN_PUPDR_FLOATING(GPIOA_CS43L22_LRCK) |\ + PIN_PUPDR_FLOATING(GPIOA_L3GD20_SCL) | \ + PIN_PUPDR_PULLUP(GPIOA_L3GD20_SD0) | \ + PIN_PUPDR_PULLUP(GPIOA_L3GD20_SDI) | \ + PIN_PUPDR_FLOATING(GPIOA_LED) | \ + PIN_PUPDR_FLOATING(GPIOA_VBUS_FS) | \ + PIN_PUPDR_FLOATING(GPIOA_OTG_FS_ID) | \ + PIN_PUPDR_FLOATING(GPIOA_OTG_FS_DM) | \ + PIN_PUPDR_FLOATING(GPIOA_OTG_FS_DP) | \ + PIN_PUPDR_FLOATING(GPIOA_SWDIO) | \ + PIN_PUPDR_FLOATING(GPIOA_SWCLK) | \ + PIN_PUPDR_PULLUP(GPIOA_PIN15)) +#define VAL_GPIOA_ODR (PIN_ODR_HIGH(GPIOA_BUTTON) | \ + PIN_ODR_HIGH(GPIOA_PIN1) | \ + PIN_ODR_HIGH(GPIOA_PIN2) | \ + PIN_ODR_HIGH(GPIOA_PIN3) | \ + PIN_ODR_HIGH(GPIOA_CS43L22_LRCK) | \ + PIN_ODR_HIGH(GPIOA_L3GD20_SCL) | \ + PIN_ODR_HIGH(GPIOA_L3GD20_SD0) | \ + PIN_ODR_HIGH(GPIOA_L3GD20_SDI) | \ + PIN_ODR_LOW(GPIOA_LED) | \ + PIN_ODR_HIGH(GPIOA_VBUS_FS) | \ + PIN_ODR_HIGH(GPIOA_OTG_FS_ID) | \ + PIN_ODR_HIGH(GPIOA_OTG_FS_DM) | \ + PIN_ODR_HIGH(GPIOA_OTG_FS_DP) | \ + PIN_ODR_HIGH(GPIOA_SWDIO) | \ + PIN_ODR_HIGH(GPIOA_SWCLK) | \ + PIN_ODR_HIGH(GPIOA_PIN15)) +#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_BUTTON, 0U) | \ + PIN_AFIO_AF(GPIOA_PIN1, 0U) | \ + PIN_AFIO_AF(GPIOA_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOA_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOA_CS43L22_LRCK, 6U) | \ + PIN_AFIO_AF(GPIOA_L3GD20_SCL, 5U) | \ + PIN_AFIO_AF(GPIOA_L3GD20_SD0, 5U) | \ + PIN_AFIO_AF(GPIOA_L3GD20_SDI, 5U)) +#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_LED, 0U) | \ + PIN_AFIO_AF(GPIOA_VBUS_FS, 0U) | \ + PIN_AFIO_AF(GPIOA_OTG_FS_ID, 10U) | \ + PIN_AFIO_AF(GPIOA_OTG_FS_DM, 10U) | \ + PIN_AFIO_AF(GPIOA_OTG_FS_DP, 10U) | \ + PIN_AFIO_AF(GPIOA_SWDIO, 0U) | \ + PIN_AFIO_AF(GPIOA_SWCLK, 0U) | \ + PIN_AFIO_AF(GPIOA_PIN15, 0U)) + +/* + * GPIOB setup: + * + * PB0 - PIN0 (input pullup). + * PB1 - PIN1 (input pullup). + * PB2 - PIN2 (input pullup). + * PB3 - SWO (alternate 0). + * PB4 - PIN4 (input pullup). + * PB5 - PIN5 (input pullup). + * PB6 - LSM303DLHC_SCL (alternate 4). + * PB7 - PIN7 (input pullup). + * PB8 - PIN8 (input pullup). + * PB9 - LSM303DLHC_SDA (alternate 4). + * PB10 - MP45DT02_CLK_IN (alternate 5). + * PB11 - PIN11 (input pullup). + * PB12 - PIN12 (input pullup). + * PB13 - PIN13 (input pullup). + * PB14 - PIN14 (input pullup). + * PB15 - PIN15 (input pullup). + */ +#define VAL_GPIOB_MODER (PIN_MODE_INPUT(GPIOB_PIN0) | \ + PIN_MODE_INPUT(GPIOB_PIN1) | \ + PIN_MODE_INPUT(GPIOB_PIN2) | \ + PIN_MODE_ALTERNATE(GPIOB_SWO) | \ + PIN_MODE_INPUT(GPIOB_PIN4) | \ + PIN_MODE_INPUT(GPIOB_PIN5) | \ + PIN_MODE_ALTERNATE(GPIOB_LSM303DLHC_SCL) |\ + PIN_MODE_INPUT(GPIOB_PIN7) | \ + PIN_MODE_INPUT(GPIOB_PIN8) | \ + PIN_MODE_ALTERNATE(GPIOB_LSM303DLHC_SDA) |\ + PIN_MODE_ALTERNATE(GPIOB_MP45DT02_CLK_IN) |\ + PIN_MODE_INPUT(GPIOB_PIN11) | \ + PIN_MODE_INPUT(GPIOB_PIN12) | \ + PIN_MODE_INPUT(GPIOB_PIN13) | \ + PIN_MODE_INPUT(GPIOB_PIN14) | \ + PIN_MODE_INPUT(GPIOB_PIN15)) +#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOB_SWO) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOB_LSM303DLHC_SCL) |\ + PIN_OTYPE_PUSHPULL(GPIOB_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOB_LSM303DLHC_SDA) |\ + PIN_OTYPE_PUSHPULL(GPIOB_MP45DT02_CLK_IN) |\ + PIN_OTYPE_PUSHPULL(GPIOB_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN15)) +#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_HIGH(GPIOB_PIN0) | \ + PIN_OSPEED_HIGH(GPIOB_PIN1) | \ + PIN_OSPEED_HIGH(GPIOB_PIN2) | \ + PIN_OSPEED_HIGH(GPIOB_SWO) | \ + PIN_OSPEED_HIGH(GPIOB_PIN4) | \ + PIN_OSPEED_HIGH(GPIOB_PIN5) | \ + PIN_OSPEED_HIGH(GPIOB_LSM303DLHC_SCL) |\ + PIN_OSPEED_HIGH(GPIOB_PIN7) | \ + PIN_OSPEED_HIGH(GPIOB_PIN8) | \ + PIN_OSPEED_HIGH(GPIOB_LSM303DLHC_SDA) |\ + PIN_OSPEED_HIGH(GPIOB_MP45DT02_CLK_IN) |\ + PIN_OSPEED_HIGH(GPIOB_PIN11) | \ + PIN_OSPEED_HIGH(GPIOB_PIN12) | \ + PIN_OSPEED_HIGH(GPIOB_PIN13) | \ + PIN_OSPEED_HIGH(GPIOB_PIN14) | \ + PIN_OSPEED_HIGH(GPIOB_PIN15)) +#define VAL_GPIOB_PUPDR (PIN_PUPDR_PULLUP(GPIOB_PIN0) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN1) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOB_SWO) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN5) | \ + PIN_PUPDR_FLOATING(GPIOB_LSM303DLHC_SCL) |\ + PIN_PUPDR_PULLUP(GPIOB_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN8) | \ + PIN_PUPDR_FLOATING(GPIOB_LSM303DLHC_SDA) |\ + PIN_PUPDR_FLOATING(GPIOB_MP45DT02_CLK_IN) |\ + PIN_PUPDR_PULLUP(GPIOB_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN13) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN14) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN15)) +#define VAL_GPIOB_ODR (PIN_ODR_HIGH(GPIOB_PIN0) | \ + PIN_ODR_HIGH(GPIOB_PIN1) | \ + PIN_ODR_HIGH(GPIOB_PIN2) | \ + PIN_ODR_HIGH(GPIOB_SWO) | \ + PIN_ODR_HIGH(GPIOB_PIN4) | \ + PIN_ODR_HIGH(GPIOB_PIN5) | \ + PIN_ODR_HIGH(GPIOB_LSM303DLHC_SCL) | \ + PIN_ODR_HIGH(GPIOB_PIN7) | \ + PIN_ODR_HIGH(GPIOB_PIN8) | \ + PIN_ODR_HIGH(GPIOB_LSM303DLHC_SDA) | \ + PIN_ODR_HIGH(GPIOB_MP45DT02_CLK_IN) | \ + PIN_ODR_HIGH(GPIOB_PIN11) | \ + PIN_ODR_HIGH(GPIOB_PIN12) | \ + PIN_ODR_HIGH(GPIOB_PIN13) | \ + PIN_ODR_HIGH(GPIOB_PIN14) | \ + PIN_ODR_HIGH(GPIOB_PIN15)) +#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_PIN0, 0U) | \ + PIN_AFIO_AF(GPIOB_PIN1, 0U) | \ + PIN_AFIO_AF(GPIOB_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOB_SWO, 0U) | \ + PIN_AFIO_AF(GPIOB_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOB_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOB_LSM303DLHC_SCL, 4U) |\ + PIN_AFIO_AF(GPIOB_PIN7, 0U)) +#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOB_LSM303DLHC_SDA, 4U) |\ + PIN_AFIO_AF(GPIOB_MP45DT02_CLK_IN, 5U) |\ + PIN_AFIO_AF(GPIOB_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOB_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOB_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOB_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOB_PIN15, 0U)) + +/* + * GPIOC setup: + * + * PC0 - OTG_FS_POWER_ON (output pushpull maximum). + * PC1 - PIN1 (input pullup). + * PC2 - PIN2 (input pullup). + * PC3 - CS43L22_AIN4x MP45DT02_PDM_OUT(alternate 5). + * PC4 - PIN4 (input pullup). + * PC5 - PIN5 (input pullup). + * PC6 - PIN6 (input pullup). + * PC7 - CS43L22_MCLK (alternate 6). + * PC8 - PIN8 (input pullup). + * PC9 - PIN9 (input pullup). + * PC10 - CS43L22_SCLK (alternate 6). + * PC11 - PIN11 (input pullup). + * PC12 - CS43L22_SDIN (alternate 6). + * PC13 - PIN13 (input pullup). + * PC14 - OSC32_IN (input floating). + * PC15 - OSC32_OUT (input floating). + */ +#define VAL_GPIOC_MODER (PIN_MODE_OUTPUT(GPIOC_OTG_FS_POWER_ON) |\ + PIN_MODE_INPUT(GPIOC_PIN1) | \ + PIN_MODE_INPUT(GPIOC_PIN2) | \ + PIN_MODE_ALTERNATE(GPIOC_CS43L22_AIN4x) |\ + PIN_MODE_INPUT(GPIOC_PIN4) | \ + PIN_MODE_INPUT(GPIOC_PIN5) | \ + PIN_MODE_INPUT(GPIOC_PIN6) | \ + PIN_MODE_ALTERNATE(GPIOC_CS43L22_MCLK) |\ + PIN_MODE_INPUT(GPIOC_PIN8) | \ + PIN_MODE_INPUT(GPIOC_PIN9) | \ + PIN_MODE_ALTERNATE(GPIOC_CS43L22_SCLK) |\ + PIN_MODE_INPUT(GPIOC_PIN11) | \ + PIN_MODE_ALTERNATE(GPIOC_CS43L22_SDIN) |\ + PIN_MODE_INPUT(GPIOC_PIN13) | \ + PIN_MODE_INPUT(GPIOC_OSC32_IN) | \ + PIN_MODE_INPUT(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_OTG_FS_POWER_ON) |\ + PIN_OTYPE_PUSHPULL(GPIOC_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOC_CS43L22_AIN4x) |\ + PIN_OTYPE_PUSHPULL(GPIOC_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOC_CS43L22_MCLK) |\ + PIN_OTYPE_PUSHPULL(GPIOC_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOC_CS43L22_SCLK) |\ + PIN_OTYPE_PUSHPULL(GPIOC_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOC_CS43L22_SDIN) |\ + PIN_OTYPE_PUSHPULL(GPIOC_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOC_OSC32_IN) | \ + PIN_OTYPE_PUSHPULL(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_HIGH(GPIOC_OTG_FS_POWER_ON) |\ + PIN_OSPEED_HIGH(GPIOC_PIN1) | \ + PIN_OSPEED_HIGH(GPIOC_PIN2) | \ + PIN_OSPEED_HIGH(GPIOC_CS43L22_AIN4x) | \ + PIN_OSPEED_HIGH(GPIOC_PIN4) | \ + PIN_OSPEED_HIGH(GPIOC_PIN5) | \ + PIN_OSPEED_HIGH(GPIOC_PIN6) | \ + PIN_OSPEED_HIGH(GPIOC_CS43L22_MCLK) | \ + PIN_OSPEED_HIGH(GPIOC_PIN8) | \ + PIN_OSPEED_HIGH(GPIOC_PIN9) | \ + PIN_OSPEED_HIGH(GPIOC_CS43L22_SCLK) | \ + PIN_OSPEED_HIGH(GPIOC_PIN11) | \ + PIN_OSPEED_HIGH(GPIOC_CS43L22_SDIN) | \ + PIN_OSPEED_HIGH(GPIOC_PIN13) | \ + PIN_OSPEED_HIGH(GPIOC_OSC32_IN) | \ + PIN_OSPEED_HIGH(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_PUPDR (PIN_PUPDR_PULLUP(GPIOC_OTG_FS_POWER_ON) |\ + PIN_PUPDR_PULLUP(GPIOC_PIN1) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN2) | \ + PIN_PUPDR_FLOATING(GPIOC_CS43L22_AIN4x) |\ + PIN_PUPDR_PULLUP(GPIOC_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOC_CS43L22_MCLK) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOC_CS43L22_SCLK) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOC_CS43L22_SDIN) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN13) | \ + PIN_PUPDR_FLOATING(GPIOC_OSC32_IN) | \ + PIN_PUPDR_FLOATING(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_ODR (PIN_ODR_HIGH(GPIOC_OTG_FS_POWER_ON) | \ + PIN_ODR_HIGH(GPIOC_PIN1) | \ + PIN_ODR_HIGH(GPIOC_PIN2) | \ + PIN_ODR_HIGH(GPIOC_CS43L22_AIN4x) | \ + PIN_ODR_HIGH(GPIOC_PIN4) | \ + PIN_ODR_HIGH(GPIOC_PIN5) | \ + PIN_ODR_HIGH(GPIOC_PIN6) | \ + PIN_ODR_HIGH(GPIOC_CS43L22_MCLK) | \ + PIN_ODR_HIGH(GPIOC_PIN8) | \ + PIN_ODR_HIGH(GPIOC_PIN9) | \ + PIN_ODR_HIGH(GPIOC_CS43L22_SCLK) | \ + PIN_ODR_HIGH(GPIOC_PIN11) | \ + PIN_ODR_HIGH(GPIOC_CS43L22_SDIN) | \ + PIN_ODR_HIGH(GPIOC_PIN13) | \ + PIN_ODR_HIGH(GPIOC_OSC32_IN) | \ + PIN_ODR_HIGH(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_OTG_FS_POWER_ON, 0U) |\ + PIN_AFIO_AF(GPIOC_PIN1, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOC_CS43L22_AIN4x, 5U) | \ + PIN_AFIO_AF(GPIOC_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOC_CS43L22_MCLK, 6U)) +#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOC_CS43L22_SCLK, 6U) | \ + PIN_AFIO_AF(GPIOC_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOC_CS43L22_SDIN, 6U) | \ + PIN_AFIO_AF(GPIOC_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOC_OSC32_IN, 0U) | \ + PIN_AFIO_AF(GPIOC_OSC32_OUT, 0U)) + +/* + * GPIOD setup: + * + * PD0 - PIN0 (input pullup). + * PD1 - PIN1 (input pullup). + * PD2 - PIN2 (input pullup). + * PD3 - PIN3 (input pullup). + * PD4 - CS43L22_RESET (output pushpull maximum). + * PD5 - OverCurrent (input floating). + * PD6 - PIN6 (input pullup). + * PD7 - PIN7 (input pullup). + * PD8 - PIN8 (input pullup). + * PD9 - PIN9 (input pullup). + * PD10 - PIN10 (input pullup). + * PD11 - PIN11 (input pullup). + * PD12 - LED4 (output pushpull maximum). + * PD13 - LED3 (output pushpull maximum). + * PD14 - LED5 (output pushpull maximum). + * PD15 - LED6 (output pushpull maximum). + */ +#define VAL_GPIOD_MODER (PIN_MODE_INPUT(GPIOD_PIN0) | \ + PIN_MODE_INPUT(GPIOD_PIN1) | \ + PIN_MODE_INPUT(GPIOD_PIN2) | \ + PIN_MODE_INPUT(GPIOD_PIN3) | \ + PIN_MODE_OUTPUT(GPIOD_CS43L22_RESET) | \ + PIN_MODE_INPUT(GPIOD_OverCurrent) | \ + PIN_MODE_INPUT(GPIOD_PIN6) | \ + PIN_MODE_INPUT(GPIOD_PIN7) | \ + PIN_MODE_INPUT(GPIOD_PIN8) | \ + PIN_MODE_INPUT(GPIOD_PIN9) | \ + PIN_MODE_INPUT(GPIOD_PIN10) | \ + PIN_MODE_INPUT(GPIOD_PIN11) | \ + PIN_MODE_OUTPUT(GPIOD_LED4) | \ + PIN_MODE_OUTPUT(GPIOD_LED3) | \ + PIN_MODE_OUTPUT(GPIOD_LED5) | \ + PIN_MODE_OUTPUT(GPIOD_LED6)) +#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOD_CS43L22_RESET) |\ + PIN_OTYPE_PUSHPULL(GPIOD_OverCurrent) |\ + PIN_OTYPE_PUSHPULL(GPIOD_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOD_LED4) | \ + PIN_OTYPE_PUSHPULL(GPIOD_LED3) | \ + PIN_OTYPE_PUSHPULL(GPIOD_LED5) | \ + PIN_OTYPE_PUSHPULL(GPIOD_LED6)) +#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_HIGH(GPIOD_PIN0) | \ + PIN_OSPEED_HIGH(GPIOD_PIN1) | \ + PIN_OSPEED_HIGH(GPIOD_PIN2) | \ + PIN_OSPEED_HIGH(GPIOD_PIN3) | \ + PIN_OSPEED_HIGH(GPIOD_CS43L22_RESET) | \ + PIN_OSPEED_HIGH(GPIOD_OverCurrent) | \ + PIN_OSPEED_HIGH(GPIOD_PIN6) | \ + PIN_OSPEED_HIGH(GPIOD_PIN7) | \ + PIN_OSPEED_HIGH(GPIOD_PIN8) | \ + PIN_OSPEED_HIGH(GPIOD_PIN9) | \ + PIN_OSPEED_HIGH(GPIOD_PIN10) | \ + PIN_OSPEED_HIGH(GPIOD_PIN11) | \ + PIN_OSPEED_HIGH(GPIOD_LED4) | \ + PIN_OSPEED_HIGH(GPIOD_LED3) | \ + PIN_OSPEED_HIGH(GPIOD_LED5) | \ + PIN_OSPEED_HIGH(GPIOD_LED6)) +#define VAL_GPIOD_PUPDR (PIN_PUPDR_PULLUP(GPIOD_PIN0) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN1) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN3) | \ + PIN_PUPDR_PULLUP(GPIOD_CS43L22_RESET) |\ + PIN_PUPDR_FLOATING(GPIOD_OverCurrent) |\ + PIN_PUPDR_PULLUP(GPIOD_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN11) | \ + PIN_PUPDR_FLOATING(GPIOD_LED4) | \ + PIN_PUPDR_FLOATING(GPIOD_LED3) | \ + PIN_PUPDR_FLOATING(GPIOD_LED5) | \ + PIN_PUPDR_FLOATING(GPIOD_LED6)) +#define VAL_GPIOD_ODR (PIN_ODR_HIGH(GPIOD_PIN0) | \ + PIN_ODR_HIGH(GPIOD_PIN1) | \ + PIN_ODR_HIGH(GPIOD_PIN2) | \ + PIN_ODR_HIGH(GPIOD_PIN3) | \ + PIN_ODR_HIGH(GPIOD_CS43L22_RESET) | \ + PIN_ODR_HIGH(GPIOD_OverCurrent) | \ + PIN_ODR_HIGH(GPIOD_PIN6) | \ + PIN_ODR_HIGH(GPIOD_PIN7) | \ + PIN_ODR_HIGH(GPIOD_PIN8) | \ + PIN_ODR_HIGH(GPIOD_PIN9) | \ + PIN_ODR_HIGH(GPIOD_PIN10) | \ + PIN_ODR_HIGH(GPIOD_PIN11) | \ + PIN_ODR_LOW(GPIOD_LED4) | \ + PIN_ODR_LOW(GPIOD_LED3) | \ + PIN_ODR_LOW(GPIOD_LED5) | \ + PIN_ODR_LOW(GPIOD_LED6)) +#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_PIN0, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN1, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOD_CS43L22_RESET, 0U) | \ + PIN_AFIO_AF(GPIOD_OverCurrent, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN7, 0U)) +#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOD_LED4, 0U) | \ + PIN_AFIO_AF(GPIOD_LED3, 0U) | \ + PIN_AFIO_AF(GPIOD_LED5, 0U) | \ + PIN_AFIO_AF(GPIOD_LED6, 0U)) + +/* + * GPIOE setup: + * + * PE0 - L3GD20_INT1 (input pullup). + * PE1 - L3GD20_INT2 (input pullup). + * PE2 - LSM303DLHC_DRDY (input floating). + * PE3 - L3GD20_CS (output pushpull maximum). + * PE4 - LSM303DLHC_INT1 (output pushpull maximum). + * PE5 - LSM303DLHC_INT2 (output pushpull maximum). + * PE6 - PIN6 (input pullup). + * PE7 - PIN7 (input pullup). + * PE8 - PIN8 (input pullup). + * PE9 - PIN9 (input pullup). + * PE10 - PIN10 (input pullup). + * PE11 - PIN11 (input pullup). + * PE12 - PIN12 (input pullup). + * PE13 - PIN13 (input pullup). + * PE14 - PIN14 (input pullup). + * PE15 - PIN15 (input pullup). + */ +#define VAL_GPIOE_MODER (PIN_MODE_INPUT(GPIOE_L3GD20_INT1) | \ + PIN_MODE_INPUT(GPIOE_L3GD20_INT2) | \ + PIN_MODE_INPUT(GPIOE_LSM303DLHC_DRDY) |\ + PIN_MODE_OUTPUT(GPIOE_L3GD20_CS) | \ + PIN_MODE_OUTPUT(GPIOE_LSM303DLHC_INT1) |\ + PIN_MODE_OUTPUT(GPIOE_LSM303DLHC_INT2) |\ + PIN_MODE_INPUT(GPIOE_PIN6) | \ + PIN_MODE_INPUT(GPIOE_PIN7) | \ + PIN_MODE_INPUT(GPIOE_PIN8) | \ + PIN_MODE_INPUT(GPIOE_PIN9) | \ + PIN_MODE_INPUT(GPIOE_PIN10) | \ + PIN_MODE_INPUT(GPIOE_PIN11) | \ + PIN_MODE_INPUT(GPIOE_PIN12) | \ + PIN_MODE_INPUT(GPIOE_PIN13) | \ + PIN_MODE_INPUT(GPIOE_PIN14) | \ + PIN_MODE_INPUT(GPIOE_PIN15)) +#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_L3GD20_INT1) |\ + PIN_OTYPE_PUSHPULL(GPIOE_L3GD20_INT2) |\ + PIN_OTYPE_PUSHPULL(GPIOE_LSM303DLHC_DRDY) |\ + PIN_OTYPE_PUSHPULL(GPIOE_L3GD20_CS) | \ + PIN_OTYPE_PUSHPULL(GPIOE_LSM303DLHC_INT1) |\ + PIN_OTYPE_PUSHPULL(GPIOE_LSM303DLHC_INT2) |\ + PIN_OTYPE_PUSHPULL(GPIOE_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN15)) +#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_HIGH(GPIOE_L3GD20_INT1) | \ + PIN_OSPEED_HIGH(GPIOE_L3GD20_INT2) | \ + PIN_OSPEED_HIGH(GPIOE_LSM303DLHC_DRDY) |\ + PIN_OSPEED_HIGH(GPIOE_L3GD20_CS) | \ + PIN_OSPEED_HIGH(GPIOE_LSM303DLHC_INT1) |\ + PIN_OSPEED_HIGH(GPIOE_LSM303DLHC_INT2) |\ + PIN_OSPEED_HIGH(GPIOE_PIN6) | \ + PIN_OSPEED_HIGH(GPIOE_PIN7) | \ + PIN_OSPEED_HIGH(GPIOE_PIN8) | \ + PIN_OSPEED_HIGH(GPIOE_PIN9) | \ + PIN_OSPEED_HIGH(GPIOE_PIN10) | \ + PIN_OSPEED_HIGH(GPIOE_PIN11) | \ + PIN_OSPEED_HIGH(GPIOE_PIN12) | \ + PIN_OSPEED_HIGH(GPIOE_PIN13) | \ + PIN_OSPEED_HIGH(GPIOE_PIN14) | \ + PIN_OSPEED_HIGH(GPIOE_PIN15)) +#define VAL_GPIOE_PUPDR (PIN_PUPDR_PULLUP(GPIOE_L3GD20_INT1) | \ + PIN_PUPDR_PULLUP(GPIOE_L3GD20_INT2) | \ + PIN_PUPDR_FLOATING(GPIOE_LSM303DLHC_DRDY) |\ + PIN_PUPDR_PULLUP(GPIOE_L3GD20_CS) | \ + PIN_PUPDR_PULLUP(GPIOE_LSM303DLHC_INT1) |\ + PIN_PUPDR_PULLUP(GPIOE_LSM303DLHC_INT2) |\ + PIN_PUPDR_PULLUP(GPIOE_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN13) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN14) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN15)) +#define VAL_GPIOE_ODR (PIN_ODR_HIGH(GPIOE_L3GD20_INT1) | \ + PIN_ODR_HIGH(GPIOE_L3GD20_INT2) | \ + PIN_ODR_HIGH(GPIOE_LSM303DLHC_DRDY) | \ + PIN_ODR_HIGH(GPIOE_L3GD20_CS) | \ + PIN_ODR_HIGH(GPIOE_LSM303DLHC_INT1) | \ + PIN_ODR_HIGH(GPIOE_LSM303DLHC_INT2) | \ + PIN_ODR_HIGH(GPIOE_PIN6) | \ + PIN_ODR_HIGH(GPIOE_PIN7) | \ + PIN_ODR_HIGH(GPIOE_PIN8) | \ + PIN_ODR_HIGH(GPIOE_PIN9) | \ + PIN_ODR_HIGH(GPIOE_PIN10) | \ + PIN_ODR_HIGH(GPIOE_PIN11) | \ + PIN_ODR_HIGH(GPIOE_PIN12) | \ + PIN_ODR_HIGH(GPIOE_PIN13) | \ + PIN_ODR_HIGH(GPIOE_PIN14) | \ + PIN_ODR_HIGH(GPIOE_PIN15)) +#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_L3GD20_INT1, 0U) | \ + PIN_AFIO_AF(GPIOE_L3GD20_INT2, 0U) | \ + PIN_AFIO_AF(GPIOE_LSM303DLHC_DRDY, 0U) |\ + PIN_AFIO_AF(GPIOE_L3GD20_CS, 0U) | \ + PIN_AFIO_AF(GPIOE_LSM303DLHC_INT1, 0U) |\ + PIN_AFIO_AF(GPIOE_LSM303DLHC_INT2, 0U) |\ + PIN_AFIO_AF(GPIOE_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN7, 0U)) +#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN15, 0U)) + +/* + * GPIOF setup: + * + * PF0 - PIN0 (input pullup). + * PF1 - PIN1 (input pullup). + * PF2 - PIN2 (input pullup). + * PF3 - PIN3 (input pullup). + * PF4 - PIN4 (input pullup). + * PF5 - PIN5 (input pullup). + * PF6 - PIN6 (input pullup). + * PF7 - PIN7 (input pullup). + * PF8 - PIN8 (input pullup). + * PF9 - PIN9 (input pullup). + * PF10 - PIN10 (input pullup). + * PF11 - PIN11 (input pullup). + * PF12 - PIN12 (input pullup). + * PF13 - PIN13 (input pullup). + * PF14 - PIN14 (input pullup). + * PF15 - PIN15 (input pullup). + */ +#define VAL_GPIOF_MODER (PIN_MODE_INPUT(GPIOF_PIN0) | \ + PIN_MODE_INPUT(GPIOF_PIN1) | \ + PIN_MODE_INPUT(GPIOF_PIN2) | \ + PIN_MODE_INPUT(GPIOF_PIN3) | \ + PIN_MODE_INPUT(GPIOF_PIN4) | \ + PIN_MODE_INPUT(GPIOF_PIN5) | \ + PIN_MODE_INPUT(GPIOF_PIN6) | \ + PIN_MODE_INPUT(GPIOF_PIN7) | \ + PIN_MODE_INPUT(GPIOF_PIN8) | \ + PIN_MODE_INPUT(GPIOF_PIN9) | \ + PIN_MODE_INPUT(GPIOF_PIN10) | \ + PIN_MODE_INPUT(GPIOF_PIN11) | \ + PIN_MODE_INPUT(GPIOF_PIN12) | \ + PIN_MODE_INPUT(GPIOF_PIN13) | \ + PIN_MODE_INPUT(GPIOF_PIN14) | \ + PIN_MODE_INPUT(GPIOF_PIN15)) +#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(GPIOF_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN15)) +#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_HIGH(GPIOF_PIN0) | \ + PIN_OSPEED_HIGH(GPIOF_PIN1) | \ + PIN_OSPEED_HIGH(GPIOF_PIN2) | \ + PIN_OSPEED_HIGH(GPIOF_PIN3) | \ + PIN_OSPEED_HIGH(GPIOF_PIN4) | \ + PIN_OSPEED_HIGH(GPIOF_PIN5) | \ + PIN_OSPEED_HIGH(GPIOF_PIN6) | \ + PIN_OSPEED_HIGH(GPIOF_PIN7) | \ + PIN_OSPEED_HIGH(GPIOF_PIN8) | \ + PIN_OSPEED_HIGH(GPIOF_PIN9) | \ + PIN_OSPEED_HIGH(GPIOF_PIN10) | \ + PIN_OSPEED_HIGH(GPIOF_PIN11) | \ + PIN_OSPEED_HIGH(GPIOF_PIN12) | \ + PIN_OSPEED_HIGH(GPIOF_PIN13) | \ + PIN_OSPEED_HIGH(GPIOF_PIN14) | \ + PIN_OSPEED_HIGH(GPIOF_PIN15)) +#define VAL_GPIOF_PUPDR (PIN_PUPDR_PULLUP(GPIOF_PIN0) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN1) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN3) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN13) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN14) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN15)) +#define VAL_GPIOF_ODR (PIN_ODR_HIGH(GPIOF_PIN0) | \ + PIN_ODR_HIGH(GPIOF_PIN1) | \ + PIN_ODR_HIGH(GPIOF_PIN2) | \ + PIN_ODR_HIGH(GPIOF_PIN3) | \ + PIN_ODR_HIGH(GPIOF_PIN4) | \ + PIN_ODR_HIGH(GPIOF_PIN5) | \ + PIN_ODR_HIGH(GPIOF_PIN6) | \ + PIN_ODR_HIGH(GPIOF_PIN7) | \ + PIN_ODR_HIGH(GPIOF_PIN8) | \ + PIN_ODR_HIGH(GPIOF_PIN9) | \ + PIN_ODR_HIGH(GPIOF_PIN10) | \ + PIN_ODR_HIGH(GPIOF_PIN11) | \ + PIN_ODR_HIGH(GPIOF_PIN12) | \ + PIN_ODR_HIGH(GPIOF_PIN13) | \ + PIN_ODR_HIGH(GPIOF_PIN14) | \ + PIN_ODR_HIGH(GPIOF_PIN15)) +#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_PIN0, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN1, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN7, 0U)) +#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN15, 0U)) + +/* + * GPIOG setup: + * + * PG0 - PIN0 (input pullup). + * PG1 - PIN1 (input pullup). + * PG2 - PIN2 (input pullup). + * PG3 - PIN3 (input pullup). + * PG4 - PIN4 (input pullup). + * PG5 - PIN5 (input pullup). + * PG6 - PIN6 (input pullup). + * PG7 - PIN7 (input pullup). + * PG8 - PIN8 (input pullup). + * PG9 - PIN9 (input pullup). + * PG10 - PIN10 (input pullup). + * PG11 - PIN11 (input pullup). + * PG12 - PIN12 (input pullup). + * PG13 - PIN13 (input pullup). + * PG14 - PIN14 (input pullup). + * PG15 - PIN15 (input pullup). + */ +#define VAL_GPIOG_MODER (PIN_MODE_INPUT(GPIOG_PIN0) | \ + PIN_MODE_INPUT(GPIOG_PIN1) | \ + PIN_MODE_INPUT(GPIOG_PIN2) | \ + PIN_MODE_INPUT(GPIOG_PIN3) | \ + PIN_MODE_INPUT(GPIOG_PIN4) | \ + PIN_MODE_INPUT(GPIOG_PIN5) | \ + PIN_MODE_INPUT(GPIOG_PIN6) | \ + PIN_MODE_INPUT(GPIOG_PIN7) | \ + PIN_MODE_INPUT(GPIOG_PIN8) | \ + PIN_MODE_INPUT(GPIOG_PIN9) | \ + PIN_MODE_INPUT(GPIOG_PIN10) | \ + PIN_MODE_INPUT(GPIOG_PIN11) | \ + PIN_MODE_INPUT(GPIOG_PIN12) | \ + PIN_MODE_INPUT(GPIOG_PIN13) | \ + PIN_MODE_INPUT(GPIOG_PIN14) | \ + PIN_MODE_INPUT(GPIOG_PIN15)) +#define VAL_GPIOG_OTYPER (PIN_OTYPE_PUSHPULL(GPIOG_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN15)) +#define VAL_GPIOG_OSPEEDR (PIN_OSPEED_HIGH(GPIOG_PIN0) | \ + PIN_OSPEED_HIGH(GPIOG_PIN1) | \ + PIN_OSPEED_HIGH(GPIOG_PIN2) | \ + PIN_OSPEED_HIGH(GPIOG_PIN3) | \ + PIN_OSPEED_HIGH(GPIOG_PIN4) | \ + PIN_OSPEED_HIGH(GPIOG_PIN5) | \ + PIN_OSPEED_HIGH(GPIOG_PIN6) | \ + PIN_OSPEED_HIGH(GPIOG_PIN7) | \ + PIN_OSPEED_HIGH(GPIOG_PIN8) | \ + PIN_OSPEED_HIGH(GPIOG_PIN9) | \ + PIN_OSPEED_HIGH(GPIOG_PIN10) | \ + PIN_OSPEED_HIGH(GPIOG_PIN11) | \ + PIN_OSPEED_HIGH(GPIOG_PIN12) | \ + PIN_OSPEED_HIGH(GPIOG_PIN13) | \ + PIN_OSPEED_HIGH(GPIOG_PIN14) | \ + PIN_OSPEED_HIGH(GPIOG_PIN15)) +#define VAL_GPIOG_PUPDR (PIN_PUPDR_PULLUP(GPIOG_PIN0) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN1) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN3) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN13) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN14) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN15)) +#define VAL_GPIOG_ODR (PIN_ODR_HIGH(GPIOG_PIN0) | \ + PIN_ODR_HIGH(GPIOG_PIN1) | \ + PIN_ODR_HIGH(GPIOG_PIN2) | \ + PIN_ODR_HIGH(GPIOG_PIN3) | \ + PIN_ODR_HIGH(GPIOG_PIN4) | \ + PIN_ODR_HIGH(GPIOG_PIN5) | \ + PIN_ODR_HIGH(GPIOG_PIN6) | \ + PIN_ODR_HIGH(GPIOG_PIN7) | \ + PIN_ODR_HIGH(GPIOG_PIN8) | \ + PIN_ODR_HIGH(GPIOG_PIN9) | \ + PIN_ODR_HIGH(GPIOG_PIN10) | \ + PIN_ODR_HIGH(GPIOG_PIN11) | \ + PIN_ODR_HIGH(GPIOG_PIN12) | \ + PIN_ODR_HIGH(GPIOG_PIN13) | \ + PIN_ODR_HIGH(GPIOG_PIN14) | \ + PIN_ODR_HIGH(GPIOG_PIN15)) +#define VAL_GPIOG_AFRL (PIN_AFIO_AF(GPIOG_PIN0, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN1, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN7, 0U)) +#define VAL_GPIOG_AFRH (PIN_AFIO_AF(GPIOG_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN15, 0U)) + +/* + * GPIOH setup: + * + * PH0 - OSC_IN (input floating). + * PH1 - OSC_OUT (input floating). + * PH2 - PIN2 (input pullup). + * PH3 - PIN3 (input pullup). + * PH4 - PIN4 (input pullup). + * PH5 - PIN5 (input pullup). + * PH6 - PIN6 (input pullup). + * PH7 - PIN7 (input pullup). + * PH8 - PIN8 (input pullup). + * PH9 - PIN9 (input pullup). + * PH10 - PIN10 (input pullup). + * PH11 - PIN11 (input pullup). + * PH12 - PIN12 (input pullup). + * PH13 - PIN13 (input pullup). + * PH14 - PIN14 (input pullup). + * PH15 - PIN15 (input pullup). + */ +#define VAL_GPIOH_MODER (PIN_MODE_INPUT(GPIOH_OSC_IN) | \ + PIN_MODE_INPUT(GPIOH_OSC_OUT) | \ + PIN_MODE_INPUT(GPIOH_PIN2) | \ + PIN_MODE_INPUT(GPIOH_PIN3) | \ + PIN_MODE_INPUT(GPIOH_PIN4) | \ + PIN_MODE_INPUT(GPIOH_PIN5) | \ + PIN_MODE_INPUT(GPIOH_PIN6) | \ + PIN_MODE_INPUT(GPIOH_PIN7) | \ + PIN_MODE_INPUT(GPIOH_PIN8) | \ + PIN_MODE_INPUT(GPIOH_PIN9) | \ + PIN_MODE_INPUT(GPIOH_PIN10) | \ + PIN_MODE_INPUT(GPIOH_PIN11) | \ + PIN_MODE_INPUT(GPIOH_PIN12) | \ + PIN_MODE_INPUT(GPIOH_PIN13) | \ + PIN_MODE_INPUT(GPIOH_PIN14) | \ + PIN_MODE_INPUT(GPIOH_PIN15)) +#define VAL_GPIOH_OTYPER (PIN_OTYPE_PUSHPULL(GPIOH_OSC_IN) | \ + PIN_OTYPE_PUSHPULL(GPIOH_OSC_OUT) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN15)) +#define VAL_GPIOH_OSPEEDR (PIN_OSPEED_HIGH(GPIOH_OSC_IN) | \ + PIN_OSPEED_HIGH(GPIOH_OSC_OUT) | \ + PIN_OSPEED_HIGH(GPIOH_PIN2) | \ + PIN_OSPEED_HIGH(GPIOH_PIN3) | \ + PIN_OSPEED_HIGH(GPIOH_PIN4) | \ + PIN_OSPEED_HIGH(GPIOH_PIN5) | \ + PIN_OSPEED_HIGH(GPIOH_PIN6) | \ + PIN_OSPEED_HIGH(GPIOH_PIN7) | \ + PIN_OSPEED_HIGH(GPIOH_PIN8) | \ + PIN_OSPEED_HIGH(GPIOH_PIN9) | \ + PIN_OSPEED_HIGH(GPIOH_PIN10) | \ + PIN_OSPEED_HIGH(GPIOH_PIN11) | \ + PIN_OSPEED_HIGH(GPIOH_PIN12) | \ + PIN_OSPEED_HIGH(GPIOH_PIN13) | \ + PIN_OSPEED_HIGH(GPIOH_PIN14) | \ + PIN_OSPEED_HIGH(GPIOH_PIN15)) +#define VAL_GPIOH_PUPDR (PIN_PUPDR_FLOATING(GPIOH_OSC_IN) | \ + PIN_PUPDR_FLOATING(GPIOH_OSC_OUT) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN3) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN13) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN14) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN15)) +#define VAL_GPIOH_ODR (PIN_ODR_HIGH(GPIOH_OSC_IN) | \ + PIN_ODR_HIGH(GPIOH_OSC_OUT) | \ + PIN_ODR_HIGH(GPIOH_PIN2) | \ + PIN_ODR_HIGH(GPIOH_PIN3) | \ + PIN_ODR_HIGH(GPIOH_PIN4) | \ + PIN_ODR_HIGH(GPIOH_PIN5) | \ + PIN_ODR_HIGH(GPIOH_PIN6) | \ + PIN_ODR_HIGH(GPIOH_PIN7) | \ + PIN_ODR_HIGH(GPIOH_PIN8) | \ + PIN_ODR_HIGH(GPIOH_PIN9) | \ + PIN_ODR_HIGH(GPIOH_PIN10) | \ + PIN_ODR_HIGH(GPIOH_PIN11) | \ + PIN_ODR_HIGH(GPIOH_PIN12) | \ + PIN_ODR_HIGH(GPIOH_PIN13) | \ + PIN_ODR_HIGH(GPIOH_PIN14) | \ + PIN_ODR_HIGH(GPIOH_PIN15)) +#define VAL_GPIOH_AFRL (PIN_AFIO_AF(GPIOH_OSC_IN, 0U) | \ + PIN_AFIO_AF(GPIOH_OSC_OUT, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN7, 0U)) +#define VAL_GPIOH_AFRH (PIN_AFIO_AF(GPIOH_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN15, 0U)) + +/* + * GPIOI setup: + * + * PI0 - PIN0 (input pullup). + * PI1 - PIN1 (input pullup). + * PI2 - PIN2 (input pullup). + * PI3 - PIN3 (input pullup). + * PI4 - PIN4 (input pullup). + * PI5 - PIN5 (input pullup). + * PI6 - PIN6 (input pullup). + * PI7 - PIN7 (input pullup). + * PI8 - PIN8 (input pullup). + * PI9 - PIN9 (input pullup). + * PI10 - PIN10 (input pullup). + * PI11 - PIN11 (input pullup). + * PI12 - PIN12 (input pullup). + * PI13 - PIN13 (input pullup). + * PI14 - PIN14 (input pullup). + * PI15 - PIN15 (input pullup). + */ +#define VAL_GPIOI_MODER (PIN_MODE_INPUT(GPIOI_PIN0) | \ + PIN_MODE_INPUT(GPIOI_PIN1) | \ + PIN_MODE_INPUT(GPIOI_PIN2) | \ + PIN_MODE_INPUT(GPIOI_PIN3) | \ + PIN_MODE_INPUT(GPIOI_PIN4) | \ + PIN_MODE_INPUT(GPIOI_PIN5) | \ + PIN_MODE_INPUT(GPIOI_PIN6) | \ + PIN_MODE_INPUT(GPIOI_PIN7) | \ + PIN_MODE_INPUT(GPIOI_PIN8) | \ + PIN_MODE_INPUT(GPIOI_PIN9) | \ + PIN_MODE_INPUT(GPIOI_PIN10) | \ + PIN_MODE_INPUT(GPIOI_PIN11) | \ + PIN_MODE_INPUT(GPIOI_PIN12) | \ + PIN_MODE_INPUT(GPIOI_PIN13) | \ + PIN_MODE_INPUT(GPIOI_PIN14) | \ + PIN_MODE_INPUT(GPIOI_PIN15)) +#define VAL_GPIOI_OTYPER (PIN_OTYPE_PUSHPULL(GPIOI_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN15)) +#define VAL_GPIOI_OSPEEDR (PIN_OSPEED_HIGH(GPIOI_PIN0) | \ + PIN_OSPEED_HIGH(GPIOI_PIN1) | \ + PIN_OSPEED_HIGH(GPIOI_PIN2) | \ + PIN_OSPEED_HIGH(GPIOI_PIN3) | \ + PIN_OSPEED_HIGH(GPIOI_PIN4) | \ + PIN_OSPEED_HIGH(GPIOI_PIN5) | \ + PIN_OSPEED_HIGH(GPIOI_PIN6) | \ + PIN_OSPEED_HIGH(GPIOI_PIN7) | \ + PIN_OSPEED_HIGH(GPIOI_PIN8) | \ + PIN_OSPEED_HIGH(GPIOI_PIN9) | \ + PIN_OSPEED_HIGH(GPIOI_PIN10) | \ + PIN_OSPEED_HIGH(GPIOI_PIN11) | \ + PIN_OSPEED_HIGH(GPIOI_PIN12) | \ + PIN_OSPEED_HIGH(GPIOI_PIN13) | \ + PIN_OSPEED_HIGH(GPIOI_PIN14) | \ + PIN_OSPEED_HIGH(GPIOI_PIN15)) +#define VAL_GPIOI_PUPDR (PIN_PUPDR_PULLUP(GPIOI_PIN0) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN1) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN3) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN13) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN14) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN15)) +#define VAL_GPIOI_ODR (PIN_ODR_HIGH(GPIOI_PIN0) | \ + PIN_ODR_HIGH(GPIOI_PIN1) | \ + PIN_ODR_HIGH(GPIOI_PIN2) | \ + PIN_ODR_HIGH(GPIOI_PIN3) | \ + PIN_ODR_HIGH(GPIOI_PIN4) | \ + PIN_ODR_HIGH(GPIOI_PIN5) | \ + PIN_ODR_HIGH(GPIOI_PIN6) | \ + PIN_ODR_HIGH(GPIOI_PIN7) | \ + PIN_ODR_HIGH(GPIOI_PIN8) | \ + PIN_ODR_HIGH(GPIOI_PIN9) | \ + PIN_ODR_HIGH(GPIOI_PIN10) | \ + PIN_ODR_HIGH(GPIOI_PIN11) | \ + PIN_ODR_HIGH(GPIOI_PIN12) | \ + PIN_ODR_HIGH(GPIOI_PIN13) | \ + PIN_ODR_HIGH(GPIOI_PIN14) | \ + PIN_ODR_HIGH(GPIOI_PIN15)) +#define VAL_GPIOI_AFRL (PIN_AFIO_AF(GPIOI_PIN0, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN1, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN7, 0U)) +#define VAL_GPIOI_AFRH (PIN_AFIO_AF(GPIOI_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN15, 0U)) + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if !defined(_FROM_ASM_) +#ifdef __cplusplus +extern "C" { +#endif + void boardInit(void); +#ifdef __cplusplus +} +#endif +#endif /* _FROM_ASM_ */ + +#endif /* BOARD_H */ diff --git a/platforms/chibios/boards/STEMCELL/board/board.mk b/platforms/chibios/boards/STEMCELL/board/board.mk new file mode 100644 index 000000000000..842e33590594 --- /dev/null +++ b/platforms/chibios/boards/STEMCELL/board/board.mk @@ -0,0 +1,9 @@ +# List of all the board related files. +BOARDSRC = $(BOARD_PATH)/board/board.c + +# Required include directories +BOARDINC = $(BOARD_PATH)/board + +# Shared variables +ALLCSRC += $(BOARDSRC) +ALLINC += $(BOARDINC) diff --git a/platforms/chibios/boards/STEMCELL/configs/board.h b/platforms/chibios/boards/STEMCELL/configs/board.h new file mode 100644 index 000000000000..30af6b0c8608 --- /dev/null +++ b/platforms/chibios/boards/STEMCELL/configs/board.h @@ -0,0 +1,20 @@ +/* Copyright 2020 Nick Brassel (tzarc) + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +#pragma once + +#include_next "board.h" + +#undef STM32_HSE_BYPASS diff --git a/platforms/chibios/boards/STEMCELL/configs/bootloader_defs.h b/platforms/chibios/boards/STEMCELL/configs/bootloader_defs.h new file mode 100644 index 000000000000..4da3d39a3268 --- /dev/null +++ b/platforms/chibios/boards/STEMCELL/configs/bootloader_defs.h @@ -0,0 +1,5 @@ +/* Address for jumping to bootloader on STM32 chips. */ +/* It is chip dependent, the correct number can be looked up here: + * http://www.st.com/web/en/resource/technical/document/application_note/CD00167594.pdf + */ +#define STM32_BOOTLOADER_ADDRESS 0x1FFF0000 diff --git a/platforms/chibios/boards/STEMCELL/configs/chconf.h b/platforms/chibios/boards/STEMCELL/configs/chconf.h new file mode 100644 index 000000000000..9e1b1727359f --- /dev/null +++ b/platforms/chibios/boards/STEMCELL/configs/chconf.h @@ -0,0 +1,6 @@ +#pragma once + +#define CH_CFG_ST_RESOLUTION 16 +#define CH_CFG_ST_FREQUENCY 10000 + +#include_next diff --git a/platforms/chibios/boards/STEMCELL/configs/config.h b/platforms/chibios/boards/STEMCELL/configs/config.h new file mode 100644 index 000000000000..ec551acfc886 --- /dev/null +++ b/platforms/chibios/boards/STEMCELL/configs/config.h @@ -0,0 +1,25 @@ +/* Copyright 2020 Nick Brassel (tzarc) + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +#pragma once + +// Only HSE clock. No LSE clock +#ifndef STM32_HSECLK +# define STM32_HSECLK 8000000U +#endif // STM32_HSECLK + +#ifndef EARLY_INIT_PERFORM_BOOTLOADER_JUMP +# define EARLY_INIT_PERFORM_BOOTLOADER_JUMP TRUE +#endif diff --git a/platforms/chibios/boards/STEMCELL/configs/halconf.h b/platforms/chibios/boards/STEMCELL/configs/halconf.h new file mode 100644 index 000000000000..3193d60e746f --- /dev/null +++ b/platforms/chibios/boards/STEMCELL/configs/halconf.h @@ -0,0 +1,27 @@ +/* Copyright 2020 Nick Brassel (tzarc) + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +#pragma once + +// #define HAL_USE_DAC TRUE +#define PAL_USE_WAIT TRUE +#define PAL_USE_CALLBACKS TRUE + +// #define HAL_USE_PWM TRUE +#define HAL_USE_I2C TRUE + +#define HAL_USE_SERIAL TRUE + +#include_next diff --git a/platforms/chibios/boards/STEMCELL/configs/mcuconf.h b/platforms/chibios/boards/STEMCELL/configs/mcuconf.h new file mode 100644 index 000000000000..ddbaf725c2fc --- /dev/null +++ b/platforms/chibios/boards/STEMCELL/configs/mcuconf.h @@ -0,0 +1,244 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef MCUCONF_H +#define MCUCONF_H + +/* + * STM32F4xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32F4xx_MCUCONF +#define STM32F401_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 +#define STM32_BKPRAM_ENABLE FALSE +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED FALSE +#define STM32_CLOCK48_REQUIRED TRUE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PLLM_VALUE 8 +#define STM32_PLLN_VALUE 336 +#define STM32_PLLP_VALUE 4 +#define STM32_PLLQ_VALUE 7 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV4 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_RTCSEL STM32_RTCSEL_LSI +#define STM32_RTCPRE_VALUE 8 +#define STM32_MCO1SEL STM32_MCO1SEL_HSI +#define STM32_MCO1PRE STM32_MCO1PRE_DIV1 +#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK +#define STM32_MCO2PRE STM32_MCO2PRE_DIV5 +#define STM32_I2SSRC STM32_I2SSRC_CKIN +#define STM32_PLLI2SN_VALUE 192 +#define STM32_PLLI2SR_VALUE 5 + +/* + * IRQ system settings. + */ +#define STM32_IRQ_EXTI0_PRIORITY 6 +#define STM32_IRQ_EXTI1_PRIORITY 6 +#define STM32_IRQ_EXTI2_PRIORITY 6 +#define STM32_IRQ_EXTI3_PRIORITY 6 +#define STM32_IRQ_EXTI4_PRIORITY 6 +#define STM32_IRQ_EXTI5_9_PRIORITY 6 +#define STM32_IRQ_EXTI10_15_PRIORITY 6 +#define STM32_IRQ_EXTI16_PRIORITY 6 +#define STM32_IRQ_EXTI17_PRIORITY 15 +#define STM32_IRQ_EXTI18_PRIORITY 6 +#define STM32_IRQ_EXTI19_PRIORITY 6 +#define STM32_IRQ_EXTI20_PRIORITY 6 +#define STM32_IRQ_EXTI21_PRIORITY 15 +#define STM32_IRQ_EXTI22_PRIORITY 15 + +#define STM32_IRQ_TIM1_BRK_TIM9_PRIORITY 7 +#define STM32_IRQ_TIM1_UP_TIM10_PRIORITY 7 +#define STM32_IRQ_TIM1_TRGCO_TIM11_PRIORITY 7 +#define STM32_IRQ_TIM1_CC_PRIORITY 7 +#define STM32_IRQ_TIM2_PRIORITY 7 +#define STM32_IRQ_TIM3_PRIORITY 7 +#define STM32_IRQ_TIM4_PRIORITY 7 +#define STM32_IRQ_TIM5_PRIORITY 7 + +#define STM32_IRQ_USART1_PRIORITY 12 +#define STM32_IRQ_USART2_PRIORITY 12 +#define STM32_IRQ_USART6_PRIORITY 12 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4 +#define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_IRQ_PRIORITY 6 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM9 FALSE +#define STM32_GPT_USE_TIM10 FALSE +#define STM32_GPT_USE_TIM11 FALSE + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 TRUE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_USE_I2C3 FALSE +#define STM32_I2C_BUSY_TIMEOUT 50 +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2C_I2C1_IRQ_PRIORITY 5 +#define STM32_I2C_I2C2_IRQ_PRIORITY 5 +#define STM32_I2C_I2C3_IRQ_PRIORITY 5 +#define STM32_I2C_I2C1_DMA_PRIORITY 3 +#define STM32_I2C_I2C2_DMA_PRIORITY 3 +#define STM32_I2C_I2C3_DMA_PRIORITY 3 +#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") + +/* + * I2S driver system settings. + */ +#define STM32_I2S_USE_SPI2 FALSE +#define STM32_I2S_USE_SPI3 FALSE +#define STM32_I2S_SPI2_IRQ_PRIORITY 10 +#define STM32_I2S_SPI3_IRQ_PRIORITY 10 +#define STM32_I2S_SPI2_DMA_PRIORITY 1 +#define STM32_I2S_SPI3_DMA_PRIORITY 1 +#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2S_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_I2S_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure") + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM9 FALSE +#define STM32_ICU_USE_TIM10 FALSE +#define STM32_ICU_USE_TIM11 FALSE + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_USE_TIM9 FALSE +#define STM32_PWM_USE_TIM10 FALSE +#define STM32_PWM_USE_TIM11 FALSE + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 TRUE +#define STM32_SERIAL_USE_USART2 TRUE +#define STM32_SERIAL_USE_USART6 FALSE + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") + +/* + * ST driver system settings. + */ +#define STM32_ST_IRQ_PRIORITY 8 +#define STM32_ST_USE_TIMER 2 + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART6 FALSE +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART6_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_OTG1 TRUE +#define STM32_USB_OTG1_IRQ_PRIORITY 14 +#define STM32_USB_OTG1_RX_FIFO_SIZE 512 +#define STM32_USB_HOST_WAKEUP_DURATION 2 + +/* + * WDG driver system settings. + */ +#define STM32_WDG_USE_IWDG FALSE + +#endif /* MCUCONF_H */ diff --git a/platforms/chibios/boards/STEMCELL/convert_to_stemcell.mk b/platforms/chibios/boards/STEMCELL/convert_to_stemcell.mk new file mode 100644 index 000000000000..d32bd0276034 --- /dev/null +++ b/platforms/chibios/boards/STEMCELL/convert_to_stemcell.mk @@ -0,0 +1,12 @@ +# Proton C MCU settings for converting AVR projects +TARGET := $(TARGET)_stemcell +MCU := STM32F401 +BOARD := STEMCELL +BOOTLOADER := tinyuf2 +OPT_DEFS += -DCONVERT_TO_STEMCELL + +SERIAL_DRIVER := usart + +# These are defaults based on what has been implemented for ARM boards +AUDIO_ENABLE ?= no +WS2812_DRIVER ?= bitbang diff --git a/platforms/chibios/boards/STEMCELL/ld/STEMCELL_tinyuf2.ld b/platforms/chibios/boards/STEMCELL/ld/STEMCELL_tinyuf2.ld new file mode 100644 index 000000000000..f4e487dc8f92 --- /dev/null +++ b/platforms/chibios/boards/STEMCELL/ld/STEMCELL_tinyuf2.ld @@ -0,0 +1,88 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * STM32F401xC memory setup. + */ +MEMORY +{ + flash0 (rx) : org = 0x08000000 + 64k, len = 256k - 64k /* tinyuf2 bootloader requires app to be located at 64k offset for this MCU */ + flash1 (rx) : org = 0x00000000, len = 0 + flash2 (rx) : org = 0x00000000, len = 0 + flash3 (rx) : org = 0x00000000, len = 0 + flash4 (rx) : org = 0x00000000, len = 0 + flash5 (rx) : org = 0x00000000, len = 0 + flash6 (rx) : org = 0x00000000, len = 0 + flash7 (rx) : org = 0x00000000, len = 0 + ram0 (wx) : org = 0x20000000, len = 64k + ram1 (wx) : org = 0x00000000, len = 0 + ram2 (wx) : org = 0x00000000, len = 0 + ram3 (wx) : org = 0x00000000, len = 0 + ram4 (wx) : org = 0x00000000, len = 0 + ram5 (wx) : org = 0x00000000, len = 0 + ram6 (wx) : org = 0x00000000, len = 0 + ram7 (wx) : org = 0x00000000, len = 0 +} + +/* For each data/text section two region are defined, a virtual region + and a load region (_LMA suffix).*/ + +/* Flash region to be used for exception vectors.*/ +REGION_ALIAS("VECTORS_FLASH", flash0); +REGION_ALIAS("VECTORS_FLASH_LMA", flash0); + +/* Flash region to be used for constructors and destructors.*/ +REGION_ALIAS("XTORS_FLASH", flash0); +REGION_ALIAS("XTORS_FLASH_LMA", flash0); + +/* Flash region to be used for code text.*/ +REGION_ALIAS("TEXT_FLASH", flash0); +REGION_ALIAS("TEXT_FLASH_LMA", flash0); + +/* Flash region to be used for read only data.*/ +REGION_ALIAS("RODATA_FLASH", flash0); +REGION_ALIAS("RODATA_FLASH_LMA", flash0); + +/* Flash region to be used for various.*/ +REGION_ALIAS("VARIOUS_FLASH", flash0); +REGION_ALIAS("VARIOUS_FLASH_LMA", flash0); + +/* Flash region to be used for RAM(n) initialization data.*/ +REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0); + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts.*/ +REGION_ALIAS("MAIN_STACK_RAM", ram0); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram0); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); +REGION_ALIAS("DATA_RAM_LMA", flash0); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram0); + +/* RAM region to be used for the default heap.*/ +REGION_ALIAS("HEAP_RAM", ram0); + +/* Generic rules inclusion.*/ +INCLUDE rules.ld + +/* TinyUF2 bootloader reset support */ +_board_dfu_dbl_tap = ORIGIN(ram0) + 64k - 4; /* this is based off the linker file for tinyuf2 */ diff --git a/platforms/chibios/boards/STEMCELL/ld/STM32F401xC_tinyuf2.ld b/platforms/chibios/boards/STEMCELL/ld/STM32F401xC_tinyuf2.ld new file mode 100644 index 000000000000..f4e487dc8f92 --- /dev/null +++ b/platforms/chibios/boards/STEMCELL/ld/STM32F401xC_tinyuf2.ld @@ -0,0 +1,88 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * STM32F401xC memory setup. + */ +MEMORY +{ + flash0 (rx) : org = 0x08000000 + 64k, len = 256k - 64k /* tinyuf2 bootloader requires app to be located at 64k offset for this MCU */ + flash1 (rx) : org = 0x00000000, len = 0 + flash2 (rx) : org = 0x00000000, len = 0 + flash3 (rx) : org = 0x00000000, len = 0 + flash4 (rx) : org = 0x00000000, len = 0 + flash5 (rx) : org = 0x00000000, len = 0 + flash6 (rx) : org = 0x00000000, len = 0 + flash7 (rx) : org = 0x00000000, len = 0 + ram0 (wx) : org = 0x20000000, len = 64k + ram1 (wx) : org = 0x00000000, len = 0 + ram2 (wx) : org = 0x00000000, len = 0 + ram3 (wx) : org = 0x00000000, len = 0 + ram4 (wx) : org = 0x00000000, len = 0 + ram5 (wx) : org = 0x00000000, len = 0 + ram6 (wx) : org = 0x00000000, len = 0 + ram7 (wx) : org = 0x00000000, len = 0 +} + +/* For each data/text section two region are defined, a virtual region + and a load region (_LMA suffix).*/ + +/* Flash region to be used for exception vectors.*/ +REGION_ALIAS("VECTORS_FLASH", flash0); +REGION_ALIAS("VECTORS_FLASH_LMA", flash0); + +/* Flash region to be used for constructors and destructors.*/ +REGION_ALIAS("XTORS_FLASH", flash0); +REGION_ALIAS("XTORS_FLASH_LMA", flash0); + +/* Flash region to be used for code text.*/ +REGION_ALIAS("TEXT_FLASH", flash0); +REGION_ALIAS("TEXT_FLASH_LMA", flash0); + +/* Flash region to be used for read only data.*/ +REGION_ALIAS("RODATA_FLASH", flash0); +REGION_ALIAS("RODATA_FLASH_LMA", flash0); + +/* Flash region to be used for various.*/ +REGION_ALIAS("VARIOUS_FLASH", flash0); +REGION_ALIAS("VARIOUS_FLASH_LMA", flash0); + +/* Flash region to be used for RAM(n) initialization data.*/ +REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0); + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts.*/ +REGION_ALIAS("MAIN_STACK_RAM", ram0); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram0); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); +REGION_ALIAS("DATA_RAM_LMA", flash0); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram0); + +/* RAM region to be used for the default heap.*/ +REGION_ALIAS("HEAP_RAM", ram0); + +/* Generic rules inclusion.*/ +INCLUDE rules.ld + +/* TinyUF2 bootloader reset support */ +_board_dfu_dbl_tap = ORIGIN(ram0) + 64k - 4; /* this is based off the linker file for tinyuf2 */ diff --git a/platforms/chibios/pin_defs.h b/platforms/chibios/pin_defs.h index c03f8de0c253..357347052169 100644 --- a/platforms/chibios/pin_defs.h +++ b/platforms/chibios/pin_defs.h @@ -53,6 +53,63 @@ # define D5 PAL_LINE(GPIOC, 13) # define B0 PAL_LINE(GPIOC, 14) # endif + +#elif defined(CONVERT_TO_STEMCELL) + +/* #if SOFT_SERIAL_PIN==D0 || SOFT_SERIAL_PIN==D1 +# define SERIAL_USART_DRIVER SD1 +# define USART1_REMAP +#elif SOFT_SERIAL_PIN==D2 || SOFT_SERIAL_PIN==D3 +# define SERIAL_USART_DRIVER SD2 +# define USART2_REMAP +#endif */ + +// Left side (front) +# ifdef CONVERT_TO_STEMCELL_UART_SWAP +# define D3 PAL_LINE(GPIOA, 3) +# define D2 PAL_LINE(GPIOA, 2) +# else +# define D3 PAL_LINE(GPIOA, 2) +# define D2 PAL_LINE(GPIOA, 3) +# endif +// GND +// GND +# ifdef CONVERT_TO_STEMCELL_I2C_SWAP +# define D1 PAL_LINE(GPIOB, 6) +# define D0 PAL_LINE(GPIOB, 7) +# else +# define D1 PAL_LINE(GPIOB, 7) +# define D0 PAL_LINE(GPIOB, 6) +# endif + +# define D4 PAL_LINE(GPIOA, 15) +# define C6 PAL_LINE(GPIOB, 3) +# define D7 PAL_LINE(GPIOB, 4) +# define E6 PAL_LINE(GPIOB, 5) +# define B4 PAL_LINE(GPIOB, 8) +# define B5 PAL_LINE(GPIOB, 9) + +// Right side (front) +// RAW +// GND +// RESET +// VCC +# define F4 PAL_LINE(GPIOB, 10) +# define F5 PAL_LINE(GPIOB, 2) +# define F6 PAL_LINE(GPIOB, 1) +# define F7 PAL_LINE(GPIOB, 0) +# define B1 PAL_LINE(GPIOA, 7) +# define B3 PAL_LINE(GPIOA, 6) +# define B2 PAL_LINE(GPIOA, 5) +# define B6 PAL_LINE(GPIOA, 4) + +# define D5 PAL_LINE(GPIOA, 8) +# define B0 PAL_LINE(GPIOA, 9) // unconnected pin + +# define SERIAL_USART_DRIVER SD1 +# define I2C1_SCL_PIN D0 +# define I2C1_SDA_PIN D1 + #else # define A0 PAL_LINE(GPIOA, 0) # define A1 PAL_LINE(GPIOA, 1) From 3cbf5192724a1de0506c25cedc2e584f9bcc0322 Mon Sep 17 00:00:00 2001 From: Mariappan Ramasamy <947300+Mariappan@users.noreply.github.com> Date: Mon, 7 Feb 2022 11:30:52 +0800 Subject: [PATCH 02/20] Use custom ld script --- .../boards/STEMCELL/convert_to_stemcell.mk | 2 + .../boards/STEMCELL/ld/STEMCELL_tinyuf2.ld | 4 +- .../boards/STEMCELL/ld/STM32F401xC_tinyuf2.ld | 88 ------------------- 3 files changed, 5 insertions(+), 89 deletions(-) delete mode 100644 platforms/chibios/boards/STEMCELL/ld/STM32F401xC_tinyuf2.ld diff --git a/platforms/chibios/boards/STEMCELL/convert_to_stemcell.mk b/platforms/chibios/boards/STEMCELL/convert_to_stemcell.mk index d32bd0276034..39578f67b742 100644 --- a/platforms/chibios/boards/STEMCELL/convert_to_stemcell.mk +++ b/platforms/chibios/boards/STEMCELL/convert_to_stemcell.mk @@ -4,6 +4,8 @@ MCU := STM32F401 BOARD := STEMCELL BOOTLOADER := tinyuf2 OPT_DEFS += -DCONVERT_TO_STEMCELL +MCU_LDSCRIPT := STEMCELL_tinyuf2 +FIRMWARE_FORMAT := uf2 SERIAL_DRIVER := usart diff --git a/platforms/chibios/boards/STEMCELL/ld/STEMCELL_tinyuf2.ld b/platforms/chibios/boards/STEMCELL/ld/STEMCELL_tinyuf2.ld index f4e487dc8f92..b590d3c7a87a 100644 --- a/platforms/chibios/boards/STEMCELL/ld/STEMCELL_tinyuf2.ld +++ b/platforms/chibios/boards/STEMCELL/ld/STEMCELL_tinyuf2.ld @@ -1,5 +1,6 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + Copyright (C) 2022 Mega Mind Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -15,8 +16,9 @@ */ /* - * STM32F401xC memory setup. + * STeMCell (STM32F4x1Cx) memory setup. */ + MEMORY { flash0 (rx) : org = 0x08000000 + 64k, len = 256k - 64k /* tinyuf2 bootloader requires app to be located at 64k offset for this MCU */ diff --git a/platforms/chibios/boards/STEMCELL/ld/STM32F401xC_tinyuf2.ld b/platforms/chibios/boards/STEMCELL/ld/STM32F401xC_tinyuf2.ld deleted file mode 100644 index f4e487dc8f92..000000000000 --- a/platforms/chibios/boards/STEMCELL/ld/STM32F401xC_tinyuf2.ld +++ /dev/null @@ -1,88 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * STM32F401xC memory setup. - */ -MEMORY -{ - flash0 (rx) : org = 0x08000000 + 64k, len = 256k - 64k /* tinyuf2 bootloader requires app to be located at 64k offset for this MCU */ - flash1 (rx) : org = 0x00000000, len = 0 - flash2 (rx) : org = 0x00000000, len = 0 - flash3 (rx) : org = 0x00000000, len = 0 - flash4 (rx) : org = 0x00000000, len = 0 - flash5 (rx) : org = 0x00000000, len = 0 - flash6 (rx) : org = 0x00000000, len = 0 - flash7 (rx) : org = 0x00000000, len = 0 - ram0 (wx) : org = 0x20000000, len = 64k - ram1 (wx) : org = 0x00000000, len = 0 - ram2 (wx) : org = 0x00000000, len = 0 - ram3 (wx) : org = 0x00000000, len = 0 - ram4 (wx) : org = 0x00000000, len = 0 - ram5 (wx) : org = 0x00000000, len = 0 - ram6 (wx) : org = 0x00000000, len = 0 - ram7 (wx) : org = 0x00000000, len = 0 -} - -/* For each data/text section two region are defined, a virtual region - and a load region (_LMA suffix).*/ - -/* Flash region to be used for exception vectors.*/ -REGION_ALIAS("VECTORS_FLASH", flash0); -REGION_ALIAS("VECTORS_FLASH_LMA", flash0); - -/* Flash region to be used for constructors and destructors.*/ -REGION_ALIAS("XTORS_FLASH", flash0); -REGION_ALIAS("XTORS_FLASH_LMA", flash0); - -/* Flash region to be used for code text.*/ -REGION_ALIAS("TEXT_FLASH", flash0); -REGION_ALIAS("TEXT_FLASH_LMA", flash0); - -/* Flash region to be used for read only data.*/ -REGION_ALIAS("RODATA_FLASH", flash0); -REGION_ALIAS("RODATA_FLASH_LMA", flash0); - -/* Flash region to be used for various.*/ -REGION_ALIAS("VARIOUS_FLASH", flash0); -REGION_ALIAS("VARIOUS_FLASH_LMA", flash0); - -/* Flash region to be used for RAM(n) initialization data.*/ -REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0); - -/* RAM region to be used for Main stack. This stack accommodates the processing - of all exceptions and interrupts.*/ -REGION_ALIAS("MAIN_STACK_RAM", ram0); - -/* RAM region to be used for the process stack. This is the stack used by - the main() function.*/ -REGION_ALIAS("PROCESS_STACK_RAM", ram0); - -/* RAM region to be used for data segment.*/ -REGION_ALIAS("DATA_RAM", ram0); -REGION_ALIAS("DATA_RAM_LMA", flash0); - -/* RAM region to be used for BSS segment.*/ -REGION_ALIAS("BSS_RAM", ram0); - -/* RAM region to be used for the default heap.*/ -REGION_ALIAS("HEAP_RAM", ram0); - -/* Generic rules inclusion.*/ -INCLUDE rules.ld - -/* TinyUF2 bootloader reset support */ -_board_dfu_dbl_tap = ORIGIN(ram0) + 64k - 4; /* this is based off the linker file for tinyuf2 */ From 162601d2bb0179b8d22a6c1731a72182d13b85bd Mon Sep 17 00:00:00 2001 From: Mariappan Ramasamy Date: Mon, 7 Feb 2022 14:14:11 +0800 Subject: [PATCH 03/20] Add copyright --- platforms/chibios/boards/STEMCELL/board/board.c | 1 + platforms/chibios/boards/STEMCELL/board/board.h | 7 ++++--- platforms/chibios/boards/STEMCELL/configs/board.h | 1 + platforms/chibios/boards/STEMCELL/configs/config.h | 1 + platforms/chibios/boards/STEMCELL/configs/halconf.h | 1 + 5 files changed, 8 insertions(+), 3 deletions(-) diff --git a/platforms/chibios/boards/STEMCELL/board/board.c b/platforms/chibios/boards/STEMCELL/board/board.c index 9ff3f758c123..4b7092fa7ab0 100644 --- a/platforms/chibios/boards/STEMCELL/board/board.c +++ b/platforms/chibios/boards/STEMCELL/board/board.c @@ -1,5 +1,6 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + Copyright (C) 2022 Mega Mind Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/platforms/chibios/boards/STEMCELL/board/board.h b/platforms/chibios/boards/STEMCELL/board/board.h index b8be7c18eeca..ed6621345be6 100644 --- a/platforms/chibios/boards/STEMCELL/board/board.h +++ b/platforms/chibios/boards/STEMCELL/board/board.h @@ -1,5 +1,6 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + Copyright (C) 2022 Mega Mind Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -27,14 +28,14 @@ /*===========================================================================*/ /* - * Setup for STMicroelectronics STM32F401C-Discovery board. + * Setup for STeMCell */ /* * Board identifier. */ -#define BOARD_ST_STM32F401C_DISCOVERY -#define BOARD_NAME "STMicroelectronics STM32F401C-Discovery" +#define BOARD_STEMCELL +#define BOARD_NAME "STeMCell" /* * Board oscillators-related settings. diff --git a/platforms/chibios/boards/STEMCELL/configs/board.h b/platforms/chibios/boards/STEMCELL/configs/board.h index 30af6b0c8608..f3d3cade416f 100644 --- a/platforms/chibios/boards/STEMCELL/configs/board.h +++ b/platforms/chibios/boards/STEMCELL/configs/board.h @@ -1,4 +1,5 @@ /* Copyright 2020 Nick Brassel (tzarc) + * Copyright (C) 2022 Mega Mind * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/platforms/chibios/boards/STEMCELL/configs/config.h b/platforms/chibios/boards/STEMCELL/configs/config.h index ec551acfc886..e611618c541c 100644 --- a/platforms/chibios/boards/STEMCELL/configs/config.h +++ b/platforms/chibios/boards/STEMCELL/configs/config.h @@ -1,4 +1,5 @@ /* Copyright 2020 Nick Brassel (tzarc) + * Copyright (C) 2022 Mega Mind * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/platforms/chibios/boards/STEMCELL/configs/halconf.h b/platforms/chibios/boards/STEMCELL/configs/halconf.h index 3193d60e746f..f7d9cf10c804 100644 --- a/platforms/chibios/boards/STEMCELL/configs/halconf.h +++ b/platforms/chibios/boards/STEMCELL/configs/halconf.h @@ -1,4 +1,5 @@ /* Copyright 2020 Nick Brassel (tzarc) + * Copyright (C) 2022 Mega Mind * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by From 6d9055e803be132be3c591c07c6c78e4c0983e35 Mon Sep 17 00:00:00 2001 From: Mariappan Ramasamy <947300+Mariappan@users.noreply.github.com> Date: Tue, 8 Feb 2022 00:30:08 +0800 Subject: [PATCH 04/20] Fix ld script and added some EEPROM hack --- .../boards/STEMCELL/ld/STEMCELL_tinyuf2.ld | 32 +++++++++---------- platforms/chibios/flash_stm32.c | 10 +++++- platforms/chibios/pin_defs.h | 1 + 3 files changed, 26 insertions(+), 17 deletions(-) diff --git a/platforms/chibios/boards/STEMCELL/ld/STEMCELL_tinyuf2.ld b/platforms/chibios/boards/STEMCELL/ld/STEMCELL_tinyuf2.ld index b590d3c7a87a..3abd470edefe 100644 --- a/platforms/chibios/boards/STEMCELL/ld/STEMCELL_tinyuf2.ld +++ b/platforms/chibios/boards/STEMCELL/ld/STEMCELL_tinyuf2.ld @@ -21,10 +21,10 @@ MEMORY { - flash0 (rx) : org = 0x08000000 + 64k, len = 256k - 64k /* tinyuf2 bootloader requires app to be located at 64k offset for this MCU */ - flash1 (rx) : org = 0x00000000, len = 0 - flash2 (rx) : org = 0x00000000, len = 0 - flash3 (rx) : org = 0x00000000, len = 0 + flash0 (rx) : org = 0x08000000, len = 64k /* Sector 0 - TinyUF2 bootloader */ + flash1 (rx) : org = 0x08010000, len = 16k /* Sector 1 - Init Code */ + flash2 (rx) : org = 0x08014000, len = 16k /* Sector 2 - Emulated eeprom */ + flash3 (rx) : org = 0x08018000, len = 256k - 96k /* Sector 3 - Firmware code */ flash4 (rx) : org = 0x00000000, len = 0 flash5 (rx) : org = 0x00000000, len = 0 flash6 (rx) : org = 0x00000000, len = 0 @@ -43,27 +43,27 @@ MEMORY and a load region (_LMA suffix).*/ /* Flash region to be used for exception vectors.*/ -REGION_ALIAS("VECTORS_FLASH", flash0); -REGION_ALIAS("VECTORS_FLASH_LMA", flash0); +REGION_ALIAS("VECTORS_FLASH", flash1); +REGION_ALIAS("VECTORS_FLASH_LMA", flash1); /* Flash region to be used for constructors and destructors.*/ -REGION_ALIAS("XTORS_FLASH", flash0); -REGION_ALIAS("XTORS_FLASH_LMA", flash0); +REGION_ALIAS("XTORS_FLASH", flash3); +REGION_ALIAS("XTORS_FLASH_LMA", flash3); /* Flash region to be used for code text.*/ -REGION_ALIAS("TEXT_FLASH", flash0); -REGION_ALIAS("TEXT_FLASH_LMA", flash0); +REGION_ALIAS("TEXT_FLASH", flash3); +REGION_ALIAS("TEXT_FLASH_LMA", flash3); /* Flash region to be used for read only data.*/ -REGION_ALIAS("RODATA_FLASH", flash0); -REGION_ALIAS("RODATA_FLASH_LMA", flash0); +REGION_ALIAS("RODATA_FLASH", flash3); +REGION_ALIAS("RODATA_FLASH_LMA", flash3); /* Flash region to be used for various.*/ -REGION_ALIAS("VARIOUS_FLASH", flash0); -REGION_ALIAS("VARIOUS_FLASH_LMA", flash0); +REGION_ALIAS("VARIOUS_FLASH", flash3); +REGION_ALIAS("VARIOUS_FLASH_LMA", flash3); /* Flash region to be used for RAM(n) initialization data.*/ -REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0); +REGION_ALIAS("RAM_INIT_FLASH_LMA", flash3); /* RAM region to be used for Main stack. This stack accommodates the processing of all exceptions and interrupts.*/ @@ -75,7 +75,7 @@ REGION_ALIAS("PROCESS_STACK_RAM", ram0); /* RAM region to be used for data segment.*/ REGION_ALIAS("DATA_RAM", ram0); -REGION_ALIAS("DATA_RAM_LMA", flash0); +REGION_ALIAS("DATA_RAM_LMA", flash3); /* RAM region to be used for BSS segment.*/ REGION_ALIAS("BSS_RAM", ram0); diff --git a/platforms/chibios/flash_stm32.c b/platforms/chibios/flash_stm32.c index 72c41b8b784d..44677b0d627e 100644 --- a/platforms/chibios/flash_stm32.c +++ b/platforms/chibios/flash_stm32.c @@ -44,6 +44,14 @@ static uint8_t ADDR2PAGE(uint32_t Page_Address) { return 2; case 0x0800C000 ... 0x0800FFFF: return 3; + case 0x08010000 ... 0x08013FFF: + return 4; + case 0x08014000 ... 0x08017FFF: + return 5; + case 0x08018000 ... 0x0801BFFF: + return 6; + case 0x0801C000 ... 0x0801FFFF: + return 7; } // TODO: bad times... @@ -163,7 +171,7 @@ FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data) { if (IS_FLASH_ADDRESS(Address)) { /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation(ProgramTimeout); - if (status == FLASH_COMPLETE) { + if (status != FLASH_BUSY) { /* if the previous operation is completed, proceed to program the new data */ #if defined(FLASH_CR_PSIZE) diff --git a/platforms/chibios/pin_defs.h b/platforms/chibios/pin_defs.h index 357347052169..398d3d0fd267 100644 --- a/platforms/chibios/pin_defs.h +++ b/platforms/chibios/pin_defs.h @@ -109,6 +109,7 @@ # define SERIAL_USART_DRIVER SD1 # define I2C1_SCL_PIN D0 # define I2C1_SDA_PIN D1 +# define FEE_PAGE_BASE_ADDRESS 0x08014000 #else # define A0 PAL_LINE(GPIOA, 0) From c9e3441733f830051abf1c20e1d1d136bfe99c81 Mon Sep 17 00:00:00 2001 From: Mariappan Ramasamy <947300+Mariappan@users.noreply.github.com> Date: Tue, 8 Feb 2022 14:17:15 +0800 Subject: [PATCH 05/20] Simplify ADDR2PAGE fn --- platforms/chibios/flash_stm32.c | 24 ++---------------------- 1 file changed, 2 insertions(+), 22 deletions(-) diff --git a/platforms/chibios/flash_stm32.c b/platforms/chibios/flash_stm32.c index 44677b0d627e..dbfff0b25828 100644 --- a/platforms/chibios/flash_stm32.c +++ b/platforms/chibios/flash_stm32.c @@ -34,28 +34,8 @@ # define FLASH_KEY1 0x45670123U # define FLASH_KEY2 0xCDEF89ABU -static uint8_t ADDR2PAGE(uint32_t Page_Address) { - switch (Page_Address) { - case 0x08000000 ... 0x08003FFF: - return 0; - case 0x08004000 ... 0x08007FFF: - return 1; - case 0x08008000 ... 0x0800BFFF: - return 2; - case 0x0800C000 ... 0x0800FFFF: - return 3; - case 0x08010000 ... 0x08013FFF: - return 4; - case 0x08014000 ... 0x08017FFF: - return 5; - case 0x08018000 ... 0x0801BFFF: - return 6; - case 0x0801C000 ... 0x0801FFFF: - return 7; - } - - // TODO: bad times... - return 7; +static inline uint8_t ADDR2PAGE(uint32_t Page_Address) { + return (Page_Address - 0x08000000)/0x4000; } #endif From 11f4b34f2b8330c36eb6c9c08969a1c2fad44c02 Mon Sep 17 00:00:00 2001 From: Mariappan Ramasamy Date: Tue, 8 Feb 2022 17:18:43 +0800 Subject: [PATCH 06/20] Fix flash addresses --- .../boards/STEMCELL/ld/STEMCELL_tinyuf2.ld | 32 +++++++++---------- platforms/chibios/flash_stm32.c | 16 ++++++++-- platforms/chibios/pin_defs.h | 2 +- 3 files changed, 31 insertions(+), 19 deletions(-) diff --git a/platforms/chibios/boards/STEMCELL/ld/STEMCELL_tinyuf2.ld b/platforms/chibios/boards/STEMCELL/ld/STEMCELL_tinyuf2.ld index 3abd470edefe..d00249aa3ccf 100644 --- a/platforms/chibios/boards/STEMCELL/ld/STEMCELL_tinyuf2.ld +++ b/platforms/chibios/boards/STEMCELL/ld/STEMCELL_tinyuf2.ld @@ -21,10 +21,10 @@ MEMORY { - flash0 (rx) : org = 0x08000000, len = 64k /* Sector 0 - TinyUF2 bootloader */ - flash1 (rx) : org = 0x08010000, len = 16k /* Sector 1 - Init Code */ - flash2 (rx) : org = 0x08014000, len = 16k /* Sector 2 - Emulated eeprom */ - flash3 (rx) : org = 0x08018000, len = 256k - 96k /* Sector 3 - Firmware code */ + flash0 (rx) : org = 0x08000000, len = 32k /* Sector 0 - TinyUF2 bootloader */ + flash1 (rx) : org = 0x08008000, len = 32k /* Sector 1 - Emulated eeprom */ + flash2 (rx) : org = 0x08010000, len = 256k - 64k /* Sector 2 - Firmware Code */ + flash3 (rx) : org = 0x00000000, len = 0 flash4 (rx) : org = 0x00000000, len = 0 flash5 (rx) : org = 0x00000000, len = 0 flash6 (rx) : org = 0x00000000, len = 0 @@ -43,27 +43,27 @@ MEMORY and a load region (_LMA suffix).*/ /* Flash region to be used for exception vectors.*/ -REGION_ALIAS("VECTORS_FLASH", flash1); -REGION_ALIAS("VECTORS_FLASH_LMA", flash1); +REGION_ALIAS("VECTORS_FLASH", flash2); +REGION_ALIAS("VECTORS_FLASH_LMA", flash2); /* Flash region to be used for constructors and destructors.*/ -REGION_ALIAS("XTORS_FLASH", flash3); -REGION_ALIAS("XTORS_FLASH_LMA", flash3); +REGION_ALIAS("XTORS_FLASH", flash2); +REGION_ALIAS("XTORS_FLASH_LMA", flash2); /* Flash region to be used for code text.*/ -REGION_ALIAS("TEXT_FLASH", flash3); -REGION_ALIAS("TEXT_FLASH_LMA", flash3); +REGION_ALIAS("TEXT_FLASH", flash2); +REGION_ALIAS("TEXT_FLASH_LMA", flash2); /* Flash region to be used for read only data.*/ -REGION_ALIAS("RODATA_FLASH", flash3); -REGION_ALIAS("RODATA_FLASH_LMA", flash3); +REGION_ALIAS("RODATA_FLASH", flash2); +REGION_ALIAS("RODATA_FLASH_LMA", flash2); /* Flash region to be used for various.*/ -REGION_ALIAS("VARIOUS_FLASH", flash3); -REGION_ALIAS("VARIOUS_FLASH_LMA", flash3); +REGION_ALIAS("VARIOUS_FLASH", flash2); +REGION_ALIAS("VARIOUS_FLASH_LMA", flash2); /* Flash region to be used for RAM(n) initialization data.*/ -REGION_ALIAS("RAM_INIT_FLASH_LMA", flash3); +REGION_ALIAS("RAM_INIT_FLASH_LMA", flash2); /* RAM region to be used for Main stack. This stack accommodates the processing of all exceptions and interrupts.*/ @@ -75,7 +75,7 @@ REGION_ALIAS("PROCESS_STACK_RAM", ram0); /* RAM region to be used for data segment.*/ REGION_ALIAS("DATA_RAM", ram0); -REGION_ALIAS("DATA_RAM_LMA", flash3); +REGION_ALIAS("DATA_RAM_LMA", flash2); /* RAM region to be used for BSS segment.*/ REGION_ALIAS("BSS_RAM", ram0); diff --git a/platforms/chibios/flash_stm32.c b/platforms/chibios/flash_stm32.c index dbfff0b25828..f69189c10867 100644 --- a/platforms/chibios/flash_stm32.c +++ b/platforms/chibios/flash_stm32.c @@ -35,7 +35,19 @@ # define FLASH_KEY2 0xCDEF89ABU static inline uint8_t ADDR2PAGE(uint32_t Page_Address) { - return (Page_Address - 0x08000000)/0x4000; + switch (Page_Address) { + case 0x08000000 ... 0x08003FFF: + return 0; + case 0x08004000 ... 0x08007FFF: + return 1; + case 0x08008000 ... 0x0800BFFF: + return 2; + case 0x0800C000 ... 0x0800FFFF: + return 3; + } + + // TODO: bad times... + return 7; } #endif @@ -151,7 +163,7 @@ FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data) { if (IS_FLASH_ADDRESS(Address)) { /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation(ProgramTimeout); - if (status != FLASH_BUSY) { + if (status == FLASH_COMPLETE) { /* if the previous operation is completed, proceed to program the new data */ #if defined(FLASH_CR_PSIZE) diff --git a/platforms/chibios/pin_defs.h b/platforms/chibios/pin_defs.h index 398d3d0fd267..9c43e06ad25e 100644 --- a/platforms/chibios/pin_defs.h +++ b/platforms/chibios/pin_defs.h @@ -109,7 +109,7 @@ # define SERIAL_USART_DRIVER SD1 # define I2C1_SCL_PIN D0 # define I2C1_SDA_PIN D1 -# define FEE_PAGE_BASE_ADDRESS 0x08014000 +# define FEE_PAGE_BASE_ADDRESS 0x08008000 #else # define A0 PAL_LINE(GPIOA, 0) From da80b988b87b64bfd0f723a3d1e0c9726b1cd3f9 Mon Sep 17 00:00:00 2001 From: Mariappan Ramasamy Date: Tue, 8 Feb 2022 17:19:03 +0800 Subject: [PATCH 07/20] add via keymap for adux --- keyboards/a_dux/keymaps/via/keymap.c | 40 ++++++++++++++++++++++++++++ keyboards/a_dux/keymaps/via/rules.mk | 4 +++ 2 files changed, 44 insertions(+) create mode 100644 keyboards/a_dux/keymaps/via/keymap.c create mode 100644 keyboards/a_dux/keymaps/via/rules.mk diff --git a/keyboards/a_dux/keymaps/via/keymap.c b/keyboards/a_dux/keymaps/via/keymap.c new file mode 100644 index 000000000000..b58c9d447f91 --- /dev/null +++ b/keyboards/a_dux/keymaps/via/keymap.c @@ -0,0 +1,40 @@ +// Copyright 2022 @filterpaper +// SPDX-License-Identifier: GPL-2.0+ + +#include QMK_KEYBOARD_H + +// Seniply layout +// https://stevep99.github.io/seniply + +const uint16_t PROGMEM keymaps[][MATRIX_ROWS][MATRIX_COLS] = { + [0] = LAYOUT_split_3x5_2( + KC_Q, KC_W, KC_E, KC_R, KC_T, KC_Y, KC_U, KC_I, KC_O, KC_P, + KC_A, KC_S, KC_D, KC_F, KC_G, KC_H, KC_J, KC_K, KC_L, KC_SCLN, + KC_Z, KC_X, KC_C, KC_V, KC_B, KC_N, KC_M, KC_COMM, KC_DOT, KC_SLSH, + LT(3,KC_TAB), KC_LSFT, KC_SPC, LT(1,KC_ENT) + ), + [1] = LAYOUT_split_3x5_2( + KC_EXLM, KC_AT, KC_SCLN, KC_COLN, KC_UNDS, KC_EQL, KC_7, KC_8, KC_9, KC_PLUS, + KC_BSLS, KC_PIPE, KC_LCBR, KC_LPRN, KC_LBRC, KC_ASTR, KC_4, KC_5, KC_6, KC_MINS, + KC_NO, KC_NO, KC_RCBR, KC_RPRN, KC_RBRC, KC_0, KC_1, KC_2, KC_3, KC_SLSH, + _______, MO(2), _______, _______ + ), + [2] = LAYOUT_split_3x5_2( + RALT(KC_1), RALT(KC_2), RALT(KC_3), RALT(KC_4), KC_BRIU, KC_NO, KC_AMPR, KC_GRV, KC_TILD, KC_NO, + KC_MUTE, KC_VOLD, KC_MPLY, KC_VOLU, KC_BRID, KC_NO, KC_DLR, KC_PERC, KC_CIRC, KC_UNDS, + KC_EJCT, KC_MPRV, KC_MSTP, KC_MNXT, KC_NO, KC_NO, KC_EXLM, KC_AT, KC_HASH, KC_NO, + _______, _______, _______, _______ + ), + [3] = LAYOUT_split_3x5_2( + KC_ESC, LALT(KC_LEFT), LCTL(KC_F), LALT(KC_RGHT), KC_INS, KC_PGUP, KC_HOME, KC_UP, KC_END, KC_CAPS, + OSM(MOD_LALT), OSM(MOD_LGUI), OSM(MOD_LSFT), OSM(MOD_LCTL), OSM(MOD_RALT), KC_PGDN, KC_LEFT, KC_DOWN, KC_RGHT, KC_DEL, + LCTL(KC_Z), LCTL(KC_X), LCTL(KC_C), KC_TAB, LCTL(KC_V), KC_ENT, KC_BSPC, KC_RCTL, KC_LALT, KC_APP, + _______, _______, _______, MO(4) + ), + [4] = LAYOUT_split_3x5_2( + KC_NO, KC_NO, RCS(KC_F), KC_PSCR, KC_NO, KC_F12, KC_F7, KC_F8, KC_F9, KC_NO, + OSM(MOD_LALT), OSM(MOD_LGUI), OSM(MOD_LSFT), OSM(MOD_LCTL), OSM(MOD_RALT), KC_F11, KC_F4, KC_F5, KC_F6, KC_NO, + RCS(KC_Z), RCS(KC_X), RCS(KC_C), LSFT(KC_TAB), RCS(KC_V), KC_F10, KC_F1, KC_F2, KC_F3, KC_NO, + _______, _______, _______, _______ + ) +}; diff --git a/keyboards/a_dux/keymaps/via/rules.mk b/keyboards/a_dux/keymaps/via/rules.mk new file mode 100644 index 000000000000..6c24ff1a0375 --- /dev/null +++ b/keyboards/a_dux/keymaps/via/rules.mk @@ -0,0 +1,4 @@ +VIA_ENABLE = yes +OLED_ENABLE = no +MOUSEKEY_ENABLE = yes +EXTRAKEY_ENABLE = yes From de0b208a93f1bd9513e7662d134ecf744b5f5100 Mon Sep 17 00:00:00 2001 From: Mariappan Ramasamy Date: Tue, 8 Feb 2022 22:26:06 +0800 Subject: [PATCH 08/20] Fix matrin setPin bug which prevents flash saving --- platforms/chibios/boards/STEMCELL/ld/STEMCELL_tinyuf2.ld | 6 +++--- platforms/chibios/flash_stm32.c | 2 +- quantum/matrix.c | 2 +- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/platforms/chibios/boards/STEMCELL/ld/STEMCELL_tinyuf2.ld b/platforms/chibios/boards/STEMCELL/ld/STEMCELL_tinyuf2.ld index d00249aa3ccf..9a40100666a2 100644 --- a/platforms/chibios/boards/STEMCELL/ld/STEMCELL_tinyuf2.ld +++ b/platforms/chibios/boards/STEMCELL/ld/STEMCELL_tinyuf2.ld @@ -21,9 +21,9 @@ MEMORY { - flash0 (rx) : org = 0x08000000, len = 32k /* Sector 0 - TinyUF2 bootloader */ - flash1 (rx) : org = 0x08008000, len = 32k /* Sector 1 - Emulated eeprom */ - flash2 (rx) : org = 0x08010000, len = 256k - 64k /* Sector 2 - Firmware Code */ + flash0 (rx) : org = 0x08000000, len = 32k /* Sector 0,1 - TinyUF2 bootloader */ + flash1 (rx) : org = 0x08008000, len = 32k /* Sector 2,3 - Emulated eeprom */ + flash2 (rx) : org = 0x08010000, len = 256k - 64k /* Sector 4..6 - Firmware Code */ flash3 (rx) : org = 0x00000000, len = 0 flash4 (rx) : org = 0x00000000, len = 0 flash5 (rx) : org = 0x00000000, len = 0 diff --git a/platforms/chibios/flash_stm32.c b/platforms/chibios/flash_stm32.c index f69189c10867..72c41b8b784d 100644 --- a/platforms/chibios/flash_stm32.c +++ b/platforms/chibios/flash_stm32.c @@ -34,7 +34,7 @@ # define FLASH_KEY1 0x45670123U # define FLASH_KEY2 0xCDEF89ABU -static inline uint8_t ADDR2PAGE(uint32_t Page_Address) { +static uint8_t ADDR2PAGE(uint32_t Page_Address) { switch (Page_Address) { case 0x08000000 ... 0x08003FFF: return 0; diff --git a/quantum/matrix.c b/quantum/matrix.c index db59b73754f5..8575a7f8de5f 100644 --- a/quantum/matrix.c +++ b/quantum/matrix.c @@ -107,7 +107,7 @@ __attribute__((weak)) void matrix_init_pins(void) { for (int row = 0; row < ROWS_PER_HAND; row++) { for (int col = 0; col < MATRIX_COLS; col++) { pin_t pin = direct_pins[row][col]; - if (pin != NO_PIN) { + if ((pin != NO_PIN) && (pin != 0)) { setPinInputHigh(pin); } } From 46db91cbadc9f93f73565cf521d057c6aa3e70a9 Mon Sep 17 00:00:00 2001 From: Mariappan Ramasamy Date: Thu, 10 Feb 2022 13:54:29 +0800 Subject: [PATCH 09/20] Fix serial default driver --- .../boards/STEMCELL/configs/bootloader_defs.h | 5 ----- platforms/chibios/pin_defs.h | 13 ++++--------- 2 files changed, 4 insertions(+), 14 deletions(-) delete mode 100644 platforms/chibios/boards/STEMCELL/configs/bootloader_defs.h diff --git a/platforms/chibios/boards/STEMCELL/configs/bootloader_defs.h b/platforms/chibios/boards/STEMCELL/configs/bootloader_defs.h deleted file mode 100644 index 4da3d39a3268..000000000000 --- a/platforms/chibios/boards/STEMCELL/configs/bootloader_defs.h +++ /dev/null @@ -1,5 +0,0 @@ -/* Address for jumping to bootloader on STM32 chips. */ -/* It is chip dependent, the correct number can be looked up here: - * http://www.st.com/web/en/resource/technical/document/application_note/CD00167594.pdf - */ -#define STM32_BOOTLOADER_ADDRESS 0x1FFF0000 diff --git a/platforms/chibios/pin_defs.h b/platforms/chibios/pin_defs.h index 9c43e06ad25e..1fb0dc638844 100644 --- a/platforms/chibios/pin_defs.h +++ b/platforms/chibios/pin_defs.h @@ -56,18 +56,14 @@ #elif defined(CONVERT_TO_STEMCELL) -/* #if SOFT_SERIAL_PIN==D0 || SOFT_SERIAL_PIN==D1 -# define SERIAL_USART_DRIVER SD1 -# define USART1_REMAP -#elif SOFT_SERIAL_PIN==D2 || SOFT_SERIAL_PIN==D3 -# define SERIAL_USART_DRIVER SD2 -# define USART2_REMAP -#endif */ - // Left side (front) # ifdef CONVERT_TO_STEMCELL_UART_SWAP # define D3 PAL_LINE(GPIOA, 3) # define D2 PAL_LINE(GPIOA, 2) +# ifndef SERIAL_USART_DRIVER +# define SERIAL_USART_DRIVER SD2 +# endif +// # define USART2_REMAP # else # define D3 PAL_LINE(GPIOA, 2) # define D2 PAL_LINE(GPIOA, 3) @@ -106,7 +102,6 @@ # define D5 PAL_LINE(GPIOA, 8) # define B0 PAL_LINE(GPIOA, 9) // unconnected pin -# define SERIAL_USART_DRIVER SD1 # define I2C1_SCL_PIN D0 # define I2C1_SDA_PIN D1 # define FEE_PAGE_BASE_ADDRESS 0x08008000 From 8dccdeea9efcc3afe590cca75c61351fa2e39a13 Mon Sep 17 00:00:00 2001 From: Mariappan Ramasamy <947300+Mariappan@users.noreply.github.com> Date: Sun, 20 Feb 2022 17:28:47 +0800 Subject: [PATCH 10/20] Fix board pinmapping and minor nitpiks --- .../chibios/boards/STEMCELL/board/board.h | 558 +++++++++--------- .../chibios/boards/STEMCELL/configs/halconf.h | 3 +- .../chibios/boards/STEMCELL/configs/mcuconf.h | 2 +- .../boards/STEMCELL/convert_to_stemcell.mk | 2 +- platforms/chibios/pin_defs.h | 1 - 5 files changed, 270 insertions(+), 296 deletions(-) diff --git a/platforms/chibios/boards/STEMCELL/board/board.h b/platforms/chibios/boards/STEMCELL/board/board.h index ed6621345be6..f4f73aa152f0 100644 --- a/platforms/chibios/boards/STEMCELL/board/board.h +++ b/platforms/chibios/boards/STEMCELL/board/board.h @@ -53,91 +53,90 @@ * Board voltages. * Required for performance limits calculation. */ -#define STM32_VDD 300U +#define STM32_VDD 330U /* * MCU type as defined in the ST header. */ -#define STM32F401xC +#define STM32F411xE /* * IO pins assignments. */ -#define GPIOA_BUTTON 0U +#define GPIOA_PIN0 0U #define GPIOA_PIN1 1U #define GPIOA_PIN2 2U #define GPIOA_PIN3 3U -#define GPIOA_CS43L22_LRCK 4U -#define GPIOA_L3GD20_SCL 5U -#define GPIOA_L3GD20_SD0 6U -#define GPIOA_L3GD20_SDI 7U -#define GPIOA_LED 8U +#define GPIOA_PIN4 4U +#define GPIOA_PIN5 5U +#define GPIOA_PIN6 6U +#define GPIOA_PIN7 7U +#define GPIOA_LED0 8U #define GPIOA_VBUS_FS 9U #define GPIOA_OTG_FS_ID 10U #define GPIOA_OTG_FS_DM 11U #define GPIOA_OTG_FS_DP 12U -#define GPIOA_SWDIO 13U -#define GPIOA_SWCLK 14U +#define GPIOA_PIN13 13U +#define GPIOA_PIN14 14U #define GPIOA_PIN15 15U #define GPIOB_PIN0 0U #define GPIOB_PIN1 1U #define GPIOB_PIN2 2U -#define GPIOB_SWO 3U +#define GPIOB_PIN3 3U #define GPIOB_PIN4 4U #define GPIOB_PIN5 5U -#define GPIOB_LSM303DLHC_SCL 6U +#define GPIOB_PIN6 6U #define GPIOB_PIN7 7U #define GPIOB_PIN8 8U -#define GPIOB_LSM303DLHC_SDA 9U -#define GPIOB_MP45DT02_CLK_IN 10U +#define GPIOB_PIN9 9U +#define GPIOB_PIN10 10U #define GPIOB_PIN11 11U #define GPIOB_PIN12 12U #define GPIOB_PIN13 13U #define GPIOB_PIN14 14U #define GPIOB_PIN15 15U -#define GPIOC_OTG_FS_POWER_ON 0U +#define GPIOC_PIN0 0U #define GPIOC_PIN1 1U #define GPIOC_PIN2 2U -#define GPIOC_CS43L22_AIN4x 3U -#define GPIOC_MP45DT02_PDM_OUT 3U +#define GPIOC_PIN3 3U #define GPIOC_PIN4 4U #define GPIOC_PIN5 5U #define GPIOC_PIN6 6U -#define GPIOC_CS43L22_MCLK 7U +#define GPIOC_PIN7 7U #define GPIOC_PIN8 8U #define GPIOC_PIN9 9U -#define GPIOC_CS43L22_SCLK 10U +#define GPIOC_PIN10 10U #define GPIOC_PIN11 11U -#define GPIOC_CS43L22_SDIN 12U +#define GPIOC_PIN12 12U #define GPIOC_PIN13 13U -#define GPIOC_OSC32_IN 14U -#define GPIOC_OSC32_OUT 15U +#define GPIOC_PIN14 14U +#define GPIOC_PIN15 15U #define GPIOD_PIN0 0U #define GPIOD_PIN1 1U #define GPIOD_PIN2 2U #define GPIOD_PIN3 3U -#define GPIOD_CS43L22_RESET 4U -#define GPIOD_OverCurrent 5U +#define GPIOD_PIN4 4U +#define GPIOD_PIN5 5U #define GPIOD_PIN6 6U #define GPIOD_PIN7 7U #define GPIOD_PIN8 8U #define GPIOD_PIN9 9U #define GPIOD_PIN10 10U #define GPIOD_PIN11 11U -#define GPIOD_LED4 12U -#define GPIOD_LED3 13U -#define GPIOD_LED5 14U -#define GPIOD_LED6 15U +#define GPIOD_PIN12 12U +#define GPIOD_PIN13 13U +#define GPIOD_PIN14 14U +#define GPIOD_PIN15 15U -#define GPIOE_L3GD20_INT1 0U -#define GPIOE_L3GD20_INT2 1U -#define GPIOE_LSM303DLHC_DRDY 2U -#define GPIOE_L3GD20_CS 3U -#define GPIOE_LSM303DLHC_INT1 4U -#define GPIOE_LSM303DLHC_INT2 5U +#define GPIOE_PIN0 0U +#define GPIOE_PIN1 1U +#define GPIOE_PIN2 2U +#define GPIOE_PIN3 3U +#define GPIOE_PIN4 4U +#define GPIOE_PIN5 5U #define GPIOE_PIN6 6U #define GPIOE_PIN7 7U #define GPIOE_PIN8 8U @@ -183,8 +182,8 @@ #define GPIOG_PIN14 14U #define GPIOG_PIN15 15U -#define GPIOH_OSC_IN 0U -#define GPIOH_OSC_OUT 1U +#define GPIOH_PIN0 0U +#define GPIOH_PIN1 1U #define GPIOH_PIN2 2U #define GPIOH_PIN3 3U #define GPIOH_PIN4 4U @@ -220,11 +219,6 @@ /* * IO lines assignments. */ -#define LINE_BUTTON PAL_LINE(GPIOA, 0U) -#define LINE_CS43L22_LRCK PAL_LINE(GPIOA, 4U) -#define LINE_L3GD20_SCL PAL_LINE(GPIOA, 5U) -#define LINE_L3GD20_SD0 PAL_LINE(GPIOA, 6U) -#define LINE_L3GD20_SDI PAL_LINE(GPIOA, 7U) #define LINE_VBUS_FS PAL_LINE(GPIOA, 9U) #define LINE_OTG_FS_ID PAL_LINE(GPIOA, 10U) #define LINE_OTG_FS_DM PAL_LINE(GPIOA, 11U) @@ -232,29 +226,9 @@ #define LINE_SWDIO PAL_LINE(GPIOA, 13U) #define LINE_SWCLK PAL_LINE(GPIOA, 14U) #define LINE_SWO PAL_LINE(GPIOB, 3U) -#define LINE_LSM303DLHC_SCL PAL_LINE(GPIOB, 6U) -#define LINE_LSM303DLHC_SDA PAL_LINE(GPIOB, 9U) -#define LINE_MP45DT02_CLK_IN PAL_LINE(GPIOB, 10U) #define LINE_OTG_FS_POWER_ON PAL_LINE(GPIOC, 0U) -#define LINE_CS43L22_AIN4x PAL_LINE(GPIOC, 3U) -#define LINE_MP45DT02_PDM_OUT PAL_LINE(GPIOC, 3U) -#define LINE_CS43L22_MCLK PAL_LINE(GPIOC, 7U) -#define LINE_CS43L22_SCLK PAL_LINE(GPIOC, 10U) -#define LINE_CS43L22_SDIN PAL_LINE(GPIOC, 12U) #define LINE_OSC32_IN PAL_LINE(GPIOC, 14U) #define LINE_OSC32_OUT PAL_LINE(GPIOC, 15U) -#define LINE_CS43L22_RESET PAL_LINE(GPIOD, 4U) -#define LINE_OverCurrent PAL_LINE(GPIOD, 5U) -#define LINE_LED4 PAL_LINE(GPIOD, 12U) -#define LINE_LED3 PAL_LINE(GPIOD, 13U) -#define LINE_LED5 PAL_LINE(GPIOD, 14U) -#define LINE_LED6 PAL_LINE(GPIOD, 15U) -#define LINE_L3GD20_INT1 PAL_LINE(GPIOE, 0U) -#define LINE_L3GD20_INT2 PAL_LINE(GPIOE, 1U) -#define LINE_LSM303DLHC_DRDY PAL_LINE(GPIOE, 2U) -#define LINE_L3GD20_CS PAL_LINE(GPIOE, 3U) -#define LINE_LSM303DLHC_INT1 PAL_LINE(GPIOE, 4U) -#define LINE_LSM303DLHC_INT2 PAL_LINE(GPIOE, 5U) #define LINE_OSC_IN PAL_LINE(GPIOH, 0U) #define LINE_OSC_OUT PAL_LINE(GPIOH, 1U) @@ -299,118 +273,118 @@ /* * GPIOA setup: * - * PA0 - BUTTON (input floating). + * PA0 - PIN0 (input pullup). * PA1 - PIN1 (input pullup). * PA2 - PIN2 (input pullup). * PA3 - PIN3 (input pullup). - * PA4 - CS43L22_LRCK (alternate 6). - * PA5 - L3GD20_SCL (alternate 5). - * PA6 - L3GD20_SD0 (alternate 5). - * PA7 - L3GD20_SDI (alternate 5). - * PA8 - LED (output pushpull maximum). + * PA4 - PIN4 (input pullup). + * PA5 - PIN5 (input pullup). + * PA6 - PIN6 (input pullup). + * PA7 - PIN7 (input pullup). + * PA8 - LED0 (output pushpull low). * PA9 - VBUS_FS (input floating). * PA10 - OTG_FS_ID (alternate 10). * PA11 - OTG_FS_DM (alternate 10). * PA12 - OTG_FS_DP (alternate 10). - * PA13 - SWDIO (alternate 0). - * PA14 - SWCLK (alternate 0). + * PA13 - PIN13 (input pullup). + * PA14 - PIN14 (input pullup). * PA15 - PIN15 (input pullup). */ -#define VAL_GPIOA_MODER (PIN_MODE_INPUT(GPIOA_BUTTON) | \ +#define VAL_GPIOA_MODER (PIN_MODE_INPUT(GPIOA_PIN0) | \ PIN_MODE_INPUT(GPIOA_PIN1) | \ PIN_MODE_INPUT(GPIOA_PIN2) | \ PIN_MODE_INPUT(GPIOA_PIN3) | \ - PIN_MODE_ALTERNATE(GPIOA_CS43L22_LRCK) |\ - PIN_MODE_ALTERNATE(GPIOA_L3GD20_SCL) | \ - PIN_MODE_ALTERNATE(GPIOA_L3GD20_SD0) | \ - PIN_MODE_ALTERNATE(GPIOA_L3GD20_SDI) | \ - PIN_MODE_OUTPUT(GPIOA_LED)| \ + PIN_MODE_INPUT(GPIOA_PIN4) | \ + PIN_MODE_INPUT(GPIOA_PIN5) | \ + PIN_MODE_INPUT(GPIOA_PIN6) | \ + PIN_MODE_INPUT(GPIOA_PIN7) | \ + PIN_MODE_OUTPUT(GPIOA_LED0) | \ PIN_MODE_INPUT(GPIOA_VBUS_FS) | \ PIN_MODE_ALTERNATE(GPIOA_OTG_FS_ID) | \ PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DM) | \ PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DP) | \ - PIN_MODE_ALTERNATE(GPIOA_SWDIO) | \ - PIN_MODE_ALTERNATE(GPIOA_SWCLK) | \ + PIN_MODE_INPUT(GPIOA_PIN13) | \ + PIN_MODE_INPUT(GPIOA_PIN14) | \ PIN_MODE_INPUT(GPIOA_PIN15)) -#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_BUTTON) | \ +#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_PIN0) | \ PIN_OTYPE_PUSHPULL(GPIOA_PIN1) | \ PIN_OTYPE_PUSHPULL(GPIOA_PIN2) | \ PIN_OTYPE_PUSHPULL(GPIOA_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOA_CS43L22_LRCK) |\ - PIN_OTYPE_PUSHPULL(GPIOA_L3GD20_SCL) | \ - PIN_OTYPE_PUSHPULL(GPIOA_L3GD20_SD0) | \ - PIN_OTYPE_PUSHPULL(GPIOA_L3GD20_SDI) | \ - PIN_OTYPE_PUSHPULL(GPIOA_LED) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOA_LED0) | \ PIN_OTYPE_PUSHPULL(GPIOA_VBUS_FS) | \ PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_ID) | \ PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_DM) | \ PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_DP) | \ - PIN_OTYPE_PUSHPULL(GPIOA_SWDIO) | \ - PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN14) | \ PIN_OTYPE_PUSHPULL(GPIOA_PIN15)) -#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_HIGH(GPIOA_BUTTON) | \ +#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_HIGH(GPIOA_PIN0) | \ PIN_OSPEED_HIGH(GPIOA_PIN1) | \ PIN_OSPEED_HIGH(GPIOA_PIN2) | \ PIN_OSPEED_HIGH(GPIOA_PIN3) | \ - PIN_OSPEED_HIGH(GPIOA_CS43L22_LRCK) | \ - PIN_OSPEED_HIGH(GPIOA_L3GD20_SCL) | \ - PIN_OSPEED_HIGH(GPIOA_L3GD20_SD0) | \ - PIN_OSPEED_HIGH(GPIOA_L3GD20_SDI) | \ - PIN_OSPEED_HIGH(GPIOA_LED) | \ + PIN_OSPEED_HIGH(GPIOA_PIN4) | \ + PIN_OSPEED_HIGH(GPIOA_PIN5) | \ + PIN_OSPEED_HIGH(GPIOA_PIN6) | \ + PIN_OSPEED_HIGH(GPIOA_PIN7) | \ + PIN_OSPEED_HIGH(GPIOA_LED0) | \ PIN_OSPEED_HIGH(GPIOA_VBUS_FS) | \ PIN_OSPEED_HIGH(GPIOA_OTG_FS_ID) | \ PIN_OSPEED_HIGH(GPIOA_OTG_FS_DM) | \ PIN_OSPEED_HIGH(GPIOA_OTG_FS_DP) | \ - PIN_OSPEED_HIGH(GPIOA_SWDIO) | \ - PIN_OSPEED_HIGH(GPIOA_SWCLK) | \ + PIN_OSPEED_HIGH(GPIOA_PIN13) | \ + PIN_OSPEED_HIGH(GPIOA_PIN14) | \ PIN_OSPEED_HIGH(GPIOA_PIN15)) -#define VAL_GPIOA_PUPDR (PIN_PUPDR_FLOATING(GPIOA_BUTTON) | \ +#define VAL_GPIOA_PUPDR (PIN_PUPDR_PULLUP(GPIOA_PIN0) | \ PIN_PUPDR_PULLUP(GPIOA_PIN1) | \ PIN_PUPDR_PULLUP(GPIOA_PIN2) | \ PIN_PUPDR_PULLUP(GPIOA_PIN3) | \ - PIN_PUPDR_FLOATING(GPIOA_CS43L22_LRCK) |\ - PIN_PUPDR_FLOATING(GPIOA_L3GD20_SCL) | \ - PIN_PUPDR_PULLUP(GPIOA_L3GD20_SD0) | \ - PIN_PUPDR_PULLUP(GPIOA_L3GD20_SDI) | \ - PIN_PUPDR_FLOATING(GPIOA_LED) | \ + PIN_PUPDR_PULLUP(GPIOA_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOA_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOA_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOA_PIN7) | \ + PIN_PUPDR_FLOATING(GPIOA_LED0) | \ PIN_PUPDR_FLOATING(GPIOA_VBUS_FS) | \ PIN_PUPDR_FLOATING(GPIOA_OTG_FS_ID) | \ PIN_PUPDR_FLOATING(GPIOA_OTG_FS_DM) | \ PIN_PUPDR_FLOATING(GPIOA_OTG_FS_DP) | \ - PIN_PUPDR_FLOATING(GPIOA_SWDIO) | \ - PIN_PUPDR_FLOATING(GPIOA_SWCLK) | \ + PIN_PUPDR_PULLUP(GPIOA_PIN13) | \ + PIN_PUPDR_PULLUP(GPIOA_PIN14) | \ PIN_PUPDR_PULLUP(GPIOA_PIN15)) -#define VAL_GPIOA_ODR (PIN_ODR_HIGH(GPIOA_BUTTON) | \ +#define VAL_GPIOA_ODR (PIN_ODR_HIGH(GPIOA_PIN0) | \ PIN_ODR_HIGH(GPIOA_PIN1) | \ PIN_ODR_HIGH(GPIOA_PIN2) | \ PIN_ODR_HIGH(GPIOA_PIN3) | \ - PIN_ODR_HIGH(GPIOA_CS43L22_LRCK) | \ - PIN_ODR_HIGH(GPIOA_L3GD20_SCL) | \ - PIN_ODR_HIGH(GPIOA_L3GD20_SD0) | \ - PIN_ODR_HIGH(GPIOA_L3GD20_SDI) | \ - PIN_ODR_LOW(GPIOA_LED) | \ + PIN_ODR_HIGH(GPIOA_PIN4) | \ + PIN_ODR_HIGH(GPIOA_PIN5) | \ + PIN_ODR_HIGH(GPIOA_PIN6) | \ + PIN_ODR_HIGH(GPIOA_PIN7) | \ + PIN_ODR_LOW(GPIOA_LED0) | \ PIN_ODR_HIGH(GPIOA_VBUS_FS) | \ PIN_ODR_HIGH(GPIOA_OTG_FS_ID) | \ PIN_ODR_HIGH(GPIOA_OTG_FS_DM) | \ PIN_ODR_HIGH(GPIOA_OTG_FS_DP) | \ - PIN_ODR_HIGH(GPIOA_SWDIO) | \ - PIN_ODR_HIGH(GPIOA_SWCLK) | \ + PIN_ODR_HIGH(GPIOA_PIN13) | \ + PIN_ODR_HIGH(GPIOA_PIN14) | \ PIN_ODR_HIGH(GPIOA_PIN15)) -#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_BUTTON, 0U) | \ +#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_PIN0, 0U) | \ PIN_AFIO_AF(GPIOA_PIN1, 0U) | \ PIN_AFIO_AF(GPIOA_PIN2, 0U) | \ PIN_AFIO_AF(GPIOA_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOA_CS43L22_LRCK, 6U) | \ - PIN_AFIO_AF(GPIOA_L3GD20_SCL, 5U) | \ - PIN_AFIO_AF(GPIOA_L3GD20_SD0, 5U) | \ - PIN_AFIO_AF(GPIOA_L3GD20_SDI, 5U)) -#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_LED, 0U) | \ + PIN_AFIO_AF(GPIOA_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOA_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOA_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOA_PIN7, 0U)) +#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_LED0, 0U) | \ PIN_AFIO_AF(GPIOA_VBUS_FS, 0U) | \ PIN_AFIO_AF(GPIOA_OTG_FS_ID, 10U) | \ PIN_AFIO_AF(GPIOA_OTG_FS_DM, 10U) | \ PIN_AFIO_AF(GPIOA_OTG_FS_DP, 10U) | \ - PIN_AFIO_AF(GPIOA_SWDIO, 0U) | \ - PIN_AFIO_AF(GPIOA_SWCLK, 0U) | \ + PIN_AFIO_AF(GPIOA_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOA_PIN14, 0U) | \ PIN_AFIO_AF(GPIOA_PIN15, 0U)) /* @@ -419,14 +393,14 @@ * PB0 - PIN0 (input pullup). * PB1 - PIN1 (input pullup). * PB2 - PIN2 (input pullup). - * PB3 - SWO (alternate 0). + * PB3 - PIN3 (input pullup). * PB4 - PIN4 (input pullup). * PB5 - PIN5 (input pullup). - * PB6 - LSM303DLHC_SCL (alternate 4). + * PB6 - PIN6 (input pullup). * PB7 - PIN7 (input pullup). * PB8 - PIN8 (input pullup). - * PB9 - LSM303DLHC_SDA (alternate 4). - * PB10 - MP45DT02_CLK_IN (alternate 5). + * PB9 - PIN9 (input pullup). + * PB10 - PIN10 (input pullup). * PB11 - PIN11 (input pullup). * PB12 - PIN12 (input pullup). * PB13 - PIN13 (input pullup). @@ -436,14 +410,14 @@ #define VAL_GPIOB_MODER (PIN_MODE_INPUT(GPIOB_PIN0) | \ PIN_MODE_INPUT(GPIOB_PIN1) | \ PIN_MODE_INPUT(GPIOB_PIN2) | \ - PIN_MODE_ALTERNATE(GPIOB_SWO) | \ + PIN_MODE_INPUT(GPIOB_PIN3) | \ PIN_MODE_INPUT(GPIOB_PIN4) | \ PIN_MODE_INPUT(GPIOB_PIN5) | \ - PIN_MODE_ALTERNATE(GPIOB_LSM303DLHC_SCL) |\ + PIN_MODE_INPUT(GPIOB_PIN6) | \ PIN_MODE_INPUT(GPIOB_PIN7) | \ PIN_MODE_INPUT(GPIOB_PIN8) | \ - PIN_MODE_ALTERNATE(GPIOB_LSM303DLHC_SDA) |\ - PIN_MODE_ALTERNATE(GPIOB_MP45DT02_CLK_IN) |\ + PIN_MODE_INPUT(GPIOB_PIN9) | \ + PIN_MODE_INPUT(GPIOB_PIN10) | \ PIN_MODE_INPUT(GPIOB_PIN11) | \ PIN_MODE_INPUT(GPIOB_PIN12) | \ PIN_MODE_INPUT(GPIOB_PIN13) | \ @@ -452,14 +426,14 @@ #define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_PIN0) | \ PIN_OTYPE_PUSHPULL(GPIOB_PIN1) | \ PIN_OTYPE_PUSHPULL(GPIOB_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOB_SWO) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN3) | \ PIN_OTYPE_PUSHPULL(GPIOB_PIN4) | \ PIN_OTYPE_PUSHPULL(GPIOB_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOB_LSM303DLHC_SCL) |\ + PIN_OTYPE_PUSHPULL(GPIOB_PIN6) | \ PIN_OTYPE_PUSHPULL(GPIOB_PIN7) | \ PIN_OTYPE_PUSHPULL(GPIOB_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOB_LSM303DLHC_SDA) |\ - PIN_OTYPE_PUSHPULL(GPIOB_MP45DT02_CLK_IN) |\ + PIN_OTYPE_PUSHPULL(GPIOB_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN10) | \ PIN_OTYPE_PUSHPULL(GPIOB_PIN11) | \ PIN_OTYPE_PUSHPULL(GPIOB_PIN12) | \ PIN_OTYPE_PUSHPULL(GPIOB_PIN13) | \ @@ -468,14 +442,14 @@ #define VAL_GPIOB_OSPEEDR (PIN_OSPEED_HIGH(GPIOB_PIN0) | \ PIN_OSPEED_HIGH(GPIOB_PIN1) | \ PIN_OSPEED_HIGH(GPIOB_PIN2) | \ - PIN_OSPEED_HIGH(GPIOB_SWO) | \ + PIN_OSPEED_HIGH(GPIOB_PIN3) | \ PIN_OSPEED_HIGH(GPIOB_PIN4) | \ PIN_OSPEED_HIGH(GPIOB_PIN5) | \ - PIN_OSPEED_HIGH(GPIOB_LSM303DLHC_SCL) |\ + PIN_OSPEED_HIGH(GPIOB_PIN6) | \ PIN_OSPEED_HIGH(GPIOB_PIN7) | \ PIN_OSPEED_HIGH(GPIOB_PIN8) | \ - PIN_OSPEED_HIGH(GPIOB_LSM303DLHC_SDA) |\ - PIN_OSPEED_HIGH(GPIOB_MP45DT02_CLK_IN) |\ + PIN_OSPEED_HIGH(GPIOB_PIN9) | \ + PIN_OSPEED_HIGH(GPIOB_PIN10) | \ PIN_OSPEED_HIGH(GPIOB_PIN11) | \ PIN_OSPEED_HIGH(GPIOB_PIN12) | \ PIN_OSPEED_HIGH(GPIOB_PIN13) | \ @@ -484,14 +458,14 @@ #define VAL_GPIOB_PUPDR (PIN_PUPDR_PULLUP(GPIOB_PIN0) | \ PIN_PUPDR_PULLUP(GPIOB_PIN1) | \ PIN_PUPDR_PULLUP(GPIOB_PIN2) | \ - PIN_PUPDR_PULLUP(GPIOB_SWO) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN3) | \ PIN_PUPDR_PULLUP(GPIOB_PIN4) | \ PIN_PUPDR_PULLUP(GPIOB_PIN5) | \ - PIN_PUPDR_FLOATING(GPIOB_LSM303DLHC_SCL) |\ + PIN_PUPDR_PULLUP(GPIOB_PIN6) | \ PIN_PUPDR_PULLUP(GPIOB_PIN7) | \ PIN_PUPDR_PULLUP(GPIOB_PIN8) | \ - PIN_PUPDR_FLOATING(GPIOB_LSM303DLHC_SDA) |\ - PIN_PUPDR_FLOATING(GPIOB_MP45DT02_CLK_IN) |\ + PIN_PUPDR_PULLUP(GPIOB_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN10) | \ PIN_PUPDR_PULLUP(GPIOB_PIN11) | \ PIN_PUPDR_PULLUP(GPIOB_PIN12) | \ PIN_PUPDR_PULLUP(GPIOB_PIN13) | \ @@ -500,14 +474,14 @@ #define VAL_GPIOB_ODR (PIN_ODR_HIGH(GPIOB_PIN0) | \ PIN_ODR_HIGH(GPIOB_PIN1) | \ PIN_ODR_HIGH(GPIOB_PIN2) | \ - PIN_ODR_HIGH(GPIOB_SWO) | \ + PIN_ODR_HIGH(GPIOB_PIN3) | \ PIN_ODR_HIGH(GPIOB_PIN4) | \ PIN_ODR_HIGH(GPIOB_PIN5) | \ - PIN_ODR_HIGH(GPIOB_LSM303DLHC_SCL) | \ + PIN_ODR_HIGH(GPIOB_PIN6) | \ PIN_ODR_HIGH(GPIOB_PIN7) | \ PIN_ODR_HIGH(GPIOB_PIN8) | \ - PIN_ODR_HIGH(GPIOB_LSM303DLHC_SDA) | \ - PIN_ODR_HIGH(GPIOB_MP45DT02_CLK_IN) | \ + PIN_ODR_HIGH(GPIOB_PIN9) | \ + PIN_ODR_HIGH(GPIOB_PIN10) | \ PIN_ODR_HIGH(GPIOB_PIN11) | \ PIN_ODR_HIGH(GPIOB_PIN12) | \ PIN_ODR_HIGH(GPIOB_PIN13) | \ @@ -516,14 +490,14 @@ #define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_PIN0, 0U) | \ PIN_AFIO_AF(GPIOB_PIN1, 0U) | \ PIN_AFIO_AF(GPIOB_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOB_SWO, 0U) | \ + PIN_AFIO_AF(GPIOB_PIN3, 0U) | \ PIN_AFIO_AF(GPIOB_PIN4, 0U) | \ PIN_AFIO_AF(GPIOB_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOB_LSM303DLHC_SCL, 4U) |\ + PIN_AFIO_AF(GPIOB_PIN6, 0U) | \ PIN_AFIO_AF(GPIOB_PIN7, 0U)) #define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOB_LSM303DLHC_SDA, 4U) |\ - PIN_AFIO_AF(GPIOB_MP45DT02_CLK_IN, 5U) |\ + PIN_AFIO_AF(GPIOB_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOB_PIN10, 0U) | \ PIN_AFIO_AF(GPIOB_PIN11, 0U) | \ PIN_AFIO_AF(GPIOB_PIN12, 0U) | \ PIN_AFIO_AF(GPIOB_PIN13, 0U) | \ @@ -533,119 +507,119 @@ /* * GPIOC setup: * - * PC0 - OTG_FS_POWER_ON (output pushpull maximum). + * PC0 - PIN0 (input pullup). * PC1 - PIN1 (input pullup). * PC2 - PIN2 (input pullup). - * PC3 - CS43L22_AIN4x MP45DT02_PDM_OUT(alternate 5). + * PC3 - PIN3 (input pullup). * PC4 - PIN4 (input pullup). * PC5 - PIN5 (input pullup). * PC6 - PIN6 (input pullup). - * PC7 - CS43L22_MCLK (alternate 6). + * PC7 - PIN7 (input pullup). * PC8 - PIN8 (input pullup). * PC9 - PIN9 (input pullup). - * PC10 - CS43L22_SCLK (alternate 6). + * PC10 - PIN10 (input pullup). * PC11 - PIN11 (input pullup). - * PC12 - CS43L22_SDIN (alternate 6). + * PC12 - PIN12 (input pullup). * PC13 - PIN13 (input pullup). - * PC14 - OSC32_IN (input floating). - * PC15 - OSC32_OUT (input floating). + * PC14 - PIN14 (input pullup). + * PC15 - PIN15 (input pullup). */ -#define VAL_GPIOC_MODER (PIN_MODE_OUTPUT(GPIOC_OTG_FS_POWER_ON) |\ +#define VAL_GPIOC_MODER (PIN_MODE_INPUT(GPIOC_PIN0) | \ PIN_MODE_INPUT(GPIOC_PIN1) | \ PIN_MODE_INPUT(GPIOC_PIN2) | \ - PIN_MODE_ALTERNATE(GPIOC_CS43L22_AIN4x) |\ + PIN_MODE_INPUT(GPIOC_PIN3) | \ PIN_MODE_INPUT(GPIOC_PIN4) | \ PIN_MODE_INPUT(GPIOC_PIN5) | \ PIN_MODE_INPUT(GPIOC_PIN6) | \ - PIN_MODE_ALTERNATE(GPIOC_CS43L22_MCLK) |\ + PIN_MODE_INPUT(GPIOC_PIN7) | \ PIN_MODE_INPUT(GPIOC_PIN8) | \ PIN_MODE_INPUT(GPIOC_PIN9) | \ - PIN_MODE_ALTERNATE(GPIOC_CS43L22_SCLK) |\ + PIN_MODE_INPUT(GPIOC_PIN10) | \ PIN_MODE_INPUT(GPIOC_PIN11) | \ - PIN_MODE_ALTERNATE(GPIOC_CS43L22_SDIN) |\ + PIN_MODE_INPUT(GPIOC_PIN12) | \ PIN_MODE_INPUT(GPIOC_PIN13) | \ - PIN_MODE_INPUT(GPIOC_OSC32_IN) | \ - PIN_MODE_INPUT(GPIOC_OSC32_OUT)) -#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_OTG_FS_POWER_ON) |\ + PIN_MODE_INPUT(GPIOC_PIN14) | \ + PIN_MODE_INPUT(GPIOC_PIN15)) +#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_PIN0) | \ PIN_OTYPE_PUSHPULL(GPIOC_PIN1) | \ PIN_OTYPE_PUSHPULL(GPIOC_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOC_CS43L22_AIN4x) |\ + PIN_OTYPE_PUSHPULL(GPIOC_PIN3) | \ PIN_OTYPE_PUSHPULL(GPIOC_PIN4) | \ PIN_OTYPE_PUSHPULL(GPIOC_PIN5) | \ PIN_OTYPE_PUSHPULL(GPIOC_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOC_CS43L22_MCLK) |\ + PIN_OTYPE_PUSHPULL(GPIOC_PIN7) | \ PIN_OTYPE_PUSHPULL(GPIOC_PIN8) | \ PIN_OTYPE_PUSHPULL(GPIOC_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOC_CS43L22_SCLK) |\ + PIN_OTYPE_PUSHPULL(GPIOC_PIN10) | \ PIN_OTYPE_PUSHPULL(GPIOC_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOC_CS43L22_SDIN) |\ + PIN_OTYPE_PUSHPULL(GPIOC_PIN12) | \ PIN_OTYPE_PUSHPULL(GPIOC_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOC_OSC32_IN) | \ - PIN_OTYPE_PUSHPULL(GPIOC_OSC32_OUT)) -#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_HIGH(GPIOC_OTG_FS_POWER_ON) |\ + PIN_OTYPE_PUSHPULL(GPIOC_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN15)) +#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_HIGH(GPIOC_PIN0) | \ PIN_OSPEED_HIGH(GPIOC_PIN1) | \ PIN_OSPEED_HIGH(GPIOC_PIN2) | \ - PIN_OSPEED_HIGH(GPIOC_CS43L22_AIN4x) | \ + PIN_OSPEED_HIGH(GPIOC_PIN3) | \ PIN_OSPEED_HIGH(GPIOC_PIN4) | \ PIN_OSPEED_HIGH(GPIOC_PIN5) | \ PIN_OSPEED_HIGH(GPIOC_PIN6) | \ - PIN_OSPEED_HIGH(GPIOC_CS43L22_MCLK) | \ + PIN_OSPEED_HIGH(GPIOC_PIN7) | \ PIN_OSPEED_HIGH(GPIOC_PIN8) | \ PIN_OSPEED_HIGH(GPIOC_PIN9) | \ - PIN_OSPEED_HIGH(GPIOC_CS43L22_SCLK) | \ + PIN_OSPEED_HIGH(GPIOC_PIN10) | \ PIN_OSPEED_HIGH(GPIOC_PIN11) | \ - PIN_OSPEED_HIGH(GPIOC_CS43L22_SDIN) | \ + PIN_OSPEED_HIGH(GPIOC_PIN12) | \ PIN_OSPEED_HIGH(GPIOC_PIN13) | \ - PIN_OSPEED_HIGH(GPIOC_OSC32_IN) | \ - PIN_OSPEED_HIGH(GPIOC_OSC32_OUT)) -#define VAL_GPIOC_PUPDR (PIN_PUPDR_PULLUP(GPIOC_OTG_FS_POWER_ON) |\ + PIN_OSPEED_HIGH(GPIOC_PIN14) | \ + PIN_OSPEED_HIGH(GPIOC_PIN15)) +#define VAL_GPIOC_PUPDR (PIN_PUPDR_PULLUP(GPIOC_PIN0) | \ PIN_PUPDR_PULLUP(GPIOC_PIN1) | \ PIN_PUPDR_PULLUP(GPIOC_PIN2) | \ - PIN_PUPDR_FLOATING(GPIOC_CS43L22_AIN4x) |\ + PIN_PUPDR_PULLUP(GPIOC_PIN3) | \ PIN_PUPDR_PULLUP(GPIOC_PIN4) | \ PIN_PUPDR_PULLUP(GPIOC_PIN5) | \ PIN_PUPDR_PULLUP(GPIOC_PIN6) | \ - PIN_PUPDR_PULLUP(GPIOC_CS43L22_MCLK) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN7) | \ PIN_PUPDR_PULLUP(GPIOC_PIN8) | \ PIN_PUPDR_PULLUP(GPIOC_PIN9) | \ - PIN_PUPDR_PULLUP(GPIOC_CS43L22_SCLK) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN10) | \ PIN_PUPDR_PULLUP(GPIOC_PIN11) | \ - PIN_PUPDR_PULLUP(GPIOC_CS43L22_SDIN) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN12) | \ PIN_PUPDR_PULLUP(GPIOC_PIN13) | \ - PIN_PUPDR_FLOATING(GPIOC_OSC32_IN) | \ - PIN_PUPDR_FLOATING(GPIOC_OSC32_OUT)) -#define VAL_GPIOC_ODR (PIN_ODR_HIGH(GPIOC_OTG_FS_POWER_ON) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN14) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN15)) +#define VAL_GPIOC_ODR (PIN_ODR_HIGH(GPIOC_PIN0) | \ PIN_ODR_HIGH(GPIOC_PIN1) | \ PIN_ODR_HIGH(GPIOC_PIN2) | \ - PIN_ODR_HIGH(GPIOC_CS43L22_AIN4x) | \ + PIN_ODR_HIGH(GPIOC_PIN3) | \ PIN_ODR_HIGH(GPIOC_PIN4) | \ PIN_ODR_HIGH(GPIOC_PIN5) | \ PIN_ODR_HIGH(GPIOC_PIN6) | \ - PIN_ODR_HIGH(GPIOC_CS43L22_MCLK) | \ + PIN_ODR_HIGH(GPIOC_PIN7) | \ PIN_ODR_HIGH(GPIOC_PIN8) | \ PIN_ODR_HIGH(GPIOC_PIN9) | \ - PIN_ODR_HIGH(GPIOC_CS43L22_SCLK) | \ + PIN_ODR_HIGH(GPIOC_PIN10) | \ PIN_ODR_HIGH(GPIOC_PIN11) | \ - PIN_ODR_HIGH(GPIOC_CS43L22_SDIN) | \ + PIN_ODR_HIGH(GPIOC_PIN12) | \ PIN_ODR_HIGH(GPIOC_PIN13) | \ - PIN_ODR_HIGH(GPIOC_OSC32_IN) | \ - PIN_ODR_HIGH(GPIOC_OSC32_OUT)) -#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_OTG_FS_POWER_ON, 0U) |\ + PIN_ODR_HIGH(GPIOC_PIN14) | \ + PIN_ODR_HIGH(GPIOC_PIN15)) +#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_PIN0, 0U) | \ PIN_AFIO_AF(GPIOC_PIN1, 0U) | \ PIN_AFIO_AF(GPIOC_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOC_CS43L22_AIN4x, 5U) | \ + PIN_AFIO_AF(GPIOC_PIN3, 0U) | \ PIN_AFIO_AF(GPIOC_PIN4, 0U) | \ PIN_AFIO_AF(GPIOC_PIN5, 0U) | \ PIN_AFIO_AF(GPIOC_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOC_CS43L22_MCLK, 6U)) + PIN_AFIO_AF(GPIOC_PIN7, 0U)) #define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_PIN8, 0U) | \ PIN_AFIO_AF(GPIOC_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOC_CS43L22_SCLK, 6U) | \ + PIN_AFIO_AF(GPIOC_PIN10, 0U) | \ PIN_AFIO_AF(GPIOC_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOC_CS43L22_SDIN, 6U) | \ + PIN_AFIO_AF(GPIOC_PIN12, 0U) | \ PIN_AFIO_AF(GPIOC_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOC_OSC32_IN, 0U) | \ - PIN_AFIO_AF(GPIOC_OSC32_OUT, 0U)) + PIN_AFIO_AF(GPIOC_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN15, 0U)) /* * GPIOD setup: @@ -654,125 +628,125 @@ * PD1 - PIN1 (input pullup). * PD2 - PIN2 (input pullup). * PD3 - PIN3 (input pullup). - * PD4 - CS43L22_RESET (output pushpull maximum). - * PD5 - OverCurrent (input floating). + * PD4 - PIN4 (input pullup). + * PD5 - PIN5 (input pullup). * PD6 - PIN6 (input pullup). * PD7 - PIN7 (input pullup). * PD8 - PIN8 (input pullup). * PD9 - PIN9 (input pullup). * PD10 - PIN10 (input pullup). * PD11 - PIN11 (input pullup). - * PD12 - LED4 (output pushpull maximum). - * PD13 - LED3 (output pushpull maximum). - * PD14 - LED5 (output pushpull maximum). - * PD15 - LED6 (output pushpull maximum). + * PD12 - PIN12 (input pullup). + * PD13 - PIN13 (input pullup). + * PD14 - PIN14 (input pullup). + * PD15 - PIN15 (input pullup). */ #define VAL_GPIOD_MODER (PIN_MODE_INPUT(GPIOD_PIN0) | \ PIN_MODE_INPUT(GPIOD_PIN1) | \ PIN_MODE_INPUT(GPIOD_PIN2) | \ PIN_MODE_INPUT(GPIOD_PIN3) | \ - PIN_MODE_OUTPUT(GPIOD_CS43L22_RESET) | \ - PIN_MODE_INPUT(GPIOD_OverCurrent) | \ + PIN_MODE_INPUT(GPIOD_PIN4) | \ + PIN_MODE_INPUT(GPIOD_PIN5) | \ PIN_MODE_INPUT(GPIOD_PIN6) | \ PIN_MODE_INPUT(GPIOD_PIN7) | \ PIN_MODE_INPUT(GPIOD_PIN8) | \ PIN_MODE_INPUT(GPIOD_PIN9) | \ PIN_MODE_INPUT(GPIOD_PIN10) | \ PIN_MODE_INPUT(GPIOD_PIN11) | \ - PIN_MODE_OUTPUT(GPIOD_LED4) | \ - PIN_MODE_OUTPUT(GPIOD_LED3) | \ - PIN_MODE_OUTPUT(GPIOD_LED5) | \ - PIN_MODE_OUTPUT(GPIOD_LED6)) + PIN_MODE_INPUT(GPIOD_PIN12) | \ + PIN_MODE_INPUT(GPIOD_PIN13) | \ + PIN_MODE_INPUT(GPIOD_PIN14) | \ + PIN_MODE_INPUT(GPIOD_PIN15)) #define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_PIN0) | \ PIN_OTYPE_PUSHPULL(GPIOD_PIN1) | \ PIN_OTYPE_PUSHPULL(GPIOD_PIN2) | \ PIN_OTYPE_PUSHPULL(GPIOD_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOD_CS43L22_RESET) |\ - PIN_OTYPE_PUSHPULL(GPIOD_OverCurrent) |\ + PIN_OTYPE_PUSHPULL(GPIOD_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN5) | \ PIN_OTYPE_PUSHPULL(GPIOD_PIN6) | \ PIN_OTYPE_PUSHPULL(GPIOD_PIN7) | \ PIN_OTYPE_PUSHPULL(GPIOD_PIN8) | \ PIN_OTYPE_PUSHPULL(GPIOD_PIN9) | \ PIN_OTYPE_PUSHPULL(GPIOD_PIN10) | \ PIN_OTYPE_PUSHPULL(GPIOD_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOD_LED4) | \ - PIN_OTYPE_PUSHPULL(GPIOD_LED3) | \ - PIN_OTYPE_PUSHPULL(GPIOD_LED5) | \ - PIN_OTYPE_PUSHPULL(GPIOD_LED6)) + PIN_OTYPE_PUSHPULL(GPIOD_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN15)) #define VAL_GPIOD_OSPEEDR (PIN_OSPEED_HIGH(GPIOD_PIN0) | \ PIN_OSPEED_HIGH(GPIOD_PIN1) | \ PIN_OSPEED_HIGH(GPIOD_PIN2) | \ PIN_OSPEED_HIGH(GPIOD_PIN3) | \ - PIN_OSPEED_HIGH(GPIOD_CS43L22_RESET) | \ - PIN_OSPEED_HIGH(GPIOD_OverCurrent) | \ + PIN_OSPEED_HIGH(GPIOD_PIN4) | \ + PIN_OSPEED_HIGH(GPIOD_PIN5) | \ PIN_OSPEED_HIGH(GPIOD_PIN6) | \ PIN_OSPEED_HIGH(GPIOD_PIN7) | \ PIN_OSPEED_HIGH(GPIOD_PIN8) | \ PIN_OSPEED_HIGH(GPIOD_PIN9) | \ PIN_OSPEED_HIGH(GPIOD_PIN10) | \ PIN_OSPEED_HIGH(GPIOD_PIN11) | \ - PIN_OSPEED_HIGH(GPIOD_LED4) | \ - PIN_OSPEED_HIGH(GPIOD_LED3) | \ - PIN_OSPEED_HIGH(GPIOD_LED5) | \ - PIN_OSPEED_HIGH(GPIOD_LED6)) + PIN_OSPEED_HIGH(GPIOD_PIN12) | \ + PIN_OSPEED_HIGH(GPIOD_PIN13) | \ + PIN_OSPEED_HIGH(GPIOD_PIN14) | \ + PIN_OSPEED_HIGH(GPIOD_PIN15)) #define VAL_GPIOD_PUPDR (PIN_PUPDR_PULLUP(GPIOD_PIN0) | \ PIN_PUPDR_PULLUP(GPIOD_PIN1) | \ PIN_PUPDR_PULLUP(GPIOD_PIN2) | \ PIN_PUPDR_PULLUP(GPIOD_PIN3) | \ - PIN_PUPDR_PULLUP(GPIOD_CS43L22_RESET) |\ - PIN_PUPDR_FLOATING(GPIOD_OverCurrent) |\ + PIN_PUPDR_PULLUP(GPIOD_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN5) | \ PIN_PUPDR_PULLUP(GPIOD_PIN6) | \ PIN_PUPDR_PULLUP(GPIOD_PIN7) | \ PIN_PUPDR_PULLUP(GPIOD_PIN8) | \ PIN_PUPDR_PULLUP(GPIOD_PIN9) | \ PIN_PUPDR_PULLUP(GPIOD_PIN10) | \ PIN_PUPDR_PULLUP(GPIOD_PIN11) | \ - PIN_PUPDR_FLOATING(GPIOD_LED4) | \ - PIN_PUPDR_FLOATING(GPIOD_LED3) | \ - PIN_PUPDR_FLOATING(GPIOD_LED5) | \ - PIN_PUPDR_FLOATING(GPIOD_LED6)) + PIN_PUPDR_PULLUP(GPIOD_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN13) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN14) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN15)) #define VAL_GPIOD_ODR (PIN_ODR_HIGH(GPIOD_PIN0) | \ PIN_ODR_HIGH(GPIOD_PIN1) | \ PIN_ODR_HIGH(GPIOD_PIN2) | \ PIN_ODR_HIGH(GPIOD_PIN3) | \ - PIN_ODR_HIGH(GPIOD_CS43L22_RESET) | \ - PIN_ODR_HIGH(GPIOD_OverCurrent) | \ + PIN_ODR_HIGH(GPIOD_PIN4) | \ + PIN_ODR_HIGH(GPIOD_PIN5) | \ PIN_ODR_HIGH(GPIOD_PIN6) | \ PIN_ODR_HIGH(GPIOD_PIN7) | \ PIN_ODR_HIGH(GPIOD_PIN8) | \ PIN_ODR_HIGH(GPIOD_PIN9) | \ PIN_ODR_HIGH(GPIOD_PIN10) | \ PIN_ODR_HIGH(GPIOD_PIN11) | \ - PIN_ODR_LOW(GPIOD_LED4) | \ - PIN_ODR_LOW(GPIOD_LED3) | \ - PIN_ODR_LOW(GPIOD_LED5) | \ - PIN_ODR_LOW(GPIOD_LED6)) + PIN_ODR_HIGH(GPIOD_PIN12) | \ + PIN_ODR_HIGH(GPIOD_PIN13) | \ + PIN_ODR_HIGH(GPIOD_PIN14) | \ + PIN_ODR_HIGH(GPIOD_PIN15)) #define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_PIN0, 0U) | \ PIN_AFIO_AF(GPIOD_PIN1, 0U) | \ PIN_AFIO_AF(GPIOD_PIN2, 0U) | \ PIN_AFIO_AF(GPIOD_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOD_CS43L22_RESET, 0U) | \ - PIN_AFIO_AF(GPIOD_OverCurrent, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN5, 0U) | \ PIN_AFIO_AF(GPIOD_PIN6, 0U) | \ PIN_AFIO_AF(GPIOD_PIN7, 0U)) #define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_PIN8, 0U) | \ PIN_AFIO_AF(GPIOD_PIN9, 0U) | \ PIN_AFIO_AF(GPIOD_PIN10, 0U) | \ PIN_AFIO_AF(GPIOD_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOD_LED4, 0U) | \ - PIN_AFIO_AF(GPIOD_LED3, 0U) | \ - PIN_AFIO_AF(GPIOD_LED5, 0U) | \ - PIN_AFIO_AF(GPIOD_LED6, 0U)) + PIN_AFIO_AF(GPIOD_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN15, 0U)) /* * GPIOE setup: * - * PE0 - L3GD20_INT1 (input pullup). - * PE1 - L3GD20_INT2 (input pullup). - * PE2 - LSM303DLHC_DRDY (input floating). - * PE3 - L3GD20_CS (output pushpull maximum). - * PE4 - LSM303DLHC_INT1 (output pushpull maximum). - * PE5 - LSM303DLHC_INT2 (output pushpull maximum). + * PE0 - PIN0 (input pullup). + * PE1 - PIN1 (input pullup). + * PE2 - PIN2 (input pullup). + * PE3 - PIN3 (input pullup). + * PE4 - PIN4 (input pullup). + * PE5 - PIN5 (input pullup). * PE6 - PIN6 (input pullup). * PE7 - PIN7 (input pullup). * PE8 - PIN8 (input pullup). @@ -784,12 +758,12 @@ * PE14 - PIN14 (input pullup). * PE15 - PIN15 (input pullup). */ -#define VAL_GPIOE_MODER (PIN_MODE_INPUT(GPIOE_L3GD20_INT1) | \ - PIN_MODE_INPUT(GPIOE_L3GD20_INT2) | \ - PIN_MODE_INPUT(GPIOE_LSM303DLHC_DRDY) |\ - PIN_MODE_OUTPUT(GPIOE_L3GD20_CS) | \ - PIN_MODE_OUTPUT(GPIOE_LSM303DLHC_INT1) |\ - PIN_MODE_OUTPUT(GPIOE_LSM303DLHC_INT2) |\ +#define VAL_GPIOE_MODER (PIN_MODE_INPUT(GPIOE_PIN0) | \ + PIN_MODE_INPUT(GPIOE_PIN1) | \ + PIN_MODE_INPUT(GPIOE_PIN2) | \ + PIN_MODE_INPUT(GPIOE_PIN3) | \ + PIN_MODE_INPUT(GPIOE_PIN4) | \ + PIN_MODE_INPUT(GPIOE_PIN5) | \ PIN_MODE_INPUT(GPIOE_PIN6) | \ PIN_MODE_INPUT(GPIOE_PIN7) | \ PIN_MODE_INPUT(GPIOE_PIN8) | \ @@ -800,12 +774,12 @@ PIN_MODE_INPUT(GPIOE_PIN13) | \ PIN_MODE_INPUT(GPIOE_PIN14) | \ PIN_MODE_INPUT(GPIOE_PIN15)) -#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_L3GD20_INT1) |\ - PIN_OTYPE_PUSHPULL(GPIOE_L3GD20_INT2) |\ - PIN_OTYPE_PUSHPULL(GPIOE_LSM303DLHC_DRDY) |\ - PIN_OTYPE_PUSHPULL(GPIOE_L3GD20_CS) | \ - PIN_OTYPE_PUSHPULL(GPIOE_LSM303DLHC_INT1) |\ - PIN_OTYPE_PUSHPULL(GPIOE_LSM303DLHC_INT2) |\ +#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN5) | \ PIN_OTYPE_PUSHPULL(GPIOE_PIN6) | \ PIN_OTYPE_PUSHPULL(GPIOE_PIN7) | \ PIN_OTYPE_PUSHPULL(GPIOE_PIN8) | \ @@ -816,12 +790,12 @@ PIN_OTYPE_PUSHPULL(GPIOE_PIN13) | \ PIN_OTYPE_PUSHPULL(GPIOE_PIN14) | \ PIN_OTYPE_PUSHPULL(GPIOE_PIN15)) -#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_HIGH(GPIOE_L3GD20_INT1) | \ - PIN_OSPEED_HIGH(GPIOE_L3GD20_INT2) | \ - PIN_OSPEED_HIGH(GPIOE_LSM303DLHC_DRDY) |\ - PIN_OSPEED_HIGH(GPIOE_L3GD20_CS) | \ - PIN_OSPEED_HIGH(GPIOE_LSM303DLHC_INT1) |\ - PIN_OSPEED_HIGH(GPIOE_LSM303DLHC_INT2) |\ +#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_HIGH(GPIOE_PIN0) | \ + PIN_OSPEED_HIGH(GPIOE_PIN1) | \ + PIN_OSPEED_HIGH(GPIOE_PIN2) | \ + PIN_OSPEED_HIGH(GPIOE_PIN3) | \ + PIN_OSPEED_HIGH(GPIOE_PIN4) | \ + PIN_OSPEED_HIGH(GPIOE_PIN5) | \ PIN_OSPEED_HIGH(GPIOE_PIN6) | \ PIN_OSPEED_HIGH(GPIOE_PIN7) | \ PIN_OSPEED_HIGH(GPIOE_PIN8) | \ @@ -832,12 +806,12 @@ PIN_OSPEED_HIGH(GPIOE_PIN13) | \ PIN_OSPEED_HIGH(GPIOE_PIN14) | \ PIN_OSPEED_HIGH(GPIOE_PIN15)) -#define VAL_GPIOE_PUPDR (PIN_PUPDR_PULLUP(GPIOE_L3GD20_INT1) | \ - PIN_PUPDR_PULLUP(GPIOE_L3GD20_INT2) | \ - PIN_PUPDR_FLOATING(GPIOE_LSM303DLHC_DRDY) |\ - PIN_PUPDR_PULLUP(GPIOE_L3GD20_CS) | \ - PIN_PUPDR_PULLUP(GPIOE_LSM303DLHC_INT1) |\ - PIN_PUPDR_PULLUP(GPIOE_LSM303DLHC_INT2) |\ +#define VAL_GPIOE_PUPDR (PIN_PUPDR_PULLUP(GPIOE_PIN0) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN1) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN3) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN5) | \ PIN_PUPDR_PULLUP(GPIOE_PIN6) | \ PIN_PUPDR_PULLUP(GPIOE_PIN7) | \ PIN_PUPDR_PULLUP(GPIOE_PIN8) | \ @@ -848,12 +822,12 @@ PIN_PUPDR_PULLUP(GPIOE_PIN13) | \ PIN_PUPDR_PULLUP(GPIOE_PIN14) | \ PIN_PUPDR_PULLUP(GPIOE_PIN15)) -#define VAL_GPIOE_ODR (PIN_ODR_HIGH(GPIOE_L3GD20_INT1) | \ - PIN_ODR_HIGH(GPIOE_L3GD20_INT2) | \ - PIN_ODR_HIGH(GPIOE_LSM303DLHC_DRDY) | \ - PIN_ODR_HIGH(GPIOE_L3GD20_CS) | \ - PIN_ODR_HIGH(GPIOE_LSM303DLHC_INT1) | \ - PIN_ODR_HIGH(GPIOE_LSM303DLHC_INT2) | \ +#define VAL_GPIOE_ODR (PIN_ODR_HIGH(GPIOE_PIN0) | \ + PIN_ODR_HIGH(GPIOE_PIN1) | \ + PIN_ODR_HIGH(GPIOE_PIN2) | \ + PIN_ODR_HIGH(GPIOE_PIN3) | \ + PIN_ODR_HIGH(GPIOE_PIN4) | \ + PIN_ODR_HIGH(GPIOE_PIN5) | \ PIN_ODR_HIGH(GPIOE_PIN6) | \ PIN_ODR_HIGH(GPIOE_PIN7) | \ PIN_ODR_HIGH(GPIOE_PIN8) | \ @@ -864,12 +838,12 @@ PIN_ODR_HIGH(GPIOE_PIN13) | \ PIN_ODR_HIGH(GPIOE_PIN14) | \ PIN_ODR_HIGH(GPIOE_PIN15)) -#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_L3GD20_INT1, 0U) | \ - PIN_AFIO_AF(GPIOE_L3GD20_INT2, 0U) | \ - PIN_AFIO_AF(GPIOE_LSM303DLHC_DRDY, 0U) |\ - PIN_AFIO_AF(GPIOE_L3GD20_CS, 0U) | \ - PIN_AFIO_AF(GPIOE_LSM303DLHC_INT1, 0U) |\ - PIN_AFIO_AF(GPIOE_LSM303DLHC_INT2, 0U) |\ +#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_PIN0, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN1, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN5, 0U) | \ PIN_AFIO_AF(GPIOE_PIN6, 0U) | \ PIN_AFIO_AF(GPIOE_PIN7, 0U)) #define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_PIN8, 0U) | \ @@ -1118,8 +1092,8 @@ /* * GPIOH setup: * - * PH0 - OSC_IN (input floating). - * PH1 - OSC_OUT (input floating). + * PH0 - PIN0 (input pullup). + * PH1 - PIN1 (input pullup). * PH2 - PIN2 (input pullup). * PH3 - PIN3 (input pullup). * PH4 - PIN4 (input pullup). @@ -1135,8 +1109,8 @@ * PH14 - PIN14 (input pullup). * PH15 - PIN15 (input pullup). */ -#define VAL_GPIOH_MODER (PIN_MODE_INPUT(GPIOH_OSC_IN) | \ - PIN_MODE_INPUT(GPIOH_OSC_OUT) | \ +#define VAL_GPIOH_MODER (PIN_MODE_INPUT(GPIOH_PIN0) | \ + PIN_MODE_INPUT(GPIOH_PIN1) | \ PIN_MODE_INPUT(GPIOH_PIN2) | \ PIN_MODE_INPUT(GPIOH_PIN3) | \ PIN_MODE_INPUT(GPIOH_PIN4) | \ @@ -1151,8 +1125,8 @@ PIN_MODE_INPUT(GPIOH_PIN13) | \ PIN_MODE_INPUT(GPIOH_PIN14) | \ PIN_MODE_INPUT(GPIOH_PIN15)) -#define VAL_GPIOH_OTYPER (PIN_OTYPE_PUSHPULL(GPIOH_OSC_IN) | \ - PIN_OTYPE_PUSHPULL(GPIOH_OSC_OUT) | \ +#define VAL_GPIOH_OTYPER (PIN_OTYPE_PUSHPULL(GPIOH_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN1) | \ PIN_OTYPE_PUSHPULL(GPIOH_PIN2) | \ PIN_OTYPE_PUSHPULL(GPIOH_PIN3) | \ PIN_OTYPE_PUSHPULL(GPIOH_PIN4) | \ @@ -1167,8 +1141,8 @@ PIN_OTYPE_PUSHPULL(GPIOH_PIN13) | \ PIN_OTYPE_PUSHPULL(GPIOH_PIN14) | \ PIN_OTYPE_PUSHPULL(GPIOH_PIN15)) -#define VAL_GPIOH_OSPEEDR (PIN_OSPEED_HIGH(GPIOH_OSC_IN) | \ - PIN_OSPEED_HIGH(GPIOH_OSC_OUT) | \ +#define VAL_GPIOH_OSPEEDR (PIN_OSPEED_HIGH(GPIOH_PIN0) | \ + PIN_OSPEED_HIGH(GPIOH_PIN1) | \ PIN_OSPEED_HIGH(GPIOH_PIN2) | \ PIN_OSPEED_HIGH(GPIOH_PIN3) | \ PIN_OSPEED_HIGH(GPIOH_PIN4) | \ @@ -1183,8 +1157,8 @@ PIN_OSPEED_HIGH(GPIOH_PIN13) | \ PIN_OSPEED_HIGH(GPIOH_PIN14) | \ PIN_OSPEED_HIGH(GPIOH_PIN15)) -#define VAL_GPIOH_PUPDR (PIN_PUPDR_FLOATING(GPIOH_OSC_IN) | \ - PIN_PUPDR_FLOATING(GPIOH_OSC_OUT) | \ +#define VAL_GPIOH_PUPDR (PIN_PUPDR_PULLUP(GPIOH_PIN0) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN1) | \ PIN_PUPDR_PULLUP(GPIOH_PIN2) | \ PIN_PUPDR_PULLUP(GPIOH_PIN3) | \ PIN_PUPDR_PULLUP(GPIOH_PIN4) | \ @@ -1199,8 +1173,8 @@ PIN_PUPDR_PULLUP(GPIOH_PIN13) | \ PIN_PUPDR_PULLUP(GPIOH_PIN14) | \ PIN_PUPDR_PULLUP(GPIOH_PIN15)) -#define VAL_GPIOH_ODR (PIN_ODR_HIGH(GPIOH_OSC_IN) | \ - PIN_ODR_HIGH(GPIOH_OSC_OUT) | \ +#define VAL_GPIOH_ODR (PIN_ODR_HIGH(GPIOH_PIN0) | \ + PIN_ODR_HIGH(GPIOH_PIN1) | \ PIN_ODR_HIGH(GPIOH_PIN2) | \ PIN_ODR_HIGH(GPIOH_PIN3) | \ PIN_ODR_HIGH(GPIOH_PIN4) | \ @@ -1215,8 +1189,8 @@ PIN_ODR_HIGH(GPIOH_PIN13) | \ PIN_ODR_HIGH(GPIOH_PIN14) | \ PIN_ODR_HIGH(GPIOH_PIN15)) -#define VAL_GPIOH_AFRL (PIN_AFIO_AF(GPIOH_OSC_IN, 0U) | \ - PIN_AFIO_AF(GPIOH_OSC_OUT, 0U) | \ +#define VAL_GPIOH_AFRL (PIN_AFIO_AF(GPIOH_PIN0, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN1, 0U) | \ PIN_AFIO_AF(GPIOH_PIN2, 0U) | \ PIN_AFIO_AF(GPIOH_PIN3, 0U) | \ PIN_AFIO_AF(GPIOH_PIN4, 0U) | \ diff --git a/platforms/chibios/boards/STEMCELL/configs/halconf.h b/platforms/chibios/boards/STEMCELL/configs/halconf.h index f7d9cf10c804..a82b898efa76 100644 --- a/platforms/chibios/boards/STEMCELL/configs/halconf.h +++ b/platforms/chibios/boards/STEMCELL/configs/halconf.h @@ -20,9 +20,10 @@ #define PAL_USE_WAIT TRUE #define PAL_USE_CALLBACKS TRUE -// #define HAL_USE_PWM TRUE #define HAL_USE_I2C TRUE #define HAL_USE_SERIAL TRUE +// #define HAL_USE_PWM TRUE + #include_next diff --git a/platforms/chibios/boards/STEMCELL/configs/mcuconf.h b/platforms/chibios/boards/STEMCELL/configs/mcuconf.h index ddbaf725c2fc..5c17ffe20250 100644 --- a/platforms/chibios/boards/STEMCELL/configs/mcuconf.h +++ b/platforms/chibios/boards/STEMCELL/configs/mcuconf.h @@ -32,7 +32,7 @@ */ #define STM32F4xx_MCUCONF -#define STM32F401_MCUCONF +#define STM32F411_MCUCONF /* * HAL driver system settings. diff --git a/platforms/chibios/boards/STEMCELL/convert_to_stemcell.mk b/platforms/chibios/boards/STEMCELL/convert_to_stemcell.mk index 39578f67b742..c12dd0797b5e 100644 --- a/platforms/chibios/boards/STEMCELL/convert_to_stemcell.mk +++ b/platforms/chibios/boards/STEMCELL/convert_to_stemcell.mk @@ -1,6 +1,6 @@ # Proton C MCU settings for converting AVR projects TARGET := $(TARGET)_stemcell -MCU := STM32F401 +MCU := STM32F411 BOARD := STEMCELL BOOTLOADER := tinyuf2 OPT_DEFS += -DCONVERT_TO_STEMCELL diff --git a/platforms/chibios/pin_defs.h b/platforms/chibios/pin_defs.h index 1fb0dc638844..19bc55223685 100644 --- a/platforms/chibios/pin_defs.h +++ b/platforms/chibios/pin_defs.h @@ -63,7 +63,6 @@ # ifndef SERIAL_USART_DRIVER # define SERIAL_USART_DRIVER SD2 # endif -// # define USART2_REMAP # else # define D3 PAL_LINE(GPIOA, 2) # define D2 PAL_LINE(GPIOA, 3) From e54e44f0941b435f68175bde597834902474a065 Mon Sep 17 00:00:00 2001 From: Mariappan Ramasamy <947300+Mariappan@users.noreply.github.com> Date: Tue, 8 Mar 2022 19:00:58 +0800 Subject: [PATCH 11/20] revert matrix_init_pin changes --- builddefs/common_features.mk | 1 + quantum/matrix.c | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/builddefs/common_features.mk b/builddefs/common_features.mk index 66f416b5f137..08d186d656c7 100644 --- a/builddefs/common_features.mk +++ b/builddefs/common_features.mk @@ -184,6 +184,7 @@ else # Automatically provided by avr-libc, nothing required else ifeq ($(PLATFORM),CHIBIOS) ifneq ($(filter STM32F3xx_% STM32F1xx_% %_STM32F401xC %_STM32F401xE %_STM32F405xG %_STM32F411xE %_STM32F072xB %_STM32F042x6 %_GD32VF103xB %_GD32VF103x8, $(MCU_SERIES)_$(MCU_LDSCRIPT)),) + # Emulated EEPROM OPT_DEFS += -DEEPROM_DRIVER -DEEPROM_STM32_FLASH_EMULATED COMMON_VPATH += $(DRIVER_PATH)/eeprom SRC += eeprom_driver.c diff --git a/quantum/matrix.c b/quantum/matrix.c index 8575a7f8de5f..db59b73754f5 100644 --- a/quantum/matrix.c +++ b/quantum/matrix.c @@ -107,7 +107,7 @@ __attribute__((weak)) void matrix_init_pins(void) { for (int row = 0; row < ROWS_PER_HAND; row++) { for (int col = 0; col < MATRIX_COLS; col++) { pin_t pin = direct_pins[row][col]; - if ((pin != NO_PIN) && (pin != 0)) { + if (pin != NO_PIN) { setPinInputHigh(pin); } } From 2ee2f2012dce27e6f8bfd74e8b7d05b47e6bdfb4 Mon Sep 17 00:00:00 2001 From: Mariappan Ramasamy <947300+Mariappan@users.noreply.github.com> Date: Tue, 8 Mar 2022 19:10:10 +0800 Subject: [PATCH 12/20] revert unintended changes. chibios & contrib --- lib/chibios | 2 +- lib/chibios-contrib | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/lib/chibios b/lib/chibios index d7b9d1c87f72..257302333c31 160000 --- a/lib/chibios +++ b/lib/chibios @@ -1 +1 @@ -Subproject commit d7b9d1c87f724bd7c8cd1486d6d0dc3ba52e0d52 +Subproject commit 257302333c31f1f710800c2b97acf3550de043e1 diff --git a/lib/chibios-contrib b/lib/chibios-contrib index d1c2126d1cd8..ff1c6ec90cfc 160000 --- a/lib/chibios-contrib +++ b/lib/chibios-contrib @@ -1 +1 @@ -Subproject commit d1c2126d1cd867c50127da84425805e225df8555 +Subproject commit ff1c6ec90cfc250d81e6f29a0d60a4faf2afb46d From fff8ece6a60dbed597461bda01b59d5b0d69ed75 Mon Sep 17 00:00:00 2001 From: Mariappan Ramasamy <947300+Mariappan@users.noreply.github.com> Date: Tue, 8 Mar 2022 19:28:32 +0800 Subject: [PATCH 13/20] Fix formatting issue --- platforms/chibios/pin_defs.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/platforms/chibios/pin_defs.h b/platforms/chibios/pin_defs.h index 19bc55223685..6717a5597c7d 100644 --- a/platforms/chibios/pin_defs.h +++ b/platforms/chibios/pin_defs.h @@ -60,9 +60,9 @@ # ifdef CONVERT_TO_STEMCELL_UART_SWAP # define D3 PAL_LINE(GPIOA, 3) # define D2 PAL_LINE(GPIOA, 2) -# ifndef SERIAL_USART_DRIVER -# define SERIAL_USART_DRIVER SD2 -# endif +# ifndef SERIAL_USART_DRIVER +# define SERIAL_USART_DRIVER SD2 +# endif # else # define D3 PAL_LINE(GPIOA, 2) # define D2 PAL_LINE(GPIOA, 3) @@ -101,9 +101,9 @@ # define D5 PAL_LINE(GPIOA, 8) # define B0 PAL_LINE(GPIOA, 9) // unconnected pin -# define I2C1_SCL_PIN D0 -# define I2C1_SDA_PIN D1 -# define FEE_PAGE_BASE_ADDRESS 0x08008000 +# define I2C1_SCL_PIN D0 +# define I2C1_SDA_PIN D1 +# define FEE_PAGE_BASE_ADDRESS 0x08008000 #else # define A0 PAL_LINE(GPIOA, 0) From 8730c633f5631a67888abdb0c6029fb29c08ed04 Mon Sep 17 00:00:00 2001 From: Mega Mind <947300+Mariappan@users.noreply.github.com> Date: Wed, 9 Mar 2022 11:52:04 +0800 Subject: [PATCH 14/20] Address comments --- builddefs/build_keyboard.mk | 10 ---------- platforms/chibios/boards/STEMCELL/configs/config.h | 5 ----- platforms/chibios/boards/STEMCELL/configs/halconf.h | 5 ----- platforms/chibios/boards/STEMCELL/configs/mcuconf.h | 12 ++++++------ .../chibios/boards/STEMCELL/convert_to_stemcell.mk | 11 +++++++++++ 5 files changed, 17 insertions(+), 26 deletions(-) diff --git a/builddefs/build_keyboard.mk b/builddefs/build_keyboard.mk index 32aa277446b3..d034b749bbe0 100644 --- a/builddefs/build_keyboard.mk +++ b/builddefs/build_keyboard.mk @@ -180,16 +180,6 @@ ifeq ($(strip $(STMC)), yes) CONVERT_TO_STEMCELL=yes endif -ifeq ($(strip $(STMC_US)), yes) - CONVERT_TO_STEMCELL_UART_SWAP=yes - OPT_DEFS += -DCONVERT_TO_STEMCELL_UART_SWAP -endif - -ifeq ($(strip $(STMC_IS)), yes) - CONVERT_TO_STEMCELL_I2C_SWAP=yes - OPT_DEFS += -DCONVERT_TO_STEMCELL_I2C_SWAP -endif - ifeq ($(strip $(CONVERT_TO_STEMCELL)), yes) include platforms/chibios/boards/STEMCELL/convert_to_stemcell.mk endif diff --git a/platforms/chibios/boards/STEMCELL/configs/config.h b/platforms/chibios/boards/STEMCELL/configs/config.h index e611618c541c..667f81ef8674 100644 --- a/platforms/chibios/boards/STEMCELL/configs/config.h +++ b/platforms/chibios/boards/STEMCELL/configs/config.h @@ -16,11 +16,6 @@ */ #pragma once -// Only HSE clock. No LSE clock -#ifndef STM32_HSECLK -# define STM32_HSECLK 8000000U -#endif // STM32_HSECLK - #ifndef EARLY_INIT_PERFORM_BOOTLOADER_JUMP # define EARLY_INIT_PERFORM_BOOTLOADER_JUMP TRUE #endif diff --git a/platforms/chibios/boards/STEMCELL/configs/halconf.h b/platforms/chibios/boards/STEMCELL/configs/halconf.h index a82b898efa76..fa12a36a75b0 100644 --- a/platforms/chibios/boards/STEMCELL/configs/halconf.h +++ b/platforms/chibios/boards/STEMCELL/configs/halconf.h @@ -16,14 +16,9 @@ */ #pragma once -// #define HAL_USE_DAC TRUE #define PAL_USE_WAIT TRUE #define PAL_USE_CALLBACKS TRUE - #define HAL_USE_I2C TRUE - #define HAL_USE_SERIAL TRUE -// #define HAL_USE_PWM TRUE - #include_next diff --git a/platforms/chibios/boards/STEMCELL/configs/mcuconf.h b/platforms/chibios/boards/STEMCELL/configs/mcuconf.h index 5c17ffe20250..636a2d99633d 100644 --- a/platforms/chibios/boards/STEMCELL/configs/mcuconf.h +++ b/platforms/chibios/boards/STEMCELL/configs/mcuconf.h @@ -48,13 +48,13 @@ #define STM32_CLOCK48_REQUIRED TRUE #define STM32_SW STM32_SW_PLL #define STM32_PLLSRC STM32_PLLSRC_HSE -#define STM32_PLLM_VALUE 8 -#define STM32_PLLN_VALUE 336 -#define STM32_PLLP_VALUE 4 -#define STM32_PLLQ_VALUE 7 +#define STM32_PLLM_VALUE 4 +#define STM32_PLLN_VALUE 96 +#define STM32_PLLP_VALUE 2 +#define STM32_PLLQ_VALUE 4 #define STM32_HPRE STM32_HPRE_DIV1 -#define STM32_PPRE1 STM32_PPRE1_DIV4 -#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_PPRE1 STM32_PPRE1_DIV2 +#define STM32_PPRE2 STM32_PPRE2_DIV1 #define STM32_RTCSEL STM32_RTCSEL_LSI #define STM32_RTCPRE_VALUE 8 #define STM32_MCO1SEL STM32_MCO1SEL_HSI diff --git a/platforms/chibios/boards/STEMCELL/convert_to_stemcell.mk b/platforms/chibios/boards/STEMCELL/convert_to_stemcell.mk index c12dd0797b5e..d5180384b897 100644 --- a/platforms/chibios/boards/STEMCELL/convert_to_stemcell.mk +++ b/platforms/chibios/boards/STEMCELL/convert_to_stemcell.mk @@ -12,3 +12,14 @@ SERIAL_DRIVER := usart # These are defaults based on what has been implemented for ARM boards AUDIO_ENABLE ?= no WS2812_DRIVER ?= bitbang + +ifeq ($(strip $(STMC_US)), yes) + CONVERT_TO_STEMCELL_UART_SWAP=yes + OPT_DEFS += -DCONVERT_TO_STEMCELL_UART_SWAP +endif + +ifeq ($(strip $(STMC_IS)), yes) + CONVERT_TO_STEMCELL_I2C_SWAP=yes + OPT_DEFS += -DCONVERT_TO_STEMCELL_I2C_SWAP +endif + From cd331723392ec2aa31e4f1ed32019dfdc4476a94 Mon Sep 17 00:00:00 2001 From: Mega Mind <947300+Mariappan@users.noreply.github.com> Date: Wed, 9 Mar 2022 14:14:23 +0800 Subject: [PATCH 15/20] Enable EEPROM defs for STM32F4 series --- builddefs/common_features.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/builddefs/common_features.mk b/builddefs/common_features.mk index 08d186d656c7..6b77e7233e63 100644 --- a/builddefs/common_features.mk +++ b/builddefs/common_features.mk @@ -183,7 +183,7 @@ else ifeq ($(PLATFORM),AVR) # Automatically provided by avr-libc, nothing required else ifeq ($(PLATFORM),CHIBIOS) - ifneq ($(filter STM32F3xx_% STM32F1xx_% %_STM32F401xC %_STM32F401xE %_STM32F405xG %_STM32F411xE %_STM32F072xB %_STM32F042x6 %_GD32VF103xB %_GD32VF103x8, $(MCU_SERIES)_$(MCU_LDSCRIPT)),) + ifneq ($(filter STM32F3xx_% STM32F1xx_% STM32F4xx_% %_STM32F401xC %_STM32F401xE %_STM32F405xG %_STM32F411xE %_STM32F072xB %_STM32F042x6 %_GD32VF103xB %_GD32VF103x8, $(MCU_SERIES)_$(MCU_LDSCRIPT)),) # Emulated EEPROM OPT_DEFS += -DEEPROM_DRIVER -DEEPROM_STM32_FLASH_EMULATED COMMON_VPATH += $(DRIVER_PATH)/eeprom From 8133b92a755cf15ff90ad6cd0dd1e9e79e81653c Mon Sep 17 00:00:00 2001 From: Mega Mind <947300+Mariappan@users.noreply.github.com> Date: Wed, 9 Mar 2022 23:00:31 +0800 Subject: [PATCH 16/20] Remove a_dux test keymaps --- keyboards/a_dux/keymaps/via/keymap.c | 40 ---------------------------- keyboards/a_dux/keymaps/via/rules.mk | 4 --- 2 files changed, 44 deletions(-) delete mode 100644 keyboards/a_dux/keymaps/via/keymap.c delete mode 100644 keyboards/a_dux/keymaps/via/rules.mk diff --git a/keyboards/a_dux/keymaps/via/keymap.c b/keyboards/a_dux/keymaps/via/keymap.c deleted file mode 100644 index b58c9d447f91..000000000000 --- a/keyboards/a_dux/keymaps/via/keymap.c +++ /dev/null @@ -1,40 +0,0 @@ -// Copyright 2022 @filterpaper -// SPDX-License-Identifier: GPL-2.0+ - -#include QMK_KEYBOARD_H - -// Seniply layout -// https://stevep99.github.io/seniply - -const uint16_t PROGMEM keymaps[][MATRIX_ROWS][MATRIX_COLS] = { - [0] = LAYOUT_split_3x5_2( - KC_Q, KC_W, KC_E, KC_R, KC_T, KC_Y, KC_U, KC_I, KC_O, KC_P, - KC_A, KC_S, KC_D, KC_F, KC_G, KC_H, KC_J, KC_K, KC_L, KC_SCLN, - KC_Z, KC_X, KC_C, KC_V, KC_B, KC_N, KC_M, KC_COMM, KC_DOT, KC_SLSH, - LT(3,KC_TAB), KC_LSFT, KC_SPC, LT(1,KC_ENT) - ), - [1] = LAYOUT_split_3x5_2( - KC_EXLM, KC_AT, KC_SCLN, KC_COLN, KC_UNDS, KC_EQL, KC_7, KC_8, KC_9, KC_PLUS, - KC_BSLS, KC_PIPE, KC_LCBR, KC_LPRN, KC_LBRC, KC_ASTR, KC_4, KC_5, KC_6, KC_MINS, - KC_NO, KC_NO, KC_RCBR, KC_RPRN, KC_RBRC, KC_0, KC_1, KC_2, KC_3, KC_SLSH, - _______, MO(2), _______, _______ - ), - [2] = LAYOUT_split_3x5_2( - RALT(KC_1), RALT(KC_2), RALT(KC_3), RALT(KC_4), KC_BRIU, KC_NO, KC_AMPR, KC_GRV, KC_TILD, KC_NO, - KC_MUTE, KC_VOLD, KC_MPLY, KC_VOLU, KC_BRID, KC_NO, KC_DLR, KC_PERC, KC_CIRC, KC_UNDS, - KC_EJCT, KC_MPRV, KC_MSTP, KC_MNXT, KC_NO, KC_NO, KC_EXLM, KC_AT, KC_HASH, KC_NO, - _______, _______, _______, _______ - ), - [3] = LAYOUT_split_3x5_2( - KC_ESC, LALT(KC_LEFT), LCTL(KC_F), LALT(KC_RGHT), KC_INS, KC_PGUP, KC_HOME, KC_UP, KC_END, KC_CAPS, - OSM(MOD_LALT), OSM(MOD_LGUI), OSM(MOD_LSFT), OSM(MOD_LCTL), OSM(MOD_RALT), KC_PGDN, KC_LEFT, KC_DOWN, KC_RGHT, KC_DEL, - LCTL(KC_Z), LCTL(KC_X), LCTL(KC_C), KC_TAB, LCTL(KC_V), KC_ENT, KC_BSPC, KC_RCTL, KC_LALT, KC_APP, - _______, _______, _______, MO(4) - ), - [4] = LAYOUT_split_3x5_2( - KC_NO, KC_NO, RCS(KC_F), KC_PSCR, KC_NO, KC_F12, KC_F7, KC_F8, KC_F9, KC_NO, - OSM(MOD_LALT), OSM(MOD_LGUI), OSM(MOD_LSFT), OSM(MOD_LCTL), OSM(MOD_RALT), KC_F11, KC_F4, KC_F5, KC_F6, KC_NO, - RCS(KC_Z), RCS(KC_X), RCS(KC_C), LSFT(KC_TAB), RCS(KC_V), KC_F10, KC_F1, KC_F2, KC_F3, KC_NO, - _______, _______, _______, _______ - ) -}; diff --git a/keyboards/a_dux/keymaps/via/rules.mk b/keyboards/a_dux/keymaps/via/rules.mk deleted file mode 100644 index 6c24ff1a0375..000000000000 --- a/keyboards/a_dux/keymaps/via/rules.mk +++ /dev/null @@ -1,4 +0,0 @@ -VIA_ENABLE = yes -OLED_ENABLE = no -MOUSEKEY_ENABLE = yes -EXTRAKEY_ENABLE = yes From 15443853645ce633c6084097b1aa0e0da8094d9f Mon Sep 17 00:00:00 2001 From: Mega Mind <947300+Mariappan@users.noreply.github.com> Date: Wed, 9 Mar 2022 23:01:36 +0800 Subject: [PATCH 17/20] Use v1.0.1 pinout since v1.0.0 is not in use anyway --- platforms/chibios/pin_defs.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/platforms/chibios/pin_defs.h b/platforms/chibios/pin_defs.h index 6717a5597c7d..0e6f27177f3f 100644 --- a/platforms/chibios/pin_defs.h +++ b/platforms/chibios/pin_defs.h @@ -93,9 +93,9 @@ # define F5 PAL_LINE(GPIOB, 2) # define F6 PAL_LINE(GPIOB, 1) # define F7 PAL_LINE(GPIOB, 0) -# define B1 PAL_LINE(GPIOA, 7) +# define B1 PAL_LINE(GPIOA, 5) # define B3 PAL_LINE(GPIOA, 6) -# define B2 PAL_LINE(GPIOA, 5) +# define B2 PAL_LINE(GPIOA, 7) # define B6 PAL_LINE(GPIOA, 4) # define D5 PAL_LINE(GPIOA, 8) From ac5223d3b5fc1f8a8d5a570726f088bc91355f63 Mon Sep 17 00:00:00 2001 From: Sadek Baroudi Date: Mon, 1 Aug 2022 00:21:47 -0700 Subject: [PATCH 18/20] updated megamind stemcell PR for latest develop branch --- builddefs/build_keyboard.mk | 8 --- data/mappings/defaults.json | 6 +++ docs/feature_converters.md | 3 ++ .../promicro_to_stemcell/_pin_defs.h | 54 +++++++++++++++++++ .../promicro_to_stemcell/converter.mk} | 6 +-- 5 files changed, 65 insertions(+), 12 deletions(-) create mode 100644 platforms/chibios/converters/promicro_to_stemcell/_pin_defs.h rename platforms/chibios/{boards/STEMCELL/convert_to_stemcell.mk => converters/promicro_to_stemcell/converter.mk} (81%) diff --git a/builddefs/build_keyboard.mk b/builddefs/build_keyboard.mk index 4cc1d15c090f..fe95dcaf15bd 100644 --- a/builddefs/build_keyboard.mk +++ b/builddefs/build_keyboard.mk @@ -182,14 +182,6 @@ endif include $(BUILDDEFS_PATH)/converters.mk -ifeq ($(strip $(STMC)), yes) - CONVERT_TO_STEMCELL=yes -endif - -ifeq ($(strip $(CONVERT_TO_STEMCELL)), yes) - include platforms/chibios/boards/STEMCELL/convert_to_stemcell.mk -endif - include $(BUILDDEFS_PATH)/mcu_selection.mk # Find all the C source files to be compiled in subfolders. diff --git a/data/mappings/defaults.json b/data/mappings/defaults.json index b62e5450b34f..136e3ddd7ed4 100644 --- a/data/mappings/defaults.json +++ b/data/mappings/defaults.json @@ -48,6 +48,12 @@ "processor": "STM32F411", "bootloader": "stm32-dfu", "board": "BLACKPILL_STM32_F411" + }, + "stemcell": { + "processor": "STM32F411", + "bootloader": "tinyuf2", + "board": "STEMCELL", + "pin_compatible": "promicro" } } } diff --git a/docs/feature_converters.md b/docs/feature_converters.md index 11dcc62b2a3a..1b36474dd8fa 100644 --- a/docs/feature_converters.md +++ b/docs/feature_converters.md @@ -14,6 +14,7 @@ Currently the following converters are available: | `promicro` | `kb2040` | | `promicro` | `promicro_rp2040` | | `promicro` | `blok` | +| `promicro` | `stemcell` | See below for more in depth information on each converter. @@ -54,6 +55,7 @@ If a board currently supported in QMK uses a [Pro Micro](https://www.sparkfun.co | [Adafruit KB2040](https://learn.adafruit.com/adafruit-kb2040) | `kb2040` | | [SparkFun Pro Micro - RP2040](https://www.sparkfun.com/products/18288) | `promicro_rp2040` | | [Blok](https://boardsource.xyz/store/628b95b494dfa308a6581622) | `blok` | +| [STeMcell](https://github.com/megamind4089/STeMCell) | `stemcell` | Converter summary: @@ -63,6 +65,7 @@ Converter summary: | `kb2040` | `-e CONVERT_TO=kb2040` | `CONVERT_TO=kb2040` | `#ifdef CONVERT_TO_KB2040` | | `promicro_rp2040` | `-e CONVERT_TO=promicro_rp2040` | `CONVERT_TO=promicro_rp2040` | `#ifdef CONVERT_TO_PROMICRO_RP2040` | | `blok` | `-e CONVERT_TO=blok` | `CONVERT_TO=blok` | `#ifdef CONVERT_TO_BLOK` | +| `stemcell` | `-e CONVERT_TO=stemcell` | `CONVERT_TO=stemcell` | `#ifdef CONVERT_TO_STEMCELL` | ### Proton C :id=proton_c diff --git a/platforms/chibios/converters/promicro_to_stemcell/_pin_defs.h b/platforms/chibios/converters/promicro_to_stemcell/_pin_defs.h new file mode 100644 index 000000000000..1f26bdebff6a --- /dev/null +++ b/platforms/chibios/converters/promicro_to_stemcell/_pin_defs.h @@ -0,0 +1,54 @@ +// Left side (front) +# ifdef CONVERT_TO_STEMCELL_UART_SWAP +# define D3 PAL_LINE(GPIOA, 3) +# define D2 PAL_LINE(GPIOA, 2) +# ifndef SERIAL_USART_DRIVER +# define SERIAL_USART_DRIVER SD2 +# endif +# else +# define D3 PAL_LINE(GPIOA, 2) +# define D2 PAL_LINE(GPIOA, 3) +# endif +// GND +// GND +# ifdef CONVERT_TO_STEMCELL_I2C_SWAP +# define D1 PAL_LINE(GPIOB, 6) +# define D0 PAL_LINE(GPIOB, 7) +# else +# define D1 PAL_LINE(GPIOB, 7) +# define D0 PAL_LINE(GPIOB, 6) +# endif + +# define D4 PAL_LINE(GPIOA, 15) +# define C6 PAL_LINE(GPIOB, 3) +# define D7 PAL_LINE(GPIOB, 4) +# define E6 PAL_LINE(GPIOB, 5) +# define B4 PAL_LINE(GPIOB, 8) +# define B5 PAL_LINE(GPIOB, 9) + +// Right side (front) +// RAW +// GND +// RESET +// VCC +# define F4 PAL_LINE(GPIOB, 10) +# define F5 PAL_LINE(GPIOB, 2) +# define F6 PAL_LINE(GPIOB, 1) +# define F7 PAL_LINE(GPIOB, 0) +# define B1 PAL_LINE(GPIOA, 5) +# define B3 PAL_LINE(GPIOA, 6) +# define B2 PAL_LINE(GPIOA, 7) +# define B6 PAL_LINE(GPIOA, 4) + +// Extra elite-c compatible pinout +# define B7 PAL_LINE(GPIOC, 13) +# define D5 PAL_LINE(GPIOC, 14) +# define C7 PAL_LINE(GPIOC, 15) +# define F1 PAL_LINE(GPIOA, 0) +# define F0 PAL_LINE(GPIOA, 1) + +# define B0 PAL_LINE(GPIOA, 9) // unconnected pin + +# define I2C1_SCL_PIN D0 +# define I2C1_SDA_PIN D1 +# define FEE_PAGE_BASE_ADDRESS 0x08008000 diff --git a/platforms/chibios/boards/STEMCELL/convert_to_stemcell.mk b/platforms/chibios/converters/promicro_to_stemcell/converter.mk similarity index 81% rename from platforms/chibios/boards/STEMCELL/convert_to_stemcell.mk rename to platforms/chibios/converters/promicro_to_stemcell/converter.mk index d5180384b897..8414dda59cbc 100644 --- a/platforms/chibios/boards/STEMCELL/convert_to_stemcell.mk +++ b/platforms/chibios/converters/promicro_to_stemcell/converter.mk @@ -1,10 +1,9 @@ -# Proton C MCU settings for converting AVR projects -TARGET := $(TARGET)_stemcell +# STEMCELL MCU settings for converting AVR projects MCU := STM32F411 BOARD := STEMCELL BOOTLOADER := tinyuf2 -OPT_DEFS += -DCONVERT_TO_STEMCELL MCU_LDSCRIPT := STEMCELL_tinyuf2 + FIRMWARE_FORMAT := uf2 SERIAL_DRIVER := usart @@ -22,4 +21,3 @@ ifeq ($(strip $(STMC_IS)), yes) CONVERT_TO_STEMCELL_I2C_SWAP=yes OPT_DEFS += -DCONVERT_TO_STEMCELL_I2C_SWAP endif - From e4c336915136f385752c3f12004d1c2669cd3ea8 Mon Sep 17 00:00:00 2001 From: Sadek Baroudi Date: Mon, 1 Aug 2022 00:42:12 -0700 Subject: [PATCH 19/20] fixed linting errors --- .../promicro_to_stemcell/_pin_defs.h | 90 +++++++++---------- 1 file changed, 45 insertions(+), 45 deletions(-) diff --git a/platforms/chibios/converters/promicro_to_stemcell/_pin_defs.h b/platforms/chibios/converters/promicro_to_stemcell/_pin_defs.h index 1f26bdebff6a..36a4ce70e286 100644 --- a/platforms/chibios/converters/promicro_to_stemcell/_pin_defs.h +++ b/platforms/chibios/converters/promicro_to_stemcell/_pin_defs.h @@ -1,54 +1,54 @@ // Left side (front) -# ifdef CONVERT_TO_STEMCELL_UART_SWAP -# define D3 PAL_LINE(GPIOA, 3) -# define D2 PAL_LINE(GPIOA, 2) -# ifndef SERIAL_USART_DRIVER -# define SERIAL_USART_DRIVER SD2 -# endif -# else -# define D3 PAL_LINE(GPIOA, 2) -# define D2 PAL_LINE(GPIOA, 3) -# endif -// GND -// GND -# ifdef CONVERT_TO_STEMCELL_I2C_SWAP -# define D1 PAL_LINE(GPIOB, 6) -# define D0 PAL_LINE(GPIOB, 7) -# else -# define D1 PAL_LINE(GPIOB, 7) -# define D0 PAL_LINE(GPIOB, 6) +#ifdef CONVERT_TO_STEMCELL_UART_SWAP +# define D3 PAL_LINE(GPIOA, 3) +# define D2 PAL_LINE(GPIOA, 2) +# ifndef SERIAL_USART_DRIVER +# define SERIAL_USART_DRIVER SD2 # endif +#else +# define D3 PAL_LINE(GPIOA, 2) +# define D2 PAL_LINE(GPIOA, 3) +#endif +// GND +// GND +#ifdef CONVERT_TO_STEMCELL_I2C_SWAP +# define D1 PAL_LINE(GPIOB, 6) +# define D0 PAL_LINE(GPIOB, 7) +#else +# define D1 PAL_LINE(GPIOB, 7) +# define D0 PAL_LINE(GPIOB, 6) +#endif -# define D4 PAL_LINE(GPIOA, 15) -# define C6 PAL_LINE(GPIOB, 3) -# define D7 PAL_LINE(GPIOB, 4) -# define E6 PAL_LINE(GPIOB, 5) -# define B4 PAL_LINE(GPIOB, 8) -# define B5 PAL_LINE(GPIOB, 9) +#define D4 PAL_LINE(GPIOA, 15) +#define C6 PAL_LINE(GPIOB, 3) +#define D7 PAL_LINE(GPIOB, 4) +#define E6 PAL_LINE(GPIOB, 5) +#define B4 PAL_LINE(GPIOB, 8) +#define B5 PAL_LINE(GPIOB, 9) // Right side (front) -// RAW -// GND -// RESET -// VCC -# define F4 PAL_LINE(GPIOB, 10) -# define F5 PAL_LINE(GPIOB, 2) -# define F6 PAL_LINE(GPIOB, 1) -# define F7 PAL_LINE(GPIOB, 0) -# define B1 PAL_LINE(GPIOA, 5) -# define B3 PAL_LINE(GPIOA, 6) -# define B2 PAL_LINE(GPIOA, 7) -# define B6 PAL_LINE(GPIOA, 4) +// RAW +// GND +// RESET +// VCC +#define F4 PAL_LINE(GPIOB, 10) +#define F5 PAL_LINE(GPIOB, 2) +#define F6 PAL_LINE(GPIOB, 1) +#define F7 PAL_LINE(GPIOB, 0) +#define B1 PAL_LINE(GPIOA, 5) +#define B3 PAL_LINE(GPIOA, 6) +#define B2 PAL_LINE(GPIOA, 7) +#define B6 PAL_LINE(GPIOA, 4) // Extra elite-c compatible pinout -# define B7 PAL_LINE(GPIOC, 13) -# define D5 PAL_LINE(GPIOC, 14) -# define C7 PAL_LINE(GPIOC, 15) -# define F1 PAL_LINE(GPIOA, 0) -# define F0 PAL_LINE(GPIOA, 1) +#define B7 PAL_LINE(GPIOC, 13) +#define D5 PAL_LINE(GPIOC, 14) +#define C7 PAL_LINE(GPIOC, 15) +#define F1 PAL_LINE(GPIOA, 0) +#define F0 PAL_LINE(GPIOA, 1) -# define B0 PAL_LINE(GPIOA, 9) // unconnected pin +#define B0 PAL_LINE(GPIOA, 9) // unconnected pin -# define I2C1_SCL_PIN D0 -# define I2C1_SDA_PIN D1 -# define FEE_PAGE_BASE_ADDRESS 0x08008000 +#define I2C1_SCL_PIN D0 +#define I2C1_SDA_PIN D1 +#define FEE_PAGE_BASE_ADDRESS 0x08008000 From 28d42ff396222dadfe5cf9ed6588635406af3525 Mon Sep 17 00:00:00 2001 From: Sadek Baroudi Date: Mon, 1 Aug 2022 20:56:06 -0700 Subject: [PATCH 20/20] Update platforms/chibios/converters/promicro_to_stemcell/_pin_defs.h Co-authored-by: Joel Challis --- .../chibios/converters/promicro_to_stemcell/_pin_defs.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/platforms/chibios/converters/promicro_to_stemcell/_pin_defs.h b/platforms/chibios/converters/promicro_to_stemcell/_pin_defs.h index 36a4ce70e286..9dcc83fd261c 100644 --- a/platforms/chibios/converters/promicro_to_stemcell/_pin_defs.h +++ b/platforms/chibios/converters/promicro_to_stemcell/_pin_defs.h @@ -1,3 +1,8 @@ +// Copyright 2022 QMK +// SPDX-License-Identifier: GPL-2.0-or-later + +#pragma once + // Left side (front) #ifdef CONVERT_TO_STEMCELL_UART_SWAP # define D3 PAL_LINE(GPIOA, 3)