From d0f6f32f4276a88bb3793ce170eaab1d612df5a6 Mon Sep 17 00:00:00 2001 From: Dom Cobley Date: Tue, 17 May 2022 12:46:42 +0100 Subject: [PATCH] kms/vc4_hdmi: Refuse 4096x2160@60 hdmi modes These are no reliable without overclocking. See: https://github.com/raspberrypi/linux/issues/5034 Signed-off-by: Dom Cobley --- drivers/gpu/drm/vc4/vc4_drv.h | 6 ++++++ drivers/gpu/drm/vc4/vc4_hdmi.c | 14 ++++++++++++++ drivers/gpu/drm/vc4/vc4_hvs.c | 5 +++++ 3 files changed, 25 insertions(+) diff --git a/drivers/gpu/drm/vc4/vc4_drv.h b/drivers/gpu/drm/vc4/vc4_drv.h index 0f600a35f09f24..4a8940ca91df34 100644 --- a/drivers/gpu/drm/vc4/vc4_drv.h +++ b/drivers/gpu/drm/vc4/vc4_drv.h @@ -351,6 +351,12 @@ struct vc4_hvs { * available. */ bool vc5_hdmi_enable_scrambling; + + /* + * 4096x2160@60 requires a core overclock to work, so register + * whether that is sufficient. + */ + bool vc5_hdmi_enable_4096by2160; }; struct vc4_plane { diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c index e7a499e733498c..1f7417c07b890e 100644 --- a/drivers/gpu/drm/vc4/vc4_hdmi.c +++ b/drivers/gpu/drm/vc4/vc4_hdmi.c @@ -1821,6 +1821,7 @@ static int vc4_hdmi_encoder_atomic_check(struct drm_encoder *encoder, struct drm_connector *connector = &vc4_hdmi->connector; struct drm_connector_state *old_conn_state = drm_atomic_get_old_connector_state(conn_state->state, connector); struct vc4_hdmi_connector_state *old_vc4_state = conn_state_to_vc4_hdmi_conn_state(old_conn_state); + struct vc4_dev *vc4 = to_vc4_dev(connector->dev); unsigned long long pixel_rate = mode->clock * 1000; unsigned long long tmds_rate; int ret; @@ -1845,6 +1846,12 @@ static int vc4_hdmi_encoder_atomic_check(struct drm_encoder *encoder, return -EINVAL; } + /* 4096x2160@60 is not reliable without overclocking core */ + if (mode->hdisplay > 3840 && mode->vdisplay >= 2160 && + drm_mode_vrefresh(mode) >= 50 && + !vc4->hvs->vc5_hdmi_enable_4096by2160) + return -EINVAL; + /* * The 1440p@60 pixel rate is in the same range than the first * WiFi channel (between 2.4GHz and 2.422GHz with 22MHz @@ -1876,6 +1883,8 @@ vc4_hdmi_encoder_mode_valid(struct drm_encoder *encoder, const struct drm_display_mode *mode) { struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); + const struct drm_connector *connector = &vc4_hdmi->connector; + struct vc4_dev *vc4 = to_vc4_dev(connector->dev); if (vc4_hdmi->variant->unsupported_odd_h_timings && !(mode->flags & DRM_MODE_FLAG_DBLCLK) && @@ -1883,6 +1892,11 @@ vc4_hdmi_encoder_mode_valid(struct drm_encoder *encoder, (mode->hsync_end % 2) || (mode->htotal % 2))) return MODE_H_ILLEGAL; + if (mode->hdisplay > 3840 && mode->vdisplay >= 2160 && + drm_mode_vrefresh(mode) >= 50 && + !vc4->hvs->vc5_hdmi_enable_4096by2160) + return MODE_CLOCK_HIGH; + return vc4_hdmi_encoder_clock_valid(vc4_hdmi, mode->clock * 1000); } diff --git a/drivers/gpu/drm/vc4/vc4_hvs.c b/drivers/gpu/drm/vc4/vc4_hvs.c index 8969d233d7536f..b0acdff916b8dc 100644 --- a/drivers/gpu/drm/vc4/vc4_hvs.c +++ b/drivers/gpu/drm/vc4/vc4_hvs.c @@ -897,6 +897,7 @@ static int vc4_hvs_bind(struct device *dev, struct device *master, void *data) hvs->regset.nregs = ARRAY_SIZE(hvs_regs); if (vc4->is_vc5) { + unsigned long min_rate; unsigned long max_rate; hvs->core_clk = devm_clk_get(&pdev->dev, NULL); @@ -909,6 +910,10 @@ static int vc4_hvs_bind(struct device *dev, struct device *master, void *data) if (max_rate >= 550000000) hvs->vc5_hdmi_enable_scrambling = true; + min_rate = clk_get_min_rate(hvs->core_clk); + if (min_rate >= 600000000) + hvs->vc5_hdmi_enable_4096by2160 = true; + ret = clk_prepare_enable(hvs->core_clk); if (ret) { dev_err(&pdev->dev, "Couldn't enable the core clock\n");