[  833.653743] xhci_hcd 0000:01:00.0: Waiting for status stage event
[  833.655493] xhci_hcd 0000:01:00.0: Waiting for status stage event
[  833.657201] xhci_hcd 0000:01:00.0: Waiting for status stage event
[  833.658990] xhci_hcd 0000:01:00.0: Waiting for status stage event
[  833.660627] xhci_hcd 0000:01:00.0: Waiting for status stage event
[  833.662372] xhci_hcd 0000:01:00.0: Waiting for status stage event
[  833.666250] dvb_usb_v2: 'August DVB-T 205:3-1.4' successfully deinitialized and disconnected
[  833.891260] xhci_hcd 0000:01:00.0: Stalled endpoint for slot 2 ep 0
[  833.891271] xhci_hcd 0000:01:00.0: Cleaning up stalled endpoint ring
[  833.891274] xhci_hcd 0000:01:00.0: Finding endpoint context
[  833.891277] xhci_hcd 0000:01:00.0: Cycle state = 0x1
[  833.891280] xhci_hcd 0000:01:00.0: New dequeue segment = 00000000590395c6 (virtual)
[  833.891283] xhci_hcd 0000:01:00.0: New dequeue pointer = 0x455151990 (DMA)
[  833.891286] xhci_hcd 0000:01:00.0: Queueing new dequeue state
[  833.891291] xhci_hcd 0000:01:00.0: Set TR Deq Ptr cmd, new deq seg = 00000000590395c6 (0x455151000 dma), new deq ptr = 00000000bd4292fb (0x455151990 dma), new cycle = 1
[  833.891293] xhci_hcd 0000:01:00.0: // Ding dong!
[  833.891327] xhci_hcd 0000:01:00.0: Giveback URB 00000000504d9cfe, len = 0, expected = 1, status = -32
[  833.891380] xhci_hcd 0000:01:00.0: Ignoring reset ep completion code of 1
[  833.891448] xhci_hcd 0000:01:00.0: Successful Set TR Deq Ptr cmd, deq = @455151990
[  833.894018] xhci_hcd 0000:01:00.0: Stalled endpoint for slot 2 ep 0
[  833.894027] xhci_hcd 0000:01:00.0: Cleaning up stalled endpoint ring
[  833.894030] xhci_hcd 0000:01:00.0: Finding endpoint context
[  833.894033] xhci_hcd 0000:01:00.0: Cycle state = 0x1
[  833.894036] xhci_hcd 0000:01:00.0: New dequeue segment = 00000000590395c6 (virtual)
[  833.894039] xhci_hcd 0000:01:00.0: New dequeue pointer = 0x4551519c0 (DMA)
[  833.894042] xhci_hcd 0000:01:00.0: Queueing new dequeue state
[  833.894046] xhci_hcd 0000:01:00.0: Set TR Deq Ptr cmd, new deq seg = 00000000590395c6 (0x455151000 dma), new deq ptr = 000000007be6d856 (0x4551519c0 dma), new cycle = 1
[  833.894049] xhci_hcd 0000:01:00.0: // Ding dong!
[  833.894082] xhci_hcd 0000:01:00.0: Giveback URB 00000000504d9cfe, len = 0, expected = 1, status = -32
[  833.894126] xhci_hcd 0000:01:00.0: Ignoring reset ep completion code of 1
[  833.894218] xhci_hcd 0000:01:00.0: Successful Set TR Deq Ptr cmd, deq = @4551519c0
[  833.897020] xhci_hcd 0000:01:00.0: Stalled endpoint for slot 2 ep 0
[  833.897028] xhci_hcd 0000:01:00.0: Cleaning up stalled endpoint ring
[  833.897031] xhci_hcd 0000:01:00.0: Finding endpoint context
[  833.897034] xhci_hcd 0000:01:00.0: Cycle state = 0x1
[  833.897037] xhci_hcd 0000:01:00.0: New dequeue segment = 00000000590395c6 (virtual)
[  833.897041] xhci_hcd 0000:01:00.0: New dequeue pointer = 0x4551519f0 (DMA)
[  833.897043] xhci_hcd 0000:01:00.0: Queueing new dequeue state
[  833.897047] xhci_hcd 0000:01:00.0: Set TR Deq Ptr cmd, new deq seg = 00000000590395c6 (0x455151000 dma), new deq ptr = 00000000f8b5d3db (0x4551519f0 dma), new cycle = 1
[  833.897050] xhci_hcd 0000:01:00.0: // Ding dong!
[  833.897083] xhci_hcd 0000:01:00.0: Giveback URB 00000000504d9cfe, len = 0, expected = 1, status = -32
[  833.897126] xhci_hcd 0000:01:00.0: Ignoring reset ep completion code of 1
[  833.897219] xhci_hcd 0000:01:00.0: Successful Set TR Deq Ptr cmd, deq = @4551519f0
[  833.899756] xhci_hcd 0000:01:00.0: Stalled endpoint for slot 2 ep 0
[  833.899758] xhci_hcd 0000:01:00.0: Cleaning up stalled endpoint ring
[  833.899759] xhci_hcd 0000:01:00.0: Finding endpoint context
[  833.899760] xhci_hcd 0000:01:00.0: Cycle state = 0x1
[  833.899761] xhci_hcd 0000:01:00.0: New dequeue segment = 00000000590395c6 (virtual)
[  833.899761] xhci_hcd 0000:01:00.0: New dequeue pointer = 0x455151a20 (DMA)
[  833.899762] xhci_hcd 0000:01:00.0: Queueing new dequeue state
[  833.899763] xhci_hcd 0000:01:00.0: Set TR Deq Ptr cmd, new deq seg = 00000000590395c6 (0x455151000 dma), new deq ptr = 00000000db7d1efe (0x455151a20 dma), new cycle = 1
[  833.899764] xhci_hcd 0000:01:00.0: // Ding dong!
[  833.899795] xhci_hcd 0000:01:00.0: Giveback URB 00000000504d9cfe, len = 0, expected = 1, status = -32
[  833.899831] xhci_hcd 0000:01:00.0: WARN halted endpoint, queueing URB anyway.
[  833.899877] xhci_hcd 0000:01:00.0: Ignoring reset ep completion code of 1
[  833.899998] xhci_hcd 0000:01:00.0: Successful Set TR Deq Ptr cmd, deq = @455151a20
[  833.902799] xhci_hcd 0000:01:00.0: Stalled endpoint for slot 2 ep 0
[  833.902801] xhci_hcd 0000:01:00.0: Cleaning up stalled endpoint ring
[  833.902802] xhci_hcd 0000:01:00.0: Finding endpoint context
[  833.902802] xhci_hcd 0000:01:00.0: Cycle state = 0x1
[  833.902803] xhci_hcd 0000:01:00.0: New dequeue segment = 00000000590395c6 (virtual)
[  833.902804] xhci_hcd 0000:01:00.0: New dequeue pointer = 0x455151a50 (DMA)
[  833.902804] xhci_hcd 0000:01:00.0: Queueing new dequeue state
[  833.902805] xhci_hcd 0000:01:00.0: Set TR Deq Ptr cmd, new deq seg = 00000000590395c6 (0x455151000 dma), new deq ptr = 000000008020e9d7 (0x455151a50 dma), new cycle = 1
[  833.902806] xhci_hcd 0000:01:00.0: // Ding dong!
[  833.902827] xhci_hcd 0000:01:00.0: Giveback URB 00000000504d9cfe, len = 0, expected = 1, status = -32
[  833.902905] xhci_hcd 0000:01:00.0: Ignoring reset ep completion code of 1
[  833.903064] xhci_hcd 0000:01:00.0: Successful Set TR Deq Ptr cmd, deq = @455151a50
[  833.905625] xhci_hcd 0000:01:00.0: Stalled endpoint for slot 2 ep 0
[  833.905627] xhci_hcd 0000:01:00.0: Cleaning up stalled endpoint ring
[  833.905628] xhci_hcd 0000:01:00.0: Finding endpoint context
[  833.905629] xhci_hcd 0000:01:00.0: Cycle state = 0x1
[  833.905630] xhci_hcd 0000:01:00.0: New dequeue segment = 00000000590395c6 (virtual)
[  833.905631] xhci_hcd 0000:01:00.0: New dequeue pointer = 0x455151a80 (DMA)
[  833.905631] xhci_hcd 0000:01:00.0: Queueing new dequeue state
[  833.905633] xhci_hcd 0000:01:00.0: Set TR Deq Ptr cmd, new deq seg = 00000000590395c6 (0x455151000 dma), new deq ptr = 0000000085d7f91b (0x455151a80 dma), new cycle = 1
[  833.905633] xhci_hcd 0000:01:00.0: // Ding dong!
[  833.905665] xhci_hcd 0000:01:00.0: Giveback URB 00000000504d9cfe, len = 0, expected = 1, status = -32
[  833.905722] xhci_hcd 0000:01:00.0: Ignoring reset ep completion code of 1
[  833.905791] xhci_hcd 0000:01:00.0: Successful Set TR Deq Ptr cmd, deq = @455151a80
[  833.908555] xhci_hcd 0000:01:00.0: Stalled endpoint for slot 2 ep 0
[  833.908557] xhci_hcd 0000:01:00.0: Cleaning up stalled endpoint ring
[  833.908558] xhci_hcd 0000:01:00.0: Finding endpoint context
[  833.908560] xhci_hcd 0000:01:00.0: Cycle state = 0x1
[  833.908563] xhci_hcd 0000:01:00.0: New dequeue segment = 00000000590395c6 (virtual)
[  833.908565] xhci_hcd 0000:01:00.0: New dequeue pointer = 0x455151ab0 (DMA)
[  833.908566] xhci_hcd 0000:01:00.0: Queueing new dequeue state
[  833.908568] xhci_hcd 0000:01:00.0: Set TR Deq Ptr cmd, new deq seg = 00000000590395c6 (0x455151000 dma), new deq ptr = 00000000a4fc2c1f (0x455151ab0 dma), new cycle = 1
[  833.908571] xhci_hcd 0000:01:00.0: // Ding dong!
[  833.908583] xhci_hcd 0000:01:00.0: Giveback URB 00000000504d9cfe, len = 0, expected = 1, status = -32
[  833.908614] xhci_hcd 0000:01:00.0: Ignoring reset ep completion code of 1
[  833.908708] xhci_hcd 0000:01:00.0: Successful Set TR Deq Ptr cmd, deq = @455151ab0
[  833.911241] xhci_hcd 0000:01:00.0: Stalled endpoint for slot 2 ep 0
[  833.911244] xhci_hcd 0000:01:00.0: Cleaning up stalled endpoint ring
[  833.911244] xhci_hcd 0000:01:00.0: Finding endpoint context
[  833.911245] xhci_hcd 0000:01:00.0: Cycle state = 0x1
[  833.911246] xhci_hcd 0000:01:00.0: New dequeue segment = 00000000590395c6 (virtual)
[  833.911247] xhci_hcd 0000:01:00.0: New dequeue pointer = 0x455151ae0 (DMA)
[  833.911248] xhci_hcd 0000:01:00.0: Queueing new dequeue state
[  833.911249] xhci_hcd 0000:01:00.0: Set TR Deq Ptr cmd, new deq seg = 00000000590395c6 (0x455151000 dma), new deq ptr = 0000000005495936 (0x455151ae0 dma), new cycle = 1
[  833.911250] xhci_hcd 0000:01:00.0: // Ding dong!
[  833.911270] xhci_hcd 0000:01:00.0: Giveback URB 00000000504d9cfe, len = 0, expected = 1, status = -32
[  833.911365] xhci_hcd 0000:01:00.0: Ignoring reset ep completion code of 1
[  833.911435] xhci_hcd 0000:01:00.0: Successful Set TR Deq Ptr cmd, deq = @455151ae0
[  835.732578] xhci_hcd 0000:01:00.0: Cancel URB 00000000f79503d6, dev 1.4, ep 0x81, starting at offset 0x45516ae10
[  835.732586] xhci_hcd 0000:01:00.0: // Ding dong!
[  835.732691] xhci_hcd 0000:01:00.0: Stopped on Transfer TRB for slot 2 ep 2
[  835.732699] xhci_hcd 0000:01:00.0: Removing canceled TD starting at 0x45516ae10 (dma).
[  835.732817] xhci_hcd 0000:01:00.0: Cancel URB 000000006637add8, dev 1.4, ep 0x81, starting at offset 0x45516af10
[  835.732824] xhci_hcd 0000:01:00.0: // Ding dong!
[  835.732966] xhci_hcd 0000:01:00.0: Stopped on Transfer TRB for slot 2 ep 2
[  835.732974] xhci_hcd 0000:01:00.0: Removing canceled TD starting at 0x45516af10 (dma).
[  835.733084] xhci_hcd 0000:01:00.0: Cancel URB 000000007faf5e6a, dev 1.4, ep 0x81, starting at offset 0x45900f020
[  835.733091] xhci_hcd 0000:01:00.0: // Ding dong!
[  835.733231] xhci_hcd 0000:01:00.0: Stopped on Transfer TRB for slot 2 ep 2
[  835.733238] xhci_hcd 0000:01:00.0: Removing canceled TD starting at 0x45900f020 (dma).
[  835.733348] xhci_hcd 0000:01:00.0: Cancel URB 00000000a8dabb6c, dev 1.4, ep 0x81, starting at offset 0x45900f120
[  835.733354] xhci_hcd 0000:01:00.0: // Ding dong!
[  835.733500] xhci_hcd 0000:01:00.0: Stopped on Transfer TRB for slot 2 ep 2
[  835.733507] xhci_hcd 0000:01:00.0: Removing canceled TD starting at 0x45900f120 (dma).
[  835.733617] xhci_hcd 0000:01:00.0: Cancel URB 00000000481f4ece, dev 1.4, ep 0x81, starting at offset 0x45900f220
[  835.733624] xhci_hcd 0000:01:00.0: // Ding dong!
[  835.733770] xhci_hcd 0000:01:00.0: Stopped on Transfer TRB for slot 2 ep 2
[  835.733778] xhci_hcd 0000:01:00.0: Removing canceled TD starting at 0x45900f220 (dma).
[  835.733870] xhci_hcd 0000:01:00.0: Cancel URB 00000000a442f37f, dev 1.4, ep 0x81, starting at offset 0x45900f320
[  835.733877] xhci_hcd 0000:01:00.0: // Ding dong!
[  835.734057] xhci_hcd 0000:01:00.0: Stopped on Transfer TRB for slot 2 ep 2
[  835.734065] xhci_hcd 0000:01:00.0: Removing canceled TD starting at 0x45900f320 (dma).
[  835.734179] xhci_hcd 0000:01:00.0: Cancel URB 00000000413c56f0, dev 1.4, ep 0x81, starting at offset 0x45900f420
[  835.734186] xhci_hcd 0000:01:00.0: // Ding dong!
[  835.734335] xhci_hcd 0000:01:00.0: Stopped on Transfer TRB for slot 2 ep 2
[  835.734343] xhci_hcd 0000:01:00.0: Removing canceled TD starting at 0x45900f420 (dma).
[  835.734383] xhci_hcd 0000:01:00.0: Cancel URB 00000000f09cd73d, dev 1.4, ep 0x81, starting at offset 0x45900f520
[  835.734387] xhci_hcd 0000:01:00.0: // Ding dong!
[  835.734487] xhci_hcd 0000:01:00.0: Stopped on Transfer TRB for slot 2 ep 2
[  835.734556] xhci_hcd 0000:01:00.0: Removing canceled TD starting at 0x45900f520 (dma).
[  835.734587] xhci_hcd 0000:01:00.0: Cancel URB 00000000d8948fff, dev 1.4, ep 0x81, starting at offset 0x45900f620
[  835.734590] xhci_hcd 0000:01:00.0: // Ding dong!
[  835.734671] xhci_hcd 0000:01:00.0: Stopped on Transfer TRB for slot 2 ep 2
[  835.734740] xhci_hcd 0000:01:00.0: Removing canceled TD starting at 0x45900f620 (dma).
[  835.734770] xhci_hcd 0000:01:00.0: Cancel URB 000000003c0c0a7b, dev 1.4, ep 0x81, starting at offset 0x45900f720
[  835.734773] xhci_hcd 0000:01:00.0: // Ding dong!
[  835.734914] xhci_hcd 0000:01:00.0: Stopped on Transfer TRB for slot 2 ep 2
[  835.734921] xhci_hcd 0000:01:00.0: Removing canceled TD starting at 0x45900f720 (dma).
[  835.734994] xhci_hcd 0000:01:00.0: Cancel URB 00000000d3173f8f, dev 1.4, ep 0x81, starting at offset 0x45900f820
[  835.734997] xhci_hcd 0000:01:00.0: // Ding dong!
[  835.735093] xhci_hcd 0000:01:00.0: Stopped on Transfer TRB for slot 2 ep 2
[  835.735097] xhci_hcd 0000:01:00.0: Removing canceled TD starting at 0x45900f820 (dma).
[  835.735167] xhci_hcd 0000:01:00.0: Cancel URB 00000000674c43ed, dev 1.4, ep 0x81, starting at offset 0x45516aa10
[  835.735171] xhci_hcd 0000:01:00.0: // Ding dong!
[  835.735250] xhci_hcd 0000:01:00.0: Stopped on Transfer TRB for slot 2 ep 2
[  835.735320] xhci_hcd 0000:01:00.0: Removing canceled TD starting at 0x45516aa10 (dma).
[  835.735322] xhci_hcd 0000:01:00.0: Finding endpoint context
[  835.735325] xhci_hcd 0000:01:00.0: Cycle state = 0x1
[  835.735329] xhci_hcd 0000:01:00.0: New dequeue segment = 00000000fad2ba43 (virtual)
[  835.735331] xhci_hcd 0000:01:00.0: New dequeue pointer = 0x45516ab10 (DMA)
[  835.735336] xhci_hcd 0000:01:00.0: Set TR Deq Ptr cmd, new deq seg = 00000000fad2ba43 (0x45516a000 dma), new deq ptr = 000000001995e1b7 (0x45516ab10 dma), new cycle = 1
[  835.735339] xhci_hcd 0000:01:00.0: // Ding dong!
[  835.735404] xhci_hcd 0000:01:00.0: Successful Set TR Deq Ptr cmd, deq = @45516ab10
[  835.735492] xhci_hcd 0000:01:00.0: Cancel URB 000000008d82fc84, dev 1.4, ep 0x81, starting at offset 0x45516ab10
[  835.735500] xhci_hcd 0000:01:00.0: // Ding dong!
[  835.735581] xhci_hcd 0000:01:00.0: Stopped on Transfer TRB for slot 2 ep 2
[  835.735712] xhci_hcd 0000:01:00.0: Removing canceled TD starting at 0x45516ab10 (dma).
[  835.735716] xhci_hcd 0000:01:00.0: Finding endpoint context
[  835.735720] xhci_hcd 0000:01:00.0: Cycle state = 0x1
[  835.735723] xhci_hcd 0000:01:00.0: New dequeue segment = 00000000fad2ba43 (virtual)
[  835.735726] xhci_hcd 0000:01:00.0: New dequeue pointer = 0x45516ac10 (DMA)
[  835.735731] xhci_hcd 0000:01:00.0: Set TR Deq Ptr cmd, new deq seg = 00000000fad2ba43 (0x45516a000 dma), new deq ptr = 00000000be36de14 (0x45516ac10 dma), new cycle = 1
[  835.735734] xhci_hcd 0000:01:00.0: // Ding dong!
[  835.735798] xhci_hcd 0000:01:00.0: Successful Set TR Deq Ptr cmd, deq = @45516ac10
[  835.735880] xhci_hcd 0000:01:00.0: Cancel URB 0000000097fc90ee, dev 1.4, ep 0x81, starting at offset 0x45516ac10
[  835.735887] xhci_hcd 0000:01:00.0: // Ding dong!
[  835.736030] xhci_hcd 0000:01:00.0: Stopped on Transfer TRB for slot 2 ep 2
[  835.736037] xhci_hcd 0000:01:00.0: Removing canceled TD starting at 0x45516ac10 (dma).
[  835.736040] xhci_hcd 0000:01:00.0: Finding endpoint context
[  835.736043] xhci_hcd 0000:01:00.0: Cycle state = 0x1
[  835.736047] xhci_hcd 0000:01:00.0: New dequeue segment = 00000000fad2ba43 (virtual)
[  835.736050] xhci_hcd 0000:01:00.0: New dequeue pointer = 0x45516ad10 (DMA)
[  835.736055] xhci_hcd 0000:01:00.0: Set TR Deq Ptr cmd, new deq seg = 00000000fad2ba43 (0x45516a000 dma), new deq ptr = 000000003e34a62b (0x45516ad10 dma), new cycle = 1
[  835.736058] xhci_hcd 0000:01:00.0: // Ding dong!
[  835.736129] xhci_hcd 0000:01:00.0: Successful Set TR Deq Ptr cmd, deq = @45516ad10
[  835.736208] xhci_hcd 0000:01:00.0: Cancel URB 00000000397bdb1e, dev 1.4, ep 0x81, starting at offset 0x45516ad10
[  835.736215] xhci_hcd 0000:01:00.0: // Ding dong!
[  835.736311] xhci_hcd 0000:01:00.0: Stopped on Transfer TRB for slot 2 ep 2
[  835.736315] xhci_hcd 0000:01:00.0: Removing canceled TD starting at 0x45516ad10 (dma).
[  835.736318] xhci_hcd 0000:01:00.0: Finding endpoint context
[  835.736320] xhci_hcd 0000:01:00.0: Cycle state = 0x1
[  835.736323] xhci_hcd 0000:01:00.0: New dequeue segment = 00000000fad2ba43 (virtual)
[  835.736326] xhci_hcd 0000:01:00.0: New dequeue pointer = 0x45516ae10 (DMA)
[  835.736330] xhci_hcd 0000:01:00.0: Set TR Deq Ptr cmd, new deq seg = 00000000fad2ba43 (0x45516a000 dma), new deq ptr = 000000002dffe0c3 (0x45516ae10 dma), new cycle = 1
[  835.736332] xhci_hcd 0000:01:00.0: // Ding dong!
[  835.736394] xhci_hcd 0000:01:00.0: Successful Set TR Deq Ptr cmd, deq = @45516ae10
[  835.750894] usb 3-1.4: dvb_usb_v2: found a 'August DVB-T 205' in warm state
[  835.767752] xhci_hcd 0000:01:00.0: // Ding dong!
[  835.767954] xhci_hcd 0000:01:00.0: // Ding dong!
[  835.782117] usb 3-1.4: dvb_usb_v2: will pass the complete MPEG2 transport stream to the software demuxer
[  835.782121] dvbdev: DVB: registering new adapter (August DVB-T 205)
[  835.784467] i2c i2c-3: Added multiplexed i2c bus 4
[  835.784469] rtl2832 3-0010: Realtek RTL2832 successfully attached
[  835.784481] usb 3-1.4: DVB: registering adapter 0 frontend 0 (Realtek RTL2832 (DVB-T))...
[  835.791179] i2c i2c-4: fc0012: Fitipower FC0012 successfully identified
[  835.792165] rtl2832_sdr rtl2832_sdr.0.auto: Registered as swradio0
[  835.792166] rtl2832_sdr rtl2832_sdr.0.auto: Realtek RTL2832 SDR attached
[  835.792167] rtl2832_sdr rtl2832_sdr.0.auto: SDR API is still slightly experimental and functionality changes may follow
[  835.811864] usb 3-1.4: dvb_usb_v2: 'August DVB-T 205' successfully initialized and connected