diff --git a/llvm/include/llvm/IR/IntrinsicsRISCVXTHeadV.td b/llvm/include/llvm/IR/IntrinsicsRISCVXTHeadV.td index b71bf8a3c70b63..9734b8d49b8d92 100644 --- a/llvm/include/llvm/IR/IntrinsicsRISCVXTHeadV.td +++ b/llvm/include/llvm/IR/IntrinsicsRISCVXTHeadV.td @@ -768,6 +768,46 @@ let TargetPrefix = "riscv" in { let VLOperand = 4; } + // For destination vector type is the same as first and second source vector. + // Input: (vector_in, vector_in, int_vector_in, vl) + class XVRGatherVVMasked + : DefaultAttrsIntrinsic<[llvm_anyvector_ty], + [LLVMMatchType<0>, LLVMMatchType<0>, LLVMVectorOfBitcastsToInt<0>, + LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyint_ty], + [IntrNoMem]>, RISCVVIntrinsic { + let VLOperand = 4; + } + + // For destination vector type is the same as first source vector (with mask). + // Second operand is XLen. + // Input: (maskedoff, vector_in, xlen_in, mask, vl) + class XVGatherVXMasked + : DefaultAttrsIntrinsic<[llvm_anyvector_ty], + [LLVMMatchType<0>, LLVMMatchType<0>, llvm_anyint_ty, + LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, LLVMMatchType<1>], + [IntrNoMem]>, RISCVVIntrinsic { + let VLOperand = 4; + } + + // Input: (vector_in, vector_in, scalar_in, vl) + class XVSlideUnMasked + : DefaultAttrsIntrinsic<[llvm_anyvector_ty], + [LLVMMatchType<0>, LLVMMatchType<0>, llvm_anyint_ty, + LLVMMatchType<1>], + [IntrNoMem]>, RISCVVIntrinsic { + let VLOperand = 3; + } + + // Input: (vector_in, vector_in, vector_in/scalar_in, mask, vl) + class XVSlideMasked + : DefaultAttrsIntrinsic<[llvm_anyvector_ty], + [LLVMMatchType<0>, LLVMMatchType<0>, llvm_anyint_ty, + LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, + LLVMMatchType<1>], + [IntrNoMem]>, RISCVVIntrinsic { + let VLOperand = 4; + } + multiclass XVBinaryAAX { def "int_riscv_" # NAME : RISCVBinaryAAXUnMasked; def "int_riscv_" # NAME # "_mask" : XVBinaryAAXMasked; @@ -832,6 +872,21 @@ let TargetPrefix = "riscv" in { def "int_riscv_" # NAME : RISCVUnaryAAUnMaskedRoundingMode; def "int_riscv_" # NAME # "_mask" : XVUnaryAAMaskedRoundingMode; } + + multiclass XVRGatherVV { + def "int_riscv_" # NAME : RISCVRGatherVVUnMasked; + def "int_riscv_" # NAME # "_mask" : XVRGatherVVMasked; + } + + multiclass XVRGatherVX { + def "int_riscv_" # NAME : RISCVGatherVXUnMasked; + def "int_riscv_" # NAME # "_mask" : XVGatherVXMasked; + } + + multiclass XVSlide { + def "int_riscv_" # NAME : XVSlideUnMasked; + def "int_riscv_" # NAME # "_mask" : XVSlideMasked; + } } let TargetPrefix = "riscv" in { @@ -1096,4 +1151,41 @@ let TargetPrefix = "riscv" in { let VLOperand = 2; } + // 17.2. Integer Scalar Move Operations + def int_riscv_th_vmv_x_s : DefaultAttrsIntrinsic<[LLVMVectorElementType<0>], + [llvm_anyint_ty], + [IntrNoMem]>, RISCVVIntrinsic; + def int_riscv_th_vmv_s_x : DefaultAttrsIntrinsic<[llvm_anyint_ty], + [LLVMMatchType<0>, + LLVMVectorElementType<0>, + llvm_anyint_ty], + [IntrNoMem]>, RISCVVIntrinsic { + let VLOperand = 2; + } + + // 17.3. Floating-Point Scalar Move Operations + def int_riscv_th_vfmv_f_s : DefaultAttrsIntrinsic<[LLVMVectorElementType<0>], + [llvm_anyfloat_ty], + [IntrNoMem]>, RISCVVIntrinsic; + def int_riscv_th_vfmv_s_f : DefaultAttrsIntrinsic<[llvm_anyfloat_ty], + [LLVMMatchType<0>, + LLVMVectorElementType<0>, + llvm_anyint_ty], + [IntrNoMem]>, RISCVVIntrinsic { + let VLOperand = 2; + } + + // 17.4. Vector Slide Operations + defm th_vslideup : XVSlide; + defm th_vslidedown : XVSlide; + defm th_vslide1up : XVBinaryAAX; + defm th_vslide1down : XVBinaryAAX; + + // 17.5. Vector Register Gather Operations + defm th_vrgather_vv : XVRGatherVV; + defm th_vrgather_vx : XVRGatherVX; + + // 17.6. Vector Compress Operations + def int_riscv_th_vcompress : RISCVCompress; + } // TargetPrefix = "riscv" diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXTHeadVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXTHeadVPseudos.td index 73d8782e043874..61e670057228fd 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoXTHeadVPseudos.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXTHeadVPseudos.td @@ -1720,6 +1720,23 @@ class XVPseudoTernaryMaskNoPolicyRoundingMode : + Pseudo<(outs RetClass:$rd), + (ins RetClass:$rs3, Op1Class:$rs1, Op2Class:$rs2, + AVL:$vl, ixlenimm:$sew), + []>, + RISCVVPseudo { + let mayLoad = 0; + let mayStore = 0; + let hasSideEffects = 0; + let Constraints = !interleave([Constraint, "$rd = $rs3"], ","); + let HasVLOp = 1; + let HasSEWOp = 1; +} + class XVPseudoTernaryNoMaskNoPolicyRoundingMode { + let VLMul = MInfo.value in { + def "_" # MInfo.MX : XVPseudoTernaryNoMaskNoPolicy; + def "_" # MInfo.MX # "_MASK" : XVPseudoBinaryMaskNoPolicy, + RISCVMaskedPseudo; + } +} + +multiclass XVPseudoVSLDV_VX { + defm _VX : XVPseudoVSLDVNoPolicy; +} + +multiclass XVPseudoVSLDV_VI { + defm _VI : XVPseudoVSLDVNoPolicy; +} + +multiclass XVPseudoVSLD_VX_VI { + foreach m = MxListXTHeadV in { + defvar mx = m.MX; + defvar WriteVISlideX_MX = !cast("WriteVISlideX_" # mx); + defvar WriteVISlideI_MX = !cast("WriteVISlideI_" # mx); + defvar ReadVISlideV_MX = !cast("ReadVISlideV_" # mx); + defvar ReadVISlideX_MX = !cast("ReadVISlideX_" # mx); + + defm "" : XVPseudoVSLDV_VX, + Sched<[WriteVISlideX_MX, ReadVISlideV_MX, ReadVISlideV_MX, + ReadVISlideX_MX, ReadVMask]>; + defm "" : XVPseudoVSLDV_VI, + Sched<[WriteVISlideI_MX, ReadVISlideV_MX, ReadVISlideV_MX, ReadVMask]>; + } +} + +multiclass XVPseudoVSLD1_VX { + foreach m = MxListXTHeadV in { + defvar mx = m.MX; + defvar WriteVISlide1X_MX = !cast("WriteVISlide1X_" # mx); + defvar ReadVISlideV_MX = !cast("ReadVISlideV_" # mx); + defvar ReadVISlideX_MX = !cast("ReadVISlideX_" # mx); + + defm "_VX" : XVPseudoBinary, + Sched<[WriteVISlide1X_MX, ReadVISlideV_MX, ReadVISlideX_MX, ReadVMask]>; + } +} + +multiclass XVPseudoVGTR_VV_VX_VI { + foreach m = MxListXTHeadV in { + defvar mx = m.MX; + defvar WriteVRGatherVX_MX = !cast("WriteVRGatherVX_" # mx); + defvar WriteVRGatherVI_MX = !cast("WriteVRGatherVI_" # mx); + defvar ReadVRGatherVX_data_MX = !cast("ReadVRGatherVX_data_" # mx); + defvar ReadVRGatherVX_index_MX = !cast("ReadVRGatherVX_index_" # mx); + defvar ReadVRGatherVI_data_MX = !cast("ReadVRGatherVI_data_" # mx); + + defm "" : XVPseudoBinaryV_VX, + Sched<[WriteVRGatherVX_MX, ReadVRGatherVX_data_MX, + ReadVRGatherVX_index_MX, ReadVMask]>; + defm "" : XVPseudoBinaryV_VI, + Sched<[WriteVRGatherVI_MX, ReadVRGatherVI_data_MX, ReadVMask]>; + + defvar sews = SchedSEWSet.val; + foreach e = sews in { + defvar WriteVRGatherVV_MX_E = !cast("WriteVRGatherVV_" # mx # "_E" # e); + defvar ReadVRGatherVV_data_MX_E = !cast("ReadVRGatherVV_data_" # mx # "_E" # e); + defvar ReadVRGatherVV_index_MX_E = !cast("ReadVRGatherVV_index_" # mx # "_E" # e); + defm "" : XVPseudoBinaryV_VV, + Sched<[WriteVRGatherVV_MX_E, ReadVRGatherVV_data_MX_E, + ReadVRGatherVV_index_MX_E, ReadVMask]>; + } + } +} + //===----------------------------------------------------------------------===// // Helpers to define the intrinsic patterns for the XTHeadVector extension. //===----------------------------------------------------------------------===// @@ -3308,6 +3400,19 @@ class XVPatTiedBinaryMaskRoundingMode; +multiclass XVPatBinaryV_VV_INT vtilist> { + foreach vti = vtilist in { + defvar ivti = GetIntVTypeInfo.Vti; + let Predicates = GetXVTypePredicates.Predicates in + defm : XVPatBinary; + } +} + multiclass XVPatBinaryV_VV vtilist, bit isSEWAware = 0> { foreach vti = vtilist in @@ -3334,6 +3439,16 @@ multiclass XVPatBinaryV_VV_RM; } +multiclass XVPatBinaryV_VX_INT vtilist> { + foreach vti = vtilist in + let Predicates = GetXVTypePredicates.Predicates in + defm : XVPatBinary; +} + multiclass XVPatBinaryV_VX vtilist, bit isSEWAware = 0> { foreach vti = vtilist in { @@ -4060,6 +4175,16 @@ multiclass XVPatUnaryV_V_RM vtilist> { + foreach vti = vtilist in { + let Predicates = GetXVTypePredicates.Predicates in + def : VPatUnaryAnyMask; + } +} + multiclass XVPatTernaryV_VV_AAXA_RM vtilist> { foreach vti = vtilist in @@ -4081,6 +4206,12 @@ multiclass XVPatTernaryV_VX_AAXA_RM; } +multiclass XVPatBinaryV_VV_VX_VI_INT vtilist, Operand ImmType = simm5> + : XVPatBinaryV_VV_INT, + XVPatBinaryV_VX_INT, + XVPatBinaryV_VI; + multiclass XVPatBinaryV_VV_VX_VI vtilist, Operand ImmType = simm5> : XVPatBinaryV_VV, @@ -4188,6 +4319,31 @@ multiclass XVPatTernaryW_VV_VX_RM, XVPatTernaryW_VX_RM; +multiclass XVPatTernaryV_VI vtilist, Operand Imm_type> { + foreach vti = vtilist in + let Predicates = GetXVTypePredicates.Predicates in + defm : VPatTernary; +} + +multiclass XVPatTernaryV_VX vtilist> { + foreach vti = vtilist in + let Predicates = GetXVTypePredicates.Predicates in + defm : VPatTernary; +} + +multiclass XVPatTernaryV_VX_VI vtilist, Operand Imm_type = simm5> + : XVPatTernaryV_VX, + XVPatTernaryV_VI; + // Can't reuse `VPatTernaryNoMask`, the name of the instruction is different // from `VPatTernaryNoMaskTA`. class XVPatTernaryNoMaskNoTA; -multiclass XVPatTernary; } -multiclass XVPatTernaryRoundingMode(!if(IsFloat, "VF", "VI") # vti.SEW # "M1"); let Predicates = GetXVTypePredicates.Predicates in - defm : XVPatTernary; + defm : XVPatTernaryNoTA; } foreach gvti = !if(IsFloat, GroupFloatXVectors, GroupIntegerXVectors) in { let Predicates = GetXVTypePredicates.Predicates in - defm : XVPatTernary; + defm : XVPatTernaryNoTA; } } @@ -4354,19 +4510,19 @@ multiclass XVPatReductionV_VS_RM(!if(IsFloat, "VF", "VI") # vti.SEW # "M1"); let Predicates = GetXVTypePredicates.Predicates in - defm : XVPatTernaryRoundingMode; + defm : XVPatTernaryNoTARoundingMode; } foreach gvti = !if(IsFloat, GroupFloatXVectors, GroupIntegerXVectors) in { let Predicates = GetXVTypePredicates.Predicates in - defm : XVPatTernaryRoundingMode; + defm : XVPatTernaryNoTARoundingMode; } } @@ -4376,12 +4532,12 @@ multiclass XVPatReductionW_VS(!if(IsFloat, "VF", "VI") # wtiSEW # "M1"); let Predicates = GetXVTypePredicates.Predicates in - defm : XVPatTernary; + defm : XVPatTernaryNoTA; } } } @@ -4392,12 +4548,12 @@ multiclass XVPatReductionW_VS_RM(!if(IsFloat, "VF", "VI") # wtiSEW # "M1"); let Predicates = GetXVTypePredicates.Predicates in - defm : XVPatTernaryRoundingMode; + defm : XVPatTernaryNoTARoundingMode; } } } @@ -5170,4 +5326,128 @@ defm PseudoTH_VID : XVPseudoVID_V; defm : XVPatUnaryV_M<"int_riscv_th_viota", "PseudoTH_VIOTA">; defm : XVPatNullaryV<"int_riscv_th_vid", "PseudoTH_VID">; +//===----------------------------------------------------------------------===// +// 17.2. Integer Scalar Move Operations +//===----------------------------------------------------------------------===// + +let Predicates = [HasVendorXTHeadV], + mayLoad = 0, mayStore = 0, hasSideEffects = 0 in { + foreach m = MxListXTHeadV in { + defvar mx = m.MX; + let VLMul = m.value in { + // `TH_VMV_X_S $rd, $vs` is mapped to `TH_VEXT_X_V $rd, $vs, X0` + let HasSEWOp = 1, BaseInstr = TH_VEXT_X_V in + def "PseudoTH_VMV_X_S" # "_" # mx: + Pseudo<(outs GPR:$rd), (ins m.vrclass:$rs2, ixlenimm:$sew), []>, + Sched<[WriteVIMovVX, ReadVIMovVX]>, + RISCVVPseudo; + let HasVLOp = 1, HasSEWOp = 1, BaseInstr = TH_VMV_S_X, + Constraints = "$rd = $rs1" in + def "PseudoTH_VMV_S_X" # "_" # mx: Pseudo<(outs m.vrclass:$rd), + (ins m.vrclass:$rs1, GPR:$rs2, + AVL:$vl, ixlenimm:$sew), + []>, + Sched<[WriteVIMovXV, ReadVIMovXV, ReadVIMovXX]>, + RISCVVPseudo; + } + } +} + +//===----------------------------------------------------------------------===// +// 17.3. Floating-Point Scalar Move Operations +//===----------------------------------------------------------------------===// + +let Predicates = [HasVendorXTHeadV], + mayLoad = 0, mayStore = 0, hasSideEffects = 0 in { + foreach f = FPListXTHeadV in { + foreach m = f.MxList in { + defvar mx = m.MX; + let VLMul = m.value in { + let HasSEWOp = 1, BaseInstr = TH_VFMV_F_S in + def "PseudoTH_VFMV_" # f.FX # "_S_" # mx : + Pseudo<(outs f.fprclass:$rd), + (ins m.vrclass:$rs2, ixlenimm:$sew), []>, + Sched<[WriteVFMovVF, ReadVFMovVF]>, + RISCVVPseudo; + let HasVLOp = 1, HasSEWOp = 1, BaseInstr = TH_VFMV_S_F, + Constraints = "$rd = $rs1" in + def "PseudoTH_VFMV_S_" # f.FX # "_" # mx : + Pseudo<(outs m.vrclass:$rd), + (ins m.vrclass:$rs1, f.fprclass:$rs2, + AVL:$vl, ixlenimm:$sew), + []>, + Sched<[WriteVFMovFV, ReadVFMovFV, ReadVFMovFX]>, + RISCVVPseudo; + } + } + } +} + +// Patterns + +foreach fvti = AllFloatXVectors in { + let Predicates = GetXVTypePredicates.Predicates in { + def : Pat<(fvti.Vector (int_riscv_th_vfmv_s_f (fvti.Vector fvti.RegClass:$rs1), + (fvti.Scalar fvti.ScalarRegClass:$rs2), VLOpFrag)), + (!cast("PseudoTH_VFMV_S_"#fvti.ScalarSuffix#"_" # + fvti.LMul.MX) + (fvti.Vector $rs1), + (fvti.Scalar fvti.ScalarRegClass:$rs2), + GPR:$vl, fvti.Log2SEW)>; + + def : Pat<(fvti.Vector (int_riscv_th_vfmv_s_f (fvti.Vector fvti.RegClass:$rs1), + (fvti.Scalar (fpimm0)), VLOpFrag)), + (!cast("PseudoTH_VMV_S_X_" # fvti.LMul.MX) + (fvti.Vector $rs1), (XLenVT X0), GPR:$vl, fvti.Log2SEW)>; + } +} + +//===----------------------------------------------------------------------===// +// 17.4. Vector Slide Operations +//===----------------------------------------------------------------------===// +let Predicates = [HasVendorXTHeadV] in { + defm PseudoTH_VSLIDEUP : XVPseudoVSLD_VX_VI; + defm PseudoTH_VSLIDEDOWN : XVPseudoVSLD_VX_VI; + defm PseudoTH_VSLIDE1UP : XVPseudoVSLD1_VX<"@earlyclobber $rd">; + defm PseudoTH_VSLIDE1DOWN : XVPseudoVSLD1_VX; +} + +// Patterns + +defm : XVPatTernaryV_VX_VI<"int_riscv_th_vslideup", "PseudoTH_VSLIDEUP", AllIntegerXVectors, uimm5>; +defm : XVPatTernaryV_VX_VI<"int_riscv_th_vslideup", "PseudoTH_VSLIDEUP", AllFloatXVectors, uimm5>; +defm : XVPatTernaryV_VX_VI<"int_riscv_th_vslidedown", "PseudoTH_VSLIDEDOWN", AllIntegerXVectors, uimm5>; +defm : XVPatTernaryV_VX_VI<"int_riscv_th_vslidedown", "PseudoTH_VSLIDEDOWN", AllFloatXVectors, uimm5>; + +defm : XVPatBinaryV_VX<"int_riscv_th_vslide1up", "PseudoTH_VSLIDE1UP", AllIntegerXVectors>; +defm : XVPatBinaryV_VX<"int_riscv_th_vslide1down", "PseudoTH_VSLIDE1DOWN", AllIntegerXVectors>; + +//===----------------------------------------------------------------------===// +// 17.5. Vector Register Gather Operations +//===----------------------------------------------------------------------===// + +defm PseudoTH_VRGATHER : XVPseudoVGTR_VV_VX_VI; + +// Patterns + +defm : XVPatBinaryV_VV_VX_VI_INT<"int_riscv_th_vrgather", "PseudoTH_VRGATHER", + AllIntegerXVectors, uimm5>; +defm : XVPatBinaryV_VV_VX_VI_INT<"int_riscv_th_vrgather", "PseudoTH_VRGATHER", + AllFloatXVectors, uimm5>; + +//===----------------------------------------------------------------------===// +// 17.6. Vector Compress Operations +//===----------------------------------------------------------------------===// + +defm PseudoTH_VCOMPRESS : VPseudoVCPR_V; + +// Patterns + +defm : XVPatUnaryV_V_AnyMask<"int_riscv_th_vcompress", "PseudoTH_VCOMPRESS", AllIntegerXVectors>; +defm : XVPatUnaryV_V_AnyMask<"int_riscv_th_vcompress", "PseudoTH_VCOMPRESS", AllIntegerXVectors>; +defm : XVPatUnaryV_V_AnyMask<"int_riscv_th_vcompress", "PseudoTH_VCOMPRESS", AllIntegerXVectors>; +defm : XVPatUnaryV_V_AnyMask<"int_riscv_th_vcompress", "PseudoTH_VCOMPRESS", AllFloatXVectors>; +defm : XVPatUnaryV_V_AnyMask<"int_riscv_th_vcompress", "PseudoTH_VCOMPRESS", AllFloatXVectors>; +defm : XVPatUnaryV_V_AnyMask<"int_riscv_th_vcompress", "PseudoTH_VCOMPRESS", AllFloatXVectors>; + include "RISCVInstrInfoXTHeadVVLPatterns.td" diff --git a/llvm/test/CodeGen/RISCV/rvv0p71/vcompress.ll b/llvm/test/CodeGen/RISCV/rvv0p71/vcompress.ll new file mode 100644 index 00000000000000..fc3143872522a9 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/rvv0p71/vcompress.ll @@ -0,0 +1,621 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+xtheadvector,+d \ +; RUN: -verify-machineinstrs | FileCheck %s +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+xtheadvector,+d \ +; RUN: -verify-machineinstrs | FileCheck %s + +declare @llvm.riscv.th.vcompress.nxv8i8( + , + , + , + iXLen); + +define @intrinsic_vcompress_vm_nxv8i8_nxv8i8( %0, %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vcompress_vm_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e8, m1, d1 +; CHECK-NEXT: th.vcompress.vm v8, v9, v0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vcompress.nxv8i8( + %0, + %1, + %2, + iXLen %3) + + ret %a +} + +declare @llvm.riscv.th.vcompress.nxv16i8( + , + , + , + iXLen); + +define @intrinsic_vcompress_vm_nxv16i8_nxv16i8( %0, %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vcompress_vm_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e8, m2, d1 +; CHECK-NEXT: th.vcompress.vm v8, v10, v0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vcompress.nxv16i8( + %0, + %1, + %2, + iXLen %3) + + ret %a +} + +declare @llvm.riscv.th.vcompress.nxv32i8( + , + , + , + iXLen); + +define @intrinsic_vcompress_vm_nxv32i8_nxv32i8( %0, %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vcompress_vm_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e8, m4, d1 +; CHECK-NEXT: th.vcompress.vm v8, v12, v0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vcompress.nxv32i8( + %0, + %1, + %2, + iXLen %3) + + ret %a +} + +declare @llvm.riscv.th.vcompress.nxv64i8( + , + , + , + iXLen); + +define @intrinsic_vcompress_vm_nxv64i8_nxv64i8( %0, %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vcompress_vm_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e8, m8, d1 +; CHECK-NEXT: th.vcompress.vm v8, v16, v0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vcompress.nxv64i8( + %0, + %1, + %2, + iXLen %3) + + ret %a +} + +declare @llvm.riscv.th.vcompress.nxv4i16( + , + , + , + iXLen); + +define @intrinsic_vcompress_vm_nxv4i16_nxv4i16( %0, %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vcompress_vm_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e16, m1, d1 +; CHECK-NEXT: th.vcompress.vm v8, v9, v0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vcompress.nxv4i16( + %0, + %1, + %2, + iXLen %3) + + ret %a +} + +declare @llvm.riscv.th.vcompress.nxv8i16( + , + , + , + iXLen); + +define @intrinsic_vcompress_vm_nxv8i16_nxv8i16( %0, %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vcompress_vm_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e16, m2, d1 +; CHECK-NEXT: th.vcompress.vm v8, v10, v0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vcompress.nxv8i16( + %0, + %1, + %2, + iXLen %3) + + ret %a +} + +declare @llvm.riscv.th.vcompress.nxv16i16( + , + , + , + iXLen); + +define @intrinsic_vcompress_vm_nxv16i16_nxv16i16( %0, %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vcompress_vm_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e16, m4, d1 +; CHECK-NEXT: th.vcompress.vm v8, v12, v0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vcompress.nxv16i16( + %0, + %1, + %2, + iXLen %3) + + ret %a +} + +declare @llvm.riscv.th.vcompress.nxv32i16( + , + , + , + iXLen); + +define @intrinsic_vcompress_vm_nxv32i16_nxv32i16( %0, %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vcompress_vm_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e16, m8, d1 +; CHECK-NEXT: th.vcompress.vm v8, v16, v0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vcompress.nxv32i16( + %0, + %1, + %2, + iXLen %3) + + ret %a +} + +declare @llvm.riscv.th.vcompress.nxv2i32( + , + , + , + iXLen); + +define @intrinsic_vcompress_vm_nxv2i32_nxv2i32( %0, %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vcompress_vm_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e32, m1, d1 +; CHECK-NEXT: th.vcompress.vm v8, v9, v0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vcompress.nxv2i32( + %0, + %1, + %2, + iXLen %3) + + ret %a +} + +declare @llvm.riscv.th.vcompress.nxv4i32( + , + , + , + iXLen); + +define @intrinsic_vcompress_vm_nxv4i32_nxv4i32( %0, %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vcompress_vm_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e32, m2, d1 +; CHECK-NEXT: th.vcompress.vm v8, v10, v0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vcompress.nxv4i32( + %0, + %1, + %2, + iXLen %3) + + ret %a +} + +declare @llvm.riscv.th.vcompress.nxv8i32( + , + , + , + iXLen); + +define @intrinsic_vcompress_vm_nxv8i32_nxv8i32( %0, %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vcompress_vm_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e32, m4, d1 +; CHECK-NEXT: th.vcompress.vm v8, v12, v0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vcompress.nxv8i32( + %0, + %1, + %2, + iXLen %3) + + ret %a +} + +declare @llvm.riscv.th.vcompress.nxv16i32( + , + , + , + iXLen); + +define @intrinsic_vcompress_vm_nxv16i32_nxv16i32( %0, %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vcompress_vm_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e32, m8, d1 +; CHECK-NEXT: th.vcompress.vm v8, v16, v0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vcompress.nxv16i32( + %0, + %1, + %2, + iXLen %3) + + ret %a +} + +declare @llvm.riscv.th.vcompress.nxv1i64( + , + , + , + iXLen); + +define @intrinsic_vcompress_vm_nxv1i64_nxv1i64( %0, %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vcompress_vm_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e64, m1, d1 +; CHECK-NEXT: th.vcompress.vm v8, v9, v0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vcompress.nxv1i64( + %0, + %1, + %2, + iXLen %3) + + ret %a +} + +declare @llvm.riscv.th.vcompress.nxv2i64( + , + , + , + iXLen); + +define @intrinsic_vcompress_vm_nxv2i64_nxv2i64( %0, %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vcompress_vm_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e64, m2, d1 +; CHECK-NEXT: th.vcompress.vm v8, v10, v0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vcompress.nxv2i64( + %0, + %1, + %2, + iXLen %3) + + ret %a +} + +declare @llvm.riscv.th.vcompress.nxv4i64( + , + , + , + iXLen); + +define @intrinsic_vcompress_vm_nxv4i64_nxv4i64( %0, %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vcompress_vm_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e64, m4, d1 +; CHECK-NEXT: th.vcompress.vm v8, v12, v0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vcompress.nxv4i64( + %0, + %1, + %2, + iXLen %3) + + ret %a +} + +declare @llvm.riscv.th.vcompress.nxv8i64( + , + , + , + iXLen); + +define @intrinsic_vcompress_vm_nxv8i64_nxv8i64( %0, %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vcompress_vm_nxv8i64_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e64, m8, d1 +; CHECK-NEXT: th.vcompress.vm v8, v16, v0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vcompress.nxv8i64( + %0, + %1, + %2, + iXLen %3) + + ret %a +} + +declare @llvm.riscv.th.vcompress.nxv4f16( + , + , + , + iXLen); + +define @intrinsic_vcompress_vm_nxv4f16_nxv4f16( %0, %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vcompress_vm_nxv4f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e16, m1, d1 +; CHECK-NEXT: th.vcompress.vm v8, v9, v0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vcompress.nxv4f16( + %0, + %1, + %2, + iXLen %3) + + ret %a +} + +declare @llvm.riscv.th.vcompress.nxv8f16( + , + , + , + iXLen); + +define @intrinsic_vcompress_vm_nxv8f16_nxv8f16( %0, %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vcompress_vm_nxv8f16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e16, m2, d1 +; CHECK-NEXT: th.vcompress.vm v8, v10, v0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vcompress.nxv8f16( + %0, + %1, + %2, + iXLen %3) + + ret %a +} + +declare @llvm.riscv.th.vcompress.nxv16f16( + , + , + , + iXLen); + +define @intrinsic_vcompress_vm_nxv16f16_nxv16f16( %0, %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vcompress_vm_nxv16f16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e16, m4, d1 +; CHECK-NEXT: th.vcompress.vm v8, v12, v0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vcompress.nxv16f16( + %0, + %1, + %2, + iXLen %3) + + ret %a +} + +declare @llvm.riscv.th.vcompress.nxv32f16( + , + , + , + iXLen); + +define @intrinsic_vcompress_vm_nxv32f16_nxv32f16( %0, %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vcompress_vm_nxv32f16_nxv32f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e16, m8, d1 +; CHECK-NEXT: th.vcompress.vm v8, v16, v0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vcompress.nxv32f16( + %0, + %1, + %2, + iXLen %3) + + ret %a +} + +declare @llvm.riscv.th.vcompress.nxv2f32( + , + , + , + iXLen); + +define @intrinsic_vcompress_vm_nxv2f32_nxv2f32( %0, %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vcompress_vm_nxv2f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e32, m1, d1 +; CHECK-NEXT: th.vcompress.vm v8, v9, v0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vcompress.nxv2f32( + %0, + %1, + %2, + iXLen %3) + + ret %a +} + +declare @llvm.riscv.th.vcompress.nxv4f32( + , + , + , + iXLen); + +define @intrinsic_vcompress_vm_nxv4f32_nxv4f32( %0, %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vcompress_vm_nxv4f32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e32, m2, d1 +; CHECK-NEXT: th.vcompress.vm v8, v10, v0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vcompress.nxv4f32( + %0, + %1, + %2, + iXLen %3) + + ret %a +} + +declare @llvm.riscv.th.vcompress.nxv8f32( + , + , + , + iXLen); + +define @intrinsic_vcompress_vm_nxv8f32_nxv8f32( %0, %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vcompress_vm_nxv8f32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e32, m4, d1 +; CHECK-NEXT: th.vcompress.vm v8, v12, v0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vcompress.nxv8f32( + %0, + %1, + %2, + iXLen %3) + + ret %a +} + +declare @llvm.riscv.th.vcompress.nxv16f32( + , + , + , + iXLen); + +define @intrinsic_vcompress_vm_nxv16f32_nxv16f32( %0, %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vcompress_vm_nxv16f32_nxv16f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e32, m8, d1 +; CHECK-NEXT: th.vcompress.vm v8, v16, v0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vcompress.nxv16f32( + %0, + %1, + %2, + iXLen %3) + + ret %a +} + +declare @llvm.riscv.th.vcompress.nxv1f64( + , + , + , + iXLen); + +define @intrinsic_vcompress_vm_nxv1f64_nxv1f64( %0, %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vcompress_vm_nxv1f64_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e64, m1, d1 +; CHECK-NEXT: th.vcompress.vm v8, v9, v0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vcompress.nxv1f64( + %0, + %1, + %2, + iXLen %3) + + ret %a +} + +declare @llvm.riscv.th.vcompress.nxv2f64( + , + , + , + iXLen); + +define @intrinsic_vcompress_vm_nxv2f64_nxv2f64( %0, %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vcompress_vm_nxv2f64_nxv2f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e64, m2, d1 +; CHECK-NEXT: th.vcompress.vm v8, v10, v0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vcompress.nxv2f64( + %0, + %1, + %2, + iXLen %3) + + ret %a +} + +declare @llvm.riscv.th.vcompress.nxv4f64( + , + , + , + iXLen); + +define @intrinsic_vcompress_vm_nxv4f64_nxv4f64( %0, %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vcompress_vm_nxv4f64_nxv4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e64, m4, d1 +; CHECK-NEXT: th.vcompress.vm v8, v12, v0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vcompress.nxv4f64( + %0, + %1, + %2, + iXLen %3) + + ret %a +} + +declare @llvm.riscv.th.vcompress.nxv8f64( + , + , + , + iXLen); + +define @intrinsic_vcompress_vm_nxv8f64_nxv8f64( %0, %1, %2, iXLen %3) nounwind { +; CHECK-LABEL: intrinsic_vcompress_vm_nxv8f64_nxv8f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e64, m8, d1 +; CHECK-NEXT: th.vcompress.vm v8, v16, v0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vcompress.nxv8f64( + %0, + %1, + %2, + iXLen %3) + + ret %a +} diff --git a/llvm/test/CodeGen/RISCV/rvv0p71/vrgather-rv32.ll b/llvm/test/CodeGen/RISCV/rvv0p71/vrgather-rv32.ll new file mode 100644 index 00000000000000..0da89d8087528f --- /dev/null +++ b/llvm/test/CodeGen/RISCV/rvv0p71/vrgather-rv32.ll @@ -0,0 +1,3105 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=riscv32 -mattr=+xtheadvector,+d -verify-machineinstrs \ +; RUN: < %s | FileCheck %s + +declare @llvm.riscv.th.vrgather.vv.nxv8i8.i32( + , + , + , + i32); + +define @intrinsic_vrgather_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e8, m1, d1 +; CHECK-NEXT: th.vrgather.vv v10, v8, v9 +; CHECK-NEXT: th.vmv.v.v v8, v10 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vv.nxv8i8.i32( + undef, + %0, + %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vv.mask.nxv8i8.i32( + , + , + , + , + i32); + +define @intrinsic_vrgather_mask_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e8, m1, d1 +; CHECK-NEXT: th.vrgather.vv v8, v9, v10, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vv.mask.nxv8i8.i32( + %0, + %1, + %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vv.nxv16i8.i32( + , + , + , + i32); + +define @intrinsic_vrgather_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e8, m2, d1 +; CHECK-NEXT: th.vrgather.vv v12, v8, v10 +; CHECK-NEXT: th.vmv.v.v v8, v12 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vv.nxv16i8.i32( + undef, + %0, + %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vv.mask.nxv16i8.i32( + , + , + , + , + i32); + +define @intrinsic_vrgather_mask_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e8, m2, d1 +; CHECK-NEXT: th.vrgather.vv v8, v10, v12, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vv.mask.nxv16i8.i32( + %0, + %1, + %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vv.nxv32i8.i32( + , + , + , + i32); + +define @intrinsic_vrgather_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e8, m4, d1 +; CHECK-NEXT: th.vrgather.vv v16, v8, v12 +; CHECK-NEXT: th.vmv.v.v v8, v16 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vv.nxv32i8.i32( + undef, + %0, + %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vv.mask.nxv32i8.i32( + , + , + , + , + i32); + +define @intrinsic_vrgather_mask_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e8, m4, d1 +; CHECK-NEXT: th.vrgather.vv v8, v12, v16, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vv.mask.nxv32i8.i32( + %0, + %1, + %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vv.nxv64i8.i32( + , + , + , + i32); + +define @intrinsic_vrgather_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e8, m8, d1 +; CHECK-NEXT: th.vrgather.vv v24, v8, v16 +; CHECK-NEXT: th.vmv.v.v v8, v24 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vv.nxv64i8.i32( + undef, + %0, + %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vv.mask.nxv64i8.i32( + , + , + , + , + i32); + +define @intrinsic_vrgather_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m8, d1 +; CHECK-NEXT: th.vle.v v24, (a0) +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e8, m8, d1 +; CHECK-NEXT: th.vrgather.vv v8, v16, v24, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vv.mask.nxv64i8.i32( + %0, + %1, + %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vv.nxv4i16.i32( + , + , + , + i32); + +define @intrinsic_vrgather_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e16, m1, d1 +; CHECK-NEXT: th.vrgather.vv v10, v8, v9 +; CHECK-NEXT: th.vmv.v.v v8, v10 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vv.nxv4i16.i32( + undef, + %0, + %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vv.mask.nxv4i16.i32( + , + , + , + , + i32); + +define @intrinsic_vrgather_mask_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e16, m1, d1 +; CHECK-NEXT: th.vrgather.vv v8, v9, v10, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vv.mask.nxv4i16.i32( + %0, + %1, + %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vv.nxv8i16.i32( + , + , + , + i32); + +define @intrinsic_vrgather_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e16, m2, d1 +; CHECK-NEXT: th.vrgather.vv v12, v8, v10 +; CHECK-NEXT: th.vmv.v.v v8, v12 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vv.nxv8i16.i32( + undef, + %0, + %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vv.mask.nxv8i16.i32( + , + , + , + , + i32); + +define @intrinsic_vrgather_mask_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e16, m2, d1 +; CHECK-NEXT: th.vrgather.vv v8, v10, v12, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vv.mask.nxv8i16.i32( + %0, + %1, + %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vv.nxv16i16.i32( + , + , + , + i32); + +define @intrinsic_vrgather_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e16, m4, d1 +; CHECK-NEXT: th.vrgather.vv v16, v8, v12 +; CHECK-NEXT: th.vmv.v.v v8, v16 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vv.nxv16i16.i32( + undef, + %0, + %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vv.mask.nxv16i16.i32( + , + , + , + , + i32); + +define @intrinsic_vrgather_mask_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e16, m4, d1 +; CHECK-NEXT: th.vrgather.vv v8, v12, v16, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vv.mask.nxv16i16.i32( + %0, + %1, + %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vv.nxv32i16.i32( + , + , + , + i32); + +define @intrinsic_vrgather_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e16, m8, d1 +; CHECK-NEXT: th.vrgather.vv v24, v8, v16 +; CHECK-NEXT: th.vmv.v.v v8, v24 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vv.nxv32i16.i32( + undef, + %0, + %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vv.mask.nxv32i16.i32( + , + , + , + , + i32); + +define @intrinsic_vrgather_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e16, m8, d1 +; CHECK-NEXT: th.vle.v v24, (a0) +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e16, m8, d1 +; CHECK-NEXT: th.vrgather.vv v8, v16, v24, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vv.mask.nxv32i16.i32( + %0, + %1, + %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vv.nxv2i32.i32( + , + , + , + i32); + +define @intrinsic_vrgather_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e32, m1, d1 +; CHECK-NEXT: th.vrgather.vv v10, v8, v9 +; CHECK-NEXT: th.vmv.v.v v8, v10 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vv.nxv2i32.i32( + undef, + %0, + %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vv.mask.nxv2i32.i32( + , + , + , + , + i32); + +define @intrinsic_vrgather_mask_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e32, m1, d1 +; CHECK-NEXT: th.vrgather.vv v8, v9, v10, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vv.mask.nxv2i32.i32( + %0, + %1, + %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vv.nxv4i32.i32( + , + , + , + i32); + +define @intrinsic_vrgather_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e32, m2, d1 +; CHECK-NEXT: th.vrgather.vv v12, v8, v10 +; CHECK-NEXT: th.vmv.v.v v8, v12 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vv.nxv4i32.i32( + undef, + %0, + %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vv.mask.nxv4i32.i32( + , + , + , + , + i32); + +define @intrinsic_vrgather_mask_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e32, m2, d1 +; CHECK-NEXT: th.vrgather.vv v8, v10, v12, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vv.mask.nxv4i32.i32( + %0, + %1, + %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vv.nxv8i32.i32( + , + , + , + i32); + +define @intrinsic_vrgather_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e32, m4, d1 +; CHECK-NEXT: th.vrgather.vv v16, v8, v12 +; CHECK-NEXT: th.vmv.v.v v8, v16 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vv.nxv8i32.i32( + undef, + %0, + %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vv.mask.nxv8i32.i32( + , + , + , + , + i32); + +define @intrinsic_vrgather_mask_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e32, m4, d1 +; CHECK-NEXT: th.vrgather.vv v8, v12, v16, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vv.mask.nxv8i32.i32( + %0, + %1, + %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vv.nxv16i32.i32( + , + , + , + i32); + +define @intrinsic_vrgather_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e32, m8, d1 +; CHECK-NEXT: th.vrgather.vv v24, v8, v16 +; CHECK-NEXT: th.vmv.v.v v8, v24 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vv.nxv16i32.i32( + undef, + %0, + %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vv.mask.nxv16i32.i32( + , + , + , + , + i32); + +define @intrinsic_vrgather_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e32, m8, d1 +; CHECK-NEXT: th.vle.v v24, (a0) +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m8, d1 +; CHECK-NEXT: th.vrgather.vv v8, v16, v24, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vv.mask.nxv16i32.i32( + %0, + %1, + %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vv.nxv4f16.i32( + , + , + , + i32); + +define @intrinsic_vrgather_vv_nxv4f16_nxv4f16_nxv4i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vv_nxv4f16_nxv4f16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e16, m1, d1 +; CHECK-NEXT: th.vrgather.vv v10, v8, v9 +; CHECK-NEXT: th.vmv.v.v v8, v10 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vv.nxv4f16.i32( + undef, + %0, + %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vv.mask.nxv4f16.i32( + , + , + , + , + i32); + +define @intrinsic_vrgather_mask_vv_nxv4f16_nxv4f16_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv4f16_nxv4f16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e16, m1, d1 +; CHECK-NEXT: th.vrgather.vv v8, v9, v10, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vv.mask.nxv4f16.i32( + %0, + %1, + %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vv.nxv8f16.i32( + , + , + , + i32); + +define @intrinsic_vrgather_vv_nxv8f16_nxv8f16_nxv8i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vv_nxv8f16_nxv8f16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e16, m2, d1 +; CHECK-NEXT: th.vrgather.vv v12, v8, v10 +; CHECK-NEXT: th.vmv.v.v v8, v12 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vv.nxv8f16.i32( + undef, + %0, + %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vv.mask.nxv8f16.i32( + , + , + , + , + i32); + +define @intrinsic_vrgather_mask_vv_nxv8f16_nxv8f16_nxv8i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv8f16_nxv8f16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e16, m2, d1 +; CHECK-NEXT: th.vrgather.vv v8, v10, v12, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vv.mask.nxv8f16.i32( + %0, + %1, + %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vv.nxv16f16.i32( + , + , + , + i32); + +define @intrinsic_vrgather_vv_nxv16f16_nxv16f16_nxv16i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vv_nxv16f16_nxv16f16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e16, m4, d1 +; CHECK-NEXT: th.vrgather.vv v16, v8, v12 +; CHECK-NEXT: th.vmv.v.v v8, v16 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vv.nxv16f16.i32( + undef, + %0, + %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vv.mask.nxv16f16.i32( + , + , + , + , + i32); + +define @intrinsic_vrgather_mask_vv_nxv16f16_nxv16f16_nxv16i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv16f16_nxv16f16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e16, m4, d1 +; CHECK-NEXT: th.vrgather.vv v8, v12, v16, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vv.mask.nxv16f16.i32( + %0, + %1, + %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vv.nxv32f16.i32( + , + , + , + i32); + +define @intrinsic_vrgather_vv_nxv32f16_nxv32f16_nxv32i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vv_nxv32f16_nxv32f16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e16, m8, d1 +; CHECK-NEXT: th.vrgather.vv v24, v8, v16 +; CHECK-NEXT: th.vmv.v.v v8, v24 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vv.nxv32f16.i32( + undef, + %0, + %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vv.mask.nxv32f16.i32( + , + , + , + , + i32); + +define @intrinsic_vrgather_mask_vv_nxv32f16_nxv32f16_nxv32i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv32f16_nxv32f16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e16, m8, d1 +; CHECK-NEXT: th.vle.v v24, (a0) +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e16, m8, d1 +; CHECK-NEXT: th.vrgather.vv v8, v16, v24, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vv.mask.nxv32f16.i32( + %0, + %1, + %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vv.nxv2f32.i32( + , + , + , + i32); + +define @intrinsic_vrgather_vv_nxv2f32_nxv2f32_nxv2i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vv_nxv2f32_nxv2f32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e32, m1, d1 +; CHECK-NEXT: th.vrgather.vv v10, v8, v9 +; CHECK-NEXT: th.vmv.v.v v8, v10 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vv.nxv2f32.i32( + undef, + %0, + %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vv.mask.nxv2f32.i32( + , + , + , + , + i32); + +define @intrinsic_vrgather_mask_vv_nxv2f32_nxv2f32_nxv2i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv2f32_nxv2f32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e32, m1, d1 +; CHECK-NEXT: th.vrgather.vv v8, v9, v10, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vv.mask.nxv2f32.i32( + %0, + %1, + %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vv.nxv4f32.i32( + , + , + , + i32); + +define @intrinsic_vrgather_vv_nxv4f32_nxv4f32_nxv4i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vv_nxv4f32_nxv4f32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e32, m2, d1 +; CHECK-NEXT: th.vrgather.vv v12, v8, v10 +; CHECK-NEXT: th.vmv.v.v v8, v12 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vv.nxv4f32.i32( + undef, + %0, + %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vv.mask.nxv4f32.i32( + , + , + , + , + i32); + +define @intrinsic_vrgather_mask_vv_nxv4f32_nxv4f32_nxv4i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv4f32_nxv4f32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e32, m2, d1 +; CHECK-NEXT: th.vrgather.vv v8, v10, v12, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vv.mask.nxv4f32.i32( + %0, + %1, + %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vv.nxv8f32.i32( + , + , + , + i32); + +define @intrinsic_vrgather_vv_nxv8f32_nxv8f32_nxv8i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vv_nxv8f32_nxv8f32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e32, m4, d1 +; CHECK-NEXT: th.vrgather.vv v16, v8, v12 +; CHECK-NEXT: th.vmv.v.v v8, v16 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vv.nxv8f32.i32( + undef, + %0, + %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vv.mask.nxv8f32.i32( + , + , + , + , + i32); + +define @intrinsic_vrgather_mask_vv_nxv8f32_nxv8f32_nxv8i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv8f32_nxv8f32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e32, m4, d1 +; CHECK-NEXT: th.vrgather.vv v8, v12, v16, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vv.mask.nxv8f32.i32( + %0, + %1, + %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vv.nxv16f32.i32( + , + , + , + i32); + +define @intrinsic_vrgather_vv_nxv16f32_nxv16f32_nxv16i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vv_nxv16f32_nxv16f32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e32, m8, d1 +; CHECK-NEXT: th.vrgather.vv v24, v8, v16 +; CHECK-NEXT: th.vmv.v.v v8, v24 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vv.nxv16f32.i32( + undef, + %0, + %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vv.mask.nxv16f32.i32( + , + , + , + , + i32); + +define @intrinsic_vrgather_mask_vv_nxv16f32_nxv16f32_nxv16i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv16f32_nxv16f32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e32, m8, d1 +; CHECK-NEXT: th.vle.v v24, (a0) +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m8, d1 +; CHECK-NEXT: th.vrgather.vv v8, v16, v24, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vv.mask.nxv16f32.i32( + %0, + %1, + %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vv.nxv1f64.i32( + , + , + , + i32); + +define @intrinsic_vrgather_vv_nxv1f64_nxv1f64_nxv1i64( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vv_nxv1f64_nxv1f64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e64, m1, d1 +; CHECK-NEXT: th.vrgather.vv v10, v8, v9 +; CHECK-NEXT: th.vmv.v.v v8, v10 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vv.nxv1f64.i32( + undef, + %0, + %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vv.mask.nxv1f64.i32( + , + , + , + , + i32); + +define @intrinsic_vrgather_mask_vv_nxv1f64_nxv1f64_nxv1i64( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv1f64_nxv1f64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e64, m1, d1 +; CHECK-NEXT: th.vrgather.vv v8, v9, v10, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vv.mask.nxv1f64.i32( + %0, + %1, + %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vv.nxv2f64.i32( + , + , + , + i32); + +define @intrinsic_vrgather_vv_nxv2f64_nxv2f64_nxv2i64( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vv_nxv2f64_nxv2f64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e64, m2, d1 +; CHECK-NEXT: th.vrgather.vv v12, v8, v10 +; CHECK-NEXT: th.vmv.v.v v8, v12 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vv.nxv2f64.i32( + undef, + %0, + %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vv.mask.nxv2f64.i32( + , + , + , + , + i32); + +define @intrinsic_vrgather_mask_vv_nxv2f64_nxv2f64_nxv2i64( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv2f64_nxv2f64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e64, m2, d1 +; CHECK-NEXT: th.vrgather.vv v8, v10, v12, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vv.mask.nxv2f64.i32( + %0, + %1, + %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vv.nxv4f64.i32( + , + , + , + i32); + +define @intrinsic_vrgather_vv_nxv4f64_nxv4f64_nxv4i64( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vv_nxv4f64_nxv4f64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e64, m4, d1 +; CHECK-NEXT: th.vrgather.vv v16, v8, v12 +; CHECK-NEXT: th.vmv.v.v v8, v16 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vv.nxv4f64.i32( + undef, + %0, + %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vv.mask.nxv4f64.i32( + , + , + , + , + i32); + +define @intrinsic_vrgather_mask_vv_nxv4f64_nxv4f64_nxv4i64( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv4f64_nxv4f64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e64, m4, d1 +; CHECK-NEXT: th.vrgather.vv v8, v12, v16, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vv.mask.nxv4f64.i32( + %0, + %1, + %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vv.nxv8f64.i32( + , + , + , + i32); + +define @intrinsic_vrgather_vv_nxv8f64_nxv8f64_nxv8i64( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vv_nxv8f64_nxv8f64_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e64, m8, d1 +; CHECK-NEXT: th.vrgather.vv v24, v8, v16 +; CHECK-NEXT: th.vmv.v.v v8, v24 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vv.nxv8f64.i32( + undef, + %0, + %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vv.mask.nxv8f64.i32( + , + , + , + , + i32); + +define @intrinsic_vrgather_mask_vv_nxv8f64_nxv8f64_nxv8i64( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv8f64_nxv8f64_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e64, m8, d1 +; CHECK-NEXT: th.vle.v v24, (a0) +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m8, d1 +; CHECK-NEXT: th.vrgather.vv v8, v16, v24, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vv.mask.nxv8f64.i32( + %0, + %1, + %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vx.nxv8i8.i32( + , + , + i32, + i32); + +define @intrinsic_vrgather_vx_nxv8i8_nxv8i8_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vx_nxv8i8_nxv8i8_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e8, m1, d1 +; CHECK-NEXT: th.vrgather.vx v9, v8, a0 +; CHECK-NEXT: th.vmv.v.v v8, v9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.nxv8i8.i32( + undef, + %0, + i32 %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vx.mask.nxv8i8.i32( + , + , + i32, + , + i32); + +define @intrinsic_vrgather_mask_vx_nxv8i8_nxv8i8_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv8i8_nxv8i8_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e8, m1, d1 +; CHECK-NEXT: th.vrgather.vx v8, v9, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.mask.nxv8i8.i32( + %0, + %1, + i32 %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vx.nxv16i8.i32( + , + , + i32, + i32); + +define @intrinsic_vrgather_vx_nxv16i8_nxv16i8_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vx_nxv16i8_nxv16i8_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e8, m2, d1 +; CHECK-NEXT: th.vrgather.vx v10, v8, a0 +; CHECK-NEXT: th.vmv.v.v v8, v10 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.nxv16i8.i32( + undef, + %0, + i32 %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vx.mask.nxv16i8.i32( + , + , + i32, + , + i32); + +define @intrinsic_vrgather_mask_vx_nxv16i8_nxv16i8_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv16i8_nxv16i8_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e8, m2, d1 +; CHECK-NEXT: th.vrgather.vx v8, v10, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.mask.nxv16i8.i32( + %0, + %1, + i32 %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vx.nxv32i8.i32( + , + , + i32, + i32); + +define @intrinsic_vrgather_vx_nxv32i8_nxv32i8_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vx_nxv32i8_nxv32i8_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e8, m4, d1 +; CHECK-NEXT: th.vrgather.vx v12, v8, a0 +; CHECK-NEXT: th.vmv.v.v v8, v12 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.nxv32i8.i32( + undef, + %0, + i32 %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vx.mask.nxv32i8.i32( + , + , + i32, + , + i32); + +define @intrinsic_vrgather_mask_vx_nxv32i8_nxv32i8_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv32i8_nxv32i8_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e8, m4, d1 +; CHECK-NEXT: th.vrgather.vx v8, v12, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.mask.nxv32i8.i32( + %0, + %1, + i32 %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vx.nxv64i8.i32( + , + , + i32, + i32); + +define @intrinsic_vrgather_vx_nxv64i8_nxv64i8_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vx_nxv64i8_nxv64i8_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e8, m8, d1 +; CHECK-NEXT: th.vrgather.vx v16, v8, a0 +; CHECK-NEXT: th.vmv.v.v v8, v16 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.nxv64i8.i32( + undef, + %0, + i32 %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vx.mask.nxv64i8.i32( + , + , + i32, + , + i32); + +define @intrinsic_vrgather_mask_vx_nxv64i8_nxv64i8_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv64i8_nxv64i8_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e8, m8, d1 +; CHECK-NEXT: th.vrgather.vx v8, v16, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.mask.nxv64i8.i32( + %0, + %1, + i32 %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vx.nxv4i16.i32( + , + , + i32, + i32); + +define @intrinsic_vrgather_vx_nxv4i16_nxv4i16_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vx_nxv4i16_nxv4i16_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e16, m1, d1 +; CHECK-NEXT: th.vrgather.vx v9, v8, a0 +; CHECK-NEXT: th.vmv.v.v v8, v9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.nxv4i16.i32( + undef, + %0, + i32 %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vx.mask.nxv4i16.i32( + , + , + i32, + , + i32); + +define @intrinsic_vrgather_mask_vx_nxv4i16_nxv4i16_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv4i16_nxv4i16_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e16, m1, d1 +; CHECK-NEXT: th.vrgather.vx v8, v9, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.mask.nxv4i16.i32( + %0, + %1, + i32 %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vx.nxv8i16.i32( + , + , + i32, + i32); + +define @intrinsic_vrgather_vx_nxv8i16_nxv8i16_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vx_nxv8i16_nxv8i16_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e16, m2, d1 +; CHECK-NEXT: th.vrgather.vx v10, v8, a0 +; CHECK-NEXT: th.vmv.v.v v8, v10 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.nxv8i16.i32( + undef, + %0, + i32 %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vx.mask.nxv8i16.i32( + , + , + i32, + , + i32); + +define @intrinsic_vrgather_mask_vx_nxv8i16_nxv8i16_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv8i16_nxv8i16_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e16, m2, d1 +; CHECK-NEXT: th.vrgather.vx v8, v10, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.mask.nxv8i16.i32( + %0, + %1, + i32 %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vx.nxv16i16.i32( + , + , + i32, + i32); + +define @intrinsic_vrgather_vx_nxv16i16_nxv16i16_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vx_nxv16i16_nxv16i16_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e16, m4, d1 +; CHECK-NEXT: th.vrgather.vx v12, v8, a0 +; CHECK-NEXT: th.vmv.v.v v8, v12 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.nxv16i16.i32( + undef, + %0, + i32 %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vx.mask.nxv16i16.i32( + , + , + i32, + , + i32); + +define @intrinsic_vrgather_mask_vx_nxv16i16_nxv16i16_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv16i16_nxv16i16_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e16, m4, d1 +; CHECK-NEXT: th.vrgather.vx v8, v12, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.mask.nxv16i16.i32( + %0, + %1, + i32 %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vx.nxv32i16.i32( + , + , + i32, + i32); + +define @intrinsic_vrgather_vx_nxv32i16_nxv32i16_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vx_nxv32i16_nxv32i16_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e16, m8, d1 +; CHECK-NEXT: th.vrgather.vx v16, v8, a0 +; CHECK-NEXT: th.vmv.v.v v8, v16 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.nxv32i16.i32( + undef, + %0, + i32 %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vx.mask.nxv32i16.i32( + , + , + i32, + , + i32); + +define @intrinsic_vrgather_mask_vx_nxv32i16_nxv32i16_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv32i16_nxv32i16_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e16, m8, d1 +; CHECK-NEXT: th.vrgather.vx v8, v16, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.mask.nxv32i16.i32( + %0, + %1, + i32 %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vx.nxv2i32.i32( + , + , + i32, + i32); + +define @intrinsic_vrgather_vx_nxv2i32_nxv2i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vrgather.vx v9, v8, a0 +; CHECK-NEXT: th.vmv.v.v v8, v9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.nxv2i32.i32( + undef, + %0, + i32 %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vx.mask.nxv2i32.i32( + , + , + i32, + , + i32); + +define @intrinsic_vrgather_mask_vx_nxv2i32_nxv2i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vrgather.vx v8, v9, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.mask.nxv2i32.i32( + %0, + %1, + i32 %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vx.nxv4i32.i32( + , + , + i32, + i32); + +define @intrinsic_vrgather_vx_nxv4i32_nxv4i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vrgather.vx v10, v8, a0 +; CHECK-NEXT: th.vmv.v.v v8, v10 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.nxv4i32.i32( + undef, + %0, + i32 %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vx.mask.nxv4i32.i32( + , + , + i32, + , + i32); + +define @intrinsic_vrgather_mask_vx_nxv4i32_nxv4i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vrgather.vx v8, v10, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.mask.nxv4i32.i32( + %0, + %1, + i32 %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vx.nxv8i32.i32( + , + , + i32, + i32); + +define @intrinsic_vrgather_vx_nxv8i32_nxv8i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vrgather.vx v12, v8, a0 +; CHECK-NEXT: th.vmv.v.v v8, v12 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.nxv8i32.i32( + undef, + %0, + i32 %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vx.mask.nxv8i32.i32( + , + , + i32, + , + i32); + +define @intrinsic_vrgather_mask_vx_nxv8i32_nxv8i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vrgather.vx v8, v12, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.mask.nxv8i32.i32( + %0, + %1, + i32 %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vx.nxv16i32.i32( + , + , + i32, + i32); + +define @intrinsic_vrgather_vx_nxv16i32_nxv16i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e32, m8, d1 +; CHECK-NEXT: th.vrgather.vx v16, v8, a0 +; CHECK-NEXT: th.vmv.v.v v8, v16 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.nxv16i32.i32( + undef, + %0, + i32 %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vx.mask.nxv16i32.i32( + , + , + i32, + , + i32); + +define @intrinsic_vrgather_mask_vx_nxv16i32_nxv16i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e32, m8, d1 +; CHECK-NEXT: th.vrgather.vx v8, v16, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.mask.nxv16i32.i32( + %0, + %1, + i32 %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vx.nxv4f16.i32( + , + , + i32, + i32); + +define @intrinsic_vrgather_vx_nxv4f16_nxv4f16_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vx_nxv4f16_nxv4f16_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e16, m1, d1 +; CHECK-NEXT: th.vrgather.vx v9, v8, a0 +; CHECK-NEXT: th.vmv.v.v v8, v9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.nxv4f16.i32( + undef, + %0, + i32 %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vx.mask.nxv4f16.i32( + , + , + i32, + , + i32); + +define @intrinsic_vrgather_mask_vx_nxv4f16_nxv4f16_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv4f16_nxv4f16_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e16, m1, d1 +; CHECK-NEXT: th.vrgather.vx v8, v9, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.mask.nxv4f16.i32( + %0, + %1, + i32 %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vx.nxv8f16.i32( + , + , + i32, + i32); + +define @intrinsic_vrgather_vx_nxv8f16_nxv8f16_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vx_nxv8f16_nxv8f16_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e16, m2, d1 +; CHECK-NEXT: th.vrgather.vx v10, v8, a0 +; CHECK-NEXT: th.vmv.v.v v8, v10 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.nxv8f16.i32( + undef, + %0, + i32 %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vx.mask.nxv8f16.i32( + , + , + i32, + , + i32); + +define @intrinsic_vrgather_mask_vx_nxv8f16_nxv8f16_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv8f16_nxv8f16_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e16, m2, d1 +; CHECK-NEXT: th.vrgather.vx v8, v10, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.mask.nxv8f16.i32( + %0, + %1, + i32 %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vx.nxv16f16.i32( + , + , + i32, + i32); + +define @intrinsic_vrgather_vx_nxv16f16_nxv16f16_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vx_nxv16f16_nxv16f16_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e16, m4, d1 +; CHECK-NEXT: th.vrgather.vx v12, v8, a0 +; CHECK-NEXT: th.vmv.v.v v8, v12 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.nxv16f16.i32( + undef, + %0, + i32 %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vx.mask.nxv16f16.i32( + , + , + i32, + , + i32); + +define @intrinsic_vrgather_mask_vx_nxv16f16_nxv16f16_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv16f16_nxv16f16_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e16, m4, d1 +; CHECK-NEXT: th.vrgather.vx v8, v12, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.mask.nxv16f16.i32( + %0, + %1, + i32 %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vx.nxv32f16.i32( + , + , + i32, + i32); + +define @intrinsic_vrgather_vx_nxv32f16_nxv32f16_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vx_nxv32f16_nxv32f16_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e16, m8, d1 +; CHECK-NEXT: th.vrgather.vx v16, v8, a0 +; CHECK-NEXT: th.vmv.v.v v8, v16 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.nxv32f16.i32( + undef, + %0, + i32 %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vx.mask.nxv32f16.i32( + , + , + i32, + , + i32); + +define @intrinsic_vrgather_mask_vx_nxv32f16_nxv32f16_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv32f16_nxv32f16_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e16, m8, d1 +; CHECK-NEXT: th.vrgather.vx v8, v16, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.mask.nxv32f16.i32( + %0, + %1, + i32 %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vx.nxv2f32.i32( + , + , + i32, + i32); + +define @intrinsic_vrgather_vx_nxv2f32_nxv2f32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vx_nxv2f32_nxv2f32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vrgather.vx v9, v8, a0 +; CHECK-NEXT: th.vmv.v.v v8, v9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.nxv2f32.i32( + undef, + %0, + i32 %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vx.mask.nxv2f32.i32( + , + , + i32, + , + i32); + +define @intrinsic_vrgather_mask_vx_nxv2f32_nxv2f32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv2f32_nxv2f32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vrgather.vx v8, v9, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.mask.nxv2f32.i32( + %0, + %1, + i32 %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vx.nxv4f32.i32( + , + , + i32, + i32); + +define @intrinsic_vrgather_vx_nxv4f32_nxv4f32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vx_nxv4f32_nxv4f32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vrgather.vx v10, v8, a0 +; CHECK-NEXT: th.vmv.v.v v8, v10 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.nxv4f32.i32( + undef, + %0, + i32 %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vx.mask.nxv4f32.i32( + , + , + i32, + , + i32); + +define @intrinsic_vrgather_mask_vx_nxv4f32_nxv4f32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv4f32_nxv4f32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vrgather.vx v8, v10, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.mask.nxv4f32.i32( + %0, + %1, + i32 %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vx.nxv8f32.i32( + , + , + i32, + i32); + +define @intrinsic_vrgather_vx_nxv8f32_nxv8f32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vx_nxv8f32_nxv8f32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vrgather.vx v12, v8, a0 +; CHECK-NEXT: th.vmv.v.v v8, v12 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.nxv8f32.i32( + undef, + %0, + i32 %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vx.mask.nxv8f32.i32( + , + , + i32, + , + i32); + +define @intrinsic_vrgather_mask_vx_nxv8f32_nxv8f32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv8f32_nxv8f32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vrgather.vx v8, v12, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.mask.nxv8f32.i32( + %0, + %1, + i32 %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vx.nxv16f32.i32( + , + , + i32, + i32); + +define @intrinsic_vrgather_vx_nxv16f32_nxv16f32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vx_nxv16f32_nxv16f32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e32, m8, d1 +; CHECK-NEXT: th.vrgather.vx v16, v8, a0 +; CHECK-NEXT: th.vmv.v.v v8, v16 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.nxv16f32.i32( + undef, + %0, + i32 %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vx.mask.nxv16f32.i32( + , + , + i32, + , + i32); + +define @intrinsic_vrgather_mask_vx_nxv16f32_nxv16f32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv16f32_nxv16f32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e32, m8, d1 +; CHECK-NEXT: th.vrgather.vx v8, v16, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.mask.nxv16f32.i32( + %0, + %1, + i32 %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vx.nxv1f64.i32( + , + , + i32, + i32); + +define @intrinsic_vrgather_vx_nxv1f64_nxv1f64_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vx_nxv1f64_nxv1f64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e64, m1, d1 +; CHECK-NEXT: th.vrgather.vx v9, v8, a0 +; CHECK-NEXT: th.vmv.v.v v8, v9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.nxv1f64.i32( + undef, + %0, + i32 %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vx.mask.nxv1f64.i32( + , + , + i32, + , + i32); + +define @intrinsic_vrgather_mask_vx_nxv1f64_nxv1f64_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv1f64_nxv1f64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e64, m1, d1 +; CHECK-NEXT: th.vrgather.vx v8, v9, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.mask.nxv1f64.i32( + %0, + %1, + i32 %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vx.nxv2f64.i32( + , + , + i32, + i32); + +define @intrinsic_vrgather_vx_nxv2f64_nxv2f64_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vx_nxv2f64_nxv2f64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e64, m2, d1 +; CHECK-NEXT: th.vrgather.vx v10, v8, a0 +; CHECK-NEXT: th.vmv.v.v v8, v10 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.nxv2f64.i32( + undef, + %0, + i32 %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vx.mask.nxv2f64.i32( + , + , + i32, + , + i32); + +define @intrinsic_vrgather_mask_vx_nxv2f64_nxv2f64_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv2f64_nxv2f64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e64, m2, d1 +; CHECK-NEXT: th.vrgather.vx v8, v10, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.mask.nxv2f64.i32( + %0, + %1, + i32 %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vx.nxv4f64.i32( + , + , + i32, + i32); + +define @intrinsic_vrgather_vx_nxv4f64_nxv4f64_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vx_nxv4f64_nxv4f64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e64, m4, d1 +; CHECK-NEXT: th.vrgather.vx v12, v8, a0 +; CHECK-NEXT: th.vmv.v.v v8, v12 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.nxv4f64.i32( + undef, + %0, + i32 %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vx.mask.nxv4f64.i32( + , + , + i32, + , + i32); + +define @intrinsic_vrgather_mask_vx_nxv4f64_nxv4f64_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv4f64_nxv4f64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e64, m4, d1 +; CHECK-NEXT: th.vrgather.vx v8, v12, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.mask.nxv4f64.i32( + %0, + %1, + i32 %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vx.nxv8f64.i32( + , + , + i32, + i32); + +define @intrinsic_vrgather_vx_nxv8f64_nxv8f64_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vx_nxv8f64_nxv8f64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e64, m8, d1 +; CHECK-NEXT: th.vrgather.vx v16, v8, a0 +; CHECK-NEXT: th.vmv.v.v v8, v16 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.nxv8f64.i32( + undef, + %0, + i32 %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vx.mask.nxv8f64.i32( + , + , + i32, + , + i32); + +define @intrinsic_vrgather_mask_vx_nxv8f64_nxv8f64_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv8f64_nxv8f64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e64, m8, d1 +; CHECK-NEXT: th.vrgather.vx v8, v16, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.mask.nxv8f64.i32( + %0, + %1, + i32 %2, + %3, + i32 %4) + + ret %a +} + +define @intrinsic_vrgather_vi_nxv8i8_nxv8i8_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vi_nxv8i8_nxv8i8_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e8, m1, d1 +; CHECK-NEXT: th.vrgather.vi v9, v8, 9 +; CHECK-NEXT: th.vmv.v.v v8, v9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.nxv8i8.i32( + undef, + %0, + i32 9, + i32 %1) + + ret %a +} + +define @intrinsic_vrgather_mask_vi_nxv8i8_nxv8i8_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv8i8_nxv8i8_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e8, m1, d1 +; CHECK-NEXT: th.vrgather.vi v8, v9, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.mask.nxv8i8.i32( + %0, + %1, + i32 9, + %2, + i32 %3) + + ret %a +} + +define @intrinsic_vrgather_vi_nxv16i8_nxv16i8_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vi_nxv16i8_nxv16i8_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e8, m2, d1 +; CHECK-NEXT: th.vrgather.vi v10, v8, 9 +; CHECK-NEXT: th.vmv.v.v v8, v10 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.nxv16i8.i32( + undef, + %0, + i32 9, + i32 %1) + + ret %a +} + +define @intrinsic_vrgather_mask_vi_nxv16i8_nxv16i8_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv16i8_nxv16i8_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e8, m2, d1 +; CHECK-NEXT: th.vrgather.vi v8, v10, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.mask.nxv16i8.i32( + %0, + %1, + i32 9, + %2, + i32 %3) + + ret %a +} + +define @intrinsic_vrgather_vi_nxv32i8_nxv32i8_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vi_nxv32i8_nxv32i8_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e8, m4, d1 +; CHECK-NEXT: th.vrgather.vi v12, v8, 9 +; CHECK-NEXT: th.vmv.v.v v8, v12 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.nxv32i8.i32( + undef, + %0, + i32 9, + i32 %1) + + ret %a +} + +define @intrinsic_vrgather_mask_vi_nxv32i8_nxv32i8_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv32i8_nxv32i8_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e8, m4, d1 +; CHECK-NEXT: th.vrgather.vi v8, v12, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.mask.nxv32i8.i32( + %0, + %1, + i32 9, + %2, + i32 %3) + + ret %a +} + +define @intrinsic_vrgather_vi_nxv64i8_nxv64i8_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vi_nxv64i8_nxv64i8_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e8, m8, d1 +; CHECK-NEXT: th.vrgather.vi v16, v8, 9 +; CHECK-NEXT: th.vmv.v.v v8, v16 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.nxv64i8.i32( + undef, + %0, + i32 9, + i32 %1) + + ret %a +} + +define @intrinsic_vrgather_mask_vi_nxv64i8_nxv64i8_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv64i8_nxv64i8_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e8, m8, d1 +; CHECK-NEXT: th.vrgather.vi v8, v16, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.mask.nxv64i8.i32( + %0, + %1, + i32 9, + %2, + i32 %3) + + ret %a +} + +define @intrinsic_vrgather_vi_nxv4i16_nxv4i16_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vi_nxv4i16_nxv4i16_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e16, m1, d1 +; CHECK-NEXT: th.vrgather.vi v9, v8, 9 +; CHECK-NEXT: th.vmv.v.v v8, v9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.nxv4i16.i32( + undef, + %0, + i32 9, + i32 %1) + + ret %a +} + +define @intrinsic_vrgather_mask_vi_nxv4i16_nxv4i16_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv4i16_nxv4i16_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e16, m1, d1 +; CHECK-NEXT: th.vrgather.vi v8, v9, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.mask.nxv4i16.i32( + %0, + %1, + i32 9, + %2, + i32 %3) + + ret %a +} + +define @intrinsic_vrgather_vi_nxv8i16_nxv8i16_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vi_nxv8i16_nxv8i16_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e16, m2, d1 +; CHECK-NEXT: th.vrgather.vi v10, v8, 9 +; CHECK-NEXT: th.vmv.v.v v8, v10 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.nxv8i16.i32( + undef, + %0, + i32 9, + i32 %1) + + ret %a +} + +define @intrinsic_vrgather_mask_vi_nxv8i16_nxv8i16_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv8i16_nxv8i16_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e16, m2, d1 +; CHECK-NEXT: th.vrgather.vi v8, v10, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.mask.nxv8i16.i32( + %0, + %1, + i32 9, + %2, + i32 %3) + + ret %a +} + +define @intrinsic_vrgather_vi_nxv16i16_nxv16i16_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vi_nxv16i16_nxv16i16_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e16, m4, d1 +; CHECK-NEXT: th.vrgather.vi v12, v8, 9 +; CHECK-NEXT: th.vmv.v.v v8, v12 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.nxv16i16.i32( + undef, + %0, + i32 9, + i32 %1) + + ret %a +} + +define @intrinsic_vrgather_mask_vi_nxv16i16_nxv16i16_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv16i16_nxv16i16_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e16, m4, d1 +; CHECK-NEXT: th.vrgather.vi v8, v12, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.mask.nxv16i16.i32( + %0, + %1, + i32 9, + %2, + i32 %3) + + ret %a +} + +define @intrinsic_vrgather_vi_nxv32i16_nxv32i16_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vi_nxv32i16_nxv32i16_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e16, m8, d1 +; CHECK-NEXT: th.vrgather.vi v16, v8, 9 +; CHECK-NEXT: th.vmv.v.v v8, v16 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.nxv32i16.i32( + undef, + %0, + i32 9, + i32 %1) + + ret %a +} + +define @intrinsic_vrgather_mask_vi_nxv32i16_nxv32i16_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv32i16_nxv32i16_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e16, m8, d1 +; CHECK-NEXT: th.vrgather.vi v8, v16, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.mask.nxv32i16.i32( + %0, + %1, + i32 9, + %2, + i32 %3) + + ret %a +} + +define @intrinsic_vrgather_vi_nxv2i32_nxv2i32_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vi_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e32, m1, d1 +; CHECK-NEXT: th.vrgather.vi v9, v8, 9 +; CHECK-NEXT: th.vmv.v.v v8, v9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.nxv2i32.i32( + undef, + %0, + i32 9, + i32 %1) + + ret %a +} + +define @intrinsic_vrgather_mask_vi_nxv2i32_nxv2i32_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e32, m1, d1 +; CHECK-NEXT: th.vrgather.vi v8, v9, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.mask.nxv2i32.i32( + %0, + %1, + i32 9, + %2, + i32 %3) + + ret %a +} + +define @intrinsic_vrgather_vi_nxv4i32_nxv4i32_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vi_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e32, m2, d1 +; CHECK-NEXT: th.vrgather.vi v10, v8, 9 +; CHECK-NEXT: th.vmv.v.v v8, v10 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.nxv4i32.i32( + undef, + %0, + i32 9, + i32 %1) + + ret %a +} + +define @intrinsic_vrgather_mask_vi_nxv4i32_nxv4i32_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e32, m2, d1 +; CHECK-NEXT: th.vrgather.vi v8, v10, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.mask.nxv4i32.i32( + %0, + %1, + i32 9, + %2, + i32 %3) + + ret %a +} + +define @intrinsic_vrgather_vi_nxv8i32_nxv8i32_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vi_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e32, m4, d1 +; CHECK-NEXT: th.vrgather.vi v12, v8, 9 +; CHECK-NEXT: th.vmv.v.v v8, v12 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.nxv8i32.i32( + undef, + %0, + i32 9, + i32 %1) + + ret %a +} + +define @intrinsic_vrgather_mask_vi_nxv8i32_nxv8i32_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e32, m4, d1 +; CHECK-NEXT: th.vrgather.vi v8, v12, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.mask.nxv8i32.i32( + %0, + %1, + i32 9, + %2, + i32 %3) + + ret %a +} + +define @intrinsic_vrgather_vi_nxv16i32_nxv16i32_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vi_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e32, m8, d1 +; CHECK-NEXT: th.vrgather.vi v16, v8, 9 +; CHECK-NEXT: th.vmv.v.v v8, v16 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.nxv16i32.i32( + undef, + %0, + i32 9, + i32 %1) + + ret %a +} + +define @intrinsic_vrgather_mask_vi_nxv16i32_nxv16i32_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e32, m8, d1 +; CHECK-NEXT: th.vrgather.vi v8, v16, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.mask.nxv16i32.i32( + %0, + %1, + i32 9, + %2, + i32 %3) + + ret %a +} + +define @intrinsic_vrgather_vi_nxv4f16_nxv4f16_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vi_nxv4f16_nxv4f16_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e16, m1, d1 +; CHECK-NEXT: th.vrgather.vi v9, v8, 9 +; CHECK-NEXT: th.vmv.v.v v8, v9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.nxv4f16.i32( + undef, + %0, + i32 9, + i32 %1) + + ret %a +} + +define @intrinsic_vrgather_mask_vi_nxv4f16_nxv4f16_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv4f16_nxv4f16_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e16, m1, d1 +; CHECK-NEXT: th.vrgather.vi v8, v9, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.mask.nxv4f16.i32( + %0, + %1, + i32 9, + %2, + i32 %3) + + ret %a +} + +define @intrinsic_vrgather_vi_nxv8f16_nxv8f16_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vi_nxv8f16_nxv8f16_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e16, m2, d1 +; CHECK-NEXT: th.vrgather.vi v10, v8, 9 +; CHECK-NEXT: th.vmv.v.v v8, v10 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.nxv8f16.i32( + undef, + %0, + i32 9, + i32 %1) + + ret %a +} + +define @intrinsic_vrgather_mask_vi_nxv8f16_nxv8f16_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv8f16_nxv8f16_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e16, m2, d1 +; CHECK-NEXT: th.vrgather.vi v8, v10, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.mask.nxv8f16.i32( + %0, + %1, + i32 9, + %2, + i32 %3) + + ret %a +} + +define @intrinsic_vrgather_vi_nxv16f16_nxv16f16_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vi_nxv16f16_nxv16f16_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e16, m4, d1 +; CHECK-NEXT: th.vrgather.vi v12, v8, 9 +; CHECK-NEXT: th.vmv.v.v v8, v12 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.nxv16f16.i32( + undef, + %0, + i32 9, + i32 %1) + + ret %a +} + +define @intrinsic_vrgather_mask_vi_nxv16f16_nxv16f16_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv16f16_nxv16f16_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e16, m4, d1 +; CHECK-NEXT: th.vrgather.vi v8, v12, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.mask.nxv16f16.i32( + %0, + %1, + i32 9, + %2, + i32 %3) + + ret %a +} + +define @intrinsic_vrgather_vi_nxv32f16_nxv32f16_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vi_nxv32f16_nxv32f16_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e16, m8, d1 +; CHECK-NEXT: th.vrgather.vi v16, v8, 9 +; CHECK-NEXT: th.vmv.v.v v8, v16 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.nxv32f16.i32( + undef, + %0, + i32 9, + i32 %1) + + ret %a +} + +define @intrinsic_vrgather_mask_vi_nxv32f16_nxv32f16_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv32f16_nxv32f16_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e16, m8, d1 +; CHECK-NEXT: th.vrgather.vi v8, v16, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.mask.nxv32f16.i32( + %0, + %1, + i32 9, + %2, + i32 %3) + + ret %a +} + +define @intrinsic_vrgather_vi_nxv2f32_nxv2f32_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vi_nxv2f32_nxv2f32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e32, m1, d1 +; CHECK-NEXT: th.vrgather.vi v9, v8, 9 +; CHECK-NEXT: th.vmv.v.v v8, v9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.nxv2f32.i32( + undef, + %0, + i32 9, + i32 %1) + + ret %a +} + +define @intrinsic_vrgather_mask_vi_nxv2f32_nxv2f32_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv2f32_nxv2f32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e32, m1, d1 +; CHECK-NEXT: th.vrgather.vi v8, v9, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.mask.nxv2f32.i32( + %0, + %1, + i32 9, + %2, + i32 %3) + + ret %a +} + +define @intrinsic_vrgather_vi_nxv4f32_nxv4f32_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vi_nxv4f32_nxv4f32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e32, m2, d1 +; CHECK-NEXT: th.vrgather.vi v10, v8, 9 +; CHECK-NEXT: th.vmv.v.v v8, v10 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.nxv4f32.i32( + undef, + %0, + i32 9, + i32 %1) + + ret %a +} + +define @intrinsic_vrgather_mask_vi_nxv4f32_nxv4f32_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv4f32_nxv4f32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e32, m2, d1 +; CHECK-NEXT: th.vrgather.vi v8, v10, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.mask.nxv4f32.i32( + %0, + %1, + i32 9, + %2, + i32 %3) + + ret %a +} + +define @intrinsic_vrgather_vi_nxv8f32_nxv8f32_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vi_nxv8f32_nxv8f32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e32, m4, d1 +; CHECK-NEXT: th.vrgather.vi v12, v8, 9 +; CHECK-NEXT: th.vmv.v.v v8, v12 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.nxv8f32.i32( + undef, + %0, + i32 9, + i32 %1) + + ret %a +} + +define @intrinsic_vrgather_mask_vi_nxv8f32_nxv8f32_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv8f32_nxv8f32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e32, m4, d1 +; CHECK-NEXT: th.vrgather.vi v8, v12, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.mask.nxv8f32.i32( + %0, + %1, + i32 9, + %2, + i32 %3) + + ret %a +} + +define @intrinsic_vrgather_vi_nxv16f32_nxv16f32_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vi_nxv16f32_nxv16f32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e32, m8, d1 +; CHECK-NEXT: th.vrgather.vi v16, v8, 9 +; CHECK-NEXT: th.vmv.v.v v8, v16 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.nxv16f32.i32( + undef, + %0, + i32 9, + i32 %1) + + ret %a +} + +define @intrinsic_vrgather_mask_vi_nxv16f32_nxv16f32_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv16f32_nxv16f32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e32, m8, d1 +; CHECK-NEXT: th.vrgather.vi v8, v16, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.mask.nxv16f32.i32( + %0, + %1, + i32 9, + %2, + i32 %3) + + ret %a +} + +define @intrinsic_vrgather_vi_nxv1f64_nxv1f64_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vi_nxv1f64_nxv1f64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e64, m1, d1 +; CHECK-NEXT: th.vrgather.vi v9, v8, 9 +; CHECK-NEXT: th.vmv.v.v v8, v9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.nxv1f64.i32( + undef, + %0, + i32 9, + i32 %1) + + ret %a +} + +define @intrinsic_vrgather_mask_vi_nxv1f64_nxv1f64_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv1f64_nxv1f64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e64, m1, d1 +; CHECK-NEXT: th.vrgather.vi v8, v9, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.mask.nxv1f64.i32( + %0, + %1, + i32 9, + %2, + i32 %3) + + ret %a +} + +define @intrinsic_vrgather_vi_nxv2f64_nxv2f64_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vi_nxv2f64_nxv2f64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e64, m2, d1 +; CHECK-NEXT: th.vrgather.vi v10, v8, 9 +; CHECK-NEXT: th.vmv.v.v v8, v10 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.nxv2f64.i32( + undef, + %0, + i32 9, + i32 %1) + + ret %a +} + +define @intrinsic_vrgather_mask_vi_nxv2f64_nxv2f64_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv2f64_nxv2f64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e64, m2, d1 +; CHECK-NEXT: th.vrgather.vi v8, v10, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.mask.nxv2f64.i32( + %0, + %1, + i32 9, + %2, + i32 %3) + + ret %a +} + +define @intrinsic_vrgather_vi_nxv4f64_nxv4f64_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vi_nxv4f64_nxv4f64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e64, m4, d1 +; CHECK-NEXT: th.vrgather.vi v12, v8, 9 +; CHECK-NEXT: th.vmv.v.v v8, v12 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.nxv4f64.i32( + undef, + %0, + i32 9, + i32 %1) + + ret %a +} + +define @intrinsic_vrgather_mask_vi_nxv4f64_nxv4f64_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv4f64_nxv4f64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e64, m4, d1 +; CHECK-NEXT: th.vrgather.vi v8, v12, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.mask.nxv4f64.i32( + %0, + %1, + i32 9, + %2, + i32 %3) + + ret %a +} + +define @intrinsic_vrgather_vi_nxv8f64_nxv8f64_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vi_nxv8f64_nxv8f64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e64, m8, d1 +; CHECK-NEXT: th.vrgather.vi v16, v8, 9 +; CHECK-NEXT: th.vmv.v.v v8, v16 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.nxv8f64.i32( + undef, + %0, + i32 9, + i32 %1) + + ret %a +} + +define @intrinsic_vrgather_mask_vi_nxv8f64_nxv8f64_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv8f64_nxv8f64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e64, m8, d1 +; CHECK-NEXT: th.vrgather.vi v8, v16, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.mask.nxv8f64.i32( + %0, + %1, + i32 9, + %2, + i32 %3) + + ret %a +} diff --git a/llvm/test/CodeGen/RISCV/rvv0p71/vrgather-rv64.ll b/llvm/test/CodeGen/RISCV/rvv0p71/vrgather-rv64.ll new file mode 100644 index 00000000000000..112d511fade607 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/rvv0p71/vrgather-rv64.ll @@ -0,0 +1,3622 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=riscv64 -mattr=+xtheadvector,+d -verify-machineinstrs \ +; RUN: < %s | FileCheck %s + +declare @llvm.riscv.th.vrgather.vv.nxv8i8.i64( + , + , + , + i64); + +define @intrinsic_vrgather_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e8, m1, d1 +; CHECK-NEXT: th.vrgather.vv v10, v8, v9 +; CHECK-NEXT: th.vmv.v.v v8, v10 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vv.nxv8i8.i64( + undef, + %0, + %1, + i64 %2) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vv.mask.nxv8i8.i64( + , + , + , + , + i64); + +define @intrinsic_vrgather_mask_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e8, m1, d1 +; CHECK-NEXT: th.vrgather.vv v8, v9, v10, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vv.mask.nxv8i8.i64( + %0, + %1, + %2, + %3, + i64 %4) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vv.nxv16i8.i64( + , + , + , + i64); + +define @intrinsic_vrgather_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e8, m2, d1 +; CHECK-NEXT: th.vrgather.vv v12, v8, v10 +; CHECK-NEXT: th.vmv.v.v v8, v12 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vv.nxv16i8.i64( + undef, + %0, + %1, + i64 %2) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vv.mask.nxv16i8.i64( + , + , + , + , + i64); + +define @intrinsic_vrgather_mask_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e8, m2, d1 +; CHECK-NEXT: th.vrgather.vv v8, v10, v12, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vv.mask.nxv16i8.i64( + %0, + %1, + %2, + %3, + i64 %4) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vv.nxv32i8.i64( + , + , + , + i64); + +define @intrinsic_vrgather_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e8, m4, d1 +; CHECK-NEXT: th.vrgather.vv v16, v8, v12 +; CHECK-NEXT: th.vmv.v.v v8, v16 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vv.nxv32i8.i64( + undef, + %0, + %1, + i64 %2) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vv.mask.nxv32i8.i64( + , + , + , + , + i64); + +define @intrinsic_vrgather_mask_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e8, m4, d1 +; CHECK-NEXT: th.vrgather.vv v8, v12, v16, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vv.mask.nxv32i8.i64( + %0, + %1, + %2, + %3, + i64 %4) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vv.nxv64i8.i64( + , + , + , + i64); + +define @intrinsic_vrgather_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e8, m8, d1 +; CHECK-NEXT: th.vrgather.vv v24, v8, v16 +; CHECK-NEXT: th.vmv.v.v v8, v24 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vv.nxv64i8.i64( + undef, + %0, + %1, + i64 %2) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vv.mask.nxv64i8.i64( + , + , + , + , + i64); + +define @intrinsic_vrgather_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e8, m8, d1 +; CHECK-NEXT: th.vle.v v24, (a0) +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e8, m8, d1 +; CHECK-NEXT: th.vrgather.vv v8, v16, v24, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vv.mask.nxv64i8.i64( + %0, + %1, + %2, + %3, + i64 %4) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vv.nxv4i16.i64( + , + , + , + i64); + +define @intrinsic_vrgather_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e16, m1, d1 +; CHECK-NEXT: th.vrgather.vv v10, v8, v9 +; CHECK-NEXT: th.vmv.v.v v8, v10 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vv.nxv4i16.i64( + undef, + %0, + %1, + i64 %2) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vv.mask.nxv4i16.i64( + , + , + , + , + i64); + +define @intrinsic_vrgather_mask_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e16, m1, d1 +; CHECK-NEXT: th.vrgather.vv v8, v9, v10, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vv.mask.nxv4i16.i64( + %0, + %1, + %2, + %3, + i64 %4) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vv.nxv8i16.i64( + , + , + , + i64); + +define @intrinsic_vrgather_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e16, m2, d1 +; CHECK-NEXT: th.vrgather.vv v12, v8, v10 +; CHECK-NEXT: th.vmv.v.v v8, v12 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vv.nxv8i16.i64( + undef, + %0, + %1, + i64 %2) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vv.mask.nxv8i16.i64( + , + , + , + , + i64); + +define @intrinsic_vrgather_mask_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e16, m2, d1 +; CHECK-NEXT: th.vrgather.vv v8, v10, v12, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vv.mask.nxv8i16.i64( + %0, + %1, + %2, + %3, + i64 %4) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vv.nxv16i16.i64( + , + , + , + i64); + +define @intrinsic_vrgather_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e16, m4, d1 +; CHECK-NEXT: th.vrgather.vv v16, v8, v12 +; CHECK-NEXT: th.vmv.v.v v8, v16 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vv.nxv16i16.i64( + undef, + %0, + %1, + i64 %2) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vv.mask.nxv16i16.i64( + , + , + , + , + i64); + +define @intrinsic_vrgather_mask_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e16, m4, d1 +; CHECK-NEXT: th.vrgather.vv v8, v12, v16, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vv.mask.nxv16i16.i64( + %0, + %1, + %2, + %3, + i64 %4) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vv.nxv32i16.i64( + , + , + , + i64); + +define @intrinsic_vrgather_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e16, m8, d1 +; CHECK-NEXT: th.vrgather.vv v24, v8, v16 +; CHECK-NEXT: th.vmv.v.v v8, v24 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vv.nxv32i16.i64( + undef, + %0, + %1, + i64 %2) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vv.mask.nxv32i16.i64( + , + , + , + , + i64); + +define @intrinsic_vrgather_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e16, m8, d1 +; CHECK-NEXT: th.vle.v v24, (a0) +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e16, m8, d1 +; CHECK-NEXT: th.vrgather.vv v8, v16, v24, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vv.mask.nxv32i16.i64( + %0, + %1, + %2, + %3, + i64 %4) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vv.nxv2i32.i64( + , + , + , + i64); + +define @intrinsic_vrgather_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e32, m1, d1 +; CHECK-NEXT: th.vrgather.vv v10, v8, v9 +; CHECK-NEXT: th.vmv.v.v v8, v10 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vv.nxv2i32.i64( + undef, + %0, + %1, + i64 %2) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vv.mask.nxv2i32.i64( + , + , + , + , + i64); + +define @intrinsic_vrgather_mask_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e32, m1, d1 +; CHECK-NEXT: th.vrgather.vv v8, v9, v10, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vv.mask.nxv2i32.i64( + %0, + %1, + %2, + %3, + i64 %4) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vv.nxv4i32.i64( + , + , + , + i64); + +define @intrinsic_vrgather_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e32, m2, d1 +; CHECK-NEXT: th.vrgather.vv v12, v8, v10 +; CHECK-NEXT: th.vmv.v.v v8, v12 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vv.nxv4i32.i64( + undef, + %0, + %1, + i64 %2) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vv.mask.nxv4i32.i64( + , + , + , + , + i64); + +define @intrinsic_vrgather_mask_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e32, m2, d1 +; CHECK-NEXT: th.vrgather.vv v8, v10, v12, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vv.mask.nxv4i32.i64( + %0, + %1, + %2, + %3, + i64 %4) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vv.nxv8i32.i64( + , + , + , + i64); + +define @intrinsic_vrgather_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e32, m4, d1 +; CHECK-NEXT: th.vrgather.vv v16, v8, v12 +; CHECK-NEXT: th.vmv.v.v v8, v16 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vv.nxv8i32.i64( + undef, + %0, + %1, + i64 %2) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vv.mask.nxv8i32.i64( + , + , + , + , + i64); + +define @intrinsic_vrgather_mask_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e32, m4, d1 +; CHECK-NEXT: th.vrgather.vv v8, v12, v16, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vv.mask.nxv8i32.i64( + %0, + %1, + %2, + %3, + i64 %4) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vv.nxv16i32.i64( + , + , + , + i64); + +define @intrinsic_vrgather_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e32, m8, d1 +; CHECK-NEXT: th.vrgather.vv v24, v8, v16 +; CHECK-NEXT: th.vmv.v.v v8, v24 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vv.nxv16i32.i64( + undef, + %0, + %1, + i64 %2) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vv.mask.nxv16i32.i64( + , + , + , + , + i64); + +define @intrinsic_vrgather_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e32, m8, d1 +; CHECK-NEXT: th.vle.v v24, (a0) +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m8, d1 +; CHECK-NEXT: th.vrgather.vv v8, v16, v24, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vv.mask.nxv16i32.i64( + %0, + %1, + %2, + %3, + i64 %4) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vv.nxv1i64.i64( + , + , + , + i64); + +define @intrinsic_vrgather_vv_nxv1i64_nxv1i64_nxv1i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vv_nxv1i64_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e64, m1, d1 +; CHECK-NEXT: th.vrgather.vv v10, v8, v9 +; CHECK-NEXT: th.vmv.v.v v8, v10 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vv.nxv1i64.i64( + undef, + %0, + %1, + i64 %2) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vv.mask.nxv1i64.i64( + , + , + , + , + i64); + +define @intrinsic_vrgather_mask_vv_nxv1i64_nxv1i64_nxv1i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv1i64_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e64, m1, d1 +; CHECK-NEXT: th.vrgather.vv v8, v9, v10, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vv.mask.nxv1i64.i64( + %0, + %1, + %2, + %3, + i64 %4) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vv.nxv2i64.i64( + , + , + , + i64); + +define @intrinsic_vrgather_vv_nxv2i64_nxv2i64_nxv2i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vv_nxv2i64_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e64, m2, d1 +; CHECK-NEXT: th.vrgather.vv v12, v8, v10 +; CHECK-NEXT: th.vmv.v.v v8, v12 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vv.nxv2i64.i64( + undef, + %0, + %1, + i64 %2) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vv.mask.nxv2i64.i64( + , + , + , + , + i64); + +define @intrinsic_vrgather_mask_vv_nxv2i64_nxv2i64_nxv2i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv2i64_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e64, m2, d1 +; CHECK-NEXT: th.vrgather.vv v8, v10, v12, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vv.mask.nxv2i64.i64( + %0, + %1, + %2, + %3, + i64 %4) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vv.nxv4i64.i64( + , + , + , + i64); + +define @intrinsic_vrgather_vv_nxv4i64_nxv4i64_nxv4i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vv_nxv4i64_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e64, m4, d1 +; CHECK-NEXT: th.vrgather.vv v16, v8, v12 +; CHECK-NEXT: th.vmv.v.v v8, v16 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vv.nxv4i64.i64( + undef, + %0, + %1, + i64 %2) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vv.mask.nxv4i64.i64( + , + , + , + , + i64); + +define @intrinsic_vrgather_mask_vv_nxv4i64_nxv4i64_nxv4i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv4i64_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e64, m4, d1 +; CHECK-NEXT: th.vrgather.vv v8, v12, v16, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vv.mask.nxv4i64.i64( + %0, + %1, + %2, + %3, + i64 %4) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vv.nxv8i64.i64( + , + , + , + i64); + +define @intrinsic_vrgather_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vv_nxv8i64_nxv8i64_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e64, m8, d1 +; CHECK-NEXT: th.vrgather.vv v24, v8, v16 +; CHECK-NEXT: th.vmv.v.v v8, v24 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vv.nxv8i64.i64( + undef, + %0, + %1, + i64 %2) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vv.mask.nxv8i64.i64( + , + , + , + , + i64); + +define @intrinsic_vrgather_mask_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv8i64_nxv8i64_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e64, m8, d1 +; CHECK-NEXT: th.vle.v v24, (a0) +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m8, d1 +; CHECK-NEXT: th.vrgather.vv v8, v16, v24, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vv.mask.nxv8i64.i64( + %0, + %1, + %2, + %3, + i64 %4) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vv.nxv4f16.i64( + , + , + , + i64); + +define @intrinsic_vrgather_vv_nxv4f16_nxv4f16_nxv4i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vv_nxv4f16_nxv4f16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e16, m1, d1 +; CHECK-NEXT: th.vrgather.vv v10, v8, v9 +; CHECK-NEXT: th.vmv.v.v v8, v10 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vv.nxv4f16.i64( + undef, + %0, + %1, + i64 %2) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vv.mask.nxv4f16.i64( + , + , + , + , + i64); + +define @intrinsic_vrgather_mask_vv_nxv4f16_nxv4f16_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv4f16_nxv4f16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e16, m1, d1 +; CHECK-NEXT: th.vrgather.vv v8, v9, v10, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vv.mask.nxv4f16.i64( + %0, + %1, + %2, + %3, + i64 %4) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vv.nxv8f16.i64( + , + , + , + i64); + +define @intrinsic_vrgather_vv_nxv8f16_nxv8f16_nxv8i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vv_nxv8f16_nxv8f16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e16, m2, d1 +; CHECK-NEXT: th.vrgather.vv v12, v8, v10 +; CHECK-NEXT: th.vmv.v.v v8, v12 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vv.nxv8f16.i64( + undef, + %0, + %1, + i64 %2) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vv.mask.nxv8f16.i64( + , + , + , + , + i64); + +define @intrinsic_vrgather_mask_vv_nxv8f16_nxv8f16_nxv8i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv8f16_nxv8f16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e16, m2, d1 +; CHECK-NEXT: th.vrgather.vv v8, v10, v12, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vv.mask.nxv8f16.i64( + %0, + %1, + %2, + %3, + i64 %4) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vv.nxv16f16.i64( + , + , + , + i64); + +define @intrinsic_vrgather_vv_nxv16f16_nxv16f16_nxv16i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vv_nxv16f16_nxv16f16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e16, m4, d1 +; CHECK-NEXT: th.vrgather.vv v16, v8, v12 +; CHECK-NEXT: th.vmv.v.v v8, v16 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vv.nxv16f16.i64( + undef, + %0, + %1, + i64 %2) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vv.mask.nxv16f16.i64( + , + , + , + , + i64); + +define @intrinsic_vrgather_mask_vv_nxv16f16_nxv16f16_nxv16i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv16f16_nxv16f16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e16, m4, d1 +; CHECK-NEXT: th.vrgather.vv v8, v12, v16, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vv.mask.nxv16f16.i64( + %0, + %1, + %2, + %3, + i64 %4) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vv.nxv32f16.i64( + , + , + , + i64); + +define @intrinsic_vrgather_vv_nxv32f16_nxv32f16_nxv32i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vv_nxv32f16_nxv32f16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e16, m8, d1 +; CHECK-NEXT: th.vrgather.vv v24, v8, v16 +; CHECK-NEXT: th.vmv.v.v v8, v24 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vv.nxv32f16.i64( + undef, + %0, + %1, + i64 %2) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vv.mask.nxv32f16.i64( + , + , + , + , + i64); + +define @intrinsic_vrgather_mask_vv_nxv32f16_nxv32f16_nxv32i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv32f16_nxv32f16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e16, m8, d1 +; CHECK-NEXT: th.vle.v v24, (a0) +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e16, m8, d1 +; CHECK-NEXT: th.vrgather.vv v8, v16, v24, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vv.mask.nxv32f16.i64( + %0, + %1, + %2, + %3, + i64 %4) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vv.nxv2f32.i64( + , + , + , + i64); + +define @intrinsic_vrgather_vv_nxv2f32_nxv2f32_nxv2i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vv_nxv2f32_nxv2f32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e32, m1, d1 +; CHECK-NEXT: th.vrgather.vv v10, v8, v9 +; CHECK-NEXT: th.vmv.v.v v8, v10 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vv.nxv2f32.i64( + undef, + %0, + %1, + i64 %2) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vv.mask.nxv2f32.i64( + , + , + , + , + i64); + +define @intrinsic_vrgather_mask_vv_nxv2f32_nxv2f32_nxv2i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv2f32_nxv2f32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e32, m1, d1 +; CHECK-NEXT: th.vrgather.vv v8, v9, v10, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vv.mask.nxv2f32.i64( + %0, + %1, + %2, + %3, + i64 %4) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vv.nxv4f32.i64( + , + , + , + i64); + +define @intrinsic_vrgather_vv_nxv4f32_nxv4f32_nxv4i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vv_nxv4f32_nxv4f32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e32, m2, d1 +; CHECK-NEXT: th.vrgather.vv v12, v8, v10 +; CHECK-NEXT: th.vmv.v.v v8, v12 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vv.nxv4f32.i64( + undef, + %0, + %1, + i64 %2) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vv.mask.nxv4f32.i64( + , + , + , + , + i64); + +define @intrinsic_vrgather_mask_vv_nxv4f32_nxv4f32_nxv4i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv4f32_nxv4f32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e32, m2, d1 +; CHECK-NEXT: th.vrgather.vv v8, v10, v12, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vv.mask.nxv4f32.i64( + %0, + %1, + %2, + %3, + i64 %4) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vv.nxv8f32.i64( + , + , + , + i64); + +define @intrinsic_vrgather_vv_nxv8f32_nxv8f32_nxv8i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vv_nxv8f32_nxv8f32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e32, m4, d1 +; CHECK-NEXT: th.vrgather.vv v16, v8, v12 +; CHECK-NEXT: th.vmv.v.v v8, v16 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vv.nxv8f32.i64( + undef, + %0, + %1, + i64 %2) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vv.mask.nxv8f32.i64( + , + , + , + , + i64); + +define @intrinsic_vrgather_mask_vv_nxv8f32_nxv8f32_nxv8i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv8f32_nxv8f32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e32, m4, d1 +; CHECK-NEXT: th.vrgather.vv v8, v12, v16, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vv.mask.nxv8f32.i64( + %0, + %1, + %2, + %3, + i64 %4) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vv.nxv16f32.i64( + , + , + , + i64); + +define @intrinsic_vrgather_vv_nxv16f32_nxv16f32_nxv16i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vv_nxv16f32_nxv16f32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e32, m8, d1 +; CHECK-NEXT: th.vrgather.vv v24, v8, v16 +; CHECK-NEXT: th.vmv.v.v v8, v24 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vv.nxv16f32.i64( + undef, + %0, + %1, + i64 %2) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vv.mask.nxv16f32.i64( + , + , + , + , + i64); + +define @intrinsic_vrgather_mask_vv_nxv16f32_nxv16f32_nxv16i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv16f32_nxv16f32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e32, m8, d1 +; CHECK-NEXT: th.vle.v v24, (a0) +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e32, m8, d1 +; CHECK-NEXT: th.vrgather.vv v8, v16, v24, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vv.mask.nxv16f32.i64( + %0, + %1, + %2, + %3, + i64 %4) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vv.nxv1f64.i64( + , + , + , + i64); + +define @intrinsic_vrgather_vv_nxv1f64_nxv1f64_nxv1i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vv_nxv1f64_nxv1f64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e64, m1, d1 +; CHECK-NEXT: th.vrgather.vv v10, v8, v9 +; CHECK-NEXT: th.vmv.v.v v8, v10 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vv.nxv1f64.i64( + undef, + %0, + %1, + i64 %2) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vv.mask.nxv1f64.i64( + , + , + , + , + i64); + +define @intrinsic_vrgather_mask_vv_nxv1f64_nxv1f64_nxv1i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv1f64_nxv1f64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e64, m1, d1 +; CHECK-NEXT: th.vrgather.vv v8, v9, v10, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vv.mask.nxv1f64.i64( + %0, + %1, + %2, + %3, + i64 %4) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vv.nxv2f64.i64( + , + , + , + i64); + +define @intrinsic_vrgather_vv_nxv2f64_nxv2f64_nxv2i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vv_nxv2f64_nxv2f64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e64, m2, d1 +; CHECK-NEXT: th.vrgather.vv v12, v8, v10 +; CHECK-NEXT: th.vmv.v.v v8, v12 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vv.nxv2f64.i64( + undef, + %0, + %1, + i64 %2) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vv.mask.nxv2f64.i64( + , + , + , + , + i64); + +define @intrinsic_vrgather_mask_vv_nxv2f64_nxv2f64_nxv2i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv2f64_nxv2f64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e64, m2, d1 +; CHECK-NEXT: th.vrgather.vv v8, v10, v12, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vv.mask.nxv2f64.i64( + %0, + %1, + %2, + %3, + i64 %4) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vv.nxv4f64.i64( + , + , + , + i64); + +define @intrinsic_vrgather_vv_nxv4f64_nxv4f64_nxv4i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vv_nxv4f64_nxv4f64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e64, m4, d1 +; CHECK-NEXT: th.vrgather.vv v16, v8, v12 +; CHECK-NEXT: th.vmv.v.v v8, v16 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vv.nxv4f64.i64( + undef, + %0, + %1, + i64 %2) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vv.mask.nxv4f64.i64( + , + , + , + , + i64); + +define @intrinsic_vrgather_mask_vv_nxv4f64_nxv4f64_nxv4i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv4f64_nxv4f64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e64, m4, d1 +; CHECK-NEXT: th.vrgather.vv v8, v12, v16, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vv.mask.nxv4f64.i64( + %0, + %1, + %2, + %3, + i64 %4) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vv.nxv8f64.i64( + , + , + , + i64); + +define @intrinsic_vrgather_vv_nxv8f64_nxv8f64_nxv8i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vv_nxv8f64_nxv8f64_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e64, m8, d1 +; CHECK-NEXT: th.vrgather.vv v24, v8, v16 +; CHECK-NEXT: th.vmv.v.v v8, v24 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vv.nxv8f64.i64( + undef, + %0, + %1, + i64 %2) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vv.mask.nxv8f64.i64( + , + , + , + , + i64); + +define @intrinsic_vrgather_mask_vv_nxv8f64_nxv8f64_nxv8i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv8f64_nxv8f64_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrr a2, vl +; CHECK-NEXT: csrr a3, vtype +; CHECK-NEXT: th.vsetvli zero, zero, e64, m8, d1 +; CHECK-NEXT: th.vle.v v24, (a0) +; CHECK-NEXT: th.vsetvl zero, a2, a3 +; CHECK-NEXT: th.vsetvli zero, a1, e64, m8, d1 +; CHECK-NEXT: th.vrgather.vv v8, v16, v24, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vv.mask.nxv8f64.i64( + %0, + %1, + %2, + %3, + i64 %4) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vx.nxv8i8.i64( + , + , + i64, + i64); + +define @intrinsic_vrgather_vx_nxv8i8_nxv8i8_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vx_nxv8i8_nxv8i8_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e8, m1, d1 +; CHECK-NEXT: th.vrgather.vx v9, v8, a0 +; CHECK-NEXT: th.vmv.v.v v8, v9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.nxv8i8.i64( + undef, + %0, + i64 %1, + i64 %2) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vx.mask.nxv8i8.i64( + , + , + i64, + , + i64); + +define @intrinsic_vrgather_mask_vx_nxv8i8_nxv8i8_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv8i8_nxv8i8_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e8, m1, d1 +; CHECK-NEXT: th.vrgather.vx v8, v9, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.mask.nxv8i8.i64( + %0, + %1, + i64 %2, + %3, + i64 %4) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vx.nxv16i8.i64( + , + , + i64, + i64); + +define @intrinsic_vrgather_vx_nxv16i8_nxv16i8_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vx_nxv16i8_nxv16i8_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e8, m2, d1 +; CHECK-NEXT: th.vrgather.vx v10, v8, a0 +; CHECK-NEXT: th.vmv.v.v v8, v10 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.nxv16i8.i64( + undef, + %0, + i64 %1, + i64 %2) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vx.mask.nxv16i8.i64( + , + , + i64, + , + i64); + +define @intrinsic_vrgather_mask_vx_nxv16i8_nxv16i8_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv16i8_nxv16i8_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e8, m2, d1 +; CHECK-NEXT: th.vrgather.vx v8, v10, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.mask.nxv16i8.i64( + %0, + %1, + i64 %2, + %3, + i64 %4) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vx.nxv32i8.i64( + , + , + i64, + i64); + +define @intrinsic_vrgather_vx_nxv32i8_nxv32i8_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vx_nxv32i8_nxv32i8_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e8, m4, d1 +; CHECK-NEXT: th.vrgather.vx v12, v8, a0 +; CHECK-NEXT: th.vmv.v.v v8, v12 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.nxv32i8.i64( + undef, + %0, + i64 %1, + i64 %2) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vx.mask.nxv32i8.i64( + , + , + i64, + , + i64); + +define @intrinsic_vrgather_mask_vx_nxv32i8_nxv32i8_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv32i8_nxv32i8_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e8, m4, d1 +; CHECK-NEXT: th.vrgather.vx v8, v12, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.mask.nxv32i8.i64( + %0, + %1, + i64 %2, + %3, + i64 %4) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vx.nxv64i8.i64( + , + , + i64, + i64); + +define @intrinsic_vrgather_vx_nxv64i8_nxv64i8_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vx_nxv64i8_nxv64i8_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e8, m8, d1 +; CHECK-NEXT: th.vrgather.vx v16, v8, a0 +; CHECK-NEXT: th.vmv.v.v v8, v16 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.nxv64i8.i64( + undef, + %0, + i64 %1, + i64 %2) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vx.mask.nxv64i8.i64( + , + , + i64, + , + i64); + +define @intrinsic_vrgather_mask_vx_nxv64i8_nxv64i8_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv64i8_nxv64i8_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e8, m8, d1 +; CHECK-NEXT: th.vrgather.vx v8, v16, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.mask.nxv64i8.i64( + %0, + %1, + i64 %2, + %3, + i64 %4) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vx.nxv4i16.i64( + , + , + i64, + i64); + +define @intrinsic_vrgather_vx_nxv4i16_nxv4i16_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vx_nxv4i16_nxv4i16_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e16, m1, d1 +; CHECK-NEXT: th.vrgather.vx v9, v8, a0 +; CHECK-NEXT: th.vmv.v.v v8, v9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.nxv4i16.i64( + undef, + %0, + i64 %1, + i64 %2) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vx.mask.nxv4i16.i64( + , + , + i64, + , + i64); + +define @intrinsic_vrgather_mask_vx_nxv4i16_nxv4i16_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv4i16_nxv4i16_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e16, m1, d1 +; CHECK-NEXT: th.vrgather.vx v8, v9, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.mask.nxv4i16.i64( + %0, + %1, + i64 %2, + %3, + i64 %4) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vx.nxv8i16.i64( + , + , + i64, + i64); + +define @intrinsic_vrgather_vx_nxv8i16_nxv8i16_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vx_nxv8i16_nxv8i16_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e16, m2, d1 +; CHECK-NEXT: th.vrgather.vx v10, v8, a0 +; CHECK-NEXT: th.vmv.v.v v8, v10 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.nxv8i16.i64( + undef, + %0, + i64 %1, + i64 %2) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vx.mask.nxv8i16.i64( + , + , + i64, + , + i64); + +define @intrinsic_vrgather_mask_vx_nxv8i16_nxv8i16_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv8i16_nxv8i16_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e16, m2, d1 +; CHECK-NEXT: th.vrgather.vx v8, v10, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.mask.nxv8i16.i64( + %0, + %1, + i64 %2, + %3, + i64 %4) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vx.nxv16i16.i64( + , + , + i64, + i64); + +define @intrinsic_vrgather_vx_nxv16i16_nxv16i16_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vx_nxv16i16_nxv16i16_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e16, m4, d1 +; CHECK-NEXT: th.vrgather.vx v12, v8, a0 +; CHECK-NEXT: th.vmv.v.v v8, v12 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.nxv16i16.i64( + undef, + %0, + i64 %1, + i64 %2) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vx.mask.nxv16i16.i64( + , + , + i64, + , + i64); + +define @intrinsic_vrgather_mask_vx_nxv16i16_nxv16i16_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv16i16_nxv16i16_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e16, m4, d1 +; CHECK-NEXT: th.vrgather.vx v8, v12, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.mask.nxv16i16.i64( + %0, + %1, + i64 %2, + %3, + i64 %4) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vx.nxv32i16.i64( + , + , + i64, + i64); + +define @intrinsic_vrgather_vx_nxv32i16_nxv32i16_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vx_nxv32i16_nxv32i16_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e16, m8, d1 +; CHECK-NEXT: th.vrgather.vx v16, v8, a0 +; CHECK-NEXT: th.vmv.v.v v8, v16 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.nxv32i16.i64( + undef, + %0, + i64 %1, + i64 %2) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vx.mask.nxv32i16.i64( + , + , + i64, + , + i64); + +define @intrinsic_vrgather_mask_vx_nxv32i16_nxv32i16_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv32i16_nxv32i16_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e16, m8, d1 +; CHECK-NEXT: th.vrgather.vx v8, v16, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.mask.nxv32i16.i64( + %0, + %1, + i64 %2, + %3, + i64 %4) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vx.nxv2i32.i64( + , + , + i64, + i64); + +define @intrinsic_vrgather_vx_nxv2i32_nxv2i32_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vx_nxv2i32_nxv2i32_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vrgather.vx v9, v8, a0 +; CHECK-NEXT: th.vmv.v.v v8, v9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.nxv2i32.i64( + undef, + %0, + i64 %1, + i64 %2) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vx.mask.nxv2i32.i64( + , + , + i64, + , + i64); + +define @intrinsic_vrgather_mask_vx_nxv2i32_nxv2i32_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv2i32_nxv2i32_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vrgather.vx v8, v9, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.mask.nxv2i32.i64( + %0, + %1, + i64 %2, + %3, + i64 %4) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vx.nxv4i32.i64( + , + , + i64, + i64); + +define @intrinsic_vrgather_vx_nxv4i32_nxv4i32_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vx_nxv4i32_nxv4i32_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vrgather.vx v10, v8, a0 +; CHECK-NEXT: th.vmv.v.v v8, v10 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.nxv4i32.i64( + undef, + %0, + i64 %1, + i64 %2) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vx.mask.nxv4i32.i64( + , + , + i64, + , + i64); + +define @intrinsic_vrgather_mask_vx_nxv4i32_nxv4i32_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv4i32_nxv4i32_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vrgather.vx v8, v10, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.mask.nxv4i32.i64( + %0, + %1, + i64 %2, + %3, + i64 %4) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vx.nxv8i32.i64( + , + , + i64, + i64); + +define @intrinsic_vrgather_vx_nxv8i32_nxv8i32_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vx_nxv8i32_nxv8i32_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vrgather.vx v12, v8, a0 +; CHECK-NEXT: th.vmv.v.v v8, v12 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.nxv8i32.i64( + undef, + %0, + i64 %1, + i64 %2) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vx.mask.nxv8i32.i64( + , + , + i64, + , + i64); + +define @intrinsic_vrgather_mask_vx_nxv8i32_nxv8i32_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv8i32_nxv8i32_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vrgather.vx v8, v12, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.mask.nxv8i32.i64( + %0, + %1, + i64 %2, + %3, + i64 %4) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vx.nxv16i32.i64( + , + , + i64, + i64); + +define @intrinsic_vrgather_vx_nxv16i32_nxv16i32_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vx_nxv16i32_nxv16i32_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e32, m8, d1 +; CHECK-NEXT: th.vrgather.vx v16, v8, a0 +; CHECK-NEXT: th.vmv.v.v v8, v16 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.nxv16i32.i64( + undef, + %0, + i64 %1, + i64 %2) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vx.mask.nxv16i32.i64( + , + , + i64, + , + i64); + +define @intrinsic_vrgather_mask_vx_nxv16i32_nxv16i32_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv16i32_nxv16i32_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e32, m8, d1 +; CHECK-NEXT: th.vrgather.vx v8, v16, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.mask.nxv16i32.i64( + %0, + %1, + i64 %2, + %3, + i64 %4) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vx.nxv1i64.i64( + , + , + i64, + i64); + +define @intrinsic_vrgather_vx_nxv1i64_nxv1i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vx_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e64, m1, d1 +; CHECK-NEXT: th.vrgather.vx v9, v8, a0 +; CHECK-NEXT: th.vmv.v.v v8, v9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.nxv1i64.i64( + undef, + %0, + i64 %1, + i64 %2) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vx.mask.nxv1i64.i64( + , + , + i64, + , + i64); + +define @intrinsic_vrgather_mask_vx_nxv1i64_nxv1i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e64, m1, d1 +; CHECK-NEXT: th.vrgather.vx v8, v9, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.mask.nxv1i64.i64( + %0, + %1, + i64 %2, + %3, + i64 %4) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vx.nxv2i64.i64( + , + , + i64, + i64); + +define @intrinsic_vrgather_vx_nxv2i64_nxv2i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vx_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e64, m2, d1 +; CHECK-NEXT: th.vrgather.vx v10, v8, a0 +; CHECK-NEXT: th.vmv.v.v v8, v10 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.nxv2i64.i64( + undef, + %0, + i64 %1, + i64 %2) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vx.mask.nxv2i64.i64( + , + , + i64, + , + i64); + +define @intrinsic_vrgather_mask_vx_nxv2i64_nxv2i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e64, m2, d1 +; CHECK-NEXT: th.vrgather.vx v8, v10, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.mask.nxv2i64.i64( + %0, + %1, + i64 %2, + %3, + i64 %4) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vx.nxv4i64.i64( + , + , + i64, + i64); + +define @intrinsic_vrgather_vx_nxv4i64_nxv4i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vx_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e64, m4, d1 +; CHECK-NEXT: th.vrgather.vx v12, v8, a0 +; CHECK-NEXT: th.vmv.v.v v8, v12 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.nxv4i64.i64( + undef, + %0, + i64 %1, + i64 %2) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vx.mask.nxv4i64.i64( + , + , + i64, + , + i64); + +define @intrinsic_vrgather_mask_vx_nxv4i64_nxv4i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e64, m4, d1 +; CHECK-NEXT: th.vrgather.vx v8, v12, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.mask.nxv4i64.i64( + %0, + %1, + i64 %2, + %3, + i64 %4) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vx.nxv8i64.i64( + , + , + i64, + i64); + +define @intrinsic_vrgather_vx_nxv8i64_nxv8i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vx_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e64, m8, d1 +; CHECK-NEXT: th.vrgather.vx v16, v8, a0 +; CHECK-NEXT: th.vmv.v.v v8, v16 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.nxv8i64.i64( + undef, + %0, + i64 %1, + i64 %2) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vx.mask.nxv8i64.i64( + , + , + i64, + , + i64); + +define @intrinsic_vrgather_mask_vx_nxv8i64_nxv8i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e64, m8, d1 +; CHECK-NEXT: th.vrgather.vx v8, v16, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.mask.nxv8i64.i64( + %0, + %1, + i64 %2, + %3, + i64 %4) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vx.nxv4f16.i64( + , + , + i64, + i64); + +define @intrinsic_vrgather_vx_nxv4f16_nxv4f16_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vx_nxv4f16_nxv4f16_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e16, m1, d1 +; CHECK-NEXT: th.vrgather.vx v9, v8, a0 +; CHECK-NEXT: th.vmv.v.v v8, v9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.nxv4f16.i64( + undef, + %0, + i64 %1, + i64 %2) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vx.mask.nxv4f16.i64( + , + , + i64, + , + i64); + +define @intrinsic_vrgather_mask_vx_nxv4f16_nxv4f16_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv4f16_nxv4f16_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e16, m1, d1 +; CHECK-NEXT: th.vrgather.vx v8, v9, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.mask.nxv4f16.i64( + %0, + %1, + i64 %2, + %3, + i64 %4) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vx.nxv8f16.i64( + , + , + i64, + i64); + +define @intrinsic_vrgather_vx_nxv8f16_nxv8f16_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vx_nxv8f16_nxv8f16_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e16, m2, d1 +; CHECK-NEXT: th.vrgather.vx v10, v8, a0 +; CHECK-NEXT: th.vmv.v.v v8, v10 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.nxv8f16.i64( + undef, + %0, + i64 %1, + i64 %2) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vx.mask.nxv8f16.i64( + , + , + i64, + , + i64); + +define @intrinsic_vrgather_mask_vx_nxv8f16_nxv8f16_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv8f16_nxv8f16_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e16, m2, d1 +; CHECK-NEXT: th.vrgather.vx v8, v10, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.mask.nxv8f16.i64( + %0, + %1, + i64 %2, + %3, + i64 %4) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vx.nxv16f16.i64( + , + , + i64, + i64); + +define @intrinsic_vrgather_vx_nxv16f16_nxv16f16_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vx_nxv16f16_nxv16f16_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e16, m4, d1 +; CHECK-NEXT: th.vrgather.vx v12, v8, a0 +; CHECK-NEXT: th.vmv.v.v v8, v12 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.nxv16f16.i64( + undef, + %0, + i64 %1, + i64 %2) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vx.mask.nxv16f16.i64( + , + , + i64, + , + i64); + +define @intrinsic_vrgather_mask_vx_nxv16f16_nxv16f16_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv16f16_nxv16f16_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e16, m4, d1 +; CHECK-NEXT: th.vrgather.vx v8, v12, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.mask.nxv16f16.i64( + %0, + %1, + i64 %2, + %3, + i64 %4) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vx.nxv32f16.i64( + , + , + i64, + i64); + +define @intrinsic_vrgather_vx_nxv32f16_nxv32f16_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vx_nxv32f16_nxv32f16_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e16, m8, d1 +; CHECK-NEXT: th.vrgather.vx v16, v8, a0 +; CHECK-NEXT: th.vmv.v.v v8, v16 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.nxv32f16.i64( + undef, + %0, + i64 %1, + i64 %2) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vx.mask.nxv32f16.i64( + , + , + i64, + , + i64); + +define @intrinsic_vrgather_mask_vx_nxv32f16_nxv32f16_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv32f16_nxv32f16_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e16, m8, d1 +; CHECK-NEXT: th.vrgather.vx v8, v16, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.mask.nxv32f16.i64( + %0, + %1, + i64 %2, + %3, + i64 %4) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vx.nxv2f32.i64( + , + , + i64, + i64); + +define @intrinsic_vrgather_vx_nxv2f32_nxv2f32_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vx_nxv2f32_nxv2f32_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vrgather.vx v9, v8, a0 +; CHECK-NEXT: th.vmv.v.v v8, v9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.nxv2f32.i64( + undef, + %0, + i64 %1, + i64 %2) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vx.mask.nxv2f32.i64( + , + , + i64, + , + i64); + +define @intrinsic_vrgather_mask_vx_nxv2f32_nxv2f32_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv2f32_nxv2f32_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vrgather.vx v8, v9, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.mask.nxv2f32.i64( + %0, + %1, + i64 %2, + %3, + i64 %4) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vx.nxv4f32.i64( + , + , + i64, + i64); + +define @intrinsic_vrgather_vx_nxv4f32_nxv4f32_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vx_nxv4f32_nxv4f32_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vrgather.vx v10, v8, a0 +; CHECK-NEXT: th.vmv.v.v v8, v10 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.nxv4f32.i64( + undef, + %0, + i64 %1, + i64 %2) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vx.mask.nxv4f32.i64( + , + , + i64, + , + i64); + +define @intrinsic_vrgather_mask_vx_nxv4f32_nxv4f32_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv4f32_nxv4f32_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vrgather.vx v8, v10, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.mask.nxv4f32.i64( + %0, + %1, + i64 %2, + %3, + i64 %4) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vx.nxv8f32.i64( + , + , + i64, + i64); + +define @intrinsic_vrgather_vx_nxv8f32_nxv8f32_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vx_nxv8f32_nxv8f32_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vrgather.vx v12, v8, a0 +; CHECK-NEXT: th.vmv.v.v v8, v12 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.nxv8f32.i64( + undef, + %0, + i64 %1, + i64 %2) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vx.mask.nxv8f32.i64( + , + , + i64, + , + i64); + +define @intrinsic_vrgather_mask_vx_nxv8f32_nxv8f32_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv8f32_nxv8f32_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vrgather.vx v8, v12, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.mask.nxv8f32.i64( + %0, + %1, + i64 %2, + %3, + i64 %4) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vx.nxv16f32.i64( + , + , + i64, + i64); + +define @intrinsic_vrgather_vx_nxv16f32_nxv16f32_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vx_nxv16f32_nxv16f32_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e32, m8, d1 +; CHECK-NEXT: th.vrgather.vx v16, v8, a0 +; CHECK-NEXT: th.vmv.v.v v8, v16 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.nxv16f32.i64( + undef, + %0, + i64 %1, + i64 %2) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vx.mask.nxv16f32.i64( + , + , + i64, + , + i64); + +define @intrinsic_vrgather_mask_vx_nxv16f32_nxv16f32_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv16f32_nxv16f32_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e32, m8, d1 +; CHECK-NEXT: th.vrgather.vx v8, v16, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.mask.nxv16f32.i64( + %0, + %1, + i64 %2, + %3, + i64 %4) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vx.nxv1f64.i64( + , + , + i64, + i64); + +define @intrinsic_vrgather_vx_nxv1f64_nxv1f64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vx_nxv1f64_nxv1f64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e64, m1, d1 +; CHECK-NEXT: th.vrgather.vx v9, v8, a0 +; CHECK-NEXT: th.vmv.v.v v8, v9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.nxv1f64.i64( + undef, + %0, + i64 %1, + i64 %2) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vx.mask.nxv1f64.i64( + , + , + i64, + , + i64); + +define @intrinsic_vrgather_mask_vx_nxv1f64_nxv1f64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv1f64_nxv1f64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e64, m1, d1 +; CHECK-NEXT: th.vrgather.vx v8, v9, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.mask.nxv1f64.i64( + %0, + %1, + i64 %2, + %3, + i64 %4) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vx.nxv2f64.i64( + , + , + i64, + i64); + +define @intrinsic_vrgather_vx_nxv2f64_nxv2f64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vx_nxv2f64_nxv2f64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e64, m2, d1 +; CHECK-NEXT: th.vrgather.vx v10, v8, a0 +; CHECK-NEXT: th.vmv.v.v v8, v10 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.nxv2f64.i64( + undef, + %0, + i64 %1, + i64 %2) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vx.mask.nxv2f64.i64( + , + , + i64, + , + i64); + +define @intrinsic_vrgather_mask_vx_nxv2f64_nxv2f64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv2f64_nxv2f64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e64, m2, d1 +; CHECK-NEXT: th.vrgather.vx v8, v10, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.mask.nxv2f64.i64( + %0, + %1, + i64 %2, + %3, + i64 %4) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vx.nxv4f64.i64( + , + , + i64, + i64); + +define @intrinsic_vrgather_vx_nxv4f64_nxv4f64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vx_nxv4f64_nxv4f64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e64, m4, d1 +; CHECK-NEXT: th.vrgather.vx v12, v8, a0 +; CHECK-NEXT: th.vmv.v.v v8, v12 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.nxv4f64.i64( + undef, + %0, + i64 %1, + i64 %2) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vx.mask.nxv4f64.i64( + , + , + i64, + , + i64); + +define @intrinsic_vrgather_mask_vx_nxv4f64_nxv4f64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv4f64_nxv4f64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e64, m4, d1 +; CHECK-NEXT: th.vrgather.vx v8, v12, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.mask.nxv4f64.i64( + %0, + %1, + i64 %2, + %3, + i64 %4) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vx.nxv8f64.i64( + , + , + i64, + i64); + +define @intrinsic_vrgather_vx_nxv8f64_nxv8f64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vx_nxv8f64_nxv8f64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e64, m8, d1 +; CHECK-NEXT: th.vrgather.vx v16, v8, a0 +; CHECK-NEXT: th.vmv.v.v v8, v16 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.nxv8f64.i64( + undef, + %0, + i64 %1, + i64 %2) + + ret %a +} + +declare @llvm.riscv.th.vrgather.vx.mask.nxv8f64.i64( + , + , + i64, + , + i64); + +define @intrinsic_vrgather_mask_vx_nxv8f64_nxv8f64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv8f64_nxv8f64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e64, m8, d1 +; CHECK-NEXT: th.vrgather.vx v8, v16, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.mask.nxv8f64.i64( + %0, + %1, + i64 %2, + %3, + i64 %4) + + ret %a +} + +define @intrinsic_vrgather_vi_nxv8i8_nxv8i8_i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vi_nxv8i8_nxv8i8_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e8, m1, d1 +; CHECK-NEXT: th.vrgather.vi v9, v8, 9 +; CHECK-NEXT: th.vmv.v.v v8, v9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.nxv8i8.i64( + undef, + %0, + i64 9, + i64 %1) + + ret %a +} + +define @intrinsic_vrgather_mask_vi_nxv8i8_nxv8i8_i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv8i8_nxv8i8_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e8, m1, d1 +; CHECK-NEXT: th.vrgather.vi v8, v9, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.mask.nxv8i8.i64( + %0, + %1, + i64 9, + %2, + i64 %3) + + ret %a +} + +define @intrinsic_vrgather_vi_nxv16i8_nxv16i8_i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vi_nxv16i8_nxv16i8_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e8, m2, d1 +; CHECK-NEXT: th.vrgather.vi v10, v8, 9 +; CHECK-NEXT: th.vmv.v.v v8, v10 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.nxv16i8.i64( + undef, + %0, + i64 9, + i64 %1) + + ret %a +} + +define @intrinsic_vrgather_mask_vi_nxv16i8_nxv16i8_i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv16i8_nxv16i8_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e8, m2, d1 +; CHECK-NEXT: th.vrgather.vi v8, v10, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.mask.nxv16i8.i64( + %0, + %1, + i64 9, + %2, + i64 %3) + + ret %a +} + +define @intrinsic_vrgather_vi_nxv32i8_nxv32i8_i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vi_nxv32i8_nxv32i8_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e8, m4, d1 +; CHECK-NEXT: th.vrgather.vi v12, v8, 9 +; CHECK-NEXT: th.vmv.v.v v8, v12 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.nxv32i8.i64( + undef, + %0, + i64 9, + i64 %1) + + ret %a +} + +define @intrinsic_vrgather_mask_vi_nxv32i8_nxv32i8_i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv32i8_nxv32i8_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e8, m4, d1 +; CHECK-NEXT: th.vrgather.vi v8, v12, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.mask.nxv32i8.i64( + %0, + %1, + i64 9, + %2, + i64 %3) + + ret %a +} + +define @intrinsic_vrgather_vi_nxv64i8_nxv64i8_i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vi_nxv64i8_nxv64i8_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e8, m8, d1 +; CHECK-NEXT: th.vrgather.vi v16, v8, 9 +; CHECK-NEXT: th.vmv.v.v v8, v16 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.nxv64i8.i64( + undef, + %0, + i64 9, + i64 %1) + + ret %a +} + +define @intrinsic_vrgather_mask_vi_nxv64i8_nxv64i8_i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv64i8_nxv64i8_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e8, m8, d1 +; CHECK-NEXT: th.vrgather.vi v8, v16, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.mask.nxv64i8.i64( + %0, + %1, + i64 9, + %2, + i64 %3) + + ret %a +} + +define @intrinsic_vrgather_vi_nxv4i16_nxv4i16_i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vi_nxv4i16_nxv4i16_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e16, m1, d1 +; CHECK-NEXT: th.vrgather.vi v9, v8, 9 +; CHECK-NEXT: th.vmv.v.v v8, v9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.nxv4i16.i64( + undef, + %0, + i64 9, + i64 %1) + + ret %a +} + +define @intrinsic_vrgather_mask_vi_nxv4i16_nxv4i16_i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv4i16_nxv4i16_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e16, m1, d1 +; CHECK-NEXT: th.vrgather.vi v8, v9, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.mask.nxv4i16.i64( + %0, + %1, + i64 9, + %2, + i64 %3) + + ret %a +} + +define @intrinsic_vrgather_vi_nxv8i16_nxv8i16_i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vi_nxv8i16_nxv8i16_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e16, m2, d1 +; CHECK-NEXT: th.vrgather.vi v10, v8, 9 +; CHECK-NEXT: th.vmv.v.v v8, v10 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.nxv8i16.i64( + undef, + %0, + i64 9, + i64 %1) + + ret %a +} + +define @intrinsic_vrgather_mask_vi_nxv8i16_nxv8i16_i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv8i16_nxv8i16_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e16, m2, d1 +; CHECK-NEXT: th.vrgather.vi v8, v10, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.mask.nxv8i16.i64( + %0, + %1, + i64 9, + %2, + i64 %3) + + ret %a +} + +define @intrinsic_vrgather_vi_nxv16i16_nxv16i16_i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vi_nxv16i16_nxv16i16_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e16, m4, d1 +; CHECK-NEXT: th.vrgather.vi v12, v8, 9 +; CHECK-NEXT: th.vmv.v.v v8, v12 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.nxv16i16.i64( + undef, + %0, + i64 9, + i64 %1) + + ret %a +} + +define @intrinsic_vrgather_mask_vi_nxv16i16_nxv16i16_i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv16i16_nxv16i16_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e16, m4, d1 +; CHECK-NEXT: th.vrgather.vi v8, v12, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.mask.nxv16i16.i64( + %0, + %1, + i64 9, + %2, + i64 %3) + + ret %a +} + +define @intrinsic_vrgather_vi_nxv32i16_nxv32i16_i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vi_nxv32i16_nxv32i16_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e16, m8, d1 +; CHECK-NEXT: th.vrgather.vi v16, v8, 9 +; CHECK-NEXT: th.vmv.v.v v8, v16 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.nxv32i16.i64( + undef, + %0, + i64 9, + i64 %1) + + ret %a +} + +define @intrinsic_vrgather_mask_vi_nxv32i16_nxv32i16_i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv32i16_nxv32i16_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e16, m8, d1 +; CHECK-NEXT: th.vrgather.vi v8, v16, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.mask.nxv32i16.i64( + %0, + %1, + i64 9, + %2, + i64 %3) + + ret %a +} + +define @intrinsic_vrgather_vi_nxv2i32_nxv2i32_i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vi_nxv2i32_nxv2i32_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e32, m1, d1 +; CHECK-NEXT: th.vrgather.vi v9, v8, 9 +; CHECK-NEXT: th.vmv.v.v v8, v9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.nxv2i32.i64( + undef, + %0, + i64 9, + i64 %1) + + ret %a +} + +define @intrinsic_vrgather_mask_vi_nxv2i32_nxv2i32_i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv2i32_nxv2i32_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e32, m1, d1 +; CHECK-NEXT: th.vrgather.vi v8, v9, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.mask.nxv2i32.i64( + %0, + %1, + i64 9, + %2, + i64 %3) + + ret %a +} + +define @intrinsic_vrgather_vi_nxv4i32_nxv4i32_i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vi_nxv4i32_nxv4i32_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e32, m2, d1 +; CHECK-NEXT: th.vrgather.vi v10, v8, 9 +; CHECK-NEXT: th.vmv.v.v v8, v10 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.nxv4i32.i64( + undef, + %0, + i64 9, + i64 %1) + + ret %a +} + +define @intrinsic_vrgather_mask_vi_nxv4i32_nxv4i32_i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv4i32_nxv4i32_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e32, m2, d1 +; CHECK-NEXT: th.vrgather.vi v8, v10, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.mask.nxv4i32.i64( + %0, + %1, + i64 9, + %2, + i64 %3) + + ret %a +} + +define @intrinsic_vrgather_vi_nxv8i32_nxv8i32_i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vi_nxv8i32_nxv8i32_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e32, m4, d1 +; CHECK-NEXT: th.vrgather.vi v12, v8, 9 +; CHECK-NEXT: th.vmv.v.v v8, v12 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.nxv8i32.i64( + undef, + %0, + i64 9, + i64 %1) + + ret %a +} + +define @intrinsic_vrgather_mask_vi_nxv8i32_nxv8i32_i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv8i32_nxv8i32_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e32, m4, d1 +; CHECK-NEXT: th.vrgather.vi v8, v12, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.mask.nxv8i32.i64( + %0, + %1, + i64 9, + %2, + i64 %3) + + ret %a +} + +define @intrinsic_vrgather_vi_nxv16i32_nxv16i32_i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vi_nxv16i32_nxv16i32_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e32, m8, d1 +; CHECK-NEXT: th.vrgather.vi v16, v8, 9 +; CHECK-NEXT: th.vmv.v.v v8, v16 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.nxv16i32.i64( + undef, + %0, + i64 9, + i64 %1) + + ret %a +} + +define @intrinsic_vrgather_mask_vi_nxv16i32_nxv16i32_i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv16i32_nxv16i32_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e32, m8, d1 +; CHECK-NEXT: th.vrgather.vi v8, v16, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.mask.nxv16i32.i64( + %0, + %1, + i64 9, + %2, + i64 %3) + + ret %a +} + +define @intrinsic_vrgather_vi_nxv1i64_nxv1i64_i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vi_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e64, m1, d1 +; CHECK-NEXT: th.vrgather.vi v9, v8, 9 +; CHECK-NEXT: th.vmv.v.v v8, v9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.nxv1i64.i64( + undef, + %0, + i64 9, + i64 %1) + + ret %a +} + +define @intrinsic_vrgather_mask_vi_nxv1i64_nxv1i64_i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e64, m1, d1 +; CHECK-NEXT: th.vrgather.vi v8, v9, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.mask.nxv1i64.i64( + %0, + %1, + i64 9, + %2, + i64 %3) + + ret %a +} + +define @intrinsic_vrgather_vi_nxv2i64_nxv2i64_i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vi_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e64, m2, d1 +; CHECK-NEXT: th.vrgather.vi v10, v8, 9 +; CHECK-NEXT: th.vmv.v.v v8, v10 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.nxv2i64.i64( + undef, + %0, + i64 9, + i64 %1) + + ret %a +} + +define @intrinsic_vrgather_mask_vi_nxv2i64_nxv2i64_i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e64, m2, d1 +; CHECK-NEXT: th.vrgather.vi v8, v10, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.mask.nxv2i64.i64( + %0, + %1, + i64 9, + %2, + i64 %3) + + ret %a +} + +define @intrinsic_vrgather_vi_nxv4i64_nxv4i64_i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vi_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e64, m4, d1 +; CHECK-NEXT: th.vrgather.vi v12, v8, 9 +; CHECK-NEXT: th.vmv.v.v v8, v12 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.nxv4i64.i64( + undef, + %0, + i64 9, + i64 %1) + + ret %a +} + +define @intrinsic_vrgather_mask_vi_nxv4i64_nxv4i64_i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e64, m4, d1 +; CHECK-NEXT: th.vrgather.vi v8, v12, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.mask.nxv4i64.i64( + %0, + %1, + i64 9, + %2, + i64 %3) + + ret %a +} + +define @intrinsic_vrgather_vi_nxv8i64_nxv8i64_i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vi_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e64, m8, d1 +; CHECK-NEXT: th.vrgather.vi v16, v8, 9 +; CHECK-NEXT: th.vmv.v.v v8, v16 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.nxv8i64.i64( + undef, + %0, + i64 9, + i64 %1) + + ret %a +} + +define @intrinsic_vrgather_mask_vi_nxv8i64_nxv8i64_i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e64, m8, d1 +; CHECK-NEXT: th.vrgather.vi v8, v16, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.mask.nxv8i64.i64( + %0, + %1, + i64 9, + %2, + i64 %3) + + ret %a +} + +define @intrinsic_vrgather_vi_nxv4f16_nxv4f16_i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vi_nxv4f16_nxv4f16_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e16, m1, d1 +; CHECK-NEXT: th.vrgather.vi v9, v8, 9 +; CHECK-NEXT: th.vmv.v.v v8, v9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.nxv4f16.i64( + undef, + %0, + i64 9, + i64 %1) + + ret %a +} + +define @intrinsic_vrgather_mask_vi_nxv4f16_nxv4f16_i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv4f16_nxv4f16_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e16, m1, d1 +; CHECK-NEXT: th.vrgather.vi v8, v9, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.mask.nxv4f16.i64( + %0, + %1, + i64 9, + %2, + i64 %3) + + ret %a +} + +define @intrinsic_vrgather_vi_nxv8f16_nxv8f16_i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vi_nxv8f16_nxv8f16_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e16, m2, d1 +; CHECK-NEXT: th.vrgather.vi v10, v8, 9 +; CHECK-NEXT: th.vmv.v.v v8, v10 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.nxv8f16.i64( + undef, + %0, + i64 9, + i64 %1) + + ret %a +} + +define @intrinsic_vrgather_mask_vi_nxv8f16_nxv8f16_i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv8f16_nxv8f16_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e16, m2, d1 +; CHECK-NEXT: th.vrgather.vi v8, v10, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.mask.nxv8f16.i64( + %0, + %1, + i64 9, + %2, + i64 %3) + + ret %a +} + +define @intrinsic_vrgather_vi_nxv16f16_nxv16f16_i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vi_nxv16f16_nxv16f16_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e16, m4, d1 +; CHECK-NEXT: th.vrgather.vi v12, v8, 9 +; CHECK-NEXT: th.vmv.v.v v8, v12 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.nxv16f16.i64( + undef, + %0, + i64 9, + i64 %1) + + ret %a +} + +define @intrinsic_vrgather_mask_vi_nxv16f16_nxv16f16_i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv16f16_nxv16f16_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e16, m4, d1 +; CHECK-NEXT: th.vrgather.vi v8, v12, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.mask.nxv16f16.i64( + %0, + %1, + i64 9, + %2, + i64 %3) + + ret %a +} + +define @intrinsic_vrgather_vi_nxv32f16_nxv32f16_i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vi_nxv32f16_nxv32f16_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e16, m8, d1 +; CHECK-NEXT: th.vrgather.vi v16, v8, 9 +; CHECK-NEXT: th.vmv.v.v v8, v16 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.nxv32f16.i64( + undef, + %0, + i64 9, + i64 %1) + + ret %a +} + +define @intrinsic_vrgather_mask_vi_nxv32f16_nxv32f16_i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv32f16_nxv32f16_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e16, m8, d1 +; CHECK-NEXT: th.vrgather.vi v8, v16, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.mask.nxv32f16.i64( + %0, + %1, + i64 9, + %2, + i64 %3) + + ret %a +} + +define @intrinsic_vrgather_vi_nxv2f32_nxv2f32_i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vi_nxv2f32_nxv2f32_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e32, m1, d1 +; CHECK-NEXT: th.vrgather.vi v9, v8, 9 +; CHECK-NEXT: th.vmv.v.v v8, v9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.nxv2f32.i64( + undef, + %0, + i64 9, + i64 %1) + + ret %a +} + +define @intrinsic_vrgather_mask_vi_nxv2f32_nxv2f32_i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv2f32_nxv2f32_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e32, m1, d1 +; CHECK-NEXT: th.vrgather.vi v8, v9, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.mask.nxv2f32.i64( + %0, + %1, + i64 9, + %2, + i64 %3) + + ret %a +} + +define @intrinsic_vrgather_vi_nxv4f32_nxv4f32_i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vi_nxv4f32_nxv4f32_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e32, m2, d1 +; CHECK-NEXT: th.vrgather.vi v10, v8, 9 +; CHECK-NEXT: th.vmv.v.v v8, v10 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.nxv4f32.i64( + undef, + %0, + i64 9, + i64 %1) + + ret %a +} + +define @intrinsic_vrgather_mask_vi_nxv4f32_nxv4f32_i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv4f32_nxv4f32_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e32, m2, d1 +; CHECK-NEXT: th.vrgather.vi v8, v10, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.mask.nxv4f32.i64( + %0, + %1, + i64 9, + %2, + i64 %3) + + ret %a +} + +define @intrinsic_vrgather_vi_nxv8f32_nxv8f32_i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vi_nxv8f32_nxv8f32_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e32, m4, d1 +; CHECK-NEXT: th.vrgather.vi v12, v8, 9 +; CHECK-NEXT: th.vmv.v.v v8, v12 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.nxv8f32.i64( + undef, + %0, + i64 9, + i64 %1) + + ret %a +} + +define @intrinsic_vrgather_mask_vi_nxv8f32_nxv8f32_i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv8f32_nxv8f32_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e32, m4, d1 +; CHECK-NEXT: th.vrgather.vi v8, v12, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.mask.nxv8f32.i64( + %0, + %1, + i64 9, + %2, + i64 %3) + + ret %a +} + +define @intrinsic_vrgather_vi_nxv16f32_nxv16f32_i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vi_nxv16f32_nxv16f32_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e32, m8, d1 +; CHECK-NEXT: th.vrgather.vi v16, v8, 9 +; CHECK-NEXT: th.vmv.v.v v8, v16 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.nxv16f32.i64( + undef, + %0, + i64 9, + i64 %1) + + ret %a +} + +define @intrinsic_vrgather_mask_vi_nxv16f32_nxv16f32_i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv16f32_nxv16f32_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e32, m8, d1 +; CHECK-NEXT: th.vrgather.vi v8, v16, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.mask.nxv16f32.i64( + %0, + %1, + i64 9, + %2, + i64 %3) + + ret %a +} + +define @intrinsic_vrgather_vi_nxv1f64_nxv1f64_i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vi_nxv1f64_nxv1f64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e64, m1, d1 +; CHECK-NEXT: th.vrgather.vi v9, v8, 9 +; CHECK-NEXT: th.vmv.v.v v8, v9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.nxv1f64.i64( + undef, + %0, + i64 9, + i64 %1) + + ret %a +} + +define @intrinsic_vrgather_mask_vi_nxv1f64_nxv1f64_i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv1f64_nxv1f64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e64, m1, d1 +; CHECK-NEXT: th.vrgather.vi v8, v9, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.mask.nxv1f64.i64( + %0, + %1, + i64 9, + %2, + i64 %3) + + ret %a +} + +define @intrinsic_vrgather_vi_nxv2f64_nxv2f64_i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vi_nxv2f64_nxv2f64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e64, m2, d1 +; CHECK-NEXT: th.vrgather.vi v10, v8, 9 +; CHECK-NEXT: th.vmv.v.v v8, v10 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.nxv2f64.i64( + undef, + %0, + i64 9, + i64 %1) + + ret %a +} + +define @intrinsic_vrgather_mask_vi_nxv2f64_nxv2f64_i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv2f64_nxv2f64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e64, m2, d1 +; CHECK-NEXT: th.vrgather.vi v8, v10, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.mask.nxv2f64.i64( + %0, + %1, + i64 9, + %2, + i64 %3) + + ret %a +} + +define @intrinsic_vrgather_vi_nxv4f64_nxv4f64_i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vi_nxv4f64_nxv4f64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e64, m4, d1 +; CHECK-NEXT: th.vrgather.vi v12, v8, 9 +; CHECK-NEXT: th.vmv.v.v v8, v12 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.nxv4f64.i64( + undef, + %0, + i64 9, + i64 %1) + + ret %a +} + +define @intrinsic_vrgather_mask_vi_nxv4f64_nxv4f64_i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv4f64_nxv4f64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e64, m4, d1 +; CHECK-NEXT: th.vrgather.vi v8, v12, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.mask.nxv4f64.i64( + %0, + %1, + i64 9, + %2, + i64 %3) + + ret %a +} + +define @intrinsic_vrgather_vi_nxv8f64_nxv8f64_i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vrgather_vi_nxv8f64_nxv8f64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e64, m8, d1 +; CHECK-NEXT: th.vrgather.vi v16, v8, 9 +; CHECK-NEXT: th.vmv.v.v v8, v16 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.nxv8f64.i64( + undef, + %0, + i64 9, + i64 %1) + + ret %a +} + +define @intrinsic_vrgather_mask_vi_nxv8f64_nxv8f64_i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv8f64_nxv8f64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e64, m8, d1 +; CHECK-NEXT: th.vrgather.vi v8, v16, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vrgather.vx.mask.nxv8f64.i64( + %0, + %1, + i64 9, + %2, + i64 %3) + + ret %a +} diff --git a/llvm/test/CodeGen/RISCV/rvv0p71/vslide1down-rv32.ll b/llvm/test/CodeGen/RISCV/rvv0p71/vslide1down-rv32.ll new file mode 100644 index 00000000000000..fd2428f38bbc9c --- /dev/null +++ b/llvm/test/CodeGen/RISCV/rvv0p71/vslide1down-rv32.ll @@ -0,0 +1,561 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=riscv32 -mattr=+xtheadvector,+d -verify-machineinstrs \ +; RUN: < %s | FileCheck %s + +declare @llvm.riscv.th.vslide1down.nxv8i8.i8( + , + , + i8, + i32); + +define @intrinsic_vslide1down_vx_nxv8i8_nxv8i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vslide1down_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e8, m1, d1 +; CHECK-NEXT: th.vslide1down.vx v8, v8, a0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslide1down.nxv8i8.i8( + undef, + %0, + i8 %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.th.vslide1down.mask.nxv8i8.i8( + , + , + i8, + , + i32); + +define @intrinsic_vslide1down_mask_vx_nxv8i8_nxv8i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e8, m1, d1 +; CHECK-NEXT: th.vslide1down.vx v8, v9, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslide1down.mask.nxv8i8.i8( + %0, + %1, + i8 %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.th.vslide1down.nxv16i8.i8( + , + , + i8, + i32); + +define @intrinsic_vslide1down_vx_nxv16i8_nxv16i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vslide1down_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e8, m2, d1 +; CHECK-NEXT: th.vslide1down.vx v8, v8, a0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslide1down.nxv16i8.i8( + undef, + %0, + i8 %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.th.vslide1down.mask.nxv16i8.i8( + , + , + i8, + , + i32); + +define @intrinsic_vslide1down_mask_vx_nxv16i8_nxv16i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e8, m2, d1 +; CHECK-NEXT: th.vslide1down.vx v8, v10, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslide1down.mask.nxv16i8.i8( + %0, + %1, + i8 %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.th.vslide1down.nxv32i8.i8( + , + , + i8, + i32); + +define @intrinsic_vslide1down_vx_nxv32i8_nxv32i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vslide1down_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e8, m4, d1 +; CHECK-NEXT: th.vslide1down.vx v8, v8, a0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslide1down.nxv32i8.i8( + undef, + %0, + i8 %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.th.vslide1down.mask.nxv32i8.i8( + , + , + i8, + , + i32); + +define @intrinsic_vslide1down_mask_vx_nxv32i8_nxv32i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e8, m4, d1 +; CHECK-NEXT: th.vslide1down.vx v8, v12, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslide1down.mask.nxv32i8.i8( + %0, + %1, + i8 %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.th.vslide1down.nxv64i8.i8( + , + , + i8, + i32); + +define @intrinsic_vslide1down_vx_nxv64i8_nxv64i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vslide1down_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e8, m8, d1 +; CHECK-NEXT: th.vslide1down.vx v8, v8, a0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslide1down.nxv64i8.i8( + undef, + %0, + i8 %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.th.vslide1down.mask.nxv64i8.i8( + , + , + i8, + , + i32); + +define @intrinsic_vslide1down_mask_vx_nxv64i8_nxv64i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e8, m8, d1 +; CHECK-NEXT: th.vslide1down.vx v8, v16, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslide1down.mask.nxv64i8.i8( + %0, + %1, + i8 %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.th.vslide1down.nxv4i16.i16( + , + , + i16, + i32); + +define @intrinsic_vslide1down_vx_nxv4i16_nxv4i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vslide1down_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e16, m1, d1 +; CHECK-NEXT: th.vslide1down.vx v8, v8, a0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslide1down.nxv4i16.i16( + undef, + %0, + i16 %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.th.vslide1down.mask.nxv4i16.i16( + , + , + i16, + , + i32); + +define @intrinsic_vslide1down_mask_vx_nxv4i16_nxv4i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e16, m1, d1 +; CHECK-NEXT: th.vslide1down.vx v8, v9, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslide1down.mask.nxv4i16.i16( + %0, + %1, + i16 %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.th.vslide1down.nxv8i16.i16( + , + , + i16, + i32); + +define @intrinsic_vslide1down_vx_nxv8i16_nxv8i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vslide1down_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e16, m2, d1 +; CHECK-NEXT: th.vslide1down.vx v8, v8, a0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslide1down.nxv8i16.i16( + undef, + %0, + i16 %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.th.vslide1down.mask.nxv8i16.i16( + , + , + i16, + , + i32); + +define @intrinsic_vslide1down_mask_vx_nxv8i16_nxv8i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e16, m2, d1 +; CHECK-NEXT: th.vslide1down.vx v8, v10, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslide1down.mask.nxv8i16.i16( + %0, + %1, + i16 %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.th.vslide1down.nxv16i16.i16( + , + , + i16, + i32); + +define @intrinsic_vslide1down_vx_nxv16i16_nxv16i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vslide1down_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e16, m4, d1 +; CHECK-NEXT: th.vslide1down.vx v8, v8, a0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslide1down.nxv16i16.i16( + undef, + %0, + i16 %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.th.vslide1down.mask.nxv16i16.i16( + , + , + i16, + , + i32); + +define @intrinsic_vslide1down_mask_vx_nxv16i16_nxv16i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e16, m4, d1 +; CHECK-NEXT: th.vslide1down.vx v8, v12, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslide1down.mask.nxv16i16.i16( + %0, + %1, + i16 %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.th.vslide1down.nxv32i16.i16( + , + , + i16, + i32); + +define @intrinsic_vslide1down_vx_nxv32i16_nxv32i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vslide1down_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e16, m8, d1 +; CHECK-NEXT: th.vslide1down.vx v8, v8, a0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslide1down.nxv32i16.i16( + undef, + %0, + i16 %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.th.vslide1down.mask.nxv32i16.i16( + , + , + i16, + , + i32); + +define @intrinsic_vslide1down_mask_vx_nxv32i16_nxv32i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e16, m8, d1 +; CHECK-NEXT: th.vslide1down.vx v8, v16, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslide1down.mask.nxv32i16.i16( + %0, + %1, + i16 %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.th.vslide1down.nxv2i32.i32( + , + , + i32, + i32); + +define @intrinsic_vslide1down_vx_nxv2i32_nxv2i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vslide1down_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vslide1down.vx v8, v8, a0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslide1down.nxv2i32.i32( + undef, + %0, + i32 %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.th.vslide1down.mask.nxv2i32.i32( + , + , + i32, + , + i32); + +define @intrinsic_vslide1down_mask_vx_nxv2i32_nxv2i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vslide1down.vx v8, v9, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslide1down.mask.nxv2i32.i32( + %0, + %1, + i32 %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.th.vslide1down.nxv4i32.i32( + , + , + i32, + i32); + +define @intrinsic_vslide1down_vx_nxv4i32_nxv4i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vslide1down_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vslide1down.vx v8, v8, a0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslide1down.nxv4i32.i32( + undef, + %0, + i32 %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.th.vslide1down.mask.nxv4i32.i32( + , + , + i32, + , + i32); + +define @intrinsic_vslide1down_mask_vx_nxv4i32_nxv4i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vslide1down.vx v8, v10, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslide1down.mask.nxv4i32.i32( + %0, + %1, + i32 %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.th.vslide1down.nxv8i32.i32( + , + , + i32, + i32); + +define @intrinsic_vslide1down_vx_nxv8i32_nxv8i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vslide1down_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vslide1down.vx v8, v8, a0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslide1down.nxv8i32.i32( + undef, + %0, + i32 %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.th.vslide1down.mask.nxv8i32.i32( + , + , + i32, + , + i32); + +define @intrinsic_vslide1down_mask_vx_nxv8i32_nxv8i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vslide1down.vx v8, v12, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslide1down.mask.nxv8i32.i32( + %0, + %1, + i32 %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.th.vslide1down.nxv16i32.i32( + , + , + i32, + i32); + +define @intrinsic_vslide1down_vx_nxv16i32_nxv16i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vslide1down_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e32, m8, d1 +; CHECK-NEXT: th.vslide1down.vx v8, v8, a0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslide1down.nxv16i32.i32( + undef, + %0, + i32 %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.th.vslide1down.mask.nxv16i32.i32( + , + , + i32, + , + i32); + +define @intrinsic_vslide1down_mask_vx_nxv16i32_nxv16i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e32, m8, d1 +; CHECK-NEXT: th.vslide1down.vx v8, v16, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslide1down.mask.nxv16i32.i32( + %0, + %1, + i32 %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.th.vslide1down.nxv1i64.i64( + , + , + i64, + i32); diff --git a/llvm/test/CodeGen/RISCV/rvv0p71/vslide1down-rv64.ll b/llvm/test/CodeGen/RISCV/rvv0p71/vslide1down-rv64.ll new file mode 100644 index 00000000000000..63031f985e001a --- /dev/null +++ b/llvm/test/CodeGen/RISCV/rvv0p71/vslide1down-rv64.ll @@ -0,0 +1,739 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=riscv64 -mattr=+xtheadvector,+d -verify-machineinstrs \ +; RUN: < %s | FileCheck %s + +declare @llvm.riscv.th.vslide1down.nxv8i8.i8( + , + , + i8, + i64); + +define @intrinsic_vslide1down_vx_nxv8i8_nxv8i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslide1down_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e8, m1, d1 +; CHECK-NEXT: th.vslide1down.vx v8, v8, a0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslide1down.nxv8i8.i8( + undef, + %0, + i8 %1, + i64 %2) + + ret %a +} + +declare @llvm.riscv.th.vslide1down.mask.nxv8i8.i8( + , + , + i8, + , + i64); + +define @intrinsic_vslide1down_mask_vx_nxv8i8_nxv8i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e8, m1, d1 +; CHECK-NEXT: th.vslide1down.vx v8, v9, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslide1down.mask.nxv8i8.i8( + %0, + %1, + i8 %2, + %3, + i64 %4) + + ret %a +} + +declare @llvm.riscv.th.vslide1down.nxv16i8.i8( + , + , + i8, + i64); + +define @intrinsic_vslide1down_vx_nxv16i8_nxv16i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslide1down_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e8, m2, d1 +; CHECK-NEXT: th.vslide1down.vx v8, v8, a0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslide1down.nxv16i8.i8( + undef, + %0, + i8 %1, + i64 %2) + + ret %a +} + +declare @llvm.riscv.th.vslide1down.mask.nxv16i8.i8( + , + , + i8, + , + i64); + +define @intrinsic_vslide1down_mask_vx_nxv16i8_nxv16i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e8, m2, d1 +; CHECK-NEXT: th.vslide1down.vx v8, v10, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslide1down.mask.nxv16i8.i8( + %0, + %1, + i8 %2, + %3, + i64 %4) + + ret %a +} + +declare @llvm.riscv.th.vslide1down.nxv32i8.i8( + , + , + i8, + i64); + +define @intrinsic_vslide1down_vx_nxv32i8_nxv32i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslide1down_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e8, m4, d1 +; CHECK-NEXT: th.vslide1down.vx v8, v8, a0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslide1down.nxv32i8.i8( + undef, + %0, + i8 %1, + i64 %2) + + ret %a +} + +declare @llvm.riscv.th.vslide1down.mask.nxv32i8.i8( + , + , + i8, + , + i64); + +define @intrinsic_vslide1down_mask_vx_nxv32i8_nxv32i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e8, m4, d1 +; CHECK-NEXT: th.vslide1down.vx v8, v12, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslide1down.mask.nxv32i8.i8( + %0, + %1, + i8 %2, + %3, + i64 %4) + + ret %a +} + +declare @llvm.riscv.th.vslide1down.nxv64i8.i8( + , + , + i8, + i64); + +define @intrinsic_vslide1down_vx_nxv64i8_nxv64i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslide1down_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e8, m8, d1 +; CHECK-NEXT: th.vslide1down.vx v8, v8, a0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslide1down.nxv64i8.i8( + undef, + %0, + i8 %1, + i64 %2) + + ret %a +} + +declare @llvm.riscv.th.vslide1down.mask.nxv64i8.i8( + , + , + i8, + , + i64); + +define @intrinsic_vslide1down_mask_vx_nxv64i8_nxv64i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e8, m8, d1 +; CHECK-NEXT: th.vslide1down.vx v8, v16, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslide1down.mask.nxv64i8.i8( + %0, + %1, + i8 %2, + %3, + i64 %4) + + ret %a +} + +declare @llvm.riscv.th.vslide1down.nxv4i16.i16( + , + , + i16, + i64); + +define @intrinsic_vslide1down_vx_nxv4i16_nxv4i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslide1down_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e16, m1, d1 +; CHECK-NEXT: th.vslide1down.vx v8, v8, a0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslide1down.nxv4i16.i16( + undef, + %0, + i16 %1, + i64 %2) + + ret %a +} + +declare @llvm.riscv.th.vslide1down.mask.nxv4i16.i16( + , + , + i16, + , + i64); + +define @intrinsic_vslide1down_mask_vx_nxv4i16_nxv4i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e16, m1, d1 +; CHECK-NEXT: th.vslide1down.vx v8, v9, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslide1down.mask.nxv4i16.i16( + %0, + %1, + i16 %2, + %3, + i64 %4) + + ret %a +} + +declare @llvm.riscv.th.vslide1down.nxv8i16.i16( + , + , + i16, + i64); + +define @intrinsic_vslide1down_vx_nxv8i16_nxv8i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslide1down_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e16, m2, d1 +; CHECK-NEXT: th.vslide1down.vx v8, v8, a0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslide1down.nxv8i16.i16( + undef, + %0, + i16 %1, + i64 %2) + + ret %a +} + +declare @llvm.riscv.th.vslide1down.mask.nxv8i16.i16( + , + , + i16, + , + i64); + +define @intrinsic_vslide1down_mask_vx_nxv8i16_nxv8i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e16, m2, d1 +; CHECK-NEXT: th.vslide1down.vx v8, v10, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslide1down.mask.nxv8i16.i16( + %0, + %1, + i16 %2, + %3, + i64 %4) + + ret %a +} + +declare @llvm.riscv.th.vslide1down.nxv16i16.i16( + , + , + i16, + i64); + +define @intrinsic_vslide1down_vx_nxv16i16_nxv16i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslide1down_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e16, m4, d1 +; CHECK-NEXT: th.vslide1down.vx v8, v8, a0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslide1down.nxv16i16.i16( + undef, + %0, + i16 %1, + i64 %2) + + ret %a +} + +declare @llvm.riscv.th.vslide1down.mask.nxv16i16.i16( + , + , + i16, + , + i64); + +define @intrinsic_vslide1down_mask_vx_nxv16i16_nxv16i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e16, m4, d1 +; CHECK-NEXT: th.vslide1down.vx v8, v12, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslide1down.mask.nxv16i16.i16( + %0, + %1, + i16 %2, + %3, + i64 %4) + + ret %a +} + +declare @llvm.riscv.th.vslide1down.nxv32i16.i16( + , + , + i16, + i64); + +define @intrinsic_vslide1down_vx_nxv32i16_nxv32i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslide1down_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e16, m8, d1 +; CHECK-NEXT: th.vslide1down.vx v8, v8, a0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslide1down.nxv32i16.i16( + undef, + %0, + i16 %1, + i64 %2) + + ret %a +} + +declare @llvm.riscv.th.vslide1down.mask.nxv32i16.i16( + , + , + i16, + , + i64); + +define @intrinsic_vslide1down_mask_vx_nxv32i16_nxv32i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e16, m8, d1 +; CHECK-NEXT: th.vslide1down.vx v8, v16, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslide1down.mask.nxv32i16.i16( + %0, + %1, + i16 %2, + %3, + i64 %4) + + ret %a +} + +declare @llvm.riscv.th.vslide1down.nxv2i32.i32( + , + , + i32, + i64); + +define @intrinsic_vslide1down_vx_nxv2i32_nxv2i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslide1down_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vslide1down.vx v8, v8, a0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslide1down.nxv2i32.i32( + undef, + %0, + i32 %1, + i64 %2) + + ret %a +} + +declare @llvm.riscv.th.vslide1down.mask.nxv2i32.i32( + , + , + i32, + , + i64); + +define @intrinsic_vslide1down_mask_vx_nxv2i32_nxv2i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vslide1down.vx v8, v9, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslide1down.mask.nxv2i32.i32( + %0, + %1, + i32 %2, + %3, + i64 %4) + + ret %a +} + +declare @llvm.riscv.th.vslide1down.nxv4i32.i32( + , + , + i32, + i64); + +define @intrinsic_vslide1down_vx_nxv4i32_nxv4i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslide1down_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vslide1down.vx v8, v8, a0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslide1down.nxv4i32.i32( + undef, + %0, + i32 %1, + i64 %2) + + ret %a +} + +declare @llvm.riscv.th.vslide1down.mask.nxv4i32.i32( + , + , + i32, + , + i64); + +define @intrinsic_vslide1down_mask_vx_nxv4i32_nxv4i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vslide1down.vx v8, v10, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslide1down.mask.nxv4i32.i32( + %0, + %1, + i32 %2, + %3, + i64 %4) + + ret %a +} + +declare @llvm.riscv.th.vslide1down.nxv8i32.i32( + , + , + i32, + i64); + +define @intrinsic_vslide1down_vx_nxv8i32_nxv8i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslide1down_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vslide1down.vx v8, v8, a0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslide1down.nxv8i32.i32( + undef, + %0, + i32 %1, + i64 %2) + + ret %a +} + +declare @llvm.riscv.th.vslide1down.mask.nxv8i32.i32( + , + , + i32, + , + i64); + +define @intrinsic_vslide1down_mask_vx_nxv8i32_nxv8i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vslide1down.vx v8, v12, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslide1down.mask.nxv8i32.i32( + %0, + %1, + i32 %2, + %3, + i64 %4) + + ret %a +} + +declare @llvm.riscv.th.vslide1down.nxv16i32.i32( + , + , + i32, + i64); + +define @intrinsic_vslide1down_vx_nxv16i32_nxv16i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslide1down_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e32, m8, d1 +; CHECK-NEXT: th.vslide1down.vx v8, v8, a0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslide1down.nxv16i32.i32( + undef, + %0, + i32 %1, + i64 %2) + + ret %a +} + +declare @llvm.riscv.th.vslide1down.mask.nxv16i32.i32( + , + , + i32, + , + i64); + +define @intrinsic_vslide1down_mask_vx_nxv16i32_nxv16i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e32, m8, d1 +; CHECK-NEXT: th.vslide1down.vx v8, v16, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslide1down.mask.nxv16i32.i32( + %0, + %1, + i32 %2, + %3, + i64 %4) + + ret %a +} + +declare @llvm.riscv.th.vslide1down.nxv1i64.i64( + , + , + i64, + i64); + +define @intrinsic_vslide1down_vx_nxv1i64_nxv1i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslide1down_vx_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e64, m1, d1 +; CHECK-NEXT: th.vslide1down.vx v8, v8, a0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslide1down.nxv1i64.i64( + undef, + %0, + i64 %1, + i64 %2) + + ret %a +} + +declare @llvm.riscv.th.vslide1down.mask.nxv1i64.i64( + , + , + i64, + , + i64); + +define @intrinsic_vslide1down_mask_vx_nxv1i64_nxv1i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e64, m1, d1 +; CHECK-NEXT: th.vslide1down.vx v8, v9, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslide1down.mask.nxv1i64.i64( + %0, + %1, + i64 %2, + %3, + i64 %4) + + ret %a +} + +declare @llvm.riscv.th.vslide1down.nxv2i64.i64( + , + , + i64, + i64); + +define @intrinsic_vslide1down_vx_nxv2i64_nxv2i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslide1down_vx_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e64, m2, d1 +; CHECK-NEXT: th.vslide1down.vx v8, v8, a0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslide1down.nxv2i64.i64( + undef, + %0, + i64 %1, + i64 %2) + + ret %a +} + +declare @llvm.riscv.th.vslide1down.mask.nxv2i64.i64( + , + , + i64, + , + i64); + +define @intrinsic_vslide1down_mask_vx_nxv2i64_nxv2i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e64, m2, d1 +; CHECK-NEXT: th.vslide1down.vx v8, v10, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslide1down.mask.nxv2i64.i64( + %0, + %1, + i64 %2, + %3, + i64 %4) + + ret %a +} + +declare @llvm.riscv.th.vslide1down.nxv4i64.i64( + , + , + i64, + i64); + +define @intrinsic_vslide1down_vx_nxv4i64_nxv4i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslide1down_vx_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e64, m4, d1 +; CHECK-NEXT: th.vslide1down.vx v8, v8, a0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslide1down.nxv4i64.i64( + undef, + %0, + i64 %1, + i64 %2) + + ret %a +} + +declare @llvm.riscv.th.vslide1down.mask.nxv4i64.i64( + , + , + i64, + , + i64); + +define @intrinsic_vslide1down_mask_vx_nxv4i64_nxv4i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e64, m4, d1 +; CHECK-NEXT: th.vslide1down.vx v8, v12, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslide1down.mask.nxv4i64.i64( + %0, + %1, + i64 %2, + %3, + i64 %4) + + ret %a +} + +declare @llvm.riscv.th.vslide1down.nxv8i64.i64( + , + , + i64, + i64); + +define @intrinsic_vslide1down_vx_nxv8i64_nxv8i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslide1down_vx_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e64, m8, d1 +; CHECK-NEXT: th.vslide1down.vx v8, v8, a0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslide1down.nxv8i64.i64( + undef, + %0, + i64 %1, + i64 %2) + + ret %a +} + +declare @llvm.riscv.th.vslide1down.mask.nxv8i64.i64( + , + , + i64, + , + i64); + +define @intrinsic_vslide1down_mask_vx_nxv8i64_nxv8i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e64, m8, d1 +; CHECK-NEXT: th.vslide1down.vx v8, v16, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslide1down.mask.nxv8i64.i64( + %0, + %1, + i64 %2, + %3, + i64 %4) + + ret %a +} diff --git a/llvm/test/CodeGen/RISCV/rvv0p71/vslide1up-rv32.ll b/llvm/test/CodeGen/RISCV/rvv0p71/vslide1up-rv32.ll new file mode 100644 index 00000000000000..6bdda43b7dab15 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/rvv0p71/vslide1up-rv32.ll @@ -0,0 +1,573 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=riscv32 -mattr=+xtheadvector,+f -verify-machineinstrs \ +; RUN: < %s | FileCheck %s + +declare @llvm.riscv.th.vslide1up.nxv8i8.i8( + , + , + i8, + i32); + +define @intrinsic_vslide1up_vx_nxv8i8_nxv8i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vslide1up_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e8, m1, d1 +; CHECK-NEXT: th.vslide1up.vx v9, v8, a0 +; CHECK-NEXT: th.vmv.v.v v8, v9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslide1up.nxv8i8.i8( + undef, + %0, + i8 %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.th.vslide1up.mask.nxv8i8.i8( + , + , + i8, + , + i32); + +define @intrinsic_vslide1up_mask_vx_nxv8i8_nxv8i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e8, m1, d1 +; CHECK-NEXT: th.vslide1up.vx v8, v9, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslide1up.mask.nxv8i8.i8( + %0, + %1, + i8 %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.th.vslide1up.nxv16i8.i8( + , + , + i8, + i32); + +define @intrinsic_vslide1up_vx_nxv16i8_nxv16i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vslide1up_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e8, m2, d1 +; CHECK-NEXT: th.vslide1up.vx v10, v8, a0 +; CHECK-NEXT: th.vmv.v.v v8, v10 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslide1up.nxv16i8.i8( + undef, + %0, + i8 %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.th.vslide1up.mask.nxv16i8.i8( + , + , + i8, + , + i32); + +define @intrinsic_vslide1up_mask_vx_nxv16i8_nxv16i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e8, m2, d1 +; CHECK-NEXT: th.vslide1up.vx v8, v10, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslide1up.mask.nxv16i8.i8( + %0, + %1, + i8 %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.th.vslide1up.nxv32i8.i8( + , + , + i8, + i32); + +define @intrinsic_vslide1up_vx_nxv32i8_nxv32i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vslide1up_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e8, m4, d1 +; CHECK-NEXT: th.vslide1up.vx v12, v8, a0 +; CHECK-NEXT: th.vmv.v.v v8, v12 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslide1up.nxv32i8.i8( + undef, + %0, + i8 %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.th.vslide1up.mask.nxv32i8.i8( + , + , + i8, + , + i32); + +define @intrinsic_vslide1up_mask_vx_nxv32i8_nxv32i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e8, m4, d1 +; CHECK-NEXT: th.vslide1up.vx v8, v12, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslide1up.mask.nxv32i8.i8( + %0, + %1, + i8 %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.th.vslide1up.nxv64i8.i8( + , + , + i8, + i32); + +define @intrinsic_vslide1up_vx_nxv64i8_nxv64i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vslide1up_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e8, m8, d1 +; CHECK-NEXT: th.vslide1up.vx v16, v8, a0 +; CHECK-NEXT: th.vmv.v.v v8, v16 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslide1up.nxv64i8.i8( + undef, + %0, + i8 %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.th.vslide1up.mask.nxv64i8.i8( + , + , + i8, + , + i32); + +define @intrinsic_vslide1up_mask_vx_nxv64i8_nxv64i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e8, m8, d1 +; CHECK-NEXT: th.vslide1up.vx v8, v16, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslide1up.mask.nxv64i8.i8( + %0, + %1, + i8 %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.th.vslide1up.nxv4i16.i16( + , + , + i16, + i32); + +define @intrinsic_vslide1up_vx_nxv4i16_nxv4i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vslide1up_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e16, m1, d1 +; CHECK-NEXT: th.vslide1up.vx v9, v8, a0 +; CHECK-NEXT: th.vmv.v.v v8, v9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslide1up.nxv4i16.i16( + undef, + %0, + i16 %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.th.vslide1up.mask.nxv4i16.i16( + , + , + i16, + , + i32); + +define @intrinsic_vslide1up_mask_vx_nxv4i16_nxv4i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e16, m1, d1 +; CHECK-NEXT: th.vslide1up.vx v8, v9, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslide1up.mask.nxv4i16.i16( + %0, + %1, + i16 %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.th.vslide1up.nxv8i16.i16( + , + , + i16, + i32); + +define @intrinsic_vslide1up_vx_nxv8i16_nxv8i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vslide1up_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e16, m2, d1 +; CHECK-NEXT: th.vslide1up.vx v10, v8, a0 +; CHECK-NEXT: th.vmv.v.v v8, v10 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslide1up.nxv8i16.i16( + undef, + %0, + i16 %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.th.vslide1up.mask.nxv8i16.i16( + , + , + i16, + , + i32); + +define @intrinsic_vslide1up_mask_vx_nxv8i16_nxv8i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e16, m2, d1 +; CHECK-NEXT: th.vslide1up.vx v8, v10, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslide1up.mask.nxv8i16.i16( + %0, + %1, + i16 %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.th.vslide1up.nxv16i16.i16( + , + , + i16, + i32); + +define @intrinsic_vslide1up_vx_nxv16i16_nxv16i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vslide1up_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e16, m4, d1 +; CHECK-NEXT: th.vslide1up.vx v12, v8, a0 +; CHECK-NEXT: th.vmv.v.v v8, v12 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslide1up.nxv16i16.i16( + undef, + %0, + i16 %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.th.vslide1up.mask.nxv16i16.i16( + , + , + i16, + , + i32); + +define @intrinsic_vslide1up_mask_vx_nxv16i16_nxv16i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e16, m4, d1 +; CHECK-NEXT: th.vslide1up.vx v8, v12, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslide1up.mask.nxv16i16.i16( + %0, + %1, + i16 %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.th.vslide1up.nxv32i16.i16( + , + , + i16, + i32); + +define @intrinsic_vslide1up_vx_nxv32i16_nxv32i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vslide1up_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e16, m8, d1 +; CHECK-NEXT: th.vslide1up.vx v16, v8, a0 +; CHECK-NEXT: th.vmv.v.v v8, v16 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslide1up.nxv32i16.i16( + undef, + %0, + i16 %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.th.vslide1up.mask.nxv32i16.i16( + , + , + i16, + , + i32); + +define @intrinsic_vslide1up_mask_vx_nxv32i16_nxv32i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e16, m8, d1 +; CHECK-NEXT: th.vslide1up.vx v8, v16, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslide1up.mask.nxv32i16.i16( + %0, + %1, + i16 %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.th.vslide1up.nxv2i32.i32( + , + , + i32, + i32); + +define @intrinsic_vslide1up_vx_nxv2i32_nxv2i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vslide1up_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vslide1up.vx v9, v8, a0 +; CHECK-NEXT: th.vmv.v.v v8, v9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslide1up.nxv2i32.i32( + undef, + %0, + i32 %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.th.vslide1up.mask.nxv2i32.i32( + , + , + i32, + , + i32); + +define @intrinsic_vslide1up_mask_vx_nxv2i32_nxv2i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vslide1up.vx v8, v9, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslide1up.mask.nxv2i32.i32( + %0, + %1, + i32 %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.th.vslide1up.nxv4i32.i32( + , + , + i32, + i32); + +define @intrinsic_vslide1up_vx_nxv4i32_nxv4i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vslide1up_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vslide1up.vx v10, v8, a0 +; CHECK-NEXT: th.vmv.v.v v8, v10 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslide1up.nxv4i32.i32( + undef, + %0, + i32 %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.th.vslide1up.mask.nxv4i32.i32( + , + , + i32, + , + i32); + +define @intrinsic_vslide1up_mask_vx_nxv4i32_nxv4i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vslide1up.vx v8, v10, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslide1up.mask.nxv4i32.i32( + %0, + %1, + i32 %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.th.vslide1up.nxv8i32.i32( + , + , + i32, + i32); + +define @intrinsic_vslide1up_vx_nxv8i32_nxv8i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vslide1up_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vslide1up.vx v12, v8, a0 +; CHECK-NEXT: th.vmv.v.v v8, v12 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslide1up.nxv8i32.i32( + undef, + %0, + i32 %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.th.vslide1up.mask.nxv8i32.i32( + , + , + i32, + , + i32); + +define @intrinsic_vslide1up_mask_vx_nxv8i32_nxv8i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vslide1up.vx v8, v12, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslide1up.mask.nxv8i32.i32( + %0, + %1, + i32 %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.th.vslide1up.nxv16i32.i32( + , + , + i32, + i32); + +define @intrinsic_vslide1up_vx_nxv16i32_nxv16i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vslide1up_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e32, m8, d1 +; CHECK-NEXT: th.vslide1up.vx v16, v8, a0 +; CHECK-NEXT: th.vmv.v.v v8, v16 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslide1up.nxv16i32.i32( + undef, + %0, + i32 %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.th.vslide1up.mask.nxv16i32.i32( + , + , + i32, + , + i32); + +define @intrinsic_vslide1up_mask_vx_nxv16i32_nxv16i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e32, m8, d1 +; CHECK-NEXT: th.vslide1up.vx v8, v16, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslide1up.mask.nxv16i32.i32( + %0, + %1, + i32 %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.th.vslide1up.nxv1i64.i64( + , + , + i64, + i32); diff --git a/llvm/test/CodeGen/RISCV/rvv0p71/vslide1up-rv64.ll b/llvm/test/CodeGen/RISCV/rvv0p71/vslide1up-rv64.ll new file mode 100644 index 00000000000000..2bdcf7f3423f20 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/rvv0p71/vslide1up-rv64.ll @@ -0,0 +1,755 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=riscv64 -mattr=+xtheadvector,+d -verify-machineinstrs \ +; RUN: < %s | FileCheck %s + +declare @llvm.riscv.th.vslide1up.nxv8i8.i8( + , + , + i8, + i64); + +define @intrinsic_vslide1up_vx_nxv8i8_nxv8i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslide1up_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e8, m1, d1 +; CHECK-NEXT: th.vslide1up.vx v9, v8, a0 +; CHECK-NEXT: th.vmv.v.v v8, v9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslide1up.nxv8i8.i8( + undef, + %0, + i8 %1, + i64 %2) + + ret %a +} + +declare @llvm.riscv.th.vslide1up.mask.nxv8i8.i8( + , + , + i8, + , + i64); + +define @intrinsic_vslide1up_mask_vx_nxv8i8_nxv8i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e8, m1, d1 +; CHECK-NEXT: th.vslide1up.vx v8, v9, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslide1up.mask.nxv8i8.i8( + %0, + %1, + i8 %2, + %3, + i64 %4) + + ret %a +} + +declare @llvm.riscv.th.vslide1up.nxv16i8.i8( + , + , + i8, + i64); + +define @intrinsic_vslide1up_vx_nxv16i8_nxv16i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslide1up_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e8, m2, d1 +; CHECK-NEXT: th.vslide1up.vx v10, v8, a0 +; CHECK-NEXT: th.vmv.v.v v8, v10 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslide1up.nxv16i8.i8( + undef, + %0, + i8 %1, + i64 %2) + + ret %a +} + +declare @llvm.riscv.th.vslide1up.mask.nxv16i8.i8( + , + , + i8, + , + i64); + +define @intrinsic_vslide1up_mask_vx_nxv16i8_nxv16i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e8, m2, d1 +; CHECK-NEXT: th.vslide1up.vx v8, v10, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslide1up.mask.nxv16i8.i8( + %0, + %1, + i8 %2, + %3, + i64 %4) + + ret %a +} + +declare @llvm.riscv.th.vslide1up.nxv32i8.i8( + , + , + i8, + i64); + +define @intrinsic_vslide1up_vx_nxv32i8_nxv32i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslide1up_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e8, m4, d1 +; CHECK-NEXT: th.vslide1up.vx v12, v8, a0 +; CHECK-NEXT: th.vmv.v.v v8, v12 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslide1up.nxv32i8.i8( + undef, + %0, + i8 %1, + i64 %2) + + ret %a +} + +declare @llvm.riscv.th.vslide1up.mask.nxv32i8.i8( + , + , + i8, + , + i64); + +define @intrinsic_vslide1up_mask_vx_nxv32i8_nxv32i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e8, m4, d1 +; CHECK-NEXT: th.vslide1up.vx v8, v12, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslide1up.mask.nxv32i8.i8( + %0, + %1, + i8 %2, + %3, + i64 %4) + + ret %a +} + +declare @llvm.riscv.th.vslide1up.nxv64i8.i8( + , + , + i8, + i64); + +define @intrinsic_vslide1up_vx_nxv64i8_nxv64i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslide1up_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e8, m8, d1 +; CHECK-NEXT: th.vslide1up.vx v16, v8, a0 +; CHECK-NEXT: th.vmv.v.v v8, v16 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslide1up.nxv64i8.i8( + undef, + %0, + i8 %1, + i64 %2) + + ret %a +} + +declare @llvm.riscv.th.vslide1up.mask.nxv64i8.i8( + , + , + i8, + , + i64); + +define @intrinsic_vslide1up_mask_vx_nxv64i8_nxv64i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e8, m8, d1 +; CHECK-NEXT: th.vslide1up.vx v8, v16, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslide1up.mask.nxv64i8.i8( + %0, + %1, + i8 %2, + %3, + i64 %4) + + ret %a +} + +declare @llvm.riscv.th.vslide1up.nxv4i16.i16( + , + , + i16, + i64); + +define @intrinsic_vslide1up_vx_nxv4i16_nxv4i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslide1up_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e16, m1, d1 +; CHECK-NEXT: th.vslide1up.vx v9, v8, a0 +; CHECK-NEXT: th.vmv.v.v v8, v9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslide1up.nxv4i16.i16( + undef, + %0, + i16 %1, + i64 %2) + + ret %a +} + +declare @llvm.riscv.th.vslide1up.mask.nxv4i16.i16( + , + , + i16, + , + i64); + +define @intrinsic_vslide1up_mask_vx_nxv4i16_nxv4i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e16, m1, d1 +; CHECK-NEXT: th.vslide1up.vx v8, v9, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslide1up.mask.nxv4i16.i16( + %0, + %1, + i16 %2, + %3, + i64 %4) + + ret %a +} + +declare @llvm.riscv.th.vslide1up.nxv8i16.i16( + , + , + i16, + i64); + +define @intrinsic_vslide1up_vx_nxv8i16_nxv8i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslide1up_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e16, m2, d1 +; CHECK-NEXT: th.vslide1up.vx v10, v8, a0 +; CHECK-NEXT: th.vmv.v.v v8, v10 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslide1up.nxv8i16.i16( + undef, + %0, + i16 %1, + i64 %2) + + ret %a +} + +declare @llvm.riscv.th.vslide1up.mask.nxv8i16.i16( + , + , + i16, + , + i64); + +define @intrinsic_vslide1up_mask_vx_nxv8i16_nxv8i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e16, m2, d1 +; CHECK-NEXT: th.vslide1up.vx v8, v10, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslide1up.mask.nxv8i16.i16( + %0, + %1, + i16 %2, + %3, + i64 %4) + + ret %a +} + +declare @llvm.riscv.th.vslide1up.nxv16i16.i16( + , + , + i16, + i64); + +define @intrinsic_vslide1up_vx_nxv16i16_nxv16i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslide1up_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e16, m4, d1 +; CHECK-NEXT: th.vslide1up.vx v12, v8, a0 +; CHECK-NEXT: th.vmv.v.v v8, v12 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslide1up.nxv16i16.i16( + undef, + %0, + i16 %1, + i64 %2) + + ret %a +} + +declare @llvm.riscv.th.vslide1up.mask.nxv16i16.i16( + , + , + i16, + , + i64); + +define @intrinsic_vslide1up_mask_vx_nxv16i16_nxv16i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e16, m4, d1 +; CHECK-NEXT: th.vslide1up.vx v8, v12, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslide1up.mask.nxv16i16.i16( + %0, + %1, + i16 %2, + %3, + i64 %4) + + ret %a +} + +declare @llvm.riscv.th.vslide1up.nxv32i16.i16( + , + , + i16, + i64); + +define @intrinsic_vslide1up_vx_nxv32i16_nxv32i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslide1up_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e16, m8, d1 +; CHECK-NEXT: th.vslide1up.vx v16, v8, a0 +; CHECK-NEXT: th.vmv.v.v v8, v16 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslide1up.nxv32i16.i16( + undef, + %0, + i16 %1, + i64 %2) + + ret %a +} + +declare @llvm.riscv.th.vslide1up.mask.nxv32i16.i16( + , + , + i16, + , + i64); + +define @intrinsic_vslide1up_mask_vx_nxv32i16_nxv32i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e16, m8, d1 +; CHECK-NEXT: th.vslide1up.vx v8, v16, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslide1up.mask.nxv32i16.i16( + %0, + %1, + i16 %2, + %3, + i64 %4) + + ret %a +} + +declare @llvm.riscv.th.vslide1up.nxv2i32.i32( + , + , + i32, + i64); + +define @intrinsic_vslide1up_vx_nxv2i32_nxv2i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslide1up_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vslide1up.vx v9, v8, a0 +; CHECK-NEXT: th.vmv.v.v v8, v9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslide1up.nxv2i32.i32( + undef, + %0, + i32 %1, + i64 %2) + + ret %a +} + +declare @llvm.riscv.th.vslide1up.mask.nxv2i32.i32( + , + , + i32, + , + i64); + +define @intrinsic_vslide1up_mask_vx_nxv2i32_nxv2i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vslide1up.vx v8, v9, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslide1up.mask.nxv2i32.i32( + %0, + %1, + i32 %2, + %3, + i64 %4) + + ret %a +} + +declare @llvm.riscv.th.vslide1up.nxv4i32.i32( + , + , + i32, + i64); + +define @intrinsic_vslide1up_vx_nxv4i32_nxv4i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslide1up_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vslide1up.vx v10, v8, a0 +; CHECK-NEXT: th.vmv.v.v v8, v10 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslide1up.nxv4i32.i32( + undef, + %0, + i32 %1, + i64 %2) + + ret %a +} + +declare @llvm.riscv.th.vslide1up.mask.nxv4i32.i32( + , + , + i32, + , + i64); + +define @intrinsic_vslide1up_mask_vx_nxv4i32_nxv4i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vslide1up.vx v8, v10, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslide1up.mask.nxv4i32.i32( + %0, + %1, + i32 %2, + %3, + i64 %4) + + ret %a +} + +declare @llvm.riscv.th.vslide1up.nxv8i32.i32( + , + , + i32, + i64); + +define @intrinsic_vslide1up_vx_nxv8i32_nxv8i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslide1up_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vslide1up.vx v12, v8, a0 +; CHECK-NEXT: th.vmv.v.v v8, v12 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslide1up.nxv8i32.i32( + undef, + %0, + i32 %1, + i64 %2) + + ret %a +} + +declare @llvm.riscv.th.vslide1up.mask.nxv8i32.i32( + , + , + i32, + , + i64); + +define @intrinsic_vslide1up_mask_vx_nxv8i32_nxv8i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vslide1up.vx v8, v12, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslide1up.mask.nxv8i32.i32( + %0, + %1, + i32 %2, + %3, + i64 %4) + + ret %a +} + +declare @llvm.riscv.th.vslide1up.nxv16i32.i32( + , + , + i32, + i64); + +define @intrinsic_vslide1up_vx_nxv16i32_nxv16i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslide1up_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e32, m8, d1 +; CHECK-NEXT: th.vslide1up.vx v16, v8, a0 +; CHECK-NEXT: th.vmv.v.v v8, v16 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslide1up.nxv16i32.i32( + undef, + %0, + i32 %1, + i64 %2) + + ret %a +} + +declare @llvm.riscv.th.vslide1up.mask.nxv16i32.i32( + , + , + i32, + , + i64); + +define @intrinsic_vslide1up_mask_vx_nxv16i32_nxv16i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e32, m8, d1 +; CHECK-NEXT: th.vslide1up.vx v8, v16, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslide1up.mask.nxv16i32.i32( + %0, + %1, + i32 %2, + %3, + i64 %4) + + ret %a +} + +declare @llvm.riscv.th.vslide1up.nxv1i64.i64( + , + , + i64, + i64); + +define @intrinsic_vslide1up_vx_nxv1i64_nxv1i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslide1up_vx_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e64, m1, d1 +; CHECK-NEXT: th.vslide1up.vx v9, v8, a0 +; CHECK-NEXT: th.vmv.v.v v8, v9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslide1up.nxv1i64.i64( + undef, + %0, + i64 %1, + i64 %2) + + ret %a +} + +declare @llvm.riscv.th.vslide1up.mask.nxv1i64.i64( + , + , + i64, + , + i64); + +define @intrinsic_vslide1up_mask_vx_nxv1i64_nxv1i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e64, m1, d1 +; CHECK-NEXT: th.vslide1up.vx v8, v9, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslide1up.mask.nxv1i64.i64( + %0, + %1, + i64 %2, + %3, + i64 %4) + + ret %a +} + +declare @llvm.riscv.th.vslide1up.nxv2i64.i64( + , + , + i64, + i64); + +define @intrinsic_vslide1up_vx_nxv2i64_nxv2i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslide1up_vx_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e64, m2, d1 +; CHECK-NEXT: th.vslide1up.vx v10, v8, a0 +; CHECK-NEXT: th.vmv.v.v v8, v10 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslide1up.nxv2i64.i64( + undef, + %0, + i64 %1, + i64 %2) + + ret %a +} + +declare @llvm.riscv.th.vslide1up.mask.nxv2i64.i64( + , + , + i64, + , + i64); + +define @intrinsic_vslide1up_mask_vx_nxv2i64_nxv2i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e64, m2, d1 +; CHECK-NEXT: th.vslide1up.vx v8, v10, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslide1up.mask.nxv2i64.i64( + %0, + %1, + i64 %2, + %3, + i64 %4) + + ret %a +} + +declare @llvm.riscv.th.vslide1up.nxv4i64.i64( + , + , + i64, + i64); + +define @intrinsic_vslide1up_vx_nxv4i64_nxv4i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslide1up_vx_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e64, m4, d1 +; CHECK-NEXT: th.vslide1up.vx v12, v8, a0 +; CHECK-NEXT: th.vmv.v.v v8, v12 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslide1up.nxv4i64.i64( + undef, + %0, + i64 %1, + i64 %2) + + ret %a +} + +declare @llvm.riscv.th.vslide1up.mask.nxv4i64.i64( + , + , + i64, + , + i64); + +define @intrinsic_vslide1up_mask_vx_nxv4i64_nxv4i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e64, m4, d1 +; CHECK-NEXT: th.vslide1up.vx v8, v12, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslide1up.mask.nxv4i64.i64( + %0, + %1, + i64 %2, + %3, + i64 %4) + + ret %a +} + +declare @llvm.riscv.th.vslide1up.nxv8i64.i64( + , + , + i64, + i64); + +define @intrinsic_vslide1up_vx_nxv8i64_nxv8i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslide1up_vx_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e64, m8, d1 +; CHECK-NEXT: th.vslide1up.vx v16, v8, a0 +; CHECK-NEXT: th.vmv.v.v v8, v16 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslide1up.nxv8i64.i64( + undef, + %0, + i64 %1, + i64 %2) + + ret %a +} + +declare @llvm.riscv.th.vslide1up.mask.nxv8i64.i64( + , + , + i64, + , + i64); + +define @intrinsic_vslide1up_mask_vx_nxv8i64_nxv8i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e64, m8, d1 +; CHECK-NEXT: th.vslide1up.vx v8, v16, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslide1up.mask.nxv8i64.i64( + %0, + %1, + i64 %2, + %3, + i64 %4) + + ret %a +} diff --git a/llvm/test/CodeGen/RISCV/rvv0p71/vslidedown-rv32.ll b/llvm/test/CodeGen/RISCV/rvv0p71/vslidedown-rv32.ll new file mode 100644 index 00000000000000..9183ce56b1ce55 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/rvv0p71/vslidedown-rv32.ll @@ -0,0 +1,1683 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=riscv32 -mattr=+xtheadvector,+d -verify-machineinstrs \ +; RUN: < %s | FileCheck %s + +declare @llvm.riscv.th.vslidedown.nxv8i8( + , + , + i32, + i32 +); + +define @intrinsic_vslidedown_vx_nxv8i8_nxv8i8( %0, %1, i32 %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vx_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e8, m1, d1 +; CHECK-NEXT: th.vslidedown.vx v8, v9, a0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.nxv8i8( + %0, + %1, + i32 %2, + i32 %3) + + ret %a +} + +declare @llvm.riscv.th.vslidedown.mask.nxv8i8( + , + , + i32, + , + i32); + +define @intrinsic_vslidedown_mask_vx_nxv8i8_nxv8i8( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e8, m1, d1 +; CHECK-NEXT: th.vslidedown.vx v8, v9, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.mask.nxv8i8( + %0, + %1, + i32 %2, + %3, + i32 %4) + + ret %a +} + +define @intrinsic_vslidedown_vi_nxv8i8_nxv8i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vi_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e8, m1, d1 +; CHECK-NEXT: th.vslidedown.vi v8, v9, 9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.nxv8i8( + %0, + %1, + i32 9, + i32 %2) + + ret %a +} + +define @intrinsic_vslidedown_mask_vi_nxv8i8_nxv8i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e8, m1, d1 +; CHECK-NEXT: th.vslidedown.vi v8, v9, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.mask.nxv8i8( + %0, + %1, + i32 9, + %2, + i32 %3) + + ret %a +} + +declare @llvm.riscv.th.vslidedown.nxv16i8( + , + , + i32, + i32 +); + +define @intrinsic_vslidedown_vx_nxv16i8_nxv16i8( %0, %1, i32 %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vx_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e8, m2, d1 +; CHECK-NEXT: th.vslidedown.vx v8, v10, a0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.nxv16i8( + %0, + %1, + i32 %2, + i32 %3) + + ret %a +} + +declare @llvm.riscv.th.vslidedown.mask.nxv16i8( + , + , + i32, + , + i32); + +define @intrinsic_vslidedown_mask_vx_nxv16i8_nxv16i8( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e8, m2, d1 +; CHECK-NEXT: th.vslidedown.vx v8, v10, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.mask.nxv16i8( + %0, + %1, + i32 %2, + %3, + i32 %4) + + ret %a +} + +define @intrinsic_vslidedown_vi_nxv16i8_nxv16i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vi_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e8, m2, d1 +; CHECK-NEXT: th.vslidedown.vi v8, v10, 9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.nxv16i8( + %0, + %1, + i32 9, + i32 %2) + + ret %a +} + +define @intrinsic_vslidedown_mask_vi_nxv16i8_nxv16i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e8, m2, d1 +; CHECK-NEXT: th.vslidedown.vi v8, v10, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.mask.nxv16i8( + %0, + %1, + i32 9, + %2, + i32 %3) + + ret %a +} + +declare @llvm.riscv.th.vslidedown.nxv32i8( + , + , + i32, + i32 +); + +define @intrinsic_vslidedown_vx_nxv32i8_nxv32i8( %0, %1, i32 %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vx_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e8, m4, d1 +; CHECK-NEXT: th.vslidedown.vx v8, v12, a0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.nxv32i8( + %0, + %1, + i32 %2, + i32 %3) + + ret %a +} + +declare @llvm.riscv.th.vslidedown.mask.nxv32i8( + , + , + i32, + , + i32); + +define @intrinsic_vslidedown_mask_vx_nxv32i8_nxv32i8( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e8, m4, d1 +; CHECK-NEXT: th.vslidedown.vx v8, v12, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.mask.nxv32i8( + %0, + %1, + i32 %2, + %3, + i32 %4) + + ret %a +} + +define @intrinsic_vslidedown_vi_nxv32i8_nxv32i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vi_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e8, m4, d1 +; CHECK-NEXT: th.vslidedown.vi v8, v12, 9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.nxv32i8( + %0, + %1, + i32 9, + i32 %2) + + ret %a +} + +define @intrinsic_vslidedown_mask_vi_nxv32i8_nxv32i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e8, m4, d1 +; CHECK-NEXT: th.vslidedown.vi v8, v12, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.mask.nxv32i8( + %0, + %1, + i32 9, + %2, + i32 %3) + + ret %a +} + +declare @llvm.riscv.th.vslidedown.nxv4i16( + , + , + i32, + i32 +); + +define @intrinsic_vslidedown_vx_nxv4i16_nxv4i16( %0, %1, i32 %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vx_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e16, m1, d1 +; CHECK-NEXT: th.vslidedown.vx v8, v9, a0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.nxv4i16( + %0, + %1, + i32 %2, + i32 %3) + + ret %a +} + +declare @llvm.riscv.th.vslidedown.mask.nxv4i16( + , + , + i32, + , + i32); + +define @intrinsic_vslidedown_mask_vx_nxv4i16_nxv4i16( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e16, m1, d1 +; CHECK-NEXT: th.vslidedown.vx v8, v9, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.mask.nxv4i16( + %0, + %1, + i32 %2, + %3, + i32 %4) + + ret %a +} + +define @intrinsic_vslidedown_vi_nxv4i16_nxv4i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vi_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e16, m1, d1 +; CHECK-NEXT: th.vslidedown.vi v8, v9, 9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.nxv4i16( + %0, + %1, + i32 9, + i32 %2) + + ret %a +} + +define @intrinsic_vslidedown_mask_vi_nxv4i16_nxv4i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e16, m1, d1 +; CHECK-NEXT: th.vslidedown.vi v8, v9, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.mask.nxv4i16( + %0, + %1, + i32 9, + %2, + i32 %3) + + ret %a +} + +declare @llvm.riscv.th.vslidedown.nxv8i16( + , + , + i32, + i32 +); + +define @intrinsic_vslidedown_vx_nxv8i16_nxv8i16( %0, %1, i32 %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vx_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e16, m2, d1 +; CHECK-NEXT: th.vslidedown.vx v8, v10, a0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.nxv8i16( + %0, + %1, + i32 %2, + i32 %3) + + ret %a +} + +declare @llvm.riscv.th.vslidedown.mask.nxv8i16( + , + , + i32, + , + i32); + +define @intrinsic_vslidedown_mask_vx_nxv8i16_nxv8i16( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e16, m2, d1 +; CHECK-NEXT: th.vslidedown.vx v8, v10, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.mask.nxv8i16( + %0, + %1, + i32 %2, + %3, + i32 %4) + + ret %a +} + +define @intrinsic_vslidedown_vi_nxv8i16_nxv8i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vi_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e16, m2, d1 +; CHECK-NEXT: th.vslidedown.vi v8, v10, 9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.nxv8i16( + %0, + %1, + i32 9, + i32 %2) + + ret %a +} + +define @intrinsic_vslidedown_mask_vi_nxv8i16_nxv8i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e16, m2, d1 +; CHECK-NEXT: th.vslidedown.vi v8, v10, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.mask.nxv8i16( + %0, + %1, + i32 9, + %2, + i32 %3) + + ret %a +} + +declare @llvm.riscv.th.vslidedown.nxv16i16( + , + , + i32, + i32 +); + +define @intrinsic_vslidedown_vx_nxv16i16_nxv16i16( %0, %1, i32 %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vx_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e16, m4, d1 +; CHECK-NEXT: th.vslidedown.vx v8, v12, a0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.nxv16i16( + %0, + %1, + i32 %2, + i32 %3) + + ret %a +} + +declare @llvm.riscv.th.vslidedown.mask.nxv16i16( + , + , + i32, + , + i32); + +define @intrinsic_vslidedown_mask_vx_nxv16i16_nxv16i16( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e16, m4, d1 +; CHECK-NEXT: th.vslidedown.vx v8, v12, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.mask.nxv16i16( + %0, + %1, + i32 %2, + %3, + i32 %4) + + ret %a +} + +define @intrinsic_vslidedown_vi_nxv16i16_nxv16i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vi_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e16, m4, d1 +; CHECK-NEXT: th.vslidedown.vi v8, v12, 9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.nxv16i16( + %0, + %1, + i32 9, + i32 %2) + + ret %a +} + +define @intrinsic_vslidedown_mask_vi_nxv16i16_nxv16i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e16, m4, d1 +; CHECK-NEXT: th.vslidedown.vi v8, v12, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.mask.nxv16i16( + %0, + %1, + i32 9, + %2, + i32 %3) + + ret %a +} + +declare @llvm.riscv.th.vslidedown.nxv2i32( + , + , + i32, + i32 +); + +define @intrinsic_vslidedown_vx_nxv2i32_nxv2i32( %0, %1, i32 %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vx_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vslidedown.vx v8, v9, a0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.nxv2i32( + %0, + %1, + i32 %2, + i32 %3) + + ret %a +} + +declare @llvm.riscv.th.vslidedown.mask.nxv2i32( + , + , + i32, + , + i32); + +define @intrinsic_vslidedown_mask_vx_nxv2i32_nxv2i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vslidedown.vx v8, v9, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.mask.nxv2i32( + %0, + %1, + i32 %2, + %3, + i32 %4) + + ret %a +} + +define @intrinsic_vslidedown_vi_nxv2i32_nxv2i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vi_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e32, m1, d1 +; CHECK-NEXT: th.vslidedown.vi v8, v9, 9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.nxv2i32( + %0, + %1, + i32 9, + i32 %2) + + ret %a +} + +define @intrinsic_vslidedown_mask_vi_nxv2i32_nxv2i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e32, m1, d1 +; CHECK-NEXT: th.vslidedown.vi v8, v9, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.mask.nxv2i32( + %0, + %1, + i32 9, + %2, + i32 %3) + + ret %a +} + +declare @llvm.riscv.th.vslidedown.nxv4i32( + , + , + i32, + i32 +); + +define @intrinsic_vslidedown_vx_nxv4i32_nxv4i32( %0, %1, i32 %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vx_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vslidedown.vx v8, v10, a0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.nxv4i32( + %0, + %1, + i32 %2, + i32 %3) + + ret %a +} + +declare @llvm.riscv.th.vslidedown.mask.nxv4i32( + , + , + i32, + , + i32); + +define @intrinsic_vslidedown_mask_vx_nxv4i32_nxv4i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vslidedown.vx v8, v10, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.mask.nxv4i32( + %0, + %1, + i32 %2, + %3, + i32 %4) + + ret %a +} + +define @intrinsic_vslidedown_vi_nxv4i32_nxv4i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vi_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e32, m2, d1 +; CHECK-NEXT: th.vslidedown.vi v8, v10, 9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.nxv4i32( + %0, + %1, + i32 9, + i32 %2) + + ret %a +} + +define @intrinsic_vslidedown_mask_vi_nxv4i32_nxv4i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e32, m2, d1 +; CHECK-NEXT: th.vslidedown.vi v8, v10, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.mask.nxv4i32( + %0, + %1, + i32 9, + %2, + i32 %3) + + ret %a +} + +declare @llvm.riscv.th.vslidedown.nxv8i32( + , + , + i32, + i32 +); + +define @intrinsic_vslidedown_vx_nxv8i32_nxv8i32( %0, %1, i32 %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vx_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vslidedown.vx v8, v12, a0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.nxv8i32( + %0, + %1, + i32 %2, + i32 %3) + + ret %a +} + +declare @llvm.riscv.th.vslidedown.mask.nxv8i32( + , + , + i32, + , + i32); + +define @intrinsic_vslidedown_mask_vx_nxv8i32_nxv8i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vslidedown.vx v8, v12, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.mask.nxv8i32( + %0, + %1, + i32 %2, + %3, + i32 %4) + + ret %a +} + +define @intrinsic_vslidedown_vi_nxv8i32_nxv8i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vi_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e32, m4, d1 +; CHECK-NEXT: th.vslidedown.vi v8, v12, 9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.nxv8i32( + %0, + %1, + i32 9, + i32 %2) + + ret %a +} + +define @intrinsic_vslidedown_mask_vi_nxv8i32_nxv8i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e32, m4, d1 +; CHECK-NEXT: th.vslidedown.vi v8, v12, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.mask.nxv8i32( + %0, + %1, + i32 9, + %2, + i32 %3) + + ret %a +} + +declare @llvm.riscv.th.vslidedown.nxv1i64( + , + , + i32, + i32 +); + +define @intrinsic_vslidedown_vx_nxv1i64_nxv1i64( %0, %1, i32 %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vx_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e64, m1, d1 +; CHECK-NEXT: th.vslidedown.vx v8, v9, a0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.nxv1i64( + %0, + %1, + i32 %2, + i32 %3) + + ret %a +} + +declare @llvm.riscv.th.vslidedown.mask.nxv1i64( + , + , + i32, + , + i32); + +define @intrinsic_vslidedown_mask_vx_nxv1i64_nxv1i64( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e64, m1, d1 +; CHECK-NEXT: th.vslidedown.vx v8, v9, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.mask.nxv1i64( + %0, + %1, + i32 %2, + %3, + i32 %4) + + ret %a +} + +define @intrinsic_vslidedown_vi_nxv1i64_nxv1i64( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vi_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e64, m1, d1 +; CHECK-NEXT: th.vslidedown.vi v8, v9, 9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.nxv1i64( + %0, + %1, + i32 9, + i32 %2) + + ret %a +} + +define @intrinsic_vslidedown_mask_vi_nxv1i64_nxv1i64( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e64, m1, d1 +; CHECK-NEXT: th.vslidedown.vi v8, v9, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.mask.nxv1i64( + %0, + %1, + i32 9, + %2, + i32 %3) + + ret %a +} + +declare @llvm.riscv.th.vslidedown.nxv2i64( + , + , + i32, + i32 +); + +define @intrinsic_vslidedown_vx_nxv2i64_nxv2i64( %0, %1, i32 %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vx_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e64, m2, d1 +; CHECK-NEXT: th.vslidedown.vx v8, v10, a0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.nxv2i64( + %0, + %1, + i32 %2, + i32 %3) + + ret %a +} + +declare @llvm.riscv.th.vslidedown.mask.nxv2i64( + , + , + i32, + , + i32); + +define @intrinsic_vslidedown_mask_vx_nxv2i64_nxv2i64( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e64, m2, d1 +; CHECK-NEXT: th.vslidedown.vx v8, v10, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.mask.nxv2i64( + %0, + %1, + i32 %2, + %3, + i32 %4) + + ret %a +} + +define @intrinsic_vslidedown_vi_nxv2i64_nxv2i64( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vi_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e64, m2, d1 +; CHECK-NEXT: th.vslidedown.vi v8, v10, 9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.nxv2i64( + %0, + %1, + i32 9, + i32 %2) + + ret %a +} + +define @intrinsic_vslidedown_mask_vi_nxv2i64_nxv2i64( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e64, m2, d1 +; CHECK-NEXT: th.vslidedown.vi v8, v10, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.mask.nxv2i64( + %0, + %1, + i32 9, + %2, + i32 %3) + + ret %a +} + +declare @llvm.riscv.th.vslidedown.nxv4i64( + , + , + i32, + i32 +); + +define @intrinsic_vslidedown_vx_nxv4i64_nxv4i64( %0, %1, i32 %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vx_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e64, m4, d1 +; CHECK-NEXT: th.vslidedown.vx v8, v12, a0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.nxv4i64( + %0, + %1, + i32 %2, + i32 %3) + + ret %a +} + +declare @llvm.riscv.th.vslidedown.mask.nxv4i64( + , + , + i32, + , + i32); + +define @intrinsic_vslidedown_mask_vx_nxv4i64_nxv4i64( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e64, m4, d1 +; CHECK-NEXT: th.vslidedown.vx v8, v12, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.mask.nxv4i64( + %0, + %1, + i32 %2, + %3, + i32 %4) + + ret %a +} + +define @intrinsic_vslidedown_vi_nxv4i64_nxv4i64( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vi_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e64, m4, d1 +; CHECK-NEXT: th.vslidedown.vi v8, v12, 9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.nxv4i64( + %0, + %1, + i32 9, + i32 %2) + + ret %a +} + +define @intrinsic_vslidedown_mask_vi_nxv4i64_nxv4i64( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e64, m4, d1 +; CHECK-NEXT: th.vslidedown.vi v8, v12, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.mask.nxv4i64( + %0, + %1, + i32 9, + %2, + i32 %3) + + ret %a +} + +declare @llvm.riscv.th.vslidedown.nxv4f16( + , + , + i32, + i32 +); + +define @intrinsic_vslidedown_vx_nxv4f16_nxv4f16( %0, %1, i32 %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vx_nxv4f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e16, m1, d1 +; CHECK-NEXT: th.vslidedown.vx v8, v9, a0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.nxv4f16( + %0, + %1, + i32 %2, + i32 %3) + + ret %a +} + +declare @llvm.riscv.th.vslidedown.mask.nxv4f16( + , + , + i32, + , + i32); + +define @intrinsic_vslidedown_mask_vx_nxv4f16_nxv4f16( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv4f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e16, m1, d1 +; CHECK-NEXT: th.vslidedown.vx v8, v9, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.mask.nxv4f16( + %0, + %1, + i32 %2, + %3, + i32 %4) + + ret %a +} + +define @intrinsic_vslidedown_vi_nxv4f16_nxv4f16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vi_nxv4f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e16, m1, d1 +; CHECK-NEXT: th.vslidedown.vi v8, v9, 9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.nxv4f16( + %0, + %1, + i32 9, + i32 %2) + + ret %a +} + +define @intrinsic_vslidedown_mask_vi_nxv4f16_nxv4f16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv4f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e16, m1, d1 +; CHECK-NEXT: th.vslidedown.vi v8, v9, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.mask.nxv4f16( + %0, + %1, + i32 9, + %2, + i32 %3) + + ret %a +} + +declare @llvm.riscv.th.vslidedown.nxv8f16( + , + , + i32, + i32 +); + +define @intrinsic_vslidedown_vx_nxv8f16_nxv8f16( %0, %1, i32 %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vx_nxv8f16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e16, m2, d1 +; CHECK-NEXT: th.vslidedown.vx v8, v10, a0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.nxv8f16( + %0, + %1, + i32 %2, + i32 %3) + + ret %a +} + +declare @llvm.riscv.th.vslidedown.mask.nxv8f16( + , + , + i32, + , + i32); + +define @intrinsic_vslidedown_mask_vx_nxv8f16_nxv8f16( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv8f16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e16, m2, d1 +; CHECK-NEXT: th.vslidedown.vx v8, v10, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.mask.nxv8f16( + %0, + %1, + i32 %2, + %3, + i32 %4) + + ret %a +} + +define @intrinsic_vslidedown_vi_nxv8f16_nxv8f16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vi_nxv8f16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e16, m2, d1 +; CHECK-NEXT: th.vslidedown.vi v8, v10, 9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.nxv8f16( + %0, + %1, + i32 9, + i32 %2) + + ret %a +} + +define @intrinsic_vslidedown_mask_vi_nxv8f16_nxv8f16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv8f16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e16, m2, d1 +; CHECK-NEXT: th.vslidedown.vi v8, v10, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.mask.nxv8f16( + %0, + %1, + i32 9, + %2, + i32 %3) + + ret %a +} + +declare @llvm.riscv.th.vslidedown.nxv16f16( + , + , + i32, + i32 +); + +define @intrinsic_vslidedown_vx_nxv16f16_nxv16f16( %0, %1, i32 %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vx_nxv16f16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e16, m4, d1 +; CHECK-NEXT: th.vslidedown.vx v8, v12, a0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.nxv16f16( + %0, + %1, + i32 %2, + i32 %3) + + ret %a +} + +declare @llvm.riscv.th.vslidedown.mask.nxv16f16( + , + , + i32, + , + i32); + +define @intrinsic_vslidedown_mask_vx_nxv16f16_nxv16f16( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv16f16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e16, m4, d1 +; CHECK-NEXT: th.vslidedown.vx v8, v12, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.mask.nxv16f16( + %0, + %1, + i32 %2, + %3, + i32 %4) + + ret %a +} + +define @intrinsic_vslidedown_vi_nxv16f16_nxv16f16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vi_nxv16f16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e16, m4, d1 +; CHECK-NEXT: th.vslidedown.vi v8, v12, 9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.nxv16f16( + %0, + %1, + i32 9, + i32 %2) + + ret %a +} + +define @intrinsic_vslidedown_mask_vi_nxv16f16_nxv16f16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv16f16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e16, m4, d1 +; CHECK-NEXT: th.vslidedown.vi v8, v12, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.mask.nxv16f16( + %0, + %1, + i32 9, + %2, + i32 %3) + + ret %a +} + +declare @llvm.riscv.th.vslidedown.nxv2f32( + , + , + i32, + i32 +); + +define @intrinsic_vslidedown_vx_nxv2f32_nxv2f32( %0, %1, i32 %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vx_nxv2f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vslidedown.vx v8, v9, a0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.nxv2f32( + %0, + %1, + i32 %2, + i32 %3) + + ret %a +} + +declare @llvm.riscv.th.vslidedown.mask.nxv2f32( + , + , + i32, + , + i32); + +define @intrinsic_vslidedown_mask_vx_nxv2f32_nxv2f32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv2f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vslidedown.vx v8, v9, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.mask.nxv2f32( + %0, + %1, + i32 %2, + %3, + i32 %4) + + ret %a +} + +define @intrinsic_vslidedown_vi_nxv2f32_nxv2f32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vi_nxv2f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e32, m1, d1 +; CHECK-NEXT: th.vslidedown.vi v8, v9, 9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.nxv2f32( + %0, + %1, + i32 9, + i32 %2) + + ret %a +} + +define @intrinsic_vslidedown_mask_vi_nxv2f32_nxv2f32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv2f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e32, m1, d1 +; CHECK-NEXT: th.vslidedown.vi v8, v9, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.mask.nxv2f32( + %0, + %1, + i32 9, + %2, + i32 %3) + + ret %a +} + +declare @llvm.riscv.th.vslidedown.nxv4f32( + , + , + i32, + i32 +); + +define @intrinsic_vslidedown_vx_nxv4f32_nxv4f32( %0, %1, i32 %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vx_nxv4f32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vslidedown.vx v8, v10, a0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.nxv4f32( + %0, + %1, + i32 %2, + i32 %3) + + ret %a +} + +declare @llvm.riscv.th.vslidedown.mask.nxv4f32( + , + , + i32, + , + i32); + +define @intrinsic_vslidedown_mask_vx_nxv4f32_nxv4f32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv4f32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vslidedown.vx v8, v10, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.mask.nxv4f32( + %0, + %1, + i32 %2, + %3, + i32 %4) + + ret %a +} + +define @intrinsic_vslidedown_vi_nxv4f32_nxv4f32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vi_nxv4f32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e32, m2, d1 +; CHECK-NEXT: th.vslidedown.vi v8, v10, 9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.nxv4f32( + %0, + %1, + i32 9, + i32 %2) + + ret %a +} + +define @intrinsic_vslidedown_mask_vi_nxv4f32_nxv4f32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv4f32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e32, m2, d1 +; CHECK-NEXT: th.vslidedown.vi v8, v10, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.mask.nxv4f32( + %0, + %1, + i32 9, + %2, + i32 %3) + + ret %a +} + +declare @llvm.riscv.th.vslidedown.nxv8f32( + , + , + i32, + i32 +); + +define @intrinsic_vslidedown_vx_nxv8f32_nxv8f32( %0, %1, i32 %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vx_nxv8f32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vslidedown.vx v8, v12, a0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.nxv8f32( + %0, + %1, + i32 %2, + i32 %3) + + ret %a +} + +declare @llvm.riscv.th.vslidedown.mask.nxv8f32( + , + , + i32, + , + i32); + +define @intrinsic_vslidedown_mask_vx_nxv8f32_nxv8f32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv8f32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vslidedown.vx v8, v12, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.mask.nxv8f32( + %0, + %1, + i32 %2, + %3, + i32 %4) + + ret %a +} + +define @intrinsic_vslidedown_vi_nxv8f32_nxv8f32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vi_nxv8f32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e32, m4, d1 +; CHECK-NEXT: th.vslidedown.vi v8, v12, 9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.nxv8f32( + %0, + %1, + i32 9, + i32 %2) + + ret %a +} + +define @intrinsic_vslidedown_mask_vi_nxv8f32_nxv8f32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv8f32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e32, m4, d1 +; CHECK-NEXT: th.vslidedown.vi v8, v12, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.mask.nxv8f32( + %0, + %1, + i32 9, + %2, + i32 %3) + + ret %a +} + +declare @llvm.riscv.th.vslidedown.nxv1f64( + , + , + i32, + i32 +); + +define @intrinsic_vslidedown_vx_nxv1f64_nxv1f64( %0, %1, i32 %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vx_nxv1f64_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e64, m1, d1 +; CHECK-NEXT: th.vslidedown.vx v8, v9, a0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.nxv1f64( + %0, + %1, + i32 %2, + i32 %3) + + ret %a +} + +declare @llvm.riscv.th.vslidedown.mask.nxv1f64( + , + , + i32, + , + i32); + +define @intrinsic_vslidedown_mask_vx_nxv1f64_nxv1f64( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv1f64_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e64, m1, d1 +; CHECK-NEXT: th.vslidedown.vx v8, v9, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.mask.nxv1f64( + %0, + %1, + i32 %2, + %3, + i32 %4) + + ret %a +} + +define @intrinsic_vslidedown_vi_nxv1f64_nxv1f64( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vi_nxv1f64_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e64, m1, d1 +; CHECK-NEXT: th.vslidedown.vi v8, v9, 9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.nxv1f64( + %0, + %1, + i32 9, + i32 %2) + + ret %a +} + +define @intrinsic_vslidedown_mask_vi_nxv1f64_nxv1f64( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv1f64_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e64, m1, d1 +; CHECK-NEXT: th.vslidedown.vi v8, v9, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.mask.nxv1f64( + %0, + %1, + i32 9, + %2, + i32 %3) + + ret %a +} + +declare @llvm.riscv.th.vslidedown.nxv2f64( + , + , + i32, + i32 +); + +define @intrinsic_vslidedown_vx_nxv2f64_nxv2f64( %0, %1, i32 %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vx_nxv2f64_nxv2f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e64, m2, d1 +; CHECK-NEXT: th.vslidedown.vx v8, v10, a0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.nxv2f64( + %0, + %1, + i32 %2, + i32 %3) + + ret %a +} + +declare @llvm.riscv.th.vslidedown.mask.nxv2f64( + , + , + i32, + , + i32); + +define @intrinsic_vslidedown_mask_vx_nxv2f64_nxv2f64( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv2f64_nxv2f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e64, m2, d1 +; CHECK-NEXT: th.vslidedown.vx v8, v10, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.mask.nxv2f64( + %0, + %1, + i32 %2, + %3, + i32 %4) + + ret %a +} + +define @intrinsic_vslidedown_vi_nxv2f64_nxv2f64( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vi_nxv2f64_nxv2f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e64, m2, d1 +; CHECK-NEXT: th.vslidedown.vi v8, v10, 9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.nxv2f64( + %0, + %1, + i32 9, + i32 %2) + + ret %a +} + +define @intrinsic_vslidedown_mask_vi_nxv2f64_nxv2f64( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv2f64_nxv2f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e64, m2, d1 +; CHECK-NEXT: th.vslidedown.vi v8, v10, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.mask.nxv2f64( + %0, + %1, + i32 9, + %2, + i32 %3) + + ret %a +} + +declare @llvm.riscv.th.vslidedown.nxv4f64( + , + , + i32, + i32 +); + +define @intrinsic_vslidedown_vx_nxv4f64_nxv4f64( %0, %1, i32 %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vx_nxv4f64_nxv4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e64, m4, d1 +; CHECK-NEXT: th.vslidedown.vx v8, v12, a0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.nxv4f64( + %0, + %1, + i32 %2, + i32 %3) + + ret %a +} + +declare @llvm.riscv.th.vslidedown.mask.nxv4f64( + , + , + i32, + , + i32); + +define @intrinsic_vslidedown_mask_vx_nxv4f64_nxv4f64( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv4f64_nxv4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e64, m4, d1 +; CHECK-NEXT: th.vslidedown.vx v8, v12, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.mask.nxv4f64( + %0, + %1, + i32 %2, + %3, + i32 %4) + + ret %a +} + +define @intrinsic_vslidedown_vi_nxv4f64_nxv4f64( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vi_nxv4f64_nxv4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e64, m4, d1 +; CHECK-NEXT: th.vslidedown.vi v8, v12, 9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.nxv4f64( + %0, + %1, + i32 9, + i32 %2) + + ret %a +} + +define @intrinsic_vslidedown_mask_vi_nxv4f64_nxv4f64( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv4f64_nxv4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e64, m4, d1 +; CHECK-NEXT: th.vslidedown.vi v8, v12, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.mask.nxv4f64( + %0, + %1, + i32 9, + %2, + i32 %3) + + ret %a +} diff --git a/llvm/test/CodeGen/RISCV/rvv0p71/vslidedown-rv64.ll b/llvm/test/CodeGen/RISCV/rvv0p71/vslidedown-rv64.ll new file mode 100644 index 00000000000000..f7aeef45035049 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/rvv0p71/vslidedown-rv64.ll @@ -0,0 +1,1683 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=riscv64 -mattr=+xtheadvector,+d -verify-machineinstrs \ +; RUN: < %s | FileCheck %s + +declare @llvm.riscv.th.vslidedown.nxv8i8( + , + , + i64, + i64 +); + +define @intrinsic_vslidedown_vx_nxv8i8_nxv8i8( %0, %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vx_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e8, m1, d1 +; CHECK-NEXT: th.vslidedown.vx v8, v9, a0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.nxv8i8( + %0, + %1, + i64 %2, + i64 %3) + + ret %a +} + +declare @llvm.riscv.th.vslidedown.mask.nxv8i8( + , + , + i64, + , + i64); + +define @intrinsic_vslidedown_mask_vx_nxv8i8_nxv8i8( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e8, m1, d1 +; CHECK-NEXT: th.vslidedown.vx v8, v9, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.mask.nxv8i8( + %0, + %1, + i64 %2, + %3, + i64 %4) + + ret %a +} + +define @intrinsic_vslidedown_vi_nxv8i8_nxv8i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vi_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e8, m1, d1 +; CHECK-NEXT: th.vslidedown.vi v8, v9, 9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.nxv8i8( + %0, + %1, + i64 9, + i64 %2) + + ret %a +} + +define @intrinsic_vslidedown_mask_vi_nxv8i8_nxv8i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e8, m1, d1 +; CHECK-NEXT: th.vslidedown.vi v8, v9, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.mask.nxv8i8( + %0, + %1, + i64 9, + %2, + i64 %3) + + ret %a +} + +declare @llvm.riscv.th.vslidedown.nxv16i8( + , + , + i64, + i64 +); + +define @intrinsic_vslidedown_vx_nxv16i8_nxv16i8( %0, %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vx_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e8, m2, d1 +; CHECK-NEXT: th.vslidedown.vx v8, v10, a0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.nxv16i8( + %0, + %1, + i64 %2, + i64 %3) + + ret %a +} + +declare @llvm.riscv.th.vslidedown.mask.nxv16i8( + , + , + i64, + , + i64); + +define @intrinsic_vslidedown_mask_vx_nxv16i8_nxv16i8( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e8, m2, d1 +; CHECK-NEXT: th.vslidedown.vx v8, v10, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.mask.nxv16i8( + %0, + %1, + i64 %2, + %3, + i64 %4) + + ret %a +} + +define @intrinsic_vslidedown_vi_nxv16i8_nxv16i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vi_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e8, m2, d1 +; CHECK-NEXT: th.vslidedown.vi v8, v10, 9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.nxv16i8( + %0, + %1, + i64 9, + i64 %2) + + ret %a +} + +define @intrinsic_vslidedown_mask_vi_nxv16i8_nxv16i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e8, m2, d1 +; CHECK-NEXT: th.vslidedown.vi v8, v10, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.mask.nxv16i8( + %0, + %1, + i64 9, + %2, + i64 %3) + + ret %a +} + +declare @llvm.riscv.th.vslidedown.nxv32i8( + , + , + i64, + i64 +); + +define @intrinsic_vslidedown_vx_nxv32i8_nxv32i8( %0, %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vx_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e8, m4, d1 +; CHECK-NEXT: th.vslidedown.vx v8, v12, a0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.nxv32i8( + %0, + %1, + i64 %2, + i64 %3) + + ret %a +} + +declare @llvm.riscv.th.vslidedown.mask.nxv32i8( + , + , + i64, + , + i64); + +define @intrinsic_vslidedown_mask_vx_nxv32i8_nxv32i8( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e8, m4, d1 +; CHECK-NEXT: th.vslidedown.vx v8, v12, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.mask.nxv32i8( + %0, + %1, + i64 %2, + %3, + i64 %4) + + ret %a +} + +define @intrinsic_vslidedown_vi_nxv32i8_nxv32i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vi_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e8, m4, d1 +; CHECK-NEXT: th.vslidedown.vi v8, v12, 9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.nxv32i8( + %0, + %1, + i64 9, + i64 %2) + + ret %a +} + +define @intrinsic_vslidedown_mask_vi_nxv32i8_nxv32i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e8, m4, d1 +; CHECK-NEXT: th.vslidedown.vi v8, v12, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.mask.nxv32i8( + %0, + %1, + i64 9, + %2, + i64 %3) + + ret %a +} + +declare @llvm.riscv.th.vslidedown.nxv4i16( + , + , + i64, + i64 +); + +define @intrinsic_vslidedown_vx_nxv4i16_nxv4i16( %0, %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vx_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e16, m1, d1 +; CHECK-NEXT: th.vslidedown.vx v8, v9, a0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.nxv4i16( + %0, + %1, + i64 %2, + i64 %3) + + ret %a +} + +declare @llvm.riscv.th.vslidedown.mask.nxv4i16( + , + , + i64, + , + i64); + +define @intrinsic_vslidedown_mask_vx_nxv4i16_nxv4i16( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e16, m1, d1 +; CHECK-NEXT: th.vslidedown.vx v8, v9, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.mask.nxv4i16( + %0, + %1, + i64 %2, + %3, + i64 %4) + + ret %a +} + +define @intrinsic_vslidedown_vi_nxv4i16_nxv4i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vi_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e16, m1, d1 +; CHECK-NEXT: th.vslidedown.vi v8, v9, 9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.nxv4i16( + %0, + %1, + i64 9, + i64 %2) + + ret %a +} + +define @intrinsic_vslidedown_mask_vi_nxv4i16_nxv4i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e16, m1, d1 +; CHECK-NEXT: th.vslidedown.vi v8, v9, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.mask.nxv4i16( + %0, + %1, + i64 9, + %2, + i64 %3) + + ret %a +} + +declare @llvm.riscv.th.vslidedown.nxv8i16( + , + , + i64, + i64 +); + +define @intrinsic_vslidedown_vx_nxv8i16_nxv8i16( %0, %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vx_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e16, m2, d1 +; CHECK-NEXT: th.vslidedown.vx v8, v10, a0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.nxv8i16( + %0, + %1, + i64 %2, + i64 %3) + + ret %a +} + +declare @llvm.riscv.th.vslidedown.mask.nxv8i16( + , + , + i64, + , + i64); + +define @intrinsic_vslidedown_mask_vx_nxv8i16_nxv8i16( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e16, m2, d1 +; CHECK-NEXT: th.vslidedown.vx v8, v10, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.mask.nxv8i16( + %0, + %1, + i64 %2, + %3, + i64 %4) + + ret %a +} + +define @intrinsic_vslidedown_vi_nxv8i16_nxv8i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vi_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e16, m2, d1 +; CHECK-NEXT: th.vslidedown.vi v8, v10, 9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.nxv8i16( + %0, + %1, + i64 9, + i64 %2) + + ret %a +} + +define @intrinsic_vslidedown_mask_vi_nxv8i16_nxv8i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e16, m2, d1 +; CHECK-NEXT: th.vslidedown.vi v8, v10, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.mask.nxv8i16( + %0, + %1, + i64 9, + %2, + i64 %3) + + ret %a +} + +declare @llvm.riscv.th.vslidedown.nxv16i16( + , + , + i64, + i64 +); + +define @intrinsic_vslidedown_vx_nxv16i16_nxv16i16( %0, %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vx_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e16, m4, d1 +; CHECK-NEXT: th.vslidedown.vx v8, v12, a0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.nxv16i16( + %0, + %1, + i64 %2, + i64 %3) + + ret %a +} + +declare @llvm.riscv.th.vslidedown.mask.nxv16i16( + , + , + i64, + , + i64); + +define @intrinsic_vslidedown_mask_vx_nxv16i16_nxv16i16( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e16, m4, d1 +; CHECK-NEXT: th.vslidedown.vx v8, v12, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.mask.nxv16i16( + %0, + %1, + i64 %2, + %3, + i64 %4) + + ret %a +} + +define @intrinsic_vslidedown_vi_nxv16i16_nxv16i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vi_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e16, m4, d1 +; CHECK-NEXT: th.vslidedown.vi v8, v12, 9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.nxv16i16( + %0, + %1, + i64 9, + i64 %2) + + ret %a +} + +define @intrinsic_vslidedown_mask_vi_nxv16i16_nxv16i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e16, m4, d1 +; CHECK-NEXT: th.vslidedown.vi v8, v12, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.mask.nxv16i16( + %0, + %1, + i64 9, + %2, + i64 %3) + + ret %a +} + +declare @llvm.riscv.th.vslidedown.nxv2i32( + , + , + i64, + i64 +); + +define @intrinsic_vslidedown_vx_nxv2i32_nxv2i32( %0, %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vx_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vslidedown.vx v8, v9, a0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.nxv2i32( + %0, + %1, + i64 %2, + i64 %3) + + ret %a +} + +declare @llvm.riscv.th.vslidedown.mask.nxv2i32( + , + , + i64, + , + i64); + +define @intrinsic_vslidedown_mask_vx_nxv2i32_nxv2i32( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vslidedown.vx v8, v9, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.mask.nxv2i32( + %0, + %1, + i64 %2, + %3, + i64 %4) + + ret %a +} + +define @intrinsic_vslidedown_vi_nxv2i32_nxv2i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vi_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e32, m1, d1 +; CHECK-NEXT: th.vslidedown.vi v8, v9, 9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.nxv2i32( + %0, + %1, + i64 9, + i64 %2) + + ret %a +} + +define @intrinsic_vslidedown_mask_vi_nxv2i32_nxv2i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e32, m1, d1 +; CHECK-NEXT: th.vslidedown.vi v8, v9, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.mask.nxv2i32( + %0, + %1, + i64 9, + %2, + i64 %3) + + ret %a +} + +declare @llvm.riscv.th.vslidedown.nxv4i32( + , + , + i64, + i64 +); + +define @intrinsic_vslidedown_vx_nxv4i32_nxv4i32( %0, %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vx_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vslidedown.vx v8, v10, a0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.nxv4i32( + %0, + %1, + i64 %2, + i64 %3) + + ret %a +} + +declare @llvm.riscv.th.vslidedown.mask.nxv4i32( + , + , + i64, + , + i64); + +define @intrinsic_vslidedown_mask_vx_nxv4i32_nxv4i32( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vslidedown.vx v8, v10, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.mask.nxv4i32( + %0, + %1, + i64 %2, + %3, + i64 %4) + + ret %a +} + +define @intrinsic_vslidedown_vi_nxv4i32_nxv4i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vi_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e32, m2, d1 +; CHECK-NEXT: th.vslidedown.vi v8, v10, 9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.nxv4i32( + %0, + %1, + i64 9, + i64 %2) + + ret %a +} + +define @intrinsic_vslidedown_mask_vi_nxv4i32_nxv4i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e32, m2, d1 +; CHECK-NEXT: th.vslidedown.vi v8, v10, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.mask.nxv4i32( + %0, + %1, + i64 9, + %2, + i64 %3) + + ret %a +} + +declare @llvm.riscv.th.vslidedown.nxv8i32( + , + , + i64, + i64 +); + +define @intrinsic_vslidedown_vx_nxv8i32_nxv8i32( %0, %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vx_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vslidedown.vx v8, v12, a0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.nxv8i32( + %0, + %1, + i64 %2, + i64 %3) + + ret %a +} + +declare @llvm.riscv.th.vslidedown.mask.nxv8i32( + , + , + i64, + , + i64); + +define @intrinsic_vslidedown_mask_vx_nxv8i32_nxv8i32( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vslidedown.vx v8, v12, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.mask.nxv8i32( + %0, + %1, + i64 %2, + %3, + i64 %4) + + ret %a +} + +define @intrinsic_vslidedown_vi_nxv8i32_nxv8i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vi_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e32, m4, d1 +; CHECK-NEXT: th.vslidedown.vi v8, v12, 9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.nxv8i32( + %0, + %1, + i64 9, + i64 %2) + + ret %a +} + +define @intrinsic_vslidedown_mask_vi_nxv8i32_nxv8i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e32, m4, d1 +; CHECK-NEXT: th.vslidedown.vi v8, v12, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.mask.nxv8i32( + %0, + %1, + i64 9, + %2, + i64 %3) + + ret %a +} + +declare @llvm.riscv.th.vslidedown.nxv1i64( + , + , + i64, + i64 +); + +define @intrinsic_vslidedown_vx_nxv1i64_nxv1i64( %0, %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vx_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e64, m1, d1 +; CHECK-NEXT: th.vslidedown.vx v8, v9, a0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.nxv1i64( + %0, + %1, + i64 %2, + i64 %3) + + ret %a +} + +declare @llvm.riscv.th.vslidedown.mask.nxv1i64( + , + , + i64, + , + i64); + +define @intrinsic_vslidedown_mask_vx_nxv1i64_nxv1i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e64, m1, d1 +; CHECK-NEXT: th.vslidedown.vx v8, v9, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.mask.nxv1i64( + %0, + %1, + i64 %2, + %3, + i64 %4) + + ret %a +} + +define @intrinsic_vslidedown_vi_nxv1i64_nxv1i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vi_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e64, m1, d1 +; CHECK-NEXT: th.vslidedown.vi v8, v9, 9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.nxv1i64( + %0, + %1, + i64 9, + i64 %2) + + ret %a +} + +define @intrinsic_vslidedown_mask_vi_nxv1i64_nxv1i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e64, m1, d1 +; CHECK-NEXT: th.vslidedown.vi v8, v9, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.mask.nxv1i64( + %0, + %1, + i64 9, + %2, + i64 %3) + + ret %a +} + +declare @llvm.riscv.th.vslidedown.nxv2i64( + , + , + i64, + i64 +); + +define @intrinsic_vslidedown_vx_nxv2i64_nxv2i64( %0, %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vx_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e64, m2, d1 +; CHECK-NEXT: th.vslidedown.vx v8, v10, a0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.nxv2i64( + %0, + %1, + i64 %2, + i64 %3) + + ret %a +} + +declare @llvm.riscv.th.vslidedown.mask.nxv2i64( + , + , + i64, + , + i64); + +define @intrinsic_vslidedown_mask_vx_nxv2i64_nxv2i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e64, m2, d1 +; CHECK-NEXT: th.vslidedown.vx v8, v10, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.mask.nxv2i64( + %0, + %1, + i64 %2, + %3, + i64 %4) + + ret %a +} + +define @intrinsic_vslidedown_vi_nxv2i64_nxv2i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vi_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e64, m2, d1 +; CHECK-NEXT: th.vslidedown.vi v8, v10, 9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.nxv2i64( + %0, + %1, + i64 9, + i64 %2) + + ret %a +} + +define @intrinsic_vslidedown_mask_vi_nxv2i64_nxv2i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e64, m2, d1 +; CHECK-NEXT: th.vslidedown.vi v8, v10, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.mask.nxv2i64( + %0, + %1, + i64 9, + %2, + i64 %3) + + ret %a +} + +declare @llvm.riscv.th.vslidedown.nxv4i64( + , + , + i64, + i64 +); + +define @intrinsic_vslidedown_vx_nxv4i64_nxv4i64( %0, %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vx_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e64, m4, d1 +; CHECK-NEXT: th.vslidedown.vx v8, v12, a0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.nxv4i64( + %0, + %1, + i64 %2, + i64 %3) + + ret %a +} + +declare @llvm.riscv.th.vslidedown.mask.nxv4i64( + , + , + i64, + , + i64); + +define @intrinsic_vslidedown_mask_vx_nxv4i64_nxv4i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e64, m4, d1 +; CHECK-NEXT: th.vslidedown.vx v8, v12, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.mask.nxv4i64( + %0, + %1, + i64 %2, + %3, + i64 %4) + + ret %a +} + +define @intrinsic_vslidedown_vi_nxv4i64_nxv4i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vi_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e64, m4, d1 +; CHECK-NEXT: th.vslidedown.vi v8, v12, 9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.nxv4i64( + %0, + %1, + i64 9, + i64 %2) + + ret %a +} + +define @intrinsic_vslidedown_mask_vi_nxv4i64_nxv4i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e64, m4, d1 +; CHECK-NEXT: th.vslidedown.vi v8, v12, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.mask.nxv4i64( + %0, + %1, + i64 9, + %2, + i64 %3) + + ret %a +} + +declare @llvm.riscv.th.vslidedown.nxv4f16( + , + , + i64, + i64 +); + +define @intrinsic_vslidedown_vx_nxv4f16_nxv4f16( %0, %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vx_nxv4f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e16, m1, d1 +; CHECK-NEXT: th.vslidedown.vx v8, v9, a0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.nxv4f16( + %0, + %1, + i64 %2, + i64 %3) + + ret %a +} + +declare @llvm.riscv.th.vslidedown.mask.nxv4f16( + , + , + i64, + , + i64); + +define @intrinsic_vslidedown_mask_vx_nxv4f16_nxv4f16( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv4f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e16, m1, d1 +; CHECK-NEXT: th.vslidedown.vx v8, v9, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.mask.nxv4f16( + %0, + %1, + i64 %2, + %3, + i64 %4) + + ret %a +} + +define @intrinsic_vslidedown_vi_nxv4f16_nxv4f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vi_nxv4f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e16, m1, d1 +; CHECK-NEXT: th.vslidedown.vi v8, v9, 9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.nxv4f16( + %0, + %1, + i64 9, + i64 %2) + + ret %a +} + +define @intrinsic_vslidedown_mask_vi_nxv4f16_nxv4f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv4f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e16, m1, d1 +; CHECK-NEXT: th.vslidedown.vi v8, v9, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.mask.nxv4f16( + %0, + %1, + i64 9, + %2, + i64 %3) + + ret %a +} + +declare @llvm.riscv.th.vslidedown.nxv8f16( + , + , + i64, + i64 +); + +define @intrinsic_vslidedown_vx_nxv8f16_nxv8f16( %0, %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vx_nxv8f16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e16, m2, d1 +; CHECK-NEXT: th.vslidedown.vx v8, v10, a0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.nxv8f16( + %0, + %1, + i64 %2, + i64 %3) + + ret %a +} + +declare @llvm.riscv.th.vslidedown.mask.nxv8f16( + , + , + i64, + , + i64); + +define @intrinsic_vslidedown_mask_vx_nxv8f16_nxv8f16( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv8f16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e16, m2, d1 +; CHECK-NEXT: th.vslidedown.vx v8, v10, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.mask.nxv8f16( + %0, + %1, + i64 %2, + %3, + i64 %4) + + ret %a +} + +define @intrinsic_vslidedown_vi_nxv8f16_nxv8f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vi_nxv8f16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e16, m2, d1 +; CHECK-NEXT: th.vslidedown.vi v8, v10, 9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.nxv8f16( + %0, + %1, + i64 9, + i64 %2) + + ret %a +} + +define @intrinsic_vslidedown_mask_vi_nxv8f16_nxv8f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv8f16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e16, m2, d1 +; CHECK-NEXT: th.vslidedown.vi v8, v10, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.mask.nxv8f16( + %0, + %1, + i64 9, + %2, + i64 %3) + + ret %a +} + +declare @llvm.riscv.th.vslidedown.nxv16f16( + , + , + i64, + i64 +); + +define @intrinsic_vslidedown_vx_nxv16f16_nxv16f16( %0, %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vx_nxv16f16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e16, m4, d1 +; CHECK-NEXT: th.vslidedown.vx v8, v12, a0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.nxv16f16( + %0, + %1, + i64 %2, + i64 %3) + + ret %a +} + +declare @llvm.riscv.th.vslidedown.mask.nxv16f16( + , + , + i64, + , + i64); + +define @intrinsic_vslidedown_mask_vx_nxv16f16_nxv16f16( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv16f16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e16, m4, d1 +; CHECK-NEXT: th.vslidedown.vx v8, v12, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.mask.nxv16f16( + %0, + %1, + i64 %2, + %3, + i64 %4) + + ret %a +} + +define @intrinsic_vslidedown_vi_nxv16f16_nxv16f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vi_nxv16f16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e16, m4, d1 +; CHECK-NEXT: th.vslidedown.vi v8, v12, 9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.nxv16f16( + %0, + %1, + i64 9, + i64 %2) + + ret %a +} + +define @intrinsic_vslidedown_mask_vi_nxv16f16_nxv16f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv16f16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e16, m4, d1 +; CHECK-NEXT: th.vslidedown.vi v8, v12, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.mask.nxv16f16( + %0, + %1, + i64 9, + %2, + i64 %3) + + ret %a +} + +declare @llvm.riscv.th.vslidedown.nxv2f32( + , + , + i64, + i64 +); + +define @intrinsic_vslidedown_vx_nxv2f32_nxv2f32( %0, %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vx_nxv2f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vslidedown.vx v8, v9, a0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.nxv2f32( + %0, + %1, + i64 %2, + i64 %3) + + ret %a +} + +declare @llvm.riscv.th.vslidedown.mask.nxv2f32( + , + , + i64, + , + i64); + +define @intrinsic_vslidedown_mask_vx_nxv2f32_nxv2f32( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv2f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vslidedown.vx v8, v9, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.mask.nxv2f32( + %0, + %1, + i64 %2, + %3, + i64 %4) + + ret %a +} + +define @intrinsic_vslidedown_vi_nxv2f32_nxv2f32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vi_nxv2f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e32, m1, d1 +; CHECK-NEXT: th.vslidedown.vi v8, v9, 9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.nxv2f32( + %0, + %1, + i64 9, + i64 %2) + + ret %a +} + +define @intrinsic_vslidedown_mask_vi_nxv2f32_nxv2f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv2f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e32, m1, d1 +; CHECK-NEXT: th.vslidedown.vi v8, v9, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.mask.nxv2f32( + %0, + %1, + i64 9, + %2, + i64 %3) + + ret %a +} + +declare @llvm.riscv.th.vslidedown.nxv4f32( + , + , + i64, + i64 +); + +define @intrinsic_vslidedown_vx_nxv4f32_nxv4f32( %0, %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vx_nxv4f32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vslidedown.vx v8, v10, a0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.nxv4f32( + %0, + %1, + i64 %2, + i64 %3) + + ret %a +} + +declare @llvm.riscv.th.vslidedown.mask.nxv4f32( + , + , + i64, + , + i64); + +define @intrinsic_vslidedown_mask_vx_nxv4f32_nxv4f32( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv4f32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vslidedown.vx v8, v10, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.mask.nxv4f32( + %0, + %1, + i64 %2, + %3, + i64 %4) + + ret %a +} + +define @intrinsic_vslidedown_vi_nxv4f32_nxv4f32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vi_nxv4f32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e32, m2, d1 +; CHECK-NEXT: th.vslidedown.vi v8, v10, 9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.nxv4f32( + %0, + %1, + i64 9, + i64 %2) + + ret %a +} + +define @intrinsic_vslidedown_mask_vi_nxv4f32_nxv4f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv4f32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e32, m2, d1 +; CHECK-NEXT: th.vslidedown.vi v8, v10, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.mask.nxv4f32( + %0, + %1, + i64 9, + %2, + i64 %3) + + ret %a +} + +declare @llvm.riscv.th.vslidedown.nxv8f32( + , + , + i64, + i64 +); + +define @intrinsic_vslidedown_vx_nxv8f32_nxv8f32( %0, %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vx_nxv8f32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vslidedown.vx v8, v12, a0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.nxv8f32( + %0, + %1, + i64 %2, + i64 %3) + + ret %a +} + +declare @llvm.riscv.th.vslidedown.mask.nxv8f32( + , + , + i64, + , + i64); + +define @intrinsic_vslidedown_mask_vx_nxv8f32_nxv8f32( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv8f32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vslidedown.vx v8, v12, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.mask.nxv8f32( + %0, + %1, + i64 %2, + %3, + i64 %4) + + ret %a +} + +define @intrinsic_vslidedown_vi_nxv8f32_nxv8f32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vi_nxv8f32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e32, m4, d1 +; CHECK-NEXT: th.vslidedown.vi v8, v12, 9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.nxv8f32( + %0, + %1, + i64 9, + i64 %2) + + ret %a +} + +define @intrinsic_vslidedown_mask_vi_nxv8f32_nxv8f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv8f32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e32, m4, d1 +; CHECK-NEXT: th.vslidedown.vi v8, v12, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.mask.nxv8f32( + %0, + %1, + i64 9, + %2, + i64 %3) + + ret %a +} + +declare @llvm.riscv.th.vslidedown.nxv1f64( + , + , + i64, + i64 +); + +define @intrinsic_vslidedown_vx_nxv1f64_nxv1f64( %0, %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vx_nxv1f64_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e64, m1, d1 +; CHECK-NEXT: th.vslidedown.vx v8, v9, a0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.nxv1f64( + %0, + %1, + i64 %2, + i64 %3) + + ret %a +} + +declare @llvm.riscv.th.vslidedown.mask.nxv1f64( + , + , + i64, + , + i64); + +define @intrinsic_vslidedown_mask_vx_nxv1f64_nxv1f64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv1f64_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e64, m1, d1 +; CHECK-NEXT: th.vslidedown.vx v8, v9, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.mask.nxv1f64( + %0, + %1, + i64 %2, + %3, + i64 %4) + + ret %a +} + +define @intrinsic_vslidedown_vi_nxv1f64_nxv1f64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vi_nxv1f64_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e64, m1, d1 +; CHECK-NEXT: th.vslidedown.vi v8, v9, 9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.nxv1f64( + %0, + %1, + i64 9, + i64 %2) + + ret %a +} + +define @intrinsic_vslidedown_mask_vi_nxv1f64_nxv1f64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv1f64_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e64, m1, d1 +; CHECK-NEXT: th.vslidedown.vi v8, v9, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.mask.nxv1f64( + %0, + %1, + i64 9, + %2, + i64 %3) + + ret %a +} + +declare @llvm.riscv.th.vslidedown.nxv2f64( + , + , + i64, + i64 +); + +define @intrinsic_vslidedown_vx_nxv2f64_nxv2f64( %0, %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vx_nxv2f64_nxv2f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e64, m2, d1 +; CHECK-NEXT: th.vslidedown.vx v8, v10, a0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.nxv2f64( + %0, + %1, + i64 %2, + i64 %3) + + ret %a +} + +declare @llvm.riscv.th.vslidedown.mask.nxv2f64( + , + , + i64, + , + i64); + +define @intrinsic_vslidedown_mask_vx_nxv2f64_nxv2f64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv2f64_nxv2f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e64, m2, d1 +; CHECK-NEXT: th.vslidedown.vx v8, v10, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.mask.nxv2f64( + %0, + %1, + i64 %2, + %3, + i64 %4) + + ret %a +} + +define @intrinsic_vslidedown_vi_nxv2f64_nxv2f64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vi_nxv2f64_nxv2f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e64, m2, d1 +; CHECK-NEXT: th.vslidedown.vi v8, v10, 9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.nxv2f64( + %0, + %1, + i64 9, + i64 %2) + + ret %a +} + +define @intrinsic_vslidedown_mask_vi_nxv2f64_nxv2f64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv2f64_nxv2f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e64, m2, d1 +; CHECK-NEXT: th.vslidedown.vi v8, v10, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.mask.nxv2f64( + %0, + %1, + i64 9, + %2, + i64 %3) + + ret %a +} + +declare @llvm.riscv.th.vslidedown.nxv4f64( + , + , + i64, + i64 +); + +define @intrinsic_vslidedown_vx_nxv4f64_nxv4f64( %0, %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vx_nxv4f64_nxv4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e64, m4, d1 +; CHECK-NEXT: th.vslidedown.vx v8, v12, a0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.nxv4f64( + %0, + %1, + i64 %2, + i64 %3) + + ret %a +} + +declare @llvm.riscv.th.vslidedown.mask.nxv4f64( + , + , + i64, + , + i64); + +define @intrinsic_vslidedown_mask_vx_nxv4f64_nxv4f64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv4f64_nxv4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e64, m4, d1 +; CHECK-NEXT: th.vslidedown.vx v8, v12, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.mask.nxv4f64( + %0, + %1, + i64 %2, + %3, + i64 %4) + + ret %a +} + +define @intrinsic_vslidedown_vi_nxv4f64_nxv4f64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vi_nxv4f64_nxv4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e64, m4, d1 +; CHECK-NEXT: th.vslidedown.vi v8, v12, 9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.nxv4f64( + %0, + %1, + i64 9, + i64 %2) + + ret %a +} + +define @intrinsic_vslidedown_mask_vi_nxv4f64_nxv4f64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv4f64_nxv4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e64, m4, d1 +; CHECK-NEXT: th.vslidedown.vi v8, v12, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslidedown.mask.nxv4f64( + %0, + %1, + i64 9, + %2, + i64 %3) + + ret %a +} diff --git a/llvm/test/CodeGen/RISCV/rvv0p71/vslideup-rv32.ll b/llvm/test/CodeGen/RISCV/rvv0p71/vslideup-rv32.ll new file mode 100644 index 00000000000000..74305c1708f0c9 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/rvv0p71/vslideup-rv32.ll @@ -0,0 +1,1683 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=riscv32 -mattr=+xtheadvector,+d -verify-machineinstrs \ +; RUN: < %s | FileCheck %s + +declare @llvm.riscv.th.vslideup.nxv8i8( + , + , + i32, + i32 +); + +define @intrinsic_vslideup_vx_nxv8i8_nxv8i8( %0, %1, i32 %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vx_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e8, m1, d1 +; CHECK-NEXT: th.vslideup.vx v8, v9, a0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.nxv8i8( + %0, + %1, + i32 %2, + i32 %3) + + ret %a +} + +declare @llvm.riscv.th.vslideup.mask.nxv8i8( + , + , + i32, + , + i32); + +define @intrinsic_vslideup_mask_vx_nxv8i8_nxv8i8( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e8, m1, d1 +; CHECK-NEXT: th.vslideup.vx v8, v9, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.mask.nxv8i8( + %0, + %1, + i32 %2, + %3, + i32 %4) + + ret %a +} + +define @intrinsic_vslideup_vi_nxv8i8_nxv8i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vi_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e8, m1, d1 +; CHECK-NEXT: th.vslideup.vi v8, v9, 9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.nxv8i8( + %0, + %1, + i32 9, + i32 %2) + + ret %a +} + +define @intrinsic_vslideup_mask_vi_nxv8i8_nxv8i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e8, m1, d1 +; CHECK-NEXT: th.vslideup.vi v8, v9, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.mask.nxv8i8( + %0, + %1, + i32 9, + %2, + i32 %3) + + ret %a +} + +declare @llvm.riscv.th.vslideup.nxv16i8( + , + , + i32, + i32 +); + +define @intrinsic_vslideup_vx_nxv16i8_nxv16i8( %0, %1, i32 %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vx_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e8, m2, d1 +; CHECK-NEXT: th.vslideup.vx v8, v10, a0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.nxv16i8( + %0, + %1, + i32 %2, + i32 %3) + + ret %a +} + +declare @llvm.riscv.th.vslideup.mask.nxv16i8( + , + , + i32, + , + i32); + +define @intrinsic_vslideup_mask_vx_nxv16i8_nxv16i8( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e8, m2, d1 +; CHECK-NEXT: th.vslideup.vx v8, v10, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.mask.nxv16i8( + %0, + %1, + i32 %2, + %3, + i32 %4) + + ret %a +} + +define @intrinsic_vslideup_vi_nxv16i8_nxv16i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vi_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e8, m2, d1 +; CHECK-NEXT: th.vslideup.vi v8, v10, 9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.nxv16i8( + %0, + %1, + i32 9, + i32 %2) + + ret %a +} + +define @intrinsic_vslideup_mask_vi_nxv16i8_nxv16i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e8, m2, d1 +; CHECK-NEXT: th.vslideup.vi v8, v10, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.mask.nxv16i8( + %0, + %1, + i32 9, + %2, + i32 %3) + + ret %a +} + +declare @llvm.riscv.th.vslideup.nxv32i8( + , + , + i32, + i32 +); + +define @intrinsic_vslideup_vx_nxv32i8_nxv32i8( %0, %1, i32 %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vx_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e8, m4, d1 +; CHECK-NEXT: th.vslideup.vx v8, v12, a0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.nxv32i8( + %0, + %1, + i32 %2, + i32 %3) + + ret %a +} + +declare @llvm.riscv.th.vslideup.mask.nxv32i8( + , + , + i32, + , + i32); + +define @intrinsic_vslideup_mask_vx_nxv32i8_nxv32i8( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e8, m4, d1 +; CHECK-NEXT: th.vslideup.vx v8, v12, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.mask.nxv32i8( + %0, + %1, + i32 %2, + %3, + i32 %4) + + ret %a +} + +define @intrinsic_vslideup_vi_nxv32i8_nxv32i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vi_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e8, m4, d1 +; CHECK-NEXT: th.vslideup.vi v8, v12, 9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.nxv32i8( + %0, + %1, + i32 9, + i32 %2) + + ret %a +} + +define @intrinsic_vslideup_mask_vi_nxv32i8_nxv32i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e8, m4, d1 +; CHECK-NEXT: th.vslideup.vi v8, v12, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.mask.nxv32i8( + %0, + %1, + i32 9, + %2, + i32 %3) + + ret %a +} + +declare @llvm.riscv.th.vslideup.nxv4i16( + , + , + i32, + i32 +); + +define @intrinsic_vslideup_vx_nxv4i16_nxv4i16( %0, %1, i32 %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vx_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e16, m1, d1 +; CHECK-NEXT: th.vslideup.vx v8, v9, a0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.nxv4i16( + %0, + %1, + i32 %2, + i32 %3) + + ret %a +} + +declare @llvm.riscv.th.vslideup.mask.nxv4i16( + , + , + i32, + , + i32); + +define @intrinsic_vslideup_mask_vx_nxv4i16_nxv4i16( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e16, m1, d1 +; CHECK-NEXT: th.vslideup.vx v8, v9, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.mask.nxv4i16( + %0, + %1, + i32 %2, + %3, + i32 %4) + + ret %a +} + +define @intrinsic_vslideup_vi_nxv4i16_nxv4i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vi_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e16, m1, d1 +; CHECK-NEXT: th.vslideup.vi v8, v9, 9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.nxv4i16( + %0, + %1, + i32 9, + i32 %2) + + ret %a +} + +define @intrinsic_vslideup_mask_vi_nxv4i16_nxv4i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e16, m1, d1 +; CHECK-NEXT: th.vslideup.vi v8, v9, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.mask.nxv4i16( + %0, + %1, + i32 9, + %2, + i32 %3) + + ret %a +} + +declare @llvm.riscv.th.vslideup.nxv8i16( + , + , + i32, + i32 +); + +define @intrinsic_vslideup_vx_nxv8i16_nxv8i16( %0, %1, i32 %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vx_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e16, m2, d1 +; CHECK-NEXT: th.vslideup.vx v8, v10, a0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.nxv8i16( + %0, + %1, + i32 %2, + i32 %3) + + ret %a +} + +declare @llvm.riscv.th.vslideup.mask.nxv8i16( + , + , + i32, + , + i32); + +define @intrinsic_vslideup_mask_vx_nxv8i16_nxv8i16( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e16, m2, d1 +; CHECK-NEXT: th.vslideup.vx v8, v10, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.mask.nxv8i16( + %0, + %1, + i32 %2, + %3, + i32 %4) + + ret %a +} + +define @intrinsic_vslideup_vi_nxv8i16_nxv8i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vi_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e16, m2, d1 +; CHECK-NEXT: th.vslideup.vi v8, v10, 9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.nxv8i16( + %0, + %1, + i32 9, + i32 %2) + + ret %a +} + +define @intrinsic_vslideup_mask_vi_nxv8i16_nxv8i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e16, m2, d1 +; CHECK-NEXT: th.vslideup.vi v8, v10, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.mask.nxv8i16( + %0, + %1, + i32 9, + %2, + i32 %3) + + ret %a +} + +declare @llvm.riscv.th.vslideup.nxv16i16( + , + , + i32, + i32 +); + +define @intrinsic_vslideup_vx_nxv16i16_nxv16i16( %0, %1, i32 %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vx_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e16, m4, d1 +; CHECK-NEXT: th.vslideup.vx v8, v12, a0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.nxv16i16( + %0, + %1, + i32 %2, + i32 %3) + + ret %a +} + +declare @llvm.riscv.th.vslideup.mask.nxv16i16( + , + , + i32, + , + i32); + +define @intrinsic_vslideup_mask_vx_nxv16i16_nxv16i16( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e16, m4, d1 +; CHECK-NEXT: th.vslideup.vx v8, v12, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.mask.nxv16i16( + %0, + %1, + i32 %2, + %3, + i32 %4) + + ret %a +} + +define @intrinsic_vslideup_vi_nxv16i16_nxv16i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vi_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e16, m4, d1 +; CHECK-NEXT: th.vslideup.vi v8, v12, 9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.nxv16i16( + %0, + %1, + i32 9, + i32 %2) + + ret %a +} + +define @intrinsic_vslideup_mask_vi_nxv16i16_nxv16i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e16, m4, d1 +; CHECK-NEXT: th.vslideup.vi v8, v12, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.mask.nxv16i16( + %0, + %1, + i32 9, + %2, + i32 %3) + + ret %a +} + +declare @llvm.riscv.th.vslideup.nxv2i32( + , + , + i32, + i32 +); + +define @intrinsic_vslideup_vx_nxv2i32_nxv2i32( %0, %1, i32 %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vx_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vslideup.vx v8, v9, a0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.nxv2i32( + %0, + %1, + i32 %2, + i32 %3) + + ret %a +} + +declare @llvm.riscv.th.vslideup.mask.nxv2i32( + , + , + i32, + , + i32); + +define @intrinsic_vslideup_mask_vx_nxv2i32_nxv2i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vslideup.vx v8, v9, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.mask.nxv2i32( + %0, + %1, + i32 %2, + %3, + i32 %4) + + ret %a +} + +define @intrinsic_vslideup_vi_nxv2i32_nxv2i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vi_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e32, m1, d1 +; CHECK-NEXT: th.vslideup.vi v8, v9, 9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.nxv2i32( + %0, + %1, + i32 9, + i32 %2) + + ret %a +} + +define @intrinsic_vslideup_mask_vi_nxv2i32_nxv2i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e32, m1, d1 +; CHECK-NEXT: th.vslideup.vi v8, v9, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.mask.nxv2i32( + %0, + %1, + i32 9, + %2, + i32 %3) + + ret %a +} + +declare @llvm.riscv.th.vslideup.nxv4i32( + , + , + i32, + i32 +); + +define @intrinsic_vslideup_vx_nxv4i32_nxv4i32( %0, %1, i32 %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vx_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vslideup.vx v8, v10, a0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.nxv4i32( + %0, + %1, + i32 %2, + i32 %3) + + ret %a +} + +declare @llvm.riscv.th.vslideup.mask.nxv4i32( + , + , + i32, + , + i32); + +define @intrinsic_vslideup_mask_vx_nxv4i32_nxv4i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vslideup.vx v8, v10, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.mask.nxv4i32( + %0, + %1, + i32 %2, + %3, + i32 %4) + + ret %a +} + +define @intrinsic_vslideup_vi_nxv4i32_nxv4i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vi_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e32, m2, d1 +; CHECK-NEXT: th.vslideup.vi v8, v10, 9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.nxv4i32( + %0, + %1, + i32 9, + i32 %2) + + ret %a +} + +define @intrinsic_vslideup_mask_vi_nxv4i32_nxv4i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e32, m2, d1 +; CHECK-NEXT: th.vslideup.vi v8, v10, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.mask.nxv4i32( + %0, + %1, + i32 9, + %2, + i32 %3) + + ret %a +} + +declare @llvm.riscv.th.vslideup.nxv8i32( + , + , + i32, + i32 +); + +define @intrinsic_vslideup_vx_nxv8i32_nxv8i32( %0, %1, i32 %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vx_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vslideup.vx v8, v12, a0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.nxv8i32( + %0, + %1, + i32 %2, + i32 %3) + + ret %a +} + +declare @llvm.riscv.th.vslideup.mask.nxv8i32( + , + , + i32, + , + i32); + +define @intrinsic_vslideup_mask_vx_nxv8i32_nxv8i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vslideup.vx v8, v12, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.mask.nxv8i32( + %0, + %1, + i32 %2, + %3, + i32 %4) + + ret %a +} + +define @intrinsic_vslideup_vi_nxv8i32_nxv8i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vi_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e32, m4, d1 +; CHECK-NEXT: th.vslideup.vi v8, v12, 9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.nxv8i32( + %0, + %1, + i32 9, + i32 %2) + + ret %a +} + +define @intrinsic_vslideup_mask_vi_nxv8i32_nxv8i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e32, m4, d1 +; CHECK-NEXT: th.vslideup.vi v8, v12, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.mask.nxv8i32( + %0, + %1, + i32 9, + %2, + i32 %3) + + ret %a +} + +declare @llvm.riscv.th.vslideup.nxv1i64( + , + , + i32, + i32 +); + +define @intrinsic_vslideup_vx_nxv1i64_nxv1i64( %0, %1, i32 %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vx_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e64, m1, d1 +; CHECK-NEXT: th.vslideup.vx v8, v9, a0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.nxv1i64( + %0, + %1, + i32 %2, + i32 %3) + + ret %a +} + +declare @llvm.riscv.th.vslideup.mask.nxv1i64( + , + , + i32, + , + i32); + +define @intrinsic_vslideup_mask_vx_nxv1i64_nxv1i64( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e64, m1, d1 +; CHECK-NEXT: th.vslideup.vx v8, v9, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.mask.nxv1i64( + %0, + %1, + i32 %2, + %3, + i32 %4) + + ret %a +} + +define @intrinsic_vslideup_vi_nxv1i64_nxv1i64( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vi_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e64, m1, d1 +; CHECK-NEXT: th.vslideup.vi v8, v9, 9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.nxv1i64( + %0, + %1, + i32 9, + i32 %2) + + ret %a +} + +define @intrinsic_vslideup_mask_vi_nxv1i64_nxv1i64( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e64, m1, d1 +; CHECK-NEXT: th.vslideup.vi v8, v9, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.mask.nxv1i64( + %0, + %1, + i32 9, + %2, + i32 %3) + + ret %a +} + +declare @llvm.riscv.th.vslideup.nxv2i64( + , + , + i32, + i32 +); + +define @intrinsic_vslideup_vx_nxv2i64_nxv2i64( %0, %1, i32 %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vx_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e64, m2, d1 +; CHECK-NEXT: th.vslideup.vx v8, v10, a0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.nxv2i64( + %0, + %1, + i32 %2, + i32 %3) + + ret %a +} + +declare @llvm.riscv.th.vslideup.mask.nxv2i64( + , + , + i32, + , + i32); + +define @intrinsic_vslideup_mask_vx_nxv2i64_nxv2i64( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e64, m2, d1 +; CHECK-NEXT: th.vslideup.vx v8, v10, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.mask.nxv2i64( + %0, + %1, + i32 %2, + %3, + i32 %4) + + ret %a +} + +define @intrinsic_vslideup_vi_nxv2i64_nxv2i64( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vi_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e64, m2, d1 +; CHECK-NEXT: th.vslideup.vi v8, v10, 9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.nxv2i64( + %0, + %1, + i32 9, + i32 %2) + + ret %a +} + +define @intrinsic_vslideup_mask_vi_nxv2i64_nxv2i64( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e64, m2, d1 +; CHECK-NEXT: th.vslideup.vi v8, v10, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.mask.nxv2i64( + %0, + %1, + i32 9, + %2, + i32 %3) + + ret %a +} + +declare @llvm.riscv.th.vslideup.nxv4i64( + , + , + i32, + i32 +); + +define @intrinsic_vslideup_vx_nxv4i64_nxv4i64( %0, %1, i32 %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vx_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e64, m4, d1 +; CHECK-NEXT: th.vslideup.vx v8, v12, a0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.nxv4i64( + %0, + %1, + i32 %2, + i32 %3) + + ret %a +} + +declare @llvm.riscv.th.vslideup.mask.nxv4i64( + , + , + i32, + , + i32); + +define @intrinsic_vslideup_mask_vx_nxv4i64_nxv4i64( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e64, m4, d1 +; CHECK-NEXT: th.vslideup.vx v8, v12, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.mask.nxv4i64( + %0, + %1, + i32 %2, + %3, + i32 %4) + + ret %a +} + +define @intrinsic_vslideup_vi_nxv4i64_nxv4i64( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vi_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e64, m4, d1 +; CHECK-NEXT: th.vslideup.vi v8, v12, 9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.nxv4i64( + %0, + %1, + i32 9, + i32 %2) + + ret %a +} + +define @intrinsic_vslideup_mask_vi_nxv4i64_nxv4i64( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e64, m4, d1 +; CHECK-NEXT: th.vslideup.vi v8, v12, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.mask.nxv4i64( + %0, + %1, + i32 9, + %2, + i32 %3) + + ret %a +} + +declare @llvm.riscv.th.vslideup.nxv4f16( + , + , + i32, + i32 +); + +define @intrinsic_vslideup_vx_nxv4f16_nxv4f16( %0, %1, i32 %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vx_nxv4f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e16, m1, d1 +; CHECK-NEXT: th.vslideup.vx v8, v9, a0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.nxv4f16( + %0, + %1, + i32 %2, + i32 %3) + + ret %a +} + +declare @llvm.riscv.th.vslideup.mask.nxv4f16( + , + , + i32, + , + i32); + +define @intrinsic_vslideup_mask_vx_nxv4f16_nxv4f16( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv4f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e16, m1, d1 +; CHECK-NEXT: th.vslideup.vx v8, v9, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.mask.nxv4f16( + %0, + %1, + i32 %2, + %3, + i32 %4) + + ret %a +} + +define @intrinsic_vslideup_vi_nxv4f16_nxv4f16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vi_nxv4f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e16, m1, d1 +; CHECK-NEXT: th.vslideup.vi v8, v9, 9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.nxv4f16( + %0, + %1, + i32 9, + i32 %2) + + ret %a +} + +define @intrinsic_vslideup_mask_vi_nxv4f16_nxv4f16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv4f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e16, m1, d1 +; CHECK-NEXT: th.vslideup.vi v8, v9, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.mask.nxv4f16( + %0, + %1, + i32 9, + %2, + i32 %3) + + ret %a +} + +declare @llvm.riscv.th.vslideup.nxv8f16( + , + , + i32, + i32 +); + +define @intrinsic_vslideup_vx_nxv8f16_nxv8f16( %0, %1, i32 %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vx_nxv8f16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e16, m2, d1 +; CHECK-NEXT: th.vslideup.vx v8, v10, a0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.nxv8f16( + %0, + %1, + i32 %2, + i32 %3) + + ret %a +} + +declare @llvm.riscv.th.vslideup.mask.nxv8f16( + , + , + i32, + , + i32); + +define @intrinsic_vslideup_mask_vx_nxv8f16_nxv8f16( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv8f16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e16, m2, d1 +; CHECK-NEXT: th.vslideup.vx v8, v10, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.mask.nxv8f16( + %0, + %1, + i32 %2, + %3, + i32 %4) + + ret %a +} + +define @intrinsic_vslideup_vi_nxv8f16_nxv8f16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vi_nxv8f16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e16, m2, d1 +; CHECK-NEXT: th.vslideup.vi v8, v10, 9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.nxv8f16( + %0, + %1, + i32 9, + i32 %2) + + ret %a +} + +define @intrinsic_vslideup_mask_vi_nxv8f16_nxv8f16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv8f16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e16, m2, d1 +; CHECK-NEXT: th.vslideup.vi v8, v10, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.mask.nxv8f16( + %0, + %1, + i32 9, + %2, + i32 %3) + + ret %a +} + +declare @llvm.riscv.th.vslideup.nxv16f16( + , + , + i32, + i32 +); + +define @intrinsic_vslideup_vx_nxv16f16_nxv16f16( %0, %1, i32 %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vx_nxv16f16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e16, m4, d1 +; CHECK-NEXT: th.vslideup.vx v8, v12, a0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.nxv16f16( + %0, + %1, + i32 %2, + i32 %3) + + ret %a +} + +declare @llvm.riscv.th.vslideup.mask.nxv16f16( + , + , + i32, + , + i32); + +define @intrinsic_vslideup_mask_vx_nxv16f16_nxv16f16( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv16f16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e16, m4, d1 +; CHECK-NEXT: th.vslideup.vx v8, v12, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.mask.nxv16f16( + %0, + %1, + i32 %2, + %3, + i32 %4) + + ret %a +} + +define @intrinsic_vslideup_vi_nxv16f16_nxv16f16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vi_nxv16f16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e16, m4, d1 +; CHECK-NEXT: th.vslideup.vi v8, v12, 9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.nxv16f16( + %0, + %1, + i32 9, + i32 %2) + + ret %a +} + +define @intrinsic_vslideup_mask_vi_nxv16f16_nxv16f16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv16f16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e16, m4, d1 +; CHECK-NEXT: th.vslideup.vi v8, v12, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.mask.nxv16f16( + %0, + %1, + i32 9, + %2, + i32 %3) + + ret %a +} + +declare @llvm.riscv.th.vslideup.nxv2f32( + , + , + i32, + i32 +); + +define @intrinsic_vslideup_vx_nxv2f32_nxv2f32( %0, %1, i32 %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vx_nxv2f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vslideup.vx v8, v9, a0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.nxv2f32( + %0, + %1, + i32 %2, + i32 %3) + + ret %a +} + +declare @llvm.riscv.th.vslideup.mask.nxv2f32( + , + , + i32, + , + i32); + +define @intrinsic_vslideup_mask_vx_nxv2f32_nxv2f32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv2f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vslideup.vx v8, v9, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.mask.nxv2f32( + %0, + %1, + i32 %2, + %3, + i32 %4) + + ret %a +} + +define @intrinsic_vslideup_vi_nxv2f32_nxv2f32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vi_nxv2f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e32, m1, d1 +; CHECK-NEXT: th.vslideup.vi v8, v9, 9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.nxv2f32( + %0, + %1, + i32 9, + i32 %2) + + ret %a +} + +define @intrinsic_vslideup_mask_vi_nxv2f32_nxv2f32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv2f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e32, m1, d1 +; CHECK-NEXT: th.vslideup.vi v8, v9, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.mask.nxv2f32( + %0, + %1, + i32 9, + %2, + i32 %3) + + ret %a +} + +declare @llvm.riscv.th.vslideup.nxv4f32( + , + , + i32, + i32 +); + +define @intrinsic_vslideup_vx_nxv4f32_nxv4f32( %0, %1, i32 %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vx_nxv4f32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vslideup.vx v8, v10, a0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.nxv4f32( + %0, + %1, + i32 %2, + i32 %3) + + ret %a +} + +declare @llvm.riscv.th.vslideup.mask.nxv4f32( + , + , + i32, + , + i32); + +define @intrinsic_vslideup_mask_vx_nxv4f32_nxv4f32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv4f32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vslideup.vx v8, v10, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.mask.nxv4f32( + %0, + %1, + i32 %2, + %3, + i32 %4) + + ret %a +} + +define @intrinsic_vslideup_vi_nxv4f32_nxv4f32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vi_nxv4f32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e32, m2, d1 +; CHECK-NEXT: th.vslideup.vi v8, v10, 9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.nxv4f32( + %0, + %1, + i32 9, + i32 %2) + + ret %a +} + +define @intrinsic_vslideup_mask_vi_nxv4f32_nxv4f32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv4f32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e32, m2, d1 +; CHECK-NEXT: th.vslideup.vi v8, v10, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.mask.nxv4f32( + %0, + %1, + i32 9, + %2, + i32 %3) + + ret %a +} + +declare @llvm.riscv.th.vslideup.nxv8f32( + , + , + i32, + i32 +); + +define @intrinsic_vslideup_vx_nxv8f32_nxv8f32( %0, %1, i32 %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vx_nxv8f32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vslideup.vx v8, v12, a0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.nxv8f32( + %0, + %1, + i32 %2, + i32 %3) + + ret %a +} + +declare @llvm.riscv.th.vslideup.mask.nxv8f32( + , + , + i32, + , + i32); + +define @intrinsic_vslideup_mask_vx_nxv8f32_nxv8f32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv8f32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vslideup.vx v8, v12, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.mask.nxv8f32( + %0, + %1, + i32 %2, + %3, + i32 %4) + + ret %a +} + +define @intrinsic_vslideup_vi_nxv8f32_nxv8f32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vi_nxv8f32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e32, m4, d1 +; CHECK-NEXT: th.vslideup.vi v8, v12, 9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.nxv8f32( + %0, + %1, + i32 9, + i32 %2) + + ret %a +} + +define @intrinsic_vslideup_mask_vi_nxv8f32_nxv8f32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv8f32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e32, m4, d1 +; CHECK-NEXT: th.vslideup.vi v8, v12, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.mask.nxv8f32( + %0, + %1, + i32 9, + %2, + i32 %3) + + ret %a +} + +declare @llvm.riscv.th.vslideup.nxv1f64( + , + , + i32, + i32 +); + +define @intrinsic_vslideup_vx_nxv1f64_nxv1f64( %0, %1, i32 %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vx_nxv1f64_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e64, m1, d1 +; CHECK-NEXT: th.vslideup.vx v8, v9, a0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.nxv1f64( + %0, + %1, + i32 %2, + i32 %3) + + ret %a +} + +declare @llvm.riscv.th.vslideup.mask.nxv1f64( + , + , + i32, + , + i32); + +define @intrinsic_vslideup_mask_vx_nxv1f64_nxv1f64( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv1f64_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e64, m1, d1 +; CHECK-NEXT: th.vslideup.vx v8, v9, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.mask.nxv1f64( + %0, + %1, + i32 %2, + %3, + i32 %4) + + ret %a +} + +define @intrinsic_vslideup_vi_nxv1f64_nxv1f64( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vi_nxv1f64_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e64, m1, d1 +; CHECK-NEXT: th.vslideup.vi v8, v9, 9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.nxv1f64( + %0, + %1, + i32 9, + i32 %2) + + ret %a +} + +define @intrinsic_vslideup_mask_vi_nxv1f64_nxv1f64( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv1f64_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e64, m1, d1 +; CHECK-NEXT: th.vslideup.vi v8, v9, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.mask.nxv1f64( + %0, + %1, + i32 9, + %2, + i32 %3) + + ret %a +} + +declare @llvm.riscv.th.vslideup.nxv2f64( + , + , + i32, + i32 +); + +define @intrinsic_vslideup_vx_nxv2f64_nxv2f64( %0, %1, i32 %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vx_nxv2f64_nxv2f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e64, m2, d1 +; CHECK-NEXT: th.vslideup.vx v8, v10, a0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.nxv2f64( + %0, + %1, + i32 %2, + i32 %3) + + ret %a +} + +declare @llvm.riscv.th.vslideup.mask.nxv2f64( + , + , + i32, + , + i32); + +define @intrinsic_vslideup_mask_vx_nxv2f64_nxv2f64( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv2f64_nxv2f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e64, m2, d1 +; CHECK-NEXT: th.vslideup.vx v8, v10, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.mask.nxv2f64( + %0, + %1, + i32 %2, + %3, + i32 %4) + + ret %a +} + +define @intrinsic_vslideup_vi_nxv2f64_nxv2f64( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vi_nxv2f64_nxv2f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e64, m2, d1 +; CHECK-NEXT: th.vslideup.vi v8, v10, 9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.nxv2f64( + %0, + %1, + i32 9, + i32 %2) + + ret %a +} + +define @intrinsic_vslideup_mask_vi_nxv2f64_nxv2f64( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv2f64_nxv2f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e64, m2, d1 +; CHECK-NEXT: th.vslideup.vi v8, v10, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.mask.nxv2f64( + %0, + %1, + i32 9, + %2, + i32 %3) + + ret %a +} + +declare @llvm.riscv.th.vslideup.nxv4f64( + , + , + i32, + i32 +); + +define @intrinsic_vslideup_vx_nxv4f64_nxv4f64( %0, %1, i32 %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vx_nxv4f64_nxv4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e64, m4, d1 +; CHECK-NEXT: th.vslideup.vx v8, v12, a0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.nxv4f64( + %0, + %1, + i32 %2, + i32 %3) + + ret %a +} + +declare @llvm.riscv.th.vslideup.mask.nxv4f64( + , + , + i32, + , + i32); + +define @intrinsic_vslideup_mask_vx_nxv4f64_nxv4f64( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv4f64_nxv4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e64, m4, d1 +; CHECK-NEXT: th.vslideup.vx v8, v12, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.mask.nxv4f64( + %0, + %1, + i32 %2, + %3, + i32 %4) + + ret %a +} + +define @intrinsic_vslideup_vi_nxv4f64_nxv4f64( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vi_nxv4f64_nxv4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e64, m4, d1 +; CHECK-NEXT: th.vslideup.vi v8, v12, 9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.nxv4f64( + %0, + %1, + i32 9, + i32 %2) + + ret %a +} + +define @intrinsic_vslideup_mask_vi_nxv4f64_nxv4f64( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv4f64_nxv4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e64, m4, d1 +; CHECK-NEXT: th.vslideup.vi v8, v12, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.mask.nxv4f64( + %0, + %1, + i32 9, + %2, + i32 %3) + + ret %a +} diff --git a/llvm/test/CodeGen/RISCV/rvv0p71/vslideup-rv64.ll b/llvm/test/CodeGen/RISCV/rvv0p71/vslideup-rv64.ll new file mode 100644 index 00000000000000..f7a693c964e869 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/rvv0p71/vslideup-rv64.ll @@ -0,0 +1,1683 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=riscv64 -mattr=+xtheadvector,+d -verify-machineinstrs \ +; RUN: < %s | FileCheck %s + +declare @llvm.riscv.th.vslideup.nxv8i8( + , + , + i64, + i64 +); + +define @intrinsic_vslideup_vx_nxv8i8_nxv8i8( %0, %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vx_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e8, m1, d1 +; CHECK-NEXT: th.vslideup.vx v8, v9, a0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.nxv8i8( + %0, + %1, + i64 %2, + i64 %3) + + ret %a +} + +declare @llvm.riscv.th.vslideup.mask.nxv8i8( + , + , + i64, + , + i64); + +define @intrinsic_vslideup_mask_vx_nxv8i8_nxv8i8( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e8, m1, d1 +; CHECK-NEXT: th.vslideup.vx v8, v9, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.mask.nxv8i8( + %0, + %1, + i64 %2, + %3, + i64 %4) + + ret %a +} + +define @intrinsic_vslideup_vi_nxv8i8_nxv8i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vi_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e8, m1, d1 +; CHECK-NEXT: th.vslideup.vi v8, v9, 9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.nxv8i8( + %0, + %1, + i64 9, + i64 %2) + + ret %a +} + +define @intrinsic_vslideup_mask_vi_nxv8i8_nxv8i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e8, m1, d1 +; CHECK-NEXT: th.vslideup.vi v8, v9, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.mask.nxv8i8( + %0, + %1, + i64 9, + %2, + i64 %3) + + ret %a +} + +declare @llvm.riscv.th.vslideup.nxv16i8( + , + , + i64, + i64 +); + +define @intrinsic_vslideup_vx_nxv16i8_nxv16i8( %0, %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vx_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e8, m2, d1 +; CHECK-NEXT: th.vslideup.vx v8, v10, a0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.nxv16i8( + %0, + %1, + i64 %2, + i64 %3) + + ret %a +} + +declare @llvm.riscv.th.vslideup.mask.nxv16i8( + , + , + i64, + , + i64); + +define @intrinsic_vslideup_mask_vx_nxv16i8_nxv16i8( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e8, m2, d1 +; CHECK-NEXT: th.vslideup.vx v8, v10, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.mask.nxv16i8( + %0, + %1, + i64 %2, + %3, + i64 %4) + + ret %a +} + +define @intrinsic_vslideup_vi_nxv16i8_nxv16i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vi_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e8, m2, d1 +; CHECK-NEXT: th.vslideup.vi v8, v10, 9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.nxv16i8( + %0, + %1, + i64 9, + i64 %2) + + ret %a +} + +define @intrinsic_vslideup_mask_vi_nxv16i8_nxv16i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e8, m2, d1 +; CHECK-NEXT: th.vslideup.vi v8, v10, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.mask.nxv16i8( + %0, + %1, + i64 9, + %2, + i64 %3) + + ret %a +} + +declare @llvm.riscv.th.vslideup.nxv32i8( + , + , + i64, + i64 +); + +define @intrinsic_vslideup_vx_nxv32i8_nxv32i8( %0, %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vx_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e8, m4, d1 +; CHECK-NEXT: th.vslideup.vx v8, v12, a0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.nxv32i8( + %0, + %1, + i64 %2, + i64 %3) + + ret %a +} + +declare @llvm.riscv.th.vslideup.mask.nxv32i8( + , + , + i64, + , + i64); + +define @intrinsic_vslideup_mask_vx_nxv32i8_nxv32i8( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e8, m4, d1 +; CHECK-NEXT: th.vslideup.vx v8, v12, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.mask.nxv32i8( + %0, + %1, + i64 %2, + %3, + i64 %4) + + ret %a +} + +define @intrinsic_vslideup_vi_nxv32i8_nxv32i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vi_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e8, m4, d1 +; CHECK-NEXT: th.vslideup.vi v8, v12, 9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.nxv32i8( + %0, + %1, + i64 9, + i64 %2) + + ret %a +} + +define @intrinsic_vslideup_mask_vi_nxv32i8_nxv32i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e8, m4, d1 +; CHECK-NEXT: th.vslideup.vi v8, v12, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.mask.nxv32i8( + %0, + %1, + i64 9, + %2, + i64 %3) + + ret %a +} + +declare @llvm.riscv.th.vslideup.nxv4i16( + , + , + i64, + i64 +); + +define @intrinsic_vslideup_vx_nxv4i16_nxv4i16( %0, %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vx_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e16, m1, d1 +; CHECK-NEXT: th.vslideup.vx v8, v9, a0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.nxv4i16( + %0, + %1, + i64 %2, + i64 %3) + + ret %a +} + +declare @llvm.riscv.th.vslideup.mask.nxv4i16( + , + , + i64, + , + i64); + +define @intrinsic_vslideup_mask_vx_nxv4i16_nxv4i16( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e16, m1, d1 +; CHECK-NEXT: th.vslideup.vx v8, v9, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.mask.nxv4i16( + %0, + %1, + i64 %2, + %3, + i64 %4) + + ret %a +} + +define @intrinsic_vslideup_vi_nxv4i16_nxv4i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vi_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e16, m1, d1 +; CHECK-NEXT: th.vslideup.vi v8, v9, 9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.nxv4i16( + %0, + %1, + i64 9, + i64 %2) + + ret %a +} + +define @intrinsic_vslideup_mask_vi_nxv4i16_nxv4i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e16, m1, d1 +; CHECK-NEXT: th.vslideup.vi v8, v9, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.mask.nxv4i16( + %0, + %1, + i64 9, + %2, + i64 %3) + + ret %a +} + +declare @llvm.riscv.th.vslideup.nxv8i16( + , + , + i64, + i64 +); + +define @intrinsic_vslideup_vx_nxv8i16_nxv8i16( %0, %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vx_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e16, m2, d1 +; CHECK-NEXT: th.vslideup.vx v8, v10, a0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.nxv8i16( + %0, + %1, + i64 %2, + i64 %3) + + ret %a +} + +declare @llvm.riscv.th.vslideup.mask.nxv8i16( + , + , + i64, + , + i64); + +define @intrinsic_vslideup_mask_vx_nxv8i16_nxv8i16( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e16, m2, d1 +; CHECK-NEXT: th.vslideup.vx v8, v10, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.mask.nxv8i16( + %0, + %1, + i64 %2, + %3, + i64 %4) + + ret %a +} + +define @intrinsic_vslideup_vi_nxv8i16_nxv8i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vi_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e16, m2, d1 +; CHECK-NEXT: th.vslideup.vi v8, v10, 9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.nxv8i16( + %0, + %1, + i64 9, + i64 %2) + + ret %a +} + +define @intrinsic_vslideup_mask_vi_nxv8i16_nxv8i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e16, m2, d1 +; CHECK-NEXT: th.vslideup.vi v8, v10, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.mask.nxv8i16( + %0, + %1, + i64 9, + %2, + i64 %3) + + ret %a +} + +declare @llvm.riscv.th.vslideup.nxv16i16( + , + , + i64, + i64 +); + +define @intrinsic_vslideup_vx_nxv16i16_nxv16i16( %0, %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vx_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e16, m4, d1 +; CHECK-NEXT: th.vslideup.vx v8, v12, a0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.nxv16i16( + %0, + %1, + i64 %2, + i64 %3) + + ret %a +} + +declare @llvm.riscv.th.vslideup.mask.nxv16i16( + , + , + i64, + , + i64); + +define @intrinsic_vslideup_mask_vx_nxv16i16_nxv16i16( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e16, m4, d1 +; CHECK-NEXT: th.vslideup.vx v8, v12, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.mask.nxv16i16( + %0, + %1, + i64 %2, + %3, + i64 %4) + + ret %a +} + +define @intrinsic_vslideup_vi_nxv16i16_nxv16i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vi_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e16, m4, d1 +; CHECK-NEXT: th.vslideup.vi v8, v12, 9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.nxv16i16( + %0, + %1, + i64 9, + i64 %2) + + ret %a +} + +define @intrinsic_vslideup_mask_vi_nxv16i16_nxv16i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e16, m4, d1 +; CHECK-NEXT: th.vslideup.vi v8, v12, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.mask.nxv16i16( + %0, + %1, + i64 9, + %2, + i64 %3) + + ret %a +} + +declare @llvm.riscv.th.vslideup.nxv2i32( + , + , + i64, + i64 +); + +define @intrinsic_vslideup_vx_nxv2i32_nxv2i32( %0, %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vx_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vslideup.vx v8, v9, a0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.nxv2i32( + %0, + %1, + i64 %2, + i64 %3) + + ret %a +} + +declare @llvm.riscv.th.vslideup.mask.nxv2i32( + , + , + i64, + , + i64); + +define @intrinsic_vslideup_mask_vx_nxv2i32_nxv2i32( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vslideup.vx v8, v9, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.mask.nxv2i32( + %0, + %1, + i64 %2, + %3, + i64 %4) + + ret %a +} + +define @intrinsic_vslideup_vi_nxv2i32_nxv2i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vi_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e32, m1, d1 +; CHECK-NEXT: th.vslideup.vi v8, v9, 9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.nxv2i32( + %0, + %1, + i64 9, + i64 %2) + + ret %a +} + +define @intrinsic_vslideup_mask_vi_nxv2i32_nxv2i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e32, m1, d1 +; CHECK-NEXT: th.vslideup.vi v8, v9, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.mask.nxv2i32( + %0, + %1, + i64 9, + %2, + i64 %3) + + ret %a +} + +declare @llvm.riscv.th.vslideup.nxv4i32( + , + , + i64, + i64 +); + +define @intrinsic_vslideup_vx_nxv4i32_nxv4i32( %0, %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vx_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vslideup.vx v8, v10, a0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.nxv4i32( + %0, + %1, + i64 %2, + i64 %3) + + ret %a +} + +declare @llvm.riscv.th.vslideup.mask.nxv4i32( + , + , + i64, + , + i64); + +define @intrinsic_vslideup_mask_vx_nxv4i32_nxv4i32( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vslideup.vx v8, v10, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.mask.nxv4i32( + %0, + %1, + i64 %2, + %3, + i64 %4) + + ret %a +} + +define @intrinsic_vslideup_vi_nxv4i32_nxv4i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vi_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e32, m2, d1 +; CHECK-NEXT: th.vslideup.vi v8, v10, 9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.nxv4i32( + %0, + %1, + i64 9, + i64 %2) + + ret %a +} + +define @intrinsic_vslideup_mask_vi_nxv4i32_nxv4i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e32, m2, d1 +; CHECK-NEXT: th.vslideup.vi v8, v10, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.mask.nxv4i32( + %0, + %1, + i64 9, + %2, + i64 %3) + + ret %a +} + +declare @llvm.riscv.th.vslideup.nxv8i32( + , + , + i64, + i64 +); + +define @intrinsic_vslideup_vx_nxv8i32_nxv8i32( %0, %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vx_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vslideup.vx v8, v12, a0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.nxv8i32( + %0, + %1, + i64 %2, + i64 %3) + + ret %a +} + +declare @llvm.riscv.th.vslideup.mask.nxv8i32( + , + , + i64, + , + i64); + +define @intrinsic_vslideup_mask_vx_nxv8i32_nxv8i32( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vslideup.vx v8, v12, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.mask.nxv8i32( + %0, + %1, + i64 %2, + %3, + i64 %4) + + ret %a +} + +define @intrinsic_vslideup_vi_nxv8i32_nxv8i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vi_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e32, m4, d1 +; CHECK-NEXT: th.vslideup.vi v8, v12, 9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.nxv8i32( + %0, + %1, + i64 9, + i64 %2) + + ret %a +} + +define @intrinsic_vslideup_mask_vi_nxv8i32_nxv8i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e32, m4, d1 +; CHECK-NEXT: th.vslideup.vi v8, v12, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.mask.nxv8i32( + %0, + %1, + i64 9, + %2, + i64 %3) + + ret %a +} + +declare @llvm.riscv.th.vslideup.nxv1i64( + , + , + i64, + i64 +); + +define @intrinsic_vslideup_vx_nxv1i64_nxv1i64( %0, %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vx_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e64, m1, d1 +; CHECK-NEXT: th.vslideup.vx v8, v9, a0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.nxv1i64( + %0, + %1, + i64 %2, + i64 %3) + + ret %a +} + +declare @llvm.riscv.th.vslideup.mask.nxv1i64( + , + , + i64, + , + i64); + +define @intrinsic_vslideup_mask_vx_nxv1i64_nxv1i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e64, m1, d1 +; CHECK-NEXT: th.vslideup.vx v8, v9, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.mask.nxv1i64( + %0, + %1, + i64 %2, + %3, + i64 %4) + + ret %a +} + +define @intrinsic_vslideup_vi_nxv1i64_nxv1i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vi_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e64, m1, d1 +; CHECK-NEXT: th.vslideup.vi v8, v9, 9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.nxv1i64( + %0, + %1, + i64 9, + i64 %2) + + ret %a +} + +define @intrinsic_vslideup_mask_vi_nxv1i64_nxv1i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e64, m1, d1 +; CHECK-NEXT: th.vslideup.vi v8, v9, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.mask.nxv1i64( + %0, + %1, + i64 9, + %2, + i64 %3) + + ret %a +} + +declare @llvm.riscv.th.vslideup.nxv2i64( + , + , + i64, + i64 +); + +define @intrinsic_vslideup_vx_nxv2i64_nxv2i64( %0, %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vx_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e64, m2, d1 +; CHECK-NEXT: th.vslideup.vx v8, v10, a0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.nxv2i64( + %0, + %1, + i64 %2, + i64 %3) + + ret %a +} + +declare @llvm.riscv.th.vslideup.mask.nxv2i64( + , + , + i64, + , + i64); + +define @intrinsic_vslideup_mask_vx_nxv2i64_nxv2i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e64, m2, d1 +; CHECK-NEXT: th.vslideup.vx v8, v10, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.mask.nxv2i64( + %0, + %1, + i64 %2, + %3, + i64 %4) + + ret %a +} + +define @intrinsic_vslideup_vi_nxv2i64_nxv2i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vi_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e64, m2, d1 +; CHECK-NEXT: th.vslideup.vi v8, v10, 9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.nxv2i64( + %0, + %1, + i64 9, + i64 %2) + + ret %a +} + +define @intrinsic_vslideup_mask_vi_nxv2i64_nxv2i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e64, m2, d1 +; CHECK-NEXT: th.vslideup.vi v8, v10, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.mask.nxv2i64( + %0, + %1, + i64 9, + %2, + i64 %3) + + ret %a +} + +declare @llvm.riscv.th.vslideup.nxv4i64( + , + , + i64, + i64 +); + +define @intrinsic_vslideup_vx_nxv4i64_nxv4i64( %0, %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vx_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e64, m4, d1 +; CHECK-NEXT: th.vslideup.vx v8, v12, a0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.nxv4i64( + %0, + %1, + i64 %2, + i64 %3) + + ret %a +} + +declare @llvm.riscv.th.vslideup.mask.nxv4i64( + , + , + i64, + , + i64); + +define @intrinsic_vslideup_mask_vx_nxv4i64_nxv4i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e64, m4, d1 +; CHECK-NEXT: th.vslideup.vx v8, v12, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.mask.nxv4i64( + %0, + %1, + i64 %2, + %3, + i64 %4) + + ret %a +} + +define @intrinsic_vslideup_vi_nxv4i64_nxv4i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vi_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e64, m4, d1 +; CHECK-NEXT: th.vslideup.vi v8, v12, 9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.nxv4i64( + %0, + %1, + i64 9, + i64 %2) + + ret %a +} + +define @intrinsic_vslideup_mask_vi_nxv4i64_nxv4i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e64, m4, d1 +; CHECK-NEXT: th.vslideup.vi v8, v12, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.mask.nxv4i64( + %0, + %1, + i64 9, + %2, + i64 %3) + + ret %a +} + +declare @llvm.riscv.th.vslideup.nxv4f16( + , + , + i64, + i64 +); + +define @intrinsic_vslideup_vx_nxv4f16_nxv4f16( %0, %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vx_nxv4f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e16, m1, d1 +; CHECK-NEXT: th.vslideup.vx v8, v9, a0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.nxv4f16( + %0, + %1, + i64 %2, + i64 %3) + + ret %a +} + +declare @llvm.riscv.th.vslideup.mask.nxv4f16( + , + , + i64, + , + i64); + +define @intrinsic_vslideup_mask_vx_nxv4f16_nxv4f16( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv4f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e16, m1, d1 +; CHECK-NEXT: th.vslideup.vx v8, v9, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.mask.nxv4f16( + %0, + %1, + i64 %2, + %3, + i64 %4) + + ret %a +} + +define @intrinsic_vslideup_vi_nxv4f16_nxv4f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vi_nxv4f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e16, m1, d1 +; CHECK-NEXT: th.vslideup.vi v8, v9, 9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.nxv4f16( + %0, + %1, + i64 9, + i64 %2) + + ret %a +} + +define @intrinsic_vslideup_mask_vi_nxv4f16_nxv4f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv4f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e16, m1, d1 +; CHECK-NEXT: th.vslideup.vi v8, v9, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.mask.nxv4f16( + %0, + %1, + i64 9, + %2, + i64 %3) + + ret %a +} + +declare @llvm.riscv.th.vslideup.nxv8f16( + , + , + i64, + i64 +); + +define @intrinsic_vslideup_vx_nxv8f16_nxv8f16( %0, %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vx_nxv8f16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e16, m2, d1 +; CHECK-NEXT: th.vslideup.vx v8, v10, a0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.nxv8f16( + %0, + %1, + i64 %2, + i64 %3) + + ret %a +} + +declare @llvm.riscv.th.vslideup.mask.nxv8f16( + , + , + i64, + , + i64); + +define @intrinsic_vslideup_mask_vx_nxv8f16_nxv8f16( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv8f16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e16, m2, d1 +; CHECK-NEXT: th.vslideup.vx v8, v10, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.mask.nxv8f16( + %0, + %1, + i64 %2, + %3, + i64 %4) + + ret %a +} + +define @intrinsic_vslideup_vi_nxv8f16_nxv8f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vi_nxv8f16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e16, m2, d1 +; CHECK-NEXT: th.vslideup.vi v8, v10, 9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.nxv8f16( + %0, + %1, + i64 9, + i64 %2) + + ret %a +} + +define @intrinsic_vslideup_mask_vi_nxv8f16_nxv8f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv8f16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e16, m2, d1 +; CHECK-NEXT: th.vslideup.vi v8, v10, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.mask.nxv8f16( + %0, + %1, + i64 9, + %2, + i64 %3) + + ret %a +} + +declare @llvm.riscv.th.vslideup.nxv16f16( + , + , + i64, + i64 +); + +define @intrinsic_vslideup_vx_nxv16f16_nxv16f16( %0, %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vx_nxv16f16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e16, m4, d1 +; CHECK-NEXT: th.vslideup.vx v8, v12, a0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.nxv16f16( + %0, + %1, + i64 %2, + i64 %3) + + ret %a +} + +declare @llvm.riscv.th.vslideup.mask.nxv16f16( + , + , + i64, + , + i64); + +define @intrinsic_vslideup_mask_vx_nxv16f16_nxv16f16( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv16f16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e16, m4, d1 +; CHECK-NEXT: th.vslideup.vx v8, v12, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.mask.nxv16f16( + %0, + %1, + i64 %2, + %3, + i64 %4) + + ret %a +} + +define @intrinsic_vslideup_vi_nxv16f16_nxv16f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vi_nxv16f16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e16, m4, d1 +; CHECK-NEXT: th.vslideup.vi v8, v12, 9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.nxv16f16( + %0, + %1, + i64 9, + i64 %2) + + ret %a +} + +define @intrinsic_vslideup_mask_vi_nxv16f16_nxv16f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv16f16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e16, m4, d1 +; CHECK-NEXT: th.vslideup.vi v8, v12, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.mask.nxv16f16( + %0, + %1, + i64 9, + %2, + i64 %3) + + ret %a +} + +declare @llvm.riscv.th.vslideup.nxv2f32( + , + , + i64, + i64 +); + +define @intrinsic_vslideup_vx_nxv2f32_nxv2f32( %0, %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vx_nxv2f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vslideup.vx v8, v9, a0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.nxv2f32( + %0, + %1, + i64 %2, + i64 %3) + + ret %a +} + +declare @llvm.riscv.th.vslideup.mask.nxv2f32( + , + , + i64, + , + i64); + +define @intrinsic_vslideup_mask_vx_nxv2f32_nxv2f32( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv2f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e32, m1, d1 +; CHECK-NEXT: th.vslideup.vx v8, v9, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.mask.nxv2f32( + %0, + %1, + i64 %2, + %3, + i64 %4) + + ret %a +} + +define @intrinsic_vslideup_vi_nxv2f32_nxv2f32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vi_nxv2f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e32, m1, d1 +; CHECK-NEXT: th.vslideup.vi v8, v9, 9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.nxv2f32( + %0, + %1, + i64 9, + i64 %2) + + ret %a +} + +define @intrinsic_vslideup_mask_vi_nxv2f32_nxv2f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv2f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e32, m1, d1 +; CHECK-NEXT: th.vslideup.vi v8, v9, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.mask.nxv2f32( + %0, + %1, + i64 9, + %2, + i64 %3) + + ret %a +} + +declare @llvm.riscv.th.vslideup.nxv4f32( + , + , + i64, + i64 +); + +define @intrinsic_vslideup_vx_nxv4f32_nxv4f32( %0, %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vx_nxv4f32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vslideup.vx v8, v10, a0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.nxv4f32( + %0, + %1, + i64 %2, + i64 %3) + + ret %a +} + +declare @llvm.riscv.th.vslideup.mask.nxv4f32( + , + , + i64, + , + i64); + +define @intrinsic_vslideup_mask_vx_nxv4f32_nxv4f32( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv4f32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e32, m2, d1 +; CHECK-NEXT: th.vslideup.vx v8, v10, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.mask.nxv4f32( + %0, + %1, + i64 %2, + %3, + i64 %4) + + ret %a +} + +define @intrinsic_vslideup_vi_nxv4f32_nxv4f32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vi_nxv4f32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e32, m2, d1 +; CHECK-NEXT: th.vslideup.vi v8, v10, 9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.nxv4f32( + %0, + %1, + i64 9, + i64 %2) + + ret %a +} + +define @intrinsic_vslideup_mask_vi_nxv4f32_nxv4f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv4f32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e32, m2, d1 +; CHECK-NEXT: th.vslideup.vi v8, v10, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.mask.nxv4f32( + %0, + %1, + i64 9, + %2, + i64 %3) + + ret %a +} + +declare @llvm.riscv.th.vslideup.nxv8f32( + , + , + i64, + i64 +); + +define @intrinsic_vslideup_vx_nxv8f32_nxv8f32( %0, %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vx_nxv8f32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vslideup.vx v8, v12, a0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.nxv8f32( + %0, + %1, + i64 %2, + i64 %3) + + ret %a +} + +declare @llvm.riscv.th.vslideup.mask.nxv8f32( + , + , + i64, + , + i64); + +define @intrinsic_vslideup_mask_vx_nxv8f32_nxv8f32( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv8f32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e32, m4, d1 +; CHECK-NEXT: th.vslideup.vx v8, v12, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.mask.nxv8f32( + %0, + %1, + i64 %2, + %3, + i64 %4) + + ret %a +} + +define @intrinsic_vslideup_vi_nxv8f32_nxv8f32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vi_nxv8f32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e32, m4, d1 +; CHECK-NEXT: th.vslideup.vi v8, v12, 9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.nxv8f32( + %0, + %1, + i64 9, + i64 %2) + + ret %a +} + +define @intrinsic_vslideup_mask_vi_nxv8f32_nxv8f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv8f32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e32, m4, d1 +; CHECK-NEXT: th.vslideup.vi v8, v12, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.mask.nxv8f32( + %0, + %1, + i64 9, + %2, + i64 %3) + + ret %a +} + +declare @llvm.riscv.th.vslideup.nxv1f64( + , + , + i64, + i64 +); + +define @intrinsic_vslideup_vx_nxv1f64_nxv1f64( %0, %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vx_nxv1f64_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e64, m1, d1 +; CHECK-NEXT: th.vslideup.vx v8, v9, a0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.nxv1f64( + %0, + %1, + i64 %2, + i64 %3) + + ret %a +} + +declare @llvm.riscv.th.vslideup.mask.nxv1f64( + , + , + i64, + , + i64); + +define @intrinsic_vslideup_mask_vx_nxv1f64_nxv1f64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv1f64_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e64, m1, d1 +; CHECK-NEXT: th.vslideup.vx v8, v9, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.mask.nxv1f64( + %0, + %1, + i64 %2, + %3, + i64 %4) + + ret %a +} + +define @intrinsic_vslideup_vi_nxv1f64_nxv1f64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vi_nxv1f64_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e64, m1, d1 +; CHECK-NEXT: th.vslideup.vi v8, v9, 9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.nxv1f64( + %0, + %1, + i64 9, + i64 %2) + + ret %a +} + +define @intrinsic_vslideup_mask_vi_nxv1f64_nxv1f64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv1f64_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e64, m1, d1 +; CHECK-NEXT: th.vslideup.vi v8, v9, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.mask.nxv1f64( + %0, + %1, + i64 9, + %2, + i64 %3) + + ret %a +} + +declare @llvm.riscv.th.vslideup.nxv2f64( + , + , + i64, + i64 +); + +define @intrinsic_vslideup_vx_nxv2f64_nxv2f64( %0, %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vx_nxv2f64_nxv2f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e64, m2, d1 +; CHECK-NEXT: th.vslideup.vx v8, v10, a0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.nxv2f64( + %0, + %1, + i64 %2, + i64 %3) + + ret %a +} + +declare @llvm.riscv.th.vslideup.mask.nxv2f64( + , + , + i64, + , + i64); + +define @intrinsic_vslideup_mask_vx_nxv2f64_nxv2f64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv2f64_nxv2f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e64, m2, d1 +; CHECK-NEXT: th.vslideup.vx v8, v10, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.mask.nxv2f64( + %0, + %1, + i64 %2, + %3, + i64 %4) + + ret %a +} + +define @intrinsic_vslideup_vi_nxv2f64_nxv2f64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vi_nxv2f64_nxv2f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e64, m2, d1 +; CHECK-NEXT: th.vslideup.vi v8, v10, 9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.nxv2f64( + %0, + %1, + i64 9, + i64 %2) + + ret %a +} + +define @intrinsic_vslideup_mask_vi_nxv2f64_nxv2f64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv2f64_nxv2f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e64, m2, d1 +; CHECK-NEXT: th.vslideup.vi v8, v10, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.mask.nxv2f64( + %0, + %1, + i64 9, + %2, + i64 %3) + + ret %a +} + +declare @llvm.riscv.th.vslideup.nxv4f64( + , + , + i64, + i64 +); + +define @intrinsic_vslideup_vx_nxv4f64_nxv4f64( %0, %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vx_nxv4f64_nxv4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e64, m4, d1 +; CHECK-NEXT: th.vslideup.vx v8, v12, a0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.nxv4f64( + %0, + %1, + i64 %2, + i64 %3) + + ret %a +} + +declare @llvm.riscv.th.vslideup.mask.nxv4f64( + , + , + i64, + , + i64); + +define @intrinsic_vslideup_mask_vx_nxv4f64_nxv4f64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv4f64_nxv4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a1, e64, m4, d1 +; CHECK-NEXT: th.vslideup.vx v8, v12, a0, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.mask.nxv4f64( + %0, + %1, + i64 %2, + %3, + i64 %4) + + ret %a +} + +define @intrinsic_vslideup_vi_nxv4f64_nxv4f64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vi_nxv4f64_nxv4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e64, m4, d1 +; CHECK-NEXT: th.vslideup.vi v8, v12, 9 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.nxv4f64( + %0, + %1, + i64 9, + i64 %2) + + ret %a +} + +define @intrinsic_vslideup_mask_vi_nxv4f64_nxv4f64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv4f64_nxv4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: th.vsetvli zero, a0, e64, m4, d1 +; CHECK-NEXT: th.vslideup.vi v8, v12, 9, v0.t +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.th.vslideup.mask.nxv4f64( + %0, + %1, + i64 9, + %2, + i64 %3) + + ret %a +}