From d8047c4b6f4432c936eaf90ee112e073622c69e5 Mon Sep 17 00:00:00 2001 From: MarcelStenzel Date: Tue, 9 Aug 2022 15:14:25 +0200 Subject: [PATCH 1/7] fix(sw): prevent zero division when calculating clk frequency --- IF/philip_pal/philip_pal/philip_if.py | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/IF/philip_pal/philip_pal/philip_if.py b/IF/philip_pal/philip_pal/philip_if.py index 37d349e..737551e 100644 --- a/IF/philip_pal/philip_pal/philip_if.py +++ b/IF/philip_pal/philip_pal/philip_if.py @@ -684,9 +684,10 @@ def get_spi_clk_freqs(self) -> list: dif_ticks = sm_buf[idx] - sm_buf[idx - 1] if (dif_ticks < 0): dif_ticks += timer_max - elif (dif_ticks == 0): + if (dif_ticks == 0): freqs.append(0) - freqs.append(self.sys_clk() / dif_ticks) + else: + freqs.append(self.sys_clk() / dif_ticks) return freqs def get_spi_clk_stats(self) -> list: From 40b24617a18707e9635174b0e6027c15ebf7d4a8 Mon Sep 17 00:00:00 2001 From: MarcelStenzel Date: Tue, 9 Aug 2022 15:30:02 +0200 Subject: [PATCH 2/7] cleanup(qual): fix errors found by flake8 Add .html to files that are skipped by codespell --- IF/philip_pal/philip_pal/philip_if.py | 8 ++--- QUALIFICATION/digilent_device.py | 3 +- QUALIFICATION/test_spi.py | 52 +++++++++++++++++---------- scripts/static_tests.sh | 2 +- 4 files changed, 40 insertions(+), 25 deletions(-) diff --git a/IF/philip_pal/philip_pal/philip_if.py b/IF/philip_pal/philip_pal/philip_if.py index 737551e..29e7c84 100644 --- a/IF/philip_pal/philip_pal/philip_if.py +++ b/IF/philip_pal/philip_pal/philip_if.py @@ -651,7 +651,6 @@ def _get_stats(self, vals: list): 'e_minus': mean(vals) - min(vals), 'e_plus': max(vals) - mean(vals), 'stdev': stdev(vals) - } def get_spi_transfer_count(self) -> int: @@ -667,7 +666,7 @@ def sys_clk(self) -> int: if not self._sys_clock: self._sys_clock = self.read_reg('sys.sys_clk')['data'] return self._sys_clock - + def get_spi_clk_freqs(self) -> list: """Calculate frequency of captured timestamps. Returns: @@ -696,7 +695,8 @@ def get_spi_clk_stats(self) -> list: def get_spi_sm_buf(self): """Get buffer of captured timestamps.""" - return self.read_reg("spi.sm_buf", size=self.get_spi_transfer_count())["data"] + return self.read_reg("spi.sm_buf", + size=self.get_spi_transfer_count())["data"] def get_spi_clk_byte_stats(self, byte=None) -> dict: """Get stats for each clock pulse of the spi clk. @@ -708,7 +708,7 @@ def get_spi_clk_byte_stats(self, byte=None) -> dict: """ num_bytes = self.get_spi_clk_frames() bit_freqs = self.get_spi_clk_freqs() - if byte != None: + if byte is not None: assert byte < num_bytes freqs_per_byte = 7 start = byte * freqs_per_byte diff --git a/QUALIFICATION/digilent_device.py b/QUALIFICATION/digilent_device.py index bb80488..463d62a 100755 --- a/QUALIFICATION/digilent_device.py +++ b/QUALIFICATION/digilent_device.py @@ -339,7 +339,8 @@ def pulse(self, pin, time_l, time_h=None, count=1, init_value=0): time_h = time_h or time_l if not isinstance(pin, int): pin = self.pins[pin] - self.driver.pulse_pin(pin, time_l, time_h, count=count, run=True, init_value=init_value) + self.driver.pulse_pin(pin, time_l, time_h, count=count, run=True, + init_value=init_value) def i2c_write_bytes(self, data, addr=None): self._i2c_mode() diff --git a/QUALIFICATION/test_spi.py b/QUALIFICATION/test_spi.py index 1195b73..ee4799f 100644 --- a/QUALIFICATION/test_spi.py +++ b/QUALIFICATION/test_spi.py @@ -10,7 +10,6 @@ DUT_NSS ------------ 9 """ import random -from time import sleep import pytest from digilent_device import DigilentAnalogDiscovery2 from philip_pal import Phil @@ -97,20 +96,21 @@ def speed_tolerance(speed): border['high'] = speed + tolerance return border + def test_spi_freq(phil: Phil, tester_dad2): measurement_if_type = 4 dut_sck_pin = tester_dad2.get_pinout()["DUT_SCK"] input_freq = 10000 - freqs = [] plot_results = [] error_freq_flag = False while input_freq < 5500000: time_step = (1/input_freq)/2 for run in range(8): - #change if_type to any other type to reset measurement + # change if_type to any other type to reset measurement phil.write_and_execute("spi.mode.if_type", 0) phil.write_and_execute("spi.mode.if_type", measurement_if_type) - tester_dad2.pulse(pin=dut_sck_pin, time_l=time_step, time_h=time_step, count=64) + tester_dad2.pulse(pin=dut_sck_pin, time_l=time_step, + time_h=time_step, count=64) results = phil.get_spi_clk_stats() results['input_freq'] = input_freq results['run'] = str(run) @@ -124,16 +124,21 @@ def test_spi_freq(phil: Phil, tester_dad2): input_freq *= 1.05 df = pd.DataFrame(plot_results) - fig = px.scatter(df, x="input_freq", y="mean", color="run", error_x="stdev", error_y_minus="e_minus", - error_y="e_plus", log_x=True, log_y=True, hover_data=['values']) + fig = px.scatter(df, x="input_freq", y="mean", color="run", + error_x="stdev", error_y_minus="e_minus", + error_y="e_plus", log_x=True, log_y=True, + hover_data=['values']) fig.show() - fig = px.scatter(df, x="input_freq", y="error", color="run", + fig.write_html("fig_stats.html") + fig = px.scatter(df, x="input_freq", y="error", color="run", log_x=True, hover_data=['error_per']) + fig.write_html("fig_error.html") fig.show() assert not error_freq_flag -#speed measure is only usable for frequencies up to 5MHz + +# speed measure is only usable for frequencies up to 5MHz @pytest.mark.parametrize("speed", [100000, 400000, 1000000, 5000000]) def test_spi_clock_speed(phil: Phil, tester_dad2, speed): measurement_if_type = 4 @@ -141,16 +146,19 @@ def test_spi_clock_speed(phil: Phil, tester_dad2, speed): time_step = (1/speed)/2 speed_tolerances = speed_tolerance(speed) for pulses in [8, 16, 64]: - #change if_type to any other type to reset measurement + # change if_type to any other type to reset measurement phil.write_and_execute("spi.mode.if_type", 0) phil.write_and_execute("spi.mode.if_type", measurement_if_type) - tester_dad2.pulse(pin=dut_sck_pin, time_l=time_step, time_h=time_step, count=pulses, init_value=0) + tester_dad2.pulse(pin=dut_sck_pin, time_l=time_step, time_h=time_step, + count=pulses, init_value=0) frame_stats = phil.get_spi_clk_frame_stats() mean_freq = (frame_stats['mean']) assert phil.read_reg("spi.transfer_count")['data'] == int(pulses) - assert (mean_freq < speed_tolerances['high']) & (mean_freq > speed_tolerances['low']) + assert ((mean_freq < speed_tolerances['high']) & + (mean_freq > speed_tolerances['low'])) assert len(frame_stats['values']) == int(pulses / 8) + def test_spi_specific_byte(phil: Phil, tester_dad2): dut_sck_pin = tester_dad2.get_pinout()["DUT_SCK"] pulses_per_byte = 8 @@ -159,11 +167,13 @@ def test_spi_specific_byte(phil: Phil, tester_dad2): speed1 = 100000 time_step1 = (1/speed1)/2 - tester_dad2.pulse(pin=dut_sck_pin, time_l=time_step1, time_h=time_step1, count=pulses_per_byte, init_value=0) + tester_dad2.pulse(pin=dut_sck_pin, time_l=time_step1, time_h=time_step1, + count=pulses_per_byte, init_value=0) speed2 = 400000 time_step2 = (1/speed2)/2 - tester_dad2.pulse(pin=dut_sck_pin, time_l=time_step2, time_h=time_step2, count=pulses_per_byte, init_value=0) + tester_dad2.pulse(pin=dut_sck_pin, time_l=time_step2, time_h=time_step2, + count=pulses_per_byte, init_value=0) byte_stats1 = phil.get_spi_clk_byte_stats(byte=0) assert len(byte_stats1['values']) == pulses_per_byte - 1 @@ -173,6 +183,7 @@ def test_spi_specific_byte(phil: Phil, tester_dad2): assert len(byte_stats2['values']) == pulses_per_byte - 1 assert byte_stats2['mean'] == speed2 + def test_spi_deadtime(phil: Phil, tester_dad2): measurement_if_type = 4 speed = 100000 @@ -180,13 +191,16 @@ def test_spi_deadtime(phil: Phil, tester_dad2): time_step = (1/speed)/2 pulses = 8 phil.write_and_execute("spi.mode.if_type", measurement_if_type) - tester_dad2.pulse(pin=dut_sck_pin, time_l=time_step, time_h=time_step, count=pulses, init_value=0) - tester_dad2.pulse(pin=dut_sck_pin, time_l=time_step, time_h=time_step, count=pulses, init_value=0) + tester_dad2.pulse(pin=dut_sck_pin, time_l=time_step, time_h=time_step, + count=pulses, init_value=0) + tester_dad2.pulse(pin=dut_sck_pin, time_l=time_step, time_h=time_step, + count=pulses, init_value=0) assert phil.read_reg("spi.transfer_count")['data'] == 2 * pulses deadtime = phil.get_spi_clk_deadtime_stats() assert len(deadtime['values']) == 1 assert deadtime['mean'] > int(phil.sys_clk() / speed) + @pytest.mark.parametrize("bytes", [3, 4, 8]) def test_spi_multiple_deadtimes(phil: Phil, tester_dad2, bytes): pulses_per_byte = 8 @@ -196,16 +210,16 @@ def test_spi_multiple_deadtimes(phil: Phil, tester_dad2, bytes): time_step = (1/speed)/2 phil.write_and_execute("spi.mode.if_type", measurement_if_type) for i in range(bytes): - tester_dad2.pulse(pin=dut_sck_pin, time_l=time_step, time_h=time_step, count=pulses_per_byte, init_value=0) - assert phil.read_reg("spi.transfer_count")['data'] == bytes * pulses_per_byte + tester_dad2.pulse(pin=dut_sck_pin, time_l=time_step, time_h=time_step, + count=pulses_per_byte, init_value=0) + assert (phil.read_reg("spi.transfer_count")['data'] == + bytes * pulses_per_byte) deadtime = phil.get_spi_clk_deadtime_stats() assert len(deadtime['values']) == bytes - 1 for i in range(len(deadtime['values'])): assert deadtime['values'][i] > int(phil.sys_clk() / speed) - - def main(): """Main program""" print(__doc__) diff --git a/scripts/static_tests.sh b/scripts/static_tests.sh index 5cf9b2a..a02d36d 100755 --- a/scripts/static_tests.sh +++ b/scripts/static_tests.sh @@ -51,7 +51,7 @@ if [[ $LANG == "c,py" ]] || [[ $LANG == "py" ]]; then run_test "FLAKE8" "flake8" fi -run_test "CODESPELL" "codespell FW/Src/ FW/MMM/ FW/Inc IF/philip_pal/philip_pal QUALIFICATION/ --skip=\"*.csv,*.pyc,*stm32f1xx*\"" +run_test "CODESPELL" "codespell FW/Src/ FW/MMM/ FW/Inc IF/philip_pal/philip_pal QUALIFICATION/ --skip=\"*.csv,*.pyc,*stm32f1xx*,*.html\"" if [[ $LANG == "c,py" ]] || [[ $LANG == "c" ]]; then cd FW From f9da073dd079af6a224a30326cdf24ed51930fbb Mon Sep 17 00:00:00 2001 From: MarcelStenzel Date: Tue, 9 Aug 2022 17:09:00 +0200 Subject: [PATCH 3/7] fix(qual): change specific byte test to check for tolerance instead of absolute value --- QUALIFICATION/test_spi.py | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/QUALIFICATION/test_spi.py b/QUALIFICATION/test_spi.py index ee4799f..9af3918 100644 --- a/QUALIFICATION/test_spi.py +++ b/QUALIFICATION/test_spi.py @@ -90,7 +90,10 @@ def test_spi_if_type_0_all_modes(phil, reg, size, pol, pha): def speed_tolerance(speed): - tolerance = speed * 0.1 + if (speed <= 1000000): + tolerance = speed * 0.03 + else: + tolerance = speed * 0.1 border = {} border['low'] = speed - tolerance border['high'] = speed + tolerance @@ -166,22 +169,28 @@ def test_spi_specific_byte(phil: Phil, tester_dad2): phil.write_and_execute("spi.mode.if_type", measurement_if_type) speed1 = 100000 + tolerances1 = speed_tolerance(speed1) time_step1 = (1/speed1)/2 tester_dad2.pulse(pin=dut_sck_pin, time_l=time_step1, time_h=time_step1, count=pulses_per_byte, init_value=0) speed2 = 400000 + tolerances2 = speed_tolerance(speed2) time_step2 = (1/speed2)/2 tester_dad2.pulse(pin=dut_sck_pin, time_l=time_step2, time_h=time_step2, count=pulses_per_byte, init_value=0) byte_stats1 = phil.get_spi_clk_byte_stats(byte=0) assert len(byte_stats1['values']) == pulses_per_byte - 1 - assert byte_stats1['mean'] == speed1 + mean_freq = byte_stats1['mean'] + assert ((mean_freq < tolerances1['high']) & + (mean_freq > tolerances1['low'])) byte_stats2 = phil.get_spi_clk_byte_stats(byte=1) assert len(byte_stats2['values']) == pulses_per_byte - 1 - assert byte_stats2['mean'] == speed2 + mean_freq = byte_stats2['mean'] + assert ((mean_freq < tolerances2['high']) & + (mean_freq > tolerances2['low'])) def test_spi_deadtime(phil: Phil, tester_dad2): From cfdb3a4c932f568a3e44a7b7242d684440ce12ca Mon Sep 17 00:00:00 2001 From: MarcelStenzel Date: Tue, 9 Aug 2022 17:11:25 +0200 Subject: [PATCH 4/7] fix(qual): add percentage tolerance for adc test --- QUALIFICATION/test_adc.py | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/QUALIFICATION/test_adc.py b/QUALIFICATION/test_adc.py index 0a11c5c..968815f 100755 --- a/QUALIFICATION/test_adc.py +++ b/QUALIFICATION/test_adc.py @@ -13,7 +13,7 @@ @pytest.mark.parametrize("fast_sample", [0, 1]) -@pytest.mark.parametrize("voltage", [0, 0.02, 0.1, 1, 2, 2.5, 3, 3.2, 3.3]) +@pytest.mark.parametrize("voltage", [0.0001, 0.02, 0.1, 1, 2, 2.5, 3, 3.2, 3.3]) def test_anal_acc(phil, tester_dad2, fast_sample, voltage): smp_cnt = phil.read_reg("adc.num_of_samples")["data"] max_voltage = 3.3 @@ -29,8 +29,9 @@ def test_anal_acc(phil, tester_dad2, fast_sample, voltage): phil.reset_mcu() cal_jitter = max(samples) - min(samples) val_error = abs(sta.mean(samples) - voltage) + per_error = abs(val_error / voltage) * 100 - assert val_error < 0.015, "error={}, meas={}".format(val_error, + assert (val_error < 0.025 or per_error < 5), "error={}, meas={}".format(val_error, sta.mean(samples)) assert cal_jitter < 0.025 From c764a0c1ffedf84d877edd79bcf475a9382ca40b Mon Sep 17 00:00:00 2001 From: MarcelStenzel Date: Thu, 11 Aug 2022 11:25:36 +0200 Subject: [PATCH 5/7] doc(qual): Add graphs for SPI qualification --- QUALIFICATION/fig_error_bluepill.html | 71 +++++++++++++++++++++++++++ QUALIFICATION/fig_error_nucleo.html | 71 +++++++++++++++++++++++++++ QUALIFICATION/fig_stats_bluepill.html | 71 +++++++++++++++++++++++++++ QUALIFICATION/fig_stats_nucleo.html | 71 +++++++++++++++++++++++++++ 4 files changed, 284 insertions(+) create mode 100644 QUALIFICATION/fig_error_bluepill.html create mode 100644 QUALIFICATION/fig_error_nucleo.html create mode 100644 QUALIFICATION/fig_stats_bluepill.html create mode 100644 QUALIFICATION/fig_stats_nucleo.html diff --git a/QUALIFICATION/fig_error_bluepill.html b/QUALIFICATION/fig_error_bluepill.html new file mode 100644 index 0000000..f828a8b --- /dev/null +++ b/QUALIFICATION/fig_error_bluepill.html @@ -0,0 +1,71 @@ + + + +
+
+ + \ No newline at end of file diff --git a/QUALIFICATION/fig_error_nucleo.html b/QUALIFICATION/fig_error_nucleo.html new file mode 100644 index 0000000..7c3eb09 --- /dev/null +++ b/QUALIFICATION/fig_error_nucleo.html @@ -0,0 +1,71 @@ + + + +
+
+ + \ No newline at end of file diff --git a/QUALIFICATION/fig_stats_bluepill.html b/QUALIFICATION/fig_stats_bluepill.html new file mode 100644 index 0000000..7429267 --- /dev/null +++ b/QUALIFICATION/fig_stats_bluepill.html @@ -0,0 +1,71 @@ + + + +
+
+ + \ No newline at end of file diff --git a/QUALIFICATION/fig_stats_nucleo.html b/QUALIFICATION/fig_stats_nucleo.html new file mode 100644 index 0000000..32d97b4 --- /dev/null +++ b/QUALIFICATION/fig_stats_nucleo.html @@ -0,0 +1,71 @@ + + + +
+
+ + \ No newline at end of file From 7be30a17c7b99b931e8500c84f6e052d15a9792a Mon Sep 17 00:00:00 2001 From: MarcelStenzel Date: Thu, 11 Aug 2022 11:27:29 +0200 Subject: [PATCH 6/7] tests(qual): Update qualification regtest files --- ...philip_base_if.test_send_and_parse_cmd.out | 2 +- .../test_philip_ext_if.test_read_reg.out | 290 ++++-------------- 2 files changed, 53 insertions(+), 239 deletions(-) diff --git a/IF/philip_pal/tests/_regtest_outputs/test_philip_base_if.test_send_and_parse_cmd.out b/IF/philip_pal/tests/_regtest_outputs/test_philip_base_if.test_send_and_parse_cmd.out index 5272270..c3d2ad0 100644 --- a/IF/philip_pal/tests/_regtest_outputs/test_philip_base_if.test_send_and_parse_cmd.out +++ b/IF/philip_pal/tests/_regtest_outputs/test_philip_base_if.test_send_and_parse_cmd.out @@ -3,4 +3,4 @@ {'cmd': 'rr 0 2', 'data': [0, 1], 'result': 'Success'} {'cmd': 'rr 0 2', 'data': [0, 1], 'result': 'Success'} {'cmd': 'help', 'result': 'Timeout'} -{'cmd': 'version', 'result': 'Success', 'version': '1.2.0'} +{'cmd': 'version', 'result': 'Success', 'version': '1.3.0'} diff --git a/IF/philip_pal/tests/_regtest_outputs/test_philip_ext_if.test_read_reg.out b/IF/philip_pal/tests/_regtest_outputs/test_philip_ext_if.test_read_reg.out index fc38af0..41cebbf 100644 --- a/IF/philip_pal/tests/_regtest_outputs/test_philip_ext_if.test_read_reg.out +++ b/IF/philip_pal/tests/_regtest_outputs/test_philip_ext_if.test_read_reg.out @@ -318,196 +318,55 @@ 0, 0, 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, + 0], + 'name': 'res', + 'result': 'Success'} +{'name': 'rtc.day', 'result': 'Success'} +{'name': 'rtc.hour', 'result': 'Success'} +{'name': 'rtc.minute', 'result': 'Success'} +{'data': 0, 'name': 'rtc.mode.disable', 'result': 'Success'} +{'data': 1, 'name': 'rtc.mode.init', 'result': 'Success'} +{'name': 'rtc.mode.res', 'result': 'Success'} +{'name': 'rtc.res', 'result': 'Success'} +{'name': 'rtc.second', 'result': 'Success'} +{'data': 0, 'name': 'rtc.set_day', 'result': 'Success'} +{'data': 0, 'name': 'rtc.set_hour', 'result': 'Success'} +{'data': 0, 'name': 'rtc.set_minute', 'result': 'Success'} +{'data': 0, 'name': 'rtc.set_second', 'result': 'Success'} +{'data': 0, 'name': 'spi.byte_ticks', 'result': 'Success'} +{'data': 0, 'name': 'spi.dut_miso.io_type', 'result': 'Success'} +{'data': 0, 'name': 'spi.dut_miso.level', 'result': 'Success'} +{'data': 0, 'name': 'spi.dut_miso.pull', 'result': 'Success'} +{'name': 'spi.dut_miso.res', 'result': 'Success'} +{'data': 0, 'name': 'spi.dut_miso.set_level', 'result': 'Success'} +{'data': 0, 'name': 'spi.dut_mosi.io_type', 'result': 'Success'} +{'data': 1, 'name': 'spi.dut_mosi.level', 'result': 'Success'} +{'data': 0, 'name': 'spi.dut_mosi.pull', 'result': 'Success'} +{'name': 'spi.dut_mosi.res', 'result': 'Success'} +{'data': 0, 'name': 'spi.dut_mosi.set_level', 'result': 'Success'} +{'data': 0, 'name': 'spi.dut_nss.io_type', 'result': 'Success'} +{'data': 1, 'name': 'spi.dut_nss.level', 'result': 'Success'} +{'data': 0, 'name': 'spi.dut_nss.pull', 'result': 'Success'} +{'name': 'spi.dut_nss.res', 'result': 'Success'} +{'data': 0, 'name': 'spi.dut_nss.set_level', 'result': 'Success'} +{'data': 0, 'name': 'spi.dut_sck.io_type', 'result': 'Success'} +{'data': 1, 'name': 'spi.dut_sck.level', 'result': 'Success'} +{'data': 0, 'name': 'spi.dut_sck.pull', 'result': 'Success'} +{'name': 'spi.dut_sck.res', 'result': 'Success'} +{'data': 0, 'name': 'spi.dut_sck.set_level', 'result': 'Success'} +{'data': 0, 'name': 'spi.frame_ticks', 'result': 'Success'} +{'data': 0, 'name': 'spi.mode.cpha', 'result': 'Success'} +{'data': 0, 'name': 'spi.mode.cpol', 'result': 'Success'} +{'data': 0, 'name': 'spi.mode.disable', 'result': 'Success'} +{'data': 0, 'name': 'spi.mode.if_type', 'result': 'Success'} +{'data': 1, 'name': 'spi.mode.init', 'result': 'Success'} +{'data': 0, 'name': 'spi.mode.reg_16_big_endian', 'result': 'Success'} +{'data': 0, 'name': 'spi.mode.reg_16_bit', 'result': 'Success'} +{'name': 'spi.mode.res', 'result': 'Success'} +{'data': 0, 'name': 'spi.prev_ticks', 'result': 'Success'} +{'data': 0, 'name': 'spi.r_count', 'result': 'Success'} +{'data': 0, 'name': 'spi.reg_index', 'result': 'Success'} +{'data': [0, 0, 0, 0, @@ -571,53 +430,8 @@ 0, 0, 0], - 'name': 'res', + 'name': 'spi.sm_buf', 'result': 'Success'} -{'name': 'rtc.day', 'result': 'Success'} -{'name': 'rtc.hour', 'result': 'Success'} -{'name': 'rtc.minute', 'result': 'Success'} -{'data': 0, 'name': 'rtc.mode.disable', 'result': 'Success'} -{'data': 1, 'name': 'rtc.mode.init', 'result': 'Success'} -{'name': 'rtc.mode.res', 'result': 'Success'} -{'name': 'rtc.res', 'result': 'Success'} -{'name': 'rtc.second', 'result': 'Success'} -{'data': 0, 'name': 'rtc.set_day', 'result': 'Success'} -{'data': 0, 'name': 'rtc.set_hour', 'result': 'Success'} -{'data': 0, 'name': 'rtc.set_minute', 'result': 'Success'} -{'data': 0, 'name': 'rtc.set_second', 'result': 'Success'} -{'data': 0, 'name': 'spi.byte_ticks', 'result': 'Success'} -{'data': 0, 'name': 'spi.dut_miso.io_type', 'result': 'Success'} -{'data': 1, 'name': 'spi.dut_miso.level', 'result': 'Success'} -{'data': 0, 'name': 'spi.dut_miso.pull', 'result': 'Success'} -{'name': 'spi.dut_miso.res', 'result': 'Success'} -{'data': 0, 'name': 'spi.dut_miso.set_level', 'result': 'Success'} -{'data': 0, 'name': 'spi.dut_mosi.io_type', 'result': 'Success'} -{'data': 1, 'name': 'spi.dut_mosi.level', 'result': 'Success'} -{'data': 0, 'name': 'spi.dut_mosi.pull', 'result': 'Success'} -{'name': 'spi.dut_mosi.res', 'result': 'Success'} -{'data': 0, 'name': 'spi.dut_mosi.set_level', 'result': 'Success'} -{'data': 0, 'name': 'spi.dut_nss.io_type', 'result': 'Success'} -{'data': 1, 'name': 'spi.dut_nss.level', 'result': 'Success'} -{'data': 0, 'name': 'spi.dut_nss.pull', 'result': 'Success'} -{'name': 'spi.dut_nss.res', 'result': 'Success'} -{'data': 0, 'name': 'spi.dut_nss.set_level', 'result': 'Success'} -{'data': 0, 'name': 'spi.dut_sck.io_type', 'result': 'Success'} -{'data': 1, 'name': 'spi.dut_sck.level', 'result': 'Success'} -{'data': 0, 'name': 'spi.dut_sck.pull', 'result': 'Success'} -{'name': 'spi.dut_sck.res', 'result': 'Success'} -{'data': 0, 'name': 'spi.dut_sck.set_level', 'result': 'Success'} -{'data': 0, 'name': 'spi.frame_ticks', 'result': 'Success'} -{'data': 0, 'name': 'spi.mode.cpha', 'result': 'Success'} -{'data': 0, 'name': 'spi.mode.cpol', 'result': 'Success'} -{'data': 0, 'name': 'spi.mode.disable', 'result': 'Success'} -{'data': 0, 'name': 'spi.mode.if_type', 'result': 'Success'} -{'data': 1, 'name': 'spi.mode.init', 'result': 'Success'} -{'data': 0, 'name': 'spi.mode.reg_16_big_endian', 'result': 'Success'} -{'data': 0, 'name': 'spi.mode.reg_16_bit', 'result': 'Success'} -{'data': 0, 'name': 'spi.prev_ticks', 'result': 'Success'} -{'data': 0, 'name': 'spi.r_count', 'result': 'Success'} -{'data': 0, 'name': 'spi.reg_index', 'result': 'Success'} -{'name': 'spi.res', 'result': 'Success'} {'data': 0, 'name': 'spi.start_reg_index', 'result': 'Success'} {'data': 0, 'name': 'spi.state', 'result': 'Success'} {'data': 0, 'name': 'spi.status.bsy', 'result': 'Success'} @@ -639,8 +453,8 @@ {'name': 'sys.build_time.second', 'result': 'Success'} {'name': 'sys.build_time.year', 'result': 'Success'} {'data': 17061, 'name': 'sys.device_num', 'result': 'Success'} -{'data': [0, 0, 2, 1], 'name': 'sys.fw_rev', 'result': 'Success'} -{'data': [0, 0, 2, 1], 'name': 'sys.if_rev', 'result': 'Success'} +{'data': [0, 0, 3, 1], 'name': 'sys.fw_rev', 'result': 'Success'} +{'data': [0, 0, 3, 1], 'name': 'sys.if_rev', 'result': 'Success'} {'data': 0, 'name': 'sys.mode.dut_rst', 'result': 'Success'} {'data': 1, 'name': 'sys.mode.init', 'result': 'Success'} {'name': 'sys.mode.res', 'result': 'Success'} From b17bdaad602c4b738d6394267a5dba25095dfe31 Mon Sep 17 00:00:00 2001 From: MarcelStenzel Date: Thu, 11 Aug 2022 11:28:18 +0200 Subject: [PATCH 7/7] doc(qual): Update qualification readme --- QUALIFICATION/README.md | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/QUALIFICATION/README.md b/QUALIFICATION/README.md index a6cad87..201b6a8 100644 --- a/QUALIFICATION/README.md +++ b/QUALIFICATION/README.md @@ -10,7 +10,7 @@ The released firmware is available in the [releases](https://github.com/riot-app The following are all the tools and packages needed to run the tests. ### Packages -- `sudo pip3 install philip_pal pytest` +- `pip install philip_pal pytest flake8 codespell` - [Digilent Waveforms](https://reference.digilentinc.com/reference/software/waveforms/waveforms-3/start) ### Tools @@ -23,7 +23,7 @@ The following are all the tools and packages needed to run the tests. ## Static Tests Even though any merges should have passed the static tests, the static tests should be run. -Go to the base directory and run `./scripts/static_tests.py`. +Go to the base directory and run `./scripts/static_tests.sh`. Everything should pass without any errors. ## Interface Tests @@ -34,6 +34,7 @@ This can be done on any PHiLIP board as it only confirms the host is up to date 1. Go to the `IF/philip_pal` directory 1. Connect PHiLIP to the computer 1. Flash the binary to the PHiLIP +1. Ensure no pins are connected or floating 1. Run tests with `./setup.py test` 1. Evaluate any changes in regression testing 1. If everything looks good then accept the changes with `./setup.py test --addopts --regtest-reset` @@ -93,6 +94,9 @@ Evaluate the following: - different modes (4) - counts and ticks (tick reading +- 12 us) - register options +- SPI clk tolerance for frequencies up to 1MHz is 3% +- SPI clk tolerance for frequencies between 1MHz and 5MHz is 10% +- Frequencies above 5MHz cannot be supported or @@ -104,6 +108,7 @@ Not tested: ## Timing Tests +Intermittent failures do sometimes occur. This is a known bug. Evaluate the following: - Connect the each pin and toggle the following and verify @@ -119,6 +124,7 @@ To run automated tests: 1. Run `pytest test_timing.py` ## ADC Tests +Error must be less than 25mV Evaluating the following: - Measure ADC samples at different voltages