From 3bcdf609cf84df9434eb764d5cf289a7017093bb Mon Sep 17 00:00:00 2001
From: britovski <49156768+britovski@users.noreply.github.com>
Date: Wed, 23 Oct 2024 22:07:55 -0300
Subject: [PATCH] Leaf SoC added

Signed-off-by: britovski <49156768+britovski@users.noreply.github.com>
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 README.md | 1 +
 1 file changed, 1 insertion(+)

diff --git a/README.md b/README.md
index 0c57be6..ad4fea8 100644
--- a/README.md
+++ b/README.md
@@ -144,6 +144,7 @@ Explore open RISC-V implementations for hands-on learning.
 | **Maestro** | A 5 stage-pipeline RV32I implementation in VHDL. | [Github](https://github.com/Artoriuz/maestro) | 2024-10-18 |
 | **RSD** | RSD: RISC-V Out-of-Order Superscalar Processor. | [Github](https://github.com/rsd-devel/rsd) | 2024-10-18 |
 | **Kronos** | Kronos is a 3-stage in-order RISC-V RV32I_Zicsr_Zifencei core geared towards FPGA implementations. | [Github](https://github.com/SonalPinto/kronos) | 2024-10-18 |
+| **Leaf** | Leaf is a small RV32I SoC for portable applications done in VHDL and implemented both in FPGA and ASIC. | [Github](https://github.com/britovski/leaf) | 2024-10-23 |
 
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