diff --git a/README.md b/README.md
index 12de963..3ddd485 100644
--- a/README.md
+++ b/README.md
@@ -1,143 +1,142 @@
-Learn RISC-V
-================
+# Learn RISC-V
[![Check Markdown links](https://github.com/riscv/learn/actions/workflows/action.yml/badge.svg?branch=main)](https://github.com/riscv/learn/actions/workflows/action.yml)
-A community-driven compilation of RISC-V resources and learning material. The list is dynamically
-updated by the community and categorized based on different contexts of the RISC-V scope, taking
-also into account different levels of experience/knowledge, allowing anyone interested in RISC-V to
-discover RISC-V resources and relevant content (courses, software, documentation, articles etc.) in
-an organized fashion.
-Feel free to navigate through the resources listed below with their descriptions.
+A community-driven compilation of RISC-V resources and learning material. The list is dynamically updated by the community and categorized based on different contexts of the RISC-V scope, taking into account different levels of experience/knowledge, allowing anyone interested in RISC-V to discover resources (courses, software, documentation, articles) in an organized fashion.
-**RISC-V** is an open standard Instruction Set Architecture (ISA) based on established Reduced Instruction Set Computer (RISC) principles.
+**RISC-V** is an open standard Instruction Set Architecture (ISA) based on established Reduced Instruction Set Computer (RISC) principles.
đź‘‹ **Want to learn about RISC-V?** Check out the [Beginner-Level](#-beginner-level-resources) or [Intermediate-Level](#-intermediate-level-resources) learning resources.
-👉 Table of Contents
-
+---
+
+## 👉 Table of Contents
- [Learn RISC-V](#learn-risc-v)
+ - [👉 Table of Contents](#-table-of-contents)
- [âž• Making Contributions](#-making-contributions)
- - [đź“š Learning Roadmap](#-learning-roadmap)
- [đź“™ Resources](#-resources)
- [Learning Resources for RISC-V](#learning-resources-for-risc-v)
- - [🟢 Beginner-level resources](#-beginner-level-resources)
- - [🔵 Intermediate-Level resources](#-intermediate-level-resources)
- - [Softwares and Tools](#softwares-and-tools)
- - [Open RISC-V Implementations](#open-risc-v-implementations)
+ - [🟢 Beginner-Level Resources](#-beginner-level-resources)
+ - [🔵 Intermediate-Level Resources](#-intermediate-level-resources)
+ - [Software and Tools](#software-and-tools)
+ - [Open RISC-V Implementations](#open-risc-v-implementations)
- [Relevant Documentation from RISC-V International](#relevant-documentation-from-risc-v-international)
- - [Articles and presentations](#articles-and-presentations)
-
-## âž• Making Contributions
+ - [Articles and Presentations](#articles-and-presentations)
-We love contributions! Thank you for your interest in contributing to our compilation of tutorial resources for RISC-V.
+---
-Contributing is easy, here are some steps to help get you started:
-
-âś” Browse through the list of beginner and intermediate-level resources [here](#learning-resources-for-risc-v) to see if your resource is already included.
+## âž• Making Contributions
-âś” If not, go to [Issues](https://github.com/riscv/learn/issues), click on `New issue` and select the template for adding a new RISC-V tutorial resource.
+We love contributions! Thank you for your interest in contributing to our RISC-V tutorial compilation.
-âś” Enter the resource information in the fields provided and click `Submit new issue`.
+Contributing is easy! Follow these steps:
-âś” If you have a different contribution, you can select the General Request issue template from the provided issue types.
+âś” Browse the beginner and intermediate-level resources [here](#resources) to check if your resource is already included.
+âś” If not, go to [Issues](https://github.com/riscv/learn/issues), click `New issue`, and select the "Add Resource" template.
+âś” Enter the resource details and submit the issue.
+âś” For other contributions, use the General Request issue template [here](https://github.com/riscv/learn/issues/new/choose).
+âś” Engage with open issues if you have feedback.
-âś” You could also engage with an already open issue.
+We may contact you for more details before adding contributions.
-We may interact with you before adding your contributions.
+
+
+---
## đź“™ Resources
### Learning Resources for RISC-V
-#### 🟢 Beginner-level resources
-
-
+#### 🟢 Beginner-Level Resources
-For those with little or no knowledge of digital logic design. After studying the [**Digital Design**](#digital-design) book in this section, you could jump to the intermediate-level [**edx RVfpga**](#computer-architecture-rvfpga) course if you wish as it expands on concepts discussed in the book.
+For those with little or no knowledge of digital logic design. After studying the [Digital Design](#digital-design) book, you may jump to intermediate-level courses like [RVfpga](#computer-architecture-rvfpga).
-| Resource | Author(s) | Description | Access | Date added |
+| Resource | Author(s) | Description | Access | Date Added |
|---|---|---|---|---|
-| **Digital Design and Computer Architecture RISC-V edition** (good starting point) | Sarah L. Harris, David M. Harris | Covers the foundational knowledge of digital logic design and segues smoothly into RISC-V Processor implementation.
Topics: Number systems and digital representation, Semiconductors and transistors, Logic gates and Digital design, C Programming, RISC-V architecture, RISC-V assembly, Memory systems, Embedded I/O systems | [Amazon book link]| 2024-01-10 |
-| **The RISC-V Reader: An Open Architecture Atlas** | David Patterson, Andrew Waterman| A beginner-friendly introduction to the RISC-V instruction set architecture as readers can start programming after the 2nd chapter.
Topics: Computer architecture, RISC-V Instruction Set Architecture (ISA) | [Available in Chineses, Japanese, Spanish, Portuguese and Korean]| 2024-03-05 |
-|**Computer Architecture Basics** | [CTU Prague - FEE](https://fel.cvut.cz/en) (Pavel Pisa) | This course introduces the fundamentals of computer architecture, covering topics such as binary number representation, CPU design, memory hierarchy, pipelined execution, and speculative execution techniques. It is paired with QtRvSim for demonstrations.
Topics: Computer architecture
| [Online course videos]| 2024-04-16 |
-| **Nand2Tetris** (optional) | Noam Nisan, Shimon Schocken | A free hands-on tutorial on building a general-purpose computer from logic gates using a hardware simulator.
Topics: Logic gates|[webpage] | 2024-01-10 |
-|**learn-FPGA episode I: from blinky to RISC-V**|[BrunoLevy](https://github.com/BrunoLevy)|A beginner's introduction to the digital design of a RISC-V softcore on FPGAs. Episode I gently starts from a very basic blinker in Verilog and morphs it step by step into a basic yet fully functional RISC-V SoC. It also explains how to write programs in C and assembly for the SoC.
Topics: Digital design, FPGA, C Programming, RISC-V assembly
Requirement: Basic knowledge of Verilog|[GitHub]| 2024-01-10 |
-|**Hands-on RISC-V Processor Design**|[Rahul Behl](https://github.com/raulbehl)|This practical tutorial offers a deep dive into the world of computer architecture and processor design, with a specific focus on the RISC-V Instruction Set Architecture (ISA).
Topics: Computer architecture, Processor design, RISC-V Instruction Set Architecture (ISA), SystemVerilog, RISC-V assembly
Requirements: SystemVerilog but not necessary|[webpage] | 2024-01-10 |
-|**LinuxFoundationX: Building a RISC-V CPU Core** | [Steve Hoover](https://www.edx.org/bio/steve-hoover) | This free EdX course by Steve Hoover (founder of Redwood EDA) is a great way for a beginner to get started with digital logic design and basic RISC-V microarchitecture design with the help of modern, freely available open source tools.
Topics: Digital logic design, RISC-V Instruction Set Architecture (ISA), CPU microarchitecture, Transaction-Level Verilog, Makerchip online IDE| [edX Course Link] | 2024-01-10 |
-|**An introduction to Assembly Programming with RISC-V** | [Prof. Edson Borin](https://www.ic.unicamp.br/~edson/index.html) | This book uses RISC-V ISA to teach fundamental assembly programming concepts.
Topics: RISC-V Instruction Set Architecture (ISA), RISC-V assembly| [webpage]| 2024-03-05 |
-|**RISC-V Assembly Introduction in Portuguese** | [Gabriel G. de Brito](https://github.com/gboncoffee) | This course is designed for the Teaching Assistant program at Federal University of Paraná, Brazil, focusing on the basics of RISC-V IM architecture with the [EGG](https://github.com/gboncoffee/egg) emulator.
Topics: RISC-V Instruction Set Architecture (ISA), RISC-V assembly
Requirements: C programming, Digital Design| [Online courses video]| 2024-04-06 |
-|**Step-by-step RISC-V OS development** | [Chen Wang](https://github.com/unicornx) | A practical guidance to develop RISC-V operating systems
Topics: RISC-V Instruction Set Architecture (ISA), Operating systems
Requirements: C programming, Data structures, Linux commands| [Teaching resources] [Online course videos in Chineses] | 2024-03-05 |
-|**Step-by-step RISC-V Compiler development** | [Shao-Ce SUN](https://github.com/sunshaoce) | A practical guidance to develop RISC-V C compiler
Topics: RISC-V Instruction Set Architecture (ISA), Compilier
Requirements: C programming, Data structures| [Teaching resources] [Sample code] [Online course videos in Chineses]| 2024-03-20 |
-|**Architecture 1005: RISC-V Assembly** | [OpenSecurityTraining](https://opensecuritytraining.info/About.html) | The class explores RISC-V RV32I/RV64I ISAs, “C” Compressed and “M” extensions from a security perspective.
Topics: RISC-V ISA, GDB
Requirements: C programming| [Online course videos]| 2024-04-15 |
-
+| **Digital Design & Computer Architecture RISC-V edition** | Sarah L. Harris, David M. Harris | Covers foundational digital logic design and RISC-V processor implementation. | [Amazon](https://www.amazon.com/Digital-Design-Computer-Architecture-RISC-V/dp/0128200642) | 2024-01-10 |
+| **The RISC-V Reader: An Open Architecture Atlas** | David Patterson, Andrew Waterman | Introduction to the RISC-V instruction set. | [RISC-V Reader](http://www.riscbook.com/) | 2024-03-05 |
+| **Computer Architecture Basics** | CTU Prague - FEE (Pavel Pisa) | Course covering computer architecture basics, including CPU design and speculative execution. | [Course Videos](https://cw.fel.cvut.cz/wiki/courses/b35apo/en/lectures/start) | 2024-04-16 |
+| **Nand2Tetris** | Noam Nisan, Shimon Schocken | Build a computer from logic gates using a hardware simulator. | [Website](https://www.nand2tetris.org/) | 2024-01-10 |
+| **learn-FPGA episode I: from blinky to RISC-V** | Bruno Levy | Design an FPGA-based RISC-V softcore starting from a basic Verilog blinker. | [GitHub](https://github.com/BrunoLevy/learn-fpga) | 2024-01-10 |
+| **Hands-on RISC-V Processor Design** | Rahul Behl | Dive into RISC-V processor design using SystemVerilog. | [QuickSilicon](https://quicksilicon.in/course/riscv) | 2024-01-10 |
+| **LinuxFoundationX: Building a RISC-V CPU Core** | Steve Hoover | Free course on RISC-V microarchitecture design using open-source tools. | [edX Course](https://www.edx.org/learn/design/the-linux-foundation-building-a-risc-v-cpu-core) | 2024-01-10 |
+| **An Introduction to Assembly Programming with RISC-V** | Prof. Edson Borin | Teaches RISC-V assembly programming concepts. | [Webpage](https://www.ic.unicamp.br/~edson/riscv-book.html) | 2024-03-05 |
+| **RISC-V Assembly Introduction (Portuguese)** | Gabriel G. de Brito | Focus on basics of RISC-V IM architecture with the EGG emulator. | [Course Videos](https://youtube.com/playlist?list=PLFe3Zrf4uj4vlRF21jK3vzfCuSSJ5I_uB) | 2024-04-06 |
+| **Step-by-step RISC-V OS Development** | Chen Wang | Practical guide for developing RISC-V operating systems. | [Teaching Resources](https://github.com/plctlab/riscv-operating-system-mooc) and [Course Videos (Chinese)](https://www.bilibili.com/video/BV1Q5411w7z5) | 2024-03-05 |
+| **Step-by-step RISC-V Compiler Development** | Shao-Ce SUN | Practical guide to RISC-V C compiler development. | [Teaching Resources](https://github.com/sunshaoce/rvcc-course) and [Course Videos (Chinese)](https://www.bilibili.com/video/BV1gY4y1E7Ue) | 2024-03-20 |
+| **Architecture 1005: RISC-V Assembly** | OpenSecurityTraining | Security-focused exploration of RISC-V ISAs and extensions. | [Course Videos](https://p.ost2.fyi/courses/course-v1:OpenSecurityTraining2+Arch1005_IntroRISCV+2024_v1/course/) | 2024-04-15 |
+
+---
+
+#### 🔵 Intermediate-Level Resources
+
+Advanced learning materials for learners familiar with digital logic design.
+
+| Resource | Author(s) | Description | Access | Date Added |
+|---|---|---|---|---|
+| **Computer Organization & Design (RISC-V Edition)** | David Patterson, John Hennessy | In-depth study of RISC-V ISA and processor implementation. | [Amazon](https://www.amazon.com/Computer-Organization-Design-RISC-V-Architecture/dp/0128203315) | 2024-01-10 |
+| **RVfpga: Computer Architecture with an Industrial RISC-V Core** | Sarah Harris, Daniel Chaver-Martinez | Hands-on learning with commercial RISC-V SoC on FPGAs. | [edX Course](https://www.edx.org/learn/computer-programming/the-linux-foundation-computer-architecture-with-an-industrial-risc-v-core) | 2024-01-10 |
+| **RVfpga (Extended): Understanding Computer Architecture** | Sarah Harris, Daniel Chaver-Martinez | Updated version of the RVfpga course with FPGA and simulation tools. | [RVfpga v3.0 Course Link](https://university.imgtec.com/rvfpga-el2-v3-0-english-downloads-page/) | 2024-02-06 |
+| **Teaching experiences with RVfpga** | ARTECS Group, Complutense University of Madrid | Demonstrates how RVfpga and the Ripes simulator were used in two courses at UCM: Computer Organization (2nd-year course) and Integrated Systems Architecture (4th-year course). | [GitHub](https://github.com/artecs-group/RVfpga-sim-addons) | 2024-10-18 |
+| **learn-FPGA episode II: pipelining** | Bruno Levy | Extends the basic RISC-V softcore from episode I with pipelining and performance optimizations. | [GitHub](https://github.com/BrunoLevy/learn-fpga/blob/master/FemtoRV/TUTORIALS/FROM_BLINKER_TO_RISCV/PIPELINE.md) | 2024-01-10 |
+| **Computer Architecture: A Quantitative Approach (6th Edition)** | David Patterson, John Hennessy | Explores advanced topics like instruction-level parallelism and GPU architectures, using RISC-V. | [Amazon](https://a.co/d/fuvp97D) | 2024-01-10 |
+| **Tutorial: RISC-V Vector Extension Demystified** | Thang Tran | In-depth introduction to the RISC-V vector extension. | [YouTube](https://youtu.be/oTaOd8qr53U) | 2024-01-10 |
+| **Learn with SHAKTI** | Shakti - RISE Lab, IITM | Tutorials on RISC-V assembly programming using the RISC-V toolchain. | [Learn with Shakti](https://shakti.org.in/learn_with_shakti/intro.html) | 2023-12-21 |
+| **LinuxFoundationX: RISC-V Toolchain and Compiler Optimization Techniques** | Aditya Kumar | Develop knowledge of RISC-V toolchain internals and compiler optimizations. | [edX Course](https://www.edx.org/learn/computer-programming/the-linux-foundation-risc-v-toolchain-and-compiler-optimization-techniques) | 2024-01-10 |
+| **RISC-V Optimization Guide** | RISE Project | Actionable optimization recommendations for RISC-V software developers. | [GitHub](https://gitlab.com/riseproject/riscv-optimization-guide) | 2024-02-19 |
+| **RV64GC Linker from Scratch in Go** | Yang Liu, PLCT Lab | Build an RV64GC architecture linker from scratch in Go. | [GitHub](https://github.com/ksco/rvld) and [Course Videos (Chinese)](https://space.bilibili.com/296494084/channel/collectiondetail?sid=857032) | 2024-04-24 |
-
+---
+### Software and Tools
-#### 🔵 Intermediate-Level resources
-A collection of more advanced learning resources for RISC-V
+Tools to enhance understanding or visualize the RISC-V ISA.
-| Resource | Author(s) | Description | Access | Date added |
+| Tool | Author(s) | Description | Access | Date Added |
|---|---|---|---|---|
-| **Computer Organization and Design RISC-V edition: The Hardware Software Interface (2nd edition)** (good starting point)| David A. Patterson, John L. Hennesy | Covers the RISC-V Instruction Set in general and does an in-depth examination of the core RISC-V instructions. It also does a deep dive into RISC-V processor implementations. Each chapter includes real-world applications by tying concepts discussed with available modern computers. The book also highlights the interactions between hardware and software by continuously optimizing a sample software program based on the new hardware concepts introduced in each chapter.
Topics: RISC-V ISA, Real world examples
Requirements: Logic design | [Amazon book link]| 2024-01-10 |
-| **RVfpga: Computer Architecture with an Industrial RISC-V Core** | Sarah Harris, Daniel Chaver-Martinez | This free EdX course expands on topics covered in **Digital Design and Computer Architecture, RISC-V edition** with hands-on learning. This course shows how to target a commercial RISC-V Core and RISC-V system-on-chip (SoC) to FPGA, program the RISC-V SoC, and add more functionalities to the RISC-V SoC
Topics: RVfpga SoC development
Requirements: Digital logic design, C programming, RISC-V ISA, processor microarchitecture, Memory systems, Embedded I/O systems| [Edx course link]| 2024-01-10 |
-| **RVfpga (extended): Understanding Computer Architecture** | Sarah Harris, Daniel Chaver-Martinez | This is an updated and extended version of the free [edx course](#computer-architecture-rvfpga) above. The RVfpga Course in Computer Architecture provides hands-on understanding of a commercial RISC-V processor, RISC-V SoC, and the RISC-V ecosystem. Specifically, the RVfpga v3.0 course shows how to target a VeeR EL2 and a VeeR EH1 based system-on-chip (SoC) to 3 different FPGA boards: the Digilent Basys 3 board ($124 academic price), the Real Digital Boolean board ($74 academic price), and the Digilent Nexys A7 board ($262 academic price). The course can also be completed only in simulation; for that purpose, several simulation tools are provided which enable the user to simulate the system at different levels: from a Boolean/Nexys A7/Basys 3 virtual board down to the VeeR EH1/EL2 pipeline.
Topics: RVfpga SoC development
Requirements: It is highly recommended to read [Digital Design and Computer Architecture, RISC-V edition](#digital-design)| [RVfpga v3.0 course link](https://university.imgtec.com/rvfpga-el2-v3-0-english-downloads-page/) | 2024-02-06 |
-|**learn-FPGA episode II: pipelining**|[BrunoLevy](https://github.com/BrunoLevy)|This tutorial explains how to transform the basic softcore from [episode I](#bruno-levy-episode-1) into an efficient pipelined processor. The tutorial follows a step-by-step approach, starting from a 5-states processor, transforming the states into stages, and solving data and control hazards by first observing what happens in real programs thanks to the included debugger/disassembler. Then it is explained how to gain more performance using register forwarding. Finally, branch prediction is introduced, from the simplest static branch prediction to more elaborate ones (gshare). The effect of the different optimizations are demonstrated using different codes (the classical dhrystones and coremark benchmarks, and a program that computes an image using raytracing).
Topics: Digital desgin, FPGA, C Programming, RISC-V assembly
Requirements: It is highly recommended to read [episode I](#bruno-levy-episode-1) before episode II !| [GitHub]| 2024-01-10 |
-| **Computer Architecture: A Quantitative Approach(6th edition)** | David A. Patterson, John L. Hennesy | Covers advanced computer architecture concepts pertaining to high performance computing principles and domain specific architectures along with examples and exercises pertaining to the RISC-V ISA-(6th Edition onwards). This is a step-up from the first book,(Hardware-Software Interface), with advanced concepts like Instruction , Data and Thread Level Parallelism along with introduction to Vector, SIMD and GPU architectures.It also continues the tradition of using real-world examples to demonstrate the concepts, by introducing memory organizations and architectures of ARM Cortex A8, Intel Core i7, Nvidia GTX-280 GPUs and so on.
Topics: Computer architecture, RISC-V ISA
Requirements: It is highly recommendeded to read [Hardware Software Interface](#hardware-software-interface) before this book| [Amazon book link]| 2024-01-10 |
-| **Tutorial: RISC-V Vector Extension Demystified** | Thang Tran | A very in-depth, three hour long video introduction to the RISC-V Vector extension.
Topics: RISC-V Vector extension| [Youtube video] | 2024-01-10 |
-|**Learn with SHAKTI**| [Shakti - RISE Lab, IITM] | A tutorial on RISC-V assembly programming using the RISC-V toolchain (Spike, riscv-pk, OpenOCD) and basic examples and assignments. More elaborate RISC-V ASM examples can be found in the: [Shakti RISC-V ASM Programmer Manual Part I]
Topics: RISC-V assembly
| [Link to: Learn with Shakti]| 2023-12-21 |
-|**LinuxFoundationX: RISC-V Toolchain and Compiler Optimization Techniques** | Aditya Kumar | Develop a working knowledge of the internals of compiler toolchains and compiler optimization techniques with a focus on RISC-V applications.
Topics: RISC-V Toolchain and Compiler
Requirements: C/C++ programming, Compiler, Git| [edX Course Link] | 2024-01-10 |
-|**RISC-V Optimization Guide** | RISE Project | The intention is to give specific actionable optimization recommendations for software developers writing code for RISC-V application processors.
Topics: RISC-V Optimization| [Github] | 2024-02-19 |
-|**RV64GC Linker from Scratch in Go** | Yang Liu, PLCT Lab | An Open course on RISC-V static linking in Go enables learners to build an RV64GC architecture linker from scratch. Note: The code repository is in English, while the videos and materials are in Chinese.
Topics: Static linkerRequirements: Compilation process, RISC-V ISA, Go| [Github], [Videos], [Materials] | 2024-04-24 |
-
-
-#### Softwares and Tools
-A collection of tools that can be used along with the beginner or intermediate-level learning resources for a better understanding or visualization of the RISC-V ISA
-
-| Resource | Author(s) | Description | Access | Date added |
-|---|---|---|---|---|
-| **emulsiV** | Guillaume Savaton, ESEO | emulsiV is a visual simulator for a simple RISC processor called Virgule. Virgule is a 32-bit RISC processor core that implements a minimal subset of the RISC-V instruction set. Here, “minimal” means that Virgule accepts only the instructions that a C compiler would generate from a pure stand-alone C program. | [website] | 2023-20-12 |
-| **RISC-V Instruction Encoder/Decoder** | LupLab @ University of California, Davis | This tool is an online encoder/decoder for RISC-V instructions. Users can input RISC-V instructions in their assembly or binary format and get the full conversion from one to the other. | [website] | 2023-20-12 |
-| **CREATOR** | Diego Camarmas Alonso,FĂ©lix GarcĂa Carballeira,Alejandro CalderĂłn Mateos,ElĂas del Pozo Puñal | CREATOR is a didactic simulator that allows the development, simulation, and debugging of RISC-V (RV32IMFD) assembly programs intuitively and interactively. It is a web application, so it can be used on any type of device (desktop, tablet, smartphone, etc.) without installing additional software. Only a modern web browser (Google Chrome, Mozilla Firefox, Apple Safari, etc.) is required. | [website] | 2023-20-12 |
-| **QtRvSim** - RISC-V CPU Simulator with Cache and Pipeline Visualization | Computer Architectures Education team at Czech Technical University | QtRvSim is educational simulator with pipeline and cache visualization (RV32IMA/RV64IMA). It supports even M-mode ecalls, ACLINT MTIMER, MSWI, SSWI, related CSR registers, serial port Rx and Tx interrupts and more. | [Github] and [Online] | 2023-20-12 |
-| **RVV intrinsics viewer** | dzaima | A third party documentation website for the vector extension intrinsics, currently including pretty much all intrinsics variations, and fuzzy search. This can be a useful resource when writing rvv code. | [website] | 2023-20-12 |
+| **emulsiV** | Guillaume Savaton | Visual simulator for a minimal 32-bit RISC processor. | [Website](https://eseo-tech.github.io/emulsiV/) | 2023-20-12 |
+| **RISC-V Instruction Encoder/Decoder** | LupLab | Online tool for encoding/decoding RISC-V instructions. | [Website](https://luplab.gitlab.io/rvcodecjs/) | 2023-20-12 |
+| **CREATOR** | Diego Camarmas Alonso, FĂ©lix GarcĂa Carballeira, Alejandro CalderĂłn Mateos, ElĂas del Pozo Puñal | Didactic simulator for RISC-V assembly programs. | [Website](https://creatorsim.github.io/creator/) | 2023-20-12 |
+| **QtRvSim** | CTU Prague | RISC-V simulator with cache and pipeline visualization. | [GitHub](https://github.com/cvut/qtrvsim/) | 2023-20-12 |
+| **RVV Intrinsics Viewer** | dzaima | Documentation for RISC-V vector extension intrinsics. | [Website](https://dzaima.github.io/intrinsics-viewer/) | 2023-20-12 |
+
+---
-#### Open RISC-V Implementations
-A list of open RISC-V Implementations
+### Open RISC-V Implementations
-| Name | Description | Access | Date added |
+Explore open RISC-V implementations for hands-on learning.
+
+| Name | Description | Access | Date Added |
|---|---|---|---|
-| **Pequeno** | Pequeno aka pqr5 is a pipelined in-order RISC-V CPU Core compliant with RV32I | [Github] | 2023-20-12 |
-| **NEORV32** | A tiny, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL. The project is highly documented, powered by a nice community, includes software examples, demo FPGA setups and targets FPGA/RISC-V starters as well as advanced users.| [[GitHub]](https://github.com/stnolting/neorv32) | 2024-01-11 |
+| **Pequeno** | Pipelined in-order RISC-V CPU core compliant with RV32I. | [GitHub](https://github.com/iammituraj/pequeno_riscv) | 2023-20-12 |
+| **NEORV32** | MCU-class RISC-V soft-core CPU, customizable and extensible. | [GitHub](https://github.com/stnolting/neorv32) | 2024-01-11 |
+
+---
### Relevant Documentation from RISC-V International
-| Resource | Description | Access |
+| Document | Description | Access |
|---|---|---|
-| **Member Benefits and Welcome deck** | A set of slides useful for new RISC-V members to familiarize themselves with the scope/organization of the RISC-V community and learn about membership benefits, as well as how to integrate into the community as a member. | [Google Doc]|
-| **Getting Started Guide for RISC-V Members** |This document is intended to give a member’s overview of the RISC-V technical organizations. The intended audience is both for new members as well as a reference for existing members.| [Google Doc]|
-| **RISC-V Technical Wiki** |This page serves as the main anchor point for the most important pieces of technical information for RISC-V. If you're looking for something technical, start here.| [webpage] |
-| **RISC-V Lifecycle Guide** |This document has been created to facilitate RISC-V member participation in the key activities involved in creating and running groups, writing of specifications, and contributing open-source software in support of RISC-V architectures. It is a guide, not the rules. |[Google Doc] |
-|**RISC-V Repository Map** |A central point that directs to different repositories relevant to the RISC-V ecosystem. It includes the technical and non-technical, ISA and non-ISA related, software related, as well as collaboration related repositories for RISC-V available on Github. | [webpage]|
+| **Member Benefits Deck** | Familiarize with RISC-V member benefits and community scope. | [Google Doc](https://docs.google.com/presentation/d/1Q8gMcVwzqdqym3ugl_Q-LW0KMUApO-v8mWVdjqQE-MI/edit#slide=id.gf097992cc3_0_1819) |
+| **Getting Started Guide** | Overview of RISC-V technical organizations for new members. | [Google Doc](https://docs.google.com/document/d/1Qjf6BwMmtqTfzftr3WWf2bRv8Cl4f0qZrWWbr0jCBSU/edit) |
+| **RISC-V Technical Wiki** | Central point for technical information related to RISC-V. | [Wiki](https://wiki.riscv.org) |
+| **RISC-V Lifecycle Guide** | Guide for RISC-V members participating in specification writing and open-source contributions. | [Google Doc](https://docs.google.com/document/d/1Au3veNdNJQKPq-oiQRKTzdgmM72FDaqZOKeH7sOnG04/) |
+| **RISC-V Repository Map** | Central directory of RISC-V-related repositories. | [GitHub Repo Map](https://wiki.riscv.org/display/HOME/GitHub+Repo+Map) |
+---
-### Articles and presentations
+### Articles and Presentations
-| Resource | Author(s) | Description | Access |
+| Resource | Author(s) | Description | Access |
|---|---|---|---|
-| **Design of the RISC-V Instruction Set Architecture** |Andrew Waterman|Andrew Waterman’s Doctorate of Philosophy dissertation in the University of California, Berkeley, about the RISC-V ISA. It covers how RISC-V is a well structured small base ISA with a variety of optional extensions, making RISC-V convenient for a range of purposes from research and education, low-power embedded devices, to more general-purpose, high-performance computing, with the existence of these optional extensions. It provides a comparison of RISC-V to other popular ISAs as well.| [pdf]|
-| **Past, Present and Future of RISC-V** | Krste Asanović | | [YouTube video]|
-| **Is RISC-V the Future** | Roddy Urquhart | |[webpage]|
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+| **Design of the RISC-V Instruction Set Architecture** | Andrew Waterman | PhD dissertation on the structure of the RISC-V ISA. | [PDF](https://www2.eecs.berkeley.edu/Pubs/TechRpts/2016/EECS-2016-1.pdf) |
+| **Past, Present and Future of RISC-V** | Krste Asanović | Overview of RISC-V’s evolution. | [YouTube](https://www.youtube.com/watch?v=RrVRMFjYti0) |
+| **Is RISC-V the Future?** | Roddy Urquhart | Examination of RISC-V’s future potential. | [Article](https://semiengineering.com/is-risc-v-the-future) |