From 4cc518a4f2c09f27f53cfe35a5f939efe14c407f Mon Sep 17 00:00:00 2001 From: Kersten Richter Date: Wed, 7 Aug 2024 12:23:13 -0500 Subject: [PATCH 1/3] Changing .adoc to .edu for wavedrom files --- src/a-st-ext.adoc | 2 +- src/c-st-ext.adoc | 36 +++++++++---------- src/counters.adoc | 2 +- .../{atomic-mem.adoc => atomic-mem.edn} | 0 .../wavedrom/{c-andi.adoc => c-andi.edn} | 0 ...oint-instr.adoc => c-breakpoint-instr.edn} | 0 ...c-cb-format-ls.adoc => c-cb-format-ls.edn} | 0 src/images/wavedrom/{c-ci.adoc => c-ci.edn} | 0 src/images/wavedrom/{c-ciw.adoc => c-ciw.edn} | 0 ...c-cj-format-ls.adoc => c-cj-format-ls.edn} | 0 ...c-cr-format-ls.adoc => c-cr-format-ls.edn} | 0 ...c-cs-format-ls.adoc => c-cs-format-ls.edn} | 0 ...legal-inst.adoc => c-def-illegal-inst.edn} | 0 ...int-reg-immed.adoc => c-int-reg-immed.edn} | 0 ...at.adoc => c-int-reg-to-reg-ca-format.edn} | 0 ...at.adoc => c-int-reg-to-reg-cr-format.edn} | 0 ...const-gen.adoc => c-integer-const-gen.edn} | 0 src/images/wavedrom/{c-mop.adoc => c-mop.edn} | 0 .../{c-nop-instr.adoc => c-nop-instr.edn} | 0 ...store-css.adoc => c-sp-load-store-css.edn} | 0 ...sp-load-store.adoc => c-sp-load-store.edn} | 0 .../{c-srli-srai.adoc => c-srli-srai.edn} | 0 .../{counters-diag.adoc => counters-diag.edn} | 0 .../{cr-register.adoc => cr-register.edn} | 0 ...egisters-new.adoc => cr-registers-new.edn} | 0 .../{csr-instr.adoc => csr-instr.edn} | 0 ...ct-conditional.adoc => ct-conditional.edn} | 0 ...ditional-2.adoc => ct-unconditional-2.edn} | 0 ...nconditional.adoc => ct-unconditional.edn} | 0 src/rv32.adoc | 6 ++-- src/zicsr.adoc | 2 +- src/zimop.adoc | 2 +- 32 files changed, 25 insertions(+), 25 deletions(-) rename src/images/wavedrom/{atomic-mem.adoc => atomic-mem.edn} (100%) rename src/images/wavedrom/{c-andi.adoc => c-andi.edn} (100%) rename src/images/wavedrom/{c-breakpoint-instr.adoc => c-breakpoint-instr.edn} (100%) rename src/images/wavedrom/{c-cb-format-ls.adoc => c-cb-format-ls.edn} (100%) rename src/images/wavedrom/{c-ci.adoc => c-ci.edn} (100%) rename src/images/wavedrom/{c-ciw.adoc => c-ciw.edn} (100%) rename src/images/wavedrom/{c-cj-format-ls.adoc => c-cj-format-ls.edn} (100%) rename src/images/wavedrom/{c-cr-format-ls.adoc => c-cr-format-ls.edn} (100%) rename src/images/wavedrom/{c-cs-format-ls.adoc => c-cs-format-ls.edn} (100%) rename src/images/wavedrom/{c-def-illegal-inst.adoc => c-def-illegal-inst.edn} (100%) rename src/images/wavedrom/{c-int-reg-immed.adoc => c-int-reg-immed.edn} (100%) rename src/images/wavedrom/{c-int-reg-to-reg-ca-format.adoc => c-int-reg-to-reg-ca-format.edn} (100%) rename src/images/wavedrom/{c-int-reg-to-reg-cr-format.adoc => c-int-reg-to-reg-cr-format.edn} (100%) rename src/images/wavedrom/{c-integer-const-gen.adoc => c-integer-const-gen.edn} (100%) rename src/images/wavedrom/{c-mop.adoc => c-mop.edn} (100%) rename src/images/wavedrom/{c-nop-instr.adoc => c-nop-instr.edn} (100%) rename src/images/wavedrom/{c-sp-load-store-css.adoc => c-sp-load-store-css.edn} (100%) rename src/images/wavedrom/{c-sp-load-store.adoc => c-sp-load-store.edn} (100%) rename src/images/wavedrom/{c-srli-srai.adoc => c-srli-srai.edn} (100%) rename src/images/wavedrom/{counters-diag.adoc => counters-diag.edn} (100%) rename src/images/wavedrom/{cr-register.adoc => cr-register.edn} (100%) rename src/images/wavedrom/{cr-registers-new.adoc => cr-registers-new.edn} (100%) rename src/images/wavedrom/{csr-instr.adoc => csr-instr.edn} (100%) rename src/images/wavedrom/{ct-conditional.adoc => ct-conditional.edn} (100%) rename src/images/wavedrom/{ct-unconditional-2.adoc => ct-unconditional-2.edn} (100%) rename src/images/wavedrom/{ct-unconditional.adoc => ct-unconditional.edn} (100%) diff --git a/src/a-st-ext.adoc b/src/a-st-ext.adoc index ff6e3f306..85d658870 100644 --- a/src/a-st-ext.adoc +++ b/src/a-st-ext.adoc @@ -355,7 +355,7 @@ substantially easier to provide in some microarchitectural styles. [[sec:amo]] === "Zaamo" Extension for Atomic Memory Operations -include::images/wavedrom/atomic-mem.adoc[] +include::images/wavedrom/atomic-mem.edn[] The atomic memory operation (AMO) instructions perform read-modify-write operations for multiprocessor synchronization and are encoded with an diff --git a/src/c-st-ext.adoc b/src/c-st-ext.adoc index 6bac419be..b4fce3bcd 100644 --- a/src/c-st-ext.adoc +++ b/src/c-st-ext.adoc @@ -217,7 +217,7 @@ For many RVC instructions, zero-valued immediates are disallowed and encoding space for other instructions requiring fewer operand bits. //[[cr-register]] -//include::images/wavedrom/cr-register.adoc[] +//include::images/wavedrom/cr-register.edn[] //.Compressed 16-bit RVC instructions //(((compressed, 16-bit))) @@ -297,7 +297,7 @@ registers. ==== Stack-Pointer-Based Loads and Stores -include::images/wavedrom/c-sp-load-store.adoc[] +include::images/wavedrom/c-sp-load-store.edn[] [[c-sp-load-store]] //.Stack-Pointer-Based Loads and Stores--these instructions use the CI format. @@ -334,7 +334,7 @@ register _rd_. It computes its effective address by adding the _zero_-extended offset, scaled by 8, to the stack pointer, `x2`. It expands to `fld rd, offset(x2)`. -include::images/wavedrom/c-sp-load-store-css.adoc[] +include::images/wavedrom/c-sp-load-store-css.edn[] [[c-sp-load-store-css]] //.Stack-Pointer-Based Loads and Stores--these instructions use the CSS format. @@ -446,7 +446,7 @@ _zero_-extended offset, scaled by 8, to the base address in register `fld rd′, offset(rs1′)`. [[c-cs-format-ls]] -include::images/wavedrom/c-cs-format-ls.adoc[] +include::images/wavedrom/c-cs-format-ls.edn[] //.Compressed, CS format load and store--these instructions use the CS format. (((compressed, cs-format load and store))) @@ -490,7 +490,7 @@ instructions. As with base RVI instructions, the offsets of all RVC control transfer instructions are in multiples of 2 bytes. [[c-cj-format-ls]] -include::images/wavedrom/c-cj-format-ls.adoc[] +include::images/wavedrom/c-cj-format-ls.edn[] //.Compressed, CJ format load and store--these instructions use the CJ format. (((compressed, cj-format load and store))) @@ -507,7 +507,7 @@ the jump (`pc+2`) to the link register, `x1`. C.JAL expands to `jal x1, offset`. [[c-cr-format-ls]] -include::images/wavedrom/c-cr-format-ls.adoc[] +include::images/wavedrom/c-cr-format-ls.edn[] //.Compressed, CR format load and store--these instructions use the CR format. (((compressed, cr-format load and store))) @@ -535,7 +535,7 @@ bytes is only a very minor change to the base microarchitecture. ==== [[c-cb-format-ls]] -include::images/wavedrom/c-cb-format-ls.adoc[] +include::images/wavedrom/c-cb-format-ls.edn[] //.Compressed, CB format load and store--these instructions use the CB format. (((compressed, cb-format load and store))) @@ -562,7 +562,7 @@ The two constant-generation instructions both use the CI instruction format and can target any integer register. [[c-integer-const-gen]] -include::images/wavedrom/c-integer-const-gen.adoc[] +include::images/wavedrom/c-integer-const-gen.edn[] //.Integer constant generation format. (((compressed, integer constant generation))) @@ -587,7 +587,7 @@ These integer register-immediate operations are encoded in the CI format and perform operations on an integer register and a 6-bit immediate. [[c-integer-register-immediate]] -include::images/wavedrom/c-int-reg-immed.adoc[] +include::images/wavedrom/c-int-reg-immed.edn[] //.Integer register-immediate format. (((compressed, integer register-immediate))) @@ -620,7 +620,7 @@ always 16-byte aligned. ==== [[c-ciw]] -include::images/wavedrom/c-ciw.adoc[] +include::images/wavedrom/c-ciw.edn[] //.CIW format. (((compressed, CIW))) C.ADDI4SPN is a CIW-format instruction that adds a _zero_-extended @@ -632,7 +632,7 @@ _nzuimm_≠0; the code points with _nzuimm_=0 are reserved. [[c-ci]] -include::images/wavedrom/c-ci.adoc[] +include::images/wavedrom/c-ci.edn[] //.CI format. (((compressed, CI))) @@ -650,7 +650,7 @@ all base ISAs, the code points with `_rd_=x0` are HINTs, except those with _shamt[5]_=1 in RV32C. [[c-srli-srai]] -include::images/wavedrom/c-srli-srai.adoc[] +include::images/wavedrom/c-srli-srai.edn[] //.C-SRLI-SRAI format. (((compressed, C.SRLI, C.SRAI))) @@ -686,7 +686,7 @@ that RV128C will not be frozen at the same point as RV32C and RV64C, to allow evaluation of typical usage of 128-bit address-space codes. ==== [[c-andi]] -include::images/wavedrom/c-andi.adoc[] +include::images/wavedrom/c-andi.edn[] //.C.ANDI format (((compressed, C.ANDI))) @@ -698,7 +698,7 @@ expands to `andi rd′, rd′, imm`. ==== Integer Register-Register Operations [[c-cr]] -include::images/wavedrom/c-int-reg-to-reg-cr-format.adoc[] +include::images/wavedrom/c-int-reg-to-reg-cr-format.edn[] //C.CR format ((((compressed. C.CR)))) These instructions use the CR format. @@ -722,7 +722,7 @@ valid when `rs2≠x0` the code points with `rs2=x0` correspond to the C.JALR and C.EBREAK instructions. The code points with `rs2≠x0` and rd=x0 are HINTs. [[c-ca]] -include::images/wavedrom/c-int-reg-to-reg-ca-format.adoc[] +include::images/wavedrom/c-int-reg-to-reg-ca-format.edn[] //C.CA format ((((compressed. C.CA)))) @@ -771,7 +771,7 @@ improvement in static and dynamic compression. ==== Defined Illegal Instruction [[c-def-illegal-inst]] -include::images/wavedrom/c-def-illegal-inst.adoc[] +include::images/wavedrom/c-def-illegal-inst.edn[] ((((compressed. C.DIINST)))) A 16-bit instruction with all bits zero is permanently reserved as an @@ -791,7 +791,7 @@ non-existent memory regions. ==== NOP Instruction [[c-nop-instr]] -include::images/wavedrom/c-nop-instr.adoc[] +include::images/wavedrom/c-nop-instr.edn[] ((((compressed. C.NOPINSTR)))) `C.NOP` is a CI-format instruction that does not change any user-visible @@ -802,7 +802,7 @@ _imm_=0; the code points with _imm_≠0 encode HINTs. ==== Breakpoint Instruction [[c-breakpoint-instr]] -include::images/wavedrom/c-breakpoint-instr.adoc[] +include::images/wavedrom/c-breakpoint-instr.edn[] ((((compressed. C.BREAKPOINTINSTR)))) Debuggers can use the `C.EBREAK` instruction, which expands to `ebreak`, diff --git a/src/counters.adoc b/src/counters.adoc index 7f036b0d8..7ec72108d 100644 --- a/src/counters.adoc +++ b/src/counters.adoc @@ -27,7 +27,7 @@ Some execution environments might prohibit access to counters, for example, to impede timing side-channel attacks. ==== -include::images/wavedrom/counters-diag.adoc[] +include::images/wavedrom/counters-diag.edn[] For base ISAs with XLEN≥64, CSR instructions can access diff --git a/src/images/wavedrom/atomic-mem.adoc b/src/images/wavedrom/atomic-mem.edn similarity index 100% rename from src/images/wavedrom/atomic-mem.adoc rename to src/images/wavedrom/atomic-mem.edn diff --git a/src/images/wavedrom/c-andi.adoc b/src/images/wavedrom/c-andi.edn similarity index 100% rename from src/images/wavedrom/c-andi.adoc rename to src/images/wavedrom/c-andi.edn diff --git a/src/images/wavedrom/c-breakpoint-instr.adoc b/src/images/wavedrom/c-breakpoint-instr.edn similarity index 100% rename from src/images/wavedrom/c-breakpoint-instr.adoc rename to src/images/wavedrom/c-breakpoint-instr.edn diff --git a/src/images/wavedrom/c-cb-format-ls.adoc b/src/images/wavedrom/c-cb-format-ls.edn similarity index 100% rename from src/images/wavedrom/c-cb-format-ls.adoc rename to src/images/wavedrom/c-cb-format-ls.edn diff --git a/src/images/wavedrom/c-ci.adoc b/src/images/wavedrom/c-ci.edn similarity index 100% rename from src/images/wavedrom/c-ci.adoc rename to src/images/wavedrom/c-ci.edn diff --git a/src/images/wavedrom/c-ciw.adoc b/src/images/wavedrom/c-ciw.edn similarity index 100% rename from src/images/wavedrom/c-ciw.adoc rename to src/images/wavedrom/c-ciw.edn diff --git a/src/images/wavedrom/c-cj-format-ls.adoc b/src/images/wavedrom/c-cj-format-ls.edn similarity index 100% rename from src/images/wavedrom/c-cj-format-ls.adoc rename to src/images/wavedrom/c-cj-format-ls.edn diff --git a/src/images/wavedrom/c-cr-format-ls.adoc b/src/images/wavedrom/c-cr-format-ls.edn similarity index 100% rename from src/images/wavedrom/c-cr-format-ls.adoc rename to src/images/wavedrom/c-cr-format-ls.edn diff --git a/src/images/wavedrom/c-cs-format-ls.adoc b/src/images/wavedrom/c-cs-format-ls.edn similarity index 100% rename from src/images/wavedrom/c-cs-format-ls.adoc rename to src/images/wavedrom/c-cs-format-ls.edn diff --git a/src/images/wavedrom/c-def-illegal-inst.adoc b/src/images/wavedrom/c-def-illegal-inst.edn similarity index 100% rename from src/images/wavedrom/c-def-illegal-inst.adoc rename to src/images/wavedrom/c-def-illegal-inst.edn diff --git a/src/images/wavedrom/c-int-reg-immed.adoc b/src/images/wavedrom/c-int-reg-immed.edn similarity index 100% rename from src/images/wavedrom/c-int-reg-immed.adoc rename to src/images/wavedrom/c-int-reg-immed.edn diff --git a/src/images/wavedrom/c-int-reg-to-reg-ca-format.adoc b/src/images/wavedrom/c-int-reg-to-reg-ca-format.edn similarity index 100% rename from src/images/wavedrom/c-int-reg-to-reg-ca-format.adoc rename to src/images/wavedrom/c-int-reg-to-reg-ca-format.edn diff --git a/src/images/wavedrom/c-int-reg-to-reg-cr-format.adoc b/src/images/wavedrom/c-int-reg-to-reg-cr-format.edn similarity index 100% rename from src/images/wavedrom/c-int-reg-to-reg-cr-format.adoc rename to src/images/wavedrom/c-int-reg-to-reg-cr-format.edn diff --git a/src/images/wavedrom/c-integer-const-gen.adoc b/src/images/wavedrom/c-integer-const-gen.edn similarity index 100% rename from src/images/wavedrom/c-integer-const-gen.adoc rename to src/images/wavedrom/c-integer-const-gen.edn diff --git a/src/images/wavedrom/c-mop.adoc b/src/images/wavedrom/c-mop.edn similarity index 100% rename from src/images/wavedrom/c-mop.adoc rename to src/images/wavedrom/c-mop.edn diff --git a/src/images/wavedrom/c-nop-instr.adoc b/src/images/wavedrom/c-nop-instr.edn similarity index 100% rename from src/images/wavedrom/c-nop-instr.adoc rename to src/images/wavedrom/c-nop-instr.edn diff --git a/src/images/wavedrom/c-sp-load-store-css.adoc b/src/images/wavedrom/c-sp-load-store-css.edn similarity index 100% rename from src/images/wavedrom/c-sp-load-store-css.adoc rename to src/images/wavedrom/c-sp-load-store-css.edn diff --git a/src/images/wavedrom/c-sp-load-store.adoc b/src/images/wavedrom/c-sp-load-store.edn similarity index 100% rename from src/images/wavedrom/c-sp-load-store.adoc rename to src/images/wavedrom/c-sp-load-store.edn diff --git a/src/images/wavedrom/c-srli-srai.adoc b/src/images/wavedrom/c-srli-srai.edn similarity index 100% rename from src/images/wavedrom/c-srli-srai.adoc rename to src/images/wavedrom/c-srli-srai.edn diff --git a/src/images/wavedrom/counters-diag.adoc b/src/images/wavedrom/counters-diag.edn similarity index 100% rename from src/images/wavedrom/counters-diag.adoc rename to src/images/wavedrom/counters-diag.edn diff --git a/src/images/wavedrom/cr-register.adoc b/src/images/wavedrom/cr-register.edn similarity index 100% rename from src/images/wavedrom/cr-register.adoc rename to src/images/wavedrom/cr-register.edn diff --git a/src/images/wavedrom/cr-registers-new.adoc b/src/images/wavedrom/cr-registers-new.edn similarity index 100% rename from src/images/wavedrom/cr-registers-new.adoc rename to src/images/wavedrom/cr-registers-new.edn diff --git a/src/images/wavedrom/csr-instr.adoc b/src/images/wavedrom/csr-instr.edn similarity index 100% rename from src/images/wavedrom/csr-instr.adoc rename to src/images/wavedrom/csr-instr.edn diff --git a/src/images/wavedrom/ct-conditional.adoc b/src/images/wavedrom/ct-conditional.edn similarity index 100% rename from src/images/wavedrom/ct-conditional.adoc rename to src/images/wavedrom/ct-conditional.edn diff --git a/src/images/wavedrom/ct-unconditional-2.adoc b/src/images/wavedrom/ct-unconditional-2.edn similarity index 100% rename from src/images/wavedrom/ct-unconditional-2.adoc rename to src/images/wavedrom/ct-unconditional-2.edn diff --git a/src/images/wavedrom/ct-unconditional.adoc b/src/images/wavedrom/ct-unconditional.edn similarity index 100% rename from src/images/wavedrom/ct-unconditional.adoc rename to src/images/wavedrom/ct-unconditional.edn diff --git a/src/rv32.adoc b/src/rv32.adoc index 64949deec..2fac938d0 100644 --- a/src/rv32.adoc +++ b/src/rv32.adoc @@ -444,7 +444,7 @@ than the regular link register. Plain unconditional jumps (assembler pseudoinstruction J) are encoded as a JAL with _rd_=`x0`. -include::images/wavedrom/ct-unconditional.adoc[] +include::images/wavedrom/ct-unconditional.edn[] [[ct-unconditional]] //.The unconditional-jump instruction, JAL @@ -462,7 +462,7 @@ Procedure returns in the standard calling convention (assembler pseudoinstruction RET) are encoded as a JALR with _rd_=`x0`, _rs1_=`x1`, and _imm_=0. -include::images/wavedrom/ct-unconditional-2.adoc[] +include::images/wavedrom/ct-unconditional-2.edn[] [[ct-unconditional-2]] //.The indirect unconditional-jump instruction, JALR @@ -556,7 +556,7 @@ is sign-extended and added to the address of the branch instruction to give the target address. The conditional branch range is ±4 KiB. -include::images/wavedrom/ct-conditional.adoc[] +include::images/wavedrom/ct-conditional.edn[] [[ct-conditional]] //.Conditional branches diff --git a/src/zicsr.adoc b/src/zicsr.adoc index 0e16de4da..8d3db68a7 100644 --- a/src/zicsr.adoc +++ b/src/zicsr.adoc @@ -24,7 +24,7 @@ CSR specifier is encoded in the 12-bit _csr_ field of the instruction held in bits 31-20. The immediate forms use a 5-bit zero-extended immediate encoded in the _rs1_ field. -include::images/wavedrom/csr-instr.adoc[] +include::images/wavedrom/csr-instr.edn[] The CSRRW (Atomic Read/Write CSR) instruction atomically swaps values in the CSRs and integer registers. CSRRW reads the old value of the CSR, diff --git a/src/zimop.adoc b/src/zimop.adoc index 63d882e05..8b50f4451 100644 --- a/src/zimop.adoc +++ b/src/zimop.adoc @@ -76,7 +76,7 @@ Their encoding allows future extensions to define them to read register The Zcmop extension depends upon the Zca extension. -include::images/wavedrom/c-mop.adoc[] +include::images/wavedrom/c-mop.edn[] [[c-mop]] NOTE: Very few suitable 16-bit encoding spaces exist. This space was chosen From 9f0df1b9a156eb4a34cc4bab24dd534366798f33 Mon Sep 17 00:00:00 2001 From: Kersten Richter Date: Wed, 7 Aug 2024 16:42:35 -0500 Subject: [PATCH 2/3] more adoc to edn --- src/a-st-ext.adoc | 2 +- src/d-st-ext.adoc | 18 +++++++-------- src/f-st-ext.adoc | 2 +- .../wavedrom/{d-xwwx.adoc => d-xwwx.edn} | 0 .../{division-op.adoc => division-op.edn} | 0 ...uble-fl-class.adoc => double-fl-class.edn} | 0 ...-fl-compare.adoc => double-fl-compare.edn} | 0 ...-fl-compute.adoc => double-fl-compute.edn} | 0 ...nvert-mv.adoc => double-fl-convert-mv.edn} | 0 .../{double-ls.adoc => double-ls.edn} | 0 ...reakpoint.adoc => env-call-breakpoint.edn} | 0 .../{fcvt-sd-ds.adoc => fcvt-sd-ds.edn} | 0 .../{float-csr.adoc => float-csr.edn} | 0 ...o-int-move.adoc => flt-pt-to-int-move.edn} | 0 ...nstr.adoc => flt-to-flt-sgn-inj-instr.edn} | 0 .../{fnmaddsub.adoc => fnmaddsub.edn} | 0 .../{fsjgnjnx-d.adoc => fsjgnjnx-d.edn} | 0 .../wavedrom/{half-ls.adoc => half-ls.edn} | 0 ...pt-class.adoc => half-pr-flt-pt-class.edn} | 0 ...ompare.adoc => half-pr-flt-pt-compare.edn} | 0 ...-and-mv.adoc => half-prec-conv-and-mv.edn} | 0 ...v.adoc => half-prec-flpt-to-flpt-conv.edn} | 0 .../{half-store.adoc => half-store.edn} | 0 ...nt-nopv_rv32i.adoc => hint-nopv_rv32i.edn} | 0 ...nt-nopv_rv64i.adoc => hint-nopv_rv64i.edn} | 0 ...e_variants.adoc => immediate-variants.edn} | 0 .../{immediate.adoc => immediate.edn} | 0 ...n_formats.adoc => instruction-formats.edn} | 0 ...-lui-aiupc.adoc => int-comp-lui-aiupc.edn} | 0 ...-srai.adoc => int-comp-slli-srli-srai.edn} | 0 .../{int_reg-reg.adoc => int-reg-reg.edn} | 0 ...ational.adoc => integer-computational.edn} | 0 ...l.adoc => load-reserve-st-conditional.edn} | 0 .../{load_store.adoc => load-store.edn} | 0 ...nt-mult.adoc => m-st-ext-for-int-mult.edn} | 0 .../{mem_order.adoc => mem-order.edn} | 0 .../{menvcfgreg.adoc => menvcfgreg.edn} | 0 .../{mm-env-call.adoc => mm-env-call.edn} | 0 src/images/wavedrom/{mop-r.adoc => mop-r.edn} | 0 .../wavedrom/{mop-rr.adoc => mop-rr.edn} | 0 .../wavedrom/{mseccfg.adoc => mseccfg.edn} | 0 .../{mstatushreg.adoc => mstatushreg.edn} | 0 ...tusreg-rv321.adoc => mstatusreg-rv321.edn} | 0 .../{mstatusreg.adoc => mstatusreg.edn} | 0 src/images/wavedrom/{nop-v.adoc => nop-v.edn} | 0 src/images/wavedrom/{nop.adoc => nop.edn} | 0 src/m-st-ext.adoc | 4 ++-- src/machine.adoc | 12 +++++----- src/rv32.adoc | 22 +++++++++---------- src/rv64.adoc | 2 +- src/zfh.adoc | 12 +++++----- src/zimop.adoc | 4 ++-- 52 files changed, 38 insertions(+), 40 deletions(-) rename src/images/wavedrom/{d-xwwx.adoc => d-xwwx.edn} (100%) rename src/images/wavedrom/{division-op.adoc => division-op.edn} (100%) rename src/images/wavedrom/{double-fl-class.adoc => double-fl-class.edn} (100%) rename src/images/wavedrom/{double-fl-compare.adoc => double-fl-compare.edn} (100%) rename src/images/wavedrom/{double-fl-compute.adoc => double-fl-compute.edn} (100%) rename src/images/wavedrom/{double-fl-convert-mv.adoc => double-fl-convert-mv.edn} (100%) rename src/images/wavedrom/{double-ls.adoc => double-ls.edn} (100%) rename src/images/wavedrom/{env_call-breakpoint.adoc => env-call-breakpoint.edn} (100%) rename src/images/wavedrom/{fcvt-sd-ds.adoc => fcvt-sd-ds.edn} (100%) rename src/images/wavedrom/{float-csr.adoc => float-csr.edn} (100%) rename src/images/wavedrom/{flt-pt-to-int-move.adoc => flt-pt-to-int-move.edn} (100%) rename src/images/wavedrom/{flt-to-flt-sgn-inj-instr.adoc => flt-to-flt-sgn-inj-instr.edn} (100%) rename src/images/wavedrom/{fnmaddsub.adoc => fnmaddsub.edn} (100%) rename src/images/wavedrom/{fsjgnjnx-d.adoc => fsjgnjnx-d.edn} (100%) rename src/images/wavedrom/{half-ls.adoc => half-ls.edn} (100%) rename src/images/wavedrom/{half-pr-flt-pt-class.adoc => half-pr-flt-pt-class.edn} (100%) rename src/images/wavedrom/{half-pr-flt-pt-compare.adoc => half-pr-flt-pt-compare.edn} (100%) rename src/images/wavedrom/{half-prec-conv-and-mv.adoc => half-prec-conv-and-mv.edn} (100%) rename src/images/wavedrom/{half-prec-flpt-to-flpt-conv.adoc => half-prec-flpt-to-flpt-conv.edn} (100%) rename src/images/wavedrom/{half-store.adoc => half-store.edn} (100%) rename src/images/wavedrom/{hint-nopv_rv32i.adoc => hint-nopv_rv32i.edn} (100%) rename src/images/wavedrom/{hint-nopv_rv64i.adoc => hint-nopv_rv64i.edn} (100%) rename src/images/wavedrom/{immediate_variants.adoc => immediate-variants.edn} (100%) rename src/images/wavedrom/{immediate.adoc => immediate.edn} (100%) rename src/images/wavedrom/{instruction_formats.adoc => instruction-formats.edn} (100%) rename src/images/wavedrom/{int-comp-lui-aiupc.adoc => int-comp-lui-aiupc.edn} (100%) rename src/images/wavedrom/{int-comp-slli-srli-srai.adoc => int-comp-slli-srli-srai.edn} (100%) rename src/images/wavedrom/{int_reg-reg.adoc => int-reg-reg.edn} (100%) rename src/images/wavedrom/{integer_computational.adoc => integer-computational.edn} (100%) rename src/images/wavedrom/{load-reserve-st-conditional.adoc => load-reserve-st-conditional.edn} (100%) rename src/images/wavedrom/{load_store.adoc => load-store.edn} (100%) rename src/images/wavedrom/{m-st-ext-for-int-mult.adoc => m-st-ext-for-int-mult.edn} (100%) rename src/images/wavedrom/{mem_order.adoc => mem-order.edn} (100%) rename src/images/wavedrom/{menvcfgreg.adoc => menvcfgreg.edn} (100%) rename src/images/wavedrom/{mm-env-call.adoc => mm-env-call.edn} (100%) rename src/images/wavedrom/{mop-r.adoc => mop-r.edn} (100%) rename src/images/wavedrom/{mop-rr.adoc => mop-rr.edn} (100%) rename src/images/wavedrom/{mseccfg.adoc => mseccfg.edn} (100%) rename src/images/wavedrom/{mstatushreg.adoc => mstatushreg.edn} (100%) rename src/images/wavedrom/{mstatusreg-rv321.adoc => mstatusreg-rv321.edn} (100%) rename src/images/wavedrom/{mstatusreg.adoc => mstatusreg.edn} (100%) rename src/images/wavedrom/{nop-v.adoc => nop-v.edn} (100%) rename src/images/wavedrom/{nop.adoc => nop.edn} (100%) diff --git a/src/a-st-ext.adoc b/src/a-st-ext.adoc index 85d658870..abc9ec38c 100644 --- a/src/a-st-ext.adoc +++ b/src/a-st-ext.adoc @@ -54,7 +54,7 @@ same address domain. [[sec:lrsc]] === "Zalrsc" Extension for Load-Reserved/Store-Conditional Instructions -include::images/wavedrom/load-reserve-st-conditional.adoc[] +include::images/wavedrom/load-reserve-st-conditional.edn[] Complex atomic memory operations on a single memory word or doubleword are performed with the load-reserved (LR) and store-conditional (SC) diff --git a/src/d-st-ext.adoc b/src/d-st-ext.adoc index e843ac1bc..fcd90c4c8 100644 --- a/src/d-st-ext.adoc +++ b/src/d-st-ext.adoc @@ -103,7 +103,7 @@ value from the floating-point registers to memory. The double-precision value may be a NaN-boxed single-precision value. ==== -include::images/wavedrom/double-ls.adoc[] +include::images/wavedrom/double-ls.edn[] [[double-ls]] //.Double-precision load and store @@ -119,7 +119,7 @@ The double-precision floating-point computational instructions are defined analogously to their single-precision counterparts, but operate on double-precision operands and produce double-precision results. -include::images/wavedrom/double-fl-compute.adoc[] +include::images/wavedrom/double-fl-compute.edn[] [[fl-compute]] //.Double-precision float computational @@ -143,7 +143,7 @@ All floating-point to integer and integer to floating-point conversion instructions round according to the _rm_ field. Note FCVT.D.W[U] always produces an exact result and is unaffected by rounding mode. -include::images/wavedrom/double-fl-convert-mv.adoc[] +include::images/wavedrom/double-fl-convert-mv.edn[] [[fl-convert-mv]] //.Double-precision float convert and move @@ -157,7 +157,7 @@ never round. (((double-precision, to single-precision))) (((single-precision, to double-precision ))) -include::images/wavedrom/fcvt-sd-ds.adoc[] +include::images/wavedrom/fcvt-sd-ds.edn[] [[fcvt-sd-ds]] //.Double-precision FCVT.S.D and FCVT.D.S @@ -166,7 +166,7 @@ FSGNJN.D, and FSGNJX.D are defined analogously to the single-precision sign-injection instruction. //FSGNJ.D, FSGNJN.D, and FSGNJX.D -include::images/wavedrom/fsjgnjnx-d.adoc[] +include::images/wavedrom/fsjgnjnx-d.edn[] //.Double-precision sign-injection For XLEN≥64 only, instructions are provided to move bit @@ -180,7 +180,7 @@ register _rd_. FMV.X.D and FMV.D.X do not modify the bits being transferred; in particular, the payloads of non-canonical NaNs are preserved. -include::images/wavedrom/d-xwwx.adoc[] +include::images/wavedrom/d-xwwx.edn[] [[fmvxddx]] //.Double-precision float move to _rd_ @@ -214,7 +214,7 @@ analogously to their single-precision counterparts, but operate on double-precision operands. (((floating-point, compare))) -include::images/wavedrom/double-fl-compare.adoc[] +include::images/wavedrom/double-fl-compare.edn[] [[fl-compare]] //.Double-precision float compare @@ -225,8 +225,6 @@ defined analogously to its single-precision counterpart, but operates on double-precision operands. (((floating-point, classify))) -include::images/wavedrom/double-fl-class.adoc[] +include::images/wavedrom/double-fl-class.edn[] [[fl-class]] //.Double-precision float classify - - diff --git a/src/f-st-ext.adoc b/src/f-st-ext.adoc index 739ecf2c3..1a3a764ca 100644 --- a/src/f-st-ext.adoc +++ b/src/f-st-ext.adoc @@ -87,7 +87,7 @@ operations and holds the accrued exception flags, as shown in <>. [[fcsr, Floating-Point Control and Status Register]] .Floating-point control and status register -include::images/wavedrom/float-csr.adoc[] +include::images/wavedrom/float-csr.edn[] The `fcsr` register can be read and written with the FRCSR and FSCSR instructions, which are assembler pseudoinstructions built on the diff --git a/src/images/wavedrom/d-xwwx.adoc b/src/images/wavedrom/d-xwwx.edn similarity index 100% rename from src/images/wavedrom/d-xwwx.adoc rename to src/images/wavedrom/d-xwwx.edn diff --git a/src/images/wavedrom/division-op.adoc b/src/images/wavedrom/division-op.edn similarity index 100% rename from src/images/wavedrom/division-op.adoc rename to src/images/wavedrom/division-op.edn diff --git a/src/images/wavedrom/double-fl-class.adoc b/src/images/wavedrom/double-fl-class.edn similarity index 100% rename from src/images/wavedrom/double-fl-class.adoc rename to src/images/wavedrom/double-fl-class.edn diff --git a/src/images/wavedrom/double-fl-compare.adoc b/src/images/wavedrom/double-fl-compare.edn similarity index 100% rename from src/images/wavedrom/double-fl-compare.adoc rename to src/images/wavedrom/double-fl-compare.edn diff --git a/src/images/wavedrom/double-fl-compute.adoc b/src/images/wavedrom/double-fl-compute.edn similarity index 100% rename from src/images/wavedrom/double-fl-compute.adoc rename to src/images/wavedrom/double-fl-compute.edn diff --git a/src/images/wavedrom/double-fl-convert-mv.adoc b/src/images/wavedrom/double-fl-convert-mv.edn similarity index 100% rename from src/images/wavedrom/double-fl-convert-mv.adoc rename to src/images/wavedrom/double-fl-convert-mv.edn diff --git a/src/images/wavedrom/double-ls.adoc b/src/images/wavedrom/double-ls.edn similarity index 100% rename from src/images/wavedrom/double-ls.adoc rename to src/images/wavedrom/double-ls.edn diff --git a/src/images/wavedrom/env_call-breakpoint.adoc b/src/images/wavedrom/env-call-breakpoint.edn similarity index 100% rename from src/images/wavedrom/env_call-breakpoint.adoc rename to src/images/wavedrom/env-call-breakpoint.edn diff --git a/src/images/wavedrom/fcvt-sd-ds.adoc b/src/images/wavedrom/fcvt-sd-ds.edn similarity index 100% rename from src/images/wavedrom/fcvt-sd-ds.adoc rename to src/images/wavedrom/fcvt-sd-ds.edn diff --git a/src/images/wavedrom/float-csr.adoc b/src/images/wavedrom/float-csr.edn similarity index 100% rename from src/images/wavedrom/float-csr.adoc rename to src/images/wavedrom/float-csr.edn diff --git a/src/images/wavedrom/flt-pt-to-int-move.adoc b/src/images/wavedrom/flt-pt-to-int-move.edn similarity index 100% rename from src/images/wavedrom/flt-pt-to-int-move.adoc rename to src/images/wavedrom/flt-pt-to-int-move.edn diff --git a/src/images/wavedrom/flt-to-flt-sgn-inj-instr.adoc b/src/images/wavedrom/flt-to-flt-sgn-inj-instr.edn similarity index 100% rename from src/images/wavedrom/flt-to-flt-sgn-inj-instr.adoc rename to src/images/wavedrom/flt-to-flt-sgn-inj-instr.edn diff --git a/src/images/wavedrom/fnmaddsub.adoc b/src/images/wavedrom/fnmaddsub.edn similarity index 100% rename from src/images/wavedrom/fnmaddsub.adoc rename to src/images/wavedrom/fnmaddsub.edn diff --git a/src/images/wavedrom/fsjgnjnx-d.adoc b/src/images/wavedrom/fsjgnjnx-d.edn similarity index 100% rename from src/images/wavedrom/fsjgnjnx-d.adoc rename to src/images/wavedrom/fsjgnjnx-d.edn diff --git a/src/images/wavedrom/half-ls.adoc b/src/images/wavedrom/half-ls.edn similarity index 100% rename from src/images/wavedrom/half-ls.adoc rename to src/images/wavedrom/half-ls.edn diff --git a/src/images/wavedrom/half-pr-flt-pt-class.adoc b/src/images/wavedrom/half-pr-flt-pt-class.edn similarity index 100% rename from src/images/wavedrom/half-pr-flt-pt-class.adoc rename to src/images/wavedrom/half-pr-flt-pt-class.edn diff --git a/src/images/wavedrom/half-pr-flt-pt-compare.adoc b/src/images/wavedrom/half-pr-flt-pt-compare.edn similarity index 100% rename from src/images/wavedrom/half-pr-flt-pt-compare.adoc rename to src/images/wavedrom/half-pr-flt-pt-compare.edn diff --git a/src/images/wavedrom/half-prec-conv-and-mv.adoc b/src/images/wavedrom/half-prec-conv-and-mv.edn similarity index 100% rename from src/images/wavedrom/half-prec-conv-and-mv.adoc rename to src/images/wavedrom/half-prec-conv-and-mv.edn diff --git a/src/images/wavedrom/half-prec-flpt-to-flpt-conv.adoc b/src/images/wavedrom/half-prec-flpt-to-flpt-conv.edn similarity index 100% rename from src/images/wavedrom/half-prec-flpt-to-flpt-conv.adoc rename to src/images/wavedrom/half-prec-flpt-to-flpt-conv.edn diff --git a/src/images/wavedrom/half-store.adoc b/src/images/wavedrom/half-store.edn similarity index 100% rename from src/images/wavedrom/half-store.adoc rename to src/images/wavedrom/half-store.edn diff --git a/src/images/wavedrom/hint-nopv_rv32i.adoc b/src/images/wavedrom/hint-nopv_rv32i.edn similarity index 100% rename from src/images/wavedrom/hint-nopv_rv32i.adoc rename to src/images/wavedrom/hint-nopv_rv32i.edn diff --git a/src/images/wavedrom/hint-nopv_rv64i.adoc b/src/images/wavedrom/hint-nopv_rv64i.edn similarity index 100% rename from src/images/wavedrom/hint-nopv_rv64i.adoc rename to src/images/wavedrom/hint-nopv_rv64i.edn diff --git a/src/images/wavedrom/immediate_variants.adoc b/src/images/wavedrom/immediate-variants.edn similarity index 100% rename from src/images/wavedrom/immediate_variants.adoc rename to src/images/wavedrom/immediate-variants.edn diff --git a/src/images/wavedrom/immediate.adoc b/src/images/wavedrom/immediate.edn similarity index 100% rename from src/images/wavedrom/immediate.adoc rename to src/images/wavedrom/immediate.edn diff --git a/src/images/wavedrom/instruction_formats.adoc b/src/images/wavedrom/instruction-formats.edn similarity index 100% rename from src/images/wavedrom/instruction_formats.adoc rename to src/images/wavedrom/instruction-formats.edn diff --git a/src/images/wavedrom/int-comp-lui-aiupc.adoc b/src/images/wavedrom/int-comp-lui-aiupc.edn similarity index 100% rename from src/images/wavedrom/int-comp-lui-aiupc.adoc rename to src/images/wavedrom/int-comp-lui-aiupc.edn diff --git a/src/images/wavedrom/int-comp-slli-srli-srai.adoc b/src/images/wavedrom/int-comp-slli-srli-srai.edn similarity index 100% rename from src/images/wavedrom/int-comp-slli-srli-srai.adoc rename to src/images/wavedrom/int-comp-slli-srli-srai.edn diff --git a/src/images/wavedrom/int_reg-reg.adoc b/src/images/wavedrom/int-reg-reg.edn similarity index 100% rename from src/images/wavedrom/int_reg-reg.adoc rename to src/images/wavedrom/int-reg-reg.edn diff --git a/src/images/wavedrom/integer_computational.adoc b/src/images/wavedrom/integer-computational.edn similarity index 100% rename from src/images/wavedrom/integer_computational.adoc rename to src/images/wavedrom/integer-computational.edn diff --git a/src/images/wavedrom/load-reserve-st-conditional.adoc b/src/images/wavedrom/load-reserve-st-conditional.edn similarity index 100% rename from src/images/wavedrom/load-reserve-st-conditional.adoc rename to src/images/wavedrom/load-reserve-st-conditional.edn diff --git a/src/images/wavedrom/load_store.adoc b/src/images/wavedrom/load-store.edn similarity index 100% rename from src/images/wavedrom/load_store.adoc rename to src/images/wavedrom/load-store.edn diff --git a/src/images/wavedrom/m-st-ext-for-int-mult.adoc b/src/images/wavedrom/m-st-ext-for-int-mult.edn similarity index 100% rename from src/images/wavedrom/m-st-ext-for-int-mult.adoc rename to src/images/wavedrom/m-st-ext-for-int-mult.edn diff --git a/src/images/wavedrom/mem_order.adoc b/src/images/wavedrom/mem-order.edn similarity index 100% rename from src/images/wavedrom/mem_order.adoc rename to src/images/wavedrom/mem-order.edn diff --git a/src/images/wavedrom/menvcfgreg.adoc b/src/images/wavedrom/menvcfgreg.edn similarity index 100% rename from src/images/wavedrom/menvcfgreg.adoc rename to src/images/wavedrom/menvcfgreg.edn diff --git a/src/images/wavedrom/mm-env-call.adoc b/src/images/wavedrom/mm-env-call.edn similarity index 100% rename from src/images/wavedrom/mm-env-call.adoc rename to src/images/wavedrom/mm-env-call.edn diff --git a/src/images/wavedrom/mop-r.adoc b/src/images/wavedrom/mop-r.edn similarity index 100% rename from src/images/wavedrom/mop-r.adoc rename to src/images/wavedrom/mop-r.edn diff --git a/src/images/wavedrom/mop-rr.adoc b/src/images/wavedrom/mop-rr.edn similarity index 100% rename from src/images/wavedrom/mop-rr.adoc rename to src/images/wavedrom/mop-rr.edn diff --git a/src/images/wavedrom/mseccfg.adoc b/src/images/wavedrom/mseccfg.edn similarity index 100% rename from src/images/wavedrom/mseccfg.adoc rename to src/images/wavedrom/mseccfg.edn diff --git a/src/images/wavedrom/mstatushreg.adoc b/src/images/wavedrom/mstatushreg.edn similarity index 100% rename from src/images/wavedrom/mstatushreg.adoc rename to src/images/wavedrom/mstatushreg.edn diff --git a/src/images/wavedrom/mstatusreg-rv321.adoc b/src/images/wavedrom/mstatusreg-rv321.edn similarity index 100% rename from src/images/wavedrom/mstatusreg-rv321.adoc rename to src/images/wavedrom/mstatusreg-rv321.edn diff --git a/src/images/wavedrom/mstatusreg.adoc b/src/images/wavedrom/mstatusreg.edn similarity index 100% rename from src/images/wavedrom/mstatusreg.adoc rename to src/images/wavedrom/mstatusreg.edn diff --git a/src/images/wavedrom/nop-v.adoc b/src/images/wavedrom/nop-v.edn similarity index 100% rename from src/images/wavedrom/nop-v.adoc rename to src/images/wavedrom/nop-v.edn diff --git a/src/images/wavedrom/nop.adoc b/src/images/wavedrom/nop.edn similarity index 100% rename from src/images/wavedrom/nop.adoc rename to src/images/wavedrom/nop.edn diff --git a/src/m-st-ext.adoc b/src/m-st-ext.adoc index 1e09b7ac4..1c036cb82 100644 --- a/src/m-st-ext.adoc +++ b/src/m-st-ext.adoc @@ -15,7 +15,7 @@ accelerators. === Multiplication Operations -include::images/wavedrom/m-st-ext-for-int-mult.adoc[] +include::images/wavedrom/m-st-ext-for-int-mult.edn[] [[m-st-ext-for-int-mult]] //.Multiplication operation instructions (((MUL, MULH))) @@ -52,7 +52,7 @@ to shift both arguments left by 32 bits, then use MULH[[S]U]. === Division Operations -include::images/wavedrom/division-op.adoc[] +include::images/wavedrom/division-op.edn[] [[division-op]] //.Division operation instructions (((MUL, DIV))) diff --git a/src/machine.adoc b/src/machine.adoc index 24a0a7598..c067ac4a9 100644 --- a/src/machine.adoc +++ b/src/machine.adoc @@ -368,18 +368,18 @@ S-level ISA. [[mstatusreg-rv32]] .Machine-mode status (`mstatus`) register for RV32 -include::images/wavedrom/mstatusreg-rv321.adoc[] +include::images/wavedrom/mstatusreg-rv321.edn[] [[mstatusreg]] .Machine-mode status (`mstatus`) register for RV64 -include::images/wavedrom/mstatusreg.adoc[] +include::images/wavedrom/mstatusreg.edn[] For RV32 only, `mstatush` is a 32-bit read/write register formatted as shown in <>. Bits 30:4 of `mstatush` generally contain the same fields found in bits 62:36 of `mstatus` for RV64. Fields SD, SXL, and UXL do not exist in `mstatush`. [[mstatushreg]] .Additional machine-mode status (`mstatush`) register for RV32. -include::images/wavedrom/mstatushreg.adoc[] +include::images/wavedrom/mstatushreg.edn[] [[privstack]] ===== Privilege and Global Interrupt-Enable Stack in `mstatus` register @@ -2100,7 +2100,7 @@ privileged than M. [[menvcfgreg]] .Machine environment configuration (`menvcfg`) register. -include::images/wavedrom/menvcfgreg.adoc[] +include::images/wavedrom/menvcfgreg.edn[] If bit FIOM (Fence of I/O implies Memory) is set to one in `menvcfg`, @@ -2227,7 +2227,7 @@ shown in <>, that controls security features. [[mseccfg]] .Machine security configuration (`mseccfg`) register. -include::images/wavedrom/mseccfg.adoc[] +include::images/wavedrom/mseccfg.edn[] The definitions of the SSEED and USEED fields will be furnished by the forthcoming entropy-source extension, Zkr. Their allocations within @@ -2348,7 +2348,7 @@ eventually, but not necessarily immediately. ==== Environment Call and Breakpoint -include::images/wavedrom/mm-env-call.adoc[] +include::images/wavedrom/mm-env-call.edn[] The ECALL instruction is used to make a request to the supporting execution environment. When executed in U-mode, S-mode, or M-mode, it diff --git a/src/rv32.adoc b/src/rv32.adoc index 2fac938d0..ebb128da4 100644 --- a/src/rv32.adoc +++ b/src/rv32.adoc @@ -174,7 +174,7 @@ bits in the instruction and have been allocated to reduce hardware complexity. In particular, the sign bit for all immediates is always in bit 31 of the instruction to speed sign-extension circuitry. -include::images/wavedrom/instruction_formats.adoc[] +include::images/wavedrom/instruction-formats.edn[] [[base_instr,Base instruction formats]] RISC-V base instruction formats. Each immediate subfield is labeled with the bit position (imm[x]) in the immediate value being produced, rather than the bit position within the instruction's immediate field as is usually done. @@ -201,7 +201,7 @@ to keep the ISA as simple as possible. There are a further two variants of the instruction formats (B/J) based on the handling of immediates, as shown in <>. -include::images/wavedrom/immediate_variants.adoc[] +include::images/wavedrom/immediate-variants.edn[] [[baseinstformatsimm,Base instruction formats immediate variants.]] //.RISC-V base instruction formats showing immediate variants. @@ -224,7 +224,7 @@ each of the base instruction formats, and is labeled to show which instruction bit (inst[_y_]) produces each bit of the immediate value. [[immtypes, Immediate types]] .Types of immediate produced by RISC-V instructions. -include::images/wavedrom/immediate.adoc[] +include::images/wavedrom/immediate.edn[] The fields are labeled with the instruction bits used to construct their value. Sign extensions always uses inst[31]. @@ -291,7 +291,7 @@ comparing the results of ADD and ADDW on the operands. ==== Integer Register-Immediate Instructions -include::images/wavedrom/integer_computational.adoc[] +include::images/wavedrom/integer-computational.edn[] //.Integer Computational Instructions ADDI adds the sign-extended 12-bit immediate to register _rs1_. @@ -312,7 +312,7 @@ XOR on register _rs1_ and the sign-extended 12-bit immediate and place the result in _rd_. Note, XORI _rd, rs1, -1_ performs a bitwise logical inversion of register _rs1_ (assembler pseudoinstruction NOT _rd, rs_). -include::images/wavedrom/int-comp-slli-srli-srai.adoc[] +include::images/wavedrom/int-comp-slli-srli-srai.edn[] [[int-comp-slli-srli-srai]] //.Integer register-immediate, SLLI, SRLI, SRAI @@ -324,7 +324,7 @@ shifted into the lower bits); SRLI is a logical right shift (zeros are shifted into the upper bits); and SRAI is an arithmetic right shift (the original sign bit is copied into the vacated upper bits). -include::images/wavedrom/int-comp-lui-aiupc.adoc[] +include::images/wavedrom/int-comp-lui-aiupc.edn[] [[int-comp-lui-aiupc]] //.Integer register-immediate, U-immediate @@ -364,7 +364,7 @@ the _rs1_ and _rs2_ registers as source operands and write the result into register _rd_. The _funct7_ and _funct3_ fields select the type of operation. -include::images/wavedrom/int_reg-reg.adoc[] +include::images/wavedrom/int-reg-reg.edn[] [[int-reg-reg]] //.Integer register-register @@ -383,7 +383,7 @@ the lower 5 bits of register _rs2_. ==== NOP Instruction -include::images/wavedrom/nop.adoc[] +include::images/wavedrom/nop.edn[] [[nop]] //.NOP instructions @@ -692,7 +692,7 @@ significance. Loads similarly transfer the contents of the greater memory byte addresses to the less-significant register bytes. ==== -include::images/wavedrom/load_store.adoc[] +include::images/wavedrom/load-store.edn[] [[load-store,load and store]] //.Load and store instructions @@ -781,7 +781,7 @@ are aligned. [[fence]] === Memory Ordering Instructions -include::images/wavedrom/mem_order.adoc[] +include::images/wavedrom/mem-order.edn[] [[mem-order]] //.Memory ordering instructions @@ -890,7 +890,7 @@ implementations might execute more of each system instruction in hardware. ==== -include::images/wavedrom/env_call-breakpoint.adoc[] +include::images/wavedrom/env-call-breakpoint.env[] [[env-call]] //.Environment call and breakpoint instructions diff --git a/src/rv64.adoc b/src/rv64.adoc index 531158a2a..e8a9ff653 100644 --- a/src/rv64.adoc +++ b/src/rv64.adoc @@ -136,7 +136,7 @@ results to 64 bits. The shift amount is given by _rs2[4:0]_. RV64I extends the address space to 64 bits. The execution environment will define what portions of the address space are legal to access. -include::images/wavedrom/load_store.adoc[] +include::images/wavedrom/load-store.edn[] [[load_store]] //.Load and store instructions diff --git a/src/zfh.adoc b/src/zfh.adoc index ab30e3d5d..1407d50d2 100644 --- a/src/zfh.adoc +++ b/src/zfh.adoc @@ -75,7 +75,7 @@ FCVT.WU.H, FCVT.LU.H, FCVT.H.WU, and FCVT.H.LU variants convert to or from unsigned integer values. FCVT.L[U].H and FCVT.H.L[U] are RV64-only instructions. -include::images/wavedrom/half-prec-conv-and-mv.adoc[] +include::images/wavedrom/half-prec-conv-and-mv.edn[] [[half-prec-conv-and-mv]] New floating-point-to-floating-point conversion instructions are added. @@ -90,14 +90,14 @@ is present, FCVT.Q.H or FCVT.H.Q converts a half-precision floating-point number to a quad-precision floating-point number, or vice-versa, respectively. -include::images/wavedrom/half-prec-flpt-to-flpt-conv.adoc[] +include::images/wavedrom/half-prec-flpt-to-flpt-conv.edn[] [[half-prec-flpt-to-flpt-conv]] Floating-point to floating-point sign-injection instructions, FSGNJ.H, FSGNJN.H, and FSGNJX.H are defined analogously to the single-precision sign-injection instruction. -include::images/wavedrom/flt-to-flt-sgn-inj-instr.adoc[] +include::images/wavedrom/flt-to-flt-sgn-inj-instr.edn[] [[flt-to-flt-sgn-inj-instr]] Instructions are provided to move bit patterns between the @@ -113,7 +113,7 @@ floating-point register _rd_, NaN-boxing the result. FMV.X.H and FMV.H.X do not modify the bits being transferred; in particular, the payloads of non-canonical NaNs are preserved. -include::images/wavedrom/flt-pt-to-int-move.adoc[] +include::images/wavedrom/flt-pt-to-int-move.edn[] [[flt-pt-to-int-move]] === Half-Precision Floating-Point Compare Instructions @@ -122,7 +122,7 @@ The half-precision floating-point compare instructions are defined analogously to their single-precision counterparts, but operate on half-precision operands. -include::images/wavedrom/half-pr-flt-pt-compare.adoc[] +include::images/wavedrom/half-pr-flt-pt-compare.edn[] [[half-pr-flt-pt-compare]] === Half-Precision Floating-Point Classify Instruction @@ -131,7 +131,7 @@ The half-precision floating-point classify instruction, FCLASS.H, is defined analogously to its single-precision counterpart, but operates on half-precision operands. -include::images/wavedrom/half-pr-flt-pt-class.adoc[] +include::images/wavedrom/half-pr-flt-pt-class.edn[] [[half-pr-flt-class]] === "Zfhmin" Standard Extension for Minimal Half-Precision Floating-Point diff --git a/src/zimop.adoc b/src/zimop.adoc index 8b50f4451..307d9a1b9 100644 --- a/src/zimop.adoc +++ b/src/zimop.adoc @@ -32,7 +32,7 @@ Unless redefined by another extension, these instructions simply write 0 to `x[rd]`. Their encoding allows future extensions to define them to read `x[rs1]`, as well as write `x[rd]`. -include::images/wavedrom/mop-r.adoc[] +include::images/wavedrom/mop-r.edn[] [[mop-r]] The Zimop extension additionally defines 8 MOP instructions named @@ -41,7 +41,7 @@ Unless redefined by another extension, these instructions simply write 0 to `x[rd]`. Their encoding allows future extensions to define them to read `x[rs1]` and `x[rs2]`, as well as write `x[rd]`. -include::images/wavedrom/mop-rr.adoc[] +include::images/wavedrom/mop-rr.edn[] [[mop-rr]] NOTE: The recommended assembly syntax for MOP.R.__n__ is MOP.R.__n__ rd, rs1, From ffe4c9bdee1dd362a4f91a8390c48fbfb0746da0 Mon Sep 17 00:00:00 2001 From: Kersten Richter Date: Wed, 7 Aug 2024 16:45:35 -0500 Subject: [PATCH 3/3] Update src/rv32.adoc Signed-off-by: Kersten Richter --- src/rv32.adoc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/rv32.adoc b/src/rv32.adoc index ebb128da4..7de4ef03d 100644 --- a/src/rv32.adoc +++ b/src/rv32.adoc @@ -890,7 +890,7 @@ implementations might execute more of each system instruction in hardware. ==== -include::images/wavedrom/env-call-breakpoint.env[] +include::images/wavedrom/env-call-breakpoint.edn[] [[env-call]] //.Environment call and breakpoint instructions