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Instructions

The instructions in the Zalasr extension require that the address held in rs1 be naturally aligned to the size in bytes (2width) of the operand. If the address is not naturally aligned, an address-misaligned exception or an access-fault exception will be generated. The access-fault exception can be generated for a memory access that would otherwise be able to complete except for the misalignment, if the misaligned access should not be emulated.

The misaligned atomicity granule PMA, defined in Volume II of this manual, optionally relaxes this alignment requirement. If all accessed bytes lie within the same misaligned atomicity granule, the instruction will not raise an exception for reasons of address alignment, and the instruction will give rise to only one memory operation for the purposes of RVWMO—i.e., it will execute atomically.

Load Acquire

Synopsis

The load-acquire instruction, atomically and subject to the ordering annotations specified in the instruction, loads a 2width-byte value from the address in rs1 into the register rd.

Mnemonic

lb.{aq,aqrl} rd, (rs1)

lh.{aq,aqrl} rd, (rs1)

lw.{aq,aqrl} rd, (rs1)

ld.{aq,aqrl} rd, (rs1)

Encoding
{reg: [
  {bits: 7,  name: 'opcode',    attr: ['7', 'AMO'], type: 8},
  {bits: 5,  name: 'rd',        attr: ['5', 'dest'], type: 2},
  {bits: 3,  name: 'funct3',    attr: ['3', 'width'], type: 8},
  {bits: 5,  name: 'rs1',       attr: ['5', 'addr'], type: 4},
  {bits: 5,  name: 'rs2',       attr: ['5', '0'], type: 4},
  {bits: 1,  name: 'rl',        attr: ['1', 'ring'], type: 8},
  {bits: 1,  name: 'aq',        attr: ['1', 'orde', '1'], type: 8},
  {bits: 5,  name: 'funct5',    attr: ['5', 'Load Acquire', '00110'], type: 8},
]}
Description

This instruction loads 2width bytes of memory from rs1 atomically. If the size (2width+3) is less than XLEN, it is sign-extended to fill the destination register. This load must have the ordering annotation aq and may have ordering annotation rl encoded in the instruction. The instruction always has an "acquire-RCsc" annotation, and if the bit rl is set the instruction has a "release-RCsc" annotation.

The versions without the aq bit set are RESERVED. LD.{AQ, AQRL} is RV64-only.

Note

The aq bit is mandatory because the two encodings that would be produced are not seen as useful at this time. The version with neither the aq nor the rl bit set would correspond to a load with no ordering annotations that was guaranteed to be performed atomically. This can be achieved with ordinary load instuctions by suitably aligning pointers. The version with only the rl bit would correspond to load-release. Load-release has theoretical applications in seqlocks, but is not supported in language-level memory models and so is not included.

Store Release

Synopsis

The store-release instruction, atomically and subject to the ordering annotations specified in the instruction, stores the 2width-byte value from the register rs2 to the address in rs1.

Mnemonic

sb.{rl,aqrl} rs2, (rs1)

sh.{rl,aqrl} rs2, (rs1)

sw.{rl,aqrl} rs2, (rs1)

sd.{rl,aqrl} rs2, (rs1)

Encoding
{reg: [
  {bits: 7,  name: 'opcode',    attr: ['7', 'AMO'], type: 8},
  {bits: 5,  name: 'rd',        attr: ['5', '0'], type: 2},
  {bits: 3,  name: 'funct3',    attr: ['3', 'width'], type: 8},
  {bits: 5,  name: 'rs1',       attr: ['5', 'addr'], type: 4},
  {bits: 5,  name: 'rs2',       attr: ['5', 'src'], type: 4},
  {bits: 1,  name: 'rl',        attr: ['1', 'ring', '1'], type: 8},
  {bits: 1,  name: 'aq',        attr: ['1', 'orde'], type: 8},
  {bits: 5,  name: 'funct5',    attr: ['5', 'Store Release', '00111'], type: 8},
]}
Description

This instruction stores 2width bytes of memory from rs1 atomically. This store must have ordering annotation rl and may have ordering annotation aq encoded in the instruction. The instruction always has an "release-RCsc" annotation, and if the bit aq is set the instruction has a "acquire-RCsc" annotation.

The versions without the rl bit set are RESERVED. SD.{RL, AQRL} is RV64-only.

Note

The rl bit is mandatory because the two encodings that would be produced are not seen as useful at this time. The version with neither the aq nor the rl bit set would correspond to a store with no ordering annotations that was guaranteed to be performed atomically. This can be achieved with ordinary store instuctions by suitably aligned pointers. The version with only the aq bit would correspond to store-acquire. Store-acquire has theoretical applications in seqlocks, but is not supported in language-level memory models and so is not included.