diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index 25ac679d6a62..16ee9d74b994 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1598,7 +1598,8 @@ riscv_parse_prefixed_ext (riscv_parse_subset_t *rps, static const char * const riscv_std_z_ext_strtab[] = { - "zicsr", "zifencei", "zihintpause", "zba", "zbb", "zbc", NULL + "zicsr", "zifencei", "zihintpause", "zba", "zbb", "zbc", + "zbpbo", "zpn", "zpsf",NULL }; static const char * const riscv_std_s_ext_strtab[] = @@ -1770,6 +1771,18 @@ riscv_parse_add_implicit_subsets (riscv_parse_subset_t *rps) RISCV_UNKNOWN_VERSION, RISCV_UNKNOWN_VERSION, TRUE); } + if (riscv_lookup_subset (rps->subset_list, "p", &subset)) + { + riscv_parse_add_subset (rps, "zpn", + RISCV_UNKNOWN_VERSION, + RISCV_UNKNOWN_VERSION, TRUE); + riscv_parse_add_subset (rps, "zpsf", + RISCV_UNKNOWN_VERSION, + RISCV_UNKNOWN_VERSION, TRUE); + riscv_parse_add_subset (rps, "zbpbo", + RISCV_UNKNOWN_VERSION, + RISCV_UNKNOWN_VERSION, TRUE); + } } /* Function for parsing ISA string. diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c index 63c35b33fc59..31777883223c 100644 --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -64,6 +64,7 @@ enum riscv_csr_class CSR_CLASS_I, CSR_CLASS_I_32, /* rv32 only */ CSR_CLASS_F, /* f-ext only */ + CSR_CLASS_P, /* rvp only */ CSR_CLASS_DEBUG /* debug CSR */ }; @@ -131,6 +132,8 @@ static const struct riscv_ext_version ext_version_table[] = {"c", ISA_SPEC_CLASS_20190608, 2, 0}, {"c", ISA_SPEC_CLASS_2P2, 2, 0}, + {"p", ISA_SPEC_CLASS_DRAFT, 2, 0}, + {"zicsr", ISA_SPEC_CLASS_20191213, 2, 0}, {"zicsr", ISA_SPEC_CLASS_20190608, 2, 0}, @@ -142,7 +145,10 @@ static const struct riscv_ext_version ext_version_table[] = {"zbb", ISA_SPEC_CLASS_DRAFT, 0, 93}, {"zba", ISA_SPEC_CLASS_DRAFT, 0, 93}, {"zbc", ISA_SPEC_CLASS_DRAFT, 0, 93}, - + + {"zpn", ISA_SPEC_CLASS_DRAFT, 2, 0}, + {"zpsf", ISA_SPEC_CLASS_DRAFT, 2, 0}, + {"zbpbo", ISA_SPEC_CLASS_DRAFT, 2, 0}, /* Terminate the list. */ {NULL, 0, 0, 0} }; @@ -340,6 +346,13 @@ riscv_multi_subset_supports (enum riscv_insn_class insn_class) return riscv_subset_supports ("zba"); case INSN_CLASS_ZBC: return riscv_subset_supports ("zbc"); + + case INSN_CLASS_ZPN: + return riscv_subset_supports ("zpn"); + case INSN_CLASS_ZPSF: + return riscv_subset_supports ("zpsf"); + case INSN_CLASS_ZBPBO: + return riscv_subset_supports ("zbpbo"); default: as_fatal ("internal: unreachable"); @@ -856,6 +869,10 @@ riscv_csr_address (const char *csr_name, result = riscv_subset_supports ("f"); need_check_version = FALSE; break; + case CSR_CLASS_P: + result = riscv_subset_supports ("zpn"); + need_check_version = FALSE; + break; case CSR_CLASS_DEBUG: need_check_version = FALSE; break; @@ -973,6 +990,29 @@ arg_lookup (char **s, const char *const *array, size_t size, unsigned *regnop) return FALSE; } +#define RVP_MAX_KEYWORD_LEN 32 + +static bfd_boolean +parse_rvp_field (const char **str, char name[RVP_MAX_KEYWORD_LEN]) +{ + char *p = name; + const char *str_t; + + str_t = *str; + str_t--; + while (ISALNUM (*str_t) || *str_t == '.' || *str_t == '_') + *p++ = *str_t++; + *p = '\0'; + + if (strncmp (name, "nds_", 4) == 0) + { + *str = str_t; + return TRUE; + } + else + return FALSE; +} + /* For consistency checking, verify that all bits are specified either by the match/mask part of the instruction definition, or by the operand list. The `length` could be 0, 4 or 8, 0 for auto detection. */ @@ -1071,6 +1111,7 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length) case 'Z': /* RS1, CSR number. */ case 'S': /* RS1, floating point. */ case 's': USE_BITS (OP_MASK_RS1, OP_SH_RS1); break; + case 'g': /* RS1 and RS2 are the same. */ case 'U': /* RS1 and RS2 are the same, floating point. */ USE_BITS (OP_MASK_RS1, OP_SH_RS1); /* Fall through. */ @@ -1083,6 +1124,7 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length) case 'P': USE_BITS (OP_MASK_PRED, OP_SH_PRED); break; case 'Q': USE_BITS (OP_MASK_SUCC, OP_SH_SUCC); break; case 'o': /* ITYPE immediate, load displacement. */ + case 'l': /* IMM6L */ case 'j': used_bits |= ENCODE_ITYPE_IMM (-1U); break; case 'a': used_bits |= ENCODE_JTYPE_IMM (-1U); break; case 'p': used_bits |= ENCODE_BTYPE_IMM (-1U); break; @@ -1118,6 +1160,36 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length) return FALSE; } break; + case 'n': + { + char field_name[RVP_MAX_KEYWORD_LEN]; + if (parse_rvp_field (&p, field_name)) + { + if (strcmp (field_name, "nds_rdp") == 0) + USE_BITS (OP_MASK_RD, OP_SH_RD); + else if (strcmp (field_name, "nds_rsp") == 0) + USE_BITS (OP_MASK_RD, OP_SH_RS1); + else if (strcmp (field_name, "nds_rtp") == 0) + USE_BITS (OP_MASK_RD, OP_SH_RS2); + else if (strcmp (field_name, "nds_i3u") == 0) + used_bits |= ENCODE_PTYPE_IMM3U (-1U); + else if (strcmp (field_name, "nds_i4u") == 0) + used_bits |= ENCODE_PTYPE_IMM4U (-1U); + else if (strcmp (field_name, "nds_i5u") == 0) + used_bits |= ENCODE_PTYPE_IMM5U (-1U); + else if (strcmp (field_name, "nds_i6u") == 0) + used_bits |= ENCODE_PTYPE_IMM6U (-1U); + else + as_bad (_("internal: bad RISC-V opcode " + "(unknown operand type `%s'): %s %s"), + field_name, opc->name, opc->args); + } + else + as_bad (_("internal: bad RISC-V opcode " + "(unknown operand type `%c'): %s %s"), + c, opc->name, opc->args); + } + break; default: as_bad (_("internal: bad RISC-V opcode " "(unknown operand type `%c'): %s %s"), @@ -2402,6 +2474,17 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr, } continue; + case 'l': + my_getExpression (imm_expr, s); + if (imm_expr->X_op != O_constant + || imm_expr->X_add_number >= xlen + || imm_expr->X_add_number < 0) + break; + ip->insn_opcode |= ENCODE_ITYPE_IMM6L (imm_expr->X_add_number); + s = expr_end; + imm_expr->X_op = O_absent; + continue; + case 'm': /* Rounding mode. */ if (arg_lookup (&s, riscv_rm, ARRAY_SIZE (riscv_rm), ®no)) { @@ -2410,6 +2493,81 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr, } break; + case 'n': + { + char field_name[RVP_MAX_KEYWORD_LEN]; + args++; + if (parse_rvp_field (&args, field_name)) + { + if (strcmp (field_name, "nds_rdp") == 0 + && reg_lookup (&s, RCLASS_GPR, ®no)) + { + if (xlen == 32 && (regno % 2) != 0) + { + as_bad (_("the number of Rd must be even " + "(limitation of register pair)")); + break; + } + INSERT_OPERAND (RD, *ip, regno); + args--; + continue; + } + else if (strcmp (field_name, "nds_rsp") == 0 + && reg_lookup (&s, RCLASS_GPR, ®no)) + { + if (xlen == 32 && (regno % 2) != 0) + { + as_bad (_("the number of Rs1 must be even " + "(limitation of register pair)")); + break; + } + INSERT_OPERAND (RS1, *ip, regno); + args--; + continue; + } + else if (strcmp (field_name, "nds_rtp") == 0 + && reg_lookup (&s, RCLASS_GPR, ®no)) + { + if (xlen == 32 && (regno % 2) != 0) + { + as_bad (_("the number of Rs2 must be even " + "(limitation of register pair)")); + break; + } + INSERT_OPERAND (RS2, *ip, regno); + args--; + continue; + } + + my_getExpression (imm_expr, s); + if (imm_expr->X_op != O_constant + || imm_expr->X_add_number >= xlen + || imm_expr->X_add_number < 0) + break; + + if (strcmp (field_name, "nds_i3u") == 0 + && VALID_PTYPE_IMM3U (imm_expr->X_add_number)) + ip->insn_opcode |= ENCODE_PTYPE_IMM3U (imm_expr->X_add_number); + else if (strcmp (field_name, "nds_i4u") == 0 + && VALID_PTYPE_IMM4U (imm_expr->X_add_number)) + ip->insn_opcode |= ENCODE_PTYPE_IMM4U (imm_expr->X_add_number); + else if (strcmp (field_name, "nds_i5u") == 0 + && VALID_PTYPE_IMM5U (imm_expr->X_add_number)) + ip->insn_opcode |= ENCODE_PTYPE_IMM5U (imm_expr->X_add_number); + else if (strcmp (field_name, "nds_i6u") == 0 + && VALID_PTYPE_IMM6U (imm_expr->X_add_number)) + ip->insn_opcode |= ENCODE_PTYPE_IMM6U (imm_expr->X_add_number); + else + break; + + s = expr_end; + imm_expr->X_op = O_absent; + args--; + continue; + } + break; + } + case 'P': case 'Q': /* Fence predecessor/successor. */ if (arg_lookup (&s, riscv_pred_succ, ARRAY_SIZE (riscv_pred_succ), @@ -2425,6 +2583,7 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr, case 'd': /* Destination register. */ case 's': /* Source register. */ + case 'g': /* RS1 and RS2. */ case 't': /* Target register. */ case 'r': /* RS3 */ if (reg_lookup (&s, RCLASS_GPR, ®no)) @@ -2443,6 +2602,9 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr, case 'd': INSERT_OPERAND (RD, *ip, regno); break; + case 'g': + INSERT_OPERAND (RS1, *ip, regno); + /* Fall through. */ case 't': INSERT_OPERAND (RS2, *ip, regno); break; diff --git a/gas/testsuite/gas/riscv/insn-dsp-zbpbo.d b/gas/testsuite/gas/riscv/insn-dsp-zbpbo.d new file mode 100644 index 000000000000..3969bafdc694 --- /dev/null +++ b/gas/testsuite/gas/riscv/insn-dsp-zbpbo.d @@ -0,0 +1,24 @@ +#as: -march=rv32gc_zbpbo_zpn_zpsf +#source: insn-dsp-zbpbo.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : +[ ]+.*:[ ]+.*[ ]+clz[ ]+a1,a2 +[ ]+.*:[ ]+.*[ ]+clz[ ]+a1,a2 +[ ]+.*:[ ]+.*[ ]+cmix[ ]+a1,a2,a3,a4 +[ ]+.*:[ ]+.*[ ]+fsr[ ]+a1,a2,a3,a4 +[ ]+.*:[ ]+.*[ ]+fsri[ ]+a1,a2,a3,0x5 +[ ]+.*:[ ]+.*[ ]+max[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+min[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+pack[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+packu[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+pack[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+packu[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+rev[ ]+a1,a2 +[ ]+.*:[ ]+.*[ ]+rev8.h[ ]+a1,a2 +[ ]+.*:[ ]+.*[ ]+rev8.h[ ]+a1,a2 diff --git a/gas/testsuite/gas/riscv/insn-dsp-zbpbo.s b/gas/testsuite/gas/riscv/insn-dsp-zbpbo.s new file mode 100644 index 000000000000..f44175c345e9 --- /dev/null +++ b/gas/testsuite/gas/riscv/insn-dsp-zbpbo.s @@ -0,0 +1,15 @@ +dsp: + clz a1,a2 + clz32 a1,a2 + cmix a1,a2,a3,a4 + fsr a1,a2,a3,a4 + fsri a1,a2,a3,5 + max a1,a2,a3 + min a1,a2,a3 + pack a1,a2,a3 + packu a1,a2,a3 + pktt16 a1,a2,a3 + pkbb16 a1,a2,a3 + rev a1,a2 + rev8.h a1,a2 + swap8 a1,a2 diff --git a/gas/testsuite/gas/riscv/insn-dsp.d b/gas/testsuite/gas/riscv/insn-dsp.d new file mode 100644 index 000000000000..de449e888429 --- /dev/null +++ b/gas/testsuite/gas/riscv/insn-dsp.d @@ -0,0 +1,255 @@ +#as: -march=rv32gc_zpn_zpsf +#source: insn-dsp.s +#objdump: -d -M no-aliases + + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : +[ ]+.*:[ ]+.*[ ]+add16[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+radd16[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+uradd16[ ]+a1,a2,a3 +[ ]+.*:[ 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]+uclip16[ ]+a1,a2,4 +[ ]+.*:[ ]+.*[ ]+khm16[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+khmx16[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+kabs16[ ]+a1,a2 +[ ]+.*:[ ]+.*[ ]+clrs16[ ]+a1,a2 +[ ]+.*:[ ]+.*[ ]+clz16[ ]+a1,a2 +[ ]+.*:[ ]+.*[ ]+pkbt16[ ]+a1,a2,a2 +[ ]+.*:[ ]+.*[ ]+smin8[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+umin8[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+smax8[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+umax8[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+khm8[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+khmx8[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+kabs8[ ]+a1,a2 +[ ]+.*:[ ]+.*[ ]+sclip8[ ]+a1,a2,3 +[ ]+.*:[ ]+.*[ ]+uclip8[ ]+a1,a2,3 +[ ]+.*:[ ]+.*[ ]+clrs8[ ]+a1,a2 +[ ]+.*:[ ]+.*[ ]+clz8[ ]+a1,a2 +[ ]+.*:[ ]+.*[ ]+swap8[ ]+a1,a2 +[ ]+.*:[ ]+.*[ ]+sunpkd810[ ]+a1,a2 +[ ]+.*:[ ]+.*[ ]+sunpkd820[ ]+a1,a2 +[ ]+.*:[ ]+.*[ ]+sunpkd830[ ]+a1,a2 +[ ]+.*:[ ]+.*[ ]+sunpkd831[ ]+a1,a2 +[ ]+.*:[ ]+.*[ ]+sunpkd832[ ]+a1,a2 +[ ]+.*:[ ]+.*[ ]+zunpkd810[ ]+a1,a2 +[ ]+.*:[ ]+.*[ ]+zunpkd820[ ]+a1,a2 +[ ]+.*:[ ]+.*[ ]+zunpkd830[ ]+a1,a2 +[ ]+.*:[ ]+.*[ ]+zunpkd831[ ]+a1,a2 +[ ]+.*:[ ]+.*[ ]+zunpkd832[ ]+a1,a2 +[ ]+.*:[ ]+.*[ ]+pkbb16[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+pkbt16[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+pktb16[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+pktt16[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+smmul[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+smmul.u[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+kmmac[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+kmmac.u[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+kmmsb[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+kmmsb.u[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+kwmmul[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+kwmmul.u[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+smmwb[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+smmwb.u[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+smmwt[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+smmwt.u[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+kmmawb[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+kmmawb.u[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+kmmawt[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+kmmawt.u[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+kmmwb2[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+kmmwb2.u[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+kmmwt2[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+kmmwt2.u[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+kmmawb2[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+kmmawb2.u[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+kmmawt2[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+kmmawt2.u[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+smbb16[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+smbt16[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+smtt16[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+kmda[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+kmxda[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+smds[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+smdrs[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+smxds[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+kmabb[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+kmabt[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+kmatt[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+kmada[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+kmaxda[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+kmads[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+kmadrs[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+kmaxds[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+kmsda[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+kmsxda[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+smal[ ]+a2,a4,a6 +[ ]+.*:[ ]+.*[ ]+sclip32[ ]+a1,a2,5 +[ ]+.*:[ ]+.*[ ]+uclip32[ ]+a1,a2,5 +[ ]+.*:[ ]+.*[ ]+clrs32[ ]+a1,a2 +[ ]+.*:[ ]+.*[ ]+clz32[ ]+a1,a2 +[ ]+.*:[ ]+.*[ ]+pbsad[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+pbsada[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+smaqa[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+umaqa[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+smaqa.su[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+add64[ ]+a2,a4,a6 +[ ]+.*:[ ]+.*[ ]+radd64[ ]+a2,a4,a6 +[ ]+.*:[ ]+.*[ ]+uradd64[ ]+a2,a4,a6 +[ ]+.*:[ ]+.*[ ]+kadd64[ ]+a2,a4,a6 +[ ]+.*:[ ]+.*[ ]+ukadd64[ ]+a2,a4,a6 +[ ]+.*:[ ]+.*[ ]+sub64[ ]+a2,a4,a6 +[ ]+.*:[ ]+.*[ ]+rsub64[ ]+a2,a4,a6 +[ ]+.*:[ ]+.*[ ]+ursub64[ ]+a2,a4,a6 +[ ]+.*:[ ]+.*[ ]+ksub64[ ]+a2,a4,a6 +[ ]+.*:[ ]+.*[ ]+uksub64[ ]+a2,a4,a6 +[ ]+.*:[ ]+.*[ ]+smar64[ ]+a2,a4,a6 +[ ]+.*:[ ]+.*[ ]+smsr64[ ]+a2,a4,a6 +[ ]+.*:[ ]+.*[ ]+umar64[ ]+a2,a4,a6 +[ ]+.*:[ ]+.*[ ]+umsr64[ ]+a2,a4,a6 +[ ]+.*:[ ]+.*[ ]+kmar64[ ]+a2,a4,a6 +[ ]+.*:[ ]+.*[ ]+kmsr64[ ]+a2,a4,a6 +[ ]+.*:[ ]+.*[ ]+ukmar64[ ]+a2,a4,a6 +[ ]+.*:[ ]+.*[ ]+ukmsr64[ ]+a2,a4,a6 +[ ]+.*:[ ]+.*[ ]+smalbb[ ]+a2,a4,a6 +[ ]+.*:[ ]+.*[ ]+smalbt[ ]+a2,a4,a6 +[ ]+.*:[ ]+.*[ ]+smaltt[ ]+a2,a4,a6 +[ ]+.*:[ ]+.*[ ]+smalda[ ]+a2,a4,a6 +[ ]+.*:[ ]+.*[ ]+smalxda[ ]+a2,a4,a6 +[ ]+.*:[ ]+.*[ ]+smalds[ ]+a2,a4,a6 +[ ]+.*:[ ]+.*[ ]+smaldrs[ ]+a2,a4,a6 +[ ]+.*:[ ]+.*[ ]+smalxds[ ]+a2,a4,a6 +[ ]+.*:[ ]+.*[ ]+smslda[ ]+a2,a4,a6 +[ ]+.*:[ ]+.*[ ]+smslxda[ ]+a2,a4,a6 +[ ]+.*:[ ]+.*[ ]+kaddh[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+ksubh[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+khmbb[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+khmbt[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+khmtt[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+ukaddh[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+uksubh[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+kaddw[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+ukaddw[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+ksubw[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+uksubw[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+kdmbb[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+kdmbt[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+kdmtt[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+kslraw[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+kslraw.u[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+ksllw[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+kslliw[ ]+a1,a2,5 +[ ]+.*:[ ]+.*[ ]+kdmabb[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+kdmabt[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+kdmatt[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+kabsw[ ]+a1,a2 +[ ]+.*:[ ]+.*[ ]+raddw[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+uraddw[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+rsubw[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+ursubw[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+csrrs[ ]+a1,vxsat,zero +[ ]+.*:[ ]+.*[ ]+csrrci[ ]+zero,vxsat,1 +[ ]+.*:[ ]+.*[ ]+ave[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+sra.u[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+srai.u[ ]+a1,a2,5 +[ ]+.*:[ ]+.*[ ]+bitrev[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+bitrevi[ ]+a1,a2,5 +[ ]+.*:[ ]+.*[ ]+wext[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+wexti[ ]+a1,a2,5 +[ ]+.*:[ ]+.*[ ]+insb[ ]+a1,a2,2 +[ ]+.*:[ ]+.*[ ]+maddr32[ ]+a2,a4,a6 +[ ]+.*:[ ]+.*[ ]+msubr32[ ]+a2,a4,a6 +[ ]+.*:[ ]+.*[ ]+mulr64[ ]+a2,a4,a6 +[ ]+.*:[ ]+.*[ ]+mulsr64[ ]+a2,a4,a6 +[ ]+.*:[ ]+.*[ ]+smul8[ ]+a2,a4,a6 +[ ]+.*:[ ]+.*[ ]+smulx8[ ]+a2,a4,a6 +[ ]+.*:[ ]+.*[ ]+smul16[ ]+a2,a4,a6 +[ ]+.*:[ ]+.*[ ]+smulx16[ ]+a2,a4,a6 +[ ]+.*:[ ]+.*[ ]+umul8[ ]+a2,a4,a6 +[ ]+.*:[ ]+.*[ ]+umulx8[ ]+a2,a4,a6 +[ ]+.*:[ ]+.*[ ]+umul16[ ]+a2,a4,a6 +[ ]+.*:[ ]+.*[ ]+umulx16[ ]+a2,a4,a6 diff --git a/gas/testsuite/gas/riscv/insn-dsp.s b/gas/testsuite/gas/riscv/insn-dsp.s new file mode 100644 index 000000000000..ff60490f90c8 --- /dev/null +++ b/gas/testsuite/gas/riscv/insn-dsp.s @@ -0,0 +1,294 @@ +dsp: + # Table 1. SIMD 16-bit Add/Subtract Instructions (30) + add16 a1, a2, a3 + radd16 a1, a2, a3 + uradd16 a1, a2, a3 + kadd16 a1, a2, a3 + ukadd16 a1, a2, a3 + sub16 a1, a2, a3 + rsub16 a1, a2, a3 + ursub16 a1, a2, a3 + ksub16 a1, a2, a3 + uksub16 a1, a2, a3 + cras16 a1, a2, a3 + rcras16 a1, a2, a3 + urcras16 a1, a2, a3 + kcras16 a1, a2, a3 + ukcras16 a1, a2, a3 + crsa16 a1, a2, a3 + rcrsa16 a1, a2, a3 + urcrsa16 a1, a2, a3 + kcrsa16 a1, a2, a3 + ukcrsa16 a1, a2, a3 + stas16 a1, a2, a3 + rstas16 a1, a2, a3 + urstas16 a1, a2, a3 + kstas16 a1, a2, a3 + ukstas16 a1, a2, a3 + stsa16 a1, a2, a3 + rstsa16 a1, a2, a3 + urstsa16 a1, a2, a3 + kstsa16 a1, a2, a3 + ukstsa16 a1, a2, a3 + + # Table 2. SIMD 8-bit Add/Subtract Instructions (10) + add8 a1, a2, a3 + radd8 a1, a2, a3 + uradd8 a1, a2, a3 + kadd8 a1, a2, a3 + ukadd8 a1, a2, a3 + sub8 a1, a2, a3 + rsub8 a1, a2, a3 + ursub8 a1, a2, a3 + ksub8 a1, a2, a3 + uksub8 a1, a2, a3 + + # Table 3. SIMD 16-bit Shift Instructions (14) + sra16 a1, a2, a3 + srai16 a1, a2, 4 + sra16.u a1, a2, a3 + srai16.u a1, a2, 4 + srl16 a1, a2, a3 + srli16 a1, a2, 4 + srl16.u a1, a2, a3 + srli16.u a1, a2, 4 + sll16 a1, a2, a3 + slli16 a1, a2, 4 + ksll16 a1, a2, a3 + kslli16 a1, a2, 4 + kslra16 a1, a2, a3 + kslra16.u a1, a2, a3 + + # Table 4. SIMD 8-bit Shift Instructions (14) + sra8 a1, a2, a3 + srai8 a1, a2, 3 + sra8.u a1, a2, a3 + srai8.u a1, a2, 4 + srl8 a1, a2, a3 + srli8 a1, a2, 3 + srl8.u a1, a2, a3 + srli8.u a1, a2, 4 + sll8 a1, a2, a3 + slli8 a1, a2, 3 + ksll8 a1, a2, a3 + kslli8 a1, a2, 3 + kslra8 a1, a2, a3 + kslra8.u a1, a2, a3 + + # Table 5. SIMD 16-bit Compare Instructions (5) + cmpeq16 a1, a2, a3 + scmplt16 a1, a2, a3 + scmple16 a1, a2, a3 + ucmplt16 a1, a2, a3 + ucmple16 a1, a2, a3 + + # Table 6. SIMD 8-bit Compare Instructions (5) + cmpeq8 a1, a2, a3 + scmplt8 a1, a2, a3 + scmple8 a1, a2, a3 + ucmplt8 a1, a2, a3 + ucmple8 a1, a2, a3 + + # Table 7. SIMD 16-bit Miscellaneous Instructions (12) + smin16 a1, a2, a3 + umin16 a1, a2, a3 + smax16 a1, a2, a3 + umax16 a1, a2, a3 + sclip16 a1, a2, 4 + uclip16 a1, a2, 4 + khm16 a1, a2, a3 + khmx16 a1, a2, a3 + kabs16 a1, a2 + clrs16 a1, a2 + clz16 a1, a2 + swap16 a1, a2 + + # Table 8. SIMD 8-bit Miscellaneous Instructions (12) + smin8 a1, a2, a3 + umin8 a1, a2, a3 + smax8 a1, a2, a3 + umax8 a1, a2, a3 + khm8 a1, a2, a3 + khmx8 a1, a2, a3 + kabs8 a1, a2 + sclip8 a1, a2, 3 + uclip8 a1, a2, 3 + clrs8 a1, a2 + clz8 a1, a2 + swap8 a1, a2 + + # Table 9. 8-bit Unpacking Instructions (10) + sunpkd810 a1, a2 + sunpkd820 a1, a2 + sunpkd830 a1, a2 + sunpkd831 a1, a2 + sunpkd832 a1, a2 + zunpkd810 a1, a2 + zunpkd820 a1, a2 + zunpkd830 a1, a2 + zunpkd831 a1, a2 + zunpkd832 a1, a2 + + # Table 10. 16-bit Packing Instructions (4) + pkbb16 a1, a2, a3 + pkbt16 a1, a2, a3 + pktb16 a1, a2, a3 + pktt16 a1, a2, a3 + + # Table 11. Signed MSW 32x32 Multiply and Add Instructions (8) + smmul a1, a2, a3 + smmul.u a1, a2, a3 + kmmac a1, a2, a3 + kmmac.u a1, a2, a3 + kmmsb a1, a2, a3 + kmmsb.u a1, a2, a3 + kwmmul a1, a2, a3 + kwmmul.u a1, a2, a3 + + # Table 12. Signed MSW 32x16 Multiply and Add Instructions (16) + smmwb a1, a2, a3 + smmwb.u a1, a2, a3 + smmwt a1, a2, a3 + smmwt.u a1, a2, a3 + kmmawb a1, a2, a3 + kmmawb.u a1, a2, a3 + kmmawt a1, a2, a3 + kmmawt.u a1, a2, a3 + kmmwb2 a1, a2, a3 + kmmwb2.u a1, a2, a3 + kmmwt2 a1, a2, a3 + kmmwt2.u a1, a2, a3 + kmmawb2 a1, a2, a3 + kmmawb2.u a1, a2, a3 + kmmawt2 a1, a2, a3 + kmmawt2.u a1, a2, a3 + + # Table 13. Signed 16-bit Multiply 32-bit Add/Subtract Instructions (18) + smbb16 a1, a2, a3 + smbt16 a1, a2, a3 + smtt16 a1, a2, a3 + kmda a1, a2, a3 + kmxda a1, a2, a3 + smds a1, a2, a3 + smdrs a1, a2, a3 + smxds a1, a2, a3 + kmabb a1, a2, a3 + kmabt a1, a2, a3 + kmatt a1, a2, a3 + kmada a1, a2, a3 + kmaxda a1, a2, a3 + kmads a1, a2, a3 + kmadrs a1, a2, a3 + kmaxds a1, a2, a3 + kmsda a1, a2, a3 + kmsxda a1, a2, a3 + + # Table 14. Signed 16-bit Multiply 64-bit Add/Subtract Instructions (1) + smal a2, a4, a6 + + # Table 15. Partial-SIMD Miscellaneous Instructions (7) + sclip32 a1, a2, 5 + uclip32 a1, a2, 5 + clrs32 a1, a2 + clz32 a1, a2 + pbsad a1, a2, a3 + pbsada a1, a2, a3 + + # Table 16. 8-bit Multiply with 32-bit Add Instructions (3) + smaqa a1, a2, a3 + umaqa a1, a2, a3 + smaqa.su a1, a2, a3 + + # Table 17. 64-bit Add/Subtract Instructions (10) + add64 a2, a4, a6 + radd64 a2, a4, a6 + uradd64 a2, a4, a6 + kadd64 a2, a4, a6 + ukadd64 a2, a4, a6 + sub64 a2, a4, a6 + rsub64 a2, a4, a6 + ursub64 a2, a4, a6 + ksub64 a2, a4, a6 + uksub64 a2, a4, a6 + + # Table 18. 32-bit Multiply 64-bit Add/Subtract Instructions (8) + smar64 a2, a4, a6 + smsr64 a2, a4, a6 + umar64 a2, a4, a6 + umsr64 a2, a4, a6 + kmar64 a2, a4, a6 + kmsr64 a2, a4, a6 + ukmar64 a2, a4, a6 + ukmsr64 a2, a4, a6 + + # Table 19. Signed 16-bit Multiply 64-bit Add/Subtract Instructions (10) + smalbb a2, a4, a6 + smalbt a2, a4, a6 + smaltt a2, a4, a6 + smalda a2, a4, a6 + smalxda a2, a4, a6 + smalds a2, a4, a6 + smaldrs a2, a4, a6 + smalxds a2, a4, a6 + smslda a2, a4, a6 + smslxda a2, a4, a6 + + # Table 20. Non-SIMD Q15 saturation ALU Instructions (7) + kaddh a1, a2, a3 + ksubh a1, a2, a3 + khmbb a1, a2, a3 + khmbt a1, a2, a3 + khmtt a1, a2, a3 + ukaddh a1, a2, a3 + uksubh a1, a2, a3 + + # Table 21. Non-SIMD Q31 saturation ALU Instructions (15) + kaddw a1, a2, a3 + ukaddw a1, a2, a3 + ksubw a1, a2, a3 + uksubw a1, a2, a3 + kdmbb a1, a2, a3 + kdmbt a1, a2, a3 + kdmtt a1, a2, a3 + kslraw a1, a2, a3 + kslraw.u a1, a2, a3 + ksllw a1, a2, a3 + kslliw a1, a2, 5 + kdmabb a1, a2, a3 + kdmabt a1, a2, a3 + kdmatt a1, a2, a3 + kabsw a1, a2 + + # Table 22. 32-bit Add/Sub Instructions (4) + raddw a1, a2, a3 + uraddw a1, a2, a3 + rsubw a1, a2, a3 + ursubw a1, a2, a3 + + # Table 23. OV (Overflow) flag Set/Clear Instructions (2) + rdov a1 + clrov + + # Table 24. Non-SIMD Miscellaneous Instructions (9) + ave a1, a2, a3 + sra.u a1, a2, a3 + srai.u a1, a2, 5 + bitrev a1, a2, a3 + bitrevi a1, a2, 5 + wext a1, a2, a3 + wexti a1, a2, 5 + insb a1, a2, 2 + + # New Instructions in ZPSF + maddr32 a2, a4, a6 + msubr32 a2, a4, a6 + mulr64 a2, a4, a6 + mulsr64 a2, a4, a6 + smul8 a2, a4, a6 + smulx8 a2, a4, a6 + smul16 a2, a4, a6 + smulx16 a2, a4, a6 + umul8 a2, a4, a6 + umulx8 a2, a4, a6 + umul16 a2, a4, a6 + umulx16 a2, a4, a6 diff --git a/gas/testsuite/gas/riscv/insn-dsp64-zbpbo.d b/gas/testsuite/gas/riscv/insn-dsp64-zbpbo.d new file mode 100644 index 000000000000..79b874c069ce --- /dev/null +++ b/gas/testsuite/gas/riscv/insn-dsp64-zbpbo.d @@ -0,0 +1,21 @@ +#as: -march=rv64gc_zbpbo_zpn_zpsf +#source: insn-dsp64-zbpbo.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : +[ ]+.*:[ ]+.*[ ]+cmix[ ]+a1,a2,a3,a4 +[ ]+.*:[ ]+.*[ ]+fsrw[ ]+a1,a2,a3,a4 +[ ]+.*:[ ]+.*[ ]+max[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+min[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+pack[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+packu[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+pack[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+packu[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+rev[ ]+a1,a2 +[ ]+.*:[ ]+.*[ ]+rev8.h[ ]+a1,a2 +[ ]+.*:[ ]+.*[ ]+rev8.h[ ]+a1,a2 diff --git a/gas/testsuite/gas/riscv/insn-dsp64-zbpbo.s b/gas/testsuite/gas/riscv/insn-dsp64-zbpbo.s new file mode 100644 index 000000000000..5aa197ca0219 --- /dev/null +++ b/gas/testsuite/gas/riscv/insn-dsp64-zbpbo.s @@ -0,0 +1,12 @@ +dsp64: + cmix a1,a2,a3,a4 + fsrw a1,a2,a3,a4 + max a1,a2,a3 + min a1,a2,a3 + pack a1,a2,a3 + packu a1,a2,a3 + pkbb32 a1,a2,a3 + pktt32 a1,a2,a3 + rev a1,a2 + rev8.h a1,a2 + swap8 a1,a2 diff --git a/gas/testsuite/gas/riscv/insn-dsp64.d b/gas/testsuite/gas/riscv/insn-dsp64.d new file mode 100644 index 000000000000..13a2912d6641 --- /dev/null +++ b/gas/testsuite/gas/riscv/insn-dsp64.d @@ -0,0 +1,91 @@ +#as: -march=rv64gc_zpn_zpsf +#source: insn-dsp64.s +#objdump: -dr + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : +[ ]+.*:[ ]+.*[ ]+add32[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+radd32[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+uradd32[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+kadd32[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+ukadd32[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+sub32[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+rsub32[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+ursub32[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+ksub32[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+uksub32[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+cras32[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+rcras32[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+urcras32[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+kcras32[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+ukcras32[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+crsa32[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+rcrsa32[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+urcrsa32[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+kcrsa32[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+ukcrsa32[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+stas32[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+rstas32[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+urstas32[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+kstas32[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+ukstas32[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+stsa32[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+rstsa32[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+urstsa32[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+kstsa32[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+ukstsa32[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+sra32[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+srai32[ ]+a1,a2,5 +[ ]+.*:[ ]+.*[ ]+sra32.u[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+srai32.u[ ]+a1,a2,5 +[ ]+.*:[ ]+.*[ ]+srl32[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+srli32[ ]+a1,a2,5 +[ ]+.*:[ ]+.*[ ]+srl32.u[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+srli32.u[ ]+a1,a2,5 +[ ]+.*:[ ]+.*[ ]+sll32[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+slli32[ ]+a1,a2,5 +[ ]+.*:[ ]+.*[ ]+ksll32[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+kslli32[ ]+a1,a2,5 +[ ]+.*:[ ]+.*[ ]+kslra32[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+kslra32.u[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+smin32[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+umin32[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+smax32[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+umax32[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+kabs32[ ]+a1,a2 +[ ]+.*:[ ]+.*[ ]+khmbb16[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+khmbt16[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+khmtt16[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+kdmbb16[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+kdmbt16[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+kdmtt16[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+kdmabb16[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+kdmabt16[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+kdmatt16[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+mulsr64[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+smbt32[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+smtt32[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+kmabb32[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+kmabt32[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+kmatt32[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+kmda32[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+kmxda32[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+kmar64[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+kmaxda32[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+kmads32[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+kmadrs32[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+kmaxds32[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+kmsda32[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+kmsxda32[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+smds32[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+smdrs32[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+smxds32[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+sraiw.u[ ]+a1,a2,5 +[ ]+.*:[ ]+.*[ ]+pkbb32[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+pkbt32[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+pktt32[ ]+a1,a2,a3 +[ ]+.*:[ ]+.*[ ]+pktb32[ ]+a1,a2,a3 diff --git a/gas/testsuite/gas/riscv/insn-dsp64.s b/gas/testsuite/gas/riscv/insn-dsp64.s new file mode 100644 index 000000000000..38a5573da112 --- /dev/null +++ b/gas/testsuite/gas/riscv/insn-dsp64.s @@ -0,0 +1,99 @@ +dsp64: + # Table 25. (RV64 Only) SIMD 32-bit Add/Subtract Instructions (30) + add32 a1, a2, a3 + radd32 a1, a2, a3 + uradd32 a1, a2, a3 + kadd32 a1, a2, a3 + ukadd32 a1, a2, a3 + sub32 a1, a2, a3 + rsub32 a1, a2, a3 + ursub32 a1, a2, a3 + ksub32 a1, a2, a3 + uksub32 a1, a2, a3 + cras32 a1, a2, a3 + rcras32 a1, a2, a3 + urcras32 a1, a2, a3 + kcras32 a1, a2, a3 + ukcras32 a1, a2, a3 + crsa32 a1, a2, a3 + rcrsa32 a1, a2, a3 + urcrsa32 a1, a2, a3 + kcrsa32 a1, a2, a3 + ukcrsa32 a1, a2, a3 + stas32 a1, a2, a3 + rstas32 a1, a2, a3 + urstas32 a1, a2, a3 + kstas32 a1, a2, a3 + ukstas32 a1, a2, a3 + stsa32 a1, a2, a3 + rstsa32 a1, a2, a3 + urstsa32 a1, a2, a3 + kstsa32 a1, a2, a3 + ukstsa32 a1, a2, a3 + + # Table 26. (RV64 Only) SIMD 32-bit Shift Instructions (14) + sra32 a1, a2, a3 + srai32 a1, a2, 5 + sra32.u a1, a2, a3 + srai32.u a1, a2, 5 + srl32 a1, a2, a3 + srli32 a1, a2, 5 + srl32.u a1, a2, a3 + srli32.u a1, a2, 5 + sll32 a1, a2, a3 + slli32 a1, a2, 5 + ksll32 a1, a2, a3 + kslli32 a1, a2, 5 + kslra32 a1, a2, a3 + kslra32.u a1, a2, a3 + + # Table 27. (RV64 Only) SIMD 32-bit Miscellaneous Instructions (5) + smin32 a1, a2, a3 + umin32 a1, a2, a3 + smax32 a1, a2, a3 + umax32 a1, a2, a3 + kabs32 a1, a2 + + # Table 28. (RV64 Only) SIMD Q15 saturating Multiply Instructions (9) + khmbb16 a1, a2, a3 + khmbt16 a1, a2, a3 + khmtt16 a1, a2, a3 + kdmbb16 a1, a2, a3 + kdmbt16 a1, a2, a3 + kdmtt16 a1, a2, a3 + kdmabb16 a1, a2, a3 + kdmabt16 a1, a2, a3 + kdmatt16 a1, a2, a3 + + # Table 29. (RV64 Only) 32-bit Multiply Instructions (3) + smbb32 a1, a2, a3 + smbt32 a1, a2, a3 + smtt32 a1, a2, a3 + + # Table 30. (RV64 Only) 32-bit Multiply & Add Instructions (3) + kmabb32 a1, a2, a3 + kmabt32 a1, a2, a3 + kmatt32 a1, a2, a3 + + # Table 31. (RV64 Only) 32-bit Parallel Multiply & Add Instructions (12) + kmda32 a1, a2, a3 + kmxda32 a1, a2, a3 + kmar64 a1, a2, a3 + kmaxda32 a1, a2, a3 + kmads32 a1, a2, a3 + kmadrs32 a1, a2, a3 + kmaxds32 a1, a2, a3 + kmsda32 a1, a2, a3 + kmsxda32 a1, a2, a3 + smds32 a1, a2, a3 + smdrs32 a1, a2, a3 + smxds32 a1, a2, a3 + + # Table 32. (RV64 Only) Non-SIMD 32-bit Shift Instructions (1) + sraiw.u a1, a2, 5 + + # Table 33. 32-bit Packing Instructions (4) + pkbb32 a1, a2, a3 + pkbt32 a1, a2, a3 + pktt32 a1, a2, a3 + pktb32 a1, a2, a3 diff --git a/gas/testsuite/gas/riscv/march-fail-version.l b/gas/testsuite/gas/riscv/march-fail-version.l index c7f8a4d5487c..b86520d74cce 100644 --- a/gas/testsuite/gas/riscv/march-fail-version.l +++ b/gas/testsuite/gas/riscv/march-fail-version.l @@ -1,3 +1,2 @@ .*Assembler messages: -.*Error: cannot find default versions of the ISA extension `p' .*Error: .*expect number after `2p' diff --git a/gas/testsuite/gas/riscv/rvp_csr.d b/gas/testsuite/gas/riscv/rvp_csr.d new file mode 100644 index 000000000000..2787389a617a --- /dev/null +++ b/gas/testsuite/gas/riscv/rvp_csr.d @@ -0,0 +1,12 @@ +#as: -march=rv32gc_zpn +#objdump: -dr + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : +[ ]+[0-9a-f]+:[ ]+00905073[ ]+csrwi[ ]+vxsat,0 +[ ]+[0-9a-f]+:[ ]+0090f073[ ]+csrci[ ]+vxsat,1 +[ ]+[0-9a-f]+:[ ]+009022f3[ ]+csrr[ ]+t0,vxsat diff --git a/gas/testsuite/gas/riscv/rvp_csr.s b/gas/testsuite/gas/riscv/rvp_csr.s new file mode 100644 index 000000000000..9820ca8dcdfd --- /dev/null +++ b/gas/testsuite/gas/riscv/rvp_csr.s @@ -0,0 +1,4 @@ +rvp: + csrwi vxsat,0 + csrci vxsat,1 + csrr t0,vxsat diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index 9999da6241a4..79bacd9a0415 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -621,6 +621,659 @@ #define MASK_C_LDSP 0xe003 #define MATCH_C_SDSP 0xe002 #define MASK_C_SDSP 0xe003 +/* Instruction opcode macros for RVP. */ +#define MATCH_ADD8 0x48000077 +#define MASK_ADD8 0xfe00707f +#define MATCH_ADD16 0x40000077 +#define MASK_ADD16 0xfe00707f +#define MATCH_ADD64 0xc0001077 +#define MASK_ADD64 0xfe00707f +#define MATCH_AVE 0xe0000077 +#define MASK_AVE 0xfe00707f +#define MATCH_BITREV 0xe6000077 +#define MASK_BITREV 0xfe00707f +#define MATCH_BITREVI 0xe8000077 +#define MASK_BITREVI 0xfc00707f +#define MATCH_CLRS8 0xae000077 +#define MASK_CLRS8 0xfff0707f +#define MATCH_CLRS16 0xae800077 +#define MASK_CLRS16 0xfff0707f +#define MATCH_CLRS32 0xaf800077 +#define MASK_CLRS32 0xfff0707f +#define MATCH_CLZ8 0xae100077 +#define MASK_CLZ8 0xfff0707f +#define MATCH_CLZ16 0xae900077 +#define MASK_CLZ16 0xfff0707f +#define MATCH_CLZ32 0xaf900077 +#define MASK_CLZ32 0xfff0707f +#define MATCH_CMPEQ8 0x4e000077 +#define MASK_CMPEQ8 0xfe00707f +#define MATCH_CMPEQ16 0x4c000077 +#define MASK_CMPEQ16 0xfe00707f +#define MATCH_CRAS16 0x44000077 +#define MASK_CRAS16 0xfe00707f +#define MATCH_CRSA16 0x46000077 +#define MASK_CRSA16 0xfe00707f +#define MATCH_INSB 0xac000077 +#define MASK_INSB 0xff80707f +#define MATCH_KABS8 0xad000077 +#define MASK_KABS8 0xfff0707f +#define MATCH_KABS16 0xad100077 +#define MASK_KABS16 0xfff0707f +#define MATCH_KABSW 0xad400077 +#define MASK_KABSW 0xfff0707f +#define MATCH_KADD8 0x18000077 +#define MASK_KADD8 0xfe00707f +#define MATCH_KADD16 0x10000077 +#define MASK_KADD16 0xfe00707f +#define MATCH_KADD64 0x90001077 +#define MASK_KADD64 0xfe00707f +#define MATCH_KADDH 0x4001077 +#define MASK_KADDH 0xfe00707f +#define MATCH_KADDW 0x1077 +#define MASK_KADDW 0xfe00707f +#define MATCH_KCRAS16 0x14000077 +#define MASK_KCRAS16 0xfe00707f +#define MATCH_KCRSA16 0x16000077 +#define MASK_KCRSA16 0xfe00707f +#define MATCH_KDMBB 0xa001077 +#define MASK_KDMBB 0xfe00707f +#define MATCH_KDMBT 0x1a001077 +#define MASK_KDMBT 0xfe00707f +#define MATCH_KDMTT 0x2a001077 +#define MASK_KDMTT 0xfe00707f +#define MATCH_KDMABB 0xd2001077 +#define MASK_KDMABB 0xfe00707f +#define MATCH_KDMABT 0xe2001077 +#define MASK_KDMABT 0xfe00707f +#define MATCH_KDMATT 0xf2001077 +#define MASK_KDMATT 0xfe00707f +#define MATCH_KHM8 0x8e000077 +#define MASK_KHM8 0xfe00707f +#define MATCH_KHMX8 0x9e000077 +#define MASK_KHMX8 0xfe00707f +#define MATCH_KHM16 0x86000077 +#define MASK_KHM16 0xfe00707f +#define MATCH_KHMX16 0x96000077 +#define MASK_KHMX16 0xfe00707f +#define MATCH_KHMBB 0xc001077 +#define MASK_KHMBB 0xfe00707f +#define MATCH_KHMBT 0x1c001077 +#define MASK_KHMBT 0xfe00707f +#define MATCH_KHMTT 0x2c001077 +#define MASK_KHMTT 0xfe00707f +#define MATCH_KMABB 0x5a001077 +#define MASK_KMABB 0xfe00707f +#define MATCH_KMABT 0x6a001077 +#define MASK_KMABT 0xfe00707f +#define MATCH_KMATT 0x7a001077 +#define MASK_KMATT 0xfe00707f +#define MATCH_KMADA 0x48001077 +#define MASK_KMADA 0xfe00707f +#define MATCH_KMAXDA 0x4a001077 +#define MASK_KMAXDA 0xfe00707f +#define MATCH_KMADS 0x5c001077 +#define MASK_KMADS 0xfe00707f +#define MATCH_KMADRS 0x6c001077 +#define MASK_KMADRS 0xfe00707f +#define MATCH_KMAXDS 0x7c001077 +#define MASK_KMAXDS 0xfe00707f +#define MATCH_KMAR64 0x94001077 +#define MASK_KMAR64 0xfe00707f +#define MATCH_KMDA 0x38001077 +#define MASK_KMDA 0xfe00707f +#define MATCH_KMXDA 0x3a001077 +#define MASK_KMXDA 0xfe00707f +#define MATCH_KMMAC 0x60001077 +#define MASK_KMMAC 0xfe00707f +#define MATCH_KMMAC_U 0x70001077 +#define MASK_KMMAC_U 0xfe00707f +#define MATCH_KMMAWB 0x46001077 +#define MASK_KMMAWB 0xfe00707f +#define MATCH_KMMAWB_U 0x56001077 +#define MASK_KMMAWB_U 0xfe00707f +#define MATCH_KMMAWB2 0xce001077 +#define MASK_KMMAWB2 0xfe00707f +#define MATCH_KMMAWB2_U 0xde001077 +#define MASK_KMMAWB2_U 0xfe00707f +#define MATCH_KMMAWT 0x66001077 +#define MASK_KMMAWT 0xfe00707f +#define MATCH_KMMAWT_U 0x76001077 +#define MASK_KMMAWT_U 0xfe00707f +#define MATCH_KMMAWT2 0xee001077 +#define MASK_KMMAWT2 0xfe00707f +#define MATCH_KMMAWT2_U 0xfe001077 +#define MASK_KMMAWT2_U 0xfe00707f +#define MATCH_KMMSB 0x42001077 +#define MASK_KMMSB 0xfe00707f +#define MATCH_KMMSB_U 0x52001077 +#define MASK_KMMSB_U 0xfe00707f +#define MATCH_KMMWB2 0x8e001077 +#define MASK_KMMWB2 0xfe00707f +#define MATCH_KMMWB2_U 0x9e001077 +#define MASK_KMMWB2_U 0xfe00707f +#define MATCH_KMMWT2 0xae001077 +#define MASK_KMMWT2 0xfe00707f +#define MATCH_KMMWT2_U 0xbe001077 +#define MASK_KMMWT2_U 0xfe00707f +#define MATCH_KMSDA 0x4c001077 +#define MASK_KMSDA 0xfe00707f +#define MATCH_KMSXDA 0x4e001077 +#define MASK_KMSXDA 0xfe00707f +#define MATCH_KMSR64 0x96001077 +#define MASK_KMSR64 0xfe00707f +#define MATCH_KSLLW 0x26001077 +#define MASK_KSLLW 0xfe00707f +#define MATCH_KSLLIW 0x36001077 +#define MASK_KSLLIW 0xfe00707f +#define MATCH_KSLL8 0x6c000077 +#define MASK_KSLL8 0xfe00707f +#define MATCH_KSLLI8 0x7c800077 +#define MASK_KSLLI8 0xff80707f +#define MATCH_KSLL16 0x64000077 +#define MASK_KSLL16 0xfe00707f +#define MATCH_KSLLI16 0x75000077 +#define MASK_KSLLI16 0xff00707f +#define MATCH_KSLRA8 0x5e000077 +#define MASK_KSLRA8 0xfe00707f +#define MATCH_KSLRA8_U 0x6e000077 +#define MASK_KSLRA8_U 0xfe00707f +#define MATCH_KSLRA16 0x56000077 +#define MASK_KSLRA16 0xfe00707f +#define MATCH_KSLRA16_U 0x66000077 +#define MASK_KSLRA16_U 0xfe00707f +#define MATCH_KSLRAW 0x6e001077 +#define MASK_KSLRAW 0xfe00707f +#define MATCH_KSLRAW_U 0x7e001077 +#define MASK_KSLRAW_U 0xfe00707f +#define MATCH_KSTAS16 0xc4002077 +#define MASK_KSTAS16 0xfe00707f +#define MATCH_KSTSA16 0xc6002077 +#define MASK_KSTSA16 0xfe00707f +#define MATCH_KSUB8 0x1a000077 +#define MASK_KSUB8 0xfe00707f +#define MATCH_KSUB16 0x12000077 +#define MASK_KSUB16 0xfe00707f +#define MATCH_KSUB64 0x92001077 +#define MASK_KSUB64 0xfe00707f +#define MATCH_KSUBH 0x6001077 +#define MASK_KSUBH 0xfe00707f +#define MATCH_KSUBW 0x2001077 +#define MASK_KSUBW 0xfe00707f +#define MATCH_KWMMUL 0x62001077 +#define MASK_KWMMUL 0xfe00707f +#define MATCH_KWMMUL_U 0x72001077 +#define MASK_KWMMUL_U 0xfe00707f +#define MATCH_MTLEI 0xfa000077 +#define MASK_MTLEI 0xfe00707f +#define MATCH_MADDR32 0xc4001077 +#define MASK_MADDR32 0xfe00707f +#define MATCH_MSUBR32 0xc6001077 +#define MASK_MSUBR32 0xfe00707f +#define MATCH_MULR64 0xf0001077 +#define MASK_MULR64 0xfe00707f +#define MATCH_MULSR64 0xe0001077 +#define MASK_MULSR64 0xfe00707f +#define MATCH_PBSAD 0xfc000077 +#define MASK_PBSAD 0xfe00707f +#define MATCH_PBSADA 0xfe000077 +#define MASK_PBSADA 0xfe00707f +#define MATCH_PKBB16 0xe001077 +#define MASK_PKBB16 0xfe00707f +#define MATCH_PKBT16 0x1e001077 +#define MASK_PKBT16 0xfe00707f +#define MATCH_PKTT16 0x2e001077 +#define MASK_PKTT16 0xfe00707f +#define MATCH_PKTB16 0x3e001077 +#define MASK_PKTB16 0xfe00707f +#define MATCH_RADD8 0x8000077 +#define MASK_RADD8 0xfe00707f +#define MATCH_RADD16 0x77 +#define MASK_RADD16 0xfe00707f +#define MATCH_RADD64 0x80001077 +#define MASK_RADD64 0xfe00707f +#define MATCH_RADDW 0x20001077 +#define MASK_RADDW 0xfe00707f +#define MATCH_RCRAS16 0x4000077 +#define MASK_RCRAS16 0xfe00707f +#define MATCH_RCRSA16 0x6000077 +#define MASK_RCRSA16 0xfe00707f +#define MATCH_RSTAS16 0xb4002077 +#define MASK_RSTAS16 0xfe00707f +#define MATCH_RSTSA16 0xb6002077 +#define MASK_RSTSA16 0xfe00707f +#define MATCH_RSUB8 0xa000077 +#define MASK_RSUB8 0xfe00707f +#define MATCH_RSUB16 0x2000077 +#define MASK_RSUB16 0xfe00707f +#define MATCH_RSUB64 0x82001077 +#define MASK_RSUB64 0xfe00707f +#define MATCH_RSUBW 0x22001077 +#define MASK_RSUBW 0xfe00707f +#define MATCH_SCLIP8 0x8c000077 +#define MASK_SCLIP8 0xff80707f +#define MATCH_SCLIP16 0x84000077 +#define MASK_SCLIP16 0xff00707f +#define MATCH_SCLIP32 0xe4000077 +#define MASK_SCLIP32 0xfe00707f +#define MATCH_SCMPLE8 0x1e000077 +#define MASK_SCMPLE8 0xfe00707f +#define MATCH_SCMPLE16 0x1c000077 +#define MASK_SCMPLE16 0xfe00707f +#define MATCH_SCMPLT8 0xe000077 +#define MASK_SCMPLT8 0xfe00707f +#define MATCH_SCMPLT16 0xc000077 +#define MASK_SCMPLT16 0xfe00707f +#define MATCH_SLL8 0x5c000077 +#define MASK_SLL8 0xfe00707f +#define MATCH_SLLI8 0x7c000077 +#define MASK_SLLI8 0xff80707f +#define MATCH_SLL16 0x54000077 +#define MASK_SLL16 0xfe00707f +#define MATCH_SLLI16 0x74000077 +#define MASK_SLLI16 0xff00707f +#define MATCH_SMAL 0x5e001077 +#define MASK_SMAL 0xfe00707f +#define MATCH_SMALBB 0x88001077 +#define MASK_SMALBB 0xfe00707f +#define MATCH_SMALBT 0x98001077 +#define MASK_SMALBT 0xfe00707f +#define MATCH_SMALTT 0xa8001077 +#define MASK_SMALTT 0xfe00707f +#define MATCH_SMALDA 0x8c001077 +#define MASK_SMALDA 0xfe00707f +#define MATCH_SMALXDA 0x9c001077 +#define MASK_SMALXDA 0xfe00707f +#define MATCH_SMALDS 0x8a001077 +#define MASK_SMALDS 0xfe00707f +#define MATCH_SMALDRS 0x9a001077 +#define MASK_SMALDRS 0xfe00707f +#define MATCH_SMALXDS 0xaa001077 +#define MASK_SMALXDS 0xfe00707f +#define MATCH_SMAR64 0x84001077 +#define MASK_SMAR64 0xfe00707f +#define MATCH_SMAQA 0xc8000077 +#define MASK_SMAQA 0xfe00707f +#define MATCH_SMAQA_SU 0xca000077 +#define MASK_SMAQA_SU 0xfe00707f +#define MATCH_SMAX8 0x8a000077 +#define MASK_SMAX8 0xfe00707f +#define MATCH_SMAX16 0x82000077 +#define MASK_SMAX16 0xfe00707f +#define MATCH_SMBB16 0x8001077 +#define MASK_SMBB16 0xfe00707f +#define MATCH_SMBT16 0x18001077 +#define MASK_SMBT16 0xfe00707f +#define MATCH_SMTT16 0x28001077 +#define MASK_SMTT16 0xfe00707f +#define MATCH_SMDS 0x58001077 +#define MASK_SMDS 0xfe00707f +#define MATCH_SMDRS 0x68001077 +#define MASK_SMDRS 0xfe00707f +#define MATCH_SMXDS 0x78001077 +#define MASK_SMXDS 0xfe00707f +#define MATCH_SMIN8 0x88000077 +#define MASK_SMIN8 0xfe00707f +#define MATCH_SMIN16 0x80000077 +#define MASK_SMIN16 0xfe00707f +#define MATCH_SMMUL 0x40001077 +#define MASK_SMMUL 0xfe00707f +#define MATCH_SMMUL_U 0x50001077 +#define MASK_SMMUL_U 0xfe00707f +#define MATCH_SMMWB 0x44001077 +#define MASK_SMMWB 0xfe00707f +#define MATCH_SMMWB_U 0x54001077 +#define MASK_SMMWB_U 0xfe00707f +#define MATCH_SMMWT 0x64001077 +#define MASK_SMMWT 0xfe00707f +#define MATCH_SMMWT_U 0x74001077 +#define MASK_SMMWT_U 0xfe00707f +#define MATCH_SMSLDA 0xac001077 +#define MASK_SMSLDA 0xfe00707f +#define MATCH_SMSLXDA 0xbc001077 +#define MASK_SMSLXDA 0xfe00707f +#define MATCH_SMSR64 0x86001077 +#define MASK_SMSR64 0xfe00707f +#define MATCH_SMUL8 0xa8000077 +#define MASK_SMUL8 0xfe00707f +#define MATCH_SMULX8 0xaa000077 +#define MASK_SMULX8 0xfe00707f +#define MATCH_SMUL16 0xa0000077 +#define MASK_SMUL16 0xfe00707f +#define MATCH_SMULX16 0xa2000077 +#define MASK_SMULX16 0xfe00707f +#define MATCH_SRA_U 0x24001077 +#define MASK_SRA_U 0xfe00707f +#define MATCH_SRAI_U 0xd4001077 +#define MASK_SRAI_U 0xfc00707f +#define MATCH_SRA8 0x58000077 +#define MASK_SRA8 0xfe00707f +#define MATCH_SRA8_U 0x68000077 +#define MASK_SRA8_U 0xfe00707f +#define MATCH_SRAI8 0x78000077 +#define MASK_SRAI8 0xff80707f +#define MATCH_SRAI8_U 0x78800077 +#define MASK_SRAI8_U 0xff80707f +#define MATCH_SRA16 0x50000077 +#define MASK_SRA16 0xfe00707f +#define MATCH_SRA16_U 0x60000077 +#define MASK_SRA16_U 0xfe00707f +#define MATCH_SRAI16 0x70000077 +#define MASK_SRAI16 0xff00707f +#define MATCH_SRAI16_U 0x71000077 +#define MASK_SRAI16_U 0xff00707f +#define MATCH_SRL8 0x5a000077 +#define MASK_SRL8 0xfe00707f +#define MATCH_SRL8_U 0x6a000077 +#define MASK_SRL8_U 0xfe00707f +#define MATCH_SRLI8 0x7a000077 +#define MASK_SRLI8 0xff80707f +#define MATCH_SRLI8_U 0x7a800077 +#define MASK_SRLI8_U 0xff80707f +#define MATCH_SRL16 0x52000077 +#define MASK_SRL16 0xfe00707f +#define MATCH_SRL16_U 0x62000077 +#define MASK_SRL16_U 0xfe00707f +#define MATCH_SRLI16 0x72000077 +#define MASK_SRLI16 0xff00707f +#define MATCH_SRLI16_U 0x73000077 +#define MASK_SRLI16_U 0xff00707f +#define MATCH_STAS16 0xf4002077 +#define MASK_STAS16 0xfe00707f +#define MATCH_STSA16 0xf6002077 +#define MASK_STSA16 0xfe00707f +#define MATCH_SUB8 0x4a000077 +#define MASK_SUB8 0xfe00707f +#define MATCH_SUB16 0x42000077 +#define MASK_SUB16 0xfe00707f +#define MATCH_SUB64 0xc2001077 +#define MASK_SUB64 0xfe00707f +#define MATCH_SUNPKD810 0xac800077 +#define MASK_SUNPKD810 0xfff0707f +#define MATCH_SUNPKD820 0xac900077 +#define MASK_SUNPKD820 0xfff0707f +#define MATCH_SUNPKD830 0xaca00077 +#define MASK_SUNPKD830 0xfff0707f +#define MATCH_SUNPKD831 0xacb00077 +#define MASK_SUNPKD831 0xfff0707f +#define MATCH_SUNPKD832 0xad300077 +#define MASK_SUNPKD832 0xfff0707f +#define MATCH_SWAP8 0xad800077 +#define MASK_SWAP8 0xfff0707f +#define MATCH_UCLIP8 0x8d000077 +#define MASK_UCLIP8 0xff80707f +#define MATCH_UCLIP16 0x85000077 +#define MASK_UCLIP16 0xff00707f +#define MATCH_UCLIP32 0xf4000077 +#define MASK_UCLIP32 0xfe00707f +#define MATCH_UCMPLE8 0x3e000077 +#define MASK_UCMPLE8 0xfe00707f +#define MATCH_UCMPLE16 0x3c000077 +#define MASK_UCMPLE16 0xfe00707f +#define MATCH_UCMPLT8 0x2e000077 +#define MASK_UCMPLT8 0xfe00707f +#define MATCH_UCMPLT16 0x2c000077 +#define MASK_UCMPLT16 0xfe00707f +#define MATCH_UKADD8 0x38000077 +#define MASK_UKADD8 0xfe00707f +#define MATCH_UKADD16 0x30000077 +#define MASK_UKADD16 0xfe00707f +#define MATCH_UKADD64 0xb0001077 +#define MASK_UKADD64 0xfe00707f +#define MATCH_UKADDH 0x14001077 +#define MASK_UKADDH 0xfe00707f +#define MATCH_UKADDW 0x10001077 +#define MASK_UKADDW 0xfe00707f +#define MATCH_UKCRAS16 0x34000077 +#define MASK_UKCRAS16 0xfe00707f +#define MATCH_UKCRSA16 0x36000077 +#define MASK_UKCRSA16 0xfe00707f +#define MATCH_UKMAR64 0xb4001077 +#define MASK_UKMAR64 0xfe00707f +#define MATCH_UKMSR64 0xb6001077 +#define MASK_UKMSR64 0xfe00707f +#define MATCH_UKSTAS16 0xe4002077 +#define MASK_UKSTAS16 0xfe00707f +#define MATCH_UKSTSA16 0xe6002077 +#define MASK_UKSTSA16 0xfe00707f +#define MATCH_UKSUB8 0x3a000077 +#define MASK_UKSUB8 0xfe00707f +#define MATCH_UKSUB16 0x32000077 +#define MASK_UKSUB16 0xfe00707f +#define MATCH_UKSUB64 0xb2001077 +#define MASK_UKSUB64 0xfe00707f +#define MATCH_UKSUBH 0x16001077 +#define MASK_UKSUBH 0xfe00707f +#define MATCH_UKSUBW 0x12001077 +#define MASK_UKSUBW 0xfe00707f +#define MATCH_UMAR64 0xa4001077 +#define MASK_UMAR64 0xfe00707f +#define MATCH_UMAQA 0xcc000077 +#define MASK_UMAQA 0xfe00707f +#define MATCH_UMAX8 0x9a000077 +#define MASK_UMAX8 0xfe00707f +#define MATCH_UMAX16 0x92000077 +#define MASK_UMAX16 0xfe00707f +#define MATCH_UMIN8 0x98000077 +#define MASK_UMIN8 0xfe00707f +#define MATCH_UMIN16 0x90000077 +#define MASK_UMIN16 0xfe00707f +#define MATCH_UMSR64 0xa6001077 +#define MASK_UMSR64 0xfe00707f +#define MATCH_UMUL8 0xb8000077 +#define MASK_UMUL8 0xfe00707f +#define MATCH_UMULX8 0xba000077 +#define MASK_UMULX8 0xfe00707f +#define MATCH_UMUL16 0xb0000077 +#define MASK_UMUL16 0xfe00707f +#define MATCH_UMULX16 0xb2000077 +#define MASK_UMULX16 0xfe00707f +#define MATCH_URADD8 0x28000077 +#define MASK_URADD8 0xfe00707f +#define MATCH_URADD16 0x20000077 +#define MASK_URADD16 0xfe00707f +#define MATCH_URADD64 0xa0001077 +#define MASK_URADD64 0xfe00707f +#define MATCH_URADDW 0x30001077 +#define MASK_URADDW 0xfe00707f +#define MATCH_URCRAS16 0x24000077 +#define MASK_URCRAS16 0xfe00707f +#define MATCH_URCRSA16 0x26000077 +#define MASK_URCRSA16 0xfe00707f +#define MATCH_URSTAS16 0xd4002077 +#define MASK_URSTAS16 0xfe00707f +#define MATCH_URSTSA16 0xd6002077 +#define MASK_URSTSA16 0xfe00707f +#define MATCH_URSUB8 0x2a000077 +#define MASK_URSUB8 0xfe00707f +#define MATCH_URSUB16 0x22000077 +#define MASK_URSUB16 0xfe00707f +#define MATCH_URSUB64 0xa2001077 +#define MASK_URSUB64 0xfe00707f +#define MATCH_URSUBW 0x32001077 +#define MASK_URSUBW 0xfe00707f +#define MATCH_WEXTI 0xde000077 +#define MASK_WEXTI 0xfe00707f +#define MATCH_WEXT 0xce000077 +#define MASK_WEXT 0xfe00707f +#define MATCH_ZUNPKD810 0xacc00077 +#define MASK_ZUNPKD810 0xfff0707f +#define MATCH_ZUNPKD820 0xacd00077 +#define MASK_ZUNPKD820 0xfff0707f +#define MATCH_ZUNPKD830 0xace00077 +#define MASK_ZUNPKD830 0xfff0707f +#define MATCH_ZUNPKD831 0xacf00077 +#define MASK_ZUNPKD831 0xfff0707f +#define MATCH_ZUNPKD832 0xad700077 +#define MASK_ZUNPKD832 0xfff0707f +#define MATCH_ADD32 0x40002077 +#define MASK_ADD32 0xfe00707f +#define MATCH_CRAS32 0x44002077 +#define MASK_CRAS32 0xfe00707f +#define MATCH_CRSA32 0x46002077 +#define MASK_CRSA32 0xfe00707f +#define MATCH_KABS32 0xad200077 +#define MASK_KABS32 0xfff0707f +#define MATCH_KADD32 0x10002077 +#define MASK_KADD32 0xfe00707f +#define MATCH_KCRAS32 0x14002077 +#define MASK_KCRAS32 0xfe00707f +#define MATCH_KCRSA32 0x16002077 +#define MASK_KCRSA32 0xfe00707f +#define MATCH_KDMBB16 0xda001077 +#define MASK_KDMBB16 0xfe00707f +#define MATCH_KDMBT16 0xea001077 +#define MASK_KDMBT16 0xfe00707f +#define MATCH_KDMTT16 0xfa001077 +#define MASK_KDMTT16 0xfe00707f +#define MATCH_KDMABB16 0xd8001077 +#define MASK_KDMABB16 0xfe00707f +#define MATCH_KDMABT16 0xe8001077 +#define MASK_KDMABT16 0xfe00707f +#define MATCH_KDMATT16 0xf8001077 +#define MASK_KDMATT16 0xfe00707f +#define MATCH_KHMBB16 0xdc001077 +#define MASK_KHMBB16 0xfe00707f +#define MATCH_KHMBT16 0xec001077 +#define MASK_KHMBT16 0xfe00707f +#define MATCH_KHMTT16 0xfc001077 +#define MASK_KHMTT16 0xfe00707f +#define MATCH_KMABB32 0x5a002077 +#define MASK_KMABB32 0xfe00707f +#define MATCH_KMABT32 0x6a002077 +#define MASK_KMABT32 0xfe00707f +#define MATCH_KMATT32 0x7a002077 +#define MASK_KMATT32 0xfe00707f +#define MATCH_KMAXDA32 0x4a002077 +#define MASK_KMAXDA32 0xfe00707f +#define MATCH_KMDA32 0x38002077 +#define MASK_KMDA32 0xfe00707f +#define MATCH_KMXDA32 0x3a002077 +#define MASK_KMXDA32 0xfe00707f +#define MATCH_KMADS32 0x5c002077 +#define MASK_KMADS32 0xfe00707f +#define MATCH_KMADRS32 0x6c002077 +#define MASK_KMADRS32 0xfe00707f +#define MATCH_KMAXDS32 0x7c002077 +#define MASK_KMAXDS32 0xfe00707f +#define MATCH_KMSDA32 0x4c002077 +#define MASK_KMSDA32 0xfe00707f +#define MATCH_KMSXDA32 0x4e002077 +#define MASK_KMSXDA32 0xfe00707f +#define MATCH_KSLL32 0x64002077 +#define MASK_KSLL32 0xfe00707f +#define MATCH_KSLLI32 0x84002077 +#define MASK_KSLLI32 0xfe00707f +#define MATCH_KSLRA32 0x56002077 +#define MASK_KSLRA32 0xfe00707f +#define MATCH_KSLRA32_U 0x66002077 +#define MASK_KSLRA32_U 0xfe00707f +#define MATCH_KSTAS32 0xc0002077 +#define MASK_KSTAS32 0xfe00707f +#define MATCH_KSTSA32 0xc2002077 +#define MASK_KSTSA32 0xfe00707f +#define MATCH_KSUB32 0x12002077 +#define MASK_KSUB32 0xfe00707f +#define MATCH_PKBB32 0xe002077 +#define MASK_PKBB32 0xfe00707f +#define MATCH_PKBT32 0x1e002077 +#define MASK_PKBT32 0xfe00707f +#define MATCH_PKTT32 0x2e002077 +#define MASK_PKTT32 0xfe00707f +#define MATCH_PKTB32 0x3e002077 +#define MASK_PKTB32 0xfe00707f +#define MATCH_RADD32 0x2077 +#define MASK_RADD32 0xfe00707f +#define MATCH_RCRAS32 0x4002077 +#define MASK_RCRAS32 0xfe00707f +#define MATCH_RCRSA32 0x06002077 +#define MASK_RCRSA32 0xfe00707f +#define MATCH_RSTAS32 0xb0002077 +#define MASK_RSTAS32 0xfe00707f +#define MATCH_RSTSA32 0xb2002077 +#define MASK_RSTSA32 0xfe00707f +#define MATCH_RSUB32 0x02002077 +#define MASK_RSUB32 0xfe00707f +#define MATCH_SLL32 0x54002077 +#define MASK_SLL32 0xfe00707f +#define MATCH_SLLI32 0x74002077 +#define MASK_SLLI32 0xfe00707f +#define MATCH_SMAX32 0x92002077 +#define MASK_SMAX32 0xfe00707f +#define MATCH_SMBT32 0x18002077 +#define MASK_SMBT32 0xfe00707f +#define MATCH_SMTT32 0x28002077 +#define MASK_SMTT32 0xfe00707f +#define MATCH_SMDS32 0x58002077 +#define MASK_SMDS32 0xfe00707f +#define MATCH_SMDRS32 0x68002077 +#define MASK_SMDRS32 0xfe00707f +#define MATCH_SMXDS32 0x78002077 +#define MASK_SMXDS32 0xfe00707f +#define MATCH_SMIN32 0x90002077 +#define MASK_SMIN32 0xfe00707f +#define MATCH_SRA32 0x50002077 +#define MASK_SRA32 0xfe00707f +#define MATCH_SRA32_U 0x60002077 +#define MASK_SRA32_U 0xfe00707f +#define MATCH_SRAI32 0x70002077 +#define MASK_SRAI32 0xfe00707f +#define MATCH_SRAI32_U 0x80002077 +#define MASK_SRAI32_U 0xfe00707f +#define MATCH_SRAIW_U 0x34001077 +#define MASK_SRAIW_U 0xfe00707f +#define MATCH_SRL32 0x52002077 +#define MASK_SRL32 0xfe00707f +#define MATCH_SRL32_U 0x62002077 +#define MASK_SRL32_U 0xfe00707f +#define MATCH_SRLI32 0x72002077 +#define MASK_SRLI32 0xfe00707f +#define MATCH_SRLI32_U 0x82002077 +#define MASK_SRLI32_U 0xfe00707f +#define MATCH_STAS32 0xf0002077 +#define MASK_STAS32 0xfe00707f +#define MATCH_STSA32 0xf2002077 +#define MASK_STSA32 0xfe00707f +#define MATCH_SUB32 0x42002077 +#define MASK_SUB32 0xfe00707f +#define MATCH_UKADD32 0x30002077 +#define MASK_UKADD32 0xfe00707f +#define MATCH_UKCRAS32 0x34002077 +#define MASK_UKCRAS32 0xfe00707f +#define MATCH_UKCRSA32 0x36002077 +#define MASK_UKCRSA32 0xfe00707f +#define MATCH_UKSTAS32 0xe0002077 +#define MASK_UKSTAS32 0xfe00707f +#define MATCH_UKSTSA32 0xe2002077 +#define MASK_UKSTSA32 0xfe00707f +#define MATCH_UKSUB32 0x32002077 +#define MASK_UKSUB32 0xfe00707f +#define MATCH_UMAX32 0xa2002077 +#define MASK_UMAX32 0xfe00707f +#define MATCH_UMIN32 0xa0002077 +#define MASK_UMIN32 0xfe00707f +#define MATCH_URADD32 0x20002077 +#define MASK_URADD32 0xfe00707f +#define MATCH_URCRAS32 0x24002077 +#define MASK_URCRAS32 0xfe00707f +#define MATCH_URCRSA32 0x26002077 +#define MASK_URCRSA32 0xfe00707f +#define MATCH_URSTAS32 0xd0002077 +#define MASK_URSTAS32 0xfe00707f +#define MATCH_URSTSA32 0xd2002077 +#define MASK_URSTSA32 0xfe00707f +#define MATCH_URSUB32 0x22002077 +#define MASK_URSUB32 0xfe00707f +#define MATCH_CMIX 0x6001033 +#define MASK_CMIX 0x600707f +#define MATCH_FSR 0x4005033 +#define MASK_FSR 0x600707f +#define MATCH_FSRI 0x4005013 +#define MASK_FSRI 0x400707f +#define MATCH_FSRW 0x400503b +#define MASK_FSRW 0x600707f +#define MATCH_PACKU 0x48004033 +#define MASK_PACKU 0xfe00707f /* Privileged CSR addresses. */ #define CSR_USTATUS 0x0 #define CSR_UIE 0x4 @@ -868,6 +1521,8 @@ #define CSR_TCONTROL 0x7a5 #define CSR_MCONTEXT 0x7a8 #define CSR_SCONTEXT 0x7aa +/* RVP CSR */ +#define CSR_VXSAT 0x009 #endif /* RISCV_ENCODING_H */ #ifdef DECLARE_INSN DECLARE_INSN(slli_rv32, MATCH_SLLI_RV32, MASK_SLLI_RV32) @@ -1162,6 +1817,332 @@ DECLARE_INSN(c_sd, MATCH_C_SD, MASK_C_SD) DECLARE_INSN(c_addiw, MATCH_C_ADDIW, MASK_C_ADDIW) DECLARE_INSN(c_ldsp, MATCH_C_LDSP, MASK_C_LDSP) DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP) +DECLARE_INSN(add8, MATCH_ADD8, MASK_ADD8) +DECLARE_INSN(add16, MATCH_ADD16, MASK_ADD16) +DECLARE_INSN(add64, MATCH_ADD64, MASK_ADD64) +DECLARE_INSN(ave, MATCH_AVE, MASK_AVE) +DECLARE_INSN(bitrev, MATCH_BITREV, MASK_BITREV) +DECLARE_INSN(bitrevi, MATCH_BITREVI, MASK_BITREVI) +DECLARE_INSN(clrs8, MATCH_CLRS8, MASK_CLRS8) +DECLARE_INSN(clrs16, MATCH_CLRS16, MASK_CLRS16) +DECLARE_INSN(clrs32, MATCH_CLRS32, MASK_CLRS32) +DECLARE_INSN(clz8, MATCH_CLZ8, MASK_CLZ8) +DECLARE_INSN(clz16, MATCH_CLZ16, MASK_CLZ16) +DECLARE_INSN(clz32, MATCH_CLZ32, MASK_CLZ32) +DECLARE_INSN(cmpeq8, MATCH_CMPEQ8, MASK_CMPEQ8) +DECLARE_INSN(cmpeq16, MATCH_CMPEQ16, MASK_CMPEQ16) +DECLARE_INSN(cras16, MATCH_CRAS16, MASK_CRAS16) +DECLARE_INSN(crsa16, MATCH_CRSA16, MASK_CRSA16) +DECLARE_INSN(insb, MATCH_INSB, MASK_INSB) +DECLARE_INSN(kabs8, MATCH_KABS8, MASK_KABS8) +DECLARE_INSN(kabs16, MATCH_KABS16, MASK_KABS16) +DECLARE_INSN(kabsw, MATCH_KABSW, MASK_KABSW) +DECLARE_INSN(kadd8, MATCH_KADD8, MASK_KADD8) +DECLARE_INSN(kadd16, MATCH_KADD16, MASK_KADD16) +DECLARE_INSN(kadd64, MATCH_KADD64, MASK_KADD64) +DECLARE_INSN(kaddh, MATCH_KADDH, MASK_KADDH) +DECLARE_INSN(kaddw, MATCH_KADDW, MASK_KADDW) +DECLARE_INSN(kcras16, MATCH_KCRAS16, MASK_KCRAS16) +DECLARE_INSN(kcrsa16, MATCH_KCRSA16, MASK_KCRSA16) +DECLARE_INSN(kdmbb, MATCH_KDMBB, MASK_KDMBB) +DECLARE_INSN(kdmbt, MATCH_KDMBT, MASK_KDMBT) +DECLARE_INSN(kdmtt, MATCH_KDMTT, MASK_KDMTT) +DECLARE_INSN(kdmabb, MATCH_KDMABB, MASK_KDMABB) +DECLARE_INSN(kdmabt, MATCH_KDMABT, MASK_KDMABT) +DECLARE_INSN(kdmatt, MATCH_KDMATT, MASK_KDMATT) +DECLARE_INSN(khm8, MATCH_KHM8, MASK_KHM8) +DECLARE_INSN(khmx8, MATCH_KHMX8, MASK_KHMX8) +DECLARE_INSN(khm16, MATCH_KHM16, MASK_KHM16) +DECLARE_INSN(khmx16, MATCH_KHMX16, MASK_KHMX16) +DECLARE_INSN(khmbb, MATCH_KHMBB, MASK_KHMBB) +DECLARE_INSN(khmbt, MATCH_KHMBT, MASK_KHMBT) +DECLARE_INSN(khmtt, MATCH_KHMTT, MASK_KHMTT) +DECLARE_INSN(khabb, MATCH_KMABB, MASK_KMABB) +DECLARE_INSN(khabt, MATCH_KMABT, MASK_KMABT) +DECLARE_INSN(kmatt, MATCH_KMATT, MASK_KMATT) +DECLARE_INSN(kmada, MATCH_KMADA, MASK_KMADA) +DECLARE_INSN(kmaxda, MATCH_KMAXDA, MASK_KMAXDA) +DECLARE_INSN(kmads, MATCH_KMADS, MASK_KMADS) +DECLARE_INSN(kmadrs, MATCH_KMADRS, MASK_KMADRS) +DECLARE_INSN(kmaxds, MATCH_KMAXDS, MASK_KMAXDS) +DECLARE_INSN(kmar64, MATCH_KMAR64, MASK_KMAR64) +DECLARE_INSN(kmda, MATCH_KMDA, MASK_KMDA) +DECLARE_INSN(kmxda, MATCH_KMXDA, MASK_KMXDA) +DECLARE_INSN(kmmac, MATCH_KMMAC, MASK_KMMAC) +DECLARE_INSN(kmmac_u, MATCH_KMMAC_U, MASK_KMMAC_U) +DECLARE_INSN(kmmawb, MATCH_KMMAWB, MASK_KMMAWB) +DECLARE_INSN(kmmawb_u, MATCH_KMMAWB_U, MASK_KMMAWB_U) +DECLARE_INSN(kmmawb2, MATCH_KMMAWB2, MASK_KMMAWB2) +DECLARE_INSN(kmmawb2_u, MATCH_KMMAWB2_U, MASK_KMMAWB2_U) +DECLARE_INSN(kmmawt, MATCH_KMMAWT, MASK_KMMAWT) +DECLARE_INSN(kmmawt_u, MATCH_KMMAWT_U, MASK_KMMAWT_U) +DECLARE_INSN(kmmawt2, MATCH_KMMAWT2, MASK_KMMAWT2) +DECLARE_INSN(kmmawt2_u, MATCH_KMMAWT2_U, MASK_KMMAWT2_U) +DECLARE_INSN(kmmsb, MATCH_KMMSB, MASK_KMMSB) +DECLARE_INSN(kmmsb_u, MATCH_KMMSB_U, MASK_KMMSB_U) +DECLARE_INSN(kmmwb2, MATCH_KMMWB2, MASK_KMMWB2) +DECLARE_INSN(kmmwb2_u, MATCH_KMMWB2_U, MASK_KMMWB2_U) +DECLARE_INSN(kmmwt2, MATCH_KMMWT2, MASK_KMMWT2) +DECLARE_INSN(kmmwt2_u, MATCH_KMMWT2_U, MASK_KMMWT2_U) +DECLARE_INSN(kmsda, MATCH_KMSDA, MASK_KMSDA) +DECLARE_INSN(kmsxda, MATCH_KMSXDA, MASK_KMSXDA) +DECLARE_INSN(kmsr64, MATCH_KMSR64, MASK_KMSR64) +DECLARE_INSN(ksll, MATCH_KSLLW, MASK_KSLLW) +DECLARE_INSN(kslli, MATCH_KSLLIW, MASK_KSLLIW) +DECLARE_INSN(ksll8, MATCH_KSLL8, MASK_KSLL8) +DECLARE_INSN(kslli8, MATCH_KSLLI8, MASK_KSLLI8) +DECLARE_INSN(ksll16, MATCH_KSLL16, MASK_KSLL16) +DECLARE_INSN(kslli16, MATCH_KSLLI16, MASK_KSLLI16) +DECLARE_INSN(kslra8, MATCH_KSLRA8, MASK_KSLRA8) +DECLARE_INSN(kslra8_u, MATCH_KSLRA8_U, MASK_KSLRA8_U) +DECLARE_INSN(kslra16, MATCH_KSLRA16, MASK_KSLRA16) +DECLARE_INSN(kslra16_u, MATCH_KSLRA16_U, MASK_KSLRA16_U) +DECLARE_INSN(kslraw, MATCH_KSLRAW, MASK_KSLRAW) +DECLARE_INSN(kslraw_u, MATCH_KSLRAW_U, MASK_KSLRAW_U) +DECLARE_INSN(kstas16, MATCH_KSTAS16, MASK_KSTAS16) +DECLARE_INSN(kstsa16, MATCH_KSTSA16, MASK_KSTSA16) +DECLARE_INSN(ksub8, MATCH_KSUB8, MASK_KSUB8) +DECLARE_INSN(ksub16, MATCH_KSUB16, MASK_KSUB16) +DECLARE_INSN(ksub64, MATCH_KSUB64, MASK_KSUB64) +DECLARE_INSN(ksubh, MATCH_KSUBH, MASK_KSUBH) +DECLARE_INSN(ksubw, MATCH_KSUBW, MASK_KSUBW) +DECLARE_INSN(kwmmul, MATCH_KWMMUL, MASK_KWMMUL) +DECLARE_INSN(kwmmul_u, MATCH_KWMMUL_U, MASK_KWMMUL_U) +DECLARE_INSN(maddr32, MATCH_MADDR32, MASK_MADDR32) +DECLARE_INSN(msubr32, MATCH_MSUBR32, MASK_MSUBR32) +DECLARE_INSN(mulr64, MATCH_MULR64, MASK_MULR64) +DECLARE_INSN(mulsr64, MATCH_MULSR64, MASK_MULSR64) +DECLARE_INSN(pbsad, MATCH_PBSAD, MASK_PBSAD) +DECLARE_INSN(pbsada, MATCH_PBSADA, MASK_PBSADA) +DECLARE_INSN(pkbb16, MATCH_PKBB16, MASK_PKBB16) +DECLARE_INSN(pkbt16, MATCH_PKBT16, MASK_PKBT16) +DECLARE_INSN(pktt, MATCH_PKTT16, MASK_PKTT16) +DECLARE_INSN(pktb16, MATCH_PKTB16, MASK_PKTB16) +DECLARE_INSN(radd8, MATCH_RADD8, MASK_RADD8) +DECLARE_INSN(radd16, MATCH_RADD16, MASK_RADD16) +DECLARE_INSN(radd64, MATCH_RADD64, MASK_RADD64) +DECLARE_INSN(raddw, MATCH_RADDW, MASK_RADDW) +DECLARE_INSN(rcras16, MATCH_RCRAS16, MASK_RCRAS16) +DECLARE_INSN(rcrsa16, MATCH_RCRSA16, MASK_RCRSA16) +DECLARE_INSN(rstas16, MATCH_RSTAS16, MASK_RSTAS16) +DECLARE_INSN(rstsa16, MATCH_RSTSA16, MASK_RSTSA16) +DECLARE_INSN(rsub8, MATCH_RSUB8, MASK_RSUB8) +DECLARE_INSN(rsub16, MATCH_RSUB16, MASK_RSUB16) +DECLARE_INSN(rsub64, MATCH_RSUB64, MASK_RSUB64) +DECLARE_INSN(rsubw, MATCH_RSUBW, MASK_RSUBW) +DECLARE_INSN(sclip8, MATCH_SCLIP8, MASK_SCLIP8) +DECLARE_INSN(sclip16, MATCH_SCLIP16, MASK_SCLIP16) +DECLARE_INSN(sclip32, MATCH_SCLIP32, MASK_SCLIP32) +DECLARE_INSN(scmple8, MATCH_SCMPLE8, MASK_SCMPLE8) +DECLARE_INSN(scmple16, MATCH_SCMPLE16, MASK_SCMPLE16) +DECLARE_INSN(scmplt8, MATCH_SCMPLT8, MASK_SCMPLT8) +DECLARE_INSN(scmplt16, MATCH_SCMPLT16, MASK_SCMPLT16) +DECLARE_INSN(sll8, MATCH_SLL8, MASK_SLL8) +DECLARE_INSN(slli8, MATCH_SLLI8, MASK_SLLI8) +DECLARE_INSN(sll16, MATCH_SLL16, MASK_SLL16) +DECLARE_INSN(slli16, MATCH_SLLI16, MASK_SLLI16) +DECLARE_INSN(smal, MATCH_SMAL, MASK_SMAL) +DECLARE_INSN(smalbb, MATCH_SMALBB, MASK_SMALBB) +DECLARE_INSN(smalbt, MATCH_SMALBT, MASK_SMALBT) +DECLARE_INSN(smaltt, MATCH_SMALTT, MASK_SMALTT) +DECLARE_INSN(smalda, MATCH_SMALDA, MASK_SMALDA) +DECLARE_INSN(smalxda, MATCH_SMALXDA, MASK_SMALXDA) +DECLARE_INSN(smalds, MATCH_SMALDS, MASK_SMALDS) +DECLARE_INSN(smaldrs, MATCH_SMALDRS, MASK_SMALDRS) +DECLARE_INSN(smalxds, MATCH_SMALXDS, MASK_SMALXDS) +DECLARE_INSN(smar64, MATCH_SMAR64, MASK_SMAR64) +DECLARE_INSN(smaqa, MATCH_SMAQA, MASK_SMAQA) +DECLARE_INSN(smaqa_su, MATCH_SMAQA_SU, MASK_SMAQA_SU) +DECLARE_INSN(smax8, MATCH_SMAX8, MASK_SMAX8) +DECLARE_INSN(smax16, MATCH_SMAX16, MASK_SMAX16) +DECLARE_INSN(smbb16, MATCH_SMBB16, MASK_SMBB16) +DECLARE_INSN(smbt16, MATCH_SMBT16, MASK_SMBT16) +DECLARE_INSN(smtt16, MATCH_SMTT16, MASK_SMTT16) +DECLARE_INSN(smds, MATCH_SMDS, MASK_SMDS) +DECLARE_INSN(smdrs, MATCH_SMDRS, MASK_SMDRS) +DECLARE_INSN(smxds, MATCH_SMXDS, MASK_SMXDS) +DECLARE_INSN(smin8, MATCH_SMIN8, MASK_SMIN8) +DECLARE_INSN(smin16, MATCH_SMIN16, MASK_SMIN16) +DECLARE_INSN(smmul, MATCH_SMMUL, MASK_SMMUL) +DECLARE_INSN(smmul_u, MATCH_SMMUL_U, MASK_SMMUL_U) +DECLARE_INSN(smmwb, MATCH_SMMWB, MASK_SMMWB) +DECLARE_INSN(smmwb_u, MATCH_SMMWB_U, MASK_SMMWB_U) +DECLARE_INSN(smmwt, MATCH_SMMWT, MASK_SMMWT) +DECLARE_INSN(smmwt_u, MATCH_SMMWT_U, MASK_SMMWT_U) +DECLARE_INSN(smslds, MATCH_SMSLDA, MASK_SMSLDA) +DECLARE_INSN(smslxda, MATCH_SMSLXDA, MASK_SMSLXDA) +DECLARE_INSN(smsr64, MATCH_SMSR64, MASK_SMSR64) +DECLARE_INSN(smul8, MATCH_SMUL8, MASK_SMUL8) +DECLARE_INSN(smulx8, MATCH_SMULX8, MASK_SMULX8) +DECLARE_INSN(smul16, MATCH_SMUL16, MASK_SMUL16) +DECLARE_INSN(smulx16, MATCH_SMULX16, MASK_SMULX16) +DECLARE_INSN(sra_u, MATCH_SRA_U, MASK_SRA_U) +DECLARE_INSN(srai_u, MATCH_SRAI_U, MASK_SRAI_U) +DECLARE_INSN(sra8, MATCH_SRA8, MASK_SRA8) +DECLARE_INSN(sra8_u, MATCH_SRA8_U, MASK_SRA8_U) +DECLARE_INSN(srai8, MATCH_SRAI8, MASK_SRAI8) +DECLARE_INSN(srai8_u, MATCH_SRAI8_U, MASK_SRAI8_U) +DECLARE_INSN(sra16, MATCH_SRA16, MASK_SRA16) +DECLARE_INSN(sra16_u, MATCH_SRA16_U, MASK_SRA16_U) +DECLARE_INSN(srai16, MATCH_SRAI16, MASK_SRAI16) +DECLARE_INSN(srai16_u, MATCH_SRAI16_U, MASK_SRAI16_U) +DECLARE_INSN(srl8, MATCH_SRL8, MASK_SRL8) +DECLARE_INSN(srl8_u, MATCH_SRL8_U, MASK_SRL8_U) +DECLARE_INSN(srli8, MATCH_SRLI8, MASK_SRLI8) +DECLARE_INSN(srli8_u, MATCH_SRLI8_U, MASK_SRLI8_U) +DECLARE_INSN(srl16, MATCH_SRL16, MASK_SRL16) +DECLARE_INSN(srl16_u, MATCH_SRL16_U, MASK_SRL16_U) +DECLARE_INSN(srli16, MATCH_SRLI16, MASK_SRLI16) +DECLARE_INSN(srli16_u, MATCH_SRLI16_U, MASK_SRLI16_U) +DECLARE_INSN(stas16, MATCH_STAS16, MASK_STAS16) +DECLARE_INSN(stsa16, MATCH_STSA16, MASK_STSA16) +DECLARE_INSN(sub8, MATCH_SUB8, MASK_SUB8) +DECLARE_INSN(sub16, MATCH_SUB16, MASK_SUB16) +DECLARE_INSN(sub64, MATCH_SUB64, MASK_SUB64) +DECLARE_INSN(sunpkd810, MATCH_SUNPKD810, MASK_SUNPKD810) +DECLARE_INSN(sunpkd820, MATCH_SUNPKD820, MASK_SUNPKD820) +DECLARE_INSN(sunpkd830, MATCH_SUNPKD830, MASK_SUNPKD830) +DECLARE_INSN(sunpkd831, MATCH_SUNPKD831, MASK_SUNPKD831) +DECLARE_INSN(sunpkd832, MATCH_SUNPKD832, MASK_SUNPKD832) +DECLARE_INSN(swap8, MATCH_SWAP8, MASK_SWAP8) +DECLARE_INSN(uclip8, MATCH_UCLIP8, MASK_UCLIP8) +DECLARE_INSN(uclip16, MATCH_UCLIP16, MASK_UCLIP16) +DECLARE_INSN(uclip32, MATCH_UCLIP32, MASK_UCLIP32) +DECLARE_INSN(ucmple8, MATCH_UCMPLE8, MASK_UCMPLE8) +DECLARE_INSN(ucmple16, MATCH_UCMPLE16, MASK_UCMPLE16) +DECLARE_INSN(ucmplt8, MATCH_UCMPLT8, MASK_UCMPLT8) +DECLARE_INSN(ucmplt16, MATCH_UCMPLT16, MASK_UCMPLT16) +DECLARE_INSN(ukadd8, MATCH_UKADD8, MASK_UKADD8) +DECLARE_INSN(ukadd16, MATCH_UKADD16, MASK_UKADD16) +DECLARE_INSN(ukadd64, MATCH_UKADD64, MASK_UKADD64) +DECLARE_INSN(ukaddh, MATCH_UKADDH, MASK_UKADDH) +DECLARE_INSN(ukaddw, MATCH_UKADDW, MASK_UKADDW) +DECLARE_INSN(ukcras16, MATCH_UKCRAS16, MASK_UKCRAS16) +DECLARE_INSN(ukcrsa16, MATCH_UKCRSA16, MASK_UKCRSA16) +DECLARE_INSN(ukmar64, MATCH_UKMAR64, MASK_UKMAR64) +DECLARE_INSN(ukmsr64, MATCH_UKMSR64, MASK_UKMSR64) +DECLARE_INSN(ukstas16, MATCH_UKSTAS16, MASK_UKSTAS16) +DECLARE_INSN(ukstsa16, MATCH_UKSTSA16, MASK_UKSTSA16) +DECLARE_INSN(uksub8, MATCH_UKSUB8, MASK_UKSUB8) +DECLARE_INSN(uksub16, MATCH_UKSUB16, MASK_UKSUB16) +DECLARE_INSN(uksub64, MATCH_UKSUB64, MASK_UKSUB64) +DECLARE_INSN(uksubh, MATCH_UKSUBH, MASK_UKSUBH) +DECLARE_INSN(uksubw, MATCH_UKSUBW, MASK_UKSUBW) +DECLARE_INSN(umar64, MATCH_UMAR64, MASK_UMAR64) +DECLARE_INSN(umaqa, MATCH_UMAQA, MASK_UMAQA) +DECLARE_INSN(umax8, MATCH_UMAX8, MASK_UMAX8) +DECLARE_INSN(umax16, MATCH_UMAX16, MASK_UMAX16) +DECLARE_INSN(umin8, MATCH_UMIN8, MASK_UMIN8) +DECLARE_INSN(umin16, MATCH_UMIN16, MASK_UMIN16) +DECLARE_INSN(umsr64, MATCH_UMSR64, MASK_UMSR64) +DECLARE_INSN(umul8, MATCH_UMUL8, MASK_UMUL8) +DECLARE_INSN(umulx8, MATCH_UMULX8, MASK_UMULX8) +DECLARE_INSN(umul16, MATCH_UMUL16, MASK_UMUL16) +DECLARE_INSN(umulx16, MATCH_UMULX16, MASK_UMULX16) +DECLARE_INSN(uradd8, MATCH_URADD8, MASK_URADD8) +DECLARE_INSN(uradd16, MATCH_URADD16, MASK_URADD16) +DECLARE_INSN(uradd64, MATCH_URADD64, MASK_URADD64) +DECLARE_INSN(uraddw, MATCH_URADDW, MASK_URADDW) +DECLARE_INSN(urcras16, MATCH_URCRAS16, MASK_URCRAS16) +DECLARE_INSN(urcrsa16, MATCH_URCRSA16, MASK_URCRSA16) +DECLARE_INSN(urstas16, MATCH_URSTAS16, MASK_URSTAS16) +DECLARE_INSN(urstsa16, MATCH_URSTSA16, MASK_URSTSA16) +DECLARE_INSN(ursub8, MATCH_URSUB8, MASK_URSUB8) +DECLARE_INSN(ursub16, MATCH_URSUB16, MASK_URSUB16) +DECLARE_INSN(ursub64, MATCH_URSUB64, MASK_URSUB64) +DECLARE_INSN(ursubw, MATCH_URSUBW, MASK_URSUBW) +DECLARE_INSN(wexti, MATCH_WEXTI, MASK_WEXTI) +DECLARE_INSN(wext, MATCH_WEXT, MASK_WEXT) +DECLARE_INSN(zunpkd810, MATCH_ZUNPKD810, MASK_ZUNPKD810) +DECLARE_INSN(zunpkd820, MATCH_ZUNPKD820, MASK_ZUNPKD820) +DECLARE_INSN(zunpkd830, MATCH_ZUNPKD830, MASK_ZUNPKD830) +DECLARE_INSN(zunpkd831, MATCH_ZUNPKD831, MASK_ZUNPKD831) +DECLARE_INSN(zunpkd832, MATCH_ZUNPKD832, MASK_ZUNPKD832) +DECLARE_INSN(add32, MATCH_ADD32, MASK_ADD32) +DECLARE_INSN(cras32, MATCH_CRAS32, MASK_CRAS32) +DECLARE_INSN(crsa32, MATCH_CRSA32, MASK_CRSA32) +DECLARE_INSN(kabs32, MATCH_KABS32, MASK_KABS32) +DECLARE_INSN(kadd32, MATCH_KADD32, MASK_KADD32) +DECLARE_INSN(kcras32, MATCH_KCRAS32, MASK_KCRAS32) +DECLARE_INSN(kcrsa32, MATCH_KCRSA32, MASK_KCRSA32) +DECLARE_INSN(kdmbb16, MATCH_KDMBB16, MASK_KDMBB16) +DECLARE_INSN(kdmbt16, MATCH_KDMBT16, MASK_KDMBT16) +DECLARE_INSN(kdmtt16, MATCH_KDMTT16, MASK_KDMTT16) +DECLARE_INSN(kdmabb16, MATCH_KDMABB16, MASK_KDMABB16) +DECLARE_INSN(kdmabt16, MATCH_KDMABT16, MASK_KDMABT16) +DECLARE_INSN(kdmatt16, MATCH_KDMATT16, MASK_KDMATT16) +DECLARE_INSN(khmbb16, MATCH_KHMBB16, MASK_KHMBB16) +DECLARE_INSN(khmbt16, MATCH_KHMBT16, MASK_KHMBT16) +DECLARE_INSN(khmtt16, MATCH_KHMTT16, MASK_KHMTT16) +DECLARE_INSN(kmabb32, MATCH_KMABB32, MASK_KMABB32) +DECLARE_INSN(kmabt32, MATCH_KMABT32, MASK_KMABT32) +DECLARE_INSN(kmatt32, MATCH_KMATT32, MASK_KMATT32) +DECLARE_INSN(kmaxda32, MATCH_KMAXDA32, MASK_KMAXDA32) +DECLARE_INSN(kmds32, MATCH_KMDA32, MASK_KMDA32) +DECLARE_INSN(kmxda32, MATCH_KMXDA32, MASK_KMXDA32) +DECLARE_INSN(kmads32, MATCH_KMADS32, MASK_KMADS32) +DECLARE_INSN(kmadrs32, MATCH_KMADRS32, MASK_KMADRS32) +DECLARE_INSN(kmaxds32, MATCH_KMAXDS32, MASK_KMAXDS32) +DECLARE_INSN(kmsda32, MATCH_KMSDA32, MASK_KMSDA32) +DECLARE_INSN(kmsxda32, MATCH_KMSXDA32, MASK_KMSXDA32) +DECLARE_INSN(ksll32, MATCH_KSLL32, MASK_KSLL32) +DECLARE_INSN(kslli32, MATCH_KSLLI32, MASK_KSLLI32) +DECLARE_INSN(kslra32, MATCH_KSLRA32, MASK_KSLRA32) +DECLARE_INSN(kslra32_u, MATCH_KSLRA32_U, MASK_KSLRA32_U) +DECLARE_INSN(kstas32, MATCH_KSTAS32, MASK_KSTAS32) +DECLARE_INSN(kstsa32, MATCH_KSTSA32, MASK_KSTSA32) +DECLARE_INSN(ksub32, MATCH_KSUB32, MASK_KSUB32) +DECLARE_INSN(pkbb32, MATCH_PKBB32, MASK_PKBB32) +DECLARE_INSN(pkbt32, MATCH_PKBT32, MASK_PKBT32) +DECLARE_INSN(pktt32, MATCH_PKTT32, MASK_PKTT32) +DECLARE_INSN(pktb32, MATCH_PKTB32, MASK_PKTB32) +DECLARE_INSN(radd32, MATCH_RADD32, MASK_RADD32) +DECLARE_INSN(rcras32, MATCH_RCRAS32, MASK_RCRAS32) +DECLARE_INSN(rcrsa32, MATCH_RCRSA32, MASK_RCRSA32) +DECLARE_INSN(rstas32, MATCH_RSTAS32, MASK_RSTAS32) +DECLARE_INSN(rstsa32, MATCH_RSTSA32, MASK_RSTSA32) +DECLARE_INSN(rsub32, MATCH_RSUB32, MASK_RSUB32) +DECLARE_INSN(sll32, MATCH_SLL32, MASK_SLL32) +DECLARE_INSN(slli32, MATCH_SLLI32, MASK_SLLI32) +DECLARE_INSN(smax32, MATCH_SMAX32, MASK_SMAX32) +DECLARE_INSN(smbt32, MATCH_SMBT32, MASK_SMBT32) +DECLARE_INSN(smtt32, MATCH_SMTT32, MASK_SMTT32) +DECLARE_INSN(smds32, MATCH_SMDS32, MASK_SMDS32) +DECLARE_INSN(smdrs32, MATCH_SMDRS32, MASK_SMDRS32) +DECLARE_INSN(smxds32, MATCH_SMXDS32, MASK_SMXDS32) +DECLARE_INSN(smin32, MATCH_SMIN32, MASK_SMIN32) +DECLARE_INSN(sra32, MATCH_SRA32, MASK_SRA32) +DECLARE_INSN(sra32_u, MATCH_SRA32_U, MASK_SRA32_U) +DECLARE_INSN(srai32, MATCH_SRAI32, MASK_SRAI32) +DECLARE_INSN(srai32_u, MATCH_SRAI32_U, MASK_SRAI32_U) +DECLARE_INSN(sraiw_u, MATCH_SRAIW_U, MASK_SRAIW_U) +DECLARE_INSN(srl32, MATCH_SRL32, MASK_SRL32) +DECLARE_INSN(srl32_u, MATCH_SRL32_U, MASK_SRL32_U) +DECLARE_INSN(srli32, MATCH_SRLI32, MASK_SRLI32) +DECLARE_INSN(srli32_u, MATCH_SRLI32_U, MASK_SRLI32_U) +DECLARE_INSN(stas32, MATCH_STAS32, MASK_STAS32) +DECLARE_INSN(stsa32, MATCH_STSA32, MASK_STSA32) +DECLARE_INSN(sub32, MATCH_SUB32, MASK_SUB32) +DECLARE_INSN(ukadd32, MATCH_UKADD32, MASK_UKADD32) +DECLARE_INSN(ukcras32, MATCH_UKCRAS32, MASK_UKCRAS32) +DECLARE_INSN(ukcrsa32, MATCH_UKCRSA32, MASK_UKCRSA32) +DECLARE_INSN(ukstas32, MATCH_UKSTAS32, MASK_UKSTAS32) +DECLARE_INSN(ukstsa32, MATCH_UKSTSA32, MASK_UKSTSA32) +DECLARE_INSN(uksub32, MATCH_UKSUB32, MASK_UKSUB32) +DECLARE_INSN(umax32, MATCH_UMAX32, MASK_UMAX32) +DECLARE_INSN(umin32, MATCH_UMIN32, MASK_UMIN32) +DECLARE_INSN(uradd32, MATCH_URADD32, MASK_URADD32) +DECLARE_INSN(urcras32, MATCH_URCRAS32, MASK_URCRAS32) +DECLARE_INSN(urcrsa32, MATCH_URCRSA32, MASK_URCRSA32) +DECLARE_INSN(urstas32, MATCH_URSTAS32, MASK_URSTAS32) +DECLARE_INSN(urstsa32, MATCH_URSTSA32, MASK_URSTSA32) +DECLARE_INSN(ursub32, MATCH_URSUB32, MASK_URSUB32) +DECLARE_INSN(cmix, MATCH_CMIX, MASK_CMIX) +DECLARE_INSN(fsr, MATCH_FSR, MASK_FSR) +DECLARE_INSN(fsri, MATCH_FSRI, MASK_FSRI) +DECLARE_INSN(fsrw, MATCH_FSRW, MASK_FSRW) +DECLARE_INSN(pack, MATCH_PACK, MASK_PACK) +DECLARE_INSN(packu, MATCH_PACKU, MASK_PACKU) #endif /* DECLARE_INSN */ #ifdef DECLARE_CSR /* Privileged CSRs. */ @@ -1412,6 +2393,7 @@ DECLARE_CSR(tinfo, CSR_TINFO, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_C DECLARE_CSR(tcontrol, CSR_TCONTROL, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) DECLARE_CSR(mcontext, CSR_MCONTEXT, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) DECLARE_CSR(scontext, CSR_SCONTEXT, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(vxsat, CSR_VXSAT, CSR_CLASS_P, ISA_SPEC_CLASS_DRAFT, PRIV_SPEC_CLASS_DRAFT) #endif /* DECLARE_CSR */ #ifdef DECLARE_CSR_ALIAS DECLARE_CSR_ALIAS(ubadaddr, CSR_UTVAL, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10) diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index fdf3df4f5c1f..45b6e21933db 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -63,6 +63,8 @@ static const char * const riscv_pred_succ[16] = #define EXTRACT_ITYPE_IMM(x) \ (RV_X(x, 20, 12) | (RV_IMM_SIGN(x) << 12)) +#define EXTRACT_ITYPE_IMM6L(x) \ + (RV_X(x, 20, 6)) #define EXTRACT_STYPE_IMM(x) \ (RV_X(x, 7, 5) | (RV_X(x, 25, 7) << 5) | (RV_IMM_SIGN(x) << 12)) #define EXTRACT_BTYPE_IMM(x) \ @@ -101,6 +103,14 @@ static const char * const riscv_pred_succ[16] = ((RV_X(x, 3, 2) << 1) | (RV_X(x, 10, 2) << 3) | (RV_X(x, 2, 1) << 5) | (RV_X(x, 5, 2) << 6) | (-RV_X(x, 12, 1) << 8)) #define EXTRACT_CJTYPE_IMM(x) \ ((RV_X(x, 3, 3) << 1) | (RV_X(x, 11, 1) << 4) | (RV_X(x, 2, 1) << 5) | (RV_X(x, 7, 1) << 6) | (RV_X(x, 6, 1) << 7) | (RV_X(x, 9, 2) << 8) | (RV_X(x, 8, 1) << 10) | (-RV_X(x, 12, 1) << 11)) +#define EXTRACT_PTYPE_IMM3U(x) \ + (RV_X(x, 20, 3)) +#define EXTRACT_PTYPE_IMM4U(x) \ + (RV_X(x, 20, 4)) +#define EXTRACT_PTYPE_IMM5U(x) \ + (RV_X(x, 20, 5)) +#define EXTRACT_PTYPE_IMM6U(x) \ + (RV_X(x, 20, 6)) #define ENCODE_ITYPE_IMM(x) \ (RV_X(x, 0, 12) << 20) @@ -142,6 +152,16 @@ static const char * const riscv_pred_succ[16] = ((RV_X(x, 1, 2) << 3) | (RV_X(x, 3, 2) << 10) | (RV_X(x, 5, 1) << 2) | (RV_X(x, 6, 2) << 5) | (RV_X(x, 8, 1) << 12)) #define ENCODE_CJTYPE_IMM(x) \ ((RV_X(x, 1, 3) << 3) | (RV_X(x, 4, 1) << 11) | (RV_X(x, 5, 1) << 2) | (RV_X(x, 6, 1) << 7) | (RV_X(x, 7, 1) << 6) | (RV_X(x, 8, 2) << 9) | (RV_X(x, 10, 1) << 8) | (RV_X(x, 11, 1) << 12)) +#define ENCODE_PTYPE_IMM3U(x) \ + (RV_X(x, 0, 3) << 20) +#define ENCODE_PTYPE_IMM4U(x) \ + (RV_X(x, 0, 4) << 20) +#define ENCODE_PTYPE_IMM5U(x) \ + (RV_X(x, 0, 5) << 20) +#define ENCODE_PTYPE_IMM6U(x) \ + (RV_X(x, 0, 6) << 20) +#define ENCODE_ITYPE_IMM6L(x) \ + (RV_X(x, 0, 6) << 20) #define VALID_ITYPE_IMM(x) (EXTRACT_ITYPE_IMM(ENCODE_ITYPE_IMM(x)) == (x)) #define VALID_STYPE_IMM(x) (EXTRACT_STYPE_IMM(ENCODE_STYPE_IMM(x)) == (x)) @@ -165,6 +185,10 @@ static const char * const riscv_pred_succ[16] = #define VALID_CLTYPE_LD_IMM(x) (EXTRACT_CLTYPE_LD_IMM(ENCODE_CLTYPE_LD_IMM(x)) == (x)) #define VALID_CBTYPE_IMM(x) (EXTRACT_CBTYPE_IMM(ENCODE_CBTYPE_IMM(x)) == (x)) #define VALID_CJTYPE_IMM(x) (EXTRACT_CJTYPE_IMM(ENCODE_CJTYPE_IMM(x)) == (x)) +#define VALID_PTYPE_IMM3U(x) (EXTRACT_PTYPE_IMM3U(ENCODE_PTYPE_IMM3U(x)) == (x)) +#define VALID_PTYPE_IMM4U(x) (EXTRACT_PTYPE_IMM4U(ENCODE_PTYPE_IMM4U(x)) == (x)) +#define VALID_PTYPE_IMM5U(x) (EXTRACT_PTYPE_IMM5U(ENCODE_PTYPE_IMM5U(x)) == (x)) +#define VALID_PTYPE_IMM6U(x) (EXTRACT_PTYPE_IMM6U(ENCODE_PTYPE_IMM6U(x)) == (x)) #define RISCV_RTYPE(insn, rd, rs1, rs2) \ ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ((rs1) << OP_SH_RS1) | ((rs2) << OP_SH_RS2)) @@ -319,6 +343,9 @@ enum riscv_insn_class INSN_CLASS_ZBA, INSN_CLASS_ZBB, INSN_CLASS_ZBC, + INSN_CLASS_ZPN, + INSN_CLASS_ZPSF, + INSN_CLASS_ZBPBO, }; /* This structure holds information for a particular instruction. */ diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c index cc80d909457e..0f7b82d7b3f5 100644 --- a/opcodes/riscv-dis.c +++ b/opcodes/riscv-dis.c @@ -164,6 +164,29 @@ maybe_print_address (struct riscv_private_data *pd, int base_reg, int offset) pd->print_addr = offset; } +#define RVP_MAX_KEYWORD_LEN 32 + +static bfd_boolean +parse_rvp_field (const char **str, char name[RVP_MAX_KEYWORD_LEN]) +{ + char *p = name; + const char *str_t; + + str_t = *str; + str_t--; + while (isalnum (*str_t) || *str_t == '.' || *str_t == '_') + *p++ = *str_t++; + *p = '\0'; + + if (strncmp (name, "nds_", 4) == 0) + { + *str = str_t; + return TRUE; + } + else + return FALSE; +} + /* Print insn arguments for 32/64-bit code. */ static void @@ -275,6 +298,7 @@ print_insn_args (const char *d, insn_t l, bfd_vma pc, disassemble_info *info) print (info->stream, "0"); break; + case 'g': case 'b': case 's': if ((l & MASK_JALR) == MATCH_JALR) @@ -287,6 +311,11 @@ print_insn_args (const char *d, insn_t l, bfd_vma pc, disassemble_info *info) riscv_gpr_names[EXTRACT_OPERAND (RS2, l)]); break; + case 'r': + print (info->stream, "%s", + riscv_gpr_names[EXTRACT_OPERAND (RS3, l)]); + break; + case 'u': print (info->stream, "0x%x", (unsigned)EXTRACT_UTYPE_IMM (l) >> RISCV_IMM_BITS); @@ -297,6 +326,10 @@ print_insn_args (const char *d, insn_t l, bfd_vma pc, disassemble_info *info) riscv_rm, ARRAY_SIZE (riscv_rm)); break; + case 'l': + print (info->stream, "%d", (int)EXTRACT_ITYPE_IMM6L (l)); + break; + case 'P': arg_print (info, EXTRACT_OPERAND (PRED, l), riscv_pred_succ, ARRAY_SIZE (riscv_pred_succ)); @@ -306,6 +339,36 @@ print_insn_args (const char *d, insn_t l, bfd_vma pc, disassemble_info *info) arg_print (info, EXTRACT_OPERAND (SUCC, l), riscv_pred_succ, ARRAY_SIZE (riscv_pred_succ)); break; + + case 'n': + { + d++; + char field_name[RVP_MAX_KEYWORD_LEN]; + if (parse_rvp_field (&d, field_name)) + { + if (strcmp (field_name, "nds_rdp") == 0) + print (info->stream, "%s", riscv_gpr_names[rd]); + else if (strcmp (field_name, "nds_rsp") == 0) + print (info->stream, "%s", riscv_gpr_names[rs1]); + else if (strcmp (field_name, "nds_rtp") == 0) + print (info->stream, "%s", + riscv_gpr_names[EXTRACT_OPERAND (RS2, l)]); + else if (strcmp (field_name, "nds_i3u") == 0) + print (info->stream, "%d", (int)EXTRACT_PTYPE_IMM3U (l)); + else if (strcmp (field_name, "nds_i4u") == 0) + print (info->stream, "%d", (int)EXTRACT_PTYPE_IMM4U (l)); + else if (strcmp (field_name, "nds_i5u") == 0) + print (info->stream, "%d", (int)EXTRACT_PTYPE_IMM5U (l)); + else if (strcmp (field_name, "nds_i6u") == 0) + print (info->stream, "%d", (int)EXTRACT_PTYPE_IMM6U (l)); + else + print (info->stream, + _("# internal error, undefined nds v5 field (%s)"), + field_name); + } + d--; + } + break; case 'o': maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l)); diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 4d83d787c375..860c353cee44 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -84,7 +84,13 @@ const char * const riscv_fpr_names_abi[NFPR] = #define MASK_SHAMT (OP_MASK_SHAMT << OP_SH_SHAMT) #define MATCH_SHAMT_REV8_32 (0b11000 << OP_SH_SHAMT) #define MATCH_SHAMT_REV8_64 (0b111000 << OP_SH_SHAMT) +#define MATCH_SHAMT_REV_32 (0b11111 << 20) +#define MATCH_SHAMT_REV_64 (0b111111 << 20) +#define MATCH_SHAMT_REV8_H (0b1000 << 20) #define MATCH_SHAMT_ORC_B (0b00111 << OP_SH_SHAMT) +#define MATCH_CLROV (MATCH_CSRRCI | (CSR_VXSAT << OP_SH_CSR) | (1 << OP_SH_RS1)) +#define MATCH_RDOV (MATCH_CSRRS|(CSR_VXSAT << OP_SH_CSR)) +#define MASK_RDOV (0xffffffffU ^ MASK_RD) static int match_opcode (const struct riscv_opcode *op, insn_t insn) @@ -783,11 +789,14 @@ const struct riscv_opcode riscv_opcodes[] = {"wfi", 0, INSN_CLASS_I, "", MATCH_WFI, MASK_WFI, match_opcode, 0 }, /* RVB instructions. */ +{"clz", 0, INSN_CLASS_ZBPBO,"d,s", MATCH_CLZ, MASK_CLZ, match_opcode, 0 }, {"clz", 0, INSN_CLASS_ZBB, "d,s", MATCH_CLZ, MASK_CLZ, match_opcode, 0 }, {"ctz", 0, INSN_CLASS_ZBB, "d,s", MATCH_CTZ, MASK_CTZ, match_opcode, 0 }, {"cpop", 0, INSN_CLASS_ZBB, "d,s", MATCH_CPOP, MASK_CPOP, match_opcode, 0 }, {"min", 0, INSN_CLASS_ZBB, "d,s,t", MATCH_MIN, MASK_MIN, match_opcode, 0 }, +{"min", 0, INSN_CLASS_ZBPBO, "d,s,t", MATCH_MIN, MASK_MIN, match_opcode, 0 }, {"max", 0, INSN_CLASS_ZBB, "d,s,t", MATCH_MAX, MASK_MAX, match_opcode, 0 }, +{"max", 0, INSN_CLASS_ZBPBO, "d,s,t", MATCH_MAX, MASK_MAX, match_opcode, 0 }, {"minu", 0, INSN_CLASS_ZBB, "d,s,t", MATCH_MINU, MASK_MINU, match_opcode, 0 }, {"maxu", 0, INSN_CLASS_ZBB, "d,s,t", MATCH_MAXU, MASK_MAXU, match_opcode, 0 }, {"sext.b", 0, INSN_CLASS_ZBB, "d,s", MATCH_SEXT_B, MASK_SEXT_B, match_opcode, 0 }, @@ -827,7 +836,348 @@ const struct riscv_opcode riscv_opcodes[] = {"clmul", 0, INSN_CLASS_ZBC, "d,s,t", MATCH_CLMUL, MASK_CLMUL, match_opcode, 0 }, {"clmulh", 0, INSN_CLASS_ZBC, "d,s,t", MATCH_CLMULH, MASK_CLMULH, match_opcode, 0 }, {"clmulr", 0, INSN_CLASS_ZBC, "d,s,t", MATCH_CLMULR, MASK_CLMULR, match_opcode, 0 }, +{"cmix", 0, INSN_CLASS_ZBPBO, "d,t,s,r", MATCH_CMIX, MASK_CMIX, match_opcode, 0 }, +{"rev8.h", 0, INSN_CLASS_ZBPBO, "d,s", MATCH_GREVI|MATCH_SHAMT_REV8_H, MASK_GREVI|(OP_MASK_SHAMT << 20), match_opcode, 0 }, +{"rev", 32, INSN_CLASS_ZBPBO, "d,s", MATCH_GREVI|MATCH_SHAMT_REV_32, MASK_GREVI|(OP_MASK_SHAMT << 20), match_opcode, 0 }, +{"rev", 64, INSN_CLASS_ZBPBO, "d,s", MATCH_GREVI|MATCH_SHAMT_REV_64, MASK_GREVI|(OP_MASK_SHAMT << 20), match_opcode, 0 }, +{"packu", 0, INSN_CLASS_ZBPBO, "d,s,t", MATCH_PACKU, MASK_PACKU, match_opcode, 0 }, +{"pack", 0, INSN_CLASS_ZBPBO, "d,s,t", MATCH_PACK, MASK_PACK, match_opcode, 0 }, +{"fsr", 32, INSN_CLASS_ZBPBO, "d,s,r,t", MATCH_FSR, MASK_FSR, match_opcode, 0 }, +{"fsri", 32, INSN_CLASS_ZBPBO, "d,s,r,>", MATCH_FSRI, MASK_FSRI, match_opcode, 0 }, +{"fsrw", 64, INSN_CLASS_ZBPBO, "d,s,r,t", MATCH_FSRW, MASK_FSRW, match_opcode, 0 }, +/* RVP instructions */ +{"add8", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_ADD8, MASK_ADD8, match_opcode, 0 }, +{"add16", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_ADD16, MASK_ADD16, match_opcode, 0 }, +{"add64", 32, INSN_CLASS_ZPSF, "nds_rdp,nds_rsp,nds_rtp", MATCH_ADD64, MASK_ADD64, match_opcode, 0 }, +{"ave", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_AVE, MASK_AVE, match_opcode, 0 }, +{"bitrev", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_BITREV, MASK_BITREV, match_opcode, 0 }, +{"bitrevi", 0, INSN_CLASS_ZPN, "d,s,l", MATCH_BITREVI, MASK_BITREVI, match_opcode, 0 }, +{"clrs8", 0, INSN_CLASS_ZPN, "d,s", MATCH_CLRS8, MASK_CLRS8, match_opcode, 0 }, +{"clrs16", 0, INSN_CLASS_ZPN, "d,s", MATCH_CLRS16, MASK_CLRS16, match_opcode, 0 }, +{"clrs32", 0, INSN_CLASS_ZPN, "d,s", MATCH_CLRS32, MASK_CLRS32, match_opcode, 0 }, +{"clz8", 0, INSN_CLASS_ZPN, "d,s", MATCH_CLZ8, MASK_CLZ8, match_opcode, 0 }, +{"clz16", 0, INSN_CLASS_ZPN, "d,s", MATCH_CLZ16, MASK_CLZ16, match_opcode, 0 }, +{"clz32", 32,INSN_CLASS_ZBPBO, "d,s", MATCH_CLZ, MASK_CLZ, match_opcode, INSN_ALIAS }, +{"clz32", 0, INSN_CLASS_ZPN, "d,s", MATCH_CLZ32, MASK_CLZ32, match_opcode, 0 }, +{"cmpeq8", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_CMPEQ8, MASK_CMPEQ8, match_opcode, 0 }, +{"cmpeq16", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_CMPEQ16, MASK_CMPEQ16, match_opcode, 0 }, +{"cras16", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_CRAS16, MASK_CRAS16, match_opcode, 0 }, +{"crsa16", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_CRSA16, MASK_CRSA16, match_opcode, 0 }, +{"insb", 0, INSN_CLASS_ZPN, "d,s,nds_i3u", MATCH_INSB, MASK_INSB, match_opcode, 0 }, +{"kabs8", 0, INSN_CLASS_ZPN, "d,s", MATCH_KABS8, MASK_KABS8, match_opcode, 0 }, +{"kabs16", 0, INSN_CLASS_ZPN, "d,s", MATCH_KABS16, MASK_KABS16, match_opcode, 0 }, +{"kabsw", 0, INSN_CLASS_ZPN, "d,s", MATCH_KABSW, MASK_KABSW, match_opcode, 0 }, +{"kadd8", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_KADD8, MASK_KADD8, match_opcode, 0 }, +{"kadd16", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_KADD16, MASK_KADD16, match_opcode, 0 }, +{"kadd64", 0, INSN_CLASS_ZPSF, "nds_rdp,nds_rsp,nds_rtp", MATCH_KADD64, MASK_KADD64, match_opcode, 0 }, +{"kaddh", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_KADDH, MASK_KADDH, match_opcode, 0 }, +{"kaddw", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_KADDW, MASK_KADDW, match_opcode, 0 }, +{"kcras16", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_KCRAS16, MASK_KCRAS16, match_opcode, 0 }, +{"kcrsa16", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_KCRSA16, MASK_KCRSA16, match_opcode, 0 }, +{"kdmbb", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_KDMBB, MASK_KDMBB, match_opcode, 0 }, +{"kdmbt", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_KDMBT, MASK_KDMBT, match_opcode, 0 }, +{"kdmtt", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_KDMTT, MASK_KDMTT, match_opcode, 0 }, +{"kdmabb", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_KDMABB, MASK_KDMABB, match_opcode, 0 }, +{"kdmabt", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_KDMABT, MASK_KDMABT, match_opcode, 0 }, +{"kdmatt", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_KDMATT, MASK_KDMATT, match_opcode, 0 }, +{"khm8", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_KHM8, MASK_KHM8, match_opcode, 0 }, +{"khmx8", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_KHMX8, MASK_KHMX8, match_opcode, 0 }, +{"khm16", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_KHM16, MASK_KHM16, match_opcode, 0 }, +{"khmx16", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_KHMX16, MASK_KHMX16, match_opcode, 0 }, +{"khmbb", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_KHMBB, MASK_KHMBB, match_opcode, 0 }, +{"khmbt", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_KHMBT, MASK_KHMBT, match_opcode, 0 }, +{"khmtt", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_KHMTT, MASK_KHMTT, match_opcode, 0 }, +{"kmabb", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_KMABB, MASK_KMABB, match_opcode, 0 }, +{"kmabt", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_KMABT, MASK_KMABT, match_opcode, 0 }, +{"kmatt", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_KMATT, MASK_KMATT, match_opcode, 0 }, +{"kmada", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_KMADA, MASK_KMADA, match_opcode, 0 }, +{"kmaxda", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_KMAXDA, MASK_KMAXDA, match_opcode, 0 }, +{"kmads", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_KMADS, MASK_KMADS, match_opcode, 0 }, +{"kmadrs", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_KMADRS, MASK_KMADRS, match_opcode, 0 }, +{"kmaxds", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_KMAXDS, MASK_KMAXDS, match_opcode, 0 }, +{"kmar64", 0, INSN_CLASS_ZPSF, "nds_rdp,s,t", MATCH_KMAR64, MASK_KMAR64, match_opcode, 0 }, +{"kmda", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_KMDA, MASK_KMDA, match_opcode, 0 }, +{"kmxda", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_KMXDA, MASK_KMXDA, match_opcode, 0 }, +{"kmmac", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_KMMAC, MASK_KMMAC, match_opcode, 0 }, +{"kmmac.u", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_KMMAC_U, MASK_KMMAC_U, match_opcode, 0 }, +{"kmmawb", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_KMMAWB, MASK_KMMAWB, match_opcode, 0 }, +{"kmmawb.u", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_KMMAWB_U, MASK_KMMAWB_U, match_opcode, 0 }, +{"kmmawb2", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_KMMAWB2, MASK_KMMAWB2, match_opcode, 0 }, +{"kmmawb2.u", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_KMMAWB2_U, MASK_KMMAWB2_U, match_opcode, 0 }, +{"kmmawt", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_KMMAWT, MASK_KMMAWT, match_opcode, 0 }, +{"kmmawt.u", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_KMMAWT_U, MASK_KMMAWT_U, match_opcode, 0 }, +{"kmmawt2", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_KMMAWT2, MASK_KMMAWT2, match_opcode, 0 }, +{"kmmawt2.u", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_KMMAWT2_U, MASK_KMMAWT2_U, match_opcode, 0 }, +{"kmmsb", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_KMMSB, MASK_KMMSB, match_opcode, 0 }, +{"kmmsb.u", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_KMMSB_U, MASK_KMMSB_U, match_opcode, 0 }, +{"kmmwb2", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_KMMWB2, MASK_KMMWB2, match_opcode, 0 }, +{"kmmwb2.u", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_KMMWB2_U, MASK_KMMWB2_U, match_opcode, 0 }, +{"kmmwt2", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_KMMWT2, MASK_KMMWT2, match_opcode, 0 }, +{"kmmwt2.u", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_KMMWT2_U, MASK_KMMWT2_U, match_opcode, 0 }, +{"kmsda", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_KMSDA, MASK_KMSDA, match_opcode, 0 }, +{"kmsxda", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_KMSXDA, MASK_KMSXDA, match_opcode, 0 }, +{"kmsr64", 0, INSN_CLASS_ZPSF, "nds_rdp,s,t", MATCH_KMSR64, MASK_KMSR64, match_opcode, 0 }, +{"ksllw", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_KSLLW, MASK_KSLLW, match_opcode, 0 }, +{"kslliw", 0, INSN_CLASS_ZPN, "d,s,nds_i5u", MATCH_KSLLIW, MASK_KSLLIW, match_opcode, 0 }, +{"ksll8", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_KSLL8, MASK_KSLL8, match_opcode, 0 }, +{"kslli8", 0, INSN_CLASS_ZPN, "d,s,nds_i3u", MATCH_KSLLI8, MASK_KSLLI8, match_opcode, 0 }, +{"ksll16", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_KSLL16, MASK_KSLL16, match_opcode, 0 }, +{"kslli16", 0, INSN_CLASS_ZPN, "d,s,nds_i4u", MATCH_KSLLI16, MASK_KSLLI16, match_opcode, 0 }, +{"kslra8", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_KSLRA8, MASK_KSLRA8, match_opcode, 0 }, +{"kslra8.u", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_KSLRA8_U, MASK_KSLRA8_U, match_opcode, 0 }, +{"kslra16", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_KSLRA16, MASK_KSLRA16, match_opcode, 0 }, +{"kslra16.u", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_KSLRA16_U, MASK_KSLRA16_U, match_opcode, 0 }, +{"kslraw", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_KSLRAW, MASK_KSLRAW, match_opcode, 0 }, +{"kslraw.u", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_KSLRAW_U, MASK_KSLRAW_U, match_opcode, 0 }, +{"kstas16", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_KSTAS16, MASK_KSTAS16, match_opcode, 0 }, +{"kstsa16", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_KSTSA16, MASK_KSTSA16, match_opcode, 0 }, +{"ksub8", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_KSUB8, MASK_KSUB8, match_opcode, 0 }, +{"ksub16", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_KSUB16, MASK_KSUB16, match_opcode, 0 }, +{"ksub64", 0, INSN_CLASS_ZPSF, "nds_rdp,nds_rsp,nds_rtp", MATCH_KSUB64, MASK_KSUB64, match_opcode, 0 }, +{"ksubh", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_KSUBH, MASK_KSUBH, match_opcode, 0 }, +{"ksubw", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_KSUBW, MASK_KSUBW, match_opcode, 0 }, +{"kwmmul", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_KWMMUL, MASK_KWMMUL, match_opcode, 0 }, +{"kwmmul.u", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_KWMMUL_U, MASK_KWMMUL_U, match_opcode, 0 }, +{"maddr32", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_MADDR32, MASK_MADDR32, match_opcode, 0 }, +{"msubr32", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_MSUBR32, MASK_MSUBR32, match_opcode, 0 }, +{"mulr64", 0, INSN_CLASS_ZPSF, "nds_rdp,s,t", MATCH_MULR64, MASK_MULR64, match_opcode, 0 }, +{"mulsr64", 0, INSN_CLASS_ZPSF, "nds_rdp,s,t", MATCH_MULSR64, MASK_MULSR64, match_opcode, 0 }, +{"pbsad", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_PBSAD, MASK_PBSAD, match_opcode, 0 }, +{"pbsada", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_PBSADA, MASK_PBSADA, match_opcode, 0 }, +{"pkbb16", 32,INSN_CLASS_ZBPBO, "d,s,t", MATCH_PACKU, MASK_PACKU, match_opcode, INSN_ALIAS }, +{"pkbb16", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_PKBB16, MASK_PKBB16, match_opcode, 0 }, +{"pkbt16", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_PKBT16, MASK_PKBT16, match_opcode, 0 }, +{"pktt16", 32,INSN_CLASS_ZBPBO, "d,s,t", MATCH_PACK, MASK_PACK, match_opcode, INSN_ALIAS }, +{"pktt16", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_PKTT16, MASK_PKTT16, match_opcode, 0 }, +{"pktb16", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_PKTB16, MASK_PKTB16, match_opcode, 0 }, +{"radd8", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_RADD8, MASK_RADD8, match_opcode, 0 }, +{"radd16", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_RADD16, MASK_RADD16, match_opcode, 0 }, +{"radd64", 0, INSN_CLASS_ZPSF, "nds_rdp,nds_rsp,nds_rtp", MATCH_RADD64, MASK_RADD64, match_opcode, 0 }, +{"raddw", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_RADDW, MASK_RADDW, match_opcode, 0 }, +{"rcras16", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_RCRAS16, MASK_RCRAS16, match_opcode, 0 }, +{"rcrsa16", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_RCRSA16, MASK_RCRSA16, match_opcode, 0 }, +{"rstas16", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_RSTAS16, MASK_RSTAS16, match_opcode, 0 }, +{"rstsa16", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_RSTSA16, MASK_RSTSA16, match_opcode, 0 }, +{"rsub8", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_RSUB8, MASK_RSUB8, match_opcode, 0 }, +{"rsub16", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_RSUB16, MASK_RSUB16, match_opcode, 0 }, +{"rsub64", 0, INSN_CLASS_ZPSF, "nds_rdp,nds_rsp,nds_rtp", MATCH_RSUB64, MASK_RSUB64, match_opcode, 0 }, +{"rsubw", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_RSUBW, MASK_RSUBW, match_opcode, 0 }, +{"sclip8", 0, INSN_CLASS_ZPN, "d,s,nds_i3u", MATCH_SCLIP8, MASK_SCLIP8, match_opcode, 0 }, +{"sclip16", 0, INSN_CLASS_ZPN, "d,s,nds_i4u", MATCH_SCLIP16, MASK_SCLIP16, match_opcode, 0 }, +{"sclip32", 0, INSN_CLASS_ZPN, "d,s,nds_i5u", MATCH_SCLIP32, MASK_SCLIP32, match_opcode, 0 }, +{"scmple8", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_SCMPLE8, MASK_SCMPLE8, match_opcode, 0 }, +{"scmple16", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_SCMPLE16, MASK_SCMPLE16, match_opcode, 0 }, +{"scmplt8", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_SCMPLT8, MASK_SCMPLT8, match_opcode, 0 }, +{"scmplt16", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_SCMPLT16, MASK_SCMPLT16, match_opcode, 0 }, +{"sll8", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_SLL8, MASK_SLL8, match_opcode, 0 }, +{"slli8", 0, INSN_CLASS_ZPN, "d,s,nds_i3u", MATCH_SLLI8, MASK_SLLI8, match_opcode, 0 }, +{"sll16", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_SLL16, MASK_SLL16, match_opcode, 0 }, +{"slli16", 0, INSN_CLASS_ZPN, "d,s,nds_i4u", MATCH_SLLI16, MASK_SLLI16, match_opcode, 0 }, +{"smal", 0, INSN_CLASS_ZPSF, "nds_rdp,nds_rsp,t", MATCH_SMAL, MASK_SMAL, match_opcode, 0 }, +{"smalbb", 0, INSN_CLASS_ZPSF, "nds_rdp,s,t", MATCH_SMALBB, MASK_SMALBB, match_opcode, 0 }, +{"smalbt", 0, INSN_CLASS_ZPSF, "nds_rdp,s,t", MATCH_SMALBT, MASK_SMALBT, match_opcode, 0 }, +{"smaltt", 0, INSN_CLASS_ZPSF, "nds_rdp,s,t", MATCH_SMALTT, MASK_SMALTT, match_opcode, 0 }, +{"smalda", 0, INSN_CLASS_ZPSF, "nds_rdp,s,t", MATCH_SMALDA, MASK_SMALDA, match_opcode, 0 }, +{"smalxda", 0, INSN_CLASS_ZPSF, "nds_rdp,s,t", MATCH_SMALXDA, MASK_SMALXDA, match_opcode, 0 }, +{"smalds", 0, INSN_CLASS_ZPSF, "nds_rdp,s,t", MATCH_SMALDS, MASK_SMALDS, match_opcode, 0 }, +{"smaldrs", 0, INSN_CLASS_ZPSF, "nds_rdp,s,t", MATCH_SMALDRS, MASK_SMALDRS, match_opcode, 0 }, +{"smalxds", 0, INSN_CLASS_ZPSF, "nds_rdp,s,t", MATCH_SMALXDS, MASK_SMALXDS, match_opcode, 0 }, +{"smar64", 0, INSN_CLASS_ZPSF, "nds_rdp,s,t", MATCH_SMAR64, MASK_SMAR64, match_opcode, 0 }, +{"smaqa", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_SMAQA, MASK_SMAQA, match_opcode, 0 }, +{"smaqa.su", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_SMAQA_SU, MASK_SMAQA_SU, match_opcode, 0 }, +{"smax8", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_SMAX8, MASK_SMAX8, match_opcode, 0 }, +{"smax16", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_SMAX16, MASK_SMAX16, match_opcode, 0 }, +{"smbb16", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_SMBB16, MASK_SMBB16, match_opcode, 0 }, +{"smbt16", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_SMBT16, MASK_SMBT16, match_opcode, 0 }, +{"smtt16", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_SMTT16, MASK_SMTT16, match_opcode, 0 }, +{"smds", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_SMDS, MASK_SMDS, match_opcode, 0 }, +{"smdrs", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_SMDRS, MASK_SMDRS, match_opcode, 0 }, +{"smxds", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_SMXDS, MASK_SMXDS, match_opcode, 0 }, +{"smin8", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_SMIN8, MASK_SMIN8, match_opcode, 0 }, +{"smin16", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_SMIN16, MASK_SMIN16, match_opcode, 0 }, +{"smmul", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_SMMUL, MASK_SMMUL, match_opcode, 0 }, +{"smmul.u", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_SMMUL_U, MASK_SMMUL_U, match_opcode, 0 }, +{"smmwb", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_SMMWB, MASK_SMMWB, match_opcode, 0 }, +{"smmwb.u", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_SMMWB_U, MASK_SMMWB_U, match_opcode, 0 }, +{"smmwt", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_SMMWT, MASK_SMMWT, match_opcode, 0 }, +{"smmwt.u", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_SMMWT_U, MASK_SMMWT_U, match_opcode, 0 }, +{"smslda", 0, INSN_CLASS_ZPSF, "nds_rdp,s,t", MATCH_SMSLDA, MASK_SMSLDA, match_opcode, 0 }, +{"smslxda", 0, INSN_CLASS_ZPSF, "nds_rdp,s,t", MATCH_SMSLXDA, MASK_SMSLXDA, match_opcode, 0 }, +{"smsr64", 0, INSN_CLASS_ZPSF, "nds_rdp,s,t", MATCH_SMSR64, MASK_SMSR64, match_opcode, 0 }, +{"smul8", 0, INSN_CLASS_ZPSF, "nds_rdp,s,t", MATCH_SMUL8, MASK_SMUL8, match_opcode, 0 }, +{"smulx8", 0, INSN_CLASS_ZPSF, "nds_rdp,s,t", MATCH_SMULX8, MASK_SMULX8, match_opcode, 0 }, +{"smul16", 0, INSN_CLASS_ZPSF, "nds_rdp,s,t", MATCH_SMUL16, MASK_SMUL16, match_opcode, 0 }, +{"smulx16", 0, INSN_CLASS_ZPSF, "nds_rdp,s,t", MATCH_SMULX16, MASK_SMULX16, match_opcode, 0 }, +{"sra.u", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_SRA_U, MASK_SRA_U, match_opcode, 0 }, +{"srai.u", 0, INSN_CLASS_ZPN, "d,s,nds_i6u", MATCH_SRAI_U, MASK_SRAI_U, match_opcode, 0 }, +{"sra8", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_SRA8, MASK_SRA8, match_opcode, 0 }, +{"sra8.u", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_SRA8_U, MASK_SRA8_U, match_opcode, 0 }, +{"srai8", 0, INSN_CLASS_ZPN, "d,s,nds_i3u", MATCH_SRAI8, MASK_SRAI8, match_opcode, 0 }, +{"srai8.u", 0, INSN_CLASS_ZPN, "d,s,nds_i3u", MATCH_SRAI8_U, MASK_SRAI8_U, match_opcode, 0 }, +{"sra16", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_SRA16, MASK_SRA16, match_opcode, 0 }, +{"sra16.u", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_SRA16_U, MASK_SRA16_U, match_opcode, 0 }, +{"srai16", 0, INSN_CLASS_ZPN, "d,s,nds_i4u", MATCH_SRAI16, MASK_SRAI16, match_opcode, 0 }, +{"srai16.u", 0, INSN_CLASS_ZPN, "d,s,nds_i4u", MATCH_SRAI16_U, MASK_SRAI16_U, match_opcode, 0 }, +{"srl8", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_SRL8, MASK_SRL8, match_opcode, 0 }, +{"srl8.u", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_SRL8_U, MASK_SRL8_U, match_opcode, 0 }, +{"srli8", 0, INSN_CLASS_ZPN, "d,s,nds_i3u", MATCH_SRLI8, MASK_SRLI8, match_opcode, 0 }, +{"srli8.u", 0, INSN_CLASS_ZPN, "d,s,nds_i3u", MATCH_SRLI8_U, MASK_SRLI8_U, match_opcode, 0 }, +{"srl16", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_SRL16, MASK_SRL16, match_opcode, 0 }, +{"srl16.u", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_SRL16_U, MASK_SRL16_U, match_opcode, 0 }, +{"srli16", 0, INSN_CLASS_ZPN, "d,s,nds_i4u", MATCH_SRLI16, MASK_SRLI16, match_opcode, 0 }, +{"srli16.u", 0, INSN_CLASS_ZPN, "d,s,nds_i4u", MATCH_SRLI16_U, MASK_SRLI16_U, match_opcode, 0 }, +{"stas16", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_STAS16, MASK_STAS16, match_opcode, 0 }, +{"stsa16", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_STSA16, MASK_STSA16, match_opcode, 0 }, +{"sub8", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_SUB8, MASK_SUB8, match_opcode, 0 }, +{"sub16", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_SUB16, MASK_SUB16, match_opcode, 0 }, +{"sub64", 32, INSN_CLASS_ZPSF, "nds_rdp,nds_rsp,nds_rtp", MATCH_SUB64, MASK_SUB64, match_opcode, 0 }, +{"sunpkd810", 0, INSN_CLASS_ZPN, "d,s", MATCH_SUNPKD810, MASK_SUNPKD810, match_opcode, 0 }, +{"sunpkd820", 0, INSN_CLASS_ZPN, "d,s", MATCH_SUNPKD820, MASK_SUNPKD820, match_opcode, 0 }, +{"sunpkd830", 0, INSN_CLASS_ZPN, "d,s", MATCH_SUNPKD830, MASK_SUNPKD830, match_opcode, 0 }, +{"sunpkd831", 0, INSN_CLASS_ZPN, "d,s", MATCH_SUNPKD831, MASK_SUNPKD831, match_opcode, 0 }, +{"sunpkd832", 0, INSN_CLASS_ZPN, "d,s", MATCH_SUNPKD832, MASK_SUNPKD832, match_opcode, 0 }, +{"swap8", 0, INSN_CLASS_ZBPBO, "d,s", MATCH_GREVI|MATCH_SHAMT_REV8_H, MASK_GREVI|(OP_MASK_SHAMT << 20), match_opcode, INSN_ALIAS }, +{"swap8", 0, INSN_CLASS_ZPN, "d,s", MATCH_SWAP8, MASK_SWAP8, match_opcode, 0 }, +{"swap16", 0, INSN_CLASS_ZPN, "d,g", MATCH_PKBT16, MASK_PKBT16, match_opcode, INSN_ALIAS }, +{"uclip8", 0, INSN_CLASS_ZPN, "d,s,nds_i3u", MATCH_UCLIP8, MASK_UCLIP8, match_opcode, 0 }, +{"uclip16", 0, INSN_CLASS_ZPN, "d,s,nds_i4u", MATCH_UCLIP16, MASK_UCLIP16, match_opcode, 0 }, +{"uclip32", 0, INSN_CLASS_ZPN, "d,s,nds_i5u", MATCH_UCLIP32, MASK_UCLIP32, match_opcode, 0 }, +{"ucmple8", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_UCMPLE8, MASK_UCMPLE8, match_opcode, 0 }, +{"ucmple16", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_UCMPLE16, MASK_UCMPLE16, match_opcode, 0 }, +{"ucmplt8", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_UCMPLT8, MASK_UCMPLT8, match_opcode, 0 }, +{"ucmplt16", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_UCMPLT16, MASK_UCMPLT16, match_opcode, 0 }, +{"ukadd8", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_UKADD8, MASK_UKADD8, match_opcode, 0 }, +{"ukadd16", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_UKADD16, MASK_UKADD16, match_opcode, 0 }, +{"ukadd64", 0, INSN_CLASS_ZPSF, "nds_rdp,nds_rsp,nds_rtp", MATCH_UKADD64, MASK_UKADD64, match_opcode, 0 }, +{"ukaddh", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_UKADDH, MASK_UKADDH, match_opcode, 0 }, +{"ukaddw", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_UKADDW, MASK_UKADDW, match_opcode, 0 }, +{"ukcras16", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_UKCRAS16, MASK_UKCRAS16, match_opcode, 0 }, +{"ukcrsa16", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_UKCRSA16, MASK_UKCRSA16, match_opcode, 0 }, +{"ukmar64", 0, INSN_CLASS_ZPSF, "nds_rdp,s,t", MATCH_UKMAR64, MASK_UKMAR64, match_opcode, 0 }, +{"ukmsr64", 0, INSN_CLASS_ZPSF, "nds_rdp,s,t", MATCH_UKMSR64, MASK_UKMSR64, match_opcode, 0 }, +{"ukstas16", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_UKSTAS16, MASK_UKSTAS16, match_opcode, 0 }, +{"ukstsa16", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_UKSTSA16, MASK_UKSTSA16, match_opcode, 0 }, +{"uksub8", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_UKSUB8, MASK_UKSUB8, match_opcode, 0 }, +{"uksub16", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_UKSUB16, MASK_UKSUB16, match_opcode, 0 }, +{"uksub64", 0, INSN_CLASS_ZPSF, "nds_rdp,nds_rsp,nds_rtp", MATCH_UKSUB64, MASK_UKSUB64, match_opcode, 0 }, +{"uksubh", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_UKSUBH, MASK_UKSUBH, match_opcode, 0 }, +{"uksubw", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_UKSUBW, MASK_UKSUBW, match_opcode, 0 }, +{"umar64", 0, INSN_CLASS_ZPSF, "nds_rdp,s,t", MATCH_UMAR64, MASK_UMAR64, match_opcode, 0 }, +{"umaqa", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_UMAQA, MASK_UMAQA, match_opcode, 0 }, +{"umax8", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_UMAX8, MASK_UMAX8, match_opcode, 0 }, +{"umax16", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_UMAX16, MASK_UMAX16, match_opcode, 0 }, +{"umin8", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_UMIN8, MASK_UMIN8, match_opcode, 0 }, +{"umin16", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_UMIN16, MASK_UMIN16, match_opcode, 0 }, +{"umsr64", 0, INSN_CLASS_ZPSF, "nds_rdp,s,t", MATCH_UMSR64, MASK_UMSR64, match_opcode, 0 }, +{"umul8", 0, INSN_CLASS_ZPSF, "d,s,t", MATCH_UMUL8, MASK_UMUL8, match_opcode, 0 }, +{"umulx8", 0, INSN_CLASS_ZPSF, "d,s,t", MATCH_UMULX8, MASK_UMULX8, match_opcode, 0 }, +{"umul16", 0, INSN_CLASS_ZPSF, "nds_rdp,s,t", MATCH_UMUL16, MASK_UMUL16, match_opcode, 0 }, +{"umulx16", 0, INSN_CLASS_ZPSF, "nds_rdp,s,t", MATCH_UMULX16, MASK_UMULX16, match_opcode, 0 }, +{"uradd8", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_URADD8, MASK_URADD8, match_opcode, 0 }, +{"uradd16", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_URADD16, MASK_URADD16, match_opcode, 0 }, +{"uradd64", 0, INSN_CLASS_ZPSF, "nds_rdp,nds_rsp,nds_rtp", MATCH_URADD64, MASK_URADD64, match_opcode, 0 }, +{"uraddw", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_URADDW, MASK_URADDW, match_opcode, 0 }, +{"urcras16", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_URCRAS16, MASK_URCRAS16, match_opcode, 0 }, +{"urcrsa16", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_URCRSA16, MASK_URCRSA16, match_opcode, 0 }, +{"urstas16", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_URSTAS16, MASK_URSTAS16, match_opcode, 0 }, +{"urstsa16", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_URSTSA16, MASK_URSTSA16, match_opcode, 0 }, +{"ursub8", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_URSUB8, MASK_URSUB8, match_opcode, 0 }, +{"ursub16", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_URSUB16, MASK_URSUB16, match_opcode, 0 }, +{"ursub64", 0, INSN_CLASS_ZPSF, "nds_rdp,nds_rsp,nds_rtp", MATCH_URSUB64, MASK_URSUB64, match_opcode, 0 }, +{"ursubw", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_URSUBW, MASK_URSUBW, match_opcode, 0 }, +{"wexti", 0, INSN_CLASS_ZPSF, "d,nds_rsp,nds_i5u", MATCH_WEXTI, MASK_WEXTI, match_opcode, 0 }, +{"wext", 0, INSN_CLASS_ZPSF, "d,nds_rsp,t", MATCH_WEXT, MASK_WEXT, match_opcode, 0 }, +{"zunpkd810", 0, INSN_CLASS_ZPN, "d,s", MATCH_ZUNPKD810, MASK_ZUNPKD810, match_opcode, 0 }, +{"zunpkd820", 0, INSN_CLASS_ZPN, "d,s", MATCH_ZUNPKD820, MASK_ZUNPKD820, match_opcode, 0 }, +{"zunpkd830", 0, INSN_CLASS_ZPN, "d,s", MATCH_ZUNPKD830, MASK_ZUNPKD830, match_opcode, 0 }, +{"zunpkd831", 0, INSN_CLASS_ZPN, "d,s", MATCH_ZUNPKD831, MASK_ZUNPKD831, match_opcode, 0 }, +{"zunpkd832", 0, INSN_CLASS_ZPN, "d,s", MATCH_ZUNPKD832, MASK_ZUNPKD832, match_opcode, 0 }, +{"rdov", 0, INSN_CLASS_ZPN, "d", MATCH_RDOV, MASK_RDOV, match_opcode, INSN_ALIAS }, +{"clrov", 0, INSN_CLASS_ZPN, "", MATCH_CLROV, 0xffffffffU, match_opcode, INSN_ALIAS }, +{"add32", 64, INSN_CLASS_ZPN, "d,s,t", MATCH_ADD32, MASK_ADD32, match_opcode, 0 }, +{"cras32", 64, INSN_CLASS_ZPN, "d,s,t", MATCH_CRAS32, MASK_CRAS32, match_opcode, 0 }, +{"crsa32", 64, INSN_CLASS_ZPN, "d,s,t", MATCH_CRSA32, MASK_CRSA32, match_opcode, 0 }, +{"kabs32", 64, INSN_CLASS_ZPN, "d,s", MATCH_KABS32, MASK_KABS32, match_opcode, 0 }, +{"kadd32", 64, INSN_CLASS_ZPN, "d,s,t", MATCH_KADD32, MASK_KADD32, match_opcode, 0 }, +{"kcras32", 64, INSN_CLASS_ZPN, "d,s,t", MATCH_KCRAS32, MASK_KCRAS32, match_opcode, 0 }, +{"kcrsa32", 64, INSN_CLASS_ZPN, "d,s,t", MATCH_KCRSA32, MASK_KCRSA32, match_opcode, 0 }, +{"kdmbb16", 64, INSN_CLASS_ZPN, "d,s,t", MATCH_KDMBB16, MASK_KDMBB16, match_opcode, 0 }, +{"kdmbt16", 64, INSN_CLASS_ZPN, "d,s,t", MATCH_KDMBT16, MASK_KDMBT16, match_opcode, 0 }, +{"kdmtt16", 64, INSN_CLASS_ZPN, "d,s,t", MATCH_KDMTT16, MASK_KDMTT16, match_opcode, 0 }, +{"kdmabb16", 64, INSN_CLASS_ZPN, "d,s,t", MATCH_KDMABB16, MASK_KDMABB16, match_opcode, 0 }, +{"kdmabt16", 64, INSN_CLASS_ZPN, "d,s,t", MATCH_KDMABT16, MASK_KDMABT16, match_opcode, 0 }, +{"kdmatt16", 64, INSN_CLASS_ZPN, "d,s,t", MATCH_KDMATT16, MASK_KDMATT16, match_opcode, 0 }, +{"khmbb16", 64, INSN_CLASS_ZPN, "d,s,t", MATCH_KHMBB16, MASK_KHMBB16, match_opcode, 0 }, +{"khmbt16", 64, INSN_CLASS_ZPN, "d,s,t", MATCH_KHMBT16, MASK_KHMBT16, match_opcode, 0 }, +{"khmtt16", 64, INSN_CLASS_ZPN, "d,s,t", MATCH_KHMTT16, MASK_KHMTT16, match_opcode, 0 }, +{"kmabb32", 64, INSN_CLASS_ZPN, "d,s,t", MATCH_KMABB32, MASK_KMABB32, match_opcode, 0 }, +{"kmabt32", 64, INSN_CLASS_ZPN, "d,s,t", MATCH_KMABT32, MASK_KMABT32, match_opcode, 0 }, +{"kmatt32", 64, INSN_CLASS_ZPN, "d,s,t", MATCH_KMATT32, MASK_KMATT32, match_opcode, 0 }, +{"kmada32", 64, INSN_CLASS_ZPN, "d,s,t", MATCH_KMAR64, MASK_KMAR64, match_opcode, INSN_ALIAS }, +{"kmaxda32", 64, INSN_CLASS_ZPN, "d,s,t", MATCH_KMAXDA32, MASK_KMAXDA32, match_opcode, 0 }, +{"kmda32", 64, INSN_CLASS_ZPN, "d,s,t", MATCH_KMDA32, MASK_KMDA32, match_opcode, 0 }, +{"kmxda32", 64, INSN_CLASS_ZPN, "d,s,t", MATCH_KMXDA32, MASK_KMXDA32, match_opcode, 0 }, +{"kmads32", 64, INSN_CLASS_ZPN, "d,s,t", MATCH_KMADS32, MASK_KMADS32, match_opcode, 0 }, +{"kmadrs32", 64, INSN_CLASS_ZPN, "d,s,t", MATCH_KMADRS32, MASK_KMADRS32, match_opcode, 0 }, +{"kmaxds32", 64, INSN_CLASS_ZPN, "d,s,t", MATCH_KMAXDS32, MASK_KMAXDS32, match_opcode, 0 }, +{"kmsda32", 64, INSN_CLASS_ZPN, "d,s,t", MATCH_KMSDA32, MASK_KMSDA32, match_opcode, 0 }, +{"kmsxda32", 64, INSN_CLASS_ZPN, "d,s,t", MATCH_KMSXDA32, MASK_KMSXDA32, match_opcode, 0 }, +{"ksll32", 64, INSN_CLASS_ZPN, "d,s,t", MATCH_KSLL32, MASK_KSLL32, match_opcode, 0 }, +{"kslli32", 64, INSN_CLASS_ZPN, "d,s,nds_i5u", MATCH_KSLLI32, MASK_KSLLI32, match_opcode, 0 }, +{"kslra32", 64, INSN_CLASS_ZPN, "d,s,t", MATCH_KSLRA32, MASK_KSLRA32, match_opcode, 0 }, +{"kslra32.u", 64, INSN_CLASS_ZPN, "d,s,t", MATCH_KSLRA32_U, MASK_KSLRA32_U, match_opcode, 0 }, +{"kstas32", 64, INSN_CLASS_ZPN, "d,s,t", MATCH_KSTAS32, MASK_KSTAS32, match_opcode, 0 }, +{"kstsa32", 64, INSN_CLASS_ZPN, "d,s,t", MATCH_KSTSA32, MASK_KSTSA32, match_opcode, 0 }, +{"ksub32", 64, INSN_CLASS_ZPN, "d,s,t", MATCH_KSUB32, MASK_KSUB32, match_opcode, 0 }, +{"pkbb32", 64, INSN_CLASS_ZBPBO, "d,s,t", MATCH_PACK, MASK_PACK, match_opcode, INSN_ALIAS }, +{"pkbb32", 64, INSN_CLASS_ZPN, "d,s,t", MATCH_PKBB32, MASK_PKBB32, match_opcode, 0 }, +{"pkbt32", 64, INSN_CLASS_ZPN, "d,s,t", MATCH_PKBT32, MASK_PKBT32, match_opcode, 0 }, +{"pktt32", 64, INSN_CLASS_ZBPBO, "d,s,t", MATCH_PACKU, MASK_PACKU, match_opcode, INSN_ALIAS }, +{"pktt32", 64, INSN_CLASS_ZPN, "d,s,t", MATCH_PKTT32, MASK_PKTT32, match_opcode, 0 }, +{"pktb32", 64, INSN_CLASS_ZPN, "d,s,t", MATCH_PKTB32, MASK_PKTB32, match_opcode, 0 }, +{"radd32", 64, INSN_CLASS_ZPN, "d,s,t", MATCH_RADD32, MASK_RADD32, match_opcode, 0 }, +{"rcras32", 64, INSN_CLASS_ZPN, "d,s,t", MATCH_RCRAS32, MASK_RCRAS32, match_opcode, 0 }, +{"rcrsa32", 64, INSN_CLASS_ZPN, "d,s,t", MATCH_RCRSA32, MASK_RCRSA32, match_opcode, 0 }, +{"rstas32", 64, INSN_CLASS_ZPN, "d,s,t", MATCH_RSTAS32, MASK_RSTAS32, match_opcode, 0 }, +{"rstsa32", 64, INSN_CLASS_ZPN, "d,s,t", MATCH_RSTSA32, MASK_RSTSA32, match_opcode, 0 }, +{"rsub32", 64, INSN_CLASS_ZPN, "d,s,t", MATCH_RSUB32, MASK_RSUB32, match_opcode, 0 }, +{"sll32", 64, INSN_CLASS_ZPN, "d,s,t", MATCH_SLL32, MASK_SLL32, match_opcode, 0 }, +{"slli32", 64, INSN_CLASS_ZPN, "d,s,nds_i5u", MATCH_SLLI32, MASK_SLLI32, match_opcode, 0 }, +{"smax32", 64, INSN_CLASS_ZPN, "d,s,t", MATCH_SMAX32, MASK_SMAX32, match_opcode, 0 }, +{"smbb32", 64, INSN_CLASS_ZPN, "d,s,t", MATCH_MULSR64, MASK_MULSR64, match_opcode, INSN_ALIAS }, +{"smbt32", 64, INSN_CLASS_ZPN, "d,s,t", MATCH_SMBT32, MASK_SMBT32, match_opcode, 0 }, +{"smtt32", 64, INSN_CLASS_ZPN, "d,s,t", MATCH_SMTT32, MASK_SMTT32, match_opcode, 0 }, +{"smds32", 64, INSN_CLASS_ZPN, "d,s,t", MATCH_SMDS32, MASK_SMDS32, match_opcode, 0 }, +{"smdrs32", 64, INSN_CLASS_ZPN, "d,s,t", MATCH_SMDRS32, MASK_SMDRS32, match_opcode, 0 }, +{"smxds32", 64, INSN_CLASS_ZPN, "d,s,t", MATCH_SMXDS32, MASK_SMXDS32, match_opcode, 0 }, +{"smin32", 64, INSN_CLASS_ZPN, "d,s,t", MATCH_SMIN32, MASK_SMIN32, match_opcode, 0 }, +{"sra32", 64, INSN_CLASS_ZPN, "d,s,t", MATCH_SRA32, MASK_SRA32, match_opcode, 0 }, +{"sra32.u", 64, INSN_CLASS_ZPN, "d,s,t", MATCH_SRA32_U, MASK_SRA32_U, match_opcode, 0 }, +{"srai32", 64, INSN_CLASS_ZPN, "d,s,nds_i5u", MATCH_SRAI32, MASK_SRAI32, match_opcode, 0 }, +{"srai32.u", 64, INSN_CLASS_ZPN, "d,s,nds_i5u", MATCH_SRAI32_U, MASK_SRAI32_U, match_opcode, 0 }, +{"sraiw.u", 64, INSN_CLASS_ZPN, "d,s,nds_i5u", MATCH_SRAIW_U, MASK_SRAIW_U, match_opcode, 0 }, +{"srl32", 64, INSN_CLASS_ZPN, "d,s,t", MATCH_SRL32, MASK_SRL32, match_opcode, 0 }, +{"srl32.u", 64, INSN_CLASS_ZPN, "d,s,t", MATCH_SRL32_U, MASK_SRL32_U, match_opcode, 0 }, +{"srli32", 64, INSN_CLASS_ZPN, "d,s,nds_i5u", MATCH_SRLI32, MASK_SRLI32, match_opcode, 0 }, +{"srli32.u", 64, INSN_CLASS_ZPN, "d,s,nds_i5u", MATCH_SRLI32_U, MASK_SRLI32_U, match_opcode, 0 }, +{"stas32", 64, INSN_CLASS_ZPN, "d,s,t", MATCH_STAS32, MASK_STAS32, match_opcode, 0 }, +{"stsa32", 64, INSN_CLASS_ZPN, "d,s,t", MATCH_STSA32, MASK_STSA32, match_opcode, 0 }, +{"sub32", 64, INSN_CLASS_ZPN, "d,s,t", MATCH_SUB32, MASK_SUB32, match_opcode, 0 }, +{"ukadd32", 64, INSN_CLASS_ZPN, "d,s,t", MATCH_UKADD32, MASK_UKADD32, match_opcode, 0 }, +{"ukcras32", 64, INSN_CLASS_ZPN, "d,s,t", MATCH_UKCRAS32, MASK_UKCRAS32, match_opcode, 0 }, +{"ukcrsa32", 64, INSN_CLASS_ZPN, "d,s,t", MATCH_UKCRSA32, MASK_UKCRSA32, match_opcode, 0 }, +{"ukstas32", 64, INSN_CLASS_ZPN, "d,s,t", MATCH_UKSTAS32, MASK_UKSTAS32, match_opcode, 0 }, +{"ukstsa32", 64, INSN_CLASS_ZPN, "d,s,t", MATCH_UKSTSA32, MASK_UKSTSA32, match_opcode, 0 }, +{"uksub32", 64, INSN_CLASS_ZPN, "d,s,t", MATCH_UKSUB32, MASK_UKSUB32, match_opcode, 0 }, +{"umax32", 64, INSN_CLASS_ZPN, "d,s,t", MATCH_UMAX32, MASK_UMAX32, match_opcode, 0 }, +{"umin32", 64, INSN_CLASS_ZPN, "d,s,t", MATCH_UMIN32, MASK_UMIN32, match_opcode, 0 }, +{"uradd32", 64, INSN_CLASS_ZPN, "d,s,t", MATCH_URADD32, MASK_URADD32, match_opcode, 0 }, +{"urcras32", 64, INSN_CLASS_ZPN, "d,s,t", MATCH_URCRAS32, MASK_URCRAS32, match_opcode, 0 }, +{"urcrsa32", 64, INSN_CLASS_ZPN, "d,s,t", MATCH_URCRSA32, MASK_URCRSA32, match_opcode, 0 }, +{"urstas32", 64, INSN_CLASS_ZPN, "d,s,t", MATCH_URSTAS32, MASK_URSTAS32, match_opcode, 0 }, +{"urstsa32", 64, INSN_CLASS_ZPN, "d,s,t", MATCH_URSTSA32, MASK_URSTSA32, match_opcode, 0 }, +{"ursub32", 64, INSN_CLASS_ZPN, "d,s,t", MATCH_URSUB32, MASK_URSUB32, match_opcode, 0 }, /* Terminate the list. */ {0, 0, INSN_CLASS_NONE, 0, 0, 0, 0, 0} };