diff --git a/librz/arch/isa/xtensa/xtensa.h b/librz/arch/isa/xtensa/xtensa.h
index 848b9658740..7ea5149d9da 100644
--- a/librz/arch/isa/xtensa/xtensa.h
+++ b/librz/arch/isa/xtensa/xtensa.h
@@ -49,5 +49,6 @@ static inline int32_t xtensa_op_l32r(cs_insn *insn, unsigned int index) {
 #define REGO(I) REG(xtensa_op_reg(ctx->insn, I))
 #define IMM(I)  xtensa_op_imm(ctx->insn, I)
 #define L32R(I) xtensa_op_l32r(ctx->insn, I)
+#define INSN_SIZE (ctx->insn->size)
 
 #endif // RIZIN_XTENSA_H
diff --git a/librz/arch/isa/xtensa/xtensa_esil.c b/librz/arch/isa/xtensa/xtensa_esil.c
index ef949436d22..ca81d1e8893 100644
--- a/librz/arch/isa/xtensa/xtensa_esil.c
+++ b/librz/arch/isa/xtensa/xtensa_esil.c
@@ -318,7 +318,7 @@ static void esil_branch_compare_imm(XtensaContext *ctx, RzAnalysisOp *op) {
 	// ISA defines branch target as offset + 4,
 	// but at the time of ESIL evaluation
 	// PC will be already incremented by 3
-	esil_push_signed_imm(&op->esil, IMM(2) + 4 - 3);
+	esil_push_signed_imm(&op->esil, IMM(2) - INSN_SIZE);
 
 	rz_strbuf_appendf(&op->esil, "pc" CM "+=" CM "}");
 }
@@ -361,7 +361,7 @@ static void esil_branch_compare(XtensaContext *ctx, RzAnalysisOp *op) {
 		REGO(0),
 		compare_op);
 
-	esil_push_signed_imm(&op->esil, IMM(2));
+	esil_push_signed_imm(&op->esil, IMM(2) - INSN_SIZE);
 
 	rz_strbuf_append(&op->esil, "pc" CM "+=" CM "}");
 }
@@ -405,7 +405,7 @@ static void esil_branch_compare_single(XtensaContext *ctx, RzAnalysisOp *op) {
 		REGO(0),
 		compare_op);
 
-	esil_push_signed_imm(&op->esil, IMM(1));
+	esil_push_signed_imm(&op->esil, IMM(1) - INSN_SIZE);
 
 	rz_strbuf_append(&op->esil, "pc" CM "+=" CM "}");
 }
@@ -461,7 +461,7 @@ static void esil_branch_check_mask(XtensaContext *ctx, RzAnalysisOp *op) {
 		REGO(1),
 		compare_op);
 
-	esil_push_signed_imm(&op->esil, IMM(2));
+	esil_push_signed_imm(&op->esil, IMM(2) - INSN_SIZE);
 
 	rz_strbuf_append(&op->esil, "pc" CM "+=" CM "}");
 }
@@ -527,7 +527,7 @@ static void esil_branch_check_bit_imm(XtensaContext *ctx, RzAnalysisOp *op) {
 		IMM(1),
 		cmp_op);
 
-	esil_push_signed_imm(&op->esil, IMM(2));
+	esil_push_signed_imm(&op->esil, IMM(2) - INSN_SIZE);
 
 	rz_strbuf_appendf(
 		&op->esil,
@@ -572,7 +572,7 @@ static void esil_branch_check_bit(XtensaContext *ctx, RzAnalysisOp *op) {
 		REGO(0),
 		cmp_op);
 
-	esil_push_signed_imm(&op->esil, IMM(2));
+	esil_push_signed_imm(&op->esil, IMM(2) - INSN_SIZE);
 
 	rz_strbuf_appendf(
 		&op->esil,
@@ -632,7 +632,7 @@ static void esil_call(XtensaContext *ctx, RzAnalysisOp *op) {
 			"=" CM);
 	}
 
-	esil_push_signed_imm(&op->esil, IMM(0));
+	esil_push_signed_imm(&op->esil, IMM(0) - INSN_SIZE);
 
 	rz_strbuf_append(&op->esil, "pc" CM "+=");
 }
@@ -835,9 +835,9 @@ void xtensa_analyze_op_esil(XtensaContext *ctx, RzAnalysisOp *op) {
 	case XTENSA_INS_EXTUI: /* extui */
 		esil_extract_unsigned(ctx, op);
 		break;
-		//	case 79: /* ill */
-		//		rz_strbuf_setf(&op->esil, "%s", "");
-		//		break;
+	case XTENSA_INS_ILL: /* ill */
+		rz_strbuf_setf(&op->esil, "%s", "");
+		break;
 		// TODO: windowed calls?
 	case XTENSA_INS_CALL4:
 		break;
diff --git a/librz/arch/p/analysis/analysis_xtensa_cs.c b/librz/arch/p/analysis/analysis_xtensa_cs.c
index 5268f60ebb0..def80904a2e 100644
--- a/librz/arch/p/analysis/analysis_xtensa_cs.c
+++ b/librz/arch/p/analysis/analysis_xtensa_cs.c
@@ -114,6 +114,7 @@ static void xtensa_analyze_op(RzAnalysis *a, RzAnalysisOp *op, XtensaContext *ct
 	case XTENSA_INS_ADDX2: /* addx2 */
 	case XTENSA_INS_ADDX4: /* addx4 */
 	case XTENSA_INS_ADDX8: /* addx8 */
+	case XTENSA_INS_ADD_N:
 		op->type = RZ_ANALYSIS_OP_TYPE_ADD;
 		break;
 	case XTENSA_INS_SUB: /* sub */
@@ -126,15 +127,20 @@ static void xtensa_analyze_op(RzAnalysis *a, RzAnalysisOp *op, XtensaContext *ct
 		op->type = RZ_ANALYSIS_OP_TYPE_MOV;
 		break;
 		//	case 0: /* excw */
+	case XTENSA_INS_EXCW:
 	case XTENSA_INS_NOP: /* nop.n */
 		op->type = RZ_ANALYSIS_OP_TYPE_NOP;
 		break;
 	case XTENSA_INS_S32I: /* s32i */
 	case XTENSA_INS_S16I: /* s16i */
 	case XTENSA_INS_S8I: /* s8i */
+	case XTENSA_INS_S32I_N:
+	case XTENSA_INS_S32C1I:
 		op->type = RZ_ANALYSIS_OP_TYPE_STORE;
 		break;
 	case XTENSA_INS_ADDI: /* addi */
+	case XTENSA_INS_ADDI_N:
+	case XTENSA_INS_ADD_S:
 		op->type = RZ_ANALYSIS_OP_TYPE_ADD;
 		break;
 	case XTENSA_INS_RET: /* ret */
@@ -145,9 +151,9 @@ static void xtensa_analyze_op(RzAnalysis *a, RzAnalysisOp *op, XtensaContext *ct
 	case XTENSA_INS_L16SI: /* l16si */
 	case XTENSA_INS_L32I: /* l32i */
 	case XTENSA_INS_L8UI: /* l8ui */
-		op->type = RZ_ANALYSIS_OP_TYPE_LOAD;
-		break;
-	case XTENSA_INS_L32R: /* l32r */
+	case XTENSA_INS_L32I_N:
+	case XTENSA_INS_L32R:
+	case XTENSA_INS_L32E:
 		op->type = RZ_ANALYSIS_OP_TYPE_LOAD;
 		break;
 	case XTENSA_INS_ADDMI: /* addmi */
@@ -211,6 +217,7 @@ static void xtensa_analyze_op(RzAnalysis *a, RzAnalysisOp *op, XtensaContext *ct
 		op->type = RZ_ANALYSIS_OP_TYPE_CMOV;
 		break;
 	case XTENSA_INS_ABS: /* abs */
+	case XTENSA_INS_ABS_S:
 		op->type = RZ_ANALYSIS_OP_TYPE_ABS;
 		break;
 	case XTENSA_INS_NEG: /* neg */
diff --git a/subprojects/capstone-next.wrap b/subprojects/capstone-next.wrap
index 943bb4f52af..c286713bccd 100644
--- a/subprojects/capstone-next.wrap
+++ b/subprojects/capstone-next.wrap
@@ -1,6 +1,6 @@
 [wrap-git]
 url = https://github.com/imbillow/capstone.git
-revision = bd401889132d2c5215cba1b9c3ca91035059db49
+revision = 4970c4abb10fe53f7df46d46a045c0a3d999e510
 directory = capstone-next
 patch_directory = capstone-next
 depth = 1