From 2c7d8674b10d4a5259015454e34c3a40b18c8b69 Mon Sep 17 00:00:00 2001
From: Venkatesh Srinivas <venkateshs@chromium.org>
Date: Tue, 22 Nov 2022 22:38:33 +0000
Subject: [PATCH] PerfCounters: Add support for AMD Family 15h Model 2
 (Piledriver)

Extends existing Family 15h Model 30 (Steamroller) support for
Piledriver. Piledriver supports PMCx0C4 (Retired Taken Branch
Instructions) and PMCx0C6 (Retired Far Control Transfer), just
like Model 30h. [1]

Note that PMCx0C4 counts all control flow changes, including
exceptions and interrupts. Like on 15h model 30-3Fh (Steamroller)
we subtract PMCx0C6 (Retired Far Control Transfers) to count
only regular taken branches.

[1]: https://www.amd.com/system/files/TechDocs/42301_15h_Mod_00h-0Fh_BKDG.pdf

Tested:
1) counters-test:
   vsrinivas@ubuntu:~/tmp/rr/src/counters-test$ sudo ./a.out
   Interrupted after 1000025 ticks, expected 1000000 ticks
   EXIT-SUCCESS
---
 src/PerfCounters.cc           | 4 ++--
 src/PerfCounters_x86.h        | 7 ++++---
 src/counters-test/counters.cc | 9 +++++----
 3 files changed, 11 insertions(+), 9 deletions(-)

diff --git a/src/PerfCounters.cc b/src/PerfCounters.cc
index 88ce8021acb..d2f91cf3cb3 100644
--- a/src/PerfCounters.cc
+++ b/src/PerfCounters.cc
@@ -100,7 +100,7 @@ enum CpuMicroarch {
   IntelMeteorLake,
   LastIntel = IntelMeteorLake,
   FirstAMD,
-  AMDF15R30 = FirstAMD,
+  AMDF15 = FirstAMD,
   AMDZen,
   AMDZen2,
   AMDZen3,
@@ -200,7 +200,7 @@ static const PmuConfig pmu_configs[] = {
   { IntelWestmere, "Intel Westmere", 0x5101c4, 0, 0, 100, PMU_TICKS_RCB },
   { IntelPenryn, "Intel Penryn", 0, 0, 0, 100, 0 },
   { IntelMerom, "Intel Merom", 0, 0, 0, 100, 0 },
-  { AMDF15R30, "AMD Family 15h Revision 30h", 0xc4, 0xc6, 0, 250, PMU_TICKS_TAKEN_BRANCHES },
+  { AMDF15, "AMD Family 15h", 0xc4, 0xc6, 0, 250, PMU_TICKS_TAKEN_BRANCHES },
   // 0xd1 == RETIRED_CONDITIONAL_BRANCH_INSTRUCTIONS - Number of retired conditional branch instructions
   // 0x2c == INTERRUPT_TAKEN - Counts the number of interrupts taken
   // Both counters are available on all Zen microarchitecures so far.
diff --git a/src/PerfCounters_x86.h b/src/PerfCounters_x86.h
index 9a6ce10b19e..76c35d67cc9 100644
--- a/src/PerfCounters_x86.h
+++ b/src/PerfCounters_x86.h
@@ -96,15 +96,16 @@ static CpuMicroarch compute_cpu_microarch() {
       return IntelEmeraldRapid;
     case 0xa06a0:
       return IntelMeteorLake;
-    case 0x30f00:
-      return AMDF15R30;
+    case 0xf20:  // Piledriver
+    case 0x30f00:  // Steamroller
+      return AMDF15;
     case 0x00f10: // A8-3530MX, Naples, Whitehaven, Summit Ridge, Snowy Owl (Zen), Milan (Zen 3) (UNTESTED)
       if (ext_family == 8) {
         return AMDZen;
       } else if (ext_family == 0xa) {
         return AMDZen3;
       } else if (ext_family == 3) {
-        return AMDF15R30;
+        return AMDF15;
       }
       break;
     case 0x00f80: // Colfax, Pinnacle Ridge (Zen+), Chagall (Zen3) (UNTESTED)
diff --git a/src/counters-test/counters.cc b/src/counters-test/counters.cc
index 88088fb5b09..9af7f589c11 100644
--- a/src/counters-test/counters.cc
+++ b/src/counters-test/counters.cc
@@ -67,7 +67,7 @@ enum CpuMicroarch {
   IntelSapphireRapid,
   LastIntel = IntelSapphireRapid,
   FirstAMD,
-  AMDF15R30 = FirstAMD,
+  AMDF15 = FirstAMD,
   AMDZen,
   LastAMD = AMDZen,
   FirstARM,
@@ -156,7 +156,7 @@ static const PmuConfig pmu_configs[] = {
   { IntelWestmere, "Intel Westmere", 0x5101c4, 0, 0, 100, PMU_TICKS_RCB },
   { IntelPenryn, "Intel Penryn", 0, 0, 0, 100, 0 },
   { IntelMerom, "Intel Merom", 0, 0, 0, 100, 0 },
-  { AMDF15R30, "AMD Family 15h Revision 30h", 0xc4, 0xc6, 0, 250, PMU_TICKS_TAKEN_BRANCHES },
+  { AMDF15, "AMD Family 15h", 0xc4, 0xc6, 0, 250, PMU_TICKS_TAKEN_BRANCHES },
   // 0xd1 == RETIRED_CONDITIONAL_BRANCH_INSTRUCTIONS - Number of retired conditional branch instructions
   // 0x2c == INTERRUPT_TAKEN - Counts the number of interrupts taken
   // Both counters are available on Zen, Zen+ and Zen2.
@@ -335,8 +335,9 @@ static CpuMicroarch compute_cpu_microarch(void) {
       return IntelRaptorlake;
     case 0x806f0:
       return IntelSapphireRapid;
+    case 0xf20:
     case 0x30f00:
-      return AMDF15R30;
+      return AMDF15;
     case 0x00f10: // Naples, Whitehaven, Summit Ridge, Snowy Owl (Zen), Milan (Zen 3) (UNTESTED)
     case 0x10f10: // Raven Ridge, Great Horned Owl (Zen) (UNTESTED)
     case 0x10f80: // Banded Kestrel (Zen), Picasso (Zen+) (UNTESTED)
@@ -350,7 +351,7 @@ static CpuMicroarch compute_cpu_microarch(void) {
       if (ext_family == 8 || ext_family == 0xa) {
         return AMDZen;
       } else if (ext_family == 3) {
-        return AMDF15R30;
+        return AMDF15;
       }
       break;
     case 0x20f10: // Vermeer (Zen 3)