From 976b34ced041d05a26320d8e9a6fc834595f811e Mon Sep 17 00:00:00 2001 From: Henri Lunnikivi Date: Wed, 19 Feb 2025 14:22:43 +0200 Subject: [PATCH 1/7] riscv: make mcycle & minstret low bits writable The RISC-V Instruction Set Manual Volume II: Privileged Architecture 20240411 specifies mcycle and minstret as "MRW" for read-write, instead of "MRO" for read-only. --- riscv/src/register/mcycle.rs | 1 + riscv/src/register/minstret.rs | 1 + 2 files changed, 2 insertions(+) diff --git a/riscv/src/register/mcycle.rs b/riscv/src/register/mcycle.rs index 0ab8dfc3..89e28e29 100644 --- a/riscv/src/register/mcycle.rs +++ b/riscv/src/register/mcycle.rs @@ -1,4 +1,5 @@ //! mcycle register read_csr_as_usize!(0xB00); +write_csr_as_usize!(0xB00); read_composite_csr!(super::mcycleh::read(), read()); diff --git a/riscv/src/register/minstret.rs b/riscv/src/register/minstret.rs index 17ba0d6b..53c38a0a 100644 --- a/riscv/src/register/minstret.rs +++ b/riscv/src/register/minstret.rs @@ -1,4 +1,5 @@ //! minstret register read_csr_as_usize!(0xB02); +write_csr_as_usize!(0xB02); read_composite_csr!(super::minstreth::read(), read()); From dc00b03defabc563dc524902145e4e197d05db4a Mon Sep 17 00:00:00 2001 From: Henri Lunnikivi Date: Wed, 19 Feb 2025 16:28:20 +0200 Subject: [PATCH 2/7] riscv: make mcycle & minstret high bits writable --- riscv/src/register/mcycleh.rs | 1 + riscv/src/register/minstreth.rs | 1 + 2 files changed, 2 insertions(+) diff --git a/riscv/src/register/mcycleh.rs b/riscv/src/register/mcycleh.rs index 31ca70cb..57036112 100644 --- a/riscv/src/register/mcycleh.rs +++ b/riscv/src/register/mcycleh.rs @@ -1,3 +1,4 @@ //! mcycleh register read_csr_as_usize_rv32!(0xB80); +write_csr_as_usize_rv32!(0xB80); diff --git a/riscv/src/register/minstreth.rs b/riscv/src/register/minstreth.rs index 5548399f..efab45f2 100644 --- a/riscv/src/register/minstreth.rs +++ b/riscv/src/register/minstreth.rs @@ -1,3 +1,4 @@ //! minstreth register read_csr_as_usize_rv32!(0xB82); +write_csr_as_usize_rv32!(0xB82); From 87e4408e458e902b8a200ed3e7ce71cbbbd5ee0a Mon Sep 17 00:00:00 2001 From: Henri Lunnikivi Date: Wed, 19 Feb 2025 17:09:31 +0200 Subject: [PATCH 3/7] riscv: add composite write macro util --- riscv/src/register/macros.rs | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/riscv/src/register/macros.rs b/riscv/src/register/macros.rs index 74793ca0..b97dace1 100644 --- a/riscv/src/register/macros.rs +++ b/riscv/src/register/macros.rs @@ -449,6 +449,30 @@ macro_rules! read_composite_csr { }; } +/// Convenience macro to write a composite value to a CSR register. +/// +/// - `RV32`: writes 32-bits into `hi` and 32-bits into `lo` to create a 64-bit value +/// - `RV64`: writes a 64-bit value into `lo` +#[macro_export] +macro_rules! write_composite_csr { + ($hi:expr, $lo:expr) => { + /// Writes the CSR as a 64-bit value + #[inline] + pub unsafe fn write64(bits: u64) { + match () { + #[cfg(target_arch = "riscv32")] + () => { + $hi((bits >> 32) as usize); + $lo(bits as usize); + } + + #[cfg(not(target_arch = "riscv32"))] + () => $lo(bits as usize), + } + } + }; +} + macro_rules! set_pmp { () => { /// Set the pmp configuration corresponding to the index. From 72d0527ba9f7db3d6cc7020f2ff6a1d2a5353f9c Mon Sep 17 00:00:00 2001 From: Henri Lunnikivi Date: Wed, 19 Feb 2025 17:09:46 +0200 Subject: [PATCH 4/7] riscv: impl composite write for mcycle, minstret --- riscv/src/register/mcycle.rs | 1 + riscv/src/register/minstret.rs | 1 + 2 files changed, 2 insertions(+) diff --git a/riscv/src/register/mcycle.rs b/riscv/src/register/mcycle.rs index 89e28e29..77c5ef5e 100644 --- a/riscv/src/register/mcycle.rs +++ b/riscv/src/register/mcycle.rs @@ -3,3 +3,4 @@ read_csr_as_usize!(0xB00); write_csr_as_usize!(0xB00); read_composite_csr!(super::mcycleh::read(), read()); +write_composite_csr!(|bits| super::mcycleh::write(bits), |bits| write(bits)); diff --git a/riscv/src/register/minstret.rs b/riscv/src/register/minstret.rs index 53c38a0a..71110491 100644 --- a/riscv/src/register/minstret.rs +++ b/riscv/src/register/minstret.rs @@ -3,3 +3,4 @@ read_csr_as_usize!(0xB02); write_csr_as_usize!(0xB02); read_composite_csr!(super::minstreth::read(), read()); +write_composite_csr!(|bits| super::minstreth::write(bits), |bits| write(bits)); From 45af14d73ff3d246f9e3ec8625ab1d9e3a946ef4 Mon Sep 17 00:00:00 2001 From: Henri Lunnikivi Date: Wed, 19 Feb 2025 14:25:37 +0200 Subject: [PATCH 5/7] riscv: update changelog --- riscv/CHANGELOG.md | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/riscv/CHANGELOG.md b/riscv/CHANGELOG.md index 14120045..22dd087e 100644 --- a/riscv/CHANGELOG.md +++ b/riscv/CHANGELOG.md @@ -7,6 +7,11 @@ and this project adheres to [Semantic Versioning](http://semver.org/). ## [Unreleased] +### Added + +- CSR helper macro `write_composite_csr` for writing 64-bit CSRs on 32-bit targets. +- Write utilities for `mcycle`, `minstret` + ## [v0.13.0] - 2025-02-18 ### Added From abb6f338e1a10cae6868c5026794edb54c460c43 Mon Sep 17 00:00:00 2001 From: Henri Lunnikivi Date: Thu, 20 Feb 2025 17:13:21 +0200 Subject: [PATCH 6/7] riscv: simplify macro call in riscv/src/register/mcycle.rs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Co-authored-by: Román Cárdenas Rodríguez --- riscv/src/register/mcycle.rs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/riscv/src/register/mcycle.rs b/riscv/src/register/mcycle.rs index 77c5ef5e..70c10f57 100644 --- a/riscv/src/register/mcycle.rs +++ b/riscv/src/register/mcycle.rs @@ -3,4 +3,4 @@ read_csr_as_usize!(0xB00); write_csr_as_usize!(0xB00); read_composite_csr!(super::mcycleh::read(), read()); -write_composite_csr!(|bits| super::mcycleh::write(bits), |bits| write(bits)); +write_composite_csr!(super::mcycleh::write, write); From 75c0048111517e874c2a66883e8309cdce6dab04 Mon Sep 17 00:00:00 2001 From: Henri Lunnikivi Date: Thu, 20 Feb 2025 17:13:33 +0200 Subject: [PATCH 7/7] riscv: simplify macro call in riscv/src/register/minstret.rs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Co-authored-by: Román Cárdenas Rodríguez --- riscv/src/register/minstret.rs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/riscv/src/register/minstret.rs b/riscv/src/register/minstret.rs index 71110491..46a4e6b2 100644 --- a/riscv/src/register/minstret.rs +++ b/riscv/src/register/minstret.rs @@ -3,4 +3,4 @@ read_csr_as_usize!(0xB02); write_csr_as_usize!(0xB02); read_composite_csr!(super::minstreth::read(), read()); -write_composite_csr!(|bits| super::minstreth::write(bits), |bits| write(bits)); +write_composite_csr!(super::minstreth::write, write);