\ No newline at end of file
diff --git a/core_simd/simd/struct.Simd.html b/core_simd/simd/struct.Simd.html
index d87c405bcff..ffffb5077b2 100644
--- a/core_simd/simd/struct.Simd.html
+++ b/core_simd/simd/struct.Simd.html
@@ -117,25 +117,25 @@
🔬This is a nightly-only experimental API. (portable_simd)
Reads contiguous elements from slice. Elements are read so long as they’re in-bounds for
the slice. Otherwise, the default value for the element type is returned.
🔬This is a nightly-only experimental API. (portable_simd)
Reads contiguous elements from slice. Elements are read so long as they’re in-bounds for
the slice. Otherwise, the corresponding value from or is passed through.
🔬This is a nightly-only experimental API. (portable_simd)
Reads from potentially discontiguous indices in slice to construct a SIMD vector.
If an index is out-of-bounds, the element is instead selected from the or vector.
§Examples// The out-of-bounds index has been masked, so it's safe to gather now.
let result = unsafe { Simd::gather_select_unchecked(&vec, enable, idxs, alt) };
assert_eq!(result, Simd::from_array([-5, 13, 10, -2]));
-
🔬This is a nightly-only experimental API. (portable_simd)
Writes the values in a SIMD vector to potentially discontiguous indices in slice.
If an index is out-of-bounds, the write is suppressed without panicking.
If two elements in the scattered vector would write to the same index
only the last element is guaranteed to actually be written.
@@ -347,7 +347,7 @@
§Examples&mut vec, idxs); // two logical writes means the last wins.
assert_eq!(vec, vec![124, 11, 12, 82, 14, 15, 16, 17, 18]);
Strictly, it is valid to impl if the vector will not be miscompiled.
Practically, it is user-unfriendly to impl it if the vector won’t compile,
even when no soundness guarantees are broken by allowing the user to try.
-
\ No newline at end of file
diff --git a/src/core_simd/lib.rs.html b/src/core_simd/lib.rs.html
index b27a428d920..0a712705f78 100644
--- a/src/core_simd/lib.rs.html
+++ b/src/core_simd/lib.rs.html
@@ -51,8 +51,10 @@
🔬This is a nightly-only experimental API. (portable_simd)
Rotates the vector such that the first OFFSET elements of the slice move to the end\nwhile the last self.len() - OFFSET elements move to the front. After calling rotate_elements_left,\nthe element previously at index OFFSET will become the first element in the slice.
🔬This is a nightly-only experimental API. (portable_simd)
Rotates the vector such that the first self.len() - OFFSET elements of the vector move to\nthe end while the last OFFSET elements move to the front. After calling rotate_elements_right,\nthe element previously at index self.len() - OFFSET will become the first element in the slice.
🔬This is a nightly-only experimental API. (portable_simd)
Reads contiguous elements from slice. Elements are read so long as they’re in-bounds for\nthe slice. Otherwise, the default value for the element type is returned.
🔬This is a nightly-only experimental API. (portable_simd)
Reads contiguous elements from slice. Elements are read so long as they’re in-bounds for\nthe slice. Otherwise, the corresponding value from or is passed through.
🔬This is a nightly-only experimental API. (portable_simd)
Reads contiguous elements from slice. Each element is read from memory if its\ncorresponding element in enable is true.
\n
When the element is disabled or out of bounds for the slice, that memory location\nis not accessed and the corresponding value from or is passed through.
🔬This is a nightly-only experimental API. (portable_simd)
Reads contiguous elements from slice. Each element is read from memory if its\ncorresponding element in enable is true.
\n
When the element is disabled or out of bounds for the slice, that memory location\nis not accessed and the corresponding value from or is passed through.
🔬This is a nightly-only experimental API. (portable_simd)
Reads from potentially discontiguous indices in slice to construct a SIMD vector.\nIf an index is out-of-bounds, the element is instead selected from the or vector.
🔬This is a nightly-only experimental API. (portable_simd)
Reads from indices in slice to construct a SIMD vector.\nThe mask enables all true indices and disables all false indices.\nIf an index is disabled or is out-of-bounds, the element is selected from the or vector.
🔬This is a nightly-only experimental API. (portable_simd)
Reads from indices in slice to construct a SIMD vector.\nThe mask enables all true indices and disables all false indices.\nIf an index is disabled, the element is selected from the or vector.
let vec: Vec<i32> = vec![10, 11, 12, 13, 14, 15, 16, 17, 18];\nlet idxs = Simd::from_array([9, 3, 0, 5]); // Includes an out-of-bounds index\nlet alt = Simd::from_array([-5, -4, -3, -2]);\nlet enable = Mask::from_array([true, true, true, false]); // Includes a masked element\n// If this mask was used to gather, it would be unsound. Let's fix that.\nlet enable = enable & idxs.simd_lt(Simd::splat(vec.len()));\n\n// The out-of-bounds index has been masked, so it's safe to gather now.\nlet result = unsafe { Simd::gather_select_unchecked(&vec, enable, idxs, alt) };\nassert_eq!(result, Simd::from_array([-5, 13, 10, -2]));
🔬This is a nightly-only experimental API. (portable_simd)
Conditionally read elementwise from pointers into a SIMD vector.\nThe mask enables all true pointers and disables all false pointers.\nIf a pointer is disabled, the element is selected from the or vector,\nand no read is performed.
🔬This is a nightly-only experimental API. (portable_simd)
Conditionally write contiguous elements to slice. The enable mask controls\nwhich elements are written, as long as they’re in-bounds of the slice.\nIf the element is disabled or out of bounds, no memory access to that location\nis made.
🔬This is a nightly-only experimental API. (portable_simd)
Conditionally write contiguous elements starting from ptr.\nThe enable mask controls which elements are written.\nWhen disabled, the memory location corresponding to that element is not accessed.
🔬This is a nightly-only experimental API. (portable_simd)
Writes the values in a SIMD vector to potentially discontiguous indices in slice.\nIf an index is out-of-bounds, the write is suppressed without panicking.\nIf two elements in the scattered vector would write to the same index\nonly the last element is guaranteed to actually be written.
🔬This is a nightly-only experimental API. (portable_simd)
Writes values from a SIMD vector to multiple potentially discontiguous indices in slice.\nThe mask enables all true indices and disables all false indices.\nIf an enabled index is out-of-bounds, the write is suppressed without panicking.\nIf two enabled elements in the scattered vector would write to the same index,\nonly the last element is guaranteed to actually be written.
🔬This is a nightly-only experimental API. (portable_simd)
Writes values from a SIMD vector to multiple potentially discontiguous indices in slice.\nThe mask enables all true indices and disables all false indices.\nIf two enabled elements in the scattered vector would write to the same index,\nonly the last element is guaranteed to actually be written.
let mut vec: Vec<i32> = vec![10, 11, 12, 13, 14, 15, 16, 17, 18];\nlet idxs = Simd::from_array([9, 3, 0, 0]);\nlet vals = Simd::from_array([-27, 82, -41, 124]);\nlet enable = Mask::from_array([true, true, true, false]); // Masks the final index\n// If this mask was used to scatter, it would be unsound. Let's fix that.\nlet enable = enable & idxs.simd_lt(Simd::splat(vec.len()));\n\n// We have masked the OOB index, so it's safe to scatter now.\nunsafe { vals.scatter_select_unchecked(&mut vec, enable, idxs); }\n// The second write to index 0 was masked, thus omitted.\nassert_eq!(vec, vec![-41, 11, 12, 82, 14, 15, 16, 17, 18]);
🔬This is a nightly-only experimental API. (portable_simd)
Conditionally write pointers elementwise into a SIMD vector.\nThe mask enables all true pointers and disables all false pointers.\nIf a pointer is disabled, the write to its pointee is skipped.
🔬This is a nightly-only experimental API. (portable_simd)
Swizzle a vector of bytes according to the index vector.\nIndices within range select the appropriate byte.\nIndices “out of bounds” instead select 0.
\n
Note that the current implementation is selected during build-time\nof the standard library, so cargo build -Zbuild-std may be necessary\nto unlock better performance, especially for larger vectors.\nA planned compiler improvement will enable using #[target_feature] instead.
🔬This is a nightly-only experimental API. (portable_simd)
Reverses the order of bits in each elemnent.\nThe least significant bit becomes the most significant bit, second least-significant bit becomes second most-significant bit, etc.
🔬This is a nightly-only experimental API. (portable_simd)
Reverses the order of bits in each elemnent.\nThe least significant bit becomes the most significant bit, second least-significant bit becomes second most-significant bit, etc.
🔬This is a nightly-only experimental API. (portable_simd)
Reverses the order of bits in each elemnent.\nThe least significant bit becomes the most significant bit, second least-significant bit becomes second most-significant bit, etc.
🔬This is a nightly-only experimental API. (portable_simd)
Reverses the order of bits in each elemnent.\nThe least significant bit becomes the most significant bit, second least-significant bit becomes second most-significant bit, etc.
🔬This is a nightly-only experimental API. (portable_simd)
Reverses the order of bits in each elemnent.\nThe least significant bit becomes the most significant bit, second least-significant bit becomes second most-significant bit, etc.
🔬This is a nightly-only experimental API. (portable_simd)
Reverses the order of bits in each elemnent.\nThe least significant bit becomes the most significant bit, second least-significant bit becomes second most-significant bit, etc.
🔬This is a nightly-only experimental API. (portable_simd)
Reverses the order of bits in each elemnent.\nThe least significant bit becomes the most significant bit, second least-significant bit becomes second most-significant bit, etc.
🔬This is a nightly-only experimental API. (portable_simd)
Reverses the order of bits in each elemnent.\nThe least significant bit becomes the most significant bit, second least-significant bit becomes second most-significant bit, etc.
🔬This is a nightly-only experimental API. (portable_simd)
Reverses the order of bits in each elemnent.\nThe least significant bit becomes the most significant bit, second least-significant bit becomes second most-significant bit, etc.
🔬This is a nightly-only experimental API. (portable_simd)
Reverses the order of bits in each elemnent.\nThe least significant bit becomes the most significant bit, second least-significant bit becomes second most-significant bit, etc.
🔬This is a nightly-only experimental API. (portable_simd)
Rotates the vector such that the first OFFSET elements of the slice move to the end\nwhile the last self.len() - OFFSET elements move to the front. After calling rotate_elements_left,\nthe element previously at index OFFSET will become the first element in the slice.
🔬This is a nightly-only experimental API. (portable_simd)
Rotates the vector such that the first self.len() - OFFSET elements of the vector move to\nthe end while the last OFFSET elements move to the front. After calling rotate_elements_right,\nthe element previously at index self.len() - OFFSET will become the first element in the slice.
🔬This is a nightly-only experimental API. (portable_simd)
Reads contiguous elements from slice. Elements are read so long as they’re in-bounds for\nthe slice. Otherwise, the default value for the element type is returned.
🔬This is a nightly-only experimental API. (portable_simd)
Reads contiguous elements from slice. Elements are read so long as they’re in-bounds for\nthe slice. Otherwise, the corresponding value from or is passed through.
🔬This is a nightly-only experimental API. (portable_simd)
Reads contiguous elements from slice. Each element is read from memory if its\ncorresponding element in enable is true.
\n
When the element is disabled or out of bounds for the slice, that memory location\nis not accessed and the corresponding value from or is passed through.
🔬This is a nightly-only experimental API. (portable_simd)
Reads contiguous elements from slice. Each element is read from memory if its\ncorresponding element in enable is true.
\n
When the element is disabled or out of bounds for the slice, that memory location\nis not accessed and the corresponding value from or is passed through.
🔬This is a nightly-only experimental API. (portable_simd)
Reads from potentially discontiguous indices in slice to construct a SIMD vector.\nIf an index is out-of-bounds, the element is instead selected from the or vector.
🔬This is a nightly-only experimental API. (portable_simd)
Reads from indices in slice to construct a SIMD vector.\nThe mask enables all true indices and disables all false indices.\nIf an index is disabled or is out-of-bounds, the element is selected from the or vector.
🔬This is a nightly-only experimental API. (portable_simd)
Reads from indices in slice to construct a SIMD vector.\nThe mask enables all true indices and disables all false indices.\nIf an index is disabled, the element is selected from the or vector.
let vec: Vec<i32> = vec![10, 11, 12, 13, 14, 15, 16, 17, 18];\nlet idxs = Simd::from_array([9, 3, 0, 5]); // Includes an out-of-bounds index\nlet alt = Simd::from_array([-5, -4, -3, -2]);\nlet enable = Mask::from_array([true, true, true, false]); // Includes a masked element\n// If this mask was used to gather, it would be unsound. Let's fix that.\nlet enable = enable & idxs.simd_lt(Simd::splat(vec.len()));\n\n// The out-of-bounds index has been masked, so it's safe to gather now.\nlet result = unsafe { Simd::gather_select_unchecked(&vec, enable, idxs, alt) };\nassert_eq!(result, Simd::from_array([-5, 13, 10, -2]));
🔬This is a nightly-only experimental API. (portable_simd)
Conditionally read elementwise from pointers into a SIMD vector.\nThe mask enables all true pointers and disables all false pointers.\nIf a pointer is disabled, the element is selected from the or vector,\nand no read is performed.
🔬This is a nightly-only experimental API. (portable_simd)
Conditionally write contiguous elements to slice. The enable mask controls\nwhich elements are written, as long as they’re in-bounds of the slice.\nIf the element is disabled or out of bounds, no memory access to that location\nis made.
🔬This is a nightly-only experimental API. (portable_simd)
Conditionally write contiguous elements starting from ptr.\nThe enable mask controls which elements are written.\nWhen disabled, the memory location corresponding to that element is not accessed.
🔬This is a nightly-only experimental API. (portable_simd)
Writes the values in a SIMD vector to potentially discontiguous indices in slice.\nIf an index is out-of-bounds, the write is suppressed without panicking.\nIf two elements in the scattered vector would write to the same index\nonly the last element is guaranteed to actually be written.
🔬This is a nightly-only experimental API. (portable_simd)
Writes values from a SIMD vector to multiple potentially discontiguous indices in slice.\nThe mask enables all true indices and disables all false indices.\nIf an enabled index is out-of-bounds, the write is suppressed without panicking.\nIf two enabled elements in the scattered vector would write to the same index,\nonly the last element is guaranteed to actually be written.
🔬This is a nightly-only experimental API. (portable_simd)
Writes values from a SIMD vector to multiple potentially discontiguous indices in slice.\nThe mask enables all true indices and disables all false indices.\nIf two enabled elements in the scattered vector would write to the same index,\nonly the last element is guaranteed to actually be written.
let mut vec: Vec<i32> = vec![10, 11, 12, 13, 14, 15, 16, 17, 18];\nlet idxs = Simd::from_array([9, 3, 0, 0]);\nlet vals = Simd::from_array([-27, 82, -41, 124]);\nlet enable = Mask::from_array([true, true, true, false]); // Masks the final index\n// If this mask was used to scatter, it would be unsound. Let's fix that.\nlet enable = enable & idxs.simd_lt(Simd::splat(vec.len()));\n\n// We have masked the OOB index, so it's safe to scatter now.\nunsafe { vals.scatter_select_unchecked(&mut vec, enable, idxs); }\n// The second write to index 0 was masked, thus omitted.\nassert_eq!(vec, vec![-41, 11, 12, 82, 14, 15, 16, 17, 18]);
🔬This is a nightly-only experimental API. (portable_simd)
Conditionally write pointers elementwise into a SIMD vector.\nThe mask enables all true pointers and disables all false pointers.\nIf a pointer is disabled, the write to its pointee is skipped.
🔬This is a nightly-only experimental API. (portable_simd)
Swizzle a vector of bytes according to the index vector.\nIndices within range select the appropriate byte.\nIndices “out of bounds” instead select 0.
\n
Note that the current implementation is selected during build-time\nof the standard library, so cargo build -Zbuild-std may be necessary\nto unlock better performance, especially for larger vectors.\nA planned compiler improvement will enable using #[target_feature] instead.
🔬This is a nightly-only experimental API. (portable_simd)
Reverses the order of bits in each elemnent.\nThe least significant bit becomes the most significant bit, second least-significant bit becomes second most-significant bit, etc.
🔬This is a nightly-only experimental API. (portable_simd)
Reverses the order of bits in each elemnent.\nThe least significant bit becomes the most significant bit, second least-significant bit becomes second most-significant bit, etc.
🔬This is a nightly-only experimental API. (portable_simd)
Reverses the order of bits in each elemnent.\nThe least significant bit becomes the most significant bit, second least-significant bit becomes second most-significant bit, etc.
🔬This is a nightly-only experimental API. (portable_simd)
Reverses the order of bits in each elemnent.\nThe least significant bit becomes the most significant bit, second least-significant bit becomes second most-significant bit, etc.
🔬This is a nightly-only experimental API. (portable_simd)
Reverses the order of bits in each elemnent.\nThe least significant bit becomes the most significant bit, second least-significant bit becomes second most-significant bit, etc.
🔬This is a nightly-only experimental API. (portable_simd)
Reverses the order of bits in each elemnent.\nThe least significant bit becomes the most significant bit, second least-significant bit becomes second most-significant bit, etc.
🔬This is a nightly-only experimental API. (portable_simd)
Reverses the order of bits in each elemnent.\nThe least significant bit becomes the most significant bit, second least-significant bit becomes second most-significant bit, etc.
🔬This is a nightly-only experimental API. (portable_simd)
Reverses the order of bits in each elemnent.\nThe least significant bit becomes the most significant bit, second least-significant bit becomes second most-significant bit, etc.
🔬This is a nightly-only experimental API. (portable_simd)
Reverses the order of bits in each elemnent.\nThe least significant bit becomes the most significant bit, second least-significant bit becomes second most-significant bit, etc.
🔬This is a nightly-only experimental API. (portable_simd)
Reverses the order of bits in each elemnent.\nThe least significant bit becomes the most significant bit, second least-significant bit becomes second most-significant bit, etc.
","Eq","core_simd::core_simd::alias::i8x1","core_simd::core_simd::alias::i8x2","core_simd::core_simd::alias::i8x4","core_simd::core_simd::alias::i8x8","core_simd::core_simd::alias::i8x16","core_simd::core_simd::alias::i8x32","core_simd::core_simd::alias::i8x64","core_simd::core_simd::alias::i16x1","core_simd::core_simd::alias::i16x2","core_simd::core_simd::alias::i16x4","core_simd::core_simd::alias::i16x8","core_simd::core_simd::alias::i16x16","core_simd::core_simd::alias::i16x32","core_simd::core_simd::alias::i16x64","core_simd::core_simd::alias::i32x1","core_simd::core_simd::alias::i32x2","core_simd::core_simd::alias::i32x4","core_simd::core_simd::alias::i32x8","core_simd::core_simd::alias::i32x16","core_simd::core_simd::alias::i32x32","core_simd::core_simd::alias::i32x64","core_simd::core_simd::alias::i64x1","core_simd::core_simd::alias::i64x2","core_simd::core_simd::alias::i64x4","core_simd::core_simd::alias::i64x8","core_simd::core_simd::alias::i64x16","core_simd::core_simd::alias::i64x32","core_simd::core_simd::alias::i64x64","core_simd::core_simd::alias::isizex1","core_simd::core_simd::alias::isizex2","core_simd::core_simd::alias::isizex4","core_simd::core_simd::alias::isizex8","core_simd::core_simd::alias::isizex16","core_simd::core_simd::alias::isizex32","core_simd::core_simd::alias::isizex64","core_simd::core_simd::alias::u8x1","core_simd::core_simd::alias::u8x2","core_simd::core_simd::alias::u8x4","core_simd::core_simd::alias::u8x8","core_simd::core_simd::alias::u8x16","core_simd::core_simd::alias::u8x32","core_simd::core_simd::alias::u8x64","core_simd::core_simd::alias::u16x1","core_simd::core_simd::alias::u16x2","core_simd::core_simd::alias::u16x4","core_simd::core_simd::alias::u16x8","core_simd::core_simd::alias::u16x16","core_simd::core_simd::alias::u16x32","core_simd::core_simd::alias::u16x64","core_simd::core_simd::alias::u32x1","core_simd::core_simd::alias::u32x2","core_simd::core_simd::alias::u32x4","core_simd::core_simd::alias::u32x8","core_simd::core_simd::alias::u32x16","core_simd::core_simd::alias::u32x32","core_simd::core_simd::alias::u32x64","core_simd::core_simd::alias::u64x1","core_simd::core_simd::alias::u64x2","core_simd::core_simd::alias::u64x4","core_simd::core_simd::alias::u64x8","core_simd::core_simd::alias::u64x16","core_simd::core_simd::alias::u64x32","core_simd::core_simd::alias::u64x64","core_simd::core_simd::alias::usizex1","core_simd::core_simd::alias::usizex2","core_simd::core_simd::alias::usizex4","core_simd::core_simd::alias::usizex8","core_simd::core_simd::alias::usizex16","core_simd::core_simd::alias::usizex32","core_simd::core_simd::alias::usizex64","core_simd::core_simd::alias::f32x1","core_simd::core_simd::alias::f32x2","core_simd::core_simd::alias::f32x4","core_simd::core_simd::alias::f32x8","core_simd::core_simd::alias::f32x16","core_simd::core_simd::alias::f32x32","core_simd::core_simd::alias::f32x64","core_simd::core_simd::alias::f64x1","core_simd::core_simd::alias::f64x2","core_simd::core_simd::alias::f64x4","core_simd::core_simd::alias::f64x8","core_simd::core_simd::alias::f64x16","core_simd::core_simd::alias::f64x32","core_simd::core_simd::alias::f64x64"]]
};if (window.register_type_impls) {window.register_type_impls(type_impls);} else {window.pending_type_impls = type_impls;}})()
\ No newline at end of file