From ddc57e564a86c971cdbb781749263a20d07948dd Mon Sep 17 00:00:00 2001 From: Nikita Popov Date: Wed, 9 Jul 2025 13:01:56 +0200 Subject: [PATCH 1/5] Update to LLVM 21 --- .gitmodules | 4 ++-- src/llvm-project | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/.gitmodules b/.gitmodules index 439fde6d76601..a6b053e88ee99 100644 --- a/.gitmodules +++ b/.gitmodules @@ -24,8 +24,8 @@ shallow = true [submodule "src/llvm-project"] path = src/llvm-project - url = https://github.com/rust-lang/llvm-project.git - branch = rustc/20.1-2025-07-13 + url = https://github.com/nikic/llvm-project.git + branch = rust-llvm-21 shallow = true [submodule "src/doc/embedded-book"] path = src/doc/embedded-book diff --git a/src/llvm-project b/src/llvm-project index d3c793b025645..a236014ec76c4 160000 --- a/src/llvm-project +++ b/src/llvm-project @@ -1 +1 @@ -Subproject commit d3c793b025645a4565ac59aceb30d2d116ff1a41 +Subproject commit a236014ec76c419969d8b6c7ad989de10259f5f9 From 39eb20c9436358d7ee00e6f4bae98d033e79a3cc Mon Sep 17 00:00:00 2001 From: Nikita Popov Date: Wed, 9 Jul 2025 14:18:37 +0200 Subject: [PATCH 2/5] Update AMDGPU data layout --- compiler/rustc_codegen_llvm/src/context.rs | 5 +++++ compiler/rustc_target/src/spec/targets/amdgcn_amd_amdhsa.rs | 2 +- 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/compiler/rustc_codegen_llvm/src/context.rs b/compiler/rustc_codegen_llvm/src/context.rs index 6a23becaa96ff..34bed2a1d2a3d 100644 --- a/compiler/rustc_codegen_llvm/src/context.rs +++ b/compiler/rustc_codegen_llvm/src/context.rs @@ -207,6 +207,11 @@ pub(crate) unsafe fn create_module<'ll>( // LLVM 21 updated the default layout on nvptx: https://github.com/llvm/llvm-project/pull/124961 target_data_layout = target_data_layout.replace("e-p6:32:32-i64", "e-i64"); } + if sess.target.arch == "amdgpu" { + // LLVM 21 adds the address width for address space 8. + // See https://github.com/llvm/llvm-project/pull/139419 + target_data_layout = target_data_layout.replace("p8:128:128:128:48", "p8:128:128") + } } // Ensure the data-layout values hardcoded remain the defaults. diff --git a/compiler/rustc_target/src/spec/targets/amdgcn_amd_amdhsa.rs b/compiler/rustc_target/src/spec/targets/amdgcn_amd_amdhsa.rs index f20782cabb878..0d6c6194e2694 100644 --- a/compiler/rustc_target/src/spec/targets/amdgcn_amd_amdhsa.rs +++ b/compiler/rustc_target/src/spec/targets/amdgcn_amd_amdhsa.rs @@ -3,7 +3,7 @@ use crate::spec::{Cc, LinkerFlavor, Lld, PanicStrategy, Target, TargetMetadata, pub(crate) fn target() -> Target { Target { arch: "amdgpu".into(), - data_layout: "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128-p9:192:256:256:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8:9".into(), + data_layout: "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128:128:48-p9:192:256:256:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8:9".into(), llvm_target: "amdgcn-amd-amdhsa".into(), metadata: TargetMetadata { description: Some("AMD GPU".into()), From 114a70772f1e95b7bc3456ff15d862bbbe1cb3cd Mon Sep 17 00:00:00 2001 From: Nikita Popov Date: Fri, 11 Jul 2025 10:11:03 +0200 Subject: [PATCH 3/5] Pass wasm exception model to TargetOptions --- compiler/rustc_codegen_llvm/src/back/owned_target_machine.rs | 2 ++ compiler/rustc_codegen_llvm/src/back/write.rs | 4 ++++ compiler/rustc_codegen_llvm/src/llvm/ffi.rs | 1 + compiler/rustc_llvm/llvm-wrapper/PassWrapper.cpp | 5 ++++- tests/assembly/wasm_exceptions.rs | 1 - 5 files changed, 11 insertions(+), 2 deletions(-) diff --git a/compiler/rustc_codegen_llvm/src/back/owned_target_machine.rs b/compiler/rustc_codegen_llvm/src/back/owned_target_machine.rs index dfde45955906c..8e82013e94ad5 100644 --- a/compiler/rustc_codegen_llvm/src/back/owned_target_machine.rs +++ b/compiler/rustc_codegen_llvm/src/back/owned_target_machine.rs @@ -39,6 +39,7 @@ impl OwnedTargetMachine { debug_info_compression: &CStr, use_emulated_tls: bool, args_cstr_buff: &[u8], + use_wasm_eh: bool, ) -> Result> { assert!(args_cstr_buff.len() > 0); assert!( @@ -72,6 +73,7 @@ impl OwnedTargetMachine { use_emulated_tls, args_cstr_buff.as_ptr() as *const c_char, args_cstr_buff.len(), + use_wasm_eh, ) }; diff --git a/compiler/rustc_codegen_llvm/src/back/write.rs b/compiler/rustc_codegen_llvm/src/back/write.rs index 313bf6d20a662..f2acce5367f65 100644 --- a/compiler/rustc_codegen_llvm/src/back/write.rs +++ b/compiler/rustc_codegen_llvm/src/back/write.rs @@ -15,6 +15,7 @@ use rustc_codegen_ssa::back::write::{ BitcodeSection, CodegenContext, EmitObj, ModuleConfig, TargetMachineFactoryConfig, TargetMachineFactoryFn, }; +use rustc_codegen_ssa::base::wants_wasm_eh; use rustc_codegen_ssa::traits::*; use rustc_codegen_ssa::{CompiledModule, ModuleCodegen, ModuleKind}; use rustc_data_structures::profiling::SelfProfilerRef; @@ -285,6 +286,8 @@ pub(crate) fn target_machine_factory( let file_name_display_preference = sess.filename_display_preference(RemapPathScopeComponents::DEBUGINFO); + let use_wasm_eh = wants_wasm_eh(sess); + Arc::new(move |config: TargetMachineFactoryConfig| { let path_to_cstring_helper = |path: Option| -> CString { let path = path.unwrap_or_default(); @@ -321,6 +324,7 @@ pub(crate) fn target_machine_factory( &debuginfo_compression, use_emulated_tls, &args_cstr_buff, + use_wasm_eh, ) }) } diff --git a/compiler/rustc_codegen_llvm/src/llvm/ffi.rs b/compiler/rustc_codegen_llvm/src/llvm/ffi.rs index 0b1e632cbc42c..80a0e5c5accc2 100644 --- a/compiler/rustc_codegen_llvm/src/llvm/ffi.rs +++ b/compiler/rustc_codegen_llvm/src/llvm/ffi.rs @@ -2425,6 +2425,7 @@ unsafe extern "C" { UseEmulatedTls: bool, ArgsCstrBuff: *const c_char, ArgsCstrBuffLen: usize, + UseWasmEH: bool, ) -> *mut TargetMachine; pub(crate) fn LLVMRustDisposeTargetMachine(T: *mut TargetMachine); diff --git a/compiler/rustc_llvm/llvm-wrapper/PassWrapper.cpp b/compiler/rustc_llvm/llvm-wrapper/PassWrapper.cpp index cc33764e485ad..e649978780e4c 100644 --- a/compiler/rustc_llvm/llvm-wrapper/PassWrapper.cpp +++ b/compiler/rustc_llvm/llvm-wrapper/PassWrapper.cpp @@ -396,7 +396,7 @@ extern "C" LLVMTargetMachineRef LLVMRustCreateTargetMachine( bool EmitStackSizeSection, bool RelaxELFRelocations, bool UseInitArray, const char *SplitDwarfFile, const char *OutputObjFile, const char *DebugInfoCompression, bool UseEmulatedTls, - const char *ArgsCstrBuff, size_t ArgsCstrBuffLen) { + const char *ArgsCstrBuff, size_t ArgsCstrBuffLen, bool UseWasmEH) { auto OptLevel = fromRust(RustOptLevel); auto RM = fromRust(RustReloc); @@ -462,6 +462,9 @@ extern "C" LLVMTargetMachineRef LLVMRustCreateTargetMachine( Options.ThreadModel = ThreadModel::Single; } + if (UseWasmEH) + Options.ExceptionModel = ExceptionHandling::Wasm; + Options.EmitStackSizeSection = EmitStackSizeSection; if (ArgsCstrBuff != nullptr) { diff --git a/tests/assembly/wasm_exceptions.rs b/tests/assembly/wasm_exceptions.rs index f05ccfadc5858..704e8026f3f48 100644 --- a/tests/assembly/wasm_exceptions.rs +++ b/tests/assembly/wasm_exceptions.rs @@ -2,7 +2,6 @@ //@ assembly-output: emit-asm //@ compile-flags: -C target-feature=+exception-handling //@ compile-flags: -C panic=unwind -//@ compile-flags: -C llvm-args=-wasm-enable-eh #![crate_type = "lib"] #![feature(core_intrinsics)] From cd31920cea90bc107e4e14b2172bf98b9224517e Mon Sep 17 00:00:00 2001 From: Nikita Popov Date: Mon, 14 Jul 2025 10:29:05 +0200 Subject: [PATCH 4/5] Make emit-arity-indicator.rs a no_core test The presence of `@add-core-stubs` indicates that this was already intended. --- .../sanitizer/kcfi/emit-arity-indicator.rs | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/tests/assembly/sanitizer/kcfi/emit-arity-indicator.rs b/tests/assembly/sanitizer/kcfi/emit-arity-indicator.rs index b3b623b509b4b..f9966a2344690 100644 --- a/tests/assembly/sanitizer/kcfi/emit-arity-indicator.rs +++ b/tests/assembly/sanitizer/kcfi/emit-arity-indicator.rs @@ -8,6 +8,14 @@ //@ min-llvm-version: 21.0.0 #![crate_type = "lib"] +#![feature(no_core)] +#![no_core] + +extern crate minicore; + +unsafe extern "C" { + safe fn add(x: i32, y: i32) -> i32; +} pub fn add_one(x: i32) -> i32 { // CHECK-LABEL: __cfi__{{.*}}7add_one{{.*}}: @@ -23,7 +31,7 @@ pub fn add_one(x: i32) -> i32 { // CHECK-NEXT: nop // CHECK-NEXT: nop // CHECK-NEXT: mov ecx, 2628068948 - x + 1 + add(x, 1) } pub fn add_two(x: i32, _y: i32) -> i32 { @@ -40,7 +48,7 @@ pub fn add_two(x: i32, _y: i32) -> i32 { // CHECK-NEXT: nop // CHECK-NEXT: nop // CHECK-NEXT: mov edx, 2505940310 - x + 2 + add(x, 2) } pub fn do_twice(f: fn(i32) -> i32, arg: i32) -> i32 { @@ -57,5 +65,5 @@ pub fn do_twice(f: fn(i32) -> i32, arg: i32) -> i32 { // CHECK-NEXT: nop // CHECK-NEXT: nop // CHECK-NEXT: mov edx, 653723426 - f(arg) + f(arg) + add(f(arg), f(arg)) } From ab7d9df10dffcc2300f685e3ff73cda9a713f788 Mon Sep 17 00:00:00 2001 From: Nikita Popov Date: Thu, 17 Jul 2025 14:25:53 +0200 Subject: [PATCH 5/5] Try updating host toolchain In the hope that this may fix the bolt issue. --- src/ci/docker/scripts/build-clang.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/ci/docker/scripts/build-clang.sh b/src/ci/docker/scripts/build-clang.sh index 536991cc06b7d..a1e9f01d97d57 100755 --- a/src/ci/docker/scripts/build-clang.sh +++ b/src/ci/docker/scripts/build-clang.sh @@ -5,7 +5,7 @@ set -ex source shared.sh # Try to keep the LLVM version here in sync with src/ci/scripts/install-clang.sh -LLVM=llvmorg-20.1.0-rc2 +LLVM=38158a93d8d9598fb3b827b8513f67771b8fcbfd mkdir llvm-project cd llvm-project