From f3441348e09b0a617e26565e579b755d5cf87f03 Mon Sep 17 00:00:00 2001 From: khyperia Date: Wed, 11 Nov 2020 17:37:01 +0100 Subject: [PATCH 1/2] Add asm register information for SPIR-V --- compiler/rustc_codegen_llvm/src/asm.rs | 12 ++++++- compiler/rustc_target/src/asm/mod.rs | 21 ++++++++++++ compiler/rustc_target/src/asm/spirv.rs | 46 ++++++++++++++++++++++++++ 3 files changed, 78 insertions(+), 1 deletion(-) create mode 100644 compiler/rustc_target/src/asm/spirv.rs diff --git a/compiler/rustc_codegen_llvm/src/asm.rs b/compiler/rustc_codegen_llvm/src/asm.rs index d856280158f2d..f0b798d2c3868 100644 --- a/compiler/rustc_codegen_llvm/src/asm.rs +++ b/compiler/rustc_codegen_llvm/src/asm.rs @@ -12,8 +12,8 @@ use rustc_codegen_ssa::mir::place::PlaceRef; use rustc_codegen_ssa::traits::*; use rustc_data_structures::fx::FxHashMap; use rustc_hir as hir; -use rustc_middle::span_bug; use rustc_middle::ty::layout::TyAndLayout; +use rustc_middle::{bug, span_bug}; use rustc_span::{Pos, Span}; use rustc_target::abi::*; use rustc_target::asm::*; @@ -260,6 +260,7 @@ impl AsmBuilderMethods<'tcx> for Builder<'a, 'll, 'tcx> { InlineAsmArch::Nvptx64 => {} InlineAsmArch::Hexagon => {} InlineAsmArch::Mips | InlineAsmArch::Mips64 => {} + InlineAsmArch::Spirv => {} } } if !options.contains(InlineAsmOptions::NOMEM) { @@ -518,6 +519,9 @@ fn reg_to_llvm(reg: InlineAsmRegOrRegClass, layout: Option<&TyAndLayout<'tcx>>) | InlineAsmRegClass::X86(X86InlineAsmRegClass::ymm_reg) => "x", InlineAsmRegClass::X86(X86InlineAsmRegClass::zmm_reg) => "v", InlineAsmRegClass::X86(X86InlineAsmRegClass::kreg) => "^Yk", + InlineAsmRegClass::Spirv(SpirvInlineAsmRegClass::reg) => { + bug!("LLVM backend does not support SPIR-V") + } } .to_string(), } @@ -580,6 +584,9 @@ fn modifier_to_llvm( _ => unreachable!(), }, InlineAsmRegClass::X86(X86InlineAsmRegClass::kreg) => None, + InlineAsmRegClass::Spirv(SpirvInlineAsmRegClass::reg) => { + bug!("LLVM backend does not support SPIR-V") + } } } @@ -619,6 +626,9 @@ fn dummy_output_type(cx: &CodegenCx<'ll, 'tcx>, reg: InlineAsmRegClass) -> &'ll | InlineAsmRegClass::X86(X86InlineAsmRegClass::ymm_reg) | InlineAsmRegClass::X86(X86InlineAsmRegClass::zmm_reg) => cx.type_f32(), InlineAsmRegClass::X86(X86InlineAsmRegClass::kreg) => cx.type_i16(), + InlineAsmRegClass::Spirv(SpirvInlineAsmRegClass::reg) => { + bug!("LLVM backend does not support SPIR-V") + } } } diff --git a/compiler/rustc_target/src/asm/mod.rs b/compiler/rustc_target/src/asm/mod.rs index 8e60085262afd..d07087d279b3e 100644 --- a/compiler/rustc_target/src/asm/mod.rs +++ b/compiler/rustc_target/src/asm/mod.rs @@ -155,6 +155,7 @@ mod hexagon; mod mips; mod nvptx; mod riscv; +mod spirv; mod x86; pub use aarch64::{AArch64InlineAsmReg, AArch64InlineAsmRegClass}; @@ -163,6 +164,7 @@ pub use hexagon::{HexagonInlineAsmReg, HexagonInlineAsmRegClass}; pub use mips::{MipsInlineAsmReg, MipsInlineAsmRegClass}; pub use nvptx::{NvptxInlineAsmReg, NvptxInlineAsmRegClass}; pub use riscv::{RiscVInlineAsmReg, RiscVInlineAsmRegClass}; +pub use spirv::{SpirvInlineAsmReg, SpirvInlineAsmRegClass}; pub use x86::{X86InlineAsmReg, X86InlineAsmRegClass}; #[derive(Copy, Clone, Encodable, Decodable, Debug, Eq, PartialEq, Hash)] @@ -177,6 +179,7 @@ pub enum InlineAsmArch { Hexagon, Mips, Mips64, + Spirv, } impl FromStr for InlineAsmArch { @@ -194,6 +197,7 @@ impl FromStr for InlineAsmArch { "hexagon" => Ok(Self::Hexagon), "mips" => Ok(Self::Mips), "mips64" => Ok(Self::Mips64), + "spirv" => Ok(Self::Spirv), _ => Err(()), } } @@ -208,6 +212,7 @@ pub enum InlineAsmReg { Nvptx(NvptxInlineAsmReg), Hexagon(HexagonInlineAsmReg), Mips(MipsInlineAsmReg), + Spirv(SpirvInlineAsmReg), } impl InlineAsmReg { @@ -264,6 +269,9 @@ impl InlineAsmReg { InlineAsmArch::Mips | InlineAsmArch::Mips64 => { Self::Mips(MipsInlineAsmReg::parse(arch, has_feature, target, &name)?) } + InlineAsmArch::Spirv => { + Self::Spirv(SpirvInlineAsmReg::parse(arch, has_feature, target, &name)?) + } }) } @@ -306,6 +314,7 @@ pub enum InlineAsmRegClass { Nvptx(NvptxInlineAsmRegClass), Hexagon(HexagonInlineAsmRegClass), Mips(MipsInlineAsmRegClass), + Spirv(SpirvInlineAsmRegClass), } impl InlineAsmRegClass { @@ -318,6 +327,7 @@ impl InlineAsmRegClass { Self::Nvptx(r) => r.name(), Self::Hexagon(r) => r.name(), Self::Mips(r) => r.name(), + Self::Spirv(r) => r.name(), } } @@ -333,6 +343,7 @@ impl InlineAsmRegClass { Self::Nvptx(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::Nvptx), Self::Hexagon(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::Hexagon), Self::Mips(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::Mips), + Self::Spirv(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::Spirv), } } @@ -355,6 +366,7 @@ impl InlineAsmRegClass { Self::Nvptx(r) => r.suggest_modifier(arch, ty), Self::Hexagon(r) => r.suggest_modifier(arch, ty), Self::Mips(r) => r.suggest_modifier(arch, ty), + Self::Spirv(r) => r.suggest_modifier(arch, ty), } } @@ -373,6 +385,7 @@ impl InlineAsmRegClass { Self::Nvptx(r) => r.default_modifier(arch), Self::Hexagon(r) => r.default_modifier(arch), Self::Mips(r) => r.default_modifier(arch), + Self::Spirv(r) => r.default_modifier(arch), } } @@ -390,6 +403,7 @@ impl InlineAsmRegClass { Self::Nvptx(r) => r.supported_types(arch), Self::Hexagon(r) => r.supported_types(arch), Self::Mips(r) => r.supported_types(arch), + Self::Spirv(r) => r.supported_types(arch), } } @@ -414,6 +428,7 @@ impl InlineAsmRegClass { InlineAsmArch::Mips | InlineAsmArch::Mips64 => { Self::Mips(MipsInlineAsmRegClass::parse(arch, name)?) } + InlineAsmArch::Spirv => Self::Spirv(SpirvInlineAsmRegClass::parse(arch, name)?), }) }) } @@ -429,6 +444,7 @@ impl InlineAsmRegClass { Self::Nvptx(r) => r.valid_modifiers(arch), Self::Hexagon(r) => r.valid_modifiers(arch), Self::Mips(r) => r.valid_modifiers(arch), + Self::Spirv(r) => r.valid_modifiers(arch), } } } @@ -571,5 +587,10 @@ pub fn allocatable_registers( mips::fill_reg_map(arch, has_feature, target, &mut map); map } + InlineAsmArch::Spirv => { + let mut map = spirv::regclass_map(); + spirv::fill_reg_map(arch, has_feature, target, &mut map); + map + } } } diff --git a/compiler/rustc_target/src/asm/spirv.rs b/compiler/rustc_target/src/asm/spirv.rs new file mode 100644 index 0000000000000..45158203d0321 --- /dev/null +++ b/compiler/rustc_target/src/asm/spirv.rs @@ -0,0 +1,46 @@ +use super::{InlineAsmArch, InlineAsmType}; +use rustc_macros::HashStable_Generic; + +def_reg_class! { + Spirv SpirvInlineAsmRegClass { + reg, + } +} + +impl SpirvInlineAsmRegClass { + pub fn valid_modifiers(self, _arch: super::InlineAsmArch) -> &'static [char] { + &[] + } + + pub fn suggest_class(self, _arch: InlineAsmArch, _ty: InlineAsmType) -> Option { + None + } + + pub fn suggest_modifier( + self, + _arch: InlineAsmArch, + _ty: InlineAsmType, + ) -> Option<(char, &'static str)> { + None + } + + pub fn default_modifier(self, _arch: InlineAsmArch) -> Option<(char, &'static str)> { + None + } + + pub fn supported_types( + self, + _arch: InlineAsmArch, + ) -> &'static [(InlineAsmType, Option<&'static str>)] { + match self { + Self::reg => { + types! { _: I8, I16, I32, I64, F32, F64; } + } + } + } +} + +def_regs! { + // SPIR-V is SSA-based, it does not have registers. + Spirv SpirvInlineAsmReg SpirvInlineAsmRegClass {} +} From 0e34b73996e87bb3f761b52616b3ac0e081fa84d Mon Sep 17 00:00:00 2001 From: khyperia Date: Wed, 11 Nov 2020 19:18:06 +0100 Subject: [PATCH 2/2] Change capitalization of Spirv to SpirV This matches the capitalization of RiscV --- compiler/rustc_codegen_llvm/src/asm.rs | 8 +++---- compiler/rustc_target/src/asm/mod.rs | 30 +++++++++++++------------- compiler/rustc_target/src/asm/spirv.rs | 6 +++--- 3 files changed, 22 insertions(+), 22 deletions(-) diff --git a/compiler/rustc_codegen_llvm/src/asm.rs b/compiler/rustc_codegen_llvm/src/asm.rs index f0b798d2c3868..b5d279eeb6f2f 100644 --- a/compiler/rustc_codegen_llvm/src/asm.rs +++ b/compiler/rustc_codegen_llvm/src/asm.rs @@ -260,7 +260,7 @@ impl AsmBuilderMethods<'tcx> for Builder<'a, 'll, 'tcx> { InlineAsmArch::Nvptx64 => {} InlineAsmArch::Hexagon => {} InlineAsmArch::Mips | InlineAsmArch::Mips64 => {} - InlineAsmArch::Spirv => {} + InlineAsmArch::SpirV => {} } } if !options.contains(InlineAsmOptions::NOMEM) { @@ -519,7 +519,7 @@ fn reg_to_llvm(reg: InlineAsmRegOrRegClass, layout: Option<&TyAndLayout<'tcx>>) | InlineAsmRegClass::X86(X86InlineAsmRegClass::ymm_reg) => "x", InlineAsmRegClass::X86(X86InlineAsmRegClass::zmm_reg) => "v", InlineAsmRegClass::X86(X86InlineAsmRegClass::kreg) => "^Yk", - InlineAsmRegClass::Spirv(SpirvInlineAsmRegClass::reg) => { + InlineAsmRegClass::SpirV(SpirVInlineAsmRegClass::reg) => { bug!("LLVM backend does not support SPIR-V") } } @@ -584,7 +584,7 @@ fn modifier_to_llvm( _ => unreachable!(), }, InlineAsmRegClass::X86(X86InlineAsmRegClass::kreg) => None, - InlineAsmRegClass::Spirv(SpirvInlineAsmRegClass::reg) => { + InlineAsmRegClass::SpirV(SpirVInlineAsmRegClass::reg) => { bug!("LLVM backend does not support SPIR-V") } } @@ -626,7 +626,7 @@ fn dummy_output_type(cx: &CodegenCx<'ll, 'tcx>, reg: InlineAsmRegClass) -> &'ll | InlineAsmRegClass::X86(X86InlineAsmRegClass::ymm_reg) | InlineAsmRegClass::X86(X86InlineAsmRegClass::zmm_reg) => cx.type_f32(), InlineAsmRegClass::X86(X86InlineAsmRegClass::kreg) => cx.type_i16(), - InlineAsmRegClass::Spirv(SpirvInlineAsmRegClass::reg) => { + InlineAsmRegClass::SpirV(SpirVInlineAsmRegClass::reg) => { bug!("LLVM backend does not support SPIR-V") } } diff --git a/compiler/rustc_target/src/asm/mod.rs b/compiler/rustc_target/src/asm/mod.rs index d07087d279b3e..5ebd6c4a2349f 100644 --- a/compiler/rustc_target/src/asm/mod.rs +++ b/compiler/rustc_target/src/asm/mod.rs @@ -164,7 +164,7 @@ pub use hexagon::{HexagonInlineAsmReg, HexagonInlineAsmRegClass}; pub use mips::{MipsInlineAsmReg, MipsInlineAsmRegClass}; pub use nvptx::{NvptxInlineAsmReg, NvptxInlineAsmRegClass}; pub use riscv::{RiscVInlineAsmReg, RiscVInlineAsmRegClass}; -pub use spirv::{SpirvInlineAsmReg, SpirvInlineAsmRegClass}; +pub use spirv::{SpirVInlineAsmReg, SpirVInlineAsmRegClass}; pub use x86::{X86InlineAsmReg, X86InlineAsmRegClass}; #[derive(Copy, Clone, Encodable, Decodable, Debug, Eq, PartialEq, Hash)] @@ -179,7 +179,7 @@ pub enum InlineAsmArch { Hexagon, Mips, Mips64, - Spirv, + SpirV, } impl FromStr for InlineAsmArch { @@ -197,7 +197,7 @@ impl FromStr for InlineAsmArch { "hexagon" => Ok(Self::Hexagon), "mips" => Ok(Self::Mips), "mips64" => Ok(Self::Mips64), - "spirv" => Ok(Self::Spirv), + "spirv" => Ok(Self::SpirV), _ => Err(()), } } @@ -212,7 +212,7 @@ pub enum InlineAsmReg { Nvptx(NvptxInlineAsmReg), Hexagon(HexagonInlineAsmReg), Mips(MipsInlineAsmReg), - Spirv(SpirvInlineAsmReg), + SpirV(SpirVInlineAsmReg), } impl InlineAsmReg { @@ -269,8 +269,8 @@ impl InlineAsmReg { InlineAsmArch::Mips | InlineAsmArch::Mips64 => { Self::Mips(MipsInlineAsmReg::parse(arch, has_feature, target, &name)?) } - InlineAsmArch::Spirv => { - Self::Spirv(SpirvInlineAsmReg::parse(arch, has_feature, target, &name)?) + InlineAsmArch::SpirV => { + Self::SpirV(SpirVInlineAsmReg::parse(arch, has_feature, target, &name)?) } }) } @@ -314,7 +314,7 @@ pub enum InlineAsmRegClass { Nvptx(NvptxInlineAsmRegClass), Hexagon(HexagonInlineAsmRegClass), Mips(MipsInlineAsmRegClass), - Spirv(SpirvInlineAsmRegClass), + SpirV(SpirVInlineAsmRegClass), } impl InlineAsmRegClass { @@ -327,7 +327,7 @@ impl InlineAsmRegClass { Self::Nvptx(r) => r.name(), Self::Hexagon(r) => r.name(), Self::Mips(r) => r.name(), - Self::Spirv(r) => r.name(), + Self::SpirV(r) => r.name(), } } @@ -343,7 +343,7 @@ impl InlineAsmRegClass { Self::Nvptx(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::Nvptx), Self::Hexagon(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::Hexagon), Self::Mips(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::Mips), - Self::Spirv(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::Spirv), + Self::SpirV(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::SpirV), } } @@ -366,7 +366,7 @@ impl InlineAsmRegClass { Self::Nvptx(r) => r.suggest_modifier(arch, ty), Self::Hexagon(r) => r.suggest_modifier(arch, ty), Self::Mips(r) => r.suggest_modifier(arch, ty), - Self::Spirv(r) => r.suggest_modifier(arch, ty), + Self::SpirV(r) => r.suggest_modifier(arch, ty), } } @@ -385,7 +385,7 @@ impl InlineAsmRegClass { Self::Nvptx(r) => r.default_modifier(arch), Self::Hexagon(r) => r.default_modifier(arch), Self::Mips(r) => r.default_modifier(arch), - Self::Spirv(r) => r.default_modifier(arch), + Self::SpirV(r) => r.default_modifier(arch), } } @@ -403,7 +403,7 @@ impl InlineAsmRegClass { Self::Nvptx(r) => r.supported_types(arch), Self::Hexagon(r) => r.supported_types(arch), Self::Mips(r) => r.supported_types(arch), - Self::Spirv(r) => r.supported_types(arch), + Self::SpirV(r) => r.supported_types(arch), } } @@ -428,7 +428,7 @@ impl InlineAsmRegClass { InlineAsmArch::Mips | InlineAsmArch::Mips64 => { Self::Mips(MipsInlineAsmRegClass::parse(arch, name)?) } - InlineAsmArch::Spirv => Self::Spirv(SpirvInlineAsmRegClass::parse(arch, name)?), + InlineAsmArch::SpirV => Self::SpirV(SpirVInlineAsmRegClass::parse(arch, name)?), }) }) } @@ -444,7 +444,7 @@ impl InlineAsmRegClass { Self::Nvptx(r) => r.valid_modifiers(arch), Self::Hexagon(r) => r.valid_modifiers(arch), Self::Mips(r) => r.valid_modifiers(arch), - Self::Spirv(r) => r.valid_modifiers(arch), + Self::SpirV(r) => r.valid_modifiers(arch), } } } @@ -587,7 +587,7 @@ pub fn allocatable_registers( mips::fill_reg_map(arch, has_feature, target, &mut map); map } - InlineAsmArch::Spirv => { + InlineAsmArch::SpirV => { let mut map = spirv::regclass_map(); spirv::fill_reg_map(arch, has_feature, target, &mut map); map diff --git a/compiler/rustc_target/src/asm/spirv.rs b/compiler/rustc_target/src/asm/spirv.rs index 45158203d0321..da82749e96a16 100644 --- a/compiler/rustc_target/src/asm/spirv.rs +++ b/compiler/rustc_target/src/asm/spirv.rs @@ -2,12 +2,12 @@ use super::{InlineAsmArch, InlineAsmType}; use rustc_macros::HashStable_Generic; def_reg_class! { - Spirv SpirvInlineAsmRegClass { + SpirV SpirVInlineAsmRegClass { reg, } } -impl SpirvInlineAsmRegClass { +impl SpirVInlineAsmRegClass { pub fn valid_modifiers(self, _arch: super::InlineAsmArch) -> &'static [char] { &[] } @@ -42,5 +42,5 @@ impl SpirvInlineAsmRegClass { def_regs! { // SPIR-V is SSA-based, it does not have registers. - Spirv SpirvInlineAsmReg SpirvInlineAsmRegClass {} + SpirV SpirVInlineAsmReg SpirVInlineAsmRegClass {} }