From 5168ef0681ff14aafe10661d04a354457eba7f04 Mon Sep 17 00:00:00 2001 From: luojia65 Date: Thu, 2 Dec 2021 17:02:01 +0800 Subject: [PATCH] Add RISC-V platform and PAUSE instruction --- .github/workflows/main.yml | 1 + crates/core_arch/src/core_arch_docs.md | 2 ++ crates/core_arch/src/mod.rs | 14 ++++++++++++++ crates/core_arch/src/riscv/mod.rs | 10 ++++++++++ 4 files changed, 27 insertions(+) create mode 100644 crates/core_arch/src/riscv/mod.rs diff --git a/.github/workflows/main.yml b/.github/workflows/main.yml index 6412075a4a..082f8b36ff 100644 --- a/.github/workflows/main.yml +++ b/.github/workflows/main.yml @@ -72,6 +72,7 @@ jobs: - arm-unknown-linux-gnueabihf - armv7-unknown-linux-gnueabihf - aarch64-unknown-linux-gnu + - riscv64gc-unknown-linux-gnu - powerpc64le-unknown-linux-gnu - mips-unknown-linux-gnu - mips64-unknown-linux-gnuabi64 diff --git a/crates/core_arch/src/core_arch_docs.md b/crates/core_arch/src/core_arch_docs.md index 96634f200f..be0f98c843 100644 --- a/crates/core_arch/src/core_arch_docs.md +++ b/crates/core_arch/src/core_arch_docs.md @@ -185,6 +185,7 @@ others at: * [`x86_64`] * [`arm`] * [`aarch64`] +* [`riscv`] * [`mips`] * [`mips64`] * [`powerpc`] @@ -196,6 +197,7 @@ others at: [`x86_64`]: x86_64/index.html [`arm`]: arm/index.html [`aarch64`]: aarch64/index.html +[`riscv`]: riscv/index.html [`mips`]: mips/index.html [`mips64`]: mips64/index.html [`powerpc`]: powerpc/index.html diff --git a/crates/core_arch/src/mod.rs b/crates/core_arch/src/mod.rs index 754336c7f6..acf78ca82f 100644 --- a/crates/core_arch/src/mod.rs +++ b/crates/core_arch/src/mod.rs @@ -55,6 +55,16 @@ pub mod arch { pub use crate::core_arch::aarch64::*; } + /// Platform-specific intrinsics for the `riscv` platform. + /// + /// See the [module documentation](../index.html) for more details. + #[cfg(any(target_arch = "riscv32", target_arch = "riscv64", doc))] + #[doc(cfg(any(target_arch = "riscv32", target_arch = "riscv64")))] + #[unstable(feature = "stdsimd", issue = "27731")] + pub mod riscv { + pub use crate::core_arch::riscv::*; + } + /// Platform-specific intrinsics for the `wasm32` platform. /// /// This module provides intrinsics specific to the WebAssembly @@ -251,6 +261,10 @@ mod aarch64; #[doc(cfg(any(target_arch = "arm")))] mod arm; +#[cfg(any(target_arch = "riscv32", target_arch = "riscv64", doc))] +#[doc(cfg(any(target_arch = "riscv32", target_arch = "riscv64")))] +mod riscv; + #[cfg(any(target_family = "wasm", doc))] #[doc(cfg(target_family = "wasm"))] mod wasm32; diff --git a/crates/core_arch/src/riscv/mod.rs b/crates/core_arch/src/riscv/mod.rs new file mode 100644 index 0000000000..d64a9748b5 --- /dev/null +++ b/crates/core_arch/src/riscv/mod.rs @@ -0,0 +1,10 @@ +//! RISC-V intrinsics + +/// Generates the `PAUSE` instruction +/// +/// The PAUSE instruction is a HINT that indicates the current hart's rate of instruction retirement +/// should be temporarily reduced or paused. The duration of its effect must be bounded and may be zero. +#[inline(always)] +pub unsafe fn pause() { + asm!(".word 0x0100000F") +}