diff --git a/src/registers/model_specific.rs b/src/registers/model_specific.rs
index 07504878..0471bfae 100644
--- a/src/registers/model_specific.rs
+++ b/src/registers/model_specific.rs
@@ -357,11 +357,11 @@ mod x86_64 {
         ///
         /// # Returns
         /// - Field 1 (SYSRET): The CS selector is set to this field + 16. SS.Sel is set to
-        /// this field + 8. Because SYSRET always returns to CPL 3, the
-        /// RPL bits 1:0 should be initialized to 11b.
+        ///   this field + 8. Because SYSRET always returns to CPL 3, the
+        ///   RPL bits 1:0 should be initialized to 11b.
         /// - Field 2 (SYSCALL): This field is copied directly into CS.Sel. SS.Sel is set to
-        ///  this field + 8. Because SYSCALL always switches to CPL 0, the RPL bits
-        /// 33:32 should be initialized to 00b.
+        ///   this field + 8. Because SYSCALL always switches to CPL 0, the RPL bits
+        ///   33:32 should be initialized to 00b.
         #[inline]
         pub fn read_raw() -> (u16, u16) {
             let msr_value = unsafe { Self::MSR.read() };
@@ -398,11 +398,11 @@ mod x86_64 {
         ///
         /// # Parameters
         /// - sysret: The CS selector is set to this field + 16. SS.Sel is set to
-        /// this field + 8. Because SYSRET always returns to CPL 3, the
-        /// RPL bits 1:0 should be initialized to 11b.
+        ///   this field + 8. Because SYSRET always returns to CPL 3, the
+        ///   RPL bits 1:0 should be initialized to 11b.
         /// - syscall: This field is copied directly into CS.Sel. SS.Sel is set to
-        ///  this field + 8. Because SYSCALL always switches to CPL 0, the RPL bits
-        /// 33:32 should be initialized to 00b.
+        ///   this field + 8. Because SYSCALL always switches to CPL 0, the RPL bits
+        ///   33:32 should be initialized to 00b.
         ///
         /// # Safety
         ///
diff --git a/src/structures/idt.rs b/src/structures/idt.rs
index 2d9beb5a..4a92bacf 100644
--- a/src/structures/idt.rs
+++ b/src/structures/idt.rs
@@ -153,9 +153,9 @@ pub struct InterruptDescriptorTable {
     ///   is enabled.
     /// - Execution of any legacy SSE instruction when `CR4.OSFXSR` is cleared to 0.
     /// - Execution of any SSE instruction (uses `YMM`/`XMM` registers), or 64-bit media
-    /// instruction (uses `MMXTM` registers) when `CR0.EM` = 1.
+    ///   instruction (uses `MMXTM` registers) when `CR0.EM` = 1.
     /// - Execution of any SSE floating-point instruction (uses `YMM`/`XMM` registers) that
-    /// causes a numeric exception when `CR4.OSXMMEXCPT` = 0.
+    ///   causes a numeric exception when `CR4.OSXMMEXCPT` = 0.
     /// - Use of the `DR4` or `DR5` debug registers when `CR4.DE` = 1.
     /// - Execution of `RSM` when not in `SMM` mode.
     ///
@@ -503,7 +503,7 @@ impl InterruptDescriptorTable {
     ///
     /// - `self` is never destroyed.
     /// - `self` always stays at the same memory location. It is recommended to wrap it in
-    /// a `Box`.
+    ///   a `Box`.
     ///
     #[cfg(all(feature = "instructions", target_arch = "x86_64"))]
     #[inline]
@@ -1642,7 +1642,7 @@ mod test {
 
     #[test]
     fn entry_derive_test() {
-        fn foo(_: impl Clone + Copy + PartialEq + fmt::Debug) {}
+        fn foo(_: impl Copy + PartialEq + fmt::Debug) {}
 
         foo(Entry::<HandlerFuncWithErrCode> {
             pointer_low: 0,
@@ -1667,9 +1667,7 @@ mod test {
         });
 
         unsafe {
-            frame
-                .as_mut()
-                .update(|f| f.instruction_pointer = f.instruction_pointer + 2u64);
+            frame.as_mut().update(|f| f.instruction_pointer += 2u64);
         }
     }
 }