From e3352bc97c0bc4e27dc58943aeb5e2ea3c9146d2 Mon Sep 17 00:00:00 2001 From: Jiuyang Liu Date: Fri, 7 Jan 2022 18:48:20 +0800 Subject: [PATCH] bump for bump for chipsalliance/rocket-chip#2841 --- src/main/scala/common/parameters.scala | 2 ++ src/main/scala/exu/decode.scala | 2 +- src/main/scala/lsu/tlb.scala | 2 +- 3 files changed, 4 insertions(+), 2 deletions(-) diff --git a/src/main/scala/common/parameters.scala b/src/main/scala/common/parameters.scala index 4f22b1979e..24e2beb455 100644 --- a/src/main/scala/common/parameters.scala +++ b/src/main/scala/common/parameters.scala @@ -80,6 +80,7 @@ case class BoomCoreParams( mulDiv: Option[freechips.rocketchip.rocket.MulDivParams] = Some(MulDivParams(divEarlyOut=true)), nBreakpoints: Int = 0, // TODO Fix with better frontend breakpoint unit nL2TLBEntries: Int = 512, + val nPTECacheEntries: Int = 8, // TODO: check nL2TLBWays: Int = 1, nLocalInterrupts: Int = 0, useNMI: Boolean = false, @@ -87,6 +88,7 @@ case class BoomCoreParams( useDebug: Boolean = true, useUser: Boolean = true, useSupervisor: Boolean = false, + useHypervisor: Boolean = false, useVM: Boolean = true, useSCIE: Boolean = false, useRVE: Boolean = false, diff --git a/src/main/scala/exu/decode.scala b/src/main/scala/exu/decode.scala index 4036d1ef9a..f0c99f6f12 100644 --- a/src/main/scala/exu/decode.scala +++ b/src/main/scala/exu/decode.scala @@ -485,7 +485,7 @@ class DecodeUnit(implicit p: Parameters) extends BoomModule val cs = Wire(new CtrlSigs()).decode(inst, decode_table) // Exception Handling - io.csr_decode.csr := inst(31,20) + io.csr_decode.csr_addr := inst val csr_en = cs.csr_cmd.isOneOf(CSR.S, CSR.C, CSR.W) val csr_ren = cs.csr_cmd.isOneOf(CSR.S, CSR.C) && uop.lrs1 === 0.U val system_insn = cs.csr_cmd === CSR.I diff --git a/src/main/scala/lsu/tlb.scala b/src/main/scala/lsu/tlb.scala index 805bbbf0e8..732f1ecaf5 100644 --- a/src/main/scala/lsu/tlb.scala +++ b/src/main/scala/lsu/tlb.scala @@ -181,7 +181,7 @@ class NBDTLB(instruction: Boolean, lgMaxSize: Int, cfg: TLBConfig)(implicit edge newEntry.c := cacheable(0) newEntry.u := pte.u newEntry.g := pte.g - newEntry.ae := io.ptw.resp.bits.ae + newEntry.ae := io.ptw.resp.bits.ae_final newEntry.sr := pte.sr() newEntry.sw := pte.sw() newEntry.sx := pte.sx()