From 53587316be34e92707d76352a642ffb29baef06c Mon Sep 17 00:00:00 2001 From: Nandkumar Joshi Date: Wed, 23 Sep 2020 02:33:53 +0530 Subject: [PATCH] Add support for L2 LIM. Update BSP files. --- .gitmodules | 3 +++ README.md | 2 ++ bsp/freedom-e310-arty/metal.default.lds | 21 +++++++++++++++- bsp/freedom-e310-arty/metal.freertos.lds | 21 +++++++++++++++- bsp/freedom-e310-arty/metal.ramrodata.lds | 21 +++++++++++++++- bsp/freedom-e310-arty/metal.scratchpad.lds | 21 +++++++++++++++- bsp/qemu-sifive-e31/metal.default.lds | 21 +++++++++++++++- bsp/qemu-sifive-e31/metal.freertos.lds | 21 +++++++++++++++- bsp/qemu-sifive-e31/metal.ramrodata.lds | 21 +++++++++++++++- bsp/qemu-sifive-e31/metal.scratchpad.lds | 21 +++++++++++++++- bsp/qemu-sifive-s51/metal.default.lds | 21 +++++++++++++++- bsp/qemu-sifive-s51/metal.freertos.lds | 21 +++++++++++++++- bsp/qemu-sifive-s51/metal.ramrodata.lds | 21 +++++++++++++++- bsp/qemu-sifive-s51/metal.scratchpad.lds | 21 +++++++++++++++- bsp/qemu-sifive-u54/metal.default.lds | 21 +++++++++++++++- bsp/qemu-sifive-u54/metal.freertos.lds | 21 +++++++++++++++- bsp/qemu-sifive-u54/metal.ramrodata.lds | 21 +++++++++++++++- bsp/qemu-sifive-u54/metal.scratchpad.lds | 21 +++++++++++++++- bsp/qemu-sifive-u54mc/metal.default.lds | 21 +++++++++++++++- bsp/qemu-sifive-u54mc/metal.freertos.lds | 21 +++++++++++++++- bsp/qemu-sifive-u54mc/metal.ramrodata.lds | 21 +++++++++++++++- bsp/qemu-sifive-u54mc/metal.scratchpad.lds | 21 +++++++++++++++- bsp/sifive-hifive-unleashed/metal.default.lds | 25 ++++++++++++++++++- .../metal.freertos.lds | 25 ++++++++++++++++++- .../metal.ramrodata.lds | 25 ++++++++++++++++++- .../metal.scratchpad.lds | 21 +++++++++++++++- bsp/sifive-hifive1-revb/metal.default.lds | 21 +++++++++++++++- bsp/sifive-hifive1-revb/metal.freertos.lds | 21 +++++++++++++++- bsp/sifive-hifive1-revb/metal.ramrodata.lds | 21 +++++++++++++++- bsp/sifive-hifive1-revb/metal.scratchpad.lds | 21 +++++++++++++++- bsp/sifive-hifive1/metal.default.lds | 21 +++++++++++++++- bsp/sifive-hifive1/metal.freertos.lds | 21 +++++++++++++++- bsp/sifive-hifive1/metal.ramrodata.lds | 21 +++++++++++++++- bsp/sifive-hifive1/metal.scratchpad.lds | 21 +++++++++++++++- bsp/spike/metal.default.lds | 21 +++++++++++++++- bsp/spike/metal.freertos.lds | 21 +++++++++++++++- bsp/spike/metal.ramrodata.lds | 21 +++++++++++++++- bsp/spike/metal.scratchpad.lds | 21 +++++++++++++++- doc/sphinx/contents.rst | 5 ++++ freedom-metal | 2 +- scripts/ldscript-generator | 2 +- software/example-lim | 1 + wit-manifest.json | 9 +++++-- 43 files changed, 752 insertions(+), 40 deletions(-) create mode 160000 software/example-lim diff --git a/.gitmodules b/.gitmodules index eadbed23c..f2a4be1d4 100644 --- a/.gitmodules +++ b/.gitmodules @@ -157,3 +157,6 @@ [submodule "software/example-l2pf"] path = software/example-l2pf url = https://github.com/sifive/example-l2pf.git +[submodule "software/example-lim"] + path = software/example-lim + url = https://github.com/sifive/example-lim.git diff --git a/README.md b/README.md index 8096b001d..d0665e2d2 100644 --- a/README.md +++ b/README.md @@ -153,6 +153,8 @@ operating systems to RISC-V. - Demonstrates usage of Sifive L2 performance monitor counter APIs to capture L2 cache event logs. - example-l2pf - Example for usage and measuring effectiveness of SiFive L2 Prefetcher. + - example-lim + - Demonstrates how to designate a function to be linked into the LIM (Loosely-Integrated Memory). - example-freertos-minimal - A simple FreeRTOS skeleton to build your FreeRTOS application. - example-freertos-blinky diff --git a/bsp/freedom-e310-arty/metal.default.lds b/bsp/freedom-e310-arty/metal.default.lds index 40e38050e..53fb37595 100644 --- a/bsp/freedom-e310-arty/metal.default.lds +++ b/bsp/freedom-e310-arty/metal.default.lds @@ -24,6 +24,7 @@ PHDRS ram PT_LOAD; itim_init PT_LOAD; text PT_LOAD; + lim_init PT_LOAD; } SECTIONS @@ -179,10 +180,28 @@ SECTIONS PROVIDE( metal_segment_itim_target_start = ADDR(.itim) ); PROVIDE( metal_segment_itim_target_end = ADDR(.itim) + SIZEOF(.itim) ); + /* LIM SECTION + * + * The following sections contain data which is copied from read-only + * memory into a loosely integrated memory (LIM), which is shared with L2 + * cache, during pre-main program initialization. + * + * Generally, the data copied into the LIM should be performance-critical + * functions which benefit from low instruction-fetch latency. + */ + + .lim : ALIGN(8) { + *(.lim .lim.*) + } >ram AT>rom :lim_init + + PROVIDE( metal_segment_lim_source_start = LOADADDR(.lim) ); + PROVIDE( metal_segment_lim_target_start = ADDR(.lim) ); + PROVIDE( metal_segment_lim_target_end = ADDR(.lim) + SIZEOF(.lim) ); + /* TEXT SECTION * * The following section contains the code of the program, excluding - * everything that's been allocated into the ITIM already + * everything that's been allocated into the ITIM/LIM already */ .text : { diff --git a/bsp/freedom-e310-arty/metal.freertos.lds b/bsp/freedom-e310-arty/metal.freertos.lds index fbfaf47b8..cb3e8b591 100644 --- a/bsp/freedom-e310-arty/metal.freertos.lds +++ b/bsp/freedom-e310-arty/metal.freertos.lds @@ -27,6 +27,7 @@ PHDRS ram PT_LOAD; itim_init PT_LOAD; text PT_LOAD; + lim_init PT_LOAD; } SECTIONS @@ -190,10 +191,28 @@ SECTIONS PROVIDE( metal_segment_itim_target_start = ADDR(.itim) ); PROVIDE( metal_segment_itim_target_end = ADDR(.itim) + SIZEOF(.itim) ); + /* LIM SECTION + * + * The following sections contain data which is copied from read-only + * memory into a loosely integrated memory (LIM), which is shared with L2 + * cache, during pre-main program initialization. + * + * Generally, the data copied into the LIM should be performance-critical + * functions which benefit from low instruction-fetch latency. + */ + + .lim : ALIGN(8) { + *(.lim .lim.*) + } >ram AT>rom :lim_init + + PROVIDE( metal_segment_lim_source_start = LOADADDR(.lim) ); + PROVIDE( metal_segment_lim_target_start = ADDR(.lim) ); + PROVIDE( metal_segment_lim_target_end = ADDR(.lim) + SIZEOF(.lim) ); + /* TEXT SECTION * * The following section contains the code of the program, excluding - * everything that's been allocated into the ITIM already + * everything that's been allocated into the ITIM/LIM already */ .text : { diff --git a/bsp/freedom-e310-arty/metal.ramrodata.lds b/bsp/freedom-e310-arty/metal.ramrodata.lds index 4cc334b02..3935fa347 100644 --- a/bsp/freedom-e310-arty/metal.ramrodata.lds +++ b/bsp/freedom-e310-arty/metal.ramrodata.lds @@ -28,6 +28,7 @@ PHDRS ram PT_LOAD; itim_init PT_LOAD; text PT_LOAD; + lim_init PT_LOAD; } SECTIONS @@ -172,10 +173,28 @@ SECTIONS PROVIDE( metal_segment_itim_target_start = ADDR(.itim) ); PROVIDE( metal_segment_itim_target_end = ADDR(.itim) + SIZEOF(.itim) ); + /* LIM SECTION + * + * The following sections contain data which is copied from read-only + * memory into a loosely integrated memory (LIM), which is shared with L2 + * cache, during pre-main program initialization. + * + * Generally, the data copied into the LIM should be performance-critical + * functions which benefit from low instruction-fetch latency. + */ + + .lim : ALIGN(8) { + *(.lim .lim.*) + } >ram AT>rom :lim_init + + PROVIDE( metal_segment_lim_source_start = LOADADDR(.lim) ); + PROVIDE( metal_segment_lim_target_start = ADDR(.lim) ); + PROVIDE( metal_segment_lim_target_end = ADDR(.lim) + SIZEOF(.lim) ); + /* TEXT SECTION * * The following section contains the code of the program, excluding - * everything that's been allocated into the ITIM already + * everything that's been allocated into the ITIM/LIM already */ .text : { diff --git a/bsp/freedom-e310-arty/metal.scratchpad.lds b/bsp/freedom-e310-arty/metal.scratchpad.lds index 22c2d89f8..6a2bcd863 100644 --- a/bsp/freedom-e310-arty/metal.scratchpad.lds +++ b/bsp/freedom-e310-arty/metal.scratchpad.lds @@ -25,6 +25,7 @@ PHDRS ram PT_LOAD; itim_init PT_LOAD; text PT_LOAD; + lim_init PT_LOAD; } SECTIONS @@ -172,10 +173,28 @@ SECTIONS PROVIDE( metal_segment_itim_target_start = ADDR(.itim) ); PROVIDE( metal_segment_itim_target_end = ADDR(.itim) + SIZEOF(.itim) ); + /* LIM SECTION + * + * The following sections contain data which is copied from read-only + * memory into a loosely integrated memory (LIM), which is shared with L2 + * cache, during pre-main program initialization. + * + * Generally, the data copied into the LIM should be performance-critical + * functions which benefit from low instruction-fetch latency. + */ + + .lim : ALIGN(8) { + *(.lim .lim.*) + } >ram AT>ram :lim_init + + PROVIDE( metal_segment_lim_source_start = LOADADDR(.lim) ); + PROVIDE( metal_segment_lim_target_start = ADDR(.lim) ); + PROVIDE( metal_segment_lim_target_end = ADDR(.lim) + SIZEOF(.lim) ); + /* TEXT SECTION * * The following section contains the code of the program, excluding - * everything that's been allocated into the ITIM already + * everything that's been allocated into the ITIM/LIM already */ .text : { diff --git a/bsp/qemu-sifive-e31/metal.default.lds b/bsp/qemu-sifive-e31/metal.default.lds index eff101d27..a557e74ad 100644 --- a/bsp/qemu-sifive-e31/metal.default.lds +++ b/bsp/qemu-sifive-e31/metal.default.lds @@ -23,6 +23,7 @@ PHDRS ram PT_LOAD; itim_init PT_LOAD; text PT_LOAD; + lim_init PT_LOAD; } SECTIONS @@ -178,10 +179,28 @@ SECTIONS PROVIDE( metal_segment_itim_target_start = ADDR(.itim) ); PROVIDE( metal_segment_itim_target_end = ADDR(.itim) + SIZEOF(.itim) ); + /* LIM SECTION + * + * The following sections contain data which is copied from read-only + * memory into a loosely integrated memory (LIM), which is shared with L2 + * cache, during pre-main program initialization. + * + * Generally, the data copied into the LIM should be performance-critical + * functions which benefit from low instruction-fetch latency. + */ + + .lim : ALIGN(8) { + *(.lim .lim.*) + } >ram AT>rom :lim_init + + PROVIDE( metal_segment_lim_source_start = LOADADDR(.lim) ); + PROVIDE( metal_segment_lim_target_start = ADDR(.lim) ); + PROVIDE( metal_segment_lim_target_end = ADDR(.lim) + SIZEOF(.lim) ); + /* TEXT SECTION * * The following section contains the code of the program, excluding - * everything that's been allocated into the ITIM already + * everything that's been allocated into the ITIM/LIM already */ .text : { diff --git a/bsp/qemu-sifive-e31/metal.freertos.lds b/bsp/qemu-sifive-e31/metal.freertos.lds index 4dc89ee9b..0ebb65933 100644 --- a/bsp/qemu-sifive-e31/metal.freertos.lds +++ b/bsp/qemu-sifive-e31/metal.freertos.lds @@ -26,6 +26,7 @@ PHDRS ram PT_LOAD; itim_init PT_LOAD; text PT_LOAD; + lim_init PT_LOAD; } SECTIONS @@ -189,10 +190,28 @@ SECTIONS PROVIDE( metal_segment_itim_target_start = ADDR(.itim) ); PROVIDE( metal_segment_itim_target_end = ADDR(.itim) + SIZEOF(.itim) ); + /* LIM SECTION + * + * The following sections contain data which is copied from read-only + * memory into a loosely integrated memory (LIM), which is shared with L2 + * cache, during pre-main program initialization. + * + * Generally, the data copied into the LIM should be performance-critical + * functions which benefit from low instruction-fetch latency. + */ + + .lim : ALIGN(8) { + *(.lim .lim.*) + } >ram AT>rom :lim_init + + PROVIDE( metal_segment_lim_source_start = LOADADDR(.lim) ); + PROVIDE( metal_segment_lim_target_start = ADDR(.lim) ); + PROVIDE( metal_segment_lim_target_end = ADDR(.lim) + SIZEOF(.lim) ); + /* TEXT SECTION * * The following section contains the code of the program, excluding - * everything that's been allocated into the ITIM already + * everything that's been allocated into the ITIM/LIM already */ .text : { diff --git a/bsp/qemu-sifive-e31/metal.ramrodata.lds b/bsp/qemu-sifive-e31/metal.ramrodata.lds index b1c9357df..26f3070cd 100644 --- a/bsp/qemu-sifive-e31/metal.ramrodata.lds +++ b/bsp/qemu-sifive-e31/metal.ramrodata.lds @@ -27,6 +27,7 @@ PHDRS ram PT_LOAD; itim_init PT_LOAD; text PT_LOAD; + lim_init PT_LOAD; } SECTIONS @@ -171,10 +172,28 @@ SECTIONS PROVIDE( metal_segment_itim_target_start = ADDR(.itim) ); PROVIDE( metal_segment_itim_target_end = ADDR(.itim) + SIZEOF(.itim) ); + /* LIM SECTION + * + * The following sections contain data which is copied from read-only + * memory into a loosely integrated memory (LIM), which is shared with L2 + * cache, during pre-main program initialization. + * + * Generally, the data copied into the LIM should be performance-critical + * functions which benefit from low instruction-fetch latency. + */ + + .lim : ALIGN(8) { + *(.lim .lim.*) + } >ram AT>rom :lim_init + + PROVIDE( metal_segment_lim_source_start = LOADADDR(.lim) ); + PROVIDE( metal_segment_lim_target_start = ADDR(.lim) ); + PROVIDE( metal_segment_lim_target_end = ADDR(.lim) + SIZEOF(.lim) ); + /* TEXT SECTION * * The following section contains the code of the program, excluding - * everything that's been allocated into the ITIM already + * everything that's been allocated into the ITIM/LIM already */ .text : { diff --git a/bsp/qemu-sifive-e31/metal.scratchpad.lds b/bsp/qemu-sifive-e31/metal.scratchpad.lds index 4b3b45480..42cf7ba96 100644 --- a/bsp/qemu-sifive-e31/metal.scratchpad.lds +++ b/bsp/qemu-sifive-e31/metal.scratchpad.lds @@ -24,6 +24,7 @@ PHDRS ram PT_LOAD; itim_init PT_LOAD; text PT_LOAD; + lim_init PT_LOAD; } SECTIONS @@ -171,10 +172,28 @@ SECTIONS PROVIDE( metal_segment_itim_target_start = ADDR(.itim) ); PROVIDE( metal_segment_itim_target_end = ADDR(.itim) + SIZEOF(.itim) ); + /* LIM SECTION + * + * The following sections contain data which is copied from read-only + * memory into a loosely integrated memory (LIM), which is shared with L2 + * cache, during pre-main program initialization. + * + * Generally, the data copied into the LIM should be performance-critical + * functions which benefit from low instruction-fetch latency. + */ + + .lim : ALIGN(8) { + *(.lim .lim.*) + } >ram AT>ram :lim_init + + PROVIDE( metal_segment_lim_source_start = LOADADDR(.lim) ); + PROVIDE( metal_segment_lim_target_start = ADDR(.lim) ); + PROVIDE( metal_segment_lim_target_end = ADDR(.lim) + SIZEOF(.lim) ); + /* TEXT SECTION * * The following section contains the code of the program, excluding - * everything that's been allocated into the ITIM already + * everything that's been allocated into the ITIM/LIM already */ .text : { diff --git a/bsp/qemu-sifive-s51/metal.default.lds b/bsp/qemu-sifive-s51/metal.default.lds index eff101d27..a557e74ad 100644 --- a/bsp/qemu-sifive-s51/metal.default.lds +++ b/bsp/qemu-sifive-s51/metal.default.lds @@ -23,6 +23,7 @@ PHDRS ram PT_LOAD; itim_init PT_LOAD; text PT_LOAD; + lim_init PT_LOAD; } SECTIONS @@ -178,10 +179,28 @@ SECTIONS PROVIDE( metal_segment_itim_target_start = ADDR(.itim) ); PROVIDE( metal_segment_itim_target_end = ADDR(.itim) + SIZEOF(.itim) ); + /* LIM SECTION + * + * The following sections contain data which is copied from read-only + * memory into a loosely integrated memory (LIM), which is shared with L2 + * cache, during pre-main program initialization. + * + * Generally, the data copied into the LIM should be performance-critical + * functions which benefit from low instruction-fetch latency. + */ + + .lim : ALIGN(8) { + *(.lim .lim.*) + } >ram AT>rom :lim_init + + PROVIDE( metal_segment_lim_source_start = LOADADDR(.lim) ); + PROVIDE( metal_segment_lim_target_start = ADDR(.lim) ); + PROVIDE( metal_segment_lim_target_end = ADDR(.lim) + SIZEOF(.lim) ); + /* TEXT SECTION * * The following section contains the code of the program, excluding - * everything that's been allocated into the ITIM already + * everything that's been allocated into the ITIM/LIM already */ .text : { diff --git a/bsp/qemu-sifive-s51/metal.freertos.lds b/bsp/qemu-sifive-s51/metal.freertos.lds index 4dc89ee9b..0ebb65933 100644 --- a/bsp/qemu-sifive-s51/metal.freertos.lds +++ b/bsp/qemu-sifive-s51/metal.freertos.lds @@ -26,6 +26,7 @@ PHDRS ram PT_LOAD; itim_init PT_LOAD; text PT_LOAD; + lim_init PT_LOAD; } SECTIONS @@ -189,10 +190,28 @@ SECTIONS PROVIDE( metal_segment_itim_target_start = ADDR(.itim) ); PROVIDE( metal_segment_itim_target_end = ADDR(.itim) + SIZEOF(.itim) ); + /* LIM SECTION + * + * The following sections contain data which is copied from read-only + * memory into a loosely integrated memory (LIM), which is shared with L2 + * cache, during pre-main program initialization. + * + * Generally, the data copied into the LIM should be performance-critical + * functions which benefit from low instruction-fetch latency. + */ + + .lim : ALIGN(8) { + *(.lim .lim.*) + } >ram AT>rom :lim_init + + PROVIDE( metal_segment_lim_source_start = LOADADDR(.lim) ); + PROVIDE( metal_segment_lim_target_start = ADDR(.lim) ); + PROVIDE( metal_segment_lim_target_end = ADDR(.lim) + SIZEOF(.lim) ); + /* TEXT SECTION * * The following section contains the code of the program, excluding - * everything that's been allocated into the ITIM already + * everything that's been allocated into the ITIM/LIM already */ .text : { diff --git a/bsp/qemu-sifive-s51/metal.ramrodata.lds b/bsp/qemu-sifive-s51/metal.ramrodata.lds index b1c9357df..26f3070cd 100644 --- a/bsp/qemu-sifive-s51/metal.ramrodata.lds +++ b/bsp/qemu-sifive-s51/metal.ramrodata.lds @@ -27,6 +27,7 @@ PHDRS ram PT_LOAD; itim_init PT_LOAD; text PT_LOAD; + lim_init PT_LOAD; } SECTIONS @@ -171,10 +172,28 @@ SECTIONS PROVIDE( metal_segment_itim_target_start = ADDR(.itim) ); PROVIDE( metal_segment_itim_target_end = ADDR(.itim) + SIZEOF(.itim) ); + /* LIM SECTION + * + * The following sections contain data which is copied from read-only + * memory into a loosely integrated memory (LIM), which is shared with L2 + * cache, during pre-main program initialization. + * + * Generally, the data copied into the LIM should be performance-critical + * functions which benefit from low instruction-fetch latency. + */ + + .lim : ALIGN(8) { + *(.lim .lim.*) + } >ram AT>rom :lim_init + + PROVIDE( metal_segment_lim_source_start = LOADADDR(.lim) ); + PROVIDE( metal_segment_lim_target_start = ADDR(.lim) ); + PROVIDE( metal_segment_lim_target_end = ADDR(.lim) + SIZEOF(.lim) ); + /* TEXT SECTION * * The following section contains the code of the program, excluding - * everything that's been allocated into the ITIM already + * everything that's been allocated into the ITIM/LIM already */ .text : { diff --git a/bsp/qemu-sifive-s51/metal.scratchpad.lds b/bsp/qemu-sifive-s51/metal.scratchpad.lds index 4b3b45480..42cf7ba96 100644 --- a/bsp/qemu-sifive-s51/metal.scratchpad.lds +++ b/bsp/qemu-sifive-s51/metal.scratchpad.lds @@ -24,6 +24,7 @@ PHDRS ram PT_LOAD; itim_init PT_LOAD; text PT_LOAD; + lim_init PT_LOAD; } SECTIONS @@ -171,10 +172,28 @@ SECTIONS PROVIDE( metal_segment_itim_target_start = ADDR(.itim) ); PROVIDE( metal_segment_itim_target_end = ADDR(.itim) + SIZEOF(.itim) ); + /* LIM SECTION + * + * The following sections contain data which is copied from read-only + * memory into a loosely integrated memory (LIM), which is shared with L2 + * cache, during pre-main program initialization. + * + * Generally, the data copied into the LIM should be performance-critical + * functions which benefit from low instruction-fetch latency. + */ + + .lim : ALIGN(8) { + *(.lim .lim.*) + } >ram AT>ram :lim_init + + PROVIDE( metal_segment_lim_source_start = LOADADDR(.lim) ); + PROVIDE( metal_segment_lim_target_start = ADDR(.lim) ); + PROVIDE( metal_segment_lim_target_end = ADDR(.lim) + SIZEOF(.lim) ); + /* TEXT SECTION * * The following section contains the code of the program, excluding - * everything that's been allocated into the ITIM already + * everything that's been allocated into the ITIM/LIM already */ .text : { diff --git a/bsp/qemu-sifive-u54/metal.default.lds b/bsp/qemu-sifive-u54/metal.default.lds index 414560476..34b473210 100644 --- a/bsp/qemu-sifive-u54/metal.default.lds +++ b/bsp/qemu-sifive-u54/metal.default.lds @@ -22,6 +22,7 @@ PHDRS ram PT_LOAD; itim_init PT_LOAD; text PT_LOAD; + lim_init PT_LOAD; } SECTIONS @@ -177,10 +178,28 @@ SECTIONS PROVIDE( metal_segment_itim_target_start = ADDR(.itim) ); PROVIDE( metal_segment_itim_target_end = ADDR(.itim) + SIZEOF(.itim) ); + /* LIM SECTION + * + * The following sections contain data which is copied from read-only + * memory into a loosely integrated memory (LIM), which is shared with L2 + * cache, during pre-main program initialization. + * + * Generally, the data copied into the LIM should be performance-critical + * functions which benefit from low instruction-fetch latency. + */ + + .lim : ALIGN(8) { + *(.lim .lim.*) + } >testram AT>testram :lim_init + + PROVIDE( metal_segment_lim_source_start = LOADADDR(.lim) ); + PROVIDE( metal_segment_lim_target_start = ADDR(.lim) ); + PROVIDE( metal_segment_lim_target_end = ADDR(.lim) + SIZEOF(.lim) ); + /* TEXT SECTION * * The following section contains the code of the program, excluding - * everything that's been allocated into the ITIM already + * everything that's been allocated into the ITIM/LIM already */ .text : { diff --git a/bsp/qemu-sifive-u54/metal.freertos.lds b/bsp/qemu-sifive-u54/metal.freertos.lds index 92e6b5125..167072049 100644 --- a/bsp/qemu-sifive-u54/metal.freertos.lds +++ b/bsp/qemu-sifive-u54/metal.freertos.lds @@ -25,6 +25,7 @@ PHDRS ram PT_LOAD; itim_init PT_LOAD; text PT_LOAD; + lim_init PT_LOAD; } SECTIONS @@ -188,10 +189,28 @@ SECTIONS PROVIDE( metal_segment_itim_target_start = ADDR(.itim) ); PROVIDE( metal_segment_itim_target_end = ADDR(.itim) + SIZEOF(.itim) ); + /* LIM SECTION + * + * The following sections contain data which is copied from read-only + * memory into a loosely integrated memory (LIM), which is shared with L2 + * cache, during pre-main program initialization. + * + * Generally, the data copied into the LIM should be performance-critical + * functions which benefit from low instruction-fetch latency. + */ + + .lim : ALIGN(8) { + *(.lim .lim.*) + } >testram AT>testram :lim_init + + PROVIDE( metal_segment_lim_source_start = LOADADDR(.lim) ); + PROVIDE( metal_segment_lim_target_start = ADDR(.lim) ); + PROVIDE( metal_segment_lim_target_end = ADDR(.lim) + SIZEOF(.lim) ); + /* TEXT SECTION * * The following section contains the code of the program, excluding - * everything that's been allocated into the ITIM already + * everything that's been allocated into the ITIM/LIM already */ .text : { diff --git a/bsp/qemu-sifive-u54/metal.ramrodata.lds b/bsp/qemu-sifive-u54/metal.ramrodata.lds index 26cdef561..2d9771227 100644 --- a/bsp/qemu-sifive-u54/metal.ramrodata.lds +++ b/bsp/qemu-sifive-u54/metal.ramrodata.lds @@ -26,6 +26,7 @@ PHDRS ram PT_LOAD; itim_init PT_LOAD; text PT_LOAD; + lim_init PT_LOAD; } SECTIONS @@ -170,10 +171,28 @@ SECTIONS PROVIDE( metal_segment_itim_target_start = ADDR(.itim) ); PROVIDE( metal_segment_itim_target_end = ADDR(.itim) + SIZEOF(.itim) ); + /* LIM SECTION + * + * The following sections contain data which is copied from read-only + * memory into a loosely integrated memory (LIM), which is shared with L2 + * cache, during pre-main program initialization. + * + * Generally, the data copied into the LIM should be performance-critical + * functions which benefit from low instruction-fetch latency. + */ + + .lim : ALIGN(8) { + *(.lim .lim.*) + } >testram AT>testram :lim_init + + PROVIDE( metal_segment_lim_source_start = LOADADDR(.lim) ); + PROVIDE( metal_segment_lim_target_start = ADDR(.lim) ); + PROVIDE( metal_segment_lim_target_end = ADDR(.lim) + SIZEOF(.lim) ); + /* TEXT SECTION * * The following section contains the code of the program, excluding - * everything that's been allocated into the ITIM already + * everything that's been allocated into the ITIM/LIM already */ .text : { diff --git a/bsp/qemu-sifive-u54/metal.scratchpad.lds b/bsp/qemu-sifive-u54/metal.scratchpad.lds index b0ada68f6..f078b855a 100644 --- a/bsp/qemu-sifive-u54/metal.scratchpad.lds +++ b/bsp/qemu-sifive-u54/metal.scratchpad.lds @@ -23,6 +23,7 @@ PHDRS ram PT_LOAD; itim_init PT_LOAD; text PT_LOAD; + lim_init PT_LOAD; } SECTIONS @@ -170,10 +171,28 @@ SECTIONS PROVIDE( metal_segment_itim_target_start = ADDR(.itim) ); PROVIDE( metal_segment_itim_target_end = ADDR(.itim) + SIZEOF(.itim) ); + /* LIM SECTION + * + * The following sections contain data which is copied from read-only + * memory into a loosely integrated memory (LIM), which is shared with L2 + * cache, during pre-main program initialization. + * + * Generally, the data copied into the LIM should be performance-critical + * functions which benefit from low instruction-fetch latency. + */ + + .lim : ALIGN(8) { + *(.lim .lim.*) + } >testram AT>testram :lim_init + + PROVIDE( metal_segment_lim_source_start = LOADADDR(.lim) ); + PROVIDE( metal_segment_lim_target_start = ADDR(.lim) ); + PROVIDE( metal_segment_lim_target_end = ADDR(.lim) + SIZEOF(.lim) ); + /* TEXT SECTION * * The following section contains the code of the program, excluding - * everything that's been allocated into the ITIM already + * everything that's been allocated into the ITIM/LIM already */ .text : { diff --git a/bsp/qemu-sifive-u54mc/metal.default.lds b/bsp/qemu-sifive-u54mc/metal.default.lds index 4263441d7..196fe85f5 100644 --- a/bsp/qemu-sifive-u54mc/metal.default.lds +++ b/bsp/qemu-sifive-u54mc/metal.default.lds @@ -22,6 +22,7 @@ PHDRS ram PT_LOAD; itim_init PT_LOAD; text PT_LOAD; + lim_init PT_LOAD; } SECTIONS @@ -177,10 +178,28 @@ SECTIONS PROVIDE( metal_segment_itim_target_start = ADDR(.itim) ); PROVIDE( metal_segment_itim_target_end = ADDR(.itim) + SIZEOF(.itim) ); + /* LIM SECTION + * + * The following sections contain data which is copied from read-only + * memory into a loosely integrated memory (LIM), which is shared with L2 + * cache, during pre-main program initialization. + * + * Generally, the data copied into the LIM should be performance-critical + * functions which benefit from low instruction-fetch latency. + */ + + .lim : ALIGN(8) { + *(.lim .lim.*) + } >testram AT>testram :lim_init + + PROVIDE( metal_segment_lim_source_start = LOADADDR(.lim) ); + PROVIDE( metal_segment_lim_target_start = ADDR(.lim) ); + PROVIDE( metal_segment_lim_target_end = ADDR(.lim) + SIZEOF(.lim) ); + /* TEXT SECTION * * The following section contains the code of the program, excluding - * everything that's been allocated into the ITIM already + * everything that's been allocated into the ITIM/LIM already */ .text : { diff --git a/bsp/qemu-sifive-u54mc/metal.freertos.lds b/bsp/qemu-sifive-u54mc/metal.freertos.lds index 2d8f5e67b..6714f51cb 100644 --- a/bsp/qemu-sifive-u54mc/metal.freertos.lds +++ b/bsp/qemu-sifive-u54mc/metal.freertos.lds @@ -25,6 +25,7 @@ PHDRS ram PT_LOAD; itim_init PT_LOAD; text PT_LOAD; + lim_init PT_LOAD; } SECTIONS @@ -188,10 +189,28 @@ SECTIONS PROVIDE( metal_segment_itim_target_start = ADDR(.itim) ); PROVIDE( metal_segment_itim_target_end = ADDR(.itim) + SIZEOF(.itim) ); + /* LIM SECTION + * + * The following sections contain data which is copied from read-only + * memory into a loosely integrated memory (LIM), which is shared with L2 + * cache, during pre-main program initialization. + * + * Generally, the data copied into the LIM should be performance-critical + * functions which benefit from low instruction-fetch latency. + */ + + .lim : ALIGN(8) { + *(.lim .lim.*) + } >testram AT>testram :lim_init + + PROVIDE( metal_segment_lim_source_start = LOADADDR(.lim) ); + PROVIDE( metal_segment_lim_target_start = ADDR(.lim) ); + PROVIDE( metal_segment_lim_target_end = ADDR(.lim) + SIZEOF(.lim) ); + /* TEXT SECTION * * The following section contains the code of the program, excluding - * everything that's been allocated into the ITIM already + * everything that's been allocated into the ITIM/LIM already */ .text : { diff --git a/bsp/qemu-sifive-u54mc/metal.ramrodata.lds b/bsp/qemu-sifive-u54mc/metal.ramrodata.lds index 705f52444..be8503f38 100644 --- a/bsp/qemu-sifive-u54mc/metal.ramrodata.lds +++ b/bsp/qemu-sifive-u54mc/metal.ramrodata.lds @@ -26,6 +26,7 @@ PHDRS ram PT_LOAD; itim_init PT_LOAD; text PT_LOAD; + lim_init PT_LOAD; } SECTIONS @@ -170,10 +171,28 @@ SECTIONS PROVIDE( metal_segment_itim_target_start = ADDR(.itim) ); PROVIDE( metal_segment_itim_target_end = ADDR(.itim) + SIZEOF(.itim) ); + /* LIM SECTION + * + * The following sections contain data which is copied from read-only + * memory into a loosely integrated memory (LIM), which is shared with L2 + * cache, during pre-main program initialization. + * + * Generally, the data copied into the LIM should be performance-critical + * functions which benefit from low instruction-fetch latency. + */ + + .lim : ALIGN(8) { + *(.lim .lim.*) + } >testram AT>testram :lim_init + + PROVIDE( metal_segment_lim_source_start = LOADADDR(.lim) ); + PROVIDE( metal_segment_lim_target_start = ADDR(.lim) ); + PROVIDE( metal_segment_lim_target_end = ADDR(.lim) + SIZEOF(.lim) ); + /* TEXT SECTION * * The following section contains the code of the program, excluding - * everything that's been allocated into the ITIM already + * everything that's been allocated into the ITIM/LIM already */ .text : { diff --git a/bsp/qemu-sifive-u54mc/metal.scratchpad.lds b/bsp/qemu-sifive-u54mc/metal.scratchpad.lds index 5adf2461a..bcdbf9e89 100644 --- a/bsp/qemu-sifive-u54mc/metal.scratchpad.lds +++ b/bsp/qemu-sifive-u54mc/metal.scratchpad.lds @@ -23,6 +23,7 @@ PHDRS ram PT_LOAD; itim_init PT_LOAD; text PT_LOAD; + lim_init PT_LOAD; } SECTIONS @@ -170,10 +171,28 @@ SECTIONS PROVIDE( metal_segment_itim_target_start = ADDR(.itim) ); PROVIDE( metal_segment_itim_target_end = ADDR(.itim) + SIZEOF(.itim) ); + /* LIM SECTION + * + * The following sections contain data which is copied from read-only + * memory into a loosely integrated memory (LIM), which is shared with L2 + * cache, during pre-main program initialization. + * + * Generally, the data copied into the LIM should be performance-critical + * functions which benefit from low instruction-fetch latency. + */ + + .lim : ALIGN(8) { + *(.lim .lim.*) + } >testram AT>testram :lim_init + + PROVIDE( metal_segment_lim_source_start = LOADADDR(.lim) ); + PROVIDE( metal_segment_lim_target_start = ADDR(.lim) ); + PROVIDE( metal_segment_lim_target_end = ADDR(.lim) + SIZEOF(.lim) ); + /* TEXT SECTION * * The following section contains the code of the program, excluding - * everything that's been allocated into the ITIM already + * everything that's been allocated into the ITIM/LIM already */ .text : { diff --git a/bsp/sifive-hifive-unleashed/metal.default.lds b/bsp/sifive-hifive-unleashed/metal.default.lds index 5ad4db43c..ef3b4288c 100644 --- a/bsp/sifive-hifive-unleashed/metal.default.lds +++ b/bsp/sifive-hifive-unleashed/metal.default.lds @@ -24,6 +24,7 @@ PHDRS ram PT_LOAD; itim_init PT_LOAD; text PT_LOAD; + lim_init PT_LOAD; } SECTIONS @@ -86,6 +87,10 @@ SECTIONS PROVIDE( metal_itim_1_memory_end = 0x1808000 + 0x10000 ); /* Default zero-scrub to at most 64KB, for limiting RTL simulation run time. */ /* User is recommended to enable the full size for manual RTL simulation run! */ + PROVIDE( metal_lim_0_memory_start = 0x8000000 ); + PROVIDE( metal_lim_0_memory_end = 0x8000000 + 0x10000 ); + /* Default zero-scrub to at most 64KB, for limiting RTL simulation run time. */ + /* User is recommended to enable the full size for manual RTL simulation run! */ PROVIDE( metal_memory_0_memory_start = 0x80000000 ); PROVIDE( metal_memory_0_memory_end = 0x80000000 + 0x10000 ); @@ -187,10 +192,28 @@ SECTIONS PROVIDE( metal_segment_itim_target_start = ADDR(.itim) ); PROVIDE( metal_segment_itim_target_end = ADDR(.itim) + SIZEOF(.itim) ); + /* LIM SECTION + * + * The following sections contain data which is copied from read-only + * memory into a loosely integrated memory (LIM), which is shared with L2 + * cache, during pre-main program initialization. + * + * Generally, the data copied into the LIM should be performance-critical + * functions which benefit from low instruction-fetch latency. + */ + + .lim : ALIGN(8) { + *(.lim .lim.*) + } >ram AT>rom :lim_init + + PROVIDE( metal_segment_lim_source_start = LOADADDR(.lim) ); + PROVIDE( metal_segment_lim_target_start = ADDR(.lim) ); + PROVIDE( metal_segment_lim_target_end = ADDR(.lim) + SIZEOF(.lim) ); + /* TEXT SECTION * * The following section contains the code of the program, excluding - * everything that's been allocated into the ITIM already + * everything that's been allocated into the ITIM/LIM already */ .text : { diff --git a/bsp/sifive-hifive-unleashed/metal.freertos.lds b/bsp/sifive-hifive-unleashed/metal.freertos.lds index 8d50fa08c..3ab330982 100644 --- a/bsp/sifive-hifive-unleashed/metal.freertos.lds +++ b/bsp/sifive-hifive-unleashed/metal.freertos.lds @@ -27,6 +27,7 @@ PHDRS ram PT_LOAD; itim_init PT_LOAD; text PT_LOAD; + lim_init PT_LOAD; } SECTIONS @@ -89,6 +90,10 @@ SECTIONS PROVIDE( metal_itim_1_memory_end = 0x1808000 + 0x10000 ); /* Default zero-scrub to at most 64KB, for limiting RTL simulation run time. */ /* User is recommended to enable the full size for manual RTL simulation run! */ + PROVIDE( metal_lim_0_memory_start = 0x8000000 ); + PROVIDE( metal_lim_0_memory_end = 0x8000000 + 0x10000 ); + /* Default zero-scrub to at most 64KB, for limiting RTL simulation run time. */ + /* User is recommended to enable the full size for manual RTL simulation run! */ PROVIDE( metal_memory_0_memory_start = 0x80000000 ); PROVIDE( metal_memory_0_memory_end = 0x80000000 + 0x10000 ); @@ -198,10 +203,28 @@ SECTIONS PROVIDE( metal_segment_itim_target_start = ADDR(.itim) ); PROVIDE( metal_segment_itim_target_end = ADDR(.itim) + SIZEOF(.itim) ); + /* LIM SECTION + * + * The following sections contain data which is copied from read-only + * memory into a loosely integrated memory (LIM), which is shared with L2 + * cache, during pre-main program initialization. + * + * Generally, the data copied into the LIM should be performance-critical + * functions which benefit from low instruction-fetch latency. + */ + + .lim : ALIGN(8) { + *(.lim .lim.*) + } >ram AT>rom :lim_init + + PROVIDE( metal_segment_lim_source_start = LOADADDR(.lim) ); + PROVIDE( metal_segment_lim_target_start = ADDR(.lim) ); + PROVIDE( metal_segment_lim_target_end = ADDR(.lim) + SIZEOF(.lim) ); + /* TEXT SECTION * * The following section contains the code of the program, excluding - * everything that's been allocated into the ITIM already + * everything that's been allocated into the ITIM/LIM already */ .text : { diff --git a/bsp/sifive-hifive-unleashed/metal.ramrodata.lds b/bsp/sifive-hifive-unleashed/metal.ramrodata.lds index fdbdff9c2..97ee98d9b 100644 --- a/bsp/sifive-hifive-unleashed/metal.ramrodata.lds +++ b/bsp/sifive-hifive-unleashed/metal.ramrodata.lds @@ -28,6 +28,7 @@ PHDRS ram PT_LOAD; itim_init PT_LOAD; text PT_LOAD; + lim_init PT_LOAD; } SECTIONS @@ -90,6 +91,10 @@ SECTIONS PROVIDE( metal_itim_1_memory_end = 0x1808000 + 0x10000 ); /* Default zero-scrub to at most 64KB, for limiting RTL simulation run time. */ /* User is recommended to enable the full size for manual RTL simulation run! */ + PROVIDE( metal_lim_0_memory_start = 0x8000000 ); + PROVIDE( metal_lim_0_memory_end = 0x8000000 + 0x10000 ); + /* Default zero-scrub to at most 64KB, for limiting RTL simulation run time. */ + /* User is recommended to enable the full size for manual RTL simulation run! */ PROVIDE( metal_memory_0_memory_start = 0x80000000 ); PROVIDE( metal_memory_0_memory_end = 0x80000000 + 0x10000 ); @@ -251,10 +256,28 @@ SECTIONS PROVIDE( metal_segment_itim_target_start = ADDR(.itim) ); PROVIDE( metal_segment_itim_target_end = ADDR(.itim) + SIZEOF(.itim) ); + /* LIM SECTION + * + * The following sections contain data which is copied from read-only + * memory into a loosely integrated memory (LIM), which is shared with L2 + * cache, during pre-main program initialization. + * + * Generally, the data copied into the LIM should be performance-critical + * functions which benefit from low instruction-fetch latency. + */ + + .lim : ALIGN(8) { + *(.lim .lim.*) + } >ram AT>rom :lim_init + + PROVIDE( metal_segment_lim_source_start = LOADADDR(.lim) ); + PROVIDE( metal_segment_lim_target_start = ADDR(.lim) ); + PROVIDE( metal_segment_lim_target_end = ADDR(.lim) + SIZEOF(.lim) ); + /* TEXT SECTION * * The following section contains the code of the program, excluding - * everything that's been allocated into the ITIM already + * everything that's been allocated into the ITIM/LIM already */ .text : { diff --git a/bsp/sifive-hifive-unleashed/metal.scratchpad.lds b/bsp/sifive-hifive-unleashed/metal.scratchpad.lds index 43664c1fc..f032c1bb7 100644 --- a/bsp/sifive-hifive-unleashed/metal.scratchpad.lds +++ b/bsp/sifive-hifive-unleashed/metal.scratchpad.lds @@ -25,6 +25,7 @@ PHDRS ram PT_LOAD; itim_init PT_LOAD; text PT_LOAD; + lim_init PT_LOAD; } SECTIONS @@ -172,10 +173,28 @@ SECTIONS PROVIDE( metal_segment_itim_target_start = ADDR(.itim) ); PROVIDE( metal_segment_itim_target_end = ADDR(.itim) + SIZEOF(.itim) ); + /* LIM SECTION + * + * The following sections contain data which is copied from read-only + * memory into a loosely integrated memory (LIM), which is shared with L2 + * cache, during pre-main program initialization. + * + * Generally, the data copied into the LIM should be performance-critical + * functions which benefit from low instruction-fetch latency. + */ + + .lim : ALIGN(8) { + *(.lim .lim.*) + } >ram AT>ram :lim_init + + PROVIDE( metal_segment_lim_source_start = LOADADDR(.lim) ); + PROVIDE( metal_segment_lim_target_start = ADDR(.lim) ); + PROVIDE( metal_segment_lim_target_end = ADDR(.lim) + SIZEOF(.lim) ); + /* TEXT SECTION * * The following section contains the code of the program, excluding - * everything that's been allocated into the ITIM already + * everything that's been allocated into the ITIM/LIM already */ .text : { diff --git a/bsp/sifive-hifive1-revb/metal.default.lds b/bsp/sifive-hifive1-revb/metal.default.lds index 3d04a1af3..094dcb61e 100644 --- a/bsp/sifive-hifive1-revb/metal.default.lds +++ b/bsp/sifive-hifive1-revb/metal.default.lds @@ -24,6 +24,7 @@ PHDRS ram PT_LOAD; itim_init PT_LOAD; text PT_LOAD; + lim_init PT_LOAD; } SECTIONS @@ -179,10 +180,28 @@ SECTIONS PROVIDE( metal_segment_itim_target_start = ADDR(.itim) ); PROVIDE( metal_segment_itim_target_end = ADDR(.itim) + SIZEOF(.itim) ); + /* LIM SECTION + * + * The following sections contain data which is copied from read-only + * memory into a loosely integrated memory (LIM), which is shared with L2 + * cache, during pre-main program initialization. + * + * Generally, the data copied into the LIM should be performance-critical + * functions which benefit from low instruction-fetch latency. + */ + + .lim : ALIGN(8) { + *(.lim .lim.*) + } >ram AT>rom :lim_init + + PROVIDE( metal_segment_lim_source_start = LOADADDR(.lim) ); + PROVIDE( metal_segment_lim_target_start = ADDR(.lim) ); + PROVIDE( metal_segment_lim_target_end = ADDR(.lim) + SIZEOF(.lim) ); + /* TEXT SECTION * * The following section contains the code of the program, excluding - * everything that's been allocated into the ITIM already + * everything that's been allocated into the ITIM/LIM already */ .text : { diff --git a/bsp/sifive-hifive1-revb/metal.freertos.lds b/bsp/sifive-hifive1-revb/metal.freertos.lds index 31c32bcd3..4798504ed 100644 --- a/bsp/sifive-hifive1-revb/metal.freertos.lds +++ b/bsp/sifive-hifive1-revb/metal.freertos.lds @@ -27,6 +27,7 @@ PHDRS ram PT_LOAD; itim_init PT_LOAD; text PT_LOAD; + lim_init PT_LOAD; } SECTIONS @@ -190,10 +191,28 @@ SECTIONS PROVIDE( metal_segment_itim_target_start = ADDR(.itim) ); PROVIDE( metal_segment_itim_target_end = ADDR(.itim) + SIZEOF(.itim) ); + /* LIM SECTION + * + * The following sections contain data which is copied from read-only + * memory into a loosely integrated memory (LIM), which is shared with L2 + * cache, during pre-main program initialization. + * + * Generally, the data copied into the LIM should be performance-critical + * functions which benefit from low instruction-fetch latency. + */ + + .lim : ALIGN(8) { + *(.lim .lim.*) + } >ram AT>rom :lim_init + + PROVIDE( metal_segment_lim_source_start = LOADADDR(.lim) ); + PROVIDE( metal_segment_lim_target_start = ADDR(.lim) ); + PROVIDE( metal_segment_lim_target_end = ADDR(.lim) + SIZEOF(.lim) ); + /* TEXT SECTION * * The following section contains the code of the program, excluding - * everything that's been allocated into the ITIM already + * everything that's been allocated into the ITIM/LIM already */ .text : { diff --git a/bsp/sifive-hifive1-revb/metal.ramrodata.lds b/bsp/sifive-hifive1-revb/metal.ramrodata.lds index 7cc59ba98..6803873ce 100644 --- a/bsp/sifive-hifive1-revb/metal.ramrodata.lds +++ b/bsp/sifive-hifive1-revb/metal.ramrodata.lds @@ -28,6 +28,7 @@ PHDRS ram PT_LOAD; itim_init PT_LOAD; text PT_LOAD; + lim_init PT_LOAD; } SECTIONS @@ -172,10 +173,28 @@ SECTIONS PROVIDE( metal_segment_itim_target_start = ADDR(.itim) ); PROVIDE( metal_segment_itim_target_end = ADDR(.itim) + SIZEOF(.itim) ); + /* LIM SECTION + * + * The following sections contain data which is copied from read-only + * memory into a loosely integrated memory (LIM), which is shared with L2 + * cache, during pre-main program initialization. + * + * Generally, the data copied into the LIM should be performance-critical + * functions which benefit from low instruction-fetch latency. + */ + + .lim : ALIGN(8) { + *(.lim .lim.*) + } >ram AT>rom :lim_init + + PROVIDE( metal_segment_lim_source_start = LOADADDR(.lim) ); + PROVIDE( metal_segment_lim_target_start = ADDR(.lim) ); + PROVIDE( metal_segment_lim_target_end = ADDR(.lim) + SIZEOF(.lim) ); + /* TEXT SECTION * * The following section contains the code of the program, excluding - * everything that's been allocated into the ITIM already + * everything that's been allocated into the ITIM/LIM already */ .text : { diff --git a/bsp/sifive-hifive1-revb/metal.scratchpad.lds b/bsp/sifive-hifive1-revb/metal.scratchpad.lds index b2bc8c1c5..356726912 100644 --- a/bsp/sifive-hifive1-revb/metal.scratchpad.lds +++ b/bsp/sifive-hifive1-revb/metal.scratchpad.lds @@ -25,6 +25,7 @@ PHDRS ram PT_LOAD; itim_init PT_LOAD; text PT_LOAD; + lim_init PT_LOAD; } SECTIONS @@ -172,10 +173,28 @@ SECTIONS PROVIDE( metal_segment_itim_target_start = ADDR(.itim) ); PROVIDE( metal_segment_itim_target_end = ADDR(.itim) + SIZEOF(.itim) ); + /* LIM SECTION + * + * The following sections contain data which is copied from read-only + * memory into a loosely integrated memory (LIM), which is shared with L2 + * cache, during pre-main program initialization. + * + * Generally, the data copied into the LIM should be performance-critical + * functions which benefit from low instruction-fetch latency. + */ + + .lim : ALIGN(8) { + *(.lim .lim.*) + } >ram AT>ram :lim_init + + PROVIDE( metal_segment_lim_source_start = LOADADDR(.lim) ); + PROVIDE( metal_segment_lim_target_start = ADDR(.lim) ); + PROVIDE( metal_segment_lim_target_end = ADDR(.lim) + SIZEOF(.lim) ); + /* TEXT SECTION * * The following section contains the code of the program, excluding - * everything that's been allocated into the ITIM already + * everything that's been allocated into the ITIM/LIM already */ .text : { diff --git a/bsp/sifive-hifive1/metal.default.lds b/bsp/sifive-hifive1/metal.default.lds index 6d9c31062..c5026e650 100644 --- a/bsp/sifive-hifive1/metal.default.lds +++ b/bsp/sifive-hifive1/metal.default.lds @@ -23,6 +23,7 @@ PHDRS ram PT_LOAD; itim_init PT_LOAD; text PT_LOAD; + lim_init PT_LOAD; } SECTIONS @@ -176,10 +177,28 @@ SECTIONS PROVIDE( metal_segment_itim_target_start = ADDR(.itim) ); PROVIDE( metal_segment_itim_target_end = ADDR(.itim) + SIZEOF(.itim) ); + /* LIM SECTION + * + * The following sections contain data which is copied from read-only + * memory into a loosely integrated memory (LIM), which is shared with L2 + * cache, during pre-main program initialization. + * + * Generally, the data copied into the LIM should be performance-critical + * functions which benefit from low instruction-fetch latency. + */ + + .lim : ALIGN(8) { + *(.lim .lim.*) + } >ram AT>rom :lim_init + + PROVIDE( metal_segment_lim_source_start = LOADADDR(.lim) ); + PROVIDE( metal_segment_lim_target_start = ADDR(.lim) ); + PROVIDE( metal_segment_lim_target_end = ADDR(.lim) + SIZEOF(.lim) ); + /* TEXT SECTION * * The following section contains the code of the program, excluding - * everything that's been allocated into the ITIM already + * everything that's been allocated into the ITIM/LIM already */ .text : { diff --git a/bsp/sifive-hifive1/metal.freertos.lds b/bsp/sifive-hifive1/metal.freertos.lds index dd5978ac2..974a7cbf8 100644 --- a/bsp/sifive-hifive1/metal.freertos.lds +++ b/bsp/sifive-hifive1/metal.freertos.lds @@ -26,6 +26,7 @@ PHDRS ram PT_LOAD; itim_init PT_LOAD; text PT_LOAD; + lim_init PT_LOAD; } SECTIONS @@ -187,10 +188,28 @@ SECTIONS PROVIDE( metal_segment_itim_target_start = ADDR(.itim) ); PROVIDE( metal_segment_itim_target_end = ADDR(.itim) + SIZEOF(.itim) ); + /* LIM SECTION + * + * The following sections contain data which is copied from read-only + * memory into a loosely integrated memory (LIM), which is shared with L2 + * cache, during pre-main program initialization. + * + * Generally, the data copied into the LIM should be performance-critical + * functions which benefit from low instruction-fetch latency. + */ + + .lim : ALIGN(8) { + *(.lim .lim.*) + } >ram AT>rom :lim_init + + PROVIDE( metal_segment_lim_source_start = LOADADDR(.lim) ); + PROVIDE( metal_segment_lim_target_start = ADDR(.lim) ); + PROVIDE( metal_segment_lim_target_end = ADDR(.lim) + SIZEOF(.lim) ); + /* TEXT SECTION * * The following section contains the code of the program, excluding - * everything that's been allocated into the ITIM already + * everything that's been allocated into the ITIM/LIM already */ .text : { diff --git a/bsp/sifive-hifive1/metal.ramrodata.lds b/bsp/sifive-hifive1/metal.ramrodata.lds index 11bd35ecb..2c63a096e 100644 --- a/bsp/sifive-hifive1/metal.ramrodata.lds +++ b/bsp/sifive-hifive1/metal.ramrodata.lds @@ -27,6 +27,7 @@ PHDRS ram PT_LOAD; itim_init PT_LOAD; text PT_LOAD; + lim_init PT_LOAD; } SECTIONS @@ -169,10 +170,28 @@ SECTIONS PROVIDE( metal_segment_itim_target_start = ADDR(.itim) ); PROVIDE( metal_segment_itim_target_end = ADDR(.itim) + SIZEOF(.itim) ); + /* LIM SECTION + * + * The following sections contain data which is copied from read-only + * memory into a loosely integrated memory (LIM), which is shared with L2 + * cache, during pre-main program initialization. + * + * Generally, the data copied into the LIM should be performance-critical + * functions which benefit from low instruction-fetch latency. + */ + + .lim : ALIGN(8) { + *(.lim .lim.*) + } >ram AT>rom :lim_init + + PROVIDE( metal_segment_lim_source_start = LOADADDR(.lim) ); + PROVIDE( metal_segment_lim_target_start = ADDR(.lim) ); + PROVIDE( metal_segment_lim_target_end = ADDR(.lim) + SIZEOF(.lim) ); + /* TEXT SECTION * * The following section contains the code of the program, excluding - * everything that's been allocated into the ITIM already + * everything that's been allocated into the ITIM/LIM already */ .text : { diff --git a/bsp/sifive-hifive1/metal.scratchpad.lds b/bsp/sifive-hifive1/metal.scratchpad.lds index dd25328e4..c53ac0ce2 100644 --- a/bsp/sifive-hifive1/metal.scratchpad.lds +++ b/bsp/sifive-hifive1/metal.scratchpad.lds @@ -24,6 +24,7 @@ PHDRS ram PT_LOAD; itim_init PT_LOAD; text PT_LOAD; + lim_init PT_LOAD; } SECTIONS @@ -171,10 +172,28 @@ SECTIONS PROVIDE( metal_segment_itim_target_start = ADDR(.itim) ); PROVIDE( metal_segment_itim_target_end = ADDR(.itim) + SIZEOF(.itim) ); + /* LIM SECTION + * + * The following sections contain data which is copied from read-only + * memory into a loosely integrated memory (LIM), which is shared with L2 + * cache, during pre-main program initialization. + * + * Generally, the data copied into the LIM should be performance-critical + * functions which benefit from low instruction-fetch latency. + */ + + .lim : ALIGN(8) { + *(.lim .lim.*) + } >ram AT>ram :lim_init + + PROVIDE( metal_segment_lim_source_start = LOADADDR(.lim) ); + PROVIDE( metal_segment_lim_target_start = ADDR(.lim) ); + PROVIDE( metal_segment_lim_target_end = ADDR(.lim) + SIZEOF(.lim) ); + /* TEXT SECTION * * The following section contains the code of the program, excluding - * everything that's been allocated into the ITIM already + * everything that's been allocated into the ITIM/LIM already */ .text : { diff --git a/bsp/spike/metal.default.lds b/bsp/spike/metal.default.lds index 414560476..34b473210 100644 --- a/bsp/spike/metal.default.lds +++ b/bsp/spike/metal.default.lds @@ -22,6 +22,7 @@ PHDRS ram PT_LOAD; itim_init PT_LOAD; text PT_LOAD; + lim_init PT_LOAD; } SECTIONS @@ -177,10 +178,28 @@ SECTIONS PROVIDE( metal_segment_itim_target_start = ADDR(.itim) ); PROVIDE( metal_segment_itim_target_end = ADDR(.itim) + SIZEOF(.itim) ); + /* LIM SECTION + * + * The following sections contain data which is copied from read-only + * memory into a loosely integrated memory (LIM), which is shared with L2 + * cache, during pre-main program initialization. + * + * Generally, the data copied into the LIM should be performance-critical + * functions which benefit from low instruction-fetch latency. + */ + + .lim : ALIGN(8) { + *(.lim .lim.*) + } >testram AT>testram :lim_init + + PROVIDE( metal_segment_lim_source_start = LOADADDR(.lim) ); + PROVIDE( metal_segment_lim_target_start = ADDR(.lim) ); + PROVIDE( metal_segment_lim_target_end = ADDR(.lim) + SIZEOF(.lim) ); + /* TEXT SECTION * * The following section contains the code of the program, excluding - * everything that's been allocated into the ITIM already + * everything that's been allocated into the ITIM/LIM already */ .text : { diff --git a/bsp/spike/metal.freertos.lds b/bsp/spike/metal.freertos.lds index 92e6b5125..167072049 100644 --- a/bsp/spike/metal.freertos.lds +++ b/bsp/spike/metal.freertos.lds @@ -25,6 +25,7 @@ PHDRS ram PT_LOAD; itim_init PT_LOAD; text PT_LOAD; + lim_init PT_LOAD; } SECTIONS @@ -188,10 +189,28 @@ SECTIONS PROVIDE( metal_segment_itim_target_start = ADDR(.itim) ); PROVIDE( metal_segment_itim_target_end = ADDR(.itim) + SIZEOF(.itim) ); + /* LIM SECTION + * + * The following sections contain data which is copied from read-only + * memory into a loosely integrated memory (LIM), which is shared with L2 + * cache, during pre-main program initialization. + * + * Generally, the data copied into the LIM should be performance-critical + * functions which benefit from low instruction-fetch latency. + */ + + .lim : ALIGN(8) { + *(.lim .lim.*) + } >testram AT>testram :lim_init + + PROVIDE( metal_segment_lim_source_start = LOADADDR(.lim) ); + PROVIDE( metal_segment_lim_target_start = ADDR(.lim) ); + PROVIDE( metal_segment_lim_target_end = ADDR(.lim) + SIZEOF(.lim) ); + /* TEXT SECTION * * The following section contains the code of the program, excluding - * everything that's been allocated into the ITIM already + * everything that's been allocated into the ITIM/LIM already */ .text : { diff --git a/bsp/spike/metal.ramrodata.lds b/bsp/spike/metal.ramrodata.lds index 26cdef561..2d9771227 100644 --- a/bsp/spike/metal.ramrodata.lds +++ b/bsp/spike/metal.ramrodata.lds @@ -26,6 +26,7 @@ PHDRS ram PT_LOAD; itim_init PT_LOAD; text PT_LOAD; + lim_init PT_LOAD; } SECTIONS @@ -170,10 +171,28 @@ SECTIONS PROVIDE( metal_segment_itim_target_start = ADDR(.itim) ); PROVIDE( metal_segment_itim_target_end = ADDR(.itim) + SIZEOF(.itim) ); + /* LIM SECTION + * + * The following sections contain data which is copied from read-only + * memory into a loosely integrated memory (LIM), which is shared with L2 + * cache, during pre-main program initialization. + * + * Generally, the data copied into the LIM should be performance-critical + * functions which benefit from low instruction-fetch latency. + */ + + .lim : ALIGN(8) { + *(.lim .lim.*) + } >testram AT>testram :lim_init + + PROVIDE( metal_segment_lim_source_start = LOADADDR(.lim) ); + PROVIDE( metal_segment_lim_target_start = ADDR(.lim) ); + PROVIDE( metal_segment_lim_target_end = ADDR(.lim) + SIZEOF(.lim) ); + /* TEXT SECTION * * The following section contains the code of the program, excluding - * everything that's been allocated into the ITIM already + * everything that's been allocated into the ITIM/LIM already */ .text : { diff --git a/bsp/spike/metal.scratchpad.lds b/bsp/spike/metal.scratchpad.lds index b0ada68f6..f078b855a 100644 --- a/bsp/spike/metal.scratchpad.lds +++ b/bsp/spike/metal.scratchpad.lds @@ -23,6 +23,7 @@ PHDRS ram PT_LOAD; itim_init PT_LOAD; text PT_LOAD; + lim_init PT_LOAD; } SECTIONS @@ -170,10 +171,28 @@ SECTIONS PROVIDE( metal_segment_itim_target_start = ADDR(.itim) ); PROVIDE( metal_segment_itim_target_end = ADDR(.itim) + SIZEOF(.itim) ); + /* LIM SECTION + * + * The following sections contain data which is copied from read-only + * memory into a loosely integrated memory (LIM), which is shared with L2 + * cache, during pre-main program initialization. + * + * Generally, the data copied into the LIM should be performance-critical + * functions which benefit from low instruction-fetch latency. + */ + + .lim : ALIGN(8) { + *(.lim .lim.*) + } >testram AT>testram :lim_init + + PROVIDE( metal_segment_lim_source_start = LOADADDR(.lim) ); + PROVIDE( metal_segment_lim_target_start = ADDR(.lim) ); + PROVIDE( metal_segment_lim_target_end = ADDR(.lim) + SIZEOF(.lim) ); + /* TEXT SECTION * * The following section contains the code of the program, excluding - * everything that's been allocated into the ITIM already + * everything that's been allocated into the ITIM/LIM already */ .text : { diff --git a/doc/sphinx/contents.rst b/doc/sphinx/contents.rst index 98e3f8438..c5ed50197 100644 --- a/doc/sphinx/contents.rst +++ b/doc/sphinx/contents.rst @@ -291,4 +291,9 @@ The example programs can be found under the ``software/`` directory. - Demonstrates usage of Sifive L2 performance monitor counter APIs to capture L2 cache event logs. - example-l2pf + - Example for usage and measuring effectiveness of SiFive L2 Prefetcher. + +- example-lim + + - Demonstrates how to designate a function to be linked into the LIM (Loosely-Integrated Memory). diff --git a/freedom-metal b/freedom-metal index 58f40ee37..54b0cbcf2 160000 --- a/freedom-metal +++ b/freedom-metal @@ -1 +1 @@ -Subproject commit 58f40ee376f85998eabbe9e35654b74e1807e03e +Subproject commit 54b0cbcf2bf129efe7ff04afbf89210a6dd29358 diff --git a/scripts/ldscript-generator b/scripts/ldscript-generator index 320c1f5ab..693073eba 160000 --- a/scripts/ldscript-generator +++ b/scripts/ldscript-generator @@ -1 +1 @@ -Subproject commit 320c1f5ab1eddb1d50c38efc80acf607071953f2 +Subproject commit 693073ebafee5b81b2b67f40fafbcaea7723f345 diff --git a/software/example-lim b/software/example-lim new file mode 160000 index 000000000..cd04f0667 --- /dev/null +++ b/software/example-lim @@ -0,0 +1 @@ +Subproject commit cd04f06675b3ba464ffabd72e5800b9ba1313104 diff --git a/wit-manifest.json b/wit-manifest.json index f3b1f7d23..c3f460448 100644 --- a/wit-manifest.json +++ b/wit-manifest.json @@ -5,7 +5,7 @@ "source": "git@github.com:sifive/freedom-devicetree-tools.git" }, { - "commit": "58f40ee376f85998eabbe9e35654b74e1807e03e", + "commit": "54b0cbcf2bf129efe7ff04afbf89210a6dd29358", "name": "freedom-metal", "source": "git@github.com:sifive/freedom-metal.git" }, @@ -20,7 +20,7 @@ "source": "git@github.com:sifive/devicetree-overlay-generator.git" }, { - "commit": "320c1f5ab1eddb1d50c38efc80acf607071953f2", + "commit": "693073ebafee5b81b2b67f40fafbcaea7723f345", "name": "ldscript-generator", "source": "git@github.com:sifive/ldscript-generator.git" }, @@ -263,5 +263,10 @@ "commit": "88e0394e61294152c487512516758bfadfb1d12e", "name": "example-l2pf", "source": "git@github.com:sifive/example-l2pf.git" + }, + { + "commit": "cd04f06675b3ba464ffabd72e5800b9ba1313104", + "name": "example-lim", + "source": "git@github.com:sifive/example-lim.git" } ]