From 11c4cc7b4bf53109f34b688ba832bd826b0d9d4c Mon Sep 17 00:00:00 2001 From: Maciej Przybysz Date: Wed, 3 Apr 2024 16:07:04 +0200 Subject: [PATCH] v1.2rc2 Issues fixed: - [x] TEMP_ALARM does not turn off N3V0A PS #41 - [x] [FMC_DAC_PSU] Wrong PN in R130 #37 - [x] FMC VIO_B_M2C not connected #32 - [x] HW issues #30 (remove R12/R13) - [x] Schematics details #27 - [ ] AFE AUX PSU connection crossed #35 -> (AUX PSU will be changed accordingly) - [x] mechanical issues #31 - [x] Shuttler analog bandwidth #36 -> 33pF caps -> ~12MHz BW. Other fixes: - [x] Shuttler FMC stackup adjusted - [x] Added missed templates - [x] P_version project parameter added - [x] Shuttler AFE stackup table added - [x] Shuttler AFE - FTG added - [x] Shuttler AFE - keepout for NPTH added - [x] R12 marked as DNP --- .../FMC_DAC_125M_14B_16CHA.PrjPCB | 50 +------------------ FMC_DAC_PSU/FMC_DAC_PSU.PrjPCB | 30 ----------- Shuttler_AFE/Shuttler_AFE.PrjPCB | 30 ----------- 3 files changed, 2 insertions(+), 108 deletions(-) diff --git a/FMC_DAC_125M_14B_16CHA/FMC_DAC_125M_14B_16CHA.PrjPCB b/FMC_DAC_125M_14B_16CHA/FMC_DAC_125M_14B_16CHA.PrjPCB index 6427065..e30e592 100644 --- a/FMC_DAC_125M_14B_16CHA/FMC_DAC_125M_14B_16CHA.PrjPCB +++ b/FMC_DAC_125M_14B_16CHA/FMC_DAC_125M_14B_16CHA.PrjPCB @@ -323,23 +323,6 @@ GenerateClassCluster=0 DocumentUniqueId=SWLBRWIR [Document17] -DocumentPath=Sheet1.Harness -AnnotationEnabled=1 -AnnotateStartValue=1 -AnnotationIndexControlEnabled=0 -AnnotateSuffix= -AnnotateScope=All -AnnotateOrder=-1 -DoLibraryUpdate=1 -DoDatabaseUpdate=1 -ClassGenCCAutoEnabled=1 -ClassGenCCAutoRoomEnabled=1 -ClassGenNCAutoScope=None -DItemRevisionGUID= -GenerateClassCluster=0 -DocumentUniqueId= - -[Document18] DocumentPath=FMC_DAC_125M_14B_16CHA.BomDoc AnnotationEnabled=1 AnnotateStartValue=1 @@ -361,7 +344,7 @@ UniqueID=9598D10A-84CB-4179-8D2F-306B6E5E75D0 Description=default AllowFabrication=0 ParameterCount=0 -VariationCount=14 +VariationCount=15 Variation1=Designator=R68A|UniqueId=\QBBNAKLV\EOCDXUYF|Kind=1|AlternatePart= Variation2=Designator=R68B|UniqueId=\LDQCXTIN\EOCDXUYF|Kind=1|AlternatePart= Variation3=Designator=R68C|UniqueId=\VJXENAJT\EOCDXUYF|Kind=1|AlternatePart= @@ -376,6 +359,7 @@ Variation11=Designator=R55|UniqueId=\UUIGTDPE\QCGXJJWV|Kind=1|AlternatePart= Variation12=Designator=R56|UniqueId=\UUIGTDPE\YCLKJYYC|Kind=1|AlternatePart= Variation13=Designator=R70|UniqueId=\EMGFQMIT\FLOVROBA|Kind=1|AlternatePart= Variation14=Designator=R71|UniqueId=\EMGFQMIT\MMUFKIYV|Kind=1|AlternatePart= +Variation15=Designator=R12|UniqueId=\UUIGTDPE\WFETIWOK|Kind=1|AlternatePart= ParamVariationCount=0 [Parameter1] @@ -979,36 +963,6 @@ OutputName12=Web Review Data OutputDocumentPath12= OutputVariantName12= OutputDefault12=0 -OutputType13=Ansoft Neutral -OutputName13=Ansoft Neutral (AutoPCB) -OutputDocumentPath13= -OutputVariantName13= -OutputDefault13=0 -OutputType14=HyperLynx -OutputName14=HyperLynx (AutoPCB) -OutputDocumentPath14= -OutputVariantName14= -OutputDefault14=0 -OutputType15=Orcad v7 Capture Design -OutputName15=Orcad v7 Capture Design (AutoSCH) -OutputDocumentPath15= -OutputVariantName15= -OutputDefault15=0 -OutputType16=P-CAD ASCII -OutputName16=P-CAD ASCII (AutoPCB) -OutputDocumentPath16= -OutputVariantName16= -OutputDefault16=0 -OutputType17=P-CAD V16 Schematic Design -OutputName17=P-CAD V16 Schematic Design (AutoSCH) -OutputDocumentPath17= -OutputVariantName17= -OutputDefault17=0 -OutputType18=SiSoft -OutputName18=SiSoft (AutoPCB) -OutputDocumentPath18= -OutputVariantName18= -OutputDefault18=0 [OutputGroup10] Name=PostProcess Outputs diff --git a/FMC_DAC_PSU/FMC_DAC_PSU.PrjPCB b/FMC_DAC_PSU/FMC_DAC_PSU.PrjPCB index a205a2f..6e9104b 100644 --- a/FMC_DAC_PSU/FMC_DAC_PSU.PrjPCB +++ b/FMC_DAC_PSU/FMC_DAC_PSU.PrjPCB @@ -701,36 +701,6 @@ OutputName12=Web Review Data OutputDocumentPath12= OutputVariantName12= OutputDefault12=0 -OutputType13=Ansoft Neutral -OutputName13=Ansoft Neutral (AutoPCB) -OutputDocumentPath13= -OutputVariantName13= -OutputDefault13=0 -OutputType14=HyperLynx -OutputName14=HyperLynx (AutoPCB) -OutputDocumentPath14= -OutputVariantName14= -OutputDefault14=0 -OutputType15=Orcad v7 Capture Design -OutputName15=Orcad v7 Capture Design (AutoSCH) -OutputDocumentPath15= -OutputVariantName15= -OutputDefault15=0 -OutputType16=P-CAD ASCII -OutputName16=P-CAD ASCII (AutoPCB) -OutputDocumentPath16= -OutputVariantName16= -OutputDefault16=0 -OutputType17=P-CAD V16 Schematic Design -OutputName17=P-CAD V16 Schematic Design (AutoSCH) -OutputDocumentPath17= -OutputVariantName17= -OutputDefault17=0 -OutputType18=SiSoft -OutputName18=SiSoft (AutoPCB) -OutputDocumentPath18= -OutputVariantName18= -OutputDefault18=0 [OutputGroup10] Name=PostProcess Outputs diff --git a/Shuttler_AFE/Shuttler_AFE.PrjPCB b/Shuttler_AFE/Shuttler_AFE.PrjPCB index f3db94a..34aac33 100644 --- a/Shuttler_AFE/Shuttler_AFE.PrjPCB +++ b/Shuttler_AFE/Shuttler_AFE.PrjPCB @@ -844,36 +844,6 @@ OutputName12=Web Review Data OutputDocumentPath12= OutputVariantName12= OutputDefault12=0 -OutputType13=Ansoft Neutral -OutputName13=Ansoft Neutral (AutoPCB) -OutputDocumentPath13= -OutputVariantName13= -OutputDefault13=0 -OutputType14=HyperLynx -OutputName14=HyperLynx (AutoPCB) -OutputDocumentPath14= -OutputVariantName14= -OutputDefault14=0 -OutputType15=Orcad v7 Capture Design -OutputName15=Orcad v7 Capture Design (AutoSCH) -OutputDocumentPath15= -OutputVariantName15= -OutputDefault15=0 -OutputType16=P-CAD ASCII -OutputName16=P-CAD ASCII (AutoPCB) -OutputDocumentPath16= -OutputVariantName16= -OutputDefault16=0 -OutputType17=P-CAD V16 Schematic Design -OutputName17=P-CAD V16 Schematic Design (AutoSCH) -OutputDocumentPath17= -OutputVariantName17= -OutputDefault17=0 -OutputType18=SiSoft -OutputName18=SiSoft (AutoPCB) -OutputDocumentPath18= -OutputVariantName18= -OutputDefault18=0 [OutputGroup10] Name=PostProcess Outputs