From f59eed4108e61ac6358c7066a98dab163eaa3576 Mon Sep 17 00:00:00 2001 From: Madhava Reddy Siddareddygari Date: Wed, 30 Jun 2021 19:29:47 -0700 Subject: [PATCH 1/4] NPU disable unused PCIe BAR NPU device enumeration was failing because of an issue in the cisco ASIC. This patch will fix address the issue by disabling unused BAR. Signed-off-by: Madhava Reddy Siddareddygari --- patch/cisco-npu-disable-other-bars.patch | 90 ++++++++++++++++++++++++ 1 file changed, 90 insertions(+) create mode 100644 patch/cisco-npu-disable-other-bars.patch diff --git a/patch/cisco-npu-disable-other-bars.patch b/patch/cisco-npu-disable-other-bars.patch new file mode 100644 index 000000000..23e46e556 --- /dev/null +++ b/patch/cisco-npu-disable-other-bars.patch @@ -0,0 +1,90 @@ +From 2bc0b2e84866a7733fc05a34bd8a93e165db99cc Mon Sep 17 00:00:00 2001 +From: Madhava Reddy Siddareddygari +Date: Tue, 9 Mar 2021 13:54:28 -0800 +Subject: [PATCH] NPU disable other bars + + This is a port of IOS XR patch + + Spitfire-pacific-disable-all-bars-other-than-0.patch + + to Debian kernel. Modifications from IOS XR: + + a. Only issue an INFO message for changed resources + b. Include the previous resource data in the INFO message + c. Prepare for the possibility of applying patch to + future NPU revisions. + + Original patch message follows: + + For Pacific, only bar 0 is valid. Hence disable all other bars as a work + around for spitfire + + CDETS: CSCvi15029 + + Signed-off-by: Gaurav Gupta + Signed-off-by: Subha Keshavaraj +--- + drivers/pci/quirks.c | 50 ++++++++++++++++++++++++++++++++++++++++++++ + 1 file changed, 50 insertions(+) + +diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c +index af2149632..932d219e7 100644 +--- a/drivers/pci/quirks.c ++++ b/drivers/pci/quirks.c +@@ -5462,3 +5462,53 @@ static void apex_pci_fixup_class(struct pci_dev *pdev) + } + DECLARE_PCI_FIXUP_CLASS_HEADER(0x1ac1, 0x089a, + PCI_CLASS_NOT_DEFINED, 8, apex_pci_fixup_class); ++ ++#define PCI_DEVICE_ID_LEABA_PACIFIC 0xabcd ++#define PCI_DEVICE_ID_LEABA_GIBRALTAR 0xa001 ++#define PCI_DEVICE_ID_LEABA_GRAPHENE 0xa003 ++#define PCI_DEVICE_ID_LEABA_PALLADIUM 0xa004 ++#define PCI_DEVICE_ID_LEABA_ARGON 0xa005 ++#define PCI_DEVICE_ID_LEABA_KRYPTON 0xa006 ++ ++/* ++ * For Pacific A0, only BAR 0 is valid ++ */ ++static void silicon_one_fixup(struct pci_dev *dev) ++{ ++ int i; ++ struct resource *r; ++ ++ for (i = 1; i <= PCI_ROM_RESOURCE; i++) { ++ r = &dev->resource[i]; ++ if (!r->start && !r->end && !r->flags) ++ continue; ++ ++ dev_info(&dev->dev, "Cisco Silicon One BAR %d %pR fixed up\n", i, r); ++ r->start = 0; ++ r->end = 0; ++ r->flags = 0; ++ } ++ /* ++ * Pacific device was misbehaving during rescan not enumerating ++ * memory for bar. Due to this HW issue, added this workaround ++ * and verified that during rescan memory gets assigned properly ++ * to the device. This is only a temporary fix. ++ */ ++ dev->class = PCI_CLASS_MEMORY_OTHER << 8; ++ dev_info(&dev->dev, "Cisco Silicon One class adjusted\n"); ++} ++DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SYNOPSYS, PCI_DEVICE_ID_LEABA_PACIFIC, ++ silicon_one_fixup); ++DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CISCO, PCI_DEVICE_ID_LEABA_PACIFIC, ++ silicon_one_fixup); ++DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CISCO, PCI_DEVICE_ID_LEABA_GIBRALTAR, ++ silicon_one_fixup); ++DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CISCO, PCI_DEVICE_ID_LEABA_GRAPHENE, ++ silicon_one_fixup); ++DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CISCO, PCI_DEVICE_ID_LEABA_PALLADIUM, ++ silicon_one_fixup); ++DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CISCO, PCI_DEVICE_ID_LEABA_ARGON, ++ silicon_one_fixup); ++DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CISCO, PCI_DEVICE_ID_LEABA_KRYPTON, ++ silicon_one_fixup); ++ +-- +2.26.2 + From a199d39fe6cd0e1e1c8a48edc0323f8222cad539 Mon Sep 17 00:00:00 2001 From: Madhava Reddy Siddareddygari Date: Mon, 12 Jul 2021 23:32:47 -0700 Subject: [PATCH 2/4] Updated with review comments Signed-off-by: Madhava Reddy Siddareddygari --- patch/cisco-npu-disable-other-bars.patch | 73 ++++++++++-------------- 1 file changed, 31 insertions(+), 42 deletions(-) diff --git a/patch/cisco-npu-disable-other-bars.patch b/patch/cisco-npu-disable-other-bars.patch index 23e46e556..10a8b16df 100644 --- a/patch/cisco-npu-disable-other-bars.patch +++ b/patch/cisco-npu-disable-other-bars.patch @@ -1,37 +1,24 @@ -From 2bc0b2e84866a7733fc05a34bd8a93e165db99cc Mon Sep 17 00:00:00 2001 +From abed4e61fa2865893ccb4f0da8c31ab9d431c4d9 Mon Sep 17 00:00:00 2001 From: Madhava Reddy Siddareddygari -Date: Tue, 9 Mar 2021 13:54:28 -0800 -Subject: [PATCH] NPU disable other bars +Date: Mon, 12 Jul 2021 23:21:08 -0700 +Subject: [PATCH] NPU disable unused PCI BAR - This is a port of IOS XR patch +For Cisco ASIC only BAR0 is valid. Not disabling other BAR's +was resulting in pci_enable_device function failure. +Further debugging and consultion with Hardware team, issue seems +to be related to ASIC and workaround suggested is to disable +unused PCI BAR - Spitfire-pacific-disable-all-bars-other-than-0.patch - - to Debian kernel. Modifications from IOS XR: - - a. Only issue an INFO message for changed resources - b. Include the previous resource data in the INFO message - c. Prepare for the possibility of applying patch to - future NPU revisions. - - Original patch message follows: - - For Pacific, only bar 0 is valid. Hence disable all other bars as a work - around for spitfire - - CDETS: CSCvi15029 - - Signed-off-by: Gaurav Gupta - Signed-off-by: Subha Keshavaraj +Signed-off-by: Madhava Reddy Siddareddygari --- - drivers/pci/quirks.c | 50 ++++++++++++++++++++++++++++++++++++++++++++ - 1 file changed, 50 insertions(+) + drivers/pci/quirks.c | 52 ++++++++++++++++++++++++++++++++++++++++++++ + 1 file changed, 52 insertions(+) diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c -index af2149632..932d219e7 100644 +index af2149632..1772d8304 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c -@@ -5462,3 +5462,53 @@ static void apex_pci_fixup_class(struct pci_dev *pdev) +@@ -5462,3 +5462,55 @@ static void apex_pci_fixup_class(struct pci_dev *pdev) } DECLARE_PCI_FIXUP_CLASS_HEADER(0x1ac1, 0x089a, PCI_CLASS_NOT_DEFINED, 8, apex_pci_fixup_class); @@ -56,7 +43,8 @@ index af2149632..932d219e7 100644 + if (!r->start && !r->end && !r->flags) + continue; + -+ dev_info(&dev->dev, "Cisco Silicon One BAR %d %pR fixed up\n", i, r); ++ dev_info(&dev->dev, ++ "Cisco Silicon One BAR %d %pR fixed up\n", i, r); + r->start = 0; + r->end = 0; + r->flags = 0; @@ -70,21 +58,22 @@ index af2149632..932d219e7 100644 + dev->class = PCI_CLASS_MEMORY_OTHER << 8; + dev_info(&dev->dev, "Cisco Silicon One class adjusted\n"); +} -+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SYNOPSYS, PCI_DEVICE_ID_LEABA_PACIFIC, -+ silicon_one_fixup); -+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CISCO, PCI_DEVICE_ID_LEABA_PACIFIC, -+ silicon_one_fixup); -+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CISCO, PCI_DEVICE_ID_LEABA_GIBRALTAR, -+ silicon_one_fixup); -+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CISCO, PCI_DEVICE_ID_LEABA_GRAPHENE, -+ silicon_one_fixup); -+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CISCO, PCI_DEVICE_ID_LEABA_PALLADIUM, -+ silicon_one_fixup); -+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CISCO, PCI_DEVICE_ID_LEABA_ARGON, -+ silicon_one_fixup); -+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CISCO, PCI_DEVICE_ID_LEABA_KRYPTON, -+ silicon_one_fixup); ++DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SYNOPSYS, ++ PCI_DEVICE_ID_LEABA_PACIFIC, silicon_one_fixup); ++DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CISCO, ++ PCI_DEVICE_ID_LEABA_PACIFIC, silicon_one_fixup); ++DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CISCO, ++ PCI_DEVICE_ID_LEABA_GIBRALTAR, silicon_one_fixup); ++DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CISCO, ++ PCI_DEVICE_ID_LEABA_GRAPHENE, silicon_one_fixup); ++DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CISCO, ++ PCI_DEVICE_ID_LEABA_PALLADIUM, silicon_one_fixup); ++DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CISCO, ++ PCI_DEVICE_ID_LEABA_ARGON, silicon_one_fixup); ++DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CISCO, ++ PCI_DEVICE_ID_LEABA_KRYPTON, silicon_one_fixup); ++ + -- -2.26.2 +2.26.2.dirty From ac3d6879b27adab7a168fe33dcb85b6679539cb4 Mon Sep 17 00:00:00 2001 From: Madhava Reddy Siddareddygari Date: Mon, 12 Jul 2021 23:38:21 -0700 Subject: [PATCH 3/4] Updated patch with review comments Signed-off-by: Madhava Reddy Siddareddygari --- patch/cisco-npu-disable-other-bars.patch | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/patch/cisco-npu-disable-other-bars.patch b/patch/cisco-npu-disable-other-bars.patch index 10a8b16df..d6e4557a6 100644 --- a/patch/cisco-npu-disable-other-bars.patch +++ b/patch/cisco-npu-disable-other-bars.patch @@ -75,5 +75,5 @@ index af2149632..1772d8304 100644 + + -- -2.26.2.dirty +2.26.2 From 81cec9d656caafb8a8462ed1ec7a4c9969bce9a3 Mon Sep 17 00:00:00 2001 From: Madhava Reddy Siddareddygari Date: Mon, 16 Aug 2021 13:00:16 -0700 Subject: [PATCH 4/4] Review comments incorporated Signed-off-by: Madhava Reddy Siddareddygari --- patch/cisco-npu-disable-other-bars.patch | 56 ++++++++++++------------ patch/series | 2 + 2 files changed, 31 insertions(+), 27 deletions(-) diff --git a/patch/cisco-npu-disable-other-bars.patch b/patch/cisco-npu-disable-other-bars.patch index d6e4557a6..c6c36ae61 100644 --- a/patch/cisco-npu-disable-other-bars.patch +++ b/patch/cisco-npu-disable-other-bars.patch @@ -1,24 +1,24 @@ -From abed4e61fa2865893ccb4f0da8c31ab9d431c4d9 Mon Sep 17 00:00:00 2001 +From 0be339b4c8468138dfe1a30de29511e94b846af6 Mon Sep 17 00:00:00 2001 From: Madhava Reddy Siddareddygari -Date: Mon, 12 Jul 2021 23:21:08 -0700 +Date: Mon, 16 Aug 2021 12:55:37 -0700 Subject: [PATCH] NPU disable unused PCI BAR For Cisco ASIC only BAR0 is valid. Not disabling other BAR's -was resulting in pci_enable_device function failure. -Further debugging and consultion with Hardware team, issue seems -to be related to ASIC and workaround suggested is to disable -unused PCI BAR +was resulting in pci_enable_device function failure in P0 +Pacific ASIC's. Further debugging and consultion with Hardware +team, issue seems to be related to only P0 version of ASIC and +workaround suggested is to disable unused PCI BAR. Signed-off-by: Madhava Reddy Siddareddygari --- - drivers/pci/quirks.c | 52 ++++++++++++++++++++++++++++++++++++++++++++ - 1 file changed, 52 insertions(+) + drivers/pci/quirks.c | 54 ++++++++++++++++++++++++++++++++++++++++++++ + 1 file changed, 54 insertions(+) diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c -index af2149632..1772d8304 100644 +index af2149632..8b99883e1 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c -@@ -5462,3 +5462,55 @@ static void apex_pci_fixup_class(struct pci_dev *pdev) +@@ -5462,3 +5462,57 @@ static void apex_pci_fixup_class(struct pci_dev *pdev) } DECLARE_PCI_FIXUP_CLASS_HEADER(0x1ac1, 0x089a, PCI_CLASS_NOT_DEFINED, 8, apex_pci_fixup_class); @@ -43,8 +43,9 @@ index af2149632..1772d8304 100644 + if (!r->start && !r->end && !r->flags) + continue; + -+ dev_info(&dev->dev, -+ "Cisco Silicon One BAR %d %pR fixed up\n", i, r); ++ dev_info(&dev->dev, ++ "Cisco Silicon One BAR %d %pR disabled due to " ++ "NPU hardware bug in P0 Pacific ASIC\n", i, r); + r->start = 0; + r->end = 0; + r->flags = 0; @@ -53,25 +54,26 @@ index af2149632..1772d8304 100644 + * Pacific device was misbehaving during rescan not enumerating + * memory for bar. Due to this HW issue, added this workaround + * and verified that during rescan memory gets assigned properly -+ * to the device. This is only a temporary fix. ++ * to the device. This is only a temporary fix for pacific ASIC ++ * only + */ + dev->class = PCI_CLASS_MEMORY_OTHER << 8; + dev_info(&dev->dev, "Cisco Silicon One class adjusted\n"); +} -+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SYNOPSYS, -+ PCI_DEVICE_ID_LEABA_PACIFIC, silicon_one_fixup); -+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CISCO, -+ PCI_DEVICE_ID_LEABA_PACIFIC, silicon_one_fixup); -+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CISCO, -+ PCI_DEVICE_ID_LEABA_GIBRALTAR, silicon_one_fixup); -+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CISCO, -+ PCI_DEVICE_ID_LEABA_GRAPHENE, silicon_one_fixup); -+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CISCO, -+ PCI_DEVICE_ID_LEABA_PALLADIUM, silicon_one_fixup); -+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CISCO, -+ PCI_DEVICE_ID_LEABA_ARGON, silicon_one_fixup); -+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CISCO, -+ PCI_DEVICE_ID_LEABA_KRYPTON, silicon_one_fixup); ++DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SYNOPSYS, PCI_DEVICE_ID_LEABA_PACIFIC, ++ silicon_one_fixup); ++DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CISCO, PCI_DEVICE_ID_LEABA_PACIFIC, ++ silicon_one_fixup); ++DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CISCO, PCI_DEVICE_ID_LEABA_GIBRALTAR, ++ silicon_one_fixup); ++DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CISCO, PCI_DEVICE_ID_LEABA_GRAPHENE, ++ silicon_one_fixup); ++DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CISCO, PCI_DEVICE_ID_LEABA_PALLADIUM, ++ silicon_one_fixup); ++DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CISCO, PCI_DEVICE_ID_LEABA_ARGON, ++ silicon_one_fixup); ++DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CISCO, PCI_DEVICE_ID_LEABA_KRYPTON, ++ silicon_one_fixup); + + -- diff --git a/patch/series b/patch/series index a85ed87bb..57aac35da 100755 --- a/patch/series +++ b/patch/series @@ -83,6 +83,8 @@ driver-ixgbe-external-phy.patch 0030-hwmon-Add-convience-macro-to-define-simple-static-se.patch 0031-backport-nvme-Add-hardware-monitoring-support.patch 0032-platform-mellanox-mlxreg-hotplug-Use-capability-regi.patch + +cisco-npu-disable-other-bars.patch ############################################################ # # Internal patches will be added below (placeholder)