From 464d2cdbb9d6283124babcbb4b0df3aca0b53d68 Mon Sep 17 00:00:00 2001 From: Stephen Sun <5379172+stephenxs@users.noreply.github.com> Date: Thu, 9 Feb 2023 10:00:18 +0800 Subject: [PATCH] Update linux kernel for hw-mgmt V.7.0020.4104 (#305) * Update linux kernel for hw-mgmt V.7.0020.4104 * Update kernel configuration Signed-off-by: Stephen Sun * Update kconfig Signed-off-by: Stephen Sun * Remove ACPI and ARCH_SUPPORTS_ACPI because they will be 'y' according to the dependencies Signed-off-by: Stephen Sun --------- Signed-off-by: Stephen Sun --- ...6-mlx-platform-Add-initial-support-f.patch | 10 +- ...-platform-Make-activation-of-some-dr.patch | 120 ++++++ ...-platform-Add-cosmetic-changes-for-a.patch | 84 +++++ ...-support-for-systems-equipped-with-t.patch | 155 ++++++++ ...x-Introduce-support-for-COMe-NVSwitc.patch | 357 ++++++++++++++++++ ...-platform-Add-support-for-new-system.patch | 97 +++++ ...ox-Add-COME-board-revision-register.patch} | 46 ++- ...upport-for-Seiko-Instruments-S-34TS0.patch | 47 +++ ...x-mlxreg-io-Add-locking-for-io-opera.patch | 106 ++++++ ...register-setting-for-400KHz-frequenc.patch | 30 ++ ...x-mlxreg-lc-Fix-cleanup-on-failure-a.patch | 194 ++++++++++ ...support-for-OSFP-transceiver-modules.patch | 59 +++ ...support-for-Infineon-Digital-Multi-p.patch | 271 +++++++++++++ ...sensors-readouts-for-MPS-Multi-phase.patch | 65 ++++ patch/kconfig-inclusions | 7 + patch/series | 14 +- 16 files changed, 1639 insertions(+), 23 deletions(-) create mode 100644 patch/0157-platform-x86-mlx-platform-Make-activation-of-some-dr.patch create mode 100644 patch/0158-platform-x86-mlx-platform-Add-cosmetic-changes-for-a.patch create mode 100644 patch/0159-mlx-platform-Add-support-for-systems-equipped-with-t.patch create mode 100644 patch/0160-platform-mellanox-Introduce-support-for-COMe-NVSwitc.patch create mode 100644 patch/0161-platform-x86-mlx-platform-Add-support-for-new-system.patch rename patch/{0163-platform-mellanox-Add-COME-board-revision-register.patch => 0162-platform-mellanox-Add-COME-board-revision-register.patch} (68%) create mode 100644 patch/0164-hwmon-jc42-Add-support-for-Seiko-Instruments-S-34TS0.patch create mode 100644 patch/0165-platform-mellanox-mlxreg-io-Add-locking-for-io-opera.patch create mode 100644 patch/0170-i2c-mlxcpld-Fix-register-setting-for-400KHz-frequenc.patch create mode 100644 patch/0171-platform-mellanox-mlxreg-lc-Fix-cleanup-on-failure-a.patch create mode 100644 patch/0173-core-Add-support-for-OSFP-transceiver-modules.patch create mode 100644 patch/0175-hwmon-pmbus-Add-support-for-Infineon-Digital-Multi-p.patch create mode 100644 patch/0180-hwmon-pmbus-Fix-sensors-readouts-for-MPS-Multi-phase.patch diff --git a/patch/0056-platform-x86-mlx-platform-Add-initial-support-f.patch b/patch/0056-platform-x86-mlx-platform-Add-initial-support-f.patch index 1d1496dec103..0864b9d6fe18 100644 --- a/patch/0056-platform-x86-mlx-platform-Add-initial-support-f.patch +++ b/patch/0056-platform-x86-mlx-platform-Add-initial-support-f.patch @@ -1,7 +1,8 @@ +From 1fe47720483933d41d480ae51c3487a2f34e6e1a Mon Sep 17 00:00:00 2001 From: Vadim Pasternak Date: Mon, 12 Jul 2021 16:39:11 +0000 -Subject: 0056 platform/x86: mlx-platform: Add initial support - for new modular system +Subject: [PATCH backport for v5.10 56/97] platform/x86: mlx-platform: Add + initial support for new modular system Add initial chassis management support for Nvidia modular Ethernet switch systems MSN4800, providing a high performance switching solution @@ -33,8 +34,7 @@ line card. The line cards are hot-pluggable. Line cards are connected to the chassis through I2C interface for the chassis management operations and through PCIe for the networking -operations. Future line cards could be connected to the chassis through -InfiniBand fabric, instead of PCIe. +operations. The first type of line card supports 16x100GbE QSFP28 Ethernet ports. Those line cards equipped with the programmable devices aimed for @@ -2884,5 +2884,5 @@ index 8bce3da32a42..6d14eb3dab50 100644 .callback = mlxplat_dmi_msn274x_matched, .matches = { -- -2.17.1 +2.20.1 diff --git a/patch/0157-platform-x86-mlx-platform-Make-activation-of-some-dr.patch b/patch/0157-platform-x86-mlx-platform-Make-activation-of-some-dr.patch new file mode 100644 index 000000000000..0bea5c955d35 --- /dev/null +++ b/patch/0157-platform-x86-mlx-platform-Make-activation-of-some-dr.patch @@ -0,0 +1,120 @@ +From b384a287a5732f7ea3b6e0b13b1aa6ba0d70c440 Mon Sep 17 00:00:00 2001 +From: Vadim Pasternak +Date: Mon, 14 Feb 2022 09:46:16 +0200 +Subject: [PATCH platform-next 1/8] platform/x86: mlx-platform: Make activation + of some drivers conditional + +Current assumption in driver that any system is capable of LED, +hotplug or watchdog support. It could be not true for some new coming +systems. +Add validation for LED, hotplug, watchdog configuration and skip +activation of relevant drivers if not configured. + +Signed-off-by: Vadim Pasternak +--- + drivers/platform/x86/mlx-platform.c | 62 ++++++++++++++++------------- + 1 file changed, 35 insertions(+), 27 deletions(-) + +diff --git a/drivers/platform/x86/mlx-platform.c b/drivers/platform/x86/mlx-platform.c +index fac4b6dcf..e0a35412f 100644 +--- a/drivers/platform/x86/mlx-platform.c ++++ b/drivers/platform/x86/mlx-platform.c +@@ -5206,16 +5206,18 @@ static int __init mlxplat_init(void) + } + + /* Add hotplug driver */ +- mlxplat_hotplug->regmap = priv->regmap; +- priv->pdev_hotplug = platform_device_register_resndata( +- &mlxplat_dev->dev, "mlxreg-hotplug", +- PLATFORM_DEVID_NONE, +- mlxplat_mlxcpld_resources, +- ARRAY_SIZE(mlxplat_mlxcpld_resources), +- mlxplat_hotplug, sizeof(*mlxplat_hotplug)); +- if (IS_ERR(priv->pdev_hotplug)) { +- err = PTR_ERR(priv->pdev_hotplug); +- goto fail_platform_mux_register; ++ if (mlxplat_hotplug) { ++ mlxplat_hotplug->regmap = priv->regmap; ++ priv->pdev_hotplug = ++ platform_device_register_resndata(&mlxplat_dev->dev, ++ "mlxreg-hotplug", PLATFORM_DEVID_NONE, ++ mlxplat_mlxcpld_resources, ++ ARRAY_SIZE(mlxplat_mlxcpld_resources), ++ mlxplat_hotplug, sizeof(*mlxplat_hotplug)); ++ if (IS_ERR(priv->pdev_hotplug)) { ++ err = PTR_ERR(priv->pdev_hotplug); ++ goto fail_platform_mux_register; ++ } + } + + /* Set default registers. */ +@@ -5228,24 +5230,26 @@ static int __init mlxplat_init(void) + } + + /* Add LED driver. */ +- mlxplat_led->regmap = priv->regmap; +- priv->pdev_led = platform_device_register_resndata( +- &mlxplat_dev->dev, "leds-mlxreg", +- PLATFORM_DEVID_NONE, NULL, 0, +- mlxplat_led, sizeof(*mlxplat_led)); +- if (IS_ERR(priv->pdev_led)) { +- err = PTR_ERR(priv->pdev_led); +- goto fail_platform_hotplug_register; ++ if (mlxplat_led) { ++ mlxplat_led->regmap = priv->regmap; ++ priv->pdev_led = ++ platform_device_register_resndata(&mlxplat_dev->dev, "leds-mlxreg", ++ PLATFORM_DEVID_NONE, NULL, 0, mlxplat_led, ++ sizeof(*mlxplat_led)); ++ if (IS_ERR(priv->pdev_led)) { ++ err = PTR_ERR(priv->pdev_led); ++ goto fail_platform_hotplug_register; ++ } + } + + /* Add registers io access driver. */ + if (mlxplat_regs_io) { + mlxplat_regs_io->regmap = priv->regmap; +- priv->pdev_io_regs = platform_device_register_resndata( +- &mlxplat_dev->dev, "mlxreg-io", +- PLATFORM_DEVID_NONE, NULL, 0, +- mlxplat_regs_io, +- sizeof(*mlxplat_regs_io)); ++ priv->pdev_io_regs = platform_device_register_resndata(&mlxplat_dev->dev, ++ "mlxreg-io", ++ PLATFORM_DEVID_NONE, NULL, ++ 0, mlxplat_regs_io, ++ sizeof(*mlxplat_regs_io)); + if (IS_ERR(priv->pdev_io_regs)) { + err = PTR_ERR(priv->pdev_io_regs); + goto fail_platform_led_register; +@@ -5302,9 +5306,11 @@ static int __init mlxplat_init(void) + if (mlxplat_regs_io) + platform_device_unregister(priv->pdev_io_regs); + fail_platform_led_register: +- platform_device_unregister(priv->pdev_led); ++ if (mlxplat_led) ++ platform_device_unregister(priv->pdev_led); + fail_platform_hotplug_register: +- platform_device_unregister(priv->pdev_hotplug); ++ if (mlxplat_hotplug) ++ platform_device_unregister(priv->pdev_hotplug); + fail_platform_mux_register: + while (--i >= 0) + platform_device_unregister(priv->pdev_mux[i]); +@@ -5327,8 +5333,10 @@ static void __exit mlxplat_exit(void) + platform_device_unregister(priv->pdev_fan); + if (priv->pdev_io_regs) + platform_device_unregister(priv->pdev_io_regs); +- platform_device_unregister(priv->pdev_led); +- platform_device_unregister(priv->pdev_hotplug); ++ if (priv->pdev_led) ++ platform_device_unregister(priv->pdev_led); ++ if (priv->pdev_hotplug) ++ platform_device_unregister(priv->pdev_hotplug); + + for (i = mlxplat_mux_num - 1; i >= 0 ; i--) + platform_device_unregister(priv->pdev_mux[i]); +-- +2.20.1 + diff --git a/patch/0158-platform-x86-mlx-platform-Add-cosmetic-changes-for-a.patch b/patch/0158-platform-x86-mlx-platform-Add-cosmetic-changes-for-a.patch new file mode 100644 index 000000000000..3696e76d8bb4 --- /dev/null +++ b/patch/0158-platform-x86-mlx-platform-Add-cosmetic-changes-for-a.patch @@ -0,0 +1,84 @@ +From cd26dadb7e9c5eedb4e24cd60d4de1cda0e8f889 Mon Sep 17 00:00:00 2001 +From: Vadim Pasternak +Date: Mon, 14 Feb 2022 10:07:11 +0200 +Subject: [PATCH platform-next 2/8] platform/x86: mlx-platform: Add cosmetic + changes for alignment + +Align the first argument with open parenthesis for +platform_device_register_resndata() calls. + +Signed-off-by: Vadim Pasternak +--- + drivers/platform/x86/mlx-platform.c | 36 +++++++++++++---------------- + 1 file changed, 16 insertions(+), 20 deletions(-) + +diff --git a/drivers/platform/x86/mlx-platform.c b/drivers/platform/x86/mlx-platform.c +index e0a35412f..a74fcd9d1 100644 +--- a/drivers/platform/x86/mlx-platform.c ++++ b/drivers/platform/x86/mlx-platform.c +@@ -5183,22 +5183,20 @@ static int __init mlxplat_init(void) + nr = (nr == mlxplat_max_adap_num) ? -1 : nr; + if (mlxplat_i2c) + mlxplat_i2c->regmap = priv->regmap; +- priv->pdev_i2c = platform_device_register_resndata( +- &mlxplat_dev->dev, "i2c_mlxcpld", +- nr, mlxplat_mlxcpld_resources, +- ARRAY_SIZE(mlxplat_mlxcpld_resources), +- mlxplat_i2c, sizeof(*mlxplat_i2c)); ++ priv->pdev_i2c = platform_device_register_resndata(&mlxplat_dev->dev, "i2c_mlxcpld", ++ nr, mlxplat_mlxcpld_resources, ++ ARRAY_SIZE(mlxplat_mlxcpld_resources), ++ mlxplat_i2c, sizeof(*mlxplat_i2c)); + if (IS_ERR(priv->pdev_i2c)) { + err = PTR_ERR(priv->pdev_i2c); + goto fail_alloc; + } + + for (i = 0; i < mlxplat_mux_num; i++) { +- priv->pdev_mux[i] = platform_device_register_resndata( +- &priv->pdev_i2c->dev, +- "i2c-mux-reg", i, NULL, +- 0, &mlxplat_mux_data[i], +- sizeof(mlxplat_mux_data[i])); ++ priv->pdev_mux[i] = platform_device_register_resndata(&priv->pdev_i2c->dev, ++ "i2c-mux-reg", i, NULL, 0, ++ &mlxplat_mux_data[i], ++ sizeof(mlxplat_mux_data[i])); + if (IS_ERR(priv->pdev_mux[i])) { + err = PTR_ERR(priv->pdev_mux[i]); + goto fail_platform_mux_register; +@@ -5259,11 +5257,10 @@ static int __init mlxplat_init(void) + /* Add FAN driver. */ + if (mlxplat_fan) { + mlxplat_fan->regmap = priv->regmap; +- priv->pdev_fan = platform_device_register_resndata( +- &mlxplat_dev->dev, "mlxreg-fan", +- PLATFORM_DEVID_NONE, NULL, 0, +- mlxplat_fan, +- sizeof(*mlxplat_fan)); ++ priv->pdev_fan = platform_device_register_resndata(&mlxplat_dev->dev, "mlxreg-fan", ++ PLATFORM_DEVID_NONE, NULL, 0, ++ mlxplat_fan, ++ sizeof(*mlxplat_fan)); + if (IS_ERR(priv->pdev_fan)) { + err = PTR_ERR(priv->pdev_fan); + goto fail_platform_io_regs_register; +@@ -5277,11 +5274,10 @@ static int __init mlxplat_init(void) + for (j = 0; j < MLXPLAT_CPLD_WD_MAX_DEVS; j++) { + if (mlxplat_wd_data[j]) { + mlxplat_wd_data[j]->regmap = priv->regmap; +- priv->pdev_wd[j] = platform_device_register_resndata( +- &mlxplat_dev->dev, "mlx-wdt", +- j, NULL, 0, +- mlxplat_wd_data[j], +- sizeof(*mlxplat_wd_data[j])); ++ priv->pdev_wd[j] = ++ platform_device_register_resndata(&mlxplat_dev->dev, "mlx-wdt", j, ++ NULL, 0, mlxplat_wd_data[j], ++ sizeof(*mlxplat_wd_data[j])); + if (IS_ERR(priv->pdev_wd[j])) { + err = PTR_ERR(priv->pdev_wd[j]); + goto fail_platform_wd_register; +-- +2.20.1 + diff --git a/patch/0159-mlx-platform-Add-support-for-systems-equipped-with-t.patch b/patch/0159-mlx-platform-Add-support-for-systems-equipped-with-t.patch new file mode 100644 index 000000000000..9f8c00636ad7 --- /dev/null +++ b/patch/0159-mlx-platform-Add-support-for-systems-equipped-with-t.patch @@ -0,0 +1,155 @@ +From a16c819d0896932ca52006fc0ba1c977bd2ad7f6 Mon Sep 17 00:00:00 2001 +From: Vadim Pasternak +Date: Wed, 26 Jan 2022 17:16:26 +0200 +Subject: [PATCH platform backport v5.10 03/10] mlx-platform: Add support for + systems equipped with two ASICs + +Motivation is to support new systems equipped with two ASICs. + +Extend driver with: +- The second ASIC health event. +- Per ASIC reset control, triggering reset of ASIC internal resources + and restarting ASIC initialization flow. + +Signed-off-by: Vadim Pasternak +Reviewed-by: Oleksandr Shamray +--- + drivers/platform/x86/mlx-platform.c | 52 ++++++++++++++++++++++++++++- + 1 file changed, 51 insertions(+), 1 deletion(-) + +diff --git a/drivers/platform/x86/mlx-platform.c b/drivers/platform/x86/mlx-platform.c +index a74fcd9d1..cbe9eab34 100644 +--- a/drivers/platform/x86/mlx-platform.c ++++ b/drivers/platform/x86/mlx-platform.c +@@ -34,6 +34,7 @@ + #define MLXPLAT_CPLD_LPC_REG_CPLD3_PN1_OFFSET 0x09 + #define MLXPLAT_CPLD_LPC_REG_CPLD4_PN_OFFSET 0x0a + #define MLXPLAT_CPLD_LPC_REG_CPLD4_PN1_OFFSET 0x0b ++#define MLXPLAT_CPLD_LPC_REG_RESET_GP2_OFFSET 0x19 + #define MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET 0x1c + #define MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET 0x1d + #define MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET 0x1e +@@ -69,6 +70,9 @@ + #define MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET 0x50 + #define MLXPLAT_CPLD_LPC_REG_ASIC_EVENT_OFFSET 0x51 + #define MLXPLAT_CPLD_LPC_REG_ASIC_MASK_OFFSET 0x52 ++#define MLXPLAT_CPLD_LPC_REG_ASIC2_HEALTH_OFFSET 0x53 ++#define MLXPLAT_CPLD_LPC_REG_ASIC2_EVENT_OFFSET 0x54 ++#define MLXPLAT_CPLD_LPC_REG_ASIC2_MASK_OFFSET 0x55 + #define MLXPLAT_CPLD_LPC_REG_AGGRLC_OFFSET 0x56 + #define MLXPLAT_CPLD_LPC_REG_AGGRLC_MASK_OFFSET 0x57 + #define MLXPLAT_CPLD_LPC_REG_PSU_OFFSET 0x58 +@@ -193,6 +197,7 @@ + MLXPLAT_CPLD_AGGR_MASK_LC_ACT | \ + MLXPLAT_CPLD_AGGR_MASK_LC_SDWN) + #define MLXPLAT_CPLD_LOW_AGGR_MASK_LOW 0xc1 ++#define MLXPLAT_CPLD_LOW_AGGR_MASK_ASIC2 BIT(2) + #define MLXPLAT_CPLD_LOW_AGGR_MASK_I2C BIT(6) + #define MLXPLAT_CPLD_PSU_MASK GENMASK(1, 0) + #define MLXPLAT_CPLD_PWR_MASK GENMASK(1, 0) +@@ -589,6 +594,15 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_asic_items_data[] = { + }, + }; + ++static struct mlxreg_core_data mlxplat_mlxcpld_default_asic2_items_data[] = { ++ { ++ .label = "asic2", ++ .reg = MLXPLAT_CPLD_LPC_REG_ASIC2_HEALTH_OFFSET, ++ .mask = MLXPLAT_CPLD_ASIC_MASK, ++ .hpdev.nr = MLXPLAT_CPLD_NR_NONE, ++ }, ++}; ++ + static struct mlxreg_core_item mlxplat_mlxcpld_default_items[] = { + { + .data = mlxplat_mlxcpld_default_psu_items_data, +@@ -1252,6 +1266,15 @@ static struct mlxreg_core_item mlxplat_mlxcpld_ext_items[] = { + .inversed = 0, + .health = true, + }, ++ { ++ .data = mlxplat_mlxcpld_default_asic2_items_data, ++ .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, ++ .reg = MLXPLAT_CPLD_LPC_REG_ASIC2_HEALTH_OFFSET, ++ .mask = MLXPLAT_CPLD_ASIC_MASK, ++ .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic2_items_data), ++ .inversed = 0, ++ .health = true, ++ } + }; + + static +@@ -1261,7 +1284,7 @@ struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_ext_data = { + .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, + .mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF | MLXPLAT_CPLD_AGGR_MASK_COMEX, + .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, +- .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW, ++ .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW | MLXPLAT_CPLD_LOW_AGGR_MASK_ASIC2, + }; + + static struct mlxreg_core_data mlxplat_mlxcpld_modular_pwr_items_data[] = { +@@ -3075,6 +3098,18 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = { + .bit = GENMASK(7, 0), + .mode = 0444, + }, ++ { ++ .label = "asic_reset", ++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP2_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(3), ++ .mode = 0644, ++ }, ++ { ++ .label = "asic2_reset", ++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP2_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(2), ++ .mode = 0444, ++ }, + { + .label = "reset_long_pb", + .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, +@@ -3214,6 +3249,13 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = { + .bit = 1, + .mode = 0444, + }, ++ { ++ .label = "asic2_health", ++ .reg = MLXPLAT_CPLD_LPC_REG_ASIC2_HEALTH_OFFSET, ++ .mask = MLXPLAT_CPLD_ASIC_MASK, ++ .bit = 1, ++ .mode = 0444, ++ }, + { + .label = "fan_dir", + .reg = MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION, +@@ -4254,6 +4296,8 @@ static bool mlxplat_mlxcpld_writeable_reg(struct device *dev, unsigned int reg) + case MLXPLAT_CPLD_LPC_REG_AGGRCX_MASK_OFFSET: + case MLXPLAT_CPLD_LPC_REG_ASIC_EVENT_OFFSET: + case MLXPLAT_CPLD_LPC_REG_ASIC_MASK_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_ASIC2_EVENT_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_ASIC2_MASK_OFFSET: + case MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET: + case MLXPLAT_CPLD_LPC_REG_PSU_MASK_OFFSET: + case MLXPLAT_CPLD_LPC_REG_PWR_EVENT_OFFSET: +@@ -4346,6 +4390,9 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg) + case MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET: + case MLXPLAT_CPLD_LPC_REG_ASIC_EVENT_OFFSET: + case MLXPLAT_CPLD_LPC_REG_ASIC_MASK_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_ASIC2_HEALTH_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_ASIC2_EVENT_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_ASIC2_MASK_OFFSET: + case MLXPLAT_CPLD_LPC_REG_PSU_OFFSET: + case MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET: + case MLXPLAT_CPLD_LPC_REG_PSU_MASK_OFFSET: +@@ -4473,6 +4520,9 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg) + case MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET: + case MLXPLAT_CPLD_LPC_REG_ASIC_EVENT_OFFSET: + case MLXPLAT_CPLD_LPC_REG_ASIC_MASK_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_ASIC2_HEALTH_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_ASIC2_EVENT_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_ASIC2_MASK_OFFSET: + case MLXPLAT_CPLD_LPC_REG_PSU_OFFSET: + case MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET: + case MLXPLAT_CPLD_LPC_REG_PSU_MASK_OFFSET: +-- +2.20.1 + diff --git a/patch/0160-platform-mellanox-Introduce-support-for-COMe-NVSwitc.patch b/patch/0160-platform-mellanox-Introduce-support-for-COMe-NVSwitc.patch new file mode 100644 index 000000000000..d6de42d39cf7 --- /dev/null +++ b/patch/0160-platform-mellanox-Introduce-support-for-COMe-NVSwitc.patch @@ -0,0 +1,357 @@ +From 333d4bcd32e3501d9bf3991dd5f2ff82061dab6b Mon Sep 17 00:00:00 2001 +From: Vadim Pasternak +Date: Wed, 26 Jan 2022 20:34:32 +0200 +Subject: [PATCH backport 5.10 01/17] platform: mellanox: Introduce support for + COMe management module for chassis + +The system is built for artificial intelligence and accelerated +analytics applications. Chassis is offered to cloud service +providers and OEMs. + +Driver is extended to support new COMe NVSwitch management module. + +Signed-off-by: Vadim Pasternak +Reviewed-by: Oleksandr Shamray +--- + drivers/platform/x86/mlx-platform.c | 269 ++++++++++++++++++++++++++++ + 1 file changed, 269 insertions(+) + +diff --git a/drivers/platform/x86/mlx-platform.c b/drivers/platform/x86/mlx-platform.c +index cbe9eab34..e06fd1725 100644 +--- a/drivers/platform/x86/mlx-platform.c ++++ b/drivers/platform/x86/mlx-platform.c +@@ -67,6 +67,9 @@ + #define MLXPLAT_CPLD_LPC_REG_AGGRCO_MASK_OFFSET 0x43 + #define MLXPLAT_CPLD_LPC_REG_AGGRCX_OFFSET 0x44 + #define MLXPLAT_CPLD_LPC_REG_AGGRCX_MASK_OFFSET 0x45 ++#define MLXPLAT_CPLD_LPC_REG_GWP_OFFSET 0x4a ++#define MLXPLAT_CPLD_LPC_REG_GWP_EVENT_OFFSET 0x4b ++#define MLXPLAT_CPLD_LPC_REG_GWP_MASK_OFFSET 0x4c + #define MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET 0x50 + #define MLXPLAT_CPLD_LPC_REG_ASIC_EVENT_OFFSET 0x51 + #define MLXPLAT_CPLD_LPC_REG_ASIC_MASK_OFFSET 0x52 +@@ -210,6 +213,7 @@ + #define MLXPLAT_CPLD_LED_LO_NIBBLE_MASK GENMASK(7, 4) + #define MLXPLAT_CPLD_LED_HI_NIBBLE_MASK GENMASK(3, 0) + #define MLXPLAT_CPLD_VOLTREG_UPD_MASK GENMASK(5, 4) ++#define MLXPLAT_CPLD_GWP_MASK GENMASK(0, 0) + #define MLXPLAT_CPLD_I2C_CAP_BIT 0x04 + #define MLXPLAT_CPLD_I2C_CAP_MASK GENMASK(5, MLXPLAT_CPLD_I2C_CAP_BIT) + +@@ -2128,6 +2132,38 @@ struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_modular_data = { + .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW, + }; + ++/* Platform hotplug for chassis blade systems family data */ ++static struct mlxreg_core_data mlxplat_mlxcpld_global_wp_items_data[] = { ++ { ++ .label = "global_wp_grant", ++ .reg = MLXPLAT_CPLD_LPC_REG_GWP_OFFSET, ++ .mask = MLXPLAT_CPLD_GWP_MASK, ++ .hpdev.nr = MLXPLAT_CPLD_NR_NONE, ++ }, ++}; ++ ++static struct mlxreg_core_item mlxplat_mlxcpld_chassis_blade_items[] = { ++ { ++ .data = mlxplat_mlxcpld_global_wp_items_data, ++ .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, ++ .reg = MLXPLAT_CPLD_LPC_REG_GWP_OFFSET, ++ .mask = MLXPLAT_CPLD_GWP_MASK, ++ .count = ARRAY_SIZE(mlxplat_mlxcpld_global_wp_items_data), ++ .inversed = 0, ++ .health = false, ++ }, ++}; ++ ++static ++struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_chassis_blade_data = { ++ .items = mlxplat_mlxcpld_chassis_blade_items, ++ .counter = ARRAY_SIZE(mlxplat_mlxcpld_chassis_blade_items), ++ .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, ++ .mask = MLXPLAT_CPLD_AGGR_MASK_COMEX, ++ .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, ++ .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW, ++}; ++ + /* Platform led default data */ + static struct mlxreg_core_data mlxplat_mlxcpld_default_led_data[] = { + { +@@ -3808,6 +3844,203 @@ static struct mlxreg_core_platform_data mlxplat_modular_regs_io_data = { + .counter = ARRAY_SIZE(mlxplat_mlxcpld_modular_regs_io_data), + }; + ++/* Platform register access for chassis blade systems family data */ ++static struct mlxreg_core_data mlxplat_mlxcpld_chassis_blade_regs_io_data[] = { ++ { ++ .label = "cpld1_version", ++ .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, ++ }, ++ { ++ .label = "cpld1_pn", ++ .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET, ++ .bit = GENMASK(15, 0), ++ .mode = 0444, ++ .regnum = 2, ++ }, ++ { ++ .label = "cpld1_version_min", ++ .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_aux_pwr_or_ref", ++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(2), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_from_comex", ++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(4), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_comex_pwr_fail", ++ .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(3), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_platform", ++ .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(4), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_soc", ++ .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(5), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_comex_wd", ++ .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(6), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_voltmon_upgrade_fail", ++ .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(0), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_system", ++ .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(1), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_sw_pwr_off", ++ .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(2), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_comex_thermal", ++ .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(3), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_reload_bios", ++ .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(5), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_ac_pwr_fail", ++ .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(6), ++ .mode = 0444, ++ }, ++ { ++ .label = "pwr_cycle", ++ .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(2), ++ .mode = 0200, ++ }, ++ { ++ .label = "pwr_down", ++ .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(3), ++ .mode = 0200, ++ }, ++ { ++ .label = "global_wp_request", ++ .reg = MLXPLAT_CPLD_LPC_REG_GP2_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(0), ++ .mode = 0644, ++ }, ++ { ++ .label = "jtag_enable", ++ .reg = MLXPLAT_CPLD_LPC_REG_GP2_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(4), ++ .mode = 0644, ++ }, ++ { ++ .label = "comm_chnl_ready", ++ .reg = MLXPLAT_CPLD_LPC_REG_GP2_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(6), ++ .mode = 0200, ++ }, ++ { ++ .label = "bios_safe_mode", ++ .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(4), ++ .mode = 0444, ++ }, ++ { ++ .label = "bios_active_image", ++ .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(5), ++ .mode = 0444, ++ }, ++ { ++ .label = "bios_auth_fail", ++ .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(6), ++ .mode = 0444, ++ }, ++ { ++ .label = "bios_upgrade_fail", ++ .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(7), ++ .mode = 0444, ++ }, ++ { ++ .label = "voltreg_update_status", ++ .reg = MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET, ++ .mask = MLXPLAT_CPLD_VOLTREG_UPD_MASK, ++ .bit = 5, ++ .mode = 0444, ++ }, ++ { ++ .label = "vpd_wp", ++ .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(3), ++ .mode = 0644, ++ }, ++ { ++ .label = "pcie_asic_reset_dis", ++ .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(4), ++ .mode = 0644, ++ }, ++ { ++ .label = "global_wp_response", ++ .reg = MLXPLAT_CPLD_LPC_REG_GWP_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(0), ++ .mode = 0444, ++ }, ++ { ++ .label = "config1", ++ .reg = MLXPLAT_CPLD_LPC_REG_CONFIG1_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, ++ }, ++ { ++ .label = "config2", ++ .reg = MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, ++ }, ++ { ++ .label = "ufm_version", ++ .reg = MLXPLAT_CPLD_LPC_REG_UFM_VERSION_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, ++ }, ++}; ++ ++static struct mlxreg_core_platform_data mlxplat_chassis_blade_regs_io_data = { ++ .data = mlxplat_mlxcpld_chassis_blade_regs_io_data, ++ .counter = ARRAY_SIZE(mlxplat_mlxcpld_chassis_blade_regs_io_data), ++}; ++ + /* Platform FAN default */ + static struct mlxreg_core_data mlxplat_mlxcpld_default_fan_data[] = { + { +@@ -4294,6 +4527,8 @@ static bool mlxplat_mlxcpld_writeable_reg(struct device *dev, unsigned int reg) + case MLXPLAT_CPLD_LPC_REG_AGGRLO_MASK_OFFSET: + case MLXPLAT_CPLD_LPC_REG_AGGRCO_MASK_OFFSET: + case MLXPLAT_CPLD_LPC_REG_AGGRCX_MASK_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_GWP_EVENT_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_GWP_MASK_OFFSET: + case MLXPLAT_CPLD_LPC_REG_ASIC_EVENT_OFFSET: + case MLXPLAT_CPLD_LPC_REG_ASIC_MASK_OFFSET: + case MLXPLAT_CPLD_LPC_REG_ASIC2_EVENT_OFFSET: +@@ -4387,6 +4622,9 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg) + case MLXPLAT_CPLD_LPC_REG_AGGRCO_MASK_OFFSET: + case MLXPLAT_CPLD_LPC_REG_AGGRCX_OFFSET: + case MLXPLAT_CPLD_LPC_REG_AGGRCX_MASK_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_GWP_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_GWP_EVENT_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_GWP_MASK_OFFSET: + case MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET: + case MLXPLAT_CPLD_LPC_REG_ASIC_EVENT_OFFSET: + case MLXPLAT_CPLD_LPC_REG_ASIC_MASK_OFFSET: +@@ -4517,6 +4755,9 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg) + case MLXPLAT_CPLD_LPC_REG_AGGRCO_MASK_OFFSET: + case MLXPLAT_CPLD_LPC_REG_AGGRCX_OFFSET: + case MLXPLAT_CPLD_LPC_REG_AGGRCX_MASK_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_GWP_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_GWP_EVENT_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_GWP_MASK_OFFSET: + case MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET: + case MLXPLAT_CPLD_LPC_REG_ASIC_EVENT_OFFSET: + case MLXPLAT_CPLD_LPC_REG_ASIC_MASK_OFFSET: +@@ -4949,6 +5190,28 @@ static int __init mlxplat_dmi_modular_matched(const struct dmi_system_id *dmi) + return 1; + } + ++static int __init mlxplat_dmi_chassis_blade_matched(const struct dmi_system_id *dmi) ++{ ++ int i; ++ ++ mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; ++ mlxplat_mux_num = ARRAY_SIZE(mlxplat_default_mux_data); ++ mlxplat_mux_data = mlxplat_default_mux_data; ++ mlxplat_hotplug = &mlxplat_mlxcpld_chassis_blade_data; ++ mlxplat_hotplug->deferred_nr = ++ mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; ++ for (i = 0; i < mlxplat_mux_num; i++) { ++ mlxplat_mux_data[i].values = mlxplat_msn21xx_channels; ++ mlxplat_mux_data[i].n_values = ++ ARRAY_SIZE(mlxplat_msn21xx_channels); ++ } ++ mlxplat_regs_io = &mlxplat_chassis_blade_regs_io_data; ++ mlxplat_i2c = &mlxplat_mlxcpld_i2c_ng_data; ++ mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_ng400; ++ ++ return 1; ++} ++ + static int __init mlxplat_dmi_modular_matched(const struct dmi_system_id *dmi) + { + int i; +@@ -5044,6 +5307,12 @@ static const struct dmi_system_id mlxplat_dmi_table[] __initconst = { + DMI_MATCH(DMI_BOARD_NAME, "VMOD0011"), + }, + }, ++ { ++ .callback = mlxplat_dmi_chassis_blade_matched, ++ .matches = { ++ DMI_MATCH(DMI_BOARD_NAME, "VMOD0015"), ++ }, ++ }, + { + .callback = mlxplat_dmi_msn274x_matched, + .matches = { +-- +2.20.1 + diff --git a/patch/0161-platform-x86-mlx-platform-Add-support-for-new-system.patch b/patch/0161-platform-x86-mlx-platform-Add-support-for-new-system.patch new file mode 100644 index 000000000000..602f752b7383 --- /dev/null +++ b/patch/0161-platform-x86-mlx-platform-Add-support-for-new-system.patch @@ -0,0 +1,97 @@ +From 993337e78b0f9b88dba2a37eba37ae69828632e1 Mon Sep 17 00:00:00 2001 +From: Felix Radensky +Date: Sun, 24 Oct 2021 16:26:40 +0000 +Subject: [PATCH backport 5.10 02/17] platform/x86: mlx-platform: Add support + for new system XH3000 + +Add support for new system type XH3000, which is a water cooling +Ethernet switch blade equipped with 32x200G Ethernet ports. + +The system is recognized by "DMI_BOARD_NAME" and "DMI_PRODUCT_SKU" matches, +when these fields are set to "VMOD0005" and "HI139" respectively. + +Signed-off-by: Felix Radensky +Reviewed-by: Vadim Pasternak +--- + drivers/platform/x86/mlx-platform.c | 51 +++++++++++++++++++++++++++++ + 1 file changed, 51 insertions(+) + +diff --git a/drivers/platform/x86/mlx-platform.c b/drivers/platform/x86/mlx-platform.c +index e06fd1725..2b1441a87 100644 +--- a/drivers/platform/x86/mlx-platform.c ++++ b/drivers/platform/x86/mlx-platform.c +@@ -2262,6 +2262,25 @@ static struct mlxreg_core_platform_data mlxplat_default_led_wc_data = { + .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_led_wc_data), + }; + ++/* Platform led default data for water cooling Ethernet switch blade */ ++static struct mlxreg_core_data mlxplat_mlxcpld_default_led_eth_wc_blade_data[] = { ++ { ++ .label = "status:green", ++ .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, ++ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, ++ }, ++ { ++ .label = "status:red", ++ .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, ++ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK ++ }, ++}; ++ ++static struct mlxreg_core_platform_data mlxplat_default_led_eth_wc_blade_data = { ++ .data = mlxplat_mlxcpld_default_led_eth_wc_blade_data, ++ .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_led_eth_wc_blade_data), ++}; ++ + /* Platform led MSN21xx system family data */ + static struct mlxreg_core_data mlxplat_mlxcpld_msn21xx_led_data[] = { + { +@@ -5028,6 +5047,31 @@ static int __init mlxplat_dmi_default_wc_matched(const struct dmi_system_id *dmi + return 1; + } + ++static int __init mlxplat_dmi_default_eth_wc_blade_matched(const struct dmi_system_id *dmi) ++{ ++ int i; ++ ++ mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; ++ mlxplat_mux_num = ARRAY_SIZE(mlxplat_default_mux_data); ++ mlxplat_mux_data = mlxplat_default_mux_data; ++ for (i = 0; i < mlxplat_mux_num; i++) { ++ mlxplat_mux_data[i].values = mlxplat_msn21xx_channels; ++ mlxplat_mux_data[i].n_values = ++ ARRAY_SIZE(mlxplat_msn21xx_channels); ++ } ++ mlxplat_hotplug = &mlxplat_mlxcpld_default_wc_data; ++ mlxplat_hotplug->deferred_nr = ++ mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; ++ mlxplat_led = &mlxplat_default_led_eth_wc_blade_data; ++ mlxplat_regs_io = &mlxplat_default_ng_regs_io_data; ++ for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type2); i++) ++ mlxplat_wd_data[i] = &mlxplat_mlxcpld_wd_set_type2[i]; ++ mlxplat_i2c = &mlxplat_mlxcpld_i2c_ng_data; ++ mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_ng; ++ ++ return 1; ++} ++ + static int __init mlxplat_dmi_msn21xx_matched(const struct dmi_system_id *dmi) + { + int i; +@@ -5277,6 +5321,13 @@ static const struct dmi_system_id mlxplat_dmi_table[] __initconst = { + DMI_MATCH(DMI_PRODUCT_NAME, "MQM87"), + }, + }, ++ { ++ .callback = mlxplat_dmi_default_eth_wc_blade_matched, ++ .matches = { ++ DMI_MATCH(DMI_BOARD_NAME, "VMOD0005"), ++ DMI_EXACT_MATCH(DMI_PRODUCT_SKU, "HI139"), ++ }, ++ }, + { + .callback = mlxplat_dmi_qmb7xx_matched, + .matches = { +-- +2.20.1 + diff --git a/patch/0163-platform-mellanox-Add-COME-board-revision-register.patch b/patch/0162-platform-mellanox-Add-COME-board-revision-register.patch similarity index 68% rename from patch/0163-platform-mellanox-Add-COME-board-revision-register.patch rename to patch/0162-platform-mellanox-Add-COME-board-revision-register.patch index ddde3148015c..1efadbe9939c 100644 --- a/patch/0163-platform-mellanox-Add-COME-board-revision-register.patch +++ b/patch/0162-platform-mellanox-Add-COME-board-revision-register.patch @@ -1,8 +1,8 @@ -From 9efa1e465f570a270a7561588a2e0dedee4ee13e Mon Sep 17 00:00:00 2001 +From 01cec35c2103e425d9f66f35f9cb91db7e9d9267 Mon Sep 17 00:00:00 2001 From: Vadim Pasternak Date: Wed, 6 Jul 2022 17:26:41 +0300 -Subject: [PATCH platform backport v5.10 1/6] platform: mellanox: Add COME - board revision register +Subject: [PATCH backport 5.10 03/17] platform: mellanox: Add COME board + revision register Add to CPLD COME board configuration register for getting a board revision. The value of this register is pushed by hardware through @@ -10,16 +10,15 @@ GPIO pins. The purpose of it is to expose some minor BOM changes. Signed-off-by: Vadim Pasternak - --- - drivers/platform/x86/mlx-platform.c | 15 +++++++++++++++ - 1 file changed, 15 insertions(+) + drivers/platform/x86/mlx-platform.c | 21 +++++++++++++++++++++ + 1 file changed, 21 insertions(+) diff --git a/drivers/platform/x86/mlx-platform.c b/drivers/platform/x86/mlx-platform.c -index 447044f..d7eea0d 100644 +index 2b1441a87..1d0c13c65 100644 --- a/drivers/platform/x86/mlx-platform.c +++ b/drivers/platform/x86/mlx-platform.c -@@ -143,6 +143,7 @@ +@@ -150,6 +150,7 @@ #define MLXPLAT_CPLD_LPC_REG_SLOT_QTY_OFFSET 0xfa #define MLXPLAT_CPLD_LPC_REG_CONFIG1_OFFSET 0xfb #define MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET 0xfc @@ -27,33 +26,46 @@ index 447044f..d7eea0d 100644 #define MLXPLAT_CPLD_LPC_IO_RANGE 0x100 #define MLXPLAT_CPLD_LPC_I2C_CH1_OFF 0xdb #define MLXPLAT_CPLD_LPC_I2C_CH2_OFF 0xda -@@ -3057,6 +3058,12 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = { +@@ -3372,6 +3373,12 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = { + .bit = GENMASK(7, 0), .mode = 0444, }, - { ++ { + .label = "config3", + .reg = MLXPLAT_CPLD_LPC_REG_CONFIG3_OFFSET, + .bit = GENMASK(7, 0), + .mode = 0444, + }, -+ { + { .label = "ufm_version", .reg = MLXPLAT_CPLD_LPC_REG_UFM_VERSION_OFFSET, +@@ -3850,6 +3857,12 @@ static struct mlxreg_core_data mlxplat_mlxcpld_modular_regs_io_data[] = { .bit = GENMASK(7, 0), -@@ -3535,6 +3542,12 @@ static struct mlxreg_core_data mlxplat_mlxcpld_modular_regs_io_data[] = { .mode = 0444, }, - { ++ { + .label = "config3", + .reg = MLXPLAT_CPLD_LPC_REG_CONFIG3_OFFSET, + .bit = GENMASK(7, 0), + .mode = 0444, + }, -+ { + { .label = "ufm_version", .reg = MLXPLAT_CPLD_LPC_REG_UFM_VERSION_OFFSET, +@@ -4047,6 +4060,12 @@ static struct mlxreg_core_data mlxplat_mlxcpld_chassis_blade_regs_io_data[] = { .bit = GENMASK(7, 0), -@@ -4100,6 +4113,7 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg) + .mode = 0444, + }, ++ { ++ .label = "config3", ++ .reg = MLXPLAT_CPLD_LPC_REG_CONFIG3_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, ++ }, + { + .label = "ufm_version", + .reg = MLXPLAT_CPLD_LPC_REG_UFM_VERSION_OFFSET, +@@ -4724,6 +4743,7 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg) case MLXPLAT_CPLD_LPC_REG_SLOT_QTY_OFFSET: case MLXPLAT_CPLD_LPC_REG_CONFIG1_OFFSET: case MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET: @@ -61,7 +73,7 @@ index 447044f..d7eea0d 100644 case MLXPLAT_CPLD_LPC_REG_UFM_VERSION_OFFSET: return true; } -@@ -4221,6 +4235,7 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg) +@@ -4851,6 +4871,7 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg) case MLXPLAT_CPLD_LPC_REG_SLOT_QTY_OFFSET: case MLXPLAT_CPLD_LPC_REG_CONFIG1_OFFSET: case MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET: @@ -70,5 +82,5 @@ index 447044f..d7eea0d 100644 return true; } -- -1.9.1 +2.20.1 diff --git a/patch/0164-hwmon-jc42-Add-support-for-Seiko-Instruments-S-34TS0.patch b/patch/0164-hwmon-jc42-Add-support-for-Seiko-Instruments-S-34TS0.patch new file mode 100644 index 000000000000..946a19675176 --- /dev/null +++ b/patch/0164-hwmon-jc42-Add-support-for-Seiko-Instruments-S-34TS0.patch @@ -0,0 +1,47 @@ +From d8f82a399f46cfc1b91c2dd64dd18741ce9d7e5a Mon Sep 17 00:00:00 2001 +From: Oleksandr Shamray +Date: Tue, 22 Feb 2022 18:55:15 +0200 +Subject: [PATCH] hwmon: (jc42) Add support for Seiko Instruments S-34TS04A + +S-34TS04A is a JC42.4 compatible temperature sensor from Seiko Instruments. + +Signed-off-by: Oleksandr Shamray +Reviewed-by: Vadim Pasternak +--- + drivers/hwmon/jc42.c | 6 ++++++ + 1 file changed, 6 insertions(+) + +diff --git a/drivers/hwmon/jc42.c b/drivers/hwmon/jc42.c +index 4a03d010e..bda2c9fb1 100644 +--- a/drivers/hwmon/jc42.c ++++ b/drivers/hwmon/jc42.c +@@ -63,6 +63,7 @@ static const unsigned short normal_i2c[] = { + #define STM_MANID 0x104a /* ST Microelectronics */ + #define GT_MANID 0x1c68 /* Giantec */ + #define GT_MANID2 0x132d /* Giantec, 2nd mfg ID */ ++#define SI_MANID 0x1c85 /* Seiko Instruments */ + + /* SMBUS register */ + #define SMBUS_STMOUT BIT(7) /* SMBus time-out, active low */ +@@ -153,6 +154,10 @@ static const unsigned short normal_i2c[] = { + #define STTS3000_DEVID 0x0200 + #define STTS3000_DEVID_MASK 0xffff + ++/* Seiko Instruments */ ++#define S34TS04A_DEVID 0x2221 ++#define S34TS04A_DEVID_MASK 0xffff ++ + static u16 jc42_hysteresis[] = { 0, 1500, 3000, 6000 }; + + struct jc42_chips { +@@ -182,6 +187,7 @@ static struct jc42_chips jc42_chips[] = { + { ONS_MANID, CAT34TS02C_DEVID, CAT34TS02C_DEVID_MASK }, + { ONS_MANID, CAT34TS04_DEVID, CAT34TS04_DEVID_MASK }, + { NXP_MANID, SE98_DEVID, SE98_DEVID_MASK }, ++ { SI_MANID, S34TS04A_DEVID, S34TS04A_DEVID_MASK }, + { STM_MANID, STTS424_DEVID, STTS424_DEVID_MASK }, + { STM_MANID, STTS424E_DEVID, STTS424E_DEVID_MASK }, + { STM_MANID, STTS2002_DEVID, STTS2002_DEVID_MASK }, +-- +2.14.1 + diff --git a/patch/0165-platform-mellanox-mlxreg-io-Add-locking-for-io-opera.patch b/patch/0165-platform-mellanox-mlxreg-io-Add-locking-for-io-opera.patch new file mode 100644 index 000000000000..76ec54b577aa --- /dev/null +++ b/patch/0165-platform-mellanox-mlxreg-io-Add-locking-for-io-opera.patch @@ -0,0 +1,106 @@ +From 77e8886b6019a37335c66dceb39429c33eb87f28 Mon Sep 17 00:00:00 2001 +From: Vadim Pasternak +Date: Mon, 7 Feb 2022 21:22:04 +0200 +Subject: [PATCH platform-next 02/10] platform/mellanox: mlxreg-io: Add locking + for io operations + +Add lock to protect user read/write access to the registers. + +Signed-off-by: Vadim Pasternak +--- + drivers/platform/mellanox/mlxreg-io.c | 23 +++++++++++++++++++++++ + 1 file changed, 23 insertions(+) + +diff --git a/drivers/platform/mellanox/mlxreg-io.c b/drivers/platform/mellanox/mlxreg-io.c +index 2c2686d5c..ddc08abf3 100644 +--- a/drivers/platform/mellanox/mlxreg-io.c ++++ b/drivers/platform/mellanox/mlxreg-io.c +@@ -31,6 +31,7 @@ + * @group: sysfs attribute group; + * @groups: list of sysfs attribute group for hwmon registration; + * @regsize: size of a register value; ++ * @io_lock: user access locking; + */ + struct mlxreg_io_priv_data { + struct platform_device *pdev; +@@ -41,6 +42,7 @@ struct mlxreg_io_priv_data { + struct attribute_group group; + const struct attribute_group *groups[2]; + int regsize; ++ struct mutex io_lock; /* Protects user access. */ + }; + + static int +@@ -116,14 +118,19 @@ mlxreg_io_attr_show(struct device *dev, struct device_attribute *attr, + u32 regval = 0; + int ret; + ++ mutex_lock(&priv->io_lock); ++ + ret = mlxreg_io_get_reg(priv->pdata->regmap, data, 0, true, + priv->regsize, ®val); + if (ret) + goto access_error; + ++ mutex_unlock(&priv->io_lock); ++ + return sprintf(buf, "%u\n", regval); + + access_error: ++ mutex_unlock(&priv->io_lock); + return ret; + } + +@@ -145,6 +152,8 @@ mlxreg_io_attr_store(struct device *dev, struct device_attribute *attr, + if (ret) + return ret; + ++ mutex_lock(&priv->io_lock); ++ + ret = mlxreg_io_get_reg(priv->pdata->regmap, data, input_val, false, + priv->regsize, ®val); + if (ret) +@@ -154,9 +163,12 @@ mlxreg_io_attr_store(struct device *dev, struct device_attribute *attr, + if (ret) + goto access_error; + ++ mutex_unlock(&priv->io_lock); ++ + return len; + + access_error: ++ mutex_unlock(&priv->io_lock); + dev_err(&priv->pdev->dev, "Bus access error\n"); + return ret; + } +@@ -246,16 +258,27 @@ static int mlxreg_io_probe(struct platform_device *pdev) + return PTR_ERR(priv->hwmon); + } + ++ mutex_init(&priv->io_lock); + dev_set_drvdata(&pdev->dev, priv); + + return 0; + } + ++static int mlxreg_io_remove(struct platform_device *pdev) ++{ ++ struct mlxreg_io_priv_data *priv = dev_get_drvdata(&pdev->dev); ++ ++ mutex_destroy(&priv->io_lock); ++ ++ return 0; ++} ++ + static struct platform_driver mlxreg_io_driver = { + .driver = { + .name = "mlxreg-io", + }, + .probe = mlxreg_io_probe, ++ .remove = mlxreg_io_remove, + }; + + module_platform_driver(mlxreg_io_driver); +-- +2.20.1 + diff --git a/patch/0170-i2c-mlxcpld-Fix-register-setting-for-400KHz-frequenc.patch b/patch/0170-i2c-mlxcpld-Fix-register-setting-for-400KHz-frequenc.patch new file mode 100644 index 000000000000..3df1c94850cd --- /dev/null +++ b/patch/0170-i2c-mlxcpld-Fix-register-setting-for-400KHz-frequenc.patch @@ -0,0 +1,30 @@ +From 553016c0c35314b0cd9fc3ed3c37d04ec0c6c14e Mon Sep 17 00:00:00 2001 +From: Vadim Pasternak +Date: Mon, 13 Jun 2022 20:51:35 +0300 +Subject: [PATCH i2c backport v5.10 1/1] i2c: mlxcpld: Fix register setting for + 400KHz frequency + +Fix setting of 'Half Cycle' register for 400KHz frequency. + +Fixes: fa1049135c15 ("i2c: mlxcpld: Modify register setting for 400KHz frequency") +Signed-off-by: Vadim Pasternak +--- + drivers/i2c/busses/i2c-mlxcpld.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/i2c/busses/i2c-mlxcpld.c b/drivers/i2c/busses/i2c-mlxcpld.c +index fb451d42a..85b78985f 100644 +--- a/drivers/i2c/busses/i2c-mlxcpld.c ++++ b/drivers/i2c/busses/i2c-mlxcpld.c +@@ -49,7 +49,7 @@ + #define MLXCPLD_LPCI2C_NACK_IND 2 + + #define MLXCPLD_I2C_FREQ_1000KHZ_SET 0x04 +-#define MLXCPLD_I2C_FREQ_400KHZ_SET 0x0c ++#define MLXCPLD_I2C_FREQ_400KHZ_SET 0x0e + #define MLXCPLD_I2C_FREQ_100KHZ_SET 0x42 + + enum mlxcpld_i2c_frequency { +-- +2.20.1 + diff --git a/patch/0171-platform-mellanox-mlxreg-lc-Fix-cleanup-on-failure-a.patch b/patch/0171-platform-mellanox-mlxreg-lc-Fix-cleanup-on-failure-a.patch new file mode 100644 index 000000000000..fd84f2801894 --- /dev/null +++ b/patch/0171-platform-mellanox-mlxreg-lc-Fix-cleanup-on-failure-a.patch @@ -0,0 +1,194 @@ +From 68ff1efc9fdb309cd9093c4317634b601984ff6e Mon Sep 17 00:00:00 2001 +From: Vadim Pasternak +Date: Wed, 22 Jun 2022 13:01:15 +0300 +Subject: [PATCH platform 1/1] platform/mellanox: mlxreg-lc: Fix cleanup on + failure and add more verbosity in error flow + +Clean client object in case of probing failure. +Prevent running remove routine in case probing failed. +Add error log for each kind of failures during probing. + +Fixes: 62f9529b8d5c ("platform/mellanox: mlxreg-lc: Add initial support for Nvidia line card devices") +Signed-off-by: Vadim Pasternak +--- + drivers/platform/mellanox/mlxreg-lc.c | 85 ++++++++++++++++++++------- + 1 file changed, 63 insertions(+), 22 deletions(-) + +diff --git a/drivers/platform/mellanox/mlxreg-lc.c b/drivers/platform/mellanox/mlxreg-lc.c +index ea8324020..79d35a281 100644 +--- a/drivers/platform/mellanox/mlxreg-lc.c ++++ b/drivers/platform/mellanox/mlxreg-lc.c +@@ -559,9 +559,6 @@ static int mlxreg_lc_event_handler(void *handle, enum mlxreg_hotplug_kind kind, + dev_info(mlxreg_lc->dev, "linecard#%d state %d event kind %d action %d\n", + mlxreg_lc->data->slot, mlxreg_lc->state, kind, action); + +- if (!(mlxreg_lc->state & MLXREG_LC_INITIALIZED)) +- return 0; +- + switch (kind) { + case MLXREG_HOTPLUG_LC_SYNCED: + /* +@@ -715,8 +712,12 @@ mlxreg_lc_config_init(struct mlxreg_lc *mlxreg_lc, void *regmap, + switch (regval) { + case MLXREG_LC_SN4800_C16: + err = mlxreg_lc_sn4800_c16_config_init(mlxreg_lc, regmap, data); +- if (err) ++ if (err) { ++ dev_err(dev, "Failed to config client %s at bus %d at addr 0x%02x\n", ++ data->hpdev.brdinfo->type, data->hpdev.nr, ++ data->hpdev.brdinfo->addr); + return err; ++ } + break; + default: + return -ENODEV; +@@ -729,8 +730,11 @@ mlxreg_lc_config_init(struct mlxreg_lc *mlxreg_lc, void *regmap, + mlxreg_lc->mux = platform_device_register_resndata(dev, "i2c-mux-mlxcpld", data->hpdev.nr, + NULL, 0, mlxreg_lc->mux_data, + sizeof(*mlxreg_lc->mux_data)); +- if (IS_ERR(mlxreg_lc->mux)) ++ if (IS_ERR(mlxreg_lc->mux)) { ++ dev_err(dev, "Failed to create mux infra for client %s at bus %d at addr 0x%02x\n", ++ data->hpdev.brdinfo->type, data->hpdev.nr, data->hpdev.brdinfo->addr); + return PTR_ERR(mlxreg_lc->mux); ++ } + + /* Register IO access driver. */ + if (mlxreg_lc->io_data) { +@@ -739,6 +743,9 @@ mlxreg_lc_config_init(struct mlxreg_lc *mlxreg_lc, void *regmap, + platform_device_register_resndata(dev, "mlxreg-io", data->hpdev.nr, NULL, 0, + mlxreg_lc->io_data, sizeof(*mlxreg_lc->io_data)); + if (IS_ERR(mlxreg_lc->io_regs)) { ++ dev_err(dev, "Failed to create regio for client %s at bus %d at addr 0x%02x\n", ++ data->hpdev.brdinfo->type, data->hpdev.nr, ++ data->hpdev.brdinfo->addr); + err = PTR_ERR(mlxreg_lc->io_regs); + goto fail_register_io; + } +@@ -752,6 +759,9 @@ mlxreg_lc_config_init(struct mlxreg_lc *mlxreg_lc, void *regmap, + mlxreg_lc->led_data, + sizeof(*mlxreg_lc->led_data)); + if (IS_ERR(mlxreg_lc->led)) { ++ dev_err(dev, "Failed to create LED objects for client %s at bus %d at addr 0x%02x\n", ++ data->hpdev.brdinfo->type, data->hpdev.nr, ++ data->hpdev.brdinfo->addr); + err = PTR_ERR(mlxreg_lc->led); + goto fail_register_led; + } +@@ -808,7 +818,8 @@ static int mlxreg_lc_probe(struct platform_device *pdev) + if (!data->hpdev.adapter) { + dev_err(&pdev->dev, "Failed to get adapter for bus %d\n", + data->hpdev.nr); +- return -EFAULT; ++ err = -EFAULT; ++ goto i2c_get_adapter_fail; + } + + /* Create device at the top of line card I2C tree.*/ +@@ -817,32 +828,40 @@ static int mlxreg_lc_probe(struct platform_device *pdev) + if (IS_ERR(data->hpdev.client)) { + dev_err(&pdev->dev, "Failed to create client %s at bus %d at addr 0x%02x\n", + data->hpdev.brdinfo->type, data->hpdev.nr, data->hpdev.brdinfo->addr); +- +- i2c_put_adapter(data->hpdev.adapter); +- data->hpdev.adapter = NULL; +- return PTR_ERR(data->hpdev.client); ++ err = PTR_ERR(data->hpdev.client); ++ goto i2c_new_device_fail; + } + + regmap = devm_regmap_init_i2c(data->hpdev.client, + &mlxreg_lc_regmap_conf); + if (IS_ERR(regmap)) { ++ dev_err(&pdev->dev, "Failed to create regmap for client %s at bus %d at addr 0x%02x\n", ++ data->hpdev.brdinfo->type, data->hpdev.nr, data->hpdev.brdinfo->addr); + err = PTR_ERR(regmap); +- goto mlxreg_lc_probe_fail; ++ goto devm_regmap_init_i2c_fail; + } + + /* Set default registers. */ + for (i = 0; i < mlxreg_lc_regmap_conf.num_reg_defaults; i++) { + err = regmap_write(regmap, mlxreg_lc_regmap_default[i].reg, + mlxreg_lc_regmap_default[i].def); +- if (err) +- goto mlxreg_lc_probe_fail; ++ if (err) { ++ dev_err(&pdev->dev, "Failed to set default regmap %d for client %s at bus %d at addr 0x%02x\n", ++ i, data->hpdev.brdinfo->type, data->hpdev.nr, ++ data->hpdev.brdinfo->addr); ++ goto regmap_write_fail; ++ } + } + + /* Sync registers with hardware. */ + regcache_mark_dirty(regmap); + err = regcache_sync(regmap); +- if (err) +- goto mlxreg_lc_probe_fail; ++ if (err) { ++ dev_err(&pdev->dev, "Failed to sync regmap for client %s at bus %d at addr 0x%02x\n", ++ data->hpdev.brdinfo->type, data->hpdev.nr, data->hpdev.brdinfo->addr); ++ err = PTR_ERR(regmap); ++ goto regcache_sync_fail; ++ } + + par_pdata = data->hpdev.brdinfo->platform_data; + mlxreg_lc->par_regmap = par_pdata->regmap; +@@ -853,12 +872,27 @@ static int mlxreg_lc_probe(struct platform_device *pdev) + /* Configure line card. */ + err = mlxreg_lc_config_init(mlxreg_lc, regmap, data); + if (err) +- goto mlxreg_lc_probe_fail; ++ goto mlxreg_lc_config_init_fail; + + return err; + +-mlxreg_lc_probe_fail: ++mlxreg_lc_config_init_fail: ++regcache_sync_fail: ++regmap_write_fail: ++devm_regmap_init_i2c_fail: ++ if (data->hpdev.client) { ++ i2c_unregister_device(data->hpdev.client); ++ data->hpdev.client = NULL; ++ } ++i2c_new_device_fail: + i2c_put_adapter(data->hpdev.adapter); ++ data->hpdev.adapter = NULL; ++i2c_get_adapter_fail: ++ /* Clear event notification callback and handle. */ ++ if (data->notifier) { ++ data->notifier->user_handler = NULL; ++ data->notifier->handle = NULL; ++ } + return err; + } + +@@ -867,11 +901,18 @@ static int mlxreg_lc_remove(struct platform_device *pdev) + struct mlxreg_core_data *data = dev_get_platdata(&pdev->dev); + struct mlxreg_lc *mlxreg_lc = platform_get_drvdata(pdev); + +- /* Clear event notification callback. */ +- if (data->notifier) { +- data->notifier->user_handler = NULL; +- data->notifier->handle = NULL; +- } ++ /* ++ * Probing and removing are invoked by hotplug events raised on line card insertion and ++ * removing. If probing procedure fails all data is cleared. However, hotplug event still ++ * will be raised on line card removing and activate removing procedure. In this case there ++ * is nothing to remove. ++ */ ++ if (!data->notifier || !data->notifier->handle) ++ return 0; ++ ++ /* Clear event notification callback and handle. */ ++ data->notifier->user_handler = NULL; ++ data->notifier->handle = NULL; + + /* Destroy static I2C device feeding by main power. */ + mlxreg_lc_destroy_static_devices(mlxreg_lc, mlxreg_lc->main_devs, +-- +2.20.1 + diff --git a/patch/0173-core-Add-support-for-OSFP-transceiver-modules.patch b/patch/0173-core-Add-support-for-OSFP-transceiver-modules.patch new file mode 100644 index 000000000000..75963661e262 --- /dev/null +++ b/patch/0173-core-Add-support-for-OSFP-transceiver-modules.patch @@ -0,0 +1,59 @@ +From 2d0cae902b722594b17335e7aceb6500d9bb4525 Mon Sep 17 00:00:00 2001 +From: Danielle Ratson +Date: Tue, 22 Feb 2022 19:17:03 +0200 +Subject: [PATCH platform backport v5.10 1/1] mlxsw: core: Add support for OSFP + transceiver modules + +The driver can already dump the EEPROM contents of QSFP-DD transceiver +modules via its ethtool_ops::get_module_info() and +ethtool_ops::get_module_eeprom() callbacks. + +Add support for OSFP transceiver modules by adding their SFF-8024 +Identifier Value (0x19). + +This is required for future NVIDIA Spectrum-4 based systems that will be +equipped with OSFP transceivers. + +Signed-off-by: Danielle Ratson +Signed-off-by: Ido Schimmel +Signed-off-by: David S. Miller +--- + drivers/net/ethernet/mellanox/mlxsw/core_env.c | 2 ++ + drivers/net/ethernet/mellanox/mlxsw/reg.h | 1 + + 2 files changed, 3 insertions(+) + +diff --git a/drivers/net/ethernet/mellanox/mlxsw/core_env.c b/drivers/net/ethernet/mellanox/mlxsw/core_env.c +index 98f7cf672d9e..f9c770eec8f8 100644 +--- a/drivers/net/ethernet/mellanox/mlxsw/core_env.c ++++ b/drivers/net/ethernet/mellanox/mlxsw/core_env.c +@@ -61,6 +61,7 @@ mlxsw_env_validate_cable_ident(struct mlxsw_core *core, u8 slot_index, int id, + *qsfp = true; + break; + case MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP_DD: ++ case MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_OSFP: + *qsfp = true; + *cmis = true; + break; +@@ -275,6 +276,7 @@ int mlxsw_env_get_module_info(struct mlxsw_core *mlxsw_core, u8 slot_index, + modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN / 2; + break; + case MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP_DD: ++ case MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_OSFP: + /* Use SFF_8636 as base type. ethtool should recognize specific + * type through the identifier value. + */ +diff --git a/drivers/net/ethernet/mellanox/mlxsw/reg.h b/drivers/net/ethernet/mellanox/mlxsw/reg.h +index ce3842ed8460..bec9d94b718a 100644 +--- a/drivers/net/ethernet/mellanox/mlxsw/reg.h ++++ b/drivers/net/ethernet/mellanox/mlxsw/reg.h +@@ -8950,6 +8950,7 @@ enum mlxsw_reg_mcia_eeprom_module_info_id { + MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP_PLUS = 0x0D, + MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP28 = 0x11, + MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP_DD = 0x18, ++ MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_OSFP = 0x19, + }; + + enum mlxsw_reg_mcia_eeprom_module_info { +-- +2.20.1 + diff --git a/patch/0175-hwmon-pmbus-Add-support-for-Infineon-Digital-Multi-p.patch b/patch/0175-hwmon-pmbus-Add-support-for-Infineon-Digital-Multi-p.patch new file mode 100644 index 000000000000..4f7b6a85b1cc --- /dev/null +++ b/patch/0175-hwmon-pmbus-Add-support-for-Infineon-Digital-Multi-p.patch @@ -0,0 +1,271 @@ +From 0daa4a8f50be59f0549bbda2d06ad5b74d5134bd Mon Sep 17 00:00:00 2001 +From: "Greg.Schwendimann@infineon.com" +Date: Wed, 27 Apr 2022 18:40:12 +0000 +Subject: [PATCH hwmon backport v5.10 1/1] hwmon: (pmbus) Add support for + Infineon Digital Multi-phase xdp152 family controllers + +Add support for devices XDPE152C4, XDPE12584. + +Signed-off-by: Greg Schwendimann +Link: https://lore.kernel.org/r/5e6d50e9b28140158f339b0de343eea4@infineon.com +Signed-off-by: Guenter Roeck +--- + Documentation/hwmon/index.rst | 1 + + Documentation/hwmon/xdpe152c4.rst | 118 ++++++++++++++++++++++++++++++ + drivers/hwmon/pmbus/Kconfig | 9 +++ + drivers/hwmon/pmbus/Makefile | 1 + + drivers/hwmon/pmbus/xdpe152c4.c | 75 +++++++++++++++++++ + 5 files changed, 204 insertions(+) + create mode 100644 Documentation/hwmon/xdpe152c4.rst + create mode 100644 drivers/hwmon/pmbus/xdpe152c4.c + +diff --git a/Documentation/hwmon/index.rst b/Documentation/hwmon/index.rst +index b797db738225..cd280009709c 100644 +--- a/Documentation/hwmon/index.rst ++++ b/Documentation/hwmon/index.rst +@@ -194,6 +194,7 @@ Hardware Monitoring Kernel Drivers + wm8350 + xgene-hwmon + xdpe12284 ++ xdpe152c4 + zl6100 + + .. only:: subproject and html +diff --git a/Documentation/hwmon/xdpe152c4.rst b/Documentation/hwmon/xdpe152c4.rst +new file mode 100644 +index 000000000000..ab92c32d4d69 +--- /dev/null ++++ b/Documentation/hwmon/xdpe152c4.rst +@@ -0,0 +1,118 @@ ++.. SPDX-License-Identifier: GPL-2.0 ++ ++Kernel driver xdpe152 ++===================== ++ ++Supported chips: ++ ++ * Infineon XDPE152C4 ++ ++ Prefix: 'xdpe152c4' ++ ++ * Infineon XDPE15284 ++ ++ Prefix: 'xdpe15284' ++ ++Authors: ++ ++ Greg Schwendimann ++ ++Description ++----------- ++ ++This driver implements support for Infineon Digital Multi-phase Controller ++XDPE152C4 and XDPE15284 dual loop voltage regulators. ++The devices are compliant with: ++ ++- Intel VR13, VR13HC and VR14 rev 1.86 ++ converter specification. ++- Intel SVID rev 1.93. protocol. ++- PMBus rev 1.3.1 interface. ++ ++Devices support linear format for reading input and output voltage, input ++and output current, input and output power and temperature. ++ ++Devices support two pages for telemetry. ++ ++The driver provides for current: input, maximum and critical thresholds ++and maximum and critical alarms. Low Critical thresholds and Low critical alarm are ++supported only for current output. ++The driver exports the following attributes for via the sysfs files, where ++indexes 1, 2 are for "iin" and 3, 4 for "iout": ++ ++**curr[1-4]_crit** ++ ++**curr[1-4]_crit_alarm** ++ ++**curr[1-4]_input** ++ ++**curr[1-4]_label** ++ ++**curr[1-4]_max** ++ ++**curr[1-4]_max_alarm** ++ ++**curr[3-4]_lcrit** ++ ++**curr[3-4]_lcrit_alarm** ++ ++**curr[3-4]_rated_max** ++ ++The driver provides for voltage: input, critical and low critical thresholds ++and critical and low critical alarms. ++The driver exports the following attributes for via the sysfs files, where ++indexes 1, 2 are for "vin" and 3, 4 for "vout": ++ ++**in[1-4]_min** ++ ++**in[1-4]_crit** ++ ++**in[1-4_crit_alarm** ++ ++**in[1-4]_input** ++ ++**in[1-4]_label** ++ ++**in[1-4]_max** ++ ++**in[1-4]_max_alarm** ++ ++**in[1-4]_min** ++ ++**in[1-4]_min_alarm** ++ ++**in[3-4]_lcrit** ++ ++**in[3-4]_lcrit_alarm** ++ ++**in[3-4]_rated_max** ++ ++**in[3-4]_rated_min** ++ ++The driver provides for power: input and alarms. ++The driver exports the following attributes for via the sysfs files, where ++indexes 1, 2 are for "pin" and 3, 4 for "pout": ++ ++**power[1-2]_alarm** ++ ++**power[1-4]_input** ++ ++**power[1-4]_label** ++ ++**power[1-4]_max** ++ ++**power[1-4]_rated_max** ++ ++The driver provides for temperature: input, maximum and critical thresholds ++and maximum and critical alarms. ++The driver exports the following attributes for via the sysfs files: ++ ++**temp[1-2]_crit** ++ ++**temp[1-2]_crit_alarm** ++ ++**temp[1-2]_input** ++ ++**temp[1-2]_max** ++ ++**temp[1-2]_max_alarm** +diff --git a/drivers/hwmon/pmbus/Kconfig b/drivers/hwmon/pmbus/Kconfig +index 41ff2bb28f0b..ee94fcfde685 100644 +--- a/drivers/hwmon/pmbus/Kconfig ++++ b/drivers/hwmon/pmbus/Kconfig +@@ -276,6 +276,15 @@ config SENSORS_UCD9200 + This driver can also be built as a module. If so, the module will + be called ucd9200. + ++config SENSORS_XDPE152 ++ tristate "Infineon XDPE152 family" ++ help ++ If you say yes here you get hardware monitoring support for Infineon ++ XDPE15284, XDPE152C4, device. ++ ++ This driver can also be built as a module. If so, the module will ++ be called xdpe152c4. ++ + config SENSORS_XDPE122 + tristate "Infineon XDPE122 family" + help +diff --git a/drivers/hwmon/pmbus/Makefile b/drivers/hwmon/pmbus/Makefile +index 8861a1b71acb..b1b9a3c8b616 100644 +--- a/drivers/hwmon/pmbus/Makefile ++++ b/drivers/hwmon/pmbus/Makefile +@@ -32,4 +32,5 @@ obj-$(CONFIG_SENSORS_TPS53679) += tps53679.o + obj-$(CONFIG_SENSORS_UCD9000) += ucd9000.o + obj-$(CONFIG_SENSORS_UCD9200) += ucd9200.o + obj-$(CONFIG_SENSORS_XDPE122) += xdpe12284.o ++obj-$(CONFIG_SENSORS_XDPE152) += xdpe152c4.o + obj-$(CONFIG_SENSORS_ZL6100) += zl6100.o +diff --git a/drivers/hwmon/pmbus/xdpe152c4.c b/drivers/hwmon/pmbus/xdpe152c4.c +new file mode 100644 +index 000000000000..b8a36ef73e45 +--- /dev/null ++++ b/drivers/hwmon/pmbus/xdpe152c4.c +@@ -0,0 +1,75 @@ ++// SPDX-License-Identifier: GPL-2.0-or-later ++/* ++ * Hardware monitoring driver for Infineon Multi-phase Digital VR Controllers ++ * ++ * Copyright (c) 2022 Infineon Technologies. All rights reserved. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include "pmbus.h" ++ ++#define XDPE152_PAGE_NUM 2 ++ ++static struct pmbus_driver_info xdpe152_info = { ++ .pages = XDPE152_PAGE_NUM, ++ .format[PSC_VOLTAGE_IN] = linear, ++ .format[PSC_VOLTAGE_OUT] = linear, ++ .format[PSC_TEMPERATURE] = linear, ++ .format[PSC_CURRENT_IN] = linear, ++ .format[PSC_CURRENT_OUT] = linear, ++ .format[PSC_POWER] = linear, ++ .func[0] = PMBUS_HAVE_VIN | PMBUS_HAVE_VOUT | PMBUS_HAVE_STATUS_VOUT | ++ PMBUS_HAVE_IIN | PMBUS_HAVE_IOUT | PMBUS_HAVE_STATUS_IOUT | ++ PMBUS_HAVE_TEMP | PMBUS_HAVE_TEMP2 | PMBUS_HAVE_STATUS_TEMP | ++ PMBUS_HAVE_POUT | PMBUS_HAVE_PIN | PMBUS_HAVE_STATUS_INPUT, ++ .func[1] = PMBUS_HAVE_VIN | PMBUS_HAVE_VOUT | PMBUS_HAVE_STATUS_VOUT | ++ PMBUS_HAVE_IIN | PMBUS_HAVE_IOUT | PMBUS_HAVE_STATUS_IOUT | ++ PMBUS_HAVE_POUT | PMBUS_HAVE_PIN | PMBUS_HAVE_STATUS_INPUT, ++}; ++ ++static int xdpe152_probe(struct i2c_client *client) ++{ ++ struct pmbus_driver_info *info; ++ ++ info = devm_kmemdup(&client->dev, &xdpe152_info, sizeof(*info), ++ GFP_KERNEL); ++ if (!info) ++ return -ENOMEM; ++ ++ return pmbus_do_probe(client, info); ++} ++ ++static const struct i2c_device_id xdpe152_id[] = { ++ {"xdpe152c4", 0}, ++ {"xdpe15284", 0}, ++ {} ++}; ++ ++MODULE_DEVICE_TABLE(i2c, xdpe152_id); ++ ++static const struct of_device_id __maybe_unused xdpe152_of_match[] = { ++ {.compatible = "infineon,xdpe152c4"}, ++ {.compatible = "infineon,xdpe15284"}, ++ {} ++}; ++MODULE_DEVICE_TABLE(of, xdpe152_of_match); ++ ++static struct i2c_driver xdpe152_driver = { ++ .driver = { ++ .name = "xdpe152c4", ++ .of_match_table = of_match_ptr(xdpe152_of_match), ++ }, ++ .probe_new = xdpe152_probe, ++ .id_table = xdpe152_id, ++}; ++ ++module_i2c_driver(xdpe152_driver); ++ ++MODULE_AUTHOR("Greg Schwendimann "); ++MODULE_DESCRIPTION("PMBus driver for Infineon XDPE152 family"); ++MODULE_LICENSE("GPL"); ++MODULE_IMPORT_NS(PMBUS); +-- +2.20.1 + diff --git a/patch/0180-hwmon-pmbus-Fix-sensors-readouts-for-MPS-Multi-phase.patch b/patch/0180-hwmon-pmbus-Fix-sensors-readouts-for-MPS-Multi-phase.patch new file mode 100644 index 000000000000..255263557f3d --- /dev/null +++ b/patch/0180-hwmon-pmbus-Fix-sensors-readouts-for-MPS-Multi-phase.patch @@ -0,0 +1,65 @@ +From ae1a79f21b9a91e1a8bf42586bd7a5c2afbb432a Mon Sep 17 00:00:00 2001 +From: Oleksandr Shamray +Date: Mon, 19 Sep 2022 14:55:22 +0300 +Subject: [PATCH hwmon 1/1] hwmon: (pmbus) Fix sensors readouts for MPS + Multi-phase mp2888 controller + +Fix scale factors for reading MPS Multi-phase mp2888 controller. +Fixed sensors: + - PIN/POUT: based on vendor documentation, set base scale factor 0.5W/LSB + - IOUT: based on vendor documentation, set base scale factor 0.25 A/LSB + +Fixes: e4db7719d037 ("hwmon: (pmbus) Add support for MPS Multi-phase mp2888 controller") +Signed-off-by: Oleksandr Shamray +Reviewed-by: Vadim Pasternak +--- + drivers/hwmon/pmbus/mp2888.c | 11 +++++------ + 1 file changed, 5 insertions(+), 6 deletions(-) + +diff --git a/drivers/hwmon/pmbus/mp2888.c b/drivers/hwmon/pmbus/mp2888.c +index 8ecd4ad..529eb3c 100644 +--- a/drivers/hwmon/pmbus/mp2888.c ++++ b/drivers/hwmon/pmbus/mp2888.c +@@ -109,7 +109,7 @@ mp2888_read_phase(struct i2c_client *client, struct mp2888_data *data, int page, + * - Kcs is the DrMOS current sense gain of power stage, which is obtained from the + * register MP2888_MFR_VR_CONFIG1, bits 13-12 with the following selection of DrMOS + * (data->curr_sense_gain): +- * 00b - 5µA/A, 01b - 8.5µA/A, 10b - 9.7µA/A, 11b - 10µA/A. ++ * 00b - 8.5µA/A, 01b - 9.7µA/A, 1b - 10µA/A, 11b - 5µA/A. + * - Rcs is the internal phase current sense resistor. This parameter depends on hardware + * assembly. By default it is set to 1kΩ. In case of different assembly, user should + * scale this parameter by dividing it by Rcs. +@@ -118,10 +118,9 @@ mp2888_read_phase(struct i2c_client *client, struct mp2888_data *data, int page, + * because sampling of current occurrence of bit weight has a big deviation, especially for + * light load. + */ +- ret = DIV_ROUND_CLOSEST(ret * 100 - 9800, data->curr_sense_gain); +- ret = (data->phase_curr_resolution) ? ret * 2 : ret; ++ ret = DIV_ROUND_CLOSEST(ret * 200 - 19600, data->curr_sense_gain); + /* Scale according to total current resolution. */ +- ret = (data->total_curr_resolution) ? ret * 8 : ret * 4; ++ ret = (data->total_curr_resolution) ? ret * 2 : ret; + return ret; + } + +@@ -212,7 +211,7 @@ static int mp2888_read_word_data(struct i2c_client *client, int page, int phase, + ret = pmbus_read_word_data(client, page, phase, reg); + if (ret < 0) + return ret; +- ret = data->total_curr_resolution ? ret * 2 : ret; ++ ret = data->total_curr_resolution ? ret : DIV_ROUND_CLOSEST(ret, 2); + break; + case PMBUS_POUT_OP_WARN_LIMIT: + ret = pmbus_read_word_data(client, page, phase, reg); +@@ -223,7 +222,7 @@ static int mp2888_read_word_data(struct i2c_client *client, int page, int phase, + * set 1. Actual power is reported with 0.5W or 1W respectively resolution. Scaling + * is needed to match both. + */ +- ret = data->total_curr_resolution ? ret * 4 : ret * 2; ++ ret = data->total_curr_resolution ? ret * 2 : ret; + break; + /* + * The below registers are not implemented by device or implemented not according to the +-- +2.8.4 + diff --git a/patch/kconfig-inclusions b/patch/kconfig-inclusions index dcb9fca833fd..9bcfe3abb16f 100644 --- a/patch/kconfig-inclusions +++ b/patch/kconfig-inclusions @@ -49,6 +49,11 @@ CONFIG_I2C_MUX_REG=m CONFIG_I2C_MUX_PCA954x=m CONFIG_I2C_MUX_MLXCPLD=m CONFIG_I2C_MLXCPLD=m +CONFIG_I2C_DESIGNWARE_PLATFORM=m +CONFIG_IOSF_MBI=y +CONFIG_I2C_DESIGNWARE_BAYTRAIL=y +CONFIG_I2C_DESIGNWARE_CORE=m +CONFIG_I2C_DESIGNWARE_PCI=m CONFIG_IIO_SYSFS_TRIGGER=m CONFIG_SENSORS_IIO_HWMON=m CONFIG_SENSORS_MLXREG_FAN=m @@ -62,6 +67,8 @@ CONFIG_SENSORS_MP2975=m CONFIG_SENSORS_TMP421=m CONFIG_SENSORS_STTS751=m CONFIG_SENSORS_POWR1220=m +CONFIG_SENSORS_XDPE152=m +CONFIG_SENSORS_DRIVETEMP=m CONFIG_TI_ADS1015=m CONFIG_GPIO_PCA953X=m CONFIG_SERIAL_8250_DETECT_IRQ=y diff --git a/patch/series b/patch/series index c0c5e9a8690e..f81628285d53 100755 --- a/patch/series +++ b/patch/series @@ -144,8 +144,20 @@ kernel-compat-always-include-linux-compat.h-from-net-compat.patch 0097-hwmon-mlxreg-fan-Support-distinctive-names-per-.patch 0999-Revert-mlxsw-thermal-Fix-out-of-bounds-memory-a.patch 0098-mlxsw-i2c-Prevent-transaction-execution-for.patch -0163-platform-mellanox-Add-COME-board-revision-register.patch +0157-platform-x86-mlx-platform-Make-activation-of-some-dr.patch +0158-platform-x86-mlx-platform-Add-cosmetic-changes-for-a.patch +0159-mlx-platform-Add-support-for-systems-equipped-with-t.patch +0160-platform-mellanox-Introduce-support-for-COMe-NVSwitc.patch +0161-platform-x86-mlx-platform-Add-support-for-new-system.patch +0162-platform-mellanox-Add-COME-board-revision-register.patch +0164-hwmon-jc42-Add-support-for-Seiko-Instruments-S-34TS0.patch +0165-platform-mellanox-mlxreg-io-Add-locking-for-io-opera.patch 0167-leds-mlxreg-Send-udev-change-event.patch +0170-i2c-mlxcpld-Fix-register-setting-for-400KHz-frequenc.patch +0171-platform-mellanox-mlxreg-lc-Fix-cleanup-on-failure-a.patch +0173-core-Add-support-for-OSFP-transceiver-modules.patch +0175-hwmon-pmbus-Add-support-for-Infineon-Digital-Multi-p.patch +0180-hwmon-pmbus-Fix-sensors-readouts-for-MPS-Multi-phase.patch # Cisco patches for 5.10 kernel cisco-mtd-part.patch