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Fixes PWM on TIM1 #187

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Feb 23, 2020
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1 change: 1 addition & 0 deletions CHANGELOG.md
Original file line number Diff line number Diff line change
Expand Up @@ -11,6 +11,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
- Use `Deref` for SPI generic implementations instead of macros
- Make traits `rcc::Enable` and `rcc::Reset` public, but `RccBus` sealed
- Add `QeiOptions` struct to configure slave mode and auto reload value of QEI interface
- Fix PWM on `TIM1`

## [v0.5.3] - 2020-01-20

Expand Down
62 changes: 20 additions & 42 deletions src/pwm.rs
Original file line number Diff line number Diff line change
Expand Up @@ -56,17 +56,13 @@
use core::marker::PhantomData;
use core::mem;

use cast::{u16, u32};
use crate::hal;
#[cfg(any(
feature = "stm32f100",
feature = "stm32f103",
feature = "stm32f105",
))]
#[cfg(any(feature = "stm32f100", feature = "stm32f103", feature = "stm32f105",))]
use crate::pac::TIM1;
use crate::pac::{TIM2, TIM3};
#[cfg(feature = "medium")]
use crate::pac::TIM4;
use crate::pac::{TIM2, TIM3};
use cast::{u16, u32};

use crate::afio::MAPR;
use crate::bb;
Expand All @@ -82,7 +78,7 @@ pub trait Pins<REMAP, P> {
type Channels;
}

use crate::timer::sealed::{Remap, Ch1, Ch2, Ch3, Ch4};
use crate::timer::sealed::{Ch1, Ch2, Ch3, Ch4, Remap};
macro_rules! pins_impl {
( $( ( $($PINX:ident),+ ), ( $($TRAIT:ident),+ ), ( $($ENCHX:ident),* ); )+ ) => {
$(
Expand Down Expand Up @@ -117,37 +113,27 @@ pins_impl!(
(P4), (Ch4), (C4);
);

#[cfg(any(
feature = "stm32f100",
feature = "stm32f103",
feature = "stm32f105",
))]
#[cfg(any(feature = "stm32f100", feature = "stm32f103", feature = "stm32f105",))]
impl Timer<TIM1> {
pub fn pwm<REMAP, P, PINS, T>(
self,
_pins: PINS,
mapr: &mut MAPR,
freq: T,
) -> PINS::Channels
pub fn pwm<REMAP, P, PINS, T>(self, _pins: PINS, mapr: &mut MAPR, freq: T) -> PINS::Channels
where
REMAP: Remap<Periph = TIM1>,
PINS: Pins<REMAP, P>,
T: Into<Hertz>,
{
mapr.modify_mapr(|_, w| unsafe { w.tim1_remap().bits(REMAP::REMAP) });

// TIM1 has a break function that deactivates the outputs, this bit automatically activates
// the output when no break input is present
self.tim.bdtr.modify(|_, w| w.aoe().set_bit());

let Self { tim, clk } = self;
tim1(tim, _pins, freq.into(), clk)
}
}

impl Timer<TIM2> {
pub fn pwm<REMAP, P, PINS, T>(
self,
_pins: PINS,
mapr: &mut MAPR,
freq: T,
) -> PINS::Channels
pub fn pwm<REMAP, P, PINS, T>(self, _pins: PINS, mapr: &mut MAPR, freq: T) -> PINS::Channels
where
REMAP: Remap<Periph = TIM2>,
PINS: Pins<REMAP, P>,
Expand All @@ -161,12 +147,7 @@ impl Timer<TIM2> {
}

impl Timer<TIM3> {
pub fn pwm<REMAP, P, PINS, T>(
self,
_pins: PINS,
mapr: &mut MAPR,
freq: T,
) -> PINS::Channels
pub fn pwm<REMAP, P, PINS, T>(self, _pins: PINS, mapr: &mut MAPR, freq: T) -> PINS::Channels
where
REMAP: Remap<Periph = TIM3>,
PINS: Pins<REMAP, P>,
Expand All @@ -181,12 +162,7 @@ impl Timer<TIM3> {

#[cfg(feature = "medium")]
impl Timer<TIM4> {
pub fn pwm<REMAP, P, PINS, T>(
self,
_pins: PINS,
mapr: &mut MAPR,
freq: T,
) -> PINS::Channels
pub fn pwm<REMAP, P, PINS, T>(self, _pins: PINS, mapr: &mut MAPR, freq: T) -> PINS::Channels
where
REMAP: Remap<Periph = TIM4>,
PINS: Pins<REMAP, P>,
Expand Down Expand Up @@ -247,6 +223,12 @@ macro_rules! hal {
let arr = u16(ticks / u32(psc + 1)).unwrap();
tim.arr.write(|w| w.arr().bits(arr));

// The psc register is buffered, so we trigger an update event to update it
// Sets the URS bit to prevent an interrupt from being triggered by the UG bit
tim.cr1.modify(|_, w| w.urs().set_bit());
tim.egr.write(|w| w.ug().set_bit());
tim.cr1.modify(|_, w| w.urs().clear_bit());

tim.cr1.write(|w|
w.cms()
.bits(0b00)
Expand Down Expand Up @@ -360,11 +342,7 @@ macro_rules! hal {
}
}

#[cfg(any(
feature = "stm32f100",
feature = "stm32f103",
feature = "stm32f105",
))]
#[cfg(any(feature = "stm32f100", feature = "stm32f103", feature = "stm32f105",))]
hal! {
TIM1: (tim1),
}
Expand Down