Handle debugger pins

[TeXitoi]

At startup, pins used by the debugger are in Debugger state, prohibiting their
use. disable_jtag allow to get PA15, PB3 and PB4 usable as GPIO or alternate
functions at the cost of disabling JTAG.

Discussed in #77

cc @MauroMombelli

[TeXitoi]

I've tested nojtag on a bluepill with success.

[TeXitoi]

It doesn't work :-( This complies:

#![deny(unsafe_code)]
#![no_main]
#![no_std]

use panic_halt as _;

use stm32f1xx_hal::{
    prelude::*,
    pac,
};
use cortex_m_rt::entry;

#[entry]
fn main() -> ! {
    let p = pac::Peripherals::take().unwrap();

    let mut rcc = p.RCC.constrain();
    let mut gpioa = p.GPIOA.split(&mut rcc.apb2);
    let mut gpiob = p.GPIOB.split(&mut rcc.apb2);
    let mut afio = p.AFIO.constrain(&mut rcc.apb2);

    //let (pa15, pb3, pb4) = afio.mapr.disable_jtag(gpioa.pa15, gpiob.pb3, gpiob.pb4);

    let mut pa15 = gpioa.pa15.into_push_pull_output(&mut gpioa.crh);
    let mut pb3 = gpiob.pb3.into_push_pull_output(&mut gpiob.crl);
    let mut pb4 = gpiob.pb4.into_push_pull_output(&mut gpiob.crl);

    loop {
        pa15.toggle();
        pb3.toggle();
        pb4.toggle();
        cortex_m::asm::delay(8_000_000);
    }
}

[thalesfragoso]

Maybe if you create a marker (empty) trait and implement it for Input<MODE>, Output<MODE>, Analog and Alternate<MODE>(maybe I'm missing another) but not for Debugger. And then you can add a bound to MODE on line 189.

Sorry for some lacking explanation, I'm on mobile right now.

[TeXitoi]

I see the idea, thanks, will try.

[TeXitoi]

@thalesfragoso Thanks it's working.

[MauroMombelli]

yay! Suggestion: those are not the only tricky pin, we could also completely disable debugging to get other 2 pin (PA13 and PA14).

PB2 could be used as GPIO or BOOT1 depending on the initial status (cant find how right now)

PD0 and PD1 are by default external clock, those could be reclaimed (not sure if they are already "fixed")

PC13 (tamper RTC), PC14(osc32_in) and PC15(osc32_out) also could be in a special state:

(GPIO is)Main function after the first backup domain power-up. Later on, it depends on the contents of the Backup registers even after reset (because these registers are not reset by the main reset). For details on how to manage these IOs, refer to theBattery backup domain and BKP register description sections in the STM32F10xxx reference manual, available from the STMicroelectronics website: www.st.com.

i took a look around and i saw a lot people banging their head against those pin used as debug by default; im sure the PR will help a lot of people to identify the problem

also i am wandering if this should be proposed to the other implementations too.

[TeXitoi]

I've blocked PA13 and PA14, freeing them would only be adding a disable_jtag_sw taking the 5 pins.

[TeXitoi]

also i am wandering if this should be proposed to the other implementations too.

I don't understand this sentence. Which other implementations?

[MauroMombelli]

I don't understand this sentence. Which other implementations?

other chip implementation like stm32f3xx-hal etc..

[therealprof]

Hm, using MaybeUninit will bump the MSRV to 1.36, i.e. the latest and greatest. I personally don't have a problem with that but I can imagine people frowning upon that...

[TeXitoi]

@therealprof so you want I dont use it? I can, that's just using uninitialized instead.

[TeXitoi]

Or i thinks i can remove this uninitialized trick.

[TeXitoi]

@therealprof no more MaybeUninit

[therealprof]

Looking good, thanks!