From 853a50086545b017dfd6989c63f4698cd764e35d Mon Sep 17 00:00:00 2001 From: Andrey Zgarbul Date: Wed, 18 Oct 2023 17:05:44 +0300 Subject: [PATCH 1/3] update to svd2rust 0.33.3 & use stm32f4-staging --- CHANGELOG.md | 6 + Cargo.toml | 6 +- examples/analog-stopwatch-with-spi-ssd1306.rs | 2 +- src/adc.rs | 110 +++--- src/crc32.rs | 14 +- src/dac.rs | 7 +- src/dma/mod.rs | 84 ++--- src/dma/traits.rs | 22 +- src/dma/traits/f4.rs | 8 +- src/flash.rs | 50 ++- src/fmpi2c.rs | 103 +++--- src/fsmc_lcd/mod.rs | 42 ++- src/fsmc_lcd/timing.rs | 24 +- src/gpio.rs | 12 +- src/gpio/convert.rs | 8 +- src/gpio/erased.rs | 8 +- src/gpio/exti.rs | 28 +- src/gpio/outport.rs | 12 +- src/gpio/partially_erased.rs | 8 +- src/i2c.rs | 79 ++--- src/i2c/dma.rs | 42 +-- src/i2s.rs | 2 +- src/qei.rs | 8 +- src/qspi.rs | 88 ++--- src/rcc/mod.rs | 94 +++-- src/rcc/pll.rs | 26 +- src/rng.rs | 6 +- src/rtc.rs | 328 +++++++++--------- src/sdio.rs | 237 ++++++------- src/serial.rs | 12 +- src/serial/uart_impls.rs | 47 +-- src/spi.rs | 64 ++-- src/timer.rs | 74 ++-- src/timer/counter.rs | 2 +- src/timer/monotonic.rs | 2 +- src/timer/monotonics.rs | 30 +- src/timer/pwm_input.rs | 16 +- src/uart.rs | 23 +- src/watchdog.rs | 20 +- 39 files changed, 867 insertions(+), 887 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index 91ad77a0b..927a1bff6 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -7,6 +7,12 @@ and this project adheres to [Semantic Versioning](http://semver.org/). ## [Unreleased] +### Changed + + - Use `stm32f4-staging` until `stm32f4` is released [#706] + +[#706]: https://github.com/stm32-rs/stm32f4xx-hal/pull/706 + ## [v0.21.0] - 2024-05-30 ### Changed diff --git a/Cargo.toml b/Cargo.toml index 26e68eb8f..ae3007873 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -33,7 +33,6 @@ cortex-m = { version = "0.7.7", features = ["critical-section-single-core"] } cortex-m-rt = "0.7.3" nb = "1.1" rand_core = "0.6.4" -stm32f4 = "0.15.1" synopsys-usb-otg = { version = "0.4.0", features = [ "cortex-m", ], optional = true } @@ -62,6 +61,11 @@ embedded-storage = "0.3" vcell = "0.1.3" document-features = "0.2" +[dependencies.stm32f4] +package = "stm32f4-staging" +version = "0.16.0" +features = ["defmt", "atomics"] + [dependencies.time] version = "0.3.14" default-features = false diff --git a/examples/analog-stopwatch-with-spi-ssd1306.rs b/examples/analog-stopwatch-with-spi-ssd1306.rs index eac2596b8..fa57ea0c6 100644 --- a/examples/analog-stopwatch-with-spi-ssd1306.rs +++ b/examples/analog-stopwatch-with-spi-ssd1306.rs @@ -65,7 +65,7 @@ enum StopwatchState { fn main() -> ! { let mut dp = pac::Peripherals::take().unwrap(); let cp = cortex_m::peripheral::Peripherals::take().unwrap(); - dp.RCC.apb2enr.write(|w| w.syscfgen().enabled()); + dp.RCC.apb2enr().write(|w| w.syscfgen().enabled()); let rcc = dp.RCC.constrain(); diff --git a/src/adc.rs b/src/adc.rs index b41a32d2c..37401998c 100644 --- a/src/adc.rs +++ b/src/adc.rs @@ -98,7 +98,7 @@ //! //! //Channel 1 //! //Disable the channel before configuring it -//! tim.ccer.modify(|_, w| w.cc1e().clear_bit()); +//! tim.ccer().modify(|_, w| w.cc1e().clear_bit()); //! //! tim.ccmr1_output().modify(|_, w| w //! //Preload enable for channel @@ -591,7 +591,7 @@ macro_rules! adc { pub fn enable_vbat(&self) { unsafe { let common = &(*pac::$common_type::ptr()); - common.ccr.modify(|_, w| w.vbate().set_bit()); + common.ccr().modify(|_, w| w.vbate().set_bit()); } } @@ -599,7 +599,7 @@ macro_rules! adc { pub fn disable_vbat(&self) { unsafe { let common = &(*pac::$common_type::ptr()); - common.ccr.modify(|_, w| w.vbate().clear_bit()); + common.ccr().modify(|_, w| w.vbate().clear_bit()); } } @@ -610,7 +610,7 @@ macro_rules! adc { self.disable_vbat(); unsafe { let common = &(*pac::$common_type::ptr()); - common.ccr.modify(|_, w| w.tsvrefe().set_bit()); + common.ccr().modify(|_, w| w.tsvrefe().set_bit()); } } @@ -618,7 +618,7 @@ macro_rules! adc { pub fn disable_temperature_and_vref(&mut self) { unsafe { let common = &(*pac::$common_type::ptr()); - common.ccr.modify(|_, w| w.tsvrefe().clear_bit()); + common.ccr().modify(|_, w| w.tsvrefe().clear_bit()); } } @@ -626,7 +626,7 @@ macro_rules! adc { pub fn temperature_and_vref_enabled(&mut self) -> bool { unsafe { let common = &(*pac::$common_type::ptr()); - common.ccr.read().tsvrefe().bit_is_set() + common.ccr().read().tsvrefe().bit_is_set() } } }; @@ -703,12 +703,12 @@ macro_rules! adc { /// Returns if the adc is enabled pub fn is_enabled(&self) -> bool { - self.adc_reg.cr2.read().adon().bit_is_set() + self.adc_reg.cr2().read().adon().bit_is_set() } /// Enables the adc pub fn enable(&mut self) { - self.adc_reg.cr2.modify(|_, w| w.adon().set_bit()); + self.adc_reg.cr2().modify(|_, w| w.adon().set_bit()); } /// Disables the adc @@ -718,7 +718,7 @@ macro_rules! adc { /// the ADC before changing them. The reference manual for the chip I'm using only states /// that the sequence registers are locked when they are being converted. pub fn disable(&mut self) { - self.adc_reg.cr2.modify(|_, w| w.adon().clear_bit()); + self.adc_reg.cr2().modify(|_, w| w.adon().clear_bit()); } /// Starts conversion sequence. Waits for the hardware to indicate it's actually started. @@ -726,9 +726,9 @@ macro_rules! adc { self.enable(); self.clear_end_of_conversion_flag(); //Start conversion - self.adc_reg.cr2.modify(|_, w| w.swstart().set_bit()); + self.adc_reg.cr2().modify(|_, w| w.swstart().set_bit()); - while !self.adc_reg.sr.read().strt().bit_is_set() {} + while !self.adc_reg.sr().read().strt().bit_is_set() {} } /// Sets the clock for the adc @@ -736,7 +736,7 @@ macro_rules! adc { self.config.clock = clock; unsafe { let common = &(*pac::$common_type::ptr()); - common.ccr.modify(|_, w| w.adcpre().bits(clock as _)); + common.ccr().modify(|_, w| w.adcpre().bits(clock as _)); } } @@ -749,19 +749,19 @@ macro_rules! adc { config::Resolution::Six => (1 << 6), }; self.config.resolution = resolution; - self.adc_reg.cr1.modify(|_, w| w.res().bits(resolution as _)); + self.adc_reg.cr1().modify(|_, w| w.res().set(resolution as _)); } /// Sets the DR register alignment to left or right pub fn set_align(&mut self, align: config::Align) { self.config.align = align; - self.adc_reg.cr2.modify(|_, w| w.align().bit(align.into())); + self.adc_reg.cr2().modify(|_, w| w.align().bit(align.into())); } /// Enables and disables scan mode pub fn set_scan(&mut self, scan: config::Scan) { self.config.scan = scan; - self.adc_reg.cr1.modify(|_, w| w.scan().bit(scan.into())); + self.adc_reg.cr1().modify(|_, w| w.scan().bit(scan.into())); } /// Sets which external trigger to use and if it is disabled, rising, falling or both @@ -772,7 +772,7 @@ macro_rules! adc { feature = "stm32f410", feature = "stm32f411", ))] // TODO: fix pac - self.adc_reg.cr2.modify(|_, w| unsafe { w + self.adc_reg.cr2().modify(|_, w| unsafe { w .extsel().bits(extsel as _) .exten().bits(edge as _) }); @@ -781,16 +781,16 @@ macro_rules! adc { feature = "stm32f410", feature = "stm32f411", )))] - self.adc_reg.cr2.modify(|_, w| w - .extsel().bits(extsel as _) - .exten().bits(edge as _) + self.adc_reg.cr2().modify(|_, w| w + .extsel().set(extsel as _) + .exten().set(edge as _) ); } /// Enables and disables continuous mode pub fn set_continuous(&mut self, continuous: config::Continuous) { self.config.continuous = continuous; - self.adc_reg.cr2.modify(|_, w| w.cont().bit(continuous.into())); + self.adc_reg.cr2().modify(|_, w| w.cont().bit(continuous.into())); } /// Sets DMA to disabled, single or continuous @@ -801,7 +801,7 @@ macro_rules! adc { config::Dma::Single => (false, true), config::Dma::Continuous => (true, true), }; - self.adc_reg.cr2.modify(|_, w| w + self.adc_reg.cr2().modify(|_, w| w //DDS stands for "DMA disable selection" //0 means do one DMA then stop //1 means keep sending DMA requests as long as DMA=1 @@ -819,13 +819,13 @@ macro_rules! adc { config::Eoc::Conversion => (true, true), config::Eoc::Sequence => (true, false), }; - self.adc_reg.cr1.modify(|_, w| w.eocie().bit(en)); - self.adc_reg.cr2.modify(|_, w| w.eocs().bit(eocs)); + self.adc_reg.cr1().modify(|_, w| w.eocie().bit(en)); + self.adc_reg.cr2().modify(|_, w| w.eocs().bit(eocs)); } /// Resets the end-of-conversion flag pub fn clear_end_of_conversion_flag(&mut self) { - self.adc_reg.sr.modify(|_, w| w.eoc().clear_bit()); + self.adc_reg.sr().modify(|_, w| w.eoc().clear_bit()); } /// Sets the default sample time that is used for one-shot conversions. @@ -837,18 +837,18 @@ macro_rules! adc { /// Returns the current sequence length. Primarily useful for configuring DMA. pub fn sequence_length(&mut self) -> u8 { - self.adc_reg.sqr1.read().l().bits() + 1 + self.adc_reg.sqr1().read().l().bits() + 1 } /// Reset the sequence pub fn reset_sequence(&mut self) { //The reset state is One conversion selected - self.adc_reg.sqr1.modify(|_, w| w.l().bits(config::Sequence::One.into())); + self.adc_reg.sqr1().modify(|_, w| w.l().set(config::Sequence::One.into())); } /// Returns the address of the ADC data register. Primarily useful for configuring DMA. pub fn data_register_address(&mut self) -> u32 { - self.adc_reg.dr.as_ptr() as u32 + self.adc_reg.dr().as_ptr() as u32 } /// Configure a channel for sampling. @@ -863,10 +863,10 @@ macro_rules! adc { CHANNEL: embedded_hal_02::adc::Channel { //Check the sequence is long enough - self.adc_reg.sqr1.modify(|r, w| { + self.adc_reg.sqr1().modify(|r, w| { let prev: config::Sequence = r.l().bits().into(); if prev < sequence { - w.l().bits(sequence.into()) + w.l().set(sequence.into()) } else { w } @@ -876,22 +876,22 @@ macro_rules! adc { //Set the channel in the right sequence field match sequence { - config::Sequence::One => self.adc_reg.sqr3.modify(|_, w| unsafe {w.sq1().bits(channel) }), - config::Sequence::Two => self.adc_reg.sqr3.modify(|_, w| unsafe {w.sq2().bits(channel) }), - config::Sequence::Three => self.adc_reg.sqr3.modify(|_, w| unsafe {w.sq3().bits(channel) }), - config::Sequence::Four => self.adc_reg.sqr3.modify(|_, w| unsafe {w.sq4().bits(channel) }), - config::Sequence::Five => self.adc_reg.sqr3.modify(|_, w| unsafe {w.sq5().bits(channel) }), - config::Sequence::Six => self.adc_reg.sqr3.modify(|_, w| unsafe {w.sq6().bits(channel) }), - config::Sequence::Seven => self.adc_reg.sqr2.modify(|_, w| unsafe {w.sq7().bits(channel) }), - config::Sequence::Eight => self.adc_reg.sqr2.modify(|_, w| unsafe {w.sq8().bits(channel) }), - config::Sequence::Nine => self.adc_reg.sqr2.modify(|_, w| unsafe {w.sq9().bits(channel) }), - config::Sequence::Ten => self.adc_reg.sqr2.modify(|_, w| unsafe {w.sq10().bits(channel) }), - config::Sequence::Eleven => self.adc_reg.sqr2.modify(|_, w| unsafe {w.sq11().bits(channel) }), - config::Sequence::Twelve => self.adc_reg.sqr2.modify(|_, w| unsafe {w.sq12().bits(channel) }), - config::Sequence::Thirteen => self.adc_reg.sqr1.modify(|_, w| unsafe {w.sq13().bits(channel) }), - config::Sequence::Fourteen => self.adc_reg.sqr1.modify(|_, w| unsafe {w.sq14().bits(channel) }), - config::Sequence::Fifteen => self.adc_reg.sqr1.modify(|_, w| unsafe {w.sq15().bits(channel) }), - config::Sequence::Sixteen => self.adc_reg.sqr1.modify(|_, w| unsafe {w.sq16().bits(channel) }), + config::Sequence::One => self.adc_reg.sqr3().modify(|_, w| unsafe {w.sq1().bits(channel) }), + config::Sequence::Two => self.adc_reg.sqr3().modify(|_, w| unsafe {w.sq2().bits(channel) }), + config::Sequence::Three => self.adc_reg.sqr3().modify(|_, w| unsafe {w.sq3().bits(channel) }), + config::Sequence::Four => self.adc_reg.sqr3().modify(|_, w| unsafe {w.sq4().bits(channel) }), + config::Sequence::Five => self.adc_reg.sqr3().modify(|_, w| unsafe {w.sq5().bits(channel) }), + config::Sequence::Six => self.adc_reg.sqr3().modify(|_, w| unsafe {w.sq6().bits(channel) }), + config::Sequence::Seven => self.adc_reg.sqr2().modify(|_, w| unsafe {w.sq7().bits(channel) }), + config::Sequence::Eight => self.adc_reg.sqr2().modify(|_, w| unsafe {w.sq8().bits(channel) }), + config::Sequence::Nine => self.adc_reg.sqr2().modify(|_, w| unsafe {w.sq9().bits(channel) }), + config::Sequence::Ten => self.adc_reg.sqr2().modify(|_, w| unsafe {w.sq10().bits(channel) }), + config::Sequence::Eleven => self.adc_reg.sqr2().modify(|_, w| unsafe {w.sq11().bits(channel) }), + config::Sequence::Twelve => self.adc_reg.sqr2().modify(|_, w| unsafe {w.sq12().bits(channel) }), + config::Sequence::Thirteen => self.adc_reg.sqr1().modify(|_, w| unsafe {w.sq13().bits(channel) }), + config::Sequence::Fourteen => self.adc_reg.sqr1().modify(|_, w| unsafe {w.sq14().bits(channel) }), + config::Sequence::Fifteen => self.adc_reg.sqr1().modify(|_, w| unsafe {w.sq15().bits(channel) }), + config::Sequence::Sixteen => self.adc_reg.sqr1().modify(|_, w| unsafe {w.sq16().bits(channel) }), } fn replace_bits(mut v: u32, offset: u32, width: u32, value: u32) -> u32 { @@ -905,15 +905,15 @@ macro_rules! adc { let st = sample_time as u32; let ch = channel as u32; match channel { - 0..=9 => self.adc_reg.smpr2.modify(|r, w| unsafe { w.bits(replace_bits(r.bits(), ch, 3, st)) }), - 10..=18 => self.adc_reg.smpr1.modify(|r, w| unsafe { w.bits(replace_bits(r.bits(), ch-10, 3, st)) }), + 0..=9 => self.adc_reg.smpr2().modify(|r, w| unsafe { w.bits(replace_bits(r.bits(), ch, 3, st)) }), + 10..=18 => self.adc_reg.smpr1().modify(|r, w| unsafe { w.bits(replace_bits(r.bits(), ch-10, 3, st)) }), _ => unimplemented!(), } } /// Returns the current sample stored in the ADC data register pub fn current_sample(&self) -> u16 { - self.adc_reg.dr.read().data().bits() + self.adc_reg.dr().read().data().bits() } /// Converts a sample value to millivolts using calibrated VDDA and configured resolution. @@ -941,12 +941,12 @@ macro_rules! adc { /// # Panics /// Will panic if there is no conversion started and the end-of-conversion bit is not set pub fn wait_for_conversion_sequence(&self) { - if !self.adc_reg.sr.read().strt().bit_is_set() && !self.adc_reg.sr.read().eoc().bit_is_set() { + if !self.adc_reg.sr().read().strt().bit_is_set() && !self.adc_reg.sr().read().eoc().bit_is_set() { panic!("Waiting for end-of-conversion but no conversion started"); } - while !self.adc_reg.sr.read().eoc().bit_is_set() {} + while !self.adc_reg.sr().read().eoc().bit_is_set() {} //Clear the conversion started flag - self.adc_reg.sr.modify(|_, w| w.strt().clear_bit()); + self.adc_reg.sr().modify(|_, w| w.strt().clear_bit()); } /// Synchronously convert a single sample @@ -955,13 +955,13 @@ macro_rules! adc { where PIN: embedded_hal_02::adc::Channel { - self.adc_reg.cr2.modify(|_, w| w + self.adc_reg.cr2().modify(|_, w| w .dma().clear_bit() //Disable dma .cont().clear_bit() //Disable continuous mode - .exten().bits(config::TriggerMode::Disabled.into()) //Disable trigger + .exten().set(config::TriggerMode::Disabled.into()) //Disable trigger .eocs().clear_bit() //EOC is set at the end of the sequence ); - self.adc_reg.cr1.modify(|_, w| w + self.adc_reg.cr1().modify(|_, w| w .scan().clear_bit() //Disable scan mode .eocie().clear_bit() //Disable end of conversion interrupt ); @@ -1017,7 +1017,7 @@ macro_rules! adc { unsafe impl PeriAddress for Adc { #[inline(always)] fn address(&self) -> u32 { - self.adc_reg.dr.as_ptr() as u32 + self.adc_reg.dr().as_ptr() as u32 } type MemSize = u16; diff --git a/src/crc32.rs b/src/crc32.rs index f4682216f..a1f75ee40 100644 --- a/src/crc32.rs +++ b/src/crc32.rs @@ -35,7 +35,7 @@ impl Crc32 { /// Reset the internal CRC32 state to the default value (0xFFFF_FFFF) #[inline(always)] pub fn init(&mut self) { - self.periph.cr.write(|w| w.reset().reset()); + self.periph.cr().write(|w| w.reset().reset()); } /// Feed words into the CRC engine. @@ -45,10 +45,10 @@ impl Crc32 { pub fn update(&mut self, data: &[u32]) -> u32 { // Feed each word into the engine for word in data { - self.periph.dr.write(|w| w.bits(*word)); + self.periph.dr().write(|w| w.set(*word)); } // Retrieve the resulting CRC - self.periph.dr.read().bits() + self.periph.dr().read().bits() } /// Feed bytes into the CRC engine. @@ -95,7 +95,7 @@ impl Crc32 { // Mark the scratch bytes as initialized, and then convert it to a // native-endian u32. Feed this into the CRC peripheral self.periph - .dr + .dr() .write(|w| w.bits(u32::from_ne_bytes(scratch.assume_init()))); }); @@ -109,11 +109,11 @@ impl Crc32 { // MOST significant bytes as zeroes scratch[..remainder.len()].copy_from_slice(remainder); self.periph - .dr - .write(|w| w.bits(u32::from_ne_bytes(scratch))); + .dr() + .write(|w| w.set(u32::from_ne_bytes(scratch))); } - self.periph.dr.read().bits() + self.periph.dr().read().bits() } /// Consume the HAL peripheral, returning the PAC peripheral diff --git a/src/dac.rs b/src/dac.rs index fc6fe4e60..0b0777b18 100644 --- a/src/dac.rs +++ b/src/dac.rs @@ -67,19 +67,19 @@ macro_rules! dac { impl DacPin for $CX { fn enable(&mut self) { let dac = unsafe { &(*DAC::ptr()) }; - dac.cr.modify(|_, w| w.$en().set_bit()); + dac.cr().modify(|_, w| w.$en().set_bit()); } } impl DacOut for $CX { fn set_value(&mut self, val: u16) { let dac = unsafe { &(*DAC::ptr()) }; - dac.$dhrx.write(|w| unsafe { w.bits(val as u32) }); + dac.$dhrx().write(|w| unsafe { w.bits(val as u32) }); } fn get_value(&mut self) -> u16 { let dac = unsafe { &(*DAC::ptr()) }; - dac.$dac_dor.read().bits() as u16 + dac.$dac_dor().read().bits() as u16 } } }; @@ -101,4 +101,5 @@ impl DacExt for DAC { } dac!(C1, en1, cen1, cal_flag1, otrim1, mode1, dhr12r1, dor1, dacc1dhr); +#[cfg(not(feature = "stm32f410"))] dac!(C2, en2, cen2, cal_flag2, otrim2, mode2, dhr12r2, dor2, dacc2dhr); diff --git a/src/dma/mod.rs b/src/dma/mod.rs index bf5d256c9..6121a94f1 100644 --- a/src/dma/mod.rs +++ b/src/dma/mod.rs @@ -383,12 +383,12 @@ impl StreamX { #[cfg(not(any(feature = "gpio-f411", feature = "gpio-f413", feature = "gpio-f410")))] #[inline(always)] unsafe fn st() -> &'static pac::dma2::ST { - &(*DMA::ptr()).st[S as usize] + (*DMA::ptr()).st(S as usize) } #[cfg(any(feature = "gpio-f411", feature = "gpio-f413", feature = "gpio-f410"))] #[inline(always)] unsafe fn st() -> &'static pac::dma1::ST { - &(*DMA::ptr()).st[S as usize] + (*DMA::ptr()).st(S as usize) } } @@ -481,183 +481,187 @@ where #[inline(always)] fn set_peripheral_address(&mut self, value: u32) { unsafe { Self::st() } - .par + .par() .write(|w| unsafe { w.pa().bits(value) }); } #[inline(always)] fn set_memory_address(&mut self, value: u32) { unsafe { Self::st() } - .m0ar + .m0ar() .write(|w| unsafe { w.m0a().bits(value) }); } #[inline(always)] fn memory_address(&self) -> u32 { - unsafe { Self::st() }.m0ar.read().m0a().bits() + unsafe { Self::st() }.m0ar().read().m0a().bits() } #[inline(always)] fn set_alternate_memory_address(&mut self, value: u32) { unsafe { Self::st() } - .m1ar + .m1ar() .write(|w| unsafe { w.m1a().bits(value) }); } #[inline(always)] fn alternate_memory_address(&self) -> u32 { - unsafe { Self::st() }.m1ar.read().m1a().bits() + unsafe { Self::st() }.m1ar().read().m1a().bits() } #[inline(always)] fn set_number_of_transfers(&mut self, value: u16) { - unsafe { Self::st() }.ndtr.write(|w| w.ndt().bits(value)); + unsafe { Self::st() }.ndtr().write(|w| w.ndt().set(value)); } #[inline(always)] fn number_of_transfers(&self) -> u16 { - unsafe { Self::st() }.ndtr.read().ndt().bits() + unsafe { Self::st() }.ndtr().read().ndt().bits() } #[inline(always)] unsafe fn enable(&mut self) { - Self::st().cr.modify(|_, w| w.en().set_bit()); + Self::st().cr().modify(|_, w| w.en().set_bit()); } #[inline(always)] fn is_enabled(&self) -> bool { - unsafe { Self::st() }.cr.read().en().bit_is_set() + unsafe { Self::st() }.cr().read().en().bit_is_set() } #[inline(always)] unsafe fn disable(&mut self) { - unsafe { Self::st() }.cr.modify(|_, w| w.en().clear_bit()); + unsafe { Self::st() }.cr().modify(|_, w| w.en().clear_bit()); } #[inline(always)] fn set_channel(&mut self, channel: DmaChannel) { unsafe { Self::st() } - .cr - .modify(|_, w| w.chsel().bits(channel.bits())); + .cr() + .modify(|_, w| w.chsel().set(channel.bits())); } #[inline(always)] fn set_priority(&mut self, priority: config::Priority) { unsafe { Self::st() } - .cr - .modify(|_, w| w.pl().bits(priority.bits())); + .cr() + .modify(|_, w| w.pl().set(priority.bits())); } #[inline(always)] fn set_peripheral_increment_offset(&mut self, value: PeripheralIncrementOffset) { unsafe { Self::st() } - .cr + .cr() .modify(|_, w| w.pincos().bit(value.bits())); } #[inline(always)] unsafe fn set_memory_size(&mut self, size: DmaDataSize) { - Self::st().cr.modify(|_, w| w.msize().bits(size.bits())); + Self::st().cr().modify(|_, w| w.msize().bits(size.bits())); } #[inline(always)] unsafe fn set_peripheral_size(&mut self, size: DmaDataSize) { - Self::st().cr.modify(|_, w| w.psize().bits(size.bits())); + Self::st().cr().modify(|_, w| w.psize().bits(size.bits())); } #[inline(always)] fn set_memory_increment(&mut self, increment: bool) { unsafe { Self::st() } - .cr + .cr() .modify(|_, w| w.minc().bit(increment)); } #[inline(always)] fn set_peripheral_increment(&mut self, increment: bool) { unsafe { Self::st() } - .cr + .cr() .modify(|_, w| w.pinc().bit(increment)); } #[inline(always)] fn set_circular_mode(&mut self, value: bool) { - unsafe { Self::st() }.cr.modify(|_, w| w.circ().bit(value)); + unsafe { Self::st() } + .cr() + .modify(|_, w| w.circ().bit(value)); } #[inline(always)] fn set_direction(&mut self, direction: DmaDirection) { unsafe { Self::st() } - .cr + .cr() .modify(|_, w| unsafe { w.dir().bits(direction.bits()) }); } #[inline(always)] fn set_flow_controller(&mut self, value: DmaFlowController) { unsafe { Self::st() } - .cr + .cr() .modify(|_, w| w.pfctrl().bit(value.bits())); } #[inline(always)] fn events(&self) -> BitFlags { - BitFlags::from_bits_truncate(unsafe { Self::st() }.cr.read().bits()) + BitFlags::from_bits_truncate(unsafe { Self::st() }.cr().read().bits()) } #[inline(always)] fn listen_fifo_error(&mut self) { - unsafe { Self::st() }.fcr.modify(|_, w| w.feie().set_bit()); + unsafe { Self::st() } + .fcr() + .modify(|_, w| w.feie().set_bit()); } #[inline(always)] fn unlisten_fifo_error(&mut self) { unsafe { Self::st() } - .fcr + .fcr() .modify(|_, w| w.feie().clear_bit()); } #[inline(always)] fn set_double_buffer(&mut self, double_buffer: bool) { unsafe { Self::st() } - .cr + .cr() .modify(|_, w| w.dbm().bit(double_buffer)); } #[inline(always)] fn set_fifo_threshold(&mut self, fifo_threshold: config::FifoThreshold) { unsafe { Self::st() } - .fcr - .modify(|_, w| w.fth().bits(fifo_threshold.bits())); + .fcr() + .modify(|_, w| w.fth().set(fifo_threshold.bits())); } #[inline(always)] fn set_fifo_enable(&mut self, fifo_enable: bool) { //Register is actually direct mode disable rather than fifo enable unsafe { Self::st() } - .fcr + .fcr() .modify(|_, w| w.dmdis().bit(fifo_enable)); } #[inline(always)] fn set_memory_burst(&mut self, memory_burst: config::BurstMode) { unsafe { Self::st() } - .cr - .modify(|_, w| w.mburst().bits(memory_burst.bits())); + .cr() + .modify(|_, w| w.mburst().set(memory_burst.bits())); } #[inline(always)] fn set_peripheral_burst(&mut self, peripheral_burst: config::BurstMode) { unsafe { Self::st() } - .cr - .modify(|_, w| w.pburst().bits(peripheral_burst.bits())); + .cr() + .modify(|_, w| w.pburst().set(peripheral_burst.bits())); } #[inline(always)] fn fifo_level(&self) -> FifoLevel { - unsafe { Self::st() }.fcr.read().fs().bits().into() + unsafe { Self::st() }.fcr().read().fs().bits().into() } fn current_buffer(&self) -> CurrentBuffer { - if unsafe { Self::st() }.cr.read().ct().bit_is_set() { + if unsafe { Self::st() }.cr().read().ct().bit_is_set() { CurrentBuffer::SecondBuffer } else { CurrentBuffer::FirstBuffer @@ -675,7 +679,7 @@ where enable: Option>, ) { unsafe { - Self::st().cr.modify(|r, w| { + Self::st().cr().modify(|r, w| { w.bits({ let mut bits = r.bits(); if let Some(d) = disable { @@ -704,7 +708,7 @@ macro_rules! dma_stream { #[inline(always)] fn clear_flags(&mut self, flags: impl Into>) { let dma = unsafe { &*I::ptr() }; - dma.$ifcr.write(|w| unsafe { w.bits(flags.into().bits() << $isr_shift) }); + dma.$ifcr().write(|w| unsafe { w.bits(flags.into().bits() << $isr_shift) }); } } @@ -717,7 +721,7 @@ macro_rules! dma_stream { //NOTE(unsafe) Atomic read with no side effects let dma = unsafe { &*I::ptr() }; BitFlags::from_bits_truncate( - ((dma.$isr.read().bits() >> $isr_shift)) + ((dma.$isr().read().bits() >> $isr_shift)) ) } } diff --git a/src/dma/traits.rs b/src/dma/traits.rs index 763abc125..96e9ef718 100644 --- a/src/dma/traits.rs +++ b/src/dma/traits.rs @@ -288,7 +288,7 @@ macro_rules! address { unsafe impl PeriAddress for $peripheral { #[inline(always)] fn address(&self) -> u32 { - self.$register.as_ptr() as u32 + self.$register().as_ptr() as u32 } type MemSize = $size; @@ -377,41 +377,45 @@ dma_map!( address!((pac::SPDIFRX, dr, u32),); #[cfg(feature = "aes")] -pub struct AES_IN(()); +#[non_exhaustive] +pub struct AES_IN; #[cfg(feature = "aes")] -pub struct AES_OUT(()); +#[non_exhaustive] +pub struct AES_OUT; #[cfg(feature = "aes")] unsafe impl PeriAddress for AES_IN { fn address(&self) -> u32 { - unsafe { (*pac::AES::ptr()).dinr.as_ptr() as u32 } + unsafe { (*pac::AES::ptr()).dinr().as_ptr() as u32 } } type MemSize = u32; } #[cfg(feature = "aes")] unsafe impl PeriAddress for AES_OUT { fn address(&self) -> u32 { - unsafe { (*pac::AES::ptr()).doutr.as_ptr() as u32 } + unsafe { (*pac::AES::ptr()).doutr().as_ptr() as u32 } } type MemSize = u32; } #[cfg(feature = "cryp")] -pub struct CRYP_IN(()); +#[non_exhaustive] +pub struct CRYP_IN; #[cfg(feature = "cryp")] -pub struct CRYP_OUT(()); +#[non_exhaustive] +pub struct CRYP_OUT; #[cfg(feature = "cryp")] unsafe impl PeriAddress for CRYP_IN { fn address(&self) -> u32 { - unsafe { (*pac::CRYP::ptr()).din.as_ptr() as u32 } + unsafe { (*pac::CRYP::ptr()).din().as_ptr() as u32 } } type MemSize = u32; } #[cfg(feature = "cryp")] unsafe impl PeriAddress for CRYP_OUT { fn address(&self) -> u32 { - unsafe { (*pac::CRYP::ptr()).dout.as_ptr() as u32 } + unsafe { (*pac::CRYP::ptr()).dout().as_ptr() as u32 } } type MemSize = u32; } diff --git a/src/dma/traits/f4.rs b/src/dma/traits/f4.rs index 8b388cab2..cc74f3fab 100644 --- a/src/dma/traits/f4.rs +++ b/src/dma/traits/f4.rs @@ -390,7 +390,7 @@ mod dfsdm1 { unsafe impl PeriAddress for FLT { #[inline(always)] fn address(&self) -> u32 { - unsafe { (*DFSDM1::ptr()).flt[F as usize].rdatar.as_ptr() as u32 } + unsafe { (*DFSDM1::ptr()).flt(F as usize).rdatar().as_ptr() as u32 } } type MemSize = u32; @@ -412,7 +412,7 @@ dma_map!( unsafe impl PeriAddress for FLT { #[inline(always)] fn address(&self) -> u32 { - unsafe { (*DFSDM2::ptr()).flt[F as usize].rdatar.as_ptr() as u32 } + unsafe { (*DFSDM2::ptr()).flt(F as usize).rdatar().as_ptr() as u32 } } type MemSize = u32; @@ -484,7 +484,7 @@ mod sai1 { unsafe impl PeriAddress for SAICH { #[inline(always)] fn address(&self) -> u32 { - unsafe { (*SAI1::ptr()).ch[C as usize].dr.as_ptr() as u32 } + unsafe { (*SAI1::ptr()).ch(C as usize).dr().as_ptr() as u32 } } type MemSize = u32; @@ -501,7 +501,7 @@ dma_map!( unsafe impl PeriAddress for SAICH { #[inline(always)] fn address(&self) -> u32 { - unsafe { (*pac::SAI2::ptr()).ch[C as usize].dr.as_ptr() as u32 } + unsafe { (*pac::SAI2::ptr()).ch(C as usize).dr().as_ptr() as u32 } } type MemSize = u32; diff --git a/src/flash.rs b/src/flash.rs index a18c6925e..9059f4ad7 100644 --- a/src/flash.rs +++ b/src/flash.rs @@ -18,7 +18,7 @@ pub enum Error { impl Error { fn read(flash: &FLASH) -> Option { - let sr = flash.sr.read(); + let sr = flash.sr().read(); if sr.pgserr().bit() { Some(Error::ProgrammingSequence) } else if sr.pgperr().bit() { @@ -84,7 +84,7 @@ impl FlashExt for FLASH { )) { // DB1M bit is not present in all SVDs // self.optcr.read().db1m().bit_is_set() - self.optcr.read().bits() & (1 << 30) != 0 + self.optcr().read().bits() & (1 << 30) != 0 } else { false } @@ -197,17 +197,16 @@ impl UnlockedFlash<'_> { let snb = if sector < 12 { sector } else { sector + 4 }; #[rustfmt::skip] - self.flash.cr.modify(|_, w| unsafe { - w - // start - .strt().set_bit() - .psize().bits(PSIZE_X8) - // sector number - .snb().bits(snb) - // sectore erase - .ser().set_bit() - // no programming - .pg().clear_bit() + self.flash.cr().modify(|_, w| unsafe { + // start + w.strt().set_bit(); + w.psize().bits(PSIZE_X8); + // sector number + w.snb().bits(snb); + // sectore erase + w.ser().set_bit(); + // no programming + w.pg().clear_bit() }); self.wait_ready(); self.ok() @@ -227,13 +226,12 @@ impl UnlockedFlash<'_> { #[rustfmt::skip] #[allow(unused_unsafe)] - self.flash.cr.modify(|_, w| unsafe { - w - .psize().bits(PSIZE_X8) - // no sector erase - .ser().clear_bit() - // programming - .pg().set_bit() + self.flash.cr().modify(|_, w| unsafe { + w.psize().bits(PSIZE_X8); + // no sector erase + w.ser().clear_bit(); + // programming + w.pg().set_bit() }); for _ in 0..amount { match bytes.next() { @@ -250,7 +248,7 @@ impl UnlockedFlash<'_> { self.wait_ready(); self.ok()?; } - self.flash.cr.modify(|_, w| w.pg().clear_bit()); + self.flash.cr().modify(|_, w| w.pg().clear_bit()); Ok(()) } @@ -260,7 +258,7 @@ impl UnlockedFlash<'_> { } fn wait_ready(&self) { - while self.flash.sr.read().bsy().bit() {} + while self.flash.sr().read().bsy().bit() {} } } @@ -269,13 +267,13 @@ const UNLOCK_KEY2: u32 = 0xCDEF89AB; #[allow(unused_unsafe)] fn unlock(flash: &FLASH) { - flash.keyr.write(|w| unsafe { w.key().bits(UNLOCK_KEY1) }); - flash.keyr.write(|w| unsafe { w.key().bits(UNLOCK_KEY2) }); - assert!(!flash.cr.read().lock().bit()) + flash.keyr().write(|w| unsafe { w.key().bits(UNLOCK_KEY1) }); + flash.keyr().write(|w| unsafe { w.key().bits(UNLOCK_KEY2) }); + assert!(!flash.cr().read().lock().bit()) } fn lock(flash: &FLASH) { - flash.cr.modify(|_, w| w.lock().set_bit()); + flash.cr().modify(|_, w| w.lock().set_bit()); } /// Flash memory sector diff --git a/src/fmpi2c.rs b/src/fmpi2c.rs index 80f5d894e..849f3fe75 100644 --- a/src/fmpi2c.rs +++ b/src/fmpi2c.rs @@ -22,7 +22,7 @@ impl Instance for FMPI2C1 { FMPI2C1::ptr() as *const _ } fn clock_hsi(rcc: &crate::pac::rcc::RegisterBlock) { - rcc.dckcfgr2.modify(|_, w| w.fmpi2c1sel().hsi()); + rcc.dckcfgr2().modify(|_, w| w.fmpi2c1sel().hsi()); } } @@ -112,7 +112,7 @@ impl FMPI2c { use core::cmp; // Make sure the I2C unit is disabled so we can configure it - self.i2c.cr1.modify(|_, w| w.pe().clear_bit()); + self.i2c.cr1().modify(|_, w| w.pe().clear_bit()); // Calculate settings for I2C speed modes let presc; @@ -151,28 +151,23 @@ impl FMPI2c { } // Enable I2C signal generator, and configure I2C for configured speed - self.i2c.timingr.write(|w| { - w.presc() - .bits(presc) - .scldel() - .bits(scldel) - .sdadel() - .bits(sdadel) - .sclh() - .bits(sclh) - .scll() - .bits(scll) + self.i2c.timingr().write(|w| { + w.presc().set(presc); + w.scldel().set(scldel); + w.sdadel().set(sdadel); + w.sclh().set(sclh); + w.scll().set(scll) }); // Enable the I2C processing - self.i2c.cr1.modify(|_, w| w.pe().set_bit()); + self.i2c.cr1().modify(|_, w| w.pe().set_bit()); } fn check_and_clear_error_flags(&self, isr: &fmpi2c1::isr::R) -> Result<(), Error> { // If we received a NACK, then this is an error if isr.nackf().bit_is_set() { self.i2c - .icr + .icr() .write(|w| w.stopcf().set_bit().nackcf().set_bit()); return Err(Error::NoAcknowledge(NoAcknowledgeSource::Unknown)); } @@ -182,7 +177,7 @@ impl FMPI2c { fn end_transaction(&self) -> Result<(), Error> { // Check and clear flags if they somehow ended up set - self.check_and_clear_error_flags(&self.i2c.isr.read()) + self.check_and_clear_error_flags(&self.i2c.isr().read()) .map_err(Error::nack_data)?; Ok(()) } @@ -190,46 +185,45 @@ impl FMPI2c { fn send_byte(&self, byte: u8) -> Result<(), Error> { // Wait until we're ready for sending while { - let isr = self.i2c.isr.read(); + let isr = self.i2c.isr().read(); self.check_and_clear_error_flags(&isr) .map_err(Error::nack_addr)?; isr.txis().bit_is_clear() } {} // Push out a byte of data - self.i2c.txdr.write(|w| unsafe { w.bits(u32::from(byte)) }); + self.i2c + .txdr() + .write(|w| unsafe { w.bits(u32::from(byte)) }); self.end_transaction() } fn recv_byte(&self) -> Result { while { - let isr = self.i2c.isr.read(); + let isr = self.i2c.isr().read(); self.check_and_clear_error_flags(&isr) .map_err(Error::nack_data)?; isr.rxne().bit_is_clear() } {} - let value = self.i2c.rxdr.read().bits() as u8; + let value = self.i2c.rxdr().read().bits() as u8; Ok(value) } pub fn read(&mut self, addr: u8, buffer: &mut [u8]) -> Result<(), Error> { // Set up current address for reading - self.i2c.cr2.modify(|_, w| { - w.sadd() - .bits(u16::from(addr) << 1) - .nbytes() - .bits(buffer.len() as u8) - .rd_wrn() - .set_bit() + self.i2c.cr2().modify(|_, w| { + w.sadd().set(u16::from(addr) << 1); + w.nbytes().set(buffer.len() as u8); + w.rd_wrn().set_bit() }); // Send a START condition - self.i2c.cr2.modify(|_, w| w.start().set_bit()); + self.i2c.cr2().modify(|_, w| w.start().set_bit()); // Send the autoend after setting the start to get a restart - self.i2c.cr2.modify(|_, w| w.autoend().set_bit()); + self.i2c.cr2().modify(|_, w| w.autoend().set_bit()); // Now read in all bytes for c in buffer.iter_mut() { @@ -241,19 +235,15 @@ impl FMPI2c { pub fn write(&mut self, addr: u8, bytes: &[u8]) -> Result<(), Error> { // Set up current slave address for writing and enable autoending - self.i2c.cr2.modify(|_, w| { - w.sadd() - .bits(u16::from(addr) << 1) - .nbytes() - .bits(bytes.len() as u8) - .rd_wrn() - .clear_bit() - .autoend() - .set_bit() + self.i2c.cr2().modify(|_, w| { + w.sadd().set(u16::from(addr) << 1); + w.nbytes().set(bytes.len() as u8); + w.rd_wrn().clear_bit(); + w.autoend().set_bit() }); // Send a START condition - self.i2c.cr2.modify(|_, w| w.start().set_bit()); + self.i2c.cr2().modify(|_, w| w.start().set_bit()); // Send out all individual bytes for c in bytes { @@ -265,23 +255,19 @@ impl FMPI2c { pub fn write_read(&mut self, addr: u8, bytes: &[u8], buffer: &mut [u8]) -> Result<(), Error> { // Set up current slave address for writing and disable autoending - self.i2c.cr2.modify(|_, w| { - w.sadd() - .bits(u16::from(addr) << 1) - .nbytes() - .bits(bytes.len() as u8) - .rd_wrn() - .clear_bit() - .autoend() - .clear_bit() + self.i2c.cr2().modify(|_, w| { + w.sadd().set(u16::from(addr) << 1); + w.nbytes().set(bytes.len() as u8); + w.rd_wrn().clear_bit(); + w.autoend().clear_bit() }); // Send a START condition - self.i2c.cr2.modify(|_, w| w.start().set_bit()); + self.i2c.cr2().modify(|_, w| w.start().set_bit()); // Wait until the transmit buffer is empty and there hasn't been any error condition while { - let isr = self.i2c.isr.read(); + let isr = self.i2c.isr().read(); self.check_and_clear_error_flags(&isr) .map_err(Error::nack_addr)?; isr.txis().bit_is_clear() && isr.tc().bit_is_clear() @@ -294,27 +280,24 @@ impl FMPI2c { // Wait until data was sent while { - let isr = self.i2c.isr.read(); + let isr = self.i2c.isr().read(); self.check_and_clear_error_flags(&isr) .map_err(Error::nack_data)?; isr.tc().bit_is_clear() } {} // Set up current address for reading - self.i2c.cr2.modify(|_, w| { - w.sadd() - .bits(u16::from(addr) << 1) - .nbytes() - .bits(buffer.len() as u8) - .rd_wrn() - .set_bit() + self.i2c.cr2().modify(|_, w| { + w.sadd().set(u16::from(addr) << 1); + w.nbytes().set(buffer.len() as u8); + w.rd_wrn().set_bit() }); // Send another START condition - self.i2c.cr2.modify(|_, w| w.start().set_bit()); + self.i2c.cr2().modify(|_, w| w.start().set_bit()); // Send the autoend after setting the start to get a restart - self.i2c.cr2.modify(|_, w| w.autoend().set_bit()); + self.i2c.cr2().modify(|_, w| w.autoend().set_bit()); // Now read in all bytes for c in buffer.iter_mut() { diff --git a/src/fsmc_lcd/mod.rs b/src/fsmc_lcd/mod.rs index ecf0244c7..5c96d7f0b 100644 --- a/src/fsmc_lcd/mod.rs +++ b/src/fsmc_lcd/mod.rs @@ -83,25 +83,29 @@ use crate::pac::FSMC; /// A sub-bank of bank 1, with its own chip select output pub trait SubBank: sealed::SealedSubBank {} /// Sub-bank 1 -pub struct SubBank1(()); +#[non_exhaustive] +pub struct SubBank1; impl sealed::SealedSubBank for SubBank1 { const BASE_ADDRESS: usize = 0x6000_0000; } impl SubBank for SubBank1 {} /// Sub-bank 2 -pub struct SubBank2(()); +#[non_exhaustive] +pub struct SubBank2; impl sealed::SealedSubBank for SubBank2 { const BASE_ADDRESS: usize = 0x6400_0000; } impl SubBank for SubBank2 {} /// Sub-bank 3 -pub struct SubBank3(()); +#[non_exhaustive] +pub struct SubBank3; impl sealed::SealedSubBank for SubBank3 { const BASE_ADDRESS: usize = 0x6800_0000; } impl SubBank for SubBank3 {} /// Sub-bank 4 -pub struct SubBank4(()); +#[non_exhaustive] +pub struct SubBank4; impl sealed::SealedSubBank for SubBank4 { const BASE_ADDRESS: usize = 0x6c00_0000; } @@ -115,14 +119,14 @@ pub struct FsmcLcd { } pub trait Word { - const MWID: fsmc::bcr1::MWID_A; + const MWID: fsmc::bcr1::MWID; } impl Word for u8 { - const MWID: fsmc::bcr1::MWID_A = fsmc::bcr1::MWID_A::Bits8; + const MWID: fsmc::bcr1::MWID = fsmc::bcr1::MWID::Bits8; } impl Word for u16 { - const MWID: fsmc::bcr1::MWID_A = fsmc::bcr1::MWID_A::Bits8; + const MWID: fsmc::bcr1::MWID = fsmc::bcr1::MWID::Bits8; } impl FsmcLcd @@ -225,18 +229,18 @@ where // and sub-banks of bank 1. This driver uses addresses in the different sub-banks of // bank 1. The configuration registers for "bank x" (like FMC_BCRx) actually refer to // sub-banks, not banks. We need to configure and enable all four of them. - configure_bcr1::(&fsmc.bcr1); - configure_bcr(&fsmc.bcr2); - configure_bcr(&fsmc.bcr3); - configure_bcr(&fsmc.bcr4); - configure_btr(&fsmc.btr1, read_timing); - configure_btr(&fsmc.btr2, read_timing); - configure_btr(&fsmc.btr3, read_timing); - configure_btr(&fsmc.btr4, read_timing); - configure_bwtr(&fsmc.bwtr1, write_timing); - configure_bwtr(&fsmc.bwtr2, write_timing); - configure_bwtr(&fsmc.bwtr3, write_timing); - configure_bwtr(&fsmc.bwtr4, write_timing); + configure_bcr1::(fsmc.bcr1()); + configure_bcr(fsmc.bcr2()); + configure_bcr(fsmc.bcr3()); + configure_bcr(fsmc.bcr4()); + configure_btr(fsmc.btr1(), read_timing); + configure_btr(fsmc.btr2(), read_timing); + configure_btr(fsmc.btr3(), read_timing); + configure_btr(fsmc.btr4(), read_timing); + configure_bwtr(fsmc.bwtr1(), write_timing); + configure_bwtr(fsmc.bwtr2(), write_timing); + configure_bwtr(fsmc.bwtr3(), write_timing); + configure_bwtr(fsmc.bwtr4(), write_timing); ( FsmcLcd { diff --git a/src/fsmc_lcd/timing.rs b/src/fsmc_lcd/timing.rs index 77acf8a26..2af4a1407 100644 --- a/src/fsmc_lcd/timing.rs +++ b/src/fsmc_lcd/timing.rs @@ -15,22 +15,22 @@ pub enum AccessMode { } impl AccessMode { - pub(crate) fn as_read_variant(&self) -> fsmc::btr::ACCMOD_A { - use fsmc::btr::ACCMOD_A; + pub(crate) fn as_read_variant(&self) -> fsmc::btr::ACCMOD { + use fsmc::btr::ACCMOD; match *self { - AccessMode::ModeA => ACCMOD_A::A, - AccessMode::ModeB => ACCMOD_A::B, - AccessMode::ModeC => ACCMOD_A::C, - AccessMode::ModeD => ACCMOD_A::D, + AccessMode::ModeA => ACCMOD::A, + AccessMode::ModeB => ACCMOD::B, + AccessMode::ModeC => ACCMOD::C, + AccessMode::ModeD => ACCMOD::D, } } - pub(crate) fn as_write_variant(&self) -> fsmc::bwtr::ACCMOD_A { - use fsmc::bwtr::ACCMOD_A; + pub(crate) fn as_write_variant(&self) -> fsmc::bwtr::ACCMOD { + use fsmc::bwtr::ACCMOD; match *self { - AccessMode::ModeA => ACCMOD_A::A, - AccessMode::ModeB => ACCMOD_A::B, - AccessMode::ModeC => ACCMOD_A::C, - AccessMode::ModeD => ACCMOD_A::D, + AccessMode::ModeA => ACCMOD::A, + AccessMode::ModeB => ACCMOD::B, + AccessMode::ModeC => ACCMOD::C, + AccessMode::ModeD => ACCMOD::D, } } } diff --git a/src/gpio.rs b/src/gpio.rs index c5664f0d5..2fa1a4a0e 100644 --- a/src/gpio.rs +++ b/src/gpio.rs @@ -322,7 +322,7 @@ where unsafe { (*gpiox::

()) - .ospeedr + .ospeedr() .modify(|r, w| w.bits((r.bits() & !(0b11 << offset)) | ((speed as u32) << offset))); } } @@ -354,7 +354,7 @@ where let value = resistor as u32; unsafe { (*gpiox::

()) - .pupdr + .pupdr() .modify(|r, w| w.bits((r.bits() & !(0b11 << offset)) | (value << offset))); } } @@ -435,22 +435,22 @@ impl Pin { #[inline(always)] fn _set_high(&mut self) { // NOTE(unsafe) atomic write to a stateless register - unsafe { (*gpiox::

()).bsrr.write(|w| w.bits(1 << N)) } + unsafe { (*gpiox::

()).bsrr().write(|w| w.bits(1 << N)) } } #[inline(always)] fn _set_low(&mut self) { // NOTE(unsafe) atomic write to a stateless register - unsafe { (*gpiox::

()).bsrr.write(|w| w.bits(1 << (16 + N))) } + unsafe { (*gpiox::

()).bsrr().write(|w| w.bits(1 << (16 + N))) } } #[inline(always)] fn _is_set_low(&self) -> bool { // NOTE(unsafe) atomic read with no side effects - unsafe { (*gpiox::

()).odr.read().bits() & (1 << N) == 0 } + unsafe { (*gpiox::

()).odr().read().bits() & (1 << N) == 0 } } #[inline(always)] fn _is_low(&self) -> bool { // NOTE(unsafe) atomic read with no side effects - unsafe { (*gpiox::

()).idr.read().bits() & (1 << N) == 0 } + unsafe { (*gpiox::

()).idr().read().bits() & (1 << N) == 0 } } } diff --git a/src/gpio/convert.rs b/src/gpio/convert.rs index 1d354e4e1..caa3a5e9b 100644 --- a/src/gpio/convert.rs +++ b/src/gpio/convert.rs @@ -115,7 +115,7 @@ macro_rules! change_mode { if MODE::OTYPER != M::OTYPER { if let Some(otyper) = M::OTYPER { $block - .otyper + .otyper() .modify(|r, w| w.bits(r.bits() & !(0b1 << $N) | (otyper << $N))); } } @@ -124,12 +124,12 @@ macro_rules! change_mode { if let Some(afr) = M::AFR { if $N < 8 { let offset2 = 4 * { $N }; - $block.afrl.modify(|r, w| { + $block.afrl().modify(|r, w| { w.bits((r.bits() & !(0b1111 << offset2)) | (afr << offset2)) }); } else { let offset2 = 4 * { $N - 8 }; - $block.afrh.modify(|r, w| { + $block.afrh().modify(|r, w| { w.bits((r.bits() & !(0b1111 << offset2)) | (afr << offset2)) }); } @@ -138,7 +138,7 @@ macro_rules! change_mode { if MODE::MODER != M::MODER { $block - .moder + .moder() .modify(|r, w| w.bits((r.bits() & !(0b11 << offset)) | (M::MODER << offset))); } } diff --git a/src/gpio/erased.rs b/src/gpio/erased.rs index 9f2466685..67df83974 100644 --- a/src/gpio/erased.rs +++ b/src/gpio/erased.rs @@ -98,7 +98,7 @@ impl ErasedPin> { #[inline(always)] pub fn set_high(&mut self) { // NOTE(unsafe) atomic write to a stateless register - unsafe { self.block().bsrr.write(|w| w.bits(1 << self.pin_id())) }; + unsafe { self.block().bsrr().write(|w| w.bits(1 << self.pin_id())) }; } /// Drives the pin low @@ -107,7 +107,7 @@ impl ErasedPin> { // NOTE(unsafe) atomic write to a stateless register unsafe { self.block() - .bsrr + .bsrr() .write(|w| w.bits(1 << (self.pin_id() + 16))) }; } @@ -140,7 +140,7 @@ impl ErasedPin> { /// Is the pin in drive low mode? #[inline(always)] pub fn is_set_low(&self) -> bool { - self.block().odr.read().bits() & (1 << self.pin_id()) == 0 + self.block().odr().read().bits() & (1 << self.pin_id()) == 0 } /// Toggle pin output @@ -167,6 +167,6 @@ where /// Is the input pin low? #[inline(always)] pub fn is_low(&self) -> bool { - self.block().idr.read().bits() & (1 << self.pin_id()) == 0 + self.block().idr().read().bits() & (1 << self.pin_id()) == 0 } } diff --git a/src/gpio/exti.rs b/src/gpio/exti.rs index 6acaaa77a..f3efe9ee0 100644 --- a/src/gpio/exti.rs +++ b/src/gpio/exti.rs @@ -56,22 +56,22 @@ where let offset = 4 * (i % 4); match i { 0..=3 => { - syscfg.exticr1.modify(|r, w| unsafe { + syscfg.exticr1().modify(|r, w| unsafe { w.bits((r.bits() & !(0xf << offset)) | (port << offset)) }); } 4..=7 => { - syscfg.exticr2.modify(|r, w| unsafe { + syscfg.exticr2().modify(|r, w| unsafe { w.bits((r.bits() & !(0xf << offset)) | (port << offset)) }); } 8..=11 => { - syscfg.exticr3.modify(|r, w| unsafe { + syscfg.exticr3().modify(|r, w| unsafe { w.bits((r.bits() & !(0xf << offset)) | (port << offset)) }); } 12..=15 => { - syscfg.exticr4.modify(|r, w| unsafe { + syscfg.exticr4().modify(|r, w| unsafe { w.bits((r.bits() & !(0xf << offset)) | (port << offset)) }); } @@ -84,21 +84,21 @@ where let i = self.pin_id(); match edge { Edge::Rising => { - exti.rtsr + exti.rtsr() .modify(|r, w| unsafe { w.bits(r.bits() | (1 << i)) }); - exti.ftsr + exti.ftsr() .modify(|r, w| unsafe { w.bits(r.bits() & !(1 << i)) }); } Edge::Falling => { - exti.ftsr + exti.ftsr() .modify(|r, w| unsafe { w.bits(r.bits() | (1 << i)) }); - exti.rtsr + exti.rtsr() .modify(|r, w| unsafe { w.bits(r.bits() & !(1 << i)) }); } Edge::RisingFalling => { - exti.rtsr + exti.rtsr() .modify(|r, w| unsafe { w.bits(r.bits() | (1 << i)) }); - exti.ftsr + exti.ftsr() .modify(|r, w| unsafe { w.bits(r.bits() | (1 << i)) }); } } @@ -106,23 +106,23 @@ where #[inline(always)] fn enable_interrupt(&mut self, exti: &mut EXTI) { - exti.imr + exti.imr() .modify(|r, w| unsafe { w.bits(r.bits() | (1 << self.pin_id())) }); } #[inline(always)] fn disable_interrupt(&mut self, exti: &mut EXTI) { - exti.imr + exti.imr() .modify(|r, w| unsafe { w.bits(r.bits() & !(1 << self.pin_id())) }); } #[inline(always)] fn clear_interrupt_pending_bit(&mut self) { - unsafe { (*EXTI::ptr()).pr.write(|w| w.bits(1 << self.pin_id())) }; + unsafe { (*EXTI::ptr()).pr().write(|w| w.bits(1 << self.pin_id())) }; } #[inline(always)] fn check_interrupt(&self) -> bool { - unsafe { ((*EXTI::ptr()).pr.read().bits() & (1 << self.pin_id())) != 0 } + unsafe { ((*EXTI::ptr()).pr().read().bits() & (1 << self.pin_id())) != 0 } } } diff --git a/src/gpio/outport.rs b/src/gpio/outport.rs index ef4691e4c..e164b5b9a 100644 --- a/src/gpio/outport.rs +++ b/src/gpio/outport.rs @@ -31,17 +31,17 @@ macro_rules! out_port { #[doc=concat!("Set/reset pins according to `", $n, "` lower bits")] #[inline(never)] pub fn write(&mut self, word: u32) { - unsafe { (*gpiox::

()).bsrr.write(|w| w.bits(Self::value_for_write_bsrr(word))) } + unsafe { (*gpiox::

()).bsrr().write(|w| w.bits(Self::value_for_write_bsrr(word))) } } /// Set all pins to `PinState::High` pub fn all_high(&mut self) { - unsafe { (*gpiox::

()).bsrr.write(|w| w.bits(Self::mask())) } + unsafe { (*gpiox::

()).bsrr().write(|w| w.bits(Self::mask())) } } /// Reset all pins to `PinState::Low` pub fn all_low(&mut self) { - unsafe { (*gpiox::

()).bsrr.write(|w| w.bits(Self::mask() << 16)) } + unsafe { (*gpiox::

()).bsrr().write(|w| w.bits(Self::mask() << 16)) } } } } @@ -87,18 +87,18 @@ impl OutPortArray { pub fn write(&mut self, word: u32) { unsafe { (*gpiox::

()) - .bsrr + .bsrr() .write(|w| w.bits(self.value_for_write_bsrr(word))) } } /// Set all pins to `PinState::High` pub fn all_high(&mut self) { - unsafe { (*gpiox::

()).bsrr.write(|w| w.bits(self.mask())) } + unsafe { (*gpiox::

()).bsrr().write(|w| w.bits(self.mask())) } } /// Reset all pins to `PinState::Low` pub fn all_low(&mut self) { - unsafe { (*gpiox::

()).bsrr.write(|w| w.bits(self.mask() << 16)) } + unsafe { (*gpiox::

()).bsrr().write(|w| w.bits(self.mask() << 16)) } } } diff --git a/src/gpio/partially_erased.rs b/src/gpio/partially_erased.rs index 4298120a7..4a2b624b8 100644 --- a/src/gpio/partially_erased.rs +++ b/src/gpio/partially_erased.rs @@ -68,14 +68,14 @@ impl PartiallyErasedPin> { #[inline(always)] pub fn set_high(&mut self) { // NOTE(unsafe) atomic write to a stateless register - unsafe { (*gpiox::

()).bsrr.write(|w| w.bits(1 << self.i)) } + unsafe { (*gpiox::

()).bsrr().write(|w| w.bits(1 << self.i)) } } /// Drives the pin low #[inline(always)] pub fn set_low(&mut self) { // NOTE(unsafe) atomic write to a stateless register - unsafe { (*gpiox::

()).bsrr.write(|w| w.bits(1 << (self.i + 16))) } + unsafe { (*gpiox::

()).bsrr().write(|w| w.bits(1 << (self.i + 16))) } } /// Is the pin in drive high or low mode? @@ -107,7 +107,7 @@ impl PartiallyErasedPin> { #[inline(always)] pub fn is_set_low(&self) -> bool { // NOTE(unsafe) atomic read with no side effects - unsafe { (*gpiox::

()).odr.read().bits() & (1 << self.i) == 0 } + unsafe { (*gpiox::

()).odr().read().bits() & (1 << self.i) == 0 } } /// Toggle pin output @@ -135,7 +135,7 @@ where #[inline(always)] pub fn is_low(&self) -> bool { // NOTE(unsafe) atomic read with no side effects - unsafe { (*gpiox::

()).idr.read().bits() & (1 << self.i) == 0 } + unsafe { (*gpiox::

()).idr().read().bits() & (1 << self.i) == 0 } } } diff --git a/src/i2c.rs b/src/i2c.rs index c9db4ad16..92c014ed2 100644 --- a/src/i2c.rs +++ b/src/i2c.rs @@ -181,7 +181,7 @@ impl I2c { fn i2c_init(&self, mode: impl Into, pclk: Hertz) { let mode = mode.into(); // Make sure the I2C unit is disabled so we can configure it - self.i2c.cr1.modify(|_, w| w.pe().clear_bit()); + self.i2c.cr1().modify(|_, w| w.pe().clear_bit()); // Calculate settings for I2C speed modes let clock = pclk.raw(); @@ -190,7 +190,7 @@ impl I2c { // Configure bus frequency into I2C peripheral self.i2c - .cr2 + .cr2() .write(|w| unsafe { w.freq().bits(clc_mhz as u8) }); let trise = match mode { @@ -199,7 +199,7 @@ impl I2c { }; // Configure correct rise times - self.i2c.trise.write(|w| w.trise().bits(trise as u8)); + self.i2c.trise().write(|w| w.trise().set(trise as u8)); match mode { // I2C clock control calculation @@ -207,13 +207,10 @@ impl I2c { let ccr = (clock / (frequency.raw() * 2)).max(4); // Set clock to standard mode with appropriate parameters for selected speed - self.i2c.ccr.write(|w| unsafe { - w.f_s() - .clear_bit() - .duty() - .clear_bit() - .ccr() - .bits(ccr as u16) + self.i2c.ccr().write(|w| unsafe { + w.f_s().clear_bit(); + w.duty().clear_bit(); + w.ccr().bits(ccr as u16) }); } Mode::Fast { @@ -224,7 +221,7 @@ impl I2c { let ccr = (clock / (frequency.raw() * 3)).max(1); // Set clock to fast mode with appropriate parameters for selected speed (2:1 duty cycle) - self.i2c.ccr.write(|w| unsafe { + self.i2c.ccr().write(|w| unsafe { w.f_s().set_bit().duty().clear_bit().ccr().bits(ccr as u16) }); } @@ -232,7 +229,7 @@ impl I2c { let ccr = (clock / (frequency.raw() * 25)).max(1); // Set clock to fast mode with appropriate parameters for selected speed (16:9 duty cycle) - self.i2c.ccr.write(|w| unsafe { + self.i2c.ccr().write(|w| unsafe { w.f_s().set_bit().duty().set_bit().ccr().bits(ccr as u16) }); } @@ -240,43 +237,43 @@ impl I2c { } // Enable the I2C processing - self.i2c.cr1.modify(|_, w| w.pe().set_bit()); + self.i2c.cr1().modify(|_, w| w.pe().set_bit()); } fn check_and_clear_error_flags(&self) -> Result { // Note that flags should only be cleared once they have been registered. If flags are // cleared otherwise, there may be an inherent race condition and flags may be missed. - let sr1 = self.i2c.sr1.read(); + let sr1 = self.i2c.sr1().read(); if sr1.timeout().bit_is_set() { - self.i2c.sr1.modify(|_, w| w.timeout().clear_bit()); + self.i2c.sr1().modify(|_, w| w.timeout().clear_bit()); return Err(Error::Timeout); } if sr1.pecerr().bit_is_set() { - self.i2c.sr1.modify(|_, w| w.pecerr().clear_bit()); + self.i2c.sr1().modify(|_, w| w.pecerr().clear_bit()); return Err(Error::Crc); } if sr1.ovr().bit_is_set() { - self.i2c.sr1.modify(|_, w| w.ovr().clear_bit()); + self.i2c.sr1().modify(|_, w| w.ovr().clear_bit()); return Err(Error::Overrun); } if sr1.af().bit_is_set() { - self.i2c.sr1.modify(|_, w| w.af().clear_bit()); + self.i2c.sr1().modify(|_, w| w.af().clear_bit()); return Err(Error::NoAcknowledge(NoAcknowledgeSource::Unknown)); } if sr1.arlo().bit_is_set() { - self.i2c.sr1.modify(|_, w| w.arlo().clear_bit()); + self.i2c.sr1().modify(|_, w| w.arlo().clear_bit()); return Err(Error::ArbitrationLoss); } // The errata indicates that BERR may be incorrectly detected. It recommends ignoring and // clearing the BERR bit instead. if sr1.berr().bit_is_set() { - self.i2c.sr1.modify(|_, w| w.berr().clear_bit()); + self.i2c.sr1().modify(|_, w| w.berr().clear_bit()); } Ok(sr1) @@ -291,10 +288,10 @@ impl I2c { // It is possible that the STOP condition is still being generated // when we reach here, so we wait until it finishes before proceeding // to start a new transaction. - while self.i2c.cr1.read().stop().bit_is_set() {} + while self.i2c.cr1().read().stop().bit_is_set() {} // Send a START condition - self.i2c.cr1.modify(|_, w| w.start().set_bit()); + self.i2c.cr1().modify(|_, w| w.start().set_bit()); // Wait until START condition was generated while self.check_and_clear_error_flags()?.sb().bit_is_clear() {} @@ -303,7 +300,7 @@ impl I2c { loop { self.check_and_clear_error_flags()?; - let sr2 = self.i2c.sr2.read(); + let sr2 = self.i2c.sr2().read(); if !(sr2.msl().bit_is_clear() && sr2.busy().bit_is_clear()) { break; } @@ -311,7 +308,7 @@ impl I2c { // Set up current address, we're trying to talk to self.i2c - .dr + .dr() .write(|w| unsafe { w.bits(u32::from(addr) << 1) }); // Wait until address was sent @@ -328,7 +325,7 @@ impl I2c { } // Clear condition by reading SR2 - self.i2c.sr2.read(); + self.i2c.sr2().read(); Ok(()) } @@ -341,38 +338,38 @@ impl I2c { // It is possible that the STOP condition is still being generated // when we reach here, so we wait until it finishes before proceeding // to start a new transaction. - while self.i2c.cr1.read().stop().bit_is_set() {} + while self.i2c.cr1().read().stop().bit_is_set() {} // Send a START condition and set ACK bit self.i2c - .cr1 + .cr1() .modify(|_, w| w.start().set_bit().ack().set_bit()); // Wait until START condition was generated - while self.i2c.sr1.read().sb().bit_is_clear() {} + while self.i2c.sr1().read().sb().bit_is_clear() {} // Also wait until signalled we're master and everything is waiting for us while { - let sr2 = self.i2c.sr2.read(); + let sr2 = self.i2c.sr2().read(); sr2.msl().bit_is_clear() && sr2.busy().bit_is_clear() } {} // Set up current address, we're trying to talk to self.i2c - .dr + .dr() .write(|w| unsafe { w.bits((u32::from(addr) << 1) + 1) }); // Wait until address was sent loop { self.check_and_clear_error_flags() .map_err(Error::nack_addr)?; - if self.i2c.sr1.read().addr().bit_is_set() { + if self.i2c.sr1().read().addr().bit_is_set() { break; } } // Clear condition by reading SR2 - self.i2c.sr2.read(); + self.i2c.sr2().read(); Ok(()) } @@ -398,7 +395,7 @@ impl I2c { {} // Push out a byte of data - self.i2c.dr.write(|w| unsafe { w.bits(u32::from(byte)) }); + self.i2c.dr().write(|w| unsafe { w.bits(u32::from(byte)) }); // Wait until byte is transferred // Check for any potential error conditions. @@ -418,12 +415,12 @@ impl I2c { self.check_and_clear_error_flags() .map_err(Error::nack_data)?; - if self.i2c.sr1.read().rx_ne().bit_is_set() { + if self.i2c.sr1().read().rx_ne().bit_is_set() { break; } } - let value = self.i2c.dr.read().bits() as u8; + let value = self.i2c.dr().read().bits() as u8; Ok(value) } @@ -453,7 +450,7 @@ impl I2c { // Prepare to send NACK then STOP after next byte self.i2c - .cr1 + .cr1() .modify(|_, w| w.ack().clear_bit().stop().set_bit()); // Receive last byte @@ -464,7 +461,7 @@ impl I2c { // operations through the DMA handle might thus encounter `WouldBlock` // error. Instead, we should make sure that the interface becomes idle // before returning. - while self.i2c.cr1.read().stop().bit_is_set() {} + while self.i2c.cr1().read().stop().bit_is_set() {} // Fallthrough is success Ok(()) @@ -483,14 +480,14 @@ impl I2c { self.write_bytes(bytes.iter().cloned())?; // Send a STOP condition - self.i2c.cr1.modify(|_, w| w.stop().set_bit()); + self.i2c.cr1().modify(|_, w| w.stop().set_bit()); // Wait for the STOP to be sent. Otherwise, the interface will still be // busy for a while after this function returns. Immediate following // operations through the DMA handle might thus encounter `WouldBlock` // error. Instead, we should make sure that the interface becomes idle // before returning. - while self.i2c.cr1.read().stop().bit_is_set() {} + while self.i2c.cr1().read().stop().bit_is_set() {} // Fallthrough is success Ok(()) @@ -504,14 +501,14 @@ impl I2c { self.write_bytes(bytes.into_iter())?; // Send a STOP condition - self.i2c.cr1.modify(|_, w| w.stop().set_bit()); + self.i2c.cr1().modify(|_, w| w.stop().set_bit()); // Wait for the STOP to be sent. Otherwise, the interface will still be // busy for a while after this function returns. Immediate following // operations through the DMA handle might thus encounter `WouldBlock` // error. Instead, we should make sure that the interface becomes idle // before returning. - while self.i2c.cr1.read().stop().bit_is_set() {} + while self.i2c.cr1().read().stop().bit_is_set() {} // Fallthrough is success Ok(()) diff --git a/src/i2c/dma.rs b/src/i2c/dma.rs index f34eb7faa..16918b5ef 100644 --- a/src/i2c/dma.rs +++ b/src/i2c/dma.rs @@ -389,7 +389,7 @@ where /// Checks if there is communication in progress #[inline(always)] pub fn busy(&self) -> bool { - self.hal_i2c.i2c.sr2.read().busy().bit_is_set() + self.hal_i2c.i2c.sr2().read().busy().bit_is_set() } /// Like `busy` but returns `WouldBlock` if busy @@ -402,22 +402,22 @@ where #[inline(always)] fn enable_dma_requests(&mut self) { - self.hal_i2c.i2c.cr2.modify(|_, w| w.dmaen().enabled()); + self.hal_i2c.i2c.cr2().modify(|_, w| w.dmaen().enabled()); } #[inline(always)] fn disable_dma_requests(&mut self) { - self.hal_i2c.i2c.cr2.modify(|_, w| w.dmaen().disabled()); + self.hal_i2c.i2c.cr2().modify(|_, w| w.dmaen().disabled()); } #[inline(always)] fn enable_error_interrupt_generation(&mut self) { - self.hal_i2c.i2c.cr2.modify(|_, w| w.iterren().enabled()); + self.hal_i2c.i2c.cr2().modify(|_, w| w.iterren().enabled()); } #[inline(always)] fn disable_error_interrupt_generation(&mut self) { - self.hal_i2c.i2c.cr2.modify(|_, w| w.iterren().disabled()); + self.hal_i2c.i2c.cr2().modify(|_, w| w.iterren().disabled()); } fn send_start(&mut self, read: bool) -> Result<(), super::Error> { @@ -427,9 +427,9 @@ where // read-modify-write operation to avoid race condition. // See PR: https://github.com/stm32-rs/stm32f4xx-hal/pull/662 if read { - i2c.cr1.modify(|_, w| w.ack().set_bit().start().set_bit()); + i2c.cr1().modify(|_, w| w.ack().set_bit().start().set_bit()); } else { - i2c.cr1.modify(|_, w| w.start().set_bit()); + i2c.cr1().modify(|_, w| w.start().set_bit()); } // Wait until START condition was generated @@ -444,7 +444,7 @@ where loop { self.hal_i2c.check_and_clear_error_flags()?; - let sr2 = i2c.sr2.read(); + let sr2 = i2c.sr2().read(); if !(sr2.msl().bit_is_clear() && sr2.busy().bit_is_clear()) { break; } @@ -454,7 +454,7 @@ where } fn send_stop(&mut self) { - self.hal_i2c.i2c.cr1.modify(|_, w| w.stop().set_bit()); + self.hal_i2c.i2c.cr1().modify(|_, w| w.stop().set_bit()); } fn send_address(&mut self, addr: u8, read: bool) -> Result<(), super::Error> { @@ -466,7 +466,7 @@ where } // Set up current address, we're trying to talk to - i2c.dr.write(|w| unsafe { w.bits(to_send_addr) }); + i2c.dr().write(|w| unsafe { w.bits(to_send_addr) }); // Wait until address was sent loop { @@ -493,7 +493,7 @@ where self.send_address(addr, false)?; // Clear condition by reading SR2. This will clear ADDR flag - self.hal_i2c.i2c.sr2.read(); + self.hal_i2c.i2c.sr2().read(); // Enable error interrupts self.enable_error_interrupt_generation(); @@ -518,17 +518,17 @@ where // Transfer Complete interrupt routine if enabled. // On small sized array we need to set ACK=0 before ADDR cleared if buf_len >= 2 { - self.hal_i2c.i2c.cr2.modify(|_, w| w.last().set_bit()); + self.hal_i2c.i2c.cr2().modify(|_, w| w.last().set_bit()); // When a single byte must be received: the NACK must be programmed during // EV6 event, i.e. program ACK=0 when ADDR=1, before clearing ADDR flag. // Then the user can program the STOP condition either after clearing ADDR // flag, or in the DMA Transfer Complete interrupt routine. } else { - self.hal_i2c.i2c.cr1.modify(|_, w| w.ack().clear_bit()); + self.hal_i2c.i2c.cr1().modify(|_, w| w.ack().clear_bit()); } // Clear condition by reading SR2. This will clear ADDR flag - self.hal_i2c.i2c.sr2.read(); + self.hal_i2c.i2c.sr2().read(); // Enable error interrupts self.enable_error_interrupt_generation(); @@ -583,7 +583,7 @@ where fn finish_transfer_with_result(&mut self, result: Result<(), Error>) { self.disable_dma_requests(); self.disable_error_interrupt_generation(); - self.hal_i2c.i2c.cr2.modify(|_, w| w.last().clear_bit()); + self.hal_i2c.i2c.cr2().modify(|_, w| w.last().clear_bit()); if let Err(Error::I2CError(super::Error::NoAcknowledge(_))) = &result { self.send_stop(); @@ -626,7 +626,7 @@ where self.finish_transfer_with_result(Ok(())); // Wait for BTF - while self.hal_i2c.i2c.sr1.read().btf().bit_is_clear() {} + while self.hal_i2c.i2c.sr1().read().btf().bit_is_clear() {} self.send_stop(); } @@ -666,7 +666,7 @@ where self.finish_transfer_with_result(Ok(())); // Clear ACK - self.hal_i2c.i2c.cr1.modify(|_, w| w.ack().clear_bit()); + self.hal_i2c.i2c.cr1().modify(|_, w| w.ack().clear_bit()); self.send_stop(); } @@ -718,7 +718,7 @@ where } // Wait for BTF - while self.hal_i2c.i2c.sr1.read().btf().bit_is_clear() {} + while self.hal_i2c.i2c.sr1().read().btf().bit_is_clear() {} // If we have prepared Rx Transfer, there are write_read command, generate restart signal if have_read_after { @@ -753,7 +753,7 @@ where self.finish_transfer_with_result(Ok(())); // Clear ACK - self.hal_i2c.i2c.cr1.modify(|_, w| w.ack().clear_bit()); + self.hal_i2c.i2c.cr1().modify(|_, w| w.ack().clear_bit()); self.send_stop(); } @@ -902,7 +902,7 @@ pub struct Rx { unsafe impl PeriAddress for Rx { #[inline(always)] fn address(&self) -> u32 { - unsafe { (*I2C::ptr()).dr.as_ptr() as u32 } + unsafe { (*I2C::ptr()).dr().as_ptr() as u32 } } type MemSize = u8; @@ -911,7 +911,7 @@ unsafe impl PeriAddress for Rx { unsafe impl PeriAddress for Tx { #[inline(always)] fn address(&self) -> u32 { - unsafe { (*I2C::ptr()).dr.as_ptr() as u32 } + unsafe { (*I2C::ptr()).dr().as_ptr() as u32 } } type MemSize = u8; diff --git a/src/i2s.rs b/src/i2s.rs index ebe46bc0c..0a42e7b71 100644 --- a/src/i2s.rs +++ b/src/i2s.rs @@ -523,7 +523,7 @@ mod dma { fn address(&self) -> u32 { let reg = unsafe { &*(DualI2s::$reg as *const RegisterBlock) }; - (®.dr) as *const _ as u32 + reg.dr().as_ptr() as u32 } } }; diff --git a/src/qei.rs b/src/qei.rs index a1f734f7f..14bdb1f09 100644 --- a/src/qei.rs +++ b/src/qei.rs @@ -111,18 +111,18 @@ macro_rules! hal { self.ccmr1_input() .write(|w| unsafe { w.cc1s().bits(0b01).cc2s().bits(0b01) }); // enable and configure to capture on rising edge - self.ccer.write(|w| { + self.ccer().write(|w| { w.cc1e().set_bit().cc1p().clear_bit(); w.cc2e().set_bit().cc2p().clear_bit() }); - self.smcr.write(|w| w.sms().encoder_mode_3()); + self.smcr().write(|w| w.sms().encoder_mode_3()); self.set_auto_reload(<$TIM as General>::Width::MAX as u32) .unwrap(); - self.cr1.write(|w| w.cen().set_bit()); + self.cr1().write(|w| w.cen().set_bit()); } fn read_direction(&self) -> bool { - self.cr1.read().dir().bit_is_clear() + self.cr1().read().dir().bit_is_clear() } } }; diff --git a/src/qspi.rs b/src/qspi.rs index 66137cad9..f14dea8aa 100644 --- a/src/qspi.rs +++ b/src/qspi.rs @@ -286,10 +286,10 @@ where ); // Disable QUADSPI before configuring it. - qspi.cr.modify(|_, w| w.en().clear_bit()); + qspi.cr().modify(|_, w| w.en().clear_bit()); // Clear all pending flags. - qspi.fcr.write(|w| { + qspi.fcr().write(|w| { w.ctof().set_bit(); w.csmf().set_bit(); w.ctcf().set_bit(); @@ -341,10 +341,10 @@ impl Qspi { ); // Disable QUADSPI before configuring it. - qspi.cr.modify(|_, w| w.en().clear_bit()); + qspi.cr().modify(|_, w| w.en().clear_bit()); // Clear all pending flags. - qspi.fcr.write(|w| { + qspi.fcr().write(|w| { w.ctof().set_bit(); w.csmf().set_bit(); w.ctcf().set_bit(); @@ -359,28 +359,28 @@ impl Qspi { impl Qspi { pub fn is_busy(&self) -> bool { - self.qspi.sr.read().busy().bit_is_set() + self.qspi.sr().read().busy().bit_is_set() } /// Aborts any ongoing transaction /// Note can cause problems if aborting writes to flash satus register pub fn abort_transmission(&mut self) { - self.qspi.cr.modify(|_, w| w.abort().set_bit()); - while self.qspi.sr.read().busy().bit_is_set() {} + self.qspi.cr().modify(|_, w| w.abort().set_bit()); + while self.qspi.sr().read().busy().bit_is_set() {} } pub fn apply_config(&mut self, config: QspiConfig) { - if self.qspi.sr.read().busy().bit_is_set() { + if self.qspi.sr().read().busy().bit_is_set() { self.abort_transmission(); } self.qspi - .cr + .cr() .modify(|_, w| unsafe { w.fthres().bits(config.fifo_threshold) }); - while self.qspi.sr.read().busy().bit_is_set() {} + while self.qspi.sr().read().busy().bit_is_set() {} - self.qspi.cr.modify(|_, w| unsafe { + self.qspi.cr().modify(|_, w| unsafe { w.prescaler() .bits(config.clock_prescaler) .sshift() @@ -393,7 +393,7 @@ impl Qspi { while self.is_busy() {} // Modify DCR with flash size, CSHT and clock mode - self.qspi.dcr.modify(|_, w| unsafe { + self.qspi.dcr().modify(|_, w| unsafe { w.fsize().bits(config.flash_size.inner); w.csht().bits(config.chip_select_high_time); w.ckmode().bit(config.clock_mode == ClockMode::Mode3) @@ -401,7 +401,7 @@ impl Qspi { while self.is_busy() {} // Enable QSPI - self.qspi.cr.modify(|_, w| w.en().set_bit()); + self.qspi.cr().modify(|_, w| w.en().set_bit()); while self.is_busy() {} self.config = config; @@ -421,12 +421,12 @@ impl Qspi { // If double data rate change shift if command.double_data_rate { - self.qspi.cr.modify(|_, w| w.sshift().bit(false)); + self.qspi.cr().modify(|_, w| w.sshift().bit(false)); } while self.is_busy() {} // Clear the transfer complete flag. - self.qspi.fcr.modify(|_, w| w.ctcf().set_bit()); + self.qspi.fcr().modify(|_, w| w.ctcf().set_bit()); let dmode: u8 = command.data.1 as u8; let mut instruction: u8 = 0; @@ -438,7 +438,7 @@ impl Qspi { // Write the length and format of data self.qspi - .dlr + .dlr() .write(|w| unsafe { w.dl().bits(buffer.len() as u32 - 1) }); // Write instruction mode @@ -458,7 +458,7 @@ impl Qspi { abmode = mode as u8; absize = a_bytes.len() as u8 - 1; - self.qspi.abr.write(|w| { + self.qspi.abr().write(|w| { let mut reg_byte: u32 = 0; for (i, element) in a_bytes.iter().rev().enumerate() { reg_byte |= (*element as u32) << (i * 8); @@ -468,7 +468,7 @@ impl Qspi { } // Write CCR register with instruction etc. - self.qspi.ccr.modify(|_, w| unsafe { + self.qspi.ccr().modify(|_, w| unsafe { w.fmode().bits(0b01 /* Indirect read */); w.admode().bits(admode); w.adsize().bits(adsize); @@ -483,26 +483,26 @@ impl Qspi { // Write address, triggers send if let Some((addr, _)) = command.address { - self.qspi.ar.write(|w| unsafe { w.address().bits(addr) }); + self.qspi.ar().write(|w| unsafe { w.address().bits(addr) }); // Transfer error - if self.qspi.sr.read().tef().bit_is_set() { + if self.qspi.sr().read().tef().bit_is_set() { return Err(QspiError::Address); } } // Transfer error - if self.qspi.sr.read().tef().bit_is_set() { + if self.qspi.sr().read().tef().bit_is_set() { return Err(QspiError::Unknown); } // Read data from the buffer let mut b = buffer.iter_mut(); - while self.qspi.sr.read().tcf().bit_is_clear() { - if self.qspi.sr.read().ftf().bit_is_set() { + while self.qspi.sr().read().tcf().bit_is_clear() { + if self.qspi.sr().read().ftf().bit_is_set() { if let Some(v) = b.next() { unsafe { - *v = core::ptr::read_volatile(self.qspi.dr.as_ptr() as *const u8); + *v = core::ptr::read_volatile(self.qspi.dr().as_ptr() as *const u8); } } else { // OVERFLOW @@ -512,10 +512,10 @@ impl Qspi { } } // When transfer complete, empty fifo buffer - while self.qspi.sr.read().flevel().bits() > 0 { + while self.qspi.sr().read().flevel().bits() > 0 { if let Some(v) = b.next() { unsafe { - *v = core::ptr::read_volatile(self.qspi.dr.as_ptr() as *const u8); + *v = core::ptr::read_volatile(self.qspi.dr().as_ptr() as *const u8); } } else { // OVERFLOW @@ -528,13 +528,13 @@ impl Qspi { if self.is_busy() { self.abort_transmission(); } - self.qspi.cr.modify(|_, w| { + self.qspi.cr().modify(|_, w| { w.sshift() .bit(self.config.sample_shift == SampleShift::HalfACycle) }); } while self.is_busy() {} - self.qspi.fcr.write(|w| w.ctcf().set_bit()); + self.qspi.fcr().write(|w| w.ctcf().set_bit()); Ok(()) } @@ -544,7 +544,7 @@ impl Qspi { return Err(QspiError::Busy); } // Clear the transfer complete flag. - self.qspi.fcr.modify(|_, w| w.ctcf().set_bit()); + self.qspi.fcr().modify(|_, w| w.ctcf().set_bit()); let mut dmode: u8 = 0; let mut instruction: u8 = 0; @@ -557,7 +557,7 @@ impl Qspi { // Write the length and format of data if let Some((data, mode)) = command.data { self.qspi - .dlr + .dlr() .write(|w| unsafe { w.dl().bits(data.len() as u32 - 1) }); dmode = mode as u8; } @@ -580,7 +580,7 @@ impl Qspi { absize = a_bytes.len() as u8 - 1; - self.qspi.abr.write(|w| { + self.qspi.abr().write(|w| { let mut reg_byte: u32 = 0; for (i, element) in a_bytes.iter().rev().enumerate() { reg_byte |= (*element as u32) << (i * 8); @@ -590,11 +590,11 @@ impl Qspi { } if command.double_data_rate { - self.qspi.cr.modify(|_, w| w.sshift().bit(false)); + self.qspi.cr().modify(|_, w| w.sshift().bit(false)); } // Write CCR register with instruction etc. - self.qspi.ccr.modify(|_, w| unsafe { + self.qspi.ccr().modify(|_, w| unsafe { w.fmode().bits(0b00 /* Indirect write mode */); w.admode().bits(admode); w.adsize().bits(adsize); @@ -609,30 +609,30 @@ impl Qspi { // Write address, triggers send if let Some((addr, _)) = command.address { - self.qspi.ar.write(|w| unsafe { w.address().bits(addr) }); + self.qspi.ar().write(|w| unsafe { w.address().bits(addr) }); } // Transfer error - if self.qspi.sr.read().tef().bit_is_set() { + if self.qspi.sr().read().tef().bit_is_set() { return Err(QspiError::Unknown); } // Write data to the FIFO if let Some((data, _)) = command.data { for byte in data { - while self.qspi.sr.read().ftf().bit_is_clear() {} + while self.qspi.sr().read().ftf().bit_is_clear() {} unsafe { - core::ptr::write_volatile(self.qspi.dr.as_ptr() as *mut u8, *byte); + core::ptr::write_volatile(self.qspi.dr().as_ptr() as *mut u8, *byte); } } } - while self.qspi.sr.read().tcf().bit_is_clear() {} + while self.qspi.sr().read().tcf().bit_is_clear() {} - self.qspi.fcr.write(|w| w.ctcf().set_bit()); + self.qspi.fcr().write(|w| w.ctcf().set_bit()); if command.double_data_rate { - self.qspi.cr.modify(|_, w| { + self.qspi.cr().modify(|_, w| { w.sshift() .bit(self.config.sample_shift == SampleShift::HalfACycle) }); @@ -653,12 +653,12 @@ impl Qspi { // If double data rate change shift if command.double_data_rate { - self.qspi.cr.modify(|_, w| w.sshift().bit(false)); + self.qspi.cr().modify(|_, w| w.sshift().bit(false)); } while self.is_busy() {} // Clear the transfer complete flag. - self.qspi.fcr.modify(|_, w| w.ctcf().set_bit()); + self.qspi.fcr().modify(|_, w| w.ctcf().set_bit()); let mut abmode: u8 = 0; let mut absize: u8 = 0; @@ -675,7 +675,7 @@ impl Qspi { abmode = mode as u8; absize = a_bytes.len() as u8 - 1; - self.qspi.abr.write(|w| { + self.qspi.abr().write(|w| { let mut reg_byte: u32 = 0; for (i, element) in a_bytes.iter().rev().enumerate() { reg_byte |= (*element as u32) << (i * 8); @@ -684,7 +684,7 @@ impl Qspi { }); } - self.qspi.ccr.modify(|_, w| unsafe { + self.qspi.ccr().modify(|_, w| unsafe { w.fmode().bits(0b11 /* Memory mapped mode */); w.admode().bits(command.address_mode as u8); w.adsize().bits(self.config.address_size as u8); diff --git a/src/rcc/mod.rs b/src/rcc/mod.rs index a6873e22c..b3b597ebe 100644 --- a/src/rcc/mod.rs +++ b/src/rcc/mod.rs @@ -40,7 +40,7 @@ //! and on the STM32F413/423 SAI clocks are generated by the I2S PLL. On these MCUs, the actual //! frequencies may substantially deviate from the requested frequencies. -use crate::pac::rcc::cfgr::{HPRE_A, SW_A}; +use crate::pac::rcc::cfgr::{HPRE, SW}; use crate::pac::{self, rcc, RCC}; use fugit::HertzU32 as Hertz; @@ -191,22 +191,21 @@ macro_rules! bus_struct { $( $(#[$attr])* #[doc = $doc] - pub struct $busX { - _0: (), - } + #[non_exhaustive] + pub struct $busX; $(#[$attr])* impl $busX { pub(crate) fn enr(rcc: &RccRB) -> &rcc::$EN { - &rcc.$en + rcc.$en() } pub(crate) fn lpenr(rcc: &RccRB) -> &rcc::$LPEN { - &rcc.$lpen + rcc.$lpen() } pub(crate) fn rstr(rcc: &RccRB) -> &rcc::$RST { - &rcc.$rst + rcc.$rst() } } )+ @@ -225,24 +224,23 @@ bus_struct! { /// AMBA High-performance Bus 3 (AHB3) registers #[cfg(any(feature = "fsmc", feature = "fmc"))] -pub struct AHB3 { - _0: (), -} +#[non_exhaustive] +pub struct AHB3; #[cfg(any(feature = "fsmc", feature = "fmc"))] impl AHB3 { #[inline(always)] fn enr(rcc: &RccRB) -> &rcc::AHB3ENR { - &rcc.ahb3enr + rcc.ahb3enr() } #[cfg(feature = "fmc")] #[inline(always)] fn lpenr(rcc: &RccRB) -> &rcc::AHB3LPENR { - &rcc.ahb3lpenr + rcc.ahb3lpenr() } #[inline(always)] fn rstr(rcc: &RccRB) -> &rcc::AHB3RSTR { - &rcc.ahb3rstr + rcc.ahb3rstr() } } @@ -582,7 +580,7 @@ impl CFGR { u32::max((i2s_pll.plli2sclk.unwrap() + (sai_clk >> 1)) / sai_clk, 1), 31, ); - rcc.dckcfgr.modify(|_, w| w.plli2sdivr().bits(div as u8)); + rcc.dckcfgr().modify(|_, w| w.plli2sdivr().set(div as u8)); let real_sai_clk = sai_clk / div; (i2s_pll, Some(real_sai_clk)) } else { @@ -599,7 +597,7 @@ impl CFGR { }) .min_by_key(|(_, real_clk, _)| (*real_clk as i32 - pll_sai_clk as i32).abs()) .unwrap(); - rcc.dckcfgr.modify(|_, w| w.plli2sdivr().bits(div as u8)); + rcc.dckcfgr().modify(|_, w| w.plli2sdivr().set(div as u8)); (i2s_pll, Some(real_sai_clk)) } else { (I2sPll::unused(), None) @@ -751,7 +749,7 @@ impl CFGR { unsafe { let flash = &(*FLASH::ptr()); // Adjust flash wait states - flash.acr.modify(|_, w| { + flash.acr().modify(|_, w| { w.latency().bits(((sysclk - 1) / flash_latency_step) as u8); w.prften().set_bit(); w.icen().set_bit(); @@ -797,15 +795,15 @@ impl CFGR { let hclk = self.hclk.unwrap_or(sysclk); let (hpre_bits, hpre_div) = match (sysclk + hclk - 1) / hclk { 0 => unreachable!(), - 1 => (HPRE_A::Div1, 1), - 2 => (HPRE_A::Div2, 2), - 3..=5 => (HPRE_A::Div4, 4), - 6..=11 => (HPRE_A::Div8, 8), - 12..=39 => (HPRE_A::Div16, 16), - 40..=95 => (HPRE_A::Div64, 64), - 96..=191 => (HPRE_A::Div128, 128), - 192..=383 => (HPRE_A::Div256, 256), - _ => (HPRE_A::Div512, 512), + 1 => (HPRE::Div1, 1), + 2 => (HPRE::Div2, 2), + 3..=5 => (HPRE::Div4, 4), + 6..=11 => (HPRE::Div8, 8), + 12..=39 => (HPRE::Div16, 16), + 40..=95 => (HPRE::Div64, 64), + 96..=191 => (HPRE::Div128, 128), + 192..=383 => (HPRE::Div256, 256), + _ => (HPRE::Div512, 512), }; // Calculate real AHB clock @@ -849,55 +847,55 @@ impl CFGR { if self.hse.is_some() { // enable HSE and wait for it to be ready - rcc.cr.modify(|_, w| { + rcc.cr().modify(|_, w| { if self.hse_bypass { w.hsebyp().bypassed(); } w.hseon().set_bit() }); - while rcc.cr.read().hserdy().bit_is_clear() {} + while rcc.cr().read().hserdy().bit_is_clear() {} } if plls.use_pll { // Enable PLL - rcc.cr.modify(|_, w| w.pllon().set_bit()); + rcc.cr().modify(|_, w| w.pllon().set_bit()); // Enable voltage regulator overdrive if HCLK is above the limit #[cfg(any(feature = "gpio-f427", feature = "gpio-f446", feature = "gpio-f469"))] if hclk > 168_000_000 { // Enable clock for PWR peripheral - rcc.apb1enr.modify(|_, w| w.pwren().set_bit()); + rcc.apb1enr().modify(|_, w| w.pwren().set_bit()); // Stall the pipeline to work around erratum 2.1.13 (DM00037591) cortex_m::asm::dsb(); let pwr = unsafe { &*crate::pac::PWR::ptr() }; - pwr.cr.modify(|_, w| w.oden().set_bit()); - while pwr.csr.read().odrdy().bit_is_clear() {} - pwr.cr.modify(|_, w| w.odswen().set_bit()); - while pwr.csr.read().odswrdy().bit_is_clear() {} + pwr.cr().modify(|_, w| w.oden().set_bit()); + while pwr.csr().read().odrdy().bit_is_clear() {} + pwr.cr().modify(|_, w| w.odswen().set_bit()); + while pwr.csr().read().odswrdy().bit_is_clear() {} } // Wait for PLL to stabilise - while rcc.cr.read().pllrdy().bit_is_clear() {} + while rcc.cr().read().pllrdy().bit_is_clear() {} } #[cfg(not(feature = "gpio-f410"))] if plls.use_i2spll { // Enable PLL. - rcc.cr.modify(|_, w| w.plli2son().set_bit()); + rcc.cr().modify(|_, w| w.plli2son().set_bit()); // Wait for PLL to stabilise - while rcc.cr.read().plli2srdy().bit_is_clear() {} + while rcc.cr().read().plli2srdy().bit_is_clear() {} } #[cfg(any(feature = "gpio-f427", feature = "gpio-f446", feature = "gpio-f469"))] if plls.use_saipll { // Enable PLL. - rcc.cr.modify(|_, w| w.pllsaion().set_bit()); + rcc.cr().modify(|_, w| w.pllsaion().set_bit()); // Wait for PLL to stabilise - while rcc.cr.read().pllsairdy().bit_is_clear() {} + while rcc.cr().read().pllsairdy().bit_is_clear() {} } // Select I2S and SAI clocks @@ -906,7 +904,7 @@ impl CFGR { plls.sai.config_clocksel(); // Set scaling factors - rcc.cfgr.modify(|_, w| unsafe { + rcc.cfgr().modify(|_, w| unsafe { w.ppre2().bits(ppre2_bits); w.ppre1().bits(ppre1_bits); w.hpre().variant(hpre_bits) @@ -917,13 +915,13 @@ impl CFGR { cortex_m::asm::delay(16); // Select system clock source - rcc.cfgr.modify(|_, w| { + rcc.cfgr().modify(|_, w| { w.sw().variant(if sysclk_on_pll { - SW_A::Pll + SW::Pll } else if self.hse.is_some() { - SW_A::Hse + SW::Hse } else { - SW_A::Hsi + SW::Hsi }) }); @@ -1063,7 +1061,7 @@ impl RealI2sClocks { feature = "gpio-f413", feature = "gpio-f446", )))] - rcc.cfgr.modify(|_, w| { + rcc.cfgr().modify(|_, w| { if self.i2s_ext { w.i2ssrc().ckin() } else { @@ -1071,7 +1069,7 @@ impl RealI2sClocks { } }); #[cfg(feature = "gpio-f410")] - rcc.dckcfgr.modify(|_, w| { + rcc.dckcfgr().modify(|_, w| { if self.i2s_ext { w.i2ssrc().i2s_ckin() } else { @@ -1079,7 +1077,7 @@ impl RealI2sClocks { } }); #[cfg(any(feature = "gpio-f412", feature = "gpio-f413", feature = "gpio-f446"))] - rcc.dckcfgr.modify(|_, w| { + rcc.dckcfgr().modify(|_, w| { if self.i2s_apb1_ext { w.i2s1src().i2s_ckin() } else { @@ -1141,7 +1139,7 @@ impl RealSaiClocks { // Configure SAI clocks. #[cfg(not(feature = "gpio-f446"))] - rcc.dckcfgr.modify(|_, w| { + rcc.dckcfgr().modify(|_, w| { if self.sai1_ext { w.sai1asrc().i2s_ckin() } else { @@ -1155,7 +1153,7 @@ impl RealSaiClocks { }); #[cfg(feature = "gpio-f446")] - rcc.dckcfgr.modify(|_, w| { + rcc.dckcfgr().modify(|_, w| { if self.sai1_ext { w.sai1src().i2s_ckin() } else { diff --git a/src/rcc/pll.rs b/src/rcc/pll.rs index adfeb227a..412fbd5d7 100644 --- a/src/rcc/pll.rs +++ b/src/rcc/pll.rs @@ -22,7 +22,7 @@ impl MainPll { // Even if we do not use the main PLL, we still need to set the PLL source as that setting // applies to the I2S and SAI PLLs as well. unsafe { &*RCC::ptr() } - .pllcfgr + .pllcfgr() .write(|w| w.pllsrc().bit(use_hse)); return MainPll { @@ -82,7 +82,7 @@ impl MainPll { let pllq = (vco_in * plln + 47_999_999) / 48_000_000; let real_pll48clk = vco_in * plln / pllq; - unsafe { &*RCC::ptr() }.pllcfgr.write(|w| unsafe { + unsafe { &*RCC::ptr() }.pllcfgr().write(|w| unsafe { w.pllm().bits(pllm as u8); w.plln().bits(plln as u16); w.pllp().bits(pllp as u8); @@ -164,7 +164,7 @@ impl MainPll { .min_by_key(|(_, _, _, _, _, error)| *error) .expect("could not find a valid main PLL configuration"); - unsafe { &*RCC::ptr() }.pllcfgr.write(|w| unsafe { + unsafe { &*RCC::ptr() }.pllcfgr().write(|w| unsafe { w.pllm().bits(pllm as u8); w.plln().bits(plln as u16); if let Some(pllp) = pllp { @@ -296,9 +296,9 @@ impl I2sPll { fn apply_config(config: SingleOutputPll) { let rcc = unsafe { &*RCC::ptr() }; // "M" may have been written before, but the value is identical. - rcc.pllcfgr + rcc.pllcfgr() .modify(|_, w| unsafe { w.pllm().bits(config.m) }); - rcc.plli2scfgr + rcc.plli2scfgr() .modify(|_, w| unsafe { w.plli2sn().bits(config.n).plli2sr().bits(config.outdiv) }); } #[cfg(any( @@ -309,7 +309,7 @@ impl I2sPll { ))] fn apply_config(config: SingleOutputPll) { let rcc = unsafe { &*RCC::ptr() }; - rcc.plli2scfgr.modify(|_, w| unsafe { + rcc.plli2scfgr().modify(|_, w| unsafe { w.plli2sm().bits(config.m); w.plli2sn().bits(config.n); w.plli2sr().bits(config.outdiv) @@ -393,20 +393,20 @@ impl SaiPll { #[cfg(not(feature = "gpio-f446"))] fn apply_config(config: SingleOutputPll, saidiv: u32) { let rcc = unsafe { &*RCC::ptr() }; - rcc.dckcfgr - .modify(|_, w| w.pllsaidivq().bits(saidiv as u8 - 1)); + rcc.dckcfgr() + .modify(|_, w| w.pllsaidivq().set(saidiv as u8 - 1)); // "M" may have been written before, but the value is identical. - rcc.pllcfgr + rcc.pllcfgr() .modify(|_, w| unsafe { w.pllm().bits(config.m) }); - rcc.pllsaicfgr + rcc.pllsaicfgr() .modify(|_, w| unsafe { w.pllsain().bits(config.n).pllsaiq().bits(config.outdiv) }); } #[cfg(feature = "gpio-f446")] fn apply_config(config: SingleOutputPll, saidiv: u32) { let rcc = unsafe { &*RCC::ptr() }; - rcc.dckcfgr - .modify(|_, w| w.pllsaidivq().bits(saidiv as u8 - 1)); - rcc.pllsaicfgr.modify(|_, w| unsafe { + rcc.dckcfgr() + .modify(|_, w| w.pllsaidivq().set(saidiv as u8 - 1)); + rcc.pllsaicfgr().modify(|_, w| unsafe { w.pllsaim().bits(config.m); w.pllsain().bits(config.n); w.pllsaiq().bits(config.outdiv) diff --git a/src/rng.rs b/src/rng.rs index 7d53f4660..3d5645f80 100644 --- a/src/rng.rs +++ b/src/rng.rs @@ -94,7 +94,7 @@ impl RngExt for RNG { assert!(rng_clk >= (hclk / 16)); // enable the RNG peripheral - self.cr.modify(|_, w| w.rngen().set_bit()); + self.cr().modify(|_, w| w.rngen().set_bit()); }); Rng { rb: self } @@ -124,7 +124,7 @@ impl Rng { /// May fail if, for example RNG_CLK is misconfigured. fn next_random_word(&mut self) -> Result { loop { - let status = self.rb.sr.read(); + let status = self.rb.sr().read(); if status.cecs().bit() { return Err(ErrorKind::ClockError); } @@ -132,7 +132,7 @@ impl Rng { return Err(ErrorKind::SeedError); } if status.drdy().bit() { - return Ok(self.rb.dr.read().rndata().bits()); + return Ok(self.rb.dr().read().rndata().bits()); } } } diff --git a/src/rtc.rs b/src/rtc.rs index 429a7e2e3..81943802a 100644 --- a/src/rtc.rs +++ b/src/rtc.rs @@ -3,7 +3,7 @@ //! [ST AN4759](https:/www.st.com%2Fresource%2Fen%2Fapplication_note%2Fdm00226326-using-the-hardware-realtime-clock-rtc-and-the-tamper-management-unit-tamp-with-stm32-microcontrollers-stmicroelectronics.pdf&usg=AOvVaw3PzvL2TfYtwS32fw-Uv37h) use crate::bb; -use crate::pac::rtc::{dr, tr, DR, TR}; +use crate::pac::rtc::{dr, tr}; use crate::pac::{self, rcc::RegisterBlock, PWR, RCC, RTC}; use crate::rcc::Enable; use core::fmt; @@ -152,21 +152,21 @@ impl Rtc { // As per the sample code, unlock comes first. (Enable PWR and DBP) result.unlock(rcc, pwr); // If necessary, enable the LSE. - if rcc.bdcr.read().lserdy().bit_is_clear() { + if rcc.bdcr().read().lserdy().bit_is_clear() { result.enable_lse(rcc, mode); } // Set clock source to LSE. - rcc.bdcr.modify(|_, w| w.rtcsel().lse()); + rcc.bdcr().modify(|_, w| w.rtcsel().lse()); result.enable(rcc); } result.modify(true, |regs| { // Set 24 Hour - regs.cr.modify(|_, w| w.fmt().clear_bit()); + regs.cr().modify(|_, w| w.fmt().clear_bit()); // Set prescalers - regs.prer.modify(|_, w| { - w.prediv_s().bits(prediv_s); - w.prediv_a().bits(prediv_a) + regs.prer().modify(|_, w| { + w.prediv_s().set(prediv_s); + w.prediv_a().set(prediv_a) }) }); @@ -181,14 +181,14 @@ impl Rtc { self.backup_reset(rcc); // Enable the LSE. // Set BDCR - Bit 0 (LSEON) - bb::set(&rcc.bdcr, 0); + bb::set(rcc.bdcr(), 0); match mode { // Set BDCR - Bit 2 (LSEBYP) - LSEClockMode::Bypass => bb::set(&rcc.bdcr, 2), + LSEClockMode::Bypass => bb::set(rcc.bdcr(), 2), // Clear BDCR - Bit 2 (LSEBYP) - LSEClockMode::Oscillator => bb::clear(&rcc.bdcr, 2), + LSEClockMode::Oscillator => bb::clear(rcc.bdcr(), 2), } - while rcc.bdcr.read().lserdy().bit_is_clear() {} + while rcc.bdcr().read().lserdy().bit_is_clear() {} } } } @@ -225,21 +225,21 @@ impl Rtc { // As per the sample code, unlock comes first. (Enable PWR and DBP) result.unlock(rcc, pwr); // If necessary, enable the LSE. - if rcc.csr.read().lsirdy().bit_is_clear() { + if rcc.csr().read().lsirdy().bit_is_clear() { result.enable_lsi(rcc); } // Set clock source to LSI. - rcc.bdcr.modify(|_, w| w.rtcsel().lsi()); + rcc.bdcr().modify(|_, w| w.rtcsel().lsi()); result.enable(rcc); } result.modify(true, |regs| { // Set 24 Hour - regs.cr.modify(|_, w| w.fmt().clear_bit()); + regs.cr().modify(|_, w| w.fmt().clear_bit()); // Set prescalers - regs.prer.modify(|_, w| { - w.prediv_s().bits(prediv_s); - w.prediv_a().bits(prediv_a) + regs.prer().modify(|_, w| { + w.prediv_s().set(prediv_s); + w.prediv_a().set(prediv_a) }) }); @@ -250,8 +250,8 @@ impl Rtc { // Force a reset of the backup domain. self.backup_reset(rcc); // Enable the LSI. - rcc.csr.modify(|_, w| w.lsion().on()); - while rcc.csr.read().lsirdy().is_not_ready() {} + rcc.csr().modify(|_, w| w.lsion().on()); + while rcc.csr().read().lsirdy().is_not_ready() {} } } @@ -261,20 +261,16 @@ impl Rtc { // Set APB1 - Bit 28 (PWREN) PWR::enable(rcc); - pwr.cr.modify(|_, w| { - w - // Enable access to the backup registers - .dbp() - .set_bit() - }); + // Enable access to the backup registers + pwr.cr().modify(|_, w| w.dbp().set_bit()); } fn backup_reset(&mut self, rcc: &RegisterBlock) { unsafe { // Set BDCR - Bit 16 (BDRST) - bb::set(&rcc.bdcr, 16); + bb::set(rcc.bdcr(), 16); // Clear BDCR - Bit 16 (BDRST) - bb::clear(&rcc.bdcr, 16); + bb::clear(rcc.bdcr(), 16); } } @@ -282,16 +278,16 @@ impl Rtc { // Start the actual RTC. // Set BDCR - Bit 15 (RTCEN) unsafe { - bb::set(&rcc.bdcr, 15); + bb::set(rcc.bdcr(), 15); } } pub fn set_prescalers(&mut self, prediv_s: u16, prediv_a: u8) { self.modify(true, |regs| { // Set prescalers - regs.prer.modify(|_, w| { - w.prediv_s().bits(prediv_s); - w.prediv_a().bits(prediv_a) + regs.prer().modify(|_, w| { + w.prediv_s().set(prediv_s); + w.prediv_a().set(prediv_a) }) }); } @@ -305,27 +301,27 @@ impl Rtc { { // Disable write protection // This is safe, as we're only writin the correct and expected values. - self.regs.wpr.write(|w| unsafe { w.bits(0xCA) }); - self.regs.wpr.write(|w| unsafe { w.bits(0x53) }); + self.regs.wpr().write(|w| unsafe { w.bits(0xCA) }); + self.regs.wpr().write(|w| unsafe { w.bits(0x53) }); // Enter init mode - if init_mode && self.regs.isr.read().initf().bit_is_clear() { - self.regs.isr.modify(|_, w| w.init().set_bit()); + if init_mode && self.regs.isr().read().initf().bit_is_clear() { + self.regs.isr().modify(|_, w| w.init().set_bit()); // wait till init state entered // ~2 RTCCLK cycles - while self.regs.isr.read().initf().bit_is_clear() {} + while self.regs.isr().read().initf().bit_is_clear() {} } // Invoke closure closure(&mut self.regs); // Exit init mode if init_mode { - self.regs.isr.modify(|_, w| w.init().clear_bit()); + self.regs.isr().modify(|_, w| w.init().clear_bit()); } // wait for last write to be done - while !self.regs.isr.read().initf().bit_is_clear() {} + while !self.regs.isr().read().initf().bit_is_clear() {} // Re-enable write protection. // This is safe, as the field accepts the full range of 8-bit values. - self.regs.wpr.write(|w| unsafe { w.bits(0xFF) }); + self.regs.wpr().write(|w| unsafe { w.bits(0xFF) }); } /// Set the time using time::Time. @@ -334,13 +330,13 @@ impl Rtc { let (mnt, mnu) = bcd2_encode(time.minute().into())?; let (st, su) = bcd2_encode(time.second().into())?; self.modify(true, |regs| { - regs.tr.write(|w| { - w.ht().bits(ht); - w.hu().bits(hu); - w.mnt().bits(mnt); - w.mnu().bits(mnu); - w.st().bits(st); - w.su().bits(su); + regs.tr().write(|w| { + w.ht().set(ht); + w.hu().set(hu); + w.mnt().set(mnt); + w.mnu().set(mnu); + w.st().set(st); + w.su().set(su); w.pm().clear_bit() }) }); @@ -355,7 +351,7 @@ impl Rtc { } let (st, su) = bcd2_encode(seconds.into())?; self.modify(true, |regs| { - regs.tr.modify(|_, w| w.st().bits(st).su().bits(su)) + regs.tr().modify(|_, w| w.st().set(st).su().set(su)) }); Ok(()) @@ -368,7 +364,7 @@ impl Rtc { } let (mnt, mnu) = bcd2_encode(minutes.into())?; self.modify(true, |regs| { - regs.tr.modify(|_, w| w.mnt().bits(mnt).mnu().bits(mnu)) + regs.tr().modify(|_, w| w.mnt().set(mnt).mnu().set(mnu)) }); Ok(()) @@ -382,7 +378,7 @@ impl Rtc { let (ht, hu) = bcd2_encode(hours.into())?; self.modify(true, |regs| { - regs.tr.modify(|_, w| w.ht().bits(ht).hu().bits(hu)) + regs.tr().modify(|_, w| w.ht().set(ht).hu().set(hu)) }); Ok(()) @@ -394,7 +390,7 @@ impl Rtc { return Err(Error::InvalidInputData); } self.modify(true, |regs| { - regs.dr.modify(|_, w| unsafe { w.wdu().bits(weekday) }) + regs.dr().modify(|_, w| unsafe { w.wdu().bits(weekday) }) }); Ok(()) @@ -407,7 +403,7 @@ impl Rtc { } let (dt, du) = bcd2_encode(day as u32)?; self.modify(true, |regs| { - regs.dr.modify(|_, w| w.dt().bits(dt).du().bits(du)) + regs.dr().modify(|_, w| w.dt().set(dt).du().set(du)) }); Ok(()) @@ -420,7 +416,7 @@ impl Rtc { } let (mt, mu) = bcd2_encode(month as u32)?; self.modify(true, |regs| { - regs.dr.modify(|_, w| w.mt().bit(mt > 0).mu().bits(mu)) + regs.dr().modify(|_, w| w.mt().bit(mt > 0).mu().set(mu)) }); Ok(()) @@ -436,7 +432,7 @@ impl Rtc { } let (yt, yu) = bcd2_encode(year as u32 - 1970)?; self.modify(true, |regs| { - regs.dr.modify(|_, w| w.yt().bits(yt).yu().bits(yu)) + regs.dr().modify(|_, w| w.yt().set(yt).yu().set(yu)) }); Ok(()) @@ -457,13 +453,13 @@ impl Rtc { let wdu = date.weekday().number_from_monday(); self.modify(true, |regs| { - regs.dr.write(|w| { - w.dt().bits(dt); - w.du().bits(du); + regs.dr().write(|w| { + w.dt().set(dt); + w.du().set(du); w.mt().bit(mt > 0); - w.mu().bits(mu); - w.yt().bits(yt); - w.yu().bits(yu); + w.mu().set(mu); + w.yt().set(yt); + w.yu().set(yu); unsafe { w.wdu().bits(wdu) } }) }); @@ -490,22 +486,22 @@ impl Rtc { let (st, su) = bcd2_encode(date.second().into())?; self.modify(true, |regs| { - regs.dr.write(|w| { - w.dt().bits(dt); - w.du().bits(du); + regs.dr().write(|w| { + w.dt().set(dt); + w.du().set(du); w.mt().bit(mt > 0); - w.mu().bits(mu); - w.yt().bits(yt); - w.yu().bits(yu); + w.mu().set(mu); + w.yt().set(yt); + w.yu().set(yu); unsafe { w.wdu().bits(wdu) } }); - regs.tr.write(|w| { - w.ht().bits(ht); - w.hu().bits(hu); - w.mnt().bits(mnt); - w.mnu().bits(mnu); - w.st().bits(st); - w.su().bits(su); + regs.tr().write(|w| { + w.ht().set(ht); + w.hu().set(hu); + w.mnt().set(mnt); + w.mnu().set(mnu); + w.st().set(st); + w.su().set(su); w.pm().clear_bit() }) }); @@ -515,16 +511,16 @@ impl Rtc { pub fn get_datetime(&mut self) -> PrimitiveDateTime { // Wait for Registers synchronization flag, to ensure consistency between the RTC_SSR, RTC_TR and RTC_DR shadow registers. - while self.regs.isr.read().rsf().bit_is_clear() {} + while self.regs.isr().read().rsf().bit_is_clear() {} // Reading either RTC_SSR or RTC_TR locks the values in the higher-order calendar shadow registers until RTC_DR is read. // So it is important to always read SSR, TR and then DR or TR and then DR. - let ss = self.regs.ssr.read().ss().bits(); - let tr = self.regs.tr.read(); - let dr = self.regs.dr.read(); + let ss = self.regs.ssr().read().ss().bits(); + let tr = self.regs.tr().read(); + let dr = self.regs.dr().read(); // In case the software makes read accesses to the calendar in a time interval smaller // than 2 RTCCLK periods: RSF must be cleared by software after the first calendar read. - self.regs.isr.modify(|_, w| w.rsf().clear_bit()); + self.regs.isr().modify(|_, w| w.rsf().clear_bit()); let seconds = decode_seconds(&tr); let minutes = decode_minutes(&tr); @@ -532,7 +528,7 @@ impl Rtc { let day = decode_day(&dr); let month = decode_month(&dr); let year = decode_year(&dr); - let prediv_s = self.regs.prer.read().prediv_s().bits(); + let prediv_s = self.regs.prer().read().prediv_s().bits(); let nano = ss_to_nano(ss, prediv_s); PrimitiveDateTime::new( @@ -548,11 +544,11 @@ impl Rtc { /// Panics if interval is greater than 2¹⁷-1 seconds. pub fn enable_wakeup(&mut self, interval: fugit::MicrosDurationU64) { self.modify(false, |regs| { - regs.cr.modify(|_, w| w.wute().clear_bit()); - regs.isr.modify(|_, w| w.wutf().clear_bit()); - while regs.isr.read().wutwf().bit_is_clear() {} + regs.cr().modify(|_, w| w.wute().clear_bit()); + regs.isr().modify(|_, w| w.wutf().clear_bit()); + while regs.isr().read().wutwf().bit_is_clear() {} - use crate::pac::rtc::cr::WUCKSEL_A; + use crate::pac::rtc::cr::WUCKSEL; if interval < fugit::MicrosDurationU64::secs(32) { // Use RTCCLK as the wakeup timer clock source let frequency: fugit::Hertz = (CS::frequency() / 2).into(); @@ -565,61 +561,61 @@ impl Rtc { } let wucksel = match prescaler { - 0 => WUCKSEL_A::Div2, - 1 => WUCKSEL_A::Div4, - 2 => WUCKSEL_A::Div8, - 3 => WUCKSEL_A::Div16, + 0 => WUCKSEL::Div2, + 1 => WUCKSEL::Div4, + 2 => WUCKSEL::Div8, + 3 => WUCKSEL::Div16, _ => unreachable!("Longer durations should use ck_spre"), }; let interval = u16::try_from((ticks_per_interval >> prescaler) - 1).unwrap(); - regs.cr.modify(|_, w| w.wucksel().variant(wucksel)); - regs.wutr.write(|w| w.wut().bits(interval)); + regs.cr().modify(|_, w| w.wucksel().variant(wucksel)); + regs.wutr().write(|w| w.wut().set(interval)); } else { // Use ck_spre (1Hz) as the wakeup timer clock source let interval = interval.to_secs(); if interval > 1 << 16 { - regs.cr - .modify(|_, w| w.wucksel().variant(WUCKSEL_A::ClockSpareWithOffset)); + regs.cr() + .modify(|_, w| w.wucksel().variant(WUCKSEL::ClockSpareWithOffset)); let interval = u16::try_from(interval - (1 << 16) - 1) .expect("Interval was too large for wakeup timer"); - regs.wutr.write(|w| w.wut().bits(interval)); + regs.wutr().write(|w| w.wut().set(interval)); } else { - regs.cr - .modify(|_, w| w.wucksel().variant(WUCKSEL_A::ClockSpare)); + regs.cr() + .modify(|_, w| w.wucksel().variant(WUCKSEL::ClockSpare)); let interval = u16::try_from(interval - 1) .expect("Interval was too large for wakeup timer"); - regs.wutr.write(|w| w.wut().bits(interval)); + regs.wutr().write(|w| w.wut().set(interval)); } } - regs.cr.modify(|_, w| w.wute().set_bit()); + regs.cr().modify(|_, w| w.wute().set_bit()); }); } /// Disables the wakeup timer pub fn disable_wakeup(&mut self) { self.modify(false, |regs| { - regs.cr.modify(|_, w| w.wute().clear_bit()); - regs.isr.modify(|_, w| w.wutf().clear_bit()); + regs.cr().modify(|_, w| w.wute().clear_bit()); + regs.isr().modify(|_, w| w.wutf().clear_bit()); }); } /// Configures the timestamp to be captured when the RTC switches to Vbat power pub fn enable_vbat_timestamp(&mut self) { self.modify(false, |regs| { - regs.cr.modify(|_, w| w.tse().clear_bit()); - regs.isr.modify(|_, w| w.tsf().clear_bit()); - regs.cr.modify(|_, w| w.tse().set_bit()); + regs.cr().modify(|_, w| w.tse().clear_bit()); + regs.isr().modify(|_, w| w.tsf().clear_bit()); + regs.cr().modify(|_, w| w.tse().set_bit()); }); } /// Disables the timestamp pub fn disable_timestamp(&mut self) { self.modify(false, |regs| { - regs.cr.modify(|_, w| w.tse().clear_bit()); - regs.isr.modify(|_, w| w.tsf().clear_bit()); + regs.cr().modify(|_, w| w.tse().clear_bit()); + regs.isr().modify(|_, w| w.tsf().clear_bit()); }); } @@ -627,24 +623,22 @@ impl Rtc { /// /// Clears the timestamp interrupt flags. pub fn read_timestamp(&self) -> PrimitiveDateTime { - while self.regs.isr.read().rsf().bit_is_clear() {} + while self.regs.isr().read().rsf().bit_is_clear() {} // Timestamp doesn't include year, get it from the main calendar - let ss = self.regs.tsssr.read().ss().bits(); + let ss = self.regs.tsssr().read().ss().bits(); // TODO: remove unsafe after PAC update - let tr = &self.regs.tstr; - let tr = unsafe { (*(tr.as_ptr() as *const TR)).read() }; - let dr = &self.regs.tsdr; - let dr = unsafe { (*(dr.as_ptr() as *const DR)).read() }; - let dry = self.regs.dr.read(); + let tr = self.regs.tstr().read(); + let dr = self.regs.tsdr().read(); + let dry = self.regs.dr().read(); let seconds = decode_seconds(&tr); let minutes = decode_minutes(&tr); let hours = decode_hours(&tr); let day = decode_day(&dr); let month = decode_month(&dr); let year = decode_year(&dry); - let prediv_s = self.regs.prer.read().prediv_s().bits(); + let prediv_s = self.regs.prer().read().prediv_s().bits(); let nano = ss_to_nano(ss, prediv_s); PrimitiveDateTime::new( @@ -673,20 +667,20 @@ impl Rtc { self.modify(false, |rtc| { unsafe { - bb::clear(&rtc.cr, 8 + (alarm as u8)); - bb::clear(&rtc.isr, 8 + (alarm as u8)); + bb::clear(rtc.cr(), 8 + (alarm as u8)); + bb::clear(rtc.isr(), 8 + (alarm as u8)); } - while rtc.isr.read().bits() & (1 << (alarm as u32)) == 0 {} - let reg = &rtc.alrmr[alarm as usize]; + while rtc.isr().read().bits() & (1 << (alarm as u32)) == 0 {} + let reg = rtc.alrmr(alarm as usize); reg.modify(|_, w| { - w.dt().bits(dt); - w.du().bits(du); - w.ht().bits(ht); - w.hu().bits(hu); - w.mnt().bits(mnt); - w.mnu().bits(mnu); - w.st().bits(st); - w.su().bits(su); + w.dt().set(dt); + w.du().set(du); + w.ht().set(ht); + w.hu().set(hu); + w.mnt().set(mnt); + w.mnu().set(mnu); + w.st().set(st); + w.su().set(su); w.pm().clear_bit(); w.wdsel().bit(wdsel); w.msk4().bit(daymask) @@ -697,7 +691,7 @@ impl Rtc { // enable alarm and reenable interrupt if it was enabled unsafe { - bb::set(&rtc.cr, 8 + (alarm as u8)); + bb::set(rtc.cr(), 8 + (alarm as u8)); } }); Ok(()) @@ -711,24 +705,24 @@ impl Rtc { // EXTI 22 = RTC Wakeup Timer self.modify(false, |regs| match event { Event::AlarmA => { - exti.rtsr.modify(|_, w| w.tr17().enabled()); - exti.imr.modify(|_, w| w.mr17().set_bit()); - regs.cr.modify(|_, w| w.alraie().set_bit()); + exti.rtsr().modify(|_, w| w.tr17().enabled()); + exti.imr().modify(|_, w| w.mr17().set_bit()); + regs.cr().modify(|_, w| w.alraie().set_bit()); } Event::AlarmB => { - exti.rtsr.modify(|_, w| w.tr17().enabled()); - exti.imr.modify(|_, w| w.mr17().set_bit()); - regs.cr.modify(|_, w| w.alrbie().set_bit()); + exti.rtsr().modify(|_, w| w.tr17().enabled()); + exti.imr().modify(|_, w| w.mr17().set_bit()); + regs.cr().modify(|_, w| w.alrbie().set_bit()); } Event::Wakeup => { - exti.rtsr.modify(|_, w| w.tr22().enabled()); - exti.imr.modify(|_, w| w.mr22().set_bit()); - regs.cr.modify(|_, w| w.wutie().set_bit()); + exti.rtsr().modify(|_, w| w.tr22().enabled()); + exti.imr().modify(|_, w| w.mr22().set_bit()); + regs.cr().modify(|_, w| w.wutie().set_bit()); } Event::Timestamp => { - exti.rtsr.modify(|_, w| w.tr21().enabled()); - exti.imr.modify(|_, w| w.mr21().set_bit()); - regs.cr.modify(|_, w| w.tsie().set_bit()); + exti.rtsr().modify(|_, w| w.tr21().enabled()); + exti.imr().modify(|_, w| w.mr21().set_bit()); + regs.cr().modify(|_, w| w.tsie().set_bit()); } }); } @@ -738,24 +732,24 @@ impl Rtc { // See the note in listen() about EXTI self.modify(false, |regs| match event { Event::AlarmA => { - regs.cr.modify(|_, w| w.alraie().clear_bit()); - exti.imr.modify(|_, w| w.mr17().clear_bit()); - exti.rtsr.modify(|_, w| w.tr17().disabled()); + regs.cr().modify(|_, w| w.alraie().clear_bit()); + exti.imr().modify(|_, w| w.mr17().clear_bit()); + exti.rtsr().modify(|_, w| w.tr17().disabled()); } Event::AlarmB => { - regs.cr.modify(|_, w| w.alrbie().clear_bit()); - exti.imr.modify(|_, w| w.mr17().clear_bit()); - exti.rtsr.modify(|_, w| w.tr17().disabled()); + regs.cr().modify(|_, w| w.alrbie().clear_bit()); + exti.imr().modify(|_, w| w.mr17().clear_bit()); + exti.rtsr().modify(|_, w| w.tr17().disabled()); } Event::Wakeup => { - regs.cr.modify(|_, w| w.wutie().clear_bit()); - exti.imr.modify(|_, w| w.mr22().clear_bit()); - exti.rtsr.modify(|_, w| w.tr22().disabled()); + regs.cr().modify(|_, w| w.wutie().clear_bit()); + exti.imr().modify(|_, w| w.mr22().clear_bit()); + exti.rtsr().modify(|_, w| w.tr22().disabled()); } Event::Timestamp => { - regs.cr.modify(|_, w| w.tsie().clear_bit()); - exti.imr.modify(|_, w| w.mr21().clear_bit()); - exti.rtsr.modify(|_, w| w.tr21().disabled()); + regs.cr().modify(|_, w| w.tsie().clear_bit()); + exti.imr().modify(|_, w| w.mr21().clear_bit()); + exti.rtsr().modify(|_, w| w.tr21().disabled()); } }); } @@ -763,10 +757,10 @@ impl Rtc { /// Returns `true` if `event` is pending pub fn is_pending(&self, event: Event) -> bool { match event { - Event::AlarmA => self.regs.isr.read().alraf().bit_is_set(), - Event::AlarmB => self.regs.isr.read().alrbf().bit_is_set(), - Event::Wakeup => self.regs.isr.read().wutf().bit_is_set(), - Event::Timestamp => self.regs.isr.read().tsf().bit_is_set(), + Event::AlarmA => self.regs.isr().read().alraf().bit_is_set(), + Event::AlarmB => self.regs.isr().read().alrbf().bit_is_set(), + Event::Wakeup => self.regs.isr().read().wutf().bit_is_set(), + Event::Timestamp => self.regs.isr().read().tsf().bit_is_set(), } } @@ -774,20 +768,36 @@ impl Rtc { pub fn clear_interrupt(&mut self, event: Event) { match event { Event::AlarmA => { - self.regs.isr.modify(|_, w| w.alraf().clear_bit()); - unsafe { (*pac::EXTI::ptr()).pr.write(|w| w.pr17().set_bit()) }; + self.regs.isr().modify(|_, w| w.alraf().clear_bit()); + unsafe { + (*pac::EXTI::ptr()) + .pr() + .write(|w| w.pr17().clear_bit_by_one()) + }; } Event::AlarmB => { - self.regs.isr.modify(|_, w| w.alrbf().clear_bit()); - unsafe { (*pac::EXTI::ptr()).pr.write(|w| w.pr17().set_bit()) }; + self.regs.isr().modify(|_, w| w.alrbf().clear_bit()); + unsafe { + (*pac::EXTI::ptr()) + .pr() + .write(|w| w.pr17().clear_bit_by_one()) + }; } Event::Wakeup => { - self.regs.isr.modify(|_, w| w.wutf().clear_bit()); - unsafe { (*pac::EXTI::ptr()).pr.write(|w| w.pr22().set_bit()) }; + self.regs.isr().modify(|_, w| w.wutf().clear_bit()); + unsafe { + (*pac::EXTI::ptr()) + .pr() + .write(|w| w.pr22().clear_bit_by_one()) + }; } Event::Timestamp => { - self.regs.isr.modify(|_, w| w.tsf().clear_bit()); - unsafe { (*pac::EXTI::ptr()).pr.write(|w| w.pr21().set_bit()) }; + self.regs.isr().modify(|_, w| w.tsf().clear_bit()); + unsafe { + (*pac::EXTI::ptr()) + .pr() + .write(|w| w.pr21().clear_bit_by_one()) + }; } } } diff --git a/src/sdio.rs b/src/sdio.rs index a24bc818c..67a2b6b00 100644 --- a/src/sdio.rs +++ b/src/sdio.rs @@ -175,26 +175,19 @@ impl Sdio

{ } // Configure clock - sdio.clkcr.write(|w| { - w.widbus() - .bus_width1() - .clken() - .enabled() - .clkdiv() - .bits(ClockFreq::F400Khz as u8) - .pwrsav() - .disabled() - .bypass() - .disabled() - .negedge() - .rising() - // Do not use hardware flow control. - // Using it causes clock glitches and CRC errors. - // See chip errata SDIO section: - // - F42x/F43x: https://www.st.com/resource/en/errata_sheet/es0206-stm32f427437-and-stm32f429439-line-limitations-stmicroelectronics.pdf - // - F40x/F41x: https://www.st.com/resource/en/errata_sheet/es0182-stm32f405407xx-and-stm32f415417xx-device-limitations-stmicroelectronics.pdf - .hwfc_en() - .disabled() + sdio.clkcr().write(|w| { + w.widbus().bus_width1(); + w.clken().enabled(); + w.clkdiv().set(ClockFreq::F400Khz as u8); + w.pwrsav().disabled(); + w.bypass().disabled(); + w.negedge().rising(); + // Do not use hardware flow control. + // Using it causes clock glitches and CRC errors. + // See chip errata SDIO section: + // - F42x/F43x: https://www.st.com/resource/en/errata_sheet/es0206-stm32f427437-and-stm32f429439-line-limitations-stmicroelectronics.pdf + // - F40x/F41x: https://www.st.com/resource/en/errata_sheet/es0182-stm32f405407xx-and-stm32f415417xx-device-limitations-stmicroelectronics.pdf + w.hwfc_en().disabled() }); let _pins = pins.convert(); @@ -212,13 +205,13 @@ impl Sdio

{ } fn power_card(&mut self, on: bool) { - use crate::pac::sdio::power::PWRCTRL_A; + use crate::pac::sdio::power::PWRCTRL; - self.sdio.power.modify(|_, w| { + self.sdio.power().modify(|_, w| { w.pwrctrl().variant(if on { - PWRCTRL_A::PowerOn + PWRCTRL::PowerOn } else { - PWRCTRL_A::PowerOff + PWRCTRL::PowerOff }) }); @@ -248,7 +241,7 @@ impl Sdio

{ let mut i = 0; let status = loop { - let sta = self.sdio.sta.read(); + let sta = self.sdio.sta().read(); if sta.rxact().bit_is_clear() { break sta; @@ -256,7 +249,7 @@ impl Sdio

{ if sta.rxfifohf().bit() { for _ in 0..8 { - let bytes = self.sdio.fifo.read().bits().to_le_bytes(); + let bytes = self.sdio.fifo().read().bits().to_le_bytes(); block[i..i + 4].copy_from_slice(&bytes); i += 4; } @@ -292,7 +285,7 @@ impl Sdio

{ let mut i = 0; let status = loop { - let sta = self.sdio.sta.read(); + let sta = self.sdio.sta().read(); if sta.txact().bit_is_clear() { break sta; @@ -303,7 +296,7 @@ impl Sdio

{ let mut wb = [0u8; 4]; wb.copy_from_slice(&block[i..i + 4]); let word = u32::from_le_bytes(wb); - self.sdio.fifo.write(|w| w.bits(word)); + self.sdio.fifo().write(|w| w.set(word)); i += 4; } } @@ -317,7 +310,7 @@ impl Sdio

{ // Wait for SDIO module to finish transmitting data loop { - let sta = self.sdio.sta.read(); + let sta = self.sdio.sta().read(); if !sta.txact().bit_is_set() { break; } @@ -330,14 +323,14 @@ impl Sdio

{ } fn start_datapath_transfer(&self, length_bytes: u32, block_size: u8, card_to_controller: bool) { - use crate::pac::sdio::dctrl::DTDIR_A; + use crate::pac::sdio::dctrl::DTDIR; // Block Size up to 2^14 bytes assert!(block_size <= 14); // Command AND Data state machines must be idle loop { - let status = self.sdio.sta.read(); + let status = self.sdio.sta().read(); if status.cmdact().bit_is_clear() && status.rxact().bit_is_clear() @@ -348,23 +341,20 @@ impl Sdio

{ } let dtdir = if card_to_controller { - DTDIR_A::CardToController + DTDIR::CardToController } else { - DTDIR_A::ControllerToCard + DTDIR::ControllerToCard }; // Data timeout, in bus cycles - self.sdio.dtimer.write(|w| w.datatime().bits(0xFFFF_FFFF)); + self.sdio.dtimer().write(|w| w.datatime().set(0xFFFF_FFFF)); // Data length, in bytes - self.sdio.dlen.write(|w| w.datalength().bits(length_bytes)); + self.sdio.dlen().write(|w| w.datalength().set(length_bytes)); // Transfer - self.sdio.dctrl.write(|w| { - w.dblocksize() - .bits(block_size) // 2^n bytes block size - .dtdir() - .variant(dtdir) - .dten() - .enabled() // Enable transfer + self.sdio.dctrl().write(|w| { + w.dblocksize().set(block_size); // 2^n bytes block size + w.dtdir().variant(dtdir); + w.dten().enabled() // Enable transfer }); } @@ -374,7 +364,7 @@ impl Sdio

{ self.cmd(common_cmd::card_status(card.get_address(), false))?; - let r1 = self.sdio.resp1.read().bits(); + let r1 = self.sdio.resp1().read().bits(); Ok(CardStatus::from(r1)) } @@ -400,34 +390,30 @@ impl Sdio

{ /// Send command to card fn cmd(&self, cmd: Cmd) -> Result<(), Error> { - use crate::pac::sdio::cmd::WAITRESP_A; + use crate::pac::sdio::cmd::WAITRESP; // Command state machines must be idle - while self.sdio.sta.read().cmdact().bit_is_set() {} + while self.sdio.sta().read().cmdact().bit_is_set() {} // Clear the interrupts before we start - clear_all_interrupts(&self.sdio.icr); + clear_all_interrupts(self.sdio.icr()); // Command arg - self.sdio.arg.write(|w| w.cmdarg().bits(cmd.arg)); + self.sdio.arg().write(|w| w.cmdarg().set(cmd.arg)); // Determine what kind of response the CPSM should wait for let waitresp = match cmd.response_len() { - ResponseLen::Zero => WAITRESP_A::NoResponse, - ResponseLen::R48 => WAITRESP_A::ShortResponse, - ResponseLen::R136 => WAITRESP_A::LongResponse, + ResponseLen::Zero => WAITRESP::NoResponse, + ResponseLen::R48 => WAITRESP::ShortResponse, + ResponseLen::R136 => WAITRESP::LongResponse, }; // Send the command - self.sdio.cmd.write(|w| { - w.waitresp() - .variant(waitresp) - .cmdindex() - .bits(cmd.cmd) - .waitint() - .disabled() - .cpsmen() - .enabled() + self.sdio.cmd().write(|w| { + w.waitresp().variant(waitresp); + w.cmdindex().set(cmd.cmd); + w.waitint().disabled(); + w.cpsmen().enabled() }); let mut timeout: u32 = 0xFFFF_FFFF; @@ -435,7 +421,7 @@ impl Sdio

{ let status = if cmd.response_len() == ResponseLen::Zero { // Wait for command sent or a timeout loop { - let sta = self.sdio.sta.read(); + let sta = self.sdio.sta().read(); if sta.cmdact().bit_is_clear() && (sta.ctimeout().bit_is_set() || sta.cmdsent().bit_is_set()) @@ -451,7 +437,7 @@ impl Sdio

{ } } else { loop { - let sta = self.sdio.sta.read(); + let sta = self.sdio.sta().read(); if sta.cmdact().bit_is_clear() && (sta.ctimeout().bit() @@ -480,13 +466,13 @@ impl Sdio { self.power_card(true); // Enable clock - self.sdio.clkcr.modify(|_, w| w.clken().enabled()); + self.sdio.clkcr().modify(|_, w| w.clken().enabled()); // Send card to idle state self.cmd(common_cmd::idle())?; // Check if cards supports CMD 8 (with pattern) self.cmd(sd_cmd::send_if_cond(1, 0xAA))?; - let cic = CIC::from(self.sdio.resp1.read().bits()); + let cic = CIC::from(self.sdio.resp1().read().bits()); // If card did't echo back the pattern, we do not have a v2 card if cic.pattern() != 0xAA { @@ -507,7 +493,7 @@ impl Sdio { Err(Error::Crc) => (), Err(err) => return Err(err), } - let ocr = OCR::from(self.sdio.resp1.read().bits()); + let ocr = OCR::from(self.sdio.resp1().read().bits()); if ocr.is_busy() { // Still powering up continue; @@ -525,25 +511,25 @@ impl Sdio { // Get CID self.cmd(common_cmd::all_send_cid())?; let mut cid = [0; 4]; - cid[3] = self.sdio.resp1.read().bits(); - cid[2] = self.sdio.resp2.read().bits(); - cid[1] = self.sdio.resp3.read().bits(); - cid[0] = self.sdio.resp4.read().bits(); + cid[3] = self.sdio.resp1().read().bits(); + cid[2] = self.sdio.resp2().read().bits(); + cid[1] = self.sdio.resp3().read().bits(); + cid[0] = self.sdio.resp4().read().bits(); let cid = CID::from(cid); // Get RCA self.cmd(sd_cmd::send_relative_address())?; - let rca = RCA::from(self.sdio.resp1.read().bits()); + let rca = RCA::from(self.sdio.resp1().read().bits()); let card_addr = rca.address(); // Get CSD self.cmd(common_cmd::send_csd(card_addr))?; let mut csd = [0; 4]; - csd[3] = self.sdio.resp1.read().bits(); - csd[2] = self.sdio.resp2.read().bits(); - csd[1] = self.sdio.resp3.read().bits(); - csd[0] = self.sdio.resp4.read().bits(); + csd[3] = self.sdio.resp1().read().bits(); + csd[2] = self.sdio.resp2().read().bits(); + csd[1] = self.sdio.resp3().read().bits(); + csd[0] = self.sdio.resp4().read().bits(); let csd = CSD::from(csd); self.select_card(card_addr)?; @@ -578,7 +564,7 @@ impl Sdio { let mut idx = 0; let s = loop { - let sta = self.sdio.sta.read(); + let sta = self.sdio.sta().read(); if sta.rxact().bit_is_clear() { break sta; @@ -586,7 +572,7 @@ impl Sdio { if sta.rxfifohf().bit() { for _ in 0..8 { - status[15 - idx] = self.sdio.fifo.read().bits().swap_bytes(); + status[15 - idx] = self.sdio.fifo().read().bits().swap_bytes(); idx += 1; } } @@ -611,14 +597,14 @@ impl Sdio { let mut i = 0; let status = loop { - let sta = self.sdio.sta.read(); + let sta = self.sdio.sta().read(); if sta.rxact().bit_is_clear() { break sta; } if sta.rxdavl().bit() { - buf[1 - i] = self.sdio.fifo.read().bits().swap_bytes(); + buf[1 - i] = self.sdio.fifo().read().bits().swap_bytes(); i += 1; } @@ -633,25 +619,22 @@ impl Sdio { /// Set bus width and clock frequency fn set_bus(&self, width: Buswidth, freq: ClockFreq) -> Result<(), Error> { - use crate::pac::sdio::clkcr::WIDBUS_A; + use crate::pac::sdio::clkcr::WIDBUS; let card_widebus = self.card()?.supports_widebus(); let width = match width { - Buswidth::Buswidth4 if card_widebus => WIDBUS_A::BusWidth4, + Buswidth::Buswidth4 if card_widebus => WIDBUS::BusWidth4, // Buswidth8 is not supported for SD cards - _ => WIDBUS_A::BusWidth1, + _ => WIDBUS::BusWidth1, }; - self.app_cmd(sd_cmd::set_bus_width(width == WIDBUS_A::BusWidth4))?; + self.app_cmd(sd_cmd::set_bus_width(width == WIDBUS::BusWidth4))?; - self.sdio.clkcr.modify(|_, w| { - w.clkdiv() - .bits(freq as u8) - .widbus() - .variant(width) - .clken() - .enabled() + self.sdio.clkcr().modify(|_, w| { + w.clkdiv().set(freq as u8); + w.widbus().variant(width); + w.clken().enabled() }); Ok(()) } @@ -666,7 +649,7 @@ impl Sdio { self.power_card(true); // Enable clock - self.sdio.clkcr.modify(|_, w| w.clken().enabled()); + self.sdio.clkcr().modify(|_, w| w.clken().enabled()); // Send card to idle state self.cmd(common_cmd::idle())?; @@ -680,7 +663,7 @@ impl Sdio { Err(Error::Crc) => (), Err(err) => return Err(err), }; - let ocr = OCR::::from(self.sdio.resp1.read().bits()); + let ocr = OCR::::from(self.sdio.resp1().read().bits()); if !ocr.is_busy() { break ocr; } @@ -689,10 +672,10 @@ impl Sdio { // Get CID self.cmd(common_cmd::all_send_cid())?; let mut cid = [0; 4]; - cid[3] = self.sdio.resp1.read().bits(); - cid[2] = self.sdio.resp2.read().bits(); - cid[1] = self.sdio.resp3.read().bits(); - cid[0] = self.sdio.resp4.read().bits(); + cid[3] = self.sdio.resp1().read().bits(); + cid[2] = self.sdio.resp2().read().bits(); + cid[1] = self.sdio.resp3().read().bits(); + cid[0] = self.sdio.resp4().read().bits(); let cid = CID::::from(cid); self.cmd(emmc_cmd::assign_relative_address(card_addr.address()))?; @@ -700,10 +683,10 @@ impl Sdio { self.cmd(common_cmd::send_csd(card_addr.address()))?; let mut csd = [0; 4]; - csd[3] = self.sdio.resp1.read().bits(); - csd[2] = self.sdio.resp2.read().bits(); - csd[1] = self.sdio.resp3.read().bits(); - csd[0] = self.sdio.resp4.read().bits(); + csd[3] = self.sdio.resp1().read().bits(); + csd[2] = self.sdio.resp2().read().bits(); + csd[1] = self.sdio.resp3().read().bits(); + csd[0] = self.sdio.resp4().read().bits(); let csd = CSD::::from(csd); self.select_card(card_addr.address())?; @@ -725,7 +708,7 @@ impl Sdio { } pub fn set_bus(&mut self, width: Buswidth, freq: ClockFreq) -> Result<(), Error> { - use crate::pac::sdio::clkcr::WIDBUS_A; + use crate::pac::sdio::clkcr::WIDBUS; // Use access mode 0b11 to write a value of 0x02 to byte 183. Cmd Set is 0 (not used). self.cmd(emmc_cmd::modify_ext_csd( @@ -735,20 +718,17 @@ impl Sdio { ))?; let width = match width { - Buswidth::Buswidth1 => WIDBUS_A::BusWidth1, - Buswidth::Buswidth4 => WIDBUS_A::BusWidth4, - Buswidth::Buswidth8 => WIDBUS_A::BusWidth8, + Buswidth::Buswidth1 => WIDBUS::BusWidth1, + Buswidth::Buswidth4 => WIDBUS::BusWidth4, + Buswidth::Buswidth8 => WIDBUS::BusWidth8, }; // CMD6 is R1b, so wait for the card to be ready again before proceeding. while !self.card_ready()? {} - self.sdio.clkcr.modify(|_, w| { - w.clkdiv() - .bits(freq as u8) - .widbus() - .variant(width) - .clken() - .enabled() + self.sdio.clkcr().modify(|_, w| { + w.clkdiv().set(freq as u8); + w.widbus().variant(width); + w.clken().enabled() }); Ok(()) } @@ -773,32 +753,19 @@ fn status_to_error(sta: pac::sdio::sta::R) -> Result<(), Error> { fn clear_all_interrupts(icr: &pac::sdio::ICR) { icr.modify(|_, w| { - w.ccrcfailc() - .set_bit() - .ctimeoutc() - .set_bit() - .ceataendc() - .set_bit() - .cmdrendc() - .set_bit() - .cmdsentc() - .set_bit() - .dataendc() - .set_bit() - .dbckendc() - .set_bit() - .dcrcfailc() - .set_bit() - .dtimeoutc() - .set_bit() - .sdioitc() - .set_bit() - .stbiterrc() - .set_bit() - .rxoverrc() - .set_bit() - .txunderrc() - .set_bit() + w.ccrcfailc().set_bit(); + w.ctimeoutc().set_bit(); + w.ceataendc().set_bit(); + w.cmdrendc().set_bit(); + w.cmdsentc().set_bit(); + w.dataendc().set_bit(); + w.dbckendc().set_bit(); + w.dcrcfailc().set_bit(); + w.dtimeoutc().set_bit(); + w.sdioitc().set_bit(); + w.stbiterrc().set_bit(); + w.rxoverrc().set_bit(); + w.txunderrc().set_bit() }); } diff --git a/src/serial.rs b/src/serial.rs index ce4a93671..77e4f6098 100644 --- a/src/serial.rs +++ b/src/serial.rs @@ -263,15 +263,15 @@ macro_rules! halUsart { } fn set_stopbits(&self, bits: config::StopBits) { - use crate::pac::usart1::cr2::STOP_A; + use crate::pac::usart1::cr2::STOP; use config::StopBits; - self.cr2.write(|w| { + self.cr2().write(|w| { w.stop().variant(match bits { - StopBits::STOP0P5 => STOP_A::Stop0p5, - StopBits::STOP1 => STOP_A::Stop1, - StopBits::STOP1P5 => STOP_A::Stop1p5, - StopBits::STOP2 => STOP_A::Stop2, + StopBits::STOP0P5 => STOP::Stop0p5, + StopBits::STOP1 => STOP::Stop1, + StopBits::STOP1P5 => STOP::Stop1p5, + StopBits::STOP2 => STOP::Stop2, }) }); } diff --git a/src/serial/uart_impls.rs b/src/serial/uart_impls.rs index 782c98928..3cc02b38d 100644 --- a/src/serial/uart_impls.rs +++ b/src/serial/uart_impls.rs @@ -211,16 +211,16 @@ macro_rules! uartCommon { }; let register_block = unsafe { &*UART::ptr() }; - register_block.brr.write(|w| unsafe { w.bits(div) }); + register_block.brr().write(|w| unsafe { w.bits(div) }); // Reset other registers to disable advanced USART features - register_block.cr2.reset(); - register_block.cr3.reset(); + register_block.cr2().reset(); + register_block.cr3().reset(); // Enable transmission and receiving // and configure frame - register_block.cr1.write(|w| { + register_block.cr1().write(|w| { w.ue().set_bit(); w.over8().bit(over8); w.te().set_bit(); @@ -231,10 +231,10 @@ macro_rules! uartCommon { }); match config.dma { - DmaConfig::Tx => register_block.cr3.write(|w| w.dmat().enabled()), - DmaConfig::Rx => register_block.cr3.write(|w| w.dmar().enabled()), + DmaConfig::Tx => register_block.cr3().write(|w| w.dmat().enabled()), + DmaConfig::Rx => register_block.cr3().write(|w| w.dmar().enabled()), DmaConfig::TxRx => register_block - .cr3 + .cr3() .write(|w| w.dmar().enabled().dmat().enabled()), DmaConfig::None => {} } @@ -249,7 +249,7 @@ macro_rules! uartCommon { fn read_u16(&self) -> nb::Result { // NOTE(unsafe) atomic read with no side effects - let sr = self.sr.read(); + let sr = self.sr().read(); // Any error requires the dr to be read to clear if sr.pe().bit_is_set() @@ -257,7 +257,7 @@ macro_rules! uartCommon { || sr.nf().bit_is_set() || sr.ore().bit_is_set() { - self.dr.read(); + self.dr().read(); } Err(if sr.pe().bit_is_set() { @@ -270,7 +270,7 @@ macro_rules! uartCommon { Error::Overrun.into() } else if sr.rxne().bit_is_set() { // NOTE(unsafe) atomic read from stateless register - return Ok(self.dr.read().dr().bits()); + return Ok(self.dr().read().dr().bits()); } else { nb::Error::WouldBlock }) @@ -278,11 +278,11 @@ macro_rules! uartCommon { fn write_u16(&self, word: u16) -> nb::Result<(), Error> { // NOTE(unsafe) atomic read with no side effects - let sr = self.sr.read(); + let sr = self.sr().read(); if sr.txe().bit_is_set() { // NOTE(unsafe) atomic write to stateless register - self.dr.write(|w| w.dr().bits(word)); + self.dr().write(|w| w.dr().set(word)); Ok(()) } else { Err(nb::Error::WouldBlock) @@ -291,7 +291,7 @@ macro_rules! uartCommon { fn flush(&self) -> nb::Result<(), Error> { // NOTE(unsafe) atomic read with no side effects - let sr = self.sr.read(); + let sr = self.sr().read(); if sr.tc().bit_is_set() { Ok(()) @@ -301,21 +301,22 @@ macro_rules! uartCommon { } fn flags(&self) -> BitFlags { - BitFlags::from_bits_truncate(self.sr.read().bits()) + BitFlags::from_bits_truncate(self.sr().read().bits()) } fn clear_flags(&self, flags: BitFlags) { - self.sr.write(|w| unsafe { w.bits(0xffff & !flags.bits()) }); + self.sr() + .write(|w| unsafe { w.bits(0xffff & !flags.bits()) }); } fn clear_idle_interrupt(&self) { - let _ = self.sr.read(); - let _ = self.dr.read(); + let _ = self.sr().read(); + let _ = self.dr().read(); } fn check_and_clear_error_flags(&self) -> Result<(), Error> { - let sr = self.sr.read(); - let _ = self.dr.read(); + let sr = self.sr().read(); + let _ = self.dr().read(); if sr.ore().bit_is_set() { Err(Error::Overrun) @@ -331,11 +332,11 @@ macro_rules! uartCommon { } fn enable_error_interrupt_generation(&self) { - self.cr3.modify(|_, w| w.eie().enabled()); + self.cr3().modify(|_, w| w.eie().enabled()); } fn disable_error_interrupt_generation(&self) { - self.cr3.modify(|_, w| w.eie().disabled()); + self.cr3().modify(|_, w| w.eie().disabled()); } fn listen_event( @@ -343,7 +344,7 @@ macro_rules! uartCommon { disable: Option>, enable: Option>, ) { - self.cr1.modify(|r, w| unsafe { + self.cr1().modify(|r, w| unsafe { w.bits({ let mut bits = r.bits(); if let Some(d) = disable { @@ -358,7 +359,7 @@ macro_rules! uartCommon { } fn peri_address(&self) -> u32 { - self.dr.as_ptr() as u32 + self.dr().as_ptr() as u32 } } }; diff --git a/src/spi.rs b/src/spi.rs index ffa305d8a..b700fbe1f 100644 --- a/src/spi.rs +++ b/src/spi.rs @@ -358,7 +358,7 @@ impl SpiExt for SPI { impl Spi { pub fn init(self) -> Self { - self.spi.cr1.modify(|_, w| { + self.spi.cr1().modify(|_, w| { // bidimode: 2-line or 1-line unidirectional w.bidimode().bit(BIDI); w.bidioe().bit(BIDI); @@ -374,7 +374,7 @@ impl Spi { impl SpiSlave { pub fn init(self) -> Self { - self.spi.cr1.modify(|_, w| { + self.spi.cr1().modify(|_, w| { // bidimode: 2-line or 1-line unidirectional w.bidimode().bit(BIDI); w.bidioe().bit(BIDI); @@ -615,7 +615,7 @@ impl Spi { /// Pre initializing the SPI bus. fn pre_init(self, mode: Mode, freq: Hertz, clock: Hertz) -> Self { // disable SS output - self.spi.cr2.write(|w| w.ssoe().clear_bit()); + self.spi.cr2().write(|w| w.ssoe().clear_bit()); let br = match clock.raw() / freq.raw() { 0 => unreachable!(), @@ -629,12 +629,12 @@ impl Spi { _ => 0b111, }; - self.spi.cr1.write(|w| { + self.spi.cr1().write(|w| { w.cpha().bit(mode.phase == Phase::CaptureOnSecondTransition); w.cpol().bit(mode.polarity == Polarity::IdleHigh); // mstr: master configuration w.mstr().set_bit(); - w.br().bits(br); + w.br().set(br); // lsbfirst: MSB first w.lsbfirst().clear_bit(); // ssm: enable software slave management (NSS pin free for other uses) @@ -653,12 +653,12 @@ impl Spi { impl SpiSlave { /// Pre initializing the SPI bus. fn pre_init(self, mode: Mode) -> Self { - self.spi.cr1.write(|w| { + self.spi.cr1().write(|w| { w.cpha().bit(mode.phase == Phase::CaptureOnSecondTransition); w.cpol().bit(mode.polarity == Polarity::IdleHigh); // mstr: slave configuration w.mstr().clear_bit(); - w.br().bits(0); + w.br().set(0); // lsbfirst: MSB first w.lsbfirst().clear_bit(); // ssm: enable software slave management (NSS pin free for other uses) @@ -676,7 +676,7 @@ impl SpiSlave { /// Set the slave select bit programmatically. #[inline] pub fn set_internal_nss(&mut self, value: bool) { - self.spi.cr1.modify(|_, w| w.ssi().bit(value)); + self.spi.cr1().modify(|_, w| w.ssi().bit(value)); } } @@ -687,7 +687,7 @@ impl Inner { /// Enable/disable spi pub fn enable(&mut self, enable: bool) { - self.spi.cr1.modify(|_, w| { + self.spi.cr1().modify(|_, w| { // spe: enable the SPI bus w.spe().bit(enable) }); @@ -696,7 +696,7 @@ impl Inner { /// Select which frame format is used for data transfers pub fn bit_format(&mut self, format: BitFormat) { self.spi - .cr1 + .cr1() .modify(|_, w| w.lsbfirst().bit(format == BitFormat::LsbFirst)); } @@ -704,62 +704,62 @@ impl Inner { /// can be written to the SPI. #[inline] pub fn is_tx_empty(&self) -> bool { - self.spi.sr.read().txe().bit_is_set() + self.spi.sr().read().txe().bit_is_set() } /// Return `true` if the RXNE flag is set, i.e. new data has been received /// and can be read from the SPI. #[inline] pub fn is_rx_not_empty(&self) -> bool { - self.spi.sr.read().rxne().bit_is_set() + self.spi.sr().read().rxne().bit_is_set() } /// Return `true` if the MODF flag is set, i.e. the SPI has experienced a /// Master Mode Fault. (see chapter 28.3.10 of the STM32F4 Reference Manual) #[inline] pub fn is_modf(&self) -> bool { - self.spi.sr.read().modf().bit_is_set() + self.spi.sr().read().modf().bit_is_set() } /// Returns true if the transfer is in progress #[inline] pub fn is_busy(&self) -> bool { - self.spi.sr.read().bsy().bit_is_set() + self.spi.sr().read().bsy().bit_is_set() } /// Return `true` if the OVR flag is set, i.e. new data has been received /// while the receive data register was already filled. #[inline] pub fn is_overrun(&self) -> bool { - self.spi.sr.read().ovr().bit_is_set() + self.spi.sr().read().ovr().bit_is_set() } #[inline] fn bidi_output(&mut self) { - self.spi.cr1.modify(|_, w| w.bidioe().set_bit()); + self.spi.cr1().modify(|_, w| w.bidioe().set_bit()); } #[inline] fn bidi_input(&mut self) { - self.spi.cr1.modify(|_, w| w.bidioe().set_bit()); + self.spi.cr1().modify(|_, w| w.bidioe().set_bit()); } fn read_data_reg(&mut self) -> W { // NOTE(read_volatile) read only 1 byte (the svd2rust API only allows // reading a half-word) - unsafe { (*(&self.spi.dr as *const pac::spi1::DR).cast::>()).get() } + unsafe { (*(self.spi.dr() as *const pac::spi1::DR).cast::>()).get() } } fn write_data_reg(&mut self, data: W) { // NOTE(write_volatile) see note above unsafe { - (*(&self.spi.dr as *const pac::spi1::DR).cast::>()).set(data) + (*(self.spi.dr() as *const pac::spi1::DR).cast::>()).set(data) } } #[inline(always)] fn check_read(&mut self) -> nb::Result { - let sr = self.spi.sr.read(); + let sr = self.spi.sr().read(); Err(if sr.ovr().bit_is_set() { Error::Overrun.into() @@ -776,19 +776,19 @@ impl Inner { #[inline(always)] fn check_send(&mut self, byte: W) -> nb::Result<(), Error> { - let sr = self.spi.sr.read(); + let sr = self.spi.sr().read(); Err(if sr.ovr().bit_is_set() { // Read from the DR to clear the OVR bit - let _ = self.spi.dr.read(); + let _ = self.spi.dr().read(); Error::Overrun.into() } else if sr.modf().bit_is_set() { // Write to CR1 to clear MODF - self.spi.cr1.modify(|_r, w| w); + self.spi.cr1().modify(|_r, w| w); Error::ModeFault.into() } else if sr.crcerr().bit_is_set() { // Clear the CRCERR bit - self.spi.sr.modify(|_r, w| w.crcerr().clear_bit()); + self.spi.sr().modify(|_r, w| w.crcerr().clear_bit()); Error::Crc.into() } else if sr.txe().bit_is_set() { self.write_data_reg(byte); @@ -798,7 +798,7 @@ impl Inner { }) } fn listen_event(&mut self, disable: Option>, enable: Option>) { - self.spi.cr2.modify(|r, w| unsafe { + self.spi.cr2().modify(|r, w| unsafe { w.bits({ let mut bits = r.bits(); if let Some(d) = disable { @@ -834,7 +834,7 @@ impl crate::ClearFlags for Inner { fn clear_flags(&mut self, flags: impl Into>) { if flags.into().contains(CFlag::CrcError) { self.spi - .sr + .sr() .write(|w| unsafe { w.bits(0xffff).crcerr().clear_bit() }) } } @@ -843,7 +843,7 @@ impl crate::ClearFlags for Inner { impl crate::ReadFlags for Inner { type Flag = Flag; fn flags(&self) -> BitFlags { - BitFlags::from_bits_truncate(self.spi.sr.read().bits()) + BitFlags::from_bits_truncate(self.spi.sr().read().bits()) } } @@ -879,17 +879,17 @@ pub struct Rx { impl DmaBuilder { pub fn tx(self) -> Tx { - self.spi.cr2.modify(|_, w| w.txdmaen().enabled()); + self.spi.cr2().modify(|_, w| w.txdmaen().enabled()); Tx { spi: PhantomData } } pub fn rx(self) -> Rx { - self.spi.cr2.modify(|_, w| w.rxdmaen().enabled()); + self.spi.cr2().modify(|_, w| w.rxdmaen().enabled()); Rx { spi: PhantomData } } pub fn txrx(self) -> (Tx, Rx) { - self.spi.cr2.modify(|_, w| { + self.spi.cr2().modify(|_, w| { w.txdmaen().enabled(); w.rxdmaen().enabled() }); @@ -900,7 +900,7 @@ impl DmaBuilder { unsafe impl PeriAddress for Rx { #[inline(always)] fn address(&self) -> u32 { - unsafe { (*SPI::ptr()).dr.as_ptr() as u32 } + unsafe { (*SPI::ptr()).dr().as_ptr() as u32 } } type MemSize = u8; @@ -914,7 +914,7 @@ unsafe impl DMASet PeriAddress for Tx { #[inline(always)] fn address(&self) -> u32 { - unsafe { (*SPI::ptr()).dr.as_ptr() as u32 } + unsafe { (*SPI::ptr()).dr().as_ptr() as u32 } } type MemSize = u8; diff --git a/src/timer.rs b/src/timer.rs index 479c85671..bdbf581aa 100644 --- a/src/timer.rs +++ b/src/timer.rs @@ -400,7 +400,7 @@ macro_rules! hal { } #[inline(always)] unsafe fn set_auto_reload_unchecked(&mut self, arr: u32) { - self.arr.write(|w| w.bits(arr)) + self.arr().write(|w| w.bits(arr)) } #[inline(always)] fn set_auto_reload(&mut self, arr: u32) -> Result<(), Error> { @@ -415,41 +415,41 @@ macro_rules! hal { #[inline(always)] fn read_auto_reload() -> u32 { let tim = unsafe { &*<$TIM>::ptr() }; - tim.arr.read().bits() + tim.arr().read().bits() } #[inline(always)] fn enable_preload(&mut self, b: bool) { - self.cr1.modify(|_, w| w.arpe().bit(b)); + self.cr1().modify(|_, w| w.arpe().bit(b)); } #[inline(always)] fn enable_counter(&mut self, b: bool) { - self.cr1.modify(|_, w| w.cen().bit(b)); + self.cr1().modify(|_, w| w.cen().bit(b)); } #[inline(always)] fn is_counter_enabled(&self) -> bool { - self.cr1.read().cen().is_enabled() + self.cr1().read().cen().is_enabled() } #[inline(always)] fn reset_counter(&mut self) { - self.cnt.reset(); + self.cnt().reset(); } #[inline(always)] fn set_prescaler(&mut self, psc: u16) { - self.psc.write(|w| w.psc().bits(psc) ); + self.psc().write(|w| w.psc().set(psc) ); } #[inline(always)] fn read_prescaler(&self) -> u16 { - self.psc.read().psc().bits() + self.psc().read().psc().bits() } #[inline(always)] fn trigger_update(&mut self) { - self.cr1.modify(|_, w| w.urs().set_bit()); - self.egr.write(|w| w.ug().set_bit()); - self.cr1.modify(|_, w| w.urs().clear_bit()); + self.cr1().modify(|_, w| w.urs().set_bit()); + self.egr().write(|w| w.ug().set_bit()); + self.cr1().modify(|_, w| w.urs().clear_bit()); } #[inline(always)] fn listen_event(&mut self, disable: Option>, enable: Option>) { - self.dier.modify(|r, w| unsafe { w.bits({ + self.dier().modify(|r, w| unsafe { w.bits({ let mut bits = r.bits(); if let Some(d) = disable { bits &= !(d.bits() as u32); @@ -462,37 +462,37 @@ macro_rules! hal { } #[inline(always)] fn clear_interrupt_flag(&mut self, event: BitFlags) { - self.sr.write(|w| unsafe { w.bits(0xffff & !(event.bits() as u32)) }); + self.sr().write(|w| unsafe { w.bits(0xffff & !(event.bits() as u32)) }); } #[inline(always)] fn get_interrupt_flag(&self) -> BitFlags { - BitFlags::from_bits_truncate(self.sr.read().bits()) + BitFlags::from_bits_truncate(self.sr().read().bits()) } #[inline(always)] fn read_count(&self) -> Self::Width { - self.cnt.read().bits() as Self::Width + self.cnt().read().bits() as Self::Width } #[inline(always)] fn write_count(&mut self, value:Self::Width) { //TODO: remove "unsafe" when possible #[allow(unused_unsafe)] - self.cnt.write(|w|unsafe{w.cnt().bits(value)}); + self.cnt().write(|w|unsafe{w.cnt().bits(value)}); } #[inline(always)] fn start_one_pulse(&mut self) { - self.cr1.modify(|_, w| unsafe { w.bits(1 << 3) }.cen().set_bit()); + self.cr1().modify(|_, w| unsafe { w.bits(1 << 3) }.cen().set_bit()); } #[inline(always)] fn start_free(&mut self, update: bool) { - self.cr1.modify(|_, w| w.cen().set_bit().udis().bit(!update)); + self.cr1().modify(|_, w| w.cen().set_bit().udis().bit(!update)); } #[inline(always)] fn cr1_reset(&mut self) { - self.cr1.reset(); + self.cr1().reset(); } #[inline(always)] fn cnt_reset(&mut self) { - self.cnt.reset(); + self.cnt().reset(); } } @@ -507,7 +507,7 @@ macro_rules! hal { fn read_cc_value(c: u8) -> u32 { let tim = unsafe { &*<$TIM>::ptr() }; if c < Self::CH_NUMBER { - tim.ccr[c as usize].read().bits() + tim.ccr(c as usize).read().bits() } else { 0 } @@ -518,7 +518,7 @@ macro_rules! hal { let tim = unsafe { &*<$TIM>::ptr() }; if c < Self::CH_NUMBER { #[allow(unused_unsafe)] - tim.ccr[c as usize].write(|w| unsafe { w.bits(value) }) + tim.ccr(c as usize).write(|w| unsafe { w.bits(value) }) } } @@ -526,7 +526,7 @@ macro_rules! hal { fn enable_channel(c: u8, b: bool) { let tim = unsafe { &*<$TIM>::ptr() }; if c < Self::CH_NUMBER { - unsafe { bb::write(&tim.ccer, c*4, b); } + unsafe { bb::write(tim.ccer(), c*4, b); } } } @@ -534,7 +534,7 @@ macro_rules! hal { fn set_channel_polarity(c: u8, p: Polarity) { let tim = unsafe { &*<$TIM>::ptr() }; if c < Self::CH_NUMBER { - unsafe { bb::write(&tim.ccer, c*4 + 1, p == Polarity::ActiveLow); } + unsafe { bb::write(tim.ccer(), c*4 + 1, p == Polarity::ActiveLow); } } } @@ -542,7 +542,7 @@ macro_rules! hal { fn set_nchannel_polarity(c: u8, p: Polarity) { let tim = unsafe { &*<$TIM>::ptr() }; if c < Self::COMP_CH_NUMBER { - unsafe { bb::write(&tim.ccer, c*4 + 3, p == Polarity::ActiveLow); } + unsafe { bb::write(tim.ccer(), c*4 + 3, p == Polarity::ActiveLow); } } } } @@ -553,26 +553,26 @@ macro_rules! hal { let $aoe = (); let tim = unsafe { &*<$TIM>::ptr() }; if c < Self::COMP_CH_NUMBER { - unsafe { bb::write(&tim.ccer, c*4 + 2, b); } + unsafe { bb::write(tim.ccer(), c*4 + 2, b); } } } fn set_dtg_value(value: u8) { let tim = unsafe { &*<$TIM>::ptr() }; - tim.bdtr.modify(|_,w| unsafe { w.dtg().bits(value) }); + tim.bdtr().modify(|_,w| w.dtg().set(value)); } fn read_dtg_value() -> u8 { let tim = unsafe { &*<$TIM>::ptr() }; - tim.bdtr.read().dtg().bits() + tim.bdtr().read().dtg().bits() } fn idle_state(c: u8, comp: bool, s: IdleState) { let tim = unsafe { &*<$TIM>::ptr() }; if !comp { if c < Self::CH_NUMBER { - unsafe { bb::write(&tim.cr2, c*2 + 8, s == IdleState::Set); } + unsafe { bb::write(tim.cr2(), c*2 + 8, s == IdleState::Set); } } } else { if c < Self::COMP_CH_NUMBER { - unsafe { bb::write(&tim.cr2, c*2 + 9, s == IdleState::Set); } + unsafe { bb::write(tim.cr2(), c*2 + 9, s == IdleState::Set); } } } } @@ -583,7 +583,7 @@ macro_rules! hal { unsafe impl PeriAddress for CCR<$TIM, C> { #[inline(always)] fn address(&self) -> u32 { - self.0.ccr[C as usize].as_ptr() as u32 + self.0.ccr(C as usize).as_ptr() as u32 } type MemSize = $bits; @@ -591,9 +591,9 @@ macro_rules! hal { )? $(impl MasterTimer for $TIM { - type Mms = pac::$timbase::cr2::MMS_A; + type Mms = pac::$timbase::cr2::MMS; fn master_mode(&mut self, mode: Self::Mms) { - self.cr2.modify(|_,w| w.mms().variant(mode)); + self.cr2().modify(|_,w| w.mms().variant(mode)); } })? }; @@ -605,7 +605,7 @@ macro_rules! with_dmar { unsafe impl PeriAddress for DMAR<$TIM> { #[inline(always)] fn address(&self) -> u32 { - self.0.dmar.as_ptr() as u32 + self.0.dmar().as_ptr() as u32 } type MemSize = $memsize; @@ -622,7 +622,7 @@ macro_rules! with_pwm { $( Channel::$Cx => { self.$ccmrx_output() - .modify(|_, w| w.$ocxpe().set_bit().$ocxm().bits(mode as _) ); + .modify(|_, w| w.$ocxpe().set_bit().$ocxm().set(mode as _) ); } )+ #[allow(unreachable_patterns)] @@ -632,8 +632,8 @@ macro_rules! with_pwm { #[inline(always)] fn start_pwm(&mut self) { - $(let $aoe = self.bdtr.modify(|_, w| w.aoe().set_bit());)? - self.cr1.modify(|_, w| w.cen().set_bit()); + $(let $aoe = self.bdtr().modify(|_, w| w.aoe().set_bit());)? + self.cr1().modify(|_, w| w.cen().set_bit()); } } }; diff --git a/src/timer/counter.rs b/src/timer/counter.rs index 7b9adbfa3..85308311a 100644 --- a/src/timer/counter.rs +++ b/src/timer/counter.rs @@ -1,6 +1,6 @@ use super::{compute_arr_presc, Error, FTimer, Flag, Instance, SysEvent, Timer}; -use crate::pac::SYST; use core::ops::{Deref, DerefMut}; +use cortex_m::peripheral::SYST; use fugit::{HertzU32 as Hertz, TimerDurationU32, TimerInstantU32}; /// Hardware timers diff --git a/src/timer/monotonic.rs b/src/timer/monotonic.rs index b5e0a2c09..e3f2af2ad 100644 --- a/src/timer/monotonic.rs +++ b/src/timer/monotonic.rs @@ -73,7 +73,7 @@ pub trait SysMonoTimerExt: Sized { } } -impl SysMonoTimerExt for crate::pac::SYST { +impl SysMonoTimerExt for cortex_m::peripheral::SYST { fn monotonic(self, clocks: &Clocks) -> Systick { Systick::new(self, clocks.hclk().raw()) } diff --git a/src/timer/monotonics.rs b/src/timer/monotonics.rs index e8b87d04c..add51d651 100644 --- a/src/timer/monotonics.rs +++ b/src/timer/monotonics.rs @@ -161,18 +161,20 @@ macro_rules! make_timer { __internal_create_stm32_timer_interrupt!($timer); // Enable full-period interrupt. - self.tim.dier.modify(|_, w| w.uie().set_bit()); + self.tim.dier().modify(|_, w| w.uie().set_bit()); // Configure and enable half-period interrupt - self.tim.ccr[2].write(|w| w.ccr().bits(($bits::MAX - ($bits::MAX >> 1)).into())); - self.tim.dier.modify(|_, w| w.cc3ie().set_bit()); + self.tim + .ccr(2) + .write(|w| w.ccr().set(($bits::MAX - ($bits::MAX >> 1)).into())); + self.tim.dier().modify(|_, w| w.cc3ie().set_bit()); // Trigger an update event to load the prescaler value to the clock. - self.tim.egr.write(|w| w.ug().set_bit()); + self.tim.egr().write(|w| w.ug().set_bit()); // The above line raises an update event which will indicate that the timer is already finished. // Since this is not the case, it should be cleared. - self.tim.sr.modify(|_, w| w.uif().clear_bit()); + self.tim.sr().modify(|_, w| w.uif().clear_bit()); $tq.initialize(MonoTimerBackend:: { _tim: PhantomData }); $overflow.store(0, Ordering::SeqCst); @@ -204,7 +206,7 @@ macro_rules! make_timer { fn now() -> Self::Ticks { calculate_now( || $overflow.load(Ordering::Relaxed), - || Self::tim().cnt.read().bits(), + || Self::tim().cnt().read().bits(), ) } @@ -220,11 +222,11 @@ macro_rules! make_timer { 0 }; - Self::tim().ccr[1].write(|r| r.ccr().bits(val.into())); + Self::tim().ccr(1).write(|r| r.ccr().set(val.into())); } fn clear_compare_flag() { - Self::tim().sr.modify(|_, w| w.cc2if().clear_bit()); + Self::tim().sr().modify(|_, w| w.cc2if().clear_bit()); } fn pend_interrupt() { @@ -232,23 +234,23 @@ macro_rules! make_timer { } fn enable_timer() { - Self::tim().dier.modify(|_, w| w.cc2ie().set_bit()); + Self::tim().dier().modify(|_, w| w.cc2ie().set_bit()); } fn disable_timer() { - Self::tim().dier.modify(|_, w| w.cc2ie().clear_bit()); + Self::tim().dier().modify(|_, w| w.cc2ie().clear_bit()); } fn on_interrupt() { // Full period - if Self::tim().sr.read().uif().bit_is_set() { - Self::tim().sr.modify(|_, w| w.uif().clear_bit()); + if Self::tim().sr().read().uif().bit_is_set() { + Self::tim().sr().modify(|_, w| w.uif().clear_bit()); let prev = $overflow.fetch_add(1, Ordering::Relaxed); assert!(prev % 2 == 1, "Monotonic must have missed an interrupt!"); } // Half period - if Self::tim().sr.read().cc3if().bit_is_set() { - Self::tim().sr.modify(|_, w| w.cc3if().clear_bit()); + if Self::tim().sr().read().cc3if().bit_is_set() { + Self::tim().sr().modify(|_, w| w.cc3if().clear_bit()); let prev = $overflow.fetch_add(1, Ordering::Relaxed); assert!(prev % 2 == 0, "Monotonic must have missed an interrupt!"); } diff --git a/src/timer/pwm_input.rs b/src/timer/pwm_input.rs index 814e74fcc..aec7a14d4 100644 --- a/src/timer/pwm_input.rs +++ b/src/timer/pwm_input.rs @@ -93,7 +93,7 @@ macro_rules! hal { self.tim.set_prescaler(psc); // Seemingly this needs to be written to - // self.tim.arr.write(|w| w.arr().bits(u16::MAX)); + // self.tim.arr().write(|w| w.arr().bits(u16::MAX)); /* For example, one can measure the period (in TIMx_CCR1 register) and the duty cycle (in @@ -113,7 +113,7 @@ macro_rules! hal { // clear): write the CC1P and CC1NP bits to ‘0’ (active on rising edge). self.tim - .ccer + .ccer() .modify(|_, w| w.cc1p().clear_bit().cc2p().clear_bit()); // disable filters and disable the input capture prescalers. @@ -131,24 +131,26 @@ macro_rules! hal { // Select the active polarity for TI1FP2 (used for capture in TIMx_CCR2): write the CC2P // and CC2NP bits to ‘1’ (active on falling edge). self.tim - .ccer + .ccer() .modify(|_, w| w.cc2p().set_bit().cc2np().set_bit()); // Select the valid trigger input: write the TS bits to 101 in the TIMx_SMCR register // (TI1FP1 selected). - self.tim.smcr.modify(|_, w| unsafe { w.ts().bits(0b101) }); + self.tim.smcr().modify(|_, w| unsafe { w.ts().bits(0b101) }); // Configure the slave mode controller in reset mode: write the SMS bits to 100 in the // TIMx_SMCR register. - self.tim.smcr.modify(|_, w| unsafe { w.sms().bits(0b100) }); + self.tim + .smcr() + .modify(|_, w| unsafe { w.sms().bits(0b100) }); // Enable the captures: write the CC1E and CC2E bits to ‘1’ in the TIMx_CCER register. self.tim - .ccer + .ccer() .modify(|_, w| w.cc1e().set_bit().cc2e().set_bit()); // enable interrupts. - self.tim.dier.modify(|_, w| w.cc2ie().set_bit()); + self.tim.dier().modify(|_, w| w.cc2ie().set_bit()); // enable the counter. self.tim.enable_counter(true); diff --git a/src/uart.rs b/src/uart.rs index b6de3ce16..4a5dcfb37 100644 --- a/src/uart.rs +++ b/src/uart.rs @@ -21,7 +21,6 @@ use crate::serial::uart_impls::{RegisterBlockImpl, RegisterBlockUart}; pub use crate::serial::{config, Error, Event, Instance, NoRx, NoTx, Rx, RxISR, Serial, Tx, TxISR}; pub use config::Config; -#[cfg(not(any(feature = "stm32f413", feature = "stm32f423",)))] macro_rules! halUart { ($UART:ty, $Serial:ident, $Rx:ident, $Tx:ident) => { pub type $Serial = Serial<$UART, WORD>; @@ -36,19 +35,19 @@ macro_rules! halUart { } fn set_stopbits(&self, bits: config::StopBits) { - use crate::pac::uart4::cr2::STOP_A; + use crate::pac::uart4::cr2::STOP; use config::StopBits; /* StopBits::STOP0P5 and StopBits::STOP1P5 aren't supported when using UART STOP_A::STOP1 and STOP_A::STOP2 will be used, respectively */ - self.cr2.write(|w| { + self.cr2().write(|w| { w.stop().variant(match bits { - StopBits::STOP0P5 => STOP_A::Stop1, - StopBits::STOP1 => STOP_A::Stop1, - StopBits::STOP1P5 => STOP_A::Stop2, - StopBits::STOP2 => STOP_A::Stop2, + StopBits::STOP0P5 => STOP::Stop1, + StopBits::STOP1 => STOP::Stop1, + StopBits::STOP1P5 => STOP::Stop2, + StopBits::STOP2 => STOP::Stop2, }) }); } @@ -87,13 +86,13 @@ impl Instance for pac::UART4 { #[cfg(feature = "uart5")] #[cfg(any(feature = "stm32f413", feature = "stm32f423"))] -crate::serial::halUsart! { pac::UART5, Serial5, Rx5, Tx5 } +halUart! { pac::UART5, Serial5, Rx5, Tx5 } #[cfg(feature = "uart7")] -crate::serial::halUsart! { pac::UART7, Serial7, Rx7, Tx7 } +halUart! { pac::UART7, Serial7, Rx7, Tx7 } #[cfg(feature = "uart8")] -crate::serial::halUsart! { pac::UART8, Serial8, Rx8, Tx8 } +halUart! { pac::UART8, Serial8, Rx8, Tx8 } #[cfg(feature = "uart9")] -crate::serial::halUsart! { pac::UART9, Serial9, Rx9, Tx9 } +halUart! { pac::UART9, Serial9, Rx9, Tx9 } #[cfg(feature = "uart10")] -crate::serial::halUsart! { pac::UART10, Serial10, Rx10, Tx10 } +halUart! { pac::UART10, Serial10, Rx10, Tx10 } diff --git a/src/watchdog.rs b/src/watchdog.rs index 79201febd..0092f16fd 100644 --- a/src/watchdog.rs +++ b/src/watchdog.rs @@ -39,7 +39,7 @@ impl IndependentWatchdog { /// Debug independent watchdog stopped when core is halted pub fn stop_on_debug(&self, dbgmcu: &DBGMCU, stop: bool) { - dbgmcu.apb1_fz.modify(|_, w| w.dbg_iwdg_stop().bit(stop)); + dbgmcu.apb1_fz().modify(|_, w| w.dbg_iwdg_stop().bit(stop)); } /// Sets the watchdog timer timout period. Max: 32768 ms @@ -60,21 +60,21 @@ impl IndependentWatchdog { let rl = (timeout_ms.ticks() * max_rl / max_period).min(max_rl) as u16; self.access_registers(|iwdg| { - iwdg.pr.modify(|_, w| w.pr().bits(pr)); - iwdg.rlr.modify(|_, w| w.rl().bits(rl)); + iwdg.pr().modify(|_, w| unsafe { w.pr().bits(pr) }); + iwdg.rlr().modify(|_, w| w.rl().set(rl)); }); } fn is_pr_updating(&self) -> bool { - self.iwdg.sr.read().pvu().bit() + self.iwdg.sr().read().pvu().bit() } /// Returns the interval in ms pub fn interval(&self) -> MilliSeconds { while self.is_pr_updating() {} - let pr = self.iwdg.pr.read().pr().bits(); - let rl = self.iwdg.rlr.read().rl().bits(); + let pr = self.iwdg.pr().read().pr().bits(); + let rl = self.iwdg.rlr().read().rl().bits(); let ms = Self::timeout_period(pr, rl); MilliSeconds::from_ticks(ms) } @@ -99,22 +99,22 @@ impl IndependentWatchdog { fn access_registers A>(&self, mut f: F) -> A { // Unprotect write access to registers - self.iwdg.kr.write(|w| unsafe { w.key().bits(KR_ACCESS) }); + self.iwdg.kr().write(|w| unsafe { w.key().bits(KR_ACCESS) }); let a = f(&self.iwdg); // Protect again - self.iwdg.kr.write(|w| unsafe { w.key().bits(KR_RELOAD) }); + self.iwdg.kr().write(|w| unsafe { w.key().bits(KR_RELOAD) }); a } pub fn start(&mut self, period: MilliSeconds) { self.setup(period); - self.iwdg.kr.write(|w| unsafe { w.key().bits(KR_START) }); + self.iwdg.kr().write(|w| unsafe { w.key().bits(KR_START) }); } pub fn feed(&mut self) { - self.iwdg.kr.write(|w| unsafe { w.key().bits(KR_RELOAD) }); + self.iwdg.kr().write(|w| unsafe { w.key().bits(KR_RELOAD) }); } } From 3a0992022f81f83c85edf6267e69601f614eaa0d Mon Sep 17 00:00:00 2001 From: Andrey Zgarbul Date: Sun, 9 Jun 2024 09:05:44 +0300 Subject: [PATCH 2/3] clean attr --- src/dma/traits/f4.rs | 14 +++++++------- src/i2s.rs | 8 ++++---- src/lib.rs | 4 ++-- src/otg_hs.rs | 2 +- src/prelude.rs | 2 +- src/rcc/pll.rs | 6 +++--- 6 files changed, 18 insertions(+), 18 deletions(-) diff --git a/src/dma/traits/f4.rs b/src/dma/traits/f4.rs index cc74f3fab..837d84433 100644 --- a/src/dma/traits/f4.rs +++ b/src/dma/traits/f4.rs @@ -119,7 +119,7 @@ dma_map!( (Stream2:3, pac::I2C3, [PeripheralToMemory]), //I2C3_RX:DMA_CHANNEL_3 ); -#[cfg(any(feature = "gpio-f401", feature = "gpio-f411",))] +#[cfg(any(feature = "gpio-f401", feature = "gpio-f411"))] dma_map!( (Stream1:3, timer::CCR3, [MemoryToPeripheral | PeripheralToMemory]), //TIM2_CH3 (Stream1:3, timer::DMAR, [MemoryToPeripheral | PeripheralToMemory]), //TIM2_UP @@ -253,7 +253,7 @@ dma_map!( ); */ -#[cfg(any(feature = "gpio-f417", feature = "gpio-f427", feature = "gpio-f469",))] +#[cfg(any(feature = "gpio-f417", feature = "gpio-f427", feature = "gpio-f469"))] dma_map!( (Stream2:3, pac::I2C3, [PeripheralToMemory]), //I2C3_RX (Stream5:2, pac::CRYP, [PeripheralToMemory]), //CRYP_OUT @@ -261,7 +261,7 @@ dma_map!( (Stream7:2, pac::HASH, [MemoryToPeripheral]), //HASH_IN ); -#[cfg(any(feature = "gpio-f417", feature = "gpio-f427", feature = "gpio-f469",))] +#[cfg(any(feature = "gpio-f417", feature = "gpio-f427", feature = "gpio-f469"))] address!((pac::HASH, din, u32), (pac::CRYP, din, u32),); #[cfg(feature = "cryp")] @@ -366,7 +366,7 @@ dma_map!( ))] address!((pac::SPI5, dr, u8),); -#[cfg(any(feature = "gpio-f411", feature = "gpio-f412", feature = "gpio-f413",))] +#[cfg(any(feature = "gpio-f411", feature = "gpio-f412", feature = "gpio-f413"))] dma_map!( (Stream4:4, pac::SPI4, [PeripheralToMemory]), //SPI4_RX ); @@ -426,7 +426,7 @@ dma_map!( #[cfg(feature = "quadspi")] address!((pac::QUADSPI, dr, u32),); -#[cfg(any(feature = "gpio-f413", feature = "gpio-f427", feature = "gpio-f469",))] +#[cfg(any(feature = "gpio-f413", feature = "gpio-f427", feature = "gpio-f469"))] dma_map!( (Stream0:5, pac::UART8, [MemoryToPeripheral]), //UART8_TX (Stream1:5, pac::UART7, [MemoryToPeripheral]), //UART7_TX @@ -434,7 +434,7 @@ dma_map!( (Stream6:5, pac::UART8, [PeripheralToMemory]), //UART8_RX ); -#[cfg(any(feature = "gpio-f413", feature = "gpio-f427", feature = "gpio-f469",))] +#[cfg(any(feature = "gpio-f413", feature = "gpio-f427", feature = "gpio-f469"))] address!((pac::UART7, dr, u8), (pac::UART8, dr, u8),); #[cfg(feature = "gpio-f413")] @@ -522,7 +522,7 @@ dma_map!( //(Stream6:0, SPDIFRX_CS, [PeripheralToMemory]), //SPDIF_RX_CS ); -#[cfg(any(feature = "gpio-f410", feature = "gpio-f412", feature = "gpio-f413",))] +#[cfg(any(feature = "gpio-f410", feature = "gpio-f412", feature = "gpio-f413"))] dma_map!( (Stream0:7, pac::FMPI2C1, [PeripheralToMemory]), //FMPI2C1_RX (Stream1:2, pac::FMPI2C1, [MemoryToPeripheral]), //FMPI2C1_TX diff --git a/src/i2s.rs b/src/i2s.rs index 0a42e7b71..59e2928a1 100644 --- a/src/i2s.rs +++ b/src/i2s.rs @@ -245,13 +245,13 @@ macro_rules! i2s { #[cfg(any(feature = "gpio-f410", feature = "gpio-f411"))] i2s!(pac::SPI1, I2s1, i2s1, i2s_clk); -#[cfg(any(feature = "gpio-f412", feature = "gpio-f413", feature = "gpio-f446",))] +#[cfg(any(feature = "gpio-f412", feature = "gpio-f413", feature = "gpio-f446"))] i2s!(pac::SPI1, I2s1, i2s1, i2s_apb2_clk); // All STM32F4 models support SPI2/I2S2 -#[cfg(not(any(feature = "gpio-f412", feature = "gpio-f413", feature = "gpio-f446",)))] +#[cfg(not(any(feature = "gpio-f412", feature = "gpio-f413", feature = "gpio-f446")))] i2s!(pac::SPI2, I2s2, i2s2, i2s_clk); -#[cfg(any(feature = "gpio-f412", feature = "gpio-f413", feature = "gpio-f446",))] +#[cfg(any(feature = "gpio-f412", feature = "gpio-f413", feature = "gpio-f446"))] i2s!(pac::SPI2, I2s2, i2s2, i2s_apb1_clk); // All STM32F4 models except STM32F410 support SPI3/I2S3 @@ -263,7 +263,7 @@ i2s!(pac::SPI2, I2s2, i2s2, i2s_apb1_clk); feature = "gpio-f469", ))] i2s!(pac::SPI3, I2s3, i2s3, i2s_clk); -#[cfg(any(feature = "gpio-f412", feature = "gpio-f413", feature = "gpio-f446",))] +#[cfg(any(feature = "gpio-f412", feature = "gpio-f413", feature = "gpio-f446"))] i2s!(pac::SPI3, I2s3, i2s3, i2s_apb1_clk); #[cfg(feature = "gpio-f411")] diff --git a/src/lib.rs b/src/lib.rs index b786bd6b9..806a8a37e 100644 --- a/src/lib.rs +++ b/src/lib.rs @@ -86,7 +86,7 @@ pub use crate::pac::interrupt; pub mod adc; pub mod bb; -#[cfg(all(feature = "can", any(feature = "can1", feature = "can2",)))] +#[cfg(all(feature = "can", any(feature = "can1", feature = "can2")))] pub mod can; pub mod crc32; #[cfg(feature = "dac")] @@ -98,7 +98,7 @@ pub mod i2c; pub mod i2s; #[cfg(all(feature = "usb_fs", feature = "otg-fs"))] pub mod otg_fs; -#[cfg(all(any(feature = "usb_hs", docsrs), feature = "otg-hs",))] +#[cfg(all(any(feature = "usb_hs", docsrs), feature = "otg-hs"))] pub mod otg_hs; #[cfg(feature = "rng")] diff --git a/src/otg_hs.rs b/src/otg_hs.rs index 80cbe8b2e..f62a603b5 100644 --- a/src/otg_hs.rs +++ b/src/otg_hs.rs @@ -49,7 +49,7 @@ unsafe impl UsbPeripheral for USB { const HIGH_SPEED: bool = true; const FIFO_DEPTH_WORDS: usize = 1024; - #[cfg(any(feature = "gpio-f417", feature = "gpio-f427",))] + #[cfg(any(feature = "gpio-f417", feature = "gpio-f427"))] const ENDPOINT_COUNT: usize = 6; #[cfg(any(feature = "gpio-f446", feature = "gpio-f469"))] const ENDPOINT_COUNT: usize = 9; diff --git a/src/prelude.rs b/src/prelude.rs index af1efa8fb..bc5e65ca1 100644 --- a/src/prelude.rs +++ b/src/prelude.rs @@ -47,7 +47,7 @@ pub use embedded_hal_nb::serial::Write as _embedded_hal_serial_nb_Write; pub use fugit::ExtU32 as _fugit_ExtU32; pub use fugit::RateExtU32 as _fugit_RateExtU32; -#[cfg(all(feature = "can", any(feature = "can1", feature = "can2",)))] +#[cfg(all(feature = "can", any(feature = "can1", feature = "can2")))] pub use crate::can::CanExt as _stm32f4xx_hal_can_CanExt; #[cfg(feature = "dac")] pub use crate::dac::DacExt as _stm32f4xx_hal_dac_DacExt; diff --git a/src/rcc/pll.rs b/src/rcc/pll.rs index 412fbd5d7..139c3b7f1 100644 --- a/src/rcc/pll.rs +++ b/src/rcc/pll.rs @@ -317,14 +317,14 @@ impl I2sPll { } } -#[cfg(any(feature = "gpio-f427", feature = "gpio-f446", feature = "gpio-f469",))] +#[cfg(any(feature = "gpio-f427", feature = "gpio-f446", feature = "gpio-f469"))] pub struct SaiPll { pub use_pll: bool, /// SAI clock (PLL output divided by the SAI clock divider). pub sai_clk: Option, } -#[cfg(any(feature = "gpio-f427", feature = "gpio-f446", feature = "gpio-f469",))] +#[cfg(any(feature = "gpio-f427", feature = "gpio-f446", feature = "gpio-f469"))] impl SaiPll { pub fn unused() -> SaiPll { SaiPll { @@ -349,7 +349,7 @@ impl SaiPll { pll } - #[cfg(any(feature = "gpio-f427", feature = "gpio-f469",))] + #[cfg(any(feature = "gpio-f427", feature = "gpio-f469"))] pub fn setup_shared_m(pllsrcclk: u32, m: Option, sai_clk: Option) -> SaiPll { // "m" is None if both other PLLs are not in use. let Some(m) = m else { From d6a4a1b1be2b0447d45bfbe6118f1cb88cd04580 Mon Sep 17 00:00:00 2001 From: Andrey Zgarbul Date: Sun, 9 Jun 2024 10:41:17 +0300 Subject: [PATCH 3/3] clippy ci --- .github/workflows/clippy.yml | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/.github/workflows/clippy.yml b/.github/workflows/clippy.yml index 2e49f121f..097b33418 100644 --- a/.github/workflows/clippy.yml +++ b/.github/workflows/clippy.yml @@ -20,5 +20,4 @@ jobs: key: v0.21.0 - run: cargo clippy --examples --features=stm32f479,usb_fs,sdio-host,can,i2s,fsmc_lcd,rtic1 - with: - token: ${{ secrets.GITHUB_TOKEN }} +