diff --git a/cores/arduino/stm32/OpenAMP/libmetal/generic/cortexm/sys.c b/cores/arduino/stm32/OpenAMP/libmetal/generic/cortexm/sys.c index 83f98dd29f..b0a7591464 100644 --- a/cores/arduino/stm32/OpenAMP/libmetal/generic/cortexm/sys.c +++ b/cores/arduino/stm32/OpenAMP/libmetal/generic/cortexm/sys.c @@ -1,5 +1,5 @@ #ifdef VIRTIOCON -#include "libmetal/lib/system/generic/cortexm/sys.c" +#include "libmetal/lib/system/generic/template/sys.c" #endif /* VIRTIOCON */ diff --git a/cores/arduino/stm32/OpenAMP/openamp.c b/cores/arduino/stm32/OpenAMP/openamp.c index a0cb64e660..351026d7ad 100644 --- a/cores/arduino/stm32/OpenAMP/openamp.c +++ b/cores/arduino/stm32/OpenAMP/openamp.c @@ -164,16 +164,6 @@ void OPENAMP_DeInit() metal_finish(); } -/** - * @brief Initialize the endpoint struct - * - * @param ept: virtio rpmsg endpoint - */ -void OPENAMP_init_ept(struct rpmsg_endpoint *ept) -{ - rpmsg_init_ept(ept, "", RPMSG_ADDR_ANY, RPMSG_ADDR_ANY, NULL, NULL); -} - /** * @brief Create and register the name service endpoint * diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_smbus_ex.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_smbus_ex.c index 4f20c0c778..05b85a93b8 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_smbus_ex.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_smbus_ex.c @@ -14,6 +14,8 @@ #include "stm32l4xx_hal_smbus_ex.c" #elif STM32L5xx #include "stm32l5xx_hal_smbus_ex.c" +#elif STM32MP1xx + #include "stm32mp1xx_hal_smbus_ex.c" #elif STM32U5xx #include "stm32u5xx_hal_smbus_ex.c" #elif STM32WBxx diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151axx_ca7.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151axx_ca7.h index 370d79fc23..072b033d6b 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151axx_ca7.h +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151axx_ca7.h @@ -10713,16 +10713,19 @@ typedef struct #define ETH_MACCR_PRELEN_Pos (2U) #define ETH_MACCR_PRELEN_Msk (0x3UL << ETH_MACCR_PRELEN_Pos) /*!< 0x0000000C */ #define ETH_MACCR_PRELEN ETH_MACCR_PRELEN_Msk /*!< Preamble Length for Transmit packets */ -#define ETH_MACCR_PRELEN_0 (0x1UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000004 */ -#define ETH_MACCR_PRELEN_1 (0x2UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000008 */ +#define ETH_MACCR_PRELEN_7 (0x0UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000000 */ +#define ETH_MACCR_PRELEN_5 (0x1UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000004 */ +#define ETH_MACCR_PRELEN_3 (0x2UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000006 */ #define ETH_MACCR_DC_Pos (4U) #define ETH_MACCR_DC_Msk (0x1UL << ETH_MACCR_DC_Pos) /*!< 0x00000010 */ #define ETH_MACCR_DC ETH_MACCR_DC_Msk /*!< Deferral Check */ #define ETH_MACCR_BL_Pos (5U) #define ETH_MACCR_BL_Msk (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */ #define ETH_MACCR_BL ETH_MACCR_BL_Msk /*!< Back-Off Limit */ -#define ETH_MACCR_BL_0 (0x1UL << ETH_MACCR_BL_Pos) /*!< 0x00000020 */ -#define ETH_MACCR_BL_1 (0x2UL << ETH_MACCR_BL_Pos) /*!< 0x00000040 */ +#define ETH_MACCR_BL_10 (0x0UL << ETH_MACCR_BL_Pos) /*!< 0x00000000 */ +#define ETH_MACCR_BL_8 (0x1UL << ETH_MACCR_BL_Pos) /*!< 0x00000020 */ +#define ETH_MACCR_BL_4 (0x2UL << ETH_MACCR_BL_Pos) /*!< 0x00000040 */ +#define ETH_MACCR_BL_1 (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */ #define ETH_MACCR_DR_Pos (8U) #define ETH_MACCR_DR_Msk (0x1UL << ETH_MACCR_DR_Pos) /*!< 0x00000100 */ #define ETH_MACCR_DR ETH_MACCR_DR_Msk /*!< Disable Retry */ @@ -10774,9 +10777,14 @@ typedef struct #define ETH_MACCR_IPG_Pos (24U) #define ETH_MACCR_IPG_Msk (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */ #define ETH_MACCR_IPG ETH_MACCR_IPG_Msk /*!< Inter-Packet Gap */ -#define ETH_MACCR_IPG_0 (0x1UL << ETH_MACCR_IPG_Pos) /*!< 0x01000000 */ -#define ETH_MACCR_IPG_1 (0x2UL << ETH_MACCR_IPG_Pos) /*!< 0x02000000 */ -#define ETH_MACCR_IPG_2 (0x4UL << ETH_MACCR_IPG_Pos) /*!< 0x04000000 */ +#define ETH_MACCR_IPG_96BIT (0x0UL << ETH_MACCR_IPG_Pos) /*!< 0x00000000 */ +#define ETH_MACCR_IPG_88BIT (0x1UL << ETH_MACCR_IPG_Pos) /*!< 0x01000000 */ +#define ETH_MACCR_IPG_80BIT (0x2UL << ETH_MACCR_IPG_Pos) /*!< 0x02000000 */ +#define ETH_MACCR_IPG_72BIT (0x3UL << ETH_MACCR_IPG_Pos) /*!< 0x03000000 */ +#define ETH_MACCR_IPG_64BIT (0x4UL << ETH_MACCR_IPG_Pos) /*!< 0x04000000 */ +#define ETH_MACCR_IPG_56BIT (0x5UL << ETH_MACCR_IPG_Pos) /*!< 0x05000000 */ +#define ETH_MACCR_IPG_48BIT (0x6UL << ETH_MACCR_IPG_Pos) /*!< 0x06000000 */ +#define ETH_MACCR_IPG_40BIT (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */ #define ETH_MACCR_IPC_Pos (27U) #define ETH_MACCR_IPC_Msk (0x1UL << ETH_MACCR_IPC_Pos) /*!< 0x08000000 */ #define ETH_MACCR_IPC ETH_MACCR_IPC_Msk /*!< Checksum Offload */ @@ -10879,10 +10887,21 @@ typedef struct #define ETH_MACWTR_WTO_Pos (0U) #define ETH_MACWTR_WTO_Msk (0xFUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000F */ #define ETH_MACWTR_WTO ETH_MACWTR_WTO_Msk /*!< Watchdog Timeout */ -#define ETH_MACWTR_WTO_0 (0x1UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000001 */ -#define ETH_MACWTR_WTO_1 (0x2UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000002 */ -#define ETH_MACWTR_WTO_2 (0x4UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000004 */ -#define ETH_MACWTR_WTO_3 (0x8UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000008 */ +#define ETH_MACWTR_WTO_2KB (0x0UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000001 */ +#define ETH_MACWTR_WTO_3KB (0x1UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000001 */ +#define ETH_MACWTR_WTO_4KB (0x2UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000002 */ +#define ETH_MACWTR_WTO_5KB (0x3UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000003 */ +#define ETH_MACWTR_WTO_6KB (0x4UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000004 */ +#define ETH_MACWTR_WTO_7KB (0x5UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000005 */ +#define ETH_MACWTR_WTO_8KB (0x6UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000006 */ +#define ETH_MACWTR_WTO_9KB (0x7UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000007 */ +#define ETH_MACWTR_WTO_10KB (0x8UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000008 */ +#define ETH_MACWTR_WTO_11KB (0x9UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000009 */ +#define ETH_MACWTR_WTO_12KB (0xAUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000A */ +#define ETH_MACWTR_WTO_13KB (0xBUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000B */ +#define ETH_MACWTR_WTO_14KB (0xCUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000C */ +#define ETH_MACWTR_WTO_15KB (0xDUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000D */ +#define ETH_MACWTR_WTO_16KB (0xEUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000E */ #define ETH_MACWTR_PWE_Pos (8U) #define ETH_MACWTR_PWE_Msk (0x1UL << ETH_MACWTR_PWE_Pos) /*!< 0x00000100 */ #define ETH_MACWTR_PWE ETH_MACWTR_PWE_Msk /*!< Programmable Watchdog Enable */ @@ -10962,6 +10981,9 @@ typedef struct #define ETH_MACHT1R_HT63T32_31 (0x80000000UL << ETH_MACHT1R_HT63T32_Pos) /*!< 0x80000000 */ /************** Bit definition for ETH_MACVTR register ***************/ +#define ETH_MACVTR_VL_VID_Pos (0U) +#define ETH_MACVTR_VL_VID_Msk (0xFFFUL << ETH_MACVTR_VL_VID_Pos) /*!< 0x00000FFF */ +#define ETH_MACVTR_VL_VID ETH_MACVTR_VL_VID_Msk /*!< VLAN Tag Identifier field of VLAN tag */ #define ETH_MACVTR_VL_Pos (0U) #define ETH_MACVTR_VL_Msk (0xFFFFUL << ETH_MACVTR_VL_Pos) /*!< 0x0000FFFF */ #define ETH_MACVTR_VL ETH_MACVTR_VL_Msk /*!< VLAN Tag Identifier for Receive Packets */ @@ -11123,9 +11145,12 @@ typedef struct #define ETH_MACQ0TXFCR_PLT_Pos (4U) #define ETH_MACQ0TXFCR_PLT_Msk (0x7UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000070 */ #define ETH_MACQ0TXFCR_PLT ETH_MACQ0TXFCR_PLT_Msk /*!< Pause Low Threshold */ -#define ETH_MACQ0TXFCR_PLT_0 (0x1UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000010 */ -#define ETH_MACQ0TXFCR_PLT_1 (0x2UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000020 */ -#define ETH_MACQ0TXFCR_PLT_2 (0x4UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000040 */ +#define ETH_MACQ0TXFCR_PLT_MINUS4 (0x0UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000000 */ +#define ETH_MACQ0TXFCR_PLT_MINUS28 (0x1UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000010 */ +#define ETH_MACQ0TXFCR_PLT_MINUS36 (0x2UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000020 */ +#define ETH_MACQ0TXFCR_PLT_MINUS144 (0x3UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000030 */ +#define ETH_MACQ0TXFCR_PLT_MINUS256 (0x4UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000040 */ +#define ETH_MACQ0TXFCR_PLT_MINUS512 (0x5UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000050 */ #define ETH_MACQ0TXFCR_DZPQ_Pos (7U) #define ETH_MACQ0TXFCR_DZPQ_Msk (0x1UL << ETH_MACQ0TXFCR_DZPQ_Pos) /*!< 0x00000080 */ #define ETH_MACQ0TXFCR_DZPQ ETH_MACQ0TXFCR_DZPQ_Msk /*!< Disable Zero-Quanta Pause */ @@ -11692,10 +11717,12 @@ typedef struct #define ETH_MACMDIOAR_CR_Pos (8U) #define ETH_MACMDIOAR_CR_Msk (0xFUL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000F00 */ #define ETH_MACMDIOAR_CR ETH_MACMDIOAR_CR_Msk /*!< CSR Clock Range */ -#define ETH_MACMDIOAR_CR_0 (0x1UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000100 */ -#define ETH_MACMDIOAR_CR_1 (0x2UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000200 */ -#define ETH_MACMDIOAR_CR_2 (0x4UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000400 */ -#define ETH_MACMDIOAR_CR_3 (0x8UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000800 */ +#define ETH_MACMDIOAR_CR_DIV42 (0x0UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000000 */ +#define ETH_MACMDIOAR_CR_DIV62 (0x1UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000100 */ +#define ETH_MACMDIOAR_CR_DIV16 (0x2UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000200 */ +#define ETH_MACMDIOAR_CR_DIV26 (0x3UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000300 */ +#define ETH_MACMDIOAR_CR_DIV102 (0x4UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000400 */ +#define ETH_MACMDIOAR_CR_DIV124 (0x5UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000500 */ #define ETH_MACMDIOAR_NTC_Pos (12U) #define ETH_MACMDIOAR_NTC_Msk (0x7UL << ETH_MACMDIOAR_NTC_Pos) /*!< 0x00007000 */ #define ETH_MACMDIOAR_NTC ETH_MACMDIOAR_NTC_Msk /*!< Number of Training Clocks */ @@ -12134,7 +12161,7 @@ typedef struct #define ETH_MMCTXIMR_TXLPIUSCIM ETH_MMCTXIMR_TXLPIUSCIM_Msk /*!< MMC Transmit LPI microsecond counter interrupt Mask */ #define ETH_MMCTXIMR_TXLPITRCIM_Pos (27U) #define ETH_MMCTXIMR_TXLPITRCIM_Msk (0x1UL << ETH_MMCTXIMR_TXLPITRCIM_Pos) /*!< 0x08000000 */ -#define ETH_MMCTXIMR_TXLPITRCIM ETH_MMC_INTERRUPT_MASK_TXLPITRCIM_Msk /*!< MMC Transmit LPI transition counter interrupt Mask */ +#define ETH_MMCTXIMR_TXLPITRCIM ETH_MMCTXIMR_TXLPITRCIM_Msk /*!< MMC Transmit LPI transition counter interrupt Mask */ /*********** Bit definition for ETH_MMC_TX_SINGLE_COLLISION_GOOD_PACKETS register ************/ #define ETH_MMCTXSCGPR_TXSNGLCOLG_Pos (0U) @@ -14837,9 +14864,10 @@ typedef struct #define ETH_DMAC0CR_DSL_Pos (18U) #define ETH_DMAC0CR_DSL_Msk (0x7UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x001C0000 */ #define ETH_DMAC0CR_DSL ETH_DMAC0CR_DSL_Msk /*!< Descriptor Skip Length */ -#define ETH_DMAC0CR_DSL_0 (0x1UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00040000 */ -#define ETH_DMAC0CR_DSL_1 (0x2UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00080000 */ -#define ETH_DMAC0CR_DSL_2 (0x4UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00100000 */ +#define ETH_DMACCR_DSL_0BIT (0x0UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00000000 */ +#define ETH_DMACCR_DSL_32BIT (0x1UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00040000 */ +#define ETH_DMACCR_DSL_64BIT (0x2UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00080000 */ +#define ETH_DMACCR_DSL_128BIT (0x4UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00100000 */ /************* Bit definition for ETH_DMAC0TXCR register *************/ #define ETH_DMAC0TXCR_ST_Pos (0U) @@ -14860,12 +14888,12 @@ typedef struct #define ETH_DMAC0TXCR_TXPBL_Pos (16U) #define ETH_DMAC0TXCR_TXPBL_Msk (0x3FUL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x003F0000 */ #define ETH_DMAC0TXCR_TXPBL ETH_DMAC0TXCR_TXPBL_Msk /*!< Transmit Programmable Burst Length */ -#define ETH_DMAC0TXCR_TXPBL_0 (0x1UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00010000 */ -#define ETH_DMAC0TXCR_TXPBL_1 (0x2UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00020000 */ -#define ETH_DMAC0TXCR_TXPBL_2 (0x4UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00040000 */ -#define ETH_DMAC0TXCR_TXPBL_3 (0x8UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00080000 */ -#define ETH_DMAC0TXCR_TXPBL_4 (0x10UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00100000 */ -#define ETH_DMAC0TXCR_TXPBL_5 (0x20UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00200000 */ +#define ETH_DMAC0TXCR_TXPBL_1PBL (0x1UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00010000 */ +#define ETH_DMAC0TXCR_TXPBL_2PBL (0x2UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00020000 */ +#define ETH_DMAC0TXCR_TXPBL_4PBL (0x4UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00040000 */ +#define ETH_DMAC0TXCR_TXPBL_8PBL (0x8UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00080000 */ +#define ETH_DMAC0TXCR_TXPBL_16PBL (0x10UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00100000 */ +#define ETH_DMAC0TXCR_TXPBL_32PBL (0x20UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00200000 */ #define ETH_DMAC0TXCR_TQOS_Pos (24U) #define ETH_DMAC0TXCR_TQOS_Msk (0xFUL << ETH_DMAC0TXCR_TQOS_Pos) /*!< 0x0F000000 */ #define ETH_DMAC0TXCR_TQOS ETH_DMAC0TXCR_TQOS_Msk /*!< Transmit QOS. */ @@ -14898,12 +14926,12 @@ typedef struct #define ETH_DMAC0RXCR_RXPBL_Pos (16U) #define ETH_DMAC0RXCR_RXPBL_Msk (0x3FUL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x003F0000 */ #define ETH_DMAC0RXCR_RXPBL ETH_DMAC0RXCR_RXPBL_Msk /*!< Receive Programmable Burst Length */ -#define ETH_DMAC0RXCR_RXPBL_0 (0x1UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00010000 */ -#define ETH_DMAC0RXCR_RXPBL_1 (0x2UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00020000 */ -#define ETH_DMAC0RXCR_RXPBL_2 (0x4UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00040000 */ -#define ETH_DMAC0RXCR_RXPBL_3 (0x8UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00080000 */ -#define ETH_DMAC0RXCR_RXPBL_4 (0x10UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00100000 */ -#define ETH_DMAC0RXCR_RXPBL_5 (0x20UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00200000 */ +#define ETH_DMAC0RXCR_RXPBL_1PBL (0x1UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00010000 */ +#define ETH_DMAC0RXCR_RXPBL_2PBL (0x2UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00020000 */ +#define ETH_DMAC0RXCR_RXPBL_4PBL (0x4UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00040000 */ +#define ETH_DMAC0RXCR_RXPBL_8PBL (0x8UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00080000 */ +#define ETH_DMAC0RXCR_RXPBL_16PBL (0x10UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00100000 */ +#define ETH_DMAC0RXCR_RXPBL_32PBL (0x20UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00200000 */ #define ETH_DMAC0RXCR_RQOS_Pos (24U) #define ETH_DMAC0RXCR_RQOS_Msk (0xFUL << ETH_DMAC0RXCR_RQOS_Pos) /*!< 0x0F000000 */ #define ETH_DMAC0RXCR_RQOS ETH_DMAC0RXCR_RQOS_Msk /*!< Rx AXI4 QOS. */ @@ -22841,6 +22869,16 @@ typedef struct #define BSEC_HWCFGR_ECC_USE_Msk (0xFUL << BSEC_HWCFGR_ECC_USE_Pos) /*!< 0x000000F0 */ #define BSEC_HWCFGR_ECC_USE BSEC_HWCFGR_ECC_USE_Msk /*!< protection / redundancy scheme used */ +/******************** Bit definition for BSEC_JTAGIN register ********************/ +#define BSEC_JTAGIN_DATA_Pos (0U) +#define BSEC_JTAGIN_DATA_Msk (0x0000FFFFUL << BSEC_JTAGIN_DATA_Pos) /*!< JTAG Input Data */ +#define BSEC_JTAGIN_DATA BSEC_JTAGIN_DATA_Msk + +/******************** Bit definition for BSEC_JTAGOUT register ********************/ +#define BSEC_JTAGOUT_DATA_Pos (0U) +#define BSEC_JTAGOUT_DATA_Msk (0x0000FFFFUL << BSEC_JTAGOUT_DATA_Pos) /*!< JTAG Output Data */ +#define BSEC_JTAGOUT_DATA BSEC_JTAGOUT_DATA_Msk + /******************** Bit definition for BSEC_VERR register********************/ #define BSEC_VERR_MINREV_Pos (0U) #define BSEC_VERR_MINREV_Msk (0xFUL << BSEC_VERR_MINREV_Pos) /*!< 0x0000000F */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151axx_cm4.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151axx_cm4.h index 34188e0fbe..361add47f6 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151axx_cm4.h +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151axx_cm4.h @@ -10679,16 +10679,19 @@ typedef struct #define ETH_MACCR_PRELEN_Pos (2U) #define ETH_MACCR_PRELEN_Msk (0x3UL << ETH_MACCR_PRELEN_Pos) /*!< 0x0000000C */ #define ETH_MACCR_PRELEN ETH_MACCR_PRELEN_Msk /*!< Preamble Length for Transmit packets */ -#define ETH_MACCR_PRELEN_0 (0x1UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000004 */ -#define ETH_MACCR_PRELEN_1 (0x2UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000008 */ +#define ETH_MACCR_PRELEN_7 (0x0UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000000 */ +#define ETH_MACCR_PRELEN_5 (0x1UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000004 */ +#define ETH_MACCR_PRELEN_3 (0x2UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000006 */ #define ETH_MACCR_DC_Pos (4U) #define ETH_MACCR_DC_Msk (0x1UL << ETH_MACCR_DC_Pos) /*!< 0x00000010 */ #define ETH_MACCR_DC ETH_MACCR_DC_Msk /*!< Deferral Check */ #define ETH_MACCR_BL_Pos (5U) #define ETH_MACCR_BL_Msk (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */ #define ETH_MACCR_BL ETH_MACCR_BL_Msk /*!< Back-Off Limit */ -#define ETH_MACCR_BL_0 (0x1UL << ETH_MACCR_BL_Pos) /*!< 0x00000020 */ -#define ETH_MACCR_BL_1 (0x2UL << ETH_MACCR_BL_Pos) /*!< 0x00000040 */ +#define ETH_MACCR_BL_10 (0x0UL << ETH_MACCR_BL_Pos) /*!< 0x00000000 */ +#define ETH_MACCR_BL_8 (0x1UL << ETH_MACCR_BL_Pos) /*!< 0x00000020 */ +#define ETH_MACCR_BL_4 (0x2UL << ETH_MACCR_BL_Pos) /*!< 0x00000040 */ +#define ETH_MACCR_BL_1 (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */ #define ETH_MACCR_DR_Pos (8U) #define ETH_MACCR_DR_Msk (0x1UL << ETH_MACCR_DR_Pos) /*!< 0x00000100 */ #define ETH_MACCR_DR ETH_MACCR_DR_Msk /*!< Disable Retry */ @@ -10740,9 +10743,14 @@ typedef struct #define ETH_MACCR_IPG_Pos (24U) #define ETH_MACCR_IPG_Msk (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */ #define ETH_MACCR_IPG ETH_MACCR_IPG_Msk /*!< Inter-Packet Gap */ -#define ETH_MACCR_IPG_0 (0x1UL << ETH_MACCR_IPG_Pos) /*!< 0x01000000 */ -#define ETH_MACCR_IPG_1 (0x2UL << ETH_MACCR_IPG_Pos) /*!< 0x02000000 */ -#define ETH_MACCR_IPG_2 (0x4UL << ETH_MACCR_IPG_Pos) /*!< 0x04000000 */ +#define ETH_MACCR_IPG_96BIT (0x0UL << ETH_MACCR_IPG_Pos) /*!< 0x00000000 */ +#define ETH_MACCR_IPG_88BIT (0x1UL << ETH_MACCR_IPG_Pos) /*!< 0x01000000 */ +#define ETH_MACCR_IPG_80BIT (0x2UL << ETH_MACCR_IPG_Pos) /*!< 0x02000000 */ +#define ETH_MACCR_IPG_72BIT (0x3UL << ETH_MACCR_IPG_Pos) /*!< 0x03000000 */ +#define ETH_MACCR_IPG_64BIT (0x4UL << ETH_MACCR_IPG_Pos) /*!< 0x04000000 */ +#define ETH_MACCR_IPG_56BIT (0x5UL << ETH_MACCR_IPG_Pos) /*!< 0x05000000 */ +#define ETH_MACCR_IPG_48BIT (0x6UL << ETH_MACCR_IPG_Pos) /*!< 0x06000000 */ +#define ETH_MACCR_IPG_40BIT (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */ #define ETH_MACCR_IPC_Pos (27U) #define ETH_MACCR_IPC_Msk (0x1UL << ETH_MACCR_IPC_Pos) /*!< 0x08000000 */ #define ETH_MACCR_IPC ETH_MACCR_IPC_Msk /*!< Checksum Offload */ @@ -10845,10 +10853,21 @@ typedef struct #define ETH_MACWTR_WTO_Pos (0U) #define ETH_MACWTR_WTO_Msk (0xFUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000F */ #define ETH_MACWTR_WTO ETH_MACWTR_WTO_Msk /*!< Watchdog Timeout */ -#define ETH_MACWTR_WTO_0 (0x1UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000001 */ -#define ETH_MACWTR_WTO_1 (0x2UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000002 */ -#define ETH_MACWTR_WTO_2 (0x4UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000004 */ -#define ETH_MACWTR_WTO_3 (0x8UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000008 */ +#define ETH_MACWTR_WTO_2KB (0x0UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000001 */ +#define ETH_MACWTR_WTO_3KB (0x1UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000001 */ +#define ETH_MACWTR_WTO_4KB (0x2UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000002 */ +#define ETH_MACWTR_WTO_5KB (0x3UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000003 */ +#define ETH_MACWTR_WTO_6KB (0x4UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000004 */ +#define ETH_MACWTR_WTO_7KB (0x5UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000005 */ +#define ETH_MACWTR_WTO_8KB (0x6UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000006 */ +#define ETH_MACWTR_WTO_9KB (0x7UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000007 */ +#define ETH_MACWTR_WTO_10KB (0x8UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000008 */ +#define ETH_MACWTR_WTO_11KB (0x9UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000009 */ +#define ETH_MACWTR_WTO_12KB (0xAUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000A */ +#define ETH_MACWTR_WTO_13KB (0xBUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000B */ +#define ETH_MACWTR_WTO_14KB (0xCUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000C */ +#define ETH_MACWTR_WTO_15KB (0xDUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000D */ +#define ETH_MACWTR_WTO_16KB (0xEUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000E */ #define ETH_MACWTR_PWE_Pos (8U) #define ETH_MACWTR_PWE_Msk (0x1UL << ETH_MACWTR_PWE_Pos) /*!< 0x00000100 */ #define ETH_MACWTR_PWE ETH_MACWTR_PWE_Msk /*!< Programmable Watchdog Enable */ @@ -10928,6 +10947,9 @@ typedef struct #define ETH_MACHT1R_HT63T32_31 (0x80000000UL << ETH_MACHT1R_HT63T32_Pos) /*!< 0x80000000 */ /************** Bit definition for ETH_MACVTR register ***************/ +#define ETH_MACVTR_VL_VID_Pos (0U) +#define ETH_MACVTR_VL_VID_Msk (0xFFFUL << ETH_MACVTR_VL_VID_Pos) /*!< 0x00000FFF */ +#define ETH_MACVTR_VL_VID ETH_MACVTR_VL_VID_Msk /*!< VLAN Tag Identifier field of VLAN tag */ #define ETH_MACVTR_VL_Pos (0U) #define ETH_MACVTR_VL_Msk (0xFFFFUL << ETH_MACVTR_VL_Pos) /*!< 0x0000FFFF */ #define ETH_MACVTR_VL ETH_MACVTR_VL_Msk /*!< VLAN Tag Identifier for Receive Packets */ @@ -11089,9 +11111,12 @@ typedef struct #define ETH_MACQ0TXFCR_PLT_Pos (4U) #define ETH_MACQ0TXFCR_PLT_Msk (0x7UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000070 */ #define ETH_MACQ0TXFCR_PLT ETH_MACQ0TXFCR_PLT_Msk /*!< Pause Low Threshold */ -#define ETH_MACQ0TXFCR_PLT_0 (0x1UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000010 */ -#define ETH_MACQ0TXFCR_PLT_1 (0x2UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000020 */ -#define ETH_MACQ0TXFCR_PLT_2 (0x4UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000040 */ +#define ETH_MACQ0TXFCR_PLT_MINUS4 (0x0UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000000 */ +#define ETH_MACQ0TXFCR_PLT_MINUS28 (0x1UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000010 */ +#define ETH_MACQ0TXFCR_PLT_MINUS36 (0x2UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000020 */ +#define ETH_MACQ0TXFCR_PLT_MINUS144 (0x3UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000030 */ +#define ETH_MACQ0TXFCR_PLT_MINUS256 (0x4UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000040 */ +#define ETH_MACQ0TXFCR_PLT_MINUS512 (0x5UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000050 */ #define ETH_MACQ0TXFCR_DZPQ_Pos (7U) #define ETH_MACQ0TXFCR_DZPQ_Msk (0x1UL << ETH_MACQ0TXFCR_DZPQ_Pos) /*!< 0x00000080 */ #define ETH_MACQ0TXFCR_DZPQ ETH_MACQ0TXFCR_DZPQ_Msk /*!< Disable Zero-Quanta Pause */ @@ -11658,10 +11683,12 @@ typedef struct #define ETH_MACMDIOAR_CR_Pos (8U) #define ETH_MACMDIOAR_CR_Msk (0xFUL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000F00 */ #define ETH_MACMDIOAR_CR ETH_MACMDIOAR_CR_Msk /*!< CSR Clock Range */ -#define ETH_MACMDIOAR_CR_0 (0x1UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000100 */ -#define ETH_MACMDIOAR_CR_1 (0x2UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000200 */ -#define ETH_MACMDIOAR_CR_2 (0x4UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000400 */ -#define ETH_MACMDIOAR_CR_3 (0x8UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000800 */ +#define ETH_MACMDIOAR_CR_DIV42 (0x0UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000000 */ +#define ETH_MACMDIOAR_CR_DIV62 (0x1UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000100 */ +#define ETH_MACMDIOAR_CR_DIV16 (0x2UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000200 */ +#define ETH_MACMDIOAR_CR_DIV26 (0x3UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000300 */ +#define ETH_MACMDIOAR_CR_DIV102 (0x4UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000400 */ +#define ETH_MACMDIOAR_CR_DIV124 (0x5UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000500 */ #define ETH_MACMDIOAR_NTC_Pos (12U) #define ETH_MACMDIOAR_NTC_Msk (0x7UL << ETH_MACMDIOAR_NTC_Pos) /*!< 0x00007000 */ #define ETH_MACMDIOAR_NTC ETH_MACMDIOAR_NTC_Msk /*!< Number of Training Clocks */ @@ -12100,7 +12127,7 @@ typedef struct #define ETH_MMCTXIMR_TXLPIUSCIM ETH_MMCTXIMR_TXLPIUSCIM_Msk /*!< MMC Transmit LPI microsecond counter interrupt Mask */ #define ETH_MMCTXIMR_TXLPITRCIM_Pos (27U) #define ETH_MMCTXIMR_TXLPITRCIM_Msk (0x1UL << ETH_MMCTXIMR_TXLPITRCIM_Pos) /*!< 0x08000000 */ -#define ETH_MMCTXIMR_TXLPITRCIM ETH_MMC_INTERRUPT_MASK_TXLPITRCIM_Msk /*!< MMC Transmit LPI transition counter interrupt Mask */ +#define ETH_MMCTXIMR_TXLPITRCIM ETH_MMCTXIMR_TXLPITRCIM_Msk /*!< MMC Transmit LPI transition counter interrupt Mask */ /*********** Bit definition for ETH_MMC_TX_SINGLE_COLLISION_GOOD_PACKETS register ************/ #define ETH_MMCTXSCGPR_TXSNGLCOLG_Pos (0U) @@ -14803,9 +14830,10 @@ typedef struct #define ETH_DMAC0CR_DSL_Pos (18U) #define ETH_DMAC0CR_DSL_Msk (0x7UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x001C0000 */ #define ETH_DMAC0CR_DSL ETH_DMAC0CR_DSL_Msk /*!< Descriptor Skip Length */ -#define ETH_DMAC0CR_DSL_0 (0x1UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00040000 */ -#define ETH_DMAC0CR_DSL_1 (0x2UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00080000 */ -#define ETH_DMAC0CR_DSL_2 (0x4UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00100000 */ +#define ETH_DMACCR_DSL_0BIT (0x0UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00000000 */ +#define ETH_DMACCR_DSL_32BIT (0x1UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00040000 */ +#define ETH_DMACCR_DSL_64BIT (0x2UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00080000 */ +#define ETH_DMACCR_DSL_128BIT (0x4UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00100000 */ /************* Bit definition for ETH_DMAC0TXCR register *************/ #define ETH_DMAC0TXCR_ST_Pos (0U) @@ -14826,12 +14854,12 @@ typedef struct #define ETH_DMAC0TXCR_TXPBL_Pos (16U) #define ETH_DMAC0TXCR_TXPBL_Msk (0x3FUL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x003F0000 */ #define ETH_DMAC0TXCR_TXPBL ETH_DMAC0TXCR_TXPBL_Msk /*!< Transmit Programmable Burst Length */ -#define ETH_DMAC0TXCR_TXPBL_0 (0x1UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00010000 */ -#define ETH_DMAC0TXCR_TXPBL_1 (0x2UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00020000 */ -#define ETH_DMAC0TXCR_TXPBL_2 (0x4UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00040000 */ -#define ETH_DMAC0TXCR_TXPBL_3 (0x8UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00080000 */ -#define ETH_DMAC0TXCR_TXPBL_4 (0x10UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00100000 */ -#define ETH_DMAC0TXCR_TXPBL_5 (0x20UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00200000 */ +#define ETH_DMAC0TXCR_TXPBL_1PBL (0x1UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00010000 */ +#define ETH_DMAC0TXCR_TXPBL_2PBL (0x2UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00020000 */ +#define ETH_DMAC0TXCR_TXPBL_4PBL (0x4UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00040000 */ +#define ETH_DMAC0TXCR_TXPBL_8PBL (0x8UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00080000 */ +#define ETH_DMAC0TXCR_TXPBL_16PBL (0x10UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00100000 */ +#define ETH_DMAC0TXCR_TXPBL_32PBL (0x20UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00200000 */ #define ETH_DMAC0TXCR_TQOS_Pos (24U) #define ETH_DMAC0TXCR_TQOS_Msk (0xFUL << ETH_DMAC0TXCR_TQOS_Pos) /*!< 0x0F000000 */ #define ETH_DMAC0TXCR_TQOS ETH_DMAC0TXCR_TQOS_Msk /*!< Transmit QOS. */ @@ -14864,12 +14892,12 @@ typedef struct #define ETH_DMAC0RXCR_RXPBL_Pos (16U) #define ETH_DMAC0RXCR_RXPBL_Msk (0x3FUL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x003F0000 */ #define ETH_DMAC0RXCR_RXPBL ETH_DMAC0RXCR_RXPBL_Msk /*!< Receive Programmable Burst Length */ -#define ETH_DMAC0RXCR_RXPBL_0 (0x1UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00010000 */ -#define ETH_DMAC0RXCR_RXPBL_1 (0x2UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00020000 */ -#define ETH_DMAC0RXCR_RXPBL_2 (0x4UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00040000 */ -#define ETH_DMAC0RXCR_RXPBL_3 (0x8UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00080000 */ -#define ETH_DMAC0RXCR_RXPBL_4 (0x10UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00100000 */ -#define ETH_DMAC0RXCR_RXPBL_5 (0x20UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00200000 */ +#define ETH_DMAC0RXCR_RXPBL_1PBL (0x1UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00010000 */ +#define ETH_DMAC0RXCR_RXPBL_2PBL (0x2UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00020000 */ +#define ETH_DMAC0RXCR_RXPBL_4PBL (0x4UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00040000 */ +#define ETH_DMAC0RXCR_RXPBL_8PBL (0x8UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00080000 */ +#define ETH_DMAC0RXCR_RXPBL_16PBL (0x10UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00100000 */ +#define ETH_DMAC0RXCR_RXPBL_32PBL (0x20UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00200000 */ #define ETH_DMAC0RXCR_RQOS_Pos (24U) #define ETH_DMAC0RXCR_RQOS_Msk (0xFUL << ETH_DMAC0RXCR_RQOS_Pos) /*!< 0x0F000000 */ #define ETH_DMAC0RXCR_RQOS ETH_DMAC0RXCR_RQOS_Msk /*!< Rx AXI4 QOS. */ @@ -22807,6 +22835,16 @@ typedef struct #define BSEC_HWCFGR_ECC_USE_Msk (0xFUL << BSEC_HWCFGR_ECC_USE_Pos) /*!< 0x000000F0 */ #define BSEC_HWCFGR_ECC_USE BSEC_HWCFGR_ECC_USE_Msk /*!< protection / redundancy scheme used */ +/******************** Bit definition for BSEC_JTAGIN register ********************/ +#define BSEC_JTAGIN_DATA_Pos (0U) +#define BSEC_JTAGIN_DATA_Msk (0x0000FFFFUL << BSEC_JTAGIN_DATA_Pos) /*!< JTAG Input Data */ +#define BSEC_JTAGIN_DATA BSEC_JTAGIN_DATA_Msk + +/******************** Bit definition for BSEC_JTAGOUT register ********************/ +#define BSEC_JTAGOUT_DATA_Pos (0U) +#define BSEC_JTAGOUT_DATA_Msk (0x0000FFFFUL << BSEC_JTAGOUT_DATA_Pos) /*!< JTAG Output Data */ +#define BSEC_JTAGOUT_DATA BSEC_JTAGOUT_DATA_Msk + /******************** Bit definition for BSEC_VERR register********************/ #define BSEC_VERR_MINREV_Pos (0U) #define BSEC_VERR_MINREV_Msk (0xFUL << BSEC_VERR_MINREV_Pos) /*!< 0x0000000F */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151cxx_ca7.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151cxx_ca7.h index 30b37c83e1..5e42245f2a 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151cxx_ca7.h +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151cxx_ca7.h @@ -10910,16 +10910,19 @@ typedef struct #define ETH_MACCR_PRELEN_Pos (2U) #define ETH_MACCR_PRELEN_Msk (0x3UL << ETH_MACCR_PRELEN_Pos) /*!< 0x0000000C */ #define ETH_MACCR_PRELEN ETH_MACCR_PRELEN_Msk /*!< Preamble Length for Transmit packets */ -#define ETH_MACCR_PRELEN_0 (0x1UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000004 */ -#define ETH_MACCR_PRELEN_1 (0x2UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000008 */ +#define ETH_MACCR_PRELEN_7 (0x0UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000000 */ +#define ETH_MACCR_PRELEN_5 (0x1UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000004 */ +#define ETH_MACCR_PRELEN_3 (0x2UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000006 */ #define ETH_MACCR_DC_Pos (4U) #define ETH_MACCR_DC_Msk (0x1UL << ETH_MACCR_DC_Pos) /*!< 0x00000010 */ #define ETH_MACCR_DC ETH_MACCR_DC_Msk /*!< Deferral Check */ #define ETH_MACCR_BL_Pos (5U) #define ETH_MACCR_BL_Msk (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */ #define ETH_MACCR_BL ETH_MACCR_BL_Msk /*!< Back-Off Limit */ -#define ETH_MACCR_BL_0 (0x1UL << ETH_MACCR_BL_Pos) /*!< 0x00000020 */ -#define ETH_MACCR_BL_1 (0x2UL << ETH_MACCR_BL_Pos) /*!< 0x00000040 */ +#define ETH_MACCR_BL_10 (0x0UL << ETH_MACCR_BL_Pos) /*!< 0x00000000 */ +#define ETH_MACCR_BL_8 (0x1UL << ETH_MACCR_BL_Pos) /*!< 0x00000020 */ +#define ETH_MACCR_BL_4 (0x2UL << ETH_MACCR_BL_Pos) /*!< 0x00000040 */ +#define ETH_MACCR_BL_1 (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */ #define ETH_MACCR_DR_Pos (8U) #define ETH_MACCR_DR_Msk (0x1UL << ETH_MACCR_DR_Pos) /*!< 0x00000100 */ #define ETH_MACCR_DR ETH_MACCR_DR_Msk /*!< Disable Retry */ @@ -10971,9 +10974,14 @@ typedef struct #define ETH_MACCR_IPG_Pos (24U) #define ETH_MACCR_IPG_Msk (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */ #define ETH_MACCR_IPG ETH_MACCR_IPG_Msk /*!< Inter-Packet Gap */ -#define ETH_MACCR_IPG_0 (0x1UL << ETH_MACCR_IPG_Pos) /*!< 0x01000000 */ -#define ETH_MACCR_IPG_1 (0x2UL << ETH_MACCR_IPG_Pos) /*!< 0x02000000 */ -#define ETH_MACCR_IPG_2 (0x4UL << ETH_MACCR_IPG_Pos) /*!< 0x04000000 */ +#define ETH_MACCR_IPG_96BIT (0x0UL << ETH_MACCR_IPG_Pos) /*!< 0x00000000 */ +#define ETH_MACCR_IPG_88BIT (0x1UL << ETH_MACCR_IPG_Pos) /*!< 0x01000000 */ +#define ETH_MACCR_IPG_80BIT (0x2UL << ETH_MACCR_IPG_Pos) /*!< 0x02000000 */ +#define ETH_MACCR_IPG_72BIT (0x3UL << ETH_MACCR_IPG_Pos) /*!< 0x03000000 */ +#define ETH_MACCR_IPG_64BIT (0x4UL << ETH_MACCR_IPG_Pos) /*!< 0x04000000 */ +#define ETH_MACCR_IPG_56BIT (0x5UL << ETH_MACCR_IPG_Pos) /*!< 0x05000000 */ +#define ETH_MACCR_IPG_48BIT (0x6UL << ETH_MACCR_IPG_Pos) /*!< 0x06000000 */ +#define ETH_MACCR_IPG_40BIT (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */ #define ETH_MACCR_IPC_Pos (27U) #define ETH_MACCR_IPC_Msk (0x1UL << ETH_MACCR_IPC_Pos) /*!< 0x08000000 */ #define ETH_MACCR_IPC ETH_MACCR_IPC_Msk /*!< Checksum Offload */ @@ -11076,10 +11084,21 @@ typedef struct #define ETH_MACWTR_WTO_Pos (0U) #define ETH_MACWTR_WTO_Msk (0xFUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000F */ #define ETH_MACWTR_WTO ETH_MACWTR_WTO_Msk /*!< Watchdog Timeout */ -#define ETH_MACWTR_WTO_0 (0x1UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000001 */ -#define ETH_MACWTR_WTO_1 (0x2UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000002 */ -#define ETH_MACWTR_WTO_2 (0x4UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000004 */ -#define ETH_MACWTR_WTO_3 (0x8UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000008 */ +#define ETH_MACWTR_WTO_2KB (0x0UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000001 */ +#define ETH_MACWTR_WTO_3KB (0x1UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000001 */ +#define ETH_MACWTR_WTO_4KB (0x2UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000002 */ +#define ETH_MACWTR_WTO_5KB (0x3UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000003 */ +#define ETH_MACWTR_WTO_6KB (0x4UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000004 */ +#define ETH_MACWTR_WTO_7KB (0x5UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000005 */ +#define ETH_MACWTR_WTO_8KB (0x6UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000006 */ +#define ETH_MACWTR_WTO_9KB (0x7UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000007 */ +#define ETH_MACWTR_WTO_10KB (0x8UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000008 */ +#define ETH_MACWTR_WTO_11KB (0x9UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000009 */ +#define ETH_MACWTR_WTO_12KB (0xAUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000A */ +#define ETH_MACWTR_WTO_13KB (0xBUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000B */ +#define ETH_MACWTR_WTO_14KB (0xCUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000C */ +#define ETH_MACWTR_WTO_15KB (0xDUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000D */ +#define ETH_MACWTR_WTO_16KB (0xEUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000E */ #define ETH_MACWTR_PWE_Pos (8U) #define ETH_MACWTR_PWE_Msk (0x1UL << ETH_MACWTR_PWE_Pos) /*!< 0x00000100 */ #define ETH_MACWTR_PWE ETH_MACWTR_PWE_Msk /*!< Programmable Watchdog Enable */ @@ -11159,6 +11178,9 @@ typedef struct #define ETH_MACHT1R_HT63T32_31 (0x80000000UL << ETH_MACHT1R_HT63T32_Pos) /*!< 0x80000000 */ /************** Bit definition for ETH_MACVTR register ***************/ +#define ETH_MACVTR_VL_VID_Pos (0U) +#define ETH_MACVTR_VL_VID_Msk (0xFFFUL << ETH_MACVTR_VL_VID_Pos) /*!< 0x00000FFF */ +#define ETH_MACVTR_VL_VID ETH_MACVTR_VL_VID_Msk /*!< VLAN Tag Identifier field of VLAN tag */ #define ETH_MACVTR_VL_Pos (0U) #define ETH_MACVTR_VL_Msk (0xFFFFUL << ETH_MACVTR_VL_Pos) /*!< 0x0000FFFF */ #define ETH_MACVTR_VL ETH_MACVTR_VL_Msk /*!< VLAN Tag Identifier for Receive Packets */ @@ -11320,9 +11342,12 @@ typedef struct #define ETH_MACQ0TXFCR_PLT_Pos (4U) #define ETH_MACQ0TXFCR_PLT_Msk (0x7UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000070 */ #define ETH_MACQ0TXFCR_PLT ETH_MACQ0TXFCR_PLT_Msk /*!< Pause Low Threshold */ -#define ETH_MACQ0TXFCR_PLT_0 (0x1UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000010 */ -#define ETH_MACQ0TXFCR_PLT_1 (0x2UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000020 */ -#define ETH_MACQ0TXFCR_PLT_2 (0x4UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000040 */ +#define ETH_MACQ0TXFCR_PLT_MINUS4 (0x0UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000000 */ +#define ETH_MACQ0TXFCR_PLT_MINUS28 (0x1UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000010 */ +#define ETH_MACQ0TXFCR_PLT_MINUS36 (0x2UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000020 */ +#define ETH_MACQ0TXFCR_PLT_MINUS144 (0x3UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000030 */ +#define ETH_MACQ0TXFCR_PLT_MINUS256 (0x4UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000040 */ +#define ETH_MACQ0TXFCR_PLT_MINUS512 (0x5UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000050 */ #define ETH_MACQ0TXFCR_DZPQ_Pos (7U) #define ETH_MACQ0TXFCR_DZPQ_Msk (0x1UL << ETH_MACQ0TXFCR_DZPQ_Pos) /*!< 0x00000080 */ #define ETH_MACQ0TXFCR_DZPQ ETH_MACQ0TXFCR_DZPQ_Msk /*!< Disable Zero-Quanta Pause */ @@ -11889,10 +11914,12 @@ typedef struct #define ETH_MACMDIOAR_CR_Pos (8U) #define ETH_MACMDIOAR_CR_Msk (0xFUL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000F00 */ #define ETH_MACMDIOAR_CR ETH_MACMDIOAR_CR_Msk /*!< CSR Clock Range */ -#define ETH_MACMDIOAR_CR_0 (0x1UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000100 */ -#define ETH_MACMDIOAR_CR_1 (0x2UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000200 */ -#define ETH_MACMDIOAR_CR_2 (0x4UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000400 */ -#define ETH_MACMDIOAR_CR_3 (0x8UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000800 */ +#define ETH_MACMDIOAR_CR_DIV42 (0x0UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000000 */ +#define ETH_MACMDIOAR_CR_DIV62 (0x1UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000100 */ +#define ETH_MACMDIOAR_CR_DIV16 (0x2UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000200 */ +#define ETH_MACMDIOAR_CR_DIV26 (0x3UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000300 */ +#define ETH_MACMDIOAR_CR_DIV102 (0x4UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000400 */ +#define ETH_MACMDIOAR_CR_DIV124 (0x5UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000500 */ #define ETH_MACMDIOAR_NTC_Pos (12U) #define ETH_MACMDIOAR_NTC_Msk (0x7UL << ETH_MACMDIOAR_NTC_Pos) /*!< 0x00007000 */ #define ETH_MACMDIOAR_NTC ETH_MACMDIOAR_NTC_Msk /*!< Number of Training Clocks */ @@ -12331,7 +12358,7 @@ typedef struct #define ETH_MMCTXIMR_TXLPIUSCIM ETH_MMCTXIMR_TXLPIUSCIM_Msk /*!< MMC Transmit LPI microsecond counter interrupt Mask */ #define ETH_MMCTXIMR_TXLPITRCIM_Pos (27U) #define ETH_MMCTXIMR_TXLPITRCIM_Msk (0x1UL << ETH_MMCTXIMR_TXLPITRCIM_Pos) /*!< 0x08000000 */ -#define ETH_MMCTXIMR_TXLPITRCIM ETH_MMC_INTERRUPT_MASK_TXLPITRCIM_Msk /*!< MMC Transmit LPI transition counter interrupt Mask */ +#define ETH_MMCTXIMR_TXLPITRCIM ETH_MMCTXIMR_TXLPITRCIM_Msk /*!< MMC Transmit LPI transition counter interrupt Mask */ /*********** Bit definition for ETH_MMC_TX_SINGLE_COLLISION_GOOD_PACKETS register ************/ #define ETH_MMCTXSCGPR_TXSNGLCOLG_Pos (0U) @@ -15034,9 +15061,10 @@ typedef struct #define ETH_DMAC0CR_DSL_Pos (18U) #define ETH_DMAC0CR_DSL_Msk (0x7UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x001C0000 */ #define ETH_DMAC0CR_DSL ETH_DMAC0CR_DSL_Msk /*!< Descriptor Skip Length */ -#define ETH_DMAC0CR_DSL_0 (0x1UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00040000 */ -#define ETH_DMAC0CR_DSL_1 (0x2UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00080000 */ -#define ETH_DMAC0CR_DSL_2 (0x4UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00100000 */ +#define ETH_DMACCR_DSL_0BIT (0x0UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00000000 */ +#define ETH_DMACCR_DSL_32BIT (0x1UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00040000 */ +#define ETH_DMACCR_DSL_64BIT (0x2UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00080000 */ +#define ETH_DMACCR_DSL_128BIT (0x4UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00100000 */ /************* Bit definition for ETH_DMAC0TXCR register *************/ #define ETH_DMAC0TXCR_ST_Pos (0U) @@ -15057,12 +15085,12 @@ typedef struct #define ETH_DMAC0TXCR_TXPBL_Pos (16U) #define ETH_DMAC0TXCR_TXPBL_Msk (0x3FUL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x003F0000 */ #define ETH_DMAC0TXCR_TXPBL ETH_DMAC0TXCR_TXPBL_Msk /*!< Transmit Programmable Burst Length */ -#define ETH_DMAC0TXCR_TXPBL_0 (0x1UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00010000 */ -#define ETH_DMAC0TXCR_TXPBL_1 (0x2UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00020000 */ -#define ETH_DMAC0TXCR_TXPBL_2 (0x4UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00040000 */ -#define ETH_DMAC0TXCR_TXPBL_3 (0x8UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00080000 */ -#define ETH_DMAC0TXCR_TXPBL_4 (0x10UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00100000 */ -#define ETH_DMAC0TXCR_TXPBL_5 (0x20UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00200000 */ +#define ETH_DMAC0TXCR_TXPBL_1PBL (0x1UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00010000 */ +#define ETH_DMAC0TXCR_TXPBL_2PBL (0x2UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00020000 */ +#define ETH_DMAC0TXCR_TXPBL_4PBL (0x4UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00040000 */ +#define ETH_DMAC0TXCR_TXPBL_8PBL (0x8UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00080000 */ +#define ETH_DMAC0TXCR_TXPBL_16PBL (0x10UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00100000 */ +#define ETH_DMAC0TXCR_TXPBL_32PBL (0x20UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00200000 */ #define ETH_DMAC0TXCR_TQOS_Pos (24U) #define ETH_DMAC0TXCR_TQOS_Msk (0xFUL << ETH_DMAC0TXCR_TQOS_Pos) /*!< 0x0F000000 */ #define ETH_DMAC0TXCR_TQOS ETH_DMAC0TXCR_TQOS_Msk /*!< Transmit QOS. */ @@ -15095,12 +15123,12 @@ typedef struct #define ETH_DMAC0RXCR_RXPBL_Pos (16U) #define ETH_DMAC0RXCR_RXPBL_Msk (0x3FUL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x003F0000 */ #define ETH_DMAC0RXCR_RXPBL ETH_DMAC0RXCR_RXPBL_Msk /*!< Receive Programmable Burst Length */ -#define ETH_DMAC0RXCR_RXPBL_0 (0x1UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00010000 */ -#define ETH_DMAC0RXCR_RXPBL_1 (0x2UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00020000 */ -#define ETH_DMAC0RXCR_RXPBL_2 (0x4UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00040000 */ -#define ETH_DMAC0RXCR_RXPBL_3 (0x8UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00080000 */ -#define ETH_DMAC0RXCR_RXPBL_4 (0x10UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00100000 */ -#define ETH_DMAC0RXCR_RXPBL_5 (0x20UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00200000 */ +#define ETH_DMAC0RXCR_RXPBL_1PBL (0x1UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00010000 */ +#define ETH_DMAC0RXCR_RXPBL_2PBL (0x2UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00020000 */ +#define ETH_DMAC0RXCR_RXPBL_4PBL (0x4UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00040000 */ +#define ETH_DMAC0RXCR_RXPBL_8PBL (0x8UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00080000 */ +#define ETH_DMAC0RXCR_RXPBL_16PBL (0x10UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00100000 */ +#define ETH_DMAC0RXCR_RXPBL_32PBL (0x20UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00200000 */ #define ETH_DMAC0RXCR_RQOS_Pos (24U) #define ETH_DMAC0RXCR_RQOS_Msk (0xFUL << ETH_DMAC0RXCR_RQOS_Pos) /*!< 0x0F000000 */ #define ETH_DMAC0RXCR_RQOS ETH_DMAC0RXCR_RQOS_Msk /*!< Rx AXI4 QOS. */ @@ -23038,6 +23066,16 @@ typedef struct #define BSEC_HWCFGR_ECC_USE_Msk (0xFUL << BSEC_HWCFGR_ECC_USE_Pos) /*!< 0x000000F0 */ #define BSEC_HWCFGR_ECC_USE BSEC_HWCFGR_ECC_USE_Msk /*!< protection / redundancy scheme used */ +/******************** Bit definition for BSEC_JTAGIN register ********************/ +#define BSEC_JTAGIN_DATA_Pos (0U) +#define BSEC_JTAGIN_DATA_Msk (0x0000FFFFUL << BSEC_JTAGIN_DATA_Pos) /*!< JTAG Input Data */ +#define BSEC_JTAGIN_DATA BSEC_JTAGIN_DATA_Msk + +/******************** Bit definition for BSEC_JTAGOUT register ********************/ +#define BSEC_JTAGOUT_DATA_Pos (0U) +#define BSEC_JTAGOUT_DATA_Msk (0x0000FFFFUL << BSEC_JTAGOUT_DATA_Pos) /*!< JTAG Output Data */ +#define BSEC_JTAGOUT_DATA BSEC_JTAGOUT_DATA_Msk + /******************** Bit definition for BSEC_VERR register********************/ #define BSEC_VERR_MINREV_Pos (0U) #define BSEC_VERR_MINREV_Msk (0xFUL << BSEC_VERR_MINREV_Pos) /*!< 0x0000000F */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151cxx_cm4.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151cxx_cm4.h index b3561409ab..55c61fa1d0 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151cxx_cm4.h +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151cxx_cm4.h @@ -10876,16 +10876,19 @@ typedef struct #define ETH_MACCR_PRELEN_Pos (2U) #define ETH_MACCR_PRELEN_Msk (0x3UL << ETH_MACCR_PRELEN_Pos) /*!< 0x0000000C */ #define ETH_MACCR_PRELEN ETH_MACCR_PRELEN_Msk /*!< Preamble Length for Transmit packets */ -#define ETH_MACCR_PRELEN_0 (0x1UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000004 */ -#define ETH_MACCR_PRELEN_1 (0x2UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000008 */ +#define ETH_MACCR_PRELEN_7 (0x0UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000000 */ +#define ETH_MACCR_PRELEN_5 (0x1UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000004 */ +#define ETH_MACCR_PRELEN_3 (0x2UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000006 */ #define ETH_MACCR_DC_Pos (4U) #define ETH_MACCR_DC_Msk (0x1UL << ETH_MACCR_DC_Pos) /*!< 0x00000010 */ #define ETH_MACCR_DC ETH_MACCR_DC_Msk /*!< Deferral Check */ #define ETH_MACCR_BL_Pos (5U) #define ETH_MACCR_BL_Msk (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */ #define ETH_MACCR_BL ETH_MACCR_BL_Msk /*!< Back-Off Limit */ -#define ETH_MACCR_BL_0 (0x1UL << ETH_MACCR_BL_Pos) /*!< 0x00000020 */ -#define ETH_MACCR_BL_1 (0x2UL << ETH_MACCR_BL_Pos) /*!< 0x00000040 */ +#define ETH_MACCR_BL_10 (0x0UL << ETH_MACCR_BL_Pos) /*!< 0x00000000 */ +#define ETH_MACCR_BL_8 (0x1UL << ETH_MACCR_BL_Pos) /*!< 0x00000020 */ +#define ETH_MACCR_BL_4 (0x2UL << ETH_MACCR_BL_Pos) /*!< 0x00000040 */ +#define ETH_MACCR_BL_1 (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */ #define ETH_MACCR_DR_Pos (8U) #define ETH_MACCR_DR_Msk (0x1UL << ETH_MACCR_DR_Pos) /*!< 0x00000100 */ #define ETH_MACCR_DR ETH_MACCR_DR_Msk /*!< Disable Retry */ @@ -10937,9 +10940,14 @@ typedef struct #define ETH_MACCR_IPG_Pos (24U) #define ETH_MACCR_IPG_Msk (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */ #define ETH_MACCR_IPG ETH_MACCR_IPG_Msk /*!< Inter-Packet Gap */ -#define ETH_MACCR_IPG_0 (0x1UL << ETH_MACCR_IPG_Pos) /*!< 0x01000000 */ -#define ETH_MACCR_IPG_1 (0x2UL << ETH_MACCR_IPG_Pos) /*!< 0x02000000 */ -#define ETH_MACCR_IPG_2 (0x4UL << ETH_MACCR_IPG_Pos) /*!< 0x04000000 */ +#define ETH_MACCR_IPG_96BIT (0x0UL << ETH_MACCR_IPG_Pos) /*!< 0x00000000 */ +#define ETH_MACCR_IPG_88BIT (0x1UL << ETH_MACCR_IPG_Pos) /*!< 0x01000000 */ +#define ETH_MACCR_IPG_80BIT (0x2UL << ETH_MACCR_IPG_Pos) /*!< 0x02000000 */ +#define ETH_MACCR_IPG_72BIT (0x3UL << ETH_MACCR_IPG_Pos) /*!< 0x03000000 */ +#define ETH_MACCR_IPG_64BIT (0x4UL << ETH_MACCR_IPG_Pos) /*!< 0x04000000 */ +#define ETH_MACCR_IPG_56BIT (0x5UL << ETH_MACCR_IPG_Pos) /*!< 0x05000000 */ +#define ETH_MACCR_IPG_48BIT (0x6UL << ETH_MACCR_IPG_Pos) /*!< 0x06000000 */ +#define ETH_MACCR_IPG_40BIT (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */ #define ETH_MACCR_IPC_Pos (27U) #define ETH_MACCR_IPC_Msk (0x1UL << ETH_MACCR_IPC_Pos) /*!< 0x08000000 */ #define ETH_MACCR_IPC ETH_MACCR_IPC_Msk /*!< Checksum Offload */ @@ -11042,10 +11050,21 @@ typedef struct #define ETH_MACWTR_WTO_Pos (0U) #define ETH_MACWTR_WTO_Msk (0xFUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000F */ #define ETH_MACWTR_WTO ETH_MACWTR_WTO_Msk /*!< Watchdog Timeout */ -#define ETH_MACWTR_WTO_0 (0x1UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000001 */ -#define ETH_MACWTR_WTO_1 (0x2UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000002 */ -#define ETH_MACWTR_WTO_2 (0x4UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000004 */ -#define ETH_MACWTR_WTO_3 (0x8UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000008 */ +#define ETH_MACWTR_WTO_2KB (0x0UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000001 */ +#define ETH_MACWTR_WTO_3KB (0x1UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000001 */ +#define ETH_MACWTR_WTO_4KB (0x2UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000002 */ +#define ETH_MACWTR_WTO_5KB (0x3UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000003 */ +#define ETH_MACWTR_WTO_6KB (0x4UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000004 */ +#define ETH_MACWTR_WTO_7KB (0x5UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000005 */ +#define ETH_MACWTR_WTO_8KB (0x6UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000006 */ +#define ETH_MACWTR_WTO_9KB (0x7UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000007 */ +#define ETH_MACWTR_WTO_10KB (0x8UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000008 */ +#define ETH_MACWTR_WTO_11KB (0x9UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000009 */ +#define ETH_MACWTR_WTO_12KB (0xAUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000A */ +#define ETH_MACWTR_WTO_13KB (0xBUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000B */ +#define ETH_MACWTR_WTO_14KB (0xCUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000C */ +#define ETH_MACWTR_WTO_15KB (0xDUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000D */ +#define ETH_MACWTR_WTO_16KB (0xEUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000E */ #define ETH_MACWTR_PWE_Pos (8U) #define ETH_MACWTR_PWE_Msk (0x1UL << ETH_MACWTR_PWE_Pos) /*!< 0x00000100 */ #define ETH_MACWTR_PWE ETH_MACWTR_PWE_Msk /*!< Programmable Watchdog Enable */ @@ -11125,6 +11144,9 @@ typedef struct #define ETH_MACHT1R_HT63T32_31 (0x80000000UL << ETH_MACHT1R_HT63T32_Pos) /*!< 0x80000000 */ /************** Bit definition for ETH_MACVTR register ***************/ +#define ETH_MACVTR_VL_VID_Pos (0U) +#define ETH_MACVTR_VL_VID_Msk (0xFFFUL << ETH_MACVTR_VL_VID_Pos) /*!< 0x00000FFF */ +#define ETH_MACVTR_VL_VID ETH_MACVTR_VL_VID_Msk /*!< VLAN Tag Identifier field of VLAN tag */ #define ETH_MACVTR_VL_Pos (0U) #define ETH_MACVTR_VL_Msk (0xFFFFUL << ETH_MACVTR_VL_Pos) /*!< 0x0000FFFF */ #define ETH_MACVTR_VL ETH_MACVTR_VL_Msk /*!< VLAN Tag Identifier for Receive Packets */ @@ -11286,9 +11308,12 @@ typedef struct #define ETH_MACQ0TXFCR_PLT_Pos (4U) #define ETH_MACQ0TXFCR_PLT_Msk (0x7UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000070 */ #define ETH_MACQ0TXFCR_PLT ETH_MACQ0TXFCR_PLT_Msk /*!< Pause Low Threshold */ -#define ETH_MACQ0TXFCR_PLT_0 (0x1UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000010 */ -#define ETH_MACQ0TXFCR_PLT_1 (0x2UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000020 */ -#define ETH_MACQ0TXFCR_PLT_2 (0x4UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000040 */ +#define ETH_MACQ0TXFCR_PLT_MINUS4 (0x0UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000000 */ +#define ETH_MACQ0TXFCR_PLT_MINUS28 (0x1UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000010 */ +#define ETH_MACQ0TXFCR_PLT_MINUS36 (0x2UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000020 */ +#define ETH_MACQ0TXFCR_PLT_MINUS144 (0x3UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000030 */ +#define ETH_MACQ0TXFCR_PLT_MINUS256 (0x4UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000040 */ +#define ETH_MACQ0TXFCR_PLT_MINUS512 (0x5UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000050 */ #define ETH_MACQ0TXFCR_DZPQ_Pos (7U) #define ETH_MACQ0TXFCR_DZPQ_Msk (0x1UL << ETH_MACQ0TXFCR_DZPQ_Pos) /*!< 0x00000080 */ #define ETH_MACQ0TXFCR_DZPQ ETH_MACQ0TXFCR_DZPQ_Msk /*!< Disable Zero-Quanta Pause */ @@ -11855,10 +11880,12 @@ typedef struct #define ETH_MACMDIOAR_CR_Pos (8U) #define ETH_MACMDIOAR_CR_Msk (0xFUL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000F00 */ #define ETH_MACMDIOAR_CR ETH_MACMDIOAR_CR_Msk /*!< CSR Clock Range */ -#define ETH_MACMDIOAR_CR_0 (0x1UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000100 */ -#define ETH_MACMDIOAR_CR_1 (0x2UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000200 */ -#define ETH_MACMDIOAR_CR_2 (0x4UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000400 */ -#define ETH_MACMDIOAR_CR_3 (0x8UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000800 */ +#define ETH_MACMDIOAR_CR_DIV42 (0x0UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000000 */ +#define ETH_MACMDIOAR_CR_DIV62 (0x1UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000100 */ +#define ETH_MACMDIOAR_CR_DIV16 (0x2UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000200 */ +#define ETH_MACMDIOAR_CR_DIV26 (0x3UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000300 */ +#define ETH_MACMDIOAR_CR_DIV102 (0x4UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000400 */ +#define ETH_MACMDIOAR_CR_DIV124 (0x5UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000500 */ #define ETH_MACMDIOAR_NTC_Pos (12U) #define ETH_MACMDIOAR_NTC_Msk (0x7UL << ETH_MACMDIOAR_NTC_Pos) /*!< 0x00007000 */ #define ETH_MACMDIOAR_NTC ETH_MACMDIOAR_NTC_Msk /*!< Number of Training Clocks */ @@ -12297,7 +12324,7 @@ typedef struct #define ETH_MMCTXIMR_TXLPIUSCIM ETH_MMCTXIMR_TXLPIUSCIM_Msk /*!< MMC Transmit LPI microsecond counter interrupt Mask */ #define ETH_MMCTXIMR_TXLPITRCIM_Pos (27U) #define ETH_MMCTXIMR_TXLPITRCIM_Msk (0x1UL << ETH_MMCTXIMR_TXLPITRCIM_Pos) /*!< 0x08000000 */ -#define ETH_MMCTXIMR_TXLPITRCIM ETH_MMC_INTERRUPT_MASK_TXLPITRCIM_Msk /*!< MMC Transmit LPI transition counter interrupt Mask */ +#define ETH_MMCTXIMR_TXLPITRCIM ETH_MMCTXIMR_TXLPITRCIM_Msk /*!< MMC Transmit LPI transition counter interrupt Mask */ /*********** Bit definition for ETH_MMC_TX_SINGLE_COLLISION_GOOD_PACKETS register ************/ #define ETH_MMCTXSCGPR_TXSNGLCOLG_Pos (0U) @@ -15000,9 +15027,10 @@ typedef struct #define ETH_DMAC0CR_DSL_Pos (18U) #define ETH_DMAC0CR_DSL_Msk (0x7UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x001C0000 */ #define ETH_DMAC0CR_DSL ETH_DMAC0CR_DSL_Msk /*!< Descriptor Skip Length */ -#define ETH_DMAC0CR_DSL_0 (0x1UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00040000 */ -#define ETH_DMAC0CR_DSL_1 (0x2UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00080000 */ -#define ETH_DMAC0CR_DSL_2 (0x4UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00100000 */ +#define ETH_DMACCR_DSL_0BIT (0x0UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00000000 */ +#define ETH_DMACCR_DSL_32BIT (0x1UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00040000 */ +#define ETH_DMACCR_DSL_64BIT (0x2UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00080000 */ +#define ETH_DMACCR_DSL_128BIT (0x4UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00100000 */ /************* Bit definition for ETH_DMAC0TXCR register *************/ #define ETH_DMAC0TXCR_ST_Pos (0U) @@ -15023,12 +15051,12 @@ typedef struct #define ETH_DMAC0TXCR_TXPBL_Pos (16U) #define ETH_DMAC0TXCR_TXPBL_Msk (0x3FUL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x003F0000 */ #define ETH_DMAC0TXCR_TXPBL ETH_DMAC0TXCR_TXPBL_Msk /*!< Transmit Programmable Burst Length */ -#define ETH_DMAC0TXCR_TXPBL_0 (0x1UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00010000 */ -#define ETH_DMAC0TXCR_TXPBL_1 (0x2UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00020000 */ -#define ETH_DMAC0TXCR_TXPBL_2 (0x4UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00040000 */ -#define ETH_DMAC0TXCR_TXPBL_3 (0x8UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00080000 */ -#define ETH_DMAC0TXCR_TXPBL_4 (0x10UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00100000 */ -#define ETH_DMAC0TXCR_TXPBL_5 (0x20UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00200000 */ +#define ETH_DMAC0TXCR_TXPBL_1PBL (0x1UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00010000 */ +#define ETH_DMAC0TXCR_TXPBL_2PBL (0x2UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00020000 */ +#define ETH_DMAC0TXCR_TXPBL_4PBL (0x4UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00040000 */ +#define ETH_DMAC0TXCR_TXPBL_8PBL (0x8UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00080000 */ +#define ETH_DMAC0TXCR_TXPBL_16PBL (0x10UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00100000 */ +#define ETH_DMAC0TXCR_TXPBL_32PBL (0x20UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00200000 */ #define ETH_DMAC0TXCR_TQOS_Pos (24U) #define ETH_DMAC0TXCR_TQOS_Msk (0xFUL << ETH_DMAC0TXCR_TQOS_Pos) /*!< 0x0F000000 */ #define ETH_DMAC0TXCR_TQOS ETH_DMAC0TXCR_TQOS_Msk /*!< Transmit QOS. */ @@ -15061,12 +15089,12 @@ typedef struct #define ETH_DMAC0RXCR_RXPBL_Pos (16U) #define ETH_DMAC0RXCR_RXPBL_Msk (0x3FUL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x003F0000 */ #define ETH_DMAC0RXCR_RXPBL ETH_DMAC0RXCR_RXPBL_Msk /*!< Receive Programmable Burst Length */ -#define ETH_DMAC0RXCR_RXPBL_0 (0x1UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00010000 */ -#define ETH_DMAC0RXCR_RXPBL_1 (0x2UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00020000 */ -#define ETH_DMAC0RXCR_RXPBL_2 (0x4UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00040000 */ -#define ETH_DMAC0RXCR_RXPBL_3 (0x8UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00080000 */ -#define ETH_DMAC0RXCR_RXPBL_4 (0x10UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00100000 */ -#define ETH_DMAC0RXCR_RXPBL_5 (0x20UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00200000 */ +#define ETH_DMAC0RXCR_RXPBL_1PBL (0x1UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00010000 */ +#define ETH_DMAC0RXCR_RXPBL_2PBL (0x2UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00020000 */ +#define ETH_DMAC0RXCR_RXPBL_4PBL (0x4UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00040000 */ +#define ETH_DMAC0RXCR_RXPBL_8PBL (0x8UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00080000 */ +#define ETH_DMAC0RXCR_RXPBL_16PBL (0x10UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00100000 */ +#define ETH_DMAC0RXCR_RXPBL_32PBL (0x20UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00200000 */ #define ETH_DMAC0RXCR_RQOS_Pos (24U) #define ETH_DMAC0RXCR_RQOS_Msk (0xFUL << ETH_DMAC0RXCR_RQOS_Pos) /*!< 0x0F000000 */ #define ETH_DMAC0RXCR_RQOS ETH_DMAC0RXCR_RQOS_Msk /*!< Rx AXI4 QOS. */ @@ -23004,6 +23032,16 @@ typedef struct #define BSEC_HWCFGR_ECC_USE_Msk (0xFUL << BSEC_HWCFGR_ECC_USE_Pos) /*!< 0x000000F0 */ #define BSEC_HWCFGR_ECC_USE BSEC_HWCFGR_ECC_USE_Msk /*!< protection / redundancy scheme used */ +/******************** Bit definition for BSEC_JTAGIN register ********************/ +#define BSEC_JTAGIN_DATA_Pos (0U) +#define BSEC_JTAGIN_DATA_Msk (0x0000FFFFUL << BSEC_JTAGIN_DATA_Pos) /*!< JTAG Input Data */ +#define BSEC_JTAGIN_DATA BSEC_JTAGIN_DATA_Msk + +/******************** Bit definition for BSEC_JTAGOUT register ********************/ +#define BSEC_JTAGOUT_DATA_Pos (0U) +#define BSEC_JTAGOUT_DATA_Msk (0x0000FFFFUL << BSEC_JTAGOUT_DATA_Pos) /*!< JTAG Output Data */ +#define BSEC_JTAGOUT_DATA BSEC_JTAGOUT_DATA_Msk + /******************** Bit definition for BSEC_VERR register********************/ #define BSEC_VERR_MINREV_Pos (0U) #define BSEC_VERR_MINREV_Msk (0xFUL << BSEC_VERR_MINREV_Pos) /*!< 0x0000000F */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151dxx_ca7.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151dxx_ca7.h index 223c36c325..190417e0c7 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151dxx_ca7.h +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151dxx_ca7.h @@ -10713,16 +10713,19 @@ typedef struct #define ETH_MACCR_PRELEN_Pos (2U) #define ETH_MACCR_PRELEN_Msk (0x3UL << ETH_MACCR_PRELEN_Pos) /*!< 0x0000000C */ #define ETH_MACCR_PRELEN ETH_MACCR_PRELEN_Msk /*!< Preamble Length for Transmit packets */ -#define ETH_MACCR_PRELEN_0 (0x1UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000004 */ -#define ETH_MACCR_PRELEN_1 (0x2UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000008 */ +#define ETH_MACCR_PRELEN_7 (0x0UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000000 */ +#define ETH_MACCR_PRELEN_5 (0x1UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000004 */ +#define ETH_MACCR_PRELEN_3 (0x2UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000006 */ #define ETH_MACCR_DC_Pos (4U) #define ETH_MACCR_DC_Msk (0x1UL << ETH_MACCR_DC_Pos) /*!< 0x00000010 */ #define ETH_MACCR_DC ETH_MACCR_DC_Msk /*!< Deferral Check */ #define ETH_MACCR_BL_Pos (5U) #define ETH_MACCR_BL_Msk (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */ #define ETH_MACCR_BL ETH_MACCR_BL_Msk /*!< Back-Off Limit */ -#define ETH_MACCR_BL_0 (0x1UL << ETH_MACCR_BL_Pos) /*!< 0x00000020 */ -#define ETH_MACCR_BL_1 (0x2UL << ETH_MACCR_BL_Pos) /*!< 0x00000040 */ +#define ETH_MACCR_BL_10 (0x0UL << ETH_MACCR_BL_Pos) /*!< 0x00000000 */ +#define ETH_MACCR_BL_8 (0x1UL << ETH_MACCR_BL_Pos) /*!< 0x00000020 */ +#define ETH_MACCR_BL_4 (0x2UL << ETH_MACCR_BL_Pos) /*!< 0x00000040 */ +#define ETH_MACCR_BL_1 (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */ #define ETH_MACCR_DR_Pos (8U) #define ETH_MACCR_DR_Msk (0x1UL << ETH_MACCR_DR_Pos) /*!< 0x00000100 */ #define ETH_MACCR_DR ETH_MACCR_DR_Msk /*!< Disable Retry */ @@ -10774,9 +10777,14 @@ typedef struct #define ETH_MACCR_IPG_Pos (24U) #define ETH_MACCR_IPG_Msk (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */ #define ETH_MACCR_IPG ETH_MACCR_IPG_Msk /*!< Inter-Packet Gap */ -#define ETH_MACCR_IPG_0 (0x1UL << ETH_MACCR_IPG_Pos) /*!< 0x01000000 */ -#define ETH_MACCR_IPG_1 (0x2UL << ETH_MACCR_IPG_Pos) /*!< 0x02000000 */ -#define ETH_MACCR_IPG_2 (0x4UL << ETH_MACCR_IPG_Pos) /*!< 0x04000000 */ +#define ETH_MACCR_IPG_96BIT (0x0UL << ETH_MACCR_IPG_Pos) /*!< 0x00000000 */ +#define ETH_MACCR_IPG_88BIT (0x1UL << ETH_MACCR_IPG_Pos) /*!< 0x01000000 */ +#define ETH_MACCR_IPG_80BIT (0x2UL << ETH_MACCR_IPG_Pos) /*!< 0x02000000 */ +#define ETH_MACCR_IPG_72BIT (0x3UL << ETH_MACCR_IPG_Pos) /*!< 0x03000000 */ +#define ETH_MACCR_IPG_64BIT (0x4UL << ETH_MACCR_IPG_Pos) /*!< 0x04000000 */ +#define ETH_MACCR_IPG_56BIT (0x5UL << ETH_MACCR_IPG_Pos) /*!< 0x05000000 */ +#define ETH_MACCR_IPG_48BIT (0x6UL << ETH_MACCR_IPG_Pos) /*!< 0x06000000 */ +#define ETH_MACCR_IPG_40BIT (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */ #define ETH_MACCR_IPC_Pos (27U) #define ETH_MACCR_IPC_Msk (0x1UL << ETH_MACCR_IPC_Pos) /*!< 0x08000000 */ #define ETH_MACCR_IPC ETH_MACCR_IPC_Msk /*!< Checksum Offload */ @@ -10879,10 +10887,21 @@ typedef struct #define ETH_MACWTR_WTO_Pos (0U) #define ETH_MACWTR_WTO_Msk (0xFUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000F */ #define ETH_MACWTR_WTO ETH_MACWTR_WTO_Msk /*!< Watchdog Timeout */ -#define ETH_MACWTR_WTO_0 (0x1UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000001 */ -#define ETH_MACWTR_WTO_1 (0x2UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000002 */ -#define ETH_MACWTR_WTO_2 (0x4UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000004 */ -#define ETH_MACWTR_WTO_3 (0x8UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000008 */ +#define ETH_MACWTR_WTO_2KB (0x0UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000001 */ +#define ETH_MACWTR_WTO_3KB (0x1UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000001 */ +#define ETH_MACWTR_WTO_4KB (0x2UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000002 */ +#define ETH_MACWTR_WTO_5KB (0x3UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000003 */ +#define ETH_MACWTR_WTO_6KB (0x4UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000004 */ +#define ETH_MACWTR_WTO_7KB (0x5UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000005 */ +#define ETH_MACWTR_WTO_8KB (0x6UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000006 */ +#define ETH_MACWTR_WTO_9KB (0x7UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000007 */ +#define ETH_MACWTR_WTO_10KB (0x8UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000008 */ +#define ETH_MACWTR_WTO_11KB (0x9UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000009 */ +#define ETH_MACWTR_WTO_12KB (0xAUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000A */ +#define ETH_MACWTR_WTO_13KB (0xBUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000B */ +#define ETH_MACWTR_WTO_14KB (0xCUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000C */ +#define ETH_MACWTR_WTO_15KB (0xDUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000D */ +#define ETH_MACWTR_WTO_16KB (0xEUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000E */ #define ETH_MACWTR_PWE_Pos (8U) #define ETH_MACWTR_PWE_Msk (0x1UL << ETH_MACWTR_PWE_Pos) /*!< 0x00000100 */ #define ETH_MACWTR_PWE ETH_MACWTR_PWE_Msk /*!< Programmable Watchdog Enable */ @@ -10962,6 +10981,9 @@ typedef struct #define ETH_MACHT1R_HT63T32_31 (0x80000000UL << ETH_MACHT1R_HT63T32_Pos) /*!< 0x80000000 */ /************** Bit definition for ETH_MACVTR register ***************/ +#define ETH_MACVTR_VL_VID_Pos (0U) +#define ETH_MACVTR_VL_VID_Msk (0xFFFUL << ETH_MACVTR_VL_VID_Pos) /*!< 0x00000FFF */ +#define ETH_MACVTR_VL_VID ETH_MACVTR_VL_VID_Msk /*!< VLAN Tag Identifier field of VLAN tag */ #define ETH_MACVTR_VL_Pos (0U) #define ETH_MACVTR_VL_Msk (0xFFFFUL << ETH_MACVTR_VL_Pos) /*!< 0x0000FFFF */ #define ETH_MACVTR_VL ETH_MACVTR_VL_Msk /*!< VLAN Tag Identifier for Receive Packets */ @@ -11123,9 +11145,12 @@ typedef struct #define ETH_MACQ0TXFCR_PLT_Pos (4U) #define ETH_MACQ0TXFCR_PLT_Msk (0x7UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000070 */ #define ETH_MACQ0TXFCR_PLT ETH_MACQ0TXFCR_PLT_Msk /*!< Pause Low Threshold */ -#define ETH_MACQ0TXFCR_PLT_0 (0x1UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000010 */ -#define ETH_MACQ0TXFCR_PLT_1 (0x2UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000020 */ -#define ETH_MACQ0TXFCR_PLT_2 (0x4UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000040 */ +#define ETH_MACQ0TXFCR_PLT_MINUS4 (0x0UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000000 */ +#define ETH_MACQ0TXFCR_PLT_MINUS28 (0x1UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000010 */ +#define ETH_MACQ0TXFCR_PLT_MINUS36 (0x2UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000020 */ +#define ETH_MACQ0TXFCR_PLT_MINUS144 (0x3UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000030 */ +#define ETH_MACQ0TXFCR_PLT_MINUS256 (0x4UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000040 */ +#define ETH_MACQ0TXFCR_PLT_MINUS512 (0x5UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000050 */ #define ETH_MACQ0TXFCR_DZPQ_Pos (7U) #define ETH_MACQ0TXFCR_DZPQ_Msk (0x1UL << ETH_MACQ0TXFCR_DZPQ_Pos) /*!< 0x00000080 */ #define ETH_MACQ0TXFCR_DZPQ ETH_MACQ0TXFCR_DZPQ_Msk /*!< Disable Zero-Quanta Pause */ @@ -11692,10 +11717,12 @@ typedef struct #define ETH_MACMDIOAR_CR_Pos (8U) #define ETH_MACMDIOAR_CR_Msk (0xFUL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000F00 */ #define ETH_MACMDIOAR_CR ETH_MACMDIOAR_CR_Msk /*!< CSR Clock Range */ -#define ETH_MACMDIOAR_CR_0 (0x1UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000100 */ -#define ETH_MACMDIOAR_CR_1 (0x2UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000200 */ -#define ETH_MACMDIOAR_CR_2 (0x4UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000400 */ -#define ETH_MACMDIOAR_CR_3 (0x8UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000800 */ +#define ETH_MACMDIOAR_CR_DIV42 (0x0UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000000 */ +#define ETH_MACMDIOAR_CR_DIV62 (0x1UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000100 */ +#define ETH_MACMDIOAR_CR_DIV16 (0x2UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000200 */ +#define ETH_MACMDIOAR_CR_DIV26 (0x3UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000300 */ +#define ETH_MACMDIOAR_CR_DIV102 (0x4UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000400 */ +#define ETH_MACMDIOAR_CR_DIV124 (0x5UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000500 */ #define ETH_MACMDIOAR_NTC_Pos (12U) #define ETH_MACMDIOAR_NTC_Msk (0x7UL << ETH_MACMDIOAR_NTC_Pos) /*!< 0x00007000 */ #define ETH_MACMDIOAR_NTC ETH_MACMDIOAR_NTC_Msk /*!< Number of Training Clocks */ @@ -12134,7 +12161,7 @@ typedef struct #define ETH_MMCTXIMR_TXLPIUSCIM ETH_MMCTXIMR_TXLPIUSCIM_Msk /*!< MMC Transmit LPI microsecond counter interrupt Mask */ #define ETH_MMCTXIMR_TXLPITRCIM_Pos (27U) #define ETH_MMCTXIMR_TXLPITRCIM_Msk (0x1UL << ETH_MMCTXIMR_TXLPITRCIM_Pos) /*!< 0x08000000 */ -#define ETH_MMCTXIMR_TXLPITRCIM ETH_MMC_INTERRUPT_MASK_TXLPITRCIM_Msk /*!< MMC Transmit LPI transition counter interrupt Mask */ +#define ETH_MMCTXIMR_TXLPITRCIM ETH_MMCTXIMR_TXLPITRCIM_Msk /*!< MMC Transmit LPI transition counter interrupt Mask */ /*********** Bit definition for ETH_MMC_TX_SINGLE_COLLISION_GOOD_PACKETS register ************/ #define ETH_MMCTXSCGPR_TXSNGLCOLG_Pos (0U) @@ -14837,9 +14864,10 @@ typedef struct #define ETH_DMAC0CR_DSL_Pos (18U) #define ETH_DMAC0CR_DSL_Msk (0x7UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x001C0000 */ #define ETH_DMAC0CR_DSL ETH_DMAC0CR_DSL_Msk /*!< Descriptor Skip Length */ -#define ETH_DMAC0CR_DSL_0 (0x1UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00040000 */ -#define ETH_DMAC0CR_DSL_1 (0x2UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00080000 */ -#define ETH_DMAC0CR_DSL_2 (0x4UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00100000 */ +#define ETH_DMACCR_DSL_0BIT (0x0UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00000000 */ +#define ETH_DMACCR_DSL_32BIT (0x1UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00040000 */ +#define ETH_DMACCR_DSL_64BIT (0x2UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00080000 */ +#define ETH_DMACCR_DSL_128BIT (0x4UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00100000 */ /************* Bit definition for ETH_DMAC0TXCR register *************/ #define ETH_DMAC0TXCR_ST_Pos (0U) @@ -14860,12 +14888,12 @@ typedef struct #define ETH_DMAC0TXCR_TXPBL_Pos (16U) #define ETH_DMAC0TXCR_TXPBL_Msk (0x3FUL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x003F0000 */ #define ETH_DMAC0TXCR_TXPBL ETH_DMAC0TXCR_TXPBL_Msk /*!< Transmit Programmable Burst Length */ -#define ETH_DMAC0TXCR_TXPBL_0 (0x1UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00010000 */ -#define ETH_DMAC0TXCR_TXPBL_1 (0x2UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00020000 */ -#define ETH_DMAC0TXCR_TXPBL_2 (0x4UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00040000 */ -#define ETH_DMAC0TXCR_TXPBL_3 (0x8UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00080000 */ -#define ETH_DMAC0TXCR_TXPBL_4 (0x10UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00100000 */ -#define ETH_DMAC0TXCR_TXPBL_5 (0x20UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00200000 */ +#define ETH_DMAC0TXCR_TXPBL_1PBL (0x1UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00010000 */ +#define ETH_DMAC0TXCR_TXPBL_2PBL (0x2UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00020000 */ +#define ETH_DMAC0TXCR_TXPBL_4PBL (0x4UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00040000 */ +#define ETH_DMAC0TXCR_TXPBL_8PBL (0x8UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00080000 */ +#define ETH_DMAC0TXCR_TXPBL_16PBL (0x10UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00100000 */ +#define ETH_DMAC0TXCR_TXPBL_32PBL (0x20UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00200000 */ #define ETH_DMAC0TXCR_TQOS_Pos (24U) #define ETH_DMAC0TXCR_TQOS_Msk (0xFUL << ETH_DMAC0TXCR_TQOS_Pos) /*!< 0x0F000000 */ #define ETH_DMAC0TXCR_TQOS ETH_DMAC0TXCR_TQOS_Msk /*!< Transmit QOS. */ @@ -14898,12 +14926,12 @@ typedef struct #define ETH_DMAC0RXCR_RXPBL_Pos (16U) #define ETH_DMAC0RXCR_RXPBL_Msk (0x3FUL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x003F0000 */ #define ETH_DMAC0RXCR_RXPBL ETH_DMAC0RXCR_RXPBL_Msk /*!< Receive Programmable Burst Length */ -#define ETH_DMAC0RXCR_RXPBL_0 (0x1UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00010000 */ -#define ETH_DMAC0RXCR_RXPBL_1 (0x2UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00020000 */ -#define ETH_DMAC0RXCR_RXPBL_2 (0x4UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00040000 */ -#define ETH_DMAC0RXCR_RXPBL_3 (0x8UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00080000 */ -#define ETH_DMAC0RXCR_RXPBL_4 (0x10UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00100000 */ -#define ETH_DMAC0RXCR_RXPBL_5 (0x20UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00200000 */ +#define ETH_DMAC0RXCR_RXPBL_1PBL (0x1UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00010000 */ +#define ETH_DMAC0RXCR_RXPBL_2PBL (0x2UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00020000 */ +#define ETH_DMAC0RXCR_RXPBL_4PBL (0x4UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00040000 */ +#define ETH_DMAC0RXCR_RXPBL_8PBL (0x8UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00080000 */ +#define ETH_DMAC0RXCR_RXPBL_16PBL (0x10UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00100000 */ +#define ETH_DMAC0RXCR_RXPBL_32PBL (0x20UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00200000 */ #define ETH_DMAC0RXCR_RQOS_Pos (24U) #define ETH_DMAC0RXCR_RQOS_Msk (0xFUL << ETH_DMAC0RXCR_RQOS_Pos) /*!< 0x0F000000 */ #define ETH_DMAC0RXCR_RQOS ETH_DMAC0RXCR_RQOS_Msk /*!< Rx AXI4 QOS. */ @@ -22841,6 +22869,16 @@ typedef struct #define BSEC_HWCFGR_ECC_USE_Msk (0xFUL << BSEC_HWCFGR_ECC_USE_Pos) /*!< 0x000000F0 */ #define BSEC_HWCFGR_ECC_USE BSEC_HWCFGR_ECC_USE_Msk /*!< protection / redundancy scheme used */ +/******************** Bit definition for BSEC_JTAGIN register ********************/ +#define BSEC_JTAGIN_DATA_Pos (0U) +#define BSEC_JTAGIN_DATA_Msk (0x0000FFFFUL << BSEC_JTAGIN_DATA_Pos) /*!< JTAG Input Data */ +#define BSEC_JTAGIN_DATA BSEC_JTAGIN_DATA_Msk + +/******************** Bit definition for BSEC_JTAGOUT register ********************/ +#define BSEC_JTAGOUT_DATA_Pos (0U) +#define BSEC_JTAGOUT_DATA_Msk (0x0000FFFFUL << BSEC_JTAGOUT_DATA_Pos) /*!< JTAG Output Data */ +#define BSEC_JTAGOUT_DATA BSEC_JTAGOUT_DATA_Msk + /******************** Bit definition for BSEC_VERR register********************/ #define BSEC_VERR_MINREV_Pos (0U) #define BSEC_VERR_MINREV_Msk (0xFUL << BSEC_VERR_MINREV_Pos) /*!< 0x0000000F */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151dxx_cm4.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151dxx_cm4.h index 144c8571d1..62d1c57923 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151dxx_cm4.h +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151dxx_cm4.h @@ -10679,16 +10679,19 @@ typedef struct #define ETH_MACCR_PRELEN_Pos (2U) #define ETH_MACCR_PRELEN_Msk (0x3UL << ETH_MACCR_PRELEN_Pos) /*!< 0x0000000C */ #define ETH_MACCR_PRELEN ETH_MACCR_PRELEN_Msk /*!< Preamble Length for Transmit packets */ -#define ETH_MACCR_PRELEN_0 (0x1UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000004 */ -#define ETH_MACCR_PRELEN_1 (0x2UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000008 */ +#define ETH_MACCR_PRELEN_7 (0x0UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000000 */ +#define ETH_MACCR_PRELEN_5 (0x1UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000004 */ +#define ETH_MACCR_PRELEN_3 (0x2UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000006 */ #define ETH_MACCR_DC_Pos (4U) #define ETH_MACCR_DC_Msk (0x1UL << ETH_MACCR_DC_Pos) /*!< 0x00000010 */ #define ETH_MACCR_DC ETH_MACCR_DC_Msk /*!< Deferral Check */ #define ETH_MACCR_BL_Pos (5U) #define ETH_MACCR_BL_Msk (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */ #define ETH_MACCR_BL ETH_MACCR_BL_Msk /*!< Back-Off Limit */ -#define ETH_MACCR_BL_0 (0x1UL << ETH_MACCR_BL_Pos) /*!< 0x00000020 */ -#define ETH_MACCR_BL_1 (0x2UL << ETH_MACCR_BL_Pos) /*!< 0x00000040 */ +#define ETH_MACCR_BL_10 (0x0UL << ETH_MACCR_BL_Pos) /*!< 0x00000000 */ +#define ETH_MACCR_BL_8 (0x1UL << ETH_MACCR_BL_Pos) /*!< 0x00000020 */ +#define ETH_MACCR_BL_4 (0x2UL << ETH_MACCR_BL_Pos) /*!< 0x00000040 */ +#define ETH_MACCR_BL_1 (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */ #define ETH_MACCR_DR_Pos (8U) #define ETH_MACCR_DR_Msk (0x1UL << ETH_MACCR_DR_Pos) /*!< 0x00000100 */ #define ETH_MACCR_DR ETH_MACCR_DR_Msk /*!< Disable Retry */ @@ -10740,9 +10743,14 @@ typedef struct #define ETH_MACCR_IPG_Pos (24U) #define ETH_MACCR_IPG_Msk (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */ #define ETH_MACCR_IPG ETH_MACCR_IPG_Msk /*!< Inter-Packet Gap */ -#define ETH_MACCR_IPG_0 (0x1UL << ETH_MACCR_IPG_Pos) /*!< 0x01000000 */ -#define ETH_MACCR_IPG_1 (0x2UL << ETH_MACCR_IPG_Pos) /*!< 0x02000000 */ -#define ETH_MACCR_IPG_2 (0x4UL << ETH_MACCR_IPG_Pos) /*!< 0x04000000 */ +#define ETH_MACCR_IPG_96BIT (0x0UL << ETH_MACCR_IPG_Pos) /*!< 0x00000000 */ +#define ETH_MACCR_IPG_88BIT (0x1UL << ETH_MACCR_IPG_Pos) /*!< 0x01000000 */ +#define ETH_MACCR_IPG_80BIT (0x2UL << ETH_MACCR_IPG_Pos) /*!< 0x02000000 */ +#define ETH_MACCR_IPG_72BIT (0x3UL << ETH_MACCR_IPG_Pos) /*!< 0x03000000 */ +#define ETH_MACCR_IPG_64BIT (0x4UL << ETH_MACCR_IPG_Pos) /*!< 0x04000000 */ +#define ETH_MACCR_IPG_56BIT (0x5UL << ETH_MACCR_IPG_Pos) /*!< 0x05000000 */ +#define ETH_MACCR_IPG_48BIT (0x6UL << ETH_MACCR_IPG_Pos) /*!< 0x06000000 */ +#define ETH_MACCR_IPG_40BIT (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */ #define ETH_MACCR_IPC_Pos (27U) #define ETH_MACCR_IPC_Msk (0x1UL << ETH_MACCR_IPC_Pos) /*!< 0x08000000 */ #define ETH_MACCR_IPC ETH_MACCR_IPC_Msk /*!< Checksum Offload */ @@ -10845,10 +10853,21 @@ typedef struct #define ETH_MACWTR_WTO_Pos (0U) #define ETH_MACWTR_WTO_Msk (0xFUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000F */ #define ETH_MACWTR_WTO ETH_MACWTR_WTO_Msk /*!< Watchdog Timeout */ -#define ETH_MACWTR_WTO_0 (0x1UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000001 */ -#define ETH_MACWTR_WTO_1 (0x2UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000002 */ -#define ETH_MACWTR_WTO_2 (0x4UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000004 */ -#define ETH_MACWTR_WTO_3 (0x8UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000008 */ +#define ETH_MACWTR_WTO_2KB (0x0UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000001 */ +#define ETH_MACWTR_WTO_3KB (0x1UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000001 */ +#define ETH_MACWTR_WTO_4KB (0x2UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000002 */ +#define ETH_MACWTR_WTO_5KB (0x3UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000003 */ +#define ETH_MACWTR_WTO_6KB (0x4UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000004 */ +#define ETH_MACWTR_WTO_7KB (0x5UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000005 */ +#define ETH_MACWTR_WTO_8KB (0x6UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000006 */ +#define ETH_MACWTR_WTO_9KB (0x7UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000007 */ +#define ETH_MACWTR_WTO_10KB (0x8UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000008 */ +#define ETH_MACWTR_WTO_11KB (0x9UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000009 */ +#define ETH_MACWTR_WTO_12KB (0xAUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000A */ +#define ETH_MACWTR_WTO_13KB (0xBUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000B */ +#define ETH_MACWTR_WTO_14KB (0xCUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000C */ +#define ETH_MACWTR_WTO_15KB (0xDUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000D */ +#define ETH_MACWTR_WTO_16KB (0xEUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000E */ #define ETH_MACWTR_PWE_Pos (8U) #define ETH_MACWTR_PWE_Msk (0x1UL << ETH_MACWTR_PWE_Pos) /*!< 0x00000100 */ #define ETH_MACWTR_PWE ETH_MACWTR_PWE_Msk /*!< Programmable Watchdog Enable */ @@ -10928,6 +10947,9 @@ typedef struct #define ETH_MACHT1R_HT63T32_31 (0x80000000UL << ETH_MACHT1R_HT63T32_Pos) /*!< 0x80000000 */ /************** Bit definition for ETH_MACVTR register ***************/ +#define ETH_MACVTR_VL_VID_Pos (0U) +#define ETH_MACVTR_VL_VID_Msk (0xFFFUL << ETH_MACVTR_VL_VID_Pos) /*!< 0x00000FFF */ +#define ETH_MACVTR_VL_VID ETH_MACVTR_VL_VID_Msk /*!< VLAN Tag Identifier field of VLAN tag */ #define ETH_MACVTR_VL_Pos (0U) #define ETH_MACVTR_VL_Msk (0xFFFFUL << ETH_MACVTR_VL_Pos) /*!< 0x0000FFFF */ #define ETH_MACVTR_VL ETH_MACVTR_VL_Msk /*!< VLAN Tag Identifier for Receive Packets */ @@ -11089,9 +11111,12 @@ typedef struct #define ETH_MACQ0TXFCR_PLT_Pos (4U) #define ETH_MACQ0TXFCR_PLT_Msk (0x7UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000070 */ #define ETH_MACQ0TXFCR_PLT ETH_MACQ0TXFCR_PLT_Msk /*!< Pause Low Threshold */ -#define ETH_MACQ0TXFCR_PLT_0 (0x1UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000010 */ -#define ETH_MACQ0TXFCR_PLT_1 (0x2UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000020 */ -#define ETH_MACQ0TXFCR_PLT_2 (0x4UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000040 */ +#define ETH_MACQ0TXFCR_PLT_MINUS4 (0x0UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000000 */ +#define ETH_MACQ0TXFCR_PLT_MINUS28 (0x1UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000010 */ +#define ETH_MACQ0TXFCR_PLT_MINUS36 (0x2UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000020 */ +#define ETH_MACQ0TXFCR_PLT_MINUS144 (0x3UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000030 */ +#define ETH_MACQ0TXFCR_PLT_MINUS256 (0x4UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000040 */ +#define ETH_MACQ0TXFCR_PLT_MINUS512 (0x5UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000050 */ #define ETH_MACQ0TXFCR_DZPQ_Pos (7U) #define ETH_MACQ0TXFCR_DZPQ_Msk (0x1UL << ETH_MACQ0TXFCR_DZPQ_Pos) /*!< 0x00000080 */ #define ETH_MACQ0TXFCR_DZPQ ETH_MACQ0TXFCR_DZPQ_Msk /*!< Disable Zero-Quanta Pause */ @@ -11658,10 +11683,12 @@ typedef struct #define ETH_MACMDIOAR_CR_Pos (8U) #define ETH_MACMDIOAR_CR_Msk (0xFUL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000F00 */ #define ETH_MACMDIOAR_CR ETH_MACMDIOAR_CR_Msk /*!< CSR Clock Range */ -#define ETH_MACMDIOAR_CR_0 (0x1UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000100 */ -#define ETH_MACMDIOAR_CR_1 (0x2UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000200 */ -#define ETH_MACMDIOAR_CR_2 (0x4UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000400 */ -#define ETH_MACMDIOAR_CR_3 (0x8UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000800 */ +#define ETH_MACMDIOAR_CR_DIV42 (0x0UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000000 */ +#define ETH_MACMDIOAR_CR_DIV62 (0x1UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000100 */ +#define ETH_MACMDIOAR_CR_DIV16 (0x2UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000200 */ +#define ETH_MACMDIOAR_CR_DIV26 (0x3UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000300 */ +#define ETH_MACMDIOAR_CR_DIV102 (0x4UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000400 */ +#define ETH_MACMDIOAR_CR_DIV124 (0x5UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000500 */ #define ETH_MACMDIOAR_NTC_Pos (12U) #define ETH_MACMDIOAR_NTC_Msk (0x7UL << ETH_MACMDIOAR_NTC_Pos) /*!< 0x00007000 */ #define ETH_MACMDIOAR_NTC ETH_MACMDIOAR_NTC_Msk /*!< Number of Training Clocks */ @@ -12100,7 +12127,7 @@ typedef struct #define ETH_MMCTXIMR_TXLPIUSCIM ETH_MMCTXIMR_TXLPIUSCIM_Msk /*!< MMC Transmit LPI microsecond counter interrupt Mask */ #define ETH_MMCTXIMR_TXLPITRCIM_Pos (27U) #define ETH_MMCTXIMR_TXLPITRCIM_Msk (0x1UL << ETH_MMCTXIMR_TXLPITRCIM_Pos) /*!< 0x08000000 */ -#define ETH_MMCTXIMR_TXLPITRCIM ETH_MMC_INTERRUPT_MASK_TXLPITRCIM_Msk /*!< MMC Transmit LPI transition counter interrupt Mask */ +#define ETH_MMCTXIMR_TXLPITRCIM ETH_MMCTXIMR_TXLPITRCIM_Msk /*!< MMC Transmit LPI transition counter interrupt Mask */ /*********** Bit definition for ETH_MMC_TX_SINGLE_COLLISION_GOOD_PACKETS register ************/ #define ETH_MMCTXSCGPR_TXSNGLCOLG_Pos (0U) @@ -14803,9 +14830,10 @@ typedef struct #define ETH_DMAC0CR_DSL_Pos (18U) #define ETH_DMAC0CR_DSL_Msk (0x7UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x001C0000 */ #define ETH_DMAC0CR_DSL ETH_DMAC0CR_DSL_Msk /*!< Descriptor Skip Length */ -#define ETH_DMAC0CR_DSL_0 (0x1UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00040000 */ -#define ETH_DMAC0CR_DSL_1 (0x2UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00080000 */ -#define ETH_DMAC0CR_DSL_2 (0x4UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00100000 */ +#define ETH_DMACCR_DSL_0BIT (0x0UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00000000 */ +#define ETH_DMACCR_DSL_32BIT (0x1UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00040000 */ +#define ETH_DMACCR_DSL_64BIT (0x2UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00080000 */ +#define ETH_DMACCR_DSL_128BIT (0x4UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00100000 */ /************* Bit definition for ETH_DMAC0TXCR register *************/ #define ETH_DMAC0TXCR_ST_Pos (0U) @@ -14826,12 +14854,12 @@ typedef struct #define ETH_DMAC0TXCR_TXPBL_Pos (16U) #define ETH_DMAC0TXCR_TXPBL_Msk (0x3FUL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x003F0000 */ #define ETH_DMAC0TXCR_TXPBL ETH_DMAC0TXCR_TXPBL_Msk /*!< Transmit Programmable Burst Length */ -#define ETH_DMAC0TXCR_TXPBL_0 (0x1UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00010000 */ -#define ETH_DMAC0TXCR_TXPBL_1 (0x2UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00020000 */ -#define ETH_DMAC0TXCR_TXPBL_2 (0x4UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00040000 */ -#define ETH_DMAC0TXCR_TXPBL_3 (0x8UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00080000 */ -#define ETH_DMAC0TXCR_TXPBL_4 (0x10UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00100000 */ -#define ETH_DMAC0TXCR_TXPBL_5 (0x20UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00200000 */ +#define ETH_DMAC0TXCR_TXPBL_1PBL (0x1UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00010000 */ +#define ETH_DMAC0TXCR_TXPBL_2PBL (0x2UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00020000 */ +#define ETH_DMAC0TXCR_TXPBL_4PBL (0x4UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00040000 */ +#define ETH_DMAC0TXCR_TXPBL_8PBL (0x8UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00080000 */ +#define ETH_DMAC0TXCR_TXPBL_16PBL (0x10UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00100000 */ +#define ETH_DMAC0TXCR_TXPBL_32PBL (0x20UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00200000 */ #define ETH_DMAC0TXCR_TQOS_Pos (24U) #define ETH_DMAC0TXCR_TQOS_Msk (0xFUL << ETH_DMAC0TXCR_TQOS_Pos) /*!< 0x0F000000 */ #define ETH_DMAC0TXCR_TQOS ETH_DMAC0TXCR_TQOS_Msk /*!< Transmit QOS. */ @@ -14864,12 +14892,12 @@ typedef struct #define ETH_DMAC0RXCR_RXPBL_Pos (16U) #define ETH_DMAC0RXCR_RXPBL_Msk (0x3FUL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x003F0000 */ #define ETH_DMAC0RXCR_RXPBL ETH_DMAC0RXCR_RXPBL_Msk /*!< Receive Programmable Burst Length */ -#define ETH_DMAC0RXCR_RXPBL_0 (0x1UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00010000 */ -#define ETH_DMAC0RXCR_RXPBL_1 (0x2UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00020000 */ -#define ETH_DMAC0RXCR_RXPBL_2 (0x4UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00040000 */ -#define ETH_DMAC0RXCR_RXPBL_3 (0x8UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00080000 */ -#define ETH_DMAC0RXCR_RXPBL_4 (0x10UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00100000 */ -#define ETH_DMAC0RXCR_RXPBL_5 (0x20UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00200000 */ +#define ETH_DMAC0RXCR_RXPBL_1PBL (0x1UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00010000 */ +#define ETH_DMAC0RXCR_RXPBL_2PBL (0x2UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00020000 */ +#define ETH_DMAC0RXCR_RXPBL_4PBL (0x4UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00040000 */ +#define ETH_DMAC0RXCR_RXPBL_8PBL (0x8UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00080000 */ +#define ETH_DMAC0RXCR_RXPBL_16PBL (0x10UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00100000 */ +#define ETH_DMAC0RXCR_RXPBL_32PBL (0x20UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00200000 */ #define ETH_DMAC0RXCR_RQOS_Pos (24U) #define ETH_DMAC0RXCR_RQOS_Msk (0xFUL << ETH_DMAC0RXCR_RQOS_Pos) /*!< 0x0F000000 */ #define ETH_DMAC0RXCR_RQOS ETH_DMAC0RXCR_RQOS_Msk /*!< Rx AXI4 QOS. */ @@ -22807,6 +22835,16 @@ typedef struct #define BSEC_HWCFGR_ECC_USE_Msk (0xFUL << BSEC_HWCFGR_ECC_USE_Pos) /*!< 0x000000F0 */ #define BSEC_HWCFGR_ECC_USE BSEC_HWCFGR_ECC_USE_Msk /*!< protection / redundancy scheme used */ +/******************** Bit definition for BSEC_JTAGIN register ********************/ +#define BSEC_JTAGIN_DATA_Pos (0U) +#define BSEC_JTAGIN_DATA_Msk (0x0000FFFFUL << BSEC_JTAGIN_DATA_Pos) /*!< JTAG Input Data */ +#define BSEC_JTAGIN_DATA BSEC_JTAGIN_DATA_Msk + +/******************** Bit definition for BSEC_JTAGOUT register ********************/ +#define BSEC_JTAGOUT_DATA_Pos (0U) +#define BSEC_JTAGOUT_DATA_Msk (0x0000FFFFUL << BSEC_JTAGOUT_DATA_Pos) /*!< JTAG Output Data */ +#define BSEC_JTAGOUT_DATA BSEC_JTAGOUT_DATA_Msk + /******************** Bit definition for BSEC_VERR register********************/ #define BSEC_VERR_MINREV_Pos (0U) #define BSEC_VERR_MINREV_Msk (0xFUL << BSEC_VERR_MINREV_Pos) /*!< 0x0000000F */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151fxx_ca7.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151fxx_ca7.h index de488f42ff..8fef3b75dc 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151fxx_ca7.h +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151fxx_ca7.h @@ -10910,16 +10910,19 @@ typedef struct #define ETH_MACCR_PRELEN_Pos (2U) #define ETH_MACCR_PRELEN_Msk (0x3UL << ETH_MACCR_PRELEN_Pos) /*!< 0x0000000C */ #define ETH_MACCR_PRELEN ETH_MACCR_PRELEN_Msk /*!< Preamble Length for Transmit packets */ -#define ETH_MACCR_PRELEN_0 (0x1UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000004 */ -#define ETH_MACCR_PRELEN_1 (0x2UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000008 */ +#define ETH_MACCR_PRELEN_7 (0x0UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000000 */ +#define ETH_MACCR_PRELEN_5 (0x1UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000004 */ +#define ETH_MACCR_PRELEN_3 (0x2UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000006 */ #define ETH_MACCR_DC_Pos (4U) #define ETH_MACCR_DC_Msk (0x1UL << ETH_MACCR_DC_Pos) /*!< 0x00000010 */ #define ETH_MACCR_DC ETH_MACCR_DC_Msk /*!< Deferral Check */ #define ETH_MACCR_BL_Pos (5U) #define ETH_MACCR_BL_Msk (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */ #define ETH_MACCR_BL ETH_MACCR_BL_Msk /*!< Back-Off Limit */ -#define ETH_MACCR_BL_0 (0x1UL << ETH_MACCR_BL_Pos) /*!< 0x00000020 */ -#define ETH_MACCR_BL_1 (0x2UL << ETH_MACCR_BL_Pos) /*!< 0x00000040 */ +#define ETH_MACCR_BL_10 (0x0UL << ETH_MACCR_BL_Pos) /*!< 0x00000000 */ +#define ETH_MACCR_BL_8 (0x1UL << ETH_MACCR_BL_Pos) /*!< 0x00000020 */ +#define ETH_MACCR_BL_4 (0x2UL << ETH_MACCR_BL_Pos) /*!< 0x00000040 */ +#define ETH_MACCR_BL_1 (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */ #define ETH_MACCR_DR_Pos (8U) #define ETH_MACCR_DR_Msk (0x1UL << ETH_MACCR_DR_Pos) /*!< 0x00000100 */ #define ETH_MACCR_DR ETH_MACCR_DR_Msk /*!< Disable Retry */ @@ -10971,9 +10974,14 @@ typedef struct #define ETH_MACCR_IPG_Pos (24U) #define ETH_MACCR_IPG_Msk (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */ #define ETH_MACCR_IPG ETH_MACCR_IPG_Msk /*!< Inter-Packet Gap */ -#define ETH_MACCR_IPG_0 (0x1UL << ETH_MACCR_IPG_Pos) /*!< 0x01000000 */ -#define ETH_MACCR_IPG_1 (0x2UL << ETH_MACCR_IPG_Pos) /*!< 0x02000000 */ -#define ETH_MACCR_IPG_2 (0x4UL << ETH_MACCR_IPG_Pos) /*!< 0x04000000 */ +#define ETH_MACCR_IPG_96BIT (0x0UL << ETH_MACCR_IPG_Pos) /*!< 0x00000000 */ +#define ETH_MACCR_IPG_88BIT (0x1UL << ETH_MACCR_IPG_Pos) /*!< 0x01000000 */ +#define ETH_MACCR_IPG_80BIT (0x2UL << ETH_MACCR_IPG_Pos) /*!< 0x02000000 */ +#define ETH_MACCR_IPG_72BIT (0x3UL << ETH_MACCR_IPG_Pos) /*!< 0x03000000 */ +#define ETH_MACCR_IPG_64BIT (0x4UL << ETH_MACCR_IPG_Pos) /*!< 0x04000000 */ +#define ETH_MACCR_IPG_56BIT (0x5UL << ETH_MACCR_IPG_Pos) /*!< 0x05000000 */ +#define ETH_MACCR_IPG_48BIT (0x6UL << ETH_MACCR_IPG_Pos) /*!< 0x06000000 */ +#define ETH_MACCR_IPG_40BIT (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */ #define ETH_MACCR_IPC_Pos (27U) #define ETH_MACCR_IPC_Msk (0x1UL << ETH_MACCR_IPC_Pos) /*!< 0x08000000 */ #define ETH_MACCR_IPC ETH_MACCR_IPC_Msk /*!< Checksum Offload */ @@ -11076,10 +11084,21 @@ typedef struct #define ETH_MACWTR_WTO_Pos (0U) #define ETH_MACWTR_WTO_Msk (0xFUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000F */ #define ETH_MACWTR_WTO ETH_MACWTR_WTO_Msk /*!< Watchdog Timeout */ -#define ETH_MACWTR_WTO_0 (0x1UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000001 */ -#define ETH_MACWTR_WTO_1 (0x2UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000002 */ -#define ETH_MACWTR_WTO_2 (0x4UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000004 */ -#define ETH_MACWTR_WTO_3 (0x8UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000008 */ +#define ETH_MACWTR_WTO_2KB (0x0UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000001 */ +#define ETH_MACWTR_WTO_3KB (0x1UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000001 */ +#define ETH_MACWTR_WTO_4KB (0x2UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000002 */ +#define ETH_MACWTR_WTO_5KB (0x3UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000003 */ +#define ETH_MACWTR_WTO_6KB (0x4UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000004 */ +#define ETH_MACWTR_WTO_7KB (0x5UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000005 */ +#define ETH_MACWTR_WTO_8KB (0x6UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000006 */ +#define ETH_MACWTR_WTO_9KB (0x7UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000007 */ +#define ETH_MACWTR_WTO_10KB (0x8UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000008 */ +#define ETH_MACWTR_WTO_11KB (0x9UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000009 */ +#define ETH_MACWTR_WTO_12KB (0xAUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000A */ +#define ETH_MACWTR_WTO_13KB (0xBUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000B */ +#define ETH_MACWTR_WTO_14KB (0xCUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000C */ +#define ETH_MACWTR_WTO_15KB (0xDUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000D */ +#define ETH_MACWTR_WTO_16KB (0xEUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000E */ #define ETH_MACWTR_PWE_Pos (8U) #define ETH_MACWTR_PWE_Msk (0x1UL << ETH_MACWTR_PWE_Pos) /*!< 0x00000100 */ #define ETH_MACWTR_PWE ETH_MACWTR_PWE_Msk /*!< Programmable Watchdog Enable */ @@ -11159,6 +11178,9 @@ typedef struct #define ETH_MACHT1R_HT63T32_31 (0x80000000UL << ETH_MACHT1R_HT63T32_Pos) /*!< 0x80000000 */ /************** Bit definition for ETH_MACVTR register ***************/ +#define ETH_MACVTR_VL_VID_Pos (0U) +#define ETH_MACVTR_VL_VID_Msk (0xFFFUL << ETH_MACVTR_VL_VID_Pos) /*!< 0x00000FFF */ +#define ETH_MACVTR_VL_VID ETH_MACVTR_VL_VID_Msk /*!< VLAN Tag Identifier field of VLAN tag */ #define ETH_MACVTR_VL_Pos (0U) #define ETH_MACVTR_VL_Msk (0xFFFFUL << ETH_MACVTR_VL_Pos) /*!< 0x0000FFFF */ #define ETH_MACVTR_VL ETH_MACVTR_VL_Msk /*!< VLAN Tag Identifier for Receive Packets */ @@ -11320,9 +11342,12 @@ typedef struct #define ETH_MACQ0TXFCR_PLT_Pos (4U) #define ETH_MACQ0TXFCR_PLT_Msk (0x7UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000070 */ #define ETH_MACQ0TXFCR_PLT ETH_MACQ0TXFCR_PLT_Msk /*!< Pause Low Threshold */ -#define ETH_MACQ0TXFCR_PLT_0 (0x1UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000010 */ -#define ETH_MACQ0TXFCR_PLT_1 (0x2UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000020 */ -#define ETH_MACQ0TXFCR_PLT_2 (0x4UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000040 */ +#define ETH_MACQ0TXFCR_PLT_MINUS4 (0x0UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000000 */ +#define ETH_MACQ0TXFCR_PLT_MINUS28 (0x1UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000010 */ +#define ETH_MACQ0TXFCR_PLT_MINUS36 (0x2UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000020 */ +#define ETH_MACQ0TXFCR_PLT_MINUS144 (0x3UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000030 */ +#define ETH_MACQ0TXFCR_PLT_MINUS256 (0x4UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000040 */ +#define ETH_MACQ0TXFCR_PLT_MINUS512 (0x5UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000050 */ #define ETH_MACQ0TXFCR_DZPQ_Pos (7U) #define ETH_MACQ0TXFCR_DZPQ_Msk (0x1UL << ETH_MACQ0TXFCR_DZPQ_Pos) /*!< 0x00000080 */ #define ETH_MACQ0TXFCR_DZPQ ETH_MACQ0TXFCR_DZPQ_Msk /*!< Disable Zero-Quanta Pause */ @@ -11889,10 +11914,12 @@ typedef struct #define ETH_MACMDIOAR_CR_Pos (8U) #define ETH_MACMDIOAR_CR_Msk (0xFUL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000F00 */ #define ETH_MACMDIOAR_CR ETH_MACMDIOAR_CR_Msk /*!< CSR Clock Range */ -#define ETH_MACMDIOAR_CR_0 (0x1UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000100 */ -#define ETH_MACMDIOAR_CR_1 (0x2UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000200 */ -#define ETH_MACMDIOAR_CR_2 (0x4UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000400 */ -#define ETH_MACMDIOAR_CR_3 (0x8UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000800 */ +#define ETH_MACMDIOAR_CR_DIV42 (0x0UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000000 */ +#define ETH_MACMDIOAR_CR_DIV62 (0x1UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000100 */ +#define ETH_MACMDIOAR_CR_DIV16 (0x2UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000200 */ +#define ETH_MACMDIOAR_CR_DIV26 (0x3UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000300 */ +#define ETH_MACMDIOAR_CR_DIV102 (0x4UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000400 */ +#define ETH_MACMDIOAR_CR_DIV124 (0x5UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000500 */ #define ETH_MACMDIOAR_NTC_Pos (12U) #define ETH_MACMDIOAR_NTC_Msk (0x7UL << ETH_MACMDIOAR_NTC_Pos) /*!< 0x00007000 */ #define ETH_MACMDIOAR_NTC ETH_MACMDIOAR_NTC_Msk /*!< Number of Training Clocks */ @@ -12331,7 +12358,7 @@ typedef struct #define ETH_MMCTXIMR_TXLPIUSCIM ETH_MMCTXIMR_TXLPIUSCIM_Msk /*!< MMC Transmit LPI microsecond counter interrupt Mask */ #define ETH_MMCTXIMR_TXLPITRCIM_Pos (27U) #define ETH_MMCTXIMR_TXLPITRCIM_Msk (0x1UL << ETH_MMCTXIMR_TXLPITRCIM_Pos) /*!< 0x08000000 */ -#define ETH_MMCTXIMR_TXLPITRCIM ETH_MMC_INTERRUPT_MASK_TXLPITRCIM_Msk /*!< MMC Transmit LPI transition counter interrupt Mask */ +#define ETH_MMCTXIMR_TXLPITRCIM ETH_MMCTXIMR_TXLPITRCIM_Msk /*!< MMC Transmit LPI transition counter interrupt Mask */ /*********** Bit definition for ETH_MMC_TX_SINGLE_COLLISION_GOOD_PACKETS register ************/ #define ETH_MMCTXSCGPR_TXSNGLCOLG_Pos (0U) @@ -15034,9 +15061,10 @@ typedef struct #define ETH_DMAC0CR_DSL_Pos (18U) #define ETH_DMAC0CR_DSL_Msk (0x7UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x001C0000 */ #define ETH_DMAC0CR_DSL ETH_DMAC0CR_DSL_Msk /*!< Descriptor Skip Length */ -#define ETH_DMAC0CR_DSL_0 (0x1UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00040000 */ -#define ETH_DMAC0CR_DSL_1 (0x2UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00080000 */ -#define ETH_DMAC0CR_DSL_2 (0x4UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00100000 */ +#define ETH_DMACCR_DSL_0BIT (0x0UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00000000 */ +#define ETH_DMACCR_DSL_32BIT (0x1UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00040000 */ +#define ETH_DMACCR_DSL_64BIT (0x2UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00080000 */ +#define ETH_DMACCR_DSL_128BIT (0x4UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00100000 */ /************* Bit definition for ETH_DMAC0TXCR register *************/ #define ETH_DMAC0TXCR_ST_Pos (0U) @@ -15057,12 +15085,12 @@ typedef struct #define ETH_DMAC0TXCR_TXPBL_Pos (16U) #define ETH_DMAC0TXCR_TXPBL_Msk (0x3FUL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x003F0000 */ #define ETH_DMAC0TXCR_TXPBL ETH_DMAC0TXCR_TXPBL_Msk /*!< Transmit Programmable Burst Length */ -#define ETH_DMAC0TXCR_TXPBL_0 (0x1UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00010000 */ -#define ETH_DMAC0TXCR_TXPBL_1 (0x2UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00020000 */ -#define ETH_DMAC0TXCR_TXPBL_2 (0x4UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00040000 */ -#define ETH_DMAC0TXCR_TXPBL_3 (0x8UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00080000 */ -#define ETH_DMAC0TXCR_TXPBL_4 (0x10UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00100000 */ -#define ETH_DMAC0TXCR_TXPBL_5 (0x20UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00200000 */ +#define ETH_DMAC0TXCR_TXPBL_1PBL (0x1UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00010000 */ +#define ETH_DMAC0TXCR_TXPBL_2PBL (0x2UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00020000 */ +#define ETH_DMAC0TXCR_TXPBL_4PBL (0x4UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00040000 */ +#define ETH_DMAC0TXCR_TXPBL_8PBL (0x8UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00080000 */ +#define ETH_DMAC0TXCR_TXPBL_16PBL (0x10UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00100000 */ +#define ETH_DMAC0TXCR_TXPBL_32PBL (0x20UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00200000 */ #define ETH_DMAC0TXCR_TQOS_Pos (24U) #define ETH_DMAC0TXCR_TQOS_Msk (0xFUL << ETH_DMAC0TXCR_TQOS_Pos) /*!< 0x0F000000 */ #define ETH_DMAC0TXCR_TQOS ETH_DMAC0TXCR_TQOS_Msk /*!< Transmit QOS. */ @@ -15095,12 +15123,12 @@ typedef struct #define ETH_DMAC0RXCR_RXPBL_Pos (16U) #define ETH_DMAC0RXCR_RXPBL_Msk (0x3FUL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x003F0000 */ #define ETH_DMAC0RXCR_RXPBL ETH_DMAC0RXCR_RXPBL_Msk /*!< Receive Programmable Burst Length */ -#define ETH_DMAC0RXCR_RXPBL_0 (0x1UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00010000 */ -#define ETH_DMAC0RXCR_RXPBL_1 (0x2UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00020000 */ -#define ETH_DMAC0RXCR_RXPBL_2 (0x4UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00040000 */ -#define ETH_DMAC0RXCR_RXPBL_3 (0x8UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00080000 */ -#define ETH_DMAC0RXCR_RXPBL_4 (0x10UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00100000 */ -#define ETH_DMAC0RXCR_RXPBL_5 (0x20UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00200000 */ +#define ETH_DMAC0RXCR_RXPBL_1PBL (0x1UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00010000 */ +#define ETH_DMAC0RXCR_RXPBL_2PBL (0x2UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00020000 */ +#define ETH_DMAC0RXCR_RXPBL_4PBL (0x4UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00040000 */ +#define ETH_DMAC0RXCR_RXPBL_8PBL (0x8UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00080000 */ +#define ETH_DMAC0RXCR_RXPBL_16PBL (0x10UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00100000 */ +#define ETH_DMAC0RXCR_RXPBL_32PBL (0x20UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00200000 */ #define ETH_DMAC0RXCR_RQOS_Pos (24U) #define ETH_DMAC0RXCR_RQOS_Msk (0xFUL << ETH_DMAC0RXCR_RQOS_Pos) /*!< 0x0F000000 */ #define ETH_DMAC0RXCR_RQOS ETH_DMAC0RXCR_RQOS_Msk /*!< Rx AXI4 QOS. */ @@ -23038,6 +23066,16 @@ typedef struct #define BSEC_HWCFGR_ECC_USE_Msk (0xFUL << BSEC_HWCFGR_ECC_USE_Pos) /*!< 0x000000F0 */ #define BSEC_HWCFGR_ECC_USE BSEC_HWCFGR_ECC_USE_Msk /*!< protection / redundancy scheme used */ +/******************** Bit definition for BSEC_JTAGIN register ********************/ +#define BSEC_JTAGIN_DATA_Pos (0U) +#define BSEC_JTAGIN_DATA_Msk (0x0000FFFFUL << BSEC_JTAGIN_DATA_Pos) /*!< JTAG Input Data */ +#define BSEC_JTAGIN_DATA BSEC_JTAGIN_DATA_Msk + +/******************** Bit definition for BSEC_JTAGOUT register ********************/ +#define BSEC_JTAGOUT_DATA_Pos (0U) +#define BSEC_JTAGOUT_DATA_Msk (0x0000FFFFUL << BSEC_JTAGOUT_DATA_Pos) /*!< JTAG Output Data */ +#define BSEC_JTAGOUT_DATA BSEC_JTAGOUT_DATA_Msk + /******************** Bit definition for BSEC_VERR register********************/ #define BSEC_VERR_MINREV_Pos (0U) #define BSEC_VERR_MINREV_Msk (0xFUL << BSEC_VERR_MINREV_Pos) /*!< 0x0000000F */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151fxx_cm4.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151fxx_cm4.h index c82e99f399..2f0cd48019 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151fxx_cm4.h +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151fxx_cm4.h @@ -10876,16 +10876,19 @@ typedef struct #define ETH_MACCR_PRELEN_Pos (2U) #define ETH_MACCR_PRELEN_Msk (0x3UL << ETH_MACCR_PRELEN_Pos) /*!< 0x0000000C */ #define ETH_MACCR_PRELEN ETH_MACCR_PRELEN_Msk /*!< Preamble Length for Transmit packets */ -#define ETH_MACCR_PRELEN_0 (0x1UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000004 */ -#define ETH_MACCR_PRELEN_1 (0x2UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000008 */ +#define ETH_MACCR_PRELEN_7 (0x0UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000000 */ +#define ETH_MACCR_PRELEN_5 (0x1UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000004 */ +#define ETH_MACCR_PRELEN_3 (0x2UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000006 */ #define ETH_MACCR_DC_Pos (4U) #define ETH_MACCR_DC_Msk (0x1UL << ETH_MACCR_DC_Pos) /*!< 0x00000010 */ #define ETH_MACCR_DC ETH_MACCR_DC_Msk /*!< Deferral Check */ #define ETH_MACCR_BL_Pos (5U) #define ETH_MACCR_BL_Msk (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */ #define ETH_MACCR_BL ETH_MACCR_BL_Msk /*!< Back-Off Limit */ -#define ETH_MACCR_BL_0 (0x1UL << ETH_MACCR_BL_Pos) /*!< 0x00000020 */ -#define ETH_MACCR_BL_1 (0x2UL << ETH_MACCR_BL_Pos) /*!< 0x00000040 */ +#define ETH_MACCR_BL_10 (0x0UL << ETH_MACCR_BL_Pos) /*!< 0x00000000 */ +#define ETH_MACCR_BL_8 (0x1UL << ETH_MACCR_BL_Pos) /*!< 0x00000020 */ +#define ETH_MACCR_BL_4 (0x2UL << ETH_MACCR_BL_Pos) /*!< 0x00000040 */ +#define ETH_MACCR_BL_1 (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */ #define ETH_MACCR_DR_Pos (8U) #define ETH_MACCR_DR_Msk (0x1UL << ETH_MACCR_DR_Pos) /*!< 0x00000100 */ #define ETH_MACCR_DR ETH_MACCR_DR_Msk /*!< Disable Retry */ @@ -10937,9 +10940,14 @@ typedef struct #define ETH_MACCR_IPG_Pos (24U) #define ETH_MACCR_IPG_Msk (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */ #define ETH_MACCR_IPG ETH_MACCR_IPG_Msk /*!< Inter-Packet Gap */ -#define ETH_MACCR_IPG_0 (0x1UL << ETH_MACCR_IPG_Pos) /*!< 0x01000000 */ -#define ETH_MACCR_IPG_1 (0x2UL << ETH_MACCR_IPG_Pos) /*!< 0x02000000 */ -#define ETH_MACCR_IPG_2 (0x4UL << ETH_MACCR_IPG_Pos) /*!< 0x04000000 */ +#define ETH_MACCR_IPG_96BIT (0x0UL << ETH_MACCR_IPG_Pos) /*!< 0x00000000 */ +#define ETH_MACCR_IPG_88BIT (0x1UL << ETH_MACCR_IPG_Pos) /*!< 0x01000000 */ +#define ETH_MACCR_IPG_80BIT (0x2UL << ETH_MACCR_IPG_Pos) /*!< 0x02000000 */ +#define ETH_MACCR_IPG_72BIT (0x3UL << ETH_MACCR_IPG_Pos) /*!< 0x03000000 */ +#define ETH_MACCR_IPG_64BIT (0x4UL << ETH_MACCR_IPG_Pos) /*!< 0x04000000 */ +#define ETH_MACCR_IPG_56BIT (0x5UL << ETH_MACCR_IPG_Pos) /*!< 0x05000000 */ +#define ETH_MACCR_IPG_48BIT (0x6UL << ETH_MACCR_IPG_Pos) /*!< 0x06000000 */ +#define ETH_MACCR_IPG_40BIT (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */ #define ETH_MACCR_IPC_Pos (27U) #define ETH_MACCR_IPC_Msk (0x1UL << ETH_MACCR_IPC_Pos) /*!< 0x08000000 */ #define ETH_MACCR_IPC ETH_MACCR_IPC_Msk /*!< Checksum Offload */ @@ -11042,10 +11050,21 @@ typedef struct #define ETH_MACWTR_WTO_Pos (0U) #define ETH_MACWTR_WTO_Msk (0xFUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000F */ #define ETH_MACWTR_WTO ETH_MACWTR_WTO_Msk /*!< Watchdog Timeout */ -#define ETH_MACWTR_WTO_0 (0x1UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000001 */ -#define ETH_MACWTR_WTO_1 (0x2UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000002 */ -#define ETH_MACWTR_WTO_2 (0x4UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000004 */ -#define ETH_MACWTR_WTO_3 (0x8UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000008 */ +#define ETH_MACWTR_WTO_2KB (0x0UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000001 */ +#define ETH_MACWTR_WTO_3KB (0x1UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000001 */ +#define ETH_MACWTR_WTO_4KB (0x2UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000002 */ +#define ETH_MACWTR_WTO_5KB (0x3UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000003 */ +#define ETH_MACWTR_WTO_6KB (0x4UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000004 */ +#define ETH_MACWTR_WTO_7KB (0x5UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000005 */ +#define ETH_MACWTR_WTO_8KB (0x6UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000006 */ +#define ETH_MACWTR_WTO_9KB (0x7UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000007 */ +#define ETH_MACWTR_WTO_10KB (0x8UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000008 */ +#define ETH_MACWTR_WTO_11KB (0x9UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000009 */ +#define ETH_MACWTR_WTO_12KB (0xAUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000A */ +#define ETH_MACWTR_WTO_13KB (0xBUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000B */ +#define ETH_MACWTR_WTO_14KB (0xCUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000C */ +#define ETH_MACWTR_WTO_15KB (0xDUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000D */ +#define ETH_MACWTR_WTO_16KB (0xEUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000E */ #define ETH_MACWTR_PWE_Pos (8U) #define ETH_MACWTR_PWE_Msk (0x1UL << ETH_MACWTR_PWE_Pos) /*!< 0x00000100 */ #define ETH_MACWTR_PWE ETH_MACWTR_PWE_Msk /*!< Programmable Watchdog Enable */ @@ -11125,6 +11144,9 @@ typedef struct #define ETH_MACHT1R_HT63T32_31 (0x80000000UL << ETH_MACHT1R_HT63T32_Pos) /*!< 0x80000000 */ /************** Bit definition for ETH_MACVTR register ***************/ +#define ETH_MACVTR_VL_VID_Pos (0U) +#define ETH_MACVTR_VL_VID_Msk (0xFFFUL << ETH_MACVTR_VL_VID_Pos) /*!< 0x00000FFF */ +#define ETH_MACVTR_VL_VID ETH_MACVTR_VL_VID_Msk /*!< VLAN Tag Identifier field of VLAN tag */ #define ETH_MACVTR_VL_Pos (0U) #define ETH_MACVTR_VL_Msk (0xFFFFUL << ETH_MACVTR_VL_Pos) /*!< 0x0000FFFF */ #define ETH_MACVTR_VL ETH_MACVTR_VL_Msk /*!< VLAN Tag Identifier for Receive Packets */ @@ -11286,9 +11308,12 @@ typedef struct #define ETH_MACQ0TXFCR_PLT_Pos (4U) #define ETH_MACQ0TXFCR_PLT_Msk (0x7UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000070 */ #define ETH_MACQ0TXFCR_PLT ETH_MACQ0TXFCR_PLT_Msk /*!< Pause Low Threshold */ -#define ETH_MACQ0TXFCR_PLT_0 (0x1UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000010 */ -#define ETH_MACQ0TXFCR_PLT_1 (0x2UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000020 */ -#define ETH_MACQ0TXFCR_PLT_2 (0x4UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000040 */ +#define ETH_MACQ0TXFCR_PLT_MINUS4 (0x0UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000000 */ +#define ETH_MACQ0TXFCR_PLT_MINUS28 (0x1UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000010 */ +#define ETH_MACQ0TXFCR_PLT_MINUS36 (0x2UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000020 */ +#define ETH_MACQ0TXFCR_PLT_MINUS144 (0x3UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000030 */ +#define ETH_MACQ0TXFCR_PLT_MINUS256 (0x4UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000040 */ +#define ETH_MACQ0TXFCR_PLT_MINUS512 (0x5UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000050 */ #define ETH_MACQ0TXFCR_DZPQ_Pos (7U) #define ETH_MACQ0TXFCR_DZPQ_Msk (0x1UL << ETH_MACQ0TXFCR_DZPQ_Pos) /*!< 0x00000080 */ #define ETH_MACQ0TXFCR_DZPQ ETH_MACQ0TXFCR_DZPQ_Msk /*!< Disable Zero-Quanta Pause */ @@ -11855,10 +11880,12 @@ typedef struct #define ETH_MACMDIOAR_CR_Pos (8U) #define ETH_MACMDIOAR_CR_Msk (0xFUL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000F00 */ #define ETH_MACMDIOAR_CR ETH_MACMDIOAR_CR_Msk /*!< CSR Clock Range */ -#define ETH_MACMDIOAR_CR_0 (0x1UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000100 */ -#define ETH_MACMDIOAR_CR_1 (0x2UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000200 */ -#define ETH_MACMDIOAR_CR_2 (0x4UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000400 */ -#define ETH_MACMDIOAR_CR_3 (0x8UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000800 */ +#define ETH_MACMDIOAR_CR_DIV42 (0x0UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000000 */ +#define ETH_MACMDIOAR_CR_DIV62 (0x1UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000100 */ +#define ETH_MACMDIOAR_CR_DIV16 (0x2UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000200 */ +#define ETH_MACMDIOAR_CR_DIV26 (0x3UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000300 */ +#define ETH_MACMDIOAR_CR_DIV102 (0x4UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000400 */ +#define ETH_MACMDIOAR_CR_DIV124 (0x5UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000500 */ #define ETH_MACMDIOAR_NTC_Pos (12U) #define ETH_MACMDIOAR_NTC_Msk (0x7UL << ETH_MACMDIOAR_NTC_Pos) /*!< 0x00007000 */ #define ETH_MACMDIOAR_NTC ETH_MACMDIOAR_NTC_Msk /*!< Number of Training Clocks */ @@ -12297,7 +12324,7 @@ typedef struct #define ETH_MMCTXIMR_TXLPIUSCIM ETH_MMCTXIMR_TXLPIUSCIM_Msk /*!< MMC Transmit LPI microsecond counter interrupt Mask */ #define ETH_MMCTXIMR_TXLPITRCIM_Pos (27U) #define ETH_MMCTXIMR_TXLPITRCIM_Msk (0x1UL << ETH_MMCTXIMR_TXLPITRCIM_Pos) /*!< 0x08000000 */ -#define ETH_MMCTXIMR_TXLPITRCIM ETH_MMC_INTERRUPT_MASK_TXLPITRCIM_Msk /*!< MMC Transmit LPI transition counter interrupt Mask */ +#define ETH_MMCTXIMR_TXLPITRCIM ETH_MMCTXIMR_TXLPITRCIM_Msk /*!< MMC Transmit LPI transition counter interrupt Mask */ /*********** Bit definition for ETH_MMC_TX_SINGLE_COLLISION_GOOD_PACKETS register ************/ #define ETH_MMCTXSCGPR_TXSNGLCOLG_Pos (0U) @@ -15000,9 +15027,10 @@ typedef struct #define ETH_DMAC0CR_DSL_Pos (18U) #define ETH_DMAC0CR_DSL_Msk (0x7UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x001C0000 */ #define ETH_DMAC0CR_DSL ETH_DMAC0CR_DSL_Msk /*!< Descriptor Skip Length */ -#define ETH_DMAC0CR_DSL_0 (0x1UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00040000 */ -#define ETH_DMAC0CR_DSL_1 (0x2UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00080000 */ -#define ETH_DMAC0CR_DSL_2 (0x4UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00100000 */ +#define ETH_DMACCR_DSL_0BIT (0x0UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00000000 */ +#define ETH_DMACCR_DSL_32BIT (0x1UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00040000 */ +#define ETH_DMACCR_DSL_64BIT (0x2UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00080000 */ +#define ETH_DMACCR_DSL_128BIT (0x4UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00100000 */ /************* Bit definition for ETH_DMAC0TXCR register *************/ #define ETH_DMAC0TXCR_ST_Pos (0U) @@ -15023,12 +15051,12 @@ typedef struct #define ETH_DMAC0TXCR_TXPBL_Pos (16U) #define ETH_DMAC0TXCR_TXPBL_Msk (0x3FUL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x003F0000 */ #define ETH_DMAC0TXCR_TXPBL ETH_DMAC0TXCR_TXPBL_Msk /*!< Transmit Programmable Burst Length */ -#define ETH_DMAC0TXCR_TXPBL_0 (0x1UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00010000 */ -#define ETH_DMAC0TXCR_TXPBL_1 (0x2UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00020000 */ -#define ETH_DMAC0TXCR_TXPBL_2 (0x4UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00040000 */ -#define ETH_DMAC0TXCR_TXPBL_3 (0x8UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00080000 */ -#define ETH_DMAC0TXCR_TXPBL_4 (0x10UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00100000 */ -#define ETH_DMAC0TXCR_TXPBL_5 (0x20UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00200000 */ +#define ETH_DMAC0TXCR_TXPBL_1PBL (0x1UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00010000 */ +#define ETH_DMAC0TXCR_TXPBL_2PBL (0x2UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00020000 */ +#define ETH_DMAC0TXCR_TXPBL_4PBL (0x4UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00040000 */ +#define ETH_DMAC0TXCR_TXPBL_8PBL (0x8UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00080000 */ +#define ETH_DMAC0TXCR_TXPBL_16PBL (0x10UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00100000 */ +#define ETH_DMAC0TXCR_TXPBL_32PBL (0x20UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00200000 */ #define ETH_DMAC0TXCR_TQOS_Pos (24U) #define ETH_DMAC0TXCR_TQOS_Msk (0xFUL << ETH_DMAC0TXCR_TQOS_Pos) /*!< 0x0F000000 */ #define ETH_DMAC0TXCR_TQOS ETH_DMAC0TXCR_TQOS_Msk /*!< Transmit QOS. */ @@ -15061,12 +15089,12 @@ typedef struct #define ETH_DMAC0RXCR_RXPBL_Pos (16U) #define ETH_DMAC0RXCR_RXPBL_Msk (0x3FUL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x003F0000 */ #define ETH_DMAC0RXCR_RXPBL ETH_DMAC0RXCR_RXPBL_Msk /*!< Receive Programmable Burst Length */ -#define ETH_DMAC0RXCR_RXPBL_0 (0x1UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00010000 */ -#define ETH_DMAC0RXCR_RXPBL_1 (0x2UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00020000 */ -#define ETH_DMAC0RXCR_RXPBL_2 (0x4UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00040000 */ -#define ETH_DMAC0RXCR_RXPBL_3 (0x8UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00080000 */ -#define ETH_DMAC0RXCR_RXPBL_4 (0x10UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00100000 */ -#define ETH_DMAC0RXCR_RXPBL_5 (0x20UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00200000 */ +#define ETH_DMAC0RXCR_RXPBL_1PBL (0x1UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00010000 */ +#define ETH_DMAC0RXCR_RXPBL_2PBL (0x2UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00020000 */ +#define ETH_DMAC0RXCR_RXPBL_4PBL (0x4UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00040000 */ +#define ETH_DMAC0RXCR_RXPBL_8PBL (0x8UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00080000 */ +#define ETH_DMAC0RXCR_RXPBL_16PBL (0x10UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00100000 */ +#define ETH_DMAC0RXCR_RXPBL_32PBL (0x20UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00200000 */ #define ETH_DMAC0RXCR_RQOS_Pos (24U) #define ETH_DMAC0RXCR_RQOS_Msk (0xFUL << ETH_DMAC0RXCR_RQOS_Pos) /*!< 0x0F000000 */ #define ETH_DMAC0RXCR_RQOS ETH_DMAC0RXCR_RQOS_Msk /*!< Rx AXI4 QOS. */ @@ -23004,6 +23032,16 @@ typedef struct #define BSEC_HWCFGR_ECC_USE_Msk (0xFUL << BSEC_HWCFGR_ECC_USE_Pos) /*!< 0x000000F0 */ #define BSEC_HWCFGR_ECC_USE BSEC_HWCFGR_ECC_USE_Msk /*!< protection / redundancy scheme used */ +/******************** Bit definition for BSEC_JTAGIN register ********************/ +#define BSEC_JTAGIN_DATA_Pos (0U) +#define BSEC_JTAGIN_DATA_Msk (0x0000FFFFUL << BSEC_JTAGIN_DATA_Pos) /*!< JTAG Input Data */ +#define BSEC_JTAGIN_DATA BSEC_JTAGIN_DATA_Msk + +/******************** Bit definition for BSEC_JTAGOUT register ********************/ +#define BSEC_JTAGOUT_DATA_Pos (0U) +#define BSEC_JTAGOUT_DATA_Msk (0x0000FFFFUL << BSEC_JTAGOUT_DATA_Pos) /*!< JTAG Output Data */ +#define BSEC_JTAGOUT_DATA BSEC_JTAGOUT_DATA_Msk + /******************** Bit definition for BSEC_VERR register********************/ #define BSEC_VERR_MINREV_Pos (0U) #define BSEC_VERR_MINREV_Msk (0xFUL << BSEC_VERR_MINREV_Pos) /*!< 0x0000000F */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153axx_ca7.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153axx_ca7.h index 7432828197..b19da6d580 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153axx_ca7.h +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153axx_ca7.h @@ -12264,16 +12264,19 @@ typedef struct #define ETH_MACCR_PRELEN_Pos (2U) #define ETH_MACCR_PRELEN_Msk (0x3UL << ETH_MACCR_PRELEN_Pos) /*!< 0x0000000C */ #define ETH_MACCR_PRELEN ETH_MACCR_PRELEN_Msk /*!< Preamble Length for Transmit packets */ -#define ETH_MACCR_PRELEN_0 (0x1UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000004 */ -#define ETH_MACCR_PRELEN_1 (0x2UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000008 */ +#define ETH_MACCR_PRELEN_7 (0x0UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000000 */ +#define ETH_MACCR_PRELEN_5 (0x1UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000004 */ +#define ETH_MACCR_PRELEN_3 (0x2UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000006 */ #define ETH_MACCR_DC_Pos (4U) #define ETH_MACCR_DC_Msk (0x1UL << ETH_MACCR_DC_Pos) /*!< 0x00000010 */ #define ETH_MACCR_DC ETH_MACCR_DC_Msk /*!< Deferral Check */ #define ETH_MACCR_BL_Pos (5U) #define ETH_MACCR_BL_Msk (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */ #define ETH_MACCR_BL ETH_MACCR_BL_Msk /*!< Back-Off Limit */ -#define ETH_MACCR_BL_0 (0x1UL << ETH_MACCR_BL_Pos) /*!< 0x00000020 */ -#define ETH_MACCR_BL_1 (0x2UL << ETH_MACCR_BL_Pos) /*!< 0x00000040 */ +#define ETH_MACCR_BL_10 (0x0UL << ETH_MACCR_BL_Pos) /*!< 0x00000000 */ +#define ETH_MACCR_BL_8 (0x1UL << ETH_MACCR_BL_Pos) /*!< 0x00000020 */ +#define ETH_MACCR_BL_4 (0x2UL << ETH_MACCR_BL_Pos) /*!< 0x00000040 */ +#define ETH_MACCR_BL_1 (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */ #define ETH_MACCR_DR_Pos (8U) #define ETH_MACCR_DR_Msk (0x1UL << ETH_MACCR_DR_Pos) /*!< 0x00000100 */ #define ETH_MACCR_DR ETH_MACCR_DR_Msk /*!< Disable Retry */ @@ -12325,9 +12328,14 @@ typedef struct #define ETH_MACCR_IPG_Pos (24U) #define ETH_MACCR_IPG_Msk (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */ #define ETH_MACCR_IPG ETH_MACCR_IPG_Msk /*!< Inter-Packet Gap */ -#define ETH_MACCR_IPG_0 (0x1UL << ETH_MACCR_IPG_Pos) /*!< 0x01000000 */ -#define ETH_MACCR_IPG_1 (0x2UL << ETH_MACCR_IPG_Pos) /*!< 0x02000000 */ -#define ETH_MACCR_IPG_2 (0x4UL << ETH_MACCR_IPG_Pos) /*!< 0x04000000 */ +#define ETH_MACCR_IPG_96BIT (0x0UL << ETH_MACCR_IPG_Pos) /*!< 0x00000000 */ +#define ETH_MACCR_IPG_88BIT (0x1UL << ETH_MACCR_IPG_Pos) /*!< 0x01000000 */ +#define ETH_MACCR_IPG_80BIT (0x2UL << ETH_MACCR_IPG_Pos) /*!< 0x02000000 */ +#define ETH_MACCR_IPG_72BIT (0x3UL << ETH_MACCR_IPG_Pos) /*!< 0x03000000 */ +#define ETH_MACCR_IPG_64BIT (0x4UL << ETH_MACCR_IPG_Pos) /*!< 0x04000000 */ +#define ETH_MACCR_IPG_56BIT (0x5UL << ETH_MACCR_IPG_Pos) /*!< 0x05000000 */ +#define ETH_MACCR_IPG_48BIT (0x6UL << ETH_MACCR_IPG_Pos) /*!< 0x06000000 */ +#define ETH_MACCR_IPG_40BIT (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */ #define ETH_MACCR_IPC_Pos (27U) #define ETH_MACCR_IPC_Msk (0x1UL << ETH_MACCR_IPC_Pos) /*!< 0x08000000 */ #define ETH_MACCR_IPC ETH_MACCR_IPC_Msk /*!< Checksum Offload */ @@ -12430,10 +12438,21 @@ typedef struct #define ETH_MACWTR_WTO_Pos (0U) #define ETH_MACWTR_WTO_Msk (0xFUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000F */ #define ETH_MACWTR_WTO ETH_MACWTR_WTO_Msk /*!< Watchdog Timeout */ -#define ETH_MACWTR_WTO_0 (0x1UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000001 */ -#define ETH_MACWTR_WTO_1 (0x2UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000002 */ -#define ETH_MACWTR_WTO_2 (0x4UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000004 */ -#define ETH_MACWTR_WTO_3 (0x8UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000008 */ +#define ETH_MACWTR_WTO_2KB (0x0UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000001 */ +#define ETH_MACWTR_WTO_3KB (0x1UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000001 */ +#define ETH_MACWTR_WTO_4KB (0x2UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000002 */ +#define ETH_MACWTR_WTO_5KB (0x3UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000003 */ +#define ETH_MACWTR_WTO_6KB (0x4UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000004 */ +#define ETH_MACWTR_WTO_7KB (0x5UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000005 */ +#define ETH_MACWTR_WTO_8KB (0x6UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000006 */ +#define ETH_MACWTR_WTO_9KB (0x7UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000007 */ +#define ETH_MACWTR_WTO_10KB (0x8UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000008 */ +#define ETH_MACWTR_WTO_11KB (0x9UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000009 */ +#define ETH_MACWTR_WTO_12KB (0xAUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000A */ +#define ETH_MACWTR_WTO_13KB (0xBUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000B */ +#define ETH_MACWTR_WTO_14KB (0xCUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000C */ +#define ETH_MACWTR_WTO_15KB (0xDUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000D */ +#define ETH_MACWTR_WTO_16KB (0xEUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000E */ #define ETH_MACWTR_PWE_Pos (8U) #define ETH_MACWTR_PWE_Msk (0x1UL << ETH_MACWTR_PWE_Pos) /*!< 0x00000100 */ #define ETH_MACWTR_PWE ETH_MACWTR_PWE_Msk /*!< Programmable Watchdog Enable */ @@ -12513,6 +12532,9 @@ typedef struct #define ETH_MACHT1R_HT63T32_31 (0x80000000UL << ETH_MACHT1R_HT63T32_Pos) /*!< 0x80000000 */ /************** Bit definition for ETH_MACVTR register ***************/ +#define ETH_MACVTR_VL_VID_Pos (0U) +#define ETH_MACVTR_VL_VID_Msk (0xFFFUL << ETH_MACVTR_VL_VID_Pos) /*!< 0x00000FFF */ +#define ETH_MACVTR_VL_VID ETH_MACVTR_VL_VID_Msk /*!< VLAN Tag Identifier field of VLAN tag */ #define ETH_MACVTR_VL_Pos (0U) #define ETH_MACVTR_VL_Msk (0xFFFFUL << ETH_MACVTR_VL_Pos) /*!< 0x0000FFFF */ #define ETH_MACVTR_VL ETH_MACVTR_VL_Msk /*!< VLAN Tag Identifier for Receive Packets */ @@ -12674,9 +12696,12 @@ typedef struct #define ETH_MACQ0TXFCR_PLT_Pos (4U) #define ETH_MACQ0TXFCR_PLT_Msk (0x7UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000070 */ #define ETH_MACQ0TXFCR_PLT ETH_MACQ0TXFCR_PLT_Msk /*!< Pause Low Threshold */ -#define ETH_MACQ0TXFCR_PLT_0 (0x1UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000010 */ -#define ETH_MACQ0TXFCR_PLT_1 (0x2UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000020 */ -#define ETH_MACQ0TXFCR_PLT_2 (0x4UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000040 */ +#define ETH_MACQ0TXFCR_PLT_MINUS4 (0x0UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000000 */ +#define ETH_MACQ0TXFCR_PLT_MINUS28 (0x1UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000010 */ +#define ETH_MACQ0TXFCR_PLT_MINUS36 (0x2UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000020 */ +#define ETH_MACQ0TXFCR_PLT_MINUS144 (0x3UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000030 */ +#define ETH_MACQ0TXFCR_PLT_MINUS256 (0x4UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000040 */ +#define ETH_MACQ0TXFCR_PLT_MINUS512 (0x5UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000050 */ #define ETH_MACQ0TXFCR_DZPQ_Pos (7U) #define ETH_MACQ0TXFCR_DZPQ_Msk (0x1UL << ETH_MACQ0TXFCR_DZPQ_Pos) /*!< 0x00000080 */ #define ETH_MACQ0TXFCR_DZPQ ETH_MACQ0TXFCR_DZPQ_Msk /*!< Disable Zero-Quanta Pause */ @@ -13243,10 +13268,12 @@ typedef struct #define ETH_MACMDIOAR_CR_Pos (8U) #define ETH_MACMDIOAR_CR_Msk (0xFUL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000F00 */ #define ETH_MACMDIOAR_CR ETH_MACMDIOAR_CR_Msk /*!< CSR Clock Range */ -#define ETH_MACMDIOAR_CR_0 (0x1UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000100 */ -#define ETH_MACMDIOAR_CR_1 (0x2UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000200 */ -#define ETH_MACMDIOAR_CR_2 (0x4UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000400 */ -#define ETH_MACMDIOAR_CR_3 (0x8UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000800 */ +#define ETH_MACMDIOAR_CR_DIV42 (0x0UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000000 */ +#define ETH_MACMDIOAR_CR_DIV62 (0x1UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000100 */ +#define ETH_MACMDIOAR_CR_DIV16 (0x2UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000200 */ +#define ETH_MACMDIOAR_CR_DIV26 (0x3UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000300 */ +#define ETH_MACMDIOAR_CR_DIV102 (0x4UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000400 */ +#define ETH_MACMDIOAR_CR_DIV124 (0x5UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000500 */ #define ETH_MACMDIOAR_NTC_Pos (12U) #define ETH_MACMDIOAR_NTC_Msk (0x7UL << ETH_MACMDIOAR_NTC_Pos) /*!< 0x00007000 */ #define ETH_MACMDIOAR_NTC ETH_MACMDIOAR_NTC_Msk /*!< Number of Training Clocks */ @@ -13685,7 +13712,7 @@ typedef struct #define ETH_MMCTXIMR_TXLPIUSCIM ETH_MMCTXIMR_TXLPIUSCIM_Msk /*!< MMC Transmit LPI microsecond counter interrupt Mask */ #define ETH_MMCTXIMR_TXLPITRCIM_Pos (27U) #define ETH_MMCTXIMR_TXLPITRCIM_Msk (0x1UL << ETH_MMCTXIMR_TXLPITRCIM_Pos) /*!< 0x08000000 */ -#define ETH_MMCTXIMR_TXLPITRCIM ETH_MMC_INTERRUPT_MASK_TXLPITRCIM_Msk /*!< MMC Transmit LPI transition counter interrupt Mask */ +#define ETH_MMCTXIMR_TXLPITRCIM ETH_MMCTXIMR_TXLPITRCIM_Msk /*!< MMC Transmit LPI transition counter interrupt Mask */ /*********** Bit definition for ETH_MMC_TX_SINGLE_COLLISION_GOOD_PACKETS register ************/ #define ETH_MMCTXSCGPR_TXSNGLCOLG_Pos (0U) @@ -16388,9 +16415,10 @@ typedef struct #define ETH_DMAC0CR_DSL_Pos (18U) #define ETH_DMAC0CR_DSL_Msk (0x7UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x001C0000 */ #define ETH_DMAC0CR_DSL ETH_DMAC0CR_DSL_Msk /*!< Descriptor Skip Length */ -#define ETH_DMAC0CR_DSL_0 (0x1UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00040000 */ -#define ETH_DMAC0CR_DSL_1 (0x2UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00080000 */ -#define ETH_DMAC0CR_DSL_2 (0x4UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00100000 */ +#define ETH_DMACCR_DSL_0BIT (0x0UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00000000 */ +#define ETH_DMACCR_DSL_32BIT (0x1UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00040000 */ +#define ETH_DMACCR_DSL_64BIT (0x2UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00080000 */ +#define ETH_DMACCR_DSL_128BIT (0x4UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00100000 */ /************* Bit definition for ETH_DMAC0TXCR register *************/ #define ETH_DMAC0TXCR_ST_Pos (0U) @@ -16411,12 +16439,12 @@ typedef struct #define ETH_DMAC0TXCR_TXPBL_Pos (16U) #define ETH_DMAC0TXCR_TXPBL_Msk (0x3FUL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x003F0000 */ #define ETH_DMAC0TXCR_TXPBL ETH_DMAC0TXCR_TXPBL_Msk /*!< Transmit Programmable Burst Length */ -#define ETH_DMAC0TXCR_TXPBL_0 (0x1UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00010000 */ -#define ETH_DMAC0TXCR_TXPBL_1 (0x2UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00020000 */ -#define ETH_DMAC0TXCR_TXPBL_2 (0x4UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00040000 */ -#define ETH_DMAC0TXCR_TXPBL_3 (0x8UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00080000 */ -#define ETH_DMAC0TXCR_TXPBL_4 (0x10UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00100000 */ -#define ETH_DMAC0TXCR_TXPBL_5 (0x20UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00200000 */ +#define ETH_DMAC0TXCR_TXPBL_1PBL (0x1UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00010000 */ +#define ETH_DMAC0TXCR_TXPBL_2PBL (0x2UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00020000 */ +#define ETH_DMAC0TXCR_TXPBL_4PBL (0x4UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00040000 */ +#define ETH_DMAC0TXCR_TXPBL_8PBL (0x8UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00080000 */ +#define ETH_DMAC0TXCR_TXPBL_16PBL (0x10UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00100000 */ +#define ETH_DMAC0TXCR_TXPBL_32PBL (0x20UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00200000 */ #define ETH_DMAC0TXCR_TQOS_Pos (24U) #define ETH_DMAC0TXCR_TQOS_Msk (0xFUL << ETH_DMAC0TXCR_TQOS_Pos) /*!< 0x0F000000 */ #define ETH_DMAC0TXCR_TQOS ETH_DMAC0TXCR_TQOS_Msk /*!< Transmit QOS. */ @@ -16449,12 +16477,12 @@ typedef struct #define ETH_DMAC0RXCR_RXPBL_Pos (16U) #define ETH_DMAC0RXCR_RXPBL_Msk (0x3FUL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x003F0000 */ #define ETH_DMAC0RXCR_RXPBL ETH_DMAC0RXCR_RXPBL_Msk /*!< Receive Programmable Burst Length */ -#define ETH_DMAC0RXCR_RXPBL_0 (0x1UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00010000 */ -#define ETH_DMAC0RXCR_RXPBL_1 (0x2UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00020000 */ -#define ETH_DMAC0RXCR_RXPBL_2 (0x4UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00040000 */ -#define ETH_DMAC0RXCR_RXPBL_3 (0x8UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00080000 */ -#define ETH_DMAC0RXCR_RXPBL_4 (0x10UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00100000 */ -#define ETH_DMAC0RXCR_RXPBL_5 (0x20UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00200000 */ +#define ETH_DMAC0RXCR_RXPBL_1PBL (0x1UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00010000 */ +#define ETH_DMAC0RXCR_RXPBL_2PBL (0x2UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00020000 */ +#define ETH_DMAC0RXCR_RXPBL_4PBL (0x4UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00040000 */ +#define ETH_DMAC0RXCR_RXPBL_8PBL (0x8UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00080000 */ +#define ETH_DMAC0RXCR_RXPBL_16PBL (0x10UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00100000 */ +#define ETH_DMAC0RXCR_RXPBL_32PBL (0x20UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00200000 */ #define ETH_DMAC0RXCR_RQOS_Pos (24U) #define ETH_DMAC0RXCR_RQOS_Msk (0xFUL << ETH_DMAC0RXCR_RQOS_Pos) /*!< 0x0F000000 */ #define ETH_DMAC0RXCR_RQOS ETH_DMAC0RXCR_RQOS_Msk /*!< Rx AXI4 QOS. */ @@ -24392,6 +24420,16 @@ typedef struct #define BSEC_HWCFGR_ECC_USE_Msk (0xFUL << BSEC_HWCFGR_ECC_USE_Pos) /*!< 0x000000F0 */ #define BSEC_HWCFGR_ECC_USE BSEC_HWCFGR_ECC_USE_Msk /*!< protection / redundancy scheme used */ +/******************** Bit definition for BSEC_JTAGIN register ********************/ +#define BSEC_JTAGIN_DATA_Pos (0U) +#define BSEC_JTAGIN_DATA_Msk (0x0000FFFFUL << BSEC_JTAGIN_DATA_Pos) /*!< JTAG Input Data */ +#define BSEC_JTAGIN_DATA BSEC_JTAGIN_DATA_Msk + +/******************** Bit definition for BSEC_JTAGOUT register ********************/ +#define BSEC_JTAGOUT_DATA_Pos (0U) +#define BSEC_JTAGOUT_DATA_Msk (0x0000FFFFUL << BSEC_JTAGOUT_DATA_Pos) /*!< JTAG Output Data */ +#define BSEC_JTAGOUT_DATA BSEC_JTAGOUT_DATA_Msk + /******************** Bit definition for BSEC_VERR register********************/ #define BSEC_VERR_MINREV_Pos (0U) #define BSEC_VERR_MINREV_Msk (0xFUL << BSEC_VERR_MINREV_Pos) /*!< 0x0000000F */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153axx_cm4.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153axx_cm4.h index ca7951989b..db1b9d82dc 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153axx_cm4.h +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153axx_cm4.h @@ -12230,16 +12230,19 @@ typedef struct #define ETH_MACCR_PRELEN_Pos (2U) #define ETH_MACCR_PRELEN_Msk (0x3UL << ETH_MACCR_PRELEN_Pos) /*!< 0x0000000C */ #define ETH_MACCR_PRELEN ETH_MACCR_PRELEN_Msk /*!< Preamble Length for Transmit packets */ -#define ETH_MACCR_PRELEN_0 (0x1UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000004 */ -#define ETH_MACCR_PRELEN_1 (0x2UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000008 */ +#define ETH_MACCR_PRELEN_7 (0x0UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000000 */ +#define ETH_MACCR_PRELEN_5 (0x1UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000004 */ +#define ETH_MACCR_PRELEN_3 (0x2UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000006 */ #define ETH_MACCR_DC_Pos (4U) #define ETH_MACCR_DC_Msk (0x1UL << ETH_MACCR_DC_Pos) /*!< 0x00000010 */ #define ETH_MACCR_DC ETH_MACCR_DC_Msk /*!< Deferral Check */ #define ETH_MACCR_BL_Pos (5U) #define ETH_MACCR_BL_Msk (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */ #define ETH_MACCR_BL ETH_MACCR_BL_Msk /*!< Back-Off Limit */ -#define ETH_MACCR_BL_0 (0x1UL << ETH_MACCR_BL_Pos) /*!< 0x00000020 */ -#define ETH_MACCR_BL_1 (0x2UL << ETH_MACCR_BL_Pos) /*!< 0x00000040 */ +#define ETH_MACCR_BL_10 (0x0UL << ETH_MACCR_BL_Pos) /*!< 0x00000000 */ +#define ETH_MACCR_BL_8 (0x1UL << ETH_MACCR_BL_Pos) /*!< 0x00000020 */ +#define ETH_MACCR_BL_4 (0x2UL << ETH_MACCR_BL_Pos) /*!< 0x00000040 */ +#define ETH_MACCR_BL_1 (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */ #define ETH_MACCR_DR_Pos (8U) #define ETH_MACCR_DR_Msk (0x1UL << ETH_MACCR_DR_Pos) /*!< 0x00000100 */ #define ETH_MACCR_DR ETH_MACCR_DR_Msk /*!< Disable Retry */ @@ -12291,9 +12294,14 @@ typedef struct #define ETH_MACCR_IPG_Pos (24U) #define ETH_MACCR_IPG_Msk (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */ #define ETH_MACCR_IPG ETH_MACCR_IPG_Msk /*!< Inter-Packet Gap */ -#define ETH_MACCR_IPG_0 (0x1UL << ETH_MACCR_IPG_Pos) /*!< 0x01000000 */ -#define ETH_MACCR_IPG_1 (0x2UL << ETH_MACCR_IPG_Pos) /*!< 0x02000000 */ -#define ETH_MACCR_IPG_2 (0x4UL << ETH_MACCR_IPG_Pos) /*!< 0x04000000 */ +#define ETH_MACCR_IPG_96BIT (0x0UL << ETH_MACCR_IPG_Pos) /*!< 0x00000000 */ +#define ETH_MACCR_IPG_88BIT (0x1UL << ETH_MACCR_IPG_Pos) /*!< 0x01000000 */ +#define ETH_MACCR_IPG_80BIT (0x2UL << ETH_MACCR_IPG_Pos) /*!< 0x02000000 */ +#define ETH_MACCR_IPG_72BIT (0x3UL << ETH_MACCR_IPG_Pos) /*!< 0x03000000 */ +#define ETH_MACCR_IPG_64BIT (0x4UL << ETH_MACCR_IPG_Pos) /*!< 0x04000000 */ +#define ETH_MACCR_IPG_56BIT (0x5UL << ETH_MACCR_IPG_Pos) /*!< 0x05000000 */ +#define ETH_MACCR_IPG_48BIT (0x6UL << ETH_MACCR_IPG_Pos) /*!< 0x06000000 */ +#define ETH_MACCR_IPG_40BIT (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */ #define ETH_MACCR_IPC_Pos (27U) #define ETH_MACCR_IPC_Msk (0x1UL << ETH_MACCR_IPC_Pos) /*!< 0x08000000 */ #define ETH_MACCR_IPC ETH_MACCR_IPC_Msk /*!< Checksum Offload */ @@ -12396,10 +12404,21 @@ typedef struct #define ETH_MACWTR_WTO_Pos (0U) #define ETH_MACWTR_WTO_Msk (0xFUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000F */ #define ETH_MACWTR_WTO ETH_MACWTR_WTO_Msk /*!< Watchdog Timeout */ -#define ETH_MACWTR_WTO_0 (0x1UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000001 */ -#define ETH_MACWTR_WTO_1 (0x2UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000002 */ -#define ETH_MACWTR_WTO_2 (0x4UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000004 */ -#define ETH_MACWTR_WTO_3 (0x8UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000008 */ +#define ETH_MACWTR_WTO_2KB (0x0UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000001 */ +#define ETH_MACWTR_WTO_3KB (0x1UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000001 */ +#define ETH_MACWTR_WTO_4KB (0x2UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000002 */ +#define ETH_MACWTR_WTO_5KB (0x3UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000003 */ +#define ETH_MACWTR_WTO_6KB (0x4UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000004 */ +#define ETH_MACWTR_WTO_7KB (0x5UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000005 */ +#define ETH_MACWTR_WTO_8KB (0x6UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000006 */ +#define ETH_MACWTR_WTO_9KB (0x7UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000007 */ +#define ETH_MACWTR_WTO_10KB (0x8UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000008 */ +#define ETH_MACWTR_WTO_11KB (0x9UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000009 */ +#define ETH_MACWTR_WTO_12KB (0xAUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000A */ +#define ETH_MACWTR_WTO_13KB (0xBUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000B */ +#define ETH_MACWTR_WTO_14KB (0xCUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000C */ +#define ETH_MACWTR_WTO_15KB (0xDUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000D */ +#define ETH_MACWTR_WTO_16KB (0xEUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000E */ #define ETH_MACWTR_PWE_Pos (8U) #define ETH_MACWTR_PWE_Msk (0x1UL << ETH_MACWTR_PWE_Pos) /*!< 0x00000100 */ #define ETH_MACWTR_PWE ETH_MACWTR_PWE_Msk /*!< Programmable Watchdog Enable */ @@ -12479,6 +12498,9 @@ typedef struct #define ETH_MACHT1R_HT63T32_31 (0x80000000UL << ETH_MACHT1R_HT63T32_Pos) /*!< 0x80000000 */ /************** Bit definition for ETH_MACVTR register ***************/ +#define ETH_MACVTR_VL_VID_Pos (0U) +#define ETH_MACVTR_VL_VID_Msk (0xFFFUL << ETH_MACVTR_VL_VID_Pos) /*!< 0x00000FFF */ +#define ETH_MACVTR_VL_VID ETH_MACVTR_VL_VID_Msk /*!< VLAN Tag Identifier field of VLAN tag */ #define ETH_MACVTR_VL_Pos (0U) #define ETH_MACVTR_VL_Msk (0xFFFFUL << ETH_MACVTR_VL_Pos) /*!< 0x0000FFFF */ #define ETH_MACVTR_VL ETH_MACVTR_VL_Msk /*!< VLAN Tag Identifier for Receive Packets */ @@ -12640,9 +12662,12 @@ typedef struct #define ETH_MACQ0TXFCR_PLT_Pos (4U) #define ETH_MACQ0TXFCR_PLT_Msk (0x7UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000070 */ #define ETH_MACQ0TXFCR_PLT ETH_MACQ0TXFCR_PLT_Msk /*!< Pause Low Threshold */ -#define ETH_MACQ0TXFCR_PLT_0 (0x1UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000010 */ -#define ETH_MACQ0TXFCR_PLT_1 (0x2UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000020 */ -#define ETH_MACQ0TXFCR_PLT_2 (0x4UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000040 */ +#define ETH_MACQ0TXFCR_PLT_MINUS4 (0x0UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000000 */ +#define ETH_MACQ0TXFCR_PLT_MINUS28 (0x1UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000010 */ +#define ETH_MACQ0TXFCR_PLT_MINUS36 (0x2UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000020 */ +#define ETH_MACQ0TXFCR_PLT_MINUS144 (0x3UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000030 */ +#define ETH_MACQ0TXFCR_PLT_MINUS256 (0x4UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000040 */ +#define ETH_MACQ0TXFCR_PLT_MINUS512 (0x5UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000050 */ #define ETH_MACQ0TXFCR_DZPQ_Pos (7U) #define ETH_MACQ0TXFCR_DZPQ_Msk (0x1UL << ETH_MACQ0TXFCR_DZPQ_Pos) /*!< 0x00000080 */ #define ETH_MACQ0TXFCR_DZPQ ETH_MACQ0TXFCR_DZPQ_Msk /*!< Disable Zero-Quanta Pause */ @@ -13209,10 +13234,12 @@ typedef struct #define ETH_MACMDIOAR_CR_Pos (8U) #define ETH_MACMDIOAR_CR_Msk (0xFUL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000F00 */ #define ETH_MACMDIOAR_CR ETH_MACMDIOAR_CR_Msk /*!< CSR Clock Range */ -#define ETH_MACMDIOAR_CR_0 (0x1UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000100 */ -#define ETH_MACMDIOAR_CR_1 (0x2UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000200 */ -#define ETH_MACMDIOAR_CR_2 (0x4UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000400 */ -#define ETH_MACMDIOAR_CR_3 (0x8UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000800 */ +#define ETH_MACMDIOAR_CR_DIV42 (0x0UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000000 */ +#define ETH_MACMDIOAR_CR_DIV62 (0x1UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000100 */ +#define ETH_MACMDIOAR_CR_DIV16 (0x2UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000200 */ +#define ETH_MACMDIOAR_CR_DIV26 (0x3UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000300 */ +#define ETH_MACMDIOAR_CR_DIV102 (0x4UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000400 */ +#define ETH_MACMDIOAR_CR_DIV124 (0x5UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000500 */ #define ETH_MACMDIOAR_NTC_Pos (12U) #define ETH_MACMDIOAR_NTC_Msk (0x7UL << ETH_MACMDIOAR_NTC_Pos) /*!< 0x00007000 */ #define ETH_MACMDIOAR_NTC ETH_MACMDIOAR_NTC_Msk /*!< Number of Training Clocks */ @@ -13651,7 +13678,7 @@ typedef struct #define ETH_MMCTXIMR_TXLPIUSCIM ETH_MMCTXIMR_TXLPIUSCIM_Msk /*!< MMC Transmit LPI microsecond counter interrupt Mask */ #define ETH_MMCTXIMR_TXLPITRCIM_Pos (27U) #define ETH_MMCTXIMR_TXLPITRCIM_Msk (0x1UL << ETH_MMCTXIMR_TXLPITRCIM_Pos) /*!< 0x08000000 */ -#define ETH_MMCTXIMR_TXLPITRCIM ETH_MMC_INTERRUPT_MASK_TXLPITRCIM_Msk /*!< MMC Transmit LPI transition counter interrupt Mask */ +#define ETH_MMCTXIMR_TXLPITRCIM ETH_MMCTXIMR_TXLPITRCIM_Msk /*!< MMC Transmit LPI transition counter interrupt Mask */ /*********** Bit definition for ETH_MMC_TX_SINGLE_COLLISION_GOOD_PACKETS register ************/ #define ETH_MMCTXSCGPR_TXSNGLCOLG_Pos (0U) @@ -16354,9 +16381,10 @@ typedef struct #define ETH_DMAC0CR_DSL_Pos (18U) #define ETH_DMAC0CR_DSL_Msk (0x7UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x001C0000 */ #define ETH_DMAC0CR_DSL ETH_DMAC0CR_DSL_Msk /*!< Descriptor Skip Length */ -#define ETH_DMAC0CR_DSL_0 (0x1UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00040000 */ -#define ETH_DMAC0CR_DSL_1 (0x2UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00080000 */ -#define ETH_DMAC0CR_DSL_2 (0x4UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00100000 */ +#define ETH_DMACCR_DSL_0BIT (0x0UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00000000 */ +#define ETH_DMACCR_DSL_32BIT (0x1UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00040000 */ +#define ETH_DMACCR_DSL_64BIT (0x2UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00080000 */ +#define ETH_DMACCR_DSL_128BIT (0x4UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00100000 */ /************* Bit definition for ETH_DMAC0TXCR register *************/ #define ETH_DMAC0TXCR_ST_Pos (0U) @@ -16377,12 +16405,12 @@ typedef struct #define ETH_DMAC0TXCR_TXPBL_Pos (16U) #define ETH_DMAC0TXCR_TXPBL_Msk (0x3FUL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x003F0000 */ #define ETH_DMAC0TXCR_TXPBL ETH_DMAC0TXCR_TXPBL_Msk /*!< Transmit Programmable Burst Length */ -#define ETH_DMAC0TXCR_TXPBL_0 (0x1UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00010000 */ -#define ETH_DMAC0TXCR_TXPBL_1 (0x2UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00020000 */ -#define ETH_DMAC0TXCR_TXPBL_2 (0x4UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00040000 */ -#define ETH_DMAC0TXCR_TXPBL_3 (0x8UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00080000 */ -#define ETH_DMAC0TXCR_TXPBL_4 (0x10UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00100000 */ -#define ETH_DMAC0TXCR_TXPBL_5 (0x20UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00200000 */ +#define ETH_DMAC0TXCR_TXPBL_1PBL (0x1UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00010000 */ +#define ETH_DMAC0TXCR_TXPBL_2PBL (0x2UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00020000 */ +#define ETH_DMAC0TXCR_TXPBL_4PBL (0x4UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00040000 */ +#define ETH_DMAC0TXCR_TXPBL_8PBL (0x8UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00080000 */ +#define ETH_DMAC0TXCR_TXPBL_16PBL (0x10UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00100000 */ +#define ETH_DMAC0TXCR_TXPBL_32PBL (0x20UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00200000 */ #define ETH_DMAC0TXCR_TQOS_Pos (24U) #define ETH_DMAC0TXCR_TQOS_Msk (0xFUL << ETH_DMAC0TXCR_TQOS_Pos) /*!< 0x0F000000 */ #define ETH_DMAC0TXCR_TQOS ETH_DMAC0TXCR_TQOS_Msk /*!< Transmit QOS. */ @@ -16415,12 +16443,12 @@ typedef struct #define ETH_DMAC0RXCR_RXPBL_Pos (16U) #define ETH_DMAC0RXCR_RXPBL_Msk (0x3FUL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x003F0000 */ #define ETH_DMAC0RXCR_RXPBL ETH_DMAC0RXCR_RXPBL_Msk /*!< Receive Programmable Burst Length */ -#define ETH_DMAC0RXCR_RXPBL_0 (0x1UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00010000 */ -#define ETH_DMAC0RXCR_RXPBL_1 (0x2UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00020000 */ -#define ETH_DMAC0RXCR_RXPBL_2 (0x4UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00040000 */ -#define ETH_DMAC0RXCR_RXPBL_3 (0x8UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00080000 */ -#define ETH_DMAC0RXCR_RXPBL_4 (0x10UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00100000 */ -#define ETH_DMAC0RXCR_RXPBL_5 (0x20UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00200000 */ +#define ETH_DMAC0RXCR_RXPBL_1PBL (0x1UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00010000 */ +#define ETH_DMAC0RXCR_RXPBL_2PBL (0x2UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00020000 */ +#define ETH_DMAC0RXCR_RXPBL_4PBL (0x4UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00040000 */ +#define ETH_DMAC0RXCR_RXPBL_8PBL (0x8UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00080000 */ +#define ETH_DMAC0RXCR_RXPBL_16PBL (0x10UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00100000 */ +#define ETH_DMAC0RXCR_RXPBL_32PBL (0x20UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00200000 */ #define ETH_DMAC0RXCR_RQOS_Pos (24U) #define ETH_DMAC0RXCR_RQOS_Msk (0xFUL << ETH_DMAC0RXCR_RQOS_Pos) /*!< 0x0F000000 */ #define ETH_DMAC0RXCR_RQOS ETH_DMAC0RXCR_RQOS_Msk /*!< Rx AXI4 QOS. */ @@ -24358,6 +24386,16 @@ typedef struct #define BSEC_HWCFGR_ECC_USE_Msk (0xFUL << BSEC_HWCFGR_ECC_USE_Pos) /*!< 0x000000F0 */ #define BSEC_HWCFGR_ECC_USE BSEC_HWCFGR_ECC_USE_Msk /*!< protection / redundancy scheme used */ +/******************** Bit definition for BSEC_JTAGIN register ********************/ +#define BSEC_JTAGIN_DATA_Pos (0U) +#define BSEC_JTAGIN_DATA_Msk (0x0000FFFFUL << BSEC_JTAGIN_DATA_Pos) /*!< JTAG Input Data */ +#define BSEC_JTAGIN_DATA BSEC_JTAGIN_DATA_Msk + +/******************** Bit definition for BSEC_JTAGOUT register ********************/ +#define BSEC_JTAGOUT_DATA_Pos (0U) +#define BSEC_JTAGOUT_DATA_Msk (0x0000FFFFUL << BSEC_JTAGOUT_DATA_Pos) /*!< JTAG Output Data */ +#define BSEC_JTAGOUT_DATA BSEC_JTAGOUT_DATA_Msk + /******************** Bit definition for BSEC_VERR register********************/ #define BSEC_VERR_MINREV_Pos (0U) #define BSEC_VERR_MINREV_Msk (0xFUL << BSEC_VERR_MINREV_Pos) /*!< 0x0000000F */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153cxx_ca7.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153cxx_ca7.h index c6c1c09e0e..b07db7e23b 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153cxx_ca7.h +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153cxx_ca7.h @@ -12461,16 +12461,19 @@ typedef struct #define ETH_MACCR_PRELEN_Pos (2U) #define ETH_MACCR_PRELEN_Msk (0x3UL << ETH_MACCR_PRELEN_Pos) /*!< 0x0000000C */ #define ETH_MACCR_PRELEN ETH_MACCR_PRELEN_Msk /*!< Preamble Length for Transmit packets */ -#define ETH_MACCR_PRELEN_0 (0x1UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000004 */ -#define ETH_MACCR_PRELEN_1 (0x2UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000008 */ +#define ETH_MACCR_PRELEN_7 (0x0UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000000 */ +#define ETH_MACCR_PRELEN_5 (0x1UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000004 */ +#define ETH_MACCR_PRELEN_3 (0x2UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000006 */ #define ETH_MACCR_DC_Pos (4U) #define ETH_MACCR_DC_Msk (0x1UL << ETH_MACCR_DC_Pos) /*!< 0x00000010 */ #define ETH_MACCR_DC ETH_MACCR_DC_Msk /*!< Deferral Check */ #define ETH_MACCR_BL_Pos (5U) #define ETH_MACCR_BL_Msk (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */ #define ETH_MACCR_BL ETH_MACCR_BL_Msk /*!< Back-Off Limit */ -#define ETH_MACCR_BL_0 (0x1UL << ETH_MACCR_BL_Pos) /*!< 0x00000020 */ -#define ETH_MACCR_BL_1 (0x2UL << ETH_MACCR_BL_Pos) /*!< 0x00000040 */ +#define ETH_MACCR_BL_10 (0x0UL << ETH_MACCR_BL_Pos) /*!< 0x00000000 */ +#define ETH_MACCR_BL_8 (0x1UL << ETH_MACCR_BL_Pos) /*!< 0x00000020 */ +#define ETH_MACCR_BL_4 (0x2UL << ETH_MACCR_BL_Pos) /*!< 0x00000040 */ +#define ETH_MACCR_BL_1 (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */ #define ETH_MACCR_DR_Pos (8U) #define ETH_MACCR_DR_Msk (0x1UL << ETH_MACCR_DR_Pos) /*!< 0x00000100 */ #define ETH_MACCR_DR ETH_MACCR_DR_Msk /*!< Disable Retry */ @@ -12522,9 +12525,14 @@ typedef struct #define ETH_MACCR_IPG_Pos (24U) #define ETH_MACCR_IPG_Msk (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */ #define ETH_MACCR_IPG ETH_MACCR_IPG_Msk /*!< Inter-Packet Gap */ -#define ETH_MACCR_IPG_0 (0x1UL << ETH_MACCR_IPG_Pos) /*!< 0x01000000 */ -#define ETH_MACCR_IPG_1 (0x2UL << ETH_MACCR_IPG_Pos) /*!< 0x02000000 */ -#define ETH_MACCR_IPG_2 (0x4UL << ETH_MACCR_IPG_Pos) /*!< 0x04000000 */ +#define ETH_MACCR_IPG_96BIT (0x0UL << ETH_MACCR_IPG_Pos) /*!< 0x00000000 */ +#define ETH_MACCR_IPG_88BIT (0x1UL << ETH_MACCR_IPG_Pos) /*!< 0x01000000 */ +#define ETH_MACCR_IPG_80BIT (0x2UL << ETH_MACCR_IPG_Pos) /*!< 0x02000000 */ +#define ETH_MACCR_IPG_72BIT (0x3UL << ETH_MACCR_IPG_Pos) /*!< 0x03000000 */ +#define ETH_MACCR_IPG_64BIT (0x4UL << ETH_MACCR_IPG_Pos) /*!< 0x04000000 */ +#define ETH_MACCR_IPG_56BIT (0x5UL << ETH_MACCR_IPG_Pos) /*!< 0x05000000 */ +#define ETH_MACCR_IPG_48BIT (0x6UL << ETH_MACCR_IPG_Pos) /*!< 0x06000000 */ +#define ETH_MACCR_IPG_40BIT (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */ #define ETH_MACCR_IPC_Pos (27U) #define ETH_MACCR_IPC_Msk (0x1UL << ETH_MACCR_IPC_Pos) /*!< 0x08000000 */ #define ETH_MACCR_IPC ETH_MACCR_IPC_Msk /*!< Checksum Offload */ @@ -12627,10 +12635,21 @@ typedef struct #define ETH_MACWTR_WTO_Pos (0U) #define ETH_MACWTR_WTO_Msk (0xFUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000F */ #define ETH_MACWTR_WTO ETH_MACWTR_WTO_Msk /*!< Watchdog Timeout */ -#define ETH_MACWTR_WTO_0 (0x1UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000001 */ -#define ETH_MACWTR_WTO_1 (0x2UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000002 */ -#define ETH_MACWTR_WTO_2 (0x4UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000004 */ -#define ETH_MACWTR_WTO_3 (0x8UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000008 */ +#define ETH_MACWTR_WTO_2KB (0x0UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000001 */ +#define ETH_MACWTR_WTO_3KB (0x1UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000001 */ +#define ETH_MACWTR_WTO_4KB (0x2UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000002 */ +#define ETH_MACWTR_WTO_5KB (0x3UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000003 */ +#define ETH_MACWTR_WTO_6KB (0x4UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000004 */ +#define ETH_MACWTR_WTO_7KB (0x5UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000005 */ +#define ETH_MACWTR_WTO_8KB (0x6UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000006 */ +#define ETH_MACWTR_WTO_9KB (0x7UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000007 */ +#define ETH_MACWTR_WTO_10KB (0x8UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000008 */ +#define ETH_MACWTR_WTO_11KB (0x9UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000009 */ +#define ETH_MACWTR_WTO_12KB (0xAUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000A */ +#define ETH_MACWTR_WTO_13KB (0xBUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000B */ +#define ETH_MACWTR_WTO_14KB (0xCUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000C */ +#define ETH_MACWTR_WTO_15KB (0xDUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000D */ +#define ETH_MACWTR_WTO_16KB (0xEUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000E */ #define ETH_MACWTR_PWE_Pos (8U) #define ETH_MACWTR_PWE_Msk (0x1UL << ETH_MACWTR_PWE_Pos) /*!< 0x00000100 */ #define ETH_MACWTR_PWE ETH_MACWTR_PWE_Msk /*!< Programmable Watchdog Enable */ @@ -12710,6 +12729,9 @@ typedef struct #define ETH_MACHT1R_HT63T32_31 (0x80000000UL << ETH_MACHT1R_HT63T32_Pos) /*!< 0x80000000 */ /************** Bit definition for ETH_MACVTR register ***************/ +#define ETH_MACVTR_VL_VID_Pos (0U) +#define ETH_MACVTR_VL_VID_Msk (0xFFFUL << ETH_MACVTR_VL_VID_Pos) /*!< 0x00000FFF */ +#define ETH_MACVTR_VL_VID ETH_MACVTR_VL_VID_Msk /*!< VLAN Tag Identifier field of VLAN tag */ #define ETH_MACVTR_VL_Pos (0U) #define ETH_MACVTR_VL_Msk (0xFFFFUL << ETH_MACVTR_VL_Pos) /*!< 0x0000FFFF */ #define ETH_MACVTR_VL ETH_MACVTR_VL_Msk /*!< VLAN Tag Identifier for Receive Packets */ @@ -12871,9 +12893,12 @@ typedef struct #define ETH_MACQ0TXFCR_PLT_Pos (4U) #define ETH_MACQ0TXFCR_PLT_Msk (0x7UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000070 */ #define ETH_MACQ0TXFCR_PLT ETH_MACQ0TXFCR_PLT_Msk /*!< Pause Low Threshold */ -#define ETH_MACQ0TXFCR_PLT_0 (0x1UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000010 */ -#define ETH_MACQ0TXFCR_PLT_1 (0x2UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000020 */ -#define ETH_MACQ0TXFCR_PLT_2 (0x4UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000040 */ +#define ETH_MACQ0TXFCR_PLT_MINUS4 (0x0UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000000 */ +#define ETH_MACQ0TXFCR_PLT_MINUS28 (0x1UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000010 */ +#define ETH_MACQ0TXFCR_PLT_MINUS36 (0x2UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000020 */ +#define ETH_MACQ0TXFCR_PLT_MINUS144 (0x3UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000030 */ +#define ETH_MACQ0TXFCR_PLT_MINUS256 (0x4UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000040 */ +#define ETH_MACQ0TXFCR_PLT_MINUS512 (0x5UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000050 */ #define ETH_MACQ0TXFCR_DZPQ_Pos (7U) #define ETH_MACQ0TXFCR_DZPQ_Msk (0x1UL << ETH_MACQ0TXFCR_DZPQ_Pos) /*!< 0x00000080 */ #define ETH_MACQ0TXFCR_DZPQ ETH_MACQ0TXFCR_DZPQ_Msk /*!< Disable Zero-Quanta Pause */ @@ -13440,10 +13465,12 @@ typedef struct #define ETH_MACMDIOAR_CR_Pos (8U) #define ETH_MACMDIOAR_CR_Msk (0xFUL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000F00 */ #define ETH_MACMDIOAR_CR ETH_MACMDIOAR_CR_Msk /*!< CSR Clock Range */ -#define ETH_MACMDIOAR_CR_0 (0x1UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000100 */ -#define ETH_MACMDIOAR_CR_1 (0x2UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000200 */ -#define ETH_MACMDIOAR_CR_2 (0x4UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000400 */ -#define ETH_MACMDIOAR_CR_3 (0x8UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000800 */ +#define ETH_MACMDIOAR_CR_DIV42 (0x0UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000000 */ +#define ETH_MACMDIOAR_CR_DIV62 (0x1UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000100 */ +#define ETH_MACMDIOAR_CR_DIV16 (0x2UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000200 */ +#define ETH_MACMDIOAR_CR_DIV26 (0x3UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000300 */ +#define ETH_MACMDIOAR_CR_DIV102 (0x4UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000400 */ +#define ETH_MACMDIOAR_CR_DIV124 (0x5UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000500 */ #define ETH_MACMDIOAR_NTC_Pos (12U) #define ETH_MACMDIOAR_NTC_Msk (0x7UL << ETH_MACMDIOAR_NTC_Pos) /*!< 0x00007000 */ #define ETH_MACMDIOAR_NTC ETH_MACMDIOAR_NTC_Msk /*!< Number of Training Clocks */ @@ -13882,7 +13909,7 @@ typedef struct #define ETH_MMCTXIMR_TXLPIUSCIM ETH_MMCTXIMR_TXLPIUSCIM_Msk /*!< MMC Transmit LPI microsecond counter interrupt Mask */ #define ETH_MMCTXIMR_TXLPITRCIM_Pos (27U) #define ETH_MMCTXIMR_TXLPITRCIM_Msk (0x1UL << ETH_MMCTXIMR_TXLPITRCIM_Pos) /*!< 0x08000000 */ -#define ETH_MMCTXIMR_TXLPITRCIM ETH_MMC_INTERRUPT_MASK_TXLPITRCIM_Msk /*!< MMC Transmit LPI transition counter interrupt Mask */ +#define ETH_MMCTXIMR_TXLPITRCIM ETH_MMCTXIMR_TXLPITRCIM_Msk /*!< MMC Transmit LPI transition counter interrupt Mask */ /*********** Bit definition for ETH_MMC_TX_SINGLE_COLLISION_GOOD_PACKETS register ************/ #define ETH_MMCTXSCGPR_TXSNGLCOLG_Pos (0U) @@ -16585,9 +16612,10 @@ typedef struct #define ETH_DMAC0CR_DSL_Pos (18U) #define ETH_DMAC0CR_DSL_Msk (0x7UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x001C0000 */ #define ETH_DMAC0CR_DSL ETH_DMAC0CR_DSL_Msk /*!< Descriptor Skip Length */ -#define ETH_DMAC0CR_DSL_0 (0x1UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00040000 */ -#define ETH_DMAC0CR_DSL_1 (0x2UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00080000 */ -#define ETH_DMAC0CR_DSL_2 (0x4UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00100000 */ +#define ETH_DMACCR_DSL_0BIT (0x0UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00000000 */ +#define ETH_DMACCR_DSL_32BIT (0x1UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00040000 */ +#define ETH_DMACCR_DSL_64BIT (0x2UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00080000 */ +#define ETH_DMACCR_DSL_128BIT (0x4UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00100000 */ /************* Bit definition for ETH_DMAC0TXCR register *************/ #define ETH_DMAC0TXCR_ST_Pos (0U) @@ -16608,12 +16636,12 @@ typedef struct #define ETH_DMAC0TXCR_TXPBL_Pos (16U) #define ETH_DMAC0TXCR_TXPBL_Msk (0x3FUL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x003F0000 */ #define ETH_DMAC0TXCR_TXPBL ETH_DMAC0TXCR_TXPBL_Msk /*!< Transmit Programmable Burst Length */ -#define ETH_DMAC0TXCR_TXPBL_0 (0x1UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00010000 */ -#define ETH_DMAC0TXCR_TXPBL_1 (0x2UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00020000 */ -#define ETH_DMAC0TXCR_TXPBL_2 (0x4UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00040000 */ -#define ETH_DMAC0TXCR_TXPBL_3 (0x8UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00080000 */ -#define ETH_DMAC0TXCR_TXPBL_4 (0x10UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00100000 */ -#define ETH_DMAC0TXCR_TXPBL_5 (0x20UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00200000 */ +#define ETH_DMAC0TXCR_TXPBL_1PBL (0x1UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00010000 */ +#define ETH_DMAC0TXCR_TXPBL_2PBL (0x2UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00020000 */ +#define ETH_DMAC0TXCR_TXPBL_4PBL (0x4UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00040000 */ +#define ETH_DMAC0TXCR_TXPBL_8PBL (0x8UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00080000 */ +#define ETH_DMAC0TXCR_TXPBL_16PBL (0x10UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00100000 */ +#define ETH_DMAC0TXCR_TXPBL_32PBL (0x20UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00200000 */ #define ETH_DMAC0TXCR_TQOS_Pos (24U) #define ETH_DMAC0TXCR_TQOS_Msk (0xFUL << ETH_DMAC0TXCR_TQOS_Pos) /*!< 0x0F000000 */ #define ETH_DMAC0TXCR_TQOS ETH_DMAC0TXCR_TQOS_Msk /*!< Transmit QOS. */ @@ -16646,12 +16674,12 @@ typedef struct #define ETH_DMAC0RXCR_RXPBL_Pos (16U) #define ETH_DMAC0RXCR_RXPBL_Msk (0x3FUL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x003F0000 */ #define ETH_DMAC0RXCR_RXPBL ETH_DMAC0RXCR_RXPBL_Msk /*!< Receive Programmable Burst Length */ -#define ETH_DMAC0RXCR_RXPBL_0 (0x1UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00010000 */ -#define ETH_DMAC0RXCR_RXPBL_1 (0x2UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00020000 */ -#define ETH_DMAC0RXCR_RXPBL_2 (0x4UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00040000 */ -#define ETH_DMAC0RXCR_RXPBL_3 (0x8UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00080000 */ -#define ETH_DMAC0RXCR_RXPBL_4 (0x10UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00100000 */ -#define ETH_DMAC0RXCR_RXPBL_5 (0x20UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00200000 */ +#define ETH_DMAC0RXCR_RXPBL_1PBL (0x1UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00010000 */ +#define ETH_DMAC0RXCR_RXPBL_2PBL (0x2UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00020000 */ +#define ETH_DMAC0RXCR_RXPBL_4PBL (0x4UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00040000 */ +#define ETH_DMAC0RXCR_RXPBL_8PBL (0x8UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00080000 */ +#define ETH_DMAC0RXCR_RXPBL_16PBL (0x10UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00100000 */ +#define ETH_DMAC0RXCR_RXPBL_32PBL (0x20UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00200000 */ #define ETH_DMAC0RXCR_RQOS_Pos (24U) #define ETH_DMAC0RXCR_RQOS_Msk (0xFUL << ETH_DMAC0RXCR_RQOS_Pos) /*!< 0x0F000000 */ #define ETH_DMAC0RXCR_RQOS ETH_DMAC0RXCR_RQOS_Msk /*!< Rx AXI4 QOS. */ @@ -24589,6 +24617,16 @@ typedef struct #define BSEC_HWCFGR_ECC_USE_Msk (0xFUL << BSEC_HWCFGR_ECC_USE_Pos) /*!< 0x000000F0 */ #define BSEC_HWCFGR_ECC_USE BSEC_HWCFGR_ECC_USE_Msk /*!< protection / redundancy scheme used */ +/******************** Bit definition for BSEC_JTAGIN register ********************/ +#define BSEC_JTAGIN_DATA_Pos (0U) +#define BSEC_JTAGIN_DATA_Msk (0x0000FFFFUL << BSEC_JTAGIN_DATA_Pos) /*!< JTAG Input Data */ +#define BSEC_JTAGIN_DATA BSEC_JTAGIN_DATA_Msk + +/******************** Bit definition for BSEC_JTAGOUT register ********************/ +#define BSEC_JTAGOUT_DATA_Pos (0U) +#define BSEC_JTAGOUT_DATA_Msk (0x0000FFFFUL << BSEC_JTAGOUT_DATA_Pos) /*!< JTAG Output Data */ +#define BSEC_JTAGOUT_DATA BSEC_JTAGOUT_DATA_Msk + /******************** Bit definition for BSEC_VERR register********************/ #define BSEC_VERR_MINREV_Pos (0U) #define BSEC_VERR_MINREV_Msk (0xFUL << BSEC_VERR_MINREV_Pos) /*!< 0x0000000F */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153cxx_cm4.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153cxx_cm4.h index e08d574871..981371e803 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153cxx_cm4.h +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153cxx_cm4.h @@ -12427,16 +12427,19 @@ typedef struct #define ETH_MACCR_PRELEN_Pos (2U) #define ETH_MACCR_PRELEN_Msk (0x3UL << ETH_MACCR_PRELEN_Pos) /*!< 0x0000000C */ #define ETH_MACCR_PRELEN ETH_MACCR_PRELEN_Msk /*!< Preamble Length for Transmit packets */ -#define ETH_MACCR_PRELEN_0 (0x1UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000004 */ -#define ETH_MACCR_PRELEN_1 (0x2UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000008 */ +#define ETH_MACCR_PRELEN_7 (0x0UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000000 */ +#define ETH_MACCR_PRELEN_5 (0x1UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000004 */ +#define ETH_MACCR_PRELEN_3 (0x2UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000006 */ #define ETH_MACCR_DC_Pos (4U) #define ETH_MACCR_DC_Msk (0x1UL << ETH_MACCR_DC_Pos) /*!< 0x00000010 */ #define ETH_MACCR_DC ETH_MACCR_DC_Msk /*!< Deferral Check */ #define ETH_MACCR_BL_Pos (5U) #define ETH_MACCR_BL_Msk (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */ #define ETH_MACCR_BL ETH_MACCR_BL_Msk /*!< Back-Off Limit */ -#define ETH_MACCR_BL_0 (0x1UL << ETH_MACCR_BL_Pos) /*!< 0x00000020 */ -#define ETH_MACCR_BL_1 (0x2UL << ETH_MACCR_BL_Pos) /*!< 0x00000040 */ +#define ETH_MACCR_BL_10 (0x0UL << ETH_MACCR_BL_Pos) /*!< 0x00000000 */ +#define ETH_MACCR_BL_8 (0x1UL << ETH_MACCR_BL_Pos) /*!< 0x00000020 */ +#define ETH_MACCR_BL_4 (0x2UL << ETH_MACCR_BL_Pos) /*!< 0x00000040 */ +#define ETH_MACCR_BL_1 (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */ #define ETH_MACCR_DR_Pos (8U) #define ETH_MACCR_DR_Msk (0x1UL << ETH_MACCR_DR_Pos) /*!< 0x00000100 */ #define ETH_MACCR_DR ETH_MACCR_DR_Msk /*!< Disable Retry */ @@ -12488,9 +12491,14 @@ typedef struct #define ETH_MACCR_IPG_Pos (24U) #define ETH_MACCR_IPG_Msk (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */ #define ETH_MACCR_IPG ETH_MACCR_IPG_Msk /*!< Inter-Packet Gap */ -#define ETH_MACCR_IPG_0 (0x1UL << ETH_MACCR_IPG_Pos) /*!< 0x01000000 */ -#define ETH_MACCR_IPG_1 (0x2UL << ETH_MACCR_IPG_Pos) /*!< 0x02000000 */ -#define ETH_MACCR_IPG_2 (0x4UL << ETH_MACCR_IPG_Pos) /*!< 0x04000000 */ +#define ETH_MACCR_IPG_96BIT (0x0UL << ETH_MACCR_IPG_Pos) /*!< 0x00000000 */ +#define ETH_MACCR_IPG_88BIT (0x1UL << ETH_MACCR_IPG_Pos) /*!< 0x01000000 */ +#define ETH_MACCR_IPG_80BIT (0x2UL << ETH_MACCR_IPG_Pos) /*!< 0x02000000 */ +#define ETH_MACCR_IPG_72BIT (0x3UL << ETH_MACCR_IPG_Pos) /*!< 0x03000000 */ +#define ETH_MACCR_IPG_64BIT (0x4UL << ETH_MACCR_IPG_Pos) /*!< 0x04000000 */ +#define ETH_MACCR_IPG_56BIT (0x5UL << ETH_MACCR_IPG_Pos) /*!< 0x05000000 */ +#define ETH_MACCR_IPG_48BIT (0x6UL << ETH_MACCR_IPG_Pos) /*!< 0x06000000 */ +#define ETH_MACCR_IPG_40BIT (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */ #define ETH_MACCR_IPC_Pos (27U) #define ETH_MACCR_IPC_Msk (0x1UL << ETH_MACCR_IPC_Pos) /*!< 0x08000000 */ #define ETH_MACCR_IPC ETH_MACCR_IPC_Msk /*!< Checksum Offload */ @@ -12593,10 +12601,21 @@ typedef struct #define ETH_MACWTR_WTO_Pos (0U) #define ETH_MACWTR_WTO_Msk (0xFUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000F */ #define ETH_MACWTR_WTO ETH_MACWTR_WTO_Msk /*!< Watchdog Timeout */ -#define ETH_MACWTR_WTO_0 (0x1UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000001 */ -#define ETH_MACWTR_WTO_1 (0x2UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000002 */ -#define ETH_MACWTR_WTO_2 (0x4UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000004 */ -#define ETH_MACWTR_WTO_3 (0x8UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000008 */ +#define ETH_MACWTR_WTO_2KB (0x0UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000001 */ +#define ETH_MACWTR_WTO_3KB (0x1UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000001 */ +#define ETH_MACWTR_WTO_4KB (0x2UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000002 */ +#define ETH_MACWTR_WTO_5KB (0x3UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000003 */ +#define ETH_MACWTR_WTO_6KB (0x4UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000004 */ +#define ETH_MACWTR_WTO_7KB (0x5UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000005 */ +#define ETH_MACWTR_WTO_8KB (0x6UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000006 */ +#define ETH_MACWTR_WTO_9KB (0x7UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000007 */ +#define ETH_MACWTR_WTO_10KB (0x8UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000008 */ +#define ETH_MACWTR_WTO_11KB (0x9UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000009 */ +#define ETH_MACWTR_WTO_12KB (0xAUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000A */ +#define ETH_MACWTR_WTO_13KB (0xBUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000B */ +#define ETH_MACWTR_WTO_14KB (0xCUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000C */ +#define ETH_MACWTR_WTO_15KB (0xDUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000D */ +#define ETH_MACWTR_WTO_16KB (0xEUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000E */ #define ETH_MACWTR_PWE_Pos (8U) #define ETH_MACWTR_PWE_Msk (0x1UL << ETH_MACWTR_PWE_Pos) /*!< 0x00000100 */ #define ETH_MACWTR_PWE ETH_MACWTR_PWE_Msk /*!< Programmable Watchdog Enable */ @@ -12676,6 +12695,9 @@ typedef struct #define ETH_MACHT1R_HT63T32_31 (0x80000000UL << ETH_MACHT1R_HT63T32_Pos) /*!< 0x80000000 */ /************** Bit definition for ETH_MACVTR register ***************/ +#define ETH_MACVTR_VL_VID_Pos (0U) +#define ETH_MACVTR_VL_VID_Msk (0xFFFUL << ETH_MACVTR_VL_VID_Pos) /*!< 0x00000FFF */ +#define ETH_MACVTR_VL_VID ETH_MACVTR_VL_VID_Msk /*!< VLAN Tag Identifier field of VLAN tag */ #define ETH_MACVTR_VL_Pos (0U) #define ETH_MACVTR_VL_Msk (0xFFFFUL << ETH_MACVTR_VL_Pos) /*!< 0x0000FFFF */ #define ETH_MACVTR_VL ETH_MACVTR_VL_Msk /*!< VLAN Tag Identifier for Receive Packets */ @@ -12837,9 +12859,12 @@ typedef struct #define ETH_MACQ0TXFCR_PLT_Pos (4U) #define ETH_MACQ0TXFCR_PLT_Msk (0x7UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000070 */ #define ETH_MACQ0TXFCR_PLT ETH_MACQ0TXFCR_PLT_Msk /*!< Pause Low Threshold */ -#define ETH_MACQ0TXFCR_PLT_0 (0x1UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000010 */ -#define ETH_MACQ0TXFCR_PLT_1 (0x2UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000020 */ -#define ETH_MACQ0TXFCR_PLT_2 (0x4UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000040 */ +#define ETH_MACQ0TXFCR_PLT_MINUS4 (0x0UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000000 */ +#define ETH_MACQ0TXFCR_PLT_MINUS28 (0x1UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000010 */ +#define ETH_MACQ0TXFCR_PLT_MINUS36 (0x2UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000020 */ +#define ETH_MACQ0TXFCR_PLT_MINUS144 (0x3UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000030 */ +#define ETH_MACQ0TXFCR_PLT_MINUS256 (0x4UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000040 */ +#define ETH_MACQ0TXFCR_PLT_MINUS512 (0x5UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000050 */ #define ETH_MACQ0TXFCR_DZPQ_Pos (7U) #define ETH_MACQ0TXFCR_DZPQ_Msk (0x1UL << ETH_MACQ0TXFCR_DZPQ_Pos) /*!< 0x00000080 */ #define ETH_MACQ0TXFCR_DZPQ ETH_MACQ0TXFCR_DZPQ_Msk /*!< Disable Zero-Quanta Pause */ @@ -13406,10 +13431,12 @@ typedef struct #define ETH_MACMDIOAR_CR_Pos (8U) #define ETH_MACMDIOAR_CR_Msk (0xFUL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000F00 */ #define ETH_MACMDIOAR_CR ETH_MACMDIOAR_CR_Msk /*!< CSR Clock Range */ -#define ETH_MACMDIOAR_CR_0 (0x1UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000100 */ -#define ETH_MACMDIOAR_CR_1 (0x2UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000200 */ -#define ETH_MACMDIOAR_CR_2 (0x4UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000400 */ -#define ETH_MACMDIOAR_CR_3 (0x8UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000800 */ +#define ETH_MACMDIOAR_CR_DIV42 (0x0UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000000 */ +#define ETH_MACMDIOAR_CR_DIV62 (0x1UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000100 */ +#define ETH_MACMDIOAR_CR_DIV16 (0x2UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000200 */ +#define ETH_MACMDIOAR_CR_DIV26 (0x3UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000300 */ +#define ETH_MACMDIOAR_CR_DIV102 (0x4UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000400 */ +#define ETH_MACMDIOAR_CR_DIV124 (0x5UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000500 */ #define ETH_MACMDIOAR_NTC_Pos (12U) #define ETH_MACMDIOAR_NTC_Msk (0x7UL << ETH_MACMDIOAR_NTC_Pos) /*!< 0x00007000 */ #define ETH_MACMDIOAR_NTC ETH_MACMDIOAR_NTC_Msk /*!< Number of Training Clocks */ @@ -13848,7 +13875,7 @@ typedef struct #define ETH_MMCTXIMR_TXLPIUSCIM ETH_MMCTXIMR_TXLPIUSCIM_Msk /*!< MMC Transmit LPI microsecond counter interrupt Mask */ #define ETH_MMCTXIMR_TXLPITRCIM_Pos (27U) #define ETH_MMCTXIMR_TXLPITRCIM_Msk (0x1UL << ETH_MMCTXIMR_TXLPITRCIM_Pos) /*!< 0x08000000 */ -#define ETH_MMCTXIMR_TXLPITRCIM ETH_MMC_INTERRUPT_MASK_TXLPITRCIM_Msk /*!< MMC Transmit LPI transition counter interrupt Mask */ +#define ETH_MMCTXIMR_TXLPITRCIM ETH_MMCTXIMR_TXLPITRCIM_Msk /*!< MMC Transmit LPI transition counter interrupt Mask */ /*********** Bit definition for ETH_MMC_TX_SINGLE_COLLISION_GOOD_PACKETS register ************/ #define ETH_MMCTXSCGPR_TXSNGLCOLG_Pos (0U) @@ -16551,9 +16578,10 @@ typedef struct #define ETH_DMAC0CR_DSL_Pos (18U) #define ETH_DMAC0CR_DSL_Msk (0x7UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x001C0000 */ #define ETH_DMAC0CR_DSL ETH_DMAC0CR_DSL_Msk /*!< Descriptor Skip Length */ -#define ETH_DMAC0CR_DSL_0 (0x1UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00040000 */ -#define ETH_DMAC0CR_DSL_1 (0x2UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00080000 */ -#define ETH_DMAC0CR_DSL_2 (0x4UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00100000 */ +#define ETH_DMACCR_DSL_0BIT (0x0UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00000000 */ +#define ETH_DMACCR_DSL_32BIT (0x1UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00040000 */ +#define ETH_DMACCR_DSL_64BIT (0x2UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00080000 */ +#define ETH_DMACCR_DSL_128BIT (0x4UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00100000 */ /************* Bit definition for ETH_DMAC0TXCR register *************/ #define ETH_DMAC0TXCR_ST_Pos (0U) @@ -16574,12 +16602,12 @@ typedef struct #define ETH_DMAC0TXCR_TXPBL_Pos (16U) #define ETH_DMAC0TXCR_TXPBL_Msk (0x3FUL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x003F0000 */ #define ETH_DMAC0TXCR_TXPBL ETH_DMAC0TXCR_TXPBL_Msk /*!< Transmit Programmable Burst Length */ -#define ETH_DMAC0TXCR_TXPBL_0 (0x1UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00010000 */ -#define ETH_DMAC0TXCR_TXPBL_1 (0x2UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00020000 */ -#define ETH_DMAC0TXCR_TXPBL_2 (0x4UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00040000 */ -#define ETH_DMAC0TXCR_TXPBL_3 (0x8UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00080000 */ -#define ETH_DMAC0TXCR_TXPBL_4 (0x10UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00100000 */ -#define ETH_DMAC0TXCR_TXPBL_5 (0x20UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00200000 */ +#define ETH_DMAC0TXCR_TXPBL_1PBL (0x1UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00010000 */ +#define ETH_DMAC0TXCR_TXPBL_2PBL (0x2UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00020000 */ +#define ETH_DMAC0TXCR_TXPBL_4PBL (0x4UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00040000 */ +#define ETH_DMAC0TXCR_TXPBL_8PBL (0x8UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00080000 */ +#define ETH_DMAC0TXCR_TXPBL_16PBL (0x10UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00100000 */ +#define ETH_DMAC0TXCR_TXPBL_32PBL (0x20UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00200000 */ #define ETH_DMAC0TXCR_TQOS_Pos (24U) #define ETH_DMAC0TXCR_TQOS_Msk (0xFUL << ETH_DMAC0TXCR_TQOS_Pos) /*!< 0x0F000000 */ #define ETH_DMAC0TXCR_TQOS ETH_DMAC0TXCR_TQOS_Msk /*!< Transmit QOS. */ @@ -16612,12 +16640,12 @@ typedef struct #define ETH_DMAC0RXCR_RXPBL_Pos (16U) #define ETH_DMAC0RXCR_RXPBL_Msk (0x3FUL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x003F0000 */ #define ETH_DMAC0RXCR_RXPBL ETH_DMAC0RXCR_RXPBL_Msk /*!< Receive Programmable Burst Length */ -#define ETH_DMAC0RXCR_RXPBL_0 (0x1UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00010000 */ -#define ETH_DMAC0RXCR_RXPBL_1 (0x2UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00020000 */ -#define ETH_DMAC0RXCR_RXPBL_2 (0x4UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00040000 */ -#define ETH_DMAC0RXCR_RXPBL_3 (0x8UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00080000 */ -#define ETH_DMAC0RXCR_RXPBL_4 (0x10UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00100000 */ -#define ETH_DMAC0RXCR_RXPBL_5 (0x20UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00200000 */ +#define ETH_DMAC0RXCR_RXPBL_1PBL (0x1UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00010000 */ +#define ETH_DMAC0RXCR_RXPBL_2PBL (0x2UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00020000 */ +#define ETH_DMAC0RXCR_RXPBL_4PBL (0x4UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00040000 */ +#define ETH_DMAC0RXCR_RXPBL_8PBL (0x8UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00080000 */ +#define ETH_DMAC0RXCR_RXPBL_16PBL (0x10UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00100000 */ +#define ETH_DMAC0RXCR_RXPBL_32PBL (0x20UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00200000 */ #define ETH_DMAC0RXCR_RQOS_Pos (24U) #define ETH_DMAC0RXCR_RQOS_Msk (0xFUL << ETH_DMAC0RXCR_RQOS_Pos) /*!< 0x0F000000 */ #define ETH_DMAC0RXCR_RQOS ETH_DMAC0RXCR_RQOS_Msk /*!< Rx AXI4 QOS. */ @@ -24555,6 +24583,16 @@ typedef struct #define BSEC_HWCFGR_ECC_USE_Msk (0xFUL << BSEC_HWCFGR_ECC_USE_Pos) /*!< 0x000000F0 */ #define BSEC_HWCFGR_ECC_USE BSEC_HWCFGR_ECC_USE_Msk /*!< protection / redundancy scheme used */ +/******************** Bit definition for BSEC_JTAGIN register ********************/ +#define BSEC_JTAGIN_DATA_Pos (0U) +#define BSEC_JTAGIN_DATA_Msk (0x0000FFFFUL << BSEC_JTAGIN_DATA_Pos) /*!< JTAG Input Data */ +#define BSEC_JTAGIN_DATA BSEC_JTAGIN_DATA_Msk + +/******************** Bit definition for BSEC_JTAGOUT register ********************/ +#define BSEC_JTAGOUT_DATA_Pos (0U) +#define BSEC_JTAGOUT_DATA_Msk (0x0000FFFFUL << BSEC_JTAGOUT_DATA_Pos) /*!< JTAG Output Data */ +#define BSEC_JTAGOUT_DATA BSEC_JTAGOUT_DATA_Msk + /******************** Bit definition for BSEC_VERR register********************/ #define BSEC_VERR_MINREV_Pos (0U) #define BSEC_VERR_MINREV_Msk (0xFUL << BSEC_VERR_MINREV_Pos) /*!< 0x0000000F */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153dxx_ca7.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153dxx_ca7.h index 4991cd1f7b..7b02d32155 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153dxx_ca7.h +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153dxx_ca7.h @@ -12264,16 +12264,19 @@ typedef struct #define ETH_MACCR_PRELEN_Pos (2U) #define ETH_MACCR_PRELEN_Msk (0x3UL << ETH_MACCR_PRELEN_Pos) /*!< 0x0000000C */ #define ETH_MACCR_PRELEN ETH_MACCR_PRELEN_Msk /*!< Preamble Length for Transmit packets */ -#define ETH_MACCR_PRELEN_0 (0x1UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000004 */ -#define ETH_MACCR_PRELEN_1 (0x2UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000008 */ +#define ETH_MACCR_PRELEN_7 (0x0UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000000 */ +#define ETH_MACCR_PRELEN_5 (0x1UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000004 */ +#define ETH_MACCR_PRELEN_3 (0x2UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000006 */ #define ETH_MACCR_DC_Pos (4U) #define ETH_MACCR_DC_Msk (0x1UL << ETH_MACCR_DC_Pos) /*!< 0x00000010 */ #define ETH_MACCR_DC ETH_MACCR_DC_Msk /*!< Deferral Check */ #define ETH_MACCR_BL_Pos (5U) #define ETH_MACCR_BL_Msk (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */ #define ETH_MACCR_BL ETH_MACCR_BL_Msk /*!< Back-Off Limit */ -#define ETH_MACCR_BL_0 (0x1UL << ETH_MACCR_BL_Pos) /*!< 0x00000020 */ -#define ETH_MACCR_BL_1 (0x2UL << ETH_MACCR_BL_Pos) /*!< 0x00000040 */ +#define ETH_MACCR_BL_10 (0x0UL << ETH_MACCR_BL_Pos) /*!< 0x00000000 */ +#define ETH_MACCR_BL_8 (0x1UL << ETH_MACCR_BL_Pos) /*!< 0x00000020 */ +#define ETH_MACCR_BL_4 (0x2UL << ETH_MACCR_BL_Pos) /*!< 0x00000040 */ +#define ETH_MACCR_BL_1 (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */ #define ETH_MACCR_DR_Pos (8U) #define ETH_MACCR_DR_Msk (0x1UL << ETH_MACCR_DR_Pos) /*!< 0x00000100 */ #define ETH_MACCR_DR ETH_MACCR_DR_Msk /*!< Disable Retry */ @@ -12325,9 +12328,14 @@ typedef struct #define ETH_MACCR_IPG_Pos (24U) #define ETH_MACCR_IPG_Msk (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */ #define ETH_MACCR_IPG ETH_MACCR_IPG_Msk /*!< Inter-Packet Gap */ -#define ETH_MACCR_IPG_0 (0x1UL << ETH_MACCR_IPG_Pos) /*!< 0x01000000 */ -#define ETH_MACCR_IPG_1 (0x2UL << ETH_MACCR_IPG_Pos) /*!< 0x02000000 */ -#define ETH_MACCR_IPG_2 (0x4UL << ETH_MACCR_IPG_Pos) /*!< 0x04000000 */ +#define ETH_MACCR_IPG_96BIT (0x0UL << ETH_MACCR_IPG_Pos) /*!< 0x00000000 */ +#define ETH_MACCR_IPG_88BIT (0x1UL << ETH_MACCR_IPG_Pos) /*!< 0x01000000 */ +#define ETH_MACCR_IPG_80BIT (0x2UL << ETH_MACCR_IPG_Pos) /*!< 0x02000000 */ +#define ETH_MACCR_IPG_72BIT (0x3UL << ETH_MACCR_IPG_Pos) /*!< 0x03000000 */ +#define ETH_MACCR_IPG_64BIT (0x4UL << ETH_MACCR_IPG_Pos) /*!< 0x04000000 */ +#define ETH_MACCR_IPG_56BIT (0x5UL << ETH_MACCR_IPG_Pos) /*!< 0x05000000 */ +#define ETH_MACCR_IPG_48BIT (0x6UL << ETH_MACCR_IPG_Pos) /*!< 0x06000000 */ +#define ETH_MACCR_IPG_40BIT (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */ #define ETH_MACCR_IPC_Pos (27U) #define ETH_MACCR_IPC_Msk (0x1UL << ETH_MACCR_IPC_Pos) /*!< 0x08000000 */ #define ETH_MACCR_IPC ETH_MACCR_IPC_Msk /*!< Checksum Offload */ @@ -12430,10 +12438,21 @@ typedef struct #define ETH_MACWTR_WTO_Pos (0U) #define ETH_MACWTR_WTO_Msk (0xFUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000F */ #define ETH_MACWTR_WTO ETH_MACWTR_WTO_Msk /*!< Watchdog Timeout */ -#define ETH_MACWTR_WTO_0 (0x1UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000001 */ -#define ETH_MACWTR_WTO_1 (0x2UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000002 */ -#define ETH_MACWTR_WTO_2 (0x4UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000004 */ -#define ETH_MACWTR_WTO_3 (0x8UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000008 */ +#define ETH_MACWTR_WTO_2KB (0x0UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000001 */ +#define ETH_MACWTR_WTO_3KB (0x1UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000001 */ +#define ETH_MACWTR_WTO_4KB (0x2UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000002 */ +#define ETH_MACWTR_WTO_5KB (0x3UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000003 */ +#define ETH_MACWTR_WTO_6KB (0x4UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000004 */ +#define ETH_MACWTR_WTO_7KB (0x5UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000005 */ +#define ETH_MACWTR_WTO_8KB (0x6UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000006 */ +#define ETH_MACWTR_WTO_9KB (0x7UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000007 */ +#define ETH_MACWTR_WTO_10KB (0x8UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000008 */ +#define ETH_MACWTR_WTO_11KB (0x9UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000009 */ +#define ETH_MACWTR_WTO_12KB (0xAUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000A */ +#define ETH_MACWTR_WTO_13KB (0xBUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000B */ +#define ETH_MACWTR_WTO_14KB (0xCUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000C */ +#define ETH_MACWTR_WTO_15KB (0xDUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000D */ +#define ETH_MACWTR_WTO_16KB (0xEUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000E */ #define ETH_MACWTR_PWE_Pos (8U) #define ETH_MACWTR_PWE_Msk (0x1UL << ETH_MACWTR_PWE_Pos) /*!< 0x00000100 */ #define ETH_MACWTR_PWE ETH_MACWTR_PWE_Msk /*!< Programmable Watchdog Enable */ @@ -12513,6 +12532,9 @@ typedef struct #define ETH_MACHT1R_HT63T32_31 (0x80000000UL << ETH_MACHT1R_HT63T32_Pos) /*!< 0x80000000 */ /************** Bit definition for ETH_MACVTR register ***************/ +#define ETH_MACVTR_VL_VID_Pos (0U) +#define ETH_MACVTR_VL_VID_Msk (0xFFFUL << ETH_MACVTR_VL_VID_Pos) /*!< 0x00000FFF */ +#define ETH_MACVTR_VL_VID ETH_MACVTR_VL_VID_Msk /*!< VLAN Tag Identifier field of VLAN tag */ #define ETH_MACVTR_VL_Pos (0U) #define ETH_MACVTR_VL_Msk (0xFFFFUL << ETH_MACVTR_VL_Pos) /*!< 0x0000FFFF */ #define ETH_MACVTR_VL ETH_MACVTR_VL_Msk /*!< VLAN Tag Identifier for Receive Packets */ @@ -12674,9 +12696,12 @@ typedef struct #define ETH_MACQ0TXFCR_PLT_Pos (4U) #define ETH_MACQ0TXFCR_PLT_Msk (0x7UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000070 */ #define ETH_MACQ0TXFCR_PLT ETH_MACQ0TXFCR_PLT_Msk /*!< Pause Low Threshold */ -#define ETH_MACQ0TXFCR_PLT_0 (0x1UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000010 */ -#define ETH_MACQ0TXFCR_PLT_1 (0x2UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000020 */ -#define ETH_MACQ0TXFCR_PLT_2 (0x4UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000040 */ +#define ETH_MACQ0TXFCR_PLT_MINUS4 (0x0UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000000 */ +#define ETH_MACQ0TXFCR_PLT_MINUS28 (0x1UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000010 */ +#define ETH_MACQ0TXFCR_PLT_MINUS36 (0x2UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000020 */ +#define ETH_MACQ0TXFCR_PLT_MINUS144 (0x3UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000030 */ +#define ETH_MACQ0TXFCR_PLT_MINUS256 (0x4UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000040 */ +#define ETH_MACQ0TXFCR_PLT_MINUS512 (0x5UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000050 */ #define ETH_MACQ0TXFCR_DZPQ_Pos (7U) #define ETH_MACQ0TXFCR_DZPQ_Msk (0x1UL << ETH_MACQ0TXFCR_DZPQ_Pos) /*!< 0x00000080 */ #define ETH_MACQ0TXFCR_DZPQ ETH_MACQ0TXFCR_DZPQ_Msk /*!< Disable Zero-Quanta Pause */ @@ -13243,10 +13268,12 @@ typedef struct #define ETH_MACMDIOAR_CR_Pos (8U) #define ETH_MACMDIOAR_CR_Msk (0xFUL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000F00 */ #define ETH_MACMDIOAR_CR ETH_MACMDIOAR_CR_Msk /*!< CSR Clock Range */ -#define ETH_MACMDIOAR_CR_0 (0x1UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000100 */ -#define ETH_MACMDIOAR_CR_1 (0x2UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000200 */ -#define ETH_MACMDIOAR_CR_2 (0x4UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000400 */ -#define ETH_MACMDIOAR_CR_3 (0x8UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000800 */ +#define ETH_MACMDIOAR_CR_DIV42 (0x0UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000000 */ +#define ETH_MACMDIOAR_CR_DIV62 (0x1UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000100 */ +#define ETH_MACMDIOAR_CR_DIV16 (0x2UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000200 */ +#define ETH_MACMDIOAR_CR_DIV26 (0x3UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000300 */ +#define ETH_MACMDIOAR_CR_DIV102 (0x4UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000400 */ +#define ETH_MACMDIOAR_CR_DIV124 (0x5UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000500 */ #define ETH_MACMDIOAR_NTC_Pos (12U) #define ETH_MACMDIOAR_NTC_Msk (0x7UL << ETH_MACMDIOAR_NTC_Pos) /*!< 0x00007000 */ #define ETH_MACMDIOAR_NTC ETH_MACMDIOAR_NTC_Msk /*!< Number of Training Clocks */ @@ -13685,7 +13712,7 @@ typedef struct #define ETH_MMCTXIMR_TXLPIUSCIM ETH_MMCTXIMR_TXLPIUSCIM_Msk /*!< MMC Transmit LPI microsecond counter interrupt Mask */ #define ETH_MMCTXIMR_TXLPITRCIM_Pos (27U) #define ETH_MMCTXIMR_TXLPITRCIM_Msk (0x1UL << ETH_MMCTXIMR_TXLPITRCIM_Pos) /*!< 0x08000000 */ -#define ETH_MMCTXIMR_TXLPITRCIM ETH_MMC_INTERRUPT_MASK_TXLPITRCIM_Msk /*!< MMC Transmit LPI transition counter interrupt Mask */ +#define ETH_MMCTXIMR_TXLPITRCIM ETH_MMCTXIMR_TXLPITRCIM_Msk /*!< MMC Transmit LPI transition counter interrupt Mask */ /*********** Bit definition for ETH_MMC_TX_SINGLE_COLLISION_GOOD_PACKETS register ************/ #define ETH_MMCTXSCGPR_TXSNGLCOLG_Pos (0U) @@ -16388,9 +16415,10 @@ typedef struct #define ETH_DMAC0CR_DSL_Pos (18U) #define ETH_DMAC0CR_DSL_Msk (0x7UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x001C0000 */ #define ETH_DMAC0CR_DSL ETH_DMAC0CR_DSL_Msk /*!< Descriptor Skip Length */ -#define ETH_DMAC0CR_DSL_0 (0x1UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00040000 */ -#define ETH_DMAC0CR_DSL_1 (0x2UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00080000 */ -#define ETH_DMAC0CR_DSL_2 (0x4UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00100000 */ +#define ETH_DMACCR_DSL_0BIT (0x0UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00000000 */ +#define ETH_DMACCR_DSL_32BIT (0x1UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00040000 */ +#define ETH_DMACCR_DSL_64BIT (0x2UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00080000 */ +#define ETH_DMACCR_DSL_128BIT (0x4UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00100000 */ /************* Bit definition for ETH_DMAC0TXCR register *************/ #define ETH_DMAC0TXCR_ST_Pos (0U) @@ -16411,12 +16439,12 @@ typedef struct #define ETH_DMAC0TXCR_TXPBL_Pos (16U) #define ETH_DMAC0TXCR_TXPBL_Msk (0x3FUL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x003F0000 */ #define ETH_DMAC0TXCR_TXPBL ETH_DMAC0TXCR_TXPBL_Msk /*!< Transmit Programmable Burst Length */ -#define ETH_DMAC0TXCR_TXPBL_0 (0x1UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00010000 */ -#define ETH_DMAC0TXCR_TXPBL_1 (0x2UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00020000 */ -#define ETH_DMAC0TXCR_TXPBL_2 (0x4UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00040000 */ -#define ETH_DMAC0TXCR_TXPBL_3 (0x8UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00080000 */ -#define ETH_DMAC0TXCR_TXPBL_4 (0x10UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00100000 */ -#define ETH_DMAC0TXCR_TXPBL_5 (0x20UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00200000 */ +#define ETH_DMAC0TXCR_TXPBL_1PBL (0x1UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00010000 */ +#define ETH_DMAC0TXCR_TXPBL_2PBL (0x2UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00020000 */ +#define ETH_DMAC0TXCR_TXPBL_4PBL (0x4UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00040000 */ +#define ETH_DMAC0TXCR_TXPBL_8PBL (0x8UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00080000 */ +#define ETH_DMAC0TXCR_TXPBL_16PBL (0x10UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00100000 */ +#define ETH_DMAC0TXCR_TXPBL_32PBL (0x20UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00200000 */ #define ETH_DMAC0TXCR_TQOS_Pos (24U) #define ETH_DMAC0TXCR_TQOS_Msk (0xFUL << ETH_DMAC0TXCR_TQOS_Pos) /*!< 0x0F000000 */ #define ETH_DMAC0TXCR_TQOS ETH_DMAC0TXCR_TQOS_Msk /*!< Transmit QOS. */ @@ -16449,12 +16477,12 @@ typedef struct #define ETH_DMAC0RXCR_RXPBL_Pos (16U) #define ETH_DMAC0RXCR_RXPBL_Msk (0x3FUL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x003F0000 */ #define ETH_DMAC0RXCR_RXPBL ETH_DMAC0RXCR_RXPBL_Msk /*!< Receive Programmable Burst Length */ -#define ETH_DMAC0RXCR_RXPBL_0 (0x1UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00010000 */ -#define ETH_DMAC0RXCR_RXPBL_1 (0x2UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00020000 */ -#define ETH_DMAC0RXCR_RXPBL_2 (0x4UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00040000 */ -#define ETH_DMAC0RXCR_RXPBL_3 (0x8UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00080000 */ -#define ETH_DMAC0RXCR_RXPBL_4 (0x10UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00100000 */ -#define ETH_DMAC0RXCR_RXPBL_5 (0x20UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00200000 */ +#define ETH_DMAC0RXCR_RXPBL_1PBL (0x1UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00010000 */ +#define ETH_DMAC0RXCR_RXPBL_2PBL (0x2UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00020000 */ +#define ETH_DMAC0RXCR_RXPBL_4PBL (0x4UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00040000 */ +#define ETH_DMAC0RXCR_RXPBL_8PBL (0x8UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00080000 */ +#define ETH_DMAC0RXCR_RXPBL_16PBL (0x10UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00100000 */ +#define ETH_DMAC0RXCR_RXPBL_32PBL (0x20UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00200000 */ #define ETH_DMAC0RXCR_RQOS_Pos (24U) #define ETH_DMAC0RXCR_RQOS_Msk (0xFUL << ETH_DMAC0RXCR_RQOS_Pos) /*!< 0x0F000000 */ #define ETH_DMAC0RXCR_RQOS ETH_DMAC0RXCR_RQOS_Msk /*!< Rx AXI4 QOS. */ @@ -24392,6 +24420,16 @@ typedef struct #define BSEC_HWCFGR_ECC_USE_Msk (0xFUL << BSEC_HWCFGR_ECC_USE_Pos) /*!< 0x000000F0 */ #define BSEC_HWCFGR_ECC_USE BSEC_HWCFGR_ECC_USE_Msk /*!< protection / redundancy scheme used */ +/******************** Bit definition for BSEC_JTAGIN register ********************/ +#define BSEC_JTAGIN_DATA_Pos (0U) +#define BSEC_JTAGIN_DATA_Msk (0x0000FFFFUL << BSEC_JTAGIN_DATA_Pos) /*!< JTAG Input Data */ +#define BSEC_JTAGIN_DATA BSEC_JTAGIN_DATA_Msk + +/******************** Bit definition for BSEC_JTAGOUT register ********************/ +#define BSEC_JTAGOUT_DATA_Pos (0U) +#define BSEC_JTAGOUT_DATA_Msk (0x0000FFFFUL << BSEC_JTAGOUT_DATA_Pos) /*!< JTAG Output Data */ +#define BSEC_JTAGOUT_DATA BSEC_JTAGOUT_DATA_Msk + /******************** Bit definition for BSEC_VERR register********************/ #define BSEC_VERR_MINREV_Pos (0U) #define BSEC_VERR_MINREV_Msk (0xFUL << BSEC_VERR_MINREV_Pos) /*!< 0x0000000F */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153dxx_cm4.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153dxx_cm4.h index 5ae2999ab8..5253c4e723 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153dxx_cm4.h +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153dxx_cm4.h @@ -12230,16 +12230,19 @@ typedef struct #define ETH_MACCR_PRELEN_Pos (2U) #define ETH_MACCR_PRELEN_Msk (0x3UL << ETH_MACCR_PRELEN_Pos) /*!< 0x0000000C */ #define ETH_MACCR_PRELEN ETH_MACCR_PRELEN_Msk /*!< Preamble Length for Transmit packets */ -#define ETH_MACCR_PRELEN_0 (0x1UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000004 */ -#define ETH_MACCR_PRELEN_1 (0x2UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000008 */ +#define ETH_MACCR_PRELEN_7 (0x0UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000000 */ +#define ETH_MACCR_PRELEN_5 (0x1UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000004 */ +#define ETH_MACCR_PRELEN_3 (0x2UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000006 */ #define ETH_MACCR_DC_Pos (4U) #define ETH_MACCR_DC_Msk (0x1UL << ETH_MACCR_DC_Pos) /*!< 0x00000010 */ #define ETH_MACCR_DC ETH_MACCR_DC_Msk /*!< Deferral Check */ #define ETH_MACCR_BL_Pos (5U) #define ETH_MACCR_BL_Msk (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */ #define ETH_MACCR_BL ETH_MACCR_BL_Msk /*!< Back-Off Limit */ -#define ETH_MACCR_BL_0 (0x1UL << ETH_MACCR_BL_Pos) /*!< 0x00000020 */ -#define ETH_MACCR_BL_1 (0x2UL << ETH_MACCR_BL_Pos) /*!< 0x00000040 */ +#define ETH_MACCR_BL_10 (0x0UL << ETH_MACCR_BL_Pos) /*!< 0x00000000 */ +#define ETH_MACCR_BL_8 (0x1UL << ETH_MACCR_BL_Pos) /*!< 0x00000020 */ +#define ETH_MACCR_BL_4 (0x2UL << ETH_MACCR_BL_Pos) /*!< 0x00000040 */ +#define ETH_MACCR_BL_1 (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */ #define ETH_MACCR_DR_Pos (8U) #define ETH_MACCR_DR_Msk (0x1UL << ETH_MACCR_DR_Pos) /*!< 0x00000100 */ #define ETH_MACCR_DR ETH_MACCR_DR_Msk /*!< Disable Retry */ @@ -12291,9 +12294,14 @@ typedef struct #define ETH_MACCR_IPG_Pos (24U) #define ETH_MACCR_IPG_Msk (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */ #define ETH_MACCR_IPG ETH_MACCR_IPG_Msk /*!< Inter-Packet Gap */ -#define ETH_MACCR_IPG_0 (0x1UL << ETH_MACCR_IPG_Pos) /*!< 0x01000000 */ -#define ETH_MACCR_IPG_1 (0x2UL << ETH_MACCR_IPG_Pos) /*!< 0x02000000 */ -#define ETH_MACCR_IPG_2 (0x4UL << ETH_MACCR_IPG_Pos) /*!< 0x04000000 */ +#define ETH_MACCR_IPG_96BIT (0x0UL << ETH_MACCR_IPG_Pos) /*!< 0x00000000 */ +#define ETH_MACCR_IPG_88BIT (0x1UL << ETH_MACCR_IPG_Pos) /*!< 0x01000000 */ +#define ETH_MACCR_IPG_80BIT (0x2UL << ETH_MACCR_IPG_Pos) /*!< 0x02000000 */ +#define ETH_MACCR_IPG_72BIT (0x3UL << ETH_MACCR_IPG_Pos) /*!< 0x03000000 */ +#define ETH_MACCR_IPG_64BIT (0x4UL << ETH_MACCR_IPG_Pos) /*!< 0x04000000 */ +#define ETH_MACCR_IPG_56BIT (0x5UL << ETH_MACCR_IPG_Pos) /*!< 0x05000000 */ +#define ETH_MACCR_IPG_48BIT (0x6UL << ETH_MACCR_IPG_Pos) /*!< 0x06000000 */ +#define ETH_MACCR_IPG_40BIT (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */ #define ETH_MACCR_IPC_Pos (27U) #define ETH_MACCR_IPC_Msk (0x1UL << ETH_MACCR_IPC_Pos) /*!< 0x08000000 */ #define ETH_MACCR_IPC ETH_MACCR_IPC_Msk /*!< Checksum Offload */ @@ -12396,10 +12404,21 @@ typedef struct #define ETH_MACWTR_WTO_Pos (0U) #define ETH_MACWTR_WTO_Msk (0xFUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000F */ #define ETH_MACWTR_WTO ETH_MACWTR_WTO_Msk /*!< Watchdog Timeout */ -#define ETH_MACWTR_WTO_0 (0x1UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000001 */ -#define ETH_MACWTR_WTO_1 (0x2UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000002 */ -#define ETH_MACWTR_WTO_2 (0x4UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000004 */ -#define ETH_MACWTR_WTO_3 (0x8UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000008 */ +#define ETH_MACWTR_WTO_2KB (0x0UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000001 */ +#define ETH_MACWTR_WTO_3KB (0x1UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000001 */ +#define ETH_MACWTR_WTO_4KB (0x2UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000002 */ +#define ETH_MACWTR_WTO_5KB (0x3UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000003 */ +#define ETH_MACWTR_WTO_6KB (0x4UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000004 */ +#define ETH_MACWTR_WTO_7KB (0x5UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000005 */ +#define ETH_MACWTR_WTO_8KB (0x6UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000006 */ +#define ETH_MACWTR_WTO_9KB (0x7UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000007 */ +#define ETH_MACWTR_WTO_10KB (0x8UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000008 */ +#define ETH_MACWTR_WTO_11KB (0x9UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000009 */ +#define ETH_MACWTR_WTO_12KB (0xAUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000A */ +#define ETH_MACWTR_WTO_13KB (0xBUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000B */ +#define ETH_MACWTR_WTO_14KB (0xCUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000C */ +#define ETH_MACWTR_WTO_15KB (0xDUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000D */ +#define ETH_MACWTR_WTO_16KB (0xEUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000E */ #define ETH_MACWTR_PWE_Pos (8U) #define ETH_MACWTR_PWE_Msk (0x1UL << ETH_MACWTR_PWE_Pos) /*!< 0x00000100 */ #define ETH_MACWTR_PWE ETH_MACWTR_PWE_Msk /*!< Programmable Watchdog Enable */ @@ -12479,6 +12498,9 @@ typedef struct #define ETH_MACHT1R_HT63T32_31 (0x80000000UL << ETH_MACHT1R_HT63T32_Pos) /*!< 0x80000000 */ /************** Bit definition for ETH_MACVTR register ***************/ +#define ETH_MACVTR_VL_VID_Pos (0U) +#define ETH_MACVTR_VL_VID_Msk (0xFFFUL << ETH_MACVTR_VL_VID_Pos) /*!< 0x00000FFF */ +#define ETH_MACVTR_VL_VID ETH_MACVTR_VL_VID_Msk /*!< VLAN Tag Identifier field of VLAN tag */ #define ETH_MACVTR_VL_Pos (0U) #define ETH_MACVTR_VL_Msk (0xFFFFUL << ETH_MACVTR_VL_Pos) /*!< 0x0000FFFF */ #define ETH_MACVTR_VL ETH_MACVTR_VL_Msk /*!< VLAN Tag Identifier for Receive Packets */ @@ -12640,9 +12662,12 @@ typedef struct #define ETH_MACQ0TXFCR_PLT_Pos (4U) #define ETH_MACQ0TXFCR_PLT_Msk (0x7UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000070 */ #define ETH_MACQ0TXFCR_PLT ETH_MACQ0TXFCR_PLT_Msk /*!< Pause Low Threshold */ -#define ETH_MACQ0TXFCR_PLT_0 (0x1UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000010 */ -#define ETH_MACQ0TXFCR_PLT_1 (0x2UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000020 */ -#define ETH_MACQ0TXFCR_PLT_2 (0x4UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000040 */ +#define ETH_MACQ0TXFCR_PLT_MINUS4 (0x0UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000000 */ +#define ETH_MACQ0TXFCR_PLT_MINUS28 (0x1UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000010 */ +#define ETH_MACQ0TXFCR_PLT_MINUS36 (0x2UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000020 */ +#define ETH_MACQ0TXFCR_PLT_MINUS144 (0x3UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000030 */ +#define ETH_MACQ0TXFCR_PLT_MINUS256 (0x4UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000040 */ +#define ETH_MACQ0TXFCR_PLT_MINUS512 (0x5UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000050 */ #define ETH_MACQ0TXFCR_DZPQ_Pos (7U) #define ETH_MACQ0TXFCR_DZPQ_Msk (0x1UL << ETH_MACQ0TXFCR_DZPQ_Pos) /*!< 0x00000080 */ #define ETH_MACQ0TXFCR_DZPQ ETH_MACQ0TXFCR_DZPQ_Msk /*!< Disable Zero-Quanta Pause */ @@ -13209,10 +13234,12 @@ typedef struct #define ETH_MACMDIOAR_CR_Pos (8U) #define ETH_MACMDIOAR_CR_Msk (0xFUL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000F00 */ #define ETH_MACMDIOAR_CR ETH_MACMDIOAR_CR_Msk /*!< CSR Clock Range */ -#define ETH_MACMDIOAR_CR_0 (0x1UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000100 */ -#define ETH_MACMDIOAR_CR_1 (0x2UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000200 */ -#define ETH_MACMDIOAR_CR_2 (0x4UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000400 */ -#define ETH_MACMDIOAR_CR_3 (0x8UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000800 */ +#define ETH_MACMDIOAR_CR_DIV42 (0x0UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000000 */ +#define ETH_MACMDIOAR_CR_DIV62 (0x1UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000100 */ +#define ETH_MACMDIOAR_CR_DIV16 (0x2UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000200 */ +#define ETH_MACMDIOAR_CR_DIV26 (0x3UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000300 */ +#define ETH_MACMDIOAR_CR_DIV102 (0x4UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000400 */ +#define ETH_MACMDIOAR_CR_DIV124 (0x5UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000500 */ #define ETH_MACMDIOAR_NTC_Pos (12U) #define ETH_MACMDIOAR_NTC_Msk (0x7UL << ETH_MACMDIOAR_NTC_Pos) /*!< 0x00007000 */ #define ETH_MACMDIOAR_NTC ETH_MACMDIOAR_NTC_Msk /*!< Number of Training Clocks */ @@ -13651,7 +13678,7 @@ typedef struct #define ETH_MMCTXIMR_TXLPIUSCIM ETH_MMCTXIMR_TXLPIUSCIM_Msk /*!< MMC Transmit LPI microsecond counter interrupt Mask */ #define ETH_MMCTXIMR_TXLPITRCIM_Pos (27U) #define ETH_MMCTXIMR_TXLPITRCIM_Msk (0x1UL << ETH_MMCTXIMR_TXLPITRCIM_Pos) /*!< 0x08000000 */ -#define ETH_MMCTXIMR_TXLPITRCIM ETH_MMC_INTERRUPT_MASK_TXLPITRCIM_Msk /*!< MMC Transmit LPI transition counter interrupt Mask */ +#define ETH_MMCTXIMR_TXLPITRCIM ETH_MMCTXIMR_TXLPITRCIM_Msk /*!< MMC Transmit LPI transition counter interrupt Mask */ /*********** Bit definition for ETH_MMC_TX_SINGLE_COLLISION_GOOD_PACKETS register ************/ #define ETH_MMCTXSCGPR_TXSNGLCOLG_Pos (0U) @@ -16354,9 +16381,10 @@ typedef struct #define ETH_DMAC0CR_DSL_Pos (18U) #define ETH_DMAC0CR_DSL_Msk (0x7UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x001C0000 */ #define ETH_DMAC0CR_DSL ETH_DMAC0CR_DSL_Msk /*!< Descriptor Skip Length */ -#define ETH_DMAC0CR_DSL_0 (0x1UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00040000 */ -#define ETH_DMAC0CR_DSL_1 (0x2UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00080000 */ -#define ETH_DMAC0CR_DSL_2 (0x4UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00100000 */ +#define ETH_DMACCR_DSL_0BIT (0x0UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00000000 */ +#define ETH_DMACCR_DSL_32BIT (0x1UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00040000 */ +#define ETH_DMACCR_DSL_64BIT (0x2UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00080000 */ +#define ETH_DMACCR_DSL_128BIT (0x4UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00100000 */ /************* Bit definition for ETH_DMAC0TXCR register *************/ #define ETH_DMAC0TXCR_ST_Pos (0U) @@ -16377,12 +16405,12 @@ typedef struct #define ETH_DMAC0TXCR_TXPBL_Pos (16U) #define ETH_DMAC0TXCR_TXPBL_Msk (0x3FUL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x003F0000 */ #define ETH_DMAC0TXCR_TXPBL ETH_DMAC0TXCR_TXPBL_Msk /*!< Transmit Programmable Burst Length */ -#define ETH_DMAC0TXCR_TXPBL_0 (0x1UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00010000 */ -#define ETH_DMAC0TXCR_TXPBL_1 (0x2UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00020000 */ -#define ETH_DMAC0TXCR_TXPBL_2 (0x4UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00040000 */ -#define ETH_DMAC0TXCR_TXPBL_3 (0x8UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00080000 */ -#define ETH_DMAC0TXCR_TXPBL_4 (0x10UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00100000 */ -#define ETH_DMAC0TXCR_TXPBL_5 (0x20UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00200000 */ +#define ETH_DMAC0TXCR_TXPBL_1PBL (0x1UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00010000 */ +#define ETH_DMAC0TXCR_TXPBL_2PBL (0x2UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00020000 */ +#define ETH_DMAC0TXCR_TXPBL_4PBL (0x4UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00040000 */ +#define ETH_DMAC0TXCR_TXPBL_8PBL (0x8UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00080000 */ +#define ETH_DMAC0TXCR_TXPBL_16PBL (0x10UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00100000 */ +#define ETH_DMAC0TXCR_TXPBL_32PBL (0x20UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00200000 */ #define ETH_DMAC0TXCR_TQOS_Pos (24U) #define ETH_DMAC0TXCR_TQOS_Msk (0xFUL << ETH_DMAC0TXCR_TQOS_Pos) /*!< 0x0F000000 */ #define ETH_DMAC0TXCR_TQOS ETH_DMAC0TXCR_TQOS_Msk /*!< Transmit QOS. */ @@ -16415,12 +16443,12 @@ typedef struct #define ETH_DMAC0RXCR_RXPBL_Pos (16U) #define ETH_DMAC0RXCR_RXPBL_Msk (0x3FUL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x003F0000 */ #define ETH_DMAC0RXCR_RXPBL ETH_DMAC0RXCR_RXPBL_Msk /*!< Receive Programmable Burst Length */ -#define ETH_DMAC0RXCR_RXPBL_0 (0x1UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00010000 */ -#define ETH_DMAC0RXCR_RXPBL_1 (0x2UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00020000 */ -#define ETH_DMAC0RXCR_RXPBL_2 (0x4UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00040000 */ -#define ETH_DMAC0RXCR_RXPBL_3 (0x8UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00080000 */ -#define ETH_DMAC0RXCR_RXPBL_4 (0x10UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00100000 */ -#define ETH_DMAC0RXCR_RXPBL_5 (0x20UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00200000 */ +#define ETH_DMAC0RXCR_RXPBL_1PBL (0x1UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00010000 */ +#define ETH_DMAC0RXCR_RXPBL_2PBL (0x2UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00020000 */ +#define ETH_DMAC0RXCR_RXPBL_4PBL (0x4UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00040000 */ +#define ETH_DMAC0RXCR_RXPBL_8PBL (0x8UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00080000 */ +#define ETH_DMAC0RXCR_RXPBL_16PBL (0x10UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00100000 */ +#define ETH_DMAC0RXCR_RXPBL_32PBL (0x20UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00200000 */ #define ETH_DMAC0RXCR_RQOS_Pos (24U) #define ETH_DMAC0RXCR_RQOS_Msk (0xFUL << ETH_DMAC0RXCR_RQOS_Pos) /*!< 0x0F000000 */ #define ETH_DMAC0RXCR_RQOS ETH_DMAC0RXCR_RQOS_Msk /*!< Rx AXI4 QOS. */ @@ -24358,6 +24386,16 @@ typedef struct #define BSEC_HWCFGR_ECC_USE_Msk (0xFUL << BSEC_HWCFGR_ECC_USE_Pos) /*!< 0x000000F0 */ #define BSEC_HWCFGR_ECC_USE BSEC_HWCFGR_ECC_USE_Msk /*!< protection / redundancy scheme used */ +/******************** Bit definition for BSEC_JTAGIN register ********************/ +#define BSEC_JTAGIN_DATA_Pos (0U) +#define BSEC_JTAGIN_DATA_Msk (0x0000FFFFUL << BSEC_JTAGIN_DATA_Pos) /*!< JTAG Input Data */ +#define BSEC_JTAGIN_DATA BSEC_JTAGIN_DATA_Msk + +/******************** Bit definition for BSEC_JTAGOUT register ********************/ +#define BSEC_JTAGOUT_DATA_Pos (0U) +#define BSEC_JTAGOUT_DATA_Msk (0x0000FFFFUL << BSEC_JTAGOUT_DATA_Pos) /*!< JTAG Output Data */ +#define BSEC_JTAGOUT_DATA BSEC_JTAGOUT_DATA_Msk + /******************** Bit definition for BSEC_VERR register********************/ #define BSEC_VERR_MINREV_Pos (0U) #define BSEC_VERR_MINREV_Msk (0xFUL << BSEC_VERR_MINREV_Pos) /*!< 0x0000000F */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153fxx_ca7.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153fxx_ca7.h index fd748e59cb..b8f727415b 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153fxx_ca7.h +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153fxx_ca7.h @@ -12461,16 +12461,19 @@ typedef struct #define ETH_MACCR_PRELEN_Pos (2U) #define ETH_MACCR_PRELEN_Msk (0x3UL << ETH_MACCR_PRELEN_Pos) /*!< 0x0000000C */ #define ETH_MACCR_PRELEN ETH_MACCR_PRELEN_Msk /*!< Preamble Length for Transmit packets */ -#define ETH_MACCR_PRELEN_0 (0x1UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000004 */ -#define ETH_MACCR_PRELEN_1 (0x2UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000008 */ +#define ETH_MACCR_PRELEN_7 (0x0UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000000 */ +#define ETH_MACCR_PRELEN_5 (0x1UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000004 */ +#define ETH_MACCR_PRELEN_3 (0x2UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000006 */ #define ETH_MACCR_DC_Pos (4U) #define ETH_MACCR_DC_Msk (0x1UL << ETH_MACCR_DC_Pos) /*!< 0x00000010 */ #define ETH_MACCR_DC ETH_MACCR_DC_Msk /*!< Deferral Check */ #define ETH_MACCR_BL_Pos (5U) #define ETH_MACCR_BL_Msk (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */ #define ETH_MACCR_BL ETH_MACCR_BL_Msk /*!< Back-Off Limit */ -#define ETH_MACCR_BL_0 (0x1UL << ETH_MACCR_BL_Pos) /*!< 0x00000020 */ -#define ETH_MACCR_BL_1 (0x2UL << ETH_MACCR_BL_Pos) /*!< 0x00000040 */ +#define ETH_MACCR_BL_10 (0x0UL << ETH_MACCR_BL_Pos) /*!< 0x00000000 */ +#define ETH_MACCR_BL_8 (0x1UL << ETH_MACCR_BL_Pos) /*!< 0x00000020 */ +#define ETH_MACCR_BL_4 (0x2UL << ETH_MACCR_BL_Pos) /*!< 0x00000040 */ +#define ETH_MACCR_BL_1 (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */ #define ETH_MACCR_DR_Pos (8U) #define ETH_MACCR_DR_Msk (0x1UL << ETH_MACCR_DR_Pos) /*!< 0x00000100 */ #define ETH_MACCR_DR ETH_MACCR_DR_Msk /*!< Disable Retry */ @@ -12522,9 +12525,14 @@ typedef struct #define ETH_MACCR_IPG_Pos (24U) #define ETH_MACCR_IPG_Msk (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */ #define ETH_MACCR_IPG ETH_MACCR_IPG_Msk /*!< Inter-Packet Gap */ -#define ETH_MACCR_IPG_0 (0x1UL << ETH_MACCR_IPG_Pos) /*!< 0x01000000 */ -#define ETH_MACCR_IPG_1 (0x2UL << ETH_MACCR_IPG_Pos) /*!< 0x02000000 */ -#define ETH_MACCR_IPG_2 (0x4UL << ETH_MACCR_IPG_Pos) /*!< 0x04000000 */ +#define ETH_MACCR_IPG_96BIT (0x0UL << ETH_MACCR_IPG_Pos) /*!< 0x00000000 */ +#define ETH_MACCR_IPG_88BIT (0x1UL << ETH_MACCR_IPG_Pos) /*!< 0x01000000 */ +#define ETH_MACCR_IPG_80BIT (0x2UL << ETH_MACCR_IPG_Pos) /*!< 0x02000000 */ +#define ETH_MACCR_IPG_72BIT (0x3UL << ETH_MACCR_IPG_Pos) /*!< 0x03000000 */ +#define ETH_MACCR_IPG_64BIT (0x4UL << ETH_MACCR_IPG_Pos) /*!< 0x04000000 */ +#define ETH_MACCR_IPG_56BIT (0x5UL << ETH_MACCR_IPG_Pos) /*!< 0x05000000 */ +#define ETH_MACCR_IPG_48BIT (0x6UL << ETH_MACCR_IPG_Pos) /*!< 0x06000000 */ +#define ETH_MACCR_IPG_40BIT (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */ #define ETH_MACCR_IPC_Pos (27U) #define ETH_MACCR_IPC_Msk (0x1UL << ETH_MACCR_IPC_Pos) /*!< 0x08000000 */ #define ETH_MACCR_IPC ETH_MACCR_IPC_Msk /*!< Checksum Offload */ @@ -12627,10 +12635,21 @@ typedef struct #define ETH_MACWTR_WTO_Pos (0U) #define ETH_MACWTR_WTO_Msk (0xFUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000F */ #define ETH_MACWTR_WTO ETH_MACWTR_WTO_Msk /*!< Watchdog Timeout */ -#define ETH_MACWTR_WTO_0 (0x1UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000001 */ -#define ETH_MACWTR_WTO_1 (0x2UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000002 */ -#define ETH_MACWTR_WTO_2 (0x4UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000004 */ -#define ETH_MACWTR_WTO_3 (0x8UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000008 */ +#define ETH_MACWTR_WTO_2KB (0x0UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000001 */ +#define ETH_MACWTR_WTO_3KB (0x1UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000001 */ +#define ETH_MACWTR_WTO_4KB (0x2UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000002 */ +#define ETH_MACWTR_WTO_5KB (0x3UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000003 */ +#define ETH_MACWTR_WTO_6KB (0x4UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000004 */ +#define ETH_MACWTR_WTO_7KB (0x5UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000005 */ +#define ETH_MACWTR_WTO_8KB (0x6UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000006 */ +#define ETH_MACWTR_WTO_9KB (0x7UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000007 */ +#define ETH_MACWTR_WTO_10KB (0x8UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000008 */ +#define ETH_MACWTR_WTO_11KB (0x9UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000009 */ +#define ETH_MACWTR_WTO_12KB (0xAUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000A */ +#define ETH_MACWTR_WTO_13KB (0xBUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000B */ +#define ETH_MACWTR_WTO_14KB (0xCUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000C */ +#define ETH_MACWTR_WTO_15KB (0xDUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000D */ +#define ETH_MACWTR_WTO_16KB (0xEUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000E */ #define ETH_MACWTR_PWE_Pos (8U) #define ETH_MACWTR_PWE_Msk (0x1UL << ETH_MACWTR_PWE_Pos) /*!< 0x00000100 */ #define ETH_MACWTR_PWE ETH_MACWTR_PWE_Msk /*!< Programmable Watchdog Enable */ @@ -12710,6 +12729,9 @@ typedef struct #define ETH_MACHT1R_HT63T32_31 (0x80000000UL << ETH_MACHT1R_HT63T32_Pos) /*!< 0x80000000 */ /************** Bit definition for ETH_MACVTR register ***************/ +#define ETH_MACVTR_VL_VID_Pos (0U) +#define ETH_MACVTR_VL_VID_Msk (0xFFFUL << ETH_MACVTR_VL_VID_Pos) /*!< 0x00000FFF */ +#define ETH_MACVTR_VL_VID ETH_MACVTR_VL_VID_Msk /*!< VLAN Tag Identifier field of VLAN tag */ #define ETH_MACVTR_VL_Pos (0U) #define ETH_MACVTR_VL_Msk (0xFFFFUL << ETH_MACVTR_VL_Pos) /*!< 0x0000FFFF */ #define ETH_MACVTR_VL ETH_MACVTR_VL_Msk /*!< VLAN Tag Identifier for Receive Packets */ @@ -12871,9 +12893,12 @@ typedef struct #define ETH_MACQ0TXFCR_PLT_Pos (4U) #define ETH_MACQ0TXFCR_PLT_Msk (0x7UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000070 */ #define ETH_MACQ0TXFCR_PLT ETH_MACQ0TXFCR_PLT_Msk /*!< Pause Low Threshold */ -#define ETH_MACQ0TXFCR_PLT_0 (0x1UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000010 */ -#define ETH_MACQ0TXFCR_PLT_1 (0x2UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000020 */ -#define ETH_MACQ0TXFCR_PLT_2 (0x4UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000040 */ +#define ETH_MACQ0TXFCR_PLT_MINUS4 (0x0UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000000 */ +#define ETH_MACQ0TXFCR_PLT_MINUS28 (0x1UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000010 */ +#define ETH_MACQ0TXFCR_PLT_MINUS36 (0x2UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000020 */ +#define ETH_MACQ0TXFCR_PLT_MINUS144 (0x3UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000030 */ +#define ETH_MACQ0TXFCR_PLT_MINUS256 (0x4UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000040 */ +#define ETH_MACQ0TXFCR_PLT_MINUS512 (0x5UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000050 */ #define ETH_MACQ0TXFCR_DZPQ_Pos (7U) #define ETH_MACQ0TXFCR_DZPQ_Msk (0x1UL << ETH_MACQ0TXFCR_DZPQ_Pos) /*!< 0x00000080 */ #define ETH_MACQ0TXFCR_DZPQ ETH_MACQ0TXFCR_DZPQ_Msk /*!< Disable Zero-Quanta Pause */ @@ -13440,10 +13465,12 @@ typedef struct #define ETH_MACMDIOAR_CR_Pos (8U) #define ETH_MACMDIOAR_CR_Msk (0xFUL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000F00 */ #define ETH_MACMDIOAR_CR ETH_MACMDIOAR_CR_Msk /*!< CSR Clock Range */ -#define ETH_MACMDIOAR_CR_0 (0x1UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000100 */ -#define ETH_MACMDIOAR_CR_1 (0x2UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000200 */ -#define ETH_MACMDIOAR_CR_2 (0x4UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000400 */ -#define ETH_MACMDIOAR_CR_3 (0x8UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000800 */ +#define ETH_MACMDIOAR_CR_DIV42 (0x0UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000000 */ +#define ETH_MACMDIOAR_CR_DIV62 (0x1UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000100 */ +#define ETH_MACMDIOAR_CR_DIV16 (0x2UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000200 */ +#define ETH_MACMDIOAR_CR_DIV26 (0x3UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000300 */ +#define ETH_MACMDIOAR_CR_DIV102 (0x4UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000400 */ +#define ETH_MACMDIOAR_CR_DIV124 (0x5UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000500 */ #define ETH_MACMDIOAR_NTC_Pos (12U) #define ETH_MACMDIOAR_NTC_Msk (0x7UL << ETH_MACMDIOAR_NTC_Pos) /*!< 0x00007000 */ #define ETH_MACMDIOAR_NTC ETH_MACMDIOAR_NTC_Msk /*!< Number of Training Clocks */ @@ -13882,7 +13909,7 @@ typedef struct #define ETH_MMCTXIMR_TXLPIUSCIM ETH_MMCTXIMR_TXLPIUSCIM_Msk /*!< MMC Transmit LPI microsecond counter interrupt Mask */ #define ETH_MMCTXIMR_TXLPITRCIM_Pos (27U) #define ETH_MMCTXIMR_TXLPITRCIM_Msk (0x1UL << ETH_MMCTXIMR_TXLPITRCIM_Pos) /*!< 0x08000000 */ -#define ETH_MMCTXIMR_TXLPITRCIM ETH_MMC_INTERRUPT_MASK_TXLPITRCIM_Msk /*!< MMC Transmit LPI transition counter interrupt Mask */ +#define ETH_MMCTXIMR_TXLPITRCIM ETH_MMCTXIMR_TXLPITRCIM_Msk /*!< MMC Transmit LPI transition counter interrupt Mask */ /*********** Bit definition for ETH_MMC_TX_SINGLE_COLLISION_GOOD_PACKETS register ************/ #define ETH_MMCTXSCGPR_TXSNGLCOLG_Pos (0U) @@ -16585,9 +16612,10 @@ typedef struct #define ETH_DMAC0CR_DSL_Pos (18U) #define ETH_DMAC0CR_DSL_Msk (0x7UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x001C0000 */ #define ETH_DMAC0CR_DSL ETH_DMAC0CR_DSL_Msk /*!< Descriptor Skip Length */ -#define ETH_DMAC0CR_DSL_0 (0x1UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00040000 */ -#define ETH_DMAC0CR_DSL_1 (0x2UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00080000 */ -#define ETH_DMAC0CR_DSL_2 (0x4UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00100000 */ +#define ETH_DMACCR_DSL_0BIT (0x0UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00000000 */ +#define ETH_DMACCR_DSL_32BIT (0x1UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00040000 */ +#define ETH_DMACCR_DSL_64BIT (0x2UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00080000 */ +#define ETH_DMACCR_DSL_128BIT (0x4UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00100000 */ /************* Bit definition for ETH_DMAC0TXCR register *************/ #define ETH_DMAC0TXCR_ST_Pos (0U) @@ -16608,12 +16636,12 @@ typedef struct #define ETH_DMAC0TXCR_TXPBL_Pos (16U) #define ETH_DMAC0TXCR_TXPBL_Msk (0x3FUL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x003F0000 */ #define ETH_DMAC0TXCR_TXPBL ETH_DMAC0TXCR_TXPBL_Msk /*!< Transmit Programmable Burst Length */ -#define ETH_DMAC0TXCR_TXPBL_0 (0x1UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00010000 */ -#define ETH_DMAC0TXCR_TXPBL_1 (0x2UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00020000 */ -#define ETH_DMAC0TXCR_TXPBL_2 (0x4UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00040000 */ -#define ETH_DMAC0TXCR_TXPBL_3 (0x8UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00080000 */ -#define ETH_DMAC0TXCR_TXPBL_4 (0x10UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00100000 */ -#define ETH_DMAC0TXCR_TXPBL_5 (0x20UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00200000 */ +#define ETH_DMAC0TXCR_TXPBL_1PBL (0x1UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00010000 */ +#define ETH_DMAC0TXCR_TXPBL_2PBL (0x2UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00020000 */ +#define ETH_DMAC0TXCR_TXPBL_4PBL (0x4UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00040000 */ +#define ETH_DMAC0TXCR_TXPBL_8PBL (0x8UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00080000 */ +#define ETH_DMAC0TXCR_TXPBL_16PBL (0x10UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00100000 */ +#define ETH_DMAC0TXCR_TXPBL_32PBL (0x20UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00200000 */ #define ETH_DMAC0TXCR_TQOS_Pos (24U) #define ETH_DMAC0TXCR_TQOS_Msk (0xFUL << ETH_DMAC0TXCR_TQOS_Pos) /*!< 0x0F000000 */ #define ETH_DMAC0TXCR_TQOS ETH_DMAC0TXCR_TQOS_Msk /*!< Transmit QOS. */ @@ -16646,12 +16674,12 @@ typedef struct #define ETH_DMAC0RXCR_RXPBL_Pos (16U) #define ETH_DMAC0RXCR_RXPBL_Msk (0x3FUL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x003F0000 */ #define ETH_DMAC0RXCR_RXPBL ETH_DMAC0RXCR_RXPBL_Msk /*!< Receive Programmable Burst Length */ -#define ETH_DMAC0RXCR_RXPBL_0 (0x1UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00010000 */ -#define ETH_DMAC0RXCR_RXPBL_1 (0x2UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00020000 */ -#define ETH_DMAC0RXCR_RXPBL_2 (0x4UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00040000 */ -#define ETH_DMAC0RXCR_RXPBL_3 (0x8UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00080000 */ -#define ETH_DMAC0RXCR_RXPBL_4 (0x10UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00100000 */ -#define ETH_DMAC0RXCR_RXPBL_5 (0x20UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00200000 */ +#define ETH_DMAC0RXCR_RXPBL_1PBL (0x1UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00010000 */ +#define ETH_DMAC0RXCR_RXPBL_2PBL (0x2UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00020000 */ +#define ETH_DMAC0RXCR_RXPBL_4PBL (0x4UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00040000 */ +#define ETH_DMAC0RXCR_RXPBL_8PBL (0x8UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00080000 */ +#define ETH_DMAC0RXCR_RXPBL_16PBL (0x10UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00100000 */ +#define ETH_DMAC0RXCR_RXPBL_32PBL (0x20UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00200000 */ #define ETH_DMAC0RXCR_RQOS_Pos (24U) #define ETH_DMAC0RXCR_RQOS_Msk (0xFUL << ETH_DMAC0RXCR_RQOS_Pos) /*!< 0x0F000000 */ #define ETH_DMAC0RXCR_RQOS ETH_DMAC0RXCR_RQOS_Msk /*!< Rx AXI4 QOS. */ @@ -24589,6 +24617,16 @@ typedef struct #define BSEC_HWCFGR_ECC_USE_Msk (0xFUL << BSEC_HWCFGR_ECC_USE_Pos) /*!< 0x000000F0 */ #define BSEC_HWCFGR_ECC_USE BSEC_HWCFGR_ECC_USE_Msk /*!< protection / redundancy scheme used */ +/******************** Bit definition for BSEC_JTAGIN register ********************/ +#define BSEC_JTAGIN_DATA_Pos (0U) +#define BSEC_JTAGIN_DATA_Msk (0x0000FFFFUL << BSEC_JTAGIN_DATA_Pos) /*!< JTAG Input Data */ +#define BSEC_JTAGIN_DATA BSEC_JTAGIN_DATA_Msk + +/******************** Bit definition for BSEC_JTAGOUT register ********************/ +#define BSEC_JTAGOUT_DATA_Pos (0U) +#define BSEC_JTAGOUT_DATA_Msk (0x0000FFFFUL << BSEC_JTAGOUT_DATA_Pos) /*!< JTAG Output Data */ +#define BSEC_JTAGOUT_DATA BSEC_JTAGOUT_DATA_Msk + /******************** Bit definition for BSEC_VERR register********************/ #define BSEC_VERR_MINREV_Pos (0U) #define BSEC_VERR_MINREV_Msk (0xFUL << BSEC_VERR_MINREV_Pos) /*!< 0x0000000F */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153fxx_cm4.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153fxx_cm4.h index a1a93a543d..f2fbefcd3c 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153fxx_cm4.h +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153fxx_cm4.h @@ -12427,16 +12427,19 @@ typedef struct #define ETH_MACCR_PRELEN_Pos (2U) #define ETH_MACCR_PRELEN_Msk (0x3UL << ETH_MACCR_PRELEN_Pos) /*!< 0x0000000C */ #define ETH_MACCR_PRELEN ETH_MACCR_PRELEN_Msk /*!< Preamble Length for Transmit packets */ -#define ETH_MACCR_PRELEN_0 (0x1UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000004 */ -#define ETH_MACCR_PRELEN_1 (0x2UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000008 */ +#define ETH_MACCR_PRELEN_7 (0x0UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000000 */ +#define ETH_MACCR_PRELEN_5 (0x1UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000004 */ +#define ETH_MACCR_PRELEN_3 (0x2UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000006 */ #define ETH_MACCR_DC_Pos (4U) #define ETH_MACCR_DC_Msk (0x1UL << ETH_MACCR_DC_Pos) /*!< 0x00000010 */ #define ETH_MACCR_DC ETH_MACCR_DC_Msk /*!< Deferral Check */ #define ETH_MACCR_BL_Pos (5U) #define ETH_MACCR_BL_Msk (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */ #define ETH_MACCR_BL ETH_MACCR_BL_Msk /*!< Back-Off Limit */ -#define ETH_MACCR_BL_0 (0x1UL << ETH_MACCR_BL_Pos) /*!< 0x00000020 */ -#define ETH_MACCR_BL_1 (0x2UL << ETH_MACCR_BL_Pos) /*!< 0x00000040 */ +#define ETH_MACCR_BL_10 (0x0UL << ETH_MACCR_BL_Pos) /*!< 0x00000000 */ +#define ETH_MACCR_BL_8 (0x1UL << ETH_MACCR_BL_Pos) /*!< 0x00000020 */ +#define ETH_MACCR_BL_4 (0x2UL << ETH_MACCR_BL_Pos) /*!< 0x00000040 */ +#define ETH_MACCR_BL_1 (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */ #define ETH_MACCR_DR_Pos (8U) #define ETH_MACCR_DR_Msk (0x1UL << ETH_MACCR_DR_Pos) /*!< 0x00000100 */ #define ETH_MACCR_DR ETH_MACCR_DR_Msk /*!< Disable Retry */ @@ -12488,9 +12491,14 @@ typedef struct #define ETH_MACCR_IPG_Pos (24U) #define ETH_MACCR_IPG_Msk (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */ #define ETH_MACCR_IPG ETH_MACCR_IPG_Msk /*!< Inter-Packet Gap */ -#define ETH_MACCR_IPG_0 (0x1UL << ETH_MACCR_IPG_Pos) /*!< 0x01000000 */ -#define ETH_MACCR_IPG_1 (0x2UL << ETH_MACCR_IPG_Pos) /*!< 0x02000000 */ -#define ETH_MACCR_IPG_2 (0x4UL << ETH_MACCR_IPG_Pos) /*!< 0x04000000 */ +#define ETH_MACCR_IPG_96BIT (0x0UL << ETH_MACCR_IPG_Pos) /*!< 0x00000000 */ +#define ETH_MACCR_IPG_88BIT (0x1UL << ETH_MACCR_IPG_Pos) /*!< 0x01000000 */ +#define ETH_MACCR_IPG_80BIT (0x2UL << ETH_MACCR_IPG_Pos) /*!< 0x02000000 */ +#define ETH_MACCR_IPG_72BIT (0x3UL << ETH_MACCR_IPG_Pos) /*!< 0x03000000 */ +#define ETH_MACCR_IPG_64BIT (0x4UL << ETH_MACCR_IPG_Pos) /*!< 0x04000000 */ +#define ETH_MACCR_IPG_56BIT (0x5UL << ETH_MACCR_IPG_Pos) /*!< 0x05000000 */ +#define ETH_MACCR_IPG_48BIT (0x6UL << ETH_MACCR_IPG_Pos) /*!< 0x06000000 */ +#define ETH_MACCR_IPG_40BIT (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */ #define ETH_MACCR_IPC_Pos (27U) #define ETH_MACCR_IPC_Msk (0x1UL << ETH_MACCR_IPC_Pos) /*!< 0x08000000 */ #define ETH_MACCR_IPC ETH_MACCR_IPC_Msk /*!< Checksum Offload */ @@ -12593,10 +12601,21 @@ typedef struct #define ETH_MACWTR_WTO_Pos (0U) #define ETH_MACWTR_WTO_Msk (0xFUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000F */ #define ETH_MACWTR_WTO ETH_MACWTR_WTO_Msk /*!< Watchdog Timeout */ -#define ETH_MACWTR_WTO_0 (0x1UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000001 */ -#define ETH_MACWTR_WTO_1 (0x2UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000002 */ -#define ETH_MACWTR_WTO_2 (0x4UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000004 */ -#define ETH_MACWTR_WTO_3 (0x8UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000008 */ +#define ETH_MACWTR_WTO_2KB (0x0UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000001 */ +#define ETH_MACWTR_WTO_3KB (0x1UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000001 */ +#define ETH_MACWTR_WTO_4KB (0x2UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000002 */ +#define ETH_MACWTR_WTO_5KB (0x3UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000003 */ +#define ETH_MACWTR_WTO_6KB (0x4UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000004 */ +#define ETH_MACWTR_WTO_7KB (0x5UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000005 */ +#define ETH_MACWTR_WTO_8KB (0x6UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000006 */ +#define ETH_MACWTR_WTO_9KB (0x7UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000007 */ +#define ETH_MACWTR_WTO_10KB (0x8UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000008 */ +#define ETH_MACWTR_WTO_11KB (0x9UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000009 */ +#define ETH_MACWTR_WTO_12KB (0xAUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000A */ +#define ETH_MACWTR_WTO_13KB (0xBUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000B */ +#define ETH_MACWTR_WTO_14KB (0xCUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000C */ +#define ETH_MACWTR_WTO_15KB (0xDUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000D */ +#define ETH_MACWTR_WTO_16KB (0xEUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000E */ #define ETH_MACWTR_PWE_Pos (8U) #define ETH_MACWTR_PWE_Msk (0x1UL << ETH_MACWTR_PWE_Pos) /*!< 0x00000100 */ #define ETH_MACWTR_PWE ETH_MACWTR_PWE_Msk /*!< Programmable Watchdog Enable */ @@ -12676,6 +12695,9 @@ typedef struct #define ETH_MACHT1R_HT63T32_31 (0x80000000UL << ETH_MACHT1R_HT63T32_Pos) /*!< 0x80000000 */ /************** Bit definition for ETH_MACVTR register ***************/ +#define ETH_MACVTR_VL_VID_Pos (0U) +#define ETH_MACVTR_VL_VID_Msk (0xFFFUL << ETH_MACVTR_VL_VID_Pos) /*!< 0x00000FFF */ +#define ETH_MACVTR_VL_VID ETH_MACVTR_VL_VID_Msk /*!< VLAN Tag Identifier field of VLAN tag */ #define ETH_MACVTR_VL_Pos (0U) #define ETH_MACVTR_VL_Msk (0xFFFFUL << ETH_MACVTR_VL_Pos) /*!< 0x0000FFFF */ #define ETH_MACVTR_VL ETH_MACVTR_VL_Msk /*!< VLAN Tag Identifier for Receive Packets */ @@ -12837,9 +12859,12 @@ typedef struct #define ETH_MACQ0TXFCR_PLT_Pos (4U) #define ETH_MACQ0TXFCR_PLT_Msk (0x7UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000070 */ #define ETH_MACQ0TXFCR_PLT ETH_MACQ0TXFCR_PLT_Msk /*!< Pause Low Threshold */ -#define ETH_MACQ0TXFCR_PLT_0 (0x1UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000010 */ -#define ETH_MACQ0TXFCR_PLT_1 (0x2UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000020 */ -#define ETH_MACQ0TXFCR_PLT_2 (0x4UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000040 */ +#define ETH_MACQ0TXFCR_PLT_MINUS4 (0x0UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000000 */ +#define ETH_MACQ0TXFCR_PLT_MINUS28 (0x1UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000010 */ +#define ETH_MACQ0TXFCR_PLT_MINUS36 (0x2UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000020 */ +#define ETH_MACQ0TXFCR_PLT_MINUS144 (0x3UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000030 */ +#define ETH_MACQ0TXFCR_PLT_MINUS256 (0x4UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000040 */ +#define ETH_MACQ0TXFCR_PLT_MINUS512 (0x5UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000050 */ #define ETH_MACQ0TXFCR_DZPQ_Pos (7U) #define ETH_MACQ0TXFCR_DZPQ_Msk (0x1UL << ETH_MACQ0TXFCR_DZPQ_Pos) /*!< 0x00000080 */ #define ETH_MACQ0TXFCR_DZPQ ETH_MACQ0TXFCR_DZPQ_Msk /*!< Disable Zero-Quanta Pause */ @@ -13406,10 +13431,12 @@ typedef struct #define ETH_MACMDIOAR_CR_Pos (8U) #define ETH_MACMDIOAR_CR_Msk (0xFUL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000F00 */ #define ETH_MACMDIOAR_CR ETH_MACMDIOAR_CR_Msk /*!< CSR Clock Range */ -#define ETH_MACMDIOAR_CR_0 (0x1UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000100 */ -#define ETH_MACMDIOAR_CR_1 (0x2UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000200 */ -#define ETH_MACMDIOAR_CR_2 (0x4UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000400 */ -#define ETH_MACMDIOAR_CR_3 (0x8UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000800 */ +#define ETH_MACMDIOAR_CR_DIV42 (0x0UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000000 */ +#define ETH_MACMDIOAR_CR_DIV62 (0x1UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000100 */ +#define ETH_MACMDIOAR_CR_DIV16 (0x2UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000200 */ +#define ETH_MACMDIOAR_CR_DIV26 (0x3UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000300 */ +#define ETH_MACMDIOAR_CR_DIV102 (0x4UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000400 */ +#define ETH_MACMDIOAR_CR_DIV124 (0x5UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000500 */ #define ETH_MACMDIOAR_NTC_Pos (12U) #define ETH_MACMDIOAR_NTC_Msk (0x7UL << ETH_MACMDIOAR_NTC_Pos) /*!< 0x00007000 */ #define ETH_MACMDIOAR_NTC ETH_MACMDIOAR_NTC_Msk /*!< Number of Training Clocks */ @@ -13848,7 +13875,7 @@ typedef struct #define ETH_MMCTXIMR_TXLPIUSCIM ETH_MMCTXIMR_TXLPIUSCIM_Msk /*!< MMC Transmit LPI microsecond counter interrupt Mask */ #define ETH_MMCTXIMR_TXLPITRCIM_Pos (27U) #define ETH_MMCTXIMR_TXLPITRCIM_Msk (0x1UL << ETH_MMCTXIMR_TXLPITRCIM_Pos) /*!< 0x08000000 */ -#define ETH_MMCTXIMR_TXLPITRCIM ETH_MMC_INTERRUPT_MASK_TXLPITRCIM_Msk /*!< MMC Transmit LPI transition counter interrupt Mask */ +#define ETH_MMCTXIMR_TXLPITRCIM ETH_MMCTXIMR_TXLPITRCIM_Msk /*!< MMC Transmit LPI transition counter interrupt Mask */ /*********** Bit definition for ETH_MMC_TX_SINGLE_COLLISION_GOOD_PACKETS register ************/ #define ETH_MMCTXSCGPR_TXSNGLCOLG_Pos (0U) @@ -16551,9 +16578,10 @@ typedef struct #define ETH_DMAC0CR_DSL_Pos (18U) #define ETH_DMAC0CR_DSL_Msk (0x7UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x001C0000 */ #define ETH_DMAC0CR_DSL ETH_DMAC0CR_DSL_Msk /*!< Descriptor Skip Length */ -#define ETH_DMAC0CR_DSL_0 (0x1UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00040000 */ -#define ETH_DMAC0CR_DSL_1 (0x2UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00080000 */ -#define ETH_DMAC0CR_DSL_2 (0x4UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00100000 */ +#define ETH_DMACCR_DSL_0BIT (0x0UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00000000 */ +#define ETH_DMACCR_DSL_32BIT (0x1UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00040000 */ +#define ETH_DMACCR_DSL_64BIT (0x2UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00080000 */ +#define ETH_DMACCR_DSL_128BIT (0x4UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00100000 */ /************* Bit definition for ETH_DMAC0TXCR register *************/ #define ETH_DMAC0TXCR_ST_Pos (0U) @@ -16574,12 +16602,12 @@ typedef struct #define ETH_DMAC0TXCR_TXPBL_Pos (16U) #define ETH_DMAC0TXCR_TXPBL_Msk (0x3FUL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x003F0000 */ #define ETH_DMAC0TXCR_TXPBL ETH_DMAC0TXCR_TXPBL_Msk /*!< Transmit Programmable Burst Length */ -#define ETH_DMAC0TXCR_TXPBL_0 (0x1UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00010000 */ -#define ETH_DMAC0TXCR_TXPBL_1 (0x2UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00020000 */ -#define ETH_DMAC0TXCR_TXPBL_2 (0x4UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00040000 */ -#define ETH_DMAC0TXCR_TXPBL_3 (0x8UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00080000 */ -#define ETH_DMAC0TXCR_TXPBL_4 (0x10UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00100000 */ -#define ETH_DMAC0TXCR_TXPBL_5 (0x20UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00200000 */ +#define ETH_DMAC0TXCR_TXPBL_1PBL (0x1UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00010000 */ +#define ETH_DMAC0TXCR_TXPBL_2PBL (0x2UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00020000 */ +#define ETH_DMAC0TXCR_TXPBL_4PBL (0x4UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00040000 */ +#define ETH_DMAC0TXCR_TXPBL_8PBL (0x8UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00080000 */ +#define ETH_DMAC0TXCR_TXPBL_16PBL (0x10UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00100000 */ +#define ETH_DMAC0TXCR_TXPBL_32PBL (0x20UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00200000 */ #define ETH_DMAC0TXCR_TQOS_Pos (24U) #define ETH_DMAC0TXCR_TQOS_Msk (0xFUL << ETH_DMAC0TXCR_TQOS_Pos) /*!< 0x0F000000 */ #define ETH_DMAC0TXCR_TQOS ETH_DMAC0TXCR_TQOS_Msk /*!< Transmit QOS. */ @@ -16612,12 +16640,12 @@ typedef struct #define ETH_DMAC0RXCR_RXPBL_Pos (16U) #define ETH_DMAC0RXCR_RXPBL_Msk (0x3FUL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x003F0000 */ #define ETH_DMAC0RXCR_RXPBL ETH_DMAC0RXCR_RXPBL_Msk /*!< Receive Programmable Burst Length */ -#define ETH_DMAC0RXCR_RXPBL_0 (0x1UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00010000 */ -#define ETH_DMAC0RXCR_RXPBL_1 (0x2UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00020000 */ -#define ETH_DMAC0RXCR_RXPBL_2 (0x4UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00040000 */ -#define ETH_DMAC0RXCR_RXPBL_3 (0x8UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00080000 */ -#define ETH_DMAC0RXCR_RXPBL_4 (0x10UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00100000 */ -#define ETH_DMAC0RXCR_RXPBL_5 (0x20UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00200000 */ +#define ETH_DMAC0RXCR_RXPBL_1PBL (0x1UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00010000 */ +#define ETH_DMAC0RXCR_RXPBL_2PBL (0x2UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00020000 */ +#define ETH_DMAC0RXCR_RXPBL_4PBL (0x4UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00040000 */ +#define ETH_DMAC0RXCR_RXPBL_8PBL (0x8UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00080000 */ +#define ETH_DMAC0RXCR_RXPBL_16PBL (0x10UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00100000 */ +#define ETH_DMAC0RXCR_RXPBL_32PBL (0x20UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00200000 */ #define ETH_DMAC0RXCR_RQOS_Pos (24U) #define ETH_DMAC0RXCR_RQOS_Msk (0xFUL << ETH_DMAC0RXCR_RQOS_Pos) /*!< 0x0F000000 */ #define ETH_DMAC0RXCR_RQOS ETH_DMAC0RXCR_RQOS_Msk /*!< Rx AXI4 QOS. */ @@ -24555,6 +24583,16 @@ typedef struct #define BSEC_HWCFGR_ECC_USE_Msk (0xFUL << BSEC_HWCFGR_ECC_USE_Pos) /*!< 0x000000F0 */ #define BSEC_HWCFGR_ECC_USE BSEC_HWCFGR_ECC_USE_Msk /*!< protection / redundancy scheme used */ +/******************** Bit definition for BSEC_JTAGIN register ********************/ +#define BSEC_JTAGIN_DATA_Pos (0U) +#define BSEC_JTAGIN_DATA_Msk (0x0000FFFFUL << BSEC_JTAGIN_DATA_Pos) /*!< JTAG Input Data */ +#define BSEC_JTAGIN_DATA BSEC_JTAGIN_DATA_Msk + +/******************** Bit definition for BSEC_JTAGOUT register ********************/ +#define BSEC_JTAGOUT_DATA_Pos (0U) +#define BSEC_JTAGOUT_DATA_Msk (0x0000FFFFUL << BSEC_JTAGOUT_DATA_Pos) /*!< JTAG Output Data */ +#define BSEC_JTAGOUT_DATA BSEC_JTAGOUT_DATA_Msk + /******************** Bit definition for BSEC_VERR register********************/ #define BSEC_VERR_MINREV_Pos (0U) #define BSEC_VERR_MINREV_Msk (0xFUL << BSEC_VERR_MINREV_Pos) /*!< 0x0000000F */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157axx_ca7.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157axx_ca7.h index 0ddf5ab012..a4799ba120 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157axx_ca7.h +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157axx_ca7.h @@ -12379,16 +12379,19 @@ typedef struct #define ETH_MACCR_PRELEN_Pos (2U) #define ETH_MACCR_PRELEN_Msk (0x3UL << ETH_MACCR_PRELEN_Pos) /*!< 0x0000000C */ #define ETH_MACCR_PRELEN ETH_MACCR_PRELEN_Msk /*!< Preamble Length for Transmit packets */ -#define ETH_MACCR_PRELEN_0 (0x1UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000004 */ -#define ETH_MACCR_PRELEN_1 (0x2UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000008 */ +#define ETH_MACCR_PRELEN_7 (0x0UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000000 */ +#define ETH_MACCR_PRELEN_5 (0x1UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000004 */ +#define ETH_MACCR_PRELEN_3 (0x2UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000006 */ #define ETH_MACCR_DC_Pos (4U) #define ETH_MACCR_DC_Msk (0x1UL << ETH_MACCR_DC_Pos) /*!< 0x00000010 */ #define ETH_MACCR_DC ETH_MACCR_DC_Msk /*!< Deferral Check */ #define ETH_MACCR_BL_Pos (5U) #define ETH_MACCR_BL_Msk (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */ #define ETH_MACCR_BL ETH_MACCR_BL_Msk /*!< Back-Off Limit */ -#define ETH_MACCR_BL_0 (0x1UL << ETH_MACCR_BL_Pos) /*!< 0x00000020 */ -#define ETH_MACCR_BL_1 (0x2UL << ETH_MACCR_BL_Pos) /*!< 0x00000040 */ +#define ETH_MACCR_BL_10 (0x0UL << ETH_MACCR_BL_Pos) /*!< 0x00000000 */ +#define ETH_MACCR_BL_8 (0x1UL << ETH_MACCR_BL_Pos) /*!< 0x00000020 */ +#define ETH_MACCR_BL_4 (0x2UL << ETH_MACCR_BL_Pos) /*!< 0x00000040 */ +#define ETH_MACCR_BL_1 (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */ #define ETH_MACCR_DR_Pos (8U) #define ETH_MACCR_DR_Msk (0x1UL << ETH_MACCR_DR_Pos) /*!< 0x00000100 */ #define ETH_MACCR_DR ETH_MACCR_DR_Msk /*!< Disable Retry */ @@ -12440,9 +12443,14 @@ typedef struct #define ETH_MACCR_IPG_Pos (24U) #define ETH_MACCR_IPG_Msk (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */ #define ETH_MACCR_IPG ETH_MACCR_IPG_Msk /*!< Inter-Packet Gap */ -#define ETH_MACCR_IPG_0 (0x1UL << ETH_MACCR_IPG_Pos) /*!< 0x01000000 */ -#define ETH_MACCR_IPG_1 (0x2UL << ETH_MACCR_IPG_Pos) /*!< 0x02000000 */ -#define ETH_MACCR_IPG_2 (0x4UL << ETH_MACCR_IPG_Pos) /*!< 0x04000000 */ +#define ETH_MACCR_IPG_96BIT (0x0UL << ETH_MACCR_IPG_Pos) /*!< 0x00000000 */ +#define ETH_MACCR_IPG_88BIT (0x1UL << ETH_MACCR_IPG_Pos) /*!< 0x01000000 */ +#define ETH_MACCR_IPG_80BIT (0x2UL << ETH_MACCR_IPG_Pos) /*!< 0x02000000 */ +#define ETH_MACCR_IPG_72BIT (0x3UL << ETH_MACCR_IPG_Pos) /*!< 0x03000000 */ +#define ETH_MACCR_IPG_64BIT (0x4UL << ETH_MACCR_IPG_Pos) /*!< 0x04000000 */ +#define ETH_MACCR_IPG_56BIT (0x5UL << ETH_MACCR_IPG_Pos) /*!< 0x05000000 */ +#define ETH_MACCR_IPG_48BIT (0x6UL << ETH_MACCR_IPG_Pos) /*!< 0x06000000 */ +#define ETH_MACCR_IPG_40BIT (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */ #define ETH_MACCR_IPC_Pos (27U) #define ETH_MACCR_IPC_Msk (0x1UL << ETH_MACCR_IPC_Pos) /*!< 0x08000000 */ #define ETH_MACCR_IPC ETH_MACCR_IPC_Msk /*!< Checksum Offload */ @@ -12545,10 +12553,21 @@ typedef struct #define ETH_MACWTR_WTO_Pos (0U) #define ETH_MACWTR_WTO_Msk (0xFUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000F */ #define ETH_MACWTR_WTO ETH_MACWTR_WTO_Msk /*!< Watchdog Timeout */ -#define ETH_MACWTR_WTO_0 (0x1UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000001 */ -#define ETH_MACWTR_WTO_1 (0x2UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000002 */ -#define ETH_MACWTR_WTO_2 (0x4UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000004 */ -#define ETH_MACWTR_WTO_3 (0x8UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000008 */ +#define ETH_MACWTR_WTO_2KB (0x0UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000001 */ +#define ETH_MACWTR_WTO_3KB (0x1UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000001 */ +#define ETH_MACWTR_WTO_4KB (0x2UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000002 */ +#define ETH_MACWTR_WTO_5KB (0x3UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000003 */ +#define ETH_MACWTR_WTO_6KB (0x4UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000004 */ +#define ETH_MACWTR_WTO_7KB (0x5UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000005 */ +#define ETH_MACWTR_WTO_8KB (0x6UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000006 */ +#define ETH_MACWTR_WTO_9KB (0x7UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000007 */ +#define ETH_MACWTR_WTO_10KB (0x8UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000008 */ +#define ETH_MACWTR_WTO_11KB (0x9UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000009 */ +#define ETH_MACWTR_WTO_12KB (0xAUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000A */ +#define ETH_MACWTR_WTO_13KB (0xBUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000B */ +#define ETH_MACWTR_WTO_14KB (0xCUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000C */ +#define ETH_MACWTR_WTO_15KB (0xDUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000D */ +#define ETH_MACWTR_WTO_16KB (0xEUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000E */ #define ETH_MACWTR_PWE_Pos (8U) #define ETH_MACWTR_PWE_Msk (0x1UL << ETH_MACWTR_PWE_Pos) /*!< 0x00000100 */ #define ETH_MACWTR_PWE ETH_MACWTR_PWE_Msk /*!< Programmable Watchdog Enable */ @@ -12628,6 +12647,9 @@ typedef struct #define ETH_MACHT1R_HT63T32_31 (0x80000000UL << ETH_MACHT1R_HT63T32_Pos) /*!< 0x80000000 */ /************** Bit definition for ETH_MACVTR register ***************/ +#define ETH_MACVTR_VL_VID_Pos (0U) +#define ETH_MACVTR_VL_VID_Msk (0xFFFUL << ETH_MACVTR_VL_VID_Pos) /*!< 0x00000FFF */ +#define ETH_MACVTR_VL_VID ETH_MACVTR_VL_VID_Msk /*!< VLAN Tag Identifier field of VLAN tag */ #define ETH_MACVTR_VL_Pos (0U) #define ETH_MACVTR_VL_Msk (0xFFFFUL << ETH_MACVTR_VL_Pos) /*!< 0x0000FFFF */ #define ETH_MACVTR_VL ETH_MACVTR_VL_Msk /*!< VLAN Tag Identifier for Receive Packets */ @@ -12789,9 +12811,12 @@ typedef struct #define ETH_MACQ0TXFCR_PLT_Pos (4U) #define ETH_MACQ0TXFCR_PLT_Msk (0x7UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000070 */ #define ETH_MACQ0TXFCR_PLT ETH_MACQ0TXFCR_PLT_Msk /*!< Pause Low Threshold */ -#define ETH_MACQ0TXFCR_PLT_0 (0x1UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000010 */ -#define ETH_MACQ0TXFCR_PLT_1 (0x2UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000020 */ -#define ETH_MACQ0TXFCR_PLT_2 (0x4UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000040 */ +#define ETH_MACQ0TXFCR_PLT_MINUS4 (0x0UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000000 */ +#define ETH_MACQ0TXFCR_PLT_MINUS28 (0x1UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000010 */ +#define ETH_MACQ0TXFCR_PLT_MINUS36 (0x2UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000020 */ +#define ETH_MACQ0TXFCR_PLT_MINUS144 (0x3UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000030 */ +#define ETH_MACQ0TXFCR_PLT_MINUS256 (0x4UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000040 */ +#define ETH_MACQ0TXFCR_PLT_MINUS512 (0x5UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000050 */ #define ETH_MACQ0TXFCR_DZPQ_Pos (7U) #define ETH_MACQ0TXFCR_DZPQ_Msk (0x1UL << ETH_MACQ0TXFCR_DZPQ_Pos) /*!< 0x00000080 */ #define ETH_MACQ0TXFCR_DZPQ ETH_MACQ0TXFCR_DZPQ_Msk /*!< Disable Zero-Quanta Pause */ @@ -13358,10 +13383,12 @@ typedef struct #define ETH_MACMDIOAR_CR_Pos (8U) #define ETH_MACMDIOAR_CR_Msk (0xFUL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000F00 */ #define ETH_MACMDIOAR_CR ETH_MACMDIOAR_CR_Msk /*!< CSR Clock Range */ -#define ETH_MACMDIOAR_CR_0 (0x1UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000100 */ -#define ETH_MACMDIOAR_CR_1 (0x2UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000200 */ -#define ETH_MACMDIOAR_CR_2 (0x4UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000400 */ -#define ETH_MACMDIOAR_CR_3 (0x8UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000800 */ +#define ETH_MACMDIOAR_CR_DIV42 (0x0UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000000 */ +#define ETH_MACMDIOAR_CR_DIV62 (0x1UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000100 */ +#define ETH_MACMDIOAR_CR_DIV16 (0x2UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000200 */ +#define ETH_MACMDIOAR_CR_DIV26 (0x3UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000300 */ +#define ETH_MACMDIOAR_CR_DIV102 (0x4UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000400 */ +#define ETH_MACMDIOAR_CR_DIV124 (0x5UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000500 */ #define ETH_MACMDIOAR_NTC_Pos (12U) #define ETH_MACMDIOAR_NTC_Msk (0x7UL << ETH_MACMDIOAR_NTC_Pos) /*!< 0x00007000 */ #define ETH_MACMDIOAR_NTC ETH_MACMDIOAR_NTC_Msk /*!< Number of Training Clocks */ @@ -13800,7 +13827,7 @@ typedef struct #define ETH_MMCTXIMR_TXLPIUSCIM ETH_MMCTXIMR_TXLPIUSCIM_Msk /*!< MMC Transmit LPI microsecond counter interrupt Mask */ #define ETH_MMCTXIMR_TXLPITRCIM_Pos (27U) #define ETH_MMCTXIMR_TXLPITRCIM_Msk (0x1UL << ETH_MMCTXIMR_TXLPITRCIM_Pos) /*!< 0x08000000 */ -#define ETH_MMCTXIMR_TXLPITRCIM ETH_MMC_INTERRUPT_MASK_TXLPITRCIM_Msk /*!< MMC Transmit LPI transition counter interrupt Mask */ +#define ETH_MMCTXIMR_TXLPITRCIM ETH_MMCTXIMR_TXLPITRCIM_Msk /*!< MMC Transmit LPI transition counter interrupt Mask */ /*********** Bit definition for ETH_MMC_TX_SINGLE_COLLISION_GOOD_PACKETS register ************/ #define ETH_MMCTXSCGPR_TXSNGLCOLG_Pos (0U) @@ -16503,9 +16530,10 @@ typedef struct #define ETH_DMAC0CR_DSL_Pos (18U) #define ETH_DMAC0CR_DSL_Msk (0x7UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x001C0000 */ #define ETH_DMAC0CR_DSL ETH_DMAC0CR_DSL_Msk /*!< Descriptor Skip Length */ -#define ETH_DMAC0CR_DSL_0 (0x1UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00040000 */ -#define ETH_DMAC0CR_DSL_1 (0x2UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00080000 */ -#define ETH_DMAC0CR_DSL_2 (0x4UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00100000 */ +#define ETH_DMACCR_DSL_0BIT (0x0UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00000000 */ +#define ETH_DMACCR_DSL_32BIT (0x1UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00040000 */ +#define ETH_DMACCR_DSL_64BIT (0x2UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00080000 */ +#define ETH_DMACCR_DSL_128BIT (0x4UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00100000 */ /************* Bit definition for ETH_DMAC0TXCR register *************/ #define ETH_DMAC0TXCR_ST_Pos (0U) @@ -16526,12 +16554,12 @@ typedef struct #define ETH_DMAC0TXCR_TXPBL_Pos (16U) #define ETH_DMAC0TXCR_TXPBL_Msk (0x3FUL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x003F0000 */ #define ETH_DMAC0TXCR_TXPBL ETH_DMAC0TXCR_TXPBL_Msk /*!< Transmit Programmable Burst Length */ -#define ETH_DMAC0TXCR_TXPBL_0 (0x1UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00010000 */ -#define ETH_DMAC0TXCR_TXPBL_1 (0x2UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00020000 */ -#define ETH_DMAC0TXCR_TXPBL_2 (0x4UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00040000 */ -#define ETH_DMAC0TXCR_TXPBL_3 (0x8UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00080000 */ -#define ETH_DMAC0TXCR_TXPBL_4 (0x10UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00100000 */ -#define ETH_DMAC0TXCR_TXPBL_5 (0x20UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00200000 */ +#define ETH_DMAC0TXCR_TXPBL_1PBL (0x1UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00010000 */ +#define ETH_DMAC0TXCR_TXPBL_2PBL (0x2UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00020000 */ +#define ETH_DMAC0TXCR_TXPBL_4PBL (0x4UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00040000 */ +#define ETH_DMAC0TXCR_TXPBL_8PBL (0x8UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00080000 */ +#define ETH_DMAC0TXCR_TXPBL_16PBL (0x10UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00100000 */ +#define ETH_DMAC0TXCR_TXPBL_32PBL (0x20UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00200000 */ #define ETH_DMAC0TXCR_TQOS_Pos (24U) #define ETH_DMAC0TXCR_TQOS_Msk (0xFUL << ETH_DMAC0TXCR_TQOS_Pos) /*!< 0x0F000000 */ #define ETH_DMAC0TXCR_TQOS ETH_DMAC0TXCR_TQOS_Msk /*!< Transmit QOS. */ @@ -16564,12 +16592,12 @@ typedef struct #define ETH_DMAC0RXCR_RXPBL_Pos (16U) #define ETH_DMAC0RXCR_RXPBL_Msk (0x3FUL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x003F0000 */ #define ETH_DMAC0RXCR_RXPBL ETH_DMAC0RXCR_RXPBL_Msk /*!< Receive Programmable Burst Length */ -#define ETH_DMAC0RXCR_RXPBL_0 (0x1UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00010000 */ -#define ETH_DMAC0RXCR_RXPBL_1 (0x2UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00020000 */ -#define ETH_DMAC0RXCR_RXPBL_2 (0x4UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00040000 */ -#define ETH_DMAC0RXCR_RXPBL_3 (0x8UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00080000 */ -#define ETH_DMAC0RXCR_RXPBL_4 (0x10UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00100000 */ -#define ETH_DMAC0RXCR_RXPBL_5 (0x20UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00200000 */ +#define ETH_DMAC0RXCR_RXPBL_1PBL (0x1UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00010000 */ +#define ETH_DMAC0RXCR_RXPBL_2PBL (0x2UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00020000 */ +#define ETH_DMAC0RXCR_RXPBL_4PBL (0x4UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00040000 */ +#define ETH_DMAC0RXCR_RXPBL_8PBL (0x8UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00080000 */ +#define ETH_DMAC0RXCR_RXPBL_16PBL (0x10UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00100000 */ +#define ETH_DMAC0RXCR_RXPBL_32PBL (0x20UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00200000 */ #define ETH_DMAC0RXCR_RQOS_Pos (24U) #define ETH_DMAC0RXCR_RQOS_Msk (0xFUL << ETH_DMAC0RXCR_RQOS_Pos) /*!< 0x0F000000 */ #define ETH_DMAC0RXCR_RQOS ETH_DMAC0RXCR_RQOS_Msk /*!< Rx AXI4 QOS. */ @@ -25615,6 +25643,16 @@ typedef struct #define BSEC_HWCFGR_ECC_USE_Msk (0xFUL << BSEC_HWCFGR_ECC_USE_Pos) /*!< 0x000000F0 */ #define BSEC_HWCFGR_ECC_USE BSEC_HWCFGR_ECC_USE_Msk /*!< protection / redundancy scheme used */ +/******************** Bit definition for BSEC_JTAGIN register ********************/ +#define BSEC_JTAGIN_DATA_Pos (0U) +#define BSEC_JTAGIN_DATA_Msk (0x0000FFFFUL << BSEC_JTAGIN_DATA_Pos) /*!< JTAG Input Data */ +#define BSEC_JTAGIN_DATA BSEC_JTAGIN_DATA_Msk + +/******************** Bit definition for BSEC_JTAGOUT register ********************/ +#define BSEC_JTAGOUT_DATA_Pos (0U) +#define BSEC_JTAGOUT_DATA_Msk (0x0000FFFFUL << BSEC_JTAGOUT_DATA_Pos) /*!< JTAG Output Data */ +#define BSEC_JTAGOUT_DATA BSEC_JTAGOUT_DATA_Msk + /******************** Bit definition for BSEC_VERR register********************/ #define BSEC_VERR_MINREV_Pos (0U) #define BSEC_VERR_MINREV_Msk (0xFUL << BSEC_VERR_MINREV_Pos) /*!< 0x0000000F */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157axx_cm4.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157axx_cm4.h index 65eabb4c16..dff41df86c 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157axx_cm4.h +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157axx_cm4.h @@ -12345,16 +12345,19 @@ typedef struct #define ETH_MACCR_PRELEN_Pos (2U) #define ETH_MACCR_PRELEN_Msk (0x3UL << ETH_MACCR_PRELEN_Pos) /*!< 0x0000000C */ #define ETH_MACCR_PRELEN ETH_MACCR_PRELEN_Msk /*!< Preamble Length for Transmit packets */ -#define ETH_MACCR_PRELEN_0 (0x1UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000004 */ -#define ETH_MACCR_PRELEN_1 (0x2UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000008 */ +#define ETH_MACCR_PRELEN_7 (0x0UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000000 */ +#define ETH_MACCR_PRELEN_5 (0x1UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000004 */ +#define ETH_MACCR_PRELEN_3 (0x2UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000006 */ #define ETH_MACCR_DC_Pos (4U) #define ETH_MACCR_DC_Msk (0x1UL << ETH_MACCR_DC_Pos) /*!< 0x00000010 */ #define ETH_MACCR_DC ETH_MACCR_DC_Msk /*!< Deferral Check */ #define ETH_MACCR_BL_Pos (5U) #define ETH_MACCR_BL_Msk (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */ #define ETH_MACCR_BL ETH_MACCR_BL_Msk /*!< Back-Off Limit */ -#define ETH_MACCR_BL_0 (0x1UL << ETH_MACCR_BL_Pos) /*!< 0x00000020 */ -#define ETH_MACCR_BL_1 (0x2UL << ETH_MACCR_BL_Pos) /*!< 0x00000040 */ +#define ETH_MACCR_BL_10 (0x0UL << ETH_MACCR_BL_Pos) /*!< 0x00000000 */ +#define ETH_MACCR_BL_8 (0x1UL << ETH_MACCR_BL_Pos) /*!< 0x00000020 */ +#define ETH_MACCR_BL_4 (0x2UL << ETH_MACCR_BL_Pos) /*!< 0x00000040 */ +#define ETH_MACCR_BL_1 (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */ #define ETH_MACCR_DR_Pos (8U) #define ETH_MACCR_DR_Msk (0x1UL << ETH_MACCR_DR_Pos) /*!< 0x00000100 */ #define ETH_MACCR_DR ETH_MACCR_DR_Msk /*!< Disable Retry */ @@ -12406,9 +12409,14 @@ typedef struct #define ETH_MACCR_IPG_Pos (24U) #define ETH_MACCR_IPG_Msk (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */ #define ETH_MACCR_IPG ETH_MACCR_IPG_Msk /*!< Inter-Packet Gap */ -#define ETH_MACCR_IPG_0 (0x1UL << ETH_MACCR_IPG_Pos) /*!< 0x01000000 */ -#define ETH_MACCR_IPG_1 (0x2UL << ETH_MACCR_IPG_Pos) /*!< 0x02000000 */ -#define ETH_MACCR_IPG_2 (0x4UL << ETH_MACCR_IPG_Pos) /*!< 0x04000000 */ +#define ETH_MACCR_IPG_96BIT (0x0UL << ETH_MACCR_IPG_Pos) /*!< 0x00000000 */ +#define ETH_MACCR_IPG_88BIT (0x1UL << ETH_MACCR_IPG_Pos) /*!< 0x01000000 */ +#define ETH_MACCR_IPG_80BIT (0x2UL << ETH_MACCR_IPG_Pos) /*!< 0x02000000 */ +#define ETH_MACCR_IPG_72BIT (0x3UL << ETH_MACCR_IPG_Pos) /*!< 0x03000000 */ +#define ETH_MACCR_IPG_64BIT (0x4UL << ETH_MACCR_IPG_Pos) /*!< 0x04000000 */ +#define ETH_MACCR_IPG_56BIT (0x5UL << ETH_MACCR_IPG_Pos) /*!< 0x05000000 */ +#define ETH_MACCR_IPG_48BIT (0x6UL << ETH_MACCR_IPG_Pos) /*!< 0x06000000 */ +#define ETH_MACCR_IPG_40BIT (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */ #define ETH_MACCR_IPC_Pos (27U) #define ETH_MACCR_IPC_Msk (0x1UL << ETH_MACCR_IPC_Pos) /*!< 0x08000000 */ #define ETH_MACCR_IPC ETH_MACCR_IPC_Msk /*!< Checksum Offload */ @@ -12511,10 +12519,21 @@ typedef struct #define ETH_MACWTR_WTO_Pos (0U) #define ETH_MACWTR_WTO_Msk (0xFUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000F */ #define ETH_MACWTR_WTO ETH_MACWTR_WTO_Msk /*!< Watchdog Timeout */ -#define ETH_MACWTR_WTO_0 (0x1UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000001 */ -#define ETH_MACWTR_WTO_1 (0x2UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000002 */ -#define ETH_MACWTR_WTO_2 (0x4UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000004 */ -#define ETH_MACWTR_WTO_3 (0x8UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000008 */ +#define ETH_MACWTR_WTO_2KB (0x0UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000001 */ +#define ETH_MACWTR_WTO_3KB (0x1UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000001 */ +#define ETH_MACWTR_WTO_4KB (0x2UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000002 */ +#define ETH_MACWTR_WTO_5KB (0x3UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000003 */ +#define ETH_MACWTR_WTO_6KB (0x4UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000004 */ +#define ETH_MACWTR_WTO_7KB (0x5UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000005 */ +#define ETH_MACWTR_WTO_8KB (0x6UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000006 */ +#define ETH_MACWTR_WTO_9KB (0x7UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000007 */ +#define ETH_MACWTR_WTO_10KB (0x8UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000008 */ +#define ETH_MACWTR_WTO_11KB (0x9UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000009 */ +#define ETH_MACWTR_WTO_12KB (0xAUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000A */ +#define ETH_MACWTR_WTO_13KB (0xBUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000B */ +#define ETH_MACWTR_WTO_14KB (0xCUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000C */ +#define ETH_MACWTR_WTO_15KB (0xDUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000D */ +#define ETH_MACWTR_WTO_16KB (0xEUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000E */ #define ETH_MACWTR_PWE_Pos (8U) #define ETH_MACWTR_PWE_Msk (0x1UL << ETH_MACWTR_PWE_Pos) /*!< 0x00000100 */ #define ETH_MACWTR_PWE ETH_MACWTR_PWE_Msk /*!< Programmable Watchdog Enable */ @@ -12594,6 +12613,9 @@ typedef struct #define ETH_MACHT1R_HT63T32_31 (0x80000000UL << ETH_MACHT1R_HT63T32_Pos) /*!< 0x80000000 */ /************** Bit definition for ETH_MACVTR register ***************/ +#define ETH_MACVTR_VL_VID_Pos (0U) +#define ETH_MACVTR_VL_VID_Msk (0xFFFUL << ETH_MACVTR_VL_VID_Pos) /*!< 0x00000FFF */ +#define ETH_MACVTR_VL_VID ETH_MACVTR_VL_VID_Msk /*!< VLAN Tag Identifier field of VLAN tag */ #define ETH_MACVTR_VL_Pos (0U) #define ETH_MACVTR_VL_Msk (0xFFFFUL << ETH_MACVTR_VL_Pos) /*!< 0x0000FFFF */ #define ETH_MACVTR_VL ETH_MACVTR_VL_Msk /*!< VLAN Tag Identifier for Receive Packets */ @@ -12755,9 +12777,12 @@ typedef struct #define ETH_MACQ0TXFCR_PLT_Pos (4U) #define ETH_MACQ0TXFCR_PLT_Msk (0x7UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000070 */ #define ETH_MACQ0TXFCR_PLT ETH_MACQ0TXFCR_PLT_Msk /*!< Pause Low Threshold */ -#define ETH_MACQ0TXFCR_PLT_0 (0x1UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000010 */ -#define ETH_MACQ0TXFCR_PLT_1 (0x2UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000020 */ -#define ETH_MACQ0TXFCR_PLT_2 (0x4UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000040 */ +#define ETH_MACQ0TXFCR_PLT_MINUS4 (0x0UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000000 */ +#define ETH_MACQ0TXFCR_PLT_MINUS28 (0x1UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000010 */ +#define ETH_MACQ0TXFCR_PLT_MINUS36 (0x2UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000020 */ +#define ETH_MACQ0TXFCR_PLT_MINUS144 (0x3UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000030 */ +#define ETH_MACQ0TXFCR_PLT_MINUS256 (0x4UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000040 */ +#define ETH_MACQ0TXFCR_PLT_MINUS512 (0x5UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000050 */ #define ETH_MACQ0TXFCR_DZPQ_Pos (7U) #define ETH_MACQ0TXFCR_DZPQ_Msk (0x1UL << ETH_MACQ0TXFCR_DZPQ_Pos) /*!< 0x00000080 */ #define ETH_MACQ0TXFCR_DZPQ ETH_MACQ0TXFCR_DZPQ_Msk /*!< Disable Zero-Quanta Pause */ @@ -13324,10 +13349,12 @@ typedef struct #define ETH_MACMDIOAR_CR_Pos (8U) #define ETH_MACMDIOAR_CR_Msk (0xFUL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000F00 */ #define ETH_MACMDIOAR_CR ETH_MACMDIOAR_CR_Msk /*!< CSR Clock Range */ -#define ETH_MACMDIOAR_CR_0 (0x1UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000100 */ -#define ETH_MACMDIOAR_CR_1 (0x2UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000200 */ -#define ETH_MACMDIOAR_CR_2 (0x4UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000400 */ -#define ETH_MACMDIOAR_CR_3 (0x8UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000800 */ +#define ETH_MACMDIOAR_CR_DIV42 (0x0UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000000 */ +#define ETH_MACMDIOAR_CR_DIV62 (0x1UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000100 */ +#define ETH_MACMDIOAR_CR_DIV16 (0x2UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000200 */ +#define ETH_MACMDIOAR_CR_DIV26 (0x3UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000300 */ +#define ETH_MACMDIOAR_CR_DIV102 (0x4UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000400 */ +#define ETH_MACMDIOAR_CR_DIV124 (0x5UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000500 */ #define ETH_MACMDIOAR_NTC_Pos (12U) #define ETH_MACMDIOAR_NTC_Msk (0x7UL << ETH_MACMDIOAR_NTC_Pos) /*!< 0x00007000 */ #define ETH_MACMDIOAR_NTC ETH_MACMDIOAR_NTC_Msk /*!< Number of Training Clocks */ @@ -13766,7 +13793,7 @@ typedef struct #define ETH_MMCTXIMR_TXLPIUSCIM ETH_MMCTXIMR_TXLPIUSCIM_Msk /*!< MMC Transmit LPI microsecond counter interrupt Mask */ #define ETH_MMCTXIMR_TXLPITRCIM_Pos (27U) #define ETH_MMCTXIMR_TXLPITRCIM_Msk (0x1UL << ETH_MMCTXIMR_TXLPITRCIM_Pos) /*!< 0x08000000 */ -#define ETH_MMCTXIMR_TXLPITRCIM ETH_MMC_INTERRUPT_MASK_TXLPITRCIM_Msk /*!< MMC Transmit LPI transition counter interrupt Mask */ +#define ETH_MMCTXIMR_TXLPITRCIM ETH_MMCTXIMR_TXLPITRCIM_Msk /*!< MMC Transmit LPI transition counter interrupt Mask */ /*********** Bit definition for ETH_MMC_TX_SINGLE_COLLISION_GOOD_PACKETS register ************/ #define ETH_MMCTXSCGPR_TXSNGLCOLG_Pos (0U) @@ -16469,9 +16496,10 @@ typedef struct #define ETH_DMAC0CR_DSL_Pos (18U) #define ETH_DMAC0CR_DSL_Msk (0x7UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x001C0000 */ #define ETH_DMAC0CR_DSL ETH_DMAC0CR_DSL_Msk /*!< Descriptor Skip Length */ -#define ETH_DMAC0CR_DSL_0 (0x1UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00040000 */ -#define ETH_DMAC0CR_DSL_1 (0x2UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00080000 */ -#define ETH_DMAC0CR_DSL_2 (0x4UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00100000 */ +#define ETH_DMACCR_DSL_0BIT (0x0UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00000000 */ +#define ETH_DMACCR_DSL_32BIT (0x1UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00040000 */ +#define ETH_DMACCR_DSL_64BIT (0x2UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00080000 */ +#define ETH_DMACCR_DSL_128BIT (0x4UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00100000 */ /************* Bit definition for ETH_DMAC0TXCR register *************/ #define ETH_DMAC0TXCR_ST_Pos (0U) @@ -16492,12 +16520,12 @@ typedef struct #define ETH_DMAC0TXCR_TXPBL_Pos (16U) #define ETH_DMAC0TXCR_TXPBL_Msk (0x3FUL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x003F0000 */ #define ETH_DMAC0TXCR_TXPBL ETH_DMAC0TXCR_TXPBL_Msk /*!< Transmit Programmable Burst Length */ -#define ETH_DMAC0TXCR_TXPBL_0 (0x1UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00010000 */ -#define ETH_DMAC0TXCR_TXPBL_1 (0x2UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00020000 */ -#define ETH_DMAC0TXCR_TXPBL_2 (0x4UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00040000 */ -#define ETH_DMAC0TXCR_TXPBL_3 (0x8UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00080000 */ -#define ETH_DMAC0TXCR_TXPBL_4 (0x10UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00100000 */ -#define ETH_DMAC0TXCR_TXPBL_5 (0x20UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00200000 */ +#define ETH_DMAC0TXCR_TXPBL_1PBL (0x1UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00010000 */ +#define ETH_DMAC0TXCR_TXPBL_2PBL (0x2UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00020000 */ +#define ETH_DMAC0TXCR_TXPBL_4PBL (0x4UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00040000 */ +#define ETH_DMAC0TXCR_TXPBL_8PBL (0x8UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00080000 */ +#define ETH_DMAC0TXCR_TXPBL_16PBL (0x10UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00100000 */ +#define ETH_DMAC0TXCR_TXPBL_32PBL (0x20UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00200000 */ #define ETH_DMAC0TXCR_TQOS_Pos (24U) #define ETH_DMAC0TXCR_TQOS_Msk (0xFUL << ETH_DMAC0TXCR_TQOS_Pos) /*!< 0x0F000000 */ #define ETH_DMAC0TXCR_TQOS ETH_DMAC0TXCR_TQOS_Msk /*!< Transmit QOS. */ @@ -16530,12 +16558,12 @@ typedef struct #define ETH_DMAC0RXCR_RXPBL_Pos (16U) #define ETH_DMAC0RXCR_RXPBL_Msk (0x3FUL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x003F0000 */ #define ETH_DMAC0RXCR_RXPBL ETH_DMAC0RXCR_RXPBL_Msk /*!< Receive Programmable Burst Length */ -#define ETH_DMAC0RXCR_RXPBL_0 (0x1UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00010000 */ -#define ETH_DMAC0RXCR_RXPBL_1 (0x2UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00020000 */ -#define ETH_DMAC0RXCR_RXPBL_2 (0x4UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00040000 */ -#define ETH_DMAC0RXCR_RXPBL_3 (0x8UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00080000 */ -#define ETH_DMAC0RXCR_RXPBL_4 (0x10UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00100000 */ -#define ETH_DMAC0RXCR_RXPBL_5 (0x20UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00200000 */ +#define ETH_DMAC0RXCR_RXPBL_1PBL (0x1UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00010000 */ +#define ETH_DMAC0RXCR_RXPBL_2PBL (0x2UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00020000 */ +#define ETH_DMAC0RXCR_RXPBL_4PBL (0x4UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00040000 */ +#define ETH_DMAC0RXCR_RXPBL_8PBL (0x8UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00080000 */ +#define ETH_DMAC0RXCR_RXPBL_16PBL (0x10UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00100000 */ +#define ETH_DMAC0RXCR_RXPBL_32PBL (0x20UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00200000 */ #define ETH_DMAC0RXCR_RQOS_Pos (24U) #define ETH_DMAC0RXCR_RQOS_Msk (0xFUL << ETH_DMAC0RXCR_RQOS_Pos) /*!< 0x0F000000 */ #define ETH_DMAC0RXCR_RQOS ETH_DMAC0RXCR_RQOS_Msk /*!< Rx AXI4 QOS. */ @@ -25581,6 +25609,16 @@ typedef struct #define BSEC_HWCFGR_ECC_USE_Msk (0xFUL << BSEC_HWCFGR_ECC_USE_Pos) /*!< 0x000000F0 */ #define BSEC_HWCFGR_ECC_USE BSEC_HWCFGR_ECC_USE_Msk /*!< protection / redundancy scheme used */ +/******************** Bit definition for BSEC_JTAGIN register ********************/ +#define BSEC_JTAGIN_DATA_Pos (0U) +#define BSEC_JTAGIN_DATA_Msk (0x0000FFFFUL << BSEC_JTAGIN_DATA_Pos) /*!< JTAG Input Data */ +#define BSEC_JTAGIN_DATA BSEC_JTAGIN_DATA_Msk + +/******************** Bit definition for BSEC_JTAGOUT register ********************/ +#define BSEC_JTAGOUT_DATA_Pos (0U) +#define BSEC_JTAGOUT_DATA_Msk (0x0000FFFFUL << BSEC_JTAGOUT_DATA_Pos) /*!< JTAG Output Data */ +#define BSEC_JTAGOUT_DATA BSEC_JTAGOUT_DATA_Msk + /******************** Bit definition for BSEC_VERR register********************/ #define BSEC_VERR_MINREV_Pos (0U) #define BSEC_VERR_MINREV_Msk (0xFUL << BSEC_VERR_MINREV_Pos) /*!< 0x0000000F */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157cxx_ca7.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157cxx_ca7.h index 0a4be66a43..037be04358 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157cxx_ca7.h +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157cxx_ca7.h @@ -12576,16 +12576,19 @@ typedef struct #define ETH_MACCR_PRELEN_Pos (2U) #define ETH_MACCR_PRELEN_Msk (0x3UL << ETH_MACCR_PRELEN_Pos) /*!< 0x0000000C */ #define ETH_MACCR_PRELEN ETH_MACCR_PRELEN_Msk /*!< Preamble Length for Transmit packets */ -#define ETH_MACCR_PRELEN_0 (0x1UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000004 */ -#define ETH_MACCR_PRELEN_1 (0x2UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000008 */ +#define ETH_MACCR_PRELEN_7 (0x0UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000000 */ +#define ETH_MACCR_PRELEN_5 (0x1UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000004 */ +#define ETH_MACCR_PRELEN_3 (0x2UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000006 */ #define ETH_MACCR_DC_Pos (4U) #define ETH_MACCR_DC_Msk (0x1UL << ETH_MACCR_DC_Pos) /*!< 0x00000010 */ #define ETH_MACCR_DC ETH_MACCR_DC_Msk /*!< Deferral Check */ #define ETH_MACCR_BL_Pos (5U) #define ETH_MACCR_BL_Msk (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */ #define ETH_MACCR_BL ETH_MACCR_BL_Msk /*!< Back-Off Limit */ -#define ETH_MACCR_BL_0 (0x1UL << ETH_MACCR_BL_Pos) /*!< 0x00000020 */ -#define ETH_MACCR_BL_1 (0x2UL << ETH_MACCR_BL_Pos) /*!< 0x00000040 */ +#define ETH_MACCR_BL_10 (0x0UL << ETH_MACCR_BL_Pos) /*!< 0x00000000 */ +#define ETH_MACCR_BL_8 (0x1UL << ETH_MACCR_BL_Pos) /*!< 0x00000020 */ +#define ETH_MACCR_BL_4 (0x2UL << ETH_MACCR_BL_Pos) /*!< 0x00000040 */ +#define ETH_MACCR_BL_1 (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */ #define ETH_MACCR_DR_Pos (8U) #define ETH_MACCR_DR_Msk (0x1UL << ETH_MACCR_DR_Pos) /*!< 0x00000100 */ #define ETH_MACCR_DR ETH_MACCR_DR_Msk /*!< Disable Retry */ @@ -12637,9 +12640,14 @@ typedef struct #define ETH_MACCR_IPG_Pos (24U) #define ETH_MACCR_IPG_Msk (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */ #define ETH_MACCR_IPG ETH_MACCR_IPG_Msk /*!< Inter-Packet Gap */ -#define ETH_MACCR_IPG_0 (0x1UL << ETH_MACCR_IPG_Pos) /*!< 0x01000000 */ -#define ETH_MACCR_IPG_1 (0x2UL << ETH_MACCR_IPG_Pos) /*!< 0x02000000 */ -#define ETH_MACCR_IPG_2 (0x4UL << ETH_MACCR_IPG_Pos) /*!< 0x04000000 */ +#define ETH_MACCR_IPG_96BIT (0x0UL << ETH_MACCR_IPG_Pos) /*!< 0x00000000 */ +#define ETH_MACCR_IPG_88BIT (0x1UL << ETH_MACCR_IPG_Pos) /*!< 0x01000000 */ +#define ETH_MACCR_IPG_80BIT (0x2UL << ETH_MACCR_IPG_Pos) /*!< 0x02000000 */ +#define ETH_MACCR_IPG_72BIT (0x3UL << ETH_MACCR_IPG_Pos) /*!< 0x03000000 */ +#define ETH_MACCR_IPG_64BIT (0x4UL << ETH_MACCR_IPG_Pos) /*!< 0x04000000 */ +#define ETH_MACCR_IPG_56BIT (0x5UL << ETH_MACCR_IPG_Pos) /*!< 0x05000000 */ +#define ETH_MACCR_IPG_48BIT (0x6UL << ETH_MACCR_IPG_Pos) /*!< 0x06000000 */ +#define ETH_MACCR_IPG_40BIT (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */ #define ETH_MACCR_IPC_Pos (27U) #define ETH_MACCR_IPC_Msk (0x1UL << ETH_MACCR_IPC_Pos) /*!< 0x08000000 */ #define ETH_MACCR_IPC ETH_MACCR_IPC_Msk /*!< Checksum Offload */ @@ -12742,10 +12750,21 @@ typedef struct #define ETH_MACWTR_WTO_Pos (0U) #define ETH_MACWTR_WTO_Msk (0xFUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000F */ #define ETH_MACWTR_WTO ETH_MACWTR_WTO_Msk /*!< Watchdog Timeout */ -#define ETH_MACWTR_WTO_0 (0x1UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000001 */ -#define ETH_MACWTR_WTO_1 (0x2UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000002 */ -#define ETH_MACWTR_WTO_2 (0x4UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000004 */ -#define ETH_MACWTR_WTO_3 (0x8UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000008 */ +#define ETH_MACWTR_WTO_2KB (0x0UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000001 */ +#define ETH_MACWTR_WTO_3KB (0x1UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000001 */ +#define ETH_MACWTR_WTO_4KB (0x2UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000002 */ +#define ETH_MACWTR_WTO_5KB (0x3UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000003 */ +#define ETH_MACWTR_WTO_6KB (0x4UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000004 */ +#define ETH_MACWTR_WTO_7KB (0x5UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000005 */ +#define ETH_MACWTR_WTO_8KB (0x6UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000006 */ +#define ETH_MACWTR_WTO_9KB (0x7UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000007 */ +#define ETH_MACWTR_WTO_10KB (0x8UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000008 */ +#define ETH_MACWTR_WTO_11KB (0x9UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000009 */ +#define ETH_MACWTR_WTO_12KB (0xAUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000A */ +#define ETH_MACWTR_WTO_13KB (0xBUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000B */ +#define ETH_MACWTR_WTO_14KB (0xCUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000C */ +#define ETH_MACWTR_WTO_15KB (0xDUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000D */ +#define ETH_MACWTR_WTO_16KB (0xEUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000E */ #define ETH_MACWTR_PWE_Pos (8U) #define ETH_MACWTR_PWE_Msk (0x1UL << ETH_MACWTR_PWE_Pos) /*!< 0x00000100 */ #define ETH_MACWTR_PWE ETH_MACWTR_PWE_Msk /*!< Programmable Watchdog Enable */ @@ -12825,6 +12844,9 @@ typedef struct #define ETH_MACHT1R_HT63T32_31 (0x80000000UL << ETH_MACHT1R_HT63T32_Pos) /*!< 0x80000000 */ /************** Bit definition for ETH_MACVTR register ***************/ +#define ETH_MACVTR_VL_VID_Pos (0U) +#define ETH_MACVTR_VL_VID_Msk (0xFFFUL << ETH_MACVTR_VL_VID_Pos) /*!< 0x00000FFF */ +#define ETH_MACVTR_VL_VID ETH_MACVTR_VL_VID_Msk /*!< VLAN Tag Identifier field of VLAN tag */ #define ETH_MACVTR_VL_Pos (0U) #define ETH_MACVTR_VL_Msk (0xFFFFUL << ETH_MACVTR_VL_Pos) /*!< 0x0000FFFF */ #define ETH_MACVTR_VL ETH_MACVTR_VL_Msk /*!< VLAN Tag Identifier for Receive Packets */ @@ -12986,9 +13008,12 @@ typedef struct #define ETH_MACQ0TXFCR_PLT_Pos (4U) #define ETH_MACQ0TXFCR_PLT_Msk (0x7UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000070 */ #define ETH_MACQ0TXFCR_PLT ETH_MACQ0TXFCR_PLT_Msk /*!< Pause Low Threshold */ -#define ETH_MACQ0TXFCR_PLT_0 (0x1UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000010 */ -#define ETH_MACQ0TXFCR_PLT_1 (0x2UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000020 */ -#define ETH_MACQ0TXFCR_PLT_2 (0x4UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000040 */ +#define ETH_MACQ0TXFCR_PLT_MINUS4 (0x0UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000000 */ +#define ETH_MACQ0TXFCR_PLT_MINUS28 (0x1UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000010 */ +#define ETH_MACQ0TXFCR_PLT_MINUS36 (0x2UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000020 */ +#define ETH_MACQ0TXFCR_PLT_MINUS144 (0x3UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000030 */ +#define ETH_MACQ0TXFCR_PLT_MINUS256 (0x4UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000040 */ +#define ETH_MACQ0TXFCR_PLT_MINUS512 (0x5UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000050 */ #define ETH_MACQ0TXFCR_DZPQ_Pos (7U) #define ETH_MACQ0TXFCR_DZPQ_Msk (0x1UL << ETH_MACQ0TXFCR_DZPQ_Pos) /*!< 0x00000080 */ #define ETH_MACQ0TXFCR_DZPQ ETH_MACQ0TXFCR_DZPQ_Msk /*!< Disable Zero-Quanta Pause */ @@ -13555,10 +13580,12 @@ typedef struct #define ETH_MACMDIOAR_CR_Pos (8U) #define ETH_MACMDIOAR_CR_Msk (0xFUL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000F00 */ #define ETH_MACMDIOAR_CR ETH_MACMDIOAR_CR_Msk /*!< CSR Clock Range */ -#define ETH_MACMDIOAR_CR_0 (0x1UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000100 */ -#define ETH_MACMDIOAR_CR_1 (0x2UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000200 */ -#define ETH_MACMDIOAR_CR_2 (0x4UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000400 */ -#define ETH_MACMDIOAR_CR_3 (0x8UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000800 */ +#define ETH_MACMDIOAR_CR_DIV42 (0x0UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000000 */ +#define ETH_MACMDIOAR_CR_DIV62 (0x1UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000100 */ +#define ETH_MACMDIOAR_CR_DIV16 (0x2UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000200 */ +#define ETH_MACMDIOAR_CR_DIV26 (0x3UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000300 */ +#define ETH_MACMDIOAR_CR_DIV102 (0x4UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000400 */ +#define ETH_MACMDIOAR_CR_DIV124 (0x5UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000500 */ #define ETH_MACMDIOAR_NTC_Pos (12U) #define ETH_MACMDIOAR_NTC_Msk (0x7UL << ETH_MACMDIOAR_NTC_Pos) /*!< 0x00007000 */ #define ETH_MACMDIOAR_NTC ETH_MACMDIOAR_NTC_Msk /*!< Number of Training Clocks */ @@ -13997,7 +14024,7 @@ typedef struct #define ETH_MMCTXIMR_TXLPIUSCIM ETH_MMCTXIMR_TXLPIUSCIM_Msk /*!< MMC Transmit LPI microsecond counter interrupt Mask */ #define ETH_MMCTXIMR_TXLPITRCIM_Pos (27U) #define ETH_MMCTXIMR_TXLPITRCIM_Msk (0x1UL << ETH_MMCTXIMR_TXLPITRCIM_Pos) /*!< 0x08000000 */ -#define ETH_MMCTXIMR_TXLPITRCIM ETH_MMC_INTERRUPT_MASK_TXLPITRCIM_Msk /*!< MMC Transmit LPI transition counter interrupt Mask */ +#define ETH_MMCTXIMR_TXLPITRCIM ETH_MMCTXIMR_TXLPITRCIM_Msk /*!< MMC Transmit LPI transition counter interrupt Mask */ /*********** Bit definition for ETH_MMC_TX_SINGLE_COLLISION_GOOD_PACKETS register ************/ #define ETH_MMCTXSCGPR_TXSNGLCOLG_Pos (0U) @@ -16700,9 +16727,10 @@ typedef struct #define ETH_DMAC0CR_DSL_Pos (18U) #define ETH_DMAC0CR_DSL_Msk (0x7UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x001C0000 */ #define ETH_DMAC0CR_DSL ETH_DMAC0CR_DSL_Msk /*!< Descriptor Skip Length */ -#define ETH_DMAC0CR_DSL_0 (0x1UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00040000 */ -#define ETH_DMAC0CR_DSL_1 (0x2UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00080000 */ -#define ETH_DMAC0CR_DSL_2 (0x4UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00100000 */ +#define ETH_DMACCR_DSL_0BIT (0x0UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00000000 */ +#define ETH_DMACCR_DSL_32BIT (0x1UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00040000 */ +#define ETH_DMACCR_DSL_64BIT (0x2UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00080000 */ +#define ETH_DMACCR_DSL_128BIT (0x4UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00100000 */ /************* Bit definition for ETH_DMAC0TXCR register *************/ #define ETH_DMAC0TXCR_ST_Pos (0U) @@ -16723,12 +16751,12 @@ typedef struct #define ETH_DMAC0TXCR_TXPBL_Pos (16U) #define ETH_DMAC0TXCR_TXPBL_Msk (0x3FUL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x003F0000 */ #define ETH_DMAC0TXCR_TXPBL ETH_DMAC0TXCR_TXPBL_Msk /*!< Transmit Programmable Burst Length */ -#define ETH_DMAC0TXCR_TXPBL_0 (0x1UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00010000 */ -#define ETH_DMAC0TXCR_TXPBL_1 (0x2UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00020000 */ -#define ETH_DMAC0TXCR_TXPBL_2 (0x4UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00040000 */ -#define ETH_DMAC0TXCR_TXPBL_3 (0x8UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00080000 */ -#define ETH_DMAC0TXCR_TXPBL_4 (0x10UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00100000 */ -#define ETH_DMAC0TXCR_TXPBL_5 (0x20UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00200000 */ +#define ETH_DMAC0TXCR_TXPBL_1PBL (0x1UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00010000 */ +#define ETH_DMAC0TXCR_TXPBL_2PBL (0x2UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00020000 */ +#define ETH_DMAC0TXCR_TXPBL_4PBL (0x4UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00040000 */ +#define ETH_DMAC0TXCR_TXPBL_8PBL (0x8UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00080000 */ +#define ETH_DMAC0TXCR_TXPBL_16PBL (0x10UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00100000 */ +#define ETH_DMAC0TXCR_TXPBL_32PBL (0x20UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00200000 */ #define ETH_DMAC0TXCR_TQOS_Pos (24U) #define ETH_DMAC0TXCR_TQOS_Msk (0xFUL << ETH_DMAC0TXCR_TQOS_Pos) /*!< 0x0F000000 */ #define ETH_DMAC0TXCR_TQOS ETH_DMAC0TXCR_TQOS_Msk /*!< Transmit QOS. */ @@ -16761,12 +16789,12 @@ typedef struct #define ETH_DMAC0RXCR_RXPBL_Pos (16U) #define ETH_DMAC0RXCR_RXPBL_Msk (0x3FUL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x003F0000 */ #define ETH_DMAC0RXCR_RXPBL ETH_DMAC0RXCR_RXPBL_Msk /*!< Receive Programmable Burst Length */ -#define ETH_DMAC0RXCR_RXPBL_0 (0x1UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00010000 */ -#define ETH_DMAC0RXCR_RXPBL_1 (0x2UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00020000 */ -#define ETH_DMAC0RXCR_RXPBL_2 (0x4UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00040000 */ -#define ETH_DMAC0RXCR_RXPBL_3 (0x8UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00080000 */ -#define ETH_DMAC0RXCR_RXPBL_4 (0x10UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00100000 */ -#define ETH_DMAC0RXCR_RXPBL_5 (0x20UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00200000 */ +#define ETH_DMAC0RXCR_RXPBL_1PBL (0x1UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00010000 */ +#define ETH_DMAC0RXCR_RXPBL_2PBL (0x2UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00020000 */ +#define ETH_DMAC0RXCR_RXPBL_4PBL (0x4UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00040000 */ +#define ETH_DMAC0RXCR_RXPBL_8PBL (0x8UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00080000 */ +#define ETH_DMAC0RXCR_RXPBL_16PBL (0x10UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00100000 */ +#define ETH_DMAC0RXCR_RXPBL_32PBL (0x20UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00200000 */ #define ETH_DMAC0RXCR_RQOS_Pos (24U) #define ETH_DMAC0RXCR_RQOS_Msk (0xFUL << ETH_DMAC0RXCR_RQOS_Pos) /*!< 0x0F000000 */ #define ETH_DMAC0RXCR_RQOS ETH_DMAC0RXCR_RQOS_Msk /*!< Rx AXI4 QOS. */ @@ -25812,6 +25840,16 @@ typedef struct #define BSEC_HWCFGR_ECC_USE_Msk (0xFUL << BSEC_HWCFGR_ECC_USE_Pos) /*!< 0x000000F0 */ #define BSEC_HWCFGR_ECC_USE BSEC_HWCFGR_ECC_USE_Msk /*!< protection / redundancy scheme used */ +/******************** Bit definition for BSEC_JTAGIN register ********************/ +#define BSEC_JTAGIN_DATA_Pos (0U) +#define BSEC_JTAGIN_DATA_Msk (0x0000FFFFUL << BSEC_JTAGIN_DATA_Pos) /*!< JTAG Input Data */ +#define BSEC_JTAGIN_DATA BSEC_JTAGIN_DATA_Msk + +/******************** Bit definition for BSEC_JTAGOUT register ********************/ +#define BSEC_JTAGOUT_DATA_Pos (0U) +#define BSEC_JTAGOUT_DATA_Msk (0x0000FFFFUL << BSEC_JTAGOUT_DATA_Pos) /*!< JTAG Output Data */ +#define BSEC_JTAGOUT_DATA BSEC_JTAGOUT_DATA_Msk + /******************** Bit definition for BSEC_VERR register********************/ #define BSEC_VERR_MINREV_Pos (0U) #define BSEC_VERR_MINREV_Msk (0xFUL << BSEC_VERR_MINREV_Pos) /*!< 0x0000000F */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157cxx_cm4.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157cxx_cm4.h index 376c30be89..cfe0c83387 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157cxx_cm4.h +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157cxx_cm4.h @@ -12542,16 +12542,19 @@ typedef struct #define ETH_MACCR_PRELEN_Pos (2U) #define ETH_MACCR_PRELEN_Msk (0x3UL << ETH_MACCR_PRELEN_Pos) /*!< 0x0000000C */ #define ETH_MACCR_PRELEN ETH_MACCR_PRELEN_Msk /*!< Preamble Length for Transmit packets */ -#define ETH_MACCR_PRELEN_0 (0x1UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000004 */ -#define ETH_MACCR_PRELEN_1 (0x2UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000008 */ +#define ETH_MACCR_PRELEN_7 (0x0UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000000 */ +#define ETH_MACCR_PRELEN_5 (0x1UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000004 */ +#define ETH_MACCR_PRELEN_3 (0x2UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000006 */ #define ETH_MACCR_DC_Pos (4U) #define ETH_MACCR_DC_Msk (0x1UL << ETH_MACCR_DC_Pos) /*!< 0x00000010 */ #define ETH_MACCR_DC ETH_MACCR_DC_Msk /*!< Deferral Check */ #define ETH_MACCR_BL_Pos (5U) #define ETH_MACCR_BL_Msk (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */ #define ETH_MACCR_BL ETH_MACCR_BL_Msk /*!< Back-Off Limit */ -#define ETH_MACCR_BL_0 (0x1UL << ETH_MACCR_BL_Pos) /*!< 0x00000020 */ -#define ETH_MACCR_BL_1 (0x2UL << ETH_MACCR_BL_Pos) /*!< 0x00000040 */ +#define ETH_MACCR_BL_10 (0x0UL << ETH_MACCR_BL_Pos) /*!< 0x00000000 */ +#define ETH_MACCR_BL_8 (0x1UL << ETH_MACCR_BL_Pos) /*!< 0x00000020 */ +#define ETH_MACCR_BL_4 (0x2UL << ETH_MACCR_BL_Pos) /*!< 0x00000040 */ +#define ETH_MACCR_BL_1 (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */ #define ETH_MACCR_DR_Pos (8U) #define ETH_MACCR_DR_Msk (0x1UL << ETH_MACCR_DR_Pos) /*!< 0x00000100 */ #define ETH_MACCR_DR ETH_MACCR_DR_Msk /*!< Disable Retry */ @@ -12603,9 +12606,14 @@ typedef struct #define ETH_MACCR_IPG_Pos (24U) #define ETH_MACCR_IPG_Msk (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */ #define ETH_MACCR_IPG ETH_MACCR_IPG_Msk /*!< Inter-Packet Gap */ -#define ETH_MACCR_IPG_0 (0x1UL << ETH_MACCR_IPG_Pos) /*!< 0x01000000 */ -#define ETH_MACCR_IPG_1 (0x2UL << ETH_MACCR_IPG_Pos) /*!< 0x02000000 */ -#define ETH_MACCR_IPG_2 (0x4UL << ETH_MACCR_IPG_Pos) /*!< 0x04000000 */ +#define ETH_MACCR_IPG_96BIT (0x0UL << ETH_MACCR_IPG_Pos) /*!< 0x00000000 */ +#define ETH_MACCR_IPG_88BIT (0x1UL << ETH_MACCR_IPG_Pos) /*!< 0x01000000 */ +#define ETH_MACCR_IPG_80BIT (0x2UL << ETH_MACCR_IPG_Pos) /*!< 0x02000000 */ +#define ETH_MACCR_IPG_72BIT (0x3UL << ETH_MACCR_IPG_Pos) /*!< 0x03000000 */ +#define ETH_MACCR_IPG_64BIT (0x4UL << ETH_MACCR_IPG_Pos) /*!< 0x04000000 */ +#define ETH_MACCR_IPG_56BIT (0x5UL << ETH_MACCR_IPG_Pos) /*!< 0x05000000 */ +#define ETH_MACCR_IPG_48BIT (0x6UL << ETH_MACCR_IPG_Pos) /*!< 0x06000000 */ +#define ETH_MACCR_IPG_40BIT (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */ #define ETH_MACCR_IPC_Pos (27U) #define ETH_MACCR_IPC_Msk (0x1UL << ETH_MACCR_IPC_Pos) /*!< 0x08000000 */ #define ETH_MACCR_IPC ETH_MACCR_IPC_Msk /*!< Checksum Offload */ @@ -12708,10 +12716,21 @@ typedef struct #define ETH_MACWTR_WTO_Pos (0U) #define ETH_MACWTR_WTO_Msk (0xFUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000F */ #define ETH_MACWTR_WTO ETH_MACWTR_WTO_Msk /*!< Watchdog Timeout */ -#define ETH_MACWTR_WTO_0 (0x1UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000001 */ -#define ETH_MACWTR_WTO_1 (0x2UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000002 */ -#define ETH_MACWTR_WTO_2 (0x4UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000004 */ -#define ETH_MACWTR_WTO_3 (0x8UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000008 */ +#define ETH_MACWTR_WTO_2KB (0x0UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000001 */ +#define ETH_MACWTR_WTO_3KB (0x1UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000001 */ +#define ETH_MACWTR_WTO_4KB (0x2UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000002 */ +#define ETH_MACWTR_WTO_5KB (0x3UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000003 */ +#define ETH_MACWTR_WTO_6KB (0x4UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000004 */ +#define ETH_MACWTR_WTO_7KB (0x5UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000005 */ +#define ETH_MACWTR_WTO_8KB (0x6UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000006 */ +#define ETH_MACWTR_WTO_9KB (0x7UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000007 */ +#define ETH_MACWTR_WTO_10KB (0x8UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000008 */ +#define ETH_MACWTR_WTO_11KB (0x9UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000009 */ +#define ETH_MACWTR_WTO_12KB (0xAUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000A */ +#define ETH_MACWTR_WTO_13KB (0xBUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000B */ +#define ETH_MACWTR_WTO_14KB (0xCUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000C */ +#define ETH_MACWTR_WTO_15KB (0xDUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000D */ +#define ETH_MACWTR_WTO_16KB (0xEUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000E */ #define ETH_MACWTR_PWE_Pos (8U) #define ETH_MACWTR_PWE_Msk (0x1UL << ETH_MACWTR_PWE_Pos) /*!< 0x00000100 */ #define ETH_MACWTR_PWE ETH_MACWTR_PWE_Msk /*!< Programmable Watchdog Enable */ @@ -12791,6 +12810,9 @@ typedef struct #define ETH_MACHT1R_HT63T32_31 (0x80000000UL << ETH_MACHT1R_HT63T32_Pos) /*!< 0x80000000 */ /************** Bit definition for ETH_MACVTR register ***************/ +#define ETH_MACVTR_VL_VID_Pos (0U) +#define ETH_MACVTR_VL_VID_Msk (0xFFFUL << ETH_MACVTR_VL_VID_Pos) /*!< 0x00000FFF */ +#define ETH_MACVTR_VL_VID ETH_MACVTR_VL_VID_Msk /*!< VLAN Tag Identifier field of VLAN tag */ #define ETH_MACVTR_VL_Pos (0U) #define ETH_MACVTR_VL_Msk (0xFFFFUL << ETH_MACVTR_VL_Pos) /*!< 0x0000FFFF */ #define ETH_MACVTR_VL ETH_MACVTR_VL_Msk /*!< VLAN Tag Identifier for Receive Packets */ @@ -12952,9 +12974,12 @@ typedef struct #define ETH_MACQ0TXFCR_PLT_Pos (4U) #define ETH_MACQ0TXFCR_PLT_Msk (0x7UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000070 */ #define ETH_MACQ0TXFCR_PLT ETH_MACQ0TXFCR_PLT_Msk /*!< Pause Low Threshold */ -#define ETH_MACQ0TXFCR_PLT_0 (0x1UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000010 */ -#define ETH_MACQ0TXFCR_PLT_1 (0x2UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000020 */ -#define ETH_MACQ0TXFCR_PLT_2 (0x4UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000040 */ +#define ETH_MACQ0TXFCR_PLT_MINUS4 (0x0UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000000 */ +#define ETH_MACQ0TXFCR_PLT_MINUS28 (0x1UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000010 */ +#define ETH_MACQ0TXFCR_PLT_MINUS36 (0x2UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000020 */ +#define ETH_MACQ0TXFCR_PLT_MINUS144 (0x3UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000030 */ +#define ETH_MACQ0TXFCR_PLT_MINUS256 (0x4UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000040 */ +#define ETH_MACQ0TXFCR_PLT_MINUS512 (0x5UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000050 */ #define ETH_MACQ0TXFCR_DZPQ_Pos (7U) #define ETH_MACQ0TXFCR_DZPQ_Msk (0x1UL << ETH_MACQ0TXFCR_DZPQ_Pos) /*!< 0x00000080 */ #define ETH_MACQ0TXFCR_DZPQ ETH_MACQ0TXFCR_DZPQ_Msk /*!< Disable Zero-Quanta Pause */ @@ -13521,10 +13546,12 @@ typedef struct #define ETH_MACMDIOAR_CR_Pos (8U) #define ETH_MACMDIOAR_CR_Msk (0xFUL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000F00 */ #define ETH_MACMDIOAR_CR ETH_MACMDIOAR_CR_Msk /*!< CSR Clock Range */ -#define ETH_MACMDIOAR_CR_0 (0x1UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000100 */ -#define ETH_MACMDIOAR_CR_1 (0x2UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000200 */ -#define ETH_MACMDIOAR_CR_2 (0x4UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000400 */ -#define ETH_MACMDIOAR_CR_3 (0x8UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000800 */ +#define ETH_MACMDIOAR_CR_DIV42 (0x0UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000000 */ +#define ETH_MACMDIOAR_CR_DIV62 (0x1UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000100 */ +#define ETH_MACMDIOAR_CR_DIV16 (0x2UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000200 */ +#define ETH_MACMDIOAR_CR_DIV26 (0x3UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000300 */ +#define ETH_MACMDIOAR_CR_DIV102 (0x4UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000400 */ +#define ETH_MACMDIOAR_CR_DIV124 (0x5UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000500 */ #define ETH_MACMDIOAR_NTC_Pos (12U) #define ETH_MACMDIOAR_NTC_Msk (0x7UL << ETH_MACMDIOAR_NTC_Pos) /*!< 0x00007000 */ #define ETH_MACMDIOAR_NTC ETH_MACMDIOAR_NTC_Msk /*!< Number of Training Clocks */ @@ -13963,7 +13990,7 @@ typedef struct #define ETH_MMCTXIMR_TXLPIUSCIM ETH_MMCTXIMR_TXLPIUSCIM_Msk /*!< MMC Transmit LPI microsecond counter interrupt Mask */ #define ETH_MMCTXIMR_TXLPITRCIM_Pos (27U) #define ETH_MMCTXIMR_TXLPITRCIM_Msk (0x1UL << ETH_MMCTXIMR_TXLPITRCIM_Pos) /*!< 0x08000000 */ -#define ETH_MMCTXIMR_TXLPITRCIM ETH_MMC_INTERRUPT_MASK_TXLPITRCIM_Msk /*!< MMC Transmit LPI transition counter interrupt Mask */ +#define ETH_MMCTXIMR_TXLPITRCIM ETH_MMCTXIMR_TXLPITRCIM_Msk /*!< MMC Transmit LPI transition counter interrupt Mask */ /*********** Bit definition for ETH_MMC_TX_SINGLE_COLLISION_GOOD_PACKETS register ************/ #define ETH_MMCTXSCGPR_TXSNGLCOLG_Pos (0U) @@ -16666,9 +16693,10 @@ typedef struct #define ETH_DMAC0CR_DSL_Pos (18U) #define ETH_DMAC0CR_DSL_Msk (0x7UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x001C0000 */ #define ETH_DMAC0CR_DSL ETH_DMAC0CR_DSL_Msk /*!< Descriptor Skip Length */ -#define ETH_DMAC0CR_DSL_0 (0x1UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00040000 */ -#define ETH_DMAC0CR_DSL_1 (0x2UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00080000 */ -#define ETH_DMAC0CR_DSL_2 (0x4UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00100000 */ +#define ETH_DMACCR_DSL_0BIT (0x0UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00000000 */ +#define ETH_DMACCR_DSL_32BIT (0x1UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00040000 */ +#define ETH_DMACCR_DSL_64BIT (0x2UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00080000 */ +#define ETH_DMACCR_DSL_128BIT (0x4UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00100000 */ /************* Bit definition for ETH_DMAC0TXCR register *************/ #define ETH_DMAC0TXCR_ST_Pos (0U) @@ -16689,12 +16717,12 @@ typedef struct #define ETH_DMAC0TXCR_TXPBL_Pos (16U) #define ETH_DMAC0TXCR_TXPBL_Msk (0x3FUL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x003F0000 */ #define ETH_DMAC0TXCR_TXPBL ETH_DMAC0TXCR_TXPBL_Msk /*!< Transmit Programmable Burst Length */ -#define ETH_DMAC0TXCR_TXPBL_0 (0x1UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00010000 */ -#define ETH_DMAC0TXCR_TXPBL_1 (0x2UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00020000 */ -#define ETH_DMAC0TXCR_TXPBL_2 (0x4UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00040000 */ -#define ETH_DMAC0TXCR_TXPBL_3 (0x8UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00080000 */ -#define ETH_DMAC0TXCR_TXPBL_4 (0x10UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00100000 */ -#define ETH_DMAC0TXCR_TXPBL_5 (0x20UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00200000 */ +#define ETH_DMAC0TXCR_TXPBL_1PBL (0x1UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00010000 */ +#define ETH_DMAC0TXCR_TXPBL_2PBL (0x2UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00020000 */ +#define ETH_DMAC0TXCR_TXPBL_4PBL (0x4UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00040000 */ +#define ETH_DMAC0TXCR_TXPBL_8PBL (0x8UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00080000 */ +#define ETH_DMAC0TXCR_TXPBL_16PBL (0x10UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00100000 */ +#define ETH_DMAC0TXCR_TXPBL_32PBL (0x20UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00200000 */ #define ETH_DMAC0TXCR_TQOS_Pos (24U) #define ETH_DMAC0TXCR_TQOS_Msk (0xFUL << ETH_DMAC0TXCR_TQOS_Pos) /*!< 0x0F000000 */ #define ETH_DMAC0TXCR_TQOS ETH_DMAC0TXCR_TQOS_Msk /*!< Transmit QOS. */ @@ -16727,12 +16755,12 @@ typedef struct #define ETH_DMAC0RXCR_RXPBL_Pos (16U) #define ETH_DMAC0RXCR_RXPBL_Msk (0x3FUL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x003F0000 */ #define ETH_DMAC0RXCR_RXPBL ETH_DMAC0RXCR_RXPBL_Msk /*!< Receive Programmable Burst Length */ -#define ETH_DMAC0RXCR_RXPBL_0 (0x1UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00010000 */ -#define ETH_DMAC0RXCR_RXPBL_1 (0x2UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00020000 */ -#define ETH_DMAC0RXCR_RXPBL_2 (0x4UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00040000 */ -#define ETH_DMAC0RXCR_RXPBL_3 (0x8UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00080000 */ -#define ETH_DMAC0RXCR_RXPBL_4 (0x10UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00100000 */ -#define ETH_DMAC0RXCR_RXPBL_5 (0x20UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00200000 */ +#define ETH_DMAC0RXCR_RXPBL_1PBL (0x1UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00010000 */ +#define ETH_DMAC0RXCR_RXPBL_2PBL (0x2UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00020000 */ +#define ETH_DMAC0RXCR_RXPBL_4PBL (0x4UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00040000 */ +#define ETH_DMAC0RXCR_RXPBL_8PBL (0x8UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00080000 */ +#define ETH_DMAC0RXCR_RXPBL_16PBL (0x10UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00100000 */ +#define ETH_DMAC0RXCR_RXPBL_32PBL (0x20UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00200000 */ #define ETH_DMAC0RXCR_RQOS_Pos (24U) #define ETH_DMAC0RXCR_RQOS_Msk (0xFUL << ETH_DMAC0RXCR_RQOS_Pos) /*!< 0x0F000000 */ #define ETH_DMAC0RXCR_RQOS ETH_DMAC0RXCR_RQOS_Msk /*!< Rx AXI4 QOS. */ @@ -25778,6 +25806,16 @@ typedef struct #define BSEC_HWCFGR_ECC_USE_Msk (0xFUL << BSEC_HWCFGR_ECC_USE_Pos) /*!< 0x000000F0 */ #define BSEC_HWCFGR_ECC_USE BSEC_HWCFGR_ECC_USE_Msk /*!< protection / redundancy scheme used */ +/******************** Bit definition for BSEC_JTAGIN register ********************/ +#define BSEC_JTAGIN_DATA_Pos (0U) +#define BSEC_JTAGIN_DATA_Msk (0x0000FFFFUL << BSEC_JTAGIN_DATA_Pos) /*!< JTAG Input Data */ +#define BSEC_JTAGIN_DATA BSEC_JTAGIN_DATA_Msk + +/******************** Bit definition for BSEC_JTAGOUT register ********************/ +#define BSEC_JTAGOUT_DATA_Pos (0U) +#define BSEC_JTAGOUT_DATA_Msk (0x0000FFFFUL << BSEC_JTAGOUT_DATA_Pos) /*!< JTAG Output Data */ +#define BSEC_JTAGOUT_DATA BSEC_JTAGOUT_DATA_Msk + /******************** Bit definition for BSEC_VERR register********************/ #define BSEC_VERR_MINREV_Pos (0U) #define BSEC_VERR_MINREV_Msk (0xFUL << BSEC_VERR_MINREV_Pos) /*!< 0x0000000F */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157dxx_ca7.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157dxx_ca7.h index c35c98c4d6..05f51c2a88 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157dxx_ca7.h +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157dxx_ca7.h @@ -12379,16 +12379,19 @@ typedef struct #define ETH_MACCR_PRELEN_Pos (2U) #define ETH_MACCR_PRELEN_Msk (0x3UL << ETH_MACCR_PRELEN_Pos) /*!< 0x0000000C */ #define ETH_MACCR_PRELEN ETH_MACCR_PRELEN_Msk /*!< Preamble Length for Transmit packets */ -#define ETH_MACCR_PRELEN_0 (0x1UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000004 */ -#define ETH_MACCR_PRELEN_1 (0x2UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000008 */ +#define ETH_MACCR_PRELEN_7 (0x0UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000000 */ +#define ETH_MACCR_PRELEN_5 (0x1UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000004 */ +#define ETH_MACCR_PRELEN_3 (0x2UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000006 */ #define ETH_MACCR_DC_Pos (4U) #define ETH_MACCR_DC_Msk (0x1UL << ETH_MACCR_DC_Pos) /*!< 0x00000010 */ #define ETH_MACCR_DC ETH_MACCR_DC_Msk /*!< Deferral Check */ #define ETH_MACCR_BL_Pos (5U) #define ETH_MACCR_BL_Msk (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */ #define ETH_MACCR_BL ETH_MACCR_BL_Msk /*!< Back-Off Limit */ -#define ETH_MACCR_BL_0 (0x1UL << ETH_MACCR_BL_Pos) /*!< 0x00000020 */ -#define ETH_MACCR_BL_1 (0x2UL << ETH_MACCR_BL_Pos) /*!< 0x00000040 */ +#define ETH_MACCR_BL_10 (0x0UL << ETH_MACCR_BL_Pos) /*!< 0x00000000 */ +#define ETH_MACCR_BL_8 (0x1UL << ETH_MACCR_BL_Pos) /*!< 0x00000020 */ +#define ETH_MACCR_BL_4 (0x2UL << ETH_MACCR_BL_Pos) /*!< 0x00000040 */ +#define ETH_MACCR_BL_1 (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */ #define ETH_MACCR_DR_Pos (8U) #define ETH_MACCR_DR_Msk (0x1UL << ETH_MACCR_DR_Pos) /*!< 0x00000100 */ #define ETH_MACCR_DR ETH_MACCR_DR_Msk /*!< Disable Retry */ @@ -12440,9 +12443,14 @@ typedef struct #define ETH_MACCR_IPG_Pos (24U) #define ETH_MACCR_IPG_Msk (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */ #define ETH_MACCR_IPG ETH_MACCR_IPG_Msk /*!< Inter-Packet Gap */ -#define ETH_MACCR_IPG_0 (0x1UL << ETH_MACCR_IPG_Pos) /*!< 0x01000000 */ -#define ETH_MACCR_IPG_1 (0x2UL << ETH_MACCR_IPG_Pos) /*!< 0x02000000 */ -#define ETH_MACCR_IPG_2 (0x4UL << ETH_MACCR_IPG_Pos) /*!< 0x04000000 */ +#define ETH_MACCR_IPG_96BIT (0x0UL << ETH_MACCR_IPG_Pos) /*!< 0x00000000 */ +#define ETH_MACCR_IPG_88BIT (0x1UL << ETH_MACCR_IPG_Pos) /*!< 0x01000000 */ +#define ETH_MACCR_IPG_80BIT (0x2UL << ETH_MACCR_IPG_Pos) /*!< 0x02000000 */ +#define ETH_MACCR_IPG_72BIT (0x3UL << ETH_MACCR_IPG_Pos) /*!< 0x03000000 */ +#define ETH_MACCR_IPG_64BIT (0x4UL << ETH_MACCR_IPG_Pos) /*!< 0x04000000 */ +#define ETH_MACCR_IPG_56BIT (0x5UL << ETH_MACCR_IPG_Pos) /*!< 0x05000000 */ +#define ETH_MACCR_IPG_48BIT (0x6UL << ETH_MACCR_IPG_Pos) /*!< 0x06000000 */ +#define ETH_MACCR_IPG_40BIT (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */ #define ETH_MACCR_IPC_Pos (27U) #define ETH_MACCR_IPC_Msk (0x1UL << ETH_MACCR_IPC_Pos) /*!< 0x08000000 */ #define ETH_MACCR_IPC ETH_MACCR_IPC_Msk /*!< Checksum Offload */ @@ -12545,10 +12553,21 @@ typedef struct #define ETH_MACWTR_WTO_Pos (0U) #define ETH_MACWTR_WTO_Msk (0xFUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000F */ #define ETH_MACWTR_WTO ETH_MACWTR_WTO_Msk /*!< Watchdog Timeout */ -#define ETH_MACWTR_WTO_0 (0x1UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000001 */ -#define ETH_MACWTR_WTO_1 (0x2UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000002 */ -#define ETH_MACWTR_WTO_2 (0x4UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000004 */ -#define ETH_MACWTR_WTO_3 (0x8UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000008 */ +#define ETH_MACWTR_WTO_2KB (0x0UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000001 */ +#define ETH_MACWTR_WTO_3KB (0x1UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000001 */ +#define ETH_MACWTR_WTO_4KB (0x2UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000002 */ +#define ETH_MACWTR_WTO_5KB (0x3UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000003 */ +#define ETH_MACWTR_WTO_6KB (0x4UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000004 */ +#define ETH_MACWTR_WTO_7KB (0x5UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000005 */ +#define ETH_MACWTR_WTO_8KB (0x6UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000006 */ +#define ETH_MACWTR_WTO_9KB (0x7UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000007 */ +#define ETH_MACWTR_WTO_10KB (0x8UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000008 */ +#define ETH_MACWTR_WTO_11KB (0x9UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000009 */ +#define ETH_MACWTR_WTO_12KB (0xAUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000A */ +#define ETH_MACWTR_WTO_13KB (0xBUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000B */ +#define ETH_MACWTR_WTO_14KB (0xCUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000C */ +#define ETH_MACWTR_WTO_15KB (0xDUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000D */ +#define ETH_MACWTR_WTO_16KB (0xEUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000E */ #define ETH_MACWTR_PWE_Pos (8U) #define ETH_MACWTR_PWE_Msk (0x1UL << ETH_MACWTR_PWE_Pos) /*!< 0x00000100 */ #define ETH_MACWTR_PWE ETH_MACWTR_PWE_Msk /*!< Programmable Watchdog Enable */ @@ -12628,6 +12647,9 @@ typedef struct #define ETH_MACHT1R_HT63T32_31 (0x80000000UL << ETH_MACHT1R_HT63T32_Pos) /*!< 0x80000000 */ /************** Bit definition for ETH_MACVTR register ***************/ +#define ETH_MACVTR_VL_VID_Pos (0U) +#define ETH_MACVTR_VL_VID_Msk (0xFFFUL << ETH_MACVTR_VL_VID_Pos) /*!< 0x00000FFF */ +#define ETH_MACVTR_VL_VID ETH_MACVTR_VL_VID_Msk /*!< VLAN Tag Identifier field of VLAN tag */ #define ETH_MACVTR_VL_Pos (0U) #define ETH_MACVTR_VL_Msk (0xFFFFUL << ETH_MACVTR_VL_Pos) /*!< 0x0000FFFF */ #define ETH_MACVTR_VL ETH_MACVTR_VL_Msk /*!< VLAN Tag Identifier for Receive Packets */ @@ -12789,9 +12811,12 @@ typedef struct #define ETH_MACQ0TXFCR_PLT_Pos (4U) #define ETH_MACQ0TXFCR_PLT_Msk (0x7UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000070 */ #define ETH_MACQ0TXFCR_PLT ETH_MACQ0TXFCR_PLT_Msk /*!< Pause Low Threshold */ -#define ETH_MACQ0TXFCR_PLT_0 (0x1UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000010 */ -#define ETH_MACQ0TXFCR_PLT_1 (0x2UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000020 */ -#define ETH_MACQ0TXFCR_PLT_2 (0x4UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000040 */ +#define ETH_MACQ0TXFCR_PLT_MINUS4 (0x0UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000000 */ +#define ETH_MACQ0TXFCR_PLT_MINUS28 (0x1UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000010 */ +#define ETH_MACQ0TXFCR_PLT_MINUS36 (0x2UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000020 */ +#define ETH_MACQ0TXFCR_PLT_MINUS144 (0x3UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000030 */ +#define ETH_MACQ0TXFCR_PLT_MINUS256 (0x4UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000040 */ +#define ETH_MACQ0TXFCR_PLT_MINUS512 (0x5UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000050 */ #define ETH_MACQ0TXFCR_DZPQ_Pos (7U) #define ETH_MACQ0TXFCR_DZPQ_Msk (0x1UL << ETH_MACQ0TXFCR_DZPQ_Pos) /*!< 0x00000080 */ #define ETH_MACQ0TXFCR_DZPQ ETH_MACQ0TXFCR_DZPQ_Msk /*!< Disable Zero-Quanta Pause */ @@ -13358,10 +13383,12 @@ typedef struct #define ETH_MACMDIOAR_CR_Pos (8U) #define ETH_MACMDIOAR_CR_Msk (0xFUL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000F00 */ #define ETH_MACMDIOAR_CR ETH_MACMDIOAR_CR_Msk /*!< CSR Clock Range */ -#define ETH_MACMDIOAR_CR_0 (0x1UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000100 */ -#define ETH_MACMDIOAR_CR_1 (0x2UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000200 */ -#define ETH_MACMDIOAR_CR_2 (0x4UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000400 */ -#define ETH_MACMDIOAR_CR_3 (0x8UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000800 */ +#define ETH_MACMDIOAR_CR_DIV42 (0x0UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000000 */ +#define ETH_MACMDIOAR_CR_DIV62 (0x1UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000100 */ +#define ETH_MACMDIOAR_CR_DIV16 (0x2UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000200 */ +#define ETH_MACMDIOAR_CR_DIV26 (0x3UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000300 */ +#define ETH_MACMDIOAR_CR_DIV102 (0x4UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000400 */ +#define ETH_MACMDIOAR_CR_DIV124 (0x5UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000500 */ #define ETH_MACMDIOAR_NTC_Pos (12U) #define ETH_MACMDIOAR_NTC_Msk (0x7UL << ETH_MACMDIOAR_NTC_Pos) /*!< 0x00007000 */ #define ETH_MACMDIOAR_NTC ETH_MACMDIOAR_NTC_Msk /*!< Number of Training Clocks */ @@ -13800,7 +13827,7 @@ typedef struct #define ETH_MMCTXIMR_TXLPIUSCIM ETH_MMCTXIMR_TXLPIUSCIM_Msk /*!< MMC Transmit LPI microsecond counter interrupt Mask */ #define ETH_MMCTXIMR_TXLPITRCIM_Pos (27U) #define ETH_MMCTXIMR_TXLPITRCIM_Msk (0x1UL << ETH_MMCTXIMR_TXLPITRCIM_Pos) /*!< 0x08000000 */ -#define ETH_MMCTXIMR_TXLPITRCIM ETH_MMC_INTERRUPT_MASK_TXLPITRCIM_Msk /*!< MMC Transmit LPI transition counter interrupt Mask */ +#define ETH_MMCTXIMR_TXLPITRCIM ETH_MMCTXIMR_TXLPITRCIM_Msk /*!< MMC Transmit LPI transition counter interrupt Mask */ /*********** Bit definition for ETH_MMC_TX_SINGLE_COLLISION_GOOD_PACKETS register ************/ #define ETH_MMCTXSCGPR_TXSNGLCOLG_Pos (0U) @@ -16503,9 +16530,10 @@ typedef struct #define ETH_DMAC0CR_DSL_Pos (18U) #define ETH_DMAC0CR_DSL_Msk (0x7UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x001C0000 */ #define ETH_DMAC0CR_DSL ETH_DMAC0CR_DSL_Msk /*!< Descriptor Skip Length */ -#define ETH_DMAC0CR_DSL_0 (0x1UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00040000 */ -#define ETH_DMAC0CR_DSL_1 (0x2UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00080000 */ -#define ETH_DMAC0CR_DSL_2 (0x4UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00100000 */ +#define ETH_DMACCR_DSL_0BIT (0x0UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00000000 */ +#define ETH_DMACCR_DSL_32BIT (0x1UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00040000 */ +#define ETH_DMACCR_DSL_64BIT (0x2UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00080000 */ +#define ETH_DMACCR_DSL_128BIT (0x4UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00100000 */ /************* Bit definition for ETH_DMAC0TXCR register *************/ #define ETH_DMAC0TXCR_ST_Pos (0U) @@ -16526,12 +16554,12 @@ typedef struct #define ETH_DMAC0TXCR_TXPBL_Pos (16U) #define ETH_DMAC0TXCR_TXPBL_Msk (0x3FUL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x003F0000 */ #define ETH_DMAC0TXCR_TXPBL ETH_DMAC0TXCR_TXPBL_Msk /*!< Transmit Programmable Burst Length */ -#define ETH_DMAC0TXCR_TXPBL_0 (0x1UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00010000 */ -#define ETH_DMAC0TXCR_TXPBL_1 (0x2UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00020000 */ -#define ETH_DMAC0TXCR_TXPBL_2 (0x4UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00040000 */ -#define ETH_DMAC0TXCR_TXPBL_3 (0x8UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00080000 */ -#define ETH_DMAC0TXCR_TXPBL_4 (0x10UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00100000 */ -#define ETH_DMAC0TXCR_TXPBL_5 (0x20UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00200000 */ +#define ETH_DMAC0TXCR_TXPBL_1PBL (0x1UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00010000 */ +#define ETH_DMAC0TXCR_TXPBL_2PBL (0x2UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00020000 */ +#define ETH_DMAC0TXCR_TXPBL_4PBL (0x4UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00040000 */ +#define ETH_DMAC0TXCR_TXPBL_8PBL (0x8UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00080000 */ +#define ETH_DMAC0TXCR_TXPBL_16PBL (0x10UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00100000 */ +#define ETH_DMAC0TXCR_TXPBL_32PBL (0x20UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00200000 */ #define ETH_DMAC0TXCR_TQOS_Pos (24U) #define ETH_DMAC0TXCR_TQOS_Msk (0xFUL << ETH_DMAC0TXCR_TQOS_Pos) /*!< 0x0F000000 */ #define ETH_DMAC0TXCR_TQOS ETH_DMAC0TXCR_TQOS_Msk /*!< Transmit QOS. */ @@ -16564,12 +16592,12 @@ typedef struct #define ETH_DMAC0RXCR_RXPBL_Pos (16U) #define ETH_DMAC0RXCR_RXPBL_Msk (0x3FUL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x003F0000 */ #define ETH_DMAC0RXCR_RXPBL ETH_DMAC0RXCR_RXPBL_Msk /*!< Receive Programmable Burst Length */ -#define ETH_DMAC0RXCR_RXPBL_0 (0x1UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00010000 */ -#define ETH_DMAC0RXCR_RXPBL_1 (0x2UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00020000 */ -#define ETH_DMAC0RXCR_RXPBL_2 (0x4UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00040000 */ -#define ETH_DMAC0RXCR_RXPBL_3 (0x8UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00080000 */ -#define ETH_DMAC0RXCR_RXPBL_4 (0x10UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00100000 */ -#define ETH_DMAC0RXCR_RXPBL_5 (0x20UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00200000 */ +#define ETH_DMAC0RXCR_RXPBL_1PBL (0x1UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00010000 */ +#define ETH_DMAC0RXCR_RXPBL_2PBL (0x2UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00020000 */ +#define ETH_DMAC0RXCR_RXPBL_4PBL (0x4UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00040000 */ +#define ETH_DMAC0RXCR_RXPBL_8PBL (0x8UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00080000 */ +#define ETH_DMAC0RXCR_RXPBL_16PBL (0x10UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00100000 */ +#define ETH_DMAC0RXCR_RXPBL_32PBL (0x20UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00200000 */ #define ETH_DMAC0RXCR_RQOS_Pos (24U) #define ETH_DMAC0RXCR_RQOS_Msk (0xFUL << ETH_DMAC0RXCR_RQOS_Pos) /*!< 0x0F000000 */ #define ETH_DMAC0RXCR_RQOS ETH_DMAC0RXCR_RQOS_Msk /*!< Rx AXI4 QOS. */ @@ -25615,6 +25643,16 @@ typedef struct #define BSEC_HWCFGR_ECC_USE_Msk (0xFUL << BSEC_HWCFGR_ECC_USE_Pos) /*!< 0x000000F0 */ #define BSEC_HWCFGR_ECC_USE BSEC_HWCFGR_ECC_USE_Msk /*!< protection / redundancy scheme used */ +/******************** Bit definition for BSEC_JTAGIN register ********************/ +#define BSEC_JTAGIN_DATA_Pos (0U) +#define BSEC_JTAGIN_DATA_Msk (0x0000FFFFUL << BSEC_JTAGIN_DATA_Pos) /*!< JTAG Input Data */ +#define BSEC_JTAGIN_DATA BSEC_JTAGIN_DATA_Msk + +/******************** Bit definition for BSEC_JTAGOUT register ********************/ +#define BSEC_JTAGOUT_DATA_Pos (0U) +#define BSEC_JTAGOUT_DATA_Msk (0x0000FFFFUL << BSEC_JTAGOUT_DATA_Pos) /*!< JTAG Output Data */ +#define BSEC_JTAGOUT_DATA BSEC_JTAGOUT_DATA_Msk + /******************** Bit definition for BSEC_VERR register********************/ #define BSEC_VERR_MINREV_Pos (0U) #define BSEC_VERR_MINREV_Msk (0xFUL << BSEC_VERR_MINREV_Pos) /*!< 0x0000000F */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157dxx_cm4.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157dxx_cm4.h index 72c43c43dd..85f876e606 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157dxx_cm4.h +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157dxx_cm4.h @@ -12345,16 +12345,19 @@ typedef struct #define ETH_MACCR_PRELEN_Pos (2U) #define ETH_MACCR_PRELEN_Msk (0x3UL << ETH_MACCR_PRELEN_Pos) /*!< 0x0000000C */ #define ETH_MACCR_PRELEN ETH_MACCR_PRELEN_Msk /*!< Preamble Length for Transmit packets */ -#define ETH_MACCR_PRELEN_0 (0x1UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000004 */ -#define ETH_MACCR_PRELEN_1 (0x2UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000008 */ +#define ETH_MACCR_PRELEN_7 (0x0UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000000 */ +#define ETH_MACCR_PRELEN_5 (0x1UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000004 */ +#define ETH_MACCR_PRELEN_3 (0x2UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000006 */ #define ETH_MACCR_DC_Pos (4U) #define ETH_MACCR_DC_Msk (0x1UL << ETH_MACCR_DC_Pos) /*!< 0x00000010 */ #define ETH_MACCR_DC ETH_MACCR_DC_Msk /*!< Deferral Check */ #define ETH_MACCR_BL_Pos (5U) #define ETH_MACCR_BL_Msk (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */ #define ETH_MACCR_BL ETH_MACCR_BL_Msk /*!< Back-Off Limit */ -#define ETH_MACCR_BL_0 (0x1UL << ETH_MACCR_BL_Pos) /*!< 0x00000020 */ -#define ETH_MACCR_BL_1 (0x2UL << ETH_MACCR_BL_Pos) /*!< 0x00000040 */ +#define ETH_MACCR_BL_10 (0x0UL << ETH_MACCR_BL_Pos) /*!< 0x00000000 */ +#define ETH_MACCR_BL_8 (0x1UL << ETH_MACCR_BL_Pos) /*!< 0x00000020 */ +#define ETH_MACCR_BL_4 (0x2UL << ETH_MACCR_BL_Pos) /*!< 0x00000040 */ +#define ETH_MACCR_BL_1 (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */ #define ETH_MACCR_DR_Pos (8U) #define ETH_MACCR_DR_Msk (0x1UL << ETH_MACCR_DR_Pos) /*!< 0x00000100 */ #define ETH_MACCR_DR ETH_MACCR_DR_Msk /*!< Disable Retry */ @@ -12406,9 +12409,14 @@ typedef struct #define ETH_MACCR_IPG_Pos (24U) #define ETH_MACCR_IPG_Msk (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */ #define ETH_MACCR_IPG ETH_MACCR_IPG_Msk /*!< Inter-Packet Gap */ -#define ETH_MACCR_IPG_0 (0x1UL << ETH_MACCR_IPG_Pos) /*!< 0x01000000 */ -#define ETH_MACCR_IPG_1 (0x2UL << ETH_MACCR_IPG_Pos) /*!< 0x02000000 */ -#define ETH_MACCR_IPG_2 (0x4UL << ETH_MACCR_IPG_Pos) /*!< 0x04000000 */ +#define ETH_MACCR_IPG_96BIT (0x0UL << ETH_MACCR_IPG_Pos) /*!< 0x00000000 */ +#define ETH_MACCR_IPG_88BIT (0x1UL << ETH_MACCR_IPG_Pos) /*!< 0x01000000 */ +#define ETH_MACCR_IPG_80BIT (0x2UL << ETH_MACCR_IPG_Pos) /*!< 0x02000000 */ +#define ETH_MACCR_IPG_72BIT (0x3UL << ETH_MACCR_IPG_Pos) /*!< 0x03000000 */ +#define ETH_MACCR_IPG_64BIT (0x4UL << ETH_MACCR_IPG_Pos) /*!< 0x04000000 */ +#define ETH_MACCR_IPG_56BIT (0x5UL << ETH_MACCR_IPG_Pos) /*!< 0x05000000 */ +#define ETH_MACCR_IPG_48BIT (0x6UL << ETH_MACCR_IPG_Pos) /*!< 0x06000000 */ +#define ETH_MACCR_IPG_40BIT (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */ #define ETH_MACCR_IPC_Pos (27U) #define ETH_MACCR_IPC_Msk (0x1UL << ETH_MACCR_IPC_Pos) /*!< 0x08000000 */ #define ETH_MACCR_IPC ETH_MACCR_IPC_Msk /*!< Checksum Offload */ @@ -12511,10 +12519,21 @@ typedef struct #define ETH_MACWTR_WTO_Pos (0U) #define ETH_MACWTR_WTO_Msk (0xFUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000F */ #define ETH_MACWTR_WTO ETH_MACWTR_WTO_Msk /*!< Watchdog Timeout */ -#define ETH_MACWTR_WTO_0 (0x1UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000001 */ -#define ETH_MACWTR_WTO_1 (0x2UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000002 */ -#define ETH_MACWTR_WTO_2 (0x4UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000004 */ -#define ETH_MACWTR_WTO_3 (0x8UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000008 */ +#define ETH_MACWTR_WTO_2KB (0x0UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000001 */ +#define ETH_MACWTR_WTO_3KB (0x1UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000001 */ +#define ETH_MACWTR_WTO_4KB (0x2UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000002 */ +#define ETH_MACWTR_WTO_5KB (0x3UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000003 */ +#define ETH_MACWTR_WTO_6KB (0x4UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000004 */ +#define ETH_MACWTR_WTO_7KB (0x5UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000005 */ +#define ETH_MACWTR_WTO_8KB (0x6UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000006 */ +#define ETH_MACWTR_WTO_9KB (0x7UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000007 */ +#define ETH_MACWTR_WTO_10KB (0x8UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000008 */ +#define ETH_MACWTR_WTO_11KB (0x9UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000009 */ +#define ETH_MACWTR_WTO_12KB (0xAUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000A */ +#define ETH_MACWTR_WTO_13KB (0xBUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000B */ +#define ETH_MACWTR_WTO_14KB (0xCUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000C */ +#define ETH_MACWTR_WTO_15KB (0xDUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000D */ +#define ETH_MACWTR_WTO_16KB (0xEUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000E */ #define ETH_MACWTR_PWE_Pos (8U) #define ETH_MACWTR_PWE_Msk (0x1UL << ETH_MACWTR_PWE_Pos) /*!< 0x00000100 */ #define ETH_MACWTR_PWE ETH_MACWTR_PWE_Msk /*!< Programmable Watchdog Enable */ @@ -12594,6 +12613,9 @@ typedef struct #define ETH_MACHT1R_HT63T32_31 (0x80000000UL << ETH_MACHT1R_HT63T32_Pos) /*!< 0x80000000 */ /************** Bit definition for ETH_MACVTR register ***************/ +#define ETH_MACVTR_VL_VID_Pos (0U) +#define ETH_MACVTR_VL_VID_Msk (0xFFFUL << ETH_MACVTR_VL_VID_Pos) /*!< 0x00000FFF */ +#define ETH_MACVTR_VL_VID ETH_MACVTR_VL_VID_Msk /*!< VLAN Tag Identifier field of VLAN tag */ #define ETH_MACVTR_VL_Pos (0U) #define ETH_MACVTR_VL_Msk (0xFFFFUL << ETH_MACVTR_VL_Pos) /*!< 0x0000FFFF */ #define ETH_MACVTR_VL ETH_MACVTR_VL_Msk /*!< VLAN Tag Identifier for Receive Packets */ @@ -12755,9 +12777,12 @@ typedef struct #define ETH_MACQ0TXFCR_PLT_Pos (4U) #define ETH_MACQ0TXFCR_PLT_Msk (0x7UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000070 */ #define ETH_MACQ0TXFCR_PLT ETH_MACQ0TXFCR_PLT_Msk /*!< Pause Low Threshold */ -#define ETH_MACQ0TXFCR_PLT_0 (0x1UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000010 */ -#define ETH_MACQ0TXFCR_PLT_1 (0x2UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000020 */ -#define ETH_MACQ0TXFCR_PLT_2 (0x4UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000040 */ +#define ETH_MACQ0TXFCR_PLT_MINUS4 (0x0UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000000 */ +#define ETH_MACQ0TXFCR_PLT_MINUS28 (0x1UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000010 */ +#define ETH_MACQ0TXFCR_PLT_MINUS36 (0x2UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000020 */ +#define ETH_MACQ0TXFCR_PLT_MINUS144 (0x3UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000030 */ +#define ETH_MACQ0TXFCR_PLT_MINUS256 (0x4UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000040 */ +#define ETH_MACQ0TXFCR_PLT_MINUS512 (0x5UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000050 */ #define ETH_MACQ0TXFCR_DZPQ_Pos (7U) #define ETH_MACQ0TXFCR_DZPQ_Msk (0x1UL << ETH_MACQ0TXFCR_DZPQ_Pos) /*!< 0x00000080 */ #define ETH_MACQ0TXFCR_DZPQ ETH_MACQ0TXFCR_DZPQ_Msk /*!< Disable Zero-Quanta Pause */ @@ -13324,10 +13349,12 @@ typedef struct #define ETH_MACMDIOAR_CR_Pos (8U) #define ETH_MACMDIOAR_CR_Msk (0xFUL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000F00 */ #define ETH_MACMDIOAR_CR ETH_MACMDIOAR_CR_Msk /*!< CSR Clock Range */ -#define ETH_MACMDIOAR_CR_0 (0x1UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000100 */ -#define ETH_MACMDIOAR_CR_1 (0x2UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000200 */ -#define ETH_MACMDIOAR_CR_2 (0x4UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000400 */ -#define ETH_MACMDIOAR_CR_3 (0x8UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000800 */ +#define ETH_MACMDIOAR_CR_DIV42 (0x0UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000000 */ +#define ETH_MACMDIOAR_CR_DIV62 (0x1UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000100 */ +#define ETH_MACMDIOAR_CR_DIV16 (0x2UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000200 */ +#define ETH_MACMDIOAR_CR_DIV26 (0x3UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000300 */ +#define ETH_MACMDIOAR_CR_DIV102 (0x4UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000400 */ +#define ETH_MACMDIOAR_CR_DIV124 (0x5UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000500 */ #define ETH_MACMDIOAR_NTC_Pos (12U) #define ETH_MACMDIOAR_NTC_Msk (0x7UL << ETH_MACMDIOAR_NTC_Pos) /*!< 0x00007000 */ #define ETH_MACMDIOAR_NTC ETH_MACMDIOAR_NTC_Msk /*!< Number of Training Clocks */ @@ -13766,7 +13793,7 @@ typedef struct #define ETH_MMCTXIMR_TXLPIUSCIM ETH_MMCTXIMR_TXLPIUSCIM_Msk /*!< MMC Transmit LPI microsecond counter interrupt Mask */ #define ETH_MMCTXIMR_TXLPITRCIM_Pos (27U) #define ETH_MMCTXIMR_TXLPITRCIM_Msk (0x1UL << ETH_MMCTXIMR_TXLPITRCIM_Pos) /*!< 0x08000000 */ -#define ETH_MMCTXIMR_TXLPITRCIM ETH_MMC_INTERRUPT_MASK_TXLPITRCIM_Msk /*!< MMC Transmit LPI transition counter interrupt Mask */ +#define ETH_MMCTXIMR_TXLPITRCIM ETH_MMCTXIMR_TXLPITRCIM_Msk /*!< MMC Transmit LPI transition counter interrupt Mask */ /*********** Bit definition for ETH_MMC_TX_SINGLE_COLLISION_GOOD_PACKETS register ************/ #define ETH_MMCTXSCGPR_TXSNGLCOLG_Pos (0U) @@ -16469,9 +16496,10 @@ typedef struct #define ETH_DMAC0CR_DSL_Pos (18U) #define ETH_DMAC0CR_DSL_Msk (0x7UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x001C0000 */ #define ETH_DMAC0CR_DSL ETH_DMAC0CR_DSL_Msk /*!< Descriptor Skip Length */ -#define ETH_DMAC0CR_DSL_0 (0x1UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00040000 */ -#define ETH_DMAC0CR_DSL_1 (0x2UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00080000 */ -#define ETH_DMAC0CR_DSL_2 (0x4UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00100000 */ +#define ETH_DMACCR_DSL_0BIT (0x0UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00000000 */ +#define ETH_DMACCR_DSL_32BIT (0x1UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00040000 */ +#define ETH_DMACCR_DSL_64BIT (0x2UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00080000 */ +#define ETH_DMACCR_DSL_128BIT (0x4UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00100000 */ /************* Bit definition for ETH_DMAC0TXCR register *************/ #define ETH_DMAC0TXCR_ST_Pos (0U) @@ -16492,12 +16520,12 @@ typedef struct #define ETH_DMAC0TXCR_TXPBL_Pos (16U) #define ETH_DMAC0TXCR_TXPBL_Msk (0x3FUL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x003F0000 */ #define ETH_DMAC0TXCR_TXPBL ETH_DMAC0TXCR_TXPBL_Msk /*!< Transmit Programmable Burst Length */ -#define ETH_DMAC0TXCR_TXPBL_0 (0x1UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00010000 */ -#define ETH_DMAC0TXCR_TXPBL_1 (0x2UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00020000 */ -#define ETH_DMAC0TXCR_TXPBL_2 (0x4UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00040000 */ -#define ETH_DMAC0TXCR_TXPBL_3 (0x8UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00080000 */ -#define ETH_DMAC0TXCR_TXPBL_4 (0x10UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00100000 */ -#define ETH_DMAC0TXCR_TXPBL_5 (0x20UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00200000 */ +#define ETH_DMAC0TXCR_TXPBL_1PBL (0x1UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00010000 */ +#define ETH_DMAC0TXCR_TXPBL_2PBL (0x2UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00020000 */ +#define ETH_DMAC0TXCR_TXPBL_4PBL (0x4UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00040000 */ +#define ETH_DMAC0TXCR_TXPBL_8PBL (0x8UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00080000 */ +#define ETH_DMAC0TXCR_TXPBL_16PBL (0x10UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00100000 */ +#define ETH_DMAC0TXCR_TXPBL_32PBL (0x20UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00200000 */ #define ETH_DMAC0TXCR_TQOS_Pos (24U) #define ETH_DMAC0TXCR_TQOS_Msk (0xFUL << ETH_DMAC0TXCR_TQOS_Pos) /*!< 0x0F000000 */ #define ETH_DMAC0TXCR_TQOS ETH_DMAC0TXCR_TQOS_Msk /*!< Transmit QOS. */ @@ -16530,12 +16558,12 @@ typedef struct #define ETH_DMAC0RXCR_RXPBL_Pos (16U) #define ETH_DMAC0RXCR_RXPBL_Msk (0x3FUL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x003F0000 */ #define ETH_DMAC0RXCR_RXPBL ETH_DMAC0RXCR_RXPBL_Msk /*!< Receive Programmable Burst Length */ -#define ETH_DMAC0RXCR_RXPBL_0 (0x1UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00010000 */ -#define ETH_DMAC0RXCR_RXPBL_1 (0x2UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00020000 */ -#define ETH_DMAC0RXCR_RXPBL_2 (0x4UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00040000 */ -#define ETH_DMAC0RXCR_RXPBL_3 (0x8UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00080000 */ -#define ETH_DMAC0RXCR_RXPBL_4 (0x10UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00100000 */ -#define ETH_DMAC0RXCR_RXPBL_5 (0x20UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00200000 */ +#define ETH_DMAC0RXCR_RXPBL_1PBL (0x1UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00010000 */ +#define ETH_DMAC0RXCR_RXPBL_2PBL (0x2UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00020000 */ +#define ETH_DMAC0RXCR_RXPBL_4PBL (0x4UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00040000 */ +#define ETH_DMAC0RXCR_RXPBL_8PBL (0x8UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00080000 */ +#define ETH_DMAC0RXCR_RXPBL_16PBL (0x10UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00100000 */ +#define ETH_DMAC0RXCR_RXPBL_32PBL (0x20UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00200000 */ #define ETH_DMAC0RXCR_RQOS_Pos (24U) #define ETH_DMAC0RXCR_RQOS_Msk (0xFUL << ETH_DMAC0RXCR_RQOS_Pos) /*!< 0x0F000000 */ #define ETH_DMAC0RXCR_RQOS ETH_DMAC0RXCR_RQOS_Msk /*!< Rx AXI4 QOS. */ @@ -25581,6 +25609,16 @@ typedef struct #define BSEC_HWCFGR_ECC_USE_Msk (0xFUL << BSEC_HWCFGR_ECC_USE_Pos) /*!< 0x000000F0 */ #define BSEC_HWCFGR_ECC_USE BSEC_HWCFGR_ECC_USE_Msk /*!< protection / redundancy scheme used */ +/******************** Bit definition for BSEC_JTAGIN register ********************/ +#define BSEC_JTAGIN_DATA_Pos (0U) +#define BSEC_JTAGIN_DATA_Msk (0x0000FFFFUL << BSEC_JTAGIN_DATA_Pos) /*!< JTAG Input Data */ +#define BSEC_JTAGIN_DATA BSEC_JTAGIN_DATA_Msk + +/******************** Bit definition for BSEC_JTAGOUT register ********************/ +#define BSEC_JTAGOUT_DATA_Pos (0U) +#define BSEC_JTAGOUT_DATA_Msk (0x0000FFFFUL << BSEC_JTAGOUT_DATA_Pos) /*!< JTAG Output Data */ +#define BSEC_JTAGOUT_DATA BSEC_JTAGOUT_DATA_Msk + /******************** Bit definition for BSEC_VERR register********************/ #define BSEC_VERR_MINREV_Pos (0U) #define BSEC_VERR_MINREV_Msk (0xFUL << BSEC_VERR_MINREV_Pos) /*!< 0x0000000F */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157fxx_ca7.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157fxx_ca7.h index deae8cd2b3..ee44fd108f 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157fxx_ca7.h +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157fxx_ca7.h @@ -12576,16 +12576,19 @@ typedef struct #define ETH_MACCR_PRELEN_Pos (2U) #define ETH_MACCR_PRELEN_Msk (0x3UL << ETH_MACCR_PRELEN_Pos) /*!< 0x0000000C */ #define ETH_MACCR_PRELEN ETH_MACCR_PRELEN_Msk /*!< Preamble Length for Transmit packets */ -#define ETH_MACCR_PRELEN_0 (0x1UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000004 */ -#define ETH_MACCR_PRELEN_1 (0x2UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000008 */ +#define ETH_MACCR_PRELEN_7 (0x0UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000000 */ +#define ETH_MACCR_PRELEN_5 (0x1UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000004 */ +#define ETH_MACCR_PRELEN_3 (0x2UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000006 */ #define ETH_MACCR_DC_Pos (4U) #define ETH_MACCR_DC_Msk (0x1UL << ETH_MACCR_DC_Pos) /*!< 0x00000010 */ #define ETH_MACCR_DC ETH_MACCR_DC_Msk /*!< Deferral Check */ #define ETH_MACCR_BL_Pos (5U) #define ETH_MACCR_BL_Msk (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */ #define ETH_MACCR_BL ETH_MACCR_BL_Msk /*!< Back-Off Limit */ -#define ETH_MACCR_BL_0 (0x1UL << ETH_MACCR_BL_Pos) /*!< 0x00000020 */ -#define ETH_MACCR_BL_1 (0x2UL << ETH_MACCR_BL_Pos) /*!< 0x00000040 */ +#define ETH_MACCR_BL_10 (0x0UL << ETH_MACCR_BL_Pos) /*!< 0x00000000 */ +#define ETH_MACCR_BL_8 (0x1UL << ETH_MACCR_BL_Pos) /*!< 0x00000020 */ +#define ETH_MACCR_BL_4 (0x2UL << ETH_MACCR_BL_Pos) /*!< 0x00000040 */ +#define ETH_MACCR_BL_1 (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */ #define ETH_MACCR_DR_Pos (8U) #define ETH_MACCR_DR_Msk (0x1UL << ETH_MACCR_DR_Pos) /*!< 0x00000100 */ #define ETH_MACCR_DR ETH_MACCR_DR_Msk /*!< Disable Retry */ @@ -12637,9 +12640,14 @@ typedef struct #define ETH_MACCR_IPG_Pos (24U) #define ETH_MACCR_IPG_Msk (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */ #define ETH_MACCR_IPG ETH_MACCR_IPG_Msk /*!< Inter-Packet Gap */ -#define ETH_MACCR_IPG_0 (0x1UL << ETH_MACCR_IPG_Pos) /*!< 0x01000000 */ -#define ETH_MACCR_IPG_1 (0x2UL << ETH_MACCR_IPG_Pos) /*!< 0x02000000 */ -#define ETH_MACCR_IPG_2 (0x4UL << ETH_MACCR_IPG_Pos) /*!< 0x04000000 */ +#define ETH_MACCR_IPG_96BIT (0x0UL << ETH_MACCR_IPG_Pos) /*!< 0x00000000 */ +#define ETH_MACCR_IPG_88BIT (0x1UL << ETH_MACCR_IPG_Pos) /*!< 0x01000000 */ +#define ETH_MACCR_IPG_80BIT (0x2UL << ETH_MACCR_IPG_Pos) /*!< 0x02000000 */ +#define ETH_MACCR_IPG_72BIT (0x3UL << ETH_MACCR_IPG_Pos) /*!< 0x03000000 */ +#define ETH_MACCR_IPG_64BIT (0x4UL << ETH_MACCR_IPG_Pos) /*!< 0x04000000 */ +#define ETH_MACCR_IPG_56BIT (0x5UL << ETH_MACCR_IPG_Pos) /*!< 0x05000000 */ +#define ETH_MACCR_IPG_48BIT (0x6UL << ETH_MACCR_IPG_Pos) /*!< 0x06000000 */ +#define ETH_MACCR_IPG_40BIT (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */ #define ETH_MACCR_IPC_Pos (27U) #define ETH_MACCR_IPC_Msk (0x1UL << ETH_MACCR_IPC_Pos) /*!< 0x08000000 */ #define ETH_MACCR_IPC ETH_MACCR_IPC_Msk /*!< Checksum Offload */ @@ -12742,10 +12750,21 @@ typedef struct #define ETH_MACWTR_WTO_Pos (0U) #define ETH_MACWTR_WTO_Msk (0xFUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000F */ #define ETH_MACWTR_WTO ETH_MACWTR_WTO_Msk /*!< Watchdog Timeout */ -#define ETH_MACWTR_WTO_0 (0x1UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000001 */ -#define ETH_MACWTR_WTO_1 (0x2UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000002 */ -#define ETH_MACWTR_WTO_2 (0x4UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000004 */ -#define ETH_MACWTR_WTO_3 (0x8UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000008 */ +#define ETH_MACWTR_WTO_2KB (0x0UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000001 */ +#define ETH_MACWTR_WTO_3KB (0x1UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000001 */ +#define ETH_MACWTR_WTO_4KB (0x2UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000002 */ +#define ETH_MACWTR_WTO_5KB (0x3UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000003 */ +#define ETH_MACWTR_WTO_6KB (0x4UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000004 */ +#define ETH_MACWTR_WTO_7KB (0x5UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000005 */ +#define ETH_MACWTR_WTO_8KB (0x6UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000006 */ +#define ETH_MACWTR_WTO_9KB (0x7UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000007 */ +#define ETH_MACWTR_WTO_10KB (0x8UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000008 */ +#define ETH_MACWTR_WTO_11KB (0x9UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000009 */ +#define ETH_MACWTR_WTO_12KB (0xAUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000A */ +#define ETH_MACWTR_WTO_13KB (0xBUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000B */ +#define ETH_MACWTR_WTO_14KB (0xCUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000C */ +#define ETH_MACWTR_WTO_15KB (0xDUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000D */ +#define ETH_MACWTR_WTO_16KB (0xEUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000E */ #define ETH_MACWTR_PWE_Pos (8U) #define ETH_MACWTR_PWE_Msk (0x1UL << ETH_MACWTR_PWE_Pos) /*!< 0x00000100 */ #define ETH_MACWTR_PWE ETH_MACWTR_PWE_Msk /*!< Programmable Watchdog Enable */ @@ -12825,6 +12844,9 @@ typedef struct #define ETH_MACHT1R_HT63T32_31 (0x80000000UL << ETH_MACHT1R_HT63T32_Pos) /*!< 0x80000000 */ /************** Bit definition for ETH_MACVTR register ***************/ +#define ETH_MACVTR_VL_VID_Pos (0U) +#define ETH_MACVTR_VL_VID_Msk (0xFFFUL << ETH_MACVTR_VL_VID_Pos) /*!< 0x00000FFF */ +#define ETH_MACVTR_VL_VID ETH_MACVTR_VL_VID_Msk /*!< VLAN Tag Identifier field of VLAN tag */ #define ETH_MACVTR_VL_Pos (0U) #define ETH_MACVTR_VL_Msk (0xFFFFUL << ETH_MACVTR_VL_Pos) /*!< 0x0000FFFF */ #define ETH_MACVTR_VL ETH_MACVTR_VL_Msk /*!< VLAN Tag Identifier for Receive Packets */ @@ -12986,9 +13008,12 @@ typedef struct #define ETH_MACQ0TXFCR_PLT_Pos (4U) #define ETH_MACQ0TXFCR_PLT_Msk (0x7UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000070 */ #define ETH_MACQ0TXFCR_PLT ETH_MACQ0TXFCR_PLT_Msk /*!< Pause Low Threshold */ -#define ETH_MACQ0TXFCR_PLT_0 (0x1UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000010 */ -#define ETH_MACQ0TXFCR_PLT_1 (0x2UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000020 */ -#define ETH_MACQ0TXFCR_PLT_2 (0x4UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000040 */ +#define ETH_MACQ0TXFCR_PLT_MINUS4 (0x0UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000000 */ +#define ETH_MACQ0TXFCR_PLT_MINUS28 (0x1UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000010 */ +#define ETH_MACQ0TXFCR_PLT_MINUS36 (0x2UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000020 */ +#define ETH_MACQ0TXFCR_PLT_MINUS144 (0x3UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000030 */ +#define ETH_MACQ0TXFCR_PLT_MINUS256 (0x4UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000040 */ +#define ETH_MACQ0TXFCR_PLT_MINUS512 (0x5UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000050 */ #define ETH_MACQ0TXFCR_DZPQ_Pos (7U) #define ETH_MACQ0TXFCR_DZPQ_Msk (0x1UL << ETH_MACQ0TXFCR_DZPQ_Pos) /*!< 0x00000080 */ #define ETH_MACQ0TXFCR_DZPQ ETH_MACQ0TXFCR_DZPQ_Msk /*!< Disable Zero-Quanta Pause */ @@ -13555,10 +13580,12 @@ typedef struct #define ETH_MACMDIOAR_CR_Pos (8U) #define ETH_MACMDIOAR_CR_Msk (0xFUL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000F00 */ #define ETH_MACMDIOAR_CR ETH_MACMDIOAR_CR_Msk /*!< CSR Clock Range */ -#define ETH_MACMDIOAR_CR_0 (0x1UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000100 */ -#define ETH_MACMDIOAR_CR_1 (0x2UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000200 */ -#define ETH_MACMDIOAR_CR_2 (0x4UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000400 */ -#define ETH_MACMDIOAR_CR_3 (0x8UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000800 */ +#define ETH_MACMDIOAR_CR_DIV42 (0x0UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000000 */ +#define ETH_MACMDIOAR_CR_DIV62 (0x1UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000100 */ +#define ETH_MACMDIOAR_CR_DIV16 (0x2UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000200 */ +#define ETH_MACMDIOAR_CR_DIV26 (0x3UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000300 */ +#define ETH_MACMDIOAR_CR_DIV102 (0x4UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000400 */ +#define ETH_MACMDIOAR_CR_DIV124 (0x5UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000500 */ #define ETH_MACMDIOAR_NTC_Pos (12U) #define ETH_MACMDIOAR_NTC_Msk (0x7UL << ETH_MACMDIOAR_NTC_Pos) /*!< 0x00007000 */ #define ETH_MACMDIOAR_NTC ETH_MACMDIOAR_NTC_Msk /*!< Number of Training Clocks */ @@ -13997,7 +14024,7 @@ typedef struct #define ETH_MMCTXIMR_TXLPIUSCIM ETH_MMCTXIMR_TXLPIUSCIM_Msk /*!< MMC Transmit LPI microsecond counter interrupt Mask */ #define ETH_MMCTXIMR_TXLPITRCIM_Pos (27U) #define ETH_MMCTXIMR_TXLPITRCIM_Msk (0x1UL << ETH_MMCTXIMR_TXLPITRCIM_Pos) /*!< 0x08000000 */ -#define ETH_MMCTXIMR_TXLPITRCIM ETH_MMC_INTERRUPT_MASK_TXLPITRCIM_Msk /*!< MMC Transmit LPI transition counter interrupt Mask */ +#define ETH_MMCTXIMR_TXLPITRCIM ETH_MMCTXIMR_TXLPITRCIM_Msk /*!< MMC Transmit LPI transition counter interrupt Mask */ /*********** Bit definition for ETH_MMC_TX_SINGLE_COLLISION_GOOD_PACKETS register ************/ #define ETH_MMCTXSCGPR_TXSNGLCOLG_Pos (0U) @@ -16700,9 +16727,10 @@ typedef struct #define ETH_DMAC0CR_DSL_Pos (18U) #define ETH_DMAC0CR_DSL_Msk (0x7UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x001C0000 */ #define ETH_DMAC0CR_DSL ETH_DMAC0CR_DSL_Msk /*!< Descriptor Skip Length */ -#define ETH_DMAC0CR_DSL_0 (0x1UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00040000 */ -#define ETH_DMAC0CR_DSL_1 (0x2UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00080000 */ -#define ETH_DMAC0CR_DSL_2 (0x4UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00100000 */ +#define ETH_DMACCR_DSL_0BIT (0x0UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00000000 */ +#define ETH_DMACCR_DSL_32BIT (0x1UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00040000 */ +#define ETH_DMACCR_DSL_64BIT (0x2UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00080000 */ +#define ETH_DMACCR_DSL_128BIT (0x4UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00100000 */ /************* Bit definition for ETH_DMAC0TXCR register *************/ #define ETH_DMAC0TXCR_ST_Pos (0U) @@ -16723,12 +16751,12 @@ typedef struct #define ETH_DMAC0TXCR_TXPBL_Pos (16U) #define ETH_DMAC0TXCR_TXPBL_Msk (0x3FUL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x003F0000 */ #define ETH_DMAC0TXCR_TXPBL ETH_DMAC0TXCR_TXPBL_Msk /*!< Transmit Programmable Burst Length */ -#define ETH_DMAC0TXCR_TXPBL_0 (0x1UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00010000 */ -#define ETH_DMAC0TXCR_TXPBL_1 (0x2UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00020000 */ -#define ETH_DMAC0TXCR_TXPBL_2 (0x4UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00040000 */ -#define ETH_DMAC0TXCR_TXPBL_3 (0x8UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00080000 */ -#define ETH_DMAC0TXCR_TXPBL_4 (0x10UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00100000 */ -#define ETH_DMAC0TXCR_TXPBL_5 (0x20UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00200000 */ +#define ETH_DMAC0TXCR_TXPBL_1PBL (0x1UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00010000 */ +#define ETH_DMAC0TXCR_TXPBL_2PBL (0x2UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00020000 */ +#define ETH_DMAC0TXCR_TXPBL_4PBL (0x4UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00040000 */ +#define ETH_DMAC0TXCR_TXPBL_8PBL (0x8UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00080000 */ +#define ETH_DMAC0TXCR_TXPBL_16PBL (0x10UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00100000 */ +#define ETH_DMAC0TXCR_TXPBL_32PBL (0x20UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00200000 */ #define ETH_DMAC0TXCR_TQOS_Pos (24U) #define ETH_DMAC0TXCR_TQOS_Msk (0xFUL << ETH_DMAC0TXCR_TQOS_Pos) /*!< 0x0F000000 */ #define ETH_DMAC0TXCR_TQOS ETH_DMAC0TXCR_TQOS_Msk /*!< Transmit QOS. */ @@ -16761,12 +16789,12 @@ typedef struct #define ETH_DMAC0RXCR_RXPBL_Pos (16U) #define ETH_DMAC0RXCR_RXPBL_Msk (0x3FUL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x003F0000 */ #define ETH_DMAC0RXCR_RXPBL ETH_DMAC0RXCR_RXPBL_Msk /*!< Receive Programmable Burst Length */ -#define ETH_DMAC0RXCR_RXPBL_0 (0x1UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00010000 */ -#define ETH_DMAC0RXCR_RXPBL_1 (0x2UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00020000 */ -#define ETH_DMAC0RXCR_RXPBL_2 (0x4UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00040000 */ -#define ETH_DMAC0RXCR_RXPBL_3 (0x8UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00080000 */ -#define ETH_DMAC0RXCR_RXPBL_4 (0x10UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00100000 */ -#define ETH_DMAC0RXCR_RXPBL_5 (0x20UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00200000 */ +#define ETH_DMAC0RXCR_RXPBL_1PBL (0x1UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00010000 */ +#define ETH_DMAC0RXCR_RXPBL_2PBL (0x2UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00020000 */ +#define ETH_DMAC0RXCR_RXPBL_4PBL (0x4UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00040000 */ +#define ETH_DMAC0RXCR_RXPBL_8PBL (0x8UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00080000 */ +#define ETH_DMAC0RXCR_RXPBL_16PBL (0x10UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00100000 */ +#define ETH_DMAC0RXCR_RXPBL_32PBL (0x20UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00200000 */ #define ETH_DMAC0RXCR_RQOS_Pos (24U) #define ETH_DMAC0RXCR_RQOS_Msk (0xFUL << ETH_DMAC0RXCR_RQOS_Pos) /*!< 0x0F000000 */ #define ETH_DMAC0RXCR_RQOS ETH_DMAC0RXCR_RQOS_Msk /*!< Rx AXI4 QOS. */ @@ -25812,6 +25840,16 @@ typedef struct #define BSEC_HWCFGR_ECC_USE_Msk (0xFUL << BSEC_HWCFGR_ECC_USE_Pos) /*!< 0x000000F0 */ #define BSEC_HWCFGR_ECC_USE BSEC_HWCFGR_ECC_USE_Msk /*!< protection / redundancy scheme used */ +/******************** Bit definition for BSEC_JTAGIN register ********************/ +#define BSEC_JTAGIN_DATA_Pos (0U) +#define BSEC_JTAGIN_DATA_Msk (0x0000FFFFUL << BSEC_JTAGIN_DATA_Pos) /*!< JTAG Input Data */ +#define BSEC_JTAGIN_DATA BSEC_JTAGIN_DATA_Msk + +/******************** Bit definition for BSEC_JTAGOUT register ********************/ +#define BSEC_JTAGOUT_DATA_Pos (0U) +#define BSEC_JTAGOUT_DATA_Msk (0x0000FFFFUL << BSEC_JTAGOUT_DATA_Pos) /*!< JTAG Output Data */ +#define BSEC_JTAGOUT_DATA BSEC_JTAGOUT_DATA_Msk + /******************** Bit definition for BSEC_VERR register********************/ #define BSEC_VERR_MINREV_Pos (0U) #define BSEC_VERR_MINREV_Msk (0xFUL << BSEC_VERR_MINREV_Pos) /*!< 0x0000000F */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157fxx_cm4.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157fxx_cm4.h index a6a9a88129..1524be361a 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157fxx_cm4.h +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157fxx_cm4.h @@ -12542,16 +12542,19 @@ typedef struct #define ETH_MACCR_PRELEN_Pos (2U) #define ETH_MACCR_PRELEN_Msk (0x3UL << ETH_MACCR_PRELEN_Pos) /*!< 0x0000000C */ #define ETH_MACCR_PRELEN ETH_MACCR_PRELEN_Msk /*!< Preamble Length for Transmit packets */ -#define ETH_MACCR_PRELEN_0 (0x1UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000004 */ -#define ETH_MACCR_PRELEN_1 (0x2UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000008 */ +#define ETH_MACCR_PRELEN_7 (0x0UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000000 */ +#define ETH_MACCR_PRELEN_5 (0x1UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000004 */ +#define ETH_MACCR_PRELEN_3 (0x2UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000006 */ #define ETH_MACCR_DC_Pos (4U) #define ETH_MACCR_DC_Msk (0x1UL << ETH_MACCR_DC_Pos) /*!< 0x00000010 */ #define ETH_MACCR_DC ETH_MACCR_DC_Msk /*!< Deferral Check */ #define ETH_MACCR_BL_Pos (5U) #define ETH_MACCR_BL_Msk (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */ #define ETH_MACCR_BL ETH_MACCR_BL_Msk /*!< Back-Off Limit */ -#define ETH_MACCR_BL_0 (0x1UL << ETH_MACCR_BL_Pos) /*!< 0x00000020 */ -#define ETH_MACCR_BL_1 (0x2UL << ETH_MACCR_BL_Pos) /*!< 0x00000040 */ +#define ETH_MACCR_BL_10 (0x0UL << ETH_MACCR_BL_Pos) /*!< 0x00000000 */ +#define ETH_MACCR_BL_8 (0x1UL << ETH_MACCR_BL_Pos) /*!< 0x00000020 */ +#define ETH_MACCR_BL_4 (0x2UL << ETH_MACCR_BL_Pos) /*!< 0x00000040 */ +#define ETH_MACCR_BL_1 (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */ #define ETH_MACCR_DR_Pos (8U) #define ETH_MACCR_DR_Msk (0x1UL << ETH_MACCR_DR_Pos) /*!< 0x00000100 */ #define ETH_MACCR_DR ETH_MACCR_DR_Msk /*!< Disable Retry */ @@ -12603,9 +12606,14 @@ typedef struct #define ETH_MACCR_IPG_Pos (24U) #define ETH_MACCR_IPG_Msk (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */ #define ETH_MACCR_IPG ETH_MACCR_IPG_Msk /*!< Inter-Packet Gap */ -#define ETH_MACCR_IPG_0 (0x1UL << ETH_MACCR_IPG_Pos) /*!< 0x01000000 */ -#define ETH_MACCR_IPG_1 (0x2UL << ETH_MACCR_IPG_Pos) /*!< 0x02000000 */ -#define ETH_MACCR_IPG_2 (0x4UL << ETH_MACCR_IPG_Pos) /*!< 0x04000000 */ +#define ETH_MACCR_IPG_96BIT (0x0UL << ETH_MACCR_IPG_Pos) /*!< 0x00000000 */ +#define ETH_MACCR_IPG_88BIT (0x1UL << ETH_MACCR_IPG_Pos) /*!< 0x01000000 */ +#define ETH_MACCR_IPG_80BIT (0x2UL << ETH_MACCR_IPG_Pos) /*!< 0x02000000 */ +#define ETH_MACCR_IPG_72BIT (0x3UL << ETH_MACCR_IPG_Pos) /*!< 0x03000000 */ +#define ETH_MACCR_IPG_64BIT (0x4UL << ETH_MACCR_IPG_Pos) /*!< 0x04000000 */ +#define ETH_MACCR_IPG_56BIT (0x5UL << ETH_MACCR_IPG_Pos) /*!< 0x05000000 */ +#define ETH_MACCR_IPG_48BIT (0x6UL << ETH_MACCR_IPG_Pos) /*!< 0x06000000 */ +#define ETH_MACCR_IPG_40BIT (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */ #define ETH_MACCR_IPC_Pos (27U) #define ETH_MACCR_IPC_Msk (0x1UL << ETH_MACCR_IPC_Pos) /*!< 0x08000000 */ #define ETH_MACCR_IPC ETH_MACCR_IPC_Msk /*!< Checksum Offload */ @@ -12708,10 +12716,21 @@ typedef struct #define ETH_MACWTR_WTO_Pos (0U) #define ETH_MACWTR_WTO_Msk (0xFUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000F */ #define ETH_MACWTR_WTO ETH_MACWTR_WTO_Msk /*!< Watchdog Timeout */ -#define ETH_MACWTR_WTO_0 (0x1UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000001 */ -#define ETH_MACWTR_WTO_1 (0x2UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000002 */ -#define ETH_MACWTR_WTO_2 (0x4UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000004 */ -#define ETH_MACWTR_WTO_3 (0x8UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000008 */ +#define ETH_MACWTR_WTO_2KB (0x0UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000001 */ +#define ETH_MACWTR_WTO_3KB (0x1UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000001 */ +#define ETH_MACWTR_WTO_4KB (0x2UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000002 */ +#define ETH_MACWTR_WTO_5KB (0x3UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000003 */ +#define ETH_MACWTR_WTO_6KB (0x4UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000004 */ +#define ETH_MACWTR_WTO_7KB (0x5UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000005 */ +#define ETH_MACWTR_WTO_8KB (0x6UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000006 */ +#define ETH_MACWTR_WTO_9KB (0x7UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000007 */ +#define ETH_MACWTR_WTO_10KB (0x8UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000008 */ +#define ETH_MACWTR_WTO_11KB (0x9UL << ETH_MACWTR_WTO_Pos) /*!< 0x00000009 */ +#define ETH_MACWTR_WTO_12KB (0xAUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000A */ +#define ETH_MACWTR_WTO_13KB (0xBUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000B */ +#define ETH_MACWTR_WTO_14KB (0xCUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000C */ +#define ETH_MACWTR_WTO_15KB (0xDUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000D */ +#define ETH_MACWTR_WTO_16KB (0xEUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000E */ #define ETH_MACWTR_PWE_Pos (8U) #define ETH_MACWTR_PWE_Msk (0x1UL << ETH_MACWTR_PWE_Pos) /*!< 0x00000100 */ #define ETH_MACWTR_PWE ETH_MACWTR_PWE_Msk /*!< Programmable Watchdog Enable */ @@ -12791,6 +12810,9 @@ typedef struct #define ETH_MACHT1R_HT63T32_31 (0x80000000UL << ETH_MACHT1R_HT63T32_Pos) /*!< 0x80000000 */ /************** Bit definition for ETH_MACVTR register ***************/ +#define ETH_MACVTR_VL_VID_Pos (0U) +#define ETH_MACVTR_VL_VID_Msk (0xFFFUL << ETH_MACVTR_VL_VID_Pos) /*!< 0x00000FFF */ +#define ETH_MACVTR_VL_VID ETH_MACVTR_VL_VID_Msk /*!< VLAN Tag Identifier field of VLAN tag */ #define ETH_MACVTR_VL_Pos (0U) #define ETH_MACVTR_VL_Msk (0xFFFFUL << ETH_MACVTR_VL_Pos) /*!< 0x0000FFFF */ #define ETH_MACVTR_VL ETH_MACVTR_VL_Msk /*!< VLAN Tag Identifier for Receive Packets */ @@ -12952,9 +12974,12 @@ typedef struct #define ETH_MACQ0TXFCR_PLT_Pos (4U) #define ETH_MACQ0TXFCR_PLT_Msk (0x7UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000070 */ #define ETH_MACQ0TXFCR_PLT ETH_MACQ0TXFCR_PLT_Msk /*!< Pause Low Threshold */ -#define ETH_MACQ0TXFCR_PLT_0 (0x1UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000010 */ -#define ETH_MACQ0TXFCR_PLT_1 (0x2UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000020 */ -#define ETH_MACQ0TXFCR_PLT_2 (0x4UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000040 */ +#define ETH_MACQ0TXFCR_PLT_MINUS4 (0x0UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000000 */ +#define ETH_MACQ0TXFCR_PLT_MINUS28 (0x1UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000010 */ +#define ETH_MACQ0TXFCR_PLT_MINUS36 (0x2UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000020 */ +#define ETH_MACQ0TXFCR_PLT_MINUS144 (0x3UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000030 */ +#define ETH_MACQ0TXFCR_PLT_MINUS256 (0x4UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000040 */ +#define ETH_MACQ0TXFCR_PLT_MINUS512 (0x5UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000050 */ #define ETH_MACQ0TXFCR_DZPQ_Pos (7U) #define ETH_MACQ0TXFCR_DZPQ_Msk (0x1UL << ETH_MACQ0TXFCR_DZPQ_Pos) /*!< 0x00000080 */ #define ETH_MACQ0TXFCR_DZPQ ETH_MACQ0TXFCR_DZPQ_Msk /*!< Disable Zero-Quanta Pause */ @@ -13521,10 +13546,12 @@ typedef struct #define ETH_MACMDIOAR_CR_Pos (8U) #define ETH_MACMDIOAR_CR_Msk (0xFUL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000F00 */ #define ETH_MACMDIOAR_CR ETH_MACMDIOAR_CR_Msk /*!< CSR Clock Range */ -#define ETH_MACMDIOAR_CR_0 (0x1UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000100 */ -#define ETH_MACMDIOAR_CR_1 (0x2UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000200 */ -#define ETH_MACMDIOAR_CR_2 (0x4UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000400 */ -#define ETH_MACMDIOAR_CR_3 (0x8UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000800 */ +#define ETH_MACMDIOAR_CR_DIV42 (0x0UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000000 */ +#define ETH_MACMDIOAR_CR_DIV62 (0x1UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000100 */ +#define ETH_MACMDIOAR_CR_DIV16 (0x2UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000200 */ +#define ETH_MACMDIOAR_CR_DIV26 (0x3UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000300 */ +#define ETH_MACMDIOAR_CR_DIV102 (0x4UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000400 */ +#define ETH_MACMDIOAR_CR_DIV124 (0x5UL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000500 */ #define ETH_MACMDIOAR_NTC_Pos (12U) #define ETH_MACMDIOAR_NTC_Msk (0x7UL << ETH_MACMDIOAR_NTC_Pos) /*!< 0x00007000 */ #define ETH_MACMDIOAR_NTC ETH_MACMDIOAR_NTC_Msk /*!< Number of Training Clocks */ @@ -13963,7 +13990,7 @@ typedef struct #define ETH_MMCTXIMR_TXLPIUSCIM ETH_MMCTXIMR_TXLPIUSCIM_Msk /*!< MMC Transmit LPI microsecond counter interrupt Mask */ #define ETH_MMCTXIMR_TXLPITRCIM_Pos (27U) #define ETH_MMCTXIMR_TXLPITRCIM_Msk (0x1UL << ETH_MMCTXIMR_TXLPITRCIM_Pos) /*!< 0x08000000 */ -#define ETH_MMCTXIMR_TXLPITRCIM ETH_MMC_INTERRUPT_MASK_TXLPITRCIM_Msk /*!< MMC Transmit LPI transition counter interrupt Mask */ +#define ETH_MMCTXIMR_TXLPITRCIM ETH_MMCTXIMR_TXLPITRCIM_Msk /*!< MMC Transmit LPI transition counter interrupt Mask */ /*********** Bit definition for ETH_MMC_TX_SINGLE_COLLISION_GOOD_PACKETS register ************/ #define ETH_MMCTXSCGPR_TXSNGLCOLG_Pos (0U) @@ -16666,9 +16693,10 @@ typedef struct #define ETH_DMAC0CR_DSL_Pos (18U) #define ETH_DMAC0CR_DSL_Msk (0x7UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x001C0000 */ #define ETH_DMAC0CR_DSL ETH_DMAC0CR_DSL_Msk /*!< Descriptor Skip Length */ -#define ETH_DMAC0CR_DSL_0 (0x1UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00040000 */ -#define ETH_DMAC0CR_DSL_1 (0x2UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00080000 */ -#define ETH_DMAC0CR_DSL_2 (0x4UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00100000 */ +#define ETH_DMACCR_DSL_0BIT (0x0UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00000000 */ +#define ETH_DMACCR_DSL_32BIT (0x1UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00040000 */ +#define ETH_DMACCR_DSL_64BIT (0x2UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00080000 */ +#define ETH_DMACCR_DSL_128BIT (0x4UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00100000 */ /************* Bit definition for ETH_DMAC0TXCR register *************/ #define ETH_DMAC0TXCR_ST_Pos (0U) @@ -16689,12 +16717,12 @@ typedef struct #define ETH_DMAC0TXCR_TXPBL_Pos (16U) #define ETH_DMAC0TXCR_TXPBL_Msk (0x3FUL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x003F0000 */ #define ETH_DMAC0TXCR_TXPBL ETH_DMAC0TXCR_TXPBL_Msk /*!< Transmit Programmable Burst Length */ -#define ETH_DMAC0TXCR_TXPBL_0 (0x1UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00010000 */ -#define ETH_DMAC0TXCR_TXPBL_1 (0x2UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00020000 */ -#define ETH_DMAC0TXCR_TXPBL_2 (0x4UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00040000 */ -#define ETH_DMAC0TXCR_TXPBL_3 (0x8UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00080000 */ -#define ETH_DMAC0TXCR_TXPBL_4 (0x10UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00100000 */ -#define ETH_DMAC0TXCR_TXPBL_5 (0x20UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00200000 */ +#define ETH_DMAC0TXCR_TXPBL_1PBL (0x1UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00010000 */ +#define ETH_DMAC0TXCR_TXPBL_2PBL (0x2UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00020000 */ +#define ETH_DMAC0TXCR_TXPBL_4PBL (0x4UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00040000 */ +#define ETH_DMAC0TXCR_TXPBL_8PBL (0x8UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00080000 */ +#define ETH_DMAC0TXCR_TXPBL_16PBL (0x10UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00100000 */ +#define ETH_DMAC0TXCR_TXPBL_32PBL (0x20UL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00200000 */ #define ETH_DMAC0TXCR_TQOS_Pos (24U) #define ETH_DMAC0TXCR_TQOS_Msk (0xFUL << ETH_DMAC0TXCR_TQOS_Pos) /*!< 0x0F000000 */ #define ETH_DMAC0TXCR_TQOS ETH_DMAC0TXCR_TQOS_Msk /*!< Transmit QOS. */ @@ -16727,12 +16755,12 @@ typedef struct #define ETH_DMAC0RXCR_RXPBL_Pos (16U) #define ETH_DMAC0RXCR_RXPBL_Msk (0x3FUL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x003F0000 */ #define ETH_DMAC0RXCR_RXPBL ETH_DMAC0RXCR_RXPBL_Msk /*!< Receive Programmable Burst Length */ -#define ETH_DMAC0RXCR_RXPBL_0 (0x1UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00010000 */ -#define ETH_DMAC0RXCR_RXPBL_1 (0x2UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00020000 */ -#define ETH_DMAC0RXCR_RXPBL_2 (0x4UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00040000 */ -#define ETH_DMAC0RXCR_RXPBL_3 (0x8UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00080000 */ -#define ETH_DMAC0RXCR_RXPBL_4 (0x10UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00100000 */ -#define ETH_DMAC0RXCR_RXPBL_5 (0x20UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00200000 */ +#define ETH_DMAC0RXCR_RXPBL_1PBL (0x1UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00010000 */ +#define ETH_DMAC0RXCR_RXPBL_2PBL (0x2UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00020000 */ +#define ETH_DMAC0RXCR_RXPBL_4PBL (0x4UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00040000 */ +#define ETH_DMAC0RXCR_RXPBL_8PBL (0x8UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00080000 */ +#define ETH_DMAC0RXCR_RXPBL_16PBL (0x10UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00100000 */ +#define ETH_DMAC0RXCR_RXPBL_32PBL (0x20UL << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00200000 */ #define ETH_DMAC0RXCR_RQOS_Pos (24U) #define ETH_DMAC0RXCR_RQOS_Msk (0xFUL << ETH_DMAC0RXCR_RQOS_Pos) /*!< 0x0F000000 */ #define ETH_DMAC0RXCR_RQOS ETH_DMAC0RXCR_RQOS_Msk /*!< Rx AXI4 QOS. */ @@ -25778,6 +25806,16 @@ typedef struct #define BSEC_HWCFGR_ECC_USE_Msk (0xFUL << BSEC_HWCFGR_ECC_USE_Pos) /*!< 0x000000F0 */ #define BSEC_HWCFGR_ECC_USE BSEC_HWCFGR_ECC_USE_Msk /*!< protection / redundancy scheme used */ +/******************** Bit definition for BSEC_JTAGIN register ********************/ +#define BSEC_JTAGIN_DATA_Pos (0U) +#define BSEC_JTAGIN_DATA_Msk (0x0000FFFFUL << BSEC_JTAGIN_DATA_Pos) /*!< JTAG Input Data */ +#define BSEC_JTAGIN_DATA BSEC_JTAGIN_DATA_Msk + +/******************** Bit definition for BSEC_JTAGOUT register ********************/ +#define BSEC_JTAGOUT_DATA_Pos (0U) +#define BSEC_JTAGOUT_DATA_Msk (0x0000FFFFUL << BSEC_JTAGOUT_DATA_Pos) /*!< JTAG Output Data */ +#define BSEC_JTAGOUT_DATA BSEC_JTAGOUT_DATA_Msk + /******************** Bit definition for BSEC_VERR register********************/ #define BSEC_VERR_MINREV_Pos (0U) #define BSEC_VERR_MINREV_Msk (0xFUL << BSEC_VERR_MINREV_Pos) /*!< 0x0000000F */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp1xx.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp1xx.h index b9706dc23d..44fffb9c7b 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp1xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp1xx.h @@ -69,7 +69,7 @@ * @brief CMSIS Device version number */ #define __STM32MP1xx_CMSIS_VERSION_MAIN (0x01U) /*!< [31:24] main version */ -#define __STM32MP1xx_CMSIS_VERSION_SUB1 (0x05U) /*!< [23:16] sub1 version */ +#define __STM32MP1xx_CMSIS_VERSION_SUB1 (0x06U) /*!< [23:16] sub1 version */ #define __STM32MP1xx_CMSIS_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ #define __STM32MP1xx_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32MP1xx_CMSIS_VERSION ((__CMSIS_DEVICE_VERSION_MAIN << 24)\ diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Release_Notes.html b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Release_Notes.html index 19f49a5e93..972d4eeded 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Release_Notes.html +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Release_Notes.html @@ -43,7 +43,7 @@

Purpose

Update History

- +

Main Changes

This is a Maintenance release for STM32MP15xx CMSIS

@@ -51,6 +51,27 @@

Contents

  • Update bit definition in header files:
      +
    • BSEC : Add missing registers
      • +
    • ETH : Update bitfield names
      • +
    • +
  • Update License declaration for startup and linker files
    • +
  • Change include in system file ( alignment with other STM32 families)
    • +
+

Known Limitations

+

None

+

Dependencies

+

None

+
+
+
+ +
+

Main Changes

+

This is a Maintenance release for STM32MP15xx CMSIS

+

Contents

+
    +
  • Update bit definition in header files: +
    • DDR : Update DDR bit registers
    • USBPHYC: Update structure and add bitfields
    • Fix MISRA warnings: @@ -67,18 +88,18 @@

      Contents

    • Update the licenses declaration
-

Known Limitations

+

Known Limitations

None

-

Dependencies

+

Dependencies

None

-

Main Changes

+

Main Changes

This is a Maintenance release for STM32MP15xx CMSIS

-

Contents

+

Contents

  • Header files:
      @@ -86,18 +107,18 @@

      Contents

    • Update RNG register structure
-

Known Limitations

+

Known Limitations

None

-

Dependencies

+

Dependencies

None

-

Main Changes

+

Main Changes

This is a Maintenance release for STM32MP15xx CMSIS

-

Contents

+

Contents

  • Header files:
      @@ -106,18 +127,18 @@

      Contents

    • Fix typo in MDMA register definition
-

Known Limitations

+

Known Limitations

None

-

Dependencies

+

Dependencies

None

-

Main Changes

+

Main Changes

This is a Maintenance release for STM32MP15xx CMSIS

-

Contents

+

Contents

  • Header files:
      @@ -131,18 +152,18 @@

      Contents

    • Add OpenAMP region ( region present by default, to comment if needed )
-

Known Limitations

+

Known Limitations

None

-

Dependencies

+

Dependencies

None

-

Main Changes

+

Main Changes

This is the First Maintenance release for STM32MP15xx CMSIS

-

Contents

+

Contents

  • Header files:
      @@ -163,24 +184,24 @@

      Contents

  • Update startup file for KEIL and IAR
-

Known Limitations

+

Known Limitations

None

-

Dependencies

+

Dependencies

None

-

Main Changes

+

Main Changes

This is the First Official release for STM32MP15xx CMSIS

-

Contents

+

Contents

  • First official release version of bits and registers definition aligned with STM32MP1 reference manual.
-

Known Limitations

+

Known Limitations

None

-

Dependencies

+

Dependencies

None

diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Source/Templates/gcc/linker/stm32mp15xx_m4.ld b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Source/Templates/gcc/linker/stm32mp15xx_m4.ld index cfdbf34344..f3841e592e 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Source/Templates/gcc/linker/stm32mp15xx_m4.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Source/Templates/gcc/linker/stm32mp15xx_m4.ld @@ -18,15 +18,14 @@ ***************************************************************************** ** @attention ** -**

© Copyright (c) 2019 STMicroelectronics. -** All rights reserved.

+** Copyright (c) 2019 STMicroelectronics. +** All rights reserved. ** -** This software component is licensed by ST under BSD 3-Clause license, -** the License; You may not use this file except in compliance with the -** License. You may obtain a copy of the License at: -** opensource.org/licenses/BSD-3-Clause +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. ** -***************************************************************************** +****************************************************************************** */ /* Entry Point */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Source/Templates/gcc/startup_stm32mp151axx_cm4.s b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Source/Templates/gcc/startup_stm32mp151axx_cm4.s index 652471d62d..29fbb40e4e 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Source/Templates/gcc/startup_stm32mp151axx_cm4.s +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Source/Templates/gcc/startup_stm32mp151axx_cm4.s @@ -14,13 +14,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2019 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Source/Templates/gcc/startup_stm32mp151cxx_cm4.s b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Source/Templates/gcc/startup_stm32mp151cxx_cm4.s index 51415f43d4..f2e7f6838d 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Source/Templates/gcc/startup_stm32mp151cxx_cm4.s +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Source/Templates/gcc/startup_stm32mp151cxx_cm4.s @@ -14,13 +14,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2019 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Source/Templates/gcc/startup_stm32mp153axx_cm4.s b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Source/Templates/gcc/startup_stm32mp153axx_cm4.s index 2745bbd8e2..4db19f0a3b 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Source/Templates/gcc/startup_stm32mp153axx_cm4.s +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Source/Templates/gcc/startup_stm32mp153axx_cm4.s @@ -14,13 +14,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2019 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Source/Templates/gcc/startup_stm32mp153cxx_cm4.s b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Source/Templates/gcc/startup_stm32mp153cxx_cm4.s index e43a955cd7..767f10d60a 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Source/Templates/gcc/startup_stm32mp153cxx_cm4.s +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Source/Templates/gcc/startup_stm32mp153cxx_cm4.s @@ -14,13 +14,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2019 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Source/Templates/gcc/startup_stm32mp157axx_cm4.s b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Source/Templates/gcc/startup_stm32mp157axx_cm4.s index 1e6a46cda6..e4180ea243 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Source/Templates/gcc/startup_stm32mp157axx_cm4.s +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Source/Templates/gcc/startup_stm32mp157axx_cm4.s @@ -14,13 +14,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2019 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Source/Templates/gcc/startup_stm32mp157cxx_cm4.s b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Source/Templates/gcc/startup_stm32mp157cxx_cm4.s index 7a3388d8a3..b2622f7669 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Source/Templates/gcc/startup_stm32mp157cxx_cm4.s +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Source/Templates/gcc/startup_stm32mp157cxx_cm4.s @@ -14,13 +14,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2019 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Source/Templates/gcc/startup_stm32mp15xx.s b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Source/Templates/gcc/startup_stm32mp15xx.s index 3b0634e9f9..96e9ce6548 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Source/Templates/gcc/startup_stm32mp15xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Source/Templates/gcc/startup_stm32mp15xx.s @@ -14,13 +14,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2019 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -788,5 +787,3 @@ g_pfnVectors: .weak WAKEUP_PIN_IRQHandler .thumb_set WAKEUP_PIN_IRQHandler,Default_Handler -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Source/Templates/system_stm32mp1xx.c b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Source/Templates/system_stm32mp1xx.c index 62d53954ea..d00a7ae855 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Source/Templates/system_stm32mp1xx.c +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Source/Templates/system_stm32mp1xx.c @@ -45,7 +45,7 @@ * @{ */ -#include "stm32mp1xx_hal.h" +#include "stm32mp1xx.h" /** * @} diff --git a/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md b/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md index fa481a149e..31aba7a745 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md +++ b/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md @@ -13,7 +13,7 @@ * STM32L1: 2.3.2 * STM32L4: 1.7.2 * STM32L5: 1.0.5 - * STM32MP1: 1.5.0 + * STM32MP1: 1.6.0 * STM32U5: 1.1.0 * STM32WB: 1.12.0 * STM32WL: 1.2.0 diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h index bc10dc166e..5362681f1f 100644 --- a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +++ b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h @@ -37,14 +37,16 @@ extern "C" { #define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF #define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR #define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR -#if defined(STM32U5) +#if defined(STM32U5) || defined(STM32H7) || defined(STM32MP1) #define CRYP_DATATYPE_32B CRYP_NO_SWAP #define CRYP_DATATYPE_16B CRYP_HALFWORD_SWAP #define CRYP_DATATYPE_8B CRYP_BYTE_SWAP #define CRYP_DATATYPE_1B CRYP_BIT_SWAP +#if defined(STM32U5) #define CRYP_CCF_CLEAR CRYP_CLEAR_CCF #define CRYP_ERR_CLEAR CRYP_CLEAR_RWEIF #endif /* STM32U5 */ +#endif /* STM32U5 || STM32H7 || STM32MP1 */ /** * @} */ @@ -104,6 +106,12 @@ extern "C" { #if defined(STM32H7) #define ADC_CHANNEL_VBAT_DIV4 ADC_CHANNEL_VBAT #endif /* STM32H7 */ + +#if defined(STM32U5) +#define ADC_SAMPLETIME_5CYCLE ADC_SAMPLETIME_5CYCLES +#define ADC_SAMPLETIME_391CYCLES_5 ADC_SAMPLETIME_391CYCLES +#define ADC4_SAMPLETIME_160CYCLES_5 ADC4_SAMPLETIME_814CYCLES_5 +#endif /* STM32U5 */ /** * @} */ @@ -411,6 +419,10 @@ extern "C" { #define DAC_TRIGGER_LP2_OUT DAC_TRIGGER_LPTIM2_OUT #endif /* STM32H7 */ + +#if defined(STM32U5) +#define GPDMA1_REQUEST_DCMI GPDMA1_REQUEST_DCMI_PSSI +#endif /* STM32U5 */ /** * @} */ @@ -658,6 +670,20 @@ extern "C" { #if defined(STM32U5) #define GPIO_AF0_RTC_50Hz GPIO_AF0_RTC_50HZ #endif /* STM32U5 */ +#if defined(STM32U5) +#define GPIO_AF0_S2DSTOP GPIO_AF0_SRDSTOP +#define GPIO_AF11_LPGPIO GPIO_AF11_LPGPIO1 +#endif /* STM32U5 */ +/** + * @} + */ + +/** @defgroup HAL_GTZC_Aliased_Defines HAL GTZC Aliased Defines maintained for legacy purpose + * @{ + */ +#if defined(STM32U5) +#define GTZC_PERIPH_DCMI GTZC_PERIPH_DCMI_PSSI +#endif /* STM32U5 */ /** * @} */ @@ -895,9 +921,19 @@ extern "C" { #define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS #define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS + +/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose + * @{ + */ +#define HAL_LPTIM_ReadCompare HAL_LPTIM_ReadCapturedValue +/** + * @} + */ + #if defined(STM32U5) #define LPTIM_ISR_CC1 LPTIM_ISR_CC1IF #define LPTIM_ISR_CC2 LPTIM_ISR_CC2IF +#define LPTIM_CHANNEL_ALL 0x00000000U #endif /* STM32U5 */ /** * @} @@ -1050,8 +1086,8 @@ extern "C" { #define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT #define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT -#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1 -#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1 +#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1 +#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1 #define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2 #define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE @@ -1062,15 +1098,22 @@ extern "C" { #define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 #define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 +#if defined(STM32F7) +#define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK +#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_IT_ENABLE_BITS_MASK +#endif /* STM32F7 */ + #if defined(STM32H7) #define RTC_TAMPCR_TAMPXE RTC_TAMPER_X #define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT +#endif /* STM32H7 */ +#if defined(STM32F7) || defined(STM32H7) #define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1 #define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2 #define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3 -#define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMPALL -#endif /* STM32H7 */ +#define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMP +#endif /* STM32F7 || STM32H7 */ /** * @} @@ -1237,6 +1280,10 @@ extern "C" { #define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2 #endif +#if defined(STM32U5) || defined(STM32MP2) +#define OCREF_CLEAR_SELECT_Pos OCREF_CLEAR_SELECT_POS +#define OCREF_CLEAR_SELECT_Msk OCREF_CLEAR_SELECT_MSK +#endif /** * @} */ @@ -1667,6 +1714,79 @@ extern "C" { #define PWR_MODE_EVT PWR_PVD_MODE_NORMAL +#if defined (STM32U5) +#define PWR_SRAM1_PAGE1_STOP_RETENTION PWR_SRAM1_PAGE1_STOP +#define PWR_SRAM1_PAGE2_STOP_RETENTION PWR_SRAM1_PAGE2_STOP +#define PWR_SRAM1_PAGE3_STOP_RETENTION PWR_SRAM1_PAGE3_STOP +#define PWR_SRAM1_PAGE4_STOP_RETENTION PWR_SRAM1_PAGE4_STOP +#define PWR_SRAM1_PAGE5_STOP_RETENTION PWR_SRAM1_PAGE5_STOP +#define PWR_SRAM1_PAGE6_STOP_RETENTION PWR_SRAM1_PAGE6_STOP +#define PWR_SRAM1_PAGE7_STOP_RETENTION PWR_SRAM1_PAGE7_STOP +#define PWR_SRAM1_PAGE8_STOP_RETENTION PWR_SRAM1_PAGE8_STOP +#define PWR_SRAM1_PAGE9_STOP_RETENTION PWR_SRAM1_PAGE9_STOP +#define PWR_SRAM1_PAGE10_STOP_RETENTION PWR_SRAM1_PAGE10_STOP +#define PWR_SRAM1_PAGE11_STOP_RETENTION PWR_SRAM1_PAGE11_STOP +#define PWR_SRAM1_PAGE12_STOP_RETENTION PWR_SRAM1_PAGE12_STOP +#define PWR_SRAM1_FULL_STOP_RETENTION PWR_SRAM1_FULL_STOP + +#define PWR_SRAM2_PAGE1_STOP_RETENTION PWR_SRAM2_PAGE1_STOP +#define PWR_SRAM2_PAGE2_STOP_RETENTION PWR_SRAM2_PAGE2_STOP +#define PWR_SRAM2_FULL_STOP_RETENTION PWR_SRAM2_FULL_STOP + +#define PWR_SRAM3_PAGE1_STOP_RETENTION PWR_SRAM3_PAGE1_STOP +#define PWR_SRAM3_PAGE2_STOP_RETENTION PWR_SRAM3_PAGE2_STOP +#define PWR_SRAM3_PAGE3_STOP_RETENTION PWR_SRAM3_PAGE3_STOP +#define PWR_SRAM3_PAGE4_STOP_RETENTION PWR_SRAM3_PAGE4_STOP +#define PWR_SRAM3_PAGE5_STOP_RETENTION PWR_SRAM3_PAGE5_STOP +#define PWR_SRAM3_PAGE6_STOP_RETENTION PWR_SRAM3_PAGE6_STOP +#define PWR_SRAM3_PAGE7_STOP_RETENTION PWR_SRAM3_PAGE7_STOP +#define PWR_SRAM3_PAGE8_STOP_RETENTION PWR_SRAM3_PAGE8_STOP +#define PWR_SRAM3_PAGE9_STOP_RETENTION PWR_SRAM3_PAGE9_STOP +#define PWR_SRAM3_PAGE10_STOP_RETENTION PWR_SRAM3_PAGE10_STOP +#define PWR_SRAM3_PAGE11_STOP_RETENTION PWR_SRAM3_PAGE11_STOP +#define PWR_SRAM3_PAGE12_STOP_RETENTION PWR_SRAM3_PAGE12_STOP +#define PWR_SRAM3_PAGE13_STOP_RETENTION PWR_SRAM3_PAGE13_STOP +#define PWR_SRAM3_FULL_STOP_RETENTION PWR_SRAM3_FULL_STOP + +#define PWR_SRAM4_FULL_STOP_RETENTION PWR_SRAM4_FULL_STOP + +#define PWR_SRAM5_PAGE1_STOP_RETENTION PWR_SRAM5_PAGE1_STOP +#define PWR_SRAM5_PAGE2_STOP_RETENTION PWR_SRAM5_PAGE2_STOP +#define PWR_SRAM5_PAGE3_STOP_RETENTION PWR_SRAM5_PAGE3_STOP +#define PWR_SRAM5_PAGE4_STOP_RETENTION PWR_SRAM5_PAGE4_STOP +#define PWR_SRAM5_PAGE5_STOP_RETENTION PWR_SRAM5_PAGE5_STOP +#define PWR_SRAM5_PAGE6_STOP_RETENTION PWR_SRAM5_PAGE6_STOP +#define PWR_SRAM5_PAGE7_STOP_RETENTION PWR_SRAM5_PAGE7_STOP +#define PWR_SRAM5_PAGE8_STOP_RETENTION PWR_SRAM5_PAGE8_STOP +#define PWR_SRAM5_PAGE9_STOP_RETENTION PWR_SRAM5_PAGE9_STOP +#define PWR_SRAM5_PAGE10_STOP_RETENTION PWR_SRAM5_PAGE10_STOP +#define PWR_SRAM5_PAGE11_STOP_RETENTION PWR_SRAM5_PAGE11_STOP +#define PWR_SRAM5_PAGE12_STOP_RETENTION PWR_SRAM5_PAGE12_STOP +#define PWR_SRAM5_PAGE13_STOP_RETENTION PWR_SRAM5_PAGE13_STOP +#define PWR_SRAM5_FULL_STOP_RETENTION PWR_SRAM5_FULL_STOP + +#define PWR_ICACHE_FULL_STOP_RETENTION PWR_ICACHE_FULL_STOP +#define PWR_DCACHE1_FULL_STOP_RETENTION PWR_DCACHE1_FULL_STOP +#define PWR_DCACHE2_FULL_STOP_RETENTION PWR_DCACHE2_FULL_STOP +#define PWR_DMA2DRAM_FULL_STOP_RETENTION PWR_DMA2DRAM_FULL_STOP +#define PWR_PERIPHRAM_FULL_STOP_RETENTION PWR_PERIPHRAM_FULL_STOP +#define PWR_PKA32RAM_FULL_STOP_RETENTION PWR_PKA32RAM_FULL_STOP +#define PWR_GRAPHICPRAM_FULL_STOP_RETENTION PWR_GRAPHICPRAM_FULL_STOP +#define PWR_DSIRAM_FULL_STOP_RETENTION PWR_DSIRAM_FULL_STOP + +#define PWR_SRAM2_PAGE1_STANDBY_RETENTION PWR_SRAM2_PAGE1_STANDBY +#define PWR_SRAM2_PAGE2_STANDBY_RETENTION PWR_SRAM2_PAGE2_STANDBY +#define PWR_SRAM2_FULL_STANDBY_RETENTION PWR_SRAM2_FULL_STANDBY + +#define PWR_SRAM1_FULL_RUN_RETENTION PWR_SRAM1_FULL_RUN +#define PWR_SRAM2_FULL_RUN_RETENTION PWR_SRAM2_FULL_RUN +#define PWR_SRAM3_FULL_RUN_RETENTION PWR_SRAM3_FULL_RUN +#define PWR_SRAM4_FULL_RUN_RETENTION PWR_SRAM4_FULL_RUN +#define PWR_SRAM5_FULL_RUN_RETENTION PWR_SRAM5_FULL_RUN + +#define PWR_ALL_RAM_RUN_RETENTION_MASK PWR_ALL_RAM_RUN_MASK +#endif + /** * @} */ @@ -3413,8 +3533,8 @@ extern "C" { #define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2 #define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1 #if defined(STM32U5) -#define MSIKPLLModeSEL RCC_MSIKPLL_MODE_SEL -#define MSISPLLModeSEL RCC_MSISPLL_MODE_SEL +#define MSIKPLLModeSEL RCC_MSIKPLL_MODE_SEL +#define MSISPLLModeSEL RCC_MSISPLL_MODE_SEL #define __HAL_RCC_AHB21_CLK_DISABLE __HAL_RCC_AHB2_1_CLK_DISABLE #define __HAL_RCC_AHB22_CLK_DISABLE __HAL_RCC_AHB2_2_CLK_DISABLE #define __HAL_RCC_AHB1_CLK_Disable_Clear __HAL_RCC_AHB1_CLK_ENABLE @@ -3430,13 +3550,20 @@ extern "C" { #define RCC_CLK48CLKSOURCE_PLL2 RCC_ICLK_CLKSOURCE_PLL2 #define RCC_CLK48CLKSOURCE_PLL1 RCC_ICLK_CLKSOURCE_PLL1 #define RCC_CLK48CLKSOURCE_MSIK RCC_ICLK_CLKSOURCE_MSIK -#define __HAL_RCC_ADC1_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE -#define __HAL_RCC_ADC1_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE -#define __HAL_RCC_ADC1_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED -#define __HAL_RCC_ADC1_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED -#define __HAL_RCC_ADC1_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET -#define __HAL_RCC_ADC1_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET -#endif +#define __HAL_RCC_ADC1_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE +#define __HAL_RCC_ADC1_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE +#define __HAL_RCC_ADC1_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED +#define __HAL_RCC_ADC1_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED +#define __HAL_RCC_ADC1_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET +#define __HAL_RCC_ADC1_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET +#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC12_CLK_SLEEP_ENABLE +#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC12_CLK_SLEEP_DISABLE +#define __HAL_RCC_GET_CLK48_SOURCE __HAL_RCC_GET_ICLK_SOURCE +#define __HAL_RCC_PLLFRACN_ENABLE __HAL_RCC_PLL_FRACN_ENABLE +#define __HAL_RCC_PLLFRACN_DISABLE __HAL_RCC_PLL_FRACN_DISABLE +#define __HAL_RCC_PLLFRACN_CONFIG __HAL_RCC_PLL_FRACN_CONFIG +#define IS_RCC_PLLFRACN_VALUE IS_RCC_PLL_FRACN_VALUE +#endif /* STM32U5 */ /** * @} @@ -3454,7 +3581,8 @@ extern "C" { /** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose * @{ */ -#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) +#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx)|| \ + defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) #else #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG #endif @@ -3518,7 +3646,7 @@ extern "C" { #define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE #define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS -#if !defined(STM32F1) && !defined(STM32F2) && !defined(STM32F4) && !defined(STM32F7) && !defined(STM32L1) +#if !defined(STM32F1) && !defined(STM32F2) && !defined(STM32F4) && !defined(STM32L1) #define eMMC_HIGH_VOLTAGE_RANGE EMMC_HIGH_VOLTAGE_RANGE #define eMMC_DUAL_VOLTAGE_RANGE EMMC_DUAL_VOLTAGE_RANGE #define eMMC_LOW_VOLTAGE_RANGE EMMC_LOW_VOLTAGE_RANGE diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal.h b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal.h index af8ae68f2e..9d51f75788 100644 --- a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal.h +++ b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal.h @@ -751,6 +751,9 @@ void HAL_ResumeTick(void); uint32_t HAL_GetHalVersion(void); uint32_t HAL_GetREVID(void); uint32_t HAL_GetDEVID(void); +uint32_t HAL_GetUIDw0(void); +uint32_t HAL_GetUIDw1(void); +uint32_t HAL_GetUIDw2(void); void HAL_SYSCFG_ETHInterfaceSelect(uint32_t SYSCFG_ETHInterface); void HAL_SYSCFG_AnalogSwitchConfig(uint32_t SYSCFG_AnalogSwitch , uint32_t SYSCFG_SwitchState ); void HAL_SYSCFG_EnableBOOST(void); diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_adc.h b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_adc.h index 2fe375f3f0..d6a4ba499b 100644 --- a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_adc.h +++ b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_adc.h @@ -1752,8 +1752,8 @@ void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc); * @{ */ /* Peripheral Control functions ***********************************************/ -HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig); -HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *AnalogWDGConfig); +HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *pConfig); +HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *pAnalogWDGConfig); /** * @} diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_adc_ex.h b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_adc_ex.h index 3a2d2a932a..b0664a66c6 100644 --- a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_adc_ex.h +++ b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_adc_ex.h @@ -1082,7 +1082,7 @@ HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc); HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_InjectionConfTypeDef *sConfigInjected); #if defined(ADC_MULTIMODE_SUPPORT) -HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode); +HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *pmultimode); #endif /* ADC_MULTIMODE_SUPPORT */ HAL_StatusTypeDef HAL_ADCEx_EnableInjectedQueue(ADC_HandleTypeDef *hadc); HAL_StatusTypeDef HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef *hadc); diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_crc.h b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_crc.h index ab066ce0a8..77e8646f27 100644 --- a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_crc.h +++ b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_crc.h @@ -59,19 +59,22 @@ typedef struct { uint8_t DefaultPolynomialUse; /*!< This parameter is a value of @ref CRC_Default_Polynomial and indicates if default polynomial is used. If set to DEFAULT_POLYNOMIAL_ENABLE, resort to default - X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2+ X +1. + X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + + X^4 + X^2+ X +1. In that case, there is no need to set GeneratingPolynomial field. - If otherwise set to DEFAULT_POLYNOMIAL_DISABLE, GeneratingPolynomial and CRCLength fields must be set. */ + If otherwise set to DEFAULT_POLYNOMIAL_DISABLE, GeneratingPolynomial and + CRCLength fields must be set. */ uint8_t DefaultInitValueUse; /*!< This parameter is a value of @ref CRC_Default_InitValue_Use and indicates if default init value is used. If set to DEFAULT_INIT_VALUE_ENABLE, resort to default - 0xFFFFFFFF value. In that case, there is no need to set InitValue field. - If otherwise set to DEFAULT_INIT_VALUE_DISABLE, InitValue field must be set. */ + 0xFFFFFFFF value. In that case, there is no need to set InitValue field. If + otherwise set to DEFAULT_INIT_VALUE_DISABLE, InitValue field must be set. */ uint32_t GeneratingPolynomial; /*!< Set CRC generating polynomial as a 7, 8, 16 or 32-bit long value for a polynomial degree - respectively equal to 7, 8, 16 or 32. This field is written in normal representation, - e.g., for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65. - No need to specify it if DefaultPolynomialUse is set to DEFAULT_POLYNOMIAL_ENABLE. */ + respectively equal to 7, 8, 16 or 32. This field is written in normal, + representation e.g., for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 + is written 0x65. No need to specify it if DefaultPolynomialUse is set to + DEFAULT_POLYNOMIAL_ENABLE. */ uint32_t CRCLength; /*!< This parameter is a value of @ref CRC_Polynomial_Sizes and indicates CRC length. Value can be either one of @@ -86,14 +89,18 @@ typedef struct uint32_t InputDataInversionMode; /*!< This parameter is a value of @ref CRCEx_Input_Data_Inversion and specifies input data inversion mode. Can be either one of the following values @arg @ref CRC_INPUTDATA_INVERSION_NONE no input data inversion - @arg @ref CRC_INPUTDATA_INVERSION_BYTE byte-wise inversion, 0x1A2B3C4D becomes 0x58D43CB2 - @arg @ref CRC_INPUTDATA_INVERSION_HALFWORD halfword-wise inversion, 0x1A2B3C4D becomes 0xD458B23C - @arg @ref CRC_INPUTDATA_INVERSION_WORD word-wise inversion, 0x1A2B3C4D becomes 0xB23CD458 */ + @arg @ref CRC_INPUTDATA_INVERSION_BYTE byte-wise inversion, 0x1A2B3C4D + becomes 0x58D43CB2 + @arg @ref CRC_INPUTDATA_INVERSION_HALFWORD halfword-wise inversion, + 0x1A2B3C4D becomes 0xD458B23C + @arg @ref CRC_INPUTDATA_INVERSION_WORD word-wise inversion, 0x1A2B3C4D + becomes 0xB23CD458 */ uint32_t OutputDataInversionMode; /*!< This parameter is a value of @ref CRCEx_Output_Data_Inversion and specifies output data (i.e. CRC) inversion mode. Can be either @arg @ref CRC_OUTPUTDATA_INVERSION_DISABLE no CRC inversion, - @arg @ref CRC_OUTPUTDATA_INVERSION_ENABLE CRC 0x11223344 is converted into 0x22CC4488 */ + @arg @ref CRC_OUTPUTDATA_INVERSION_ENABLE CRC 0x11223344 is converted + into 0x22CC4488 */ } CRC_InitTypeDef; /** @@ -111,12 +118,16 @@ typedef struct uint32_t InputDataFormat; /*!< This parameter is a value of @ref CRC_Input_Buffer_Format and specifies input data format. Can be either - @arg @ref CRC_INPUTDATA_FORMAT_BYTES input data is a stream of bytes (8-bit data) - @arg @ref CRC_INPUTDATA_FORMAT_HALFWORDS input data is a stream of half-words (16-bit data) - @arg @ref CRC_INPUTDATA_FORMAT_WORDS input data is a stream of words (32-bit data) - - Note that constant CRC_INPUT_FORMAT_UNDEFINED is defined but an initialization error - must occur if InputBufferFormat is not one of the three values listed above */ + @arg @ref CRC_INPUTDATA_FORMAT_BYTES input data is a stream of bytes + (8-bit data) + @arg @ref CRC_INPUTDATA_FORMAT_HALFWORDS input data is a stream of + half-words (16-bit data) + @arg @ref CRC_INPUTDATA_FORMAT_WORDS input data is a stream of words + (32-bit data) + + Note that constant CRC_INPUT_FORMAT_UNDEFINED is defined but an initialization + error must occur if InputBufferFormat is not one of the three values listed + above */ } CRC_HandleTypeDef; /** * @} @@ -198,15 +209,6 @@ typedef struct * @} */ -/** @defgroup CRC_Aliases CRC API aliases - * @{ - */ -#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for inter STM32 series compatibility */ -#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for inter STM32 series compatibility */ -/** - * @} - */ - /** * @} */ @@ -266,7 +268,6 @@ typedef struct #define IS_DEFAULT_POLYNOMIAL(DEFAULT) (((DEFAULT) == DEFAULT_POLYNOMIAL_ENABLE) || \ ((DEFAULT) == DEFAULT_POLYNOMIAL_DISABLE)) - #define IS_DEFAULT_INIT_VALUE(VALUE) (((VALUE) == DEFAULT_INIT_VALUE_ENABLE) || \ ((VALUE) == DEFAULT_INIT_VALUE_DISABLE)) diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_def.h b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_def.h index dce9550a32..ef51f32906 100644 --- a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_def.h +++ b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_def.h @@ -139,6 +139,17 @@ typedef enum #endif /* __ALIGN_BEGIN */ #endif /* __GNUC__ */ +/* Macro to get variable aligned on 32-bytes,needed for cache maintenance purpose */ +#if defined (__GNUC__) /* GNU Compiler */ +#define ALIGN_32BYTES(buf) buf __attribute__ ((aligned (32))) +#elif defined (__ICCARM__) /* IAR Compiler */ +#define ALIGN_32BYTES(buf) _Pragma("data_alignment=32") buf +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#define ALIGN_32BYTES(buf) __ALIGNED(32) buf +#elif defined (__CC_ARM) /* ARM Compiler */ +#define ALIGN_32BYTES(buf) __align(32) buf +#endif /* __GNUC__ */ + /** * @brief __RAM_FUNC definition */ diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_dma.h b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_dma.h index 740fef77c2..9c81099e19 100644 --- a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_dma.h +++ b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_dma.h @@ -214,7 +214,7 @@ typedef struct __DMA_HandleTypeDef * @brief DMA Request selection * @{ */ -/* D2 Domain : DMAMUX1 requests */ +/* DMAMUX1 requests */ #define DMA_REQUEST_MEM2MEM 0U /*!< memory to memory transfer */ #define DMA_REQUEST_GENERATOR0 1U /*!< DMAMUX1 request generator 0 */ @@ -265,6 +265,7 @@ typedef struct __DMA_HandleTypeDef #define DMA_REQUEST_SPI2_RX 39U /*!< DMAMUX1 SPI2 RX request */ #define DMA_REQUEST_SPI2_TX 40U /*!< DMAMUX1 SPI2 TX request */ + #define DMA_REQUEST_USART2_RX 43U /*!< DMAMUX1 USART2 RX request */ #define DMA_REQUEST_USART2_TX 44U /*!< DMAMUX1 USART2 TX request */ #define DMA_REQUEST_USART3_RX 45U /*!< DMAMUX1 USART3 RX request */ @@ -293,8 +294,10 @@ typedef struct __DMA_HandleTypeDef #define DMA_REQUEST_UART5_RX 65U /*!< DMAMUX1 UART5 RX request */ #define DMA_REQUEST_UART5_TX 66U /*!< DMAMUX1 UART5 TX request */ +#if defined (DAC1) #define DMA_REQUEST_DAC1 67U /*!< DMAMUX1 DAC1 request */ #define DMA_REQUEST_DAC2 68U /*!< DMAMUX1 DAC2 request */ +#endif #define DMA_REQUEST_TIM6_UP 69U /*!< DMAMUX1 TIM6 UP request */ #define DMA_REQUEST_TIM7_UP 70U /*!< DMAMUX1 TIM7 UP request */ @@ -305,14 +308,19 @@ typedef struct __DMA_HandleTypeDef #define DMA_REQUEST_I2C3_RX 73U /*!< DMAMUX1 I2C3 RX request */ #define DMA_REQUEST_I2C3_TX 74U /*!< DMAMUX1 I2C3 TX request */ +#if defined (DCMI) #define DMA_REQUEST_DCMI 75U /*!< DMAMUX1 DCMI request */ +#endif #if defined(CRYP2) #define DMA_REQUEST_CRYP2_IN 76U /*!< DMAMUX1 CRYP2 IN request */ #define DMA_REQUEST_CRYP2_OUT 77U /*!< DMAMUX1 CRYP2 OUT request */ #endif + +#if defined (HASH2) #define DMA_REQUEST_HASH2_IN 78U /*!< DMAMUX1 HASH2 IN request */ +#endif #define DMA_REQUEST_UART7_RX 79U /*!< DMAMUX1 UART7 RX request */ #define DMA_REQUEST_UART7_TX 80U /*!< DMAMUX1 UART7 TX request */ @@ -335,8 +343,10 @@ typedef struct __DMA_HandleTypeDef #define DMA_REQUEST_SPDIF_RX_DT 93U /*!< DMAMUX1 SPDIF RXDT request*/ #define DMA_REQUEST_SPDIF_RX_CS 94U /*!< DMAMUX1 SPDIF RXCS request*/ +#if defined (SAI4) #define DMA_REQUEST_SAI4_A 99U /*!< DMAMUX1 SAI4 A request */ #define DMA_REQUEST_SAI4_B 100U /*!< DMAMUX1 SAI4 B request */ +#endif #define DMA_REQUEST_DFSDM1_FLT0 101U /*!< DMAMUX1 DFSDM Filter0 request */ #define DMA_REQUEST_DFSDM1_FLT1 102U /*!< DMAMUX1 DFSDM Filter1 request */ @@ -354,12 +364,16 @@ typedef struct __DMA_HandleTypeDef #define DMA_REQUEST_TIM17_CH1 111U /*!< DMAMUX1 TIM17 CH1 request */ #define DMA_REQUEST_TIM17_UP 112U /*!< DMAMUX1 TIM17 UP request */ +#if defined (SAI3) #define DMA_REQUEST_SAI3_A 113U /*!< DMAMUX1 SAI3 A request */ #define DMA_REQUEST_SAI3_B 114U /*!< DMAMUX1 SAI3 B request */ +#endif #define DMA_REQUEST_I2C5_RX 115U /*!< DMAMUX1 I2C5 RX request */ #define DMA_REQUEST_I2C5_TX 116U /*!< DMAMUX1 I2C5 TX request */ + + /** * @} */ @@ -596,7 +610,6 @@ typedef struct __DMA_HandleTypeDef ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_TCIF3_7 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_TCIF3_7 :\ (uint32_t)0x00000000) - /** * @brief Return the current DMA Stream half transfer complete flag. * @param __HANDLE__: DMA handle @@ -620,7 +633,6 @@ typedef struct __DMA_HandleTypeDef ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_HTIF3_7 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_HTIF3_7 :\ (uint32_t)0x00000000) - /** * @brief Return the current DMA Stream transfer error flag. * @param __HANDLE__: DMA handle @@ -644,7 +656,6 @@ typedef struct __DMA_HandleTypeDef ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_TEIF3_7 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_TEIF3_7 :\ (uint32_t)0x00000000) - /** * @brief Return the current DMA Stream FIFO error flag. * @param __HANDLE__: DMA handle @@ -693,7 +704,6 @@ typedef struct __DMA_HandleTypeDef ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_DMEIF3_7 :\ (uint32_t)0x00000000) - /** * @brief Get the DMA Stream pending flags. * @param __HANDLE__: DMA handle @@ -873,7 +883,10 @@ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); #define IS_DMA_REQUEST(REQUEST) ((REQUEST) <= DMA_REQUEST_I2C5_TX) -#define IS_DMA_INSTANCE(__HANDLE__) (((uint32_t)((__HANDLE__)->Instance) >= ((uint32_t)DMA1_Stream0)) && ((uint32_t)((__HANDLE__)->Instance) <= ((uint32_t)DMA2_Stream7))) +#define IS_DMA_INSTANCE(__HANDLE__) ( \ + (((uint32_t)((__HANDLE__)->Instance) >= ((uint32_t)DMA1_Stream0)) && \ + ((uint32_t)((__HANDLE__)->Instance) <= ((uint32_t)DMA2_Stream7))) \ + ) #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_dma_ex.h b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_dma_ex.h index beb20665a7..338f624e62 100644 --- a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_dma_ex.h +++ b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_dma_ex.h @@ -106,14 +106,14 @@ typedef struct * @brief DMAEx MUX SyncSignalID selection * @{ */ -#define HAL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT 0U /*!< Domain synchronization Signal is DMAMUX1 Channel0 Event */ -#define HAL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT 1U /*!< Domain synchronization Signal is DMAMUX1 Channel1 Event */ -#define HAL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT 2U /*!< Domain synchronization Signal is DMAMUX1 Channel2 Event */ -#define HAL_DMAMUX1_SYNC_LPTIM1_OUT 3U /*!< Domain synchronization Signal is LPTIM1 OUT */ -#define HAL_DMAMUX1_SYNC_LPTIM2_OUT 4U /*!< Domain synchronization Signal is LPTIM2 OUT */ -#define HAL_DMAMUX1_SYNC_LPTIM3_OUT 5U /*!< Domain synchronization Signal is LPTIM3 OUT */ -#define HAL_DMAMUX1_SYNC_EXTI0 6U /*!< Domain synchronization Signal is EXTI0 IT */ -#define HAL_DMAMUX1_SYNC_TIM12_TRGO 7U /*!< Domain synchronization Signal is TIM12 TRGO */ +#define HAL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT 0U /*!< DMAMUX1 synchronization Signal is DMAMUX1 Channel0 Event */ +#define HAL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT 1U /*!< DMAMUX1 synchronization Signal is DMAMUX1 Channel1 Event */ +#define HAL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT 2U /*!< DMAMUX1 synchronization Signal is DMAMUX1 Channel2 Event */ +#define HAL_DMAMUX1_SYNC_LPTIM1_OUT 3U /*!< DMAMUX1 synchronization Signal is LPTIM1 OUT */ +#define HAL_DMAMUX1_SYNC_LPTIM2_OUT 4U /*!< DMAMUX1 synchronization Signal is LPTIM2 OUT */ +#define HAL_DMAMUX1_SYNC_LPTIM3_OUT 5U /*!< DMAMUX1 synchronization Signal is LPTIM3 OUT */ +#define HAL_DMAMUX1_SYNC_EXTI0 6U /*!< DMAMUX1 synchronization Signal is EXTI0 IT */ +#define HAL_DMAMUX1_SYNC_TIM12_TRGO 7U /*!< DMAMUX1 synchronization Signal is TIM12 TRGO */ /** * @} @@ -137,14 +137,14 @@ typedef struct * @brief DMAEx MUX SignalGeneratorID selection * @{ */ -#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT 0U /*!< Domain Request generator Signal is DMAMUX1 Channel0 Event */ -#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT 1U /*!< Domain Request generator Signal is DMAMUX1 Channel1 Event */ -#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT 2U /*!< Domain Request generator Signal is DMAMUX1 Channel2 Event */ -#define HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT 3U /*!< Domain Request generator Signal is LPTIM1 OUT */ -#define HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT 4U /*!< Domain Request generator Signal is LPTIM2 OUT */ -#define HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT 5U /*!< Domain Request generator Signal is LPTIM3 OUT */ -#define HAL_DMAMUX1_REQ_GEN_EXTI0 6U /*!< Domain Request generator Signal is EXTI0 IT */ -#define HAL_DMAMUX1_REQ_GEN_TIM12_TRGO 7U /*!< Domain Request generator Signal is TIM12 TRGO */ +#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT 0U /*!< DMAMUX1 Request generator Signal is DMAMUX1 Channel0 Event */ +#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT 1U /*!< DMAMUX1 Request generator Signal is DMAMUX1 Channel1 Event */ +#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT 2U /*!< DMAMUX1 Request generator Signal is DMAMUX1 Channel2 Event */ +#define HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT 3U /*!< DMAMUX1 Request generator Signal is LPTIM1 OUT */ +#define HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT 4U /*!< DMAMUX1 Request generator Signal is LPTIM2 OUT */ +#define HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT 5U /*!< DMAMUX1 Request generator Signal is LPTIM3 OUT */ +#define HAL_DMAMUX1_REQ_GEN_EXTI0 6U /*!< DMAMUX1 Request generator Signal is EXTI0 IT */ +#define HAL_DMAMUX1_REQ_GEN_TIM12_TRGO 7U /*!< DMAMUX1 Request generator Signal is TIM12 TRGO */ /** @@ -203,8 +203,7 @@ void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma); */ #define IS_DMAMUX_SYNC_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX1_SYNC_TIM12_TRGO) - -#define IS_DMAMUX_SYNC_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0) && ((REQUEST_NUMBER) <= 32)) +#define IS_DMAMUX_SYNC_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U)) #define IS_DMAMUX_SYNC_POLARITY(POLARITY) (((POLARITY) == HAL_DMAMUX_SYNC_NO_EVENT) || \ ((POLARITY) == HAL_DMAMUX_SYNC_RISING) || \ @@ -218,7 +217,7 @@ void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma); #define IS_DMAMUX_REQUEST_GEN_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX1_REQ_GEN_TIM12_TRGO) -#define IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0) && ((REQUEST_NUMBER) <= 32)) +#define IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U)) #define IS_DMAMUX_REQUEST_GEN_POLARITY(POLARITY) (((POLARITY) == HAL_DMAMUX_REQ_GEN_NO_EVENT) || \ ((POLARITY) == HAL_DMAMUX_REQ_GEN_RISING) || \ @@ -250,4 +249,4 @@ void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma); } #endif -#endif /* STM32MP1xx_HAL_DMA_H */ +#endif /* STM32MP1xx_HAL_DMA_EX_H */ diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_exti.h b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_exti.h index 614c85d824..3344b6c2e0 100644 --- a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_exti.h +++ b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_exti.h @@ -172,6 +172,7 @@ typedef struct /** @defgroup EXTI_Mode EXTI Mode * @{ */ + #define EXTI_MODE_C1_NONE 0x00000010u #define EXTI_MODE_C1_INTERRUPT 0x00000011u #define EXTI_MODE_C2_NONE 0x00000020u @@ -307,7 +308,6 @@ typedef struct ((__PORT__) == EXTI_GPIOI) || \ ((__PORT__) == EXTI_GPIOK) || \ ((__PORT__) == EXTI_GPIOZ)) - #define IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16u) /** diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_ipcc.h b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_ipcc.h index 45719731af..6d36014a4e 100644 --- a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_ipcc.h +++ b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_ipcc.h @@ -287,4 +287,3 @@ void HAL_IPCC_RxCallback(IPCC_HandleTypeDef *hipcc, uint32_t ChannelIndex, IPCC_ #endif /* STM32MP1xx_HAL_IPCC_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_qspi.h b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_qspi.h index bfa8c59830..a12eb6d3ca 100755 --- a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_qspi.h +++ b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_qspi.h @@ -457,7 +457,7 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi); * @{ */ /** @brief Reset QSPI handle state. - * @param __HANDLE__ : QSPI handle. + * @param __HANDLE__ QSPI handle. * @retval None */ #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) @@ -471,20 +471,20 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi); #endif /** @brief Enable the QSPI peripheral. - * @param __HANDLE__ : specifies the QSPI Handle. + * @param __HANDLE__ specifies the QSPI Handle. * @retval None */ #define __HAL_QSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN) /** @brief Disable the QSPI peripheral. - * @param __HANDLE__ : specifies the QSPI Handle. + * @param __HANDLE__ specifies the QSPI Handle. * @retval None */ #define __HAL_QSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN) /** @brief Enable the specified QSPI interrupt. - * @param __HANDLE__ : specifies the QSPI Handle. - * @param __INTERRUPT__ : specifies the QSPI interrupt source to enable. + * @param __HANDLE__ specifies the QSPI Handle. + * @param __INTERRUPT__ specifies the QSPI interrupt source to enable. * This parameter can be one of the following values: * @arg QSPI_IT_TO: QSPI Timeout interrupt * @arg QSPI_IT_SM: QSPI Status match interrupt @@ -497,8 +497,8 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi); /** @brief Disable the specified QSPI interrupt. - * @param __HANDLE__ : specifies the QSPI Handle. - * @param __INTERRUPT__ : specifies the QSPI interrupt source to disable. + * @param __HANDLE__ specifies the QSPI Handle. + * @param __INTERRUPT__ specifies the QSPI interrupt source to disable. * This parameter can be one of the following values: * @arg QSPI_IT_TO: QSPI Timeout interrupt * @arg QSPI_IT_SM: QSPI Status match interrupt @@ -510,8 +510,8 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi); #define __HAL_QSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) /** @brief Check whether the specified QSPI interrupt source is enabled or not. - * @param __HANDLE__ : specifies the QSPI Handle. - * @param __INTERRUPT__ : specifies the QSPI interrupt source to check. + * @param __HANDLE__ specifies the QSPI Handle. + * @param __INTERRUPT__ specifies the QSPI interrupt source to check. * This parameter can be one of the following values: * @arg QSPI_IT_TO: QSPI Timeout interrupt * @arg QSPI_IT_SM: QSPI Status match interrupt @@ -524,8 +524,8 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi); /** * @brief Check whether the selected QSPI flag is set or not. - * @param __HANDLE__ : specifies the QSPI Handle. - * @param __FLAG__ : specifies the QSPI flag to check. + * @param __HANDLE__ specifies the QSPI Handle. + * @param __FLAG__ specifies the QSPI flag to check. * This parameter can be one of the following values: * @arg QSPI_FLAG_BUSY: QSPI Busy flag * @arg QSPI_FLAG_TO: QSPI Timeout flag @@ -538,8 +538,8 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi); #define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0U) ? SET : RESET) /** @brief Clears the specified QSPI's flag status. - * @param __HANDLE__ : specifies the QSPI Handle. - * @param __FLAG__ : specifies the QSPI clear register flag that needs to be set + * @param __HANDLE__ specifies the QSPI Handle. + * @param __FLAG__ specifies the QSPI clear register flag that needs to be set * This parameter can be one of the following values: * @arg QSPI_FLAG_TO: QSPI Timeout flag * @arg QSPI_FLAG_SM: QSPI Status match flag @@ -742,7 +742,7 @@ HAL_StatusTypeDef HAL_QSPI_SetFlashID (QSPI_HandleTypeDef *hqspi, uint3 * @} */ -#endif /* defined(QUADSPI) || defined(QUADSPI1) || defined(QUADSPI2) */ +#endif /* defined(QUADSPI) */ #ifdef __cplusplus } diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_smbus.h b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_smbus.h index 60dc3ea3b3..275afc1a01 100644 --- a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_smbus.h +++ b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_smbus.h @@ -511,6 +511,7 @@ typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t * @param __HANDLE__ specifies the SMBUS Handle. * @param __FLAG__ specifies the flag to clear. * This parameter can be any combination of the following values: + * @arg @ref SMBUS_FLAG_TXE Transmit data register empty * @arg @ref SMBUS_FLAG_ADDR Address matched (slave mode) * @arg @ref SMBUS_FLAG_AF NACK received flag * @arg @ref SMBUS_FLAG_STOPF STOP detection flag @@ -523,7 +524,9 @@ typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t * * @retval None */ -#define __HAL_SMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) +#define __HAL_SMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == SMBUS_FLAG_TXE) ? \ + ((__HANDLE__)->Instance->ISR |= (__FLAG__)) : \ + ((__HANDLE__)->Instance->ICR = (__FLAG__))) /** @brief Enable the specified SMBUS peripheral. * @param __HANDLE__ specifies the SMBUS Handle. @@ -652,6 +655,8 @@ typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t * @} */ +/* Include SMBUS HAL Extended module */ +#include "stm32mp1xx_hal_smbus_ex.h" /* Exported functions --------------------------------------------------------*/ /** @addtogroup SMBUS_Exported_Functions SMBUS Exported Functions diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_smbus_ex.h b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_smbus_ex.h new file mode 100644 index 0000000000..a92f5550a3 --- /dev/null +++ b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_smbus_ex.h @@ -0,0 +1,143 @@ +/** + ****************************************************************************** + * @file stm32mp1xx_hal_smbus_ex.h + * @author MCD Application Team + * @brief Header file of SMBUS HAL Extended module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32MP1xx_HAL_SMBUS_EX_H +#define STM32MP1xx_HAL_SMBUS_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32mp1xx_hal_def.h" + +/** @addtogroup STM32MP1xx_HAL_Driver + * @{ + */ + +/** @addtogroup SMBUSEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup SMBUSEx_Exported_Constants SMBUS Extended Exported Constants + * @{ + */ + +/** @defgroup SMBUSEx_FastModePlus SMBUS Extended Fast Mode Plus + * @{ + */ +#define SMBUS_FASTMODEPLUS_I2C1 SYSCFG_PMCSETR_I2C1_FMP /*!< Enable Fast Mode Plus on I2C1 pins */ +#define SMBUS_FASTMODEPLUS_I2C2 SYSCFG_PMCSETR_I2C2_FMP /*!< Enable Fast Mode Plus on I2C2 pins */ +#define SMBUS_FASTMODEPLUS_I2C3 SYSCFG_PMCSETR_I2C3_FMP /*!< Enable Fast Mode Plus on I2C3 pins */ +#define SMBUS_FASTMODEPLUS_I2C4 SYSCFG_PMCSETR_I2C4_FMP /*!< Enable Fast Mode Plus on I2C4 pins */ +#define SMBUS_FASTMODEPLUS_I2C5 SYSCFG_PMCSETR_I2C5_FMP /*!< Enable Fast Mode Plus on I2C5 pins */ +#define SMBUS_FASTMODEPLUS_I2C6 SYSCFG_PMCSETR_I2C6_FMP /*!< Enable Fast Mode Plus on I2C6 pins */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup SMBUSEx_Exported_Macros SMBUS Extended Exported Macros + * @{ + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup SMBUSEx_Exported_Functions SMBUS Extended Exported Functions + * @{ + */ + +/** @addtogroup SMBUSEx_Exported_Functions_Group2 WakeUp Mode Functions + * @{ + */ +/* Peripheral Control functions ************************************************/ +HAL_StatusTypeDef HAL_SMBUSEx_EnableWakeUp(SMBUS_HandleTypeDef *hsmbus); +HAL_StatusTypeDef HAL_SMBUSEx_DisableWakeUp(SMBUS_HandleTypeDef *hsmbus); +/** + * @} + */ + +/** @addtogroup SMBUSEx_Exported_Functions_Group3 Fast Mode Plus Functions + * @{ + */ +void HAL_SMBUSEx_EnableFastModePlus(uint32_t ConfigFastModePlus); +void HAL_SMBUSEx_DisableFastModePlus(uint32_t ConfigFastModePlus); +/** + * @} + */ + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup SMBUSEx_Private_Constants SMBUS Extended Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup SMBUSEx_Private_Macro SMBUS Extended Private Macros + * @{ + */ +#define IS_SMBUS_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & (SMBUS_FASTMODEPLUS_I2C1)) == SMBUS_FASTMODEPLUS_I2C1) || \ + (((__CONFIG__) & (SMBUS_FASTMODEPLUS_I2C2)) == SMBUS_FASTMODEPLUS_I2C2) || \ + (((__CONFIG__) & (SMBUS_FASTMODEPLUS_I2C3)) == SMBUS_FASTMODEPLUS_I2C3) || \ + (((__CONFIG__) & (SMBUS_FASTMODEPLUS_I2C4)) == SMBUS_FASTMODEPLUS_I2C4) || \ + (((__CONFIG__) & (SMBUS_FASTMODEPLUS_I2C5)) == SMBUS_FASTMODEPLUS_I2C5) || \ + (((__CONFIG__) & (SMBUS_FASTMODEPLUS_I2C6)) == SMBUS_FASTMODEPLUS_I2C6)) + +/** + * @} + */ + +/* Private Functions ---------------------------------------------------------*/ +/** @defgroup SMBUSEx_Private_Functions SMBUS Extended Private Functions + * @{ + */ +/* Private functions are defined in stm32mp1xx_hal_smbus_ex.c file */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32MP1xx_HAL_SMBUS_EX_H */ diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_spi.h b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_spi.h index 37f8f9f0e2..6fb6d775d0 100644 --- a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_spi.h +++ b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_spi.h @@ -150,7 +150,7 @@ typedef enum */ typedef struct { - uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */ + const uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */ uint16_t TxXferSize; /*!< SPI Tx Transfer size to reload */ @@ -172,7 +172,7 @@ typedef struct __SPI_HandleTypeDef SPI_InitTypeDef Init; /*!< SPI communication parameters */ - uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */ + const uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */ uint16_t TxXferSize; /*!< SPI Tx Transfer size */ @@ -215,6 +215,7 @@ typedef struct __SPI_HandleTypeDef void (* TxRxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI TxRx Half Completed callback */ void (* ErrorCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Error callback */ void (* AbortCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Abort callback */ + void (* SuspendCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Suspend callback */ void (* MspInitCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Msp Init callback */ void (* MspDeInitCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Msp DeInit callback */ @@ -235,8 +236,9 @@ typedef enum HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID = 0x05UL, /*!< SPI TxRx Half Completed callback ID */ HAL_SPI_ERROR_CB_ID = 0x06UL, /*!< SPI Error callback ID */ HAL_SPI_ABORT_CB_ID = 0x07UL, /*!< SPI Abort callback ID */ - HAL_SPI_MSPINIT_CB_ID = 0x08UL, /*!< SPI Msp Init callback ID */ - HAL_SPI_MSPDEINIT_CB_ID = 0x09UL /*!< SPI Msp DeInit callback ID */ + HAL_SPI_SUSPEND_CB_ID = 0x08UL, /*!< SPI Suspend callback ID */ + HAL_SPI_MSPINIT_CB_ID = 0x09UL, /*!< SPI Msp Init callback ID */ + HAL_SPI_MSPDEINIT_CB_ID = 0x0AUL /*!< SPI Msp DeInit callback ID */ } HAL_SPI_CallbackIDTypeDef; @@ -860,24 +862,24 @@ HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_Ca * @{ */ /* I/O operation functions ***************************************************/ -HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, - uint32_t Timeout); -HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, +HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size); -HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, +HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size); #if defined(USE_SPI_RELOAD_TRANSFER) -HAL_StatusTypeDef HAL_SPI_Reload_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_Reload_Transmit_IT(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_SPI_Reload_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_SPI_Reload_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, +HAL_StatusTypeDef HAL_SPI_Reload_TransmitReceive_IT(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size); #endif /* USE_SPI_RELOAD_TRANSFER */ @@ -898,6 +900,7 @@ void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi); void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi); void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi); void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_SuspendCallback(SPI_HandleTypeDef *hspi); /** * @} */ @@ -907,8 +910,8 @@ void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi); */ /* Peripheral State and Error functions ***************************************/ -HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi); -uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi); +HAL_SPI_StateTypeDef HAL_SPI_GetState(const SPI_HandleTypeDef *hspi); +uint32_t HAL_SPI_GetError(const SPI_HandleTypeDef *hspi); /** * @} */ @@ -922,19 +925,40 @@ uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi); * @{ */ -/** @brief Set the SPI transmit-only mode. +/** @brief Set the SPI transmit-only mode in 1Line configuration. * @param __HANDLE__: specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ -#define SPI_1LINE_TX(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1 , SPI_CR1_HDDIR) +#define SPI_1LINE_TX(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_HDDIR) -/** @brief Set the SPI receive-only mode. +/** @brief Set the SPI receive-only mode in 1Line configuration. * @param __HANDLE__: specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ -#define SPI_1LINE_RX(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1 ,SPI_CR1_HDDIR) +#define SPI_1LINE_RX(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_HDDIR) + +/** @brief Set the SPI transmit-only mode in 2Lines configuration. + * @param __HANDLE__: specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define SPI_2LINES_TX(__HANDLE__) MODIFY_REG((__HANDLE__)->Instance->CFG2, SPI_CFG2_COMM, SPI_CFG2_COMM_0) + +/** @brief Set the SPI receive-only mode in 2Lines configuration. + * @param __HANDLE__: specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define SPI_2LINES_RX(__HANDLE__) MODIFY_REG((__HANDLE__)->Instance->CFG2, SPI_CFG2_COMM, SPI_CFG2_COMM_1) + +/** @brief Set the SPI Transmit-Receive mode in 2Lines configuration. + * @param __HANDLE__: specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define SPI_2LINES(__HANDLE__) MODIFY_REG((__HANDLE__)->Instance->CFG2, SPI_CFG2_COMM, 0x00000000UL) #define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \ ((MODE) == SPI_MODE_MASTER)) @@ -1078,6 +1102,8 @@ uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi); ((MODE) == SPI_UNDERRUN_BEHAV_LAST_RECEIVED) || \ ((MODE) == SPI_UNDERRUN_BEHAV_LAST_TRANSMITTED)) +#define IS_SPI_MASTER_RX_AUTOSUSP(MODE) (((MODE) == SPI_MASTER_RX_AUTOSUSP_DISABLE) || \ + ((MODE) == SPI_MASTER_RX_AUTOSUSP_ENABLE)) /** * @} */ diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_spi_ex.h b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_spi_ex.h index 19e575bacb..e70657ca7f 100644 --- a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_spi_ex.h +++ b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_spi_ex.h @@ -72,7 +72,7 @@ extern "C" { /** @addtogroup SPIEx_Exported_Functions_Group1 * @{ */ -HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(SPI_HandleTypeDef *hspi); +HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(const SPI_HandleTypeDef *hspi); HAL_StatusTypeDef HAL_SPIEx_EnableLockConfiguration(SPI_HandleTypeDef *hspi); HAL_StatusTypeDef HAL_SPIEx_ConfigureUnderrun(SPI_HandleTypeDef *hspi, uint32_t UnderrunDetection, uint32_t UnderrunBehaviour); diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_usart.h b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_usart.h index d4e83976d0..a8ac31dddf 100644 --- a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_usart.h +++ b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_usart.h @@ -127,7 +127,7 @@ typedef struct __USART_HandleTypeDef USART_InitTypeDef Init; /*!< USART communication parameters */ - uint8_t *pTxBuffPtr; /*!< Pointer to USART Tx transfer Buffer */ + const uint8_t *pTxBuffPtr; /*!< Pointer to USART Tx transfer Buffer */ uint16_t TxXferSize; /*!< USART Tx Transfer size */ @@ -607,7 +607,7 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin */ #define __HAL_USART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\ & (0x01U << (((__INTERRUPT__) & USART_ISR_MASK)>>\ - USART_ISR_POS))) != 0U) ? SET : RESET) + USART_ISR_POS))) != 0U) ? SET : RESET) /** @brief Check whether the specified USART interrupt source is enabled or not. * @param __HANDLE__ specifies the USART Handle. @@ -965,17 +965,18 @@ HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_ */ /* IO operation functions *****************************************************/ -HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size, + uint32_t Timeout); HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, +HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size); +HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size); HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size); -HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, +HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size); -HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size); +HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size); HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size); -HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, +HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size); HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart); HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart); diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_ll_adc.h b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_ll_adc.h index a85134b794..9f0893b2c2 100644 --- a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_ll_adc.h +++ b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_ll_adc.h @@ -79,22 +79,22 @@ extern "C" { /* Definition of ADC group regular sequencer bits information to be inserted */ /* into ADC group regular sequencer ranks literals definition. */ -#define ADC_REG_RANK_1_SQRX_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_SQR1_SQ1" position in register */ -#define ADC_REG_RANK_2_SQRX_BITOFFSET_POS (12UL) /* Value equivalent to bitfield "ADC_SQR1_SQ2" position in register */ -#define ADC_REG_RANK_3_SQRX_BITOFFSET_POS (18UL) /* Value equivalent to bitfield "ADC_SQR1_SQ3" position in register */ -#define ADC_REG_RANK_4_SQRX_BITOFFSET_POS (24UL) /* Value equivalent to bitfield "ADC_SQR1_SQ4" position in register */ -#define ADC_REG_RANK_5_SQRX_BITOFFSET_POS ( 0UL) /* Value equivalent to bitfield "ADC_SQR2_SQ5" position in register */ -#define ADC_REG_RANK_6_SQRX_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_SQR2_SQ6" position in register */ -#define ADC_REG_RANK_7_SQRX_BITOFFSET_POS (12UL) /* Value equivalent to bitfield "ADC_SQR2_SQ7" position in register */ -#define ADC_REG_RANK_8_SQRX_BITOFFSET_POS (18UL) /* Value equivalent to bitfield "ADC_SQR2_SQ8" position in register */ -#define ADC_REG_RANK_9_SQRX_BITOFFSET_POS (24UL) /* Value equivalent to bitfield "ADC_SQR2_SQ9" position in register */ -#define ADC_REG_RANK_10_SQRX_BITOFFSET_POS ( 0UL) /* Value equivalent to bitfield "ADC_SQR3_SQ10" position in register */ -#define ADC_REG_RANK_11_SQRX_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_SQR3_SQ11" position in register */ -#define ADC_REG_RANK_12_SQRX_BITOFFSET_POS (12UL) /* Value equivalent to bitfield "ADC_SQR3_SQ12" position in register */ -#define ADC_REG_RANK_13_SQRX_BITOFFSET_POS (18UL) /* Value equivalent to bitfield "ADC_SQR3_SQ13" position in register */ -#define ADC_REG_RANK_14_SQRX_BITOFFSET_POS (24UL) /* Value equivalent to bitfield "ADC_SQR3_SQ14" position in register */ -#define ADC_REG_RANK_15_SQRX_BITOFFSET_POS ( 0UL) /* Value equivalent to bitfield "ADC_SQR4_SQ15" position in register */ -#define ADC_REG_RANK_16_SQRX_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_SQR4_SQ16" position in register */ +#define ADC_REG_RANK_1_SQRX_BITOFFSET_POS ( 6UL) /* Equivalent to bitfield "ADC_SQR1_SQ1" position in register */ +#define ADC_REG_RANK_2_SQRX_BITOFFSET_POS (12UL) /* Equivalent to bitfield "ADC_SQR1_SQ2" position in register */ +#define ADC_REG_RANK_3_SQRX_BITOFFSET_POS (18UL) /* Equivalent to bitfield "ADC_SQR1_SQ3" position in register */ +#define ADC_REG_RANK_4_SQRX_BITOFFSET_POS (24UL) /* Equivalent to bitfield "ADC_SQR1_SQ4" position in register */ +#define ADC_REG_RANK_5_SQRX_BITOFFSET_POS ( 0UL) /* Equivalent to bitfield "ADC_SQR2_SQ5" position in register */ +#define ADC_REG_RANK_6_SQRX_BITOFFSET_POS ( 6UL) /* Equivalent to bitfield "ADC_SQR2_SQ6" position in register */ +#define ADC_REG_RANK_7_SQRX_BITOFFSET_POS (12UL) /* Equivalent to bitfield "ADC_SQR2_SQ7" position in register */ +#define ADC_REG_RANK_8_SQRX_BITOFFSET_POS (18UL) /* Equivalent to bitfield "ADC_SQR2_SQ8" position in register */ +#define ADC_REG_RANK_9_SQRX_BITOFFSET_POS (24UL) /* Equivalent to bitfield "ADC_SQR2_SQ9" position in register */ +#define ADC_REG_RANK_10_SQRX_BITOFFSET_POS ( 0UL) /* Equivalent to bitfield "ADC_SQR3_SQ10" position in register */ +#define ADC_REG_RANK_11_SQRX_BITOFFSET_POS ( 6UL) /* Equivalent to bitfield "ADC_SQR3_SQ11" position in register */ +#define ADC_REG_RANK_12_SQRX_BITOFFSET_POS (12UL) /* Equivalent to bitfield "ADC_SQR3_SQ12" position in register */ +#define ADC_REG_RANK_13_SQRX_BITOFFSET_POS (18UL) /* Equivalent to bitfield "ADC_SQR3_SQ13" position in register */ +#define ADC_REG_RANK_14_SQRX_BITOFFSET_POS (24UL) /* Equivalent to bitfield "ADC_SQR3_SQ14" position in register */ +#define ADC_REG_RANK_15_SQRX_BITOFFSET_POS ( 0UL) /* Equivalent to bitfield "ADC_SQR4_SQ15" position in register */ +#define ADC_REG_RANK_16_SQRX_BITOFFSET_POS ( 6UL) /* Equivalent to bitfield "ADC_SQR4_SQ16" position in register */ @@ -147,8 +147,8 @@ extern "C" { ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 3UL)) ) /* Definition of ADC group regular trigger bits information. */ -#define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_CFGR_EXTSEL" position in register */ -#define ADC_REG_TRIG_EXTEN_BITOFFSET_POS (10UL) /* Value equivalent to bitfield "ADC_CFGR_EXTEN" position in register */ +#define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS ( 6UL) /* Equivalent to bitfield "ADC_CFGR_EXTSEL" position in register */ +#define ADC_REG_TRIG_EXTEN_BITOFFSET_POS (10UL) /* Equivalent to bitfield "ADC_CFGR_EXTEN" position in register */ @@ -175,8 +175,8 @@ extern "C" { ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 3UL)) ) /* Definition of ADC group injected trigger bits information. */ -#define ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS ( 2UL) /* Value equivalent to bitfield "ADC_JSQR_JEXTSEL" position in register */ -#define ADC_INJ_TRIG_EXTEN_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_JSQR_JEXTEN" position in register */ +#define ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS ( 2UL) /* Equivalent to bitfield "ADC_JSQR_JEXTSEL" position in register */ +#define ADC_INJ_TRIG_EXTEN_BITOFFSET_POS ( 6UL) /* Equivalent to bitfield "ADC_JSQR_JEXTEN" position in register */ @@ -193,7 +193,7 @@ extern "C" { /* and SMPx bits positions into SMPRx register */ #define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CFGR_AWD1CH) #define ADC_CHANNEL_ID_BITFIELD_MASK (ADC_AWD2CR_AWD2CH) -#define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS (26UL)/* Value equivalent to bitfield "ADC_CHANNEL_ID_NUMBER_MASK" position in register */ +#define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS (26UL)/* Equivalent to bitfield "ADC_CHANNEL_ID_NUMBER_MASK" position in register */ #define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_BITFIELD_MASK \ | ADC_CHANNEL_ID_INTERNAL_CH_MASK) /* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */ @@ -211,7 +211,7 @@ extern "C" { #define ADC_SMPRX_REGOFFSET_POS (25UL) /* Position of bits ADC_SMPRx_REGOFFSET in ADC_CHANNEL_SMPRX_REGOFFSET_MASK */ #define ADC_CHANNEL_SMPx_BITOFFSET_MASK (0x01F00000UL) -#define ADC_CHANNEL_SMPx_BITOFFSET_POS (20UL) /* Value equivalent to bitfield "ADC_CHANNEL_SMPx_BITOFFSET_MASK" position in register */ +#define ADC_CHANNEL_SMPx_BITOFFSET_POS (20UL) /* Equivalent to bitfield "ADC_CHANNEL_SMPx_BITOFFSET_MASK" position in register */ /* Definition of channels ID number information to be inserted into */ /* channels literals definition. */ @@ -3153,17 +3153,17 @@ __STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t Tri */ __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx) { - __IO uint32_t TriggerSource = READ_BIT(ADCx->CFGR, ADC_CFGR_EXTSEL | ADC_CFGR_EXTEN); + __IO uint32_t trigger_source = READ_BIT(ADCx->CFGR, ADC_CFGR_EXTSEL | ADC_CFGR_EXTEN); /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */ /* corresponding to ADC_CFGR_EXTEN {0; 1; 2; 3}. */ - uint32_t ShiftExten = ((TriggerSource & ADC_CFGR_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2UL)); + uint32_t shift_exten = ((trigger_source & ADC_CFGR_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2UL)); /* Set bitfield corresponding to ADC_CFGR_EXTEN and ADC_CFGR_EXTSEL */ /* to match with triggers literals definition. */ - return ((TriggerSource - & (ADC_REG_TRIG_SOURCE_MASK >> ShiftExten) & ADC_CFGR_EXTSEL) - | ((ADC_REG_TRIG_EDGE_MASK >> ShiftExten) & ADC_CFGR_EXTEN) + return ((trigger_source + & (ADC_REG_TRIG_SOURCE_MASK >> shift_exten) & ADC_CFGR_EXTSEL) + | ((ADC_REG_TRIG_EDGE_MASK >> shift_exten) & ADC_CFGR_EXTEN) ); } @@ -3801,17 +3801,17 @@ __STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t Tri */ __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(ADC_TypeDef *ADCx) { - __IO uint32_t TriggerSource = READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN); + __IO uint32_t trigger_source = READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN); /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */ /* corresponding to ADC_JSQR_JEXTEN {0; 1; 2; 3}. */ - uint32_t ShiftJexten = ((TriggerSource & ADC_JSQR_JEXTEN) >> (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 2UL)); + uint32_t shift_jexten = ((trigger_source & ADC_JSQR_JEXTEN) >> (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 2UL)); /* Set bitfield corresponding to ADC_JSQR_JEXTEN and ADC_JSQR_JEXTSEL */ /* to match with triggers literals definition. */ - return ((TriggerSource - & (ADC_INJ_TRIG_SOURCE_MASK >> ShiftJexten) & ADC_JSQR_JEXTSEL) - | ((ADC_INJ_TRIG_EDGE_MASK >> ShiftJexten) & ADC_JSQR_JEXTEN) + return ((trigger_source + & (ADC_INJ_TRIG_SOURCE_MASK >> shift_jexten) & ADC_JSQR_JEXTSEL) + | ((ADC_INJ_TRIG_EDGE_MASK >> shift_jexten) & ADC_JSQR_JEXTEN) ); } @@ -4993,20 +4993,20 @@ __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS) + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL)); - uint32_t AnalogWDMonitChannels = (READ_BIT(*preg, AWDy) & AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK); + uint32_t analog_wd_monit_channels = (READ_BIT(*preg, AWDy) & AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK); - /* If "AnalogWDMonitChannels" == 0, then the selected AWD is disabled */ + /* If "analog_wd_monit_channels" == 0, then the selected AWD is disabled */ /* (parameter value LL_ADC_AWD_DISABLE). */ /* Else, the selected AWD is enabled and is monitoring a group of channels */ /* or a single channel. */ - if (AnalogWDMonitChannels != 0UL) + if (analog_wd_monit_channels != 0UL) { if (AWDy == LL_ADC_AWD1) { - if ((AnalogWDMonitChannels & ADC_CFGR_AWD1SGL) == 0UL) + if ((analog_wd_monit_channels & ADC_CFGR_AWD1SGL) == 0UL) { /* AWD monitoring a group of channels */ - AnalogWDMonitChannels = ((AnalogWDMonitChannels + analog_wd_monit_channels = ((analog_wd_monit_channels | (ADC_AWD_CR23_CHANNEL_MASK) ) & (~(ADC_CFGR_AWD1CH)) @@ -5015,17 +5015,17 @@ __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint else { /* AWD monitoring a single channel */ - AnalogWDMonitChannels = (AnalogWDMonitChannels - | (ADC_AWD2CR_AWD2CH_0 << (AnalogWDMonitChannels >> ADC_CFGR_AWD1CH_Pos)) + analog_wd_monit_channels = (analog_wd_monit_channels + | (ADC_AWD2CR_AWD2CH_0 << (analog_wd_monit_channels >> ADC_CFGR_AWD1CH_Pos)) ); } } else { - if ((AnalogWDMonitChannels & ADC_AWD_CR23_CHANNEL_MASK) == ADC_AWD_CR23_CHANNEL_MASK) + if ((analog_wd_monit_channels & ADC_AWD_CR23_CHANNEL_MASK) == ADC_AWD_CR23_CHANNEL_MASK) { /* AWD monitoring a group of channels */ - AnalogWDMonitChannels = (ADC_AWD_CR23_CHANNEL_MASK + analog_wd_monit_channels = (ADC_AWD_CR23_CHANNEL_MASK | ((ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN)) ); } @@ -5033,15 +5033,15 @@ __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint { /* AWD monitoring a single channel */ /* AWD monitoring a group of channels */ - AnalogWDMonitChannels = (AnalogWDMonitChannels + analog_wd_monit_channels = (analog_wd_monit_channels | (ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) - | (__LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDMonitChannels) << ADC_CFGR_AWD1CH_Pos) + | (__LL_ADC_CHANNEL_TO_DECIMAL_NB(analog_wd_monit_channels) << ADC_CFGR_AWD1CH_Pos) ); } } } - return AnalogWDMonitChannels; + return analog_wd_monit_channels; } /** diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_ll_dma.h b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_ll_dma.h index 19ca953f7c..4f794b0af8 100644 --- a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_ll_dma.h +++ b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_ll_dma.h @@ -473,7 +473,7 @@ typedef struct */ __STATIC_INLINE void LL_DMA_EnableStream(DMA_TypeDef *DMAx, uint32_t Stream) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_EN); } @@ -495,7 +495,7 @@ __STATIC_INLINE void LL_DMA_EnableStream(DMA_TypeDef *DMAx, uint32_t Stream) */ __STATIC_INLINE void LL_DMA_DisableStream(DMA_TypeDef *DMAx, uint32_t Stream) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_EN); } @@ -517,7 +517,7 @@ __STATIC_INLINE void LL_DMA_DisableStream(DMA_TypeDef *DMAx, uint32_t Stream) */ __STATIC_INLINE uint32_t LL_DMA_IsEnabledStream(DMA_TypeDef *DMAx, uint32_t Stream) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_EN) == (DMA_SxCR_EN)) ? 1UL : 0UL); } @@ -554,7 +554,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledStream(DMA_TypeDef *DMAx, uint32_t Stre */ __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Configuration) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DIR | DMA_SxCR_CIRC | DMA_SxCR_PINC | DMA_SxCR_MINC | DMA_SxCR_PSIZE | DMA_SxCR_MSIZE | DMA_SxCR_PL | DMA_SxCR_PFCTRL, @@ -582,7 +582,7 @@ __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Stream, u */ __STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Direction) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DIR, Direction); } @@ -607,7 +607,7 @@ __STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t */ __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DIR)); } @@ -634,7 +634,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint */ __STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mode) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_CIRC | DMA_SxCR_PFCTRL, Mode); } @@ -660,7 +660,7 @@ __STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t */ __STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Stream) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_CIRC | DMA_SxCR_PFCTRL)); } @@ -685,7 +685,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Stream) */ __STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PINC, IncrementMode); } @@ -709,7 +709,7 @@ __STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream, */ __STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PINC)); } @@ -734,7 +734,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Str */ __STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MINC, IncrementMode); } @@ -758,7 +758,7 @@ __STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream, */ __STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MINC)); } @@ -784,7 +784,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Str */ __STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Size) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PSIZE, Size); } @@ -809,7 +809,7 @@ __STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream, ui */ __STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PSIZE)); } @@ -835,7 +835,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream */ __STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Size) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MSIZE, Size); } @@ -860,7 +860,7 @@ __STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream, ui */ __STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MSIZE)); } @@ -885,7 +885,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream */ __STATIC_INLINE void LL_DMA_SetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t OffsetSize) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PINCOS, OffsetSize); } @@ -909,7 +909,7 @@ __STATIC_INLINE void LL_DMA_SetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream, */ __STATIC_INLINE uint32_t LL_DMA_GetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PINCOS)); } @@ -936,7 +936,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Str */ __STATIC_INLINE void LL_DMA_SetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Priority) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PL, Priority); } @@ -962,7 +962,7 @@ __STATIC_INLINE void LL_DMA_SetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t S */ __STATIC_INLINE uint32_t LL_DMA_GetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PL)); } @@ -987,7 +987,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32 */ __STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t NbData) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->NDTR, DMA_SxNDT, NbData); } @@ -1011,10 +1011,11 @@ __STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Stream, ui */ __STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Stream) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->NDTR, DMA_SxNDT)); } + /** * @brief Set DMA request for DMA Streams on DMAMUX Channel x. * @note DMAMUX channel 0 to 7 are mapped to DMA1 stream 0 to 7. @@ -1301,7 +1302,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t St */ __STATIC_INLINE void LL_DMA_SetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mburst) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MBURST, Mburst); } @@ -1327,7 +1328,7 @@ __STATIC_INLINE void LL_DMA_SetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Strea */ __STATIC_INLINE uint32_t LL_DMA_GetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MBURST)); } @@ -1354,7 +1355,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t S */ __STATIC_INLINE void LL_DMA_SetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Pburst) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PBURST, Pburst); } @@ -1380,7 +1381,7 @@ __STATIC_INLINE void LL_DMA_SetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Strea */ __STATIC_INLINE uint32_t LL_DMA_GetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PBURST)); } @@ -1405,7 +1406,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t S */ __STATIC_INLINE void LL_DMA_SetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t CurrentMemory) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_CT, CurrentMemory); } @@ -1429,7 +1430,7 @@ __STATIC_INLINE void LL_DMA_SetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stre */ __STATIC_INLINE uint32_t LL_DMA_GetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_CT)); } @@ -1451,7 +1452,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t */ __STATIC_INLINE void LL_DMA_EnableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DBM); } @@ -1473,7 +1474,7 @@ __STATIC_INLINE void LL_DMA_EnableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t S */ __STATIC_INLINE void LL_DMA_DisableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DBM); } @@ -1501,7 +1502,7 @@ __STATIC_INLINE void LL_DMA_DisableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t */ __STATIC_INLINE uint32_t LL_DMA_GetFIFOStatus(DMA_TypeDef *DMAx, uint32_t Stream) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FS)); } @@ -1523,7 +1524,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetFIFOStatus(DMA_TypeDef *DMAx, uint32_t Stream */ __STATIC_INLINE void LL_DMA_DisableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_DMDIS); } @@ -1545,7 +1546,7 @@ __STATIC_INLINE void LL_DMA_DisableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream) */ __STATIC_INLINE void LL_DMA_EnableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_DMDIS); } @@ -1572,7 +1573,7 @@ __STATIC_INLINE void LL_DMA_EnableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream) */ __STATIC_INLINE void LL_DMA_SetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Threshold) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FTH, Threshold); } @@ -1598,7 +1599,7 @@ __STATIC_INLINE void LL_DMA_SetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream, */ __STATIC_INLINE uint32_t LL_DMA_GetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FTH)); } @@ -1629,7 +1630,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Str */ __STATIC_INLINE void LL_DMA_ConfigFifo(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t FifoMode, uint32_t FifoThreshold) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FTH | DMA_SxFCR_DMDIS, FifoMode | FifoThreshold); } @@ -1659,7 +1660,7 @@ __STATIC_INLINE void LL_DMA_ConfigFifo(DMA_TypeDef *DMAx, uint32_t Stream, uint3 */ __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t SrcAddress, uint32_t DstAddress, uint32_t Direction) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; /* Direction Memory to Periph */ if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) @@ -1695,7 +1696,7 @@ __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Stream, */ __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t MemoryAddress) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR, MemoryAddress); } @@ -1720,7 +1721,7 @@ __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Stream, */ __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t PeriphAddress) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR, PeriphAddress); } @@ -1743,7 +1744,7 @@ __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Stream, */ __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Stream) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; return (READ_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR)); } @@ -1766,7 +1767,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Str */ __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Stream) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; return (READ_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR)); } @@ -1791,7 +1792,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Str */ __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t MemoryAddress) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR, MemoryAddress); } @@ -1816,7 +1817,7 @@ __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Stream, */ __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t MemoryAddress) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR, MemoryAddress); } @@ -1839,7 +1840,7 @@ __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Stream, */ __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Stream) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; return (READ_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR)); } @@ -1862,7 +1863,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Str */ __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Stream) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; return (READ_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR)); } @@ -1885,7 +1886,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Str */ __STATIC_INLINE void LL_DMA_SetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Address) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M1AR, DMA_SxM1AR_M1A, Address); } @@ -1907,7 +1908,7 @@ __STATIC_INLINE void LL_DMA_SetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream */ __STATIC_INLINE uint32_t LL_DMA_GetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; return (((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M1AR); } @@ -2825,7 +2826,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_FE7(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_HTIE); } @@ -2847,7 +2848,7 @@ __STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream) */ __STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TEIE); } @@ -2869,7 +2870,7 @@ __STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream) */ __STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TCIE); } @@ -2891,7 +2892,7 @@ __STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream) */ __STATIC_INLINE void LL_DMA_EnableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DMEIE); } @@ -2913,7 +2914,7 @@ __STATIC_INLINE void LL_DMA_EnableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream) */ __STATIC_INLINE void LL_DMA_EnableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FEIE); } @@ -2935,7 +2936,7 @@ __STATIC_INLINE void LL_DMA_EnableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream) */ __STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_HTIE); } @@ -2957,7 +2958,7 @@ __STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream) */ __STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TEIE); } @@ -2979,7 +2980,7 @@ __STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream) */ __STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TCIE); } @@ -3001,7 +3002,7 @@ __STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream) */ __STATIC_INLINE void LL_DMA_DisableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DMEIE); } @@ -3023,7 +3024,7 @@ __STATIC_INLINE void LL_DMA_DisableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream) */ __STATIC_INLINE void LL_DMA_DisableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FEIE); } @@ -3045,7 +3046,7 @@ __STATIC_INLINE void LL_DMA_DisableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream) */ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Stream) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_HTIE) == DMA_SxCR_HTIE) ? 1UL : 0UL); } @@ -3067,7 +3068,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Strea */ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Stream) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TEIE) == DMA_SxCR_TEIE) ? 1UL : 0UL); } @@ -3089,7 +3090,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Strea */ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Stream) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TCIE) == DMA_SxCR_TCIE) ? 1UL : 0UL); } @@ -3111,7 +3112,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Strea */ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_DME(DMA_TypeDef *DMAx, uint32_t Stream) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DMEIE) == DMA_SxCR_DMEIE) ? 1UL : 0UL); } @@ -3133,7 +3134,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_DME(DMA_TypeDef *DMAx, uint32_t Stre */ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_FE(DMA_TypeDef *DMAx, uint32_t Stream) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FEIE) == DMA_SxFCR_FEIE) ? 1UL : 0UL); } @@ -3165,7 +3166,6 @@ void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct); */ #endif /* DMA1 || DMA2 */ - /** * @} */ diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_ll_dmamux.h b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_ll_dmamux.h index fb0f94e201..c7c843e92c 100644 --- a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_ll_dmamux.h +++ b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_ll_dmamux.h @@ -140,11 +140,9 @@ extern "C" { * @} */ -/** @defgroup DMAMUX_LL_EC_REQUEST Transfer request - * @brief DMA Request selection +/** @defgroup DMAMUX_LL_EC_REQUEST DMAMUX1 Request * @{ */ -/* D2 Domain : DMAMUX1 requests */ #define LL_DMAMUX1_REQ_MEM2MEM 0U /*!< memory to memory transfer */ #define LL_DMAMUX1_REQ_GENERATOR0 1U /*!< DMAMUX1 request generator 0 */ #define LL_DMAMUX1_REQ_GENERATOR1 2U /*!< DMAMUX1 request generator 1 */ @@ -209,18 +207,26 @@ extern "C" { #define LL_DMAMUX1_REQ_UART4_TX 64U /*!< DMAMUX1 UART4 TX request */ #define LL_DMAMUX1_REQ_UART5_RX 65U /*!< DMAMUX1 UART5 RX request */ #define LL_DMAMUX1_REQ_UART5_TX 66U /*!< DMAMUX1 UART5 TX request */ -#define LL_DMAMUX1_REQ_DAC1 67U /*!< DMAMUX1 DAC1 Channel 1 request */ -#define LL_DMAMUX1_REQ_DAC2 68U /*!< DMAMUX1 DAC1 Channel 2 request */ +#if defined (DAC1) +#define LL_DMAMUX1_REQ_DAC1 67U /*!< DMAMUX1 DAC1 request */ +#define LL_DMAMUX1_REQ_DAC2 68U /*!< DMAMUX1 DAC2 request */ +#endif #define LL_DMAMUX1_REQ_TIM6_UP 69U /*!< DMAMUX1 TIM6 UP request */ #define LL_DMAMUX1_REQ_TIM7_UP 70U /*!< DMAMUX1 TIM7 UP request */ #define LL_DMAMUX1_REQ_USART6_RX 71U /*!< DMAMUX1 USART6 RX request */ #define LL_DMAMUX1_REQ_USART6_TX 72U /*!< DMAMUX1 USART6 TX request */ #define LL_DMAMUX1_REQ_I2C3_RX 73U /*!< DMAMUX1 I2C3 RX request */ #define LL_DMAMUX1_REQ_I2C3_TX 74U /*!< DMAMUX1 I2C3 TX request */ +#if defined (DCMI) #define LL_DMAMUX1_REQ_DCMI 75U /*!< DMAMUX1 DCMI request */ -#define LL_DMAMUX1_REQ_CRYP2_IN 76U /*!< DMAMUX1 CRYP2 IN request */ -#define LL_DMAMUX1_REQ_CRYP2_OUT 77U /*!< DMAMUX1 CRYP2 OUT request */ -#define LL_DMAMUX1_REQ_HASH2_IN 78U /*!< DMAMUX1 HASH2 IN request */ +#endif +#if defined(CRYP2) +#define LL_DMAMUX1_REQ_CRYP2_IN 76U /*!< DMAMUX1 CRYP2 IN request */ +#define LL_DMAMUX1_REQ_CRYP2_OUT 77U /*!< DMAMUX1 CRYP2 OUT request */ +#endif +#if defined (HASH2) +#define LL_DMAMUX1_REQ_HASH2_IN 78U /*!< DMAMUX1 HASH2 IN request */ +#endif #define LL_DMAMUX1_REQ_UART7_RX 79U /*!< DMAMUX1 UART7 RX request */ #define LL_DMAMUX1_REQ_UART7_TX 80U /*!< DMAMUX1 UART7 TX request */ #define LL_DMAMUX1_REQ_UART8_RX 81U /*!< DMAMUX1 UART8 RX request */ @@ -233,12 +239,14 @@ extern "C" { #define LL_DMAMUX1_REQ_SAI1_B 88U /*!< DMAMUX1 SAI1 B request */ #define LL_DMAMUX1_REQ_SAI2_A 89U /*!< DMAMUX1 SAI2 A request */ #define LL_DMAMUX1_REQ_SAI2_B 90U /*!< DMAMUX1 SAI2 B request */ -#define LL_DMAMUX1_REQ_DFSDM1_FLT4 91U /*!< DMAMUX1 DFSDM Filter4 request */ -#define LL_DMAMUX1_REQ_DFSDM1_FLT5 92U /*!< DMAMUX1 DFSDM Filter5 request */ +#define LL_DMAMUX1_REQ_DFSDM1_FLT4 91U /*!< DMAMUX1 DFSDM1 Filter4 request */ +#define LL_DMAMUX1_REQ_DFSDM1_FLT5 92U /*!< DMAMUX1 DFSDM1 Filter5 request */ #define LL_DMAMUX1_REQ_SPDIF_RX_DT 93U /*!< DMAMUX1 SPDIF RXDT request*/ #define LL_DMAMUX1_REQ_SPDIF_RX_CS 94U /*!< DMAMUX1 SPDIF RXCS request*/ +#if defined (SAI4) #define LL_DMAMUX1_REQ_SAI4_A 99U /*!< DMAMUX1 SAI4 A request */ #define LL_DMAMUX1_REQ_SAI4_B 100U /*!< DMAMUX1 SAI4 B request */ +#endif #define LL_DMAMUX1_REQ_DFSDM1_FLT0 101U /*!< DMAMUX1 DFSDM Filter0 request */ #define LL_DMAMUX1_REQ_DFSDM1_FLT1 102U /*!< DMAMUX1 DFSDM Filter1 request */ #define LL_DMAMUX1_REQ_DFSDM1_FLT2 103U /*!< DMAMUX1 DFSDM Filter2 request */ @@ -251,10 +259,12 @@ extern "C" { #define LL_DMAMUX1_REQ_TIM16_UP 110U /*!< DMAMUX1 TIM16 UP request */ #define LL_DMAMUX1_REQ_TIM17_CH1 111U /*!< DMAMUX1 TIM17 CH1 request */ #define LL_DMAMUX1_REQ_TIM17_UP 112U /*!< DMAMUX1 TIM17 UP request */ +#if defined (SAI3) #define LL_DMAMUX1_REQ_SAI3_A 113U /*!< DMAMUX1 SAI3 A request */ #define LL_DMAMUX1_REQ_SAI3_B 114U /*!< DMAMUX1 SAI3 B request */ -#define LL_DMAMUX1_REQ_I2C5_RX 115U /*!< DMAMUX1 I2C5 RX request */ -#define LL_DMAMUX1_REQ_I2C5_TX 116U /*!< DMAMUX1 I2C5 TX request */ +#endif +#define LL_DMAMUX1_REQ_I2C5_RX 115U /*!< DMAMUX1 I2C5 RX request */ +#define LL_DMAMUX1_REQ_I2C5_TX 116U /*!< DMAMUX1 I2C5 TX request */ /** * @} */ @@ -271,14 +281,14 @@ extern "C" { #define LL_DMAMUX_CHANNEL_5 0x00000005U /*!< DMAMUX1 Channel 5 connected to DMA1 Channel 5 */ #define LL_DMAMUX_CHANNEL_6 0x00000006U /*!< DMAMUX1 Channel 6 connected to DMA1 Channel 6 */ #define LL_DMAMUX_CHANNEL_7 0x00000007U /*!< DMAMUX1 Channel 7 connected to DMA1 Channel 7 */ -#define LL_DMAMUX_CHANNEL_8 0x00000008U /*!< DMAMUX1 Channel 8 connected to DMA1 Channel 8 */ -#define LL_DMAMUX_CHANNEL_9 0x00000009U /*!< DMAMUX1 Channel 9 connected to DMA1 Channel 9 */ -#define LL_DMAMUX_CHANNEL_10 0x0000000AU /*!< DMAMUX1 Channel 10 connected to DMA1 Channel 10 */ -#define LL_DMAMUX_CHANNEL_11 0x0000000BU /*!< DMAMUX1 Channel 11 connected to DMA1 Channel 11 */ -#define LL_DMAMUX_CHANNEL_12 0x0000000CU /*!< DMAMUX1 Channel 12 connected to DMA1 Channel 12 */ -#define LL_DMAMUX_CHANNEL_13 0x0000000DU /*!< DMAMUX1 Channel 13 connected to DMA1 Channel 13 */ -#define LL_DMAMUX_CHANNEL_14 0x0000000EU /*!< DMAMUX1 Channel 14 connected to DMA1 Channel 14 */ -#define LL_DMAMUX_CHANNEL_15 0x0000000FU /*!< DMAMUX1 Channel 15 connected to DMA& Channel 15 */ +#define LL_DMAMUX_CHANNEL_8 0x00000008U /*!< DMAMUX1 Channel 8 connected to DMA2 Channel 0 */ +#define LL_DMAMUX_CHANNEL_9 0x00000009U /*!< DMAMUX1 Channel 9 connected to DMA2 Channel 1 */ +#define LL_DMAMUX_CHANNEL_10 0x0000000AU /*!< DMAMUX1 Channel 10 connected to DMA2 Channel 2 */ +#define LL_DMAMUX_CHANNEL_11 0x0000000BU /*!< DMAMUX1 Channel 11 connected to DMA2 Channel 3 */ +#define LL_DMAMUX_CHANNEL_12 0x0000000CU /*!< DMAMUX1 Channel 12 connected to DMA2 Channel 4 */ +#define LL_DMAMUX_CHANNEL_13 0x0000000DU /*!< DMAMUX1 Channel 13 connected to DMA2 Channel 5 */ +#define LL_DMAMUX_CHANNEL_14 0x0000000EU /*!< DMAMUX1 Channel 14 connected to DMA2 Channel 6 */ +#define LL_DMAMUX_CHANNEL_15 0x0000000FU /*!< DMAMUX1 Channel 15 connected to DMA2 Channel 7 */ /** * @} */ @@ -297,15 +307,14 @@ extern "C" { /** @defgroup DMAMUX_LL_EC_SYNC_EVT Synchronization Signal Event * @{ */ -#define LL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT 0x00000000U /*!< D2 Domain synchronization Signal is DMAMUX1 Channel0 Event */ -#define LL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT 0x01000000U /*!< D2 Domain synchronization Signal is DMAMUX1 Channel1 Event */ -#define LL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT 0x02000000U /*!< D2 Domain synchronization Signal is DMAMUX1 Channel2 Event */ -#define LL_DMAMUX1_SYNC_LPTIM1_OUT 0x03000000U /*!< D2 Domain synchronization Signal is LPTIM1 OUT */ -#define LL_DMAMUX1_SYNC_LPTIM2_OUT 0x04000000U /*!< D2 Domain synchronization Signal is LPTIM2 OUT */ -#define LL_DMAMUX1_SYNC_LPTIM3_OUT 0x05000000U /*!< D2 Domain synchronization Signal is LPTIM3 OUT */ -#define LL_DMAMUX1_SYNC_EXTI0 0x06000000U /*!< D2 Domain synchronization Signal is EXTI0 IT */ -#define LL_DMAMUX1_SYNC_TIM12_TRGO 0x07000000U /*!< D2 Domain synchronization Signal is TIM12 TRGO */ - +#define LL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT 0x00000000U /*!< DMAMUX1 synchronization Signal is DMAMUX1 Channel0 Event */ +#define LL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT 0x01000000U /*!< DMAMUX1 synchronization Signal is DMAMUX1 Channel1 Event */ +#define LL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT 0x02000000U /*!< DMAMUX1 synchronization Signal is DMAMUX1 Channel2 Event */ +#define LL_DMAMUX1_SYNC_LPTIM1_OUT 0x03000000U /*!< DMAMUX1 synchronization Signal is LPTIM1 OUT */ +#define LL_DMAMUX1_SYNC_LPTIM2_OUT 0x04000000U /*!< DMAMUX1 synchronization Signal is LPTIM2 OUT */ +#define LL_DMAMUX1_SYNC_LPTIM3_OUT 0x05000000U /*!< DMAMUX1 synchronization Signal is LPTIM3 OUT */ +#define LL_DMAMUX1_SYNC_EXTI0 0x06000000U /*!< DMAMUX1 synchronization Signal is EXTI0 IT */ +#define LL_DMAMUX1_SYNC_TIM12_TRGO 0x07000000U /*!< DMAMUX1 synchronization Signal is TIM12 TRGO */ /** * @} */ @@ -339,14 +348,14 @@ extern "C" { /** @defgroup DMAMUX_LL_EC_REQUEST_GEN External Request Signal Generation * @{ */ -#define LL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT 0U /*!< D2 domain Request generator Signal is DMAMUX1 Channel0 Event */ -#define LL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT 1U /*!< D2 domain Request generator Signal is DMAMUX1 Channel1 Event */ -#define LL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT 2U /*!< D2 domain Request generator Signal is DMAMUX1 Channel2 Event */ -#define LL_DMAMUX1_REQ_GEN_LPTIM1_OUT 3U /*!< D2 domain Request generator Signal is LPTIM1 OUT */ -#define LL_DMAMUX1_REQ_GEN_LPTIM2_OUT 4U /*!< D2 domain Request generator Signal is LPTIM2 OUT */ -#define LL_DMAMUX1_REQ_GEN_LPTIM3_OUT 5U /*!< D2 domain Request generator Signal is LPTIM3 OUT */ -#define LL_DMAMUX1_REQ_GEN_EXTI0 6U /*!< D2 domain Request generator Signal is EXTI0 IT */ -#define LL_DMAMUX1_REQ_GEN_TIM12_TRGO 7U /*!< D2 domain Request generator Signal is TIM12 TRGO */ +#define LL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT 0U /*!< DMAMUX1 Request generator Signal is DMAMUX1 Channel0 Event */ +#define LL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT 1U /*!< DMAMUX1 Request generator Signal is DMAMUX1 Channel1 Event */ +#define LL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT 2U /*!< DMAMUX1 Request generator Signal is DMAMUX1 Channel2 Event */ +#define LL_DMAMUX1_REQ_GEN_LPTIM1_OUT 3U /*!< DMAMUX1 Request generator Signal is LPTIM1 OUT */ +#define LL_DMAMUX1_REQ_GEN_LPTIM2_OUT 4U /*!< DMAMUX1 Request generator Signal is LPTIM2 OUT */ +#define LL_DMAMUX1_REQ_GEN_LPTIM3_OUT 5U /*!< DMAMUX1 Request generator Signal is LPTIM3 OUT */ +#define LL_DMAMUX1_REQ_GEN_EXTI0 6U /*!< DMAMUX1 Request generator Signal is EXTI0 IT */ +#define LL_DMAMUX1_REQ_GEN_TIM12_TRGO 7U /*!< DMAMUX1 Request generator Signal is TIM12 TRGO */ /** * @} */ @@ -397,9 +406,8 @@ extern "C" { */ /** * @brief Set DMAMUX request ID for DMAMUX Channel x. - * @note DMAMUX1 channel 0 to 7 are mapped to DMA1 channel 0 to 7. - * DMAMUX1 channel 8 to 15 are mapped to DMA2 channel 0 to 7. - * DMAMUX2 channel 0 to 7 are mapped to BDMA channel 0 to 7. + * @note DMAMUX channel 0 to 7 are mapped to DMA1 channel 0 to 7. + * DMAMUX channel 8 to 15 are mapped to DMA2 channel 0 to 7. * @rmtoll CxCR DMAREQ_ID LL_DMAMUX_SetRequestID * @param DMAMUXx DMAMUXx Instance * @param Channel This parameter can be one of the following values: @@ -534,14 +542,15 @@ extern "C" { */ __STATIC_INLINE void LL_DMAMUX_SetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Request) { - MODIFY_REG(((DMAMUX_Channel_TypeDef *)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, DMAMUX_CxCR_DMAREQ_ID, Request); + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + MODIFY_REG(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_DMAREQ_ID, Request); } /** * @brief Get DMAMUX request ID for DMAMUX Channel x. - * @note DMAMUX1 channel 0 to 7 are mapped to DMA1 channel 0 to 7. - * DMAMUX1 channel 8 to 15 are mapped to DMA2 channel 0 to 7. - * DMAMUX2 channel 0 to 7 are mapped to BDMA channel 0 to 7. + * @note DMAMUX channel 0 to 7 are mapped to DMA1 channel 0 to 7. + * DMAMUX channel 8 to 15 are mapped to DMA2 channel 0 to 7. * @rmtoll CxCR DMAREQ_ID LL_DMAMUX_GetRequestID * @param DMAMUXx DMAMUXx Instance * @param Channel This parameter can be one of the following values: @@ -675,7 +684,9 @@ __STATIC_INLINE void LL_DMAMUX_SetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx, uin */ __STATIC_INLINE uint32_t LL_DMAMUX_GetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { - return (uint32_t)(READ_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, DMAMUX_CxCR_DMAREQ_ID)); + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return (uint32_t)(READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_DMAREQ_ID)); } /** @@ -704,7 +715,9 @@ __STATIC_INLINE uint32_t LL_DMAMUX_GetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx, */ __STATIC_INLINE void LL_DMAMUX_SetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t RequestNb) { - MODIFY_REG(((DMAMUX_Channel_TypeDef *)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, DMAMUX_CxCR_NBREQ, (RequestNb - 1U) << DMAMUX_CxCR_NBREQ_Pos); + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + MODIFY_REG(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_NBREQ, (RequestNb - 1U) << DMAMUX_CxCR_NBREQ_Pos); } /** @@ -732,7 +745,9 @@ __STATIC_INLINE void LL_DMAMUX_SetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, */ __STATIC_INLINE uint32_t LL_DMAMUX_GetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { - return (uint32_t)((READ_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, DMAMUX_CxCR_NBREQ) >> DMAMUX_CxCR_NBREQ_Pos) + 1U); + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return (uint32_t)((READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_NBREQ) >> DMAMUX_CxCR_NBREQ_Pos) + 1U); } /** @@ -765,7 +780,9 @@ __STATIC_INLINE uint32_t LL_DMAMUX_GetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAM */ __STATIC_INLINE void LL_DMAMUX_SetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Polarity) { - MODIFY_REG(((DMAMUX_Channel_TypeDef *)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, DMAMUX_CxCR_SPOL, Polarity); + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + MODIFY_REG(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SPOL, Polarity); } /** @@ -797,7 +814,9 @@ __STATIC_INLINE void LL_DMAMUX_SetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, */ __STATIC_INLINE uint32_t LL_DMAMUX_GetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { - return (uint32_t)(READ_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, DMAMUX_CxCR_SPOL)); + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return (uint32_t)(READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SPOL)); } /** @@ -825,7 +844,9 @@ __STATIC_INLINE uint32_t LL_DMAMUX_GetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMU */ __STATIC_INLINE void LL_DMAMUX_EnableEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { - SET_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, DMAMUX_CxCR_EGE); + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + SET_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_EGE); } /** @@ -853,7 +874,9 @@ __STATIC_INLINE void LL_DMAMUX_EnableEventGeneration(DMAMUX_Channel_TypeDef *DMA */ __STATIC_INLINE void LL_DMAMUX_DisableEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { - CLEAR_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, DMAMUX_CxCR_EGE); + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + CLEAR_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_EGE); } /** @@ -881,7 +904,9 @@ __STATIC_INLINE void LL_DMAMUX_DisableEventGeneration(DMAMUX_Channel_TypeDef *DM */ __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { - return ((READ_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, DMAMUX_CxCR_EGE) == (DMAMUX_CxCR_EGE)) ? 1UL : 0UL); + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return ((READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_EGE) == (DMAMUX_CxCR_EGE)) ? 1UL : 0UL); } /** @@ -909,7 +934,9 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledEventGeneration(DMAMUX_Channel_TypeD */ __STATIC_INLINE void LL_DMAMUX_EnableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { - SET_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, DMAMUX_CxCR_SE); + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + SET_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SE); } /** @@ -937,7 +964,9 @@ __STATIC_INLINE void LL_DMAMUX_EnableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint3 */ __STATIC_INLINE void LL_DMAMUX_DisableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { - CLEAR_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, DMAMUX_CxCR_SE); + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + CLEAR_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SE); } /** @@ -965,7 +994,9 @@ __STATIC_INLINE void LL_DMAMUX_DisableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint */ __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { - return ((READ_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, DMAMUX_CxCR_SE) == (DMAMUX_CxCR_SE)) ? 1UL : 0UL); + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return ((READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SE) == (DMAMUX_CxCR_SE)) ? 1UL : 0UL); } /** @@ -1002,7 +1033,9 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledSync(DMAMUX_Channel_TypeDef *DMAMUXx */ __STATIC_INLINE void LL_DMAMUX_SetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t SyncID) { - MODIFY_REG(((DMAMUX_Channel_TypeDef *)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, DMAMUX_CxCR_SYNC_ID, SyncID); + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + MODIFY_REG(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SYNC_ID, SyncID); } /** @@ -1038,7 +1071,9 @@ __STATIC_INLINE void LL_DMAMUX_SetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32 */ __STATIC_INLINE uint32_t LL_DMAMUX_GetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { - return (uint32_t)(READ_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, DMAMUX_CxCR_SYNC_ID)); + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return (uint32_t)(READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SYNC_ID)); } /** @@ -1058,7 +1093,9 @@ __STATIC_INLINE uint32_t LL_DMAMUX_GetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx, ui */ __STATIC_INLINE void LL_DMAMUX_EnableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) { - SET_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)((uint32_t)DMAMUXx + DMAMUX_REQ_GEN_OFFSET) + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GE); + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + SET_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * (RequestGenChannel))))->RGCR, DMAMUX_RGxCR_GE); } /** @@ -1074,7 +1111,9 @@ __STATIC_INLINE void LL_DMAMUX_EnableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, */ __STATIC_INLINE void LL_DMAMUX_DisableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) { - CLEAR_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)((uint32_t)DMAMUXx + DMAMUX_REQ_GEN_OFFSET) + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GE); + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + CLEAR_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * (RequestGenChannel))))->RGCR, DMAMUX_RGxCR_GE); } /** @@ -1094,7 +1133,9 @@ __STATIC_INLINE void LL_DMAMUX_DisableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx */ __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) { - return ((READ_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)DMAMUXx + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_GE) == (DMAMUX_RGxCR_GE)) ? 1UL : 0UL); + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return ((READ_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_GE) == (DMAMUX_RGxCR_GE)) ? 1UL : 0UL); } /** @@ -1119,7 +1160,9 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledRequestGen(DMAMUX_Channel_TypeDef *D */ __STATIC_INLINE void LL_DMAMUX_SetRequestGenPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t Polarity) { - MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)((uint32_t)DMAMUXx + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_GPOL, Polarity); + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_GPOL, Polarity); } /** @@ -1143,7 +1186,9 @@ __STATIC_INLINE void LL_DMAMUX_SetRequestGenPolarity(DMAMUX_Channel_TypeDef *DMA */ __STATIC_INLINE uint32_t LL_DMAMUX_GetRequestGenPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) { - return (uint32_t)(READ_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)DMAMUXx + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_GPOL)); + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return (uint32_t)(READ_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_GPOL)); } /** @@ -1165,7 +1210,9 @@ __STATIC_INLINE uint32_t LL_DMAMUX_GetRequestGenPolarity(DMAMUX_Channel_TypeDef */ __STATIC_INLINE void LL_DMAMUX_SetGenRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t RequestNb) { - MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)((uint32_t)DMAMUXx + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_GNBREQ, (RequestNb - 1U) << DMAMUX_RGxCR_GNBREQ_Pos); + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_GNBREQ, (RequestNb - 1U) << DMAMUX_RGxCR_GNBREQ_Pos); } /** @@ -1185,7 +1232,9 @@ __STATIC_INLINE void LL_DMAMUX_SetGenRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, */ __STATIC_INLINE uint32_t LL_DMAMUX_GetGenRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) { - return (uint32_t)((READ_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)DMAMUXx + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_GNBREQ) >> DMAMUX_RGxCR_GNBREQ_Pos) + 1U); + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return (uint32_t)((READ_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_GNBREQ) >> DMAMUX_RGxCR_GNBREQ_Pos) + 1U); } /** @@ -1214,7 +1263,9 @@ __STATIC_INLINE uint32_t LL_DMAMUX_GetGenRequestNb(DMAMUX_Channel_TypeDef *DMAMU */ __STATIC_INLINE void LL_DMAMUX_SetRequestSignalID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t RequestSignalID) { - MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)((uint32_t)DMAMUXx + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_SIG_ID, RequestSignalID); + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_SIG_ID, RequestSignalID); } /** @@ -1242,7 +1293,9 @@ __STATIC_INLINE void LL_DMAMUX_SetRequestSignalID(DMAMUX_Channel_TypeDef *DMAMUX */ __STATIC_INLINE uint32_t LL_DMAMUX_GetRequestSignalID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) { - return (uint32_t)(READ_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)DMAMUXx + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_SIG_ID)); + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return (uint32_t)(READ_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_SIG_ID)); } /** @@ -1261,7 +1314,9 @@ __STATIC_INLINE uint32_t LL_DMAMUX_GetRequestSignalID(DMAMUX_Channel_TypeDef *DM */ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO0(DMAMUX_Channel_TypeDef *DMAMUXx) { - return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)((uint32_t)DMAMUXx + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF0) == (DMAMUX_CSR_SOF0)) ? 1UL : 0UL); + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF0) == (DMAMUX_CSR_SOF0)) ? 1UL : 0UL); } /** @@ -1272,7 +1327,9 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO0(DMAMUX_Channel_TypeDef *DMAM */ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO1(DMAMUX_Channel_TypeDef *DMAMUXx) { - return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)((uint32_t)DMAMUXx + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF1) == (DMAMUX_CSR_SOF1)) ? 1UL : 0UL); + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF1) == (DMAMUX_CSR_SOF1)) ? 1UL : 0UL); } /** @@ -1283,7 +1340,9 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO1(DMAMUX_Channel_TypeDef *DMAM */ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO2(DMAMUX_Channel_TypeDef *DMAMUXx) { - return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)((uint32_t)DMAMUXx + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF2) == (DMAMUX_CSR_SOF2)) ? 1UL : 0UL); + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF2) == (DMAMUX_CSR_SOF2)) ? 1UL : 0UL); } /** @@ -1294,7 +1353,9 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO2(DMAMUX_Channel_TypeDef *DMAM */ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO3(DMAMUX_Channel_TypeDef *DMAMUXx) { - return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)((uint32_t)DMAMUXx + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF3) == (DMAMUX_CSR_SOF3)) ? 1UL : 0UL); + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF3) == (DMAMUX_CSR_SOF3)) ? 1UL : 0UL); } /** @@ -1305,7 +1366,9 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO3(DMAMUX_Channel_TypeDef *DMAM */ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO4(DMAMUX_Channel_TypeDef *DMAMUXx) { - return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)((uint32_t)DMAMUXx + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF4) == (DMAMUX_CSR_SOF4)) ? 1UL : 0UL); + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF4) == (DMAMUX_CSR_SOF4)) ? 1UL : 0UL); } /** @@ -1316,7 +1379,9 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO4(DMAMUX_Channel_TypeDef *DMAM */ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO5(DMAMUX_Channel_TypeDef *DMAMUXx) { - return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)((uint32_t)DMAMUXx + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF5) == (DMAMUX_CSR_SOF5)) ? 1UL : 0UL); + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF5) == (DMAMUX_CSR_SOF5)) ? 1UL : 0UL); } /** @@ -1327,7 +1392,9 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO5(DMAMUX_Channel_TypeDef *DMAM */ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO6(DMAMUX_Channel_TypeDef *DMAMUXx) { - return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)((uint32_t)DMAMUXx + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF6) == (DMAMUX_CSR_SOF6)) ? 1UL : 0UL); + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF6) == (DMAMUX_CSR_SOF6)) ? 1UL : 0UL); } /** @@ -1338,7 +1405,9 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO6(DMAMUX_Channel_TypeDef *DMAM */ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO7(DMAMUX_Channel_TypeDef *DMAMUXx) { - return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)((uint32_t)DMAMUXx + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF7) == (DMAMUX_CSR_SOF7)) ? 1UL : 0UL); + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF7) == (DMAMUX_CSR_SOF7)) ? 1UL : 0UL); } /** @@ -1349,7 +1418,9 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO7(DMAMUX_Channel_TypeDef *DMAM */ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO8(DMAMUX_Channel_TypeDef *DMAMUXx) { - return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)((uint32_t)DMAMUXx + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF8) == (DMAMUX_CSR_SOF8)) ? 1UL : 0UL); + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF8) == (DMAMUX_CSR_SOF8)) ? 1UL : 0UL); } /** @@ -1360,7 +1431,9 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO8(DMAMUX_Channel_TypeDef *DMAM */ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO9(DMAMUX_Channel_TypeDef *DMAMUXx) { - return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)((uint32_t)DMAMUXx + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF9) == (DMAMUX_CSR_SOF9)) ? 1UL : 0UL); + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF9) == (DMAMUX_CSR_SOF9)) ? 1UL : 0UL); } /** @@ -1371,7 +1444,9 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO9(DMAMUX_Channel_TypeDef *DMAM */ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO10(DMAMUX_Channel_TypeDef *DMAMUXx) { - return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)((uint32_t)DMAMUXx + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF10) == (DMAMUX_CSR_SOF10)) ? 1UL : 0UL); + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF10) == (DMAMUX_CSR_SOF10)) ? 1UL : 0UL); } /** @@ -1382,7 +1457,9 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO10(DMAMUX_Channel_TypeDef *DMA */ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO11(DMAMUX_Channel_TypeDef *DMAMUXx) { - return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)((uint32_t)DMAMUXx + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF11) == (DMAMUX_CSR_SOF11)) ? 1UL : 0UL); + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF11) == (DMAMUX_CSR_SOF11)) ? 1UL : 0UL); } /** @@ -1393,7 +1470,9 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO11(DMAMUX_Channel_TypeDef *DMA */ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO12(DMAMUX_Channel_TypeDef *DMAMUXx) { - return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)((uint32_t)DMAMUXx + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF12) == (DMAMUX_CSR_SOF12)) ? 1UL : 0UL); + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF12) == (DMAMUX_CSR_SOF12)) ? 1UL : 0UL); } /** @@ -1404,7 +1483,9 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO12(DMAMUX_Channel_TypeDef *DMA */ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO13(DMAMUX_Channel_TypeDef *DMAMUXx) { - return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)((uint32_t)DMAMUXx + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF13) == (DMAMUX_CSR_SOF13)) ? 1UL : 0UL); + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF13) == (DMAMUX_CSR_SOF13)) ? 1UL : 0UL); } /** @@ -1415,7 +1496,9 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO13(DMAMUX_Channel_TypeDef *DMA */ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO14(DMAMUX_Channel_TypeDef *DMAMUXx) { - return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)((uint32_t)DMAMUXx + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF14) == (DMAMUX_CSR_SOF14)) ? 1UL : 0UL); + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF14) == (DMAMUX_CSR_SOF14)) ? 1UL : 0UL); } /** @@ -1426,7 +1509,9 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO14(DMAMUX_Channel_TypeDef *DMA */ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO15(DMAMUX_Channel_TypeDef *DMAMUXx) { - return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)((uint32_t)DMAMUXx + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF15) == (DMAMUX_CSR_SOF15)) ? 1UL : 0UL); + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF15) == (DMAMUX_CSR_SOF15)) ? 1UL : 0UL); } /** @@ -1437,7 +1522,9 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO15(DMAMUX_Channel_TypeDef *DMA */ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO0(DMAMUX_Channel_TypeDef *DMAMUXx) { - return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)((uint32_t)DMAMUXx + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF0) == (DMAMUX_RGSR_OF0)) ? 1UL : 0UL); + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF0) == (DMAMUX_RGSR_OF0)) ? 1UL : 0UL); } /** @@ -1448,7 +1535,9 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO0(DMAMUX_Channel_TypeDef *DMA */ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO1(DMAMUX_Channel_TypeDef *DMAMUXx) { - return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)((uint32_t)DMAMUXx + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF1) == (DMAMUX_RGSR_OF1)) ? 1UL : 0UL); + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF1) == (DMAMUX_RGSR_OF1)) ? 1UL : 0UL); } /** @@ -1459,7 +1548,9 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO1(DMAMUX_Channel_TypeDef *DMA */ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO2(DMAMUX_Channel_TypeDef *DMAMUXx) { - return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)((uint32_t)DMAMUXx + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF2) == (DMAMUX_RGSR_OF2)) ? 1UL : 0UL); + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF2) == (DMAMUX_RGSR_OF2)) ? 1UL : 0UL); } /** @@ -1470,7 +1561,9 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO2(DMAMUX_Channel_TypeDef *DMA */ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO3(DMAMUX_Channel_TypeDef *DMAMUXx) { - return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)((uint32_t)DMAMUXx + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF3) == (DMAMUX_RGSR_OF3)) ? 1UL : 0UL); + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF3) == (DMAMUX_RGSR_OF3)) ? 1UL : 0UL); } /** @@ -1481,7 +1574,9 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO3(DMAMUX_Channel_TypeDef *DMA */ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO4(DMAMUX_Channel_TypeDef *DMAMUXx) { - return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)((uint32_t)DMAMUXx + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF4) == (DMAMUX_RGSR_OF4)) ? 1UL : 0UL); + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF4) == (DMAMUX_RGSR_OF4)) ? 1UL : 0UL); } /** @@ -1492,7 +1587,9 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO4(DMAMUX_Channel_TypeDef *DMA */ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO5(DMAMUX_Channel_TypeDef *DMAMUXx) { - return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)((uint32_t)DMAMUXx + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF5) == (DMAMUX_RGSR_OF5)) ? 1UL : 0UL); + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF5) == (DMAMUX_RGSR_OF5)) ? 1UL : 0UL); } /** @@ -1503,7 +1600,9 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO5(DMAMUX_Channel_TypeDef *DMA */ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO6(DMAMUX_Channel_TypeDef *DMAMUXx) { - return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)((uint32_t)DMAMUXx + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF6) == (DMAMUX_RGSR_OF6)) ? 1UL : 0UL); + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF6) == (DMAMUX_RGSR_OF6)) ? 1UL : 0UL); } /** @@ -1514,7 +1613,9 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO6(DMAMUX_Channel_TypeDef *DMA */ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO7(DMAMUX_Channel_TypeDef *DMAMUXx) { - return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)((uint32_t)DMAMUXx + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF7) == (DMAMUX_RGSR_OF7)) ? 1UL : 0UL); + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF7) == (DMAMUX_RGSR_OF7)) ? 1UL : 0UL); } /** @@ -1525,7 +1626,9 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO7(DMAMUX_Channel_TypeDef *DMA */ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO0(DMAMUX_Channel_TypeDef *DMAMUXx) { - SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)((uint32_t)DMAMUXx + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF0); + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF0); } /** @@ -1536,7 +1639,9 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO0(DMAMUX_Channel_TypeDef *DMAMUXx) */ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO1(DMAMUX_Channel_TypeDef *DMAMUXx) { - SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)((uint32_t)DMAMUXx + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF1); + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF1); } /** @@ -1547,7 +1652,9 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO1(DMAMUX_Channel_TypeDef *DMAMUXx) */ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO2(DMAMUX_Channel_TypeDef *DMAMUXx) { - SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)((uint32_t)DMAMUXx + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF2); + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF2); } /** @@ -1558,7 +1665,9 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO2(DMAMUX_Channel_TypeDef *DMAMUXx) */ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO3(DMAMUX_Channel_TypeDef *DMAMUXx) { - SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)((uint32_t)DMAMUXx + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF3); + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF3); } /** @@ -1569,7 +1678,9 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO3(DMAMUX_Channel_TypeDef *DMAMUXx) */ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO4(DMAMUX_Channel_TypeDef *DMAMUXx) { - SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)((uint32_t)DMAMUXx + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF4); + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF4); } /** @@ -1580,7 +1691,9 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO4(DMAMUX_Channel_TypeDef *DMAMUXx) */ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO5(DMAMUX_Channel_TypeDef *DMAMUXx) { - SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)((uint32_t)DMAMUXx + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF5); + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF5); } /** @@ -1591,7 +1704,9 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO5(DMAMUX_Channel_TypeDef *DMAMUXx) */ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO6(DMAMUX_Channel_TypeDef *DMAMUXx) { - SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)((uint32_t)DMAMUXx + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF6); + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF6); } /** @@ -1602,7 +1717,9 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO6(DMAMUX_Channel_TypeDef *DMAMUXx) */ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO7(DMAMUX_Channel_TypeDef *DMAMUXx) { - SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)((uint32_t)DMAMUXx + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF7); + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF7); } /** @@ -1613,7 +1730,9 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO7(DMAMUX_Channel_TypeDef *DMAMUXx) */ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO8(DMAMUX_Channel_TypeDef *DMAMUXx) { - SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)((uint32_t)DMAMUXx + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF8); + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF8); } /** @@ -1624,7 +1743,9 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO8(DMAMUX_Channel_TypeDef *DMAMUXx) */ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO9(DMAMUX_Channel_TypeDef *DMAMUXx) { - SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)((uint32_t)DMAMUXx + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF9); + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF9); } /** @@ -1635,7 +1756,9 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO9(DMAMUX_Channel_TypeDef *DMAMUXx) */ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO10(DMAMUX_Channel_TypeDef *DMAMUXx) { - SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)((uint32_t)DMAMUXx + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF10); + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF10); } /** @@ -1646,7 +1769,9 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO10(DMAMUX_Channel_TypeDef *DMAMUXx) */ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO11(DMAMUX_Channel_TypeDef *DMAMUXx) { - SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)((uint32_t)DMAMUXx + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF11); + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF11); } /** @@ -1657,7 +1782,9 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO11(DMAMUX_Channel_TypeDef *DMAMUXx) */ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO12(DMAMUX_Channel_TypeDef *DMAMUXx) { - SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)((uint32_t)DMAMUXx + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF12); + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF12); } /** @@ -1668,7 +1795,9 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO12(DMAMUX_Channel_TypeDef *DMAMUXx) */ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO13(DMAMUX_Channel_TypeDef *DMAMUXx) { - SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)((uint32_t)DMAMUXx + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF13); + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF13); } /** @@ -1679,7 +1808,9 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO13(DMAMUX_Channel_TypeDef *DMAMUXx) */ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO14(DMAMUX_Channel_TypeDef *DMAMUXx) { - SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)((uint32_t)DMAMUXx + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF14); + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF14); } /** @@ -1690,7 +1821,9 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO14(DMAMUX_Channel_TypeDef *DMAMUXx) */ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO15(DMAMUX_Channel_TypeDef *DMAMUXx) { - SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)((uint32_t)DMAMUXx + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF15); + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF15); } /** @@ -1701,7 +1834,9 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO15(DMAMUX_Channel_TypeDef *DMAMUXx) */ __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO0(DMAMUX_Channel_TypeDef *DMAMUXx) { - SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)((uint32_t)DMAMUXx + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF0); + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF0); } /** @@ -1712,7 +1847,9 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO0(DMAMUX_Channel_TypeDef *DMAMUXx) */ __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO1(DMAMUX_Channel_TypeDef *DMAMUXx) { - SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)((uint32_t)DMAMUXx + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF1); + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF1); } /** @@ -1723,7 +1860,9 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO1(DMAMUX_Channel_TypeDef *DMAMUXx) */ __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO2(DMAMUX_Channel_TypeDef *DMAMUXx) { - SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)((uint32_t)DMAMUXx + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF2); + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF2); } /** @@ -1734,7 +1873,9 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO2(DMAMUX_Channel_TypeDef *DMAMUXx) */ __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO3(DMAMUX_Channel_TypeDef *DMAMUXx) { - SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)((uint32_t)DMAMUXx + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF3); + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF3); } /** @@ -1745,7 +1886,9 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO3(DMAMUX_Channel_TypeDef *DMAMUXx) */ __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO4(DMAMUX_Channel_TypeDef *DMAMUXx) { - SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)((uint32_t)DMAMUXx + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF4); + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF4); } /** @@ -1756,7 +1899,9 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO4(DMAMUX_Channel_TypeDef *DMAMUXx) */ __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO5(DMAMUX_Channel_TypeDef *DMAMUXx) { - SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)((uint32_t)DMAMUXx + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF5); + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF5); } /** @@ -1767,7 +1912,9 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO5(DMAMUX_Channel_TypeDef *DMAMUXx) */ __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO6(DMAMUX_Channel_TypeDef *DMAMUXx) { - SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)((uint32_t)DMAMUXx + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF6); + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF6); } /** @@ -1778,7 +1925,9 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO6(DMAMUX_Channel_TypeDef *DMAMUXx) */ __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO7(DMAMUX_Channel_TypeDef *DMAMUXx) { - SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)((uint32_t)DMAMUXx + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF7); + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF7); } /** @@ -1814,7 +1963,9 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO7(DMAMUX_Channel_TypeDef *DMAMUXx) */ __STATIC_INLINE void LL_DMAMUX_EnableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { - SET_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, DMAMUX_CxCR_SOIE); + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + SET_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, DMAMUX_CxCR_SOIE); } /** @@ -1842,7 +1993,9 @@ __STATIC_INLINE void LL_DMAMUX_EnableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint */ __STATIC_INLINE void LL_DMAMUX_DisableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { - CLEAR_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, DMAMUX_CxCR_SOIE); + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + CLEAR_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, DMAMUX_CxCR_SOIE); } /** @@ -1870,7 +2023,9 @@ __STATIC_INLINE void LL_DMAMUX_DisableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uin */ __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { - return (READ_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, DMAMUX_CxCR_SOIE)); + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return (READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SOIE)); } /** @@ -1890,7 +2045,9 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_SO(DMAMUX_Channel_TypeDef *DMAMUX */ __STATIC_INLINE void LL_DMAMUX_EnableIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) { - SET_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)DMAMUXx + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_OIE); + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + SET_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_OIE); } /** @@ -1910,7 +2067,9 @@ __STATIC_INLINE void LL_DMAMUX_EnableIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uin */ __STATIC_INLINE void LL_DMAMUX_DisableIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) { - CLEAR_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)DMAMUXx + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_OIE); + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + CLEAR_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_OIE); } /** @@ -1930,7 +2089,9 @@ __STATIC_INLINE void LL_DMAMUX_DisableIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, ui */ __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) { - return ((READ_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)DMAMUXx + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_OIE) == (DMAMUX_RGxCR_OIE)) ? 1UL : 0UL); + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return ((READ_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_OIE) == (DMAMUX_RGxCR_OIE)) ? 1UL : 0UL); } /** diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_ll_ipcc.h b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_ll_ipcc.h index 8041443b4c..06c14c27bd 100644 --- a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_ll_ipcc.h +++ b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_ll_ipcc.h @@ -730,4 +730,3 @@ __STATIC_INLINE uint32_t LL_IPCC_GetChannelNumber(IPCC_TypeDef *IPCCx) #endif /* STM32MP1xx_LL_IPCC_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_ll_rcc.h b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_ll_rcc.h index 4a661e8f5c..b8b5598d54 100644 --- a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_ll_rcc.h +++ b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_ll_rcc.h @@ -340,22 +340,22 @@ typedef struct /** @defgroup RCC_LL_EC_MCO2_DIV MCO2 prescaler * @{ */ -#define LL_RCC_MCO2_DIV_1 RCC_MCO2CFGR_MCO2DIV_0 /*!< MCO not divided */ -#define LL_RCC_MCO2_DIV_2 RCC_MCO2CFGR_MCO2DIV_1 /*!< MCO divided by 2 */ -#define LL_RCC_MCO2_DIV_3 RCC_MCO2CFGR_MCO2DIV_2 /*!< MCO divided by 3 */ -#define LL_RCC_MCO2_DIV_4 RCC_MCO2CFGR_MCO2DIV_3 /*!< MCO divided by 4 */ -#define LL_RCC_MCO2_DIV_5 RCC_MCO2CFGR_MCO2DIV_4 /*!< MCO divided by 5 */ -#define LL_RCC_MCO2_DIV_6 RCC_MCO2CFGR_MCO2DIV_5 /*!< MCO divided by 6 */ -#define LL_RCC_MCO2_DIV_7 RCC_MCO2CFGR_MCO2DIV_6 /*!< MCO divided by 7 */ -#define LL_RCC_MCO2_DIV_8 RCC_MCO2CFGR_MCO2DIV_7 /*!< MCO divided by 8 */ -#define LL_RCC_MCO2_DIV_9 RCC_MCO2CFGR_MCO2DIV_8 /*!< MCO divided by 9 */ -#define LL_RCC_MCO2_DIV_10 RCC_MCO2CFGR_MCO2DIV_9 /*!< MCO divided by 10 */ -#define LL_RCC_MCO2_DIV_11 RCC_MCO2CFGR_MCO2DIV_10 /*!< MCO divided by 11 */ -#define LL_RCC_MCO2_DIV_12 RCC_MCO2CFGR_MCO2DIV_11 /*!< MCO divided by 12 */ -#define LL_RCC_MCO2_DIV_13 RCC_MCO2CFGR_MCO2DIV_12 /*!< MCO divided by 13 */ -#define LL_RCC_MCO2_DIV_14 RCC_MCO2CFGR_MCO2DIV_13 /*!< MCO divided by 14 */ -#define LL_RCC_MCO2_DIV_15 RCC_MCO2CFGR_MCO2DIV_14 /*!< MCO divided by 15 */ -#define LL_RCC_MCO2_DIV_16 RCC_MCO2CFGR_MCO2DIV_15 /*!< MCO divided by 16 */ +#define LL_RCC_MCO2_DIV_1 0U /*!< MCO not divided */ +#define LL_RCC_MCO2_DIV_2 RCC_MCO2CFGR_MCO2DIV_0 /*!< MCO divided by 2 */ +#define LL_RCC_MCO2_DIV_3 RCC_MCO2CFGR_MCO2DIV_1 /*!< MCO divided by 3 */ +#define LL_RCC_MCO2_DIV_4 (RCC_MCO2CFGR_MCO2DIV_1 | RCC_MCO2CFGR_MCO2DIV_0) /*!< MCO divided by 4 */ +#define LL_RCC_MCO2_DIV_5 RCC_MCO2CFGR_MCO2DIV_2 /*!< MCO divided by 5 */ +#define LL_RCC_MCO2_DIV_6 (RCC_MCO2CFGR_MCO2DIV_2 | RCC_MCO2CFGR_MCO2DIV_0) /*!< MCO divided by 6 */ +#define LL_RCC_MCO2_DIV_7 (RCC_MCO2CFGR_MCO2DIV_2 | RCC_MCO2CFGR_MCO2DIV_1) /*!< MCO divided by 7 */ +#define LL_RCC_MCO2_DIV_8 (RCC_MCO2CFGR_MCO2DIV_2 | RCC_MCO2CFGR_MCO2DIV_1 | RCC_MCO2CFGR_MCO2DIV_0) /*!< MCO divided by 8 */ +#define LL_RCC_MCO2_DIV_9 RCC_MCO2CFGR_MCO2DIV_3 /*!< MCO divided by 9 */ +#define LL_RCC_MCO2_DIV_10 (RCC_MCO2CFGR_MCO2DIV_3 | RCC_MCO2CFGR_MCO2DIV_0) /*!< MCO divided by 10 */ +#define LL_RCC_MCO2_DIV_11 (RCC_MCO2CFGR_MCO2DIV_3 | RCC_MCO2CFGR_MCO2DIV_1) /*!< MCO divided by 11 */ +#define LL_RCC_MCO2_DIV_12 (RCC_MCO2CFGR_MCO2DIV_3 | RCC_MCO2CFGR_MCO2DIV_1 | RCC_MCO2CFGR_MCO2DIV_0) /*!< MCO divided by 12 */ +#define LL_RCC_MCO2_DIV_13 (RCC_MCO2CFGR_MCO2DIV_3 | RCC_MCO2CFGR_MCO2DIV_2) /*!< MCO divided by 13 */ +#define LL_RCC_MCO2_DIV_14 (RCC_MCO2CFGR_MCO2DIV_3 | RCC_MCO2CFGR_MCO2DIV_2 | RCC_MCO2CFGR_MCO2DIV_0) /*!< MCO divided by 14 */ +#define LL_RCC_MCO2_DIV_15 (RCC_MCO2CFGR_MCO2DIV_3 | RCC_MCO2CFGR_MCO2DIV_2 | RCC_MCO2CFGR_MCO2DIV_1) /*!< MCO divided by 15 */ +#define LL_RCC_MCO2_DIV_16 (RCC_MCO2CFGR_MCO2DIV_3 | RCC_MCO2CFGR_MCO2DIV_2 | RCC_MCO2CFGR_MCO2DIV_1 | RCC_MCO2CFGR_MCO2DIV_0) /*!< MCO divided by 16 */ /** * @} */ @@ -363,70 +363,70 @@ typedef struct /** @defgroup RCC_LL_EC_RTC_HSEDIV HSE prescaler for RTC clock * @{ */ -#define LL_RCC_RTC_HSE_DIV_1 RCC_RTCDIVR_RTCDIV_1 -#define LL_RCC_RTC_HSE_DIV_2 RCC_RTCDIVR_RTCDIV_2 -#define LL_RCC_RTC_HSE_DIV_3 RCC_RTCDIVR_RTCDIV_3 -#define LL_RCC_RTC_HSE_DIV_4 RCC_RTCDIVR_RTCDIV_4 -#define LL_RCC_RTC_HSE_DIV_5 RCC_RTCDIVR_RTCDIV_5 -#define LL_RCC_RTC_HSE_DIV_6 RCC_RTCDIVR_RTCDIV_6 -#define LL_RCC_RTC_HSE_DIV_7 RCC_RTCDIVR_RTCDIV_7 -#define LL_RCC_RTC_HSE_DIV_8 RCC_RTCDIVR_RTCDIV_8 -#define LL_RCC_RTC_HSE_DIV_9 RCC_RTCDIVR_RTCDIV_9 -#define LL_RCC_RTC_HSE_DIV_10 RCC_RTCDIVR_RTCDIV_10 -#define LL_RCC_RTC_HSE_DIV_11 RCC_RTCDIVR_RTCDIV_11 -#define LL_RCC_RTC_HSE_DIV_12 RCC_RTCDIVR_RTCDIV_12 -#define LL_RCC_RTC_HSE_DIV_13 RCC_RTCDIVR_RTCDIV_13 -#define LL_RCC_RTC_HSE_DIV_14 RCC_RTCDIVR_RTCDIV_14 -#define LL_RCC_RTC_HSE_DIV_15 RCC_RTCDIVR_RTCDIV_15 -#define LL_RCC_RTC_HSE_DIV_16 RCC_RTCDIVR_RTCDIV_16 -#define LL_RCC_RTC_HSE_DIV_17 RCC_RTCDIVR_RTCDIV_17 -#define LL_RCC_RTC_HSE_DIV_18 RCC_RTCDIVR_RTCDIV_18 -#define LL_RCC_RTC_HSE_DIV_19 RCC_RTCDIVR_RTCDIV_19 -#define LL_RCC_RTC_HSE_DIV_20 RCC_RTCDIVR_RTCDIV_20 -#define LL_RCC_RTC_HSE_DIV_21 RCC_RTCDIVR_RTCDIV_21 -#define LL_RCC_RTC_HSE_DIV_22 RCC_RTCDIVR_RTCDIV_22 -#define LL_RCC_RTC_HSE_DIV_23 RCC_RTCDIVR_RTCDIV_23 -#define LL_RCC_RTC_HSE_DIV_24 RCC_RTCDIVR_RTCDIV_24 -#define LL_RCC_RTC_HSE_DIV_25 RCC_RTCDIVR_RTCDIV_25 -#define LL_RCC_RTC_HSE_DIV_26 RCC_RTCDIVR_RTCDIV_26 -#define LL_RCC_RTC_HSE_DIV_27 RCC_RTCDIVR_RTCDIV_27 -#define LL_RCC_RTC_HSE_DIV_28 RCC_RTCDIVR_RTCDIV_28 -#define LL_RCC_RTC_HSE_DIV_29 RCC_RTCDIVR_RTCDIV_29 -#define LL_RCC_RTC_HSE_DIV_30 RCC_RTCDIVR_RTCDIV_30 -#define LL_RCC_RTC_HSE_DIV_31 RCC_RTCDIVR_RTCDIV_31 -#define LL_RCC_RTC_HSE_DIV_32 RCC_RTCDIVR_RTCDIV_32 -#define LL_RCC_RTC_HSE_DIV_33 RCC_RTCDIVR_RTCDIV_33 -#define LL_RCC_RTC_HSE_DIV_34 RCC_RTCDIVR_RTCDIV_34 -#define LL_RCC_RTC_HSE_DIV_35 RCC_RTCDIVR_RTCDIV_35 -#define LL_RCC_RTC_HSE_DIV_36 RCC_RTCDIVR_RTCDIV_36 -#define LL_RCC_RTC_HSE_DIV_37 RCC_RTCDIVR_RTCDIV_37 -#define LL_RCC_RTC_HSE_DIV_38 RCC_RTCDIVR_RTCDIV_38 -#define LL_RCC_RTC_HSE_DIV_39 RCC_RTCDIVR_RTCDIV_39 -#define LL_RCC_RTC_HSE_DIV_40 RCC_RTCDIVR_RTCDIV_40 -#define LL_RCC_RTC_HSE_DIV_41 RCC_RTCDIVR_RTCDIV_41 -#define LL_RCC_RTC_HSE_DIV_42 RCC_RTCDIVR_RTCDIV_42 -#define LL_RCC_RTC_HSE_DIV_43 RCC_RTCDIVR_RTCDIV_43 -#define LL_RCC_RTC_HSE_DIV_44 RCC_RTCDIVR_RTCDIV_44 -#define LL_RCC_RTC_HSE_DIV_45 RCC_RTCDIVR_RTCDIV_45 -#define LL_RCC_RTC_HSE_DIV_46 RCC_RTCDIVR_RTCDIV_46 -#define LL_RCC_RTC_HSE_DIV_47 RCC_RTCDIVR_RTCDIV_47 -#define LL_RCC_RTC_HSE_DIV_48 RCC_RTCDIVR_RTCDIV_48 -#define LL_RCC_RTC_HSE_DIV_49 RCC_RTCDIVR_RTCDIV_49 -#define LL_RCC_RTC_HSE_DIV_50 RCC_RTCDIVR_RTCDIV_50 -#define LL_RCC_RTC_HSE_DIV_51 RCC_RTCDIVR_RTCDIV_51 -#define LL_RCC_RTC_HSE_DIV_52 RCC_RTCDIVR_RTCDIV_52 -#define LL_RCC_RTC_HSE_DIV_53 RCC_RTCDIVR_RTCDIV_53 -#define LL_RCC_RTC_HSE_DIV_54 RCC_RTCDIVR_RTCDIV_54 -#define LL_RCC_RTC_HSE_DIV_55 RCC_RTCDIVR_RTCDIV_55 -#define LL_RCC_RTC_HSE_DIV_56 RCC_RTCDIVR_RTCDIV_56 -#define LL_RCC_RTC_HSE_DIV_57 RCC_RTCDIVR_RTCDIV_57 -#define LL_RCC_RTC_HSE_DIV_58 RCC_RTCDIVR_RTCDIV_58 -#define LL_RCC_RTC_HSE_DIV_59 RCC_RTCDIVR_RTCDIV_59 -#define LL_RCC_RTC_HSE_DIV_60 RCC_RTCDIVR_RTCDIV_60 -#define LL_RCC_RTC_HSE_DIV_61 RCC_RTCDIVR_RTCDIV_61 -#define LL_RCC_RTC_HSE_DIV_62 RCC_RTCDIVR_RTCDIV_62 -#define LL_RCC_RTC_HSE_DIV_63 RCC_RTCDIVR_RTCDIV_63 -#define LL_RCC_RTC_HSE_DIV_64 RCC_RTCDIVR_RTCDIV_64 +#define LL_RCC_RTC_HSE_DIV_1 0U +#define LL_RCC_RTC_HSE_DIV_2 RCC_RTCDIVR_RTCDIV_0 +#define LL_RCC_RTC_HSE_DIV_3 RCC_RTCDIVR_RTCDIV_1 +#define LL_RCC_RTC_HSE_DIV_4 (RCC_RTCDIVR_RTCDIV_1 | RCC_RTCDIVR_RTCDIV_0) +#define LL_RCC_RTC_HSE_DIV_5 RCC_RTCDIVR_RTCDIV_2 +#define LL_RCC_RTC_HSE_DIV_6 (RCC_RTCDIVR_RTCDIV_2 | RCC_RTCDIVR_RTCDIV_0) +#define LL_RCC_RTC_HSE_DIV_7 (RCC_RTCDIVR_RTCDIV_2 | RCC_RTCDIVR_RTCDIV_1) +#define LL_RCC_RTC_HSE_DIV_8 (RCC_RTCDIVR_RTCDIV_2 | RCC_RTCDIVR_RTCDIV_1 | RCC_RTCDIVR_RTCDIV_0) +#define LL_RCC_RTC_HSE_DIV_9 RCC_RTCDIVR_RTCDIV_3 +#define LL_RCC_RTC_HSE_DIV_10 (RCC_RTCDIVR_RTCDIV_3 | RCC_RTCDIVR_RTCDIV_0) +#define LL_RCC_RTC_HSE_DIV_11 (RCC_RTCDIVR_RTCDIV_3 | RCC_RTCDIVR_RTCDIV_1) +#define LL_RCC_RTC_HSE_DIV_12 (RCC_RTCDIVR_RTCDIV_3 | RCC_RTCDIVR_RTCDIV_1 | RCC_RTCDIVR_RTCDIV_0) +#define LL_RCC_RTC_HSE_DIV_13 (RCC_RTCDIVR_RTCDIV_3 | RCC_RTCDIVR_RTCDIV_2) +#define LL_RCC_RTC_HSE_DIV_14 (RCC_RTCDIVR_RTCDIV_3 | RCC_RTCDIVR_RTCDIV_2 | RCC_RTCDIVR_RTCDIV_0) +#define LL_RCC_RTC_HSE_DIV_15 (RCC_RTCDIVR_RTCDIV_3 | RCC_RTCDIVR_RTCDIV_2 | RCC_RTCDIVR_RTCDIV_1) +#define LL_RCC_RTC_HSE_DIV_16 (RCC_RTCDIVR_RTCDIV_3 | RCC_RTCDIVR_RTCDIV_2 | RCC_RTCDIVR_RTCDIV_1 | RCC_RTCDIVR_RTCDIV_0) +#define LL_RCC_RTC_HSE_DIV_17 RCC_RTCDIVR_RTCDIV_4 +#define LL_RCC_RTC_HSE_DIV_18 (RCC_RTCDIVR_RTCDIV_4 | RCC_RTCDIVR_RTCDIV_0) +#define LL_RCC_RTC_HSE_DIV_19 (RCC_RTCDIVR_RTCDIV_4 | RCC_RTCDIVR_RTCDIV_1) +#define LL_RCC_RTC_HSE_DIV_20 (RCC_RTCDIVR_RTCDIV_4 | RCC_RTCDIVR_RTCDIV_1 | RCC_RTCDIVR_RTCDIV_0) +#define LL_RCC_RTC_HSE_DIV_21 (RCC_RTCDIVR_RTCDIV_4 | RCC_RTCDIVR_RTCDIV_2) +#define LL_RCC_RTC_HSE_DIV_22 (RCC_RTCDIVR_RTCDIV_4 | RCC_RTCDIVR_RTCDIV_2 | RCC_RTCDIVR_RTCDIV_0) +#define LL_RCC_RTC_HSE_DIV_23 (RCC_RTCDIVR_RTCDIV_4 | RCC_RTCDIVR_RTCDIV_2 | RCC_RTCDIVR_RTCDIV_1) +#define LL_RCC_RTC_HSE_DIV_24 (RCC_RTCDIVR_RTCDIV_4 | RCC_RTCDIVR_RTCDIV_2 | RCC_RTCDIVR_RTCDIV_1 | RCC_RTCDIVR_RTCDIV_0) +#define LL_RCC_RTC_HSE_DIV_25 (RCC_RTCDIVR_RTCDIV_4 | RCC_RTCDIVR_RTCDIV_3) +#define LL_RCC_RTC_HSE_DIV_26 (RCC_RTCDIVR_RTCDIV_4 | RCC_RTCDIVR_RTCDIV_3 | RCC_RTCDIVR_RTCDIV_0) +#define LL_RCC_RTC_HSE_DIV_27 (RCC_RTCDIVR_RTCDIV_4 | RCC_RTCDIVR_RTCDIV_3 | RCC_RTCDIVR_RTCDIV_1) +#define LL_RCC_RTC_HSE_DIV_28 (RCC_RTCDIVR_RTCDIV_4 | RCC_RTCDIVR_RTCDIV_3 | RCC_RTCDIVR_RTCDIV_1 | RCC_RTCDIVR_RTCDIV_0) +#define LL_RCC_RTC_HSE_DIV_29 (RCC_RTCDIVR_RTCDIV_4 | RCC_RTCDIVR_RTCDIV_3 | RCC_RTCDIVR_RTCDIV_2) +#define LL_RCC_RTC_HSE_DIV_30 (RCC_RTCDIVR_RTCDIV_4 | RCC_RTCDIVR_RTCDIV_3 | RCC_RTCDIVR_RTCDIV_2 | RCC_RTCDIVR_RTCDIV_0) +#define LL_RCC_RTC_HSE_DIV_31 (RCC_RTCDIVR_RTCDIV_4 | RCC_RTCDIVR_RTCDIV_3 | RCC_RTCDIVR_RTCDIV_2 | RCC_RTCDIVR_RTCDIV_1) +#define LL_RCC_RTC_HSE_DIV_32 (RCC_RTCDIVR_RTCDIV_4 | RCC_RTCDIVR_RTCDIV_3 | RCC_RTCDIVR_RTCDIV_2 | RCC_RTCDIVR_RTCDIV_1 | RCC_RTCDIVR_RTCDIV_0) +#define LL_RCC_RTC_HSE_DIV_33 RCC_RTCDIVR_RTCDIV_5 +#define LL_RCC_RTC_HSE_DIV_34 (RCC_RTCDIVR_RTCDIV_5 | RCC_RTCDIVR_RTCDIV_0) +#define LL_RCC_RTC_HSE_DIV_35 (RCC_RTCDIVR_RTCDIV_5 | RCC_RTCDIVR_RTCDIV_1) +#define LL_RCC_RTC_HSE_DIV_36 (RCC_RTCDIVR_RTCDIV_5 | RCC_RTCDIVR_RTCDIV_1 | RCC_RTCDIVR_RTCDIV_0) +#define LL_RCC_RTC_HSE_DIV_37 (RCC_RTCDIVR_RTCDIV_5 | RCC_RTCDIVR_RTCDIV_2) +#define LL_RCC_RTC_HSE_DIV_38 (RCC_RTCDIVR_RTCDIV_5 | RCC_RTCDIVR_RTCDIV_2 | RCC_RTCDIVR_RTCDIV_0) +#define LL_RCC_RTC_HSE_DIV_39 (RCC_RTCDIVR_RTCDIV_5 | RCC_RTCDIVR_RTCDIV_2 | RCC_RTCDIVR_RTCDIV_1) +#define LL_RCC_RTC_HSE_DIV_40 (RCC_RTCDIVR_RTCDIV_5 | RCC_RTCDIVR_RTCDIV_2 | RCC_RTCDIVR_RTCDIV_1 | RCC_RTCDIVR_RTCDIV_0) +#define LL_RCC_RTC_HSE_DIV_41 (RCC_RTCDIVR_RTCDIV_5 | RCC_RTCDIVR_RTCDIV_3) +#define LL_RCC_RTC_HSE_DIV_42 (RCC_RTCDIVR_RTCDIV_5 | RCC_RTCDIVR_RTCDIV_3 | RCC_RTCDIVR_RTCDIV_0) +#define LL_RCC_RTC_HSE_DIV_43 (RCC_RTCDIVR_RTCDIV_5 | RCC_RTCDIVR_RTCDIV_3 | RCC_RTCDIVR_RTCDIV_1) +#define LL_RCC_RTC_HSE_DIV_44 (RCC_RTCDIVR_RTCDIV_5 | RCC_RTCDIVR_RTCDIV_3 | RCC_RTCDIVR_RTCDIV_1 | RCC_RTCDIVR_RTCDIV_0) +#define LL_RCC_RTC_HSE_DIV_45 (RCC_RTCDIVR_RTCDIV_5 | RCC_RTCDIVR_RTCDIV_3 | RCC_RTCDIVR_RTCDIV_2) +#define LL_RCC_RTC_HSE_DIV_46 (RCC_RTCDIVR_RTCDIV_5 | RCC_RTCDIVR_RTCDIV_3 | RCC_RTCDIVR_RTCDIV_2 | RCC_RTCDIVR_RTCDIV_0) +#define LL_RCC_RTC_HSE_DIV_47 (RCC_RTCDIVR_RTCDIV_5 | RCC_RTCDIVR_RTCDIV_3 | RCC_RTCDIVR_RTCDIV_2 | RCC_RTCDIVR_RTCDIV_1) +#define LL_RCC_RTC_HSE_DIV_48 (RCC_RTCDIVR_RTCDIV_5 | RCC_RTCDIVR_RTCDIV_3 | RCC_RTCDIVR_RTCDIV_2 | RCC_RTCDIVR_RTCDIV_1 | RCC_RTCDIVR_RTCDIV_0) +#define LL_RCC_RTC_HSE_DIV_49 (RCC_RTCDIVR_RTCDIV_5 | RCC_RTCDIVR_RTCDIV_4) +#define LL_RCC_RTC_HSE_DIV_50 (RCC_RTCDIVR_RTCDIV_5 | RCC_RTCDIVR_RTCDIV_4 | RCC_RTCDIVR_RTCDIV_0) +#define LL_RCC_RTC_HSE_DIV_51 (RCC_RTCDIVR_RTCDIV_5 | RCC_RTCDIVR_RTCDIV_4 | RCC_RTCDIVR_RTCDIV_1) +#define LL_RCC_RTC_HSE_DIV_52 (RCC_RTCDIVR_RTCDIV_5 | RCC_RTCDIVR_RTCDIV_4 | RCC_RTCDIVR_RTCDIV_1 | RCC_RTCDIVR_RTCDIV_0) +#define LL_RCC_RTC_HSE_DIV_53 (RCC_RTCDIVR_RTCDIV_5 | RCC_RTCDIVR_RTCDIV_4 | RCC_RTCDIVR_RTCDIV_2) +#define LL_RCC_RTC_HSE_DIV_54 (RCC_RTCDIVR_RTCDIV_5 | RCC_RTCDIVR_RTCDIV_4 | RCC_RTCDIVR_RTCDIV_2 | RCC_RTCDIVR_RTCDIV_0) +#define LL_RCC_RTC_HSE_DIV_55 (RCC_RTCDIVR_RTCDIV_5 | RCC_RTCDIVR_RTCDIV_4 | RCC_RTCDIVR_RTCDIV_2 | RCC_RTCDIVR_RTCDIV_1) +#define LL_RCC_RTC_HSE_DIV_56 (RCC_RTCDIVR_RTCDIV_5 | RCC_RTCDIVR_RTCDIV_4 | RCC_RTCDIVR_RTCDIV_2 | RCC_RTCDIVR_RTCDIV_1 | RCC_RTCDIVR_RTCDIV_0) +#define LL_RCC_RTC_HSE_DIV_57 (RCC_RTCDIVR_RTCDIV_5 | RCC_RTCDIVR_RTCDIV_4 | RCC_RTCDIVR_RTCDIV_3) +#define LL_RCC_RTC_HSE_DIV_58 (RCC_RTCDIVR_RTCDIV_5 | RCC_RTCDIVR_RTCDIV_4 | RCC_RTCDIVR_RTCDIV_3 | RCC_RTCDIVR_RTCDIV_0) +#define LL_RCC_RTC_HSE_DIV_59 (RCC_RTCDIVR_RTCDIV_5 | RCC_RTCDIVR_RTCDIV_4 | RCC_RTCDIVR_RTCDIV_3 | RCC_RTCDIVR_RTCDIV_1) +#define LL_RCC_RTC_HSE_DIV_60 (RCC_RTCDIVR_RTCDIV_5 | RCC_RTCDIVR_RTCDIV_4 | RCC_RTCDIVR_RTCDIV_3 | RCC_RTCDIVR_RTCDIV_1 | RCC_RTCDIVR_RTCDIV_0) +#define LL_RCC_RTC_HSE_DIV_61 (RCC_RTCDIVR_RTCDIV_5 | RCC_RTCDIVR_RTCDIV_4 | RCC_RTCDIVR_RTCDIV_3 | RCC_RTCDIVR_RTCDIV_2) +#define LL_RCC_RTC_HSE_DIV_62 (RCC_RTCDIVR_RTCDIV_5 | RCC_RTCDIVR_RTCDIV_4 | RCC_RTCDIVR_RTCDIV_3 | RCC_RTCDIVR_RTCDIV_2 | RCC_RTCDIVR_RTCDIV_0) +#define LL_RCC_RTC_HSE_DIV_63 (RCC_RTCDIVR_RTCDIV_5 | RCC_RTCDIVR_RTCDIV_4 | RCC_RTCDIVR_RTCDIV_3 | RCC_RTCDIVR_RTCDIV_2 | RCC_RTCDIVR_RTCDIV_1) +#define LL_RCC_RTC_HSE_DIV_64 (RCC_RTCDIVR_RTCDIV_5 | RCC_RTCDIVR_RTCDIV_4 | RCC_RTCDIVR_RTCDIV_3 | RCC_RTCDIVR_RTCDIV_2 | RCC_RTCDIVR_RTCDIV_1 | RCC_RTCDIVR_RTCDIV_0) /** * @} */ @@ -445,10 +445,10 @@ typedef struct /** @defgroup RCC_LL_EC_MPU_CLKSOURCE_STATUS MPU clock switch status * @{ */ -#define LL_RCC_MPU_CLKSOURCE_STATUS_HSI RCC_MPCKSELR_MPUSRC_0 /*!< HSI used as MPU clock */ -#define LL_RCC_MPU_CLKSOURCE_STATUS_HSE RCC_MPCKSELR_MPUSRC_1 /*!< HSE used as MPU clock */ -#define LL_RCC_MPU_CLKSOURCE_STATUS_PLL1 RCC_MPCKSELR_MPUSRC_2 /*!< PLL1 used as MPU clock */ -#define LL_RCC_MPU_CLKSOURCE_STATUS_MPUDIV RCC_MPCKSELR_MPUSRC_3 /*!< MPUDIV used as MPU clock */ +#define LL_RCC_MPU_CLKSOURCE_STATUS_HSI 0U /*!< HSI used as MPU clock */ +#define LL_RCC_MPU_CLKSOURCE_STATUS_HSE RCC_MPCKSELR_MPUSRC_0 /*!< HSE used as MPU clock */ +#define LL_RCC_MPU_CLKSOURCE_STATUS_PLL1 RCC_MPCKSELR_MPUSRC_1 /*!< PLL1 used as MPU clock */ +#define LL_RCC_MPU_CLKSOURCE_STATUS_MPUDIV (RCC_MPCKSELR_MPUSRC_1 | RCC_MPCKSELR_MPUSRC_0) /*!< MPUDIV used as MPU clock */ /** * @} */ @@ -456,11 +456,11 @@ typedef struct /** @defgroup RCC_LL_EC_MPU_DIV MPUDIV prescaler * @{ */ -#define LL_RCC_MPU_DIV_OFF RCC_MPCKDIVR_MPUDIV_0 /*!< MPU div is disabled, no clock generated */ -#define LL_RCC_MPU_DIV_2 RCC_MPCKDIVR_MPUDIV_1 /*!< MPUSS is equal to pll1_p_ck divided by 2 */ -#define LL_RCC_MPU_DIV_4 RCC_MPCKDIVR_MPUDIV_2 /*!< MPUSS is equal to pll1_p_ck divided by 4 */ -#define LL_RCC_MPU_DIV_8 RCC_MPCKDIVR_MPUDIV_3 /*!< MPUSS is equal to pll1_p_ck divided by 8 */ -#define LL_RCC_MPU_DIV_16 RCC_MPCKDIVR_MPUDIV_4 /*!< MPUSS is equal to pll1_p_ck divided by 16 */ +#define LL_RCC_MPU_DIV_OFF 0U /*!< MPU div is disabled, no clock generated */ +#define LL_RCC_MPU_DIV_2 RCC_MPCKDIVR_MPUDIV_0 /*!< MPUSS is equal to pll1_p_ck divided by 2 */ +#define LL_RCC_MPU_DIV_4 RCC_MPCKDIVR_MPUDIV_1 /*!< MPUSS is equal to pll1_p_ck divided by 4 */ +#define LL_RCC_MPU_DIV_8 (RCC_MPCKDIVR_MPUDIV_1 | RCC_MPCKDIVR_MPUDIV_0) /*!< MPUSS is equal to pll1_p_ck divided by 8 */ +#define LL_RCC_MPU_DIV_16 RCC_MPCKDIVR_MPUDIV_2 /*!< MPUSS is equal to pll1_p_ck divided by 16 */ /** * @} */ @@ -490,10 +490,10 @@ typedef struct /** @defgroup RCC_LL_EC_AXI_DIV AXI, AHB5 and AHB6 prescaler * @{ */ -#define LL_RCC_AXI_DIV_1 RCC_AXIDIVR_AXIDIV_0 /*!< AXISS not divided */ -#define LL_RCC_AXI_DIV_2 RCC_AXIDIVR_AXIDIV_1 /*!< AXISS divided by 2 */ -#define LL_RCC_AXI_DIV_3 RCC_AXIDIVR_AXIDIV_2 /*!< AXISS divided by 3 */ -#define LL_RCC_AXI_DIV_4 RCC_AXIDIVR_AXIDIV_3 /*!< AXISS divided by 4 */ +#define LL_RCC_AXI_DIV_1 0U /*!< AXISS not divided */ +#define LL_RCC_AXI_DIV_2 RCC_AXIDIVR_AXIDIV_0 /*!< AXISS divided by 2 */ +#define LL_RCC_AXI_DIV_3 RCC_AXIDIVR_AXIDIV_1 /*!< AXISS divided by 3 */ +#define LL_RCC_AXI_DIV_4 RCC_AXIDIVR_AXIDIV_2 /*!< AXISS divided by 4 */ /** * @} */ @@ -512,10 +512,10 @@ typedef struct /** @defgroup RCC_LL_EC_MCUSS_CLKSOURCE_STATUS MCUSS clock switch status * @{ */ -#define LL_RCC_MCUSS_CLKSOURCE_STATUS_HSI RCC_MSSCKSELR_MCUSSRC_0 /*!< HSI used as MCUSS clock */ -#define LL_RCC_MCUSS_CLKSOURCE_STATUS_HSE RCC_MSSCKSELR_MCUSSRC_1 /*!< HSE used as MCUSS clock */ -#define LL_RCC_MCUSS_CLKSOURCE_STATUS_CSI RCC_MSSCKSELR_MCUSSRC_2 /*!< CSI used as MCUSS clock */ -#define LL_RCC_MCUSS_CLKSOURCE_STATUS_PLL3 RCC_MSSCKSELR_MCUSSRC_3 /*!< PLL3 used as MCUSS clock */ +#define LL_RCC_MCUSS_CLKSOURCE_STATUS_HSI 0U /*!< HSI used as MCUSS clock */ +#define LL_RCC_MCUSS_CLKSOURCE_STATUS_HSE RCC_MSSCKSELR_MCUSSRC_0 /*!< HSE used as MCUSS clock */ +#define LL_RCC_MCUSS_CLKSOURCE_STATUS_CSI RCC_MSSCKSELR_MCUSSRC_1 /*!< CSI used as MCUSS clock */ +#define LL_RCC_MCUSS_CLKSOURCE_STATUS_PLL3 (RCC_MSSCKSELR_MCUSSRC_1 | RCC_MSSCKSELR_MCUSSRC_0) /*!< PLL3 used as MCUSS clock */ /** * @} */ @@ -523,16 +523,16 @@ typedef struct /** @defgroup RCC_LL_EC_MCU_DIV MCUDIV prescaler * @{ */ -#define LL_RCC_MCU_DIV_1 RCC_MCUDIVR_MCUDIV_0 /*!< MCUSS not divided */ -#define LL_RCC_MCU_DIV_2 RCC_MCUDIVR_MCUDIV_1 /*!< MCUSS divided by 2 */ -#define LL_RCC_MCU_DIV_4 RCC_MCUDIVR_MCUDIV_2 /*!< MCUSS divided by 4 */ -#define LL_RCC_MCU_DIV_8 RCC_MCUDIVR_MCUDIV_3 /*!< MCUSS divided by 8 */ -#define LL_RCC_MCU_DIV_16 RCC_MCUDIVR_MCUDIV_4 /*!< MCUSS divided by 16 */ -#define LL_RCC_MCU_DIV_32 RCC_MCUDIVR_MCUDIV_5 /*!< MCUSS divided by 32 */ -#define LL_RCC_MCU_DIV_64 RCC_MCUDIVR_MCUDIV_6 /*!< MCUSS divided by 64 */ -#define LL_RCC_MCU_DIV_128 RCC_MCUDIVR_MCUDIV_7 /*!< MCUSS divided by 128 */ -#define LL_RCC_MCU_DIV_256 RCC_MCUDIVR_MCUDIV_8 /*!< MCUSS divided by 256 */ -#define LL_RCC_MCU_DIV_512 RCC_MCUDIVR_MCUDIV_9 /*!< MCUSS divided by 512 */ +#define LL_RCC_MCU_DIV_1 0U /*!< MCUSS not divided */ +#define LL_RCC_MCU_DIV_2 RCC_MCUDIVR_MCUDIV_0 /*!< MCUSS divided by 2 */ +#define LL_RCC_MCU_DIV_4 RCC_MCUDIVR_MCUDIV_1 /*!< MCUSS divided by 4 */ +#define LL_RCC_MCU_DIV_8 (RCC_MCUDIVR_MCUDIV_1 | RCC_MCUDIVR_MCUDIV_0) /*!< MCUSS divided by 8 */ +#define LL_RCC_MCU_DIV_16 RCC_MCUDIVR_MCUDIV_2 /*!< MCUSS divided by 16 */ +#define LL_RCC_MCU_DIV_32 (RCC_MCUDIVR_MCUDIV_2 | RCC_MCUDIVR_MCUDIV_0) /*!< MCUSS divided by 32 */ +#define LL_RCC_MCU_DIV_64 (RCC_MCUDIVR_MCUDIV_2 | RCC_MCUDIVR_MCUDIV_1) /*!< MCUSS divided by 64 */ +#define LL_RCC_MCU_DIV_128 (RCC_MCUDIVR_MCUDIV_2 | RCC_MCUDIVR_MCUDIV_1 | RCC_MCUDIVR_MCUDIV_0) /*!< MCUSS divided by 128 */ +#define LL_RCC_MCU_DIV_256 RCC_MCUDIVR_MCUDIV_3 /*!< MCUSS divided by 256 */ +#define LL_RCC_MCU_DIV_512 (RCC_MCUDIVR_MCUDIV_3 | RCC_MCUDIVR_MCUDIV_0) /*!< MCUSS divided by 512 */ /** * @} */ @@ -600,10 +600,10 @@ typedef struct /** @defgroup RCC_LL_EC_LSEDRIVE LSE oscillator drive capability * @{ */ -#define LL_RCC_LSEDRIVE_LOW RCC_BDCR_LSEDRV_0 /*!< Xtal mode lower driving capability */ -#define LL_RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_1 /*!< Xtal mode medium low driving capability */ -#define LL_RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_2 /*!< Xtal mode medium high driving capability */ -#define LL_RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV_3 /*!< Xtal mode higher driving capability */ +#define LL_RCC_LSEDRIVE_LOW 0U /*!< Xtal mode lower driving capability */ +#define LL_RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0 /*!< Xtal mode medium low driving capability */ +#define LL_RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1 /*!< Xtal mode medium high driving capability */ +#define LL_RCC_LSEDRIVE_HIGH (RCC_BDCR_LSEDRV_1 | RCC_BDCR_LSEDRV_0) /*!< Xtal mode higher driving capability */ /** * @} */ diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_ll_spi.h b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_ll_spi.h index 82e6883237..ead70bfbde 100644 --- a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_ll_spi.h +++ b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_ll_spi.h @@ -2412,7 +2412,27 @@ __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->CFG1, SPI_CFG1_TXDMAEN) == (SPI_CFG1_TXDMAEN)) ? 1UL : 0UL); } +/** + * @brief Get the data register address used for DMA transfer + * @rmtoll TXDR TXDR LL_SPI_DMA_GetTxRegAddr + * @param SPIx SPI Instance + * @retval Address of data register + */ +__STATIC_INLINE uint32_t LL_SPI_DMA_GetTxRegAddr(SPI_TypeDef *SPIx) +{ + return (uint32_t) &(SPIx->TXDR); +} +/** + * @brief Get the data register address used for DMA transfer + * @rmtoll RXDR RXDR LL_SPI_DMA_GetRxRegAddr + * @param SPIx SPI Instance + * @retval Address of data register + */ +__STATIC_INLINE uint32_t LL_SPI_DMA_GetRxRegAddr(SPI_TypeDef *SPIx) +{ + return (uint32_t) &(SPIx->RXDR); +} /** * @} */ @@ -2440,7 +2460,12 @@ __STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx) */ __STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx) { - return (uint16_t)(READ_REG(SPIx->RXDR)); +#if defined (__GNUC__) + __IO uint16_t *spirxdr = (__IO uint16_t *)(&(SPIx->RXDR)); + return (*spirxdr); +#else + return (*((__IO uint16_t *)&SPIx->RXDR)); +#endif /* __GNUC__ */ } /** @@ -2479,7 +2504,7 @@ __STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData) __IO uint16_t *spitxdr = ((__IO uint16_t *)&SPIx->TXDR); *spitxdr = TxData; #else - SPIx->TXDR = TxData; + *((__IO uint16_t *)&SPIx->TXDR) = TxData; #endif /* __GNUC__ */ } @@ -3711,6 +3736,7 @@ __STATIC_INLINE void LL_I2S_TransmitData32(SPI_TypeDef *SPIx, uint32_t TxData) LL_SPI_TransmitData32(SPIx, TxData); } + /** * @} */ diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_ll_tim.h b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_ll_tim.h index 606d189c70..6f21e52dc5 100644 --- a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_ll_tim.h +++ b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_ll_tim.h @@ -600,8 +600,8 @@ typedef struct /** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode * @{ */ -#define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter is not stopped at update event */ -#define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter stops counting at the next update event */ +#define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */ +#define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */ /** * @} */ @@ -609,10 +609,10 @@ typedef struct /** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode * @{ */ -#define LL_TIM_COUNTERMODE_UP 0x00000000U /*!GTPR, (uint16_t)USART_GTPR_PSC, (uint16_t)PrescalerValue); + MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, (uint16_t)PrescalerValue); } /** @@ -2240,7 +2240,7 @@ __STATIC_INLINE uint32_t LL_USART_GetSmartcardAutoRetryCount(USART_TypeDef *USAR */ __STATIC_INLINE void LL_USART_SetSmartcardPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue) { - MODIFY_REG(USARTx->GTPR, (uint16_t)USART_GTPR_PSC, (uint16_t)PrescalerValue); + MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, (uint16_t)PrescalerValue); } /** @@ -2269,7 +2269,7 @@ __STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_SetSmartcardGuardTime(USART_TypeDef *USARTx, uint32_t GuardTime) { - MODIFY_REG(USARTx->GTPR, (uint16_t)USART_GTPR_GT, (uint16_t)(GuardTime << USART_GTPR_GT_Pos)); + MODIFY_REG(USARTx->GTPR, USART_GTPR_GT, (uint16_t)(GuardTime << USART_GTPR_GT_Pos)); } /** diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_ll_utils.h b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_ll_utils.h index b6e3940a80..bd9ac3e6fb 100644 --- a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_ll_utils.h +++ b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_ll_utils.h @@ -395,4 +395,3 @@ ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, #endif /* STM32MP1xx_LL_UTILS_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Release_Notes.html b/system/Drivers/STM32MP1xx_HAL_Driver/Release_Notes.html index e304ed8032..30af4e68b1 100644 --- a/system/Drivers/STM32MP1xx_HAL_Driver/Release_Notes.html +++ b/system/Drivers/STM32MP1xx_HAL_Driver/Release_Notes.html @@ -40,7 +40,7 @@

Purpose

Update History

- +

Main Changes

    @@ -51,6 +51,77 @@

    Contents

  • General updates to fix known defects and enhancements implementation
  • Major update of drivers for STM32MP15xx devices:
      +
    • HAL: +
        +
      • Implement HAL_GetUIDw{0,1,2} (New API)
        • +
      • Add ALIGN_32BYTES definitions
        • +
      • +
    • ADC (No API change) +
        +
      • Fix loop index computation at low frequency
        • +
      • Fix HAL_GetTick() timeout vulnerability
        • +
      • Fix HAL_ADC_MspDeInit: disable clock should not reset all ADCs
        • +
      • Update function parameters pointers with prefix “p”
        • +
      • +
    • SPI +
        +
      • Alignment with other STM32 families (No API Change)
        • +
      • +
    • TIM +
        +
      • LL : ONEPULSEMODE defines description are inverted
        • +
      • LL : COUNTERMODE defines are inverted for TIM_CR1_CMS
        • +
      • +
    • CRC, DMA and USART +
        +
      • Alignment with other STM32 families (No API Change)
        • +
      • +
    • EXTI (No API change) +
        +
      • Fix some MISRA warnings
        • +
      • Optimize Get Config API
        • +
      • +
    • SMBUS : Alignment with other STM32 families +
        +
      • SMBUS Extended files support (API Change)
        • +
      • +
    • QSPI (No API change) +
        +
      • Fix typo comments
        • +
      • Fix error for HAL_QSPI_Abort function in memory-mapped mode.
        • +
      • +
    • RCC (No API change) +
        +
      • (HAL) : Fix pllxvco calculation
        • +
      • (LL) : Fix compilation issue ( some missing register alignement with CMSIS Device)
        • +
      • +
    • +
+

Known Limitations

+
    +
  • N/A
    • +
+

Supported Devices

+
    +
  • The drivers provided support the following devices : +
      +
    • STM32MP157Cxx, STM32MP157Axx, STM32MP157Dxx, STM32MP157Fxx
      • +
    • STM32MP153Cxx, STM32MP153Axx, STM32MP153Dxx, STM32MP153Fxx
      • +
    • STM32MP151Cxx, STM32MP151Axx, STM32MP151Dxx, STM32MP151Fxx
      • +
    • +
+
+
+
+ +
+

Main Changes

+

Maintenance release of HAL and LL drivers for STM32MP15xx devices

+

Contents

+
    +
  • General updates to fix known defects and enhancements implementation
    • +
  • Major update of drivers for STM32MP15xx devices: +
    • All HAL and LL Drivers
      • Update the way to declare licenses in Cube
        • @@ -80,11 +151,11 @@

        Contents

-

Known Limitations

+

Known Limitations

    -
  • N/A
    • +
  • None
-

Supported Devices

+

Supported Devices

  • The drivers provided support the following devices :
      @@ -98,9 +169,9 @@

      Supported Devices

      -

      Main Changes

      +

      Main Changes

      Maintenance release of HAL and LL drivers for STM32MP15xx devices

      -

      Contents

      +

      Contents

      • General updates to fix known defects and enhancements implementation
      • Major update of drivers for STM32MP15xx devices: @@ -133,7 +204,7 @@

        Contents

-

Known Limitations

+

Known Limitations

  • None
@@ -141,7 +212,7 @@

Dependencies

  • None
-

Supported Devices

+

Supported Devices

  • The drivers provided support the following devices :
      @@ -155,9 +226,9 @@

      Supported Devices

      -

      Main Changes

      +

      Main Changes

      Maintenance release of HAL and LL drivers for STM32MP15xx devices

      -

      Contents

      +

      Contents

      • General updates to fix known defects and enhancements implementation
      • Major update of drivers for STM32MP15xx devices: @@ -204,7 +275,7 @@

        Contents

-

Known Limitations

+

Known Limitations

  • None
@@ -212,7 +283,7 @@

Dependencies

  • None
-

Supported Devices

+

Supported Devices

  • The drivers provided support the following devices :
      @@ -226,9 +297,9 @@

      Supported Devices

      -

      Main Changes

      +

      Main Changes

      Maintenance release of HAL and LL drivers for STM32MP15xx devices

      -

      Contents

      +

      Contents

      • General updates to fix known defects and enhancements implementation
      • Major update of drivers for STM32MP15xx devices: @@ -279,7 +350,7 @@

        Contents

-

Known Limitations

+

Known Limitations

  • None
@@ -287,7 +358,7 @@

Dependencies

  • None
-

Supported Devices

+

Supported Devices

  • The drivers provided support the following devices :
      @@ -301,9 +372,9 @@

      Supported Devices

      -

      Main Changes

      +

      Main Changes

      First Maintenance release of HAL and LL drivers for STM32MP15xx devices

      -

      Contents

      +

      Contents

      • General updates to fix known defects and enhancements implementation
      • Implementation of LL APIs: @@ -362,7 +433,7 @@

        Contents

-

Known Limitations

+

Known Limitations

  • None
@@ -375,9 +446,9 @@

Dependencies

-

Main Changes

+

Main Changes

First official release of HAL and LL drivers for STM32MP15xx devices

-

Known Limitations

+

Known Limitations

  • None
diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal.c b/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal.c index 61d5f9a02f..3f08bfdffd 100644 --- a/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal.c +++ b/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal.c @@ -54,7 +54,7 @@ * @brief STM32MP1xx HAL Driver version number */ #define __STM32MP1xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ -#define __STM32MP1xx_HAL_VERSION_SUB1 (0x05U) /*!< [23:16] sub1 version */ +#define __STM32MP1xx_HAL_VERSION_SUB1 (0x06U) /*!< [23:16] sub1 version */ #define __STM32MP1xx_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ #define __STM32MP1xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32MP1xx_HAL_VERSION ((__STM32MP1xx_HAL_VERSION_MAIN << 24)\ @@ -523,6 +523,33 @@ uint32_t HAL_GetDEVID(void) return((DBGMCU->IDCODE) & IDCODE_DEVID_MASK); } +/** + * @brief Return the first word of the unique device identifier (UID based on 96 bits) + * @retval Device identifier + */ +uint32_t HAL_GetUIDw0(void) +{ + return(READ_REG(*((uint32_t *)UID_BASE))); +} + +/** + * @brief Return the second word of the unique device identifier (UID based on 96 bits) + * @retval Device identifier + */ +uint32_t HAL_GetUIDw1(void) +{ + return(READ_REG(*((uint32_t *)(UID_BASE + 4U)))); +} + +/** + * @brief Return the third word of the unique device identifier (UID based on 96 bits) + * @retval Device identifier + */ +uint32_t HAL_GetUIDw2(void) +{ + return(READ_REG(*((uint32_t *)(UID_BASE + 8U)))); +} + /** * @brief Enable DBG wake up on AIEC * @retval None diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_adc.c b/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_adc.c index b9a92b01e4..64551cc7b1 100644 --- a/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_adc.c +++ b/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_adc.c @@ -487,7 +487,7 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc) /* Note: Variable divided by 2 to compensate partially */ /* CPU processing cycles, scaling in us split to not */ /* exceed 32 bits register capacity and handle low frequency. */ - wait_loop_index = ((LL_ADC_DELAY_INTERNAL_REGUL_STAB_US / 10UL) * (SystemCoreClock / (100000UL * 2UL))); + wait_loop_index = ((LL_ADC_DELAY_INTERNAL_REGUL_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); while (wait_loop_index != 0UL) { wait_loop_index--; @@ -676,7 +676,6 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc) tmp_hal_status = HAL_ERROR; } - /* Return function status */ return tmp_hal_status; } @@ -860,31 +859,28 @@ HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc) HAL_ADC_ConfigChannel() or HAL_ADCEx_InjectedConfigChannel() ) */ ADC_CLEAR_COMMON_CONTROL_REGISTER(hadc); - } - - /* DeInit the low level hardware. - - For example: - __HAL_RCC_ADC_FORCE_RESET(); - __HAL_RCC_ADC_RELEASE_RESET(); - __HAL_RCC_ADC_CLK_DISABLE(); - Keep in mind that all ADCs use the same clock: disabling - the clock will reset all ADCs. - - */ + /* ========== Hard reset ADC peripheral ========== */ + /* Performs a global reset of the entire ADC peripherals instances */ + /* sharing the same common ADC instance: ADC state is forced to */ + /* a similar state as after device power-on. */ + /* Note: A possible implementation is to add RCC bus reset of ADC */ + /* (for example, using macro */ + /* __HAL_RCC_ADC..._FORCE_RESET()/..._RELEASE_RESET()/..._CLK_DISABLE()) */ + /* in function "void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc)": */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) - if (hadc->MspDeInitCallback == NULL) - { - hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */ - } + if (hadc->MspDeInitCallback == NULL) + { + hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */ + } - /* DeInit the low level hardware */ - hadc->MspDeInitCallback(hadc); + /* DeInit the low level hardware */ + hadc->MspDeInitCallback(hadc); #else - /* DeInit the low level hardware */ - HAL_ADC_MspDeInit(hadc); + /* DeInit the low level hardware */ + HAL_ADC_MspDeInit(hadc); #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + } /* Set ADC error code to none */ ADC_CLEAR_ERRORCODE(hadc); @@ -896,10 +892,8 @@ HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc) /* Set ADC state */ hadc->State = HAL_ADC_STATE_RESET; - /* Process unlocked */ __HAL_UNLOCK(hadc); - /* Return function status */ return tmp_hal_status; } @@ -1274,7 +1268,6 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc) /* (To ensure of no unknown state from potential previous ADC operations) */ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR)); - /* Process unlocked */ /* Unlock before starting ADC conversions: in case of potential */ /* interruption, to let the process to ADC IRQ Handler. */ __HAL_UNLOCK(hadc); @@ -1328,7 +1321,6 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc) } else { - /* Process unlocked */ __HAL_UNLOCK(hadc); } } @@ -1337,7 +1329,6 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc) tmp_hal_status = HAL_BUSY; } - /* Return function status */ return tmp_hal_status; } @@ -1379,10 +1370,8 @@ HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc) } } - /* Process unlocked */ __HAL_UNLOCK(hadc); - /* Return function status */ return tmp_hal_status; } @@ -1486,13 +1475,16 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Ti { if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL)) { - /* Update ADC state machine to timeout */ - SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); + /* New check to avoid false timeout detection in case of preemption */ + if ((hadc->Instance->ISR & tmp_Flag_End) == 0UL) + { + /* Update ADC state machine to timeout */ + SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); - /* Process unlocked */ - __HAL_UNLOCK(hadc); + __HAL_UNLOCK(hadc); - return HAL_TIMEOUT; + return HAL_TIMEOUT; + } } } } @@ -1559,7 +1551,6 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Ti } } - /* Return function status */ return HAL_OK; } @@ -1602,13 +1593,16 @@ HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventTy { if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL)) { - /* Update ADC state machine to timeout */ - SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); + /* New check to avoid false timeout detection in case of preemption */ + if (__HAL_ADC_GET_FLAG(hadc, EventType) == 0UL) + { + /* Update ADC state machine to timeout */ + SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); - /* Process unlocked */ - __HAL_UNLOCK(hadc); + __HAL_UNLOCK(hadc); - return HAL_TIMEOUT; + return HAL_TIMEOUT; + } } } } @@ -1701,7 +1695,6 @@ HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventTy break; } - /* Return function status */ return HAL_OK; } @@ -1787,7 +1780,6 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc) /* (To ensure of no unknown state from potential previous ADC operations) */ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR)); - /* Process unlocked */ /* Unlock before starting ADC conversions: in case of potential */ /* interruption, to let the process to ADC IRQ Handler. */ __HAL_UNLOCK(hadc); @@ -1914,7 +1906,6 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc) } else { - /* Process unlocked */ __HAL_UNLOCK(hadc); } @@ -1924,7 +1915,6 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc) tmp_hal_status = HAL_BUSY; } - /* Return function status */ return tmp_hal_status; } @@ -1968,10 +1958,8 @@ HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc) } } - /* Process unlocked */ __HAL_UNLOCK(hadc); - /* Return function status */ return tmp_hal_status; } @@ -2068,7 +2056,6 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, ui /* operations) */ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR)); - /* Process unlocked */ /* Unlock before starting ADC conversions: in case of potential */ /* interruption, to let the process to ADC IRQ Handler. */ __HAL_UNLOCK(hadc); @@ -2093,7 +2080,6 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, ui } else { - /* Process unlocked */ __HAL_UNLOCK(hadc); } @@ -2102,7 +2088,6 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, ui else { tmp_hal_status = HAL_ERROR; - /* Process unlocked */ __HAL_UNLOCK(hadc); } #endif @@ -2112,7 +2097,6 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, ui tmp_hal_status = HAL_BUSY; } - /* Return function status */ return tmp_hal_status; } @@ -2188,10 +2172,8 @@ HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc) } - /* Process unlocked */ __HAL_UNLOCK(hadc); - /* Return function status */ return tmp_hal_status; } @@ -2698,10 +2680,10 @@ __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc) * The setting of these parameters is conditioned to ADC state: * Refer to comments of structure "ADC_ChannelConfTypeDef". * @param hadc ADC handle - * @param sConfig Structure of ADC channel assigned to ADC group regular. + * @param pConfig Structure of ADC channel assigned to ADC group regular. * @retval HAL status */ -HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig) +HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *pConfig) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; uint32_t tmpOffsetShifted; @@ -2712,38 +2694,38 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank)); - assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime)); - assert_param(IS_ADC_SINGLE_DIFFERENTIAL(sConfig->SingleDiff)); - assert_param(IS_ADC_OFFSET_NUMBER(sConfig->OffsetNumber)); + assert_param(IS_ADC_REGULAR_RANK(pConfig->Rank)); + assert_param(IS_ADC_SAMPLE_TIME(pConfig->SamplingTime)); + assert_param(IS_ADC_SINGLE_DIFFERENTIAL(pConfig->SingleDiff)); + assert_param(IS_ADC_OFFSET_NUMBER(pConfig->OffsetNumber)); /* Check offset range according to oversampling setting */ if (hadc->Init.OversamplingMode == ENABLE) { - assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), sConfig->Offset/(hadc->Init.Oversampling.Ratio+1U))); + assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), pConfig->Offset/(hadc->Init.Oversampling.Ratio+1U))); } else { - assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), sConfig->Offset)); + assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), pConfig->Offset)); } /* if ROVSE is set, the value of the OFFSETy_EN bit in ADCx_OFRy register is ignored (considered as reset) */ - assert_param(!((sConfig->OffsetNumber != ADC_OFFSET_NONE) && (hadc->Init.OversamplingMode == ENABLE))); + assert_param(!((pConfig->OffsetNumber != ADC_OFFSET_NONE) && (hadc->Init.OversamplingMode == ENABLE))); /* Verification of channel number */ - if (sConfig->SingleDiff != ADC_DIFFERENTIAL_ENDED) + if (pConfig->SingleDiff != ADC_DIFFERENTIAL_ENDED) { - assert_param(IS_ADC_CHANNEL(sConfig->Channel)); + assert_param(IS_ADC_CHANNEL(pConfig->Channel)); } else { if (hadc->Instance == ADC1) { - assert_param(IS_ADC1_DIFF_CHANNEL(sConfig->Channel)); + assert_param(IS_ADC1_DIFF_CHANNEL(pConfig->Channel)); } if (hadc->Instance == ADC2) { - assert_param(IS_ADC2_DIFF_CHANNEL(sConfig->Channel)); + assert_param(IS_ADC2_DIFF_CHANNEL(pConfig->Channel)); } } @@ -2758,10 +2740,10 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) { /* ADC channels preselection */ - hadc->Instance->PCSEL |= (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) & 0x1FUL)); + hadc->Instance->PCSEL |= (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)pConfig->Channel) & 0x1FUL)); /* Set ADC group regular sequence: channel on the selected scan sequence rank */ - LL_ADC_REG_SetSequencerRanks(hadc->Instance, sConfig->Rank, sConfig->Channel); + LL_ADC_REG_SetSequencerRanks(hadc->Instance, pConfig->Rank, pConfig->Channel); /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated when ADC is disabled or enabled without */ @@ -2775,46 +2757,46 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf ) { /* Set sampling time of the selected ADC channel */ - LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfig->Channel, sConfig->SamplingTime); + LL_ADC_SetChannelSamplingTime(hadc->Instance, pConfig->Channel, pConfig->SamplingTime); /* Configure the offset: offset enable/disable, channel, offset value */ /* Shift the offset with respect to the selected ADC resolution. */ /* Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0 */ - tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, (uint32_t)sConfig->Offset); + tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, (uint32_t)pConfig->Offset); - if (sConfig->OffsetNumber != ADC_OFFSET_NONE) + if (pConfig->OffsetNumber != ADC_OFFSET_NONE) { /* Set ADC selected offset number */ - LL_ADC_SetOffset(hadc->Instance, sConfig->OffsetNumber, sConfig->Channel, tmpOffsetShifted); + LL_ADC_SetOffset(hadc->Instance, pConfig->OffsetNumber, pConfig->Channel, tmpOffsetShifted); - assert_param(IS_FUNCTIONAL_STATE(sConfig->OffsetSignedSaturation)); + assert_param(IS_FUNCTIONAL_STATE(pConfig->OffsetSignedSaturation)); /* Set ADC selected offset signed saturation */ - LL_ADC_SetOffsetSignedSaturation(hadc->Instance, sConfig->OffsetNumber, (sConfig->OffsetSignedSaturation == ENABLE) ? LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE : LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE); + LL_ADC_SetOffsetSignedSaturation(hadc->Instance, pConfig->OffsetNumber, (pConfig->OffsetSignedSaturation == ENABLE) ? LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE : LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE); - assert_param(IS_FUNCTIONAL_STATE(sConfig->OffsetRightShift)); + assert_param(IS_FUNCTIONAL_STATE(pConfig->OffsetRightShift)); /* Set ADC selected offset right shift */ - LL_ADC_SetDataRightShift(hadc->Instance, sConfig->OffsetNumber, (sConfig->OffsetRightShift == ENABLE) ? LL_ADC_OFFSET_RSHIFT_ENABLE : LL_ADC_OFFSET_RSHIFT_DISABLE); + LL_ADC_SetDataRightShift(hadc->Instance, pConfig->OffsetNumber, (pConfig->OffsetRightShift == ENABLE) ? LL_ADC_OFFSET_RSHIFT_ENABLE : LL_ADC_OFFSET_RSHIFT_DISABLE); } else { /* Scan OFR1, OFR2, OFR3, OFR4 to check if the selected channel is enabled. If this is the case, offset OFRx is disabled since - sConfig->OffsetNumber = ADC_OFFSET_NONE. */ - if (((hadc->Instance->OFR1) & ADC_OFR1_OFFSET1_CH) == ADC_OFR_CHANNEL(sConfig->Channel)) + pConfig->OffsetNumber = ADC_OFFSET_NONE. */ + if (((hadc->Instance->OFR1) & ADC_OFR1_OFFSET1_CH) == ADC_OFR_CHANNEL(pConfig->Channel)) { CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_SSATE); } - if (((hadc->Instance->OFR2) & ADC_OFR2_OFFSET2_CH) == ADC_OFR_CHANNEL(sConfig->Channel)) + if (((hadc->Instance->OFR2) & ADC_OFR2_OFFSET2_CH) == ADC_OFR_CHANNEL(pConfig->Channel)) { CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_SSATE); } - if (((hadc->Instance->OFR3) & ADC_OFR3_OFFSET3_CH) == ADC_OFR_CHANNEL(sConfig->Channel)) + if (((hadc->Instance->OFR3) & ADC_OFR3_OFFSET3_CH) == ADC_OFR_CHANNEL(pConfig->Channel)) { CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_SSATE); } - if (((hadc->Instance->OFR4) & ADC_OFR4_OFFSET4_CH) == ADC_OFR_CHANNEL(sConfig->Channel)) + if (((hadc->Instance->OFR4) & ADC_OFR4_OFFSET4_CH) == ADC_OFR_CHANNEL(pConfig->Channel)) { CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_SSATE); } @@ -2828,16 +2810,16 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) { /* Set mode single-ended or differential input of the selected ADC channel */ - LL_ADC_SetChannelSingleDiff(hadc->Instance, sConfig->Channel, sConfig->SingleDiff); + LL_ADC_SetChannelSingleDiff(hadc->Instance, pConfig->Channel, pConfig->SingleDiff); /* Configuration of differential mode */ - if (sConfig->SingleDiff == ADC_DIFFERENTIAL_ENDED) + if (pConfig->SingleDiff == ADC_DIFFERENTIAL_ENDED) { /* Set sampling time of the selected ADC channel */ /* Note: ADC channel number masked with value "0x1F" to ensure shift value within 32 bits range */ LL_ADC_SetChannelSamplingTime(hadc->Instance, - (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) + 1UL) & 0x1FUL)), - sConfig->SamplingTime); + (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)pConfig->Channel) + 1UL) & 0x1FUL)), + pConfig->SamplingTime); } /* Management of internal measurement channels: Vbat/VrefInt/TempSensor/VddCore. */ @@ -2846,7 +2828,7 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf /* Note: these internal measurement paths can be disabled using */ /* HAL_ADC_DeInit(). */ - if (__LL_ADC_IS_CHANNEL_INTERNAL(sConfig->Channel)) + if (__LL_ADC_IS_CHANNEL_INTERNAL(pConfig->Channel)) { /* Configuration of common ADC parameters */ @@ -2858,7 +2840,7 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf { /* If the requested internal measurement path has already been enabled, */ /* bypass the configuration processing. */ - if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) + if ((pConfig->Channel == ADC_CHANNEL_TEMPSENSOR) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL)) { if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc)) @@ -2870,28 +2852,28 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf /* Note: Variable divided by 2 to compensate partially */ /* CPU processing cycles, scaling in us split to not */ /* exceed 32 bits register capacity and handle low frequency. */ - wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * (SystemCoreClock / (100000UL * 2UL))); + wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); while(wait_loop_index != 0UL) { wait_loop_index--; } } } - else if ((sConfig->Channel == ADC_CHANNEL_VBAT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL)) + else if ((pConfig->Channel == ADC_CHANNEL_VBAT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL)) { if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc)) { LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VBAT | tmp_config_internal_channel); } } - else if ((sConfig->Channel == ADC_CHANNEL_VREFINT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL)) + else if ((pConfig->Channel == ADC_CHANNEL_VREFINT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL)) { if (ADC_VREFINT_INSTANCE(hadc)) { LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VREFINT | tmp_config_internal_channel); } } - else if ((sConfig->Channel == ADC_CHANNEL_VCORE) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VDDCORE) == 0UL)) + else if ((pConfig->Channel == ADC_CHANNEL_VCORE) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VDDCORE) == 0UL)) { if (ADC_VDDCORE_INSTANCE(hadc)) { @@ -2928,10 +2910,8 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf tmp_hal_status = HAL_ERROR; } - /* Process unlocked */ __HAL_UNLOCK(hadc); - /* Return function status */ return tmp_hal_status; } @@ -2948,28 +2928,28 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf * @note On this STM32 series, analog watchdog thresholds cannot be modified * while ADC conversion is on going. * @param hadc ADC handle - * @param AnalogWDGConfig Structure of ADC analog watchdog configuration + * @param pAnalogWDGConfig Structure of ADC analog watchdog configuration * @retval HAL status */ -HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *AnalogWDGConfig) +HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *pAnalogWDGConfig) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; - uint32_t tmpAWDHighThresholdShifted; - uint32_t tmpAWDLowThresholdShifted; + uint32_t tmp_awd_high_threshold_shifted; + uint32_t tmp_awd_low_threshold_shifted; uint32_t tmp_adc_is_conversion_on_going_regular; uint32_t tmp_adc_is_conversion_on_going_injected; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - assert_param(IS_ADC_ANALOG_WATCHDOG_NUMBER(AnalogWDGConfig->WatchdogNumber)); - assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(AnalogWDGConfig->WatchdogMode)); - assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode)); + assert_param(IS_ADC_ANALOG_WATCHDOG_NUMBER(pAnalogWDGConfig->WatchdogNumber)); + assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(pAnalogWDGConfig->WatchdogMode)); + assert_param(IS_FUNCTIONAL_STATE(pAnalogWDGConfig->ITMode)); - if ((AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG) || - (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || - (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC)) + if ((pAnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG) || + (pAnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || + (pAnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC)) { - assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel)); + assert_param(IS_ADC_CHANNEL(pAnalogWDGConfig->Channel)); } /* Verify thresholds range */ @@ -2977,14 +2957,14 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDG { /* Case of oversampling enabled: thresholds are compared to oversampling intermediate computation (after ratio, before shift application) */ - assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->HighThreshold / (hadc->Init.Oversampling.Ratio + 1UL))); - assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->LowThreshold / (hadc->Init.Oversampling.Ratio + 1UL))); + assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), pAnalogWDGConfig->HighThreshold / (hadc->Init.Oversampling.Ratio + 1UL))); + assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), pAnalogWDGConfig->LowThreshold / (hadc->Init.Oversampling.Ratio + 1UL))); } else { /* Verify if thresholds are within the selected ADC resolution */ - assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->HighThreshold)); - assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->LowThreshold)); + assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), pAnalogWDGConfig->HighThreshold)); + assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), pAnalogWDGConfig->LowThreshold)); } /* Process locked */ @@ -3002,25 +2982,25 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDG ) { /* Analog watchdog configuration */ - if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_1) + if (pAnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_1) { /* Configuration of analog watchdog: */ /* - Set the analog watchdog enable mode: one or overall group of */ /* channels, on groups regular and-or injected. */ - switch (AnalogWDGConfig->WatchdogMode) + switch (pAnalogWDGConfig->WatchdogMode) { case ADC_ANALOGWATCHDOG_SINGLE_REG: - LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, __LL_ADC_ANALOGWD_CHANNEL_GROUP(AnalogWDGConfig->Channel, + LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, __LL_ADC_ANALOGWD_CHANNEL_GROUP(pAnalogWDGConfig->Channel, LL_ADC_GROUP_REGULAR)); break; case ADC_ANALOGWATCHDOG_SINGLE_INJEC: - LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, __LL_ADC_ANALOGWD_CHANNEL_GROUP(AnalogWDGConfig->Channel, + LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, __LL_ADC_ANALOGWD_CHANNEL_GROUP(pAnalogWDGConfig->Channel, LL_ADC_GROUP_INJECTED)); break; case ADC_ANALOGWATCHDOG_SINGLE_REGINJEC: - LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, __LL_ADC_ANALOGWD_CHANNEL_GROUP(AnalogWDGConfig->Channel, + LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, __LL_ADC_ANALOGWD_CHANNEL_GROUP(pAnalogWDGConfig->Channel, LL_ADC_GROUP_REGULAR_INJECTED)); break; @@ -3044,12 +3024,12 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDG /* Shift the offset in function of the selected ADC resolution: */ /* Thresholds have to be left-aligned on bit 11, the LSB (right bits) */ /* are set to 0 */ - tmpAWDHighThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold); - tmpAWDLowThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold); + tmp_awd_high_threshold_shifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, pAnalogWDGConfig->HighThreshold); + tmp_awd_low_threshold_shifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, pAnalogWDGConfig->LowThreshold); /* Set the high and low thresholds */ - MODIFY_REG(hadc->Instance->LTR1, ADC_LTR1_LT1 , tmpAWDLowThresholdShifted); - MODIFY_REG(hadc->Instance->HTR1, ADC_HTR1_HT1 , tmpAWDHighThresholdShifted); + MODIFY_REG(hadc->Instance->LTR1, ADC_LTR1_LT1 , tmp_awd_low_threshold_shifted); + MODIFY_REG(hadc->Instance->HTR1, ADC_HTR1_HT1 , tmp_awd_high_threshold_shifted); /* Update state, clear previous result related to AWD1 */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD1); @@ -3061,7 +3041,7 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDG LL_ADC_ClearFlag_AWD1(hadc->Instance); /* Configure ADC analog watchdog interrupt */ - if (AnalogWDGConfig->ITMode == ENABLE) + if (pAnalogWDGConfig->ITMode == ENABLE) { LL_ADC_EnableIT_AWD1(hadc->Instance); } @@ -3073,20 +3053,20 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDG /* Case of ADC_ANALOGWATCHDOG_2 or ADC_ANALOGWATCHDOG_3 */ else { - switch (AnalogWDGConfig->WatchdogMode) + switch (pAnalogWDGConfig->WatchdogMode) { case ADC_ANALOGWATCHDOG_SINGLE_REG: case ADC_ANALOGWATCHDOG_SINGLE_INJEC: case ADC_ANALOGWATCHDOG_SINGLE_REGINJEC: /* Update AWD by bitfield to keep the possibility to monitor */ /* several channels by successive calls of this function. */ - if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2) + if (pAnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2) { - SET_BIT(hadc->Instance->AWD2CR, (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDGConfig->Channel) & 0x1FUL))); + SET_BIT(hadc->Instance->AWD2CR, (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(pAnalogWDGConfig->Channel) & 0x1FUL))); } else { - SET_BIT(hadc->Instance->AWD3CR, (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDGConfig->Channel) & 0x1FUL))); + SET_BIT(hadc->Instance->AWD3CR, (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(pAnalogWDGConfig->Channel) & 0x1FUL))); } break; @@ -3095,40 +3075,40 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDG case ADC_ANALOGWATCHDOG_ALL_REGINJEC: /* Update AWD by bitfield to keep the possibility to monitor */ /* several channels by successive calls of this function. */ - if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2) + if (pAnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2) { - SET_BIT(hadc->Instance->AWD2CR, (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDGConfig->Channel) & 0x1FUL))); + SET_BIT(hadc->Instance->AWD2CR, (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(pAnalogWDGConfig->Channel) & 0x1FUL))); } else { - SET_BIT(hadc->Instance->AWD3CR, (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDGConfig->Channel) & 0x1FUL))); + SET_BIT(hadc->Instance->AWD3CR, (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(pAnalogWDGConfig->Channel) & 0x1FUL))); } break; default: /* ADC_ANALOGWATCHDOG_NONE */ - LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, AnalogWDGConfig->WatchdogNumber, LL_ADC_AWD_DISABLE); + LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, pAnalogWDGConfig->WatchdogNumber, LL_ADC_AWD_DISABLE); break; } /* Shift the thresholds in function of the selected ADC resolution */ /* have to be left-aligned on bit 15, the LSB (right bits) are set to 0 */ - tmpAWDHighThresholdShifted = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold); - tmpAWDLowThresholdShifted = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold); + tmp_awd_high_threshold_shifted = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, pAnalogWDGConfig->HighThreshold); + tmp_awd_low_threshold_shifted = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, pAnalogWDGConfig->LowThreshold); - if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2) + if (pAnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2) { /* Set ADC analog watchdog thresholds value of both thresholds high and low */ - MODIFY_REG(hadc->Instance->LTR2, ADC_LTR2_LT2 , tmpAWDLowThresholdShifted); - MODIFY_REG(hadc->Instance->HTR2, ADC_HTR2_HT2 , tmpAWDHighThresholdShifted); + MODIFY_REG(hadc->Instance->LTR2, ADC_LTR2_LT2 , tmp_awd_low_threshold_shifted); + MODIFY_REG(hadc->Instance->HTR2, ADC_HTR2_HT2 , tmp_awd_high_threshold_shifted); } else { /* Set ADC analog watchdog thresholds value of both thresholds high and low */ - MODIFY_REG(hadc->Instance->LTR3, ADC_LTR3_LT3 , tmpAWDLowThresholdShifted); - MODIFY_REG(hadc->Instance->HTR3, ADC_HTR3_HT3 , tmpAWDHighThresholdShifted); + MODIFY_REG(hadc->Instance->LTR3, ADC_LTR3_LT3 , tmp_awd_low_threshold_shifted); + MODIFY_REG(hadc->Instance->HTR3, ADC_HTR3_HT3 , tmp_awd_high_threshold_shifted); } - if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2) + if (pAnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2) { /* Update state, clear previous result related to AWD2 */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD2); @@ -3140,7 +3120,7 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDG LL_ADC_ClearFlag_AWD2(hadc->Instance); /* Configure ADC analog watchdog interrupt */ - if (AnalogWDGConfig->ITMode == ENABLE) + if (pAnalogWDGConfig->ITMode == ENABLE) { LL_ADC_EnableIT_AWD2(hadc->Instance); } @@ -3149,7 +3129,7 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDG LL_ADC_DisableIT_AWD2(hadc->Instance); } } - /* (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_3) */ + /* (pAnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_3) */ else { /* Update state, clear previous result related to AWD3 */ @@ -3162,7 +3142,7 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDG LL_ADC_ClearFlag_AWD3(hadc->Instance); /* Configure ADC analog watchdog interrupt */ - if (AnalogWDGConfig->ITMode == ENABLE) + if (pAnalogWDGConfig->ITMode == ENABLE) { LL_ADC_EnableIT_AWD3(hadc->Instance); } @@ -3183,10 +3163,8 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDG tmp_hal_status = HAL_ERROR; } - /* Process unlocked */ __HAL_UNLOCK(hadc); - /* Return function status */ return tmp_hal_status; } @@ -3371,16 +3349,19 @@ HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc, uint32_t Conversio { if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT) { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + /* New check to avoid false timeout detection in case of preemption */ + if ((hadc->Instance->CR & tmp_ADC_CR_ADSTART_JADSTART) != 0UL) + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - /* Set ADC error code to ADC peripheral internal error */ - SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + /* Set ADC error code to ADC peripheral internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - return HAL_ERROR; + return HAL_ERROR; + } } } - } /* Return HAL status */ @@ -3448,13 +3429,17 @@ HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc) if ((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT) { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + /* New check to avoid false timeout detection in case of preemption */ + if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL) + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - /* Set ADC error code to ADC peripheral internal error */ - SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + /* Set ADC error code to ADC peripheral internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - return HAL_ERROR; + return HAL_ERROR; + } } } } @@ -3510,13 +3495,17 @@ HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc) { if ((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT) { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + /* New check to avoid false timeout detection in case of preemption */ + if ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL) + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - /* Set ADC error code to ADC peripheral internal error */ - SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + /* Set ADC error code to ADC peripheral internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - return HAL_ERROR; + return HAL_ERROR; + } } } } diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_adc_ex.c b/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_adc_ex.c index af9af89de2..6067a0fed9 100644 --- a/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_adc_ex.c +++ b/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_adc_ex.c @@ -160,7 +160,6 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL); - /* Process unlocked */ __HAL_UNLOCK(hadc); return HAL_ERROR; @@ -180,10 +179,8 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t /* to state "HAL_ERROR" by function disabling the ADC. */ } - /* Process unlocked */ __HAL_UNLOCK(hadc); - /* Return function status */ return tmp_hal_status; } @@ -295,10 +292,8 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32 tmp_hal_status = HAL_ERROR; } - /* Process unlocked */ __HAL_UNLOCK(hadc); - /* Return function status */ return tmp_hal_status; } @@ -454,7 +449,6 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef *hadc) /* (To ensure of no unknown state from potential previous ADC operations) */ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS)); - /* Process unlocked */ /* Unlock before starting ADC conversions: in case of potential */ /* interruption, to let the process to ADC IRQ Handler. */ __HAL_UNLOCK(hadc); @@ -500,11 +494,9 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef *hadc) } else { - /* Process unlocked */ __HAL_UNLOCK(hadc); } - /* Return function status */ return tmp_hal_status; } } @@ -565,10 +557,8 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef *hadc) } } - /* Process unlocked */ __HAL_UNLOCK(hadc); - /* Return function status */ return tmp_hal_status; } @@ -616,13 +606,16 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef *hadc, u { if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL)) { - /* Update ADC state machine to timeout */ - SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); + /* New check to avoid false timeout detection in case of preemption */ + if ((hadc->Instance->ISR & tmp_Flag_End) == 0UL) + { + /* Update ADC state machine to timeout */ + SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); - /* Process unlocked */ - __HAL_UNLOCK(hadc); + __HAL_UNLOCK(hadc); - return HAL_TIMEOUT; + return HAL_TIMEOUT; + } } } } @@ -795,7 +788,6 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef *hadc) /* (To ensure of no unknown state from potential previous ADC operations) */ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS)); - /* Process unlocked */ /* Unlock before starting ADC conversions: in case of potential */ /* interruption, to let the process to ADC IRQ Handler. */ __HAL_UNLOCK(hadc); @@ -862,11 +854,9 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef *hadc) } else { - /* Process unlocked */ __HAL_UNLOCK(hadc); } - /* Return function status */ return tmp_hal_status; } } @@ -934,10 +924,8 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc) } } - /* Process unlocked */ __HAL_UNLOCK(hadc); - /* Return function status */ return tmp_hal_status; } @@ -960,7 +948,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc) HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length) { HAL_StatusTypeDef tmp_hal_status; - ADC_HandleTypeDef tmphadcSlave; + ADC_HandleTypeDef tmphadcSlave={0}; ADC_Common_TypeDef *tmpADC_Common; /* Check the parameters */ @@ -977,6 +965,10 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t /* Process locked */ __HAL_LOCK(hadc); + /* Temporary handle minimum initialization */ + __HAL_ADC_RESET_HANDLE_STATE(&tmphadcSlave); + ADC_CLEAR_ERRORCODE(&tmphadcSlave); + /* Set a temporary handle of the ADC slave associated to the ADC master */ ADC_MULTI_SLAVE(hadc, &tmphadcSlave); @@ -985,7 +977,6 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); - /* Process unlocked */ __HAL_UNLOCK(hadc); return HAL_ERROR; @@ -1029,7 +1020,6 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t /* (To ensure of no unknown state from potential previous ADC operations) */ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR)); - /* Process unlocked */ /* Unlock before starting ADC conversions: in case of potential */ /* interruption, to let the process to ADC IRQ Handler. */ __HAL_UNLOCK(hadc); @@ -1049,11 +1039,9 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t } else { - /* Process unlocked */ __HAL_UNLOCK(hadc); } - /* Return function status */ return tmp_hal_status; } } @@ -1075,7 +1063,7 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status; uint32_t tickstart; - ADC_HandleTypeDef tmphadcSlave; + ADC_HandleTypeDef tmphadcSlave={0}; uint32_t tmphadcSlave_conversion_on_going; HAL_StatusTypeDef tmphadcSlave_disable_status; @@ -1092,6 +1080,10 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc) /* Disable ADC peripheral if conversions are effectively stopped */ if (tmp_hal_status == HAL_OK) { + /* Temporary handle minimum initialization */ + __HAL_ADC_RESET_HANDLE_STATE(&tmphadcSlave); + ADC_CLEAR_ERRORCODE(&tmphadcSlave); + /* Set a temporary handle of the ADC slave associated to the ADC master */ ADC_MULTI_SLAVE(hadc, &tmphadcSlave); @@ -1100,7 +1092,6 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc) /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); - /* Process unlocked */ __HAL_UNLOCK(hadc); return HAL_ERROR; @@ -1119,13 +1110,19 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc) { if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT) { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + /* New check to avoid false timeout detection in case of preemption */ + tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance); + if ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL) + || (tmphadcSlave_conversion_on_going == 1UL) + ) + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - /* Process unlocked */ - __HAL_UNLOCK(hadc); + __HAL_UNLOCK(hadc); - return HAL_ERROR; + return HAL_ERROR; + } } tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance); @@ -1172,10 +1169,8 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc) HAL_ADC_STATE_READY); } - /* Process unlocked */ __HAL_UNLOCK(hadc); - /* Return function status */ return tmp_hal_status; } @@ -1390,10 +1385,8 @@ HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef *hadc) } } - /* Process unlocked */ __HAL_UNLOCK(hadc); - /* Return function status */ return tmp_hal_status; } @@ -1448,10 +1441,8 @@ HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef *hadc) } } - /* Process unlocked */ __HAL_UNLOCK(hadc); - /* Return function status */ return tmp_hal_status; } @@ -1532,10 +1523,8 @@ HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef *hadc) } } - /* Process unlocked */ __HAL_UNLOCK(hadc); - /* Return function status */ return tmp_hal_status; } @@ -1557,7 +1546,7 @@ HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status; uint32_t tickstart; - ADC_HandleTypeDef tmphadcSlave; + ADC_HandleTypeDef tmphadcSlave={0}; uint32_t tmphadcSlave_conversion_on_going; /* Check the parameters */ @@ -1576,6 +1565,10 @@ HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc) /* Clear HAL_ADC_STATE_REG_BUSY bit */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); + /* Temporary handle minimum initialization */ + __HAL_ADC_RESET_HANDLE_STATE(&tmphadcSlave); + ADC_CLEAR_ERRORCODE(&tmphadcSlave); + /* Set a temporary handle of the ADC slave associated to the ADC master */ ADC_MULTI_SLAVE(hadc, &tmphadcSlave); @@ -1584,7 +1577,6 @@ HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc) /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); - /* Process unlocked */ __HAL_UNLOCK(hadc); return HAL_ERROR; @@ -1603,13 +1595,19 @@ HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc) { if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT) { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + /* New check to avoid false timeout detection in case of preemption */ + tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance); + if ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL) + || (tmphadcSlave_conversion_on_going == 1UL) + ) + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - /* Process unlocked */ - __HAL_UNLOCK(hadc); + __HAL_UNLOCK(hadc); - return HAL_ERROR; + return HAL_ERROR; + } } tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance); @@ -1663,10 +1661,8 @@ HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc) } } - /* Process unlocked */ __HAL_UNLOCK(hadc); - /* Return function status */ return tmp_hal_status; } #endif /* ADC_MULTIMODE_SUPPORT */ @@ -1723,11 +1719,11 @@ HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc) * start once the 1st context is set, that is after the first three * HAL_ADCEx_InjectedConfigChannel() calls. The 2nd context can be set on the fly. * @param hadc ADC handle - * @param sConfigInjected Structure of ADC injected group and ADC channel for + * @param pConfigInjected Structure of ADC injected group and ADC channel for * injected group. * @retval HAL status */ -HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_InjectionConfTypeDef *sConfigInjected) +HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_InjectionConfTypeDef *pConfigInjected) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; uint32_t tmpOffsetShifted; @@ -1740,53 +1736,53 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - assert_param(IS_ADC_SAMPLE_TIME(sConfigInjected->InjectedSamplingTime)); - assert_param(IS_ADC_SINGLE_DIFFERENTIAL(sConfigInjected->InjectedSingleDiff)); - assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->AutoInjectedConv)); - assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->QueueInjectedContext)); - assert_param(IS_ADC_EXTTRIGINJEC_EDGE(sConfigInjected->ExternalTrigInjecConvEdge)); - assert_param(IS_ADC_EXTTRIGINJEC(sConfigInjected->ExternalTrigInjecConv)); - assert_param(IS_ADC_OFFSET_NUMBER(sConfigInjected->InjectedOffsetNumber)); - assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), sConfigInjected->InjectedOffset)); - assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjecOversamplingMode)); + assert_param(IS_ADC_SAMPLE_TIME(pConfigInjected->InjectedSamplingTime)); + assert_param(IS_ADC_SINGLE_DIFFERENTIAL(pConfigInjected->InjectedSingleDiff)); + assert_param(IS_FUNCTIONAL_STATE(pConfigInjected->AutoInjectedConv)); + assert_param(IS_FUNCTIONAL_STATE(pConfigInjected->QueueInjectedContext)); + assert_param(IS_ADC_EXTTRIGINJEC_EDGE(pConfigInjected->ExternalTrigInjecConvEdge)); + assert_param(IS_ADC_EXTTRIGINJEC(pConfigInjected->ExternalTrigInjecConv)); + assert_param(IS_ADC_OFFSET_NUMBER(pConfigInjected->InjectedOffsetNumber)); + assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), pConfigInjected->InjectedOffset)); + assert_param(IS_FUNCTIONAL_STATE(pConfigInjected->InjecOversamplingMode)); if (hadc->Init.ScanConvMode != ADC_SCAN_DISABLE) { - assert_param(IS_ADC_INJECTED_RANK(sConfigInjected->InjectedRank)); - assert_param(IS_ADC_INJECTED_NB_CONV(sConfigInjected->InjectedNbrOfConversion)); - assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedDiscontinuousConvMode)); + assert_param(IS_ADC_INJECTED_RANK(pConfigInjected->InjectedRank)); + assert_param(IS_ADC_INJECTED_NB_CONV(pConfigInjected->InjectedNbrOfConversion)); + assert_param(IS_FUNCTIONAL_STATE(pConfigInjected->InjectedDiscontinuousConvMode)); } /* Check offset range according to oversampling setting */ if (hadc->Init.OversamplingMode == ENABLE) { - assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), sConfigInjected->InjectedOffset/(hadc->Init.Oversampling.Ratio+1U))); + assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), pConfigInjected->InjectedOffset/(hadc->Init.Oversampling.Ratio+1U))); } else { - assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), sConfigInjected->InjectedOffset)); + assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), pConfigInjected->InjectedOffset)); } /* JDISCEN and JAUTO bits can't be set at the same time */ - assert_param(!((sConfigInjected->InjectedDiscontinuousConvMode == ENABLE) && (sConfigInjected->AutoInjectedConv == ENABLE))); + assert_param(!((pConfigInjected->InjectedDiscontinuousConvMode == ENABLE) && (pConfigInjected->AutoInjectedConv == ENABLE))); /* DISCEN and JAUTO bits can't be set at the same time */ - assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (sConfigInjected->AutoInjectedConv == ENABLE))); + assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (pConfigInjected->AutoInjectedConv == ENABLE))); /* Verification of channel number */ - if (sConfigInjected->InjectedSingleDiff != ADC_DIFFERENTIAL_ENDED) + if (pConfigInjected->InjectedSingleDiff != ADC_DIFFERENTIAL_ENDED) { - assert_param(IS_ADC_CHANNEL(sConfigInjected->InjectedChannel)); + assert_param(IS_ADC_CHANNEL(pConfigInjected->InjectedChannel)); } else { if (hadc->Instance == ADC1) { - assert_param(IS_ADC1_DIFF_CHANNEL(sConfigInjected->InjectedChannel)); + assert_param(IS_ADC1_DIFF_CHANNEL(pConfigInjected->InjectedChannel)); } if (hadc->Instance == ADC2) { - assert_param(IS_ADC2_DIFF_CHANNEL(sConfigInjected->InjectedChannel)); + assert_param(IS_ADC2_DIFF_CHANNEL(pConfigInjected->InjectedChannel)); } } @@ -1815,7 +1811,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I /* by software for alignment over all STM32 devices. */ if ((hadc->Init.ScanConvMode == ADC_SCAN_DISABLE) || - (sConfigInjected->InjectedNbrOfConversion == 1U)) + (pConfigInjected->InjectedNbrOfConversion == 1U)) { /* Configuration of context register JSQR: */ /* - number of ranks in injected group sequencer: fixed to 1st rank */ @@ -1824,23 +1820,23 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I /* - external trigger polarity */ /* - channel set to rank 1 (scan mode disabled, only rank 1 can be used) */ - if (sConfigInjected->InjectedRank == ADC_INJECTED_RANK_1) + if (pConfigInjected->InjectedRank == ADC_INJECTED_RANK_1) { /* Enable external trigger if trigger selection is different of */ /* software start. */ /* Note: This configuration keeps the hardware feature of parameter */ /* ExternalTrigInjecConvEdge "trigger edge none" equivalent to */ /* software start. */ - if (sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START) + if (pConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START) { - tmp_JSQR_ContextQueueBeingBuilt = (ADC_JSQR_RK(sConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1) - | (sConfigInjected->ExternalTrigInjecConv & ADC_JSQR_JEXTSEL) - | sConfigInjected->ExternalTrigInjecConvEdge + tmp_JSQR_ContextQueueBeingBuilt = (ADC_JSQR_RK(pConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1) + | (pConfigInjected->ExternalTrigInjecConv & ADC_JSQR_JEXTSEL) + | pConfigInjected->ExternalTrigInjecConvEdge ); } else { - tmp_JSQR_ContextQueueBeingBuilt = (ADC_JSQR_RK(sConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1)); + tmp_JSQR_ContextQueueBeingBuilt = (ADC_JSQR_RK(pConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1)); } MODIFY_REG(hadc->Instance->JSQR, ADC_JSQR_FIELDS, tmp_JSQR_ContextQueueBeingBuilt); @@ -1865,7 +1861,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I { /* Initialize number of channels that will be configured on the context */ /* being built */ - hadc->InjectionConfig.ChannelCount = sConfigInjected->InjectedNbrOfConversion; + hadc->InjectionConfig.ChannelCount = pConfigInjected->InjectedNbrOfConversion; /* Handle hadc saves the context under build up over each HAL_ADCEx_InjectedConfigChannel() call, this context will be written in JSQR register at the last call. At this point, the context is merely reset */ @@ -1881,16 +1877,16 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I /* Note: This configuration keeps the hardware feature of parameter */ /* ExternalTrigInjecConvEdge "trigger edge none" equivalent to */ /* software start. */ - if (sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START) + if (pConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START) { - tmp_JSQR_ContextQueueBeingBuilt = ((sConfigInjected->InjectedNbrOfConversion - 1U) - | (sConfigInjected->ExternalTrigInjecConv & ADC_JSQR_JEXTSEL) - | sConfigInjected->ExternalTrigInjecConvEdge + tmp_JSQR_ContextQueueBeingBuilt = ((pConfigInjected->InjectedNbrOfConversion - 1U) + | (pConfigInjected->ExternalTrigInjecConv & ADC_JSQR_JEXTSEL) + | pConfigInjected->ExternalTrigInjecConvEdge ); } else { - tmp_JSQR_ContextQueueBeingBuilt = ((sConfigInjected->InjectedNbrOfConversion - 1U)); + tmp_JSQR_ContextQueueBeingBuilt = ((pConfigInjected->InjectedNbrOfConversion - 1U)); } } @@ -1898,10 +1894,10 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I /* 2. Continue setting of context under definition with parameter */ /* related to each channel: channel rank sequence */ /* Clear the old JSQx bits for the selected rank */ - tmp_JSQR_ContextQueueBeingBuilt &= ~ADC_JSQR_RK(ADC_SQR3_SQ10, sConfigInjected->InjectedRank); + tmp_JSQR_ContextQueueBeingBuilt &= ~ADC_JSQR_RK(ADC_SQR3_SQ10, pConfigInjected->InjectedRank); /* Set the JSQx bits for the selected rank */ - tmp_JSQR_ContextQueueBeingBuilt |= ADC_JSQR_RK(sConfigInjected->InjectedChannel, sConfigInjected->InjectedRank); + tmp_JSQR_ContextQueueBeingBuilt |= ADC_JSQR_RK(pConfigInjected->InjectedChannel, pConfigInjected->InjectedRank); /* Decrease channel count */ hadc->InjectionConfig.ChannelCount--; @@ -1929,15 +1925,15 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL) { /* ADC channels preselection */ - hadc->Instance->PCSEL |= (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel) & 0x1FUL)); + hadc->Instance->PCSEL |= (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfigInjected->InjectedChannel) & 0x1FUL)); /* If auto-injected mode is disabled: no constraint */ - if (sConfigInjected->AutoInjectedConv == DISABLE) + if (pConfigInjected->AutoInjectedConv == DISABLE) { MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_JQM | ADC_CFGR_JDISCEN, - ADC_CFGR_INJECT_CONTEXT_QUEUE((uint32_t)sConfigInjected->QueueInjectedContext) | - ADC_CFGR_INJECT_DISCCONTINUOUS((uint32_t)sConfigInjected->InjectedDiscontinuousConvMode)); + ADC_CFGR_INJECT_CONTEXT_QUEUE((uint32_t)pConfigInjected->QueueInjectedContext) | + ADC_CFGR_INJECT_DISCCONTINUOUS((uint32_t)pConfigInjected->InjectedDiscontinuousConvMode)); } /* If auto-injected mode is enabled: Injected discontinuous setting is */ /* discarded. */ @@ -1945,7 +1941,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I { MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_JQM | ADC_CFGR_JDISCEN, - ADC_CFGR_INJECT_CONTEXT_QUEUE((uint32_t)sConfigInjected->QueueInjectedContext)); + ADC_CFGR_INJECT_CONTEXT_QUEUE((uint32_t)pConfigInjected->QueueInjectedContext)); } } @@ -1966,10 +1962,10 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I { /* If injected group external triggers are disabled (set to injected */ /* software start): no constraint */ - if ((sConfigInjected->ExternalTrigInjecConv == ADC_INJECTED_SOFTWARE_START) - || (sConfigInjected->ExternalTrigInjecConvEdge == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE)) + if ((pConfigInjected->ExternalTrigInjecConv == ADC_INJECTED_SOFTWARE_START) + || (pConfigInjected->ExternalTrigInjecConvEdge == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE)) { - if (sConfigInjected->AutoInjectedConv == ENABLE) + if (pConfigInjected->AutoInjectedConv == ENABLE) { SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO); } @@ -1982,7 +1978,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I /* due to injected group external triggers enabled, error is reported. */ else { - if (sConfigInjected->AutoInjectedConv == ENABLE) + if (pConfigInjected->AutoInjectedConv == ENABLE) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); @@ -1995,10 +1991,10 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I } } - if (sConfigInjected->InjecOversamplingMode == ENABLE) + if (pConfigInjected->InjecOversamplingMode == ENABLE) { - assert_param(IS_ADC_OVERSAMPLING_RATIO(sConfigInjected->InjecOversampling.Ratio)); - assert_param(IS_ADC_RIGHT_BIT_SHIFT(sConfigInjected->InjecOversampling.RightBitShift)); + assert_param(IS_ADC_OVERSAMPLING_RATIO(pConfigInjected->InjecOversampling.Ratio)); + assert_param(IS_ADC_RIGHT_BIT_SHIFT(pConfigInjected->InjecOversampling.RightBitShift)); /* JOVSE must be reset in case of triggered regular mode */ assert_param(!(READ_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_TROVS) == (ADC_CFGR2_ROVSE | ADC_CFGR2_TROVS))); @@ -2013,8 +2009,8 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I ADC_CFGR2_OVSR | ADC_CFGR2_OVSS, ADC_CFGR2_JOVSE | - ((sConfigInjected->InjecOversampling.Ratio - 1UL) << ADC_CFGR2_OSR_Pos) | - sConfigInjected->InjecOversampling.RightBitShift + ((pConfigInjected->InjecOversampling.Ratio - 1UL) << ADC_CFGR2_OSR_Pos) | + pConfigInjected->InjecOversampling.RightBitShift ); } else @@ -2024,25 +2020,25 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I } /* Set sampling time of the selected ADC channel */ - LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfigInjected->InjectedChannel, sConfigInjected->InjectedSamplingTime); + LL_ADC_SetChannelSamplingTime(hadc->Instance, pConfigInjected->InjectedChannel, pConfigInjected->InjectedSamplingTime); /* Configure the offset: offset enable/disable, channel, offset value */ /* Shift the offset with respect to the selected ADC resolution. */ /* Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0 */ - tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, sConfigInjected->InjectedOffset); + tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, pConfigInjected->InjectedOffset); - if (sConfigInjected->InjectedOffsetNumber != ADC_OFFSET_NONE) + if (pConfigInjected->InjectedOffsetNumber != ADC_OFFSET_NONE) { /* Set ADC selected offset number */ - LL_ADC_SetOffset(hadc->Instance, sConfigInjected->InjectedOffsetNumber, sConfigInjected->InjectedChannel, + LL_ADC_SetOffset(hadc->Instance, pConfigInjected->InjectedOffsetNumber, pConfigInjected->InjectedChannel, tmpOffsetShifted); /* Set ADC selected offset signed saturation */ - LL_ADC_SetOffsetSignedSaturation(hadc->Instance, sConfigInjected->InjectedOffsetNumber, (sConfigInjected->InjectedOffsetSignedSaturation == ENABLE) ? LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE : LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE); + LL_ADC_SetOffsetSignedSaturation(hadc->Instance, pConfigInjected->InjectedOffsetNumber, (pConfigInjected->InjectedOffsetSignedSaturation == ENABLE) ? LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE : LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE); /* Set ADC selected offset right shift */ - LL_ADC_SetDataRightShift(hadc->Instance, sConfigInjected->InjectedOffsetNumber, (sConfigInjected->InjectedOffsetRightShift == (uint32_t)ENABLE) ? LL_ADC_OFFSET_RSHIFT_ENABLE : LL_ADC_OFFSET_RSHIFT_DISABLE); + LL_ADC_SetDataRightShift(hadc->Instance, pConfigInjected->InjectedOffsetNumber, (pConfigInjected->InjectedOffsetRightShift == (uint32_t)ENABLE) ? LL_ADC_OFFSET_RSHIFT_ENABLE : LL_ADC_OFFSET_RSHIFT_DISABLE); } else @@ -2050,24 +2046,24 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I /* Scan each offset register to check if the selected channel is targeted. */ /* If this is the case, the corresponding offset number is disabled. */ if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1)) - == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel)) + == __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfigInjected->InjectedChannel)) { - LL_ADC_SetOffset(hadc->Instance, LL_ADC_OFFSET_1, sConfigInjected->InjectedChannel, LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE); + LL_ADC_SetOffset(hadc->Instance, LL_ADC_OFFSET_1, pConfigInjected->InjectedChannel, LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE); } if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2)) - == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel)) + == __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfigInjected->InjectedChannel)) { - LL_ADC_SetOffset(hadc->Instance, LL_ADC_OFFSET_2, sConfigInjected->InjectedChannel, LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE); + LL_ADC_SetOffset(hadc->Instance, LL_ADC_OFFSET_2, pConfigInjected->InjectedChannel, LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE); } if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3)) - == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel)) + == __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfigInjected->InjectedChannel)) { - LL_ADC_SetOffset(hadc->Instance, LL_ADC_OFFSET_4, sConfigInjected->InjectedChannel, LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE); + LL_ADC_SetOffset(hadc->Instance, LL_ADC_OFFSET_4, pConfigInjected->InjectedChannel, LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE); } if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4)) - == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel)) + == __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfigInjected->InjectedChannel)) { - LL_ADC_SetOffset(hadc->Instance, LL_ADC_OFFSET_4, sConfigInjected->InjectedChannel, LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE); + LL_ADC_SetOffset(hadc->Instance, LL_ADC_OFFSET_4, pConfigInjected->InjectedChannel, LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE); } } @@ -2080,16 +2076,16 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) { /* Set mode single-ended or differential input of the selected ADC channel */ - LL_ADC_SetChannelSingleDiff(hadc->Instance, sConfigInjected->InjectedChannel, sConfigInjected->InjectedSingleDiff); + LL_ADC_SetChannelSingleDiff(hadc->Instance, pConfigInjected->InjectedChannel, pConfigInjected->InjectedSingleDiff); /* Configuration of differential mode */ /* Note: ADC channel number masked with value "0x1F" to ensure shift value within 32 bits range */ - if (sConfigInjected->InjectedSingleDiff == ADC_DIFFERENTIAL_ENDED) + if (pConfigInjected->InjectedSingleDiff == ADC_DIFFERENTIAL_ENDED) { /* Set sampling time of the selected ADC channel */ LL_ADC_SetChannelSamplingTime(hadc->Instance, - (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfigInjected->InjectedChannel) - + 1UL) & 0x1FUL)), sConfigInjected->InjectedSamplingTime); + (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)pConfigInjected->InjectedChannel) + + 1UL) & 0x1FUL)), pConfigInjected->InjectedSamplingTime); } /* Management of internal measurement channels: Vbat/VrefInt/TempSensor/VddCore */ @@ -2098,7 +2094,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I /* Note: these internal measurement paths can be disabled using */ /* HAL_ADC_DeInit(). */ - if (__LL_ADC_IS_CHANNEL_INTERNAL(sConfigInjected->InjectedChannel)) + if (__LL_ADC_IS_CHANNEL_INTERNAL(pConfigInjected->InjectedChannel)) { /* Configuration of common ADC parameters (continuation) */ /* Software is allowed to change common parameters only when all ADCs */ @@ -2109,7 +2105,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I /* If the requested internal measurement path has already been enabled, */ /* bypass the configuration processing. */ - if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL)) + if ((pConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL)) { if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc)) { @@ -2120,28 +2116,28 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I /* Note: Variable divided by 2 to compensate partially */ /* CPU processing cycles, scaling in us split to not */ /* exceed 32 bits register capacity and handle low frequency. */ - wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * (SystemCoreClock / (100000UL * 2UL))); + wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); while(wait_loop_index != 0UL) { wait_loop_index--; } } } - else if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL)) + else if ((pConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL)) { if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc)) { LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VBAT | tmp_config_internal_channel); } } - else if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL)) + else if ((pConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL)) { if (ADC_VREFINT_INSTANCE(hadc)) { LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VREFINT | tmp_config_internal_channel); } } - else if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_VCORE) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VDDCORE) == 0UL)) + else if ((pConfigInjected->InjectedChannel == ADC_CHANNEL_VCORE) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VDDCORE) == 0UL)) { if (ADC_VDDCORE_INSTANCE(hadc)) { @@ -2167,10 +2163,8 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I } - /* Process unlocked */ __HAL_UNLOCK(hadc); - /* Return function status */ return tmp_hal_status; } @@ -2188,28 +2182,32 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I * @note To move back configuration from multimode to single mode, ADC must * be reset (using function HAL_ADC_Init() ). * @param hadc Master ADC handle - * @param multimode Structure of ADC multimode configuration + * @param pmultimode Structure of ADC multimode configuration * @retval HAL status */ -HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode) +HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *pmultimode) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; ADC_Common_TypeDef *tmpADC_Common; - ADC_HandleTypeDef tmphadcSlave; + ADC_HandleTypeDef tmphadcSlave={0}; uint32_t tmphadcSlave_conversion_on_going; /* Check the parameters */ assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance)); - assert_param(IS_ADC_MULTIMODE(multimode->Mode)); - if (multimode->Mode != ADC_MODE_INDEPENDENT) + assert_param(IS_ADC_MULTIMODE(pmultimode->Mode)); + if (pmultimode->Mode != ADC_MODE_INDEPENDENT) { - assert_param(IS_ADC_DUAL_DATA_MODE(multimode->DualModeData)); - assert_param(IS_ADC_SAMPLING_DELAY(multimode->TwoSamplingDelay)); + assert_param(IS_ADC_DUAL_DATA_MODE(pmultimode->DualModeData)); + assert_param(IS_ADC_SAMPLING_DELAY(pmultimode->TwoSamplingDelay)); } /* Process locked */ __HAL_LOCK(hadc); + /* Temporary handle minimum initialization */ + __HAL_ADC_RESET_HANDLE_STATE(&tmphadcSlave); + ADC_CLEAR_ERRORCODE(&tmphadcSlave); + ADC_MULTI_SLAVE(hadc, &tmphadcSlave); if (tmphadcSlave.Instance == NULL) @@ -2217,7 +2215,6 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_ /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); - /* Process unlocked */ __HAL_UNLOCK(hadc); return HAL_ERROR; @@ -2237,9 +2234,9 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_ /* If multimode is selected, configure all multimode parameters. */ /* Otherwise, reset multimode parameters (can be used in case of */ /* transition from multimode to independent mode). */ - if (multimode->Mode != ADC_MODE_INDEPENDENT) + if (pmultimode->Mode != ADC_MODE_INDEPENDENT) { - MODIFY_REG(tmpADC_Common->CCR, ADC_CCR_DAMDF, multimode->DualModeData); + MODIFY_REG(tmpADC_Common->CCR, ADC_CCR_DAMDF, pmultimode->DualModeData); /* Parameters that can be updated only when ADC is disabled: */ /* - Multimode mode selection */ @@ -2257,8 +2254,8 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_ MODIFY_REG(tmpADC_Common->CCR, ADC_CCR_DUAL | ADC_CCR_DELAY, - multimode->Mode | - multimode->TwoSamplingDelay + pmultimode->Mode | + pmultimode->TwoSamplingDelay ); } } @@ -2285,10 +2282,8 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_ tmp_hal_status = HAL_ERROR; } - /* Process unlocked */ __HAL_UNLOCK(hadc); - /* Return function status */ return tmp_hal_status; } #endif /* ADC_MULTIMODE_SUPPORT */ diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_cortex.c b/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_cortex.c index 84453c1677..185e3f0df4 100644 --- a/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_cortex.c +++ b/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_cortex.c @@ -436,4 +436,3 @@ __weak void HAL_SYSTICK_Callback(void) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_crc.c b/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_crc.c index c062f53927..b679139d48 100644 --- a/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_crc.c +++ b/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_crc.c @@ -62,8 +62,8 @@ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /** @defgroup CRC_Private_Functions CRC Private Functions - * @{ - */ + * @{ + */ static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength); static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength); /** @@ -77,8 +77,8 @@ static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint3 */ /** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions. - * + * @brief Initialization and Configuration functions. + * @verbatim =============================================================================== ##### Initialization and de-initialization functions ##### @@ -250,8 +250,8 @@ __weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc) */ /** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions - * @brief management functions. - * + * @brief management functions. + * @verbatim =============================================================================== ##### Peripheral Control functions ##### @@ -385,8 +385,8 @@ uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t */ /** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions - * @brief Peripheral State functions. - * + * @brief Peripheral State functions. + * @verbatim =============================================================================== ##### Peripheral State functions ##### @@ -418,8 +418,8 @@ HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc) */ /** @addtogroup CRC_Private_Functions - * @{ - */ + * @{ + */ /** * @brief Enter 8-bit input data to the CRC calculator. diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_crc_ex.c b/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_crc_ex.c index 533ae0875c..e82f0439f2 100644 --- a/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_crc_ex.c +++ b/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_crc_ex.c @@ -22,7 +22,7 @@ ##### How to use this driver ##### ================================================================================ [..] - (+) Set user-defined generating polynomial thru HAL_CRCEx_Polynomial_Set() + (+) Set user-defined generating polynomial through HAL_CRCEx_Polynomial_Set() (+) Configure Input or Output data inversion @endverbatim diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_dma.c b/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_dma.c index 800e5343a0..677c3af789 100644 --- a/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_dma.c +++ b/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_dma.c @@ -175,7 +175,7 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) { uint32_t registerValue; uint32_t tickstart = HAL_GetTick(); - DMA_Base_Registers *regs; + DMA_Base_Registers *regs_dma; /* Check the DMA peripheral handle */ if (hdma == NULL) @@ -193,11 +193,10 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) assert_param(IS_DMA_MODE(hdma->Init.Mode)); assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); - - if (IS_DMA_INSTANCE(hdma) != RESET) /*DMA2/DMA1 stream */ + if(IS_DMA_INSTANCE(hdma) != 0U) /* DMA1 or DMA2 instance */ { -// assert_param(IS_DMA_REQUEST(hdma->Init.Request)); + assert_param(IS_DMA_REQUEST(hdma->Init.Request)); assert_param(IS_DMA_FIFO_MODE_STATE(hdma->Init.FIFOMode)); /* Check the memory burst, peripheral burst and FIFO threshold parameters only when FIFO mode is enabled */ @@ -208,12 +207,14 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst)); } - /* Allocate lock resource */ - __HAL_UNLOCK(hdma); + /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; + /* Allocate lock resource */ + __HAL_UNLOCK(hdma); + /* Disable the peripheral */ __HAL_DMA_DISABLE(hdma); @@ -295,10 +296,10 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */ - regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma); + regs_dma = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma); /* Clear all interrupt flags */ - regs->IFCR = 0x3FUL << hdma->StreamIndex; + regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU); } else { @@ -333,8 +334,7 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) if ((hdma->Init.Request >= DMA_REQUEST_GENERATOR0) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR7)) { /* Initialize parameters for DMAMUX request generator : - DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask - */ + DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask */ DMA_CalcDMAMUXRequestGenBaseAndMask(hdma); /* Reset the DMAMUX request generator register*/ @@ -367,7 +367,7 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) */ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) { - DMA_Base_Registers *regs; + DMA_Base_Registers *regs_dma; /* Check the DMA peripheral handle */ if (hdma == NULL) @@ -375,16 +375,6 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) return HAL_ERROR; } - /* Check the DMA peripheral state */ - if (hdma->State == HAL_DMA_STATE_BUSY) - { - /* Set the error code to busy */ - hdma->ErrorCode = HAL_DMA_ERROR_BUSY; - - /* Return error status */ - return HAL_ERROR; - } - /* Disable the selected DMA Streamx */ __HAL_DMA_DISABLE(hdma); @@ -408,15 +398,15 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) ((DMA_Stream_TypeDef *)hdma->Instance)->FCR = (uint32_t)0x00000021U; /* Get DMA steam Base Address */ - regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma); + regs_dma = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma); /* Clear all interrupt flags at correct offset within the register */ - regs->IFCR = 0x3FUL << hdma->StreamIndex; + regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU); /* Initialize parameters for DMAMUX channel : DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask */ DMA_CalcDMAMUXChannelBaseAndMask(hdma); - if(hdma->DMAmuxChannel != NULL) + if(hdma->DMAmuxChannel != 0U) { /* Resett he DMAMUX channel that corresponds to the DMA stream */ hdma->DMAmuxChannel->CCR = 0U; @@ -428,8 +418,7 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) if ((hdma->Init.Request >= DMA_REQUEST_GENERATOR0) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR7)) { /* Initialize parameters for DMAMUX request generator : - DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask - */ + DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask */ DMA_CalcDMAMUXRequestGenBaseAndMask(hdma); /* Reset the DMAMUX request generator register*/ @@ -530,12 +519,12 @@ HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, ui } else { - /* Process unlocked */ - __HAL_UNLOCK(hdma); - /* Set the error code to busy */ hdma->ErrorCode = HAL_DMA_ERROR_BUSY; + /* Process unlocked */ + __HAL_UNLOCK(hdma); + /* Return error status */ status = HAL_ERROR; } @@ -583,8 +572,6 @@ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, /* Enable Common interrupts*/ MODIFY_REG(((DMA_Stream_TypeDef *)hdma->Instance)->CR, (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT), (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME)); - ((DMA_Stream_TypeDef *)hdma->Instance)->FCR |= DMA_IT_FE; - if (hdma->XferHalfCpltCallback != NULL) { /*Enable Half Transfer IT if corresponding Callback is set*/ @@ -598,7 +585,7 @@ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE; } - if(hdma->DMAmuxRequestGen != NULL) + if(hdma->DMAmuxRequestGen != 0U) { /* if using DMAMUX request generator, enable the DMAMUX request generator overrun IT*/ /* enable the request gen overrun IT*/ @@ -611,12 +598,12 @@ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, } else { - /* Process unlocked */ - __HAL_UNLOCK(hdma); - /* Set the error code to busy */ hdma->ErrorCode = HAL_DMA_ERROR_BUSY; + /* Process unlocked */ + __HAL_UNLOCK(hdma); + /* Return error status */ status = HAL_ERROR; } @@ -639,7 +626,7 @@ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) { /* calculate DMA base and stream number */ - DMA_Base_Registers *regs = NULL; + DMA_Base_Registers *regs_dma; const __IO uint32_t *enableRegister; uint32_t tickstart = HAL_GetTick(); @@ -666,7 +653,6 @@ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT); ((DMA_Stream_TypeDef *)hdma->Instance)->FCR &= ~(DMA_IT_FE); - regs = (DMA_Base_Registers *)hdma->StreamBaseAddress; enableRegister = (__IO uint32_t *)(&(((DMA_Stream_TypeDef *)hdma->Instance)->CR)); /* disable the DMAMUX sync overrun IT*/ @@ -684,21 +670,22 @@ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - /* Change the DMA state */ hdma->State = HAL_DMA_STATE_ERROR; + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + return HAL_ERROR; } } - regs->IFCR = 0x3FUL << hdma->StreamIndex; + regs_dma = (DMA_Base_Registers *)hdma->StreamBaseAddress; + regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU); /* Clear the DMAMUX synchro overrun flag */ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; - if(hdma->DMAmuxRequestGen != NULL) + if(hdma->DMAmuxRequestGen != 0U) { /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/ /* disable the request gen overrun IT*/ @@ -708,11 +695,10 @@ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; } - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - /* Change the DMA state*/ hdma->State = HAL_DMA_STATE_READY; + /* Process Unlocked */ + __HAL_UNLOCK(hdma); } return HAL_OK; } @@ -753,7 +739,7 @@ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @param CompleteLevel: Specifies the DMA level complete. - * @note The polling mode is kept in this version for legacy. it is recommanded to use the IT model instead. + * @note The polling mode is kept in this version for legacy. it is recommended to use the IT model instead. * This model could be used for debug purpose. * @note The HAL_DMA_PollForTransfer API cannot be used in circular and double buffering mode (automatic circular mode). * @param Timeout: Timeout duration. @@ -795,19 +781,59 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_Level if (CompleteLevel == HAL_DMA_FULL_TRANSFER) { /* Transfer Complete flag */ - cpltlevel_mask = DMA_FLAG_TCIF0_4 << hdma->StreamIndex; + cpltlevel_mask = DMA_FLAG_TCIF0_4 << (hdma->StreamIndex & 0x1FU); } else { /* Half Transfer Complete flag */ - cpltlevel_mask = DMA_FLAG_HTIF0_4 << hdma->StreamIndex; + cpltlevel_mask = DMA_FLAG_HTIF0_4 << (hdma->StreamIndex & 0x1FU); } isr_reg = &(((DMA_Base_Registers *)hdma->StreamBaseAddress)->ISR); ifcr_reg = &(((DMA_Base_Registers *)hdma->StreamBaseAddress)->IFCR); - while ((((*isr_reg) & cpltlevel_mask) == 0U) && ((hdma->ErrorCode & HAL_DMA_ERROR_TE) == 0U)) + while(((*isr_reg) & cpltlevel_mask) == 0U) { + if(IS_DMA_INSTANCE(hdma) != 0U) /* DMA1 or DMA2 instance */ + { + if(((*isr_reg) & (DMA_FLAG_FEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) + { + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_FE; + + /* Clear the FIFO error flag */ + (*ifcr_reg) = DMA_FLAG_FEIF0_4 << (hdma->StreamIndex & 0x1FU); + } + + if(((*isr_reg) & (DMA_FLAG_DMEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) + { + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_DME; + + /* Clear the Direct Mode error flag */ + (*ifcr_reg) = DMA_FLAG_DMEIF0_4 << (hdma->StreamIndex & 0x1FU); + } + + if(((*isr_reg) & (DMA_FLAG_TEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) + { + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_TE; + + /* Clear the transfer error flag */ + (*ifcr_reg) = DMA_FLAG_TEIF0_4 << (hdma->StreamIndex & 0x1FU); + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + } + + } + /* Check for the Timeout (Not applicable in circular mode)*/ if (Timeout != HAL_MAX_DELAY) { @@ -817,22 +843,22 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_Level hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; /* if timeout then abort the current transfer */ - if (HAL_DMA_Abort(hdma) == HAL_OK) - { + /* No need to check return value: as in this case we will return HAL_ERROR with HAL_DMA_ERROR_TIMEOUT error code */ + (void) HAL_DMA_Abort(hdma); /* Note that the Abort function will - Clear the transfer error flags - Unlock - Set the State */ - } + return HAL_ERROR; } } /*Check for DMAMUX Request generator (if used) overrun status */ - if(hdma->DMAmuxRequestGen != NULL) + if(hdma->DMAmuxRequestGen != 0U) { /* if using DMAMUX request generator Check for DMAMUX request generator overrun */ if ((hdma->DMAmuxRequestGenStatus->RGSR & hdma->DMAmuxRequestGenStatusMask) != 0U) @@ -855,78 +881,27 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_Level hdma->ErrorCode |= HAL_DMA_ERROR_SYNC; } - if (((*isr_reg) & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != 0U) - { - /* Update error code */ - hdma->ErrorCode |= HAL_DMA_ERROR_TE; - /* Clear the transfer error flag */ - (*ifcr_reg) = DMA_FLAG_TEIF0_4 << hdma->StreamIndex; - } - if (((*isr_reg) & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != 0U) + /* Get the level transfer complete flag */ + if(CompleteLevel == HAL_DMA_FULL_TRANSFER) { - /* Update error code */ - hdma->ErrorCode |= HAL_DMA_ERROR_FE; - - /* Clear the FIFO error flag */ - (*ifcr_reg) = DMA_FLAG_FEIF0_4 << hdma->StreamIndex; - } - - if (((*isr_reg) & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != 0U) + /* Clear the half transfer and transfer complete flags */ + if(IS_DMA_INSTANCE(hdma) != 0U) /* DMA1 or DMA2 instance */ { - /* Update error code */ - hdma->ErrorCode |= HAL_DMA_ERROR_DME; - - /* Clear the Direct Mode error flag */ - (*ifcr_reg) = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex; + (*ifcr_reg) = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << (hdma->StreamIndex & 0x1FU); } - } - - - if (hdma->ErrorCode != HAL_DMA_ERROR_NONE) - { - if ((hdma->ErrorCode & HAL_DMA_ERROR_TE) != 0U) - { - if (IS_DMA_INSTANCE(hdma) != RESET) /* DMA : DMA1 or DMA2 */ - { - if (HAL_DMA_Abort(hdma) == HAL_OK) - { - /* - Note that the Abort function will - - Clear the transfer error flags - - Unlock - - Set the State - */ - } - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - - /* Change the DMA state */ - hdma->State = HAL_DMA_STATE_READY; - } - - return HAL_ERROR; - } - } - - /* Get the level transfer complete flag */ - if (CompleteLevel == HAL_DMA_FULL_TRANSFER) - { - /* Clear the half transfer and transfer complete flags */ - (*ifcr_reg) = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << hdma->StreamIndex; + hdma->State = HAL_DMA_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hdma); - - hdma->State = HAL_DMA_STATE_READY; } else /*CompleteLevel = HAL_DMA_HALF_TRANSFER*/ { /* Clear the half transfer and transfer complete flags */ - (*ifcr_reg) = (DMA_FLAG_HTIF0_4) << hdma->StreamIndex; + if(IS_DMA_INSTANCE(hdma) != 0U) /* DMA1 or DMA2 instance */ + { + (*ifcr_reg) = (DMA_FLAG_HTIF0_4) << (hdma->StreamIndex & 0x1FU); + } } return status; @@ -940,19 +915,19 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_Level */ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) { - uint32_t tmpisr; + uint32_t tmpisr_dma; __IO uint32_t count = 0U; uint32_t timeout = SystemCoreClock / 9600U; /* calculate DMA base and stream number */ - DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress; + DMA_Base_Registers *regs_dma = (DMA_Base_Registers *)hdma->StreamBaseAddress; - tmpisr = regs->ISR; + tmpisr_dma = regs_dma->ISR; - if (IS_DMA_INSTANCE(hdma) != RESET) /*D2 domain DMA : DMA1 or DMA2*/ + if(IS_DMA_INSTANCE(hdma) != 0U) /* DMA1 or DMA2 instance */ { /* Transfer Error Interrupt management ***************************************/ - if ((tmpisr & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != 0U) + if ((tmpisr_dma & (DMA_FLAG_TEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) { if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != 0U) { @@ -960,43 +935,43 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TE); /* Clear the transfer error flag */ - regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex; + regs_dma->IFCR = DMA_FLAG_TEIF0_4 << (hdma->StreamIndex & 0x1FU); /* Update error code */ hdma->ErrorCode |= HAL_DMA_ERROR_TE; } } /* FIFO Error Interrupt management ******************************************/ - if ((tmpisr & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != 0U) + if ((tmpisr_dma & (DMA_FLAG_FEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) { if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_FE) != 0U) { /* Clear the FIFO error flag */ - regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex; + regs_dma->IFCR = DMA_FLAG_FEIF0_4 << (hdma->StreamIndex & 0x1FU); /* Update error code */ hdma->ErrorCode |= HAL_DMA_ERROR_FE; } } /* Direct Mode Error Interrupt management ***********************************/ - if ((tmpisr & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != 0U) + if ((tmpisr_dma & (DMA_FLAG_DMEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) { if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DME) != 0U) { /* Clear the direct mode error flag */ - regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex; + regs_dma->IFCR = DMA_FLAG_DMEIF0_4 << (hdma->StreamIndex & 0x1FU); /* Update error code */ hdma->ErrorCode |= HAL_DMA_ERROR_DME; } } /* Half Transfer Complete Interrupt management ******************************/ - if ((tmpisr & (DMA_FLAG_HTIF0_4 << hdma->StreamIndex)) != 0U) + if ((tmpisr_dma & (DMA_FLAG_HTIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) { if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != 0U) { /* Clear the half transfer complete flag */ - regs->IFCR = DMA_FLAG_HTIF0_4 << hdma->StreamIndex; + regs_dma->IFCR = DMA_FLAG_HTIF0_4 << (hdma->StreamIndex & 0x1FU); /* Multi_Buffering mode enabled */ if (((((DMA_Stream_TypeDef *)hdma->Instance)->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0U) @@ -1038,12 +1013,12 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) } } /* Transfer Complete Interrupt management ***********************************/ - if ((tmpisr & (DMA_FLAG_TCIF0_4 << hdma->StreamIndex)) != 0U) + if ((tmpisr_dma & (DMA_FLAG_TCIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) { if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != 0U) { /* Clear the transfer complete flag */ - regs->IFCR = DMA_FLAG_TCIF0_4 << hdma->StreamIndex; + regs_dma->IFCR = DMA_FLAG_TCIF0_4 << (hdma->StreamIndex & 0x1FU); if (HAL_DMA_STATE_ABORT == hdma->State) { @@ -1057,14 +1032,14 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) } /* Clear all interrupt flags at correct offset within the register */ - regs->IFCR = 0x3FUL << hdma->StreamIndex; - - /* Process Unlocked */ - __HAL_UNLOCK(hdma); + regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU); /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + if (hdma->XferAbortCallback != NULL) { hdma->XferAbortCallback(hdma); @@ -1101,11 +1076,10 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) /* Disable the transfer complete interrupt */ ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TC); - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; + /* Process Unlocked */ + __HAL_UNLOCK(hdma); } if (hdma->XferCpltCallback != NULL) @@ -1136,9 +1110,6 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) } while ((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U); - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - if ((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U) { /* Change the DMA state to error if DMA disable fails */ @@ -1149,6 +1120,8 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) /* Change the DMA state to Ready if DMA disable success */ hdma->State = HAL_DMA_STATE_READY; } + /* Process Unlocked */ + __HAL_UNLOCK(hdma); } if (hdma->XferErrorCallback != NULL) @@ -1168,9 +1141,9 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) * @brief Register callbacks * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. - * @param CallbackID: User Callback identifer + * @param CallbackID: User Callback identifier * a DMA_HandleTypeDef structure as parameter. - * @param pCallback: pointer to private callbacsk function which has pointer to + * @param pCallback: pointer to private callback function which has pointer to * a DMA_HandleTypeDef structure as parameter. * @retval HAL status */ @@ -1217,6 +1190,7 @@ HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_Call break; default: + status = HAL_ERROR; break; } } @@ -1236,7 +1210,7 @@ HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_Call * @brief UnRegister callbacks * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. - * @param CallbackID: User Callback identifer + * @param CallbackID: User Callback identifier * a HAL_DMA_CallbackIDTypeDef ENUM as parameter. * @retval HAL status */ @@ -1366,23 +1340,23 @@ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma) * @param SrcAddress: The source memory Buffer address * @param DstAddress: The destination memory Buffer address * @param DataLength: The length of data to be transferred from source to destination - * @retval HAL status + * @retval None */ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) { /* calculate DMA base and stream number */ - DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress; + DMA_Base_Registers *regs_dma = (DMA_Base_Registers *)hdma->StreamBaseAddress; /* Clear the DMAMUX synchro overrun flag */ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; - if(hdma->DMAmuxRequestGen != NULL) + if(hdma->DMAmuxRequestGen != 0U) { /* Clear the DMAMUX request generator overrun flag */ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; } /* Clear all interrupt flags at correct offset within the register */ - regs->IFCR = 0x3FUL << hdma->StreamIndex; + regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU); /* Clear DBM bit */ ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= (uint32_t)(~DMA_SxCR_DBM); @@ -1550,9 +1524,11 @@ static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma) { stream_number += 8U; } + hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_Channel0) + (stream_number * 4U))); hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus; - hdma->DMAmuxChannelStatusMask = 1UL << stream_number; + hdma->DMAmuxChannelStatusMask = 1UL << (stream_number & 0x1FU); + } /** @@ -1567,7 +1543,6 @@ static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma) if ((request >= DMA_REQUEST_GENERATOR0) && (request <= DMA_REQUEST_GENERATOR7)) { - /*DMA1 and DMA2 Streams use DMAMUX1 request generator blocks*/ hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_RequestGenerator0) + ((request - 1U) * 4U))); hdma->DMAmuxRequestGenStatus = DMAMUX1_RequestGenStatus; diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_dma_ex.c b/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_dma_ex.c index 07c01676ae..4baa6e733b 100644 --- a/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_dma_ex.c +++ b/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_dma_ex.c @@ -66,8 +66,6 @@ /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private Constants ---------------------------------------------------------*/ -#define DMAMUX_POSITION_CxCR_SE (uint32_t)POSITION_VAL(DMAMUX_CxCR_SE) /*!< Required for left shift of the DMAMUX SYNC enable/disable */ -#define DMAMUX_POSITION_CxCR_EGE (uint32_t)POSITION_VAL(DMAMUX_CxCR_EGE) /*!< Required for left shift of the DMAMUX SYNC EVENT enable/disable */ /* Private macros ------------------------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ /** @addtogroup DMAEx_Private_Functions @@ -128,10 +126,10 @@ HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t S /* Check the parameters */ assert_param(IS_DMA_BUFFER_SIZE(DataLength)); + assert_param(IS_DMA_STREAM_ALL_INSTANCE(hdma->Instance)); /* Memory-to-memory transfer not supported in double buffering mode */ - /* double buffering mode not supported for BDMA (D3 DMA) */ - if ((IS_DMA_INSTANCE(hdma) == 0U) || (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)) + if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY) { hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED; status = HAL_ERROR; @@ -149,7 +147,7 @@ HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t S /* Initialize the error code */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; - /* Enable the double buffer mode */ + /* Enable the Double buffer mode */ ((DMA_Stream_TypeDef *)hdma->Instance)->CR |= (uint32_t)DMA_SxCR_DBM; /* Configure DMA Stream destination address */ @@ -162,12 +160,12 @@ HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t S ifcRegister_Base = (uint32_t *)((uint32_t)(hdma->StreamBaseAddress + 8U)); /* Clear all flags */ - *ifcRegister_Base = 0x3FUL << hdma->StreamIndex; + *ifcRegister_Base = 0x3FUL << (hdma->StreamIndex & 0x1FU); /* Clear the DMAMUX synchro overrun flag */ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; - if(hdma->DMAmuxRequestGen != NULL) + if(hdma->DMAmuxRequestGen != 0U) { /* Clear the DMAMUX request generator overrun flag */ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; @@ -205,9 +203,10 @@ HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_ /* Check the parameters */ assert_param(IS_DMA_BUFFER_SIZE(DataLength)); + assert_param(IS_DMA_STREAM_ALL_INSTANCE(hdma->Instance)); /* Memory-to-memory transfer not supported in double buffering mode */ - if ((IS_DMA_INSTANCE(hdma) == 0U) || (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)) + if(hdma->Init.Direction == DMA_MEMORY_TO_MEMORY) { hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED; return HAL_ERROR; @@ -237,12 +236,12 @@ HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_ ifcRegister_Base = (uint32_t *)((uint32_t)(hdma->StreamBaseAddress + 8U)); /* Clear all flags */ - *ifcRegister_Base = 0x3FUL << hdma->StreamIndex; + *ifcRegister_Base = 0x3FUL << (hdma->StreamIndex & 0x1FU); /* Clear the DMAMUX synchro overrun flag */ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; - if(hdma->DMAmuxRequestGen != NULL) + if(hdma->DMAmuxRequestGen != 0U) { /* Clear the DMAMUX request generator overrun flag */ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; @@ -252,7 +251,7 @@ HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_ MODIFY_REG(((DMA_Stream_TypeDef *)hdma->Instance)->CR, (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT), (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME)); ((DMA_Stream_TypeDef *)hdma->Instance)->FCR |= DMA_IT_FE; - if (hdma->XferHalfCpltCallback != NULL) + if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL)) { /*Enable Half Transfer IT if corresponding Callback is set*/ ((DMA_Stream_TypeDef *)hdma->Instance)->CR |= DMA_IT_HT; @@ -265,7 +264,7 @@ HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_ hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE; } - if(hdma->DMAmuxRequestGen != NULL) + if(hdma->DMAmuxRequestGen != 0U) { /* if using DMAMUX request generator, enable the DMAMUX request generator overrun IT*/ /* enable the request gen overrun IT*/ @@ -354,10 +353,10 @@ HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSy /* Set the new synchronization parameters (and keep the request ID filled during the Init)*/ MODIFY_REG(hdma->DMAmuxChannel->CCR, \ (~DMAMUX_CxCR_DMAREQ_ID), \ - (syncSignalID << POSITION_VAL(DMAMUX_CxCR_SYNC_ID)) | \ - ((pSyncConfig->RequestNumber - 1U) << POSITION_VAL(DMAMUX_CxCR_NBREQ)) | \ - syncPolarity | ((uint32_t)pSyncConfig->SyncEnable << DMAMUX_POSITION_CxCR_SE) | \ - ((uint32_t)pSyncConfig->EventEnable << DMAMUX_POSITION_CxCR_EGE)); + (syncSignalID << DMAMUX_CxCR_SYNC_ID_Pos) | \ + ((pSyncConfig->RequestNumber - 1U) << DMAMUX_CxCR_NBREQ_Pos) | \ + syncPolarity | ((uint32_t)pSyncConfig->SyncEnable << DMAMUX_CxCR_SE_Pos) | \ + ((uint32_t)pSyncConfig->EventEnable << DMAMUX_CxCR_EGE_Pos)); /* Process Locked */ __HAL_UNLOCK(hdma); @@ -386,6 +385,7 @@ HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSy HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator(DMA_HandleTypeDef *hdma, HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig) { HAL_StatusTypeDef status; + HAL_DMA_StateTypeDef temp_state = hdma->State; /* Check the parameters */ assert_param(IS_DMA_STREAM_ALL_INSTANCE(hdma->Instance)); @@ -398,7 +398,7 @@ HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator(DMA_HandleTypeDef *hdma, H /* check if the DMA state is ready and DMA is using a DMAMUX request generator block */ - if(hdma->DMAmuxRequestGen == NULL) + if(hdma->DMAmuxRequestGen == 0U) { /* Set the error code to busy */ hdma->ErrorCode = HAL_DMA_ERROR_PARAM; @@ -406,7 +406,7 @@ HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator(DMA_HandleTypeDef *hdma, H /* error status */ status = HAL_ERROR; } - else if ((hdma->State == HAL_DMA_STATE_READY) && ((hdma->DMAmuxRequestGen->RGCR & DMAMUX_RGxCR_GE) == 0U)) + else if(((hdma->DMAmuxRequestGen->RGCR & DMAMUX_RGxCR_GE) == 0U) && (temp_state == HAL_DMA_STATE_READY)) { /* RequestGenerator must be disable prior to the configuration i.e GE bit is 0 */ @@ -415,7 +415,7 @@ HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator(DMA_HandleTypeDef *hdma, H /* Set the request generator new parameters*/ hdma->DMAmuxRequestGen->RGCR = pRequestGeneratorConfig->SignalID | \ - ((pRequestGeneratorConfig->RequestNumber - 1U) << POSITION_VAL(DMAMUX_RGxCR_GNBREQ)) | \ + ((pRequestGeneratorConfig->RequestNumber - 1U) << DMAMUX_RGxCR_GNBREQ_Pos)| \ pRequestGeneratorConfig->Polarity; /* Process Locked */ __HAL_UNLOCK(hdma); @@ -446,9 +446,8 @@ HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator(DMA_HandleTypeDef *hdma) assert_param(IS_DMA_STREAM_ALL_INSTANCE(hdma->Instance)); /* check if the DMA state is ready - and DMA is using a DMAMUX request generator block - */ - if((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != NULL)) + and DMA is using a DMAMUX request generator block */ + if((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != 0U)) { /* Enable the request generator*/ @@ -474,9 +473,8 @@ HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator(DMA_HandleTypeDef *hdma) assert_param(IS_DMA_STREAM_ALL_INSTANCE(hdma->Instance)); /* check if the DMA state is ready - and DMA is using a DMAMUX request generator block - */ - if((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != NULL)) + and DMA is using a DMAMUX request generator block */ + if((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != 0U)) { /* Disable the request generator*/ @@ -517,7 +515,7 @@ void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma) } } - if(hdma->DMAmuxRequestGen != NULL) + if(hdma->DMAmuxRequestGen != 0) { /* if using a DMAMUX request generator block Check for DMAMUX request generator overrun */ if ((hdma->DMAmuxRequestGenStatus->RGSR & hdma->DMAmuxRequestGenStatusMask) != 0U) @@ -564,6 +562,8 @@ void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma) */ static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) { + assert_param(IS_DMA_STREAM_ALL_INSTANCE(hdma->Instance)); + /* Configure DMA Stream data length */ ((DMA_Stream_TypeDef *)hdma->Instance)->NDTR = DataLength; diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_exti.c b/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_exti.c index 10728218cf..68eeba7f29 100644 --- a/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_exti.c +++ b/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_exti.c @@ -174,7 +174,7 @@ HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigT maskline = (1uL << linepos); /* Configure triggers for configurable lines */ - if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u) + if ((pExtiConfig->Line & EXTI_CONFIG) != 0x0u) { assert_param(IS_EXTI_TRIGGER(pExtiConfig->Trigger)); @@ -183,7 +183,7 @@ HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigT regval = *regaddr; /* Mask or set line */ - if ((pExtiConfig->Trigger & EXTI_TRIGGER_RISING) != 0x00u) + if ((pExtiConfig->Trigger & EXTI_TRIGGER_RISING) != 0x0u) { regval |= maskline; } @@ -200,7 +200,7 @@ HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigT regval = *regaddr; /* Mask or set line */ - if ((pExtiConfig->Trigger & EXTI_TRIGGER_FALLING) != 0x00u) + if ((pExtiConfig->Trigger & EXTI_TRIGGER_FALLING) != 0x0u) { regval |= maskline; } @@ -225,15 +225,16 @@ HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigT } } + /*Set Interrupt And Event Mask for Core 1 if configuration for Core 1 given into parameter mode */ - if ((pExtiConfig->Mode & EXTI_MODE_C1) != 0x00u) + if ((pExtiConfig->Mode & EXTI_MODE_C1) != 0x0u) { regaddr = (&EXTI->C1IMR1 + (EXTI_MODE_OFFSET * offset)); regval = *regaddr; /* Mask or set line */ - if ((pExtiConfig->Mode & EXTI_MODE_INTERRUPT) != 0x00u) + if ((pExtiConfig->Mode & EXTI_MODE_INTERRUPT) != 0x0u) { regval |= maskline; } @@ -244,18 +245,17 @@ HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigT /* Store interrupt mode */ *regaddr = regval; - } /*Set Interrupt And Event Mask for Core 2 if configuration for Core 2 given into parameter mode */ - if ((pExtiConfig->Mode & EXTI_MODE_C2) != 0x00u) + if ((pExtiConfig->Mode & EXTI_MODE_C2) != 0x0u) { regaddr = (&EXTI->C2IMR1 + (EXTI_MODE_OFFSET * offset)); regval = *regaddr; /* Mask or set line */ - if ((pExtiConfig->Mode & EXTI_MODE_INTERRUPT) != 0x00u) + if ((pExtiConfig->Mode & EXTI_MODE_INTERRUPT) != 0x0u) { regval |= maskline; } @@ -275,7 +275,7 @@ HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigT regval = *regaddr; /* Mask or set line */ - if ((pExtiConfig->Mode & EXTI_MODE_EVENT) != 0x00u) + if ((pExtiConfig->Mode & EXTI_MODE_EVENT) != 0x0u) { regval |= maskline; } @@ -323,12 +323,13 @@ HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigT linepos = (pExtiConfig->Line & EXTI_PIN_MASK); maskline = (1uL << linepos); + /* 1] Get core 1 mode : interrupt */ regaddr = (&EXTI->C1IMR1 + (EXTI_MODE_OFFSET * offset)); regval = *regaddr; /* Check if selected line is enable */ - if ((regval & maskline) != 0x00u) + if ((regval & maskline) != 0x0u) { pExtiConfig->Mode = EXTI_MODE_C1_INTERRUPT; } @@ -342,7 +343,7 @@ HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigT regval = *regaddr; /* Check if selected line is enable */ - if ((regval & maskline) != 0x00u) + if ((regval & maskline) != 0x0u) { pExtiConfig->Mode |= EXTI_MODE_C2_INTERRUPT; } @@ -356,33 +357,33 @@ HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigT regval = *regaddr; /* Check if selected line is enable */ - if ((regval & maskline) != 0x00u) + if ((regval & maskline) != 0x0u) { pExtiConfig->Mode |= EXTI_MODE_C2_EVENT; } + /* Get default Trigger and GPIOSel configuration */ + pExtiConfig->Trigger = EXTI_TRIGGER_NONE; + pExtiConfig->GPIOSel = 0x0u; + /* 2] Get trigger for configurable lines : rising */ - if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u) + if ((pExtiConfig->Line & EXTI_CONFIG) != 0x0u) { regaddr = (&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset)); regval = *regaddr; /* Check if configuration of selected line is enable */ - if ((regval & maskline) != 0x00u) + if ((regval & maskline) != 0x0u) { pExtiConfig->Trigger = EXTI_TRIGGER_RISING; } - else - { - pExtiConfig->Trigger = EXTI_TRIGGER_NONE; - } /* Get falling configuration */ regaddr = (&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset)); regval = *regaddr; /* Check if configuration of selected line is enable */ - if ((regval & maskline) != 0x00u) + if ((regval & maskline) != 0x0u) { pExtiConfig->Trigger |= EXTI_TRIGGER_FALLING; } @@ -395,15 +396,6 @@ HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigT regval = EXTI->EXTICR[linepos >> 2u]; pExtiConfig->GPIOSel = ((regval << (EXTI_EXTICR1_EXTI1_Pos * (3uL - (linepos & 0x03u)))) >> 24); } - else - { - pExtiConfig->GPIOSel = 0x00u; - } - } - else - { - pExtiConfig->Trigger = EXTI_TRIGGER_NONE; - pExtiConfig->GPIOSel = 0x00u; } return HAL_OK; @@ -447,13 +439,12 @@ HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti) *regaddr = regval; /* 2] Clear event mode */ - regaddr = (&EXTI->C2EMR1 + (EXTI_MODE_OFFSET * offset)); regval = (*regaddr & ~maskline); *regaddr = regval; /* 3] Clear triggers in case of configurable lines */ - if ((hexti->Line & EXTI_CONFIG) != 0x00u) + if ((hexti->Line & EXTI_CONFIG) != 0x0u) { regaddr = (&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset)); regval = (*regaddr & ~maskline); @@ -577,7 +568,7 @@ void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti) regaddr = (&EXTI->RPR1 + (EXTI_CONFIG_OFFSET * offset)); regval = (*regaddr & maskline); - if (regval != 0x00u) + if (regval != 0x0u) { /* Clear pending bit */ *regaddr = maskline; @@ -593,7 +584,7 @@ void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti) regaddr = (&EXTI->FPR1 + (EXTI_CONFIG_OFFSET * offset)); regval = (*regaddr & maskline); - if (regval != 0x00u) + if (regval != 0x0u) { /* Clear pending bit */ *regaddr = maskline; diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_ipcc.c b/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_ipcc.c index e115d0c8bd..178a434197 100644 --- a/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_ipcc.c +++ b/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_ipcc.c @@ -776,4 +776,3 @@ void IPCC_Reset_Register(IPCC_CommonTypeDef *Instance) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_qspi.c b/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_qspi.c index e04be1a705..936cd95326 100755 --- a/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_qspi.c +++ b/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_qspi.c @@ -106,16 +106,16 @@ (#) Configure the SourceInc and DestinationInc of MDMA parameters in the HAL_QSPI_MspInit() function : (++) MDMA settings for write operation : (+) The DestinationInc should be MDMA_DEST_INC_DISABLE - (+) The SourceInc must be a value of @ref MDMA_Source_increment_mode (Except the MDMA_SRC_INC_DOUBLEWORD). - (+) The SourceDataSize must be a value of @ref MDMA Source data size (Except the MDMA_SRC_DATASIZE_DOUBLEWORD) - aligned with @ref MDMA_Source_increment_mode . - (+) The DestDataSize must be a value of @ref MDMA Destination data size (Except the MDMA_DEST_DATASIZE_DOUBLEWORD) + (+) The SourceInc must be a value of MDMA_Source_increment_mode (Except the MDMA_SRC_INC_DOUBLEWORD). + (+) The SourceDataSize must be a value of MDMA Source data size (Except the MDMA_SRC_DATASIZE_DOUBLEWORD) + aligned with MDMA_Source_increment_mode . + (+) The DestDataSize must be a value of MDMA Destination data size (Except the MDMA_DEST_DATASIZE_DOUBLEWORD) (++) MDMA settings for read operation : (+) The SourceInc should be MDMA_SRC_INC_DISABLE - (+) The DestinationInc must be a value of @ref MDMA_Destination_increment_mode (Except the MDMA_DEST_INC_DOUBLEWORD). - (+) The SourceDataSize must be a value of @ref MDMA Source data size (Except the MDMA_SRC_DATASIZE_DOUBLEWORD) . - (+) The DestDataSize must be a value of @ref MDMA Destination data size (Except the MDMA_DEST_DATASIZE_DOUBLEWORD) - aligned with @ref MDMA_Destination_increment_mode. + (+) The DestinationInc must be a value of MDMA_Destination_increment_mode (Except the MDMA_DEST_INC_DOUBLEWORD). + (+) The SourceDataSize must be a value of MDMA Source data size (Except the MDMA_SRC_DATASIZE_DOUBLEWORD) . + (+) The DestDataSize must be a value of MDMA Destination data size (Except the MDMA_DEST_DATASIZE_DOUBLEWORD) + aligned with MDMA_Destination_increment_mode. (++)The buffer Transfer Length (BufferTransferLength) = number of bytes in the FIFO (FifoThreshold) of the Quadspi. (#)In case of wrong MDMA setting (++) For write operation : @@ -145,7 +145,7 @@ ================================================= [..] (#) HAL_QSPI_GetError() function gives the error raised during the last operation. - (#) HAL_QSPI_Abort() and HAL_QSPI_AbortIT() functions aborts any on-going operation and + (#) HAL_QSPI_Abort() and HAL_QSPI_Abort_IT() functions aborts any on-going operation and flushes the fifo : (++) In polling mode, the output of the function is done when the transfer complete bit is set and the busy bit cleared. @@ -167,7 +167,7 @@ The compilation define USE_HAL_QSPI_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. - Use Functions @ref HAL_QSPI_RegisterCallback() to register a user callback, + Use Functions HAL_QSPI_RegisterCallback() to register a user callback, it allows to register following callbacks: (+) ErrorCallback : callback when error occurs. (+) AbortCpltCallback : callback when abort is completed. @@ -184,7 +184,7 @@ This function takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. - Use function @ref HAL_QSPI_UnRegisterCallback() to reset a callback to the default + Use function HAL_QSPI_UnRegisterCallback() to reset a callback to the default weak (surcharged) function. It allows to reset following callbacks: (+) ErrorCallback : callback when error occurs. (+) AbortCpltCallback : callback when abort is completed. @@ -200,12 +200,12 @@ (+) MspDeInitCallback : QSPI MspDeInit. This function) takes as parameters the HAL peripheral handle and the Callback ID. - By default, after the @ref HAL_QSPI_Init and if the state is HAL_QSPI_STATE_RESET + By default, after the HAL_QSPI_Init and if the state is HAL_QSPI_STATE_RESET all callbacks are reset to the corresponding legacy weak (surcharged) functions. Exception done for MspInit and MspDeInit callbacks that are respectively - reset to the legacy weak (surcharged) functions in the @ref HAL_QSPI_Init - and @ref HAL_QSPI_DeInit only when these callbacks are null (not registered beforehand). - If not, MspInit or MspDeInit are not null, the @ref HAL_QSPI_Init and @ref HAL_QSPI_DeInit + reset to the legacy weak (surcharged) functions in the HAL_QSPI_Init + and HAL_QSPI_DeInit only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_QSPI_Init and HAL_QSPI_DeInit keep and use the user MspInit/MspDeInit callbacks (registered beforehand) Callbacks can be registered/unregistered in READY state only. @@ -213,8 +213,8 @@ in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_QSPI_RegisterCallback before calling @ref HAL_QSPI_DeInit - or @ref HAL_QSPI_Init function. + using HAL_QSPI_RegisterCallback before calling HAL_QSPI_DeInit + or HAL_QSPI_Init function. When The compilation define USE_HAL_QSPI_REGISTER_CALLBACKS is set to 0 or not defined, the callback registering feature is not available @@ -306,7 +306,7 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin /** * @brief Initialize the QSPI mode according to the specified parameters * in the QSPI_InitTypeDef and initialize the associated handle. - * @param hqspi : QSPI handle + * @param hqspi QSPI handle * @retval HAL status */ HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi) @@ -410,7 +410,7 @@ HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi) /** * @brief De-Initialize the QSPI peripheral. - * @param hqspi : QSPI handle + * @param hqspi QSPI handle * @retval HAL status */ HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi) @@ -454,7 +454,7 @@ HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi) /** * @brief Initialize the QSPI MSP. - * @param hqspi : QSPI handle + * @param hqspi QSPI handle * @retval None */ __weak void HAL_QSPI_MspInit(QSPI_HandleTypeDef *hqspi) @@ -469,7 +469,7 @@ __weak void HAL_QSPI_MspInit(QSPI_HandleTypeDef *hqspi) /** * @brief DeInitialize the QSPI MSP. - * @param hqspi : QSPI handle + * @param hqspi QSPI handle * @retval None */ __weak void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi) @@ -508,7 +508,7 @@ __weak void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi) /** * @brief Handle QSPI interrupt request. - * @param hqspi : QSPI handle + * @param hqspi QSPI handle * @retval None */ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) @@ -794,9 +794,9 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) /** * @brief Set the command configuration. - * @param hqspi : QSPI handle + * @param hqspi QSPI handle * @param cmd : structure that contains the command configuration information - * @param Timeout : Timeout duration + * @param Timeout Timeout duration * @note This function is used only in Indirect Read or Write Modes * @retval HAL status */ @@ -884,8 +884,8 @@ HAL_StatusTypeDef HAL_QSPI_Command(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDe /** * @brief Set the command configuration in interrupt mode. - * @param hqspi : QSPI handle - * @param cmd : structure that contains the command configuration information + * @param hqspi QSPI handle + * @param cmd structure that contains the command configuration information * @note This function is used only in Indirect Read or Write Modes * @retval HAL status */ @@ -983,9 +983,9 @@ HAL_StatusTypeDef HAL_QSPI_Command_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTyp /** * @brief Transmit an amount of data in blocking mode. - * @param hqspi : QSPI handle - * @param pData : pointer to data buffer - * @param Timeout : Timeout duration + * @param hqspi QSPI handle + * @param pData pointer to data buffer + * @param Timeout Timeout duration * @note This function is used only in Indirect Write Mode * @retval HAL status */ @@ -1066,9 +1066,9 @@ HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef *hqspi, uint8_t *pData, u /** * @brief Receive an amount of data in blocking mode. - * @param hqspi : QSPI handle - * @param pData : pointer to data buffer - * @param Timeout : Timeout duration + * @param hqspi QSPI handle + * @param pData pointer to data buffer + * @param Timeout Timeout duration * @note This function is used only in Indirect Read Mode * @retval HAL status */ @@ -1152,8 +1152,8 @@ HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef *hqspi, uint8_t *pData, ui /** * @brief Send an amount of data in non-blocking mode with interrupt. - * @param hqspi : QSPI handle - * @param pData : pointer to data buffer + * @param hqspi QSPI handle + * @param pData pointer to data buffer * @note This function is used only in Indirect Write Mode * @retval HAL status */ @@ -1212,8 +1212,8 @@ HAL_StatusTypeDef HAL_QSPI_Transmit_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData /** * @brief Receive an amount of data in non-blocking mode with interrupt. - * @param hqspi : QSPI handle - * @param pData : pointer to data buffer + * @param hqspi QSPI handle + * @param pData pointer to data buffer * @note This function is used only in Indirect Read Mode * @retval HAL status */ @@ -1276,8 +1276,8 @@ HAL_StatusTypeDef HAL_QSPI_Receive_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData) /** * @brief Send an amount of data in non-blocking mode with DMA. - * @param hqspi : QSPI handle - * @param pData : pointer to data buffer + * @param hqspi QSPI handle + * @param pData pointer to data buffer * @note This function is used only in Indirect Write Mode * @retval HAL status */ @@ -1387,8 +1387,8 @@ HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pDat /** * @brief Receive an amount of data in non-blocking mode with DMA. - * @param hqspi : QSPI handle - * @param pData : pointer to data buffer. + * @param hqspi QSPI handle + * @param pData pointer to data buffer. * @note This function is used only in Indirect Read Mode * @retval HAL status */ @@ -1504,10 +1504,10 @@ HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData /** * @brief Configure the QSPI Automatic Polling Mode in blocking mode. - * @param hqspi : QSPI handle - * @param cmd : structure that contains the command configuration information. - * @param cfg : structure that contains the polling configuration information. - * @param Timeout : Timeout duration + * @param hqspi QSPI handle + * @param cmd structure that contains the command configuration information. + * @param cfg structure that contains the polling configuration information. + * @param Timeout Timeout duration * @note This function is used only in Automatic Polling Mode * @retval HAL status */ @@ -1605,9 +1605,9 @@ HAL_StatusTypeDef HAL_QSPI_AutoPolling(QSPI_HandleTypeDef *hqspi, QSPI_CommandTy /** * @brief Configure the QSPI Automatic Polling Mode in non-blocking mode. - * @param hqspi : QSPI handle - * @param cmd : structure that contains the command configuration information. - * @param cfg : structure that contains the polling configuration information. + * @param hqspi QSPI handle + * @param cmd structure that contains the command configuration information. + * @param cfg structure that contains the polling configuration information. * @note This function is used only in Automatic Polling Mode * @retval HAL status */ @@ -1709,9 +1709,9 @@ HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_Comman /** * @brief Configure the Memory Mapped mode. - * @param hqspi : QSPI handle - * @param cmd : structure that contains the command configuration information. - * @param cfg : structure that contains the memory mapped configuration information. + * @param hqspi QSPI handle + * @param cmd structure that contains the command configuration information. + * @param cfg structure that contains the memory mapped configuration information. * @note This function is used only in Memory mapped Mode * @retval HAL status */ @@ -1798,7 +1798,7 @@ HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandT /** * @brief Transfer Error callback. - * @param hqspi : QSPI handle + * @param hqspi QSPI handle * @retval None */ __weak void HAL_QSPI_ErrorCallback(QSPI_HandleTypeDef *hqspi) @@ -1813,7 +1813,7 @@ __weak void HAL_QSPI_ErrorCallback(QSPI_HandleTypeDef *hqspi) /** * @brief Abort completed callback. - * @param hqspi : QSPI handle + * @param hqspi QSPI handle * @retval None */ __weak void HAL_QSPI_AbortCpltCallback(QSPI_HandleTypeDef *hqspi) @@ -1828,7 +1828,7 @@ __weak void HAL_QSPI_AbortCpltCallback(QSPI_HandleTypeDef *hqspi) /** * @brief Command completed callback. - * @param hqspi : QSPI handle + * @param hqspi QSPI handle * @retval None */ __weak void HAL_QSPI_CmdCpltCallback(QSPI_HandleTypeDef *hqspi) @@ -1843,7 +1843,7 @@ __weak void HAL_QSPI_CmdCpltCallback(QSPI_HandleTypeDef *hqspi) /** * @brief Rx Transfer completed callback. - * @param hqspi : QSPI handle + * @param hqspi QSPI handle * @retval None */ __weak void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi) @@ -1858,7 +1858,7 @@ __weak void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi) /** * @brief Tx Transfer completed callback. - * @param hqspi : QSPI handle + * @param hqspi QSPI handle * @retval None */ __weak void HAL_QSPI_TxCpltCallback(QSPI_HandleTypeDef *hqspi) @@ -1873,7 +1873,7 @@ __weak void HAL_QSPI_TxCpltCallback(QSPI_HandleTypeDef *hqspi) /** * @brief Rx Half Transfer completed callback. - * @param hqspi : QSPI handle + * @param hqspi QSPI handle * @retval None */ __weak void HAL_QSPI_RxHalfCpltCallback(QSPI_HandleTypeDef *hqspi) @@ -1888,7 +1888,7 @@ __weak void HAL_QSPI_RxHalfCpltCallback(QSPI_HandleTypeDef *hqspi) /** * @brief Tx Half Transfer completed callback. - * @param hqspi : QSPI handle + * @param hqspi QSPI handle * @retval None */ __weak void HAL_QSPI_TxHalfCpltCallback(QSPI_HandleTypeDef *hqspi) @@ -1903,7 +1903,7 @@ __weak void HAL_QSPI_TxHalfCpltCallback(QSPI_HandleTypeDef *hqspi) /** * @brief FIFO Threshold callback. - * @param hqspi : QSPI handle + * @param hqspi QSPI handle * @retval None */ __weak void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi) @@ -1918,7 +1918,7 @@ __weak void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi) /** * @brief Status Match callback. - * @param hqspi : QSPI handle + * @param hqspi QSPI handle * @retval None */ __weak void HAL_QSPI_StatusMatchCallback(QSPI_HandleTypeDef *hqspi) @@ -1933,7 +1933,7 @@ __weak void HAL_QSPI_StatusMatchCallback(QSPI_HandleTypeDef *hqspi) /** * @brief Timeout callback. - * @param hqspi : QSPI handle + * @param hqspi QSPI handle * @retval None */ __weak void HAL_QSPI_TimeOutCallback(QSPI_HandleTypeDef *hqspi) @@ -1949,8 +1949,8 @@ __weak void HAL_QSPI_TimeOutCallback(QSPI_HandleTypeDef *hqspi) /** * @brief Register a User QSPI Callback * To be used instead of the weak (surcharged) predefined callback - * @param hqspi : QSPI handle - * @param CallbackId : ID of the callback to be registered + * @param hqspi QSPI handle + * @param CallbackId ID of the callback to be registered * This parameter can be one of the following values: * @arg @ref HAL_QSPI_ERROR_CB_ID QSPI Error Callback ID * @arg @ref HAL_QSPI_ABORT_CB_ID QSPI Abort Callback ID @@ -1964,7 +1964,7 @@ __weak void HAL_QSPI_TimeOutCallback(QSPI_HandleTypeDef *hqspi) * @arg @ref HAL_QSPI_TIMEOUT_CB_ID QSPI Timeout Callback ID * @arg @ref HAL_QSPI_MSP_INIT_CB_ID QSPI MspInit callback ID * @arg @ref HAL_QSPI_MSP_DEINIT_CB_ID QSPI MspDeInit callback ID - * @param pCallback : pointer to the Callback function + * @param pCallback pointer to the Callback function * @retval status */ HAL_StatusTypeDef HAL_QSPI_RegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId, pQSPI_CallbackTypeDef pCallback) @@ -2063,8 +2063,8 @@ HAL_StatusTypeDef HAL_QSPI_RegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI /** * @brief Unregister a User QSPI Callback * QSPI Callback is redirected to the weak (surcharged) predefined callback - * @param hqspi : QSPI handle - * @param CallbackId : ID of the callback to be unregistered + * @param hqspi QSPI handle + * @param CallbackId ID of the callback to be unregistered * This parameter can be one of the following values: * @arg @ref HAL_QSPI_ERROR_CB_ID QSPI Error Callback ID * @arg @ref HAL_QSPI_ABORT_CB_ID QSPI Abort Callback ID @@ -2191,7 +2191,7 @@ HAL_StatusTypeDef HAL_QSPI_UnRegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QS /** * @brief Return the QSPI handle state. - * @param hqspi : QSPI handle + * @param hqspi QSPI handle * @retval HAL state */ HAL_QSPI_StateTypeDef HAL_QSPI_GetState(QSPI_HandleTypeDef *hqspi) @@ -2202,7 +2202,7 @@ HAL_QSPI_StateTypeDef HAL_QSPI_GetState(QSPI_HandleTypeDef *hqspi) /** * @brief Return the QSPI error code. -* @param hqspi : QSPI handle +* @param hqspi QSPI handle * @retval QSPI Error Code */ uint32_t HAL_QSPI_GetError(QSPI_HandleTypeDef *hqspi) @@ -2212,7 +2212,7 @@ uint32_t HAL_QSPI_GetError(QSPI_HandleTypeDef *hqspi) /** * @brief Abort the current transmission. -* @param hqspi : QSPI handle +* @param hqspi QSPI handle * @retval HAL status */ HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi) @@ -2239,25 +2239,33 @@ HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi) } } - /* Configure QSPI: CR register with Abort request */ - SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT); + if (__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_BUSY) != RESET) + { + /* Configure QSPI: CR register with Abort request */ + SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT); - /* Wait until TC flag is set to go back in idle state */ - status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, hqspi->Timeout); + /* Wait until TC flag is set to go back in idle state */ + status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, hqspi->Timeout); - if (status == HAL_OK) - { - __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); + if (status == HAL_OK) + { + __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); - /* Wait until BUSY flag is reset */ - status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout); - } + /* Wait until BUSY flag is reset */ + status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout); + } - if (status == HAL_OK) - { - /* Reset functional mode configuration to indirect write mode by default */ - CLEAR_BIT(hqspi->Instance->CCR, QUADSPI_CCR_FMODE); + if (status == HAL_OK) + { + /* Reset functional mode configuration to indirect write mode by default */ + CLEAR_BIT(hqspi->Instance->CCR, QUADSPI_CCR_FMODE); + /* Update state */ + hqspi->State = HAL_QSPI_STATE_READY; + } + } + else + { /* Update state */ hqspi->State = HAL_QSPI_STATE_READY; } @@ -2268,7 +2276,7 @@ HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi) /** * @brief Abort the current transmission (non-blocking function) -* @param hqspi : QSPI handle +* @param hqspi QSPI handle * @retval HAL status */ HAL_StatusTypeDef HAL_QSPI_Abort_IT(QSPI_HandleTypeDef *hqspi) @@ -2309,22 +2317,30 @@ HAL_StatusTypeDef HAL_QSPI_Abort_IT(QSPI_HandleTypeDef *hqspi) } else { - /* Clear interrupt */ - __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); + if (__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_BUSY) != RESET) + { + /* Clear interrupt */ + __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); - /* Enable the QSPI Transfer Complete Interrupt */ - __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC); + /* Enable the QSPI Transfer Complete Interrupt */ + __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC); - /* Configure QSPI: CR register with Abort request */ - SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT); + /* Configure QSPI: CR register with Abort request */ + SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT); + } + else + { + /* Change state of QSPI */ + hqspi->State = HAL_QSPI_STATE_READY; + } } } return status; } /** @brief Set QSPI timeout. - * @param hqspi : QSPI handle. - * @param Timeout : Timeout for the QSPI memory access. + * @param hqspi QSPI handle. + * @param Timeout Timeout for the QSPI memory access. * @retval None */ void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout) @@ -2333,8 +2349,8 @@ void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout) } /** @brief Set QSPI Fifo threshold. - * @param hqspi : QSPI handle. - * @param Threshold : Threshold of the Fifo (value between 1 and 16). + * @param hqspi QSPI handle. + * @param Threshold Threshold of the Fifo (value between 1 and 16). * @retval HAL status */ HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold) @@ -2366,7 +2382,7 @@ HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t } /** @brief Get QSPI Fifo threshold. - * @param hqspi : QSPI handle. + * @param hqspi QSPI handle. * @retval Fifo threshold (value between 1 and 16) */ uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi) @@ -2375,8 +2391,8 @@ uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi) } /** @brief Set FlashID. - * @param hqspi : QSPI handle. - * @param FlashID : Index of the flash memory to be accessed. + * @param hqspi QSPI handle. + * @param FlashID Index of the flash memory to be accessed. * This parameter can be a value of @ref QSPI_Flash_Select. * @note The FlashID is ignored when dual flash mode is enabled. * @retval HAL status @@ -2425,7 +2441,7 @@ HAL_StatusTypeDef HAL_QSPI_SetFlashID(QSPI_HandleTypeDef *hqspi, uint32_t FlashI /** * @brief DMA QSPI receive process complete callback. - * @param hmdma : MDMA handle + * @param hmdma MDMA handle * @retval None */ static void QSPI_DMARxCplt(MDMA_HandleTypeDef *hmdma) @@ -2439,7 +2455,7 @@ static void QSPI_DMARxCplt(MDMA_HandleTypeDef *hmdma) /** * @brief DMA QSPI transmit process complete callback. - * @param hmdma : MDMA handle + * @param hmdma MDMA handle * @retval None */ static void QSPI_DMATxCplt(MDMA_HandleTypeDef *hmdma) @@ -2453,7 +2469,7 @@ static void QSPI_DMATxCplt(MDMA_HandleTypeDef *hmdma) /** * @brief DMA QSPI communication error callback. - * @param hmdma : MDMA handle + * @param hmdma MDMA handle * @retval None */ static void QSPI_DMAError(MDMA_HandleTypeDef *hmdma) @@ -2474,7 +2490,7 @@ static void QSPI_DMAError(MDMA_HandleTypeDef *hmdma) /** * @brief MDMA QSPI abort complete callback. - * @param hmdma : MDMA handle + * @param hmdma MDMA handle * @retval None */ static void QSPI_DMAAbortCplt(MDMA_HandleTypeDef *hmdma) @@ -2513,11 +2529,11 @@ static void QSPI_DMAAbortCplt(MDMA_HandleTypeDef *hmdma) /** * @brief Wait for a flag state until timeout. - * @param hqspi : QSPI handle - * @param Flag : Flag checked - * @param State : Value of the flag expected - * @param Tickstart : Tick start value - * @param Timeout : Duration of the timeout + * @param hqspi QSPI handle + * @param Flag Flag checked + * @param State Value of the flag expected + * @param Tickstart Tick start value + * @param Timeout Duration of the timeout * @retval HAL status */ static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag, @@ -2543,9 +2559,9 @@ static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqsp /** * @brief Configure the communication registers. - * @param hqspi : QSPI handle - * @param cmd : structure that contains the command configuration information - * @param FunctionalMode : functional mode to configured + * @param hqspi QSPI handle + * @param cmd structure that contains the command configuration information + * @param FunctionalMode functional mode to configured * This parameter can be one of the following values: * @arg QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE: Indirect write mode * @arg QSPI_FUNCTIONAL_MODE_INDIRECT_READ: Indirect read mode diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_rcc.c b/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_rcc.c index 82a149e1f3..44356bab01 100644 --- a/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_rcc.c +++ b/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_rcc.c @@ -1992,7 +1992,7 @@ __weak void HAL_RCC_GetPLL1ClockFreq(PLL1_ClocksTypeDef *PLL1_Clocks) pll1m = ((RCC->PLL1CFGR1 & RCC_PLL1CFGR1_DIVM1) >> RCC_PLL1CFGR1_DIVM1_Pos) + 1U; pll1fracen = (RCC->PLL1FRACR & RCC_PLL1FRACR_FRACLE) >> RCC_PLL1FRACR_FRACLE_Pos; fracn1 = (float)(pll1fracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACV) >> RCC_PLL1FRACR_FRACV_Pos)); - pll1vco = (float)((float)((RCC->PLL1CFGR1 & RCC_PLL1CFGR1_DIVN) + 1U) + (fracn1 / (float)0x1FFF)); //Intermediary value + pll1vco = (float)((float)((RCC->PLL1CFGR1 & RCC_PLL1CFGR1_DIVN) + 1U) + (fracn1 / (float)0x2000)); //Intermediary value switch (pllsource) { case RCC_PLL12SOURCE_HSI: /* HSI used as PLL clock source */ @@ -2050,7 +2050,7 @@ __weak void HAL_RCC_GetPLL2ClockFreq(PLL2_ClocksTypeDef *PLL2_Clocks) pll2m = ((RCC->PLL2CFGR1 & RCC_PLL2CFGR1_DIVM2) >> RCC_PLL2CFGR1_DIVM2_Pos) + 1U; pll2fracen = (RCC->PLL2FRACR & RCC_PLL2FRACR_FRACLE) >> RCC_PLL2FRACR_FRACLE_Pos; fracn1 = (float)(pll2fracen * ((RCC->PLL2FRACR & RCC_PLL2FRACR_FRACV) >> RCC_PLL2FRACR_FRACV_Pos)); - pll2vco = (float)((float)((RCC->PLL2CFGR1 & RCC_PLL2CFGR1_DIVN) + 1U) + (fracn1 / (float)0x1FFF)); //Intermediary value + pll2vco = (float)((float)((RCC->PLL2CFGR1 & RCC_PLL2CFGR1_DIVN) + 1U) + (fracn1 / (float)0x2000)); //Intermediary value switch (pllsource) { case RCC_PLL12SOURCE_HSI: /* HSI used as PLL clock source */ @@ -2107,7 +2107,7 @@ __weak void HAL_RCC_GetPLL3ClockFreq(PLL3_ClocksTypeDef *PLL3_Clocks) pll3m = ((RCC->PLL3CFGR1 & RCC_PLL3CFGR1_DIVM3) >> RCC_PLL3CFGR1_DIVM3_Pos) + 1U; pll3fracen = (RCC->PLL3FRACR & RCC_PLL3FRACR_FRACLE) >> RCC_PLL3FRACR_FRACLE_Pos; fracn1 = (float)(pll3fracen * ((RCC->PLL3FRACR & RCC_PLL3FRACR_FRACV) >> RCC_PLL3FRACR_FRACV_Pos)); - pll3vco = (float)((float)((RCC->PLL3CFGR1 & RCC_PLL3CFGR1_DIVN) + 1U) + (fracn1 / (float) 0x1FFF)); //Intermediary value + pll3vco = (float)((float)((RCC->PLL3CFGR1 & RCC_PLL3CFGR1_DIVN) + 1U) + (fracn1 / (float) 0x2000)); //Intermediary value switch (pllsource) { case RCC_PLL3SOURCE_HSI: /* HSI used as PLL clock source */ @@ -2166,7 +2166,7 @@ __weak void HAL_RCC_GetPLL4ClockFreq(PLL4_ClocksTypeDef *PLL4_Clocks) pll4m = ((RCC->PLL4CFGR1 & RCC_PLL4CFGR1_DIVM4) >> RCC_PLL4CFGR1_DIVM4_Pos) + 1U; pll4fracen = (RCC->PLL4FRACR & RCC_PLL4FRACR_FRACLE) >> RCC_PLL4FRACR_FRACLE_Pos; fracn1 = (float)(pll4fracen * ((RCC->PLL4FRACR & RCC_PLL4FRACR_FRACV) >> RCC_PLL4FRACR_FRACV_Pos)); - pll4vco = (float)((float)((RCC->PLL4CFGR1 & RCC_PLL4CFGR1_DIVN) + 1U) + (fracn1 / (float) 0x1FFF)); //Intermediary value + pll4vco = (float)((float)((RCC->PLL4CFGR1 & RCC_PLL4CFGR1_DIVN) + 1U) + (fracn1 / (float) 0x2000)); //Intermediary value switch (pllsource) { case RCC_PLL4SOURCE_HSI: /* HSI used as PLL clock source */ diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_smbus.c b/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_smbus.c index 9b8bea5611..3b0680e118 100644 --- a/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_smbus.c +++ b/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_smbus.c @@ -208,20 +208,28 @@ /** @addtogroup SMBUS_Private_Functions SMBUS Private Functions * @{ */ +/* Private functions to handle flags during polling transfer */ static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout); -static void SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest); -static void SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest); +/* Private functions for SMBUS transfer IRQ handler */ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags); static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags); +static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus); -static void SMBUS_ConvertOtherXferOptions(SMBUS_HandleTypeDef *hsmbus); +/* Private functions to centralize the enable/disable of Interrupts */ +static void SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest); +static void SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest); -static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus); +/* Private function to flush TXDR register */ +static void SMBUS_Flush_TXDR(SMBUS_HandleTypeDef *hsmbus); +/* Private function to handle start, restart or stop a transfer */ static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request); + +/* Private function to Convert Specific options */ +static void SMBUS_ConvertOtherXferOptions(SMBUS_HandleTypeDef *hsmbus); /** * @} */ @@ -1871,6 +1879,9 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t /* No need to generate STOP, it is automatically done */ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ACKF; + /* Flush TX register */ + SMBUS_Flush_TXDR(hsmbus); + /* Process Unlocked */ __HAL_UNLOCK(hsmbus); @@ -2161,6 +2172,9 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t S /* Clear NACK Flag */ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF); + /* Flush TX register */ + SMBUS_Flush_TXDR(hsmbus); + /* Process Unlocked */ __HAL_UNLOCK(hsmbus); } @@ -2182,6 +2196,9 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t S /* Set ErrorCode corresponding to a Non-Acknowledge */ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ACKF; + /* Flush TX register */ + SMBUS_Flush_TXDR(hsmbus); + /* Process Unlocked */ __HAL_UNLOCK(hsmbus); @@ -2583,7 +2600,10 @@ static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus) __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_PECERR); } - /* Store current volatile hsmbus->State, misra rule */ + /* Flush TX register */ + SMBUS_Flush_TXDR(hsmbus); + + /* Store current volatile hsmbus->ErrorCode, misra rule */ tmperror = hsmbus->ErrorCode; /* Call the Error Callback in case of Error detected */ @@ -2653,6 +2673,27 @@ static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbu return HAL_OK; } +/** + * @brief SMBUS Tx data register flush process. + * @param hsmbus SMBUS handle. + * @retval None + */ +static void SMBUS_Flush_TXDR(SMBUS_HandleTypeDef *hsmbus) +{ + /* If a pending TXIS flag is set */ + /* Write a dummy data in TXDR to clear it */ + if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TXIS) != RESET) + { + hsmbus->Instance->TXDR = 0x00U; + } + + /* Flush TX register if not empty */ + if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TXE) == RESET) + { + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_TXE); + } +} + /** * @brief Handle SMBUSx communication when starting transfer or during transfer (TC or TCR flag are set). * @param hsmbus SMBUS handle. diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_smbus_ex.c b/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_smbus_ex.c new file mode 100644 index 0000000000..b6ec72f7de --- /dev/null +++ b/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_smbus_ex.c @@ -0,0 +1,262 @@ +/** + ****************************************************************************** + * @file stm32mp1xx_hal_smbus_ex.c + * @author MCD Application Team + * @brief SMBUS Extended HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of SMBUS Extended peripheral: + * + Extended features functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### SMBUS peripheral Extended features ##### + ============================================================================== + + [..] Comparing to other previous devices, the SMBUS interface for STM32MP1xx + devices contains the following additional features + + (+) Disable or enable wakeup from Stop mode(s) + (+) Disable or enable Fast Mode Plus + + ##### How to use this driver ##### + ============================================================================== + (#) Configure the enable or disable of SMBUS Wake Up Mode using the functions : + (++) HAL_SMBUSEx_EnableWakeUp() + (++) HAL_SMBUSEx_DisableWakeUp() + (#) Configure the enable or disable of fast mode plus driving capability using the functions : + (++) HAL_SMBUSEx_EnableFastModePlus() + (++) HAL_SMBUSEx_DisableFastModePlus() + @endverbatim + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32mp1xx_hal.h" + +/** @addtogroup STM32MP1xx_HAL_Driver + * @{ + */ + +/** @defgroup SMBUSEx SMBUSEx + * @brief SMBUS Extended HAL module driver + * @{ + */ + +#ifdef HAL_SMBUS_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup SMBUSEx_Exported_Functions SMBUS Extended Exported Functions + * @{ + */ + +/** @defgroup SMBUSEx_Exported_Functions_Group2 WakeUp Mode Functions + * @brief WakeUp Mode Functions + * +@verbatim + =============================================================================== + ##### WakeUp Mode Functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure Wake Up Feature + +@endverbatim + * @{ + */ + +/** + * @brief Enable SMBUS wakeup from Stop mode(s). + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUSx peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMBUSEx_EnableWakeUp(SMBUS_HandleTypeDef *hsmbus) +{ + /* Check the parameters */ + assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hsmbus->Instance)); + + if (hsmbus->State == HAL_SMBUS_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hsmbus); + + hsmbus->State = HAL_SMBUS_STATE_BUSY; + + /* Disable the selected SMBUS peripheral */ + __HAL_SMBUS_DISABLE(hsmbus); + + /* Enable wakeup from stop mode */ + hsmbus->Instance->CR1 |= I2C_CR1_WUPEN; + + __HAL_SMBUS_ENABLE(hsmbus); + + hsmbus->State = HAL_SMBUS_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Disable SMBUS wakeup from Stop mode(s). + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUSx peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMBUSEx_DisableWakeUp(SMBUS_HandleTypeDef *hsmbus) +{ + /* Check the parameters */ + assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hsmbus->Instance)); + + if (hsmbus->State == HAL_SMBUS_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hsmbus); + + hsmbus->State = HAL_SMBUS_STATE_BUSY; + + /* Disable the selected SMBUS peripheral */ + __HAL_SMBUS_DISABLE(hsmbus); + + /* Disable wakeup from stop mode */ + hsmbus->Instance->CR1 &= ~(I2C_CR1_WUPEN); + + __HAL_SMBUS_ENABLE(hsmbus); + + hsmbus->State = HAL_SMBUS_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} +/** + * @} + */ + +/** @defgroup SMBUSEx_Exported_Functions_Group3 Fast Mode Plus Functions + * @brief Fast Mode Plus Functions + * +@verbatim + =============================================================================== + ##### Fast Mode Plus Functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure Fast Mode Plus + +@endverbatim + * @{ + */ + +/** + * @brief Enable the SMBUS fast mode plus driving capability. + * @param ConfigFastModePlus Selects the pin. + * This parameter can be one of the @ref SMBUSEx_FastModePlus values + * @note For I2C1, fast mode plus driving capability can be enabled on all selected + * I2C1 pins using SMBUS_FASTMODEPLUS_I2C1 parameter or independently + * on each one of the following pins PB6, PB7, PB8 and PB9. + * @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability + * can be enabled only by using SMBUS_FASTMODEPLUS_I2C1 parameter. + * @note For all I2C2 pins fast mode plus driving capability can be enabled + * only by using SMBUS_FASTMODEPLUS_I2C2 parameter. + * @note For all I2C3 pins fast mode plus driving capability can be enabled + * only by using SMBUS_FASTMODEPLUS_I2C3 parameter. + * @note For all I2C4 pins fast mode plus driving capability can be enabled + * only by using SMBUS_FASTMODEPLUS_I2C4 parameter. + * @note For all I2C5 pins fast mode plus driving capability can be enabled + * only by using SMBUS_FASTMODEPLUS_I2C5 parameter. + * @note For all I2C6 pins fast mode plus driving capability can be enabled + * only by using SMBUS_FASTMODEPLUS_I2C6 parameter. + * @retval None + */ +void HAL_SMBUSEx_EnableFastModePlus(uint32_t ConfigFastModePlus) +{ + /* Check the parameter */ + assert_param(IS_SMBUS_FASTMODEPLUS(ConfigFastModePlus)); + + /* Enable SYSCFG clock */ + __HAL_RCC_SYSCFG_CLK_ENABLE(); + + /* Enable fast mode plus driving capability for selected pin */ + SET_BIT(SYSCFG->PMCSETR, (uint32_t)ConfigFastModePlus); +} + +/** + * @brief Disable the SMBUS fast mode plus driving capability. + * @param ConfigFastModePlus Selects the pin. + * This parameter can be one of the @ref SMBUSEx_FastModePlus values + * @note For I2C1, fast mode plus driving capability can be disabled on all selected + * I2C1 pins using SMBUS_FASTMODEPLUS_I2C1 parameter or independently + * on each one of the following pins PB6, PB7, PB8 and PB9. + * @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability + * can be disabled only by using SMBUS_FASTMODEPLUS_I2C1 parameter. + * @note For all I2C2 pins fast mode plus driving capability can be disabled + * only by using SMBUS_FASTMODEPLUS_I2C2 parameter. + * @note For all I2C3 pins fast mode plus driving capability can be disabled + * only by using SMBUS_FASTMODEPLUS_I2C3 parameter. + * @note For all I2C4 pins fast mode plus driving capability can be disabled + * only by using SMBUS_FASTMODEPLUS_I2C4 parameter. + * @note For all I2C5 pins fast mode plus driving capability can be disabled + * only by using SMBUS_FASTMODEPLUS_I2C5 parameter. + * @note For all I2C6 pins fast mode plus driving capability can be disabled + * only by using SMBUS_FASTMODEPLUS_I2C6 parameter. + * @retval None + */ +void HAL_SMBUSEx_DisableFastModePlus(uint32_t ConfigFastModePlus) +{ + /* Check the parameter */ + assert_param(IS_SMBUS_FASTMODEPLUS(ConfigFastModePlus)); + + /* Enable SYSCFG clock */ + __HAL_RCC_SYSCFG_CLK_ENABLE(); + + /* Disable fast mode plus driving capability for selected pin */ + SET_BIT(SYSCFG->PMCCLRR, (uint32_t)ConfigFastModePlus); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_SMBUS_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_spi.c b/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_spi.c index 2268fa4001..a90df5d2d8 100644 --- a/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_spi.c +++ b/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_spi.c @@ -70,6 +70,7 @@ (+) TxRxHalfCpltCallback : SPI TxRx Half Completed callback (+) ErrorCallback : SPI Error callback (+) AbortCpltCallback : SPI Abort callback + (+) SuspendCallback : SPI Suspend callback (+) MspInitCallback : SPI Msp Init callback (+) MspDeInitCallback : SPI Msp DeInit callback This function takes as parameters the HAL peripheral handle, the Callback ID @@ -89,6 +90,7 @@ (+) TxRxHalfCpltCallback : SPI TxRx Half Completed callback (+) ErrorCallback : SPI Error callback (+) AbortCpltCallback : SPI Abort callback + (+) SuspendCallback : SPI Suspend callback (+) MspInitCallback : SPI Msp Init callback (+) MspDeInitCallback : SPI Msp DeInit callback @@ -113,6 +115,10 @@ not defined, the callback registering feature is not available and weak (surcharged) callbacks are used. + SuspendCallback restriction: + SuspendCallback is called only when MasterReceiverAutoSusp is enabled and + EOT interrupt is activated. SuspendCallback is used in relation with functions + HAL_SPI_Transmit_IT, HAL_SPI_Receive_IT and HAL_SPI_TransmitReceive_IT. [..] Circular mode restriction: @@ -332,6 +338,7 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */ hspi->ErrorCallback = HAL_SPI_ErrorCallback; /* Legacy weak ErrorCallback */ hspi->AbortCpltCallback = HAL_SPI_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + hspi->SuspendCallback = HAL_SPI_SuspendCallback; /* Legacy weak SuspendCallback */ if (hspi->MspInitCallback == NULL) { @@ -369,6 +376,16 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) SET_BIT(hspi->Instance->CR1, SPI_CR1_SSI); } + /* SPIx Master Rx Auto Suspend Configuration */ + if (((hspi->Init.Mode & SPI_MODE_MASTER) == SPI_MODE_MASTER) && (hspi->Init.DataSize >= SPI_DATASIZE_8BIT)) + { + MODIFY_REG(hspi->Instance->CR1, SPI_CR1_MASRX, hspi->Init.MasterReceiverAutoSusp); + } + else + { + CLEAR_BIT(hspi->Instance->CR1, SPI_CR1_MASRX); + } + /* SPIx CFG1 Configuration */ WRITE_REG(hspi->Instance->CFG1, (hspi->Init.BaudRatePrescaler | hspi->Init.CRCCalculation | crc_length | hspi->Init.FifoThreshold | hspi->Init.DataSize)); @@ -590,7 +607,11 @@ HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_Call hspi->AbortCpltCallback = pCallback; break; - case HAL_SPI_MSPINIT_CB_ID : + case HAL_SPI_SUSPEND_CB_ID : + hspi->SuspendCallback = pCallback; + break; + + case HAL_SPI_MSPINIT_CB_ID : hspi->MspInitCallback = pCallback; break; @@ -693,6 +714,10 @@ HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_Ca hspi->AbortCpltCallback = HAL_SPI_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ break; + case HAL_SPI_SUSPEND_CB_ID : + hspi->SuspendCallback = HAL_SPI_SuspendCallback; /* Legacy weak SuspendCallback */ + break; + case HAL_SPI_MSPINIT_CB_ID : hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */ break; @@ -791,7 +816,7 @@ HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_Ca * @param Timeout: Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) +HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size, uint32_t Timeout) { #if defined (__GNUC__) __IO uint16_t *ptxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->TXDR)); @@ -826,7 +851,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_TX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pTxBuffPtr = (uint8_t *)pData; + hspi->pTxBuffPtr = (const uint8_t *)pData; hspi->TxXferSize = Size; hspi->TxXferCount = Size; @@ -842,6 +867,10 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint { SPI_1LINE_TX(hspi); } + else + { + SPI_2LINES_TX(hspi); + } /* Set the number of data at current transfer */ MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size); @@ -864,7 +893,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint /* Wait until TXP flag is set to send data */ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP)) { - *((__IO uint32_t *)&hspi->Instance->TXDR) = *((uint32_t *)hspi->pTxBuffPtr); + *((__IO uint32_t *)&hspi->Instance->TXDR) = *((const uint32_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint32_t); hspi->TxXferCount--; } @@ -897,16 +926,16 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint { if ((hspi->TxXferCount > 1UL) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_01DATA)) { - *((__IO uint32_t *)&hspi->Instance->TXDR) = *((uint32_t *)hspi->pTxBuffPtr); + *((__IO uint32_t *)&hspi->Instance->TXDR) = *((const uint32_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint32_t); hspi->TxXferCount -= (uint16_t)2UL; } else { #if defined (__GNUC__) - *ptxdr_16bits = *((uint16_t *)hspi->pTxBuffPtr); + *ptxdr_16bits = *((const uint16_t *)hspi->pTxBuffPtr); #else - *((__IO uint16_t *)&hspi->Instance->TXDR) = *((uint16_t *)hspi->pTxBuffPtr); + *((__IO uint16_t *)&hspi->Instance->TXDR) = *((const uint16_t *)hspi->pTxBuffPtr); #endif /* __GNUC__ */ hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount--; @@ -940,23 +969,23 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint { if ((hspi->TxXferCount > 3UL) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_03DATA)) { - *((__IO uint32_t *)&hspi->Instance->TXDR) = *((uint32_t *)hspi->pTxBuffPtr); + *((__IO uint32_t *)&hspi->Instance->TXDR) = *((const uint32_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint32_t); hspi->TxXferCount -= (uint16_t)4UL; } else if ((hspi->TxXferCount > 1UL) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_01DATA)) { #if defined (__GNUC__) - *ptxdr_16bits = *((uint16_t *)hspi->pTxBuffPtr); + *ptxdr_16bits = *((const uint16_t *)hspi->pTxBuffPtr); #else - *((__IO uint16_t *)&hspi->Instance->TXDR) = *((uint16_t *)hspi->pTxBuffPtr); + *((__IO uint16_t *)&hspi->Instance->TXDR) = *((const uint16_t *)hspi->pTxBuffPtr); #endif /* __GNUC__ */ hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount -= (uint16_t)2UL; } else { - *((__IO uint8_t *)&hspi->Instance->TXDR) = *((uint8_t *)hspi->pTxBuffPtr); + *((__IO uint8_t *)&hspi->Instance->TXDR) = *((const uint8_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint8_t); hspi->TxXferCount--; } @@ -1021,13 +1050,6 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(hspi->Init.Direction)); - if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES)) - { - hspi->State = HAL_SPI_STATE_BUSY_RX; - /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */ - return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout); - } - /* Lock the process */ __HAL_LOCK(hspi); @@ -1067,6 +1089,10 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 { SPI_1LINE_RX(hspi); } + else + { + SPI_2LINES_RX(hspi); + } /* Set the number of data at current transfer */ MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size); @@ -1117,25 +1143,16 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 /* Transfer loop */ while (hspi->RxXferCount > 0UL) { - /* Check the RXWNE/FRLVL flag */ - if ((hspi->Instance->SR & (SPI_FLAG_RXWNE | SPI_FLAG_FRLVL)) != 0UL) + /* Check the RXP flag */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXP)) { - if ((hspi->Instance->SR & SPI_FLAG_RXWNE) != 0UL) - { - *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR); - hspi->pRxBuffPtr += sizeof(uint32_t); - hspi->RxXferCount -= (uint16_t)2UL; - } - else - { #if defined (__GNUC__) - *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits; + *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits; #else - *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR); + *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR); #endif /* __GNUC__ */ - hspi->pRxBuffPtr += sizeof(uint16_t); - hspi->RxXferCount--; - } + hspi->pRxBuffPtr += sizeof(uint16_t); + hspi->RxXferCount--; } else { @@ -1161,31 +1178,12 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 /* Transfer loop */ while (hspi->RxXferCount > 0UL) { - /* Check the RXWNE/FRLVL flag */ - if ((hspi->Instance->SR & (SPI_FLAG_RXWNE | SPI_FLAG_FRLVL)) != 0UL) + /* Check the RXP flag */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXP)) { - if ((hspi->Instance->SR & SPI_FLAG_RXWNE) != 0UL) - { - *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR); - hspi->pRxBuffPtr += sizeof(uint32_t); - hspi->RxXferCount -= (uint16_t)4UL; - } - else if ((hspi->Instance->SR & SPI_FLAG_FRLVL) > SPI_RX_FIFO_1PACKET) - { -#if defined (__GNUC__) - *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits; -#else - *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR); -#endif /* __GNUC__ */ - hspi->pRxBuffPtr += sizeof(uint16_t); - hspi->RxXferCount -= (uint16_t)2UL; - } - else - { - *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR); - hspi->pRxBuffPtr += sizeof(uint8_t); - hspi->RxXferCount--; - } + *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint8_t); + hspi->RxXferCount--; } else { @@ -1242,10 +1240,9 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 * @param Timeout: Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, - uint32_t Timeout) +HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size, uint32_t Timeout) { - HAL_SPI_StateTypeDef tmp_state; HAL_StatusTypeDef errorcode = HAL_OK; #if defined (__GNUC__) __IO uint16_t *ptxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->TXDR)); @@ -1253,7 +1250,6 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD #endif /* __GNUC__ */ uint32_t tickstart; - uint32_t tmp_mode; uint16_t initial_TxXferCount; uint16_t initial_RxXferCount; @@ -1268,13 +1264,8 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD initial_TxXferCount = Size; initial_RxXferCount = Size; - tmp_state = hspi->State; - tmp_mode = hspi->Init.Mode; - if (!((tmp_state == HAL_SPI_STATE_READY) || \ - ((tmp_mode == SPI_MODE_MASTER) && \ - (hspi->Init.Direction == SPI_DIRECTION_2LINES) && \ - (tmp_state == HAL_SPI_STATE_BUSY_RX)))) + if (hspi->State != HAL_SPI_STATE_READY) { errorcode = HAL_BUSY; __HAL_UNLOCK(hspi); @@ -1288,18 +1279,13 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD return errorcode; } - /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ - if (hspi->State != HAL_SPI_STATE_BUSY_RX) - { - hspi->State = HAL_SPI_STATE_BUSY_TX_RX; - } - /* Set the transaction information */ + hspi->State = HAL_SPI_STATE_BUSY_TX_RX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; hspi->pRxBuffPtr = (uint8_t *)pRxData; hspi->RxXferCount = Size; hspi->RxXferSize = Size; - hspi->pTxBuffPtr = (uint8_t *)pTxData; + hspi->pTxBuffPtr = (const uint8_t *)pTxData; hspi->TxXferCount = Size; hspi->TxXferSize = Size; @@ -1307,6 +1293,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD hspi->RxISR = NULL; hspi->TxISR = NULL; + /* Set Full-Duplex mode */ + SPI_2LINES(hspi); + /* Set the number of data at current transfer */ MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size); @@ -1326,7 +1315,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD /* Check TXP flag */ if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP)) && (initial_TxXferCount > 0UL)) { - *((__IO uint32_t *)&hspi->Instance->TXDR) = *((uint32_t *)hspi->pTxBuffPtr); + *((__IO uint32_t *)&hspi->Instance->TXDR) = *((const uint32_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint32_t); hspi->TxXferCount --; initial_TxXferCount = hspi->TxXferCount; @@ -1361,50 +1350,30 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD { while ((initial_TxXferCount > 0UL) || (initial_RxXferCount > 0UL)) { - /* Check TXP flag */ + /* Check the TXP flag */ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP) && (initial_TxXferCount > 0UL)) { - if ((initial_TxXferCount > 1UL) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_01DATA)) - { - *((__IO uint32_t *)&hspi->Instance->TXDR) = *((uint32_t *)hspi->pTxBuffPtr); - hspi->pTxBuffPtr += sizeof(uint32_t); - hspi->TxXferCount -= (uint16_t)2UL; - initial_TxXferCount = hspi->TxXferCount; - } - else - { #if defined (__GNUC__) - *ptxdr_16bits = *((uint16_t *)hspi->pTxBuffPtr); + *ptxdr_16bits = *((const uint16_t *)hspi->pTxBuffPtr); #else - *((__IO uint16_t *)&hspi->Instance->TXDR) = *((uint16_t *)hspi->pTxBuffPtr); + *((__IO uint16_t *)&hspi->Instance->TXDR) = *((const uint16_t *)hspi->pTxBuffPtr); #endif /* __GNUC__ */ - hspi->pTxBuffPtr += sizeof(uint16_t); - hspi->TxXferCount--; - initial_TxXferCount = hspi->TxXferCount; - } + hspi->pTxBuffPtr += sizeof(uint16_t); + hspi->TxXferCount--; + initial_TxXferCount = hspi->TxXferCount; } - /* Check RXWNE/FRLVL flag */ - if (((hspi->Instance->SR & (SPI_FLAG_RXWNE | SPI_FLAG_FRLVL)) != 0UL) && (initial_RxXferCount > 0UL)) + /* Check the RXP flag */ + if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXP)) && (initial_RxXferCount > 0UL)) { - if ((hspi->Instance->SR & SPI_FLAG_RXWNE) != 0UL) - { - *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR); - hspi->pRxBuffPtr += sizeof(uint32_t); - hspi->RxXferCount -= (uint16_t)2UL; - initial_RxXferCount = hspi->RxXferCount; - } - else - { #if defined (__GNUC__) - *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits; + *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits; #else - *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR); + *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR); #endif /* __GNUC__ */ - hspi->pRxBuffPtr += sizeof(uint16_t); - hspi->RxXferCount--; - initial_RxXferCount = hspi->RxXferCount; - } + hspi->pRxBuffPtr += sizeof(uint16_t); + hspi->RxXferCount--; + initial_RxXferCount = hspi->RxXferCount; } /* Timeout management */ @@ -1427,64 +1396,22 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD { while ((initial_TxXferCount > 0UL) || (initial_RxXferCount > 0UL)) { - /* check TXP flag */ + /* Check the TXP flag */ if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP)) && (initial_TxXferCount > 0UL)) { - if ((initial_TxXferCount > 3UL) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_03DATA)) - { - *((__IO uint32_t *)&hspi->Instance->TXDR) = *((uint32_t *)hspi->pTxBuffPtr); - hspi->pTxBuffPtr += sizeof(uint32_t); - hspi->TxXferCount -= (uint16_t)4UL; - initial_TxXferCount = hspi->TxXferCount; - } - else if ((initial_TxXferCount > 1UL) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_01DATA)) - { -#if defined (__GNUC__) - *ptxdr_16bits = *((uint16_t *)hspi->pTxBuffPtr); -#else - *((__IO uint16_t *)&hspi->Instance->TXDR) = *((uint16_t *)hspi->pTxBuffPtr); -#endif /* __GNUC__ */ - hspi->pTxBuffPtr += sizeof(uint16_t); - hspi->TxXferCount -= (uint16_t)2UL; - initial_TxXferCount = hspi->TxXferCount; - } - else - { - *((__IO uint8_t *)&hspi->Instance->TXDR) = *((uint8_t *)hspi->pTxBuffPtr); - hspi->pTxBuffPtr += sizeof(uint8_t); - hspi->TxXferCount--; - initial_TxXferCount = hspi->TxXferCount; - } + *((__IO uint8_t *)&hspi->Instance->TXDR) = *((const uint8_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint8_t); + hspi->TxXferCount--; + initial_TxXferCount = hspi->TxXferCount; } - /* Wait until RXWNE/FRLVL flag is reset */ - if (((hspi->Instance->SR & (SPI_FLAG_RXWNE | SPI_FLAG_FRLVL)) != 0UL) && (initial_RxXferCount > 0UL)) + /* Check the RXP flag */ + if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXP)) && (initial_RxXferCount > 0UL)) { - if ((hspi->Instance->SR & SPI_FLAG_RXWNE) != 0UL) - { - *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR); - hspi->pRxBuffPtr += sizeof(uint32_t); - hspi->RxXferCount -= (uint16_t)4UL; - initial_RxXferCount = hspi->RxXferCount; - } - else if ((hspi->Instance->SR & SPI_FLAG_FRLVL) > SPI_RX_FIFO_1PACKET) - { -#if defined (__GNUC__) - *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits; -#else - *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR); -#endif /* __GNUC__ */ - hspi->pRxBuffPtr += sizeof(uint16_t); - hspi->RxXferCount -= (uint16_t)2UL; - initial_RxXferCount = hspi->RxXferCount; - } - else - { - *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR); - hspi->pRxBuffPtr += sizeof(uint8_t); - hspi->RxXferCount--; - initial_RxXferCount = hspi->RxXferCount; - } + *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint8_t); + hspi->RxXferCount--; + initial_RxXferCount = hspi->RxXferCount; } /* Timeout management */ @@ -1532,7 +1459,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD * @param Size : amount of data to be sent * @retval HAL status */ -HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size) { HAL_StatusTypeDef errorcode = HAL_OK; @@ -1559,7 +1486,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_TX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pTxBuffPtr = (uint8_t *)pData; + hspi->pTxBuffPtr = (const uint8_t *)pData; hspi->TxXferSize = Size; hspi->TxXferCount = Size; @@ -1588,6 +1515,10 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u { SPI_1LINE_TX(hspi); } + else + { + SPI_2LINES_TX(hspi); + } /* Set the number of data at current transfer */ MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size); @@ -1623,13 +1554,6 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(hspi->Init.Direction)); - if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER)) - { - hspi->State = HAL_SPI_STATE_BUSY_RX; - /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */ - return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size); - } - /* Lock the process */ __HAL_LOCK(hspi); @@ -1679,6 +1603,10 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui { SPI_1LINE_RX(hspi); } + else + { + SPI_2LINES_RX(hspi); + } /* Note : The SPI must be enabled after unlocking current process to avoid the risk of SPI interrupt handle execution before current @@ -1713,33 +1641,23 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui * @param Size : amount of data to be sent and received * @retval HAL status */ -HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) +HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size) { - HAL_SPI_StateTypeDef tmp_state; HAL_StatusTypeDef errorcode = HAL_OK; - uint32_t max_fifo_length = 0UL; uint32_t tmp_TxXferCount; #if defined (__GNUC__) __IO uint16_t *ptxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->TXDR)); #endif /* __GNUC__ */ - uint32_t tmp_mode; - /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); /* Lock the process */ __HAL_LOCK(hspi); - /* Init temporary variables */ - tmp_state = hspi->State; - tmp_mode = hspi->Init.Mode; - - if (!((tmp_state == HAL_SPI_STATE_READY) || \ - ((tmp_mode == SPI_MODE_MASTER) && \ - (hspi->Init.Direction == SPI_DIRECTION_2LINES) && \ - (tmp_state == HAL_SPI_STATE_BUSY_RX)))) + if (hspi->State != HAL_SPI_STATE_READY) { errorcode = HAL_BUSY; __HAL_UNLOCK(hspi); @@ -1753,15 +1671,10 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p return errorcode; } - /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ - if (hspi->State != HAL_SPI_STATE_BUSY_RX) - { - hspi->State = HAL_SPI_STATE_BUSY_TX_RX; - } - /* Set the transaction information */ + hspi->State = HAL_SPI_STATE_BUSY_TX_RX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pTxBuffPtr = (uint8_t *)pTxData; + hspi->pTxBuffPtr = (const uint8_t *)pTxData; hspi->TxXferSize = Size; hspi->TxXferCount = Size; hspi->pRxBuffPtr = (uint8_t *)pRxData; @@ -1786,6 +1699,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p hspi->TxISR = SPI_TxISR_8BIT; } + /* Set Full-Duplex mode */ + SPI_2LINES(hspi); + /* Set the number of data at current transfer */ MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size); @@ -1795,75 +1711,33 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p /* Fill in the TxFIFO */ while ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP)) && (tmp_TxXferCount != 0UL)) { - if (max_fifo_length < MAX_FIFO_LENGTH) + /* Transmit data in 32 Bit mode */ + if (hspi->Init.DataSize > SPI_DATASIZE_16BIT) + { + *((__IO uint32_t *)&hspi->Instance->TXDR) = *((const uint32_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint32_t); + hspi->TxXferCount--; + tmp_TxXferCount = hspi->TxXferCount; + } + /* Transmit data in 16 Bit mode */ + else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) { - /* Transmit data in 32 Bit mode */ - if (hspi->Init.DataSize > SPI_DATASIZE_16BIT) - { - *((__IO uint32_t *)&hspi->Instance->TXDR) = *((uint32_t *)hspi->pTxBuffPtr); - hspi->pTxBuffPtr += sizeof(uint32_t); - hspi->TxXferCount--; - tmp_TxXferCount = hspi->TxXferCount; - } - /* Transmit data in 16 Bit mode */ - else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) - { - if ((hspi->TxXferCount > 1UL) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_01DATA)) - { - *((__IO uint32_t *)&hspi->Instance->TXDR) = *((uint32_t *)hspi->pTxBuffPtr); - hspi->pTxBuffPtr += sizeof(uint32_t); - hspi->TxXferCount -= (uint16_t)2UL; - tmp_TxXferCount = hspi->TxXferCount; - } - else - { -#if defined (__GNUC__) - *ptxdr_16bits = *((uint16_t *)hspi->pTxBuffPtr); -#else - *((__IO uint16_t *)&hspi->Instance->TXDR) = *((uint16_t *)hspi->pTxBuffPtr); -#endif /* __GNUC__ */ - hspi->pTxBuffPtr += sizeof(uint16_t); - hspi->TxXferCount--; - tmp_TxXferCount = hspi->TxXferCount; - } - } - /* Transmit data in 8 Bit mode */ - else - { - if ((hspi->TxXferCount > 3UL) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_03DATA)) - { - *((__IO uint32_t *)&hspi->Instance->TXDR) = *((uint32_t *)hspi->pTxBuffPtr); - hspi->pTxBuffPtr += sizeof(uint32_t); - hspi->TxXferCount -= (uint16_t)4UL; - tmp_TxXferCount = hspi->TxXferCount; - } - else if ((hspi->TxXferCount > 1UL) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_01DATA)) - { #if defined (__GNUC__) - *ptxdr_16bits = *((uint16_t *)hspi->pTxBuffPtr); + *ptxdr_16bits = *((const uint16_t *)hspi->pTxBuffPtr); #else - *((__IO uint16_t *)&hspi->Instance->TXDR) = *((uint16_t *)hspi->pTxBuffPtr); + *((__IO uint16_t *)&hspi->Instance->TXDR) = *((const uint16_t *)hspi->pTxBuffPtr); #endif /* __GNUC__ */ - hspi->pTxBuffPtr += sizeof(uint16_t); - hspi->TxXferCount -= (uint16_t)2UL; - tmp_TxXferCount = hspi->TxXferCount; - } - else - { - *((__IO uint8_t *)&hspi->Instance->TXDR) = *((uint8_t *)hspi->pTxBuffPtr); - hspi->pTxBuffPtr += sizeof(uint8_t); - hspi->TxXferCount--; - tmp_TxXferCount = hspi->TxXferCount; - } - } - - max_fifo_length++; + hspi->pTxBuffPtr += sizeof(uint16_t); + hspi->TxXferCount--; + tmp_TxXferCount = hspi->TxXferCount; } + /* Transmit data in 8 Bit mode */ else { - errorcode = HAL_BUSY; - __HAL_UNLOCK(hspi); - return errorcode; + *((__IO uint8_t *)&hspi->Instance->TXDR) = *((const uint8_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint8_t); + hspi->TxXferCount--; + tmp_TxXferCount = hspi->TxXferCount; } } @@ -1891,7 +1765,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p * @param Size : amount of data to be sent * @retval HAL status */ -HAL_StatusTypeDef HAL_SPI_Reload_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_SPI_Reload_Transmit_IT(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size) { HAL_StatusTypeDef errorcode = HAL_OK; HAL_SPI_StateTypeDef tmp_state; @@ -1921,7 +1795,7 @@ HAL_StatusTypeDef HAL_SPI_Reload_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *p /* Set the transaction information */ hspi->Reload.Requested = 1UL; - hspi->Reload.pTxBuffPtr = (uint8_t *)pData; + hspi->Reload.pTxBuffPtr = (const uint8_t *)pData; hspi->Reload.TxXferSize = Size; tmp_state = hspi->State; @@ -2024,7 +1898,8 @@ HAL_StatusTypeDef HAL_SPI_Reload_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pD * @param Size : amount of data to be sent and received * @retval HAL status */ -HAL_StatusTypeDef HAL_SPI_Reload_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) +HAL_StatusTypeDef HAL_SPI_Reload_TransmitReceive_IT(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, + uint8_t *pRxData, uint16_t Size) { HAL_StatusTypeDef errorcode = HAL_OK; HAL_SPI_StateTypeDef tmp_state; @@ -2054,7 +1929,7 @@ HAL_StatusTypeDef HAL_SPI_Reload_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uin /* Set the transaction information */ hspi->Reload.Requested = 1UL; - hspi->Reload.pTxBuffPtr = (uint8_t *)pTxData; + hspi->Reload.pTxBuffPtr = (const uint8_t *)pTxData; hspi->Reload.TxXferSize = Size; hspi->Reload.pRxBuffPtr = (uint8_t *)pRxData; hspi->Reload.RxXferSize = Size; @@ -2091,7 +1966,7 @@ HAL_StatusTypeDef HAL_SPI_Reload_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uin * @param Size : amount of data to be sent * @retval HAL status */ -HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size) { HAL_StatusTypeDef errorcode = HAL_OK; @@ -2118,7 +1993,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_TX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pTxBuffPtr = (uint8_t *)pData; + hspi->pTxBuffPtr = (const uint8_t *)pData; hspi->TxXferSize = Size; hspi->TxXferCount = Size; @@ -2134,6 +2009,10 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, { SPI_1LINE_TX(hspi); } + else + { + SPI_2LINES_TX(hspi); + } /* Packing mode management is enabled by the DMA settings */ if (((hspi->Init.DataSize > SPI_DATASIZE_16BIT) && (hspi->hdmatx->Init.MemDataAlignment != DMA_MDATAALIGN_WORD)) || \ @@ -2246,13 +2125,6 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(hspi->Init.Direction)); - if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER)) - { - hspi->State = HAL_SPI_STATE_BUSY_RX; - /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */ - return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size); - } - /* Lock the process */ __HAL_LOCK(hspi); @@ -2288,6 +2160,10 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u { SPI_1LINE_RX(hspi); } + else + { + SPI_2LINES_RX(hspi); + } /* Packing mode management is enabled by the DMA settings */ if (((hspi->Init.DataSize > SPI_DATASIZE_16BIT) && (hspi->hdmarx->Init.MemDataAlignment != DMA_MDATAALIGN_WORD)) || \ @@ -2394,28 +2270,18 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u * @note When the CRC feature is enabled the pRxData Length must be Size + 1 * @retval HAL status */ -HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, +HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) { - HAL_SPI_StateTypeDef tmp_state; HAL_StatusTypeDef errorcode = HAL_OK; - uint32_t tmp_mode; - /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); /* Lock the process */ __HAL_LOCK(hspi); - /* Init temporary variables */ - tmp_state = hspi->State; - tmp_mode = hspi->Init.Mode; - - if (!((tmp_state == HAL_SPI_STATE_READY) || \ - ((tmp_mode == SPI_MODE_MASTER) && \ - (hspi->Init.Direction == SPI_DIRECTION_2LINES) && \ - (tmp_state == HAL_SPI_STATE_BUSY_RX)))) + if (hspi->State != HAL_SPI_STATE_READY) { errorcode = HAL_BUSY; __HAL_UNLOCK(hspi); @@ -2429,15 +2295,10 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * return errorcode; } - /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ - if (hspi->State != HAL_SPI_STATE_BUSY_RX) - { - hspi->State = HAL_SPI_STATE_BUSY_TX_RX; - } - /* Set the transaction information */ + hspi->State = HAL_SPI_STATE_BUSY_TX_RX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pTxBuffPtr = (uint8_t *)pTxData; + hspi->pTxBuffPtr = (const uint8_t *)pTxData; hspi->TxXferSize = Size; hspi->TxXferCount = Size; hspi->pRxBuffPtr = (uint8_t *)pRxData; @@ -2448,6 +2309,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * hspi->RxISR = NULL; hspi->TxISR = NULL; + /* Set Full-Duplex mode */ + SPI_2LINES(hspi); + /* Reset the Tx/Rx DMA bits */ CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN); @@ -2541,9 +2405,11 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * is performed in DMA reception complete callback */ hspi->hdmatx->XferHalfCpltCallback = NULL; hspi->hdmatx->XferCpltCallback = NULL; - hspi->hdmatx->XferErrorCallback = NULL; hspi->hdmatx->XferAbortCallback = NULL; + /* Set the DMA error callback */ + hspi->hdmatx->XferErrorCallback = SPI_DMAError; + /* Enable the Tx DMA Stream/Channel */ if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->TXDR, hspi->TxXferCount)) @@ -2620,6 +2486,20 @@ HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi) /* If master communication on going, make sure current frame is done before closing the connection */ if (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART)) { + /* Disable EOT interrupt */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_EOT); + do + { + count--; + if (count == 0UL) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + break; + } + } + while (HAL_IS_BIT_SET(hspi->Instance->IER, SPI_IT_EOT)); + + /* Request a Suspend transfer */ SET_BIT(hspi->Instance->CR1, SPI_CR1_CSUSP); do { @@ -2629,7 +2509,21 @@ HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi) SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); break; } - } while (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART)); + } + while (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART)); + + /* Clear SUSP flag */ + __HAL_SPI_CLEAR_SUSPFLAG(hspi); + do + { + count--; + if (count == 0UL) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + break; + } + } + while (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_SUSP)); } /* Disable the SPI DMA Tx request if enabled */ @@ -2726,6 +2620,20 @@ HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi) /* If master communication on going, make sure current frame is done before closing the connection */ if (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART)) { + /* Disable EOT interrupt */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_EOT); + do + { + count--; + if (count == 0UL) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + break; + } + } + while (HAL_IS_BIT_SET(hspi->Instance->IER, SPI_IT_EOT)); + + /* Request a Suspend transfer */ SET_BIT(hspi->Instance->CR1, SPI_CR1_CSUSP); do { @@ -2735,7 +2643,21 @@ HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi) SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); break; } - } while (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART)); + } + while (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART)); + + /* Clear SUSP flag */ + __HAL_SPI_CLEAR_SUSPFLAG(hspi); + do + { + count--; + if (count == 0UL) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + break; + } + } + while (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_SUSP)); } /* If DMA Tx and/or DMA Rx Handles are associated to SPI Handle, DMA Abort complete callbacks should be initialized @@ -2887,6 +2809,20 @@ void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi) __IO uint16_t *prxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->RXDR)); #endif /* __GNUC__ */ + /* SPI in SUSPEND mode ----------------------------------------------------*/ + if (HAL_IS_BIT_SET(itflag, SPI_FLAG_SUSP) && HAL_IS_BIT_SET(itsource, SPI_FLAG_EOT)) + { + /* Clear the Suspend flag */ + __HAL_SPI_CLEAR_SUSPFLAG(hspi); + + /* Suspend on going, Call the Suspend callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) + hspi->SuspendCallback(hspi); +#else + HAL_SPI_SuspendCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + return; + } /* SPI in mode Transmitter and Receiver ------------------------------------*/ if (HAL_IS_BIT_CLR(trigger, SPI_FLAG_OVR) && HAL_IS_BIT_CLR(trigger, SPI_FLAG_UDR) && \ @@ -2938,57 +2874,51 @@ void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi) /* Disable EOT interrupt */ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_EOT); - /* DMA Normal Mode */ - if (HAL_IS_BIT_CLR(cfg1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN) || - ((State != HAL_SPI_STATE_BUSY_RX) && (hspi->hdmatx->Init.Mode == DMA_NORMAL)) || - ((State != HAL_SPI_STATE_BUSY_TX) && (hspi->hdmarx->Init.Mode == DMA_NORMAL))) + /* For the IT based receive extra polling maybe required for last packet */ + if (HAL_IS_BIT_CLR(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN)) { - /* For the IT based receive extra polling maybe required for last packet */ - if (HAL_IS_BIT_CLR(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN)) + /* Pooling remaining data */ + while (hspi->RxXferCount != 0UL) { - /* Pooling remaining data */ - while (hspi->RxXferCount != 0UL) + /* Receive data in 32 Bit mode */ + if (hspi->Init.DataSize > SPI_DATASIZE_16BIT) + { + *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint32_t); + } + /* Receive data in 16 Bit mode */ + else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) { - /* Receive data in 32 Bit mode */ - if (hspi->Init.DataSize > SPI_DATASIZE_16BIT) - { - *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR); - hspi->pRxBuffPtr += sizeof(uint32_t); - } - /* Receive data in 16 Bit mode */ - else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) - { #if defined (__GNUC__) - *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits; + *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits; #else - *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR); + *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR); #endif /* __GNUC__ */ - hspi->pRxBuffPtr += sizeof(uint16_t); - } - /* Receive data in 8 Bit mode */ - else - { - *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR); - hspi->pRxBuffPtr += sizeof(uint8_t); - } - - hspi->RxXferCount--; + hspi->pRxBuffPtr += sizeof(uint16_t); + } + /* Receive data in 8 Bit mode */ + else + { + *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint8_t); } + + hspi->RxXferCount--; } + } - /* Call SPI Standard close procedure */ - SPI_CloseTransfer(hspi); + /* Call SPI Standard close procedure */ + SPI_CloseTransfer(hspi); - hspi->State = HAL_SPI_STATE_READY; - if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) - { + hspi->State = HAL_SPI_STATE_READY; + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) + { #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) - hspi->ErrorCallback(hspi); + hspi->ErrorCallback(hspi); #else - HAL_SPI_ErrorCallback(hspi); + HAL_SPI_ErrorCallback(hspi); #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ - return; - } + return; } #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) @@ -3028,14 +2958,6 @@ void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi) return; } - if (HAL_IS_BIT_SET(itflag, SPI_FLAG_SUSP) && HAL_IS_BIT_SET(itsource, SPI_FLAG_EOT)) - { - /* Abort on going, clear SUSP flag to avoid infinite looping */ - __HAL_SPI_CLEAR_SUSPFLAG(hspi); - - return; - } - /* SPI in Error Treatment --------------------------------------------------*/ if ((trigger & (SPI_FLAG_MODF | SPI_FLAG_OVR | SPI_FLAG_FRE | SPI_FLAG_UDR)) != 0UL) { @@ -3252,6 +3174,21 @@ __weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi) */ } +/** + * @brief SPI Suspend callback. + * @param hspi SPI handle. + * @retval None + */ +__weak void HAL_SPI_SuspendCallback(SPI_HandleTypeDef *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_SuspendCallback can be implemented in the user file. + */ +} + /** * @} */ @@ -3277,7 +3214,7 @@ __weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi) * the configuration information for SPI module. * @retval SPI state */ -HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi) +HAL_SPI_StateTypeDef HAL_SPI_GetState(const SPI_HandleTypeDef *hspi) { /* Return SPI handle state */ return hspi->State; @@ -3289,7 +3226,7 @@ HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi) * the configuration information for SPI module. * @retval SPI error code in bitmap format */ -uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi) +uint32_t HAL_SPI_GetError(const SPI_HandleTypeDef *hspi) { /* Return SPI ErrorCode */ return hspi->ErrorCode; @@ -3691,7 +3628,7 @@ static void SPI_RxISR_32BIT(SPI_HandleTypeDef *hspi) static void SPI_TxISR_8BIT(SPI_HandleTypeDef *hspi) { /* Transmit data in 8 Bit mode */ - *(__IO uint8_t *)&hspi->Instance->TXDR = *((uint8_t *)hspi->pTxBuffPtr); + *(__IO uint8_t *)&hspi->Instance->TXDR = *((const uint8_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint8_t); hspi->TxXferCount--; @@ -3730,9 +3667,9 @@ static void SPI_TxISR_16BIT(SPI_HandleTypeDef *hspi) #if defined (__GNUC__) __IO uint16_t *ptxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->TXDR)); - *ptxdr_16bits = *((uint16_t *)hspi->pTxBuffPtr); + *ptxdr_16bits = *((const uint16_t *)hspi->pTxBuffPtr); #else - *((__IO uint16_t *)&hspi->Instance->TXDR) = *((uint16_t *)hspi->pTxBuffPtr); + *((__IO uint16_t *)&hspi->Instance->TXDR) = *((const uint16_t *)hspi->pTxBuffPtr); #endif /* __GNUC__ */ hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount--; @@ -3769,7 +3706,7 @@ static void SPI_TxISR_16BIT(SPI_HandleTypeDef *hspi) static void SPI_TxISR_32BIT(SPI_HandleTypeDef *hspi) { /* Transmit data in 32 Bit mode */ - *((__IO uint32_t *)&hspi->Instance->TXDR) = *((uint32_t *)hspi->pTxBuffPtr); + *((__IO uint32_t *)&hspi->Instance->TXDR) = *((const uint32_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint32_t); hspi->TxXferCount--; diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_spi_ex.c b/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_spi_ex.c index 3bce154f68..4687fa512d 100644 --- a/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_spi_ex.c +++ b/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_spi_ex.c @@ -72,7 +72,7 @@ * the configuration information for the specified SPI module. * @retval HAL status */ -HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(SPI_HandleTypeDef *hspi) +HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(const SPI_HandleTypeDef *hspi) { uint8_t count = 0; uint32_t itflag = hspi->Instance->SR; diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_usart.c b/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_usart.c index 3aaf3623c4..b0b38e80f1 100644 --- a/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_usart.c +++ b/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_usart.c @@ -73,8 +73,8 @@ allows the user to configure dynamically the driver callbacks. [..] - Use Function @ref HAL_USART_RegisterCallback() to register a user callback. - Function @ref HAL_USART_RegisterCallback() allows to register following callbacks: + Use Function HAL_USART_RegisterCallback() to register a user callback. + Function HAL_USART_RegisterCallback() allows to register following callbacks: (+) TxHalfCpltCallback : Tx Half Complete Callback. (+) TxCpltCallback : Tx Complete Callback. (+) RxHalfCpltCallback : Rx Half Complete Callback. @@ -90,9 +90,9 @@ and a pointer to the user callback function. [..] - Use function @ref HAL_USART_UnRegisterCallback() to reset a callback to the default + Use function HAL_USART_UnRegisterCallback() to reset a callback to the default weak (surcharged) function. - @ref HAL_USART_UnRegisterCallback() takes as parameters the HAL peripheral handle, + HAL_USART_UnRegisterCallback() takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: (+) TxHalfCpltCallback : Tx Half Complete Callback. @@ -108,13 +108,13 @@ (+) MspDeInitCallback : USART MspDeInit. [..] - By default, after the @ref HAL_USART_Init() and when the state is HAL_USART_STATE_RESET + By default, after the HAL_USART_Init() and when the state is HAL_USART_STATE_RESET all callbacks are set to the corresponding weak (surcharged) functions: - examples @ref HAL_USART_TxCpltCallback(), @ref HAL_USART_RxHalfCpltCallback(). + examples HAL_USART_TxCpltCallback(), HAL_USART_RxHalfCpltCallback(). Exception done for MspInit and MspDeInit functions that are respectively - reset to the legacy weak (surcharged) functions in the @ref HAL_USART_Init() - and @ref HAL_USART_DeInit() only when these callbacks are null (not registered beforehand). - If not, MspInit or MspDeInit are not null, the @ref HAL_USART_Init() and @ref HAL_USART_DeInit() + reset to the legacy weak (surcharged) functions in the HAL_USART_Init() + and HAL_USART_DeInit() only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_USART_Init() and HAL_USART_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand). [..] @@ -123,8 +123,8 @@ in HAL_USART_STATE_READY or HAL_USART_STATE_RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_USART_RegisterCallback() before calling @ref HAL_USART_DeInit() - or @ref HAL_USART_Init() function. + using HAL_USART_RegisterCallback() before calling HAL_USART_DeInit() + or HAL_USART_Init() function. [..] When The compilation define USE_HAL_USART_REGISTER_CALLBACKS is set to 0 or @@ -756,10 +756,11 @@ HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_ * @param Timeout Timeout duration. * @retval HAL status */ -HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout) +HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size, + uint32_t Timeout) { - uint8_t *ptxdata8bits; - uint16_t *ptxdata16bits; + const uint8_t *ptxdata8bits; + const uint16_t *ptxdata16bits; uint32_t tickstart; if (husart->State == HAL_USART_STATE_READY) @@ -785,7 +786,7 @@ HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxDa if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) { ptxdata8bits = NULL; - ptxdata16bits = (uint16_t *) pTxData; + ptxdata16bits = (const uint16_t *) pTxData; } else { @@ -965,13 +966,13 @@ HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxDat * @param Timeout Timeout duration. * @retval HAL status */ -HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, +HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout) { uint8_t *prxdata8bits; uint16_t *prxdata16bits; - uint8_t *ptxdata8bits; - uint16_t *ptxdata16bits; + const uint8_t *ptxdata8bits; + const uint16_t *ptxdata16bits; uint16_t uhMask; uint16_t rxdatacount; uint32_t tickstart; @@ -1006,7 +1007,7 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t { prxdata8bits = NULL; ptxdata8bits = NULL; - ptxdata16bits = (uint16_t *) pTxData; + ptxdata16bits = (const uint16_t *) pTxData; prxdata16bits = (uint16_t *) pRxData; } else @@ -1112,7 +1113,7 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t * @param Size amount of data elements (u8 or u16) to be sent. * @retval HAL status */ -HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size) +HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size) { if (husart->State == HAL_USART_STATE_READY) { @@ -1239,7 +1240,10 @@ HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRx __HAL_UNLOCK(husart); /* Enable the USART Parity Error interrupt and RX FIFO Threshold interrupt */ - SET_BIT(husart->Instance->CR1, USART_CR1_PEIE); + if (husart->Init.Parity != USART_PARITY_NONE) + { + SET_BIT(husart->Instance->CR1, USART_CR1_PEIE); + } SET_BIT(husart->Instance->CR3, USART_CR3_RXFTIE); } else @@ -1258,7 +1262,14 @@ HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRx __HAL_UNLOCK(husart); /* Enable the USART Parity Error and Data Register not empty Interrupts */ - SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE); + if (husart->Init.Parity != USART_PARITY_NONE) + { + SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE); + } + else + { + SET_BIT(husart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); + } } if (husart->SlaveMode == USART_SLAVEMODE_DISABLE) @@ -1299,7 +1310,7 @@ HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRx * @param Size amount of data elements (u8 or u16) to be sent (same amount to be received). * @retval HAL status */ -HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, +HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) { @@ -1347,8 +1358,11 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */ SET_BIT(husart->Instance->CR3, USART_CR3_EIE); - /* Enable the USART Parity Error interrupt */ - SET_BIT(husart->Instance->CR1, USART_CR1_PEIE); + if (husart->Init.Parity != USART_PARITY_NONE) + { + /* Enable the USART Parity Error interrupt */ + SET_BIT(husart->Instance->CR1, USART_CR1_PEIE); + } /* Enable the TX and RX FIFO Threshold interrupts */ SET_BIT(husart->Instance->CR3, (USART_CR3_TXFTIE | USART_CR3_RXFTIE)); @@ -1373,7 +1387,14 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint SET_BIT(husart->Instance->CR3, USART_CR3_EIE); /* Enable the USART Parity Error and USART Data Register not empty Interrupts */ - SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE); + if (husart->Init.Parity != USART_PARITY_NONE) + { + SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE); + } + else + { + SET_BIT(husart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); + } /* Enable the USART Transmit Data Register Empty Interrupt */ SET_BIT(husart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); @@ -1397,10 +1418,10 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint * @param Size amount of data elements (u8 or u16) to be sent. * @retval HAL status */ -HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size) +HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size) { HAL_StatusTypeDef status = HAL_OK; - uint32_t *tmp; + const uint32_t *tmp; if (husart->State == HAL_USART_STATE_READY) { @@ -1431,8 +1452,8 @@ HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *p husart->hdmatx->XferErrorCallback = USART_DMAError; /* Enable the USART transmit DMA channel */ - tmp = (uint32_t *)&pTxData; - status = HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t *)tmp, (uint32_t)&husart->Instance->TDR, Size); + tmp = (const uint32_t *)&pTxData; + status = HAL_DMA_Start_IT(husart->hdmatx, *(const uint32_t *)tmp, (uint32_t)&husart->Instance->TDR, Size); } #ifdef HAL_MDMA_MODULE_ENABLED if (husart->hmdmatx != NULL) @@ -1444,8 +1465,8 @@ HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *p husart->hmdmatx->XferErrorCallback = USART_MDMAError; /* Enable the USART transmit MDMA channel */ - tmp = (uint32_t *)&pTxData; - status = HAL_MDMA_Start_IT(husart->hmdmatx, *(uint32_t *)tmp, (uint32_t)&husart->Instance->TDR, Size, 1); + tmp = (const uint32_t *)&pTxData; + status = HAL_MDMA_Start_IT(husart->hmdmatx, *(const uint32_t *)tmp, (uint32_t)&husart->Instance->TDR, Size, 1); } #endif @@ -1578,8 +1599,11 @@ HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pR /* Process Unlocked */ __HAL_UNLOCK(husart); - /* Enable the USART Parity Error Interrupt */ - SET_BIT(husart->Instance->CR1, USART_CR1_PEIE); + if (husart->Init.Parity != USART_PARITY_NONE) + { + /* Enable the USART Parity Error Interrupt */ + SET_BIT(husart->Instance->CR1, USART_CR1_PEIE); + } /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */ SET_BIT(husart->Instance->CR3, USART_CR3_EIE); @@ -1640,11 +1664,11 @@ HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pR * @param Size amount of data elements (u8 or u16) to be received/sent. * @retval HAL status */ -HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, +HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) { HAL_StatusTypeDef status; - uint32_t *tmp; + const uint32_t *tmp; if (husart->State == HAL_USART_STATE_READY) { @@ -1686,13 +1710,13 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uin /* Enable the USART receive DMA channel */ tmp = (uint32_t *)&pRxData; - status = HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->RDR, *(uint32_t *)tmp, Size); + status = HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->RDR, *(const uint32_t *)tmp, Size); /* Enable the USART transmit DMA channel */ if (status == HAL_OK) { - tmp = (uint32_t *)&pTxData; - status = HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t *)tmp, (uint32_t)&husart->Instance->TDR, Size); + tmp = (const uint32_t *)&pTxData; + status = HAL_DMA_Start_IT(husart->hdmatx, *(const uint32_t *)tmp, (uint32_t)&husart->Instance->TDR, Size); } } else @@ -1722,7 +1746,7 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uin /* Enable the USART transmit MDMA channel */ if (status == HAL_OK) { - tmp = (uint32_t *)&pTxData; + tmp = (const uint32_t *)&pTxData; status = HAL_MDMA_Start_IT(husart->hmdmatx, *(uint32_t *)tmp, (uint32_t)&husart->Instance->TDR, Size, 1); } } @@ -1737,8 +1761,11 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uin /* Process Unlocked */ __HAL_UNLOCK(husart); - /* Enable the USART Parity Error Interrupt */ - SET_BIT(husart->Instance->CR1, USART_CR1_PEIE); + if (husart->Init.Parity != USART_PARITY_NONE) + { + /* Enable the USART Parity Error Interrupt */ + SET_BIT(husart->Instance->CR1, USART_CR1_PEIE); + } /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */ SET_BIT(husart->Instance->CR3, USART_CR3_EIE); @@ -1861,7 +1888,10 @@ HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart) __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF); /* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */ - SET_BIT(husart->Instance->CR1, USART_CR1_PEIE); + if (husart->Init.Parity != USART_PARITY_NONE) + { + SET_BIT(husart->Instance->CR1, USART_CR1_PEIE); + } SET_BIT(husart->Instance->CR3, USART_CR3_EIE); /* Enable the USART DMA Rx request before the DMA Tx request */ @@ -1983,9 +2013,10 @@ HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart) USART_CR1_TCIE)); CLEAR_BIT(husart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE)); - /* Disable the USART DMA Tx request if enabled */ + /* Abort the USART DMA Tx channel if enabled */ if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT)) { + /* Disable the USART DMA Tx request if enabled */ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT); /* Abort the USART DMA Tx channel : use blocking DMA Abort API (no callback) */ @@ -2027,9 +2058,10 @@ HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart) #endif } - /* Disable the USART DMA Rx request if enabled */ + /* Abort the USART DMA Rx channel if enabled */ if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)) { + /* Disable the USART DMA Rx request if enabled */ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR); /* Abort the USART DMA Rx channel : use blocking DMA Abort API (no callback) */ @@ -2184,7 +2216,7 @@ HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart) } #endif - /* Disable the USART DMA Tx request if enabled */ + /* Abort the USART DMA Tx channel if enabled */ if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT)) { /* Disable DMA Tx at USART level */ @@ -2226,9 +2258,10 @@ HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart) #endif } - /* Disable the USART DMA Rx request if enabled */ + /* Abort the USART DMA Rx channel if enabled */ if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)) { + /* Disable the USART DMA Rx request if enabled */ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR); /* Abort the USART DMA Rx channel : use non blocking DMA Abort API (callback) */ @@ -2427,9 +2460,10 @@ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart) Disable Interrupts, and disable DMA requests, if ongoing */ USART_EndTransfer(husart); - /* Disable the USART DMA Rx request if enabled */ + /* Abort the USART DMA Rx channel if enabled */ if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)) { + /* Disable the USART DMA Rx request if enabled */ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR | USART_CR3_DMAR); /* Abort the USART DMA Tx channel */ @@ -3286,10 +3320,11 @@ static void USART_MDMARxAbortCallback(MDMA_HandleTypeDef *hmdma) #endif /** - * @brief Handle USART Communication Timeout. + * @brief Handle USART Communication Timeout. It waits + * until a flag is no longer in the specified status. * @param husart USART handle. * @param Flag Specifies the USART flag to check. - * @param Status the Flag status (SET or RESET). + * @param Status the actual Flag status (SET or RESET). * @param Tickstart Tick start value * @param Timeout timeout duration. * @retval HAL status @@ -3391,7 +3426,8 @@ static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart) break; case USART_CLOCKSOURCE_PLL3Q: HAL_RCC_GetPLL3ClockFreq(&pll3_clocks); - usartdiv = (uint32_t)(USART_DIV_SAMPLING8(pll3_clocks.PLL3_Q_Frequency, husart->Init.BaudRate, husart->Init.ClockPrescaler)); + usartdiv = (uint32_t)(USART_DIV_SAMPLING8(pll3_clocks.PLL3_Q_Frequency, husart->Init.BaudRate, + husart->Init.ClockPrescaler)); break; case USART_CLOCKSOURCE_PLL4Q: HAL_RCC_GetPLL4ClockFreq(&pll4_clocks); @@ -3527,7 +3563,7 @@ static void USART_TxISR_8BIT(USART_HandleTypeDef *husart) static void USART_TxISR_16BIT(USART_HandleTypeDef *husart) { const HAL_USART_StateTypeDef state = husart->State; - uint16_t *tmp; + const uint16_t *tmp; if ((state == HAL_USART_STATE_BUSY_TX) || (state == HAL_USART_STATE_BUSY_TX_RX)) @@ -3542,7 +3578,7 @@ static void USART_TxISR_16BIT(USART_HandleTypeDef *husart) } else { - tmp = (uint16_t *) husart->pTxBuffPtr; + tmp = (const uint16_t *) husart->pTxBuffPtr; husart->Instance->TDR = (uint16_t)(*tmp & 0x01FFU); husart->pTxBuffPtr += 2U; husart->TxXferCount--; @@ -3608,7 +3644,7 @@ static void USART_TxISR_8BIT_FIFOEN(USART_HandleTypeDef *husart) static void USART_TxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart) { const HAL_USART_StateTypeDef state = husart->State; - uint16_t *tmp; + const uint16_t *tmp; uint16_t nb_tx_data; /* Check that a Tx process is ongoing */ @@ -3629,7 +3665,7 @@ static void USART_TxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart) } else if (__HAL_USART_GET_FLAG(husart, USART_FLAG_TXFNF) == SET) { - tmp = (uint16_t *) husart->pTxBuffPtr; + tmp = (const uint16_t *) husart->pTxBuffPtr; husart->Instance->TDR = (uint16_t)(*tmp & 0x01FFU); husart->pTxBuffPtr += 2U; husart->TxXferCount--; diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_usart_ex.c b/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_usart_ex.c index 5cd9a86cbe..c2e8a5f4ea 100644 --- a/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_usart_ex.c +++ b/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_usart_ex.c @@ -58,10 +58,10 @@ * @{ */ /* USART RX FIFO depth */ -#define RX_FIFO_DEPTH 8U +#define RX_FIFO_DEPTH 16U /* USART TX FIFO depth */ -#define TX_FIFO_DEPTH 8U +#define TX_FIFO_DEPTH 16U /** * @} */ diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_ll_adc.c b/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_ll_adc.c index a2552f4683..cdab6d37a5 100644 --- a/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_ll_adc.c +++ b/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_ll_adc.c @@ -347,25 +347,25 @@ ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON) * must be disabled. * @param ADCxy_COMMON ADC common instance * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) - * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure + * @param pADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure * @retval An ErrorStatus enumeration value: * - SUCCESS: ADC common registers are initialized * - ERROR: ADC common registers are not initialized */ -ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct) +ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct) { ErrorStatus status = SUCCESS; /* Check the parameters */ assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON)); - assert_param(IS_LL_ADC_COMMON_CLOCK(ADC_CommonInitStruct->CommonClock)); + assert_param(IS_LL_ADC_COMMON_CLOCK(pADC_CommonInitStruct->CommonClock)); #if defined(ADC_MULTIMODE_SUPPORT) - assert_param(IS_LL_ADC_MULTI_MODE(ADC_CommonInitStruct->Multimode)); - if (ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT) + assert_param(IS_LL_ADC_MULTI_MODE(pADC_CommonInitStruct->Multimode)); + if (pADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT) { - assert_param(IS_LL_ADC_MULTI_DMA_TRANSFER(ADC_CommonInitStruct->MultiDMATransfer)); - assert_param(IS_LL_ADC_MULTI_TWOSMP_DELAY(ADC_CommonInitStruct->MultiTwoSamplingDelay)); + assert_param(IS_LL_ADC_MULTI_DMA_TRANSFER(pADC_CommonInitStruct->MultiDMATransfer)); + assert_param(IS_LL_ADC_MULTI_TWOSMP_DELAY(pADC_CommonInitStruct->MultiTwoSamplingDelay)); } #endif /* ADC_MULTIMODE_SUPPORT */ @@ -386,7 +386,7 @@ ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonIni /* - Set ADC multimode DMA transfer */ /* - Set ADC multimode: delay between 2 sampling phases */ #if defined(ADC_MULTIMODE_SUPPORT) - if (ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT) + if (pADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT) { MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_CKMODE @@ -395,10 +395,10 @@ ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonIni | ADC_CCR_DAMDF | ADC_CCR_DELAY , - ADC_CommonInitStruct->CommonClock - | ADC_CommonInitStruct->Multimode - | ADC_CommonInitStruct->MultiDMATransfer - | ADC_CommonInitStruct->MultiTwoSamplingDelay + pADC_CommonInitStruct->CommonClock + | pADC_CommonInitStruct->Multimode + | pADC_CommonInitStruct->MultiDMATransfer + | pADC_CommonInitStruct->MultiTwoSamplingDelay ); } else @@ -410,12 +410,12 @@ ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonIni | ADC_CCR_DAMDF | ADC_CCR_DELAY , - ADC_CommonInitStruct->CommonClock + pADC_CommonInitStruct->CommonClock | LL_ADC_MULTI_INDEPENDENT ); } #else - LL_ADC_SetCommonClock(ADCxy_COMMON, ADC_CommonInitStruct->CommonClock); + LL_ADC_SetCommonClock(ADCxy_COMMON, pADC_CommonInitStruct->CommonClock); #endif } else @@ -430,22 +430,22 @@ ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonIni /** * @brief Set each @ref LL_ADC_CommonInitTypeDef field to default value. - * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure + * @param pADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure * whose fields will be set to default values. * @retval None */ -void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct) +void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct) { /* Set ADC_CommonInitStruct fields to default values */ /* Set fields of ADC common */ /* (all ADC instances belonging to the same ADC common instance) */ - ADC_CommonInitStruct->CommonClock = LL_ADC_CLOCK_SYNC_PCLK_DIV2; + pADC_CommonInitStruct->CommonClock = LL_ADC_CLOCK_SYNC_PCLK_DIV2; #if defined(ADC_MULTIMODE_SUPPORT) /* Set fields of ADC multimode */ - ADC_CommonInitStruct->Multimode = LL_ADC_MULTI_INDEPENDENT; - ADC_CommonInitStruct->MultiDMATransfer = LL_ADC_MULTI_REG_DMA_EACH_ADC; - ADC_CommonInitStruct->MultiTwoSamplingDelay = LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE_5; + pADC_CommonInitStruct->Multimode = LL_ADC_MULTI_INDEPENDENT; + pADC_CommonInitStruct->MultiDMATransfer = LL_ADC_MULTI_REG_DMA_EACH_ADC; + pADC_CommonInitStruct->MultiTwoSamplingDelay = LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE_5; #endif /* ADC_MULTIMODE_SUPPORT */ } @@ -744,21 +744,21 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx) * - Set ADC channel sampling time * Refer to function LL_ADC_SetChannelSamplingTime(); * @param ADCx ADC instance - * @param ADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure + * @param pADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure * @retval An ErrorStatus enumeration value: * - SUCCESS: ADC registers are initialized * - ERROR: ADC registers are not initialized */ -ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct) +ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *pADC_InitStruct) { ErrorStatus status = SUCCESS; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(ADCx)); - assert_param(IS_LL_ADC_RESOLUTION(ADC_InitStruct->Resolution)); - assert_param(IS_LL_ADC_LEFT_BIT_SHIFT(ADC_InitStruct->LeftBitShift)); - assert_param(IS_LL_ADC_LOW_POWER(ADC_InitStruct->LowPowerMode)); + assert_param(IS_LL_ADC_RESOLUTION(pADC_InitStruct->Resolution)); + assert_param(IS_LL_ADC_LEFT_BIT_SHIFT(pADC_InitStruct->LeftBitShift)); + assert_param(IS_LL_ADC_LOW_POWER(pADC_InitStruct->LowPowerMode)); /* Note: Hardware constraint (refer to description of this function): */ /* ADC instance must be disabled. */ @@ -773,11 +773,11 @@ ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct) ADC_CFGR_RES | ADC_CFGR_AUTDLY , - ADC_InitStruct->Resolution - | ADC_InitStruct->LowPowerMode + pADC_InitStruct->Resolution + | pADC_InitStruct->LowPowerMode ); - MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_LSHIFT, ADC_InitStruct->LeftBitShift); + MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_LSHIFT, pADC_InitStruct->LeftBitShift); } else { @@ -790,17 +790,17 @@ ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct) /** * @brief Set each @ref LL_ADC_InitTypeDef field to default value. - * @param ADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure + * @param pADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure * whose fields will be set to default values. * @retval None */ -void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct) +void LL_ADC_StructInit(LL_ADC_InitTypeDef *pADC_InitStruct) { /* Set ADC_InitStruct fields to default values */ /* Set fields of ADC instance */ - ADC_InitStruct->Resolution = LL_ADC_RESOLUTION_16B; - ADC_InitStruct->LeftBitShift = LL_ADC_LEFT_BIT_SHIFT_NONE; - ADC_InitStruct->LowPowerMode = LL_ADC_LP_MODE_NONE; + pADC_InitStruct->Resolution = LL_ADC_RESOLUTION_16B; + pADC_InitStruct->LeftBitShift = LL_ADC_LEFT_BIT_SHIFT_NONE; + pADC_InitStruct->LowPowerMode = LL_ADC_LP_MODE_NONE; } @@ -831,31 +831,31 @@ void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct) * - Set ADC channel sampling time * Refer to function LL_ADC_SetChannelSamplingTime(); * @param ADCx ADC instance - * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure + * @param pADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure * @retval An ErrorStatus enumeration value: * - SUCCESS: ADC registers are initialized * - ERROR: ADC registers are not initialized */ -ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct) +ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *pADC_REG_InitStruct) { ErrorStatus status = SUCCESS; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(ADCx)); - assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADC_REG_InitStruct->TriggerSource)); - assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(ADC_REG_InitStruct->SequencerLength)); - if (ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) + assert_param(IS_LL_ADC_REG_TRIG_SOURCE(pADC_REG_InitStruct->TriggerSource)); + assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(pADC_REG_InitStruct->SequencerLength)); + if (pADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) { - assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont)); + assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(pADC_REG_InitStruct->SequencerDiscont)); /* ADC group regular continuous mode and discontinuous mode */ /* can not be enabled simultenaeously */ - assert_param((ADC_REG_InitStruct->ContinuousMode == LL_ADC_REG_CONV_SINGLE) - || (ADC_REG_InitStruct->SequencerDiscont == LL_ADC_REG_SEQ_DISCONT_DISABLE)); + assert_param((pADC_REG_InitStruct->ContinuousMode == LL_ADC_REG_CONV_SINGLE) + || (pADC_REG_InitStruct->SequencerDiscont == LL_ADC_REG_SEQ_DISCONT_DISABLE)); } - assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode)); - assert_param(IS_LL_ADC_REG_DATA_TRANSFER_MODE(ADC_REG_InitStruct->DataTransferMode)); - assert_param(IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(ADC_REG_InitStruct->Overrun)); + assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(pADC_REG_InitStruct->ContinuousMode)); + assert_param(IS_LL_ADC_REG_DATA_TRANSFER_MODE(pADC_REG_InitStruct->DataTransferMode)); + assert_param(IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(pADC_REG_InitStruct->Overrun)); /* Note: Hardware constraint (refer to description of this function): */ /* ADC instance must be disabled. */ @@ -872,7 +872,7 @@ ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_I /* - Set ADC group regular overrun behavior */ /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by */ /* setting of trigger source to SW start. */ - if (ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) + if (pADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) { MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTSEL @@ -883,11 +883,11 @@ ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_I | ADC_CFGR_DMNGT | ADC_CFGR_OVRMOD , - ADC_REG_InitStruct->TriggerSource - | ADC_REG_InitStruct->SequencerDiscont - | ADC_REG_InitStruct->ContinuousMode - | ADC_REG_InitStruct->DataTransferMode - | ADC_REG_InitStruct->Overrun + pADC_REG_InitStruct->TriggerSource + | pADC_REG_InitStruct->SequencerDiscont + | pADC_REG_InitStruct->ContinuousMode + | pADC_REG_InitStruct->DataTransferMode + | pADC_REG_InitStruct->Overrun ); } else @@ -901,16 +901,16 @@ ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_I | ADC_CFGR_DMNGT | ADC_CFGR_OVRMOD , - ADC_REG_InitStruct->TriggerSource + pADC_REG_InitStruct->TriggerSource | LL_ADC_REG_SEQ_DISCONT_DISABLE - | ADC_REG_InitStruct->ContinuousMode - | ADC_REG_InitStruct->DataTransferMode - | ADC_REG_InitStruct->Overrun + | pADC_REG_InitStruct->ContinuousMode + | pADC_REG_InitStruct->DataTransferMode + | pADC_REG_InitStruct->Overrun ); } /* Set ADC group regular sequencer length and scan direction */ - LL_ADC_REG_SetSequencerLength(ADCx, ADC_REG_InitStruct->SequencerLength); + LL_ADC_REG_SetSequencerLength(ADCx, pADC_REG_InitStruct->SequencerLength); } else { @@ -922,22 +922,22 @@ ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_I /** * @brief Set each @ref LL_ADC_REG_InitTypeDef field to default value. - * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure + * @param pADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure * whose fields will be set to default values. * @retval None */ -void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct) +void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *pADC_REG_InitStruct) { /* Set ADC_REG_InitStruct fields to default values */ /* Set fields of ADC group regular */ /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by */ /* setting of trigger source to SW start. */ - ADC_REG_InitStruct->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE; - ADC_REG_InitStruct->SequencerLength = LL_ADC_REG_SEQ_SCAN_DISABLE; - ADC_REG_InitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE; - ADC_REG_InitStruct->ContinuousMode = LL_ADC_REG_CONV_SINGLE; - ADC_REG_InitStruct->DataTransferMode = LL_ADC_REG_DR_TRANSFER; - ADC_REG_InitStruct->Overrun = LL_ADC_REG_OVR_DATA_OVERWRITTEN; + pADC_REG_InitStruct->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE; + pADC_REG_InitStruct->SequencerLength = LL_ADC_REG_SEQ_SCAN_DISABLE; + pADC_REG_InitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE; + pADC_REG_InitStruct->ContinuousMode = LL_ADC_REG_CONV_SINGLE; + pADC_REG_InitStruct->DataTransferMode = LL_ADC_REG_DR_TRANSFER; + pADC_REG_InitStruct->Overrun = LL_ADC_REG_OVR_DATA_OVERWRITTEN; } /** @@ -973,24 +973,24 @@ void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct) * To set several features of ADC group injected, use * function @ref LL_ADC_INJ_ConfigQueueContext(). * @param ADCx ADC instance - * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure + * @param pADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure * @retval An ErrorStatus enumeration value: * - SUCCESS: ADC registers are initialized * - ERROR: ADC registers are not initialized */ -ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct) +ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *pADC_INJ_InitStruct) { ErrorStatus status = SUCCESS; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(ADCx)); - assert_param(IS_LL_ADC_INJ_TRIG_SOURCE(ADC_INJ_InitStruct->TriggerSource)); - assert_param(IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(ADC_INJ_InitStruct->SequencerLength)); - if (ADC_INJ_InitStruct->SequencerLength != LL_ADC_INJ_SEQ_SCAN_DISABLE) + assert_param(IS_LL_ADC_INJ_TRIG_SOURCE(pADC_INJ_InitStruct->TriggerSource)); + assert_param(IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(pADC_INJ_InitStruct->SequencerLength)); + if (pADC_INJ_InitStruct->SequencerLength != LL_ADC_INJ_SEQ_SCAN_DISABLE) { - assert_param(IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(ADC_INJ_InitStruct->SequencerDiscont)); + assert_param(IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(pADC_INJ_InitStruct->SequencerDiscont)); } - assert_param(IS_LL_ADC_INJ_TRIG_AUTO(ADC_INJ_InitStruct->TrigAuto)); + assert_param(IS_LL_ADC_INJ_TRIG_AUTO(pADC_INJ_InitStruct->TrigAuto)); /* Note: Hardware constraint (refer to description of this function): */ /* ADC instance must be disabled. */ @@ -1005,14 +1005,14 @@ ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_I /* from ADC group regular */ /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by */ /* setting of trigger source to SW start. */ - if (ADC_INJ_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) + if (pADC_INJ_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) { MODIFY_REG(ADCx->CFGR, ADC_CFGR_JDISCEN | ADC_CFGR_JAUTO , - ADC_INJ_InitStruct->SequencerDiscont - | ADC_INJ_InitStruct->TrigAuto + pADC_INJ_InitStruct->SequencerDiscont + | pADC_INJ_InitStruct->TrigAuto ); } else @@ -1022,7 +1022,7 @@ ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_I | ADC_CFGR_JAUTO , LL_ADC_REG_SEQ_DISCONT_DISABLE - | ADC_INJ_InitStruct->TrigAuto + | pADC_INJ_InitStruct->TrigAuto ); } @@ -1031,8 +1031,8 @@ ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_I | ADC_JSQR_JEXTEN | ADC_JSQR_JL , - ADC_INJ_InitStruct->TriggerSource - | ADC_INJ_InitStruct->SequencerLength + pADC_INJ_InitStruct->TriggerSource + | pADC_INJ_InitStruct->SequencerLength ); } else @@ -1045,18 +1045,18 @@ ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_I /** * @brief Set each @ref LL_ADC_INJ_InitTypeDef field to default value. - * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure + * @param pADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure * whose fields will be set to default values. * @retval None */ -void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct) +void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *pADC_INJ_InitStruct) { /* Set ADC_INJ_InitStruct fields to default values */ /* Set fields of ADC group injected */ - ADC_INJ_InitStruct->TriggerSource = LL_ADC_INJ_TRIG_SOFTWARE; - ADC_INJ_InitStruct->SequencerLength = LL_ADC_INJ_SEQ_SCAN_DISABLE; - ADC_INJ_InitStruct->SequencerDiscont = LL_ADC_INJ_SEQ_DISCONT_DISABLE; - ADC_INJ_InitStruct->TrigAuto = LL_ADC_INJ_TRIG_INDEPENDENT; + pADC_INJ_InitStruct->TriggerSource = LL_ADC_INJ_TRIG_SOFTWARE; + pADC_INJ_InitStruct->SequencerLength = LL_ADC_INJ_SEQ_SCAN_DISABLE; + pADC_INJ_InitStruct->SequencerDiscont = LL_ADC_INJ_SEQ_DISCONT_DISABLE; + pADC_INJ_InitStruct->TrigAuto = LL_ADC_INJ_TRIG_INDEPENDENT; } /** diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_ll_dma.c b/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_ll_dma.c index aa35cd945a..e41b064a4d 100644 --- a/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_ll_dma.c +++ b/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_ll_dma.c @@ -69,6 +69,7 @@ #define IS_LL_DMA_REQUEST(REQUEST) (((REQUEST) <= LL_DMAMUX1_REQ_I2C5_TX)) + #define IS_LL_DMA_PRIORITY(__VALUE__) (((__VALUE__) == LL_DMA_PRIORITY_LOW) || \ ((__VALUE__) == LL_DMA_PRIORITY_MEDIUM) || \ ((__VALUE__) == LL_DMA_PRIORITY_HIGH) || \ @@ -94,7 +95,6 @@ ((STREAM) == LL_DMA_STREAM_6) || \ ((STREAM) == LL_DMA_STREAM_7) || \ ((STREAM) == LL_DMA_STREAM_ALL)))) - #define IS_LL_DMA_FIFO_MODE_STATE(STATE) (((STATE) == LL_DMA_FIFOMODE_DISABLE ) || \ ((STATE) == LL_DMA_FIFOMODE_ENABLE)) @@ -287,7 +287,10 @@ uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Stream, LL_DMA_InitTypeDef *DMA assert_param(IS_LL_DMA_PERIPHDATASIZE(DMA_InitStruct->PeriphOrM2MSrcDataSize)); assert_param(IS_LL_DMA_MEMORYDATASIZE(DMA_InitStruct->MemoryOrM2MDstDataSize)); assert_param(IS_LL_DMA_NBDATA(DMA_InitStruct->NbData)); - assert_param(IS_LL_DMA_REQUEST(DMA_InitStruct->PeriphRequest)); + if ((DMAx == DMA1) || (DMAx == DMA2)) + { + assert_param(IS_LL_DMA_REQUEST(DMA_InitStruct->PeriphRequest)); + } assert_param(IS_LL_DMA_PRIORITY(DMA_InitStruct->Priority)); assert_param(IS_LL_DMA_FIFO_MODE_STATE(DMA_InitStruct->FIFOMode)); /* Check the memory burst, peripheral burst and FIFO threshold parameters only @@ -299,72 +302,75 @@ uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Stream, LL_DMA_InitTypeDef *DMA assert_param(IS_LL_DMA_PERIPHERAL_BURST(DMA_InitStruct->PeriphBurst)); } - /*---------------------------- DMAx SxCR Configuration ------------------------ - * Configure DMAx_Streamy: data transfer direction, data transfer mode, - * peripheral and memory increment mode, - * data size alignment and priority level with parameters : - * - Direction: DMA_SxCR_DIR[1:0] bits - * - Mode: DMA_SxCR_CIRC bit - * - PeriphOrM2MSrcIncMode: DMA_SxCR_PINC bit - * - MemoryOrM2MDstIncMode: DMA_SxCR_MINC bit - * - PeriphOrM2MSrcDataSize: DMA_SxCR_PSIZE[1:0] bits - * - MemoryOrM2MDstDataSize: DMA_SxCR_MSIZE[1:0] bits - * - Priority: DMA_SxCR_PL[1:0] bits - */ - LL_DMA_ConfigTransfer(DMAx, Stream, DMA_InitStruct->Direction | \ - DMA_InitStruct->Mode | \ - DMA_InitStruct->PeriphOrM2MSrcIncMode | \ - DMA_InitStruct->MemoryOrM2MDstIncMode | \ - DMA_InitStruct->PeriphOrM2MSrcDataSize | \ - DMA_InitStruct->MemoryOrM2MDstDataSize | \ - DMA_InitStruct->Priority - ); - - if (DMA_InitStruct->FIFOMode != LL_DMA_FIFOMODE_DISABLE) + if (IS_LL_DMA_ALL_STREAM_INSTANCE(DMAx, Stream)) { - /*---------------------------- DMAx SxFCR Configuration ------------------------ - * Configure DMAx_Streamy: fifo mode and fifo threshold with parameters : - * - FIFOMode: DMA_SxFCR_DMDIS bit - * - FIFOThreshold: DMA_SxFCR_FTH[1:0] bits + /*---------------------------- DMAx SxCR Configuration ------------------------ + * Configure DMAx_Streamy: data transfer direction, data transfer mode, + * peripheral and memory increment mode, + * data size alignment and priority level with parameters : + * - Direction: DMA_SxCR_DIR[1:0] bits + * - Mode: DMA_SxCR_CIRC bit + * - PeriphOrM2MSrcIncMode: DMA_SxCR_PINC bit + * - MemoryOrM2MDstIncMode: DMA_SxCR_MINC bit + * - PeriphOrM2MSrcDataSize: DMA_SxCR_PSIZE[1:0] bits + * - MemoryOrM2MDstDataSize: DMA_SxCR_MSIZE[1:0] bits + * - Priority: DMA_SxCR_PL[1:0] bits */ - LL_DMA_ConfigFifo(DMAx, Stream, DMA_InitStruct->FIFOMode, DMA_InitStruct->FIFOThreshold); + LL_DMA_ConfigTransfer(DMAx, Stream, DMA_InitStruct->Direction | \ + DMA_InitStruct->Mode | \ + DMA_InitStruct->PeriphOrM2MSrcIncMode | \ + DMA_InitStruct->MemoryOrM2MDstIncMode | \ + DMA_InitStruct->PeriphOrM2MSrcDataSize | \ + DMA_InitStruct->MemoryOrM2MDstDataSize | \ + DMA_InitStruct->Priority + ); + + if (DMA_InitStruct->FIFOMode != LL_DMA_FIFOMODE_DISABLE) + { + /*---------------------------- DMAx SxFCR Configuration ------------------------ + * Configure DMAx_Streamy: fifo mode and fifo threshold with parameters : + * - FIFOMode: DMA_SxFCR_DMDIS bit + * - FIFOThreshold: DMA_SxFCR_FTH[1:0] bits + */ + LL_DMA_ConfigFifo(DMAx, Stream, DMA_InitStruct->FIFOMode, DMA_InitStruct->FIFOThreshold); + + /*---------------------------- DMAx SxCR Configuration -------------------------- + * Configure DMAx_Streamy: memory burst transfer with parameters : + * - MemBurst: DMA_SxCR_MBURST[1:0] bits + */ + LL_DMA_SetMemoryBurstxfer(DMAx, Stream, DMA_InitStruct->MemBurst); + + /*---------------------------- DMAx SxCR Configuration -------------------------- + * Configure DMAx_Streamy: peripheral burst transfer with parameters : + * - PeriphBurst: DMA_SxCR_PBURST[1:0] bits + */ + LL_DMA_SetPeriphBurstxfer(DMAx, Stream, DMA_InitStruct->PeriphBurst); + } - /*---------------------------- DMAx SxCR Configuration -------------------------- - * Configure DMAx_Streamy: memory burst transfer with parameters : - * - MemBurst: DMA_SxCR_MBURST[1:0] bits + /*-------------------------- DMAx SxM0AR Configuration -------------------------- + * Configure the memory or destination base address with parameter : + * - MemoryOrM2MDstAddress: DMA_SxM0AR_M0A[31:0] bits */ - LL_DMA_SetMemoryBurstxfer(DMAx, Stream, DMA_InitStruct->MemBurst); + LL_DMA_SetMemoryAddress(DMAx, Stream, DMA_InitStruct->MemoryOrM2MDstAddress); - /*---------------------------- DMAx SxCR Configuration -------------------------- - * Configure DMAx_Streamy: peripheral burst transfer with parameters : - * - PeriphBurst: DMA_SxCR_PBURST[1:0] bits + /*-------------------------- DMAx SxPAR Configuration --------------------------- + * Configure the peripheral or source base address with parameter : + * - PeriphOrM2MSrcAddress: DMA_SxPAR_PA[31:0] bits */ - LL_DMA_SetPeriphBurstxfer(DMAx, Stream, DMA_InitStruct->PeriphBurst); - } + LL_DMA_SetPeriphAddress(DMAx, Stream, DMA_InitStruct->PeriphOrM2MSrcAddress); + + /*--------------------------- DMAx SxNDTR Configuration ------------------------- + * Configure the peripheral base address with parameter : + * - NbData: DMA_SxNDT[15:0] bits + */ + LL_DMA_SetDataLength(DMAx, Stream, DMA_InitStruct->NbData); - /*-------------------------- DMAx SxM0AR Configuration -------------------------- - * Configure the memory or destination base address with parameter : - * - MemoryOrM2MDstAddress: DMA_SxM0AR_M0A[31:0] bits - */ - LL_DMA_SetMemoryAddress(DMAx, Stream, DMA_InitStruct->MemoryOrM2MDstAddress); - - /*-------------------------- DMAx SxPAR Configuration --------------------------- - * Configure the peripheral or source base address with parameter : - * - PeriphOrM2MSrcAddress: DMA_SxPAR_PA[31:0] bits - */ - LL_DMA_SetPeriphAddress(DMAx, Stream, DMA_InitStruct->PeriphOrM2MSrcAddress); - - /*--------------------------- DMAx SxNDTR Configuration ------------------------- - * Configure the peripheral base address with parameter : - * - NbData: DMA_SxNDT[15:0] bits - */ - LL_DMA_SetDataLength(DMAx, Stream, DMA_InitStruct->NbData); - - /*--------------------------- DMA SxCR_CHSEL Configuration ---------------------- - * Configure the peripheral base address with parameter : - * - PeriphRequest: DMA_SxCR_CHSEL[3:0] bits - */ - LL_DMA_SetPeriphRequest(DMAx, Stream, DMA_InitStruct->PeriphRequest); + /*--------------------------- DMA SxCR_CHSEL Configuration ---------------------- + * Configure the peripheral base address with parameter : + * - PeriphRequest: DMA_SxCR_CHSEL[3:0] bits + */ + LL_DMA_SetPeriphRequest(DMAx, Stream, DMA_InitStruct->PeriphRequest); + } return (uint32_t)SUCCESS; } diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_ll_exti.c b/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_ll_exti.c index 4c6af600b4..f6b3db65aa 100644 --- a/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_ll_exti.c +++ b/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_ll_exti.c @@ -108,7 +108,7 @@ ErrorStatus LL_EXTI_DeInit(void) LL_EXTI_WriteReg(FPR3, EXTI_PR3_Msk); /* Interrupt mask register set to default reset values */ - LL_EXTI_WriteReg(C2IMR1, 0xFFFE0000); + LL_EXTI_WriteReg(C2IMR1, 0xFFFE0000U); /* Event mask register set to default reset values */ LL_EXTI_WriteReg(C2EMR1, 0x00000000U); diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_ll_spi.c b/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_ll_spi.c index 6b62ce354e..415b1097d8 100644 --- a/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_ll_spi.c +++ b/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_ll_spi.c @@ -342,6 +342,7 @@ ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct) ErrorStatus status = ERROR; uint32_t tmp_nss; uint32_t tmp_mode; + uint32_t tmp_nss_polarity; /* Check the SPI Instance SPIx*/ assert_param(IS_SPI_ALL_INSTANCE(SPIx)); @@ -371,11 +372,12 @@ ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct) tmp_nss = SPI_InitStruct->NSS; tmp_mode = SPI_InitStruct->Mode; + tmp_nss_polarity = LL_SPI_GetNSSPolarity(SPIx); /* Checks to setup Internal SS signal level and avoid a MODF Error */ - if ((tmp_nss == LL_SPI_NSS_SOFT) && (((LL_SPI_GetNSSPolarity(SPIx) == LL_SPI_NSS_POLARITY_LOW) && \ - (tmp_mode == LL_SPI_MODE_MASTER)) || \ - ((LL_SPI_GetNSSPolarity(SPIx) == LL_SPI_NSS_POLARITY_HIGH) && \ + if ((tmp_nss == LL_SPI_NSS_SOFT) && (((tmp_nss_polarity == LL_SPI_NSS_POLARITY_LOW) && \ + (tmp_mode == LL_SPI_MODE_MASTER)) || \ + ((tmp_nss_polarity == LL_SPI_NSS_POLARITY_HIGH) && \ (tmp_mode == LL_SPI_MODE_SLAVE)))) { LL_SPI_SetInternalSSLevel(SPIx, LL_SPI_SS_LEVEL_HIGH); @@ -677,7 +679,7 @@ ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct) i2sdiv = tmp / 2UL; } - /* Test if the obtain values are forbiden or out of range */ + /* Test if the obtain values are forbidden or out of range */ if (((i2sodd == 1UL) && (i2sdiv == 1UL)) || (i2sdiv > 0xFFUL)) { /* Set the default values */ diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_ll_usart.c b/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_ll_usart.c index b9dbf2550a..6edc2cefad 100644 --- a/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_ll_usart.c +++ b/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_ll_usart.c @@ -65,9 +65,6 @@ /* __VALUE__ In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. */ #define IS_LL_USART_BRR_MIN(__VALUE__) ((__VALUE__) >= 16U) -/* __VALUE__ BRR content must be lower than or equal to 0xFFFF. */ -#define IS_LL_USART_BRR_MAX(__VALUE__) ((__VALUE__) <= 0x0000FFFFU) - #define IS_LL_USART_DIRECTION(__VALUE__) (((__VALUE__) == LL_USART_DIRECTION_NONE) \ || ((__VALUE__) == LL_USART_DIRECTION_RX) \ || ((__VALUE__) == LL_USART_DIRECTION_TX) \ @@ -325,9 +322,6 @@ ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_Ini /* Check BRR is greater than or equal to 16d */ assert_param(IS_LL_USART_BRR_MIN(USARTx->BRR)); - - /* Check BRR is lower than or equal to 0xFFFF */ - assert_param(IS_LL_USART_BRR_MAX(USARTx->BRR)); } /*---------------------------- USART PRESC Configuration ----------------------- diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_ll_utils.c b/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_ll_utils.c index e05f40f732..ecc38a48cc 100644 --- a/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_ll_utils.c +++ b/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_ll_utils.c @@ -647,4 +647,3 @@ static void UTILS_EnablePLLAndSwitchSystem( * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32YYxx_HAL_Driver_version.md b/system/Drivers/STM32YYxx_HAL_Driver_version.md index a551c9d884..9ab5eefd9f 100644 --- a/system/Drivers/STM32YYxx_HAL_Driver_version.md +++ b/system/Drivers/STM32YYxx_HAL_Driver_version.md @@ -13,7 +13,7 @@ * STM32L1: 1.4.4 * STM32L4: 1.13.3 * STM32L5: 1.0.5 - * STM32MP1: 1.5.0 + * STM32MP1: 1.6.0 * STM32U5: 1.1.0 * STM32WB: 1.12.0 * STM32WL: 1.3.0 diff --git a/system/Middlewares/OpenAMP/libmetal/CMakeLists.txt b/system/Middlewares/OpenAMP/libmetal/CMakeLists.txt index 8095465988..7ea8f7bc99 100644 --- a/system/Middlewares/OpenAMP/libmetal/CMakeLists.txt +++ b/system/Middlewares/OpenAMP/libmetal/CMakeLists.txt @@ -7,6 +7,8 @@ if (POLICY CMP0077) cmake_policy(SET CMP0077 NEW) endif() +set (LIBMETAL_ROOT_DIR "${CMAKE_CURRENT_SOURCE_DIR}") + list (APPEND CMAKE_MODULE_PATH "${CMAKE_CURRENT_SOURCE_DIR}/cmake" "${CMAKE_CURRENT_SOURCE_DIR}/cmake/modules" diff --git a/system/Middlewares/OpenAMP/libmetal/MAINTAINERS.md b/system/Middlewares/OpenAMP/libmetal/MAINTAINERS.md index 5f388dea0e..077c58b8aa 100644 --- a/system/Middlewares/OpenAMP/libmetal/MAINTAINERS.md +++ b/system/Middlewares/OpenAMP/libmetal/MAINTAINERS.md @@ -1,6 +1,6 @@ # libmetal Maintainers -libmetal project is maintained by the OpenAMP open source community. +The libmetal project is maintained by the OpenAMP open source community. Everyone is encouraged to submit issues and changes to improve libmetal. The intention of this file is to provide a set of names that developers can @@ -8,15 +8,8 @@ consult when they have a question about OpenAMP and to provide a a set of names to be CC'd when submitting a patch. ## Project Administration -Ed Mooring +Ed Mooring Arnaud Pouliquen ### All patches CC here openamp-rp@lists.openampproject.org - -## Machines -### Xilinx Platform - Zynq-7000 -Ed Mooring - -### Xilinx Platform - Zynq UltraScale+ MPSoC -Ed Mooring diff --git a/system/Middlewares/OpenAMP/libmetal/VERSION b/system/Middlewares/OpenAMP/libmetal/VERSION index 28f0f0226d..61df8f44d6 100644 --- a/system/Middlewares/OpenAMP/libmetal/VERSION +++ b/system/Middlewares/OpenAMP/libmetal/VERSION @@ -1,3 +1,3 @@ VERSION_MAJOR = 1 -VERSION_MINOR = 0 +VERSION_MINOR = 1 VERSION_PATCH = 0 diff --git a/system/Middlewares/OpenAMP/libmetal/cmake/options.cmake b/system/Middlewares/OpenAMP/libmetal/cmake/options.cmake index 4b866164c3..cbf1c2b0e0 100644 --- a/system/Middlewares/OpenAMP/libmetal/cmake/options.cmake +++ b/system/Middlewares/OpenAMP/libmetal/cmake/options.cmake @@ -1,4 +1,4 @@ -file(READ ${CMAKE_SOURCE_DIR}/VERSION ver) +file(READ ${LIBMETAL_ROOT_DIR}/VERSION ver) string(REGEX MATCH "VERSION_MAJOR = ([0-9]*)" _ ${ver}) set(PROJECT_VERSION_MAJOR ${CMAKE_MATCH_1}) diff --git a/system/Middlewares/OpenAMP/libmetal/cmake/syscheck.cmake b/system/Middlewares/OpenAMP/libmetal/cmake/syscheck.cmake index 1ff4a12ff2..70225adb68 100644 --- a/system/Middlewares/OpenAMP/libmetal/cmake/syscheck.cmake +++ b/system/Middlewares/OpenAMP/libmetal/cmake/syscheck.cmake @@ -7,7 +7,8 @@ if (WITH_ZEPHYR) if (NOT WITH_ZEPHYR_LIB) include($ENV{ZEPHYR_BASE}/cmake/app/boilerplate.cmake NO_POLICY_SCOPE) endif() - if (CONFIG_CPU_CORTEX_M) - set (MACHINE "cortexm" CACHE STRING "") - endif (CONFIG_CPU_CORTEX_M) + if (CONFIG_ARM) + set (MACHINE "arm" CACHE STRING "") + endif(CONFIG_ARM) + endif (WITH_ZEPHYR) diff --git a/system/Middlewares/OpenAMP/libmetal/lib/alloc.h b/system/Middlewares/OpenAMP/libmetal/lib/alloc.h index f5b9a5d325..fb4728c174 100644 --- a/system/Middlewares/OpenAMP/libmetal/lib/alloc.h +++ b/system/Middlewares/OpenAMP/libmetal/lib/alloc.h @@ -36,12 +36,13 @@ static inline void *metal_allocate_memory(unsigned int size); */ static inline void metal_free_memory(void *ptr); -#include - /** @} */ #ifdef __cplusplus } #endif +#include + + #endif /* __METAL_ALLOC__H__ */ diff --git a/system/Middlewares/OpenAMP/libmetal/lib/condition.h b/system/Middlewares/OpenAMP/libmetal/lib/condition.h index 97c3776ed2..536b2becd2 100644 --- a/system/Middlewares/OpenAMP/libmetal/lib/condition.h +++ b/system/Middlewares/OpenAMP/libmetal/lib/condition.h @@ -63,12 +63,12 @@ static inline int metal_condition_broadcast(struct metal_condition *cv); */ int metal_condition_wait(struct metal_condition *cv, metal_mutex_t *m); -#include - /** @} */ #ifdef __cplusplus } #endif +#include + #endif /* __METAL_CONDITION__H__ */ diff --git a/system/Middlewares/OpenAMP/libmetal/lib/dma.h b/system/Middlewares/OpenAMP/libmetal/lib/dma.h index 32554bded8..9bb7e54c83 100644 --- a/system/Middlewares/OpenAMP/libmetal/lib/dma.h +++ b/system/Middlewares/OpenAMP/libmetal/lib/dma.h @@ -12,6 +12,9 @@ #ifndef __METAL_DMA__H__ #define __METAL_DMA__H__ +#include +#include + #ifdef __cplusplus extern "C" { #endif @@ -20,9 +23,6 @@ extern "C" { * @{ */ -#include -#include - #define METAL_DMA_DEV_R 1 /**< DMA direction, device read */ #define METAL_DMA_DEV_W 2 /**< DMA direction, device write */ #define METAL_DMA_DEV_WR 3 /**< DMA direction, device read/write */ diff --git a/system/Middlewares/OpenAMP/libmetal/lib/include/metal/alloc.h b/system/Middlewares/OpenAMP/libmetal/lib/include/metal/alloc.h index fb7771fabc..b9b2c72990 100644 --- a/system/Middlewares/OpenAMP/libmetal/lib/include/metal/alloc.h +++ b/system/Middlewares/OpenAMP/libmetal/lib/include/metal/alloc.h @@ -36,16 +36,16 @@ static inline void *metal_allocate_memory(unsigned int size); */ static inline void metal_free_memory(void *ptr); -#ifdef METAL_FREERTOS -#include -#else -#include -#endif - /** @} */ #ifdef __cplusplus } #endif +#ifdef METAL_FREERTOS +#include +#else +#include +#endif + #endif /* __METAL_ALLOC__H__ */ diff --git a/system/Middlewares/OpenAMP/libmetal/lib/include/metal/condition.h b/system/Middlewares/OpenAMP/libmetal/lib/include/metal/condition.h index dc41e42c09..9d63de08e7 100644 --- a/system/Middlewares/OpenAMP/libmetal/lib/include/metal/condition.h +++ b/system/Middlewares/OpenAMP/libmetal/lib/include/metal/condition.h @@ -63,16 +63,16 @@ static inline int metal_condition_broadcast(struct metal_condition *cv); */ int metal_condition_wait(struct metal_condition *cv, metal_mutex_t *m); -#ifdef METAL_FREERTOS -#include -#else -#include -#endif - /** @} */ #ifdef __cplusplus } #endif +#ifdef METAL_FREERTOS +#include +#else +#include +#endif + #endif /* __METAL_CONDITION__H__ */ diff --git a/system/Middlewares/OpenAMP/libmetal/lib/include/metal/config.h b/system/Middlewares/OpenAMP/libmetal/lib/include/metal/config.h index 5059d96bbb..28f6d8d925 100644 --- a/system/Middlewares/OpenAMP/libmetal/lib/include/metal/config.h +++ b/system/Middlewares/OpenAMP/libmetal/lib/include/metal/config.h @@ -20,13 +20,13 @@ extern "C" { #define METAL_VER_MAJOR 1 /** Library minor version number. */ -#define METAL_VER_MINOR 0 +#define METAL_VER_MINOR 1 /** Library patch level. */ #define METAL_VER_PATCH 0 /** Library version string. */ -#define METAL_VER "1.0.0" +#define METAL_VER "1.1.0" /** System type (linux, generic, ...). */ #ifdef METAL_FREERTOS diff --git a/system/Middlewares/OpenAMP/libmetal/lib/include/metal/dma.h b/system/Middlewares/OpenAMP/libmetal/lib/include/metal/dma.h index 32554bded8..9bb7e54c83 100644 --- a/system/Middlewares/OpenAMP/libmetal/lib/include/metal/dma.h +++ b/system/Middlewares/OpenAMP/libmetal/lib/include/metal/dma.h @@ -12,6 +12,9 @@ #ifndef __METAL_DMA__H__ #define __METAL_DMA__H__ +#include +#include + #ifdef __cplusplus extern "C" { #endif @@ -20,9 +23,6 @@ extern "C" { * @{ */ -#include -#include - #define METAL_DMA_DEV_R 1 /**< DMA direction, device read */ #define METAL_DMA_DEV_W 2 /**< DMA direction, device write */ #define METAL_DMA_DEV_WR 3 /**< DMA direction, device read/write */ diff --git a/system/Middlewares/OpenAMP/libmetal/lib/include/metal/io.h b/system/Middlewares/OpenAMP/libmetal/lib/include/metal/io.h index 1c2e9f3430..268eed8f9b 100644 --- a/system/Middlewares/OpenAMP/libmetal/lib/include/metal/io.h +++ b/system/Middlewares/OpenAMP/libmetal/lib/include/metal/io.h @@ -132,7 +132,7 @@ static inline void * metal_io_virt(struct metal_io_region *io, unsigned long offset) { return (io->virt != METAL_BAD_VA && offset < io->size - ? (uint8_t *)io->virt + offset + ? (void *)((uintptr_t)io->virt + offset) : NULL); } @@ -145,7 +145,7 @@ metal_io_virt(struct metal_io_region *io, unsigned long offset) static inline unsigned long metal_io_virt_to_offset(struct metal_io_region *io, void *virt) { - size_t offset = (uint8_t *)virt - (uint8_t *)io->virt; + size_t offset = (uintptr_t)virt - (uintptr_t)io->virt; return (offset < io->size ? offset : METAL_BAD_OFFSET); } @@ -363,16 +363,16 @@ int metal_io_block_write(struct metal_io_region *io, unsigned long offset, int metal_io_block_set(struct metal_io_region *io, unsigned long offset, unsigned char value, int len); -#ifdef METAL_FREERTOS -#include -#else -#include -#endif - /** @} */ #ifdef __cplusplus } #endif +#ifdef METAL_FREERTOS +#include +#else +#include +#endif + #endif /* __METAL_IO__H__ */ diff --git a/system/Middlewares/OpenAMP/libmetal/lib/include/metal/irq.h b/system/Middlewares/OpenAMP/libmetal/lib/include/metal/irq.h index 46f0e4d4da..769e3689d8 100644 --- a/system/Middlewares/OpenAMP/libmetal/lib/include/metal/irq.h +++ b/system/Middlewares/OpenAMP/libmetal/lib/include/metal/irq.h @@ -12,6 +12,9 @@ #ifndef __METAL_IRQ__H__ #define __METAL_IRQ__H__ +#include +#include + #ifdef __cplusplus extern "C" { #endif @@ -20,9 +23,6 @@ extern "C" { * @{ */ -#include -#include - /** IRQ handled status */ #define METAL_IRQ_NOT_HANDLED 0 #define METAL_IRQ_HANDLED 1 diff --git a/system/Middlewares/OpenAMP/libmetal/lib/include/metal/softirq.h b/system/Middlewares/OpenAMP/libmetal/lib/include/metal/softirq.h index 4ad4d42d5b..52ea00f18c 100644 --- a/system/Middlewares/OpenAMP/libmetal/lib/include/metal/softirq.h +++ b/system/Middlewares/OpenAMP/libmetal/lib/include/metal/softirq.h @@ -12,6 +12,8 @@ #ifndef __METAL_SOFTIRQ__H__ #define __METAL_SOFTIRQ__H__ +#include + #ifdef __cplusplus extern "C" { #endif @@ -20,8 +22,6 @@ extern "C" { * @{ */ -#include - /** * @brief metal_softirq_init * diff --git a/system/Middlewares/OpenAMP/libmetal/lib/include/metal/system/freertos/mutex.h b/system/Middlewares/OpenAMP/libmetal/lib/include/metal/system/freertos/mutex.h index d9983e67b1..1f1449af08 100644 --- a/system/Middlewares/OpenAMP/libmetal/lib/include/metal/system/freertos/mutex.h +++ b/system/Middlewares/OpenAMP/libmetal/lib/include/metal/system/freertos/mutex.h @@ -33,7 +33,17 @@ typedef struct { * METAL_MUTEX_INIT - used for initializing an mutex element in a static struct * or global */ +#if defined(__GNUC__) +#define METAL_MUTEX_INIT(m) { NULL }; \ +_Pragma("GCC warning\"static initialisation of the mutex is deprecated\"") +#elif defined(__ICCARM__) +#define DO_PRAGMA(x) _Pragma(#x) +#define METAL_MUTEX_INIT(m) { NULL }; \ +DO_PRAGMA(message("Warning: static initialisation of the mutex is deprecated")) +#else #define METAL_MUTEX_INIT(m) { NULL } +#endif + /* * METAL_MUTEX_DEFINE - used for defining and initializing a global or * static singleton mutex diff --git a/system/Middlewares/OpenAMP/libmetal/lib/include/metal/time.h b/system/Middlewares/OpenAMP/libmetal/lib/include/metal/time.h index 9e1762e089..bc24e61348 100644 --- a/system/Middlewares/OpenAMP/libmetal/lib/include/metal/time.h +++ b/system/Middlewares/OpenAMP/libmetal/lib/include/metal/time.h @@ -12,6 +12,9 @@ #ifndef __METAL_TIME__H__ #define __METAL_TIME__H__ +#include +#include + #ifdef __cplusplus extern "C" { #endif @@ -20,9 +23,6 @@ extern "C" { * @{ */ -#include -#include - /** * @brief get timestamp * This function returns the timestampe as unsigned long long diff --git a/system/Middlewares/OpenAMP/libmetal/lib/io.c b/system/Middlewares/OpenAMP/libmetal/lib/io.c index 8376ded0db..7faf40502e 100644 --- a/system/Middlewares/OpenAMP/libmetal/lib/io.c +++ b/system/Middlewares/OpenAMP/libmetal/lib/io.c @@ -39,7 +39,7 @@ int metal_io_block_read(struct metal_io_region *io, unsigned long offset, unsigned char *dest = dst; int retlen; - if (offset >= io->size) + if (!ptr) return -ERANGE; if ((offset + len) > io->size) len = io->size - offset; @@ -76,7 +76,7 @@ int metal_io_block_write(struct metal_io_region *io, unsigned long offset, const unsigned char *source = src; int retlen; - if (offset >= io->size) + if (!ptr) return -ERANGE; if ((offset + len) > io->size) len = io->size - offset; @@ -112,7 +112,7 @@ int metal_io_block_set(struct metal_io_region *io, unsigned long offset, unsigned char *ptr = metal_io_virt(io, offset); int retlen = len; - if (offset >= io->size) + if (!ptr) return -ERANGE; if ((offset + len) > io->size) len = io->size - offset; diff --git a/system/Middlewares/OpenAMP/libmetal/lib/io.h b/system/Middlewares/OpenAMP/libmetal/lib/io.h index 565872bed9..ba416dd505 100644 --- a/system/Middlewares/OpenAMP/libmetal/lib/io.h +++ b/system/Middlewares/OpenAMP/libmetal/lib/io.h @@ -132,7 +132,7 @@ static inline void * metal_io_virt(struct metal_io_region *io, unsigned long offset) { return (io->virt != METAL_BAD_VA && offset < io->size - ? (uint8_t *)io->virt + offset + ? (void *)((uintptr_t)io->virt + offset) : NULL); } @@ -145,7 +145,7 @@ metal_io_virt(struct metal_io_region *io, unsigned long offset) static inline unsigned long metal_io_virt_to_offset(struct metal_io_region *io, void *virt) { - size_t offset = (uint8_t *)virt - (uint8_t *)io->virt; + size_t offset = (uintptr_t)virt - (uintptr_t)io->virt; return (offset < io->size ? offset : METAL_BAD_OFFSET); } @@ -363,12 +363,12 @@ int metal_io_block_write(struct metal_io_region *io, unsigned long offset, int metal_io_block_set(struct metal_io_region *io, unsigned long offset, unsigned char value, int len); -#include - /** @} */ #ifdef __cplusplus } #endif +#include + #endif /* __METAL_IO__H__ */ diff --git a/system/Middlewares/OpenAMP/libmetal/lib/irq.h b/system/Middlewares/OpenAMP/libmetal/lib/irq.h index 2b21ff35ca..a8b837757d 100644 --- a/system/Middlewares/OpenAMP/libmetal/lib/irq.h +++ b/system/Middlewares/OpenAMP/libmetal/lib/irq.h @@ -12,6 +12,9 @@ #ifndef __METAL_IRQ__H__ #define __METAL_IRQ__H__ +#include +#include + #ifdef __cplusplus extern "C" { #endif @@ -20,9 +23,6 @@ extern "C" { * @{ */ -#include -#include - /** IRQ handled status */ #define METAL_IRQ_NOT_HANDLED 0 #define METAL_IRQ_HANDLED 1 diff --git a/system/Middlewares/OpenAMP/libmetal/lib/mutex.h b/system/Middlewares/OpenAMP/libmetal/lib/mutex.h index f81c32192c..a45aa7976f 100644 --- a/system/Middlewares/OpenAMP/libmetal/lib/mutex.h +++ b/system/Middlewares/OpenAMP/libmetal/lib/mutex.h @@ -12,6 +12,8 @@ #ifndef __METAL_MUTEX__H__ #define __METAL_MUTEX__H__ +#include + #ifdef __cplusplus extern "C" { #endif @@ -20,8 +22,6 @@ extern "C" { * @{ */ -#include - /** * @brief Initialize a libmetal mutex. * @param[in] mutex Mutex to initialize. diff --git a/system/Middlewares/OpenAMP/libmetal/lib/processor/xtensa/CMakeLists.txt b/system/Middlewares/OpenAMP/libmetal/lib/processor/xtensa/CMakeLists.txt new file mode 100644 index 0000000000..13ce023007 --- /dev/null +++ b/system/Middlewares/OpenAMP/libmetal/lib/processor/xtensa/CMakeLists.txt @@ -0,0 +1,2 @@ +collect (PROJECT_LIB_HEADERS atomic.h) +collect (PROJECT_LIB_HEADERS cpu.h) diff --git a/system/Middlewares/OpenAMP/libmetal/lib/processor/xtensa/atomic.h b/system/Middlewares/OpenAMP/libmetal/lib/processor/xtensa/atomic.h new file mode 100644 index 0000000000..6f87ea9273 --- /dev/null +++ b/system/Middlewares/OpenAMP/libmetal/lib/processor/xtensa/atomic.h @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2021, Xiaomi Inc. and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* + * @file xtensa/atomic.h + * @brief Xtensa specific atomic primitives for libmetal. + */ + +#ifndef __METAL_XTENSA_ATOMIC__H__ +#define __METAL_XTENSA_ATOMIC__H__ + +#endif /* __METAL_XTENSA_ATOMIC__H__ */ diff --git a/system/Middlewares/OpenAMP/libmetal/lib/processor/xtensa/cpu.h b/system/Middlewares/OpenAMP/libmetal/lib/processor/xtensa/cpu.h new file mode 100644 index 0000000000..719f9c1d77 --- /dev/null +++ b/system/Middlewares/OpenAMP/libmetal/lib/processor/xtensa/cpu.h @@ -0,0 +1,18 @@ +/* + * Copyright (c) 2021, Xiaomi Inc. and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* + * @file cpu.h + * @brief CPU specific primatives + */ + +#ifndef __METAL_XTENSA_CPU__H__ +#define __METAL_XTENSA_CPU__H__ + +#define metal_cpu_yield() +#define __sync_synchronize() + +#endif /* __METAL_XTENSA_CPU__H__ */ diff --git a/system/Middlewares/OpenAMP/libmetal/lib/softirq.h b/system/Middlewares/OpenAMP/libmetal/lib/softirq.h index 4ad4d42d5b..52ea00f18c 100644 --- a/system/Middlewares/OpenAMP/libmetal/lib/softirq.h +++ b/system/Middlewares/OpenAMP/libmetal/lib/softirq.h @@ -12,6 +12,8 @@ #ifndef __METAL_SOFTIRQ__H__ #define __METAL_SOFTIRQ__H__ +#include + #ifdef __cplusplus extern "C" { #endif @@ -20,8 +22,6 @@ extern "C" { * @{ */ -#include - /** * @brief metal_softirq_init * diff --git a/system/Middlewares/OpenAMP/libmetal/lib/system/freertos/cortexm/sys.c b/system/Middlewares/OpenAMP/libmetal/lib/system/freertos/cortexm/sys.c deleted file mode 100644 index e8970dc14d..0000000000 --- a/system/Middlewares/OpenAMP/libmetal/lib/system/freertos/cortexm/sys.c +++ /dev/null @@ -1,74 +0,0 @@ -/* - * Copyright (c) 2018, Linaro Inc. and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -/* - * @file freertos/template/sys.c - * @brief machine specific system primitives implementation. - */ - -#include -#include -#include -#include - -void sys_irq_restore_enable(unsigned int flags) -{ - metal_unused(flags); - /* Add implementation here */ -} - -unsigned int sys_irq_save_disable(void) -{ - return 0; - /* Add implementation here */ -} - -void sys_irq_enable(unsigned int vector) -{ - metal_unused(vector); - - /* Add implementation here */ -} - -void sys_irq_disable(unsigned int vector) -{ - metal_unused(vector); - - /* Add implementation here */ -} - -void metal_machine_cache_flush(void *addr, unsigned int len) -{ - metal_unused(addr); - metal_unused(len); - - /* Add implementation here */ -} - -void metal_machine_cache_invalidate(void *addr, unsigned int len) -{ - metal_unused(addr); - metal_unused(len); - - /* Add implementation here */ -} - -void metal_generic_default_poll(void) -{ - /* Add implementation here */ -} - -void *metal_machine_io_mem_map(void *va, metal_phys_addr_t pa, - size_t size, unsigned int flags) -{ - metal_unused(pa); - metal_unused(size); - metal_unused(flags); - - /* Add implementation here */ - - return va; -} diff --git a/system/Middlewares/OpenAMP/libmetal/lib/system/freertos/cortexm/sys.h b/system/Middlewares/OpenAMP/libmetal/lib/system/freertos/cortexm/sys.h deleted file mode 100644 index 2be8eb87d2..0000000000 --- a/system/Middlewares/OpenAMP/libmetal/lib/system/freertos/cortexm/sys.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Copyright (c) 2018, Linaro Inc. and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -/* - * @file freertos/template/sys.h - * @brief freertos template system primitives for libmetal. - */ - -#ifndef __METAL_FREERTOS_SYS__H__ -#error "Include metal/sys.h instead of metal/freertos/@PROJECT_MACHINE@/sys.h" -#endif - -#ifndef __METAL_FREERTOS_TEMPLATE_SYS__H__ -#define __METAL_FREERTOS_TEMPLATE_SYS__H__ - -#ifdef __cplusplus -extern "C" { -#endif - -#ifdef METAL_INTERNAL - -void sys_irq_enable(unsigned int vector); - -void sys_irq_disable(unsigned int vector); - -#endif /* METAL_INTERNAL */ - -#ifdef __cplusplus -} -#endif - -#endif /* __METAL_FREERTOS_SYS__H__ */ diff --git a/system/Middlewares/OpenAMP/libmetal/lib/system/freertos/mutex.h b/system/Middlewares/OpenAMP/libmetal/lib/system/freertos/mutex.h index 97f61aec19..4efaab2527 100644 --- a/system/Middlewares/OpenAMP/libmetal/lib/system/freertos/mutex.h +++ b/system/Middlewares/OpenAMP/libmetal/lib/system/freertos/mutex.h @@ -33,7 +33,17 @@ typedef struct { * METAL_MUTEX_INIT - used for initializing an mutex element in a static struct * or global */ +#if defined(__GNUC__) +#define METAL_MUTEX_INIT(m) { NULL }; \ +_Pragma("GCC warning\"static initialisation of the mutex is deprecated\"") +#elif defined(__ICCARM__) +#define DO_PRAGMA(x) _Pragma(#x) +#define METAL_MUTEX_INIT(m) { NULL }; \ +DO_PRAGMA(message("Warning: static initialisation of the mutex is deprecated")) +#else #define METAL_MUTEX_INIT(m) { NULL } +#endif + /* * METAL_MUTEX_DEFINE - used for defining and initializing a global or * static singleton mutex diff --git a/system/Middlewares/OpenAMP/libmetal/lib/system/freertos/template/sys.c b/system/Middlewares/OpenAMP/libmetal/lib/system/freertos/template/sys.c index 8d3652fa5f..e8970dc14d 100644 --- a/system/Middlewares/OpenAMP/libmetal/lib/system/freertos/template/sys.c +++ b/system/Middlewares/OpenAMP/libmetal/lib/system/freertos/template/sys.c @@ -5,7 +5,7 @@ */ /* - * @file generic/template/sys.c + * @file freertos/template/sys.c * @brief machine specific system primitives implementation. */ diff --git a/system/Middlewares/OpenAMP/libmetal/lib/system/generic/cortexm/CMakeLists.txt b/system/Middlewares/OpenAMP/libmetal/lib/system/generic/cortexm/CMakeLists.txt deleted file mode 100644 index 7d824ce188..0000000000 --- a/system/Middlewares/OpenAMP/libmetal/lib/system/generic/cortexm/CMakeLists.txt +++ /dev/null @@ -1,5 +0,0 @@ -collect (PROJECT_LIB_HEADERS sys.h) - -collect (PROJECT_LIB_SOURCES sys.c) - -# vim: expandtab:ts=2:sw=2:smartindent diff --git a/system/Middlewares/OpenAMP/libmetal/lib/system/generic/cortexm/sys.c b/system/Middlewares/OpenAMP/libmetal/lib/system/generic/cortexm/sys.c deleted file mode 100644 index 7b0b3856fe..0000000000 --- a/system/Middlewares/OpenAMP/libmetal/lib/system/generic/cortexm/sys.c +++ /dev/null @@ -1,77 +0,0 @@ -/* - * Copyright (c) 2016, Xilinx Inc. and Contributors. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. Neither the name of Xilinx nor the names of its contributors may be used - * to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -/* - * @file generic/sys.c - * @brief machine specific system primitives implementation. - */ - - -#include "metal/io.h" -#include "metal/sys.h" - -void sys_irq_restore_enable(unsigned int flags) -{ -} - -unsigned int sys_irq_save_disable(void) -{ - return 0; -} - -void metal_machine_cache_flush(void *addr, unsigned int len) -{ - (void)addr; - (void)len; -} - -void metal_machine_cache_invalidate(void *addr, unsigned int len) -{ - (void)addr; - (void)len; -} - -/** - * @brief poll function until some event happens - */ -void __attribute__((weak)) metal_generic_default_poll(void) -{ -} - -void *metal_machine_io_mem_map(void *va, metal_phys_addr_t pa, - size_t size, unsigned int flags) -{ - (void)va; - (void)pa; - (void)size; - (void)flags; - - return va; -} diff --git a/system/Middlewares/OpenAMP/libmetal/lib/system/generic/cortexm/sys.h b/system/Middlewares/OpenAMP/libmetal/lib/system/generic/cortexm/sys.h deleted file mode 100644 index 7fd8144cbf..0000000000 --- a/system/Middlewares/OpenAMP/libmetal/lib/system/generic/cortexm/sys.h +++ /dev/null @@ -1,65 +0,0 @@ -/* - * Copyright (c) 2015, Xilinx Inc. and Contributors. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. Neither the name of Xilinx nor the names of its contributors may be used - * to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -/* - * @file generic/mp1_m4/sys.h - * @brief generic mp1_m4 system primitives for libmetal. - */ - -#ifndef __METAL_GENERIC_SYS__H__ -#error "Include metal/sys.h instead of metal/generic/@PROJECT_MACHINE@/sys.h" -#endif - -#ifndef __METAL_GENERIC_MP1_M4_SYS__H__ -#define __METAL_GENERIC_MP1_M4_SYS__H__ - -#ifdef __cplusplus -extern "C" { -#endif - -#if !defined(MAX_IRQS) -#define MAX_IRQS 8 /**< maximum number of irqs */ -#endif - -static inline void sys_irq_enable(unsigned int vector) -{ - (void)vector; -} - -static inline void sys_irq_disable(unsigned int vector) -{ - (void)vector; -} - -#ifdef __cplusplus -} -#endif - -#endif /* __METAL_GENERIC_MP1_M4_SYS__H__ */ diff --git a/system/Middlewares/OpenAMP/libmetal/lib/system/linux/device.c b/system/Middlewares/OpenAMP/libmetal/lib/system/linux/device.c index fa1864ab00..734b473eec 100644 --- a/system/Middlewares/OpenAMP/libmetal/lib/system/linux/device.c +++ b/system/Middlewares/OpenAMP/libmetal/lib/system/linux/device.c @@ -266,7 +266,12 @@ static void metal_uio_dev_close(struct linux_bus *lbus, struct linux_device *ldev) { (void)lbus; + unsigned int i; + for (i = 0; i < ldev->device.num_regions; i++) { + metal_unmap(ldev->device.regions[i].virt, + ldev->device.regions[i].size); + } if (ldev->override) { sysfs_write_attribute(ldev->override, "", 1); ldev->override = NULL; diff --git a/system/Middlewares/OpenAMP/libmetal/lib/system/nuttx/io.c b/system/Middlewares/OpenAMP/libmetal/lib/system/nuttx/io.c index 9ce1e293a9..4fa4727eb4 100644 --- a/system/Middlewares/OpenAMP/libmetal/lib/system/nuttx/io.c +++ b/system/Middlewares/OpenAMP/libmetal/lib/system/nuttx/io.c @@ -75,13 +75,13 @@ static void metal_io_close_(struct metal_io_region *io) static metal_phys_addr_t metal_io_offset_to_phys_(struct metal_io_region *io, unsigned long offset) { - return up_addrenv_va_to_pa((char *)io->virt + offset); + return up_addrenv_va_to_pa((void *)((uintptr_t)io->virt + offset)); } static unsigned long metal_io_phys_to_offset_(struct metal_io_region *io, metal_phys_addr_t phys) { - return (char *)up_addrenv_pa_to_va(phys) - (char *)io->virt; + return (uintptr_t)up_addrenv_pa_to_va(phys) - (uintptr_t)io->virt; } static metal_phys_addr_t metal_io_phys_start_; diff --git a/system/Middlewares/OpenAMP/libmetal/lib/system/freertos/cortexm/CMakeLists.txt b/system/Middlewares/OpenAMP/libmetal/lib/system/zephyr/arm/CMakeLists.txt similarity index 100% rename from system/Middlewares/OpenAMP/libmetal/lib/system/freertos/cortexm/CMakeLists.txt rename to system/Middlewares/OpenAMP/libmetal/lib/system/zephyr/arm/CMakeLists.txt diff --git a/system/Middlewares/OpenAMP/libmetal/lib/system/zephyr/cortexm/sys.c b/system/Middlewares/OpenAMP/libmetal/lib/system/zephyr/arm/sys.c similarity index 100% rename from system/Middlewares/OpenAMP/libmetal/lib/system/zephyr/cortexm/sys.c rename to system/Middlewares/OpenAMP/libmetal/lib/system/zephyr/arm/sys.c diff --git a/system/Middlewares/OpenAMP/libmetal/lib/system/zephyr/cortexm/sys.h b/system/Middlewares/OpenAMP/libmetal/lib/system/zephyr/arm/sys.h similarity index 100% rename from system/Middlewares/OpenAMP/libmetal/lib/system/zephyr/cortexm/sys.h rename to system/Middlewares/OpenAMP/libmetal/lib/system/zephyr/arm/sys.h diff --git a/system/Middlewares/OpenAMP/libmetal/lib/system/zephyr/cache.h b/system/Middlewares/OpenAMP/libmetal/lib/system/zephyr/cache.h index e6efbc7adf..700d6e5558 100644 --- a/system/Middlewares/OpenAMP/libmetal/lib/system/zephyr/cache.h +++ b/system/Middlewares/OpenAMP/libmetal/lib/system/zephyr/cache.h @@ -25,13 +25,12 @@ extern "C" { static inline void __metal_cache_flush(void *addr, unsigned int len) { - sys_cache_flush((vaddr_t) addr, len); + sys_cache_data_range(addr, len, K_CACHE_WB); } static inline void __metal_cache_invalidate(void *addr, unsigned int len) { - metal_unused(addr); - metal_unused(len); + sys_cache_data_range(addr, len, K_CACHE_INVD); } #ifdef __cplusplus diff --git a/system/Middlewares/OpenAMP/libmetal/lib/system/zephyr/cortexm/CMakeLists.txt b/system/Middlewares/OpenAMP/libmetal/lib/system/zephyr/cortexm/CMakeLists.txt deleted file mode 100644 index 7d824ce188..0000000000 --- a/system/Middlewares/OpenAMP/libmetal/lib/system/zephyr/cortexm/CMakeLists.txt +++ /dev/null @@ -1,5 +0,0 @@ -collect (PROJECT_LIB_HEADERS sys.h) - -collect (PROJECT_LIB_SOURCES sys.c) - -# vim: expandtab:ts=2:sw=2:smartindent diff --git a/system/Middlewares/OpenAMP/libmetal/lib/time.h b/system/Middlewares/OpenAMP/libmetal/lib/time.h index 9e1762e089..bc24e61348 100644 --- a/system/Middlewares/OpenAMP/libmetal/lib/time.h +++ b/system/Middlewares/OpenAMP/libmetal/lib/time.h @@ -12,6 +12,9 @@ #ifndef __METAL_TIME__H__ #define __METAL_TIME__H__ +#include +#include + #ifdef __cplusplus extern "C" { #endif @@ -20,9 +23,6 @@ extern "C" { * @{ */ -#include -#include - /** * @brief get timestamp * This function returns the timestampe as unsigned long long diff --git a/system/Middlewares/OpenAMP/libmetal/st_readme.txt b/system/Middlewares/OpenAMP/libmetal/st_readme.txt index 1b9fe27a01..72532d1cf5 100644 --- a/system/Middlewares/OpenAMP/libmetal/st_readme.txt +++ b/system/Middlewares/OpenAMP/libmetal/st_readme.txt @@ -8,7 +8,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2021 STMicroelectronics. All rights reserved. + * Copyright (c) 2021-2022 STMicroelectronics. All rights reserved. * * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the @@ -18,6 +18,116 @@ ****************************************************************************** @endverbatim +### V1.0.5/18-January-2022 ### +=============================== + + Integrate official release v2021.10 + + + Fix compilation error with gcc++ + - lib/alloc.h + - lib/condition.h + - lib/dma.h + - lib/io.h + - lib/irq.h + - lib/mutex.h + - lib/softirq.h + - lib/time.h + + + Add include file generated by cmake + - lib/include/metal/alloc.h + - lib/include/metal/assert.h + - lib/include/metal/atomic.h + - lib/include/metal/cache.h + - lib/include/metal/compiler.h + - lib/include/metal/compiler/armcc/errno.h + - lib/include/metal/compiler/gcc/atomic.h + - lib/include/metal/compiler/gcc/compiler.h + - lib/include/metal/compiler/iar/compiler.h + - lib/include/metal/compiler/iar/errno.h + - lib/include/metal/condition.h + - lib/include/metal/config.h + - lib/include/metal/cpu.h + - lib/include/metal/device.h + - lib/include/metal/dma.h + - lib/include/metal/errno.h + - lib/include/metal/io.h + - lib/include/metal/irq.h + - lib/include/metal/irq_controller.h + - lib/include/metal/list.h + - lib/include/metal/log.h + - lib/include/metal/mutex.h + - lib/include/metal/processor/arm/atomic.h + - lib/include/metal/processor/arm/cpu.h + - lib/include/metal/shmem.h + - lib/include/metal/sleep.h + - lib/include/metal/softirq.h + - lib/include/metal/spinlock.h + - lib/include/metal/sys.h + - lib/include/metal/system/generic/alloc.h + - lib/include/metal/system/generic/assert.h + - lib/include/metal/system/generic/cache.h + - lib/include/metal/system/generic/condition.h + - lib/include/metal/system/generic/io.h + - lib/include/metal/system/generic/irq.h + - lib/include/metal/system/generic/log.h + - lib/include/metal/system/generic/mutex.h + - lib/include/metal/system/generic/sleep.h + - lib/include/metal/system/generic/sys.h + - .../metal/system/generic/template/sys.h + - lib/include/metal/time.h + - lib/include/metal/utilities.h + - lib/include/metal/version.h + + + Rename files to avoid compile error in IAR EWARM: + - lib/system/generic/device.c --> lib/system/generic/generic_device.c + - lib/system/generic/init.c --> lib/system/generic/generic_init.c + - lib/system/generic/io.c --> lib/system/generic/generic_io.c + - lib/system/generic/shmem.c --> lib/system/generic/generic_shmem.c + - lib/system/freertos/device.c --> lib/system/freertos/freertos_device.c + - lib/system/freertos/init.c --> lib/system/freertos/freertos_init.c + - lib/system/freertos/io.c --> lib/system/freertos/freertos_io.c + - lib/system/freertos/shmem.c --> lib/system/freertos/freertos_shmem.c + + + Reconfigure the libmetal for Freertos support: + - lib/include/metal/alloc.h + - lib/include/metal/assert.h + - lib/include/metal/cache.h + - lib/include/metal/condition.h + - lib/include/metal/config.h + - lib/include/metal/io.h + - lib/include/metal/irq.h + - lib/include/metal/log.h + - lib/include/metal/mutex.h + - lib/include/metal/sleep.h + - lib/include/metal/sys.h + - lib/include/metal/system/freertos/alloc.h + - lib/include/metal/system/freertos/assert.h + - lib/include/metal/system/freertos/cache.h + - lib/include/metal/system/freertos/condition.h + - lib/include/metal/system/freertos/io.h + - lib/include/metal/system/freertos/irq.h + - lib/include/metal/system/freertos/log.h + - lib/include/metal/system/freertos/mutex.h + - lib/include/metal/system/freertos/sleep.h + - lib/include/metal/system/freertos/sys.h + - .../metal/system/freertos/template/sys.h + + + lib:Add METAL_FREERTOS compilation configs + - lib/include/metal/alloc.h + - lib/include/metal/assert.h + - lib/include/metal/cache.h + - lib/include/metal/condition.h + - lib/include/metal/config.h + - lib/include/metal/io.h + - lib/include/metal/irq.h + - lib/include/metal/log.h + - lib/include/metal/mutex.h + - lib/include/metal/sleep.h + - lib/include/metal/sys.h + - lib/include/metal/system/freertos/mutex.h + + + Fix compile error reported by EWARM toolchain + - lib/system/freertos/freertos_io.c + ### V1.0.4/13-October-2021 ### =============================== + Fix compile error reported by EWARM toolchain diff --git a/system/Middlewares/OpenAMP/libmetal/test/CMakeLists.txt b/system/Middlewares/OpenAMP/libmetal/test/CMakeLists.txt index 95c57785bb..c0f40ccc8b 100644 --- a/system/Middlewares/OpenAMP/libmetal/test/CMakeLists.txt +++ b/system/Middlewares/OpenAMP/libmetal/test/CMakeLists.txt @@ -68,7 +68,7 @@ else (WITH_ZEPHYR) foreach (INCLUDE ${_headers}) string (REGEX REPLACE "[^a-zA-Z0-9]+" "-" _f ${INCLUDE}) configure_file (metal-header-template.c ${_f}.c) - list (APPEND _flist "${CMAKE_CURRENT_BINARY_DIR}/${_f}") + list (APPEND _flist "${CMAKE_CURRENT_BINARY_DIR}/${_f}.c") endforeach (INCLUDE) add_library (metal-headers STATIC ${_flist}) endif (WITH_ZEPHYR) diff --git a/system/Middlewares/OpenAMP/libmetal/test/system/zephyr/alloc.c b/system/Middlewares/OpenAMP/libmetal/test/system/zephyr/alloc.c index e3b86df0c6..2944b62ec7 100644 --- a/system/Middlewares/OpenAMP/libmetal/test/system/zephyr/alloc.c +++ b/system/Middlewares/OpenAMP/libmetal/test/system/zephyr/alloc.c @@ -7,6 +7,7 @@ #include #include +#include #include #include #include @@ -19,7 +20,7 @@ static int alloc(void) ptr = metal_allocate_memory(1000); if (!ptr) { metal_log(METAL_LOG_DEBUG, "failed to allocate memmory\n"); - return errno; + return -errno; } metal_free_memory(ptr); diff --git a/system/Middlewares/OpenAMP/mw_if/app_if/openamp_template.h b/system/Middlewares/OpenAMP/mw_if/app_if/openamp_template.h index 0fb1123b47..dab212faac 100644 --- a/system/Middlewares/OpenAMP/mw_if/app_if/openamp_template.h +++ b/system/Middlewares/OpenAMP/mw_if/app_if/openamp_template.h @@ -20,13 +20,14 @@ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __openamp_H #define __openamp_H -#ifdef __cplusplus - extern "C" { -#endif #include "openamp/open_amp.h" #include "openamp_conf.h" +#ifdef __cplusplus + extern "C" { +#endif + /* Private includes ----------------------------------------------------------*/ /* USER CODE BEGIN Includes */ diff --git a/system/Middlewares/OpenAMP/mw_if/st_readme.txt b/system/Middlewares/OpenAMP/mw_if/st_readme.txt index b5af2511c6..f607932186 100644 --- a/system/Middlewares/OpenAMP/mw_if/st_readme.txt +++ b/system/Middlewares/OpenAMP/mw_if/st_readme.txt @@ -8,7 +8,7 @@ ******************************************************************************** * @attention * - * Copyright (c) 2021 STMicroelectronics. All rights reserved. + * Copyright (c) 2022 STMicroelectronics. All rights reserved. * * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the @@ -18,6 +18,11 @@ ****************************************************************************** @endverbatim +### V1.0.6/18-January-2022 ### +================================ + + openamp_template.h + - fix include declaration with gcc++ + ### V1.0.5/15-September-2021 ### ================================ + openamp_template.c, openamp_template.h diff --git a/system/Middlewares/OpenAMP/open-amp/.github/actions/build_ci/entrypoint.sh b/system/Middlewares/OpenAMP/open-amp/.github/actions/build_ci/entrypoint.sh index aac6c7def2..10cd70245b 100644 --- a/system/Middlewares/OpenAMP/open-amp/.github/actions/build_ci/entrypoint.sh +++ b/system/Middlewares/OpenAMP/open-amp/.github/actions/build_ci/entrypoint.sh @@ -4,9 +4,9 @@ readonly TARGET="$1" ZEPHYR_TOOLCHAIN_VARIANT=zephyr ZEPHYR_SDK_INSTALL_DIR=/opt/zephyr-sdk -ZEPHYR_SDK_VERSION=0.11.4 +ZEPHYR_SDK_VERSION=0.13.1 ZEPHYR_SDK_DOWNLOAD_FOLDER=https://github.com/zephyrproject-rtos/sdk-ng/releases/download/v$ZEPHYR_SDK_VERSION -ZEPHYR_SDK_SETUP_BINARY=zephyr-sdk-$ZEPHYR_SDK_VERSION-setup.run +ZEPHYR_SDK_SETUP_BINARY=zephyr-sdk-$ZEPHYR_SDK_VERSION-linux-x86_64-setup.run ZEPHYR_SDK_DOWNLOAD_URL=$ZEPHYR_SDK_DOWNLOAD_FOLDER/$ZEPHYR_SDK_SETUP_BINARY FREERTOS_ZIP_URL=https://cfhcable.dl.sourceforge.net/project/freertos/FreeRTOS/V10.0.1/FreeRTOSv10.0.1.zip @@ -16,7 +16,8 @@ pre_build(){ echo 'Etc/UTC' > /etc/timezone || exit 1 ln -s /usr/share/zoneinfo/Etc/UTC /etc/localtime || exit 1 apt update || exit 1 - apt-get install -y cmake make + apt-get install -y make || exit 1 + sudo pip3 install cmake || exit 1 } build_linux(){ diff --git a/system/Middlewares/OpenAMP/open-amp/MAINTAINERS.md b/system/Middlewares/OpenAMP/open-amp/MAINTAINERS.md index cb6709b8f8..2e5273299a 100644 --- a/system/Middlewares/OpenAMP/open-amp/MAINTAINERS.md +++ b/system/Middlewares/OpenAMP/open-amp/MAINTAINERS.md @@ -1,23 +1,17 @@ # OpenAMP Maintainers -OpenAMP project is maintained by the OpenAMP open source community. Everyone -is encouraged to submit issues and changes to improve OpenAMP. +The OpenAMP project is maintained by the OpenAMP open source +community. Everyone is encouraged to submit issues and changes to +improve OpenAMP. -The intention of this file is to provide a set of names that developers can -consult when they have a question about OpenAMP and to provide a a set of -names to be CC'd when submitting a patch. +The intention of this file is to provide a set of names that developers +can consult when they have a question about OpenAMP and to provide a +set of names to be CC'd when submitting a patch. ## Project Administration -Ed Mooring +Ed Mooring Arnaud Pouliquen ### All patches CC here openamp-rp@lists.openampproject.org - -## Machines -### Xilinx Platform - Zynq-7000 -Ed Mooring - -### Xilinx Platform - Zynq UltraScale+ MPSoC -Ed Mooring diff --git a/system/Middlewares/OpenAMP/open-amp/README.md b/system/Middlewares/OpenAMP/open-amp/README.md index 4aff63d935..f983c36579 100644 --- a/system/Middlewares/OpenAMP/open-amp/README.md +++ b/system/Middlewares/OpenAMP/open-amp/README.md @@ -90,6 +90,10 @@ library for it project: * **WITH_SHARED_LIB** (default ON): Build with a shared library. * **WITH_ZEPHYR** (default OFF): Build open-amp as a zephyr library. This option is mandatory in a Zephyr environment. +* **WITH_DCACHE_VRINGS** (default OFF): Build with data cache operations + enabled on vrings. +* **WITH_DCACHE_BUFFERS** (default OFF): Build with data cache operations + enabled on buffers. * **RPMSG_BUFFER_SIZE** (default 512): adjust the size of the RPMsg buffers. The default value of the RPMsg size is compatible with the Linux Kernel hard coded value. If you AMP configuration is Linux kernel master/ OpenAMP remote, diff --git a/system/Middlewares/OpenAMP/open-amp/VERSION b/system/Middlewares/OpenAMP/open-amp/VERSION index 28f0f0226d..61df8f44d6 100644 --- a/system/Middlewares/OpenAMP/open-amp/VERSION +++ b/system/Middlewares/OpenAMP/open-amp/VERSION @@ -1,3 +1,3 @@ VERSION_MAJOR = 1 -VERSION_MINOR = 0 +VERSION_MINOR = 1 VERSION_PATCH = 0 diff --git a/system/Middlewares/OpenAMP/open-amp/apps/examples/CMakeLists.txt b/system/Middlewares/OpenAMP/open-amp/apps/examples/CMakeLists.txt index fa72d9ed7a..e75473e79e 100644 --- a/system/Middlewares/OpenAMP/open-amp/apps/examples/CMakeLists.txt +++ b/system/Middlewares/OpenAMP/open-amp/apps/examples/CMakeLists.txt @@ -13,5 +13,6 @@ if (WITH_LOAD_FW) endif (WITH_LOAD_FW) if (WITH_PROXY_APPS) add_subdirectory (rpc_demo) +add_subdirectory (linux_rpc_demo) endif (WITH_PROXY_APPS) endif (MACHINE MATCHES ".*microblaze.*") diff --git a/system/Middlewares/OpenAMP/open-amp/apps/examples/linux_rpc_demo/CMakeLists.txt b/system/Middlewares/OpenAMP/open-amp/apps/examples/linux_rpc_demo/CMakeLists.txt new file mode 100644 index 0000000000..f10cb898cc --- /dev/null +++ b/system/Middlewares/OpenAMP/open-amp/apps/examples/linux_rpc_demo/CMakeLists.txt @@ -0,0 +1,47 @@ +set (_cflags "${CMAKE_C_FLAGS} ${APP_EXTRA_C_FLAGS}") +set (_fw_dir "${APPS_SHARE_DIR}") + +collector_list (_list PROJECT_INC_DIRS) +collector_list (_app_list APP_INC_DIRS) +include_directories (${_list} ${_app_list} ${CMAKE_CURRENT_SOURCE_DIR}) + +collector_list (_list PROJECT_LIB_DIRS) +collector_list (_app_list APP_LIB_DIRS) +link_directories (${_list} ${_app_list}) + +get_property (_linker_opt GLOBAL PROPERTY APP_LINKER_LARGE_TEXT_OPT) +if (NOT _linker_opt) + get_property (_linker_opt GLOBAL PROPERTY APP_LINKER_OPT) +endif (NOT _linker_opt) +collector_list (_deps PROJECT_LIB_DEPS) + +set (OPENAMP_LIB open_amp) + +if (${PROJECT_SYSTEM} STREQUAL "linux") + set (app_list linux_rpc_demod linux_rpc_demo) +endif (${PROJECT_SYSTEM} STREQUAL "linux") + +foreach (_app ${app_list}) + collector_list (_sources APP_COMMON_SOURCES) + list (APPEND _sources "${CMAKE_CURRENT_SOURCE_DIR}/${_app}.c") + + if (WITH_SHARED_LIB) + add_executable (${_app}-shared ${_sources}) + target_link_libraries (${_app}-shared ${OPENAMP_LIB}-shared ${_deps}) + install (TARGETS ${_app}-shared RUNTIME DESTINATION ${CMAKE_INSTALL_BINDIR}) + endif (WITH_SHARED_LIB) + + if (WITH_STATIC_LIB) + if (${PROJECT_SYSTEM} STREQUAL "linux") + add_executable (${_app}-static ${_sources}) + target_link_libraries (${_app}-static ${OPENAMP_LIB}-static ${_deps}) + install (TARGETS ${_app}-static RUNTIME DESTINATION ${CMAKE_INSTALL_BINDIR}) + else (${PROJECT_SYSTEM}) + add_executable (${_app}.out ${_sources}) + set_source_files_properties(${_sources} PROPERTIES COMPILE_FLAGS "${_cflags}") + + target_link_libraries(${_app}.out -Wl,-Map=${_app}.map -Wl,--gc-sections ${_linker_opt} -Wl,--start-group ${OPENAMP_LIB}-static ${_deps} -Wl,--end-group) + install (TARGETS ${_app}.out RUNTIME DESTINATION ${CMAKE_INSTALL_BINDIR}) + endif (${PROJECT_SYSTEM} STREQUAL "linux" ) + endif (WITH_STATIC_LIB) +endforeach(_app) diff --git a/system/Middlewares/OpenAMP/open-amp/apps/examples/linux_rpc_demo/README.md b/system/Middlewares/OpenAMP/open-amp/apps/examples/linux_rpc_demo/README.md new file mode 100644 index 0000000000..40deb9d465 --- /dev/null +++ b/system/Middlewares/OpenAMP/open-amp/apps/examples/linux_rpc_demo/README.md @@ -0,0 +1,58 @@ +# linux_rpc_demo +This readme is about the OpenAMP linux_rpc_demo. + +The linux_rpc_demo is about remote procedure calls between linux master and linux +slave using rpmsg to perform +1. File operations such as open, read, write and close +2. I/O operation such as printf, scanf + +## Compilation + +### Linux Compilation +* Install libsysfs devel and libhugetlbfs devel packages on your Linux. +* build libmetal library: + + ``` + $ mkdir -p build-libmetal + $ cd build-libmetal + $ cmake + $ make VERBOSE=1 DESTDIR= install + ``` + +* build OpenAMP library: + + ``` + $ mkdir -p build-openamp + $ cd build-openamp + $ cmake -DCMAKE_INCLUDE_PATH= \ + -DCMAKE_LIBRARY_PATH= -DWITH_APPS=ON -DWITH_PROXY=ON + $ make VERBOSE=1 DESTDIR=$(pwd) install + ``` + +The OpenAMP library will be generated to `build/usr/local/lib` directory, headers will be +generated to `build/usr/local/include` directory, and the applications executable will be +generated to `build/usr/local/bin` directory. + +* cmake option `-DWITH_APPS=ON` is to build the demonstration applications. +* cmake option `-DWITH_PROXY=ON` to build the linux rpc app. + +## Run the Demo + +### linux_rpc_demo: + +* Start rpc demo server on one console + ``` + $ sudo LD_LIBRARY_PATH=/usr/local/lib:/usr/local/lib \ + build-openamp/usr/local/bin/linux_rpc_demod-shared + ``` + +* Run rpc demo client on another console to perform file and I/O operations on the server + ``` + $ sudo LD_LIBRARY_PATH=/usr/local/lib:/usr/local/lib \ + build-openamp/usr/local/bin/linux_rpc_demo-shared 1 + ``` +Enter the inputs on the master side the same gets printed on the remote side. You will see communication between the master and remote process using rpmsg calls. + +## Note: +`sudo` is required to run the OpenAMP demos between Linux processes, as it doesn't work on +some systems if you are normal users. diff --git a/system/Middlewares/OpenAMP/open-amp/apps/examples/linux_rpc_demo/linux-rpmsg-rpc-demo.h b/system/Middlewares/OpenAMP/open-amp/apps/examples/linux_rpc_demo/linux-rpmsg-rpc-demo.h new file mode 100644 index 0000000000..3340f9e6a3 --- /dev/null +++ b/system/Middlewares/OpenAMP/open-amp/apps/examples/linux_rpc_demo/linux-rpmsg-rpc-demo.h @@ -0,0 +1,79 @@ +/* + * Copyright (c) 2021, L&T Technology Services Ltd. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef RPMSG_RPC_DEMO_H +#define RPMSG_RPC_DEMO_H + +#define OPEN_ID 0x1UL +#define CLOSE_ID 0x2UL +#define WRITE_ID 0x3UL +#define READ_ID 0x4UL +#define ACK_STATUS_ID 0x5UL +#define TERM_ID 0x6UL +#define INPUT_ID 0x7UL +#define MAX_STRING_LEN 300 +#define MAX_FILE_NAME_LEN 10 + +typedef int (*rpmsg_rpc_poll)(void *arg); + +struct polling { + rpmsg_rpc_poll poll; + void *poll_arg; +}; + +struct rpmsg_rpc_req_open { + char filename[MAX_FILE_NAME_LEN]; + int flags; + int mode; +}; + +struct rpmsg_rpc_req_read { + int fd; + uint32_t buflen; +}; + +struct rpmsg_rpc_req_input { + uint32_t buflen; +}; + +struct rpmsg_rpc_req_write { + int fd; + uint32_t len; + char ptr[MAX_STRING_LEN]; +}; + +struct rpmsg_rpc_req_close { + int fd; +}; + +struct rpmsg_rpc_req_term { + int id; +}; + +struct rpmsg_rpc_resp_open { + int fd; +}; + +struct rpmsg_rpc_resp_read { + int bytes_read; + char buf[MAX_STRING_LEN]; +}; + +struct rpmsg_rpc_resp_input { + int bytes_read; + char buf[MAX_STRING_LEN]; +}; + +struct rpmsg_rpc_resp_write { + int bytes_written; +}; + +struct rpmsg_rpc_resp_close { + int close_ret; +}; + +#endif /* RPMSG_RPC_DEMO_H */ diff --git a/system/Middlewares/OpenAMP/open-amp/apps/examples/linux_rpc_demo/linux_rpc_demo.c b/system/Middlewares/OpenAMP/open-amp/apps/examples/linux_rpc_demo/linux_rpc_demo.c new file mode 100644 index 0000000000..63d2c780a8 --- /dev/null +++ b/system/Middlewares/OpenAMP/open-amp/apps/examples/linux_rpc_demo/linux_rpc_demo.c @@ -0,0 +1,599 @@ +/* + * Copyright (c) 2021, L&T Technology Services Ltd. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*This is a sample demonstration application that showcases usage of proxy + *from the remote core. + *This application is meant to run on the remote CPU running linux. + *This application can print to the master console and perform file I/O through + *rpmsg channels. + */ + +#include +#include +#include +#include +#include +#include +#include +#include "rsc_table.h" +#include "platform_info.h" +#include "linux-rpmsg-rpc-demo.h" + +#define REDEF_O_CREAT 0000100 +#define REDEF_O_EXCL 0000200 +#define REDEF_O_RDONLY 0000000 +#define REDEF_O_WRONLY 0000001 +#define REDEF_O_RDWR 0000002 +#define REDEF_O_APPEND 0002000 +#define REDEF_O_ACCMODE 0000003 + +#define LPRINTF(format, ...) printf(format, ##__VA_ARGS__) +#define LPERROR(format, ...) LPRINTF("ERROR: " format, ##__VA_ARGS__) + +static struct rpmsg_rpc_clt *rpmsg_default_rpc; +static int fd, bytes_written, bytes_read; +static struct polling poll; +static atomic_int wait_resp; + +static void rpmsg_rpc_shutdown(struct rpmsg_rpc_clt *rpc) +{ + (void)rpc; + LPRINTF("RPMSG RPC is shutting down.\r\n"); +} + +void linux_rpmsg_set_default_rpc(struct rpmsg_rpc_clt *rpc) +{ + if (!rpc) + return; + rpmsg_default_rpc = rpc; +} + +/************************************************************************* + * + * FUNCTION + * + * rpmsg_open_cb + * + * DESCRIPTION + * + * Callback function of rpmsg_open + * + *************************************************************************/ +void rpmsg_open_cb(struct rpmsg_rpc_clt *rpc, int status, void *data, + size_t len) +{ + struct rpmsg_rpc_resp_open *resp = + (struct rpmsg_rpc_resp_open *)data; + (void)len; + (void)rpc; + + /* Assign value from return args */ + if (status) + fd = 0; + else + fd = resp->fd; + + /* to clear the flag set in the caller function */ + atomic_flag_clear(&wait_resp); + +} + +/************************************************************************* + * + * FUNCTION + * + * rpmsg_open + * + * DESCRIPTION + * + * Open a file. + * + *************************************************************************/ +int rpmsg_open(const char *filename, int flags, int mode) +{ + struct rpmsg_rpc_clt *rpc = rpmsg_default_rpc; + struct rpmsg_rpc_req_open rpc_open_req; + int filename_len = strlen(filename) + 1; + unsigned int payload_size = sizeof(rpc_open_req); + + if (!filename || payload_size > (int)MAX_BUF_LEN || !rpc) { + return -EINVAL; + } + + /* Construct rpc payload */ + rpc_open_req.flags = flags; + rpc_open_req.mode = mode; + memcpy(rpc_open_req.filename, filename, filename_len); + + /* flag set to wait for response from endpoint callback */ + (void)atomic_flag_test_and_set(&wait_resp); + + /* Trying to send until the endpoint is ready */ + while (rpmsg_rpc_client_send(rpc, OPEN_ID, &rpc_open_req, payload_size) + < 0) { + if (poll.poll) + poll.poll(poll.poll_arg); + } + + /* waiting to get response from endpoint callback */ + while ((atomic_flag_test_and_set(&wait_resp))) { + if (poll.poll) + poll.poll(poll.poll_arg); + } + + return 0; +} + +static char *read_req_buffer; + +/************************************************************************* + * + * FUNCTION + * + * rpmsg_read_cb + * + * DESCRIPTION + * + * Callback function of rpmsg_read + * + *************************************************************************/ +void rpmsg_read_cb(struct rpmsg_rpc_clt *rpc, int status, void *data, + size_t len) +{ + struct rpmsg_rpc_resp_read *resp = + (struct rpmsg_rpc_resp_read *)data; + (void)len; + (void)rpc; + + if (status) { + bytes_read = 0; + goto out; + } + + /* Assign value from return args */ + if (resp->bytes_read > 0) { + memcpy(read_req_buffer, resp->buf, sizeof(resp->buf)); + } + bytes_read = resp->bytes_read; + +out: + /* to clear the flag set in the caller function */ + atomic_flag_clear(&wait_resp); +} + +/************************************************************************* + * + * FUNCTION + * + * rpmsg_read + * + * DESCRIPTION + * + * Read data through RPMsg channel + * + * return the number of data read, à in error case + *************************************************************************/ +int rpmsg_read(int fd, char *buffer, int buflen) +{ + struct rpmsg_rpc_clt *rpc = rpmsg_default_rpc; + struct rpmsg_rpc_req_read rpc_read_req; + unsigned int payload_size = sizeof(rpc_read_req); + int ret; + + if (!rpc || !buffer || buflen == 0) + return -EINVAL; + + /* store buffer address and size for the callback */ + read_req_buffer = buffer; + bytes_read = 0; + + /* Construct rpc payload */ + rpc_read_req.fd = fd; + rpc_read_req.buflen = buflen; + + /* flag set to wait for response from endpoint callback */ + (void)atomic_flag_test_and_set(&wait_resp); + + ret = rpmsg_rpc_client_send(rpc, READ_ID, &rpc_read_req, payload_size); + if (ret < 0) + return 0; + + /* waiting to get response from endpoint callback */ + while ((atomic_flag_test_and_set(&wait_resp))) { + if (poll.poll) + poll.poll(poll.poll_arg); + } + + return bytes_read; +} + +/************************************************************************* + * + * FUNCTION + * + * rpmsg_write_cb + * + * DESCRIPTION + * + * Callback function of rpmsg_write + * + *************************************************************************/ +void rpmsg_write_cb(struct rpmsg_rpc_clt *rpc, int status, void *data, + size_t len) +{ + struct rpmsg_rpc_resp_write *resp = + (struct rpmsg_rpc_resp_write *)data; + (void)len; + (void)rpc; + + if (status) + bytes_written = 0; + else + /* Assign value from return args */ + bytes_written = resp->bytes_written; + + /* to clear the flag set in the caller function */ + atomic_flag_clear(&wait_resp); +} + +/************************************************************************* + * + * FUNCTION + * + * rpmsg_write + * + * DESCRIPTION + * + * Write data through RPMsg channel + * + * return the number of data written, à in error case + *************************************************************************/ +int rpmsg_write(int fd, char *ptr, int len) +{ + struct rpmsg_rpc_clt *rpc = rpmsg_default_rpc; + struct rpmsg_rpc_req_write rpc_write_req; + unsigned int payload_size = sizeof(rpc_write_req); + int ret; + + if (!rpc) + return -EINVAL; + + bytes_written = 0; + + /* Construct rpc payload */ + rpc_write_req.fd = fd; + memcpy(rpc_write_req.ptr, ptr, len + 1); + rpc_write_req.len = len; + + /* flag set to wait for response from endpoint callback */ + (void)atomic_flag_test_and_set(&wait_resp); + + ret = rpmsg_rpc_client_send(rpc, WRITE_ID, &rpc_write_req, + payload_size); + if (ret < 0) + return 0; + + /* waiting to get response from endpoint callback */ + while ((atomic_flag_test_and_set(&wait_resp))) { + if (poll.poll) + poll.poll(poll.poll_arg); + } + + return bytes_written; + +} + +/************************************************************************* + * + * FUNCTION + * + * rpmsg_close_cb + * + * DESCRIPTION + * + * Callback function of rpmsg_close + * + *************************************************************************/ +void rpmsg_close_cb(struct rpmsg_rpc_clt *rpc, int status, void *data, + size_t len) +{ + (void)rpc; + (void)status; + (void)data; + (void)len; + + /* to clear the flag set in the caller function */ + atomic_flag_clear(&wait_resp); +} + +/************************************************************************* + * + * FUNCTION + * + * rpmsg_close + * + * DESCRIPTION + * + * Close a file. + * + *************************************************************************/ +int rpmsg_close(int fd) +{ + struct rpmsg_rpc_clt *rpc = rpmsg_default_rpc; + struct rpmsg_rpc_req_close rpc_close_req; + unsigned int payload_size = sizeof(rpc_close_req); + int ret; + + if (!rpc) + return -EINVAL; + + /* Construct rpc payload */ + rpc_close_req.fd = fd; + + /* flag set to wait for response from endpoint callback */ + (void)atomic_flag_test_and_set(&wait_resp); + + ret = rpmsg_rpc_client_send(rpc, CLOSE_ID, &rpc_close_req, + payload_size); + + /* waiting to get response from endpoint callback */ + while ((atomic_flag_test_and_set(&wait_resp))) { + if (poll.poll) + poll.poll(poll.poll_arg); + } + + return ret; +} + +static char *input_req_buffer; + +/************************************************************************* + * + * FUNCTION + * + * rpmsg_input_cb + * + * DESCRIPTION + * + * Callback function of rpmsg_input + * + *************************************************************************/ +void rpmsg_input_cb(struct rpmsg_rpc_clt *rpc, int status, void *data, + size_t len) +{ + struct rpmsg_rpc_resp_input *resp = + (struct rpmsg_rpc_resp_input *)data; + (void)len; + (void)rpc; + + if (status) { + bytes_read = 0; + goto out; + } + + /* Assign value from return args */ + if (resp->bytes_read > 0) { + memcpy(input_req_buffer, resp->buf, sizeof(resp->buf)); + } + + bytes_read = resp->bytes_read; + +out: + /* to clear the flag set in the caller function */ + atomic_flag_clear(&wait_resp); + +} + +/************************************************************************* + * + * FUNCTION + * + * rpmsg_input + * + * DESCRIPTION + * + * Read input through RPMsg channel + * + * return the number of byte read, 0 in error case + *************************************************************************/ +int rpmsg_input(char *buffer, int buflen) +{ + struct rpmsg_rpc_clt *rpc = rpmsg_default_rpc; + struct rpmsg_rpc_req_input rpc_input_req; + unsigned int payload_size = sizeof(rpc_input_req); + int ret; + + if (!rpc || !buffer || buflen == 0) + return -EINVAL; + + /* store buffer address and size for the callback */ + input_req_buffer = buffer; + bytes_read = 0; + + /* Construct rpc payload */ + rpc_input_req.buflen = buflen; + + /* flag set to wait for response from endpoint callback */ + (void)atomic_flag_test_and_set(&wait_resp); + ret = rpmsg_rpc_client_send(rpc, INPUT_ID, &buflen, payload_size); + if (ret < 0) + return 0; + + /* waiting to get response from endpoint callback */ + while ((atomic_flag_test_and_set(&wait_resp))) { + if (poll.poll) + poll.poll(poll.poll_arg); + } + + return bytes_read; +} + +/* Mapping ID with Callbacks into table */ +static const struct rpmsg_rpc_client_services rpc_table[] = { + {OPEN_ID, &rpmsg_open_cb }, + {READ_ID, &rpmsg_read_cb }, + {WRITE_ID, &rpmsg_write_cb }, + {CLOSE_ID, &rpmsg_close_cb }, + {INPUT_ID, &rpmsg_input_cb } + }; +/*----------------------------------------------------------------------------- + * + * Application specific + * + *----------------------------------------------------------------------------- + */ +int app(struct rpmsg_device *rdev, void *priv) +{ + struct rpmsg_rpc_clt rpc; + struct rpmsg_rpc_req_term rpccall; + + poll.poll = platform_poll; + poll.poll_arg = priv; + char *fname = "remote.file"; + char wbuff[50]; + char rbuff[300]; + char ubuff[50]; + char idata[50]; + char fdata[50]; + int table_len; + int ret; + + /* redirect I/Os */ + LPRINTF("Initializating I/Os redirection...\r\n"); + table_len = (int)sizeof(rpc_table) / sizeof(struct rpmsg_rpc_services); + atomic_init(&wait_resp, 1); + + ret = rpmsg_rpc_client_init(&rpc, rdev, + rpmsg_rpc_shutdown, rpc_table, table_len); + linux_rpmsg_set_default_rpc(&rpc); + + if (ret) { + LPRINTF("Failed to initialize rpmsg rpc\r\n"); + return -1; + } + + printf("\nRemote>Linux Remote Procedure Call (RPC) Demonstration\r\n"); + printf("\nRemote>***************************************************" + "\r\n"); + + printf("\nRemote>Rpmsg based retargetting to proxy initialized..\r\n"); + + /* Remote performing file IO on Master */ + printf("\nRemote>FileIO demo ..\r\n"); + + printf("\nRemote>Creating a file on master and writing to it..\r\n"); + rpmsg_open(fname, REDEF_O_CREAT | REDEF_O_WRONLY | REDEF_O_APPEND, + S_IRUSR | S_IWUSR); + printf("\nRemote>Opened file '%s' with fd = %d\r\n", fname, fd); + sprintf(wbuff, "This is a test string being written to file.."); + rpmsg_write(fd, wbuff, strlen(wbuff)); + printf("\nRemote>Wrote to fd = %d, size = %d, content = %s\r\n", fd, + bytes_written, wbuff); + rpmsg_close(fd); + printf("\nRemote>Closed fd = %d\r\n", fd); + + /* Remote performing file IO on Master */ + printf("\nRemote>Reading a file on master and displaying its " + "contents..\r\n"); + rpmsg_open(fname, REDEF_O_RDONLY, S_IRUSR | S_IWUSR); + printf("\nRemote>Opened file '%s' with fd = %d\r\n", fname, fd); + rpmsg_read(fd, rbuff, sizeof(rbuff)); + *(char *)(&rbuff[0] + bytes_read) = 0; + printf("\nRemote>Read from fd = %d, size = %d, " + "printing contents below .. %s\r\n", fd, bytes_read, rbuff); + rpmsg_close(fd); + printf("\nRemote>Closed fd = %d\r\n", fd); + + while (1) { + /* Remote performing STDIO on Master */ + printf("\nRemote>Remote firmware using scanf and printf .." + "\r\n"); + printf("\nRemote>Scanning user input from master..\r\n"); + printf("\nRemote>Enter name\r\n"); + rpmsg_input(ubuff, sizeof(ubuff)); + ret = bytes_read; + if (ret) { + printf("\nRemote>Enter age\r\n"); + rpmsg_input(idata, sizeof(idata)); + ret = bytes_read; + if (ret) { + printf("\nRemote>Enter value for pi\r\n"); + rpmsg_input(fdata, sizeof(fdata)); + ret = bytes_read; + if (ret) { + printf("\nRemote>User name = '%s'" + "\r\n", ubuff); + printf("\nRemote>User age = '%s'\r\n", + idata); + printf("\nRemote>User entered value of " + "pi = '%s'\r\n", fdata); + } + } + } + if (!ret) { + rpmsg_input(ubuff, sizeof(ubuff)); + printf("Remote> Invalid value. Starting again...."); + } else { + printf("\nRemote>Repeat demo ? (enter yes or no) \r\n"); + scanf("%s", ubuff); + if ((strcmp(ubuff, "no")) && (strcmp(ubuff, "yes"))) { + printf("\nRemote>Invalid option. Starting again" + "....\r\n"); + } else if ((!strcmp(ubuff, "no"))) { + printf("\nRemote>RPC retargetting quitting ..." + "\r\n"); + break; + } + } + } + + printf("\nRemote> Firmware's rpmsg-rpc-channel going down! \r\n"); + rpccall.id = TERM_ID; + (void)rpmsg_rpc_client_send(&rpc, TERM_ID, &rpccall, sizeof(rpccall)); + + LPRINTF("Release remoteproc procedure call\r\n"); + rpmsg_rpc_client_release(&rpc); + return 0; +} + +/*-----------------------------------------------------------------------------* + * Application entry point + *----------------------------------------------------------------------------- + */ + +int main(int argc, char *argv[]) +{ + void *platform; + struct rpmsg_device *rpdev; + int ret; + + LPRINTF("Starting application...\r\n"); + + /* Initialize platform */ + ret = platform_init(argc, argv, &platform); + if (ret) { + LPERROR("Failed to initialize platform.\r\n"); + ret = -1; + } else { + rpdev = platform_create_rpmsg_vdev(platform, 0, + VIRTIO_DEV_SLAVE, + NULL, NULL); + if (!rpdev) { + LPERROR("Failed to create rpmsg virtio device.\r\n"); + ret = -1; + } else { + app(rpdev, platform); + platform_release_rpmsg_vdev(rpdev, platform); + ret = 0; + } + } + + LPRINTF("Stopping application...\r\n"); + platform_cleanup(platform); + + return ret; +} diff --git a/system/Middlewares/OpenAMP/open-amp/apps/examples/linux_rpc_demo/linux_rpc_demod.c b/system/Middlewares/OpenAMP/open-amp/apps/examples/linux_rpc_demo/linux_rpc_demod.c new file mode 100644 index 0000000000..13772c6bc5 --- /dev/null +++ b/system/Middlewares/OpenAMP/open-amp/apps/examples/linux_rpc_demo/linux_rpc_demod.c @@ -0,0 +1,316 @@ +/* + * Copyright (c) 2021, L&T Technology Services Ltd. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*This is a sample demonstration application that showcases usage of proxy + *from the remote core. + *This application is meant to run on the remote CPU running linux. + *This application can print to the master console and perform file I/O through + *rpmsg channels. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "platform_info.h" +#include "linux-rpmsg-rpc-demo.h" + +#define REDEF_O_CREAT 100 +#define REDEF_O_EXCL 200 +#define REDEF_O_RDONLY 0 +#define REDEF_O_WRONLY 1 +#define REDEF_O_RDWR 2 +#define REDEF_O_APPEND 2000 +#define REDEF_O_ACCMODE 3 + +#define raw_printf(format, ...) printf(format, ##__VA_ARGS__) +#define LPRINTF(format, ...) raw_printf("Master> " format, ##__VA_ARGS__) +#define LPERROR(format, ...) LPRINTF("ERROR: " format, ##__VA_ARGS__) + +static void *platform; +static struct rpmsg_device *rpdev; +static struct rpmsg_rpc_svr rpcs; +int request_termination; +int ept_deleted; + +void rpmsg_service_server_unbind(struct rpmsg_endpoint *ept) +{ + (void)ept; + rpmsg_destroy_ept(&rpcs.ept); + LPRINTF("Endpoint is destroyed\r\n"); + ept_deleted = 1; +} + +void terminate_rpc_app(void) +{ + LPRINTF("Destroying endpoint.\r\n"); + if (!ept_deleted) + rpmsg_destroy_ept(&rpcs.ept); +} + +void exit_action_handler(int signum) +{ + (void)signum; + terminate_rpc_app(); +} + +void kill_action_handler(int signum) +{ + (void)signum; + LPRINTF("RPC service killed !!\r\n"); + + terminate_rpc_app(); + + if (rpdev) + platform_release_rpmsg_vdev(rpdev, platform); + if (platform) + platform_cleanup(platform); +} + +int rpmsg_handle_open(void *data, struct rpmsg_rpc_svr *rpcs) +{ + void *req_ptr = data + MAX_FUNC_ID_LEN; + struct rpmsg_rpc_req_open *rpc_open_req = req_ptr; + char *buf; + struct rpmsg_rpc_resp_open rpc_open_resp; + int payload_size = sizeof(rpc_open_resp); + struct rpmsg_endpoint *ept = &rpcs->ept; + int fd, ret; + + if (!rpc_open_req || !ept) + return -EINVAL; + buf = rpc_open_req->filename; + + /* Open remote fd */ + fd = open(buf, rpc_open_req->flags, rpc_open_req->mode); + + /* Construct rpc response */ + rpc_open_resp.fd = fd; + + /* Transmit rpc response */ + ret = rpmsg_rpc_server_send(rpcs, OPEN_ID, RPMSG_RPC_OK, &rpc_open_resp, + payload_size); + + return ret > 0 ? 0 : ret; +} + +int rpmsg_handle_close(void *data, struct rpmsg_rpc_svr *rpcs) +{ + void *req_ptr = data + MAX_FUNC_ID_LEN; + struct rpmsg_rpc_req_close *rpc_close_req = req_ptr; + struct rpmsg_rpc_resp_close rpc_close_resp; + struct rpmsg_endpoint *ept = &rpcs->ept; + int payload_size = sizeof(rpc_close_resp); + int ret; + + if (!rpc_close_req || !ept) + return -EINVAL; + + /* Close remote fd */ + ret = close(rpc_close_req->fd); + + /* Construct rpc response */ + rpc_close_resp.close_ret = ret; + + /* Transmit rpc response */ + ret = rpmsg_rpc_server_send(rpcs, CLOSE_ID, RPMSG_RPC_OK, + &rpc_close_resp, payload_size); + + return ret > 0 ? 0 : ret; +} + +int rpmsg_handle_read(void *data, struct rpmsg_rpc_svr *rpcs) +{ + void *req_ptr = data + MAX_FUNC_ID_LEN; + struct rpmsg_rpc_req_read *rpc_read_req = req_ptr; + struct rpmsg_rpc_resp_read rpc_read_resp; + struct rpmsg_endpoint *ept = &rpcs->ept; + unsigned long int bytes_read; + int payload_size = sizeof(rpc_read_resp); + int ret; + + if (!rpc_read_req || !ept) + return -EINVAL; + + if (rpc_read_req->fd == 0) { + bytes_read = MAX_STRING_LEN; + /* Perform read from fd for large size since this is a + * STD/I request + */ + bytes_read = read(rpc_read_req->fd, rpc_read_resp.buf, + bytes_read); + } else { + /* Perform read from fd */ + bytes_read = read(rpc_read_req->fd, rpc_read_resp.buf, + rpc_read_req->buflen); + } + + /* Construct rpc response */ + rpc_read_resp.bytes_read = bytes_read; + + /* Transmit rpc response */ + ret = rpmsg_rpc_server_send(rpcs, READ_ID, RPMSG_RPC_OK, &rpc_read_resp, + payload_size); + + return ret > 0 ? 0 : ret; +} + +int rpmsg_handle_write(void *data, struct rpmsg_rpc_svr *rpcs) +{ + void *req_ptr = data + MAX_FUNC_ID_LEN; + struct rpmsg_rpc_req_write *rpc_write_req = req_ptr; + struct rpmsg_rpc_resp_write rpc_write_resp; + struct rpmsg_endpoint *ept = &rpcs->ept; + int payload_size = sizeof(rpc_write_resp); + int bytes_written; + int ret; + + if (!rpc_write_req || !ept) + return -EINVAL; + + /* Write to remote fd */ + bytes_written = write(rpc_write_req->fd, rpc_write_req->ptr, + rpc_write_req->len); + + /* Construct rpc response */ + rpc_write_resp.bytes_written = bytes_written; + + /* Transmit rpc response */ + ret = rpmsg_rpc_server_send(rpcs, WRITE_ID, RPMSG_RPC_OK, + &rpc_write_resp, payload_size); + + return ret > 0 ? 0 : ret; +} + +int rpmsg_handle_input(void *data, struct rpmsg_rpc_svr *rpcs) +{ + void *req_ptr = data + MAX_FUNC_ID_LEN; + struct rpmsg_rpc_req_input *rpc_input_req = req_ptr; + struct rpmsg_rpc_resp_input rpc_input_resp; + struct rpmsg_endpoint *ept = &rpcs->ept; + int bytes_read; + int payload_size = sizeof(rpc_input_resp); + int ret; + + if (!rpc_input_req || !ept) + return -EINVAL; + + /* Input from remote */ + scanf("%s", rpc_input_resp.buf); + bytes_read = sizeof(rpc_input_resp.buf); + + /* Construct rpc response */ + rpc_input_resp.bytes_read = bytes_read; + + /* Transmit rpc response */ + ret = rpmsg_rpc_server_send(rpcs, INPUT_ID, RPMSG_RPC_OK, + &rpc_input_resp, payload_size); + + return ret > 0 ? 0 : ret; +} + +int rpmsg_handle_term(void *data, struct rpmsg_rpc_svr *rpcs) +{ + void *req_ptr = data + MAX_FUNC_ID_LEN; + struct rpmsg_rpc_req_term *rpc_term_req = req_ptr; + struct rpmsg_endpoint *ept = &rpcs->ept; + + printf("Received termination request at id %d from endpoint %s\r\n", + rpc_term_req->id, ept->name); + request_termination = 1; + + return 0; +} + +/* Service table */ +static struct rpmsg_rpc_services rpc_table[] = { + {OPEN_ID, &rpmsg_handle_open }, + {READ_ID, &rpmsg_handle_read }, + {WRITE_ID, &rpmsg_handle_write }, + {CLOSE_ID, &rpmsg_handle_close }, + {INPUT_ID, &rpmsg_handle_input }, + {TERM_ID, &rpmsg_handle_term } + }; + +/* Application entry point */ +int app(struct rpmsg_device *rdev, void *priv) +{ + int ret = 0; + struct sigaction exit_action; + struct sigaction kill_action; + + /* Initialize signalling infrastructure */ + memset(&exit_action, 0, sizeof(struct sigaction)); + memset(&kill_action, 0, sizeof(struct sigaction)); + exit_action.sa_handler = exit_action_handler; + kill_action.sa_handler = kill_action_handler; + sigaction(SIGTERM, &exit_action, NULL); + sigaction(SIGINT, &exit_action, NULL); + sigaction(SIGKILL, &kill_action, NULL); + sigaction(SIGHUP, &kill_action, NULL); + + /* Initialize RPMSG framework */ + LPRINTF("Try to create rpmsg endpoint.\r\n"); + + ret = rpmsg_rpc_server_init(&rpcs, rdev, rpc_table, + (int)sizeof(rpc_table) / sizeof( + struct rpmsg_rpc_services), + rpmsg_service_server_unbind); + + if (ret) { + LPERROR("Failed to create endpoint.\r\n"); + return -EINVAL; + } + + LPRINTF("Successfully created rpmsg endpoint.\r\n"); + while (1) { + platform_poll(priv); + /* we got a shutdown request, exit */ + if (ept_deleted || request_termination) { + break; + } + } + LPRINTF("\nRPC service exiting !!\r\n"); + + terminate_rpc_app(); + return ret; +} + +int main(int argc, char *argv[]) +{ + int ret; + + LPRINTF("Starting application...\r\n"); + + /* Initialize platform */ + ret = platform_init(argc, argv, &platform); + if (ret) { + LPERROR("Failed to initialize platform.\r\n"); + ret = -1; + } else { + rpdev = platform_create_rpmsg_vdev(platform, 0, + VIRTIO_DEV_MASTER, + NULL, NULL); + if (!rpdev) { + LPERROR("Failed to create rpmsg virtio device.\r\n"); + ret = -1; + } else { + app(rpdev, platform); + platform_release_rpmsg_vdev(rpdev, platform); + ret = 0; + } + } + + LPRINTF("Stopping application...\r\n"); + platform_cleanup(platform); + + return ret; +} diff --git a/system/Middlewares/OpenAMP/open-amp/cmake/options.cmake b/system/Middlewares/OpenAMP/open-amp/cmake/options.cmake index edb368982f..269f179728 100644 --- a/system/Middlewares/OpenAMP/open-amp/cmake/options.cmake +++ b/system/Middlewares/OpenAMP/open-amp/cmake/options.cmake @@ -74,6 +74,18 @@ if (NOT WITH_VIRTIO_SLAVE) add_definitions(-DVIRTIO_MASTER_ONLY) endif (NOT WITH_VIRTIO_SLAVE) +option (WITH_DCACHE_VRINGS "Build with vrings cache operations enabled" OFF) + +if (WITH_DCACHE_VRINGS) + add_definitions(-DVIRTIO_CACHED_VRINGS) +endif (WITH_DCACHE_VRINGS) + +option (WITH_DCACHE_BUFFERS "Build with vrings cache operations enabled" OFF) + +if (WITH_DCACHE_BUFFERS) + add_definitions(-DVIRTIO_CACHED_BUFFERS) +endif (WITH_DCACHE_BUFFERS) + # Set the complication flags set (CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -Wall -Wextra") diff --git a/system/Middlewares/OpenAMP/open-amp/lib/CMakeLists.txt b/system/Middlewares/OpenAMP/open-amp/lib/CMakeLists.txt index 3ff74d5b42..7962e9e9c5 100644 --- a/system/Middlewares/OpenAMP/open-amp/lib/CMakeLists.txt +++ b/system/Middlewares/OpenAMP/open-amp/lib/CMakeLists.txt @@ -13,6 +13,7 @@ add_subdirectory (remoteproc) if (WITH_PROXY) add_subdirectory (proxy) + add_subdirectory (service/rpmsg/rpc) endif (WITH_PROXY) set (OPENAMP_LIB open_amp) diff --git a/system/Middlewares/OpenAMP/open-amp/lib/include/openamp/rpmsg_rpc_client_server.h b/system/Middlewares/OpenAMP/open-amp/lib/include/openamp/rpmsg_rpc_client_server.h new file mode 100644 index 0000000000..78af1d2732 --- /dev/null +++ b/system/Middlewares/OpenAMP/open-amp/lib/include/openamp/rpmsg_rpc_client_server.h @@ -0,0 +1,207 @@ +/* + * Copyright (c) 2021, L&T Technology Services Ltd. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef RPMSG_RPC_CLIENT_SERVER_H +#define RPMSG_RPC_CLIENT_SERVER_H + +#include +#include + +#if defined __cplusplus +extern "C" { +#endif + +#define RPMSG_RPC_OK 0 +#define RPMSG_RPC_INVALID_ID (-1L) +#define RPMSG_RPC_SERVICE_NAME "rpmsg-rpc" + +/* RPMSG_BUFFER_SIZE = 512 + * sizeof(struct rpmsg_hdr) = 16 + * RPMSG_BUFFER_SIZE - sizeof(struct rpmsg_hdr) - 1 = 495 + * Aligning to 64 bits -> 488UL + */ +#define MAX_BUF_LEN 488UL +#define MAX_FUNC_ID_LEN sizeof(unsigned long int) + +struct rpmsg_rpc_clt; +struct rpmsg_rpc_svr; + +typedef void (*rpmsg_rpc_shutdown_cb)(struct rpmsg_rpc_clt *rpc); +typedef void (*app_cb)(struct rpmsg_rpc_clt *rpc, int statust, void *data, + size_t len); +typedef int (*rpmsg_rpc_syscall_cb)(void *data, struct rpmsg_rpc_svr *rpcs); + +/** + * struct rpmsg_rpc_request - rpc request message + * + * @id: service id + * @params: request params + * + */ +struct rpmsg_rpc_request { + uint32_t id; + unsigned char params[MAX_BUF_LEN]; +}; + +/** + * struct rpmsg_rpc_answer - rpc request message + * + * @id: service id + * @status: status of rpc + * @params: answer params + * + */ +METAL_PACKED_BEGIN +struct rpmsg_rpc_answer { + uint32_t id; + int32_t status; + unsigned char params[MAX_BUF_LEN]; +} METAL_PACKED_END; + +/** + * struct rpmsg_rpc_services - table for services + * + * @id: service id + * @cb_function: id callback + * + */ +struct rpmsg_rpc_services { + uint32_t id; + rpmsg_rpc_syscall_cb cb_function; +}; + +/** + * struct rpmsg_rpc_client_services - table for client services + * + * @id: service id + * @app_cb: id callback + * + */ +struct rpmsg_rpc_client_services { + uint32_t id; + app_cb cb; +}; + +/** + * struct rpmsg_rpc_svr - server remote procedure call data + * + * RPMsg RPC will send request to endpoint + * + * @ept: rpmsg_endpoint structure + * @services: service table + * @n_services: number of services + * + */ +struct rpmsg_rpc_svr { + struct rpmsg_endpoint ept; + const struct rpmsg_rpc_services *services; + unsigned int n_services; +}; + +/** + * struct rpmsg_rpc_clt - client remote procedure call data + * + * RPMsg RPC will send request to remote and + * wait for callback. + * + * @ept: rpmsg_endpoint structure + * @shutdown_cb: shutdown callback function + * @services: service table + * @n_services: number of services + * + */ +struct rpmsg_rpc_clt { + struct rpmsg_endpoint ept; + rpmsg_rpc_shutdown_cb shutdown_cb; + const struct rpmsg_rpc_client_services *services; + unsigned int n_services; +}; + +/** + * rpmsg_rpc_client_release - release RPMsg remote procedure call + * + * This function is to release remoteproc procedure call service + * + * @rpc: pointer to the client remote procedure call data + * + */ +void rpmsg_rpc_client_release(struct rpmsg_rpc_clt *rpc); + +/** + * rpmsg_rpc_client_init - initialize RPMsg remote procedure call + * + * This function is to initialize the remote procedure call + * client data. RPMsg RPC will send request to remote and + * wait for callback and load services to table + * + * @rpc: pointer to the client remote procedure call data + * @rdev: pointer to the rpmsg device + * @shutdown_cb: shutdown callback function + * @services: pointer to service table + * @len: length of table + * + * return 0 for success, and negative value for failure + */ +int rpmsg_rpc_client_init(struct rpmsg_rpc_clt *rpc, + struct rpmsg_device *rdev, + rpmsg_rpc_shutdown_cb shutdown_cb, + const struct rpmsg_rpc_client_services *services, + int len); + +/** + * rpmsg_rpc_server_init - initialize RPMsg rpc for server + * + * This function create endpoint and loads services into table + * + * @rpcs: pointer to the server rpc + * @rdev: pointer to the rpmsg device + * @services: pointer to service table + * @len: length of table + * @rpmsg_service_server_unbind: unbind function callback + * + * return 0 for success, and negative value for failure + */ +int rpmsg_rpc_server_init(struct rpmsg_rpc_svr *rpcs, struct rpmsg_device *rdev, + const struct rpmsg_rpc_services *services, int len, + rpmsg_ns_unbind_cb rpmsg_service_server_unbind); + +/** + * rpmsg_rpc_client_send - Request RPMsg RPC call + * + * @rpc: pointer to client remoteproc procedure call data + * @rpc_id: function id + * @request_param: pointer to request buffer + * @req_param_size: length of the request data + * + * return length of the received response, negative value for failure. + */ +int rpmsg_rpc_client_send(struct rpmsg_rpc_clt *rpc, + unsigned int rpc_id, void *request_param, + size_t req_param_size); + +/** + * rpmsg_rpc_server_send - Request RPMsg RPC call + * + * This function sends RPC request + * + * @rpcs: pointer to server rpc data + * @rpc_id: function id + * @status: status of rpc + * @request_param: pointer to request buffer + * @param_size: length of the request data + * + * return length of the received response, negative value for failure. + */ +int rpmsg_rpc_server_send(struct rpmsg_rpc_svr *rpcs, uint32_t rpc_id, + int status, void *request_param, + size_t param_size); + +#if defined __cplusplus +} +#endif + +#endif /* RPMSG_RPC_CLIENT_SERVER_H */ diff --git a/system/Middlewares/OpenAMP/open-amp/lib/rpmsg/rpmsg_virtio.c b/system/Middlewares/OpenAMP/open-amp/lib/rpmsg/rpmsg_virtio.c index 86a23ad497..c7c578d620 100644 --- a/system/Middlewares/OpenAMP/open-amp/lib/rpmsg/rpmsg_virtio.c +++ b/system/Middlewares/OpenAMP/open-amp/lib/rpmsg/rpmsg_virtio.c @@ -8,6 +8,7 @@ */ #include +#include #include #include #include @@ -102,6 +103,11 @@ static int rpmsg_virtio_enqueue_buffer(struct rpmsg_virtio_device *rvdev, uint16_t idx) { unsigned int role = rpmsg_virtio_get_role(rvdev); + +#ifdef VIRTIO_CACHED_BUFFERS + metal_cache_flush(buffer, len); +#endif /* VIRTIO_CACHED_BUFFERS */ + #ifndef VIRTIO_SLAVE_ONLY if (role == RPMSG_MASTER) { struct virtqueue_buf vqbuf; @@ -192,6 +198,11 @@ static void *rpmsg_virtio_get_rx_buffer(struct rpmsg_virtio_device *rvdev, } #endif /*!VIRTIO_MASTER_ONLY*/ +#ifdef VIRTIO_CACHED_BUFFERS + /* Invalidate the buffer before returning it */ + metal_cache_invalidate(data, *len); +#endif /* VIRTIO_CACHED_BUFFERS */ + return data; } diff --git a/system/Middlewares/OpenAMP/open-amp/lib/service/rpmsg/rpc/CMakeLists.txt b/system/Middlewares/OpenAMP/open-amp/lib/service/rpmsg/rpc/CMakeLists.txt new file mode 100644 index 0000000000..e583405aa2 --- /dev/null +++ b/system/Middlewares/OpenAMP/open-amp/lib/service/rpmsg/rpc/CMakeLists.txt @@ -0,0 +1,2 @@ +collect (PROJECT_LIB_SOURCES rpmsg_rpc_client.c) +collect (PROJECT_LIB_SOURCES rpmsg_rpc_server.c) diff --git a/system/Middlewares/OpenAMP/open-amp/lib/service/rpmsg/rpc/rpmsg_rpc_client.c b/system/Middlewares/OpenAMP/open-amp/lib/service/rpmsg/rpc/rpmsg_rpc_client.c new file mode 100644 index 0000000000..f4e30b2e16 --- /dev/null +++ b/system/Middlewares/OpenAMP/open-amp/lib/service/rpmsg/rpc/rpmsg_rpc_client.c @@ -0,0 +1,115 @@ +/* + * Copyright (c) 2021, L&T Technology Services Ltd. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +static int rpmsg_endpoint_client_cb(struct rpmsg_endpoint *, void *, size_t, + uint32_t, void *); + +static void rpmsg_service_client_unbind(struct rpmsg_endpoint *ept) +{ + struct rpmsg_rpc_clt *rpc; + (void)ept; + + rpc = metal_container_of(ept, struct rpmsg_rpc_clt, ept); + rpmsg_destroy_ept(&rpc->ept); + if (rpc->shutdown_cb) + rpc->shutdown_cb(rpc); +} + +int rpmsg_rpc_client_init(struct rpmsg_rpc_clt *rpc, + struct rpmsg_device *rdev, + rpmsg_rpc_shutdown_cb shutdown_cb, + const struct rpmsg_rpc_client_services *services, + int len) +{ + int ret; + + if (!rpc || !rdev) + return -EINVAL; + + rpc->services = services; + rpc->n_services = len; + + rpc->shutdown_cb = shutdown_cb; + + ret = rpmsg_create_ept(&rpc->ept, rdev, + RPMSG_RPC_SERVICE_NAME, RPMSG_ADDR_ANY, + RPMSG_ADDR_ANY, + rpmsg_endpoint_client_cb, + rpmsg_service_client_unbind); + + return ret; +} + +int rpmsg_rpc_client_send(struct rpmsg_rpc_clt *rpc, + unsigned int rpc_id, void *request_param, + size_t req_param_size) +{ + unsigned char tmpbuf[MAX_BUF_LEN]; + + if (!rpc) + return -EINVAL; + + /* to optimize with the zero copy API */ + memcpy(tmpbuf, &rpc_id, MAX_FUNC_ID_LEN); + memcpy(&tmpbuf[MAX_FUNC_ID_LEN], request_param, req_param_size); + return rpmsg_send(&rpc->ept, tmpbuf, MAX_FUNC_ID_LEN + req_param_size); +} + +static const struct rpmsg_rpc_client_services *find_service(struct + rpmsg_rpc_clt * rpc, + uint32_t id) +{ + const struct rpmsg_rpc_client_services *service; + + for (unsigned int i = 0; i < rpc->n_services; i++) { + service = &rpc->services[i]; + + if (service->id == id) { + return service; + } + } + return NULL; +} + +void rpmsg_rpc_client_release(struct rpmsg_rpc_clt *rpc) +{ + if (!rpc) + return; + if (&rpc->ept) + rpmsg_destroy_ept(&rpc->ept); + +} + +static int rpmsg_endpoint_client_cb(struct rpmsg_endpoint *ept, + void *data, size_t len, + uint32_t src, void *priv) +{ + struct rpmsg_rpc_clt *rpc; + const struct rpmsg_rpc_client_services *service; + struct rpmsg_rpc_answer *msg; + (void)priv; + (void)src; + + if (!data || !ept) + return -EINVAL; + + msg = (struct rpmsg_rpc_answer *)data; + + rpc = metal_container_of(ept, + struct rpmsg_rpc_clt, + ept); + service = find_service(rpc, msg->id); + if (!service) + return -EINVAL; + + /* Invoke the callback function of the rpc */ + service->cb(rpc, msg->status, msg->params, len); + + return RPMSG_SUCCESS; +} diff --git a/system/Middlewares/OpenAMP/open-amp/lib/service/rpmsg/rpc/rpmsg_rpc_server.c b/system/Middlewares/OpenAMP/open-amp/lib/service/rpmsg/rpc/rpmsg_rpc_server.c new file mode 100644 index 0000000000..33a51c10d9 --- /dev/null +++ b/system/Middlewares/OpenAMP/open-amp/lib/service/rpmsg/rpc/rpmsg_rpc_server.c @@ -0,0 +1,97 @@ +/* + * Copyright (c) 2021, L&T Technology Services Ltd. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#define LPERROR(format, ...) metal_log(METAL_LOG_ERROR, format, ##__VA_ARGS__) + +static int rpmsg_endpoint_server_cb(struct rpmsg_endpoint *, void *, + size_t, uint32_t, void *); + +int rpmsg_rpc_server_init(struct rpmsg_rpc_svr *rpcs, struct rpmsg_device *rdev, + const struct rpmsg_rpc_services *services, int len, + rpmsg_ns_unbind_cb rpmsg_service_server_unbind) +{ + int ret; + + rpcs->services = services; + rpcs->n_services = len; + + ret = rpmsg_create_ept(&rpcs->ept, rdev, RPMSG_RPC_SERVICE_NAME, + RPMSG_ADDR_ANY, RPMSG_ADDR_ANY, + rpmsg_endpoint_server_cb, + rpmsg_service_server_unbind); + if (ret) + return ret; + + return ret; +} + +static const struct rpmsg_rpc_services *find_service(struct rpmsg_rpc_svr *rpcs, + unsigned int id) +{ + const struct rpmsg_rpc_services *service; + + for (unsigned int i = 0; i < rpcs->n_services; i++) { + service = &rpcs->services[i]; + + if (service->id == id) { + return service; + } + } + return NULL; +} + +static int rpmsg_endpoint_server_cb(struct rpmsg_endpoint *ept, void *data, + size_t len, + uint32_t src, void *priv) +{ + unsigned char buf[MAX_BUF_LEN]; + unsigned int id; + const struct rpmsg_rpc_services *service; + struct rpmsg_rpc_svr *rpcs; + (void)priv; + (void)src; + + if (len > MAX_BUF_LEN) + return -EINVAL; + + rpcs = metal_container_of(ept, struct rpmsg_rpc_svr, ept); + + memcpy(buf, data, len); + id = *buf; + service = find_service(rpcs, id); + + if (service) { + if (service->cb_function(buf, rpcs)) { + LPERROR("Service failed at rpc id: %ld\r\n", id); + } + } else { + LPERROR("Handling remote procedure call errors: rpc id %ld\r\n", + id); + rpmsg_rpc_server_send(rpcs, id, RPMSG_RPC_INVALID_ID, NULL, 0); + } + return RPMSG_SUCCESS; +} + +int rpmsg_rpc_server_send(struct rpmsg_rpc_svr *rpcs, uint32_t rpc_id, + int status, void *request_param, size_t param_size) +{ + struct rpmsg_endpoint *ept = &rpcs->ept; + struct rpmsg_rpc_answer msg; + + if (!ept) + return -EINVAL; + if (param_size > (MAX_BUF_LEN - sizeof(msg.status))) + return -EINVAL; + + msg.id = rpc_id; + msg.status = status; + memcpy(msg.params, request_param, param_size); + + return rpmsg_send(ept, &msg, MAX_FUNC_ID_LEN + param_size); +} diff --git a/system/Middlewares/OpenAMP/open-amp/lib/virtio/virtqueue.c b/system/Middlewares/OpenAMP/open-amp/lib/virtio/virtqueue.c index c7edf583c5..889f5b6377 100644 --- a/system/Middlewares/OpenAMP/open-amp/lib/virtio/virtqueue.c +++ b/system/Middlewares/OpenAMP/open-amp/lib/virtio/virtqueue.c @@ -11,6 +11,7 @@ #include #include #include +#include /* Prototype for internal functions. */ static void vq_ring_init(struct virtqueue *, void *, int); @@ -28,6 +29,14 @@ static int virtqueue_nused(struct virtqueue *vq); static int virtqueue_navail(struct virtqueue *vq); #endif +#ifdef VIRTIO_CACHED_VRINGS +#define VRING_FLUSH(x) metal_cache_flush(&x, sizeof(x)) +#define VRING_INVALIDATE(x) metal_cache_invalidate(&x, sizeof(x)) +#else +#define VRING_FLUSH(x) do { } while (0) +#define VRING_INVALIDATE(x) do { } while (0) +#endif /* VIRTIO_CACHED_VRINGS */ + /* Default implementation of P2V based on libmetal */ static inline void *virtqueue_phys_to_virt(struct virtqueue *vq, metal_phys_addr_t phys) @@ -88,6 +97,11 @@ int virtqueue_create(struct virtio_device *virt_dev, unsigned short id, vq_ring_init(vq, ring->vaddr, ring->align); } + /* + * CACHE: nothing to be done here. Only desc.next is setup at this + * stage but that is only written by master, so no need to flush it. + */ + return status; } @@ -174,6 +188,9 @@ void *virtqueue_get_buffer(struct virtqueue *vq, uint32_t *len, uint16_t *idx) void *cookie; uint16_t used_idx, desc_idx; + /* Used.idx is updated by slave, so we need to invalidate */ + VRING_INVALIDATE(vq->vq_ring.used->idx); + if (!vq || vq->vq_used_cons_idx == vq->vq_ring.used->idx) return NULL; @@ -184,6 +201,9 @@ void *virtqueue_get_buffer(struct virtqueue *vq, uint32_t *len, uint16_t *idx) atomic_thread_fence(memory_order_seq_cst); + /* Used.ring is written by slave, invalidate it */ + VRING_INVALIDATE(vq->vq_ring.used->ring[used_idx]); + desc_idx = (uint16_t)uep->id; if (len) *len = uep->len; @@ -202,6 +222,7 @@ void *virtqueue_get_buffer(struct virtqueue *vq, uint32_t *len, uint16_t *idx) uint32_t virtqueue_get_buffer_length(struct virtqueue *vq, uint16_t idx) { + VRING_INVALIDATE(vq->vq_ring.desc[idx].len); return vq->vq_ring.desc[idx].len; } @@ -241,15 +262,23 @@ void *virtqueue_get_available_buffer(struct virtqueue *vq, uint16_t *avail_idx, void *buffer; atomic_thread_fence(memory_order_seq_cst); + + /* Avail.idx is updated by master, invalidate it */ + VRING_INVALIDATE(vq->vq_ring.avail->idx); if (vq->vq_available_idx == vq->vq_ring.avail->idx) { return NULL; } VQUEUE_BUSY(vq); + /* Avail.ring is updated by master, invalidate it */ + VRING_INVALIDATE(vq->vq_ring.avail->ring[head_idx]); + head_idx = vq->vq_available_idx++ & (vq->vq_nentries - 1); *avail_idx = vq->vq_ring.avail->ring[head_idx]; + /* Invalidate the desc entry written by master before accessing it */ + VRING_INVALIDATE(vq->vq_ring.desc[*avail_idx]); buffer = virtqueue_phys_to_virt(vq, vq->vq_ring.desc[*avail_idx].addr); *len = vq->vq_ring.desc[*avail_idx].len; @@ -279,15 +308,22 @@ int virtqueue_add_consumed_buffer(struct virtqueue *vq, uint16_t head_idx, VQUEUE_BUSY(vq); + /* CACHE: used is never written by master, so it's safe to directly access it */ used_idx = vq->vq_ring.used->idx & (vq->vq_nentries - 1); used_desc = &vq->vq_ring.used->ring[used_idx]; used_desc->id = head_idx; used_desc->len = len; + /* We still need to flush it because this is read by master */ + VRING_FLUSH(vq->vq_ring.used->ring[used_idx]); + atomic_thread_fence(memory_order_seq_cst); vq->vq_ring.used->idx++; + /* Used.idx is read by master, so we need to flush it */ + VRING_FLUSH(vq->vq_ring.used->idx); + /* Keep pending count until virtqueue_notify(). */ vq->vq_queued_cnt++; @@ -323,22 +359,28 @@ void virtqueue_disable_cb(struct virtqueue *vq) if (vq->vq_dev->role == VIRTIO_DEV_MASTER) { vring_used_event(&vq->vq_ring) = vq->vq_used_cons_idx - vq->vq_nentries - 1; + VRING_FLUSH(vring_used_event(&vq->vq_ring)); } #endif /*VIRTIO_SLAVE_ONLY*/ #ifndef VIRTIO_MASTER_ONLY if (vq->vq_dev->role == VIRTIO_DEV_SLAVE) { vring_avail_event(&vq->vq_ring) = vq->vq_available_idx - vq->vq_nentries - 1; + VRING_FLUSH(vring_avail_event(&vq->vq_ring)); } #endif /*VIRTIO_MASTER_ONLY*/ } else { #ifndef VIRTIO_SLAVE_ONLY - if (vq->vq_dev->role == VIRTIO_DEV_MASTER) + if (vq->vq_dev->role == VIRTIO_DEV_MASTER) { vq->vq_ring.avail->flags |= VRING_AVAIL_F_NO_INTERRUPT; + VRING_FLUSH(vq->vq_ring.avail->flags); + } #endif /*VIRTIO_SLAVE_ONLY*/ #ifndef VIRTIO_MASTER_ONLY - if (vq->vq_dev->role == VIRTIO_DEV_SLAVE) + if (vq->vq_dev->role == VIRTIO_DEV_SLAVE) { vq->vq_ring.used->flags |= VRING_USED_F_NO_NOTIFY; + VRING_FLUSH(vq->vq_ring.used->flags); + } #endif /*VIRTIO_MASTER_ONLY*/ } @@ -375,6 +417,9 @@ void virtqueue_dump(struct virtqueue *vq) if (!vq) return; + VRING_INVALIDATE(vq->vq_ring.avail); + VRING_INVALIDATE(vq->vq_ring.used); + metal_log(METAL_LOG_DEBUG, "VQ: %s - size=%d; free=%d; queued=%d; " "desc_head_idx=%d; avail.idx=%d; used_cons_idx=%d; " @@ -399,14 +444,24 @@ uint32_t virtqueue_get_desc_size(struct virtqueue *vq) uint16_t avail_idx = 0; uint32_t len = 0; + /* Avail.idx is updated by master, invalidate it */ + VRING_INVALIDATE(vq->vq_ring.avail->idx); + if (vq->vq_available_idx == vq->vq_ring.avail->idx) { return 0; } VQUEUE_BUSY(vq); + /* Avail.ring is updated by master, invalidate it */ + VRING_INVALIDATE(vq->vq_ring.avail->ring[head_idx]); + head_idx = vq->vq_available_idx & (vq->vq_nentries - 1); avail_idx = vq->vq_ring.avail->ring[head_idx]; + + /* Invalidate the desc entry written by master before accessing it */ + VRING_INVALIDATE(vq->vq_ring.desc[avail_idx].len); + len = vq->vq_ring.desc[avail_idx].len; VQUEUE_IDLE(vq); @@ -440,6 +495,7 @@ static uint16_t vq_ring_add_buffer(struct virtqueue *vq, VQASSERT(vq, idx != VQ_RING_DESC_CHAIN_END, "premature end of free desc chain"); + /* CACHE: No need to invalidate desc because it is only written by master */ dp = &desc[idx]; dp->addr = virtqueue_virt_to_phys(vq, buf_list[i].buf); dp->len = buf_list[i].len; @@ -454,6 +510,13 @@ static uint16_t vq_ring_add_buffer(struct virtqueue *vq, */ if (i >= readable) dp->flags |= VRING_DESC_F_WRITE; + + /* + * Instead of flushing the whole desc region, we flush only the + * single entry hopefully saving some cycles + */ + VRING_FLUSH(desc[idx]); + } return idx; @@ -469,6 +532,7 @@ static void vq_ring_free_chain(struct virtqueue *vq, uint16_t desc_idx) struct vring_desc *dp; struct vq_desc_extra *dxp; + /* CACHE: desc is never written by slave, no need to invalidate */ VQ_RING_ASSERT_VALID_IDX(vq, desc_idx); dp = &vq->vq_ring.desc[desc_idx]; dxp = &vq->vq_descx[desc_idx]; @@ -495,6 +559,8 @@ static void vq_ring_free_chain(struct virtqueue *vq, uint16_t desc_idx) * We must append the existing free chain, if any, to the end of * newly freed chain. If the virtqueue was completely used, then * head would be VQ_RING_DESC_CHAIN_END (ASSERTed above). + * + * CACHE: desc.next is never read by slave, no need to flush it. */ dp->next = vq->vq_desc_head_idx; vq->vq_desc_head_idx = desc_idx; @@ -541,14 +607,22 @@ static void vq_ring_update_avail(struct virtqueue *vq, uint16_t desc_idx) * deferring to virtqueue_notify() in the hopes that if the host is * currently running on another CPU, we can keep it processing the new * descriptor. + * + * CACHE: avail is never written by slave, so it is safe to not invalidate here */ avail_idx = vq->vq_ring.avail->idx & (vq->vq_nentries - 1); vq->vq_ring.avail->ring[avail_idx] = desc_idx; + /* We still need to flush the ring */ + VRING_FLUSH(vq->vq_ring.avail->ring[avail_idx]); + atomic_thread_fence(memory_order_seq_cst); vq->vq_ring.avail->idx++; + /* And the index */ + VRING_FLUSH(vq->vq_ring.avail->idx); + /* Keep pending count until virtqueue_notify(). */ vq->vq_queued_cnt++; } @@ -566,23 +640,31 @@ static int vq_ring_enable_interrupt(struct virtqueue *vq, uint16_t ndesc) */ if (vq->vq_dev->features & VIRTIO_RING_F_EVENT_IDX) { #ifndef VIRTIO_SLAVE_ONLY - if (vq->vq_dev->role == VIRTIO_DEV_MASTER) + if (vq->vq_dev->role == VIRTIO_DEV_MASTER) { vring_used_event(&vq->vq_ring) = vq->vq_used_cons_idx + ndesc; + VRING_FLUSH(vring_used_event(&vq->vq_ring)); + } #endif /*VIRTIO_SLAVE_ONLY*/ #ifndef VIRTIO_MASTER_ONLY - if (vq->vq_dev->role == VIRTIO_DEV_SLAVE) + if (vq->vq_dev->role == VIRTIO_DEV_SLAVE) { vring_avail_event(&vq->vq_ring) = vq->vq_available_idx + ndesc; + VRING_FLUSH(vring_avail_event(&vq->vq_ring)); + } #endif /*VIRTIO_MASTER_ONLY*/ } else { #ifndef VIRTIO_SLAVE_ONLY - if (vq->vq_dev->role == VIRTIO_DEV_MASTER) + if (vq->vq_dev->role == VIRTIO_DEV_MASTER) { vq->vq_ring.avail->flags &= ~VRING_AVAIL_F_NO_INTERRUPT; + VRING_FLUSH(vq->vq_ring.avail->flags); + } #endif /*VIRTIO_SLAVE_ONLY*/ #ifndef VIRTIO_MASTER_ONLY - if (vq->vq_dev->role == VIRTIO_DEV_SLAVE) + if (vq->vq_dev->role == VIRTIO_DEV_SLAVE) { vq->vq_ring.used->flags &= ~VRING_USED_F_NO_NOTIFY; + VRING_FLUSH(vq->vq_ring.used->flags); + } #endif /*VIRTIO_MASTER_ONLY*/ } @@ -635,8 +717,10 @@ static int vq_ring_must_notify(struct virtqueue *vq) if (vq->vq_dev->features & VIRTIO_RING_F_EVENT_IDX) { #ifndef VIRTIO_SLAVE_ONLY if (vq->vq_dev->role == VIRTIO_DEV_MASTER) { + /* CACHE: no need to invalidate avail */ new_idx = vq->vq_ring.avail->idx; prev_idx = new_idx - vq->vq_queued_cnt; + VRING_INVALIDATE(vring_avail_event(&vq->vq_ring)); event_idx = vring_avail_event(&vq->vq_ring); return vring_need_event(event_idx, new_idx, prev_idx) != 0; @@ -644,8 +728,10 @@ static int vq_ring_must_notify(struct virtqueue *vq) #endif /*VIRTIO_SLAVE_ONLY*/ #ifndef VIRTIO_MASTER_ONLY if (vq->vq_dev->role == VIRTIO_DEV_SLAVE) { + /* CACHE: no need to invalidate used */ new_idx = vq->vq_ring.used->idx; prev_idx = new_idx - vq->vq_queued_cnt; + VRING_INVALIDATE(vring_used_event(&vq->vq_ring)); event_idx = vring_used_event(&vq->vq_ring); return vring_need_event(event_idx, new_idx, prev_idx) != 0; @@ -653,14 +739,18 @@ static int vq_ring_must_notify(struct virtqueue *vq) #endif /*VIRTIO_MASTER_ONLY*/ } else { #ifndef VIRTIO_SLAVE_ONLY - if (vq->vq_dev->role == VIRTIO_DEV_MASTER) + if (vq->vq_dev->role == VIRTIO_DEV_MASTER) { + VRING_INVALIDATE(vq->vq_ring.used->flags); return (vq->vq_ring.used->flags & VRING_USED_F_NO_NOTIFY) == 0; + } #endif /*VIRTIO_SLAVE_ONLY*/ #ifndef VIRTIO_MASTER_ONLY - if (vq->vq_dev->role == VIRTIO_DEV_SLAVE) + if (vq->vq_dev->role == VIRTIO_DEV_SLAVE) { + VRING_INVALIDATE(vq->vq_ring.avail->flags); return (vq->vq_ring.avail->flags & VRING_AVAIL_F_NO_INTERRUPT) == 0; + } #endif /*VIRTIO_MASTER_ONLY*/ } @@ -688,6 +778,8 @@ static int virtqueue_nused(struct virtqueue *vq) { uint16_t used_idx, nused; + /* Used is written by slave */ + VRING_INVALIDATE(vq->vq_ring.used->idx); used_idx = vq->vq_ring.used->idx; nused = (uint16_t)(used_idx - vq->vq_used_cons_idx); @@ -707,6 +799,9 @@ static int virtqueue_navail(struct virtqueue *vq) { uint16_t avail_idx, navail; + /* Avail is written by master */ + VRING_INVALIDATE(vq->vq_ring.avail->idx); + avail_idx = vq->vq_ring.avail->idx; navail = (uint16_t)(avail_idx - vq->vq_available_idx); diff --git a/system/Middlewares/OpenAMP/open-amp/st_readme.txt b/system/Middlewares/OpenAMP/open-amp/st_readme.txt index bf814bb560..a12fd94e98 100644 --- a/system/Middlewares/OpenAMP/open-amp/st_readme.txt +++ b/system/Middlewares/OpenAMP/open-amp/st_readme.txt @@ -8,7 +8,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2019 STMicroelectronics. All rights reserved. + * Copyright (c) 2022 STMicroelectronics. All rights reserved. * * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the @@ -19,6 +19,10 @@ @endverbatim +### V1.0.4/18-January-2022 ### +================================ + + Integrate official release v2021.10 + ### V1.0.3/15-September-2021 ### ================================ + Integrate official release v2021.04 diff --git a/system/Middlewares/OpenAMP/virtual_driver/virt_uart.c b/system/Middlewares/OpenAMP/virtual_driver/virt_uart.c index a739be93ee..7d60f29116 100644 --- a/system/Middlewares/OpenAMP/virtual_driver/virt_uart.c +++ b/system/Middlewares/OpenAMP/virtual_driver/virt_uart.c @@ -46,7 +46,13 @@ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* this string will be sent to remote processor */ -#define RPMSG_SERVICE_NAME "rpmsg-tty-channel" +/* Since openSTLinux distribution 4.0 with Linux 5.15, + RPMSG_SERVICE_NAME has been renamed from 'rpmsg-tty-channel' to 'rpmsg-tty' + if older distribution is used, it is required to redefine it to 'rpmsg-tty-channel' +*/ +#ifndef RPMSG_SERVICE_NAME + #define RPMSG_SERVICE_NAME "rpmsg-tty" +#endif /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ diff --git a/variants/STM32MP1xx/MP153AAC_MP153CAC_MP153DAC_MP153FAC_MP157AAC_MP157CAC_MP157DAC_MP157FAC/README.md b/variants/STM32MP1xx/MP153AAC_MP153CAC_MP153DAC_MP153FAC_MP157AAC_MP157CAC_MP157DAC_MP157FAC/README.md index 527340eb20..0c634de6e7 100644 --- a/variants/STM32MP1xx/MP153AAC_MP153CAC_MP153DAC_MP153FAC_MP157AAC_MP157CAC_MP157DAC_MP157FAC/README.md +++ b/variants/STM32MP1xx/MP153AAC_MP153CAC_MP153DAC_MP153FAC_MP157AAC_MP157CAC_MP157DAC_MP157FAC/README.md @@ -109,6 +109,10 @@ To increase the performance of SerialVirtIO you can resize the related buffer co The recommended option is to resize `VRING_NUM_BUFFS`. Be very cautious when resizing `RPMSG_BUFFER_SIZE`, which must be matched with the Linux kernel definition. Also `VIRTIO_BUFFER_SIZE` has the minimum required size depending on the other two. See their links above for further descriptions. +#### Note + +* Since openSTLinux distribution 4.0 with Linux 5.15, `RPMSG_SERVICE_NAME` has been renamed from `rpmsg-tty-channel` to `rpmsg-tty`, if older distribution is used, it is required to redefine it to `rpmsg-tty-channel` + To redefine these definitions, see how to create `build_opt.h` described in Debugging section below. ### Virtual Serial Example