From f09a584d4554787ebbc84d4e1787f862e0c42a5e Mon Sep 17 00:00:00 2001 From: Alexandre Bourdiol Date: Mon, 6 Dec 2021 14:57:26 +0100 Subject: [PATCH] system(WB): update STM32WBxx CMSIS Drivers to v1.10.0 Included in STM32CubeWB FW v1.13.0 Signed-off-by: Alexandre Bourdiol --- .../Device/ST/STM32WBxx/Include/stm32wb10xx.h | 175 ++++++------------ .../Device/ST/STM32WBxx/Include/stm32wb15xx.h | 118 ++++++------ .../Device/ST/STM32WBxx/Include/stm32wb30xx.h | 170 +++++++++-------- .../Device/ST/STM32WBxx/Include/stm32wb35xx.h | 170 +++++++++-------- .../Device/ST/STM32WBxx/Include/stm32wb50xx.h | 170 +++++++++-------- .../Device/ST/STM32WBxx/Include/stm32wb55xx.h | 170 +++++++++-------- .../Device/ST/STM32WBxx/Include/stm32wb5mxx.h | 170 +++++++++-------- .../Device/ST/STM32WBxx/Include/stm32wbxx.h | 7 +- .../ST/STM32WBxx/Include/system_stm32wbxx.h | 5 +- .../CMSIS/Device/ST/STM32WBxx/License.md | 14 +- .../CMSIS/Device/ST/STM32WBxx/README.md | 23 ++- .../Device/ST/STM32WBxx/Release_Notes.html | 47 +++-- .../gcc/linker/stm32wb10xx_flash_cm4.ld | 13 +- .../gcc/linker/stm32wb15xx_flash_cm4.ld | 13 +- .../gcc/linker/stm32wb30xx_flash_cm4.ld | 30 +-- .../gcc/linker/stm32wb35xx_flash_cm4.ld | 30 +-- .../gcc/linker/stm32wb50xx_flash_cm4.ld | 30 +-- .../gcc/linker/stm32wb55xx_flash_cm4.ld | 30 +-- .../gcc/linker/stm32wb5mxx_flash_cm4.ld | 30 +-- .../Templates/gcc/startup_stm32wb10xx_cm4.s | 3 +- .../Templates/gcc/startup_stm32wb15xx_cm4.s | 3 +- .../Templates/gcc/startup_stm32wb30xx_cm4.s | 3 +- .../Templates/gcc/startup_stm32wb35xx_cm4.s | 3 +- .../Templates/gcc/startup_stm32wb50xx_cm4.s | 3 +- .../Templates/gcc/startup_stm32wb55xx_cm4.s | 3 +- .../Templates/gcc/startup_stm32wb5mxx_cm4.s | 3 +- .../Source/Templates/system_stm32wbxx.c | 4 +- .../Device/ST/STM32YYxx_CMSIS_version.md | 2 +- system/STM32WBxx/system_stm32wbxx.c | 4 +- 29 files changed, 651 insertions(+), 795 deletions(-) diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBxx/Include/stm32wb10xx.h b/system/Drivers/CMSIS/Device/ST/STM32WBxx/Include/stm32wb10xx.h index eb159c30a3..2b65345f1d 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32WBxx/Include/stm32wb10xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32WBxx/Include/stm32wb10xx.h @@ -380,7 +380,7 @@ uint32_t RESERVED0[2]; /*!< Reserved, __IO uint32_t CIER; /*!< RCC Clock Interrupt Enable Register, Address offset: 0x18 */ __IO uint32_t CIFR; /*!< RCC Clock Interrupt Flag Register, Address offset: 0x1C */ __IO uint32_t CICR; /*!< RCC Clock Interrupt Clear Register, Address offset: 0x20 */ - __IO uint32_t SMPSCR; /*!< RCC SMPS step-down converter control register, Address offset: 0x24 */ +uint32_t RESERVED11; /*!< Reserved, Address offset: 0x24 */ __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x28 */ __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x2C */ __IO uint32_t AHB3RSTR; /*!< RCC AHB3 & AHB4 peripheral reset register, Address offset: 0x30 */ @@ -413,7 +413,7 @@ uint32_t RESERVED6; /*!< Reserved, __IO uint32_t HSECR; /*!< RCC HSE Clock Register, Address offset: 0x9C */ uint32_t RESERVED7[26]; /*!< Reserved, Address offset: 0xA0-0x104 */ __IO uint32_t EXTCFGR; /*!< RCC Extended Clock Recovery Register, Address offset: 0x108 */ -uint32_t RESERVED8[15]; /*!< Reserved, Address offset: 0x10C-0x144 */ +uint32_t RESERVED8[15]; /*!< Reserved, Address offset: 0x10C-0x144 */ __IO uint32_t C2AHB1ENR; /*!< RRCC AHB1 peripheral CPU2 clocks enable register, Address offset: 0x148 */ __IO uint32_t C2AHB2ENR; /*!< RCC AHB2 peripheral CPU2 clocks enable register, Address offset: 0x14C */ __IO uint32_t C2AHB3ENR; /*!< RCC AHB3 & AHB4 peripheral CPU2 clocks enable register,, Address offset: 0x150 */ @@ -755,10 +755,10 @@ typedef struct /*!< Memory, OTP and Option bytes */ /* Base addresses */ -#define SYSTEM_MEMORY_BASE (0x1FFF0000UL) /*!< System Memory : 28Kb (0x1FFF0000 – 0x1FFF6FFF) */ -#define OTP_AREA_BASE (0x1FFF7000UL) /*!< OTP area : 1kB (0x1FFF7000 – 0x1FFF73FF) */ -#define OPTION_BYTE_BASE (0x1FFF7800UL) /*!< Option Bytes : 128B (0x1FFF7800 – 0x1FFF787F) */ -#define ENGI_BYTE_BASE (0x1FFF7400UL) /*!< Engi Bytes : 3kB (0x1FFF7400 – 0x1FFF7FFF) */ +#define SYSTEM_MEMORY_BASE (0x1FFF0000UL) /*!< System Memory : 28Kb (0x1FFF0000 - 0x1FFF6FFF) */ +#define OTP_AREA_BASE (0x1FFF7000UL) /*!< OTP area : 1kB (0x1FFF7000 - 0x1FFF73FF) */ +#define OPTION_BYTE_BASE (0x1FFF7800UL) /*!< Option Bytes : 128B (0x1FFF7800 - 0x1FFF787F) */ +#define ENGI_BYTE_BASE (0x1FFF7400UL) /*!< Engi Bytes : 3kB (0x1FFF7400 - 0x1FFF7FFF) */ #define SRAM1_BASE SRAM_BASE /*!< SRAM1(up to 12 KB) base address */ #define SRAM2A_BASE (SRAM_BASE + 0x00030000UL)/*!< SRAM2A(32 KB) base address */ @@ -771,14 +771,14 @@ typedef struct #define SRAM2B_SIZE 0x00001000UL /*!< SRAM2b default size : 4 KB */ /* End addresses */ -#define SRAM1_END_ADDR (0x20002FFFUL) /*!< SRAM1 : 12KB (0x20000000 – 0x20002FFF) */ -#define SRAM2A_END_ADDR (0x20037FFFUL) /*!< SRAM2a (backup) : 32KB (0x20030000 – 0x20037FFF) */ -#define SRAM2B_END_ADDR (0x20038FFFUL) /*!< SRAM2b (backup) : 4KB (0x20038000 – 0x20038FFF) */ +#define SRAM1_END_ADDR (0x20002FFFUL) /*!< SRAM1 : 12KB (0x20000000 - 0x20002FFF) */ +#define SRAM2A_END_ADDR (0x20037FFFUL) /*!< SRAM2a (backup) : 32KB (0x20030000 - 0x20037FFF) */ +#define SRAM2B_END_ADDR (0x20038FFFUL) /*!< SRAM2b (backup) : 4KB (0x20038000 - 0x20038FFF) */ -#define SYSTEM_MEMORY_END_ADDR (0x1FFF6FFFUL) /*!< System Memory : 28KB (0x1FFF0000 – 0x1FFF6FFF) */ -#define OTP_AREA_END_ADDR (0x1FFF73FFUL) /*!< OTP area : 1KB (0x1FFF7000 – 0x1FFF73FF) */ -#define OPTION_BYTE_END_ADDR (0x1FFF8FFFUL) /*!< Option Bytes : 4KB (0x1FFF8000 – 0x1FFF8FFF) */ -#define ENGI_BYTE_END_ADDR (0x1FFF7FFFUL) /*!< Engi Bytes : 3kB (0x1FFF7400 – 0x1FFF7FFF) */ +#define SYSTEM_MEMORY_END_ADDR (0x1FFF6FFFUL) /*!< System Memory : 28KB (0x1FFF0000 - 0x1FFF6FFF) */ +#define OTP_AREA_END_ADDR (0x1FFF73FFUL) /*!< OTP area : 1KB (0x1FFF7000 - 0x1FFF73FF) */ +#define OPTION_BYTE_END_ADDR (0x1FFF8FFFUL) /*!< Option Bytes : 4KB (0x1FFF8000 - 0x1FFF8FFF) */ +#define ENGI_BYTE_END_ADDR (0x1FFF7FFFUL) /*!< Engi Bytes : 3kB (0x1FFF7400 - 0x1FFF7FFF) */ /*!< Peripheral memory map */ #define APB1PERIPH_BASE PERIPH_BASE @@ -1086,7 +1086,7 @@ typedef struct #define ADC_CFGR1_ALIGN_Pos (5U) #define ADC_CFGR1_ALIGN_Msk (0x1UL << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */ -#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignement */ +#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignment */ #define ADC_CFGR1_EXTSEL_Pos (6U) #define ADC_CFGR1_EXTSEL_Msk (0x7UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */ @@ -1136,7 +1136,7 @@ typedef struct #define ADC_CFGR1_AWD1CH_3 (0x08UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x20000000 */ #define ADC_CFGR1_AWD1CH_4 (0x10UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x40000000 */ -/* Definitions for cohabitation of ADC peripherals 2.5Ms/sec and 5Ms/sec accross STM32WB serie */ +/* Definitions for cohabitation of ADC peripherals 2.5Ms/sec and 5Ms/sec across STM32WB series */ #define ADC_CFGR_DMAEN_Pos ADC_CFGR1_DMAEN_Pos #define ADC_CFGR_DMAEN_Msk ADC_CFGR1_DMAEN_Msk #define ADC_CFGR_DMAEN ADC_CFGR1_DMAEN @@ -1477,7 +1477,7 @@ typedef struct #define ADC_DR_DATA_14 (0x4000UL << ADC_DR_DATA_Pos) /*!< 0x00004000 */ #define ADC_DR_DATA_15 (0x8000UL << ADC_DR_DATA_Pos) /*!< 0x00008000 */ -/* Definitions for cohabitation of ADC peripherals 2.5Ms/sec and 5Ms/sec accross STM32WB serie */ +/* Definitions for cohabitation of ADC peripherals 2.5Ms/sec and 5Ms/sec across STM32WB series */ #define ADC_DR_RDATA_Pos ADC_DR_DATA_Pos #define ADC_DR_RDATA_Msk ADC_DR_DATA_Msk #define ADC_DR_RDATA ADC_DR_DATA @@ -3040,12 +3040,12 @@ typedef struct /* Arithmetic addition output data */ #define PKA_ARITHMETIC_ADD_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ -/* Arithmetic substraction input data */ +/* Arithmetic subtraction input data */ #define PKA_ARITHMETIC_SUB_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ #define PKA_ARITHMETIC_SUB_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ #define PKA_ARITHMETIC_SUB_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ -/* Arithmetic substraction output data */ +/* Arithmetic subtraction output data */ #define PKA_ARITHMETIC_SUB_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ /* Arithmetic multiplication input data */ @@ -3081,13 +3081,13 @@ typedef struct /* Modular inversion output data */ #define PKA_MODULAR_INV_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ -/* Modular substraction input data */ +/* Modular subtraction input data */ #define PKA_MODULAR_SUB_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ #define PKA_MODULAR_SUB_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ #define PKA_MODULAR_SUB_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ #define PKA_MODULAR_SUB_IN_OP3_MOD ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 */ -/* Modular substraction output data */ +/* Modular subtraction output data */ #define PKA_MODULAR_SUB_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ /* Montgomery multiplication input data */ @@ -5498,13 +5498,6 @@ typedef struct #define PWR_SR1_WUFI PWR_SR1_WUFI_Msk /*!< Internal wakeup interrupt flag */ /******************** Bit definition for PWR_SR2 register ********************/ -#define PWR_SR2_SMPSBF_Pos (0U) -#define PWR_SR2_SMPSBF_Msk (0x1UL << PWR_SR2_SMPSBF_Pos) /*!< 0x00000001 */ -#define PWR_SR2_SMPSBF PWR_SR2_SMPSBF_Msk /*!< SMPS step down converter in operating mode bypass flag */ -#define PWR_SR2_SMPSF_Pos (1U) -#define PWR_SR2_SMPSF_Msk (0x1UL << PWR_SR2_SMPSF_Pos) /*!< 0x00000002 */ -#define PWR_SR2_SMPSF PWR_SR2_SMPSF_Msk /*!< SMPS step down converter in operating mode step down flag */ - #define PWR_SR2_REGLPS_Pos (8U) #define PWR_SR2_REGLPS_Msk (0x1UL << PWR_SR2_REGLPS_Pos) /*!< 0x00000100 */ #define PWR_SR2_REGLPS PWR_SR2_REGLPS_Msk /*!< Low-power regulator started */ @@ -5531,10 +5524,6 @@ typedef struct #define PWR_SCR_CWUF4_Msk (0x1UL << PWR_SCR_CWUF4_Pos) /*!< 0x00000008 */ #define PWR_SCR_CWUF4 PWR_SCR_CWUF4_Msk /*!< Clear Wake-up Pin 4 [Flag 3] */ -#define PWR_SCR_CSMPSFBF_Pos (7U) -#define PWR_SCR_CSMPSFBF_Msk (0x1UL << PWR_SCR_CSMPSFBF_Pos) /*!< 0x00000080 */ -#define PWR_SCR_CSMPSFBF PWR_SCR_CSMPSFBF_Msk /*!< Clear SMPS Step Down converter forced in bypass mode interrupt flag */ - #define PWR_SCR_CBORHF_Pos (8U) #define PWR_SCR_CBORHF_Msk (0x1UL << PWR_SCR_CBORHF_Pos) /*!< 0x00000100 */ #define PWR_SCR_CBORHF PWR_SCR_CBORHF_Msk /*!< Clear BORH interrupt flag */ @@ -5554,30 +5543,6 @@ typedef struct #define PWR_SCR_CC2HF_Msk (0x1UL << PWR_SCR_CC2HF_Pos) /*!< 0x00004000 */ #define PWR_SCR_CC2HF PWR_SCR_CC2HF_Msk /*!< Clear CPU2 Hold interrupt flag */ -/******************** Bit definition for PWR_CR5 register ********************/ -#define PWR_CR5_SMPSVOS_Pos (0U) -#define PWR_CR5_SMPSVOS_Msk (0xFUL << PWR_CR5_SMPSVOS_Pos) /*!< 0x0000000F */ -#define PWR_CR5_SMPSVOS PWR_CR5_SMPSVOS_Msk /*!< SMPS step down converter voltage output scaling voltage level */ -#define PWR_CR5_SMPSVOS_0 (0x01U << PWR_CR5_SMPSVOS_Pos) /*!< 0x00000001 */ -#define PWR_CR5_SMPSVOS_1 (0x02U << PWR_CR5_SMPSVOS_Pos) /*!< 0x00000002 */ -#define PWR_CR5_SMPSVOS_2 (0x04U << PWR_CR5_SMPSVOS_Pos) /*!< 0x00000004 */ -#define PWR_CR5_SMPSVOS_3 (0x08U << PWR_CR5_SMPSVOS_Pos) /*!< 0x00000008 */ - -#define PWR_CR5_SMPSSC_Pos (4U) -#define PWR_CR5_SMPSSC_Msk (0x7UL << PWR_CR5_SMPSSC_Pos) /*!< 0x00000070 */ -#define PWR_CR5_SMPSSC PWR_CR5_SMPSSC_Msk /*!< SMPS step down converter supply startup current selection */ -#define PWR_CR5_SMPSSC_0 (0x01U << PWR_CR5_SMPSSC_Pos) /*!< 0x00000010 */ -#define PWR_CR5_SMPSSC_1 (0x02U << PWR_CR5_SMPSSC_Pos) /*!< 0x00000020 */ -#define PWR_CR5_SMPSSC_2 (0x04U << PWR_CR5_SMPSSC_Pos) /*!< 0x00000040 */ - -#define PWR_CR5_BORHC_Pos (8U) -#define PWR_CR5_BORHC_Msk (0x1UL << PWR_CR5_BORHC_Pos) /*!< 0x00000100 */ -#define PWR_CR5_BORHC PWR_CR5_BORHC_Msk /*!< BORH configuration selection */ - -#define PWR_CR5_SMPSEN_Pos (15U) -#define PWR_CR5_SMPSEN_Msk (0x1UL << PWR_CR5_SMPSEN_Pos) /*!< 0x00008000 */ -#define PWR_CR5_SMPSEN PWR_CR5_SMPSEN_Msk /*!< Enable SMPS Step Down converter SMPS mode enable */ - /******************** Bit definition for PWR_PUCRA register *****************/ #define PWR_PUCRA_PA0_Pos (0U) #define PWR_PUCRA_PA0_Msk (0x1UL << PWR_PUCRA_PA0_Pos) /*!< 0x00000001 */ @@ -5852,7 +5817,6 @@ typedef struct /* * @brief Specific device feature definitions */ -#define RCC_SMPS_SUPPORT /******************** Bit definition for RCC_CR register *****************/ #define RCC_CR_MSION_Pos (0U) @@ -6189,25 +6153,6 @@ typedef struct #define RCC_CICR_LSI2RDYC_Msk (0x1UL << RCC_CICR_LSI2RDYC_Pos) /*!< 0x00000800 */ #define RCC_CICR_LSI2RDYC RCC_CICR_LSI2RDYC_Msk -/******************** Bit definition for RCC_SMPSCR register ******************/ -#define RCC_SMPSCR_SMPSSEL_Pos (0U) -#define RCC_SMPSCR_SMPSSEL_Msk (0x3UL << RCC_SMPSCR_SMPSSEL_Pos) /*!< 0x00000003 */ -#define RCC_SMPSCR_SMPSSEL RCC_SMPSCR_SMPSSEL_Msk -#define RCC_SMPSCR_SMPSSEL_0 (0x1U << RCC_SMPSCR_SMPSSEL_Pos) /*!< 0x00000001 */ -#define RCC_SMPSCR_SMPSSEL_1 (0x2U << RCC_SMPSCR_SMPSSEL_Pos) /*!< 0x00000002 */ - -#define RCC_SMPSCR_SMPSDIV_Pos (4U) -#define RCC_SMPSCR_SMPSDIV_Msk (0x3UL << RCC_SMPSCR_SMPSDIV_Pos) /*!< 0x00000030 */ -#define RCC_SMPSCR_SMPSDIV RCC_SMPSCR_SMPSDIV_Msk -#define RCC_SMPSCR_SMPSDIV_0 (0x1U << RCC_SMPSCR_SMPSDIV_Pos) /*!< 0x00000010 */ -#define RCC_SMPSCR_SMPSDIV_1 (0x2U << RCC_SMPSCR_SMPSDIV_Pos) /*!< 0x00000020 */ - -#define RCC_SMPSCR_SMPSSWS_Pos (8U) -#define RCC_SMPSCR_SMPSSWS_Msk (0x3UL << RCC_SMPSCR_SMPSSWS_Pos) /*!< 0x00000300 */ -#define RCC_SMPSCR_SMPSSWS RCC_SMPSCR_SMPSSWS_Msk -#define RCC_SMPSCR_SMPSSWS_0 (0x1U << RCC_SMPSCR_SMPSSWS_Pos) /*!< 0x00000100 */ -#define RCC_SMPSCR_SMPSSWS_1 (0x2U << RCC_SMPSCR_SMPSSWS_Pos) /*!< 0x00000200 */ - /******************** Bit definition for RCC_AHB1RSTR register **************/ #define RCC_AHB1RSTR_DMA1RST_Pos (0U) #define RCC_AHB1RSTR_DMA1RST_Msk (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos) /*!< 0x00000001 */ @@ -7009,10 +6954,10 @@ typedef struct #define RTC_CR_OSEL_1 (0x2U << RTC_CR_OSEL_Pos) /*!< 0x00400000 */ #define RTC_CR_POL_Pos (20U) #define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */ -#define RTC_CR_POL RTC_CR_POL_Msk /*!< Ouput polarity */ +#define RTC_CR_POL RTC_CR_POL_Msk /*!< Output polarity */ #define RTC_CR_COSEL_Pos (19U) #define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ -#define RTC_CR_COSEL RTC_CR_COSEL_Msk /*!< Calibration ouput selection */ +#define RTC_CR_COSEL RTC_CR_COSEL_Msk /*!< Calibration output selection */ #define RTC_CR_BKP_Pos (18U) #define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */ #define RTC_CR_BKP RTC_CR_BKP_Msk /*!< Backup */ @@ -7281,7 +7226,7 @@ typedef struct /******************** Bits definition for RTC_SHIFTR register ***************/ #define RTC_SHIFTR_SUBFS_Pos (0U) #define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */ -#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk /*!< Substract a fraction of a second */ +#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk /*!< Subtract a fraction of a second */ #define RTC_SHIFTR_ADD1S_Pos (31U) #define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */ #define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk /*!< Add on second */ @@ -8427,100 +8372,100 @@ typedef struct /***************** Bit definition for SYSCFG_SWPR1 register (SYSCFG SRAM2A write protection register) *********************************************************/ #define SYSCFG_SWPR1_PAGE0_Pos (0U) #define SYSCFG_SWPR1_PAGE0_Msk (0x1UL << SYSCFG_SWPR1_PAGE0_Pos) /*!< 0x00000001 */ -#define SYSCFG_SWPR1_PAGE0 SYSCFG_SWPR1_PAGE0_Msk /*!< SRAM2A Write protection page 0 (0x20030000 – 0x200303FF) */ +#define SYSCFG_SWPR1_PAGE0 SYSCFG_SWPR1_PAGE0_Msk /*!< SRAM2A Write protection page 0 (0x20030000 - 0x200303FF) */ #define SYSCFG_SWPR1_PAGE1_Pos (1U) #define SYSCFG_SWPR1_PAGE1_Msk (0x1UL << SYSCFG_SWPR1_PAGE1_Pos) /*!< 0x00000002 */ -#define SYSCFG_SWPR1_PAGE1 SYSCFG_SWPR1_PAGE1_Msk /*!< SRAM2A Write protection page 1 (0x20030400 – 0x200307FF) */ +#define SYSCFG_SWPR1_PAGE1 SYSCFG_SWPR1_PAGE1_Msk /*!< SRAM2A Write protection page 1 (0x20030400 - 0x200307FF) */ #define SYSCFG_SWPR1_PAGE2_Pos (2U) #define SYSCFG_SWPR1_PAGE2_Msk (0x1UL << SYSCFG_SWPR1_PAGE2_Pos) /*!< 0x00000004 */ -#define SYSCFG_SWPR1_PAGE2 SYSCFG_SWPR1_PAGE2_Msk /*!< SRAM2A Write protection page 2 (0x20030800 – 0x20030BFF) */ +#define SYSCFG_SWPR1_PAGE2 SYSCFG_SWPR1_PAGE2_Msk /*!< SRAM2A Write protection page 2 (0x20030800 - 0x20030BFF) */ #define SYSCFG_SWPR1_PAGE3_Pos (3U) #define SYSCFG_SWPR1_PAGE3_Msk (0x1UL << SYSCFG_SWPR1_PAGE3_Pos) /*!< 0x00000008 */ -#define SYSCFG_SWPR1_PAGE3 SYSCFG_SWPR1_PAGE3_Msk /*!< SRAM2A Write protection page 3 (0x20030C00 – 0x20030FFF) */ +#define SYSCFG_SWPR1_PAGE3 SYSCFG_SWPR1_PAGE3_Msk /*!< SRAM2A Write protection page 3 (0x20030C00 - 0x20030FFF) */ #define SYSCFG_SWPR1_PAGE4_Pos (4U) #define SYSCFG_SWPR1_PAGE4_Msk (0x1UL << SYSCFG_SWPR1_PAGE4_Pos) /*!< 0x00000010 */ -#define SYSCFG_SWPR1_PAGE4 SYSCFG_SWPR1_PAGE4_Msk /*!< SRAM2A Write protection page 4 (0x20031000 – 0x200313FF) */ +#define SYSCFG_SWPR1_PAGE4 SYSCFG_SWPR1_PAGE4_Msk /*!< SRAM2A Write protection page 4 (0x20031000 - 0x200313FF) */ #define SYSCFG_SWPR1_PAGE5_Pos (5U) #define SYSCFG_SWPR1_PAGE5_Msk (0x1UL << SYSCFG_SWPR1_PAGE5_Pos) /*!< 0x00000020 */ -#define SYSCFG_SWPR1_PAGE5 SYSCFG_SWPR1_PAGE5_Msk /*!< SRAM2A Write protection page 5 (0x20031400 – 0x200317FF) */ +#define SYSCFG_SWPR1_PAGE5 SYSCFG_SWPR1_PAGE5_Msk /*!< SRAM2A Write protection page 5 (0x20031400 - 0x200317FF) */ #define SYSCFG_SWPR1_PAGE6_Pos (6U) #define SYSCFG_SWPR1_PAGE6_Msk (0x1UL << SYSCFG_SWPR1_PAGE6_Pos) /*!< 0x00000040 */ -#define SYSCFG_SWPR1_PAGE6 SYSCFG_SWPR1_PAGE6_Msk /*!< SRAM2A Write protection page 6 (0x20031800 – 0x20031BFF) */ +#define SYSCFG_SWPR1_PAGE6 SYSCFG_SWPR1_PAGE6_Msk /*!< SRAM2A Write protection page 6 (0x20031800 - 0x20031BFF) */ #define SYSCFG_SWPR1_PAGE7_Pos (7U) #define SYSCFG_SWPR1_PAGE7_Msk (0x1UL << SYSCFG_SWPR1_PAGE7_Pos) /*!< 0x00000080 */ -#define SYSCFG_SWPR1_PAGE7 SYSCFG_SWPR1_PAGE7_Msk /*!< SRAM2A Write protection page 7 (0x20031C00 – 0x20031FFF) */ +#define SYSCFG_SWPR1_PAGE7 SYSCFG_SWPR1_PAGE7_Msk /*!< SRAM2A Write protection page 7 (0x20031C00 - 0x20031FFF) */ #define SYSCFG_SWPR1_PAGE8_Pos (8U) #define SYSCFG_SWPR1_PAGE8_Msk (0x1UL << SYSCFG_SWPR1_PAGE8_Pos) /*!< 0x00000100 */ -#define SYSCFG_SWPR1_PAGE8 SYSCFG_SWPR1_PAGE8_Msk /*!< SRAM2A Write protection page 8 (0x20032000 – 0x200323FF) */ +#define SYSCFG_SWPR1_PAGE8 SYSCFG_SWPR1_PAGE8_Msk /*!< SRAM2A Write protection page 8 (0x20032000 - 0x200323FF) */ #define SYSCFG_SWPR1_PAGE9_Pos (9U) #define SYSCFG_SWPR1_PAGE9_Msk (0x1UL << SYSCFG_SWPR1_PAGE9_Pos) /*!< 0x00000200 */ -#define SYSCFG_SWPR1_PAGE9 SYSCFG_SWPR1_PAGE9_Msk /*!< SRAM2A Write protection page 9 (0x20032400 – 0x200327FF) */ +#define SYSCFG_SWPR1_PAGE9 SYSCFG_SWPR1_PAGE9_Msk /*!< SRAM2A Write protection page 9 (0x20032400 - 0x200327FF) */ #define SYSCFG_SWPR1_PAGE10_Pos (10U) #define SYSCFG_SWPR1_PAGE10_Msk (0x1UL << SYSCFG_SWPR1_PAGE10_Pos) /*!< 0x00000400 */ -#define SYSCFG_SWPR1_PAGE10 SYSCFG_SWPR1_PAGE10_Msk /*!< SRAM2A Write protection page 10 (0x20032800 – 0x20032BFF) */ +#define SYSCFG_SWPR1_PAGE10 SYSCFG_SWPR1_PAGE10_Msk /*!< SRAM2A Write protection page 10 (0x20032800 - 0x20032BFF) */ #define SYSCFG_SWPR1_PAGE11_Pos (11U) #define SYSCFG_SWPR1_PAGE11_Msk (0x1UL << SYSCFG_SWPR1_PAGE11_Pos) /*!< 0x00000800 */ -#define SYSCFG_SWPR1_PAGE11 SYSCFG_SWPR1_PAGE11_Msk /*!< SRAM2A Write protection page 11 (0x20032C00 – 0x20032FFF) */ +#define SYSCFG_SWPR1_PAGE11 SYSCFG_SWPR1_PAGE11_Msk /*!< SRAM2A Write protection page 11 (0x20032C00 - 0x20032FFF) */ #define SYSCFG_SWPR1_PAGE12_Pos (12U) #define SYSCFG_SWPR1_PAGE12_Msk (0x1UL << SYSCFG_SWPR1_PAGE12_Pos) /*!< 0x00001000 */ -#define SYSCFG_SWPR1_PAGE12 SYSCFG_SWPR1_PAGE12_Msk /*!< SRAM2A Write protection page 12 (0x20033000 – 0x200333FF) */ +#define SYSCFG_SWPR1_PAGE12 SYSCFG_SWPR1_PAGE12_Msk /*!< SRAM2A Write protection page 12 (0x20033000 - 0x200333FF) */ #define SYSCFG_SWPR1_PAGE13_Pos (13U) #define SYSCFG_SWPR1_PAGE13_Msk (0x1UL << SYSCFG_SWPR1_PAGE13_Pos) /*!< 0x00002000 */ -#define SYSCFG_SWPR1_PAGE13 SYSCFG_SWPR1_PAGE13_Msk /*!< SRAM2A Write protection page 13 (0x20033400 – 0x200337FF) */ +#define SYSCFG_SWPR1_PAGE13 SYSCFG_SWPR1_PAGE13_Msk /*!< SRAM2A Write protection page 13 (0x20033400 - 0x200337FF) */ #define SYSCFG_SWPR1_PAGE14_Pos (14U) #define SYSCFG_SWPR1_PAGE14_Msk (0x1UL << SYSCFG_SWPR1_PAGE14_Pos) /*!< 0x00004000 */ -#define SYSCFG_SWPR1_PAGE14 SYSCFG_SWPR1_PAGE14_Msk /*!< SRAM2A Write protection page 14 (0x20033800 – 0x20033BFF) */ +#define SYSCFG_SWPR1_PAGE14 SYSCFG_SWPR1_PAGE14_Msk /*!< SRAM2A Write protection page 14 (0x20033800 - 0x20033BFF) */ #define SYSCFG_SWPR1_PAGE15_Pos (15U) #define SYSCFG_SWPR1_PAGE15_Msk (0x1UL << SYSCFG_SWPR1_PAGE15_Pos) /*!< 0x00008000 */ -#define SYSCFG_SWPR1_PAGE15 SYSCFG_SWPR1_PAGE15_Msk /*!< SRAM2A Write protection page 15 (0x20033C00 – 0x20033FFF) */ +#define SYSCFG_SWPR1_PAGE15 SYSCFG_SWPR1_PAGE15_Msk /*!< SRAM2A Write protection page 15 (0x20033C00 - 0x20033FFF) */ #define SYSCFG_SWPR1_PAGE16_Pos (16U) #define SYSCFG_SWPR1_PAGE16_Msk (0x1UL << SYSCFG_SWPR1_PAGE16_Pos) /*!< 0x00010000 */ -#define SYSCFG_SWPR1_PAGE16 SYSCFG_SWPR1_PAGE16_Msk /*!< SRAM2A Write protection page 16 (0x20034000 – 0x200343FF) */ +#define SYSCFG_SWPR1_PAGE16 SYSCFG_SWPR1_PAGE16_Msk /*!< SRAM2A Write protection page 16 (0x20034000 - 0x200343FF) */ #define SYSCFG_SWPR1_PAGE17_Pos (17U) #define SYSCFG_SWPR1_PAGE17_Msk (0x1UL << SYSCFG_SWPR1_PAGE17_Pos) /*!< 0x00020000 */ -#define SYSCFG_SWPR1_PAGE17 SYSCFG_SWPR1_PAGE17_Msk /*!< SRAM2A Write protection page 17 (0x20034400 – 0x200347FF) */ +#define SYSCFG_SWPR1_PAGE17 SYSCFG_SWPR1_PAGE17_Msk /*!< SRAM2A Write protection page 17 (0x20034400 - 0x200347FF) */ #define SYSCFG_SWPR1_PAGE18_Pos (18U) #define SYSCFG_SWPR1_PAGE18_Msk (0x1UL << SYSCFG_SWPR1_PAGE18_Pos) /*!< 0x00040000 */ -#define SYSCFG_SWPR1_PAGE18 SYSCFG_SWPR1_PAGE18_Msk /*!< SRAM2A Write protection page 18 (0x20034800 – 0x20034BFF) */ +#define SYSCFG_SWPR1_PAGE18 SYSCFG_SWPR1_PAGE18_Msk /*!< SRAM2A Write protection page 18 (0x20034800 - 0x20034BFF) */ #define SYSCFG_SWPR1_PAGE19_Pos (19U) #define SYSCFG_SWPR1_PAGE19_Msk (0x1UL << SYSCFG_SWPR1_PAGE19_Pos) /*!< 0x00080000 */ -#define SYSCFG_SWPR1_PAGE19 SYSCFG_SWPR1_PAGE19_Msk /*!< SRAM2A Write protection page 19 (0x20034C00 – 0x20034FFF) */ +#define SYSCFG_SWPR1_PAGE19 SYSCFG_SWPR1_PAGE19_Msk /*!< SRAM2A Write protection page 19 (0x20034C00 - 0x20034FFF) */ #define SYSCFG_SWPR1_PAGE20_Pos (20U) #define SYSCFG_SWPR1_PAGE20_Msk (0x1UL << SYSCFG_SWPR1_PAGE20_Pos) /*!< 0x00100000 */ -#define SYSCFG_SWPR1_PAGE20 SYSCFG_SWPR1_PAGE20_Msk /*!< SRAM2A Write protection page 20 (0x20035000 – 0x200353FF) */ +#define SYSCFG_SWPR1_PAGE20 SYSCFG_SWPR1_PAGE20_Msk /*!< SRAM2A Write protection page 20 (0x20035000 - 0x200353FF) */ #define SYSCFG_SWPR1_PAGE21_Pos (21U) #define SYSCFG_SWPR1_PAGE21_Msk (0x1UL << SYSCFG_SWPR1_PAGE21_Pos) /*!< 0x00200000 */ -#define SYSCFG_SWPR1_PAGE21 SYSCFG_SWPR1_PAGE21_Msk /*!< SRAM2A Write protection page 21 (0x20035400 – 0x200357FF) */ +#define SYSCFG_SWPR1_PAGE21 SYSCFG_SWPR1_PAGE21_Msk /*!< SRAM2A Write protection page 21 (0x20035400 - 0x200357FF) */ #define SYSCFG_SWPR1_PAGE22_Pos (22U) #define SYSCFG_SWPR1_PAGE22_Msk (0x1UL << SYSCFG_SWPR1_PAGE22_Pos) /*!< 0x00400000 */ -#define SYSCFG_SWPR1_PAGE22 SYSCFG_SWPR1_PAGE22_Msk /*!< SRAM2A Write protection page 22 (0x20035800 – 0x20035BFF) */ +#define SYSCFG_SWPR1_PAGE22 SYSCFG_SWPR1_PAGE22_Msk /*!< SRAM2A Write protection page 22 (0x20035800 - 0x20035BFF) */ #define SYSCFG_SWPR1_PAGE23_Pos (23U) #define SYSCFG_SWPR1_PAGE23_Msk (0x1UL << SYSCFG_SWPR1_PAGE23_Pos) /*!< 0x00800000 */ -#define SYSCFG_SWPR1_PAGE23 SYSCFG_SWPR1_PAGE23_Msk /*!< SRAM2A Write protection page 23 (0x20035C00 – 0x20035FFF) */ +#define SYSCFG_SWPR1_PAGE23 SYSCFG_SWPR1_PAGE23_Msk /*!< SRAM2A Write protection page 23 (0x20035C00 - 0x20035FFF) */ #define SYSCFG_SWPR1_PAGE24_Pos (24U) #define SYSCFG_SWPR1_PAGE24_Msk (0x1UL << SYSCFG_SWPR1_PAGE24_Pos) /*!< 0x01000000 */ -#define SYSCFG_SWPR1_PAGE24 SYSCFG_SWPR1_PAGE24_Msk /*!< SRAM2A Write protection page 24 (0x20036000 – 0x200363FF) */ +#define SYSCFG_SWPR1_PAGE24 SYSCFG_SWPR1_PAGE24_Msk /*!< SRAM2A Write protection page 24 (0x20036000 - 0x200363FF) */ #define SYSCFG_SWPR1_PAGE25_Pos (25U) #define SYSCFG_SWPR1_PAGE25_Msk (0x1UL << SYSCFG_SWPR1_PAGE25_Pos) /*!< 0x02000000 */ -#define SYSCFG_SWPR1_PAGE25 SYSCFG_SWPR1_PAGE25_Msk /*!< SRAM2A Write protection page 25 (0x20036400 – 0x200367FF) */ +#define SYSCFG_SWPR1_PAGE25 SYSCFG_SWPR1_PAGE25_Msk /*!< SRAM2A Write protection page 25 (0x20036400 - 0x200367FF) */ #define SYSCFG_SWPR1_PAGE26_Pos (26U) #define SYSCFG_SWPR1_PAGE26_Msk (0x1UL << SYSCFG_SWPR1_PAGE26_Pos) /*!< 0x04000000 */ -#define SYSCFG_SWPR1_PAGE26 SYSCFG_SWPR1_PAGE26_Msk /*!< SRAM2A Write protection page 26 (0x20036800 – 0x20036BFF) */ +#define SYSCFG_SWPR1_PAGE26 SYSCFG_SWPR1_PAGE26_Msk /*!< SRAM2A Write protection page 26 (0x20036800 - 0x20036BFF) */ #define SYSCFG_SWPR1_PAGE27_Pos (27U) #define SYSCFG_SWPR1_PAGE27_Msk (0x1UL << SYSCFG_SWPR1_PAGE27_Pos) /*!< 0x08000000 */ -#define SYSCFG_SWPR1_PAGE27 SYSCFG_SWPR1_PAGE27_Msk /*!< SRAM2A Write protection page 27 (0x20036C00 – 0x20036FFF) */ +#define SYSCFG_SWPR1_PAGE27 SYSCFG_SWPR1_PAGE27_Msk /*!< SRAM2A Write protection page 27 (0x20036C00 - 0x20036FFF) */ #define SYSCFG_SWPR1_PAGE28_Pos (28U) #define SYSCFG_SWPR1_PAGE28_Msk (0x1UL << SYSCFG_SWPR1_PAGE28_Pos) /*!< 0x10000000 */ -#define SYSCFG_SWPR1_PAGE28 SYSCFG_SWPR1_PAGE28_Msk /*!< SRAM2A Write protection page 28 (0x20037000 – 0x200373FF) */ +#define SYSCFG_SWPR1_PAGE28 SYSCFG_SWPR1_PAGE28_Msk /*!< SRAM2A Write protection page 28 (0x20037000 - 0x200373FF) */ #define SYSCFG_SWPR1_PAGE29_Pos (29U) #define SYSCFG_SWPR1_PAGE29_Msk (0x1UL << SYSCFG_SWPR1_PAGE29_Pos) /*!< 0x20000000 */ -#define SYSCFG_SWPR1_PAGE29 SYSCFG_SWPR1_PAGE29_Msk /*!< SRAM2A Write protection page 29 (0x20037400 – 0x200377FF) */ +#define SYSCFG_SWPR1_PAGE29 SYSCFG_SWPR1_PAGE29_Msk /*!< SRAM2A Write protection page 29 (0x20037400 - 0x200377FF) */ #define SYSCFG_SWPR1_PAGE30_Pos (30U) #define SYSCFG_SWPR1_PAGE30_Msk (0x1UL << SYSCFG_SWPR1_PAGE30_Pos) /*!< 0x40000000 */ -#define SYSCFG_SWPR1_PAGE30 SYSCFG_SWPR1_PAGE30_Msk /*!< SRAM2A Write protection page 30 (0x20037800 – 0x20037BFF) */ +#define SYSCFG_SWPR1_PAGE30 SYSCFG_SWPR1_PAGE30_Msk /*!< SRAM2A Write protection page 30 (0x20037800 - 0x20037BFF) */ #define SYSCFG_SWPR1_PAGE31_Pos (31U) #define SYSCFG_SWPR1_PAGE31_Msk (0x1UL << SYSCFG_SWPR1_PAGE31_Pos) /*!< 0x80000000 */ -#define SYSCFG_SWPR1_PAGE31 SYSCFG_SWPR1_PAGE31_Msk /*!< SRAM2A Write protection page 31 (0x20037C00 – 0x20037FFF) */ +#define SYSCFG_SWPR1_PAGE31 SYSCFG_SWPR1_PAGE31_Msk /*!< SRAM2A Write protection page 31 (0x20037C00 - 0x20037FFF) */ /***************** Bit definition for SYSCFG_SKR register (SYSCFG SRAM2 key register) *************************************************************************/ #define SYSCFG_SKR_KEY_Pos (0U) @@ -8530,16 +8475,16 @@ typedef struct /***************** Bit definition for SYSCFG_SWPR2 register (SYSCFG SRAM2 write protection register) **********************************************************/ #define SYSCFG_SWPR2_PAGE32_Pos (0U) #define SYSCFG_SWPR2_PAGE32_Msk (0x1UL << SYSCFG_SWPR2_PAGE32_Pos) /*!< 0x00000001 */ -#define SYSCFG_SWPR2_PAGE32 SYSCFG_SWPR2_PAGE32_Msk /*!< SRAM2B Write protection page 0 (0x20038000 – 0x200383FF) */ +#define SYSCFG_SWPR2_PAGE32 SYSCFG_SWPR2_PAGE32_Msk /*!< SRAM2B Write protection page 0 (0x20038000 - 0x200383FF) */ #define SYSCFG_SWPR2_PAGE33_Pos (1U) #define SYSCFG_SWPR2_PAGE33_Msk (0x1UL << SYSCFG_SWPR2_PAGE33_Pos) /*!< 0x00000002 */ -#define SYSCFG_SWPR2_PAGE33 SYSCFG_SWPR2_PAGE33_Msk /*!< SRAM2B Write protection page 1 (0x20038400 – 0x200387FF) */ +#define SYSCFG_SWPR2_PAGE33 SYSCFG_SWPR2_PAGE33_Msk /*!< SRAM2B Write protection page 1 (0x20038400 - 0x200387FF) */ #define SYSCFG_SWPR2_PAGE34_Pos (2U) #define SYSCFG_SWPR2_PAGE34_Msk (0x1UL << SYSCFG_SWPR2_PAGE34_Pos) /*!< 0x00000004 */ -#define SYSCFG_SWPR2_PAGE34 SYSCFG_SWPR2_PAGE34_Msk /*!< SRAM2B Write protection page 2 (0x20038800 – 0x20038bFF) */ +#define SYSCFG_SWPR2_PAGE34 SYSCFG_SWPR2_PAGE34_Msk /*!< SRAM2B Write protection page 2 (0x20038800 - 0x20038bFF) */ #define SYSCFG_SWPR2_PAGE35_Pos (3U) #define SYSCFG_SWPR2_PAGE35_Msk (0x1UL << SYSCFG_SWPR2_PAGE35_Pos) /*!< 0x00000008 */ -#define SYSCFG_SWPR2_PAGE35 SYSCFG_SWPR2_PAGE35_Msk /*!< SRAM2B Write protection page 3 (0x20038C00 – 0x20038FFF) */ +#define SYSCFG_SWPR2_PAGE35 SYSCFG_SWPR2_PAGE35_Msk /*!< SRAM2B Write protection page 3 (0x20038C00 - 0x20038FFF) */ /***************** Bit definition for SYSCFG_IMR1 register (Interrupt masks control and status register on CPU1 - part 1) *******************************************/ #define SYSCFG_IMR1_TIM1IM_Pos (13U) @@ -10864,5 +10809,3 @@ typedef struct /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBxx/Include/stm32wb15xx.h b/system/Drivers/CMSIS/Device/ST/STM32WBxx/Include/stm32wb15xx.h index effa71885a..c0cdd0bf0e 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32WBxx/Include/stm32wb15xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32WBxx/Include/stm32wb15xx.h @@ -423,7 +423,7 @@ uint32_t RESERVED6; /*!< Reserved, __IO uint32_t HSECR; /*!< RCC HSE Clock Register, Address offset: 0x9C */ uint32_t RESERVED7[26]; /*!< Reserved, Address offset: 0xA0-0x104 */ __IO uint32_t EXTCFGR; /*!< RCC Extended Clock Recovery Register, Address offset: 0x108 */ -uint32_t RESERVED8[15]; /*!< Reserved, Address offset: 0x10C-0x144 */ +uint32_t RESERVED8[15]; /*!< Reserved, Address offset: 0x10C-0x144 */ __IO uint32_t C2AHB1ENR; /*!< RRCC AHB1 peripheral CPU2 clocks enable register, Address offset: 0x148 */ __IO uint32_t C2AHB2ENR; /*!< RCC AHB2 peripheral CPU2 clocks enable register, Address offset: 0x14C */ __IO uint32_t C2AHB3ENR; /*!< RCC AHB3 & AHB4 peripheral CPU2 clocks enable register,, Address offset: 0x150 */ @@ -765,10 +765,10 @@ typedef struct /*!< Memory, OTP and Option bytes */ /* Base addresses */ -#define SYSTEM_MEMORY_BASE (0x1FFF0000UL) /*!< System Memory : 28Kb (0x1FFF0000 – 0x1FFF6FFF) */ -#define OTP_AREA_BASE (0x1FFF7000UL) /*!< OTP area : 1kB (0x1FFF7000 – 0x1FFF73FF) */ -#define OPTION_BYTE_BASE (0x1FFF7800UL) /*!< Option Bytes : 128B (0x1FFF7800 – 0x1FFF787F) */ -#define ENGI_BYTE_BASE (0x1FFF7400UL) /*!< Engi Bytes : 3kB (0x1FFF7400 – 0x1FFF7FFF) */ +#define SYSTEM_MEMORY_BASE (0x1FFF0000UL) /*!< System Memory : 28Kb (0x1FFF0000 - 0x1FFF6FFF) */ +#define OTP_AREA_BASE (0x1FFF7000UL) /*!< OTP area : 1kB (0x1FFF7000 - 0x1FFF73FF) */ +#define OPTION_BYTE_BASE (0x1FFF7800UL) /*!< Option Bytes : 128B (0x1FFF7800 - 0x1FFF787F) */ +#define ENGI_BYTE_BASE (0x1FFF7400UL) /*!< Engi Bytes : 3kB (0x1FFF7400 - 0x1FFF7FFF) */ #define SRAM1_BASE SRAM_BASE /*!< SRAM1(up to 12 KB) base address */ #define SRAM2A_BASE (SRAM_BASE + 0x00030000UL)/*!< SRAM2A(32 KB) base address */ @@ -781,14 +781,14 @@ typedef struct #define SRAM2B_SIZE 0x00001000UL /*!< SRAM2b default size : 4 KB */ /* End addresses */ -#define SRAM1_END_ADDR (0x20002FFFUL) /*!< SRAM1 : 12KB (0x20000000 – 0x20002FFF) */ -#define SRAM2A_END_ADDR (0x20037FFFUL) /*!< SRAM2a (backup) : 32KB (0x20030000 – 0x20037FFF) */ -#define SRAM2B_END_ADDR (0x20038FFFUL) /*!< SRAM2b (backup) : 4KB (0x20038000 – 0x20038FFF) */ +#define SRAM1_END_ADDR (0x20002FFFUL) /*!< SRAM1 : 12KB (0x20000000 - 0x20002FFF) */ +#define SRAM2A_END_ADDR (0x20037FFFUL) /*!< SRAM2a (backup) : 32KB (0x20030000 - 0x20037FFF) */ +#define SRAM2B_END_ADDR (0x20038FFFUL) /*!< SRAM2b (backup) : 4KB (0x20038000 - 0x20038FFF) */ -#define SYSTEM_MEMORY_END_ADDR (0x1FFF6FFFUL) /*!< System Memory : 28KB (0x1FFF0000 – 0x1FFF6FFF) */ -#define OTP_AREA_END_ADDR (0x1FFF73FFUL) /*!< OTP area : 1KB (0x1FFF7000 – 0x1FFF73FF) */ -#define OPTION_BYTE_END_ADDR (0x1FFF8FFFUL) /*!< Option Bytes : 4KB (0x1FFF8000 – 0x1FFF8FFF) */ -#define ENGI_BYTE_END_ADDR (0x1FFF7FFFUL) /*!< Engi Bytes : 3kB (0x1FFF7400 – 0x1FFF7FFF) */ +#define SYSTEM_MEMORY_END_ADDR (0x1FFF6FFFUL) /*!< System Memory : 28KB (0x1FFF0000 - 0x1FFF6FFF) */ +#define OTP_AREA_END_ADDR (0x1FFF73FFUL) /*!< OTP area : 1KB (0x1FFF7000 - 0x1FFF73FF) */ +#define OPTION_BYTE_END_ADDR (0x1FFF8FFFUL) /*!< Option Bytes : 4KB (0x1FFF8000 - 0x1FFF8FFF) */ +#define ENGI_BYTE_END_ADDR (0x1FFF7FFFUL) /*!< Engi Bytes : 3kB (0x1FFF7400 - 0x1FFF7FFF) */ /*!< Peripheral memory map */ #define APB1PERIPH_BASE PERIPH_BASE @@ -1101,7 +1101,7 @@ typedef struct #define ADC_CFGR1_ALIGN_Pos (5U) #define ADC_CFGR1_ALIGN_Msk (0x1UL << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */ -#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignement */ +#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignment */ #define ADC_CFGR1_EXTSEL_Pos (6U) #define ADC_CFGR1_EXTSEL_Msk (0x7UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */ @@ -1151,7 +1151,7 @@ typedef struct #define ADC_CFGR1_AWD1CH_3 (0x08UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x20000000 */ #define ADC_CFGR1_AWD1CH_4 (0x10UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x40000000 */ -/* Definitions for cohabitation of ADC peripherals 2.5Ms/sec and 5Ms/sec accross STM32WB serie */ +/* Definitions for cohabitation of ADC peripherals 2.5Ms/sec and 5Ms/sec across STM32WB series */ #define ADC_CFGR_DMAEN_Pos ADC_CFGR1_DMAEN_Pos #define ADC_CFGR_DMAEN_Msk ADC_CFGR1_DMAEN_Msk #define ADC_CFGR_DMAEN ADC_CFGR1_DMAEN @@ -1492,7 +1492,7 @@ typedef struct #define ADC_DR_DATA_14 (0x4000UL << ADC_DR_DATA_Pos) /*!< 0x00004000 */ #define ADC_DR_DATA_15 (0x8000UL << ADC_DR_DATA_Pos) /*!< 0x00008000 */ -/* Definitions for cohabitation of ADC peripherals 2.5Ms/sec and 5Ms/sec accross STM32WB serie */ +/* Definitions for cohabitation of ADC peripherals 2.5Ms/sec and 5Ms/sec across STM32WB series */ #define ADC_DR_RDATA_Pos ADC_DR_DATA_Pos #define ADC_DR_RDATA_Msk ADC_DR_DATA_Msk #define ADC_DR_RDATA ADC_DR_DATA @@ -3136,12 +3136,12 @@ typedef struct /* Arithmetic addition output data */ #define PKA_ARITHMETIC_ADD_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ -/* Arithmetic substraction input data */ +/* Arithmetic subtraction input data */ #define PKA_ARITHMETIC_SUB_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ #define PKA_ARITHMETIC_SUB_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ #define PKA_ARITHMETIC_SUB_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ -/* Arithmetic substraction output data */ +/* Arithmetic subtraction output data */ #define PKA_ARITHMETIC_SUB_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ /* Arithmetic multiplication input data */ @@ -3177,13 +3177,13 @@ typedef struct /* Modular inversion output data */ #define PKA_MODULAR_INV_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ -/* Modular substraction input data */ +/* Modular subtraction input data */ #define PKA_MODULAR_SUB_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ #define PKA_MODULAR_SUB_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ #define PKA_MODULAR_SUB_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ #define PKA_MODULAR_SUB_IN_OP3_MOD ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 */ -/* Modular substraction output data */ +/* Modular subtraction output data */ #define PKA_MODULAR_SUB_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ /* Montgomery multiplication input data */ @@ -7126,10 +7126,10 @@ typedef struct #define RTC_CR_OSEL_1 (0x2U << RTC_CR_OSEL_Pos) /*!< 0x00400000 */ #define RTC_CR_POL_Pos (20U) #define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */ -#define RTC_CR_POL RTC_CR_POL_Msk /*!< Ouput polarity */ +#define RTC_CR_POL RTC_CR_POL_Msk /*!< Output polarity */ #define RTC_CR_COSEL_Pos (19U) #define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ -#define RTC_CR_COSEL RTC_CR_COSEL_Msk /*!< Calibration ouput selection */ +#define RTC_CR_COSEL RTC_CR_COSEL_Msk /*!< Calibration output selection */ #define RTC_CR_BKP_Pos (18U) #define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */ #define RTC_CR_BKP RTC_CR_BKP_Msk /*!< Backup */ @@ -7398,7 +7398,7 @@ typedef struct /******************** Bits definition for RTC_SHIFTR register ***************/ #define RTC_SHIFTR_SUBFS_Pos (0U) #define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */ -#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk /*!< Substract a fraction of a second */ +#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk /*!< Subtract a fraction of a second */ #define RTC_SHIFTR_ADD1S_Pos (31U) #define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */ #define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk /*!< Add on second */ @@ -8544,100 +8544,100 @@ typedef struct /***************** Bit definition for SYSCFG_SWPR1 register (SYSCFG SRAM2A write protection register) *********************************************************/ #define SYSCFG_SWPR1_PAGE0_Pos (0U) #define SYSCFG_SWPR1_PAGE0_Msk (0x1UL << SYSCFG_SWPR1_PAGE0_Pos) /*!< 0x00000001 */ -#define SYSCFG_SWPR1_PAGE0 SYSCFG_SWPR1_PAGE0_Msk /*!< SRAM2A Write protection page 0 (0x20030000 – 0x200303FF) */ +#define SYSCFG_SWPR1_PAGE0 SYSCFG_SWPR1_PAGE0_Msk /*!< SRAM2A Write protection page 0 (0x20030000 - 0x200303FF) */ #define SYSCFG_SWPR1_PAGE1_Pos (1U) #define SYSCFG_SWPR1_PAGE1_Msk (0x1UL << SYSCFG_SWPR1_PAGE1_Pos) /*!< 0x00000002 */ -#define SYSCFG_SWPR1_PAGE1 SYSCFG_SWPR1_PAGE1_Msk /*!< SRAM2A Write protection page 1 (0x20030400 – 0x200307FF) */ +#define SYSCFG_SWPR1_PAGE1 SYSCFG_SWPR1_PAGE1_Msk /*!< SRAM2A Write protection page 1 (0x20030400 - 0x200307FF) */ #define SYSCFG_SWPR1_PAGE2_Pos (2U) #define SYSCFG_SWPR1_PAGE2_Msk (0x1UL << SYSCFG_SWPR1_PAGE2_Pos) /*!< 0x00000004 */ -#define SYSCFG_SWPR1_PAGE2 SYSCFG_SWPR1_PAGE2_Msk /*!< SRAM2A Write protection page 2 (0x20030800 – 0x20030BFF) */ +#define SYSCFG_SWPR1_PAGE2 SYSCFG_SWPR1_PAGE2_Msk /*!< SRAM2A Write protection page 2 (0x20030800 - 0x20030BFF) */ #define SYSCFG_SWPR1_PAGE3_Pos (3U) #define SYSCFG_SWPR1_PAGE3_Msk (0x1UL << SYSCFG_SWPR1_PAGE3_Pos) /*!< 0x00000008 */ -#define SYSCFG_SWPR1_PAGE3 SYSCFG_SWPR1_PAGE3_Msk /*!< SRAM2A Write protection page 3 (0x20030C00 – 0x20030FFF) */ +#define SYSCFG_SWPR1_PAGE3 SYSCFG_SWPR1_PAGE3_Msk /*!< SRAM2A Write protection page 3 (0x20030C00 - 0x20030FFF) */ #define SYSCFG_SWPR1_PAGE4_Pos (4U) #define SYSCFG_SWPR1_PAGE4_Msk (0x1UL << SYSCFG_SWPR1_PAGE4_Pos) /*!< 0x00000010 */ -#define SYSCFG_SWPR1_PAGE4 SYSCFG_SWPR1_PAGE4_Msk /*!< SRAM2A Write protection page 4 (0x20031000 – 0x200313FF) */ +#define SYSCFG_SWPR1_PAGE4 SYSCFG_SWPR1_PAGE4_Msk /*!< SRAM2A Write protection page 4 (0x20031000 - 0x200313FF) */ #define SYSCFG_SWPR1_PAGE5_Pos (5U) #define SYSCFG_SWPR1_PAGE5_Msk (0x1UL << SYSCFG_SWPR1_PAGE5_Pos) /*!< 0x00000020 */ -#define SYSCFG_SWPR1_PAGE5 SYSCFG_SWPR1_PAGE5_Msk /*!< SRAM2A Write protection page 5 (0x20031400 – 0x200317FF) */ +#define SYSCFG_SWPR1_PAGE5 SYSCFG_SWPR1_PAGE5_Msk /*!< SRAM2A Write protection page 5 (0x20031400 - 0x200317FF) */ #define SYSCFG_SWPR1_PAGE6_Pos (6U) #define SYSCFG_SWPR1_PAGE6_Msk (0x1UL << SYSCFG_SWPR1_PAGE6_Pos) /*!< 0x00000040 */ -#define SYSCFG_SWPR1_PAGE6 SYSCFG_SWPR1_PAGE6_Msk /*!< SRAM2A Write protection page 6 (0x20031800 – 0x20031BFF) */ +#define SYSCFG_SWPR1_PAGE6 SYSCFG_SWPR1_PAGE6_Msk /*!< SRAM2A Write protection page 6 (0x20031800 - 0x20031BFF) */ #define SYSCFG_SWPR1_PAGE7_Pos (7U) #define SYSCFG_SWPR1_PAGE7_Msk (0x1UL << SYSCFG_SWPR1_PAGE7_Pos) /*!< 0x00000080 */ -#define SYSCFG_SWPR1_PAGE7 SYSCFG_SWPR1_PAGE7_Msk /*!< SRAM2A Write protection page 7 (0x20031C00 – 0x20031FFF) */ +#define SYSCFG_SWPR1_PAGE7 SYSCFG_SWPR1_PAGE7_Msk /*!< SRAM2A Write protection page 7 (0x20031C00 - 0x20031FFF) */ #define SYSCFG_SWPR1_PAGE8_Pos (8U) #define SYSCFG_SWPR1_PAGE8_Msk (0x1UL << SYSCFG_SWPR1_PAGE8_Pos) /*!< 0x00000100 */ -#define SYSCFG_SWPR1_PAGE8 SYSCFG_SWPR1_PAGE8_Msk /*!< SRAM2A Write protection page 8 (0x20032000 – 0x200323FF) */ +#define SYSCFG_SWPR1_PAGE8 SYSCFG_SWPR1_PAGE8_Msk /*!< SRAM2A Write protection page 8 (0x20032000 - 0x200323FF) */ #define SYSCFG_SWPR1_PAGE9_Pos (9U) #define SYSCFG_SWPR1_PAGE9_Msk (0x1UL << SYSCFG_SWPR1_PAGE9_Pos) /*!< 0x00000200 */ -#define SYSCFG_SWPR1_PAGE9 SYSCFG_SWPR1_PAGE9_Msk /*!< SRAM2A Write protection page 9 (0x20032400 – 0x200327FF) */ +#define SYSCFG_SWPR1_PAGE9 SYSCFG_SWPR1_PAGE9_Msk /*!< SRAM2A Write protection page 9 (0x20032400 - 0x200327FF) */ #define SYSCFG_SWPR1_PAGE10_Pos (10U) #define SYSCFG_SWPR1_PAGE10_Msk (0x1UL << SYSCFG_SWPR1_PAGE10_Pos) /*!< 0x00000400 */ -#define SYSCFG_SWPR1_PAGE10 SYSCFG_SWPR1_PAGE10_Msk /*!< SRAM2A Write protection page 10 (0x20032800 – 0x20032BFF) */ +#define SYSCFG_SWPR1_PAGE10 SYSCFG_SWPR1_PAGE10_Msk /*!< SRAM2A Write protection page 10 (0x20032800 - 0x20032BFF) */ #define SYSCFG_SWPR1_PAGE11_Pos (11U) #define SYSCFG_SWPR1_PAGE11_Msk (0x1UL << SYSCFG_SWPR1_PAGE11_Pos) /*!< 0x00000800 */ -#define SYSCFG_SWPR1_PAGE11 SYSCFG_SWPR1_PAGE11_Msk /*!< SRAM2A Write protection page 11 (0x20032C00 – 0x20032FFF) */ +#define SYSCFG_SWPR1_PAGE11 SYSCFG_SWPR1_PAGE11_Msk /*!< SRAM2A Write protection page 11 (0x20032C00 - 0x20032FFF) */ #define SYSCFG_SWPR1_PAGE12_Pos (12U) #define SYSCFG_SWPR1_PAGE12_Msk (0x1UL << SYSCFG_SWPR1_PAGE12_Pos) /*!< 0x00001000 */ -#define SYSCFG_SWPR1_PAGE12 SYSCFG_SWPR1_PAGE12_Msk /*!< SRAM2A Write protection page 12 (0x20033000 – 0x200333FF) */ +#define SYSCFG_SWPR1_PAGE12 SYSCFG_SWPR1_PAGE12_Msk /*!< SRAM2A Write protection page 12 (0x20033000 - 0x200333FF) */ #define SYSCFG_SWPR1_PAGE13_Pos (13U) #define SYSCFG_SWPR1_PAGE13_Msk (0x1UL << SYSCFG_SWPR1_PAGE13_Pos) /*!< 0x00002000 */ -#define SYSCFG_SWPR1_PAGE13 SYSCFG_SWPR1_PAGE13_Msk /*!< SRAM2A Write protection page 13 (0x20033400 – 0x200337FF) */ +#define SYSCFG_SWPR1_PAGE13 SYSCFG_SWPR1_PAGE13_Msk /*!< SRAM2A Write protection page 13 (0x20033400 - 0x200337FF) */ #define SYSCFG_SWPR1_PAGE14_Pos (14U) #define SYSCFG_SWPR1_PAGE14_Msk (0x1UL << SYSCFG_SWPR1_PAGE14_Pos) /*!< 0x00004000 */ -#define SYSCFG_SWPR1_PAGE14 SYSCFG_SWPR1_PAGE14_Msk /*!< SRAM2A Write protection page 14 (0x20033800 – 0x20033BFF) */ +#define SYSCFG_SWPR1_PAGE14 SYSCFG_SWPR1_PAGE14_Msk /*!< SRAM2A Write protection page 14 (0x20033800 - 0x20033BFF) */ #define SYSCFG_SWPR1_PAGE15_Pos (15U) #define SYSCFG_SWPR1_PAGE15_Msk (0x1UL << SYSCFG_SWPR1_PAGE15_Pos) /*!< 0x00008000 */ -#define SYSCFG_SWPR1_PAGE15 SYSCFG_SWPR1_PAGE15_Msk /*!< SRAM2A Write protection page 15 (0x20033C00 – 0x20033FFF) */ +#define SYSCFG_SWPR1_PAGE15 SYSCFG_SWPR1_PAGE15_Msk /*!< SRAM2A Write protection page 15 (0x20033C00 - 0x20033FFF) */ #define SYSCFG_SWPR1_PAGE16_Pos (16U) #define SYSCFG_SWPR1_PAGE16_Msk (0x1UL << SYSCFG_SWPR1_PAGE16_Pos) /*!< 0x00010000 */ -#define SYSCFG_SWPR1_PAGE16 SYSCFG_SWPR1_PAGE16_Msk /*!< SRAM2A Write protection page 16 (0x20034000 – 0x200343FF) */ +#define SYSCFG_SWPR1_PAGE16 SYSCFG_SWPR1_PAGE16_Msk /*!< SRAM2A Write protection page 16 (0x20034000 - 0x200343FF) */ #define SYSCFG_SWPR1_PAGE17_Pos (17U) #define SYSCFG_SWPR1_PAGE17_Msk (0x1UL << SYSCFG_SWPR1_PAGE17_Pos) /*!< 0x00020000 */ -#define SYSCFG_SWPR1_PAGE17 SYSCFG_SWPR1_PAGE17_Msk /*!< SRAM2A Write protection page 17 (0x20034400 – 0x200347FF) */ +#define SYSCFG_SWPR1_PAGE17 SYSCFG_SWPR1_PAGE17_Msk /*!< SRAM2A Write protection page 17 (0x20034400 - 0x200347FF) */ #define SYSCFG_SWPR1_PAGE18_Pos (18U) #define SYSCFG_SWPR1_PAGE18_Msk (0x1UL << SYSCFG_SWPR1_PAGE18_Pos) /*!< 0x00040000 */ -#define SYSCFG_SWPR1_PAGE18 SYSCFG_SWPR1_PAGE18_Msk /*!< SRAM2A Write protection page 18 (0x20034800 – 0x20034BFF) */ +#define SYSCFG_SWPR1_PAGE18 SYSCFG_SWPR1_PAGE18_Msk /*!< SRAM2A Write protection page 18 (0x20034800 - 0x20034BFF) */ #define SYSCFG_SWPR1_PAGE19_Pos (19U) #define SYSCFG_SWPR1_PAGE19_Msk (0x1UL << SYSCFG_SWPR1_PAGE19_Pos) /*!< 0x00080000 */ -#define SYSCFG_SWPR1_PAGE19 SYSCFG_SWPR1_PAGE19_Msk /*!< SRAM2A Write protection page 19 (0x20034C00 – 0x20034FFF) */ +#define SYSCFG_SWPR1_PAGE19 SYSCFG_SWPR1_PAGE19_Msk /*!< SRAM2A Write protection page 19 (0x20034C00 - 0x20034FFF) */ #define SYSCFG_SWPR1_PAGE20_Pos (20U) #define SYSCFG_SWPR1_PAGE20_Msk (0x1UL << SYSCFG_SWPR1_PAGE20_Pos) /*!< 0x00100000 */ -#define SYSCFG_SWPR1_PAGE20 SYSCFG_SWPR1_PAGE20_Msk /*!< SRAM2A Write protection page 20 (0x20035000 – 0x200353FF) */ +#define SYSCFG_SWPR1_PAGE20 SYSCFG_SWPR1_PAGE20_Msk /*!< SRAM2A Write protection page 20 (0x20035000 - 0x200353FF) */ #define SYSCFG_SWPR1_PAGE21_Pos (21U) #define SYSCFG_SWPR1_PAGE21_Msk (0x1UL << SYSCFG_SWPR1_PAGE21_Pos) /*!< 0x00200000 */ -#define SYSCFG_SWPR1_PAGE21 SYSCFG_SWPR1_PAGE21_Msk /*!< SRAM2A Write protection page 21 (0x20035400 – 0x200357FF) */ +#define SYSCFG_SWPR1_PAGE21 SYSCFG_SWPR1_PAGE21_Msk /*!< SRAM2A Write protection page 21 (0x20035400 - 0x200357FF) */ #define SYSCFG_SWPR1_PAGE22_Pos (22U) #define SYSCFG_SWPR1_PAGE22_Msk (0x1UL << SYSCFG_SWPR1_PAGE22_Pos) /*!< 0x00400000 */ -#define SYSCFG_SWPR1_PAGE22 SYSCFG_SWPR1_PAGE22_Msk /*!< SRAM2A Write protection page 22 (0x20035800 – 0x20035BFF) */ +#define SYSCFG_SWPR1_PAGE22 SYSCFG_SWPR1_PAGE22_Msk /*!< SRAM2A Write protection page 22 (0x20035800 - 0x20035BFF) */ #define SYSCFG_SWPR1_PAGE23_Pos (23U) #define SYSCFG_SWPR1_PAGE23_Msk (0x1UL << SYSCFG_SWPR1_PAGE23_Pos) /*!< 0x00800000 */ -#define SYSCFG_SWPR1_PAGE23 SYSCFG_SWPR1_PAGE23_Msk /*!< SRAM2A Write protection page 23 (0x20035C00 – 0x20035FFF) */ +#define SYSCFG_SWPR1_PAGE23 SYSCFG_SWPR1_PAGE23_Msk /*!< SRAM2A Write protection page 23 (0x20035C00 - 0x20035FFF) */ #define SYSCFG_SWPR1_PAGE24_Pos (24U) #define SYSCFG_SWPR1_PAGE24_Msk (0x1UL << SYSCFG_SWPR1_PAGE24_Pos) /*!< 0x01000000 */ -#define SYSCFG_SWPR1_PAGE24 SYSCFG_SWPR1_PAGE24_Msk /*!< SRAM2A Write protection page 24 (0x20036000 – 0x200363FF) */ +#define SYSCFG_SWPR1_PAGE24 SYSCFG_SWPR1_PAGE24_Msk /*!< SRAM2A Write protection page 24 (0x20036000 - 0x200363FF) */ #define SYSCFG_SWPR1_PAGE25_Pos (25U) #define SYSCFG_SWPR1_PAGE25_Msk (0x1UL << SYSCFG_SWPR1_PAGE25_Pos) /*!< 0x02000000 */ -#define SYSCFG_SWPR1_PAGE25 SYSCFG_SWPR1_PAGE25_Msk /*!< SRAM2A Write protection page 25 (0x20036400 – 0x200367FF) */ +#define SYSCFG_SWPR1_PAGE25 SYSCFG_SWPR1_PAGE25_Msk /*!< SRAM2A Write protection page 25 (0x20036400 - 0x200367FF) */ #define SYSCFG_SWPR1_PAGE26_Pos (26U) #define SYSCFG_SWPR1_PAGE26_Msk (0x1UL << SYSCFG_SWPR1_PAGE26_Pos) /*!< 0x04000000 */ -#define SYSCFG_SWPR1_PAGE26 SYSCFG_SWPR1_PAGE26_Msk /*!< SRAM2A Write protection page 26 (0x20036800 – 0x20036BFF) */ +#define SYSCFG_SWPR1_PAGE26 SYSCFG_SWPR1_PAGE26_Msk /*!< SRAM2A Write protection page 26 (0x20036800 - 0x20036BFF) */ #define SYSCFG_SWPR1_PAGE27_Pos (27U) #define SYSCFG_SWPR1_PAGE27_Msk (0x1UL << SYSCFG_SWPR1_PAGE27_Pos) /*!< 0x08000000 */ -#define SYSCFG_SWPR1_PAGE27 SYSCFG_SWPR1_PAGE27_Msk /*!< SRAM2A Write protection page 27 (0x20036C00 – 0x20036FFF) */ +#define SYSCFG_SWPR1_PAGE27 SYSCFG_SWPR1_PAGE27_Msk /*!< SRAM2A Write protection page 27 (0x20036C00 - 0x20036FFF) */ #define SYSCFG_SWPR1_PAGE28_Pos (28U) #define SYSCFG_SWPR1_PAGE28_Msk (0x1UL << SYSCFG_SWPR1_PAGE28_Pos) /*!< 0x10000000 */ -#define SYSCFG_SWPR1_PAGE28 SYSCFG_SWPR1_PAGE28_Msk /*!< SRAM2A Write protection page 28 (0x20037000 – 0x200373FF) */ +#define SYSCFG_SWPR1_PAGE28 SYSCFG_SWPR1_PAGE28_Msk /*!< SRAM2A Write protection page 28 (0x20037000 - 0x200373FF) */ #define SYSCFG_SWPR1_PAGE29_Pos (29U) #define SYSCFG_SWPR1_PAGE29_Msk (0x1UL << SYSCFG_SWPR1_PAGE29_Pos) /*!< 0x20000000 */ -#define SYSCFG_SWPR1_PAGE29 SYSCFG_SWPR1_PAGE29_Msk /*!< SRAM2A Write protection page 29 (0x20037400 – 0x200377FF) */ +#define SYSCFG_SWPR1_PAGE29 SYSCFG_SWPR1_PAGE29_Msk /*!< SRAM2A Write protection page 29 (0x20037400 - 0x200377FF) */ #define SYSCFG_SWPR1_PAGE30_Pos (30U) #define SYSCFG_SWPR1_PAGE30_Msk (0x1UL << SYSCFG_SWPR1_PAGE30_Pos) /*!< 0x40000000 */ -#define SYSCFG_SWPR1_PAGE30 SYSCFG_SWPR1_PAGE30_Msk /*!< SRAM2A Write protection page 30 (0x20037800 – 0x20037BFF) */ +#define SYSCFG_SWPR1_PAGE30 SYSCFG_SWPR1_PAGE30_Msk /*!< SRAM2A Write protection page 30 (0x20037800 - 0x20037BFF) */ #define SYSCFG_SWPR1_PAGE31_Pos (31U) #define SYSCFG_SWPR1_PAGE31_Msk (0x1UL << SYSCFG_SWPR1_PAGE31_Pos) /*!< 0x80000000 */ -#define SYSCFG_SWPR1_PAGE31 SYSCFG_SWPR1_PAGE31_Msk /*!< SRAM2A Write protection page 31 (0x20037C00 – 0x20037FFF) */ +#define SYSCFG_SWPR1_PAGE31 SYSCFG_SWPR1_PAGE31_Msk /*!< SRAM2A Write protection page 31 (0x20037C00 - 0x20037FFF) */ /***************** Bit definition for SYSCFG_SKR register (SYSCFG SRAM2 key register) *************************************************************************/ #define SYSCFG_SKR_KEY_Pos (0U) @@ -8647,16 +8647,16 @@ typedef struct /***************** Bit definition for SYSCFG_SWPR2 register (SYSCFG SRAM2 write protection register) **********************************************************/ #define SYSCFG_SWPR2_PAGE32_Pos (0U) #define SYSCFG_SWPR2_PAGE32_Msk (0x1UL << SYSCFG_SWPR2_PAGE32_Pos) /*!< 0x00000001 */ -#define SYSCFG_SWPR2_PAGE32 SYSCFG_SWPR2_PAGE32_Msk /*!< SRAM2B Write protection page 0 (0x20038000 – 0x200383FF) */ +#define SYSCFG_SWPR2_PAGE32 SYSCFG_SWPR2_PAGE32_Msk /*!< SRAM2B Write protection page 0 (0x20038000 - 0x200383FF) */ #define SYSCFG_SWPR2_PAGE33_Pos (1U) #define SYSCFG_SWPR2_PAGE33_Msk (0x1UL << SYSCFG_SWPR2_PAGE33_Pos) /*!< 0x00000002 */ -#define SYSCFG_SWPR2_PAGE33 SYSCFG_SWPR2_PAGE33_Msk /*!< SRAM2B Write protection page 1 (0x20038400 – 0x200387FF) */ +#define SYSCFG_SWPR2_PAGE33 SYSCFG_SWPR2_PAGE33_Msk /*!< SRAM2B Write protection page 1 (0x20038400 - 0x200387FF) */ #define SYSCFG_SWPR2_PAGE34_Pos (2U) #define SYSCFG_SWPR2_PAGE34_Msk (0x1UL << SYSCFG_SWPR2_PAGE34_Pos) /*!< 0x00000004 */ -#define SYSCFG_SWPR2_PAGE34 SYSCFG_SWPR2_PAGE34_Msk /*!< SRAM2B Write protection page 2 (0x20038800 – 0x20038bFF) */ +#define SYSCFG_SWPR2_PAGE34 SYSCFG_SWPR2_PAGE34_Msk /*!< SRAM2B Write protection page 2 (0x20038800 - 0x20038bFF) */ #define SYSCFG_SWPR2_PAGE35_Pos (3U) #define SYSCFG_SWPR2_PAGE35_Msk (0x1UL << SYSCFG_SWPR2_PAGE35_Pos) /*!< 0x00000008 */ -#define SYSCFG_SWPR2_PAGE35 SYSCFG_SWPR2_PAGE35_Msk /*!< SRAM2B Write protection page 3 (0x20038C00 – 0x20038FFF) */ +#define SYSCFG_SWPR2_PAGE35 SYSCFG_SWPR2_PAGE35_Msk /*!< SRAM2B Write protection page 3 (0x20038C00 - 0x20038FFF) */ /***************** Bit definition for SYSCFG_IMR1 register (Interrupt masks control and status register on CPU1 - part 1) *******************************************/ #define SYSCFG_IMR1_TIM1IM_Pos (13U) @@ -10994,5 +10994,3 @@ typedef struct /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBxx/Include/stm32wb30xx.h b/system/Drivers/CMSIS/Device/ST/STM32WBxx/Include/stm32wb30xx.h index b788995cf7..e558bde1f8 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32WBxx/Include/stm32wb30xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32WBxx/Include/stm32wb30xx.h @@ -431,7 +431,7 @@ uint32_t RESERVED6; /*!< Reserved, __IO uint32_t HSECR; /*!< RCC HSE Clock Register, Address offset: 0x9C */ uint32_t RESERVED7[26]; /*!< Reserved, Address offset: 0xA0-0x104 */ __IO uint32_t EXTCFGR; /*!< RCC Extended Clock Recovery Register, Address offset: 0x108 */ -uint32_t RESERVED8[15]; /*!< Reserved, Address offset: 0x10C-0x144 */ +uint32_t RESERVED8[15]; /*!< Reserved, Address offset: 0x10C-0x144 */ __IO uint32_t C2AHB1ENR; /*!< RRCC AHB1 peripheral CPU2 clocks enable register, Address offset: 0x148 */ __IO uint32_t C2AHB2ENR; /*!< RCC AHB2 peripheral CPU2 clocks enable register, Address offset: 0x14C */ __IO uint32_t C2AHB3ENR; /*!< RCC AHB3 & AHB4 peripheral CPU2 clocks enable register,, Address offset: 0x150 */ @@ -752,10 +752,10 @@ typedef struct /*!< Memory, OTP and Option bytes */ /* Base addresses */ -#define SYSTEM_MEMORY_BASE (0x1FFF0000UL) /*!< System Memory : 28Kb (0x1FFF0000 – 0x1FFF6FFF) */ -#define OTP_AREA_BASE (0x1FFF7000UL) /*!< OTP area : 1kB (0x1FFF7000 – 0x1FFF73FF) */ -#define OPTION_BYTE_BASE (0x1FFF8000UL) /*!< Option Bytes : 4kB (0x1FFF8000 – 0x1FFF8FFF) */ -#define ENGI_BYTE_BASE (0x1FFF7400UL) /*!< Engi Bytes : 3kB (0x1FFF7400 – 0x1FFF7FFF) */ +#define SYSTEM_MEMORY_BASE (0x1FFF0000UL) /*!< System Memory : 28Kb (0x1FFF0000 - 0x1FFF6FFF) */ +#define OTP_AREA_BASE (0x1FFF7000UL) /*!< OTP area : 1kB (0x1FFF7000 - 0x1FFF73FF) */ +#define OPTION_BYTE_BASE (0x1FFF8000UL) /*!< Option Bytes : 4kB (0x1FFF8000 - 0x1FFF8FFF) */ +#define ENGI_BYTE_BASE (0x1FFF7400UL) /*!< Engi Bytes : 3kB (0x1FFF7400 - 0x1FFF7FFF) */ #define SRAM1_BASE SRAM_BASE /*!< SRAM1(up to 32 KB) base address */ #define SRAM2A_BASE (SRAM_BASE + 0x00030000UL)/*!< SRAM2A(32 KB) base address */ @@ -768,14 +768,14 @@ typedef struct #define SRAM2B_SIZE 0x00008000UL /*!< SRAM2b default size : 32 kB */ /* End addresses */ -#define SRAM1_END_ADDR (0x20007FFFUL) /*!< SRAM1 : 32KB (0x20000000 – 0x20007FFF) */ -#define SRAM2A_END_ADDR (0x20037FFFUL) /*!< SRAM2a (backup) : 32KB (0x20030000 – 0x20037FFF) */ -#define SRAM2B_END_ADDR (0x2003FFFFUL) /*!< SRAM2b (non-backup) : 32KB (0x20038000 – 0x2003FFFF) */ +#define SRAM1_END_ADDR (0x20007FFFUL) /*!< SRAM1 : 32KB (0x20000000 - 0x20007FFF) */ +#define SRAM2A_END_ADDR (0x20037FFFUL) /*!< SRAM2a (backup) : 32KB (0x20030000 - 0x20037FFF) */ +#define SRAM2B_END_ADDR (0x2003FFFFUL) /*!< SRAM2b (non-backup) : 32KB (0x20038000 - 0x2003FFFF) */ -#define SYSTEM_MEMORY_END_ADDR (0x1FFF6FFFUL) /*!< System Memory : 28KB (0x1FFF0000 – 0x1FFF6FFF) */ -#define OTP_AREA_END_ADDR (0x1FFF73FFUL) /*!< OTP area : 1KB (0x1FFF7000 – 0x1FFF73FF) */ -#define OPTION_BYTE_END_ADDR (0x1FFF8FFFUL) /*!< Option Bytes : 4KB (0x1FFF8000 – 0x1FFF8FFF) */ -#define ENGI_BYTE_END_ADDR (0x1FFF7FFFUL) /*!< Engi Bytes : 3kB (0x1FFF7400 – 0x1FFF7FFF) */ +#define SYSTEM_MEMORY_END_ADDR (0x1FFF6FFFUL) /*!< System Memory : 28KB (0x1FFF0000 - 0x1FFF6FFF) */ +#define OTP_AREA_END_ADDR (0x1FFF73FFUL) /*!< OTP area : 1KB (0x1FFF7000 - 0x1FFF73FF) */ +#define OPTION_BYTE_END_ADDR (0x1FFF8FFFUL) /*!< Option Bytes : 4KB (0x1FFF8000 - 0x1FFF8FFF) */ +#define ENGI_BYTE_END_ADDR (0x1FFF7FFFUL) /*!< Engi Bytes : 3kB (0x1FFF7400 - 0x1FFF7FFF) */ /*!< Peripheral memory map */ #define APB1PERIPH_BASE PERIPH_BASE @@ -1100,7 +1100,7 @@ typedef struct #define ADC_CFGR_ALIGN_Pos (5U) #define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00000020 */ -#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */ +#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignment */ #define ADC_CFGR_EXTSEL_Pos (6U) #define ADC_CFGR_EXTSEL_Msk (0xFUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003C0 */ @@ -3521,12 +3521,12 @@ typedef struct /* Arithmetic addition output data */ #define PKA_ARITHMETIC_ADD_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ -/* Arithmetic substraction input data */ +/* Arithmetic subtraction input data */ #define PKA_ARITHMETIC_SUB_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ #define PKA_ARITHMETIC_SUB_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ #define PKA_ARITHMETIC_SUB_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ -/* Arithmetic substraction output data */ +/* Arithmetic subtraction output data */ #define PKA_ARITHMETIC_SUB_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ /* Arithmetic multiplication input data */ @@ -3562,13 +3562,13 @@ typedef struct /* Modular inversion output data */ #define PKA_MODULAR_INV_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ -/* Modular substraction input data */ +/* Modular subtraction input data */ #define PKA_MODULAR_SUB_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ #define PKA_MODULAR_SUB_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ #define PKA_MODULAR_SUB_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ #define PKA_MODULAR_SUB_IN_OP3_MOD ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 */ -/* Modular substraction output data */ +/* Modular subtraction output data */ #define PKA_MODULAR_SUB_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ /* Montgomery multiplication input data */ @@ -7494,10 +7494,10 @@ typedef struct #define RTC_CR_OSEL_1 (0x2U << RTC_CR_OSEL_Pos) /*!< 0x00400000 */ #define RTC_CR_POL_Pos (20U) #define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */ -#define RTC_CR_POL RTC_CR_POL_Msk /*!< Ouput polarity */ +#define RTC_CR_POL RTC_CR_POL_Msk /*!< Output polarity */ #define RTC_CR_COSEL_Pos (19U) #define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ -#define RTC_CR_COSEL RTC_CR_COSEL_Msk /*!< Calibration ouput selection */ +#define RTC_CR_COSEL RTC_CR_COSEL_Msk /*!< Calibration output selection */ #define RTC_CR_BKP_Pos (18U) #define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */ #define RTC_CR_BKP RTC_CR_BKP_Msk /*!< Backup */ @@ -7766,7 +7766,7 @@ typedef struct /******************** Bits definition for RTC_SHIFTR register ***************/ #define RTC_SHIFTR_SUBFS_Pos (0U) #define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */ -#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk /*!< Substract a fraction of a second */ +#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk /*!< Subtract a fraction of a second */ #define RTC_SHIFTR_ADD1S_Pos (31U) #define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */ #define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk /*!< Add on second */ @@ -8466,100 +8466,100 @@ typedef struct /***************** Bit definition for SYSCFG_SWPR1 register (SYSCFG SRAM2A write protection register) *********************************************************/ #define SYSCFG_SWPR1_PAGE0_Pos (0U) #define SYSCFG_SWPR1_PAGE0_Msk (0x1UL << SYSCFG_SWPR1_PAGE0_Pos) /*!< 0x00000001 */ -#define SYSCFG_SWPR1_PAGE0 SYSCFG_SWPR1_PAGE0_Msk /*!< SRAM2A Write protection page 0 (0x20030000 – 0x200303FF) */ +#define SYSCFG_SWPR1_PAGE0 SYSCFG_SWPR1_PAGE0_Msk /*!< SRAM2A Write protection page 0 (0x20030000 - 0x200303FF) */ #define SYSCFG_SWPR1_PAGE1_Pos (1U) #define SYSCFG_SWPR1_PAGE1_Msk (0x1UL << SYSCFG_SWPR1_PAGE1_Pos) /*!< 0x00000002 */ -#define SYSCFG_SWPR1_PAGE1 SYSCFG_SWPR1_PAGE1_Msk /*!< SRAM2A Write protection page 1 (0x20030400 – 0x200307FF) */ +#define SYSCFG_SWPR1_PAGE1 SYSCFG_SWPR1_PAGE1_Msk /*!< SRAM2A Write protection page 1 (0x20030400 - 0x200307FF) */ #define SYSCFG_SWPR1_PAGE2_Pos (2U) #define SYSCFG_SWPR1_PAGE2_Msk (0x1UL << SYSCFG_SWPR1_PAGE2_Pos) /*!< 0x00000004 */ -#define SYSCFG_SWPR1_PAGE2 SYSCFG_SWPR1_PAGE2_Msk /*!< SRAM2A Write protection page 2 (0x20030800 – 0x20030BFF) */ +#define SYSCFG_SWPR1_PAGE2 SYSCFG_SWPR1_PAGE2_Msk /*!< SRAM2A Write protection page 2 (0x20030800 - 0x20030BFF) */ #define SYSCFG_SWPR1_PAGE3_Pos (3U) #define SYSCFG_SWPR1_PAGE3_Msk (0x1UL << SYSCFG_SWPR1_PAGE3_Pos) /*!< 0x00000008 */ -#define SYSCFG_SWPR1_PAGE3 SYSCFG_SWPR1_PAGE3_Msk /*!< SRAM2A Write protection page 3 (0x20030C00 – 0x20030FFF) */ +#define SYSCFG_SWPR1_PAGE3 SYSCFG_SWPR1_PAGE3_Msk /*!< SRAM2A Write protection page 3 (0x20030C00 - 0x20030FFF) */ #define SYSCFG_SWPR1_PAGE4_Pos (4U) #define SYSCFG_SWPR1_PAGE4_Msk (0x1UL << SYSCFG_SWPR1_PAGE4_Pos) /*!< 0x00000010 */ -#define SYSCFG_SWPR1_PAGE4 SYSCFG_SWPR1_PAGE4_Msk /*!< SRAM2A Write protection page 4 (0x20031000 – 0x200313FF) */ +#define SYSCFG_SWPR1_PAGE4 SYSCFG_SWPR1_PAGE4_Msk /*!< SRAM2A Write protection page 4 (0x20031000 - 0x200313FF) */ #define SYSCFG_SWPR1_PAGE5_Pos (5U) #define SYSCFG_SWPR1_PAGE5_Msk (0x1UL << SYSCFG_SWPR1_PAGE5_Pos) /*!< 0x00000020 */ -#define SYSCFG_SWPR1_PAGE5 SYSCFG_SWPR1_PAGE5_Msk /*!< SRAM2A Write protection page 5 (0x20031400 – 0x200317FF) */ +#define SYSCFG_SWPR1_PAGE5 SYSCFG_SWPR1_PAGE5_Msk /*!< SRAM2A Write protection page 5 (0x20031400 - 0x200317FF) */ #define SYSCFG_SWPR1_PAGE6_Pos (6U) #define SYSCFG_SWPR1_PAGE6_Msk (0x1UL << SYSCFG_SWPR1_PAGE6_Pos) /*!< 0x00000040 */ -#define SYSCFG_SWPR1_PAGE6 SYSCFG_SWPR1_PAGE6_Msk /*!< SRAM2A Write protection page 6 (0x20031800 – 0x20031BFF) */ +#define SYSCFG_SWPR1_PAGE6 SYSCFG_SWPR1_PAGE6_Msk /*!< SRAM2A Write protection page 6 (0x20031800 - 0x20031BFF) */ #define SYSCFG_SWPR1_PAGE7_Pos (7U) #define SYSCFG_SWPR1_PAGE7_Msk (0x1UL << SYSCFG_SWPR1_PAGE7_Pos) /*!< 0x00000080 */ -#define SYSCFG_SWPR1_PAGE7 SYSCFG_SWPR1_PAGE7_Msk /*!< SRAM2A Write protection page 7 (0x20031C00 – 0x20031FFF) */ +#define SYSCFG_SWPR1_PAGE7 SYSCFG_SWPR1_PAGE7_Msk /*!< SRAM2A Write protection page 7 (0x20031C00 - 0x20031FFF) */ #define SYSCFG_SWPR1_PAGE8_Pos (8U) #define SYSCFG_SWPR1_PAGE8_Msk (0x1UL << SYSCFG_SWPR1_PAGE8_Pos) /*!< 0x00000100 */ -#define SYSCFG_SWPR1_PAGE8 SYSCFG_SWPR1_PAGE8_Msk /*!< SRAM2A Write protection page 8 (0x20032000 – 0x200323FF) */ +#define SYSCFG_SWPR1_PAGE8 SYSCFG_SWPR1_PAGE8_Msk /*!< SRAM2A Write protection page 8 (0x20032000 - 0x200323FF) */ #define SYSCFG_SWPR1_PAGE9_Pos (9U) #define SYSCFG_SWPR1_PAGE9_Msk (0x1UL << SYSCFG_SWPR1_PAGE9_Pos) /*!< 0x00000200 */ -#define SYSCFG_SWPR1_PAGE9 SYSCFG_SWPR1_PAGE9_Msk /*!< SRAM2A Write protection page 9 (0x20032400 – 0x200327FF) */ +#define SYSCFG_SWPR1_PAGE9 SYSCFG_SWPR1_PAGE9_Msk /*!< SRAM2A Write protection page 9 (0x20032400 - 0x200327FF) */ #define SYSCFG_SWPR1_PAGE10_Pos (10U) #define SYSCFG_SWPR1_PAGE10_Msk (0x1UL << SYSCFG_SWPR1_PAGE10_Pos) /*!< 0x00000400 */ -#define SYSCFG_SWPR1_PAGE10 SYSCFG_SWPR1_PAGE10_Msk /*!< SRAM2A Write protection page 10 (0x20032800 – 0x20032BFF) */ +#define SYSCFG_SWPR1_PAGE10 SYSCFG_SWPR1_PAGE10_Msk /*!< SRAM2A Write protection page 10 (0x20032800 - 0x20032BFF) */ #define SYSCFG_SWPR1_PAGE11_Pos (11U) #define SYSCFG_SWPR1_PAGE11_Msk (0x1UL << SYSCFG_SWPR1_PAGE11_Pos) /*!< 0x00000800 */ -#define SYSCFG_SWPR1_PAGE11 SYSCFG_SWPR1_PAGE11_Msk /*!< SRAM2A Write protection page 11 (0x20032C00 – 0x20032FFF) */ +#define SYSCFG_SWPR1_PAGE11 SYSCFG_SWPR1_PAGE11_Msk /*!< SRAM2A Write protection page 11 (0x20032C00 - 0x20032FFF) */ #define SYSCFG_SWPR1_PAGE12_Pos (12U) #define SYSCFG_SWPR1_PAGE12_Msk (0x1UL << SYSCFG_SWPR1_PAGE12_Pos) /*!< 0x00001000 */ -#define SYSCFG_SWPR1_PAGE12 SYSCFG_SWPR1_PAGE12_Msk /*!< SRAM2A Write protection page 12 (0x20033000 – 0x200333FF) */ +#define SYSCFG_SWPR1_PAGE12 SYSCFG_SWPR1_PAGE12_Msk /*!< SRAM2A Write protection page 12 (0x20033000 - 0x200333FF) */ #define SYSCFG_SWPR1_PAGE13_Pos (13U) #define SYSCFG_SWPR1_PAGE13_Msk (0x1UL << SYSCFG_SWPR1_PAGE13_Pos) /*!< 0x00002000 */ -#define SYSCFG_SWPR1_PAGE13 SYSCFG_SWPR1_PAGE13_Msk /*!< SRAM2A Write protection page 13 (0x20033400 – 0x200337FF) */ +#define SYSCFG_SWPR1_PAGE13 SYSCFG_SWPR1_PAGE13_Msk /*!< SRAM2A Write protection page 13 (0x20033400 - 0x200337FF) */ #define SYSCFG_SWPR1_PAGE14_Pos (14U) #define SYSCFG_SWPR1_PAGE14_Msk (0x1UL << SYSCFG_SWPR1_PAGE14_Pos) /*!< 0x00004000 */ -#define SYSCFG_SWPR1_PAGE14 SYSCFG_SWPR1_PAGE14_Msk /*!< SRAM2A Write protection page 14 (0x20033800 – 0x20033BFF) */ +#define SYSCFG_SWPR1_PAGE14 SYSCFG_SWPR1_PAGE14_Msk /*!< SRAM2A Write protection page 14 (0x20033800 - 0x20033BFF) */ #define SYSCFG_SWPR1_PAGE15_Pos (15U) #define SYSCFG_SWPR1_PAGE15_Msk (0x1UL << SYSCFG_SWPR1_PAGE15_Pos) /*!< 0x00008000 */ -#define SYSCFG_SWPR1_PAGE15 SYSCFG_SWPR1_PAGE15_Msk /*!< SRAM2A Write protection page 15 (0x20033C00 – 0x20033FFF) */ +#define SYSCFG_SWPR1_PAGE15 SYSCFG_SWPR1_PAGE15_Msk /*!< SRAM2A Write protection page 15 (0x20033C00 - 0x20033FFF) */ #define SYSCFG_SWPR1_PAGE16_Pos (16U) #define SYSCFG_SWPR1_PAGE16_Msk (0x1UL << SYSCFG_SWPR1_PAGE16_Pos) /*!< 0x00010000 */ -#define SYSCFG_SWPR1_PAGE16 SYSCFG_SWPR1_PAGE16_Msk /*!< SRAM2A Write protection page 16 (0x20034000 – 0x200343FF) */ +#define SYSCFG_SWPR1_PAGE16 SYSCFG_SWPR1_PAGE16_Msk /*!< SRAM2A Write protection page 16 (0x20034000 - 0x200343FF) */ #define SYSCFG_SWPR1_PAGE17_Pos (17U) #define SYSCFG_SWPR1_PAGE17_Msk (0x1UL << SYSCFG_SWPR1_PAGE17_Pos) /*!< 0x00020000 */ -#define SYSCFG_SWPR1_PAGE17 SYSCFG_SWPR1_PAGE17_Msk /*!< SRAM2A Write protection page 17 (0x20034400 – 0x200347FF) */ +#define SYSCFG_SWPR1_PAGE17 SYSCFG_SWPR1_PAGE17_Msk /*!< SRAM2A Write protection page 17 (0x20034400 - 0x200347FF) */ #define SYSCFG_SWPR1_PAGE18_Pos (18U) #define SYSCFG_SWPR1_PAGE18_Msk (0x1UL << SYSCFG_SWPR1_PAGE18_Pos) /*!< 0x00040000 */ -#define SYSCFG_SWPR1_PAGE18 SYSCFG_SWPR1_PAGE18_Msk /*!< SRAM2A Write protection page 18 (0x20034800 – 0x20034BFF) */ +#define SYSCFG_SWPR1_PAGE18 SYSCFG_SWPR1_PAGE18_Msk /*!< SRAM2A Write protection page 18 (0x20034800 - 0x20034BFF) */ #define SYSCFG_SWPR1_PAGE19_Pos (19U) #define SYSCFG_SWPR1_PAGE19_Msk (0x1UL << SYSCFG_SWPR1_PAGE19_Pos) /*!< 0x00080000 */ -#define SYSCFG_SWPR1_PAGE19 SYSCFG_SWPR1_PAGE19_Msk /*!< SRAM2A Write protection page 19 (0x20034C00 – 0x20034FFF) */ +#define SYSCFG_SWPR1_PAGE19 SYSCFG_SWPR1_PAGE19_Msk /*!< SRAM2A Write protection page 19 (0x20034C00 - 0x20034FFF) */ #define SYSCFG_SWPR1_PAGE20_Pos (20U) #define SYSCFG_SWPR1_PAGE20_Msk (0x1UL << SYSCFG_SWPR1_PAGE20_Pos) /*!< 0x00100000 */ -#define SYSCFG_SWPR1_PAGE20 SYSCFG_SWPR1_PAGE20_Msk /*!< SRAM2A Write protection page 20 (0x20035000 – 0x200353FF) */ +#define SYSCFG_SWPR1_PAGE20 SYSCFG_SWPR1_PAGE20_Msk /*!< SRAM2A Write protection page 20 (0x20035000 - 0x200353FF) */ #define SYSCFG_SWPR1_PAGE21_Pos (21U) #define SYSCFG_SWPR1_PAGE21_Msk (0x1UL << SYSCFG_SWPR1_PAGE21_Pos) /*!< 0x00200000 */ -#define SYSCFG_SWPR1_PAGE21 SYSCFG_SWPR1_PAGE21_Msk /*!< SRAM2A Write protection page 21 (0x20035400 – 0x200357FF) */ +#define SYSCFG_SWPR1_PAGE21 SYSCFG_SWPR1_PAGE21_Msk /*!< SRAM2A Write protection page 21 (0x20035400 - 0x200357FF) */ #define SYSCFG_SWPR1_PAGE22_Pos (22U) #define SYSCFG_SWPR1_PAGE22_Msk (0x1UL << SYSCFG_SWPR1_PAGE22_Pos) /*!< 0x00400000 */ -#define SYSCFG_SWPR1_PAGE22 SYSCFG_SWPR1_PAGE22_Msk /*!< SRAM2A Write protection page 22 (0x20035800 – 0x20035BFF) */ +#define SYSCFG_SWPR1_PAGE22 SYSCFG_SWPR1_PAGE22_Msk /*!< SRAM2A Write protection page 22 (0x20035800 - 0x20035BFF) */ #define SYSCFG_SWPR1_PAGE23_Pos (23U) #define SYSCFG_SWPR1_PAGE23_Msk (0x1UL << SYSCFG_SWPR1_PAGE23_Pos) /*!< 0x00800000 */ -#define SYSCFG_SWPR1_PAGE23 SYSCFG_SWPR1_PAGE23_Msk /*!< SRAM2A Write protection page 23 (0x20035C00 – 0x20035FFF) */ +#define SYSCFG_SWPR1_PAGE23 SYSCFG_SWPR1_PAGE23_Msk /*!< SRAM2A Write protection page 23 (0x20035C00 - 0x20035FFF) */ #define SYSCFG_SWPR1_PAGE24_Pos (24U) #define SYSCFG_SWPR1_PAGE24_Msk (0x1UL << SYSCFG_SWPR1_PAGE24_Pos) /*!< 0x01000000 */ -#define SYSCFG_SWPR1_PAGE24 SYSCFG_SWPR1_PAGE24_Msk /*!< SRAM2A Write protection page 24 (0x20036000 – 0x200363FF) */ +#define SYSCFG_SWPR1_PAGE24 SYSCFG_SWPR1_PAGE24_Msk /*!< SRAM2A Write protection page 24 (0x20036000 - 0x200363FF) */ #define SYSCFG_SWPR1_PAGE25_Pos (25U) #define SYSCFG_SWPR1_PAGE25_Msk (0x1UL << SYSCFG_SWPR1_PAGE25_Pos) /*!< 0x02000000 */ -#define SYSCFG_SWPR1_PAGE25 SYSCFG_SWPR1_PAGE25_Msk /*!< SRAM2A Write protection page 25 (0x20036400 – 0x200367FF) */ +#define SYSCFG_SWPR1_PAGE25 SYSCFG_SWPR1_PAGE25_Msk /*!< SRAM2A Write protection page 25 (0x20036400 - 0x200367FF) */ #define SYSCFG_SWPR1_PAGE26_Pos (26U) #define SYSCFG_SWPR1_PAGE26_Msk (0x1UL << SYSCFG_SWPR1_PAGE26_Pos) /*!< 0x04000000 */ -#define SYSCFG_SWPR1_PAGE26 SYSCFG_SWPR1_PAGE26_Msk /*!< SRAM2A Write protection page 26 (0x20036800 – 0x20036BFF) */ +#define SYSCFG_SWPR1_PAGE26 SYSCFG_SWPR1_PAGE26_Msk /*!< SRAM2A Write protection page 26 (0x20036800 - 0x20036BFF) */ #define SYSCFG_SWPR1_PAGE27_Pos (27U) #define SYSCFG_SWPR1_PAGE27_Msk (0x1UL << SYSCFG_SWPR1_PAGE27_Pos) /*!< 0x08000000 */ -#define SYSCFG_SWPR1_PAGE27 SYSCFG_SWPR1_PAGE27_Msk /*!< SRAM2A Write protection page 27 (0x20036C00 – 0x20036FFF) */ +#define SYSCFG_SWPR1_PAGE27 SYSCFG_SWPR1_PAGE27_Msk /*!< SRAM2A Write protection page 27 (0x20036C00 - 0x20036FFF) */ #define SYSCFG_SWPR1_PAGE28_Pos (28U) #define SYSCFG_SWPR1_PAGE28_Msk (0x1UL << SYSCFG_SWPR1_PAGE28_Pos) /*!< 0x10000000 */ -#define SYSCFG_SWPR1_PAGE28 SYSCFG_SWPR1_PAGE28_Msk /*!< SRAM2A Write protection page 28 (0x20037000 – 0x200373FF) */ +#define SYSCFG_SWPR1_PAGE28 SYSCFG_SWPR1_PAGE28_Msk /*!< SRAM2A Write protection page 28 (0x20037000 - 0x200373FF) */ #define SYSCFG_SWPR1_PAGE29_Pos (29U) #define SYSCFG_SWPR1_PAGE29_Msk (0x1UL << SYSCFG_SWPR1_PAGE29_Pos) /*!< 0x20000000 */ -#define SYSCFG_SWPR1_PAGE29 SYSCFG_SWPR1_PAGE29_Msk /*!< SRAM2A Write protection page 29 (0x20037400 – 0x200377FF) */ +#define SYSCFG_SWPR1_PAGE29 SYSCFG_SWPR1_PAGE29_Msk /*!< SRAM2A Write protection page 29 (0x20037400 - 0x200377FF) */ #define SYSCFG_SWPR1_PAGE30_Pos (30U) #define SYSCFG_SWPR1_PAGE30_Msk (0x1UL << SYSCFG_SWPR1_PAGE30_Pos) /*!< 0x40000000 */ -#define SYSCFG_SWPR1_PAGE30 SYSCFG_SWPR1_PAGE30_Msk /*!< SRAM2A Write protection page 30 (0x20037800 – 0x20037BFF) */ +#define SYSCFG_SWPR1_PAGE30 SYSCFG_SWPR1_PAGE30_Msk /*!< SRAM2A Write protection page 30 (0x20037800 - 0x20037BFF) */ #define SYSCFG_SWPR1_PAGE31_Pos (31U) #define SYSCFG_SWPR1_PAGE31_Msk (0x1UL << SYSCFG_SWPR1_PAGE31_Pos) /*!< 0x80000000 */ -#define SYSCFG_SWPR1_PAGE31 SYSCFG_SWPR1_PAGE31_Msk /*!< SRAM2A Write protection page 31 (0x20037C00 – 0x20037FFF) */ +#define SYSCFG_SWPR1_PAGE31 SYSCFG_SWPR1_PAGE31_Msk /*!< SRAM2A Write protection page 31 (0x20037C00 - 0x20037FFF) */ /***************** Bit definition for SYSCFG_SKR register (SYSCFG SRAM2 key register) *************************************************************************/ #define SYSCFG_SKR_KEY_Pos (0U) @@ -8569,100 +8569,100 @@ typedef struct /***************** Bit definition for SYSCFG_SWPR2 register (SYSCFG SRAM2 write protection register) **********************************************************/ #define SYSCFG_SWPR2_PAGE32_Pos (0U) #define SYSCFG_SWPR2_PAGE32_Msk (0x1UL << SYSCFG_SWPR2_PAGE32_Pos) /*!< 0x00000001 */ -#define SYSCFG_SWPR2_PAGE32 SYSCFG_SWPR2_PAGE32_Msk /*!< SRAM2B Write protection page 0 (0x20038000 – 0x200383FF) */ +#define SYSCFG_SWPR2_PAGE32 SYSCFG_SWPR2_PAGE32_Msk /*!< SRAM2B Write protection page 0 (0x20038000 - 0x200383FF) */ #define SYSCFG_SWPR2_PAGE33_Pos (1U) #define SYSCFG_SWPR2_PAGE33_Msk (0x1UL << SYSCFG_SWPR2_PAGE33_Pos) /*!< 0x00000002 */ -#define SYSCFG_SWPR2_PAGE33 SYSCFG_SWPR2_PAGE33_Msk /*!< SRAM2B Write protection page 1 (0x20038400 – 0x200387FF) */ +#define SYSCFG_SWPR2_PAGE33 SYSCFG_SWPR2_PAGE33_Msk /*!< SRAM2B Write protection page 1 (0x20038400 - 0x200387FF) */ #define SYSCFG_SWPR2_PAGE34_Pos (2U) #define SYSCFG_SWPR2_PAGE34_Msk (0x1UL << SYSCFG_SWPR2_PAGE34_Pos) /*!< 0x00000004 */ -#define SYSCFG_SWPR2_PAGE34 SYSCFG_SWPR2_PAGE34_Msk /*!< SRAM2B Write protection page 2 (0x20038800 – 0x20038bFF) */ +#define SYSCFG_SWPR2_PAGE34 SYSCFG_SWPR2_PAGE34_Msk /*!< SRAM2B Write protection page 2 (0x20038800 - 0x20038bFF) */ #define SYSCFG_SWPR2_PAGE35_Pos (3U) #define SYSCFG_SWPR2_PAGE35_Msk (0x1UL << SYSCFG_SWPR2_PAGE35_Pos) /*!< 0x00000008 */ -#define SYSCFG_SWPR2_PAGE35 SYSCFG_SWPR2_PAGE35_Msk /*!< SRAM2B Write protection page 3 (0x20038C00 – 0x20038FFF) */ +#define SYSCFG_SWPR2_PAGE35 SYSCFG_SWPR2_PAGE35_Msk /*!< SRAM2B Write protection page 3 (0x20038C00 - 0x20038FFF) */ #define SYSCFG_SWPR2_PAGE36_Pos (4U) #define SYSCFG_SWPR2_PAGE36_Msk (0x1UL << SYSCFG_SWPR2_PAGE36_Pos) /*!< 0x00000010 */ -#define SYSCFG_SWPR2_PAGE36 SYSCFG_SWPR2_PAGE36_Msk /*!< SRAM2B Write protection page 4 (0x20039000 – 0x200393FF) */ +#define SYSCFG_SWPR2_PAGE36 SYSCFG_SWPR2_PAGE36_Msk /*!< SRAM2B Write protection page 4 (0x20039000 - 0x200393FF) */ #define SYSCFG_SWPR2_PAGE37_Pos (5U) #define SYSCFG_SWPR2_PAGE37_Msk (0x1UL << SYSCFG_SWPR2_PAGE37_Pos) /*!< 0x00000020 */ -#define SYSCFG_SWPR2_PAGE37 SYSCFG_SWPR2_PAGE37_Msk /*!< SRAM2B Write protection page 5 (0x20039400 – 0x200397FF) */ +#define SYSCFG_SWPR2_PAGE37 SYSCFG_SWPR2_PAGE37_Msk /*!< SRAM2B Write protection page 5 (0x20039400 - 0x200397FF) */ #define SYSCFG_SWPR2_PAGE38_Pos (6U) #define SYSCFG_SWPR2_PAGE38_Msk (0x1UL << SYSCFG_SWPR2_PAGE38_Pos) /*!< 0x00000040 */ -#define SYSCFG_SWPR2_PAGE38 SYSCFG_SWPR2_PAGE38_Msk /*!< SRAM2B Write protection page 6 (0x20039800 – 0x20039BFF) */ +#define SYSCFG_SWPR2_PAGE38 SYSCFG_SWPR2_PAGE38_Msk /*!< SRAM2B Write protection page 6 (0x20039800 - 0x20039BFF) */ #define SYSCFG_SWPR2_PAGE39_Pos (7U) #define SYSCFG_SWPR2_PAGE39_Msk (0x1UL << SYSCFG_SWPR2_PAGE39_Pos) /*!< 0x00000080 */ -#define SYSCFG_SWPR2_PAGE39 SYSCFG_SWPR2_PAGE39_Msk /*!< SRAM2B Write protection page 7 (0x20039C00 – 0x20039FFF) */ +#define SYSCFG_SWPR2_PAGE39 SYSCFG_SWPR2_PAGE39_Msk /*!< SRAM2B Write protection page 7 (0x20039C00 - 0x20039FFF) */ #define SYSCFG_SWPR2_PAGE40_Pos (8U) #define SYSCFG_SWPR2_PAGE40_Msk (0x1UL << SYSCFG_SWPR2_PAGE40_Pos) /*!< 0x00000100 */ -#define SYSCFG_SWPR2_PAGE40 SYSCFG_SWPR2_PAGE40_Msk /*!< SRAM2B Write protection page 8 (0x2003A000 – 0x2003A3FF) */ +#define SYSCFG_SWPR2_PAGE40 SYSCFG_SWPR2_PAGE40_Msk /*!< SRAM2B Write protection page 8 (0x2003A000 - 0x2003A3FF) */ #define SYSCFG_SWPR2_PAGE41_Pos (9U) #define SYSCFG_SWPR2_PAGE41_Msk (0x1UL << SYSCFG_SWPR2_PAGE41_Pos) /*!< 0x00000200 */ -#define SYSCFG_SWPR2_PAGE41 SYSCFG_SWPR2_PAGE41_Msk /*!< SRAM2B Write protection page 9 (0x2003A400 – 0x2003A7FF) */ +#define SYSCFG_SWPR2_PAGE41 SYSCFG_SWPR2_PAGE41_Msk /*!< SRAM2B Write protection page 9 (0x2003A400 - 0x2003A7FF) */ #define SYSCFG_SWPR2_PAGE42_Pos (10U) #define SYSCFG_SWPR2_PAGE42_Msk (0x1UL << SYSCFG_SWPR2_PAGE42_Pos) /*!< 0x00000400 */ -#define SYSCFG_SWPR2_PAGE42 SYSCFG_SWPR2_PAGE42_Msk /*!< SRAM2B Write protection page 10 (0x2003A800 – 0x2003ABFF) */ +#define SYSCFG_SWPR2_PAGE42 SYSCFG_SWPR2_PAGE42_Msk /*!< SRAM2B Write protection page 10 (0x2003A800 - 0x2003ABFF) */ #define SYSCFG_SWPR2_PAGE43_Pos (11U) #define SYSCFG_SWPR2_PAGE43_Msk (0x1UL << SYSCFG_SWPR2_PAGE43_Pos) /*!< 0x00000800 */ -#define SYSCFG_SWPR2_PAGE43 SYSCFG_SWPR2_PAGE43_Msk /*!< SRAM2B Write protection page 11 (0x2003AC00 – 0x2003AFFF) */ +#define SYSCFG_SWPR2_PAGE43 SYSCFG_SWPR2_PAGE43_Msk /*!< SRAM2B Write protection page 11 (0x2003AC00 - 0x2003AFFF) */ #define SYSCFG_SWPR2_PAGE44_Pos (12U) #define SYSCFG_SWPR2_PAGE44_Msk (0x1UL << SYSCFG_SWPR2_PAGE44_Pos) /*!< 0x00001000 */ -#define SYSCFG_SWPR2_PAGE44 SYSCFG_SWPR2_PAGE44_Msk /*!< SRAM2B Write protection page 12 (0x2003B000 – 0x2003B3FF) */ +#define SYSCFG_SWPR2_PAGE44 SYSCFG_SWPR2_PAGE44_Msk /*!< SRAM2B Write protection page 12 (0x2003B000 - 0x2003B3FF) */ #define SYSCFG_SWPR2_PAGE45_Pos (13U) #define SYSCFG_SWPR2_PAGE45_Msk (0x1UL << SYSCFG_SWPR2_PAGE45_Pos) /*!< 0x00002000 */ -#define SYSCFG_SWPR2_PAGE45 SYSCFG_SWPR2_PAGE45_Msk /*!< SRAM2B Write protection page 13 (0x2003B400 – 0x2003B7FF) */ +#define SYSCFG_SWPR2_PAGE45 SYSCFG_SWPR2_PAGE45_Msk /*!< SRAM2B Write protection page 13 (0x2003B400 - 0x2003B7FF) */ #define SYSCFG_SWPR2_PAGE46_Pos (14U) #define SYSCFG_SWPR2_PAGE46_Msk (0x1UL << SYSCFG_SWPR2_PAGE46_Pos) /*!< 0x00004000 */ -#define SYSCFG_SWPR2_PAGE46 SYSCFG_SWPR2_PAGE46_Msk /*!< SRAM2B Write protection page 14 (0x2003B800 – 0x2003BBFF) */ +#define SYSCFG_SWPR2_PAGE46 SYSCFG_SWPR2_PAGE46_Msk /*!< SRAM2B Write protection page 14 (0x2003B800 - 0x2003BBFF) */ #define SYSCFG_SWPR2_PAGE47_Pos (15U) #define SYSCFG_SWPR2_PAGE47_Msk (0x1UL << SYSCFG_SWPR2_PAGE47_Pos) /*!< 0x00008000 */ -#define SYSCFG_SWPR2_PAGE47 SYSCFG_SWPR2_PAGE47_Msk /*!< SRAM2B Write protection page 15 (0x2003BC00 – 0x2003BFFF) */ +#define SYSCFG_SWPR2_PAGE47 SYSCFG_SWPR2_PAGE47_Msk /*!< SRAM2B Write protection page 15 (0x2003BC00 - 0x2003BFFF) */ #define SYSCFG_SWPR2_PAGE48_Pos (16U) #define SYSCFG_SWPR2_PAGE48_Msk (0x1UL << SYSCFG_SWPR2_PAGE48_Pos) /*!< 0x00010000 */ -#define SYSCFG_SWPR2_PAGE48 SYSCFG_SWPR2_PAGE48_Msk /*!< SRAM2B Write protection page 16 (0x2003C000 – 0x2003C3FF) */ +#define SYSCFG_SWPR2_PAGE48 SYSCFG_SWPR2_PAGE48_Msk /*!< SRAM2B Write protection page 16 (0x2003C000 - 0x2003C3FF) */ #define SYSCFG_SWPR2_PAGE49_Pos (17U) #define SYSCFG_SWPR2_PAGE49_Msk (0x1UL << SYSCFG_SWPR2_PAGE49_Pos) /*!< 0x00020000 */ -#define SYSCFG_SWPR2_PAGE49 SYSCFG_SWPR2_PAGE49_Msk /*!< SRAM2B Write protection page 17 (0x2003C400 – 0x2003C7FF) */ +#define SYSCFG_SWPR2_PAGE49 SYSCFG_SWPR2_PAGE49_Msk /*!< SRAM2B Write protection page 17 (0x2003C400 - 0x2003C7FF) */ #define SYSCFG_SWPR2_PAGE50_Pos (18U) #define SYSCFG_SWPR2_PAGE50_Msk (0x1UL << SYSCFG_SWPR2_PAGE50_Pos) /*!< 0x00040000 */ -#define SYSCFG_SWPR2_PAGE50 SYSCFG_SWPR2_PAGE50_Msk /*!< SRAM2B Write protection page 18 (0x2003C800 – 0x2003CBFF) */ +#define SYSCFG_SWPR2_PAGE50 SYSCFG_SWPR2_PAGE50_Msk /*!< SRAM2B Write protection page 18 (0x2003C800 - 0x2003CBFF) */ #define SYSCFG_SWPR2_PAGE51_Pos (19U) #define SYSCFG_SWPR2_PAGE51_Msk (0x1UL << SYSCFG_SWPR2_PAGE51_Pos) /*!< 0x00080000 */ -#define SYSCFG_SWPR2_PAGE51 SYSCFG_SWPR2_PAGE51_Msk /*!< SRAM2B Write protection page 19 (0x2003CC00 – 0x2003CFFF) */ +#define SYSCFG_SWPR2_PAGE51 SYSCFG_SWPR2_PAGE51_Msk /*!< SRAM2B Write protection page 19 (0x2003CC00 - 0x2003CFFF) */ #define SYSCFG_SWPR2_PAGE52_Pos (20U) #define SYSCFG_SWPR2_PAGE52_Msk (0x1UL << SYSCFG_SWPR2_PAGE52_Pos) /*!< 0x00100000 */ -#define SYSCFG_SWPR2_PAGE52 SYSCFG_SWPR2_PAGE52_Msk /*!< SRAM2B Write protection page 20 (0x2003D000 – 0x2003D3FF) */ +#define SYSCFG_SWPR2_PAGE52 SYSCFG_SWPR2_PAGE52_Msk /*!< SRAM2B Write protection page 20 (0x2003D000 - 0x2003D3FF) */ #define SYSCFG_SWPR2_PAGE53_Pos (21U) #define SYSCFG_SWPR2_PAGE53_Msk (0x1UL << SYSCFG_SWPR2_PAGE53_Pos) /*!< 0x00200000 */ -#define SYSCFG_SWPR2_PAGE53 SYSCFG_SWPR2_PAGE53_Msk /*!< SRAM2B Write protection page 21 (0x2003D400 – 0x2003D7FF) */ +#define SYSCFG_SWPR2_PAGE53 SYSCFG_SWPR2_PAGE53_Msk /*!< SRAM2B Write protection page 21 (0x2003D400 - 0x2003D7FF) */ #define SYSCFG_SWPR2_PAGE54_Pos (22U) #define SYSCFG_SWPR2_PAGE54_Msk (0x1UL << SYSCFG_SWPR2_PAGE54_Pos) /*!< 0x00400000 */ -#define SYSCFG_SWPR2_PAGE54 SYSCFG_SWPR2_PAGE54_Msk /*!< SRAM2B Write protection page 22 (0x2003D800 – 0x2003DBFF) */ +#define SYSCFG_SWPR2_PAGE54 SYSCFG_SWPR2_PAGE54_Msk /*!< SRAM2B Write protection page 22 (0x2003D800 - 0x2003DBFF) */ #define SYSCFG_SWPR2_PAGE55_Pos (23U) #define SYSCFG_SWPR2_PAGE55_Msk (0x1UL << SYSCFG_SWPR2_PAGE55_Pos) /*!< 0x00800000 */ -#define SYSCFG_SWPR2_PAGE55 SYSCFG_SWPR2_PAGE55_Msk /*!< SRAM2B Write protection page 23 (0x2003DC00 – 0x2003DFFF) */ +#define SYSCFG_SWPR2_PAGE55 SYSCFG_SWPR2_PAGE55_Msk /*!< SRAM2B Write protection page 23 (0x2003DC00 - 0x2003DFFF) */ #define SYSCFG_SWPR2_PAGE56_Pos (24U) #define SYSCFG_SWPR2_PAGE56_Msk (0x1UL << SYSCFG_SWPR2_PAGE56_Pos) /*!< 0x01000000 */ -#define SYSCFG_SWPR2_PAGE56 SYSCFG_SWPR2_PAGE56_Msk /*!< SRAM2B Write protection page 24 (0x2003E000 – 0x2003E3FF) */ +#define SYSCFG_SWPR2_PAGE56 SYSCFG_SWPR2_PAGE56_Msk /*!< SRAM2B Write protection page 24 (0x2003E000 - 0x2003E3FF) */ #define SYSCFG_SWPR2_PAGE57_Pos (25U) #define SYSCFG_SWPR2_PAGE57_Msk (0x1UL << SYSCFG_SWPR2_PAGE57_Pos) /*!< 0x02000000 */ -#define SYSCFG_SWPR2_PAGE57 SYSCFG_SWPR2_PAGE57_Msk /*!< SRAM2B Write protection page 25 (0x2003E400 – 0x2003E7FF) */ +#define SYSCFG_SWPR2_PAGE57 SYSCFG_SWPR2_PAGE57_Msk /*!< SRAM2B Write protection page 25 (0x2003E400 - 0x2003E7FF) */ #define SYSCFG_SWPR2_PAGE58_Pos (26U) #define SYSCFG_SWPR2_PAGE58_Msk (0x1UL << SYSCFG_SWPR2_PAGE58_Pos) /*!< 0x04000000 */ -#define SYSCFG_SWPR2_PAGE58 SYSCFG_SWPR2_PAGE58_Msk /*!< SRAM2B Write protection page 26 (0x2003E800 – 0x2003EBFF) */ +#define SYSCFG_SWPR2_PAGE58 SYSCFG_SWPR2_PAGE58_Msk /*!< SRAM2B Write protection page 26 (0x2003E800 - 0x2003EBFF) */ #define SYSCFG_SWPR2_PAGE59_Pos (27U) #define SYSCFG_SWPR2_PAGE59_Msk (0x1UL << SYSCFG_SWPR2_PAGE59_Pos) /*!< 0x08000000 */ -#define SYSCFG_SWPR2_PAGE59 SYSCFG_SWPR2_PAGE59_Msk /*!< SRAM2B Write protection page 27 (0x2003EC00 – 0x2003EFFF) */ +#define SYSCFG_SWPR2_PAGE59 SYSCFG_SWPR2_PAGE59_Msk /*!< SRAM2B Write protection page 27 (0x2003EC00 - 0x2003EFFF) */ #define SYSCFG_SWPR2_PAGE60_Pos (28U) #define SYSCFG_SWPR2_PAGE60_Msk (0x1UL << SYSCFG_SWPR2_PAGE60_Pos) /*!< 0x10000000 */ -#define SYSCFG_SWPR2_PAGE60 SYSCFG_SWPR2_PAGE60_Msk /*!< SRAM2B Write protection page 28 (0x2003F000 – 0x2003F3FF) */ +#define SYSCFG_SWPR2_PAGE60 SYSCFG_SWPR2_PAGE60_Msk /*!< SRAM2B Write protection page 28 (0x2003F000 - 0x2003F3FF) */ #define SYSCFG_SWPR2_PAGE61_Pos (29U) #define SYSCFG_SWPR2_PAGE61_Msk (0x1UL << SYSCFG_SWPR2_PAGE61_Pos) /*!< 0x20000000 */ -#define SYSCFG_SWPR2_PAGE61 SYSCFG_SWPR2_PAGE61_Msk /*!< SRAM2B Write protection page 29 (0x2003F400 – 0x2003F7FF) */ +#define SYSCFG_SWPR2_PAGE61 SYSCFG_SWPR2_PAGE61_Msk /*!< SRAM2B Write protection page 29 (0x2003F400 - 0x2003F7FF) */ #define SYSCFG_SWPR2_PAGE62_Pos (30U) #define SYSCFG_SWPR2_PAGE62_Msk (0x1UL << SYSCFG_SWPR2_PAGE62_Pos) /*!< 0x40000000 */ -#define SYSCFG_SWPR2_PAGE62 SYSCFG_SWPR2_PAGE62_Msk /*!< SRAM2B Write protection page 30 (0x2003F800 – 0x2003FBFF) */ +#define SYSCFG_SWPR2_PAGE62 SYSCFG_SWPR2_PAGE62_Msk /*!< SRAM2B Write protection page 30 (0x2003F800 - 0x2003FBFF) */ #define SYSCFG_SWPR2_PAGE63_Pos (31U) #define SYSCFG_SWPR2_PAGE63_Msk (0x1UL << SYSCFG_SWPR2_PAGE63_Pos) /*!< 0x80000000 */ -#define SYSCFG_SWPR2_PAGE63 SYSCFG_SWPR2_PAGE63_Msk /*!< SRAM2B Write protection page 31 (0x2003FC00 – 0x2003FFFF) */ +#define SYSCFG_SWPR2_PAGE63 SYSCFG_SWPR2_PAGE63_Msk /*!< SRAM2B Write protection page 31 (0x2003FC00 - 0x2003FFFF) */ /***************** Bit definition for SYSCFG_IMR1 register (Interrupt masks control and status register on CPU1 - part 1) *******************************************/ #define SYSCFG_IMR1_TIM1IM_Pos (13U) @@ -11033,5 +11033,3 @@ typedef struct /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBxx/Include/stm32wb35xx.h b/system/Drivers/CMSIS/Device/ST/STM32WBxx/Include/stm32wb35xx.h index 0390b68f29..6e124e0fb2 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32WBxx/Include/stm32wb35xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32WBxx/Include/stm32wb35xx.h @@ -483,7 +483,7 @@ uint32_t RESERVED6; /*!< Reserved, __IO uint32_t HSECR; /*!< RCC HSE Clock Register, Address offset: 0x9C */ uint32_t RESERVED7[26]; /*!< Reserved, Address offset: 0xA0-0x104 */ __IO uint32_t EXTCFGR; /*!< RCC Extended Clock Recovery Register, Address offset: 0x108 */ -uint32_t RESERVED8[15]; /*!< Reserved, Address offset: 0x10C-0x144 */ +uint32_t RESERVED8[15]; /*!< Reserved, Address offset: 0x10C-0x144 */ __IO uint32_t C2AHB1ENR; /*!< RRCC AHB1 peripheral CPU2 clocks enable register, Address offset: 0x148 */ __IO uint32_t C2AHB2ENR; /*!< RCC AHB2 peripheral CPU2 clocks enable register, Address offset: 0x14C */ __IO uint32_t C2AHB3ENR; /*!< RCC AHB3 & AHB4 peripheral CPU2 clocks enable register,, Address offset: 0x150 */ @@ -884,10 +884,10 @@ typedef struct /*!< Memory, OTP and Option bytes */ /* Base addresses */ -#define SYSTEM_MEMORY_BASE (0x1FFF0000UL) /*!< System Memory : 28Kb (0x1FFF0000 – 0x1FFF6FFF) */ -#define OTP_AREA_BASE (0x1FFF7000UL) /*!< OTP area : 1kB (0x1FFF7000 – 0x1FFF73FF) */ -#define OPTION_BYTE_BASE (0x1FFF8000UL) /*!< Option Bytes : 4kB (0x1FFF8000 – 0x1FFF8FFF) */ -#define ENGI_BYTE_BASE (0x1FFF7400UL) /*!< Engi Bytes : 3kB (0x1FFF7400 – 0x1FFF7FFF) */ +#define SYSTEM_MEMORY_BASE (0x1FFF0000UL) /*!< System Memory : 28Kb (0x1FFF0000 - 0x1FFF6FFF) */ +#define OTP_AREA_BASE (0x1FFF7000UL) /*!< OTP area : 1kB (0x1FFF7000 - 0x1FFF73FF) */ +#define OPTION_BYTE_BASE (0x1FFF8000UL) /*!< Option Bytes : 4kB (0x1FFF8000 - 0x1FFF8FFF) */ +#define ENGI_BYTE_BASE (0x1FFF7400UL) /*!< Engi Bytes : 3kB (0x1FFF7400 - 0x1FFF7FFF) */ #define SRAM1_BASE SRAM_BASE /*!< SRAM1(up to 32 KB) base address */ #define SRAM2A_BASE (SRAM_BASE + 0x00030000UL)/*!< SRAM2A(32 KB) base address */ @@ -900,14 +900,14 @@ typedef struct #define SRAM2B_SIZE 0x00008000UL /*!< SRAM2b default size : 32 kB */ /* End addresses */ -#define SRAM1_END_ADDR (0x20007FFFUL) /*!< SRAM1 : 32KB (0x20000000 – 0x20007FFF) */ -#define SRAM2A_END_ADDR (0x20037FFFUL) /*!< SRAM2a (backup) : 32KB (0x20030000 – 0x20037FFF) */ -#define SRAM2B_END_ADDR (0x2003FFFFUL) /*!< SRAM2b (non-backup) : 32KB (0x20038000 – 0x2003FFFF) */ +#define SRAM1_END_ADDR (0x20007FFFUL) /*!< SRAM1 : 32KB (0x20000000 - 0x20007FFF) */ +#define SRAM2A_END_ADDR (0x20037FFFUL) /*!< SRAM2a (backup) : 32KB (0x20030000 - 0x20037FFF) */ +#define SRAM2B_END_ADDR (0x2003FFFFUL) /*!< SRAM2b (non-backup) : 32KB (0x20038000 - 0x2003FFFF) */ -#define SYSTEM_MEMORY_END_ADDR (0x1FFF6FFFUL) /*!< System Memory : 28KB (0x1FFF0000 – 0x1FFF6FFF) */ -#define OTP_AREA_END_ADDR (0x1FFF73FFUL) /*!< OTP area : 1KB (0x1FFF7000 – 0x1FFF73FF) */ -#define OPTION_BYTE_END_ADDR (0x1FFF8FFFUL) /*!< Option Bytes : 4KB (0x1FFF8000 – 0x1FFF8FFF) */ -#define ENGI_BYTE_END_ADDR (0x1FFF7FFFUL) /*!< Engi Bytes : 3kB (0x1FFF7400 – 0x1FFF7FFF) */ +#define SYSTEM_MEMORY_END_ADDR (0x1FFF6FFFUL) /*!< System Memory : 28KB (0x1FFF0000 - 0x1FFF6FFF) */ +#define OTP_AREA_END_ADDR (0x1FFF73FFUL) /*!< OTP area : 1KB (0x1FFF7000 - 0x1FFF73FF) */ +#define OPTION_BYTE_END_ADDR (0x1FFF8FFFUL) /*!< Option Bytes : 4KB (0x1FFF8000 - 0x1FFF8FFF) */ +#define ENGI_BYTE_END_ADDR (0x1FFF7FFFUL) /*!< Engi Bytes : 3kB (0x1FFF7400 - 0x1FFF7FFF) */ /*!< Peripheral memory map */ #define APB1PERIPH_BASE PERIPH_BASE @@ -1292,7 +1292,7 @@ typedef struct #define ADC_CFGR_ALIGN_Pos (5U) #define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00000020 */ -#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */ +#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignment */ #define ADC_CFGR_EXTSEL_Pos (6U) #define ADC_CFGR_EXTSEL_Msk (0xFUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003C0 */ @@ -3899,12 +3899,12 @@ typedef struct /* Arithmetic addition output data */ #define PKA_ARITHMETIC_ADD_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ -/* Arithmetic substraction input data */ +/* Arithmetic subtraction input data */ #define PKA_ARITHMETIC_SUB_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ #define PKA_ARITHMETIC_SUB_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ #define PKA_ARITHMETIC_SUB_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ -/* Arithmetic substraction output data */ +/* Arithmetic subtraction output data */ #define PKA_ARITHMETIC_SUB_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ /* Arithmetic multiplication input data */ @@ -3940,13 +3940,13 @@ typedef struct /* Modular inversion output data */ #define PKA_MODULAR_INV_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ -/* Modular substraction input data */ +/* Modular subtraction input data */ #define PKA_MODULAR_SUB_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ #define PKA_MODULAR_SUB_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ #define PKA_MODULAR_SUB_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ #define PKA_MODULAR_SUB_IN_OP3_MOD ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 */ -/* Modular substraction output data */ +/* Modular subtraction output data */ #define PKA_MODULAR_SUB_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ /* Montgomery multiplication input data */ @@ -8495,10 +8495,10 @@ typedef struct #define RTC_CR_OSEL_1 (0x2U << RTC_CR_OSEL_Pos) /*!< 0x00400000 */ #define RTC_CR_POL_Pos (20U) #define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */ -#define RTC_CR_POL RTC_CR_POL_Msk /*!< Ouput polarity */ +#define RTC_CR_POL RTC_CR_POL_Msk /*!< Output polarity */ #define RTC_CR_COSEL_Pos (19U) #define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ -#define RTC_CR_COSEL RTC_CR_COSEL_Msk /*!< Calibration ouput selection */ +#define RTC_CR_COSEL RTC_CR_COSEL_Msk /*!< Calibration output selection */ #define RTC_CR_BKP_Pos (18U) #define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */ #define RTC_CR_BKP RTC_CR_BKP_Msk /*!< Backup */ @@ -8773,7 +8773,7 @@ typedef struct /******************** Bits definition for RTC_SHIFTR register ***************/ #define RTC_SHIFTR_SUBFS_Pos (0U) #define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */ -#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk /*!< Substract a fraction of a second */ +#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk /*!< Subtract a fraction of a second */ #define RTC_SHIFTR_ADD1S_Pos (31U) #define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */ #define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk /*!< Add on second */ @@ -9815,100 +9815,100 @@ typedef struct /***************** Bit definition for SYSCFG_SWPR1 register (SYSCFG SRAM2A write protection register) *********************************************************/ #define SYSCFG_SWPR1_PAGE0_Pos (0U) #define SYSCFG_SWPR1_PAGE0_Msk (0x1UL << SYSCFG_SWPR1_PAGE0_Pos) /*!< 0x00000001 */ -#define SYSCFG_SWPR1_PAGE0 SYSCFG_SWPR1_PAGE0_Msk /*!< SRAM2A Write protection page 0 (0x20030000 – 0x200303FF) */ +#define SYSCFG_SWPR1_PAGE0 SYSCFG_SWPR1_PAGE0_Msk /*!< SRAM2A Write protection page 0 (0x20030000 - 0x200303FF) */ #define SYSCFG_SWPR1_PAGE1_Pos (1U) #define SYSCFG_SWPR1_PAGE1_Msk (0x1UL << SYSCFG_SWPR1_PAGE1_Pos) /*!< 0x00000002 */ -#define SYSCFG_SWPR1_PAGE1 SYSCFG_SWPR1_PAGE1_Msk /*!< SRAM2A Write protection page 1 (0x20030400 – 0x200307FF) */ +#define SYSCFG_SWPR1_PAGE1 SYSCFG_SWPR1_PAGE1_Msk /*!< SRAM2A Write protection page 1 (0x20030400 - 0x200307FF) */ #define SYSCFG_SWPR1_PAGE2_Pos (2U) #define SYSCFG_SWPR1_PAGE2_Msk (0x1UL << SYSCFG_SWPR1_PAGE2_Pos) /*!< 0x00000004 */ -#define SYSCFG_SWPR1_PAGE2 SYSCFG_SWPR1_PAGE2_Msk /*!< SRAM2A Write protection page 2 (0x20030800 – 0x20030BFF) */ +#define SYSCFG_SWPR1_PAGE2 SYSCFG_SWPR1_PAGE2_Msk /*!< SRAM2A Write protection page 2 (0x20030800 - 0x20030BFF) */ #define SYSCFG_SWPR1_PAGE3_Pos (3U) #define SYSCFG_SWPR1_PAGE3_Msk (0x1UL << SYSCFG_SWPR1_PAGE3_Pos) /*!< 0x00000008 */ -#define SYSCFG_SWPR1_PAGE3 SYSCFG_SWPR1_PAGE3_Msk /*!< SRAM2A Write protection page 3 (0x20030C00 – 0x20030FFF) */ +#define SYSCFG_SWPR1_PAGE3 SYSCFG_SWPR1_PAGE3_Msk /*!< SRAM2A Write protection page 3 (0x20030C00 - 0x20030FFF) */ #define SYSCFG_SWPR1_PAGE4_Pos (4U) #define SYSCFG_SWPR1_PAGE4_Msk (0x1UL << SYSCFG_SWPR1_PAGE4_Pos) /*!< 0x00000010 */ -#define SYSCFG_SWPR1_PAGE4 SYSCFG_SWPR1_PAGE4_Msk /*!< SRAM2A Write protection page 4 (0x20031000 – 0x200313FF) */ +#define SYSCFG_SWPR1_PAGE4 SYSCFG_SWPR1_PAGE4_Msk /*!< SRAM2A Write protection page 4 (0x20031000 - 0x200313FF) */ #define SYSCFG_SWPR1_PAGE5_Pos (5U) #define SYSCFG_SWPR1_PAGE5_Msk (0x1UL << SYSCFG_SWPR1_PAGE5_Pos) /*!< 0x00000020 */ -#define SYSCFG_SWPR1_PAGE5 SYSCFG_SWPR1_PAGE5_Msk /*!< SRAM2A Write protection page 5 (0x20031400 – 0x200317FF) */ +#define SYSCFG_SWPR1_PAGE5 SYSCFG_SWPR1_PAGE5_Msk /*!< SRAM2A Write protection page 5 (0x20031400 - 0x200317FF) */ #define SYSCFG_SWPR1_PAGE6_Pos (6U) #define SYSCFG_SWPR1_PAGE6_Msk (0x1UL << SYSCFG_SWPR1_PAGE6_Pos) /*!< 0x00000040 */ -#define SYSCFG_SWPR1_PAGE6 SYSCFG_SWPR1_PAGE6_Msk /*!< SRAM2A Write protection page 6 (0x20031800 – 0x20031BFF) */ +#define SYSCFG_SWPR1_PAGE6 SYSCFG_SWPR1_PAGE6_Msk /*!< SRAM2A Write protection page 6 (0x20031800 - 0x20031BFF) */ #define SYSCFG_SWPR1_PAGE7_Pos (7U) #define SYSCFG_SWPR1_PAGE7_Msk (0x1UL << SYSCFG_SWPR1_PAGE7_Pos) /*!< 0x00000080 */ -#define SYSCFG_SWPR1_PAGE7 SYSCFG_SWPR1_PAGE7_Msk /*!< SRAM2A Write protection page 7 (0x20031C00 – 0x20031FFF) */ +#define SYSCFG_SWPR1_PAGE7 SYSCFG_SWPR1_PAGE7_Msk /*!< SRAM2A Write protection page 7 (0x20031C00 - 0x20031FFF) */ #define SYSCFG_SWPR1_PAGE8_Pos (8U) #define SYSCFG_SWPR1_PAGE8_Msk (0x1UL << SYSCFG_SWPR1_PAGE8_Pos) /*!< 0x00000100 */ -#define SYSCFG_SWPR1_PAGE8 SYSCFG_SWPR1_PAGE8_Msk /*!< SRAM2A Write protection page 8 (0x20032000 – 0x200323FF) */ +#define SYSCFG_SWPR1_PAGE8 SYSCFG_SWPR1_PAGE8_Msk /*!< SRAM2A Write protection page 8 (0x20032000 - 0x200323FF) */ #define SYSCFG_SWPR1_PAGE9_Pos (9U) #define SYSCFG_SWPR1_PAGE9_Msk (0x1UL << SYSCFG_SWPR1_PAGE9_Pos) /*!< 0x00000200 */ -#define SYSCFG_SWPR1_PAGE9 SYSCFG_SWPR1_PAGE9_Msk /*!< SRAM2A Write protection page 9 (0x20032400 – 0x200327FF) */ +#define SYSCFG_SWPR1_PAGE9 SYSCFG_SWPR1_PAGE9_Msk /*!< SRAM2A Write protection page 9 (0x20032400 - 0x200327FF) */ #define SYSCFG_SWPR1_PAGE10_Pos (10U) #define SYSCFG_SWPR1_PAGE10_Msk (0x1UL << SYSCFG_SWPR1_PAGE10_Pos) /*!< 0x00000400 */ -#define SYSCFG_SWPR1_PAGE10 SYSCFG_SWPR1_PAGE10_Msk /*!< SRAM2A Write protection page 10 (0x20032800 – 0x20032BFF) */ +#define SYSCFG_SWPR1_PAGE10 SYSCFG_SWPR1_PAGE10_Msk /*!< SRAM2A Write protection page 10 (0x20032800 - 0x20032BFF) */ #define SYSCFG_SWPR1_PAGE11_Pos (11U) #define SYSCFG_SWPR1_PAGE11_Msk (0x1UL << SYSCFG_SWPR1_PAGE11_Pos) /*!< 0x00000800 */ -#define SYSCFG_SWPR1_PAGE11 SYSCFG_SWPR1_PAGE11_Msk /*!< SRAM2A Write protection page 11 (0x20032C00 – 0x20032FFF) */ +#define SYSCFG_SWPR1_PAGE11 SYSCFG_SWPR1_PAGE11_Msk /*!< SRAM2A Write protection page 11 (0x20032C00 - 0x20032FFF) */ #define SYSCFG_SWPR1_PAGE12_Pos (12U) #define SYSCFG_SWPR1_PAGE12_Msk (0x1UL << SYSCFG_SWPR1_PAGE12_Pos) /*!< 0x00001000 */ -#define SYSCFG_SWPR1_PAGE12 SYSCFG_SWPR1_PAGE12_Msk /*!< SRAM2A Write protection page 12 (0x20033000 – 0x200333FF) */ +#define SYSCFG_SWPR1_PAGE12 SYSCFG_SWPR1_PAGE12_Msk /*!< SRAM2A Write protection page 12 (0x20033000 - 0x200333FF) */ #define SYSCFG_SWPR1_PAGE13_Pos (13U) #define SYSCFG_SWPR1_PAGE13_Msk (0x1UL << SYSCFG_SWPR1_PAGE13_Pos) /*!< 0x00002000 */ -#define SYSCFG_SWPR1_PAGE13 SYSCFG_SWPR1_PAGE13_Msk /*!< SRAM2A Write protection page 13 (0x20033400 – 0x200337FF) */ +#define SYSCFG_SWPR1_PAGE13 SYSCFG_SWPR1_PAGE13_Msk /*!< SRAM2A Write protection page 13 (0x20033400 - 0x200337FF) */ #define SYSCFG_SWPR1_PAGE14_Pos (14U) #define SYSCFG_SWPR1_PAGE14_Msk (0x1UL << SYSCFG_SWPR1_PAGE14_Pos) /*!< 0x00004000 */ -#define SYSCFG_SWPR1_PAGE14 SYSCFG_SWPR1_PAGE14_Msk /*!< SRAM2A Write protection page 14 (0x20033800 – 0x20033BFF) */ +#define SYSCFG_SWPR1_PAGE14 SYSCFG_SWPR1_PAGE14_Msk /*!< SRAM2A Write protection page 14 (0x20033800 - 0x20033BFF) */ #define SYSCFG_SWPR1_PAGE15_Pos (15U) #define SYSCFG_SWPR1_PAGE15_Msk (0x1UL << SYSCFG_SWPR1_PAGE15_Pos) /*!< 0x00008000 */ -#define SYSCFG_SWPR1_PAGE15 SYSCFG_SWPR1_PAGE15_Msk /*!< SRAM2A Write protection page 15 (0x20033C00 – 0x20033FFF) */ +#define SYSCFG_SWPR1_PAGE15 SYSCFG_SWPR1_PAGE15_Msk /*!< SRAM2A Write protection page 15 (0x20033C00 - 0x20033FFF) */ #define SYSCFG_SWPR1_PAGE16_Pos (16U) #define SYSCFG_SWPR1_PAGE16_Msk (0x1UL << SYSCFG_SWPR1_PAGE16_Pos) /*!< 0x00010000 */ -#define SYSCFG_SWPR1_PAGE16 SYSCFG_SWPR1_PAGE16_Msk /*!< SRAM2A Write protection page 16 (0x20034000 – 0x200343FF) */ +#define SYSCFG_SWPR1_PAGE16 SYSCFG_SWPR1_PAGE16_Msk /*!< SRAM2A Write protection page 16 (0x20034000 - 0x200343FF) */ #define SYSCFG_SWPR1_PAGE17_Pos (17U) #define SYSCFG_SWPR1_PAGE17_Msk (0x1UL << SYSCFG_SWPR1_PAGE17_Pos) /*!< 0x00020000 */ -#define SYSCFG_SWPR1_PAGE17 SYSCFG_SWPR1_PAGE17_Msk /*!< SRAM2A Write protection page 17 (0x20034400 – 0x200347FF) */ +#define SYSCFG_SWPR1_PAGE17 SYSCFG_SWPR1_PAGE17_Msk /*!< SRAM2A Write protection page 17 (0x20034400 - 0x200347FF) */ #define SYSCFG_SWPR1_PAGE18_Pos (18U) #define SYSCFG_SWPR1_PAGE18_Msk (0x1UL << SYSCFG_SWPR1_PAGE18_Pos) /*!< 0x00040000 */ -#define SYSCFG_SWPR1_PAGE18 SYSCFG_SWPR1_PAGE18_Msk /*!< SRAM2A Write protection page 18 (0x20034800 – 0x20034BFF) */ +#define SYSCFG_SWPR1_PAGE18 SYSCFG_SWPR1_PAGE18_Msk /*!< SRAM2A Write protection page 18 (0x20034800 - 0x20034BFF) */ #define SYSCFG_SWPR1_PAGE19_Pos (19U) #define SYSCFG_SWPR1_PAGE19_Msk (0x1UL << SYSCFG_SWPR1_PAGE19_Pos) /*!< 0x00080000 */ -#define SYSCFG_SWPR1_PAGE19 SYSCFG_SWPR1_PAGE19_Msk /*!< SRAM2A Write protection page 19 (0x20034C00 – 0x20034FFF) */ +#define SYSCFG_SWPR1_PAGE19 SYSCFG_SWPR1_PAGE19_Msk /*!< SRAM2A Write protection page 19 (0x20034C00 - 0x20034FFF) */ #define SYSCFG_SWPR1_PAGE20_Pos (20U) #define SYSCFG_SWPR1_PAGE20_Msk (0x1UL << SYSCFG_SWPR1_PAGE20_Pos) /*!< 0x00100000 */ -#define SYSCFG_SWPR1_PAGE20 SYSCFG_SWPR1_PAGE20_Msk /*!< SRAM2A Write protection page 20 (0x20035000 – 0x200353FF) */ +#define SYSCFG_SWPR1_PAGE20 SYSCFG_SWPR1_PAGE20_Msk /*!< SRAM2A Write protection page 20 (0x20035000 - 0x200353FF) */ #define SYSCFG_SWPR1_PAGE21_Pos (21U) #define SYSCFG_SWPR1_PAGE21_Msk (0x1UL << SYSCFG_SWPR1_PAGE21_Pos) /*!< 0x00200000 */ -#define SYSCFG_SWPR1_PAGE21 SYSCFG_SWPR1_PAGE21_Msk /*!< SRAM2A Write protection page 21 (0x20035400 – 0x200357FF) */ +#define SYSCFG_SWPR1_PAGE21 SYSCFG_SWPR1_PAGE21_Msk /*!< SRAM2A Write protection page 21 (0x20035400 - 0x200357FF) */ #define SYSCFG_SWPR1_PAGE22_Pos (22U) #define SYSCFG_SWPR1_PAGE22_Msk (0x1UL << SYSCFG_SWPR1_PAGE22_Pos) /*!< 0x00400000 */ -#define SYSCFG_SWPR1_PAGE22 SYSCFG_SWPR1_PAGE22_Msk /*!< SRAM2A Write protection page 22 (0x20035800 – 0x20035BFF) */ +#define SYSCFG_SWPR1_PAGE22 SYSCFG_SWPR1_PAGE22_Msk /*!< SRAM2A Write protection page 22 (0x20035800 - 0x20035BFF) */ #define SYSCFG_SWPR1_PAGE23_Pos (23U) #define SYSCFG_SWPR1_PAGE23_Msk (0x1UL << SYSCFG_SWPR1_PAGE23_Pos) /*!< 0x00800000 */ -#define SYSCFG_SWPR1_PAGE23 SYSCFG_SWPR1_PAGE23_Msk /*!< SRAM2A Write protection page 23 (0x20035C00 – 0x20035FFF) */ +#define SYSCFG_SWPR1_PAGE23 SYSCFG_SWPR1_PAGE23_Msk /*!< SRAM2A Write protection page 23 (0x20035C00 - 0x20035FFF) */ #define SYSCFG_SWPR1_PAGE24_Pos (24U) #define SYSCFG_SWPR1_PAGE24_Msk (0x1UL << SYSCFG_SWPR1_PAGE24_Pos) /*!< 0x01000000 */ -#define SYSCFG_SWPR1_PAGE24 SYSCFG_SWPR1_PAGE24_Msk /*!< SRAM2A Write protection page 24 (0x20036000 – 0x200363FF) */ +#define SYSCFG_SWPR1_PAGE24 SYSCFG_SWPR1_PAGE24_Msk /*!< SRAM2A Write protection page 24 (0x20036000 - 0x200363FF) */ #define SYSCFG_SWPR1_PAGE25_Pos (25U) #define SYSCFG_SWPR1_PAGE25_Msk (0x1UL << SYSCFG_SWPR1_PAGE25_Pos) /*!< 0x02000000 */ -#define SYSCFG_SWPR1_PAGE25 SYSCFG_SWPR1_PAGE25_Msk /*!< SRAM2A Write protection page 25 (0x20036400 – 0x200367FF) */ +#define SYSCFG_SWPR1_PAGE25 SYSCFG_SWPR1_PAGE25_Msk /*!< SRAM2A Write protection page 25 (0x20036400 - 0x200367FF) */ #define SYSCFG_SWPR1_PAGE26_Pos (26U) #define SYSCFG_SWPR1_PAGE26_Msk (0x1UL << SYSCFG_SWPR1_PAGE26_Pos) /*!< 0x04000000 */ -#define SYSCFG_SWPR1_PAGE26 SYSCFG_SWPR1_PAGE26_Msk /*!< SRAM2A Write protection page 26 (0x20036800 – 0x20036BFF) */ +#define SYSCFG_SWPR1_PAGE26 SYSCFG_SWPR1_PAGE26_Msk /*!< SRAM2A Write protection page 26 (0x20036800 - 0x20036BFF) */ #define SYSCFG_SWPR1_PAGE27_Pos (27U) #define SYSCFG_SWPR1_PAGE27_Msk (0x1UL << SYSCFG_SWPR1_PAGE27_Pos) /*!< 0x08000000 */ -#define SYSCFG_SWPR1_PAGE27 SYSCFG_SWPR1_PAGE27_Msk /*!< SRAM2A Write protection page 27 (0x20036C00 – 0x20036FFF) */ +#define SYSCFG_SWPR1_PAGE27 SYSCFG_SWPR1_PAGE27_Msk /*!< SRAM2A Write protection page 27 (0x20036C00 - 0x20036FFF) */ #define SYSCFG_SWPR1_PAGE28_Pos (28U) #define SYSCFG_SWPR1_PAGE28_Msk (0x1UL << SYSCFG_SWPR1_PAGE28_Pos) /*!< 0x10000000 */ -#define SYSCFG_SWPR1_PAGE28 SYSCFG_SWPR1_PAGE28_Msk /*!< SRAM2A Write protection page 28 (0x20037000 – 0x200373FF) */ +#define SYSCFG_SWPR1_PAGE28 SYSCFG_SWPR1_PAGE28_Msk /*!< SRAM2A Write protection page 28 (0x20037000 - 0x200373FF) */ #define SYSCFG_SWPR1_PAGE29_Pos (29U) #define SYSCFG_SWPR1_PAGE29_Msk (0x1UL << SYSCFG_SWPR1_PAGE29_Pos) /*!< 0x20000000 */ -#define SYSCFG_SWPR1_PAGE29 SYSCFG_SWPR1_PAGE29_Msk /*!< SRAM2A Write protection page 29 (0x20037400 – 0x200377FF) */ +#define SYSCFG_SWPR1_PAGE29 SYSCFG_SWPR1_PAGE29_Msk /*!< SRAM2A Write protection page 29 (0x20037400 - 0x200377FF) */ #define SYSCFG_SWPR1_PAGE30_Pos (30U) #define SYSCFG_SWPR1_PAGE30_Msk (0x1UL << SYSCFG_SWPR1_PAGE30_Pos) /*!< 0x40000000 */ -#define SYSCFG_SWPR1_PAGE30 SYSCFG_SWPR1_PAGE30_Msk /*!< SRAM2A Write protection page 30 (0x20037800 – 0x20037BFF) */ +#define SYSCFG_SWPR1_PAGE30 SYSCFG_SWPR1_PAGE30_Msk /*!< SRAM2A Write protection page 30 (0x20037800 - 0x20037BFF) */ #define SYSCFG_SWPR1_PAGE31_Pos (31U) #define SYSCFG_SWPR1_PAGE31_Msk (0x1UL << SYSCFG_SWPR1_PAGE31_Pos) /*!< 0x80000000 */ -#define SYSCFG_SWPR1_PAGE31 SYSCFG_SWPR1_PAGE31_Msk /*!< SRAM2A Write protection page 31 (0x20037C00 – 0x20037FFF) */ +#define SYSCFG_SWPR1_PAGE31 SYSCFG_SWPR1_PAGE31_Msk /*!< SRAM2A Write protection page 31 (0x20037C00 - 0x20037FFF) */ /***************** Bit definition for SYSCFG_SKR register (SYSCFG SRAM2 key register) *************************************************************************/ #define SYSCFG_SKR_KEY_Pos (0U) @@ -9918,100 +9918,100 @@ typedef struct /***************** Bit definition for SYSCFG_SWPR2 register (SYSCFG SRAM2 write protection register) **********************************************************/ #define SYSCFG_SWPR2_PAGE32_Pos (0U) #define SYSCFG_SWPR2_PAGE32_Msk (0x1UL << SYSCFG_SWPR2_PAGE32_Pos) /*!< 0x00000001 */ -#define SYSCFG_SWPR2_PAGE32 SYSCFG_SWPR2_PAGE32_Msk /*!< SRAM2B Write protection page 0 (0x20038000 – 0x200383FF) */ +#define SYSCFG_SWPR2_PAGE32 SYSCFG_SWPR2_PAGE32_Msk /*!< SRAM2B Write protection page 0 (0x20038000 - 0x200383FF) */ #define SYSCFG_SWPR2_PAGE33_Pos (1U) #define SYSCFG_SWPR2_PAGE33_Msk (0x1UL << SYSCFG_SWPR2_PAGE33_Pos) /*!< 0x00000002 */ -#define SYSCFG_SWPR2_PAGE33 SYSCFG_SWPR2_PAGE33_Msk /*!< SRAM2B Write protection page 1 (0x20038400 – 0x200387FF) */ +#define SYSCFG_SWPR2_PAGE33 SYSCFG_SWPR2_PAGE33_Msk /*!< SRAM2B Write protection page 1 (0x20038400 - 0x200387FF) */ #define SYSCFG_SWPR2_PAGE34_Pos (2U) #define SYSCFG_SWPR2_PAGE34_Msk (0x1UL << SYSCFG_SWPR2_PAGE34_Pos) /*!< 0x00000004 */ -#define SYSCFG_SWPR2_PAGE34 SYSCFG_SWPR2_PAGE34_Msk /*!< SRAM2B Write protection page 2 (0x20038800 – 0x20038bFF) */ +#define SYSCFG_SWPR2_PAGE34 SYSCFG_SWPR2_PAGE34_Msk /*!< SRAM2B Write protection page 2 (0x20038800 - 0x20038bFF) */ #define SYSCFG_SWPR2_PAGE35_Pos (3U) #define SYSCFG_SWPR2_PAGE35_Msk (0x1UL << SYSCFG_SWPR2_PAGE35_Pos) /*!< 0x00000008 */ -#define SYSCFG_SWPR2_PAGE35 SYSCFG_SWPR2_PAGE35_Msk /*!< SRAM2B Write protection page 3 (0x20038C00 – 0x20038FFF) */ +#define SYSCFG_SWPR2_PAGE35 SYSCFG_SWPR2_PAGE35_Msk /*!< SRAM2B Write protection page 3 (0x20038C00 - 0x20038FFF) */ #define SYSCFG_SWPR2_PAGE36_Pos (4U) #define SYSCFG_SWPR2_PAGE36_Msk (0x1UL << SYSCFG_SWPR2_PAGE36_Pos) /*!< 0x00000010 */ -#define SYSCFG_SWPR2_PAGE36 SYSCFG_SWPR2_PAGE36_Msk /*!< SRAM2B Write protection page 4 (0x20039000 – 0x200393FF) */ +#define SYSCFG_SWPR2_PAGE36 SYSCFG_SWPR2_PAGE36_Msk /*!< SRAM2B Write protection page 4 (0x20039000 - 0x200393FF) */ #define SYSCFG_SWPR2_PAGE37_Pos (5U) #define SYSCFG_SWPR2_PAGE37_Msk (0x1UL << SYSCFG_SWPR2_PAGE37_Pos) /*!< 0x00000020 */ -#define SYSCFG_SWPR2_PAGE37 SYSCFG_SWPR2_PAGE37_Msk /*!< SRAM2B Write protection page 5 (0x20039400 – 0x200397FF) */ +#define SYSCFG_SWPR2_PAGE37 SYSCFG_SWPR2_PAGE37_Msk /*!< SRAM2B Write protection page 5 (0x20039400 - 0x200397FF) */ #define SYSCFG_SWPR2_PAGE38_Pos (6U) #define SYSCFG_SWPR2_PAGE38_Msk (0x1UL << SYSCFG_SWPR2_PAGE38_Pos) /*!< 0x00000040 */ -#define SYSCFG_SWPR2_PAGE38 SYSCFG_SWPR2_PAGE38_Msk /*!< SRAM2B Write protection page 6 (0x20039800 – 0x20039BFF) */ +#define SYSCFG_SWPR2_PAGE38 SYSCFG_SWPR2_PAGE38_Msk /*!< SRAM2B Write protection page 6 (0x20039800 - 0x20039BFF) */ #define SYSCFG_SWPR2_PAGE39_Pos (7U) #define SYSCFG_SWPR2_PAGE39_Msk (0x1UL << SYSCFG_SWPR2_PAGE39_Pos) /*!< 0x00000080 */ -#define SYSCFG_SWPR2_PAGE39 SYSCFG_SWPR2_PAGE39_Msk /*!< SRAM2B Write protection page 7 (0x20039C00 – 0x20039FFF) */ +#define SYSCFG_SWPR2_PAGE39 SYSCFG_SWPR2_PAGE39_Msk /*!< SRAM2B Write protection page 7 (0x20039C00 - 0x20039FFF) */ #define SYSCFG_SWPR2_PAGE40_Pos (8U) #define SYSCFG_SWPR2_PAGE40_Msk (0x1UL << SYSCFG_SWPR2_PAGE40_Pos) /*!< 0x00000100 */ -#define SYSCFG_SWPR2_PAGE40 SYSCFG_SWPR2_PAGE40_Msk /*!< SRAM2B Write protection page 8 (0x2003A000 – 0x2003A3FF) */ +#define SYSCFG_SWPR2_PAGE40 SYSCFG_SWPR2_PAGE40_Msk /*!< SRAM2B Write protection page 8 (0x2003A000 - 0x2003A3FF) */ #define SYSCFG_SWPR2_PAGE41_Pos (9U) #define SYSCFG_SWPR2_PAGE41_Msk (0x1UL << SYSCFG_SWPR2_PAGE41_Pos) /*!< 0x00000200 */ -#define SYSCFG_SWPR2_PAGE41 SYSCFG_SWPR2_PAGE41_Msk /*!< SRAM2B Write protection page 9 (0x2003A400 – 0x2003A7FF) */ +#define SYSCFG_SWPR2_PAGE41 SYSCFG_SWPR2_PAGE41_Msk /*!< SRAM2B Write protection page 9 (0x2003A400 - 0x2003A7FF) */ #define SYSCFG_SWPR2_PAGE42_Pos (10U) #define SYSCFG_SWPR2_PAGE42_Msk (0x1UL << SYSCFG_SWPR2_PAGE42_Pos) /*!< 0x00000400 */ -#define SYSCFG_SWPR2_PAGE42 SYSCFG_SWPR2_PAGE42_Msk /*!< SRAM2B Write protection page 10 (0x2003A800 – 0x2003ABFF) */ +#define SYSCFG_SWPR2_PAGE42 SYSCFG_SWPR2_PAGE42_Msk /*!< SRAM2B Write protection page 10 (0x2003A800 - 0x2003ABFF) */ #define SYSCFG_SWPR2_PAGE43_Pos (11U) #define SYSCFG_SWPR2_PAGE43_Msk (0x1UL << SYSCFG_SWPR2_PAGE43_Pos) /*!< 0x00000800 */ -#define SYSCFG_SWPR2_PAGE43 SYSCFG_SWPR2_PAGE43_Msk /*!< SRAM2B Write protection page 11 (0x2003AC00 – 0x2003AFFF) */ +#define SYSCFG_SWPR2_PAGE43 SYSCFG_SWPR2_PAGE43_Msk /*!< SRAM2B Write protection page 11 (0x2003AC00 - 0x2003AFFF) */ #define SYSCFG_SWPR2_PAGE44_Pos (12U) #define SYSCFG_SWPR2_PAGE44_Msk (0x1UL << SYSCFG_SWPR2_PAGE44_Pos) /*!< 0x00001000 */ -#define SYSCFG_SWPR2_PAGE44 SYSCFG_SWPR2_PAGE44_Msk /*!< SRAM2B Write protection page 12 (0x2003B000 – 0x2003B3FF) */ +#define SYSCFG_SWPR2_PAGE44 SYSCFG_SWPR2_PAGE44_Msk /*!< SRAM2B Write protection page 12 (0x2003B000 - 0x2003B3FF) */ #define SYSCFG_SWPR2_PAGE45_Pos (13U) #define SYSCFG_SWPR2_PAGE45_Msk (0x1UL << SYSCFG_SWPR2_PAGE45_Pos) /*!< 0x00002000 */ -#define SYSCFG_SWPR2_PAGE45 SYSCFG_SWPR2_PAGE45_Msk /*!< SRAM2B Write protection page 13 (0x2003B400 – 0x2003B7FF) */ +#define SYSCFG_SWPR2_PAGE45 SYSCFG_SWPR2_PAGE45_Msk /*!< SRAM2B Write protection page 13 (0x2003B400 - 0x2003B7FF) */ #define SYSCFG_SWPR2_PAGE46_Pos (14U) #define SYSCFG_SWPR2_PAGE46_Msk (0x1UL << SYSCFG_SWPR2_PAGE46_Pos) /*!< 0x00004000 */ -#define SYSCFG_SWPR2_PAGE46 SYSCFG_SWPR2_PAGE46_Msk /*!< SRAM2B Write protection page 14 (0x2003B800 – 0x2003BBFF) */ +#define SYSCFG_SWPR2_PAGE46 SYSCFG_SWPR2_PAGE46_Msk /*!< SRAM2B Write protection page 14 (0x2003B800 - 0x2003BBFF) */ #define SYSCFG_SWPR2_PAGE47_Pos (15U) #define SYSCFG_SWPR2_PAGE47_Msk (0x1UL << SYSCFG_SWPR2_PAGE47_Pos) /*!< 0x00008000 */ -#define SYSCFG_SWPR2_PAGE47 SYSCFG_SWPR2_PAGE47_Msk /*!< SRAM2B Write protection page 15 (0x2003BC00 – 0x2003BFFF) */ +#define SYSCFG_SWPR2_PAGE47 SYSCFG_SWPR2_PAGE47_Msk /*!< SRAM2B Write protection page 15 (0x2003BC00 - 0x2003BFFF) */ #define SYSCFG_SWPR2_PAGE48_Pos (16U) #define SYSCFG_SWPR2_PAGE48_Msk (0x1UL << SYSCFG_SWPR2_PAGE48_Pos) /*!< 0x00010000 */ -#define SYSCFG_SWPR2_PAGE48 SYSCFG_SWPR2_PAGE48_Msk /*!< SRAM2B Write protection page 16 (0x2003C000 – 0x2003C3FF) */ +#define SYSCFG_SWPR2_PAGE48 SYSCFG_SWPR2_PAGE48_Msk /*!< SRAM2B Write protection page 16 (0x2003C000 - 0x2003C3FF) */ #define SYSCFG_SWPR2_PAGE49_Pos (17U) #define SYSCFG_SWPR2_PAGE49_Msk (0x1UL << SYSCFG_SWPR2_PAGE49_Pos) /*!< 0x00020000 */ -#define SYSCFG_SWPR2_PAGE49 SYSCFG_SWPR2_PAGE49_Msk /*!< SRAM2B Write protection page 17 (0x2003C400 – 0x2003C7FF) */ +#define SYSCFG_SWPR2_PAGE49 SYSCFG_SWPR2_PAGE49_Msk /*!< SRAM2B Write protection page 17 (0x2003C400 - 0x2003C7FF) */ #define SYSCFG_SWPR2_PAGE50_Pos (18U) #define SYSCFG_SWPR2_PAGE50_Msk (0x1UL << SYSCFG_SWPR2_PAGE50_Pos) /*!< 0x00040000 */ -#define SYSCFG_SWPR2_PAGE50 SYSCFG_SWPR2_PAGE50_Msk /*!< SRAM2B Write protection page 18 (0x2003C800 – 0x2003CBFF) */ +#define SYSCFG_SWPR2_PAGE50 SYSCFG_SWPR2_PAGE50_Msk /*!< SRAM2B Write protection page 18 (0x2003C800 - 0x2003CBFF) */ #define SYSCFG_SWPR2_PAGE51_Pos (19U) #define SYSCFG_SWPR2_PAGE51_Msk (0x1UL << SYSCFG_SWPR2_PAGE51_Pos) /*!< 0x00080000 */ -#define SYSCFG_SWPR2_PAGE51 SYSCFG_SWPR2_PAGE51_Msk /*!< SRAM2B Write protection page 19 (0x2003CC00 – 0x2003CFFF) */ +#define SYSCFG_SWPR2_PAGE51 SYSCFG_SWPR2_PAGE51_Msk /*!< SRAM2B Write protection page 19 (0x2003CC00 - 0x2003CFFF) */ #define SYSCFG_SWPR2_PAGE52_Pos (20U) #define SYSCFG_SWPR2_PAGE52_Msk (0x1UL << SYSCFG_SWPR2_PAGE52_Pos) /*!< 0x00100000 */ -#define SYSCFG_SWPR2_PAGE52 SYSCFG_SWPR2_PAGE52_Msk /*!< SRAM2B Write protection page 20 (0x2003D000 – 0x2003D3FF) */ +#define SYSCFG_SWPR2_PAGE52 SYSCFG_SWPR2_PAGE52_Msk /*!< SRAM2B Write protection page 20 (0x2003D000 - 0x2003D3FF) */ #define SYSCFG_SWPR2_PAGE53_Pos (21U) #define SYSCFG_SWPR2_PAGE53_Msk (0x1UL << SYSCFG_SWPR2_PAGE53_Pos) /*!< 0x00200000 */ -#define SYSCFG_SWPR2_PAGE53 SYSCFG_SWPR2_PAGE53_Msk /*!< SRAM2B Write protection page 21 (0x2003D400 – 0x2003D7FF) */ +#define SYSCFG_SWPR2_PAGE53 SYSCFG_SWPR2_PAGE53_Msk /*!< SRAM2B Write protection page 21 (0x2003D400 - 0x2003D7FF) */ #define SYSCFG_SWPR2_PAGE54_Pos (22U) #define SYSCFG_SWPR2_PAGE54_Msk (0x1UL << SYSCFG_SWPR2_PAGE54_Pos) /*!< 0x00400000 */ -#define SYSCFG_SWPR2_PAGE54 SYSCFG_SWPR2_PAGE54_Msk /*!< SRAM2B Write protection page 22 (0x2003D800 – 0x2003DBFF) */ +#define SYSCFG_SWPR2_PAGE54 SYSCFG_SWPR2_PAGE54_Msk /*!< SRAM2B Write protection page 22 (0x2003D800 - 0x2003DBFF) */ #define SYSCFG_SWPR2_PAGE55_Pos (23U) #define SYSCFG_SWPR2_PAGE55_Msk (0x1UL << SYSCFG_SWPR2_PAGE55_Pos) /*!< 0x00800000 */ -#define SYSCFG_SWPR2_PAGE55 SYSCFG_SWPR2_PAGE55_Msk /*!< SRAM2B Write protection page 23 (0x2003DC00 – 0x2003DFFF) */ +#define SYSCFG_SWPR2_PAGE55 SYSCFG_SWPR2_PAGE55_Msk /*!< SRAM2B Write protection page 23 (0x2003DC00 - 0x2003DFFF) */ #define SYSCFG_SWPR2_PAGE56_Pos (24U) #define SYSCFG_SWPR2_PAGE56_Msk (0x1UL << SYSCFG_SWPR2_PAGE56_Pos) /*!< 0x01000000 */ -#define SYSCFG_SWPR2_PAGE56 SYSCFG_SWPR2_PAGE56_Msk /*!< SRAM2B Write protection page 24 (0x2003E000 – 0x2003E3FF) */ +#define SYSCFG_SWPR2_PAGE56 SYSCFG_SWPR2_PAGE56_Msk /*!< SRAM2B Write protection page 24 (0x2003E000 - 0x2003E3FF) */ #define SYSCFG_SWPR2_PAGE57_Pos (25U) #define SYSCFG_SWPR2_PAGE57_Msk (0x1UL << SYSCFG_SWPR2_PAGE57_Pos) /*!< 0x02000000 */ -#define SYSCFG_SWPR2_PAGE57 SYSCFG_SWPR2_PAGE57_Msk /*!< SRAM2B Write protection page 25 (0x2003E400 – 0x2003E7FF) */ +#define SYSCFG_SWPR2_PAGE57 SYSCFG_SWPR2_PAGE57_Msk /*!< SRAM2B Write protection page 25 (0x2003E400 - 0x2003E7FF) */ #define SYSCFG_SWPR2_PAGE58_Pos (26U) #define SYSCFG_SWPR2_PAGE58_Msk (0x1UL << SYSCFG_SWPR2_PAGE58_Pos) /*!< 0x04000000 */ -#define SYSCFG_SWPR2_PAGE58 SYSCFG_SWPR2_PAGE58_Msk /*!< SRAM2B Write protection page 26 (0x2003E800 – 0x2003EBFF) */ +#define SYSCFG_SWPR2_PAGE58 SYSCFG_SWPR2_PAGE58_Msk /*!< SRAM2B Write protection page 26 (0x2003E800 - 0x2003EBFF) */ #define SYSCFG_SWPR2_PAGE59_Pos (27U) #define SYSCFG_SWPR2_PAGE59_Msk (0x1UL << SYSCFG_SWPR2_PAGE59_Pos) /*!< 0x08000000 */ -#define SYSCFG_SWPR2_PAGE59 SYSCFG_SWPR2_PAGE59_Msk /*!< SRAM2B Write protection page 27 (0x2003EC00 – 0x2003EFFF) */ +#define SYSCFG_SWPR2_PAGE59 SYSCFG_SWPR2_PAGE59_Msk /*!< SRAM2B Write protection page 27 (0x2003EC00 - 0x2003EFFF) */ #define SYSCFG_SWPR2_PAGE60_Pos (28U) #define SYSCFG_SWPR2_PAGE60_Msk (0x1UL << SYSCFG_SWPR2_PAGE60_Pos) /*!< 0x10000000 */ -#define SYSCFG_SWPR2_PAGE60 SYSCFG_SWPR2_PAGE60_Msk /*!< SRAM2B Write protection page 28 (0x2003F000 – 0x2003F3FF) */ +#define SYSCFG_SWPR2_PAGE60 SYSCFG_SWPR2_PAGE60_Msk /*!< SRAM2B Write protection page 28 (0x2003F000 - 0x2003F3FF) */ #define SYSCFG_SWPR2_PAGE61_Pos (29U) #define SYSCFG_SWPR2_PAGE61_Msk (0x1UL << SYSCFG_SWPR2_PAGE61_Pos) /*!< 0x20000000 */ -#define SYSCFG_SWPR2_PAGE61 SYSCFG_SWPR2_PAGE61_Msk /*!< SRAM2B Write protection page 29 (0x2003F400 – 0x2003F7FF) */ +#define SYSCFG_SWPR2_PAGE61 SYSCFG_SWPR2_PAGE61_Msk /*!< SRAM2B Write protection page 29 (0x2003F400 - 0x2003F7FF) */ #define SYSCFG_SWPR2_PAGE62_Pos (30U) #define SYSCFG_SWPR2_PAGE62_Msk (0x1UL << SYSCFG_SWPR2_PAGE62_Pos) /*!< 0x40000000 */ -#define SYSCFG_SWPR2_PAGE62 SYSCFG_SWPR2_PAGE62_Msk /*!< SRAM2B Write protection page 30 (0x2003F800 – 0x2003FBFF) */ +#define SYSCFG_SWPR2_PAGE62 SYSCFG_SWPR2_PAGE62_Msk /*!< SRAM2B Write protection page 30 (0x2003F800 - 0x2003FBFF) */ #define SYSCFG_SWPR2_PAGE63_Pos (31U) #define SYSCFG_SWPR2_PAGE63_Msk (0x1UL << SYSCFG_SWPR2_PAGE63_Pos) /*!< 0x80000000 */ -#define SYSCFG_SWPR2_PAGE63 SYSCFG_SWPR2_PAGE63_Msk /*!< SRAM2B Write protection page 31 (0x2003FC00 – 0x2003FFFF) */ +#define SYSCFG_SWPR2_PAGE63 SYSCFG_SWPR2_PAGE63_Msk /*!< SRAM2B Write protection page 31 (0x2003FC00 - 0x2003FFFF) */ /***************** Bit definition for SYSCFG_IMR1 register (Interrupt masks control and status register on CPU1 - part 1) *******************************************/ #define SYSCFG_IMR1_TIM1IM_Pos (13U) @@ -12777,5 +12777,3 @@ typedef struct /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBxx/Include/stm32wb50xx.h b/system/Drivers/CMSIS/Device/ST/STM32WBxx/Include/stm32wb50xx.h index 933473ab43..37843535e0 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32WBxx/Include/stm32wb50xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32WBxx/Include/stm32wb50xx.h @@ -432,7 +432,7 @@ uint32_t RESERVED6; /*!< Reserved, __IO uint32_t HSECR; /*!< RCC HSE Clock Register, Address offset: 0x9C */ uint32_t RESERVED7[26]; /*!< Reserved, Address offset: 0xA0-0x104 */ __IO uint32_t EXTCFGR; /*!< RCC Extended Clock Recovery Register, Address offset: 0x108 */ -uint32_t RESERVED8[15]; /*!< Reserved, Address offset: 0x10C-0x144 */ +uint32_t RESERVED8[15]; /*!< Reserved, Address offset: 0x10C-0x144 */ __IO uint32_t C2AHB1ENR; /*!< RRCC AHB1 peripheral CPU2 clocks enable register, Address offset: 0x148 */ __IO uint32_t C2AHB2ENR; /*!< RCC AHB2 peripheral CPU2 clocks enable register, Address offset: 0x14C */ __IO uint32_t C2AHB3ENR; /*!< RCC AHB3 & AHB4 peripheral CPU2 clocks enable register,, Address offset: 0x150 */ @@ -753,10 +753,10 @@ typedef struct /*!< Memory, OTP and Option bytes */ /* Base addresses */ -#define SYSTEM_MEMORY_BASE (0x1FFF0000UL) /*!< System Memory : 28Kb (0x1FFF0000 – 0x1FFF6FFF) */ -#define OTP_AREA_BASE (0x1FFF7000UL) /*!< OTP area : 1kB (0x1FFF7000 – 0x1FFF73FF) */ -#define OPTION_BYTE_BASE (0x1FFF8000UL) /*!< Option Bytes : 4kB (0x1FFF8000 – 0x1FFF8FFF) */ -#define ENGI_BYTE_BASE (0x1FFF7400UL) /*!< Engi Bytes : 3kB (0x1FFF7400 – 0x1FFF7FFF) */ +#define SYSTEM_MEMORY_BASE (0x1FFF0000UL) /*!< System Memory : 28Kb (0x1FFF0000 - 0x1FFF6FFF) */ +#define OTP_AREA_BASE (0x1FFF7000UL) /*!< OTP area : 1kB (0x1FFF7000 - 0x1FFF73FF) */ +#define OPTION_BYTE_BASE (0x1FFF8000UL) /*!< Option Bytes : 4kB (0x1FFF8000 - 0x1FFF8FFF) */ +#define ENGI_BYTE_BASE (0x1FFF7400UL) /*!< Engi Bytes : 3kB (0x1FFF7400 - 0x1FFF7FFF) */ #define SRAM1_BASE SRAM_BASE /*!< SRAM1(up to 64 KB) base address */ #define SRAM2A_BASE (SRAM_BASE + 0x00030000UL)/*!< SRAM2A(32 KB) base address */ @@ -769,14 +769,14 @@ typedef struct #define SRAM2B_SIZE 0x00008000UL /*!< SRAM2b default size : 32 kB */ /* End addresses */ -#define SRAM1_END_ADDR (0x2000FFFFUL) /*!< SRAM1 : 64KB (0x20000000 – 0x2000FFFF) */ -#define SRAM2A_END_ADDR (0x20037FFFUL) /*!< SRAM2a (backup) : 32KB (0x20030000 – 0x20037FFF) */ -#define SRAM2B_END_ADDR (0x2003FFFFUL) /*!< SRAM2b (non-backup) : 32KB (0x20038000 – 0x2003FFFF) */ +#define SRAM1_END_ADDR (0x2000FFFFUL) /*!< SRAM1 : 64KB (0x20000000 - 0x2000FFFF) */ +#define SRAM2A_END_ADDR (0x20037FFFUL) /*!< SRAM2a (backup) : 32KB (0x20030000 - 0x20037FFF) */ +#define SRAM2B_END_ADDR (0x2003FFFFUL) /*!< SRAM2b (non-backup) : 32KB (0x20038000 - 0x2003FFFF) */ -#define SYSTEM_MEMORY_END_ADDR (0x1FFF6FFFUL) /*!< System Memory : 28KB (0x1FFF0000 – 0x1FFF6FFF) */ -#define OTP_AREA_END_ADDR (0x1FFF73FFUL) /*!< OTP area : 1KB (0x1FFF7000 – 0x1FFF73FF) */ -#define OPTION_BYTE_END_ADDR (0x1FFF8FFFUL) /*!< Option Bytes : 4KB (0x1FFF8000 – 0x1FFF8FFF) */ -#define ENGI_BYTE_END_ADDR (0x1FFF7FFFUL) /*!< Engi Bytes : 3kB (0x1FFF7400 – 0x1FFF7FFF) */ +#define SYSTEM_MEMORY_END_ADDR (0x1FFF6FFFUL) /*!< System Memory : 28KB (0x1FFF0000 - 0x1FFF6FFF) */ +#define OTP_AREA_END_ADDR (0x1FFF73FFUL) /*!< OTP area : 1KB (0x1FFF7000 - 0x1FFF73FF) */ +#define OPTION_BYTE_END_ADDR (0x1FFF8FFFUL) /*!< Option Bytes : 4KB (0x1FFF8000 - 0x1FFF8FFF) */ +#define ENGI_BYTE_END_ADDR (0x1FFF7FFFUL) /*!< Engi Bytes : 3kB (0x1FFF7400 - 0x1FFF7FFF) */ /*!< Peripheral memory map */ #define APB1PERIPH_BASE PERIPH_BASE @@ -1101,7 +1101,7 @@ typedef struct #define ADC_CFGR_ALIGN_Pos (5U) #define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00000020 */ -#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */ +#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignment */ #define ADC_CFGR_EXTSEL_Pos (6U) #define ADC_CFGR_EXTSEL_Msk (0xFUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003C0 */ @@ -3522,12 +3522,12 @@ typedef struct /* Arithmetic addition output data */ #define PKA_ARITHMETIC_ADD_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ -/* Arithmetic substraction input data */ +/* Arithmetic subtraction input data */ #define PKA_ARITHMETIC_SUB_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ #define PKA_ARITHMETIC_SUB_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ #define PKA_ARITHMETIC_SUB_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ -/* Arithmetic substraction output data */ +/* Arithmetic subtraction output data */ #define PKA_ARITHMETIC_SUB_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ /* Arithmetic multiplication input data */ @@ -3563,13 +3563,13 @@ typedef struct /* Modular inversion output data */ #define PKA_MODULAR_INV_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ -/* Modular substraction input data */ +/* Modular subtraction input data */ #define PKA_MODULAR_SUB_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ #define PKA_MODULAR_SUB_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ #define PKA_MODULAR_SUB_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ #define PKA_MODULAR_SUB_IN_OP3_MOD ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 */ -/* Modular substraction output data */ +/* Modular subtraction output data */ #define PKA_MODULAR_SUB_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ /* Montgomery multiplication input data */ @@ -7495,10 +7495,10 @@ typedef struct #define RTC_CR_OSEL_1 (0x2U << RTC_CR_OSEL_Pos) /*!< 0x00400000 */ #define RTC_CR_POL_Pos (20U) #define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */ -#define RTC_CR_POL RTC_CR_POL_Msk /*!< Ouput polarity */ +#define RTC_CR_POL RTC_CR_POL_Msk /*!< Output polarity */ #define RTC_CR_COSEL_Pos (19U) #define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ -#define RTC_CR_COSEL RTC_CR_COSEL_Msk /*!< Calibration ouput selection */ +#define RTC_CR_COSEL RTC_CR_COSEL_Msk /*!< Calibration output selection */ #define RTC_CR_BKP_Pos (18U) #define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */ #define RTC_CR_BKP RTC_CR_BKP_Msk /*!< Backup */ @@ -7767,7 +7767,7 @@ typedef struct /******************** Bits definition for RTC_SHIFTR register ***************/ #define RTC_SHIFTR_SUBFS_Pos (0U) #define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */ -#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk /*!< Substract a fraction of a second */ +#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk /*!< Subtract a fraction of a second */ #define RTC_SHIFTR_ADD1S_Pos (31U) #define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */ #define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk /*!< Add on second */ @@ -8467,100 +8467,100 @@ typedef struct /***************** Bit definition for SYSCFG_SWPR1 register (SYSCFG SRAM2A write protection register) *********************************************************/ #define SYSCFG_SWPR1_PAGE0_Pos (0U) #define SYSCFG_SWPR1_PAGE0_Msk (0x1UL << SYSCFG_SWPR1_PAGE0_Pos) /*!< 0x00000001 */ -#define SYSCFG_SWPR1_PAGE0 SYSCFG_SWPR1_PAGE0_Msk /*!< SRAM2A Write protection page 0 (0x20030000 – 0x200303FF) */ +#define SYSCFG_SWPR1_PAGE0 SYSCFG_SWPR1_PAGE0_Msk /*!< SRAM2A Write protection page 0 (0x20030000 - 0x200303FF) */ #define SYSCFG_SWPR1_PAGE1_Pos (1U) #define SYSCFG_SWPR1_PAGE1_Msk (0x1UL << SYSCFG_SWPR1_PAGE1_Pos) /*!< 0x00000002 */ -#define SYSCFG_SWPR1_PAGE1 SYSCFG_SWPR1_PAGE1_Msk /*!< SRAM2A Write protection page 1 (0x20030400 – 0x200307FF) */ +#define SYSCFG_SWPR1_PAGE1 SYSCFG_SWPR1_PAGE1_Msk /*!< SRAM2A Write protection page 1 (0x20030400 - 0x200307FF) */ #define SYSCFG_SWPR1_PAGE2_Pos (2U) #define SYSCFG_SWPR1_PAGE2_Msk (0x1UL << SYSCFG_SWPR1_PAGE2_Pos) /*!< 0x00000004 */ -#define SYSCFG_SWPR1_PAGE2 SYSCFG_SWPR1_PAGE2_Msk /*!< SRAM2A Write protection page 2 (0x20030800 – 0x20030BFF) */ +#define SYSCFG_SWPR1_PAGE2 SYSCFG_SWPR1_PAGE2_Msk /*!< SRAM2A Write protection page 2 (0x20030800 - 0x20030BFF) */ #define SYSCFG_SWPR1_PAGE3_Pos (3U) #define SYSCFG_SWPR1_PAGE3_Msk (0x1UL << SYSCFG_SWPR1_PAGE3_Pos) /*!< 0x00000008 */ -#define SYSCFG_SWPR1_PAGE3 SYSCFG_SWPR1_PAGE3_Msk /*!< SRAM2A Write protection page 3 (0x20030C00 – 0x20030FFF) */ +#define SYSCFG_SWPR1_PAGE3 SYSCFG_SWPR1_PAGE3_Msk /*!< SRAM2A Write protection page 3 (0x20030C00 - 0x20030FFF) */ #define SYSCFG_SWPR1_PAGE4_Pos (4U) #define SYSCFG_SWPR1_PAGE4_Msk (0x1UL << SYSCFG_SWPR1_PAGE4_Pos) /*!< 0x00000010 */ -#define SYSCFG_SWPR1_PAGE4 SYSCFG_SWPR1_PAGE4_Msk /*!< SRAM2A Write protection page 4 (0x20031000 – 0x200313FF) */ +#define SYSCFG_SWPR1_PAGE4 SYSCFG_SWPR1_PAGE4_Msk /*!< SRAM2A Write protection page 4 (0x20031000 - 0x200313FF) */ #define SYSCFG_SWPR1_PAGE5_Pos (5U) #define SYSCFG_SWPR1_PAGE5_Msk (0x1UL << SYSCFG_SWPR1_PAGE5_Pos) /*!< 0x00000020 */ -#define SYSCFG_SWPR1_PAGE5 SYSCFG_SWPR1_PAGE5_Msk /*!< SRAM2A Write protection page 5 (0x20031400 – 0x200317FF) */ +#define SYSCFG_SWPR1_PAGE5 SYSCFG_SWPR1_PAGE5_Msk /*!< SRAM2A Write protection page 5 (0x20031400 - 0x200317FF) */ #define SYSCFG_SWPR1_PAGE6_Pos (6U) #define SYSCFG_SWPR1_PAGE6_Msk (0x1UL << SYSCFG_SWPR1_PAGE6_Pos) /*!< 0x00000040 */ -#define SYSCFG_SWPR1_PAGE6 SYSCFG_SWPR1_PAGE6_Msk /*!< SRAM2A Write protection page 6 (0x20031800 – 0x20031BFF) */ +#define SYSCFG_SWPR1_PAGE6 SYSCFG_SWPR1_PAGE6_Msk /*!< SRAM2A Write protection page 6 (0x20031800 - 0x20031BFF) */ #define SYSCFG_SWPR1_PAGE7_Pos (7U) #define SYSCFG_SWPR1_PAGE7_Msk (0x1UL << SYSCFG_SWPR1_PAGE7_Pos) /*!< 0x00000080 */ -#define SYSCFG_SWPR1_PAGE7 SYSCFG_SWPR1_PAGE7_Msk /*!< SRAM2A Write protection page 7 (0x20031C00 – 0x20031FFF) */ +#define SYSCFG_SWPR1_PAGE7 SYSCFG_SWPR1_PAGE7_Msk /*!< SRAM2A Write protection page 7 (0x20031C00 - 0x20031FFF) */ #define SYSCFG_SWPR1_PAGE8_Pos (8U) #define SYSCFG_SWPR1_PAGE8_Msk (0x1UL << SYSCFG_SWPR1_PAGE8_Pos) /*!< 0x00000100 */ -#define SYSCFG_SWPR1_PAGE8 SYSCFG_SWPR1_PAGE8_Msk /*!< SRAM2A Write protection page 8 (0x20032000 – 0x200323FF) */ +#define SYSCFG_SWPR1_PAGE8 SYSCFG_SWPR1_PAGE8_Msk /*!< SRAM2A Write protection page 8 (0x20032000 - 0x200323FF) */ #define SYSCFG_SWPR1_PAGE9_Pos (9U) #define SYSCFG_SWPR1_PAGE9_Msk (0x1UL << SYSCFG_SWPR1_PAGE9_Pos) /*!< 0x00000200 */ -#define SYSCFG_SWPR1_PAGE9 SYSCFG_SWPR1_PAGE9_Msk /*!< SRAM2A Write protection page 9 (0x20032400 – 0x200327FF) */ +#define SYSCFG_SWPR1_PAGE9 SYSCFG_SWPR1_PAGE9_Msk /*!< SRAM2A Write protection page 9 (0x20032400 - 0x200327FF) */ #define SYSCFG_SWPR1_PAGE10_Pos (10U) #define SYSCFG_SWPR1_PAGE10_Msk (0x1UL << SYSCFG_SWPR1_PAGE10_Pos) /*!< 0x00000400 */ -#define SYSCFG_SWPR1_PAGE10 SYSCFG_SWPR1_PAGE10_Msk /*!< SRAM2A Write protection page 10 (0x20032800 – 0x20032BFF) */ +#define SYSCFG_SWPR1_PAGE10 SYSCFG_SWPR1_PAGE10_Msk /*!< SRAM2A Write protection page 10 (0x20032800 - 0x20032BFF) */ #define SYSCFG_SWPR1_PAGE11_Pos (11U) #define SYSCFG_SWPR1_PAGE11_Msk (0x1UL << SYSCFG_SWPR1_PAGE11_Pos) /*!< 0x00000800 */ -#define SYSCFG_SWPR1_PAGE11 SYSCFG_SWPR1_PAGE11_Msk /*!< SRAM2A Write protection page 11 (0x20032C00 – 0x20032FFF) */ +#define SYSCFG_SWPR1_PAGE11 SYSCFG_SWPR1_PAGE11_Msk /*!< SRAM2A Write protection page 11 (0x20032C00 - 0x20032FFF) */ #define SYSCFG_SWPR1_PAGE12_Pos (12U) #define SYSCFG_SWPR1_PAGE12_Msk (0x1UL << SYSCFG_SWPR1_PAGE12_Pos) /*!< 0x00001000 */ -#define SYSCFG_SWPR1_PAGE12 SYSCFG_SWPR1_PAGE12_Msk /*!< SRAM2A Write protection page 12 (0x20033000 – 0x200333FF) */ +#define SYSCFG_SWPR1_PAGE12 SYSCFG_SWPR1_PAGE12_Msk /*!< SRAM2A Write protection page 12 (0x20033000 - 0x200333FF) */ #define SYSCFG_SWPR1_PAGE13_Pos (13U) #define SYSCFG_SWPR1_PAGE13_Msk (0x1UL << SYSCFG_SWPR1_PAGE13_Pos) /*!< 0x00002000 */ -#define SYSCFG_SWPR1_PAGE13 SYSCFG_SWPR1_PAGE13_Msk /*!< SRAM2A Write protection page 13 (0x20033400 – 0x200337FF) */ +#define SYSCFG_SWPR1_PAGE13 SYSCFG_SWPR1_PAGE13_Msk /*!< SRAM2A Write protection page 13 (0x20033400 - 0x200337FF) */ #define SYSCFG_SWPR1_PAGE14_Pos (14U) #define SYSCFG_SWPR1_PAGE14_Msk (0x1UL << SYSCFG_SWPR1_PAGE14_Pos) /*!< 0x00004000 */ -#define SYSCFG_SWPR1_PAGE14 SYSCFG_SWPR1_PAGE14_Msk /*!< SRAM2A Write protection page 14 (0x20033800 – 0x20033BFF) */ +#define SYSCFG_SWPR1_PAGE14 SYSCFG_SWPR1_PAGE14_Msk /*!< SRAM2A Write protection page 14 (0x20033800 - 0x20033BFF) */ #define SYSCFG_SWPR1_PAGE15_Pos (15U) #define SYSCFG_SWPR1_PAGE15_Msk (0x1UL << SYSCFG_SWPR1_PAGE15_Pos) /*!< 0x00008000 */ -#define SYSCFG_SWPR1_PAGE15 SYSCFG_SWPR1_PAGE15_Msk /*!< SRAM2A Write protection page 15 (0x20033C00 – 0x20033FFF) */ +#define SYSCFG_SWPR1_PAGE15 SYSCFG_SWPR1_PAGE15_Msk /*!< SRAM2A Write protection page 15 (0x20033C00 - 0x20033FFF) */ #define SYSCFG_SWPR1_PAGE16_Pos (16U) #define SYSCFG_SWPR1_PAGE16_Msk (0x1UL << SYSCFG_SWPR1_PAGE16_Pos) /*!< 0x00010000 */ -#define SYSCFG_SWPR1_PAGE16 SYSCFG_SWPR1_PAGE16_Msk /*!< SRAM2A Write protection page 16 (0x20034000 – 0x200343FF) */ +#define SYSCFG_SWPR1_PAGE16 SYSCFG_SWPR1_PAGE16_Msk /*!< SRAM2A Write protection page 16 (0x20034000 - 0x200343FF) */ #define SYSCFG_SWPR1_PAGE17_Pos (17U) #define SYSCFG_SWPR1_PAGE17_Msk (0x1UL << SYSCFG_SWPR1_PAGE17_Pos) /*!< 0x00020000 */ -#define SYSCFG_SWPR1_PAGE17 SYSCFG_SWPR1_PAGE17_Msk /*!< SRAM2A Write protection page 17 (0x20034400 – 0x200347FF) */ +#define SYSCFG_SWPR1_PAGE17 SYSCFG_SWPR1_PAGE17_Msk /*!< SRAM2A Write protection page 17 (0x20034400 - 0x200347FF) */ #define SYSCFG_SWPR1_PAGE18_Pos (18U) #define SYSCFG_SWPR1_PAGE18_Msk (0x1UL << SYSCFG_SWPR1_PAGE18_Pos) /*!< 0x00040000 */ -#define SYSCFG_SWPR1_PAGE18 SYSCFG_SWPR1_PAGE18_Msk /*!< SRAM2A Write protection page 18 (0x20034800 – 0x20034BFF) */ +#define SYSCFG_SWPR1_PAGE18 SYSCFG_SWPR1_PAGE18_Msk /*!< SRAM2A Write protection page 18 (0x20034800 - 0x20034BFF) */ #define SYSCFG_SWPR1_PAGE19_Pos (19U) #define SYSCFG_SWPR1_PAGE19_Msk (0x1UL << SYSCFG_SWPR1_PAGE19_Pos) /*!< 0x00080000 */ -#define SYSCFG_SWPR1_PAGE19 SYSCFG_SWPR1_PAGE19_Msk /*!< SRAM2A Write protection page 19 (0x20034C00 – 0x20034FFF) */ +#define SYSCFG_SWPR1_PAGE19 SYSCFG_SWPR1_PAGE19_Msk /*!< SRAM2A Write protection page 19 (0x20034C00 - 0x20034FFF) */ #define SYSCFG_SWPR1_PAGE20_Pos (20U) #define SYSCFG_SWPR1_PAGE20_Msk (0x1UL << SYSCFG_SWPR1_PAGE20_Pos) /*!< 0x00100000 */ -#define SYSCFG_SWPR1_PAGE20 SYSCFG_SWPR1_PAGE20_Msk /*!< SRAM2A Write protection page 20 (0x20035000 – 0x200353FF) */ +#define SYSCFG_SWPR1_PAGE20 SYSCFG_SWPR1_PAGE20_Msk /*!< SRAM2A Write protection page 20 (0x20035000 - 0x200353FF) */ #define SYSCFG_SWPR1_PAGE21_Pos (21U) #define SYSCFG_SWPR1_PAGE21_Msk (0x1UL << SYSCFG_SWPR1_PAGE21_Pos) /*!< 0x00200000 */ -#define SYSCFG_SWPR1_PAGE21 SYSCFG_SWPR1_PAGE21_Msk /*!< SRAM2A Write protection page 21 (0x20035400 – 0x200357FF) */ +#define SYSCFG_SWPR1_PAGE21 SYSCFG_SWPR1_PAGE21_Msk /*!< SRAM2A Write protection page 21 (0x20035400 - 0x200357FF) */ #define SYSCFG_SWPR1_PAGE22_Pos (22U) #define SYSCFG_SWPR1_PAGE22_Msk (0x1UL << SYSCFG_SWPR1_PAGE22_Pos) /*!< 0x00400000 */ -#define SYSCFG_SWPR1_PAGE22 SYSCFG_SWPR1_PAGE22_Msk /*!< SRAM2A Write protection page 22 (0x20035800 – 0x20035BFF) */ +#define SYSCFG_SWPR1_PAGE22 SYSCFG_SWPR1_PAGE22_Msk /*!< SRAM2A Write protection page 22 (0x20035800 - 0x20035BFF) */ #define SYSCFG_SWPR1_PAGE23_Pos (23U) #define SYSCFG_SWPR1_PAGE23_Msk (0x1UL << SYSCFG_SWPR1_PAGE23_Pos) /*!< 0x00800000 */ -#define SYSCFG_SWPR1_PAGE23 SYSCFG_SWPR1_PAGE23_Msk /*!< SRAM2A Write protection page 23 (0x20035C00 – 0x20035FFF) */ +#define SYSCFG_SWPR1_PAGE23 SYSCFG_SWPR1_PAGE23_Msk /*!< SRAM2A Write protection page 23 (0x20035C00 - 0x20035FFF) */ #define SYSCFG_SWPR1_PAGE24_Pos (24U) #define SYSCFG_SWPR1_PAGE24_Msk (0x1UL << SYSCFG_SWPR1_PAGE24_Pos) /*!< 0x01000000 */ -#define SYSCFG_SWPR1_PAGE24 SYSCFG_SWPR1_PAGE24_Msk /*!< SRAM2A Write protection page 24 (0x20036000 – 0x200363FF) */ +#define SYSCFG_SWPR1_PAGE24 SYSCFG_SWPR1_PAGE24_Msk /*!< SRAM2A Write protection page 24 (0x20036000 - 0x200363FF) */ #define SYSCFG_SWPR1_PAGE25_Pos (25U) #define SYSCFG_SWPR1_PAGE25_Msk (0x1UL << SYSCFG_SWPR1_PAGE25_Pos) /*!< 0x02000000 */ -#define SYSCFG_SWPR1_PAGE25 SYSCFG_SWPR1_PAGE25_Msk /*!< SRAM2A Write protection page 25 (0x20036400 – 0x200367FF) */ +#define SYSCFG_SWPR1_PAGE25 SYSCFG_SWPR1_PAGE25_Msk /*!< SRAM2A Write protection page 25 (0x20036400 - 0x200367FF) */ #define SYSCFG_SWPR1_PAGE26_Pos (26U) #define SYSCFG_SWPR1_PAGE26_Msk (0x1UL << SYSCFG_SWPR1_PAGE26_Pos) /*!< 0x04000000 */ -#define SYSCFG_SWPR1_PAGE26 SYSCFG_SWPR1_PAGE26_Msk /*!< SRAM2A Write protection page 26 (0x20036800 – 0x20036BFF) */ +#define SYSCFG_SWPR1_PAGE26 SYSCFG_SWPR1_PAGE26_Msk /*!< SRAM2A Write protection page 26 (0x20036800 - 0x20036BFF) */ #define SYSCFG_SWPR1_PAGE27_Pos (27U) #define SYSCFG_SWPR1_PAGE27_Msk (0x1UL << SYSCFG_SWPR1_PAGE27_Pos) /*!< 0x08000000 */ -#define SYSCFG_SWPR1_PAGE27 SYSCFG_SWPR1_PAGE27_Msk /*!< SRAM2A Write protection page 27 (0x20036C00 – 0x20036FFF) */ +#define SYSCFG_SWPR1_PAGE27 SYSCFG_SWPR1_PAGE27_Msk /*!< SRAM2A Write protection page 27 (0x20036C00 - 0x20036FFF) */ #define SYSCFG_SWPR1_PAGE28_Pos (28U) #define SYSCFG_SWPR1_PAGE28_Msk (0x1UL << SYSCFG_SWPR1_PAGE28_Pos) /*!< 0x10000000 */ -#define SYSCFG_SWPR1_PAGE28 SYSCFG_SWPR1_PAGE28_Msk /*!< SRAM2A Write protection page 28 (0x20037000 – 0x200373FF) */ +#define SYSCFG_SWPR1_PAGE28 SYSCFG_SWPR1_PAGE28_Msk /*!< SRAM2A Write protection page 28 (0x20037000 - 0x200373FF) */ #define SYSCFG_SWPR1_PAGE29_Pos (29U) #define SYSCFG_SWPR1_PAGE29_Msk (0x1UL << SYSCFG_SWPR1_PAGE29_Pos) /*!< 0x20000000 */ -#define SYSCFG_SWPR1_PAGE29 SYSCFG_SWPR1_PAGE29_Msk /*!< SRAM2A Write protection page 29 (0x20037400 – 0x200377FF) */ +#define SYSCFG_SWPR1_PAGE29 SYSCFG_SWPR1_PAGE29_Msk /*!< SRAM2A Write protection page 29 (0x20037400 - 0x200377FF) */ #define SYSCFG_SWPR1_PAGE30_Pos (30U) #define SYSCFG_SWPR1_PAGE30_Msk (0x1UL << SYSCFG_SWPR1_PAGE30_Pos) /*!< 0x40000000 */ -#define SYSCFG_SWPR1_PAGE30 SYSCFG_SWPR1_PAGE30_Msk /*!< SRAM2A Write protection page 30 (0x20037800 – 0x20037BFF) */ +#define SYSCFG_SWPR1_PAGE30 SYSCFG_SWPR1_PAGE30_Msk /*!< SRAM2A Write protection page 30 (0x20037800 - 0x20037BFF) */ #define SYSCFG_SWPR1_PAGE31_Pos (31U) #define SYSCFG_SWPR1_PAGE31_Msk (0x1UL << SYSCFG_SWPR1_PAGE31_Pos) /*!< 0x80000000 */ -#define SYSCFG_SWPR1_PAGE31 SYSCFG_SWPR1_PAGE31_Msk /*!< SRAM2A Write protection page 31 (0x20037C00 – 0x20037FFF) */ +#define SYSCFG_SWPR1_PAGE31 SYSCFG_SWPR1_PAGE31_Msk /*!< SRAM2A Write protection page 31 (0x20037C00 - 0x20037FFF) */ /***************** Bit definition for SYSCFG_SKR register (SYSCFG SRAM2 key register) *************************************************************************/ #define SYSCFG_SKR_KEY_Pos (0U) @@ -8570,100 +8570,100 @@ typedef struct /***************** Bit definition for SYSCFG_SWPR2 register (SYSCFG SRAM2 write protection register) **********************************************************/ #define SYSCFG_SWPR2_PAGE32_Pos (0U) #define SYSCFG_SWPR2_PAGE32_Msk (0x1UL << SYSCFG_SWPR2_PAGE32_Pos) /*!< 0x00000001 */ -#define SYSCFG_SWPR2_PAGE32 SYSCFG_SWPR2_PAGE32_Msk /*!< SRAM2B Write protection page 0 (0x20038000 – 0x200383FF) */ +#define SYSCFG_SWPR2_PAGE32 SYSCFG_SWPR2_PAGE32_Msk /*!< SRAM2B Write protection page 0 (0x20038000 - 0x200383FF) */ #define SYSCFG_SWPR2_PAGE33_Pos (1U) #define SYSCFG_SWPR2_PAGE33_Msk (0x1UL << SYSCFG_SWPR2_PAGE33_Pos) /*!< 0x00000002 */ -#define SYSCFG_SWPR2_PAGE33 SYSCFG_SWPR2_PAGE33_Msk /*!< SRAM2B Write protection page 1 (0x20038400 – 0x200387FF) */ +#define SYSCFG_SWPR2_PAGE33 SYSCFG_SWPR2_PAGE33_Msk /*!< SRAM2B Write protection page 1 (0x20038400 - 0x200387FF) */ #define SYSCFG_SWPR2_PAGE34_Pos (2U) #define SYSCFG_SWPR2_PAGE34_Msk (0x1UL << SYSCFG_SWPR2_PAGE34_Pos) /*!< 0x00000004 */ -#define SYSCFG_SWPR2_PAGE34 SYSCFG_SWPR2_PAGE34_Msk /*!< SRAM2B Write protection page 2 (0x20038800 – 0x20038bFF) */ +#define SYSCFG_SWPR2_PAGE34 SYSCFG_SWPR2_PAGE34_Msk /*!< SRAM2B Write protection page 2 (0x20038800 - 0x20038bFF) */ #define SYSCFG_SWPR2_PAGE35_Pos (3U) #define SYSCFG_SWPR2_PAGE35_Msk (0x1UL << SYSCFG_SWPR2_PAGE35_Pos) /*!< 0x00000008 */ -#define SYSCFG_SWPR2_PAGE35 SYSCFG_SWPR2_PAGE35_Msk /*!< SRAM2B Write protection page 3 (0x20038C00 – 0x20038FFF) */ +#define SYSCFG_SWPR2_PAGE35 SYSCFG_SWPR2_PAGE35_Msk /*!< SRAM2B Write protection page 3 (0x20038C00 - 0x20038FFF) */ #define SYSCFG_SWPR2_PAGE36_Pos (4U) #define SYSCFG_SWPR2_PAGE36_Msk (0x1UL << SYSCFG_SWPR2_PAGE36_Pos) /*!< 0x00000010 */ -#define SYSCFG_SWPR2_PAGE36 SYSCFG_SWPR2_PAGE36_Msk /*!< SRAM2B Write protection page 4 (0x20039000 – 0x200393FF) */ +#define SYSCFG_SWPR2_PAGE36 SYSCFG_SWPR2_PAGE36_Msk /*!< SRAM2B Write protection page 4 (0x20039000 - 0x200393FF) */ #define SYSCFG_SWPR2_PAGE37_Pos (5U) #define SYSCFG_SWPR2_PAGE37_Msk (0x1UL << SYSCFG_SWPR2_PAGE37_Pos) /*!< 0x00000020 */ -#define SYSCFG_SWPR2_PAGE37 SYSCFG_SWPR2_PAGE37_Msk /*!< SRAM2B Write protection page 5 (0x20039400 – 0x200397FF) */ +#define SYSCFG_SWPR2_PAGE37 SYSCFG_SWPR2_PAGE37_Msk /*!< SRAM2B Write protection page 5 (0x20039400 - 0x200397FF) */ #define SYSCFG_SWPR2_PAGE38_Pos (6U) #define SYSCFG_SWPR2_PAGE38_Msk (0x1UL << SYSCFG_SWPR2_PAGE38_Pos) /*!< 0x00000040 */ -#define SYSCFG_SWPR2_PAGE38 SYSCFG_SWPR2_PAGE38_Msk /*!< SRAM2B Write protection page 6 (0x20039800 – 0x20039BFF) */ +#define SYSCFG_SWPR2_PAGE38 SYSCFG_SWPR2_PAGE38_Msk /*!< SRAM2B Write protection page 6 (0x20039800 - 0x20039BFF) */ #define SYSCFG_SWPR2_PAGE39_Pos (7U) #define SYSCFG_SWPR2_PAGE39_Msk (0x1UL << SYSCFG_SWPR2_PAGE39_Pos) /*!< 0x00000080 */ -#define SYSCFG_SWPR2_PAGE39 SYSCFG_SWPR2_PAGE39_Msk /*!< SRAM2B Write protection page 7 (0x20039C00 – 0x20039FFF) */ +#define SYSCFG_SWPR2_PAGE39 SYSCFG_SWPR2_PAGE39_Msk /*!< SRAM2B Write protection page 7 (0x20039C00 - 0x20039FFF) */ #define SYSCFG_SWPR2_PAGE40_Pos (8U) #define SYSCFG_SWPR2_PAGE40_Msk (0x1UL << SYSCFG_SWPR2_PAGE40_Pos) /*!< 0x00000100 */ -#define SYSCFG_SWPR2_PAGE40 SYSCFG_SWPR2_PAGE40_Msk /*!< SRAM2B Write protection page 8 (0x2003A000 – 0x2003A3FF) */ +#define SYSCFG_SWPR2_PAGE40 SYSCFG_SWPR2_PAGE40_Msk /*!< SRAM2B Write protection page 8 (0x2003A000 - 0x2003A3FF) */ #define SYSCFG_SWPR2_PAGE41_Pos (9U) #define SYSCFG_SWPR2_PAGE41_Msk (0x1UL << SYSCFG_SWPR2_PAGE41_Pos) /*!< 0x00000200 */ -#define SYSCFG_SWPR2_PAGE41 SYSCFG_SWPR2_PAGE41_Msk /*!< SRAM2B Write protection page 9 (0x2003A400 – 0x2003A7FF) */ +#define SYSCFG_SWPR2_PAGE41 SYSCFG_SWPR2_PAGE41_Msk /*!< SRAM2B Write protection page 9 (0x2003A400 - 0x2003A7FF) */ #define SYSCFG_SWPR2_PAGE42_Pos (10U) #define SYSCFG_SWPR2_PAGE42_Msk (0x1UL << SYSCFG_SWPR2_PAGE42_Pos) /*!< 0x00000400 */ -#define SYSCFG_SWPR2_PAGE42 SYSCFG_SWPR2_PAGE42_Msk /*!< SRAM2B Write protection page 10 (0x2003A800 – 0x2003ABFF) */ +#define SYSCFG_SWPR2_PAGE42 SYSCFG_SWPR2_PAGE42_Msk /*!< SRAM2B Write protection page 10 (0x2003A800 - 0x2003ABFF) */ #define SYSCFG_SWPR2_PAGE43_Pos (11U) #define SYSCFG_SWPR2_PAGE43_Msk (0x1UL << SYSCFG_SWPR2_PAGE43_Pos) /*!< 0x00000800 */ -#define SYSCFG_SWPR2_PAGE43 SYSCFG_SWPR2_PAGE43_Msk /*!< SRAM2B Write protection page 11 (0x2003AC00 – 0x2003AFFF) */ +#define SYSCFG_SWPR2_PAGE43 SYSCFG_SWPR2_PAGE43_Msk /*!< SRAM2B Write protection page 11 (0x2003AC00 - 0x2003AFFF) */ #define SYSCFG_SWPR2_PAGE44_Pos (12U) #define SYSCFG_SWPR2_PAGE44_Msk (0x1UL << SYSCFG_SWPR2_PAGE44_Pos) /*!< 0x00001000 */ -#define SYSCFG_SWPR2_PAGE44 SYSCFG_SWPR2_PAGE44_Msk /*!< SRAM2B Write protection page 12 (0x2003B000 – 0x2003B3FF) */ +#define SYSCFG_SWPR2_PAGE44 SYSCFG_SWPR2_PAGE44_Msk /*!< SRAM2B Write protection page 12 (0x2003B000 - 0x2003B3FF) */ #define SYSCFG_SWPR2_PAGE45_Pos (13U) #define SYSCFG_SWPR2_PAGE45_Msk (0x1UL << SYSCFG_SWPR2_PAGE45_Pos) /*!< 0x00002000 */ -#define SYSCFG_SWPR2_PAGE45 SYSCFG_SWPR2_PAGE45_Msk /*!< SRAM2B Write protection page 13 (0x2003B400 – 0x2003B7FF) */ +#define SYSCFG_SWPR2_PAGE45 SYSCFG_SWPR2_PAGE45_Msk /*!< SRAM2B Write protection page 13 (0x2003B400 - 0x2003B7FF) */ #define SYSCFG_SWPR2_PAGE46_Pos (14U) #define SYSCFG_SWPR2_PAGE46_Msk (0x1UL << SYSCFG_SWPR2_PAGE46_Pos) /*!< 0x00004000 */ -#define SYSCFG_SWPR2_PAGE46 SYSCFG_SWPR2_PAGE46_Msk /*!< SRAM2B Write protection page 14 (0x2003B800 – 0x2003BBFF) */ +#define SYSCFG_SWPR2_PAGE46 SYSCFG_SWPR2_PAGE46_Msk /*!< SRAM2B Write protection page 14 (0x2003B800 - 0x2003BBFF) */ #define SYSCFG_SWPR2_PAGE47_Pos (15U) #define SYSCFG_SWPR2_PAGE47_Msk (0x1UL << SYSCFG_SWPR2_PAGE47_Pos) /*!< 0x00008000 */ -#define SYSCFG_SWPR2_PAGE47 SYSCFG_SWPR2_PAGE47_Msk /*!< SRAM2B Write protection page 15 (0x2003BC00 – 0x2003BFFF) */ +#define SYSCFG_SWPR2_PAGE47 SYSCFG_SWPR2_PAGE47_Msk /*!< SRAM2B Write protection page 15 (0x2003BC00 - 0x2003BFFF) */ #define SYSCFG_SWPR2_PAGE48_Pos (16U) #define SYSCFG_SWPR2_PAGE48_Msk (0x1UL << SYSCFG_SWPR2_PAGE48_Pos) /*!< 0x00010000 */ -#define SYSCFG_SWPR2_PAGE48 SYSCFG_SWPR2_PAGE48_Msk /*!< SRAM2B Write protection page 16 (0x2003C000 – 0x2003C3FF) */ +#define SYSCFG_SWPR2_PAGE48 SYSCFG_SWPR2_PAGE48_Msk /*!< SRAM2B Write protection page 16 (0x2003C000 - 0x2003C3FF) */ #define SYSCFG_SWPR2_PAGE49_Pos (17U) #define SYSCFG_SWPR2_PAGE49_Msk (0x1UL << SYSCFG_SWPR2_PAGE49_Pos) /*!< 0x00020000 */ -#define SYSCFG_SWPR2_PAGE49 SYSCFG_SWPR2_PAGE49_Msk /*!< SRAM2B Write protection page 17 (0x2003C400 – 0x2003C7FF) */ +#define SYSCFG_SWPR2_PAGE49 SYSCFG_SWPR2_PAGE49_Msk /*!< SRAM2B Write protection page 17 (0x2003C400 - 0x2003C7FF) */ #define SYSCFG_SWPR2_PAGE50_Pos (18U) #define SYSCFG_SWPR2_PAGE50_Msk (0x1UL << SYSCFG_SWPR2_PAGE50_Pos) /*!< 0x00040000 */ -#define SYSCFG_SWPR2_PAGE50 SYSCFG_SWPR2_PAGE50_Msk /*!< SRAM2B Write protection page 18 (0x2003C800 – 0x2003CBFF) */ +#define SYSCFG_SWPR2_PAGE50 SYSCFG_SWPR2_PAGE50_Msk /*!< SRAM2B Write protection page 18 (0x2003C800 - 0x2003CBFF) */ #define SYSCFG_SWPR2_PAGE51_Pos (19U) #define SYSCFG_SWPR2_PAGE51_Msk (0x1UL << SYSCFG_SWPR2_PAGE51_Pos) /*!< 0x00080000 */ -#define SYSCFG_SWPR2_PAGE51 SYSCFG_SWPR2_PAGE51_Msk /*!< SRAM2B Write protection page 19 (0x2003CC00 – 0x2003CFFF) */ +#define SYSCFG_SWPR2_PAGE51 SYSCFG_SWPR2_PAGE51_Msk /*!< SRAM2B Write protection page 19 (0x2003CC00 - 0x2003CFFF) */ #define SYSCFG_SWPR2_PAGE52_Pos (20U) #define SYSCFG_SWPR2_PAGE52_Msk (0x1UL << SYSCFG_SWPR2_PAGE52_Pos) /*!< 0x00100000 */ -#define SYSCFG_SWPR2_PAGE52 SYSCFG_SWPR2_PAGE52_Msk /*!< SRAM2B Write protection page 20 (0x2003D000 – 0x2003D3FF) */ +#define SYSCFG_SWPR2_PAGE52 SYSCFG_SWPR2_PAGE52_Msk /*!< SRAM2B Write protection page 20 (0x2003D000 - 0x2003D3FF) */ #define SYSCFG_SWPR2_PAGE53_Pos (21U) #define SYSCFG_SWPR2_PAGE53_Msk (0x1UL << SYSCFG_SWPR2_PAGE53_Pos) /*!< 0x00200000 */ -#define SYSCFG_SWPR2_PAGE53 SYSCFG_SWPR2_PAGE53_Msk /*!< SRAM2B Write protection page 21 (0x2003D400 – 0x2003D7FF) */ +#define SYSCFG_SWPR2_PAGE53 SYSCFG_SWPR2_PAGE53_Msk /*!< SRAM2B Write protection page 21 (0x2003D400 - 0x2003D7FF) */ #define SYSCFG_SWPR2_PAGE54_Pos (22U) #define SYSCFG_SWPR2_PAGE54_Msk (0x1UL << SYSCFG_SWPR2_PAGE54_Pos) /*!< 0x00400000 */ -#define SYSCFG_SWPR2_PAGE54 SYSCFG_SWPR2_PAGE54_Msk /*!< SRAM2B Write protection page 22 (0x2003D800 – 0x2003DBFF) */ +#define SYSCFG_SWPR2_PAGE54 SYSCFG_SWPR2_PAGE54_Msk /*!< SRAM2B Write protection page 22 (0x2003D800 - 0x2003DBFF) */ #define SYSCFG_SWPR2_PAGE55_Pos (23U) #define SYSCFG_SWPR2_PAGE55_Msk (0x1UL << SYSCFG_SWPR2_PAGE55_Pos) /*!< 0x00800000 */ -#define SYSCFG_SWPR2_PAGE55 SYSCFG_SWPR2_PAGE55_Msk /*!< SRAM2B Write protection page 23 (0x2003DC00 – 0x2003DFFF) */ +#define SYSCFG_SWPR2_PAGE55 SYSCFG_SWPR2_PAGE55_Msk /*!< SRAM2B Write protection page 23 (0x2003DC00 - 0x2003DFFF) */ #define SYSCFG_SWPR2_PAGE56_Pos (24U) #define SYSCFG_SWPR2_PAGE56_Msk (0x1UL << SYSCFG_SWPR2_PAGE56_Pos) /*!< 0x01000000 */ -#define SYSCFG_SWPR2_PAGE56 SYSCFG_SWPR2_PAGE56_Msk /*!< SRAM2B Write protection page 24 (0x2003E000 – 0x2003E3FF) */ +#define SYSCFG_SWPR2_PAGE56 SYSCFG_SWPR2_PAGE56_Msk /*!< SRAM2B Write protection page 24 (0x2003E000 - 0x2003E3FF) */ #define SYSCFG_SWPR2_PAGE57_Pos (25U) #define SYSCFG_SWPR2_PAGE57_Msk (0x1UL << SYSCFG_SWPR2_PAGE57_Pos) /*!< 0x02000000 */ -#define SYSCFG_SWPR2_PAGE57 SYSCFG_SWPR2_PAGE57_Msk /*!< SRAM2B Write protection page 25 (0x2003E400 – 0x2003E7FF) */ +#define SYSCFG_SWPR2_PAGE57 SYSCFG_SWPR2_PAGE57_Msk /*!< SRAM2B Write protection page 25 (0x2003E400 - 0x2003E7FF) */ #define SYSCFG_SWPR2_PAGE58_Pos (26U) #define SYSCFG_SWPR2_PAGE58_Msk (0x1UL << SYSCFG_SWPR2_PAGE58_Pos) /*!< 0x04000000 */ -#define SYSCFG_SWPR2_PAGE58 SYSCFG_SWPR2_PAGE58_Msk /*!< SRAM2B Write protection page 26 (0x2003E800 – 0x2003EBFF) */ +#define SYSCFG_SWPR2_PAGE58 SYSCFG_SWPR2_PAGE58_Msk /*!< SRAM2B Write protection page 26 (0x2003E800 - 0x2003EBFF) */ #define SYSCFG_SWPR2_PAGE59_Pos (27U) #define SYSCFG_SWPR2_PAGE59_Msk (0x1UL << SYSCFG_SWPR2_PAGE59_Pos) /*!< 0x08000000 */ -#define SYSCFG_SWPR2_PAGE59 SYSCFG_SWPR2_PAGE59_Msk /*!< SRAM2B Write protection page 27 (0x2003EC00 – 0x2003EFFF) */ +#define SYSCFG_SWPR2_PAGE59 SYSCFG_SWPR2_PAGE59_Msk /*!< SRAM2B Write protection page 27 (0x2003EC00 - 0x2003EFFF) */ #define SYSCFG_SWPR2_PAGE60_Pos (28U) #define SYSCFG_SWPR2_PAGE60_Msk (0x1UL << SYSCFG_SWPR2_PAGE60_Pos) /*!< 0x10000000 */ -#define SYSCFG_SWPR2_PAGE60 SYSCFG_SWPR2_PAGE60_Msk /*!< SRAM2B Write protection page 28 (0x2003F000 – 0x2003F3FF) */ +#define SYSCFG_SWPR2_PAGE60 SYSCFG_SWPR2_PAGE60_Msk /*!< SRAM2B Write protection page 28 (0x2003F000 - 0x2003F3FF) */ #define SYSCFG_SWPR2_PAGE61_Pos (29U) #define SYSCFG_SWPR2_PAGE61_Msk (0x1UL << SYSCFG_SWPR2_PAGE61_Pos) /*!< 0x20000000 */ -#define SYSCFG_SWPR2_PAGE61 SYSCFG_SWPR2_PAGE61_Msk /*!< SRAM2B Write protection page 29 (0x2003F400 – 0x2003F7FF) */ +#define SYSCFG_SWPR2_PAGE61 SYSCFG_SWPR2_PAGE61_Msk /*!< SRAM2B Write protection page 29 (0x2003F400 - 0x2003F7FF) */ #define SYSCFG_SWPR2_PAGE62_Pos (30U) #define SYSCFG_SWPR2_PAGE62_Msk (0x1UL << SYSCFG_SWPR2_PAGE62_Pos) /*!< 0x40000000 */ -#define SYSCFG_SWPR2_PAGE62 SYSCFG_SWPR2_PAGE62_Msk /*!< SRAM2B Write protection page 30 (0x2003F800 – 0x2003FBFF) */ +#define SYSCFG_SWPR2_PAGE62 SYSCFG_SWPR2_PAGE62_Msk /*!< SRAM2B Write protection page 30 (0x2003F800 - 0x2003FBFF) */ #define SYSCFG_SWPR2_PAGE63_Pos (31U) #define SYSCFG_SWPR2_PAGE63_Msk (0x1UL << SYSCFG_SWPR2_PAGE63_Pos) /*!< 0x80000000 */ -#define SYSCFG_SWPR2_PAGE63 SYSCFG_SWPR2_PAGE63_Msk /*!< SRAM2B Write protection page 31 (0x2003FC00 – 0x2003FFFF) */ +#define SYSCFG_SWPR2_PAGE63 SYSCFG_SWPR2_PAGE63_Msk /*!< SRAM2B Write protection page 31 (0x2003FC00 - 0x2003FFFF) */ /***************** Bit definition for SYSCFG_IMR1 register (Interrupt masks control and status register on CPU1 - part 1) *******************************************/ #define SYSCFG_IMR1_TIM1IM_Pos (13U) @@ -11037,5 +11037,3 @@ typedef struct /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBxx/Include/stm32wb55xx.h b/system/Drivers/CMSIS/Device/ST/STM32WBxx/Include/stm32wb55xx.h index 8e86e06ee0..5e776c2481 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32WBxx/Include/stm32wb55xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32WBxx/Include/stm32wb55xx.h @@ -487,7 +487,7 @@ uint32_t RESERVED6; /*!< Reserved, __IO uint32_t HSECR; /*!< RCC HSE Clock Register, Address offset: 0x9C */ uint32_t RESERVED7[26]; /*!< Reserved, Address offset: 0xA0-0x104 */ __IO uint32_t EXTCFGR; /*!< RCC Extended Clock Recovery Register, Address offset: 0x108 */ -uint32_t RESERVED8[15]; /*!< Reserved, Address offset: 0x10C-0x144 */ +uint32_t RESERVED8[15]; /*!< Reserved, Address offset: 0x10C-0x144 */ __IO uint32_t C2AHB1ENR; /*!< RRCC AHB1 peripheral CPU2 clocks enable register, Address offset: 0x148 */ __IO uint32_t C2AHB2ENR; /*!< RCC AHB2 peripheral CPU2 clocks enable register, Address offset: 0x14C */ __IO uint32_t C2AHB3ENR; /*!< RCC AHB3 & AHB4 peripheral CPU2 clocks enable register,, Address offset: 0x150 */ @@ -922,10 +922,10 @@ typedef struct /*!< Memory, OTP and Option bytes */ /* Base addresses */ -#define SYSTEM_MEMORY_BASE (0x1FFF0000UL) /*!< System Memory : 28Kb (0x1FFF0000 – 0x1FFF6FFF) */ -#define OTP_AREA_BASE (0x1FFF7000UL) /*!< OTP area : 1kB (0x1FFF7000 – 0x1FFF73FF) */ -#define OPTION_BYTE_BASE (0x1FFF8000UL) /*!< Option Bytes : 4kB (0x1FFF8000 – 0x1FFF8FFF) */ -#define ENGI_BYTE_BASE (0x1FFF7400UL) /*!< Engi Bytes : 3kB (0x1FFF7400 – 0x1FFF7FFF) */ +#define SYSTEM_MEMORY_BASE (0x1FFF0000UL) /*!< System Memory : 28Kb (0x1FFF0000 - 0x1FFF6FFF) */ +#define OTP_AREA_BASE (0x1FFF7000UL) /*!< OTP area : 1kB (0x1FFF7000 - 0x1FFF73FF) */ +#define OPTION_BYTE_BASE (0x1FFF8000UL) /*!< Option Bytes : 4kB (0x1FFF8000 - 0x1FFF8FFF) */ +#define ENGI_BYTE_BASE (0x1FFF7400UL) /*!< Engi Bytes : 3kB (0x1FFF7400 - 0x1FFF7FFF) */ #define SRAM1_BASE SRAM_BASE /*!< SRAM1(up to 192 KB) base address */ #define SRAM2A_BASE (SRAM_BASE + 0x00030000UL)/*!< SRAM2A(32 KB) base address */ @@ -938,14 +938,14 @@ typedef struct #define SRAM2B_SIZE 0x00008000UL /*!< SRAM2b default size : 32 kB */ /* End addresses */ -#define SRAM1_END_ADDR (0x2002FFFFUL) /*!< SRAM1 : 192KB (0x20000000 – 0x2002FFFF) */ -#define SRAM2A_END_ADDR (0x20037FFFUL) /*!< SRAM2a (backup) : 32KB (0x20030000 – 0x20037FFF) */ -#define SRAM2B_END_ADDR (0x2003FFFFUL) /*!< SRAM2b (non-backup) : 32KB (0x20038000 – 0x2003FFFF) */ +#define SRAM1_END_ADDR (0x2002FFFFUL) /*!< SRAM1 : 192KB (0x20000000 - 0x2002FFFF) */ +#define SRAM2A_END_ADDR (0x20037FFFUL) /*!< SRAM2a (backup) : 32KB (0x20030000 - 0x20037FFF) */ +#define SRAM2B_END_ADDR (0x2003FFFFUL) /*!< SRAM2b (non-backup) : 32KB (0x20038000 - 0x2003FFFF) */ -#define SYSTEM_MEMORY_END_ADDR (0x1FFF6FFFUL) /*!< System Memory : 28KB (0x1FFF0000 – 0x1FFF6FFF) */ -#define OTP_AREA_END_ADDR (0x1FFF73FFUL) /*!< OTP area : 1KB (0x1FFF7000 – 0x1FFF73FF) */ -#define OPTION_BYTE_END_ADDR (0x1FFF8FFFUL) /*!< Option Bytes : 4KB (0x1FFF8000 – 0x1FFF8FFF) */ -#define ENGI_BYTE_END_ADDR (0x1FFF7FFFUL) /*!< Engi Bytes : 3kB (0x1FFF7400 – 0x1FFF7FFF) */ +#define SYSTEM_MEMORY_END_ADDR (0x1FFF6FFFUL) /*!< System Memory : 28KB (0x1FFF0000 - 0x1FFF6FFF) */ +#define OTP_AREA_END_ADDR (0x1FFF73FFUL) /*!< OTP area : 1KB (0x1FFF7000 - 0x1FFF73FF) */ +#define OPTION_BYTE_END_ADDR (0x1FFF8FFFUL) /*!< Option Bytes : 4KB (0x1FFF8000 - 0x1FFF8FFF) */ +#define ENGI_BYTE_END_ADDR (0x1FFF7FFFUL) /*!< Engi Bytes : 3kB (0x1FFF7400 - 0x1FFF7FFF) */ /*!< Peripheral memory map */ #define APB1PERIPH_BASE PERIPH_BASE @@ -1338,7 +1338,7 @@ typedef struct #define ADC_CFGR_ALIGN_Pos (5U) #define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00000020 */ -#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */ +#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignment */ #define ADC_CFGR_EXTSEL_Pos (6U) #define ADC_CFGR_EXTSEL_Msk (0xFUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003C0 */ @@ -3951,12 +3951,12 @@ typedef struct /* Arithmetic addition output data */ #define PKA_ARITHMETIC_ADD_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ -/* Arithmetic substraction input data */ +/* Arithmetic subtraction input data */ #define PKA_ARITHMETIC_SUB_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ #define PKA_ARITHMETIC_SUB_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ #define PKA_ARITHMETIC_SUB_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ -/* Arithmetic substraction output data */ +/* Arithmetic subtraction output data */ #define PKA_ARITHMETIC_SUB_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ /* Arithmetic multiplication input data */ @@ -3992,13 +3992,13 @@ typedef struct /* Modular inversion output data */ #define PKA_MODULAR_INV_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ -/* Modular substraction input data */ +/* Modular subtraction input data */ #define PKA_MODULAR_SUB_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ #define PKA_MODULAR_SUB_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ #define PKA_MODULAR_SUB_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ #define PKA_MODULAR_SUB_IN_OP3_MOD ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 */ -/* Modular substraction output data */ +/* Modular subtraction output data */ #define PKA_MODULAR_SUB_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ /* Montgomery multiplication input data */ @@ -8746,10 +8746,10 @@ typedef struct #define RTC_CR_OSEL_1 (0x2U << RTC_CR_OSEL_Pos) /*!< 0x00400000 */ #define RTC_CR_POL_Pos (20U) #define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */ -#define RTC_CR_POL RTC_CR_POL_Msk /*!< Ouput polarity */ +#define RTC_CR_POL RTC_CR_POL_Msk /*!< Output polarity */ #define RTC_CR_COSEL_Pos (19U) #define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ -#define RTC_CR_COSEL RTC_CR_COSEL_Msk /*!< Calibration ouput selection */ +#define RTC_CR_COSEL RTC_CR_COSEL_Msk /*!< Calibration output selection */ #define RTC_CR_BKP_Pos (18U) #define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */ #define RTC_CR_BKP RTC_CR_BKP_Msk /*!< Backup */ @@ -9024,7 +9024,7 @@ typedef struct /******************** Bits definition for RTC_SHIFTR register ***************/ #define RTC_SHIFTR_SUBFS_Pos (0U) #define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */ -#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk /*!< Substract a fraction of a second */ +#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk /*!< Subtract a fraction of a second */ #define RTC_SHIFTR_ADD1S_Pos (31U) #define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */ #define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk /*!< Add on second */ @@ -10714,100 +10714,100 @@ typedef struct /***************** Bit definition for SYSCFG_SWPR1 register (SYSCFG SRAM2A write protection register) *********************************************************/ #define SYSCFG_SWPR1_PAGE0_Pos (0U) #define SYSCFG_SWPR1_PAGE0_Msk (0x1UL << SYSCFG_SWPR1_PAGE0_Pos) /*!< 0x00000001 */ -#define SYSCFG_SWPR1_PAGE0 SYSCFG_SWPR1_PAGE0_Msk /*!< SRAM2A Write protection page 0 (0x20030000 – 0x200303FF) */ +#define SYSCFG_SWPR1_PAGE0 SYSCFG_SWPR1_PAGE0_Msk /*!< SRAM2A Write protection page 0 (0x20030000 - 0x200303FF) */ #define SYSCFG_SWPR1_PAGE1_Pos (1U) #define SYSCFG_SWPR1_PAGE1_Msk (0x1UL << SYSCFG_SWPR1_PAGE1_Pos) /*!< 0x00000002 */ -#define SYSCFG_SWPR1_PAGE1 SYSCFG_SWPR1_PAGE1_Msk /*!< SRAM2A Write protection page 1 (0x20030400 – 0x200307FF) */ +#define SYSCFG_SWPR1_PAGE1 SYSCFG_SWPR1_PAGE1_Msk /*!< SRAM2A Write protection page 1 (0x20030400 - 0x200307FF) */ #define SYSCFG_SWPR1_PAGE2_Pos (2U) #define SYSCFG_SWPR1_PAGE2_Msk (0x1UL << SYSCFG_SWPR1_PAGE2_Pos) /*!< 0x00000004 */ -#define SYSCFG_SWPR1_PAGE2 SYSCFG_SWPR1_PAGE2_Msk /*!< SRAM2A Write protection page 2 (0x20030800 – 0x20030BFF) */ +#define SYSCFG_SWPR1_PAGE2 SYSCFG_SWPR1_PAGE2_Msk /*!< SRAM2A Write protection page 2 (0x20030800 - 0x20030BFF) */ #define SYSCFG_SWPR1_PAGE3_Pos (3U) #define SYSCFG_SWPR1_PAGE3_Msk (0x1UL << SYSCFG_SWPR1_PAGE3_Pos) /*!< 0x00000008 */ -#define SYSCFG_SWPR1_PAGE3 SYSCFG_SWPR1_PAGE3_Msk /*!< SRAM2A Write protection page 3 (0x20030C00 – 0x20030FFF) */ +#define SYSCFG_SWPR1_PAGE3 SYSCFG_SWPR1_PAGE3_Msk /*!< SRAM2A Write protection page 3 (0x20030C00 - 0x20030FFF) */ #define SYSCFG_SWPR1_PAGE4_Pos (4U) #define SYSCFG_SWPR1_PAGE4_Msk (0x1UL << SYSCFG_SWPR1_PAGE4_Pos) /*!< 0x00000010 */ -#define SYSCFG_SWPR1_PAGE4 SYSCFG_SWPR1_PAGE4_Msk /*!< SRAM2A Write protection page 4 (0x20031000 – 0x200313FF) */ +#define SYSCFG_SWPR1_PAGE4 SYSCFG_SWPR1_PAGE4_Msk /*!< SRAM2A Write protection page 4 (0x20031000 - 0x200313FF) */ #define SYSCFG_SWPR1_PAGE5_Pos (5U) #define SYSCFG_SWPR1_PAGE5_Msk (0x1UL << SYSCFG_SWPR1_PAGE5_Pos) /*!< 0x00000020 */ -#define SYSCFG_SWPR1_PAGE5 SYSCFG_SWPR1_PAGE5_Msk /*!< SRAM2A Write protection page 5 (0x20031400 – 0x200317FF) */ +#define SYSCFG_SWPR1_PAGE5 SYSCFG_SWPR1_PAGE5_Msk /*!< SRAM2A Write protection page 5 (0x20031400 - 0x200317FF) */ #define SYSCFG_SWPR1_PAGE6_Pos (6U) #define SYSCFG_SWPR1_PAGE6_Msk (0x1UL << SYSCFG_SWPR1_PAGE6_Pos) /*!< 0x00000040 */ -#define SYSCFG_SWPR1_PAGE6 SYSCFG_SWPR1_PAGE6_Msk /*!< SRAM2A Write protection page 6 (0x20031800 – 0x20031BFF) */ +#define SYSCFG_SWPR1_PAGE6 SYSCFG_SWPR1_PAGE6_Msk /*!< SRAM2A Write protection page 6 (0x20031800 - 0x20031BFF) */ #define SYSCFG_SWPR1_PAGE7_Pos (7U) #define SYSCFG_SWPR1_PAGE7_Msk (0x1UL << SYSCFG_SWPR1_PAGE7_Pos) /*!< 0x00000080 */ -#define SYSCFG_SWPR1_PAGE7 SYSCFG_SWPR1_PAGE7_Msk /*!< SRAM2A Write protection page 7 (0x20031C00 – 0x20031FFF) */ +#define SYSCFG_SWPR1_PAGE7 SYSCFG_SWPR1_PAGE7_Msk /*!< SRAM2A Write protection page 7 (0x20031C00 - 0x20031FFF) */ #define SYSCFG_SWPR1_PAGE8_Pos (8U) #define SYSCFG_SWPR1_PAGE8_Msk (0x1UL << SYSCFG_SWPR1_PAGE8_Pos) /*!< 0x00000100 */ -#define SYSCFG_SWPR1_PAGE8 SYSCFG_SWPR1_PAGE8_Msk /*!< SRAM2A Write protection page 8 (0x20032000 – 0x200323FF) */ +#define SYSCFG_SWPR1_PAGE8 SYSCFG_SWPR1_PAGE8_Msk /*!< SRAM2A Write protection page 8 (0x20032000 - 0x200323FF) */ #define SYSCFG_SWPR1_PAGE9_Pos (9U) #define SYSCFG_SWPR1_PAGE9_Msk (0x1UL << SYSCFG_SWPR1_PAGE9_Pos) /*!< 0x00000200 */ -#define SYSCFG_SWPR1_PAGE9 SYSCFG_SWPR1_PAGE9_Msk /*!< SRAM2A Write protection page 9 (0x20032400 – 0x200327FF) */ +#define SYSCFG_SWPR1_PAGE9 SYSCFG_SWPR1_PAGE9_Msk /*!< SRAM2A Write protection page 9 (0x20032400 - 0x200327FF) */ #define SYSCFG_SWPR1_PAGE10_Pos (10U) #define SYSCFG_SWPR1_PAGE10_Msk (0x1UL << SYSCFG_SWPR1_PAGE10_Pos) /*!< 0x00000400 */ -#define SYSCFG_SWPR1_PAGE10 SYSCFG_SWPR1_PAGE10_Msk /*!< SRAM2A Write protection page 10 (0x20032800 – 0x20032BFF) */ +#define SYSCFG_SWPR1_PAGE10 SYSCFG_SWPR1_PAGE10_Msk /*!< SRAM2A Write protection page 10 (0x20032800 - 0x20032BFF) */ #define SYSCFG_SWPR1_PAGE11_Pos (11U) #define SYSCFG_SWPR1_PAGE11_Msk (0x1UL << SYSCFG_SWPR1_PAGE11_Pos) /*!< 0x00000800 */ -#define SYSCFG_SWPR1_PAGE11 SYSCFG_SWPR1_PAGE11_Msk /*!< SRAM2A Write protection page 11 (0x20032C00 – 0x20032FFF) */ +#define SYSCFG_SWPR1_PAGE11 SYSCFG_SWPR1_PAGE11_Msk /*!< SRAM2A Write protection page 11 (0x20032C00 - 0x20032FFF) */ #define SYSCFG_SWPR1_PAGE12_Pos (12U) #define SYSCFG_SWPR1_PAGE12_Msk (0x1UL << SYSCFG_SWPR1_PAGE12_Pos) /*!< 0x00001000 */ -#define SYSCFG_SWPR1_PAGE12 SYSCFG_SWPR1_PAGE12_Msk /*!< SRAM2A Write protection page 12 (0x20033000 – 0x200333FF) */ +#define SYSCFG_SWPR1_PAGE12 SYSCFG_SWPR1_PAGE12_Msk /*!< SRAM2A Write protection page 12 (0x20033000 - 0x200333FF) */ #define SYSCFG_SWPR1_PAGE13_Pos (13U) #define SYSCFG_SWPR1_PAGE13_Msk (0x1UL << SYSCFG_SWPR1_PAGE13_Pos) /*!< 0x00002000 */ -#define SYSCFG_SWPR1_PAGE13 SYSCFG_SWPR1_PAGE13_Msk /*!< SRAM2A Write protection page 13 (0x20033400 – 0x200337FF) */ +#define SYSCFG_SWPR1_PAGE13 SYSCFG_SWPR1_PAGE13_Msk /*!< SRAM2A Write protection page 13 (0x20033400 - 0x200337FF) */ #define SYSCFG_SWPR1_PAGE14_Pos (14U) #define SYSCFG_SWPR1_PAGE14_Msk (0x1UL << SYSCFG_SWPR1_PAGE14_Pos) /*!< 0x00004000 */ -#define SYSCFG_SWPR1_PAGE14 SYSCFG_SWPR1_PAGE14_Msk /*!< SRAM2A Write protection page 14 (0x20033800 – 0x20033BFF) */ +#define SYSCFG_SWPR1_PAGE14 SYSCFG_SWPR1_PAGE14_Msk /*!< SRAM2A Write protection page 14 (0x20033800 - 0x20033BFF) */ #define SYSCFG_SWPR1_PAGE15_Pos (15U) #define SYSCFG_SWPR1_PAGE15_Msk (0x1UL << SYSCFG_SWPR1_PAGE15_Pos) /*!< 0x00008000 */ -#define SYSCFG_SWPR1_PAGE15 SYSCFG_SWPR1_PAGE15_Msk /*!< SRAM2A Write protection page 15 (0x20033C00 – 0x20033FFF) */ +#define SYSCFG_SWPR1_PAGE15 SYSCFG_SWPR1_PAGE15_Msk /*!< SRAM2A Write protection page 15 (0x20033C00 - 0x20033FFF) */ #define SYSCFG_SWPR1_PAGE16_Pos (16U) #define SYSCFG_SWPR1_PAGE16_Msk (0x1UL << SYSCFG_SWPR1_PAGE16_Pos) /*!< 0x00010000 */ -#define SYSCFG_SWPR1_PAGE16 SYSCFG_SWPR1_PAGE16_Msk /*!< SRAM2A Write protection page 16 (0x20034000 – 0x200343FF) */ +#define SYSCFG_SWPR1_PAGE16 SYSCFG_SWPR1_PAGE16_Msk /*!< SRAM2A Write protection page 16 (0x20034000 - 0x200343FF) */ #define SYSCFG_SWPR1_PAGE17_Pos (17U) #define SYSCFG_SWPR1_PAGE17_Msk (0x1UL << SYSCFG_SWPR1_PAGE17_Pos) /*!< 0x00020000 */ -#define SYSCFG_SWPR1_PAGE17 SYSCFG_SWPR1_PAGE17_Msk /*!< SRAM2A Write protection page 17 (0x20034400 – 0x200347FF) */ +#define SYSCFG_SWPR1_PAGE17 SYSCFG_SWPR1_PAGE17_Msk /*!< SRAM2A Write protection page 17 (0x20034400 - 0x200347FF) */ #define SYSCFG_SWPR1_PAGE18_Pos (18U) #define SYSCFG_SWPR1_PAGE18_Msk (0x1UL << SYSCFG_SWPR1_PAGE18_Pos) /*!< 0x00040000 */ -#define SYSCFG_SWPR1_PAGE18 SYSCFG_SWPR1_PAGE18_Msk /*!< SRAM2A Write protection page 18 (0x20034800 – 0x20034BFF) */ +#define SYSCFG_SWPR1_PAGE18 SYSCFG_SWPR1_PAGE18_Msk /*!< SRAM2A Write protection page 18 (0x20034800 - 0x20034BFF) */ #define SYSCFG_SWPR1_PAGE19_Pos (19U) #define SYSCFG_SWPR1_PAGE19_Msk (0x1UL << SYSCFG_SWPR1_PAGE19_Pos) /*!< 0x00080000 */ -#define SYSCFG_SWPR1_PAGE19 SYSCFG_SWPR1_PAGE19_Msk /*!< SRAM2A Write protection page 19 (0x20034C00 – 0x20034FFF) */ +#define SYSCFG_SWPR1_PAGE19 SYSCFG_SWPR1_PAGE19_Msk /*!< SRAM2A Write protection page 19 (0x20034C00 - 0x20034FFF) */ #define SYSCFG_SWPR1_PAGE20_Pos (20U) #define SYSCFG_SWPR1_PAGE20_Msk (0x1UL << SYSCFG_SWPR1_PAGE20_Pos) /*!< 0x00100000 */ -#define SYSCFG_SWPR1_PAGE20 SYSCFG_SWPR1_PAGE20_Msk /*!< SRAM2A Write protection page 20 (0x20035000 – 0x200353FF) */ +#define SYSCFG_SWPR1_PAGE20 SYSCFG_SWPR1_PAGE20_Msk /*!< SRAM2A Write protection page 20 (0x20035000 - 0x200353FF) */ #define SYSCFG_SWPR1_PAGE21_Pos (21U) #define SYSCFG_SWPR1_PAGE21_Msk (0x1UL << SYSCFG_SWPR1_PAGE21_Pos) /*!< 0x00200000 */ -#define SYSCFG_SWPR1_PAGE21 SYSCFG_SWPR1_PAGE21_Msk /*!< SRAM2A Write protection page 21 (0x20035400 – 0x200357FF) */ +#define SYSCFG_SWPR1_PAGE21 SYSCFG_SWPR1_PAGE21_Msk /*!< SRAM2A Write protection page 21 (0x20035400 - 0x200357FF) */ #define SYSCFG_SWPR1_PAGE22_Pos (22U) #define SYSCFG_SWPR1_PAGE22_Msk (0x1UL << SYSCFG_SWPR1_PAGE22_Pos) /*!< 0x00400000 */ -#define SYSCFG_SWPR1_PAGE22 SYSCFG_SWPR1_PAGE22_Msk /*!< SRAM2A Write protection page 22 (0x20035800 – 0x20035BFF) */ +#define SYSCFG_SWPR1_PAGE22 SYSCFG_SWPR1_PAGE22_Msk /*!< SRAM2A Write protection page 22 (0x20035800 - 0x20035BFF) */ #define SYSCFG_SWPR1_PAGE23_Pos (23U) #define SYSCFG_SWPR1_PAGE23_Msk (0x1UL << SYSCFG_SWPR1_PAGE23_Pos) /*!< 0x00800000 */ -#define SYSCFG_SWPR1_PAGE23 SYSCFG_SWPR1_PAGE23_Msk /*!< SRAM2A Write protection page 23 (0x20035C00 – 0x20035FFF) */ +#define SYSCFG_SWPR1_PAGE23 SYSCFG_SWPR1_PAGE23_Msk /*!< SRAM2A Write protection page 23 (0x20035C00 - 0x20035FFF) */ #define SYSCFG_SWPR1_PAGE24_Pos (24U) #define SYSCFG_SWPR1_PAGE24_Msk (0x1UL << SYSCFG_SWPR1_PAGE24_Pos) /*!< 0x01000000 */ -#define SYSCFG_SWPR1_PAGE24 SYSCFG_SWPR1_PAGE24_Msk /*!< SRAM2A Write protection page 24 (0x20036000 – 0x200363FF) */ +#define SYSCFG_SWPR1_PAGE24 SYSCFG_SWPR1_PAGE24_Msk /*!< SRAM2A Write protection page 24 (0x20036000 - 0x200363FF) */ #define SYSCFG_SWPR1_PAGE25_Pos (25U) #define SYSCFG_SWPR1_PAGE25_Msk (0x1UL << SYSCFG_SWPR1_PAGE25_Pos) /*!< 0x02000000 */ -#define SYSCFG_SWPR1_PAGE25 SYSCFG_SWPR1_PAGE25_Msk /*!< SRAM2A Write protection page 25 (0x20036400 – 0x200367FF) */ +#define SYSCFG_SWPR1_PAGE25 SYSCFG_SWPR1_PAGE25_Msk /*!< SRAM2A Write protection page 25 (0x20036400 - 0x200367FF) */ #define SYSCFG_SWPR1_PAGE26_Pos (26U) #define SYSCFG_SWPR1_PAGE26_Msk (0x1UL << SYSCFG_SWPR1_PAGE26_Pos) /*!< 0x04000000 */ -#define SYSCFG_SWPR1_PAGE26 SYSCFG_SWPR1_PAGE26_Msk /*!< SRAM2A Write protection page 26 (0x20036800 – 0x20036BFF) */ +#define SYSCFG_SWPR1_PAGE26 SYSCFG_SWPR1_PAGE26_Msk /*!< SRAM2A Write protection page 26 (0x20036800 - 0x20036BFF) */ #define SYSCFG_SWPR1_PAGE27_Pos (27U) #define SYSCFG_SWPR1_PAGE27_Msk (0x1UL << SYSCFG_SWPR1_PAGE27_Pos) /*!< 0x08000000 */ -#define SYSCFG_SWPR1_PAGE27 SYSCFG_SWPR1_PAGE27_Msk /*!< SRAM2A Write protection page 27 (0x20036C00 – 0x20036FFF) */ +#define SYSCFG_SWPR1_PAGE27 SYSCFG_SWPR1_PAGE27_Msk /*!< SRAM2A Write protection page 27 (0x20036C00 - 0x20036FFF) */ #define SYSCFG_SWPR1_PAGE28_Pos (28U) #define SYSCFG_SWPR1_PAGE28_Msk (0x1UL << SYSCFG_SWPR1_PAGE28_Pos) /*!< 0x10000000 */ -#define SYSCFG_SWPR1_PAGE28 SYSCFG_SWPR1_PAGE28_Msk /*!< SRAM2A Write protection page 28 (0x20037000 – 0x200373FF) */ +#define SYSCFG_SWPR1_PAGE28 SYSCFG_SWPR1_PAGE28_Msk /*!< SRAM2A Write protection page 28 (0x20037000 - 0x200373FF) */ #define SYSCFG_SWPR1_PAGE29_Pos (29U) #define SYSCFG_SWPR1_PAGE29_Msk (0x1UL << SYSCFG_SWPR1_PAGE29_Pos) /*!< 0x20000000 */ -#define SYSCFG_SWPR1_PAGE29 SYSCFG_SWPR1_PAGE29_Msk /*!< SRAM2A Write protection page 29 (0x20037400 – 0x200377FF) */ +#define SYSCFG_SWPR1_PAGE29 SYSCFG_SWPR1_PAGE29_Msk /*!< SRAM2A Write protection page 29 (0x20037400 - 0x200377FF) */ #define SYSCFG_SWPR1_PAGE30_Pos (30U) #define SYSCFG_SWPR1_PAGE30_Msk (0x1UL << SYSCFG_SWPR1_PAGE30_Pos) /*!< 0x40000000 */ -#define SYSCFG_SWPR1_PAGE30 SYSCFG_SWPR1_PAGE30_Msk /*!< SRAM2A Write protection page 30 (0x20037800 – 0x20037BFF) */ +#define SYSCFG_SWPR1_PAGE30 SYSCFG_SWPR1_PAGE30_Msk /*!< SRAM2A Write protection page 30 (0x20037800 - 0x20037BFF) */ #define SYSCFG_SWPR1_PAGE31_Pos (31U) #define SYSCFG_SWPR1_PAGE31_Msk (0x1UL << SYSCFG_SWPR1_PAGE31_Pos) /*!< 0x80000000 */ -#define SYSCFG_SWPR1_PAGE31 SYSCFG_SWPR1_PAGE31_Msk /*!< SRAM2A Write protection page 31 (0x20037C00 – 0x20037FFF) */ +#define SYSCFG_SWPR1_PAGE31 SYSCFG_SWPR1_PAGE31_Msk /*!< SRAM2A Write protection page 31 (0x20037C00 - 0x20037FFF) */ /***************** Bit definition for SYSCFG_SKR register (SYSCFG SRAM2 key register) *************************************************************************/ #define SYSCFG_SKR_KEY_Pos (0U) @@ -10817,100 +10817,100 @@ typedef struct /***************** Bit definition for SYSCFG_SWPR2 register (SYSCFG SRAM2 write protection register) **********************************************************/ #define SYSCFG_SWPR2_PAGE32_Pos (0U) #define SYSCFG_SWPR2_PAGE32_Msk (0x1UL << SYSCFG_SWPR2_PAGE32_Pos) /*!< 0x00000001 */ -#define SYSCFG_SWPR2_PAGE32 SYSCFG_SWPR2_PAGE32_Msk /*!< SRAM2B Write protection page 0 (0x20038000 – 0x200383FF) */ +#define SYSCFG_SWPR2_PAGE32 SYSCFG_SWPR2_PAGE32_Msk /*!< SRAM2B Write protection page 0 (0x20038000 - 0x200383FF) */ #define SYSCFG_SWPR2_PAGE33_Pos (1U) #define SYSCFG_SWPR2_PAGE33_Msk (0x1UL << SYSCFG_SWPR2_PAGE33_Pos) /*!< 0x00000002 */ -#define SYSCFG_SWPR2_PAGE33 SYSCFG_SWPR2_PAGE33_Msk /*!< SRAM2B Write protection page 1 (0x20038400 – 0x200387FF) */ +#define SYSCFG_SWPR2_PAGE33 SYSCFG_SWPR2_PAGE33_Msk /*!< SRAM2B Write protection page 1 (0x20038400 - 0x200387FF) */ #define SYSCFG_SWPR2_PAGE34_Pos (2U) #define SYSCFG_SWPR2_PAGE34_Msk (0x1UL << SYSCFG_SWPR2_PAGE34_Pos) /*!< 0x00000004 */ -#define SYSCFG_SWPR2_PAGE34 SYSCFG_SWPR2_PAGE34_Msk /*!< SRAM2B Write protection page 2 (0x20038800 – 0x20038bFF) */ +#define SYSCFG_SWPR2_PAGE34 SYSCFG_SWPR2_PAGE34_Msk /*!< SRAM2B Write protection page 2 (0x20038800 - 0x20038bFF) */ #define SYSCFG_SWPR2_PAGE35_Pos (3U) #define SYSCFG_SWPR2_PAGE35_Msk (0x1UL << SYSCFG_SWPR2_PAGE35_Pos) /*!< 0x00000008 */ -#define SYSCFG_SWPR2_PAGE35 SYSCFG_SWPR2_PAGE35_Msk /*!< SRAM2B Write protection page 3 (0x20038C00 – 0x20038FFF) */ +#define SYSCFG_SWPR2_PAGE35 SYSCFG_SWPR2_PAGE35_Msk /*!< SRAM2B Write protection page 3 (0x20038C00 - 0x20038FFF) */ #define SYSCFG_SWPR2_PAGE36_Pos (4U) #define SYSCFG_SWPR2_PAGE36_Msk (0x1UL << SYSCFG_SWPR2_PAGE36_Pos) /*!< 0x00000010 */ -#define SYSCFG_SWPR2_PAGE36 SYSCFG_SWPR2_PAGE36_Msk /*!< SRAM2B Write protection page 4 (0x20039000 – 0x200393FF) */ +#define SYSCFG_SWPR2_PAGE36 SYSCFG_SWPR2_PAGE36_Msk /*!< SRAM2B Write protection page 4 (0x20039000 - 0x200393FF) */ #define SYSCFG_SWPR2_PAGE37_Pos (5U) #define SYSCFG_SWPR2_PAGE37_Msk (0x1UL << SYSCFG_SWPR2_PAGE37_Pos) /*!< 0x00000020 */ -#define SYSCFG_SWPR2_PAGE37 SYSCFG_SWPR2_PAGE37_Msk /*!< SRAM2B Write protection page 5 (0x20039400 – 0x200397FF) */ +#define SYSCFG_SWPR2_PAGE37 SYSCFG_SWPR2_PAGE37_Msk /*!< SRAM2B Write protection page 5 (0x20039400 - 0x200397FF) */ #define SYSCFG_SWPR2_PAGE38_Pos (6U) #define SYSCFG_SWPR2_PAGE38_Msk (0x1UL << SYSCFG_SWPR2_PAGE38_Pos) /*!< 0x00000040 */ -#define SYSCFG_SWPR2_PAGE38 SYSCFG_SWPR2_PAGE38_Msk /*!< SRAM2B Write protection page 6 (0x20039800 – 0x20039BFF) */ +#define SYSCFG_SWPR2_PAGE38 SYSCFG_SWPR2_PAGE38_Msk /*!< SRAM2B Write protection page 6 (0x20039800 - 0x20039BFF) */ #define SYSCFG_SWPR2_PAGE39_Pos (7U) #define SYSCFG_SWPR2_PAGE39_Msk (0x1UL << SYSCFG_SWPR2_PAGE39_Pos) /*!< 0x00000080 */ -#define SYSCFG_SWPR2_PAGE39 SYSCFG_SWPR2_PAGE39_Msk /*!< SRAM2B Write protection page 7 (0x20039C00 – 0x20039FFF) */ +#define SYSCFG_SWPR2_PAGE39 SYSCFG_SWPR2_PAGE39_Msk /*!< SRAM2B Write protection page 7 (0x20039C00 - 0x20039FFF) */ #define SYSCFG_SWPR2_PAGE40_Pos (8U) #define SYSCFG_SWPR2_PAGE40_Msk (0x1UL << SYSCFG_SWPR2_PAGE40_Pos) /*!< 0x00000100 */ -#define SYSCFG_SWPR2_PAGE40 SYSCFG_SWPR2_PAGE40_Msk /*!< SRAM2B Write protection page 8 (0x2003A000 – 0x2003A3FF) */ +#define SYSCFG_SWPR2_PAGE40 SYSCFG_SWPR2_PAGE40_Msk /*!< SRAM2B Write protection page 8 (0x2003A000 - 0x2003A3FF) */ #define SYSCFG_SWPR2_PAGE41_Pos (9U) #define SYSCFG_SWPR2_PAGE41_Msk (0x1UL << SYSCFG_SWPR2_PAGE41_Pos) /*!< 0x00000200 */ -#define SYSCFG_SWPR2_PAGE41 SYSCFG_SWPR2_PAGE41_Msk /*!< SRAM2B Write protection page 9 (0x2003A400 – 0x2003A7FF) */ +#define SYSCFG_SWPR2_PAGE41 SYSCFG_SWPR2_PAGE41_Msk /*!< SRAM2B Write protection page 9 (0x2003A400 - 0x2003A7FF) */ #define SYSCFG_SWPR2_PAGE42_Pos (10U) #define SYSCFG_SWPR2_PAGE42_Msk (0x1UL << SYSCFG_SWPR2_PAGE42_Pos) /*!< 0x00000400 */ -#define SYSCFG_SWPR2_PAGE42 SYSCFG_SWPR2_PAGE42_Msk /*!< SRAM2B Write protection page 10 (0x2003A800 – 0x2003ABFF) */ +#define SYSCFG_SWPR2_PAGE42 SYSCFG_SWPR2_PAGE42_Msk /*!< SRAM2B Write protection page 10 (0x2003A800 - 0x2003ABFF) */ #define SYSCFG_SWPR2_PAGE43_Pos (11U) #define SYSCFG_SWPR2_PAGE43_Msk (0x1UL << SYSCFG_SWPR2_PAGE43_Pos) /*!< 0x00000800 */ -#define SYSCFG_SWPR2_PAGE43 SYSCFG_SWPR2_PAGE43_Msk /*!< SRAM2B Write protection page 11 (0x2003AC00 – 0x2003AFFF) */ +#define SYSCFG_SWPR2_PAGE43 SYSCFG_SWPR2_PAGE43_Msk /*!< SRAM2B Write protection page 11 (0x2003AC00 - 0x2003AFFF) */ #define SYSCFG_SWPR2_PAGE44_Pos (12U) #define SYSCFG_SWPR2_PAGE44_Msk (0x1UL << SYSCFG_SWPR2_PAGE44_Pos) /*!< 0x00001000 */ -#define SYSCFG_SWPR2_PAGE44 SYSCFG_SWPR2_PAGE44_Msk /*!< SRAM2B Write protection page 12 (0x2003B000 – 0x2003B3FF) */ +#define SYSCFG_SWPR2_PAGE44 SYSCFG_SWPR2_PAGE44_Msk /*!< SRAM2B Write protection page 12 (0x2003B000 - 0x2003B3FF) */ #define SYSCFG_SWPR2_PAGE45_Pos (13U) #define SYSCFG_SWPR2_PAGE45_Msk (0x1UL << SYSCFG_SWPR2_PAGE45_Pos) /*!< 0x00002000 */ -#define SYSCFG_SWPR2_PAGE45 SYSCFG_SWPR2_PAGE45_Msk /*!< SRAM2B Write protection page 13 (0x2003B400 – 0x2003B7FF) */ +#define SYSCFG_SWPR2_PAGE45 SYSCFG_SWPR2_PAGE45_Msk /*!< SRAM2B Write protection page 13 (0x2003B400 - 0x2003B7FF) */ #define SYSCFG_SWPR2_PAGE46_Pos (14U) #define SYSCFG_SWPR2_PAGE46_Msk (0x1UL << SYSCFG_SWPR2_PAGE46_Pos) /*!< 0x00004000 */ -#define SYSCFG_SWPR2_PAGE46 SYSCFG_SWPR2_PAGE46_Msk /*!< SRAM2B Write protection page 14 (0x2003B800 – 0x2003BBFF) */ +#define SYSCFG_SWPR2_PAGE46 SYSCFG_SWPR2_PAGE46_Msk /*!< SRAM2B Write protection page 14 (0x2003B800 - 0x2003BBFF) */ #define SYSCFG_SWPR2_PAGE47_Pos (15U) #define SYSCFG_SWPR2_PAGE47_Msk (0x1UL << SYSCFG_SWPR2_PAGE47_Pos) /*!< 0x00008000 */ -#define SYSCFG_SWPR2_PAGE47 SYSCFG_SWPR2_PAGE47_Msk /*!< SRAM2B Write protection page 15 (0x2003BC00 – 0x2003BFFF) */ +#define SYSCFG_SWPR2_PAGE47 SYSCFG_SWPR2_PAGE47_Msk /*!< SRAM2B Write protection page 15 (0x2003BC00 - 0x2003BFFF) */ #define SYSCFG_SWPR2_PAGE48_Pos (16U) #define SYSCFG_SWPR2_PAGE48_Msk (0x1UL << SYSCFG_SWPR2_PAGE48_Pos) /*!< 0x00010000 */ -#define SYSCFG_SWPR2_PAGE48 SYSCFG_SWPR2_PAGE48_Msk /*!< SRAM2B Write protection page 16 (0x2003C000 – 0x2003C3FF) */ +#define SYSCFG_SWPR2_PAGE48 SYSCFG_SWPR2_PAGE48_Msk /*!< SRAM2B Write protection page 16 (0x2003C000 - 0x2003C3FF) */ #define SYSCFG_SWPR2_PAGE49_Pos (17U) #define SYSCFG_SWPR2_PAGE49_Msk (0x1UL << SYSCFG_SWPR2_PAGE49_Pos) /*!< 0x00020000 */ -#define SYSCFG_SWPR2_PAGE49 SYSCFG_SWPR2_PAGE49_Msk /*!< SRAM2B Write protection page 17 (0x2003C400 – 0x2003C7FF) */ +#define SYSCFG_SWPR2_PAGE49 SYSCFG_SWPR2_PAGE49_Msk /*!< SRAM2B Write protection page 17 (0x2003C400 - 0x2003C7FF) */ #define SYSCFG_SWPR2_PAGE50_Pos (18U) #define SYSCFG_SWPR2_PAGE50_Msk (0x1UL << SYSCFG_SWPR2_PAGE50_Pos) /*!< 0x00040000 */ -#define SYSCFG_SWPR2_PAGE50 SYSCFG_SWPR2_PAGE50_Msk /*!< SRAM2B Write protection page 18 (0x2003C800 – 0x2003CBFF) */ +#define SYSCFG_SWPR2_PAGE50 SYSCFG_SWPR2_PAGE50_Msk /*!< SRAM2B Write protection page 18 (0x2003C800 - 0x2003CBFF) */ #define SYSCFG_SWPR2_PAGE51_Pos (19U) #define SYSCFG_SWPR2_PAGE51_Msk (0x1UL << SYSCFG_SWPR2_PAGE51_Pos) /*!< 0x00080000 */ -#define SYSCFG_SWPR2_PAGE51 SYSCFG_SWPR2_PAGE51_Msk /*!< SRAM2B Write protection page 19 (0x2003CC00 – 0x2003CFFF) */ +#define SYSCFG_SWPR2_PAGE51 SYSCFG_SWPR2_PAGE51_Msk /*!< SRAM2B Write protection page 19 (0x2003CC00 - 0x2003CFFF) */ #define SYSCFG_SWPR2_PAGE52_Pos (20U) #define SYSCFG_SWPR2_PAGE52_Msk (0x1UL << SYSCFG_SWPR2_PAGE52_Pos) /*!< 0x00100000 */ -#define SYSCFG_SWPR2_PAGE52 SYSCFG_SWPR2_PAGE52_Msk /*!< SRAM2B Write protection page 20 (0x2003D000 – 0x2003D3FF) */ +#define SYSCFG_SWPR2_PAGE52 SYSCFG_SWPR2_PAGE52_Msk /*!< SRAM2B Write protection page 20 (0x2003D000 - 0x2003D3FF) */ #define SYSCFG_SWPR2_PAGE53_Pos (21U) #define SYSCFG_SWPR2_PAGE53_Msk (0x1UL << SYSCFG_SWPR2_PAGE53_Pos) /*!< 0x00200000 */ -#define SYSCFG_SWPR2_PAGE53 SYSCFG_SWPR2_PAGE53_Msk /*!< SRAM2B Write protection page 21 (0x2003D400 – 0x2003D7FF) */ +#define SYSCFG_SWPR2_PAGE53 SYSCFG_SWPR2_PAGE53_Msk /*!< SRAM2B Write protection page 21 (0x2003D400 - 0x2003D7FF) */ #define SYSCFG_SWPR2_PAGE54_Pos (22U) #define SYSCFG_SWPR2_PAGE54_Msk (0x1UL << SYSCFG_SWPR2_PAGE54_Pos) /*!< 0x00400000 */ -#define SYSCFG_SWPR2_PAGE54 SYSCFG_SWPR2_PAGE54_Msk /*!< SRAM2B Write protection page 22 (0x2003D800 – 0x2003DBFF) */ +#define SYSCFG_SWPR2_PAGE54 SYSCFG_SWPR2_PAGE54_Msk /*!< SRAM2B Write protection page 22 (0x2003D800 - 0x2003DBFF) */ #define SYSCFG_SWPR2_PAGE55_Pos (23U) #define SYSCFG_SWPR2_PAGE55_Msk (0x1UL << SYSCFG_SWPR2_PAGE55_Pos) /*!< 0x00800000 */ -#define SYSCFG_SWPR2_PAGE55 SYSCFG_SWPR2_PAGE55_Msk /*!< SRAM2B Write protection page 23 (0x2003DC00 – 0x2003DFFF) */ +#define SYSCFG_SWPR2_PAGE55 SYSCFG_SWPR2_PAGE55_Msk /*!< SRAM2B Write protection page 23 (0x2003DC00 - 0x2003DFFF) */ #define SYSCFG_SWPR2_PAGE56_Pos (24U) #define SYSCFG_SWPR2_PAGE56_Msk (0x1UL << SYSCFG_SWPR2_PAGE56_Pos) /*!< 0x01000000 */ -#define SYSCFG_SWPR2_PAGE56 SYSCFG_SWPR2_PAGE56_Msk /*!< SRAM2B Write protection page 24 (0x2003E000 – 0x2003E3FF) */ +#define SYSCFG_SWPR2_PAGE56 SYSCFG_SWPR2_PAGE56_Msk /*!< SRAM2B Write protection page 24 (0x2003E000 - 0x2003E3FF) */ #define SYSCFG_SWPR2_PAGE57_Pos (25U) #define SYSCFG_SWPR2_PAGE57_Msk (0x1UL << SYSCFG_SWPR2_PAGE57_Pos) /*!< 0x02000000 */ -#define SYSCFG_SWPR2_PAGE57 SYSCFG_SWPR2_PAGE57_Msk /*!< SRAM2B Write protection page 25 (0x2003E400 – 0x2003E7FF) */ +#define SYSCFG_SWPR2_PAGE57 SYSCFG_SWPR2_PAGE57_Msk /*!< SRAM2B Write protection page 25 (0x2003E400 - 0x2003E7FF) */ #define SYSCFG_SWPR2_PAGE58_Pos (26U) #define SYSCFG_SWPR2_PAGE58_Msk (0x1UL << SYSCFG_SWPR2_PAGE58_Pos) /*!< 0x04000000 */ -#define SYSCFG_SWPR2_PAGE58 SYSCFG_SWPR2_PAGE58_Msk /*!< SRAM2B Write protection page 26 (0x2003E800 – 0x2003EBFF) */ +#define SYSCFG_SWPR2_PAGE58 SYSCFG_SWPR2_PAGE58_Msk /*!< SRAM2B Write protection page 26 (0x2003E800 - 0x2003EBFF) */ #define SYSCFG_SWPR2_PAGE59_Pos (27U) #define SYSCFG_SWPR2_PAGE59_Msk (0x1UL << SYSCFG_SWPR2_PAGE59_Pos) /*!< 0x08000000 */ -#define SYSCFG_SWPR2_PAGE59 SYSCFG_SWPR2_PAGE59_Msk /*!< SRAM2B Write protection page 27 (0x2003EC00 – 0x2003EFFF) */ +#define SYSCFG_SWPR2_PAGE59 SYSCFG_SWPR2_PAGE59_Msk /*!< SRAM2B Write protection page 27 (0x2003EC00 - 0x2003EFFF) */ #define SYSCFG_SWPR2_PAGE60_Pos (28U) #define SYSCFG_SWPR2_PAGE60_Msk (0x1UL << SYSCFG_SWPR2_PAGE60_Pos) /*!< 0x10000000 */ -#define SYSCFG_SWPR2_PAGE60 SYSCFG_SWPR2_PAGE60_Msk /*!< SRAM2B Write protection page 28 (0x2003F000 – 0x2003F3FF) */ +#define SYSCFG_SWPR2_PAGE60 SYSCFG_SWPR2_PAGE60_Msk /*!< SRAM2B Write protection page 28 (0x2003F000 - 0x2003F3FF) */ #define SYSCFG_SWPR2_PAGE61_Pos (29U) #define SYSCFG_SWPR2_PAGE61_Msk (0x1UL << SYSCFG_SWPR2_PAGE61_Pos) /*!< 0x20000000 */ -#define SYSCFG_SWPR2_PAGE61 SYSCFG_SWPR2_PAGE61_Msk /*!< SRAM2B Write protection page 29 (0x2003F400 – 0x2003F7FF) */ +#define SYSCFG_SWPR2_PAGE61 SYSCFG_SWPR2_PAGE61_Msk /*!< SRAM2B Write protection page 29 (0x2003F400 - 0x2003F7FF) */ #define SYSCFG_SWPR2_PAGE62_Pos (30U) #define SYSCFG_SWPR2_PAGE62_Msk (0x1UL << SYSCFG_SWPR2_PAGE62_Pos) /*!< 0x40000000 */ -#define SYSCFG_SWPR2_PAGE62 SYSCFG_SWPR2_PAGE62_Msk /*!< SRAM2B Write protection page 30 (0x2003F800 – 0x2003FBFF) */ +#define SYSCFG_SWPR2_PAGE62 SYSCFG_SWPR2_PAGE62_Msk /*!< SRAM2B Write protection page 30 (0x2003F800 - 0x2003FBFF) */ #define SYSCFG_SWPR2_PAGE63_Pos (31U) #define SYSCFG_SWPR2_PAGE63_Msk (0x1UL << SYSCFG_SWPR2_PAGE63_Pos) /*!< 0x80000000 */ -#define SYSCFG_SWPR2_PAGE63 SYSCFG_SWPR2_PAGE63_Msk /*!< SRAM2B Write protection page 31 (0x2003FC00 – 0x2003FFFF) */ +#define SYSCFG_SWPR2_PAGE63 SYSCFG_SWPR2_PAGE63_Msk /*!< SRAM2B Write protection page 31 (0x2003FC00 - 0x2003FFFF) */ /***************** Bit definition for SYSCFG_IMR1 register (Interrupt masks control and status register on CPU1 - part 1) *******************************************/ #define SYSCFG_IMR1_TIM1IM_Pos (13U) @@ -13690,5 +13690,3 @@ typedef struct /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBxx/Include/stm32wb5mxx.h b/system/Drivers/CMSIS/Device/ST/STM32WBxx/Include/stm32wb5mxx.h index 2be7194a87..522dc2f168 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32WBxx/Include/stm32wb5mxx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32WBxx/Include/stm32wb5mxx.h @@ -487,7 +487,7 @@ uint32_t RESERVED6; /*!< Reserved, __IO uint32_t HSECR; /*!< RCC HSE Clock Register, Address offset: 0x9C */ uint32_t RESERVED7[26]; /*!< Reserved, Address offset: 0xA0-0x104 */ __IO uint32_t EXTCFGR; /*!< RCC Extended Clock Recovery Register, Address offset: 0x108 */ -uint32_t RESERVED8[15]; /*!< Reserved, Address offset: 0x10C-0x144 */ +uint32_t RESERVED8[15]; /*!< Reserved, Address offset: 0x10C-0x144 */ __IO uint32_t C2AHB1ENR; /*!< RRCC AHB1 peripheral CPU2 clocks enable register, Address offset: 0x148 */ __IO uint32_t C2AHB2ENR; /*!< RCC AHB2 peripheral CPU2 clocks enable register, Address offset: 0x14C */ __IO uint32_t C2AHB3ENR; /*!< RCC AHB3 & AHB4 peripheral CPU2 clocks enable register,, Address offset: 0x150 */ @@ -922,10 +922,10 @@ typedef struct /*!< Memory, OTP and Option bytes */ /* Base addresses */ -#define SYSTEM_MEMORY_BASE (0x1FFF0000UL) /*!< System Memory : 28Kb (0x1FFF0000 – 0x1FFF6FFF) */ -#define OTP_AREA_BASE (0x1FFF7000UL) /*!< OTP area : 1kB (0x1FFF7000 – 0x1FFF73FF) */ -#define OPTION_BYTE_BASE (0x1FFF8000UL) /*!< Option Bytes : 4kB (0x1FFF8000 – 0x1FFF8FFF) */ -#define ENGI_BYTE_BASE (0x1FFF7400UL) /*!< Engi Bytes : 3kB (0x1FFF7400 – 0x1FFF7FFF) */ +#define SYSTEM_MEMORY_BASE (0x1FFF0000UL) /*!< System Memory : 28Kb (0x1FFF0000 - 0x1FFF6FFF) */ +#define OTP_AREA_BASE (0x1FFF7000UL) /*!< OTP area : 1kB (0x1FFF7000 - 0x1FFF73FF) */ +#define OPTION_BYTE_BASE (0x1FFF8000UL) /*!< Option Bytes : 4kB (0x1FFF8000 - 0x1FFF8FFF) */ +#define ENGI_BYTE_BASE (0x1FFF7400UL) /*!< Engi Bytes : 3kB (0x1FFF7400 - 0x1FFF7FFF) */ #define SRAM1_BASE SRAM_BASE /*!< SRAM1(up to 192 KB) base address */ #define SRAM2A_BASE (SRAM_BASE + 0x00030000UL)/*!< SRAM2A(32 KB) base address */ @@ -938,14 +938,14 @@ typedef struct #define SRAM2B_SIZE 0x00008000UL /*!< SRAM2b default size : 32 kB */ /* End addresses */ -#define SRAM1_END_ADDR (0x2002FFFFUL) /*!< SRAM1 : 192KB (0x20000000 – 0x2002FFFF) */ -#define SRAM2A_END_ADDR (0x20037FFFUL) /*!< SRAM2a (backup) : 32KB (0x20030000 – 0x20037FFF) */ -#define SRAM2B_END_ADDR (0x2003FFFFUL) /*!< SRAM2b (non-backup) : 32KB (0x20038000 – 0x2003FFFF) */ +#define SRAM1_END_ADDR (0x2002FFFFUL) /*!< SRAM1 : 192KB (0x20000000 - 0x2002FFFF) */ +#define SRAM2A_END_ADDR (0x20037FFFUL) /*!< SRAM2a (backup) : 32KB (0x20030000 - 0x20037FFF) */ +#define SRAM2B_END_ADDR (0x2003FFFFUL) /*!< SRAM2b (non-backup) : 32KB (0x20038000 - 0x2003FFFF) */ -#define SYSTEM_MEMORY_END_ADDR (0x1FFF6FFFUL) /*!< System Memory : 28KB (0x1FFF0000 – 0x1FFF6FFF) */ -#define OTP_AREA_END_ADDR (0x1FFF73FFUL) /*!< OTP area : 1KB (0x1FFF7000 – 0x1FFF73FF) */ -#define OPTION_BYTE_END_ADDR (0x1FFF8FFFUL) /*!< Option Bytes : 4KB (0x1FFF8000 – 0x1FFF8FFF) */ -#define ENGI_BYTE_END_ADDR (0x1FFF7FFFUL) /*!< Engi Bytes : 3kB (0x1FFF7400 – 0x1FFF7FFF) */ +#define SYSTEM_MEMORY_END_ADDR (0x1FFF6FFFUL) /*!< System Memory : 28KB (0x1FFF0000 - 0x1FFF6FFF) */ +#define OTP_AREA_END_ADDR (0x1FFF73FFUL) /*!< OTP area : 1KB (0x1FFF7000 - 0x1FFF73FF) */ +#define OPTION_BYTE_END_ADDR (0x1FFF8FFFUL) /*!< Option Bytes : 4KB (0x1FFF8000 - 0x1FFF8FFF) */ +#define ENGI_BYTE_END_ADDR (0x1FFF7FFFUL) /*!< Engi Bytes : 3kB (0x1FFF7400 - 0x1FFF7FFF) */ /*!< Peripheral memory map */ #define APB1PERIPH_BASE PERIPH_BASE @@ -1338,7 +1338,7 @@ typedef struct #define ADC_CFGR_ALIGN_Pos (5U) #define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00000020 */ -#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */ +#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignment */ #define ADC_CFGR_EXTSEL_Pos (6U) #define ADC_CFGR_EXTSEL_Msk (0xFUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003C0 */ @@ -3951,12 +3951,12 @@ typedef struct /* Arithmetic addition output data */ #define PKA_ARITHMETIC_ADD_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ -/* Arithmetic substraction input data */ +/* Arithmetic subtraction input data */ #define PKA_ARITHMETIC_SUB_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ #define PKA_ARITHMETIC_SUB_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ #define PKA_ARITHMETIC_SUB_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ -/* Arithmetic substraction output data */ +/* Arithmetic subtraction output data */ #define PKA_ARITHMETIC_SUB_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ /* Arithmetic multiplication input data */ @@ -3992,13 +3992,13 @@ typedef struct /* Modular inversion output data */ #define PKA_MODULAR_INV_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ -/* Modular substraction input data */ +/* Modular subtraction input data */ #define PKA_MODULAR_SUB_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ #define PKA_MODULAR_SUB_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ #define PKA_MODULAR_SUB_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ #define PKA_MODULAR_SUB_IN_OP3_MOD ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 */ -/* Modular substraction output data */ +/* Modular subtraction output data */ #define PKA_MODULAR_SUB_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ /* Montgomery multiplication input data */ @@ -8746,10 +8746,10 @@ typedef struct #define RTC_CR_OSEL_1 (0x2U << RTC_CR_OSEL_Pos) /*!< 0x00400000 */ #define RTC_CR_POL_Pos (20U) #define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */ -#define RTC_CR_POL RTC_CR_POL_Msk /*!< Ouput polarity */ +#define RTC_CR_POL RTC_CR_POL_Msk /*!< Output polarity */ #define RTC_CR_COSEL_Pos (19U) #define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ -#define RTC_CR_COSEL RTC_CR_COSEL_Msk /*!< Calibration ouput selection */ +#define RTC_CR_COSEL RTC_CR_COSEL_Msk /*!< Calibration output selection */ #define RTC_CR_BKP_Pos (18U) #define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */ #define RTC_CR_BKP RTC_CR_BKP_Msk /*!< Backup */ @@ -9024,7 +9024,7 @@ typedef struct /******************** Bits definition for RTC_SHIFTR register ***************/ #define RTC_SHIFTR_SUBFS_Pos (0U) #define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */ -#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk /*!< Substract a fraction of a second */ +#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk /*!< Subtract a fraction of a second */ #define RTC_SHIFTR_ADD1S_Pos (31U) #define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */ #define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk /*!< Add on second */ @@ -10714,100 +10714,100 @@ typedef struct /***************** Bit definition for SYSCFG_SWPR1 register (SYSCFG SRAM2A write protection register) *********************************************************/ #define SYSCFG_SWPR1_PAGE0_Pos (0U) #define SYSCFG_SWPR1_PAGE0_Msk (0x1UL << SYSCFG_SWPR1_PAGE0_Pos) /*!< 0x00000001 */ -#define SYSCFG_SWPR1_PAGE0 SYSCFG_SWPR1_PAGE0_Msk /*!< SRAM2A Write protection page 0 (0x20030000 – 0x200303FF) */ +#define SYSCFG_SWPR1_PAGE0 SYSCFG_SWPR1_PAGE0_Msk /*!< SRAM2A Write protection page 0 (0x20030000 - 0x200303FF) */ #define SYSCFG_SWPR1_PAGE1_Pos (1U) #define SYSCFG_SWPR1_PAGE1_Msk (0x1UL << SYSCFG_SWPR1_PAGE1_Pos) /*!< 0x00000002 */ -#define SYSCFG_SWPR1_PAGE1 SYSCFG_SWPR1_PAGE1_Msk /*!< SRAM2A Write protection page 1 (0x20030400 – 0x200307FF) */ +#define SYSCFG_SWPR1_PAGE1 SYSCFG_SWPR1_PAGE1_Msk /*!< SRAM2A Write protection page 1 (0x20030400 - 0x200307FF) */ #define SYSCFG_SWPR1_PAGE2_Pos (2U) #define SYSCFG_SWPR1_PAGE2_Msk (0x1UL << SYSCFG_SWPR1_PAGE2_Pos) /*!< 0x00000004 */ -#define SYSCFG_SWPR1_PAGE2 SYSCFG_SWPR1_PAGE2_Msk /*!< SRAM2A Write protection page 2 (0x20030800 – 0x20030BFF) */ +#define SYSCFG_SWPR1_PAGE2 SYSCFG_SWPR1_PAGE2_Msk /*!< SRAM2A Write protection page 2 (0x20030800 - 0x20030BFF) */ #define SYSCFG_SWPR1_PAGE3_Pos (3U) #define SYSCFG_SWPR1_PAGE3_Msk (0x1UL << SYSCFG_SWPR1_PAGE3_Pos) /*!< 0x00000008 */ -#define SYSCFG_SWPR1_PAGE3 SYSCFG_SWPR1_PAGE3_Msk /*!< SRAM2A Write protection page 3 (0x20030C00 – 0x20030FFF) */ +#define SYSCFG_SWPR1_PAGE3 SYSCFG_SWPR1_PAGE3_Msk /*!< SRAM2A Write protection page 3 (0x20030C00 - 0x20030FFF) */ #define SYSCFG_SWPR1_PAGE4_Pos (4U) #define SYSCFG_SWPR1_PAGE4_Msk (0x1UL << SYSCFG_SWPR1_PAGE4_Pos) /*!< 0x00000010 */ -#define SYSCFG_SWPR1_PAGE4 SYSCFG_SWPR1_PAGE4_Msk /*!< SRAM2A Write protection page 4 (0x20031000 – 0x200313FF) */ +#define SYSCFG_SWPR1_PAGE4 SYSCFG_SWPR1_PAGE4_Msk /*!< SRAM2A Write protection page 4 (0x20031000 - 0x200313FF) */ #define SYSCFG_SWPR1_PAGE5_Pos (5U) #define SYSCFG_SWPR1_PAGE5_Msk (0x1UL << SYSCFG_SWPR1_PAGE5_Pos) /*!< 0x00000020 */ -#define SYSCFG_SWPR1_PAGE5 SYSCFG_SWPR1_PAGE5_Msk /*!< SRAM2A Write protection page 5 (0x20031400 – 0x200317FF) */ +#define SYSCFG_SWPR1_PAGE5 SYSCFG_SWPR1_PAGE5_Msk /*!< SRAM2A Write protection page 5 (0x20031400 - 0x200317FF) */ #define SYSCFG_SWPR1_PAGE6_Pos (6U) #define SYSCFG_SWPR1_PAGE6_Msk (0x1UL << SYSCFG_SWPR1_PAGE6_Pos) /*!< 0x00000040 */ -#define SYSCFG_SWPR1_PAGE6 SYSCFG_SWPR1_PAGE6_Msk /*!< SRAM2A Write protection page 6 (0x20031800 – 0x20031BFF) */ +#define SYSCFG_SWPR1_PAGE6 SYSCFG_SWPR1_PAGE6_Msk /*!< SRAM2A Write protection page 6 (0x20031800 - 0x20031BFF) */ #define SYSCFG_SWPR1_PAGE7_Pos (7U) #define SYSCFG_SWPR1_PAGE7_Msk (0x1UL << SYSCFG_SWPR1_PAGE7_Pos) /*!< 0x00000080 */ -#define SYSCFG_SWPR1_PAGE7 SYSCFG_SWPR1_PAGE7_Msk /*!< SRAM2A Write protection page 7 (0x20031C00 – 0x20031FFF) */ +#define SYSCFG_SWPR1_PAGE7 SYSCFG_SWPR1_PAGE7_Msk /*!< SRAM2A Write protection page 7 (0x20031C00 - 0x20031FFF) */ #define SYSCFG_SWPR1_PAGE8_Pos (8U) #define SYSCFG_SWPR1_PAGE8_Msk (0x1UL << SYSCFG_SWPR1_PAGE8_Pos) /*!< 0x00000100 */ -#define SYSCFG_SWPR1_PAGE8 SYSCFG_SWPR1_PAGE8_Msk /*!< SRAM2A Write protection page 8 (0x20032000 – 0x200323FF) */ +#define SYSCFG_SWPR1_PAGE8 SYSCFG_SWPR1_PAGE8_Msk /*!< SRAM2A Write protection page 8 (0x20032000 - 0x200323FF) */ #define SYSCFG_SWPR1_PAGE9_Pos (9U) #define SYSCFG_SWPR1_PAGE9_Msk (0x1UL << SYSCFG_SWPR1_PAGE9_Pos) /*!< 0x00000200 */ -#define SYSCFG_SWPR1_PAGE9 SYSCFG_SWPR1_PAGE9_Msk /*!< SRAM2A Write protection page 9 (0x20032400 – 0x200327FF) */ +#define SYSCFG_SWPR1_PAGE9 SYSCFG_SWPR1_PAGE9_Msk /*!< SRAM2A Write protection page 9 (0x20032400 - 0x200327FF) */ #define SYSCFG_SWPR1_PAGE10_Pos (10U) #define SYSCFG_SWPR1_PAGE10_Msk (0x1UL << SYSCFG_SWPR1_PAGE10_Pos) /*!< 0x00000400 */ -#define SYSCFG_SWPR1_PAGE10 SYSCFG_SWPR1_PAGE10_Msk /*!< SRAM2A Write protection page 10 (0x20032800 – 0x20032BFF) */ +#define SYSCFG_SWPR1_PAGE10 SYSCFG_SWPR1_PAGE10_Msk /*!< SRAM2A Write protection page 10 (0x20032800 - 0x20032BFF) */ #define SYSCFG_SWPR1_PAGE11_Pos (11U) #define SYSCFG_SWPR1_PAGE11_Msk (0x1UL << SYSCFG_SWPR1_PAGE11_Pos) /*!< 0x00000800 */ -#define SYSCFG_SWPR1_PAGE11 SYSCFG_SWPR1_PAGE11_Msk /*!< SRAM2A Write protection page 11 (0x20032C00 – 0x20032FFF) */ +#define SYSCFG_SWPR1_PAGE11 SYSCFG_SWPR1_PAGE11_Msk /*!< SRAM2A Write protection page 11 (0x20032C00 - 0x20032FFF) */ #define SYSCFG_SWPR1_PAGE12_Pos (12U) #define SYSCFG_SWPR1_PAGE12_Msk (0x1UL << SYSCFG_SWPR1_PAGE12_Pos) /*!< 0x00001000 */ -#define SYSCFG_SWPR1_PAGE12 SYSCFG_SWPR1_PAGE12_Msk /*!< SRAM2A Write protection page 12 (0x20033000 – 0x200333FF) */ +#define SYSCFG_SWPR1_PAGE12 SYSCFG_SWPR1_PAGE12_Msk /*!< SRAM2A Write protection page 12 (0x20033000 - 0x200333FF) */ #define SYSCFG_SWPR1_PAGE13_Pos (13U) #define SYSCFG_SWPR1_PAGE13_Msk (0x1UL << SYSCFG_SWPR1_PAGE13_Pos) /*!< 0x00002000 */ -#define SYSCFG_SWPR1_PAGE13 SYSCFG_SWPR1_PAGE13_Msk /*!< SRAM2A Write protection page 13 (0x20033400 – 0x200337FF) */ +#define SYSCFG_SWPR1_PAGE13 SYSCFG_SWPR1_PAGE13_Msk /*!< SRAM2A Write protection page 13 (0x20033400 - 0x200337FF) */ #define SYSCFG_SWPR1_PAGE14_Pos (14U) #define SYSCFG_SWPR1_PAGE14_Msk (0x1UL << SYSCFG_SWPR1_PAGE14_Pos) /*!< 0x00004000 */ -#define SYSCFG_SWPR1_PAGE14 SYSCFG_SWPR1_PAGE14_Msk /*!< SRAM2A Write protection page 14 (0x20033800 – 0x20033BFF) */ +#define SYSCFG_SWPR1_PAGE14 SYSCFG_SWPR1_PAGE14_Msk /*!< SRAM2A Write protection page 14 (0x20033800 - 0x20033BFF) */ #define SYSCFG_SWPR1_PAGE15_Pos (15U) #define SYSCFG_SWPR1_PAGE15_Msk (0x1UL << SYSCFG_SWPR1_PAGE15_Pos) /*!< 0x00008000 */ -#define SYSCFG_SWPR1_PAGE15 SYSCFG_SWPR1_PAGE15_Msk /*!< SRAM2A Write protection page 15 (0x20033C00 – 0x20033FFF) */ +#define SYSCFG_SWPR1_PAGE15 SYSCFG_SWPR1_PAGE15_Msk /*!< SRAM2A Write protection page 15 (0x20033C00 - 0x20033FFF) */ #define SYSCFG_SWPR1_PAGE16_Pos (16U) #define SYSCFG_SWPR1_PAGE16_Msk (0x1UL << SYSCFG_SWPR1_PAGE16_Pos) /*!< 0x00010000 */ -#define SYSCFG_SWPR1_PAGE16 SYSCFG_SWPR1_PAGE16_Msk /*!< SRAM2A Write protection page 16 (0x20034000 – 0x200343FF) */ +#define SYSCFG_SWPR1_PAGE16 SYSCFG_SWPR1_PAGE16_Msk /*!< SRAM2A Write protection page 16 (0x20034000 - 0x200343FF) */ #define SYSCFG_SWPR1_PAGE17_Pos (17U) #define SYSCFG_SWPR1_PAGE17_Msk (0x1UL << SYSCFG_SWPR1_PAGE17_Pos) /*!< 0x00020000 */ -#define SYSCFG_SWPR1_PAGE17 SYSCFG_SWPR1_PAGE17_Msk /*!< SRAM2A Write protection page 17 (0x20034400 – 0x200347FF) */ +#define SYSCFG_SWPR1_PAGE17 SYSCFG_SWPR1_PAGE17_Msk /*!< SRAM2A Write protection page 17 (0x20034400 - 0x200347FF) */ #define SYSCFG_SWPR1_PAGE18_Pos (18U) #define SYSCFG_SWPR1_PAGE18_Msk (0x1UL << SYSCFG_SWPR1_PAGE18_Pos) /*!< 0x00040000 */ -#define SYSCFG_SWPR1_PAGE18 SYSCFG_SWPR1_PAGE18_Msk /*!< SRAM2A Write protection page 18 (0x20034800 – 0x20034BFF) */ +#define SYSCFG_SWPR1_PAGE18 SYSCFG_SWPR1_PAGE18_Msk /*!< SRAM2A Write protection page 18 (0x20034800 - 0x20034BFF) */ #define SYSCFG_SWPR1_PAGE19_Pos (19U) #define SYSCFG_SWPR1_PAGE19_Msk (0x1UL << SYSCFG_SWPR1_PAGE19_Pos) /*!< 0x00080000 */ -#define SYSCFG_SWPR1_PAGE19 SYSCFG_SWPR1_PAGE19_Msk /*!< SRAM2A Write protection page 19 (0x20034C00 – 0x20034FFF) */ +#define SYSCFG_SWPR1_PAGE19 SYSCFG_SWPR1_PAGE19_Msk /*!< SRAM2A Write protection page 19 (0x20034C00 - 0x20034FFF) */ #define SYSCFG_SWPR1_PAGE20_Pos (20U) #define SYSCFG_SWPR1_PAGE20_Msk (0x1UL << SYSCFG_SWPR1_PAGE20_Pos) /*!< 0x00100000 */ -#define SYSCFG_SWPR1_PAGE20 SYSCFG_SWPR1_PAGE20_Msk /*!< SRAM2A Write protection page 20 (0x20035000 – 0x200353FF) */ +#define SYSCFG_SWPR1_PAGE20 SYSCFG_SWPR1_PAGE20_Msk /*!< SRAM2A Write protection page 20 (0x20035000 - 0x200353FF) */ #define SYSCFG_SWPR1_PAGE21_Pos (21U) #define SYSCFG_SWPR1_PAGE21_Msk (0x1UL << SYSCFG_SWPR1_PAGE21_Pos) /*!< 0x00200000 */ -#define SYSCFG_SWPR1_PAGE21 SYSCFG_SWPR1_PAGE21_Msk /*!< SRAM2A Write protection page 21 (0x20035400 – 0x200357FF) */ +#define SYSCFG_SWPR1_PAGE21 SYSCFG_SWPR1_PAGE21_Msk /*!< SRAM2A Write protection page 21 (0x20035400 - 0x200357FF) */ #define SYSCFG_SWPR1_PAGE22_Pos (22U) #define SYSCFG_SWPR1_PAGE22_Msk (0x1UL << SYSCFG_SWPR1_PAGE22_Pos) /*!< 0x00400000 */ -#define SYSCFG_SWPR1_PAGE22 SYSCFG_SWPR1_PAGE22_Msk /*!< SRAM2A Write protection page 22 (0x20035800 – 0x20035BFF) */ +#define SYSCFG_SWPR1_PAGE22 SYSCFG_SWPR1_PAGE22_Msk /*!< SRAM2A Write protection page 22 (0x20035800 - 0x20035BFF) */ #define SYSCFG_SWPR1_PAGE23_Pos (23U) #define SYSCFG_SWPR1_PAGE23_Msk (0x1UL << SYSCFG_SWPR1_PAGE23_Pos) /*!< 0x00800000 */ -#define SYSCFG_SWPR1_PAGE23 SYSCFG_SWPR1_PAGE23_Msk /*!< SRAM2A Write protection page 23 (0x20035C00 – 0x20035FFF) */ +#define SYSCFG_SWPR1_PAGE23 SYSCFG_SWPR1_PAGE23_Msk /*!< SRAM2A Write protection page 23 (0x20035C00 - 0x20035FFF) */ #define SYSCFG_SWPR1_PAGE24_Pos (24U) #define SYSCFG_SWPR1_PAGE24_Msk (0x1UL << SYSCFG_SWPR1_PAGE24_Pos) /*!< 0x01000000 */ -#define SYSCFG_SWPR1_PAGE24 SYSCFG_SWPR1_PAGE24_Msk /*!< SRAM2A Write protection page 24 (0x20036000 – 0x200363FF) */ +#define SYSCFG_SWPR1_PAGE24 SYSCFG_SWPR1_PAGE24_Msk /*!< SRAM2A Write protection page 24 (0x20036000 - 0x200363FF) */ #define SYSCFG_SWPR1_PAGE25_Pos (25U) #define SYSCFG_SWPR1_PAGE25_Msk (0x1UL << SYSCFG_SWPR1_PAGE25_Pos) /*!< 0x02000000 */ -#define SYSCFG_SWPR1_PAGE25 SYSCFG_SWPR1_PAGE25_Msk /*!< SRAM2A Write protection page 25 (0x20036400 – 0x200367FF) */ +#define SYSCFG_SWPR1_PAGE25 SYSCFG_SWPR1_PAGE25_Msk /*!< SRAM2A Write protection page 25 (0x20036400 - 0x200367FF) */ #define SYSCFG_SWPR1_PAGE26_Pos (26U) #define SYSCFG_SWPR1_PAGE26_Msk (0x1UL << SYSCFG_SWPR1_PAGE26_Pos) /*!< 0x04000000 */ -#define SYSCFG_SWPR1_PAGE26 SYSCFG_SWPR1_PAGE26_Msk /*!< SRAM2A Write protection page 26 (0x20036800 – 0x20036BFF) */ +#define SYSCFG_SWPR1_PAGE26 SYSCFG_SWPR1_PAGE26_Msk /*!< SRAM2A Write protection page 26 (0x20036800 - 0x20036BFF) */ #define SYSCFG_SWPR1_PAGE27_Pos (27U) #define SYSCFG_SWPR1_PAGE27_Msk (0x1UL << SYSCFG_SWPR1_PAGE27_Pos) /*!< 0x08000000 */ -#define SYSCFG_SWPR1_PAGE27 SYSCFG_SWPR1_PAGE27_Msk /*!< SRAM2A Write protection page 27 (0x20036C00 – 0x20036FFF) */ +#define SYSCFG_SWPR1_PAGE27 SYSCFG_SWPR1_PAGE27_Msk /*!< SRAM2A Write protection page 27 (0x20036C00 - 0x20036FFF) */ #define SYSCFG_SWPR1_PAGE28_Pos (28U) #define SYSCFG_SWPR1_PAGE28_Msk (0x1UL << SYSCFG_SWPR1_PAGE28_Pos) /*!< 0x10000000 */ -#define SYSCFG_SWPR1_PAGE28 SYSCFG_SWPR1_PAGE28_Msk /*!< SRAM2A Write protection page 28 (0x20037000 – 0x200373FF) */ +#define SYSCFG_SWPR1_PAGE28 SYSCFG_SWPR1_PAGE28_Msk /*!< SRAM2A Write protection page 28 (0x20037000 - 0x200373FF) */ #define SYSCFG_SWPR1_PAGE29_Pos (29U) #define SYSCFG_SWPR1_PAGE29_Msk (0x1UL << SYSCFG_SWPR1_PAGE29_Pos) /*!< 0x20000000 */ -#define SYSCFG_SWPR1_PAGE29 SYSCFG_SWPR1_PAGE29_Msk /*!< SRAM2A Write protection page 29 (0x20037400 – 0x200377FF) */ +#define SYSCFG_SWPR1_PAGE29 SYSCFG_SWPR1_PAGE29_Msk /*!< SRAM2A Write protection page 29 (0x20037400 - 0x200377FF) */ #define SYSCFG_SWPR1_PAGE30_Pos (30U) #define SYSCFG_SWPR1_PAGE30_Msk (0x1UL << SYSCFG_SWPR1_PAGE30_Pos) /*!< 0x40000000 */ -#define SYSCFG_SWPR1_PAGE30 SYSCFG_SWPR1_PAGE30_Msk /*!< SRAM2A Write protection page 30 (0x20037800 – 0x20037BFF) */ +#define SYSCFG_SWPR1_PAGE30 SYSCFG_SWPR1_PAGE30_Msk /*!< SRAM2A Write protection page 30 (0x20037800 - 0x20037BFF) */ #define SYSCFG_SWPR1_PAGE31_Pos (31U) #define SYSCFG_SWPR1_PAGE31_Msk (0x1UL << SYSCFG_SWPR1_PAGE31_Pos) /*!< 0x80000000 */ -#define SYSCFG_SWPR1_PAGE31 SYSCFG_SWPR1_PAGE31_Msk /*!< SRAM2A Write protection page 31 (0x20037C00 – 0x20037FFF) */ +#define SYSCFG_SWPR1_PAGE31 SYSCFG_SWPR1_PAGE31_Msk /*!< SRAM2A Write protection page 31 (0x20037C00 - 0x20037FFF) */ /***************** Bit definition for SYSCFG_SKR register (SYSCFG SRAM2 key register) *************************************************************************/ #define SYSCFG_SKR_KEY_Pos (0U) @@ -10817,100 +10817,100 @@ typedef struct /***************** Bit definition for SYSCFG_SWPR2 register (SYSCFG SRAM2 write protection register) **********************************************************/ #define SYSCFG_SWPR2_PAGE32_Pos (0U) #define SYSCFG_SWPR2_PAGE32_Msk (0x1UL << SYSCFG_SWPR2_PAGE32_Pos) /*!< 0x00000001 */ -#define SYSCFG_SWPR2_PAGE32 SYSCFG_SWPR2_PAGE32_Msk /*!< SRAM2B Write protection page 0 (0x20038000 – 0x200383FF) */ +#define SYSCFG_SWPR2_PAGE32 SYSCFG_SWPR2_PAGE32_Msk /*!< SRAM2B Write protection page 0 (0x20038000 - 0x200383FF) */ #define SYSCFG_SWPR2_PAGE33_Pos (1U) #define SYSCFG_SWPR2_PAGE33_Msk (0x1UL << SYSCFG_SWPR2_PAGE33_Pos) /*!< 0x00000002 */ -#define SYSCFG_SWPR2_PAGE33 SYSCFG_SWPR2_PAGE33_Msk /*!< SRAM2B Write protection page 1 (0x20038400 – 0x200387FF) */ +#define SYSCFG_SWPR2_PAGE33 SYSCFG_SWPR2_PAGE33_Msk /*!< SRAM2B Write protection page 1 (0x20038400 - 0x200387FF) */ #define SYSCFG_SWPR2_PAGE34_Pos (2U) #define SYSCFG_SWPR2_PAGE34_Msk (0x1UL << SYSCFG_SWPR2_PAGE34_Pos) /*!< 0x00000004 */ -#define SYSCFG_SWPR2_PAGE34 SYSCFG_SWPR2_PAGE34_Msk /*!< SRAM2B Write protection page 2 (0x20038800 – 0x20038bFF) */ +#define SYSCFG_SWPR2_PAGE34 SYSCFG_SWPR2_PAGE34_Msk /*!< SRAM2B Write protection page 2 (0x20038800 - 0x20038bFF) */ #define SYSCFG_SWPR2_PAGE35_Pos (3U) #define SYSCFG_SWPR2_PAGE35_Msk (0x1UL << SYSCFG_SWPR2_PAGE35_Pos) /*!< 0x00000008 */ -#define SYSCFG_SWPR2_PAGE35 SYSCFG_SWPR2_PAGE35_Msk /*!< SRAM2B Write protection page 3 (0x20038C00 – 0x20038FFF) */ +#define SYSCFG_SWPR2_PAGE35 SYSCFG_SWPR2_PAGE35_Msk /*!< SRAM2B Write protection page 3 (0x20038C00 - 0x20038FFF) */ #define SYSCFG_SWPR2_PAGE36_Pos (4U) #define SYSCFG_SWPR2_PAGE36_Msk (0x1UL << SYSCFG_SWPR2_PAGE36_Pos) /*!< 0x00000010 */ -#define SYSCFG_SWPR2_PAGE36 SYSCFG_SWPR2_PAGE36_Msk /*!< SRAM2B Write protection page 4 (0x20039000 – 0x200393FF) */ +#define SYSCFG_SWPR2_PAGE36 SYSCFG_SWPR2_PAGE36_Msk /*!< SRAM2B Write protection page 4 (0x20039000 - 0x200393FF) */ #define SYSCFG_SWPR2_PAGE37_Pos (5U) #define SYSCFG_SWPR2_PAGE37_Msk (0x1UL << SYSCFG_SWPR2_PAGE37_Pos) /*!< 0x00000020 */ -#define SYSCFG_SWPR2_PAGE37 SYSCFG_SWPR2_PAGE37_Msk /*!< SRAM2B Write protection page 5 (0x20039400 – 0x200397FF) */ +#define SYSCFG_SWPR2_PAGE37 SYSCFG_SWPR2_PAGE37_Msk /*!< SRAM2B Write protection page 5 (0x20039400 - 0x200397FF) */ #define SYSCFG_SWPR2_PAGE38_Pos (6U) #define SYSCFG_SWPR2_PAGE38_Msk (0x1UL << SYSCFG_SWPR2_PAGE38_Pos) /*!< 0x00000040 */ -#define SYSCFG_SWPR2_PAGE38 SYSCFG_SWPR2_PAGE38_Msk /*!< SRAM2B Write protection page 6 (0x20039800 – 0x20039BFF) */ +#define SYSCFG_SWPR2_PAGE38 SYSCFG_SWPR2_PAGE38_Msk /*!< SRAM2B Write protection page 6 (0x20039800 - 0x20039BFF) */ #define SYSCFG_SWPR2_PAGE39_Pos (7U) #define SYSCFG_SWPR2_PAGE39_Msk (0x1UL << SYSCFG_SWPR2_PAGE39_Pos) /*!< 0x00000080 */ -#define SYSCFG_SWPR2_PAGE39 SYSCFG_SWPR2_PAGE39_Msk /*!< SRAM2B Write protection page 7 (0x20039C00 – 0x20039FFF) */ +#define SYSCFG_SWPR2_PAGE39 SYSCFG_SWPR2_PAGE39_Msk /*!< SRAM2B Write protection page 7 (0x20039C00 - 0x20039FFF) */ #define SYSCFG_SWPR2_PAGE40_Pos (8U) #define SYSCFG_SWPR2_PAGE40_Msk (0x1UL << SYSCFG_SWPR2_PAGE40_Pos) /*!< 0x00000100 */ -#define SYSCFG_SWPR2_PAGE40 SYSCFG_SWPR2_PAGE40_Msk /*!< SRAM2B Write protection page 8 (0x2003A000 – 0x2003A3FF) */ +#define SYSCFG_SWPR2_PAGE40 SYSCFG_SWPR2_PAGE40_Msk /*!< SRAM2B Write protection page 8 (0x2003A000 - 0x2003A3FF) */ #define SYSCFG_SWPR2_PAGE41_Pos (9U) #define SYSCFG_SWPR2_PAGE41_Msk (0x1UL << SYSCFG_SWPR2_PAGE41_Pos) /*!< 0x00000200 */ -#define SYSCFG_SWPR2_PAGE41 SYSCFG_SWPR2_PAGE41_Msk /*!< SRAM2B Write protection page 9 (0x2003A400 – 0x2003A7FF) */ +#define SYSCFG_SWPR2_PAGE41 SYSCFG_SWPR2_PAGE41_Msk /*!< SRAM2B Write protection page 9 (0x2003A400 - 0x2003A7FF) */ #define SYSCFG_SWPR2_PAGE42_Pos (10U) #define SYSCFG_SWPR2_PAGE42_Msk (0x1UL << SYSCFG_SWPR2_PAGE42_Pos) /*!< 0x00000400 */ -#define SYSCFG_SWPR2_PAGE42 SYSCFG_SWPR2_PAGE42_Msk /*!< SRAM2B Write protection page 10 (0x2003A800 – 0x2003ABFF) */ +#define SYSCFG_SWPR2_PAGE42 SYSCFG_SWPR2_PAGE42_Msk /*!< SRAM2B Write protection page 10 (0x2003A800 - 0x2003ABFF) */ #define SYSCFG_SWPR2_PAGE43_Pos (11U) #define SYSCFG_SWPR2_PAGE43_Msk (0x1UL << SYSCFG_SWPR2_PAGE43_Pos) /*!< 0x00000800 */ -#define SYSCFG_SWPR2_PAGE43 SYSCFG_SWPR2_PAGE43_Msk /*!< SRAM2B Write protection page 11 (0x2003AC00 – 0x2003AFFF) */ +#define SYSCFG_SWPR2_PAGE43 SYSCFG_SWPR2_PAGE43_Msk /*!< SRAM2B Write protection page 11 (0x2003AC00 - 0x2003AFFF) */ #define SYSCFG_SWPR2_PAGE44_Pos (12U) #define SYSCFG_SWPR2_PAGE44_Msk (0x1UL << SYSCFG_SWPR2_PAGE44_Pos) /*!< 0x00001000 */ -#define SYSCFG_SWPR2_PAGE44 SYSCFG_SWPR2_PAGE44_Msk /*!< SRAM2B Write protection page 12 (0x2003B000 – 0x2003B3FF) */ +#define SYSCFG_SWPR2_PAGE44 SYSCFG_SWPR2_PAGE44_Msk /*!< SRAM2B Write protection page 12 (0x2003B000 - 0x2003B3FF) */ #define SYSCFG_SWPR2_PAGE45_Pos (13U) #define SYSCFG_SWPR2_PAGE45_Msk (0x1UL << SYSCFG_SWPR2_PAGE45_Pos) /*!< 0x00002000 */ -#define SYSCFG_SWPR2_PAGE45 SYSCFG_SWPR2_PAGE45_Msk /*!< SRAM2B Write protection page 13 (0x2003B400 – 0x2003B7FF) */ +#define SYSCFG_SWPR2_PAGE45 SYSCFG_SWPR2_PAGE45_Msk /*!< SRAM2B Write protection page 13 (0x2003B400 - 0x2003B7FF) */ #define SYSCFG_SWPR2_PAGE46_Pos (14U) #define SYSCFG_SWPR2_PAGE46_Msk (0x1UL << SYSCFG_SWPR2_PAGE46_Pos) /*!< 0x00004000 */ -#define SYSCFG_SWPR2_PAGE46 SYSCFG_SWPR2_PAGE46_Msk /*!< SRAM2B Write protection page 14 (0x2003B800 – 0x2003BBFF) */ +#define SYSCFG_SWPR2_PAGE46 SYSCFG_SWPR2_PAGE46_Msk /*!< SRAM2B Write protection page 14 (0x2003B800 - 0x2003BBFF) */ #define SYSCFG_SWPR2_PAGE47_Pos (15U) #define SYSCFG_SWPR2_PAGE47_Msk (0x1UL << SYSCFG_SWPR2_PAGE47_Pos) /*!< 0x00008000 */ -#define SYSCFG_SWPR2_PAGE47 SYSCFG_SWPR2_PAGE47_Msk /*!< SRAM2B Write protection page 15 (0x2003BC00 – 0x2003BFFF) */ +#define SYSCFG_SWPR2_PAGE47 SYSCFG_SWPR2_PAGE47_Msk /*!< SRAM2B Write protection page 15 (0x2003BC00 - 0x2003BFFF) */ #define SYSCFG_SWPR2_PAGE48_Pos (16U) #define SYSCFG_SWPR2_PAGE48_Msk (0x1UL << SYSCFG_SWPR2_PAGE48_Pos) /*!< 0x00010000 */ -#define SYSCFG_SWPR2_PAGE48 SYSCFG_SWPR2_PAGE48_Msk /*!< SRAM2B Write protection page 16 (0x2003C000 – 0x2003C3FF) */ +#define SYSCFG_SWPR2_PAGE48 SYSCFG_SWPR2_PAGE48_Msk /*!< SRAM2B Write protection page 16 (0x2003C000 - 0x2003C3FF) */ #define SYSCFG_SWPR2_PAGE49_Pos (17U) #define SYSCFG_SWPR2_PAGE49_Msk (0x1UL << SYSCFG_SWPR2_PAGE49_Pos) /*!< 0x00020000 */ -#define SYSCFG_SWPR2_PAGE49 SYSCFG_SWPR2_PAGE49_Msk /*!< SRAM2B Write protection page 17 (0x2003C400 – 0x2003C7FF) */ +#define SYSCFG_SWPR2_PAGE49 SYSCFG_SWPR2_PAGE49_Msk /*!< SRAM2B Write protection page 17 (0x2003C400 - 0x2003C7FF) */ #define SYSCFG_SWPR2_PAGE50_Pos (18U) #define SYSCFG_SWPR2_PAGE50_Msk (0x1UL << SYSCFG_SWPR2_PAGE50_Pos) /*!< 0x00040000 */ -#define SYSCFG_SWPR2_PAGE50 SYSCFG_SWPR2_PAGE50_Msk /*!< SRAM2B Write protection page 18 (0x2003C800 – 0x2003CBFF) */ +#define SYSCFG_SWPR2_PAGE50 SYSCFG_SWPR2_PAGE50_Msk /*!< SRAM2B Write protection page 18 (0x2003C800 - 0x2003CBFF) */ #define SYSCFG_SWPR2_PAGE51_Pos (19U) #define SYSCFG_SWPR2_PAGE51_Msk (0x1UL << SYSCFG_SWPR2_PAGE51_Pos) /*!< 0x00080000 */ -#define SYSCFG_SWPR2_PAGE51 SYSCFG_SWPR2_PAGE51_Msk /*!< SRAM2B Write protection page 19 (0x2003CC00 – 0x2003CFFF) */ +#define SYSCFG_SWPR2_PAGE51 SYSCFG_SWPR2_PAGE51_Msk /*!< SRAM2B Write protection page 19 (0x2003CC00 - 0x2003CFFF) */ #define SYSCFG_SWPR2_PAGE52_Pos (20U) #define SYSCFG_SWPR2_PAGE52_Msk (0x1UL << SYSCFG_SWPR2_PAGE52_Pos) /*!< 0x00100000 */ -#define SYSCFG_SWPR2_PAGE52 SYSCFG_SWPR2_PAGE52_Msk /*!< SRAM2B Write protection page 20 (0x2003D000 – 0x2003D3FF) */ +#define SYSCFG_SWPR2_PAGE52 SYSCFG_SWPR2_PAGE52_Msk /*!< SRAM2B Write protection page 20 (0x2003D000 - 0x2003D3FF) */ #define SYSCFG_SWPR2_PAGE53_Pos (21U) #define SYSCFG_SWPR2_PAGE53_Msk (0x1UL << SYSCFG_SWPR2_PAGE53_Pos) /*!< 0x00200000 */ -#define SYSCFG_SWPR2_PAGE53 SYSCFG_SWPR2_PAGE53_Msk /*!< SRAM2B Write protection page 21 (0x2003D400 – 0x2003D7FF) */ +#define SYSCFG_SWPR2_PAGE53 SYSCFG_SWPR2_PAGE53_Msk /*!< SRAM2B Write protection page 21 (0x2003D400 - 0x2003D7FF) */ #define SYSCFG_SWPR2_PAGE54_Pos (22U) #define SYSCFG_SWPR2_PAGE54_Msk (0x1UL << SYSCFG_SWPR2_PAGE54_Pos) /*!< 0x00400000 */ -#define SYSCFG_SWPR2_PAGE54 SYSCFG_SWPR2_PAGE54_Msk /*!< SRAM2B Write protection page 22 (0x2003D800 – 0x2003DBFF) */ +#define SYSCFG_SWPR2_PAGE54 SYSCFG_SWPR2_PAGE54_Msk /*!< SRAM2B Write protection page 22 (0x2003D800 - 0x2003DBFF) */ #define SYSCFG_SWPR2_PAGE55_Pos (23U) #define SYSCFG_SWPR2_PAGE55_Msk (0x1UL << SYSCFG_SWPR2_PAGE55_Pos) /*!< 0x00800000 */ -#define SYSCFG_SWPR2_PAGE55 SYSCFG_SWPR2_PAGE55_Msk /*!< SRAM2B Write protection page 23 (0x2003DC00 – 0x2003DFFF) */ +#define SYSCFG_SWPR2_PAGE55 SYSCFG_SWPR2_PAGE55_Msk /*!< SRAM2B Write protection page 23 (0x2003DC00 - 0x2003DFFF) */ #define SYSCFG_SWPR2_PAGE56_Pos (24U) #define SYSCFG_SWPR2_PAGE56_Msk (0x1UL << SYSCFG_SWPR2_PAGE56_Pos) /*!< 0x01000000 */ -#define SYSCFG_SWPR2_PAGE56 SYSCFG_SWPR2_PAGE56_Msk /*!< SRAM2B Write protection page 24 (0x2003E000 – 0x2003E3FF) */ +#define SYSCFG_SWPR2_PAGE56 SYSCFG_SWPR2_PAGE56_Msk /*!< SRAM2B Write protection page 24 (0x2003E000 - 0x2003E3FF) */ #define SYSCFG_SWPR2_PAGE57_Pos (25U) #define SYSCFG_SWPR2_PAGE57_Msk (0x1UL << SYSCFG_SWPR2_PAGE57_Pos) /*!< 0x02000000 */ -#define SYSCFG_SWPR2_PAGE57 SYSCFG_SWPR2_PAGE57_Msk /*!< SRAM2B Write protection page 25 (0x2003E400 – 0x2003E7FF) */ +#define SYSCFG_SWPR2_PAGE57 SYSCFG_SWPR2_PAGE57_Msk /*!< SRAM2B Write protection page 25 (0x2003E400 - 0x2003E7FF) */ #define SYSCFG_SWPR2_PAGE58_Pos (26U) #define SYSCFG_SWPR2_PAGE58_Msk (0x1UL << SYSCFG_SWPR2_PAGE58_Pos) /*!< 0x04000000 */ -#define SYSCFG_SWPR2_PAGE58 SYSCFG_SWPR2_PAGE58_Msk /*!< SRAM2B Write protection page 26 (0x2003E800 – 0x2003EBFF) */ +#define SYSCFG_SWPR2_PAGE58 SYSCFG_SWPR2_PAGE58_Msk /*!< SRAM2B Write protection page 26 (0x2003E800 - 0x2003EBFF) */ #define SYSCFG_SWPR2_PAGE59_Pos (27U) #define SYSCFG_SWPR2_PAGE59_Msk (0x1UL << SYSCFG_SWPR2_PAGE59_Pos) /*!< 0x08000000 */ -#define SYSCFG_SWPR2_PAGE59 SYSCFG_SWPR2_PAGE59_Msk /*!< SRAM2B Write protection page 27 (0x2003EC00 – 0x2003EFFF) */ +#define SYSCFG_SWPR2_PAGE59 SYSCFG_SWPR2_PAGE59_Msk /*!< SRAM2B Write protection page 27 (0x2003EC00 - 0x2003EFFF) */ #define SYSCFG_SWPR2_PAGE60_Pos (28U) #define SYSCFG_SWPR2_PAGE60_Msk (0x1UL << SYSCFG_SWPR2_PAGE60_Pos) /*!< 0x10000000 */ -#define SYSCFG_SWPR2_PAGE60 SYSCFG_SWPR2_PAGE60_Msk /*!< SRAM2B Write protection page 28 (0x2003F000 – 0x2003F3FF) */ +#define SYSCFG_SWPR2_PAGE60 SYSCFG_SWPR2_PAGE60_Msk /*!< SRAM2B Write protection page 28 (0x2003F000 - 0x2003F3FF) */ #define SYSCFG_SWPR2_PAGE61_Pos (29U) #define SYSCFG_SWPR2_PAGE61_Msk (0x1UL << SYSCFG_SWPR2_PAGE61_Pos) /*!< 0x20000000 */ -#define SYSCFG_SWPR2_PAGE61 SYSCFG_SWPR2_PAGE61_Msk /*!< SRAM2B Write protection page 29 (0x2003F400 – 0x2003F7FF) */ +#define SYSCFG_SWPR2_PAGE61 SYSCFG_SWPR2_PAGE61_Msk /*!< SRAM2B Write protection page 29 (0x2003F400 - 0x2003F7FF) */ #define SYSCFG_SWPR2_PAGE62_Pos (30U) #define SYSCFG_SWPR2_PAGE62_Msk (0x1UL << SYSCFG_SWPR2_PAGE62_Pos) /*!< 0x40000000 */ -#define SYSCFG_SWPR2_PAGE62 SYSCFG_SWPR2_PAGE62_Msk /*!< SRAM2B Write protection page 30 (0x2003F800 – 0x2003FBFF) */ +#define SYSCFG_SWPR2_PAGE62 SYSCFG_SWPR2_PAGE62_Msk /*!< SRAM2B Write protection page 30 (0x2003F800 - 0x2003FBFF) */ #define SYSCFG_SWPR2_PAGE63_Pos (31U) #define SYSCFG_SWPR2_PAGE63_Msk (0x1UL << SYSCFG_SWPR2_PAGE63_Pos) /*!< 0x80000000 */ -#define SYSCFG_SWPR2_PAGE63 SYSCFG_SWPR2_PAGE63_Msk /*!< SRAM2B Write protection page 31 (0x2003FC00 – 0x2003FFFF) */ +#define SYSCFG_SWPR2_PAGE63 SYSCFG_SWPR2_PAGE63_Msk /*!< SRAM2B Write protection page 31 (0x2003FC00 - 0x2003FFFF) */ /***************** Bit definition for SYSCFG_IMR1 register (Interrupt masks control and status register on CPU1 - part 1) *******************************************/ #define SYSCFG_IMR1_TIM1IM_Pos (13U) @@ -13690,5 +13690,3 @@ typedef struct /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBxx/Include/stm32wbxx.h b/system/Drivers/CMSIS/Device/ST/STM32WBxx/Include/stm32wbxx.h index 197059705b..c9b60bf274 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32WBxx/Include/stm32wbxx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32WBxx/Include/stm32wbxx.h @@ -68,7 +68,7 @@ * @brief CMSIS Device version number */ #define __STM32WBxx_CMSIS_VERSION_MAIN (0x01U) /*!< [31:24] main version */ -#define __STM32WBxx_CMSIS_VERSION_SUB1 (0x09U) /*!< [23:16] sub1 version */ +#define __STM32WBxx_CMSIS_VERSION_SUB1 (0x0AU) /*!< [23:16] sub1 version */ #define __STM32WBxx_CMSIS_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ #define __STM32WBxx_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32WBxx_CMSIS_DEVICE_VERSION ((__STM32WBxx_CMSIS_VERSION_MAIN << 24)\ @@ -226,8 +226,3 @@ typedef enum /** * @} */ - - - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBxx/Include/system_stm32wbxx.h b/system/Drivers/CMSIS/Device/ST/STM32WBxx/Include/system_stm32wbxx.h index 24dcb93b38..5915e83a59 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32WBxx/Include/system_stm32wbxx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32WBxx/Include/system_stm32wbxx.h @@ -63,7 +63,7 @@ extern const uint32_t AHBPrescTable[16]; /*!< AHB prescalers table values */ extern const uint32_t APBPrescTable[8]; /*!< APB prescalers table values */ extern const uint32_t MSIRangeTable[16]; /*!< MSI ranges table values */ -#if defined(STM32WB55xx) || defined(STM32WB5Mxx) || defined(STM32WB35xx) || defined (STM32WB15xx) || defined (STM32WB10xx) +#if defined(STM32WB55xx) || defined(STM32WB5Mxx) || defined(STM32WB35xx) || defined (STM32WB15xx) extern const uint32_t SmpsPrescalerTable[4][6]; /*!< SMPS factor ranges table values */ #endif /** @@ -108,5 +108,4 @@ extern void SystemCoreClockUpdate(void); /** * @} - */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBxx/License.md b/system/Drivers/CMSIS/Device/ST/STM32WBxx/License.md index 1a68e07096..261eeb9e9f 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32WBxx/License.md +++ b/system/Drivers/CMSIS/Device/ST/STM32WBxx/License.md @@ -175,8 +175,18 @@ END OF TERMS AND CONDITIONS - - Copyright 2019 STMicroelectronics + APPENDIX: How to apply the Apache License to your work. + + To apply the Apache License to your work, attach the following + boilerplate notice, with the fields enclosed by brackets "[]" + replaced with your own identifying information. (Don't include + the brackets!) The text should be enclosed in the appropriate + comment syntax for the file format. We also recommend that a + file or class name and description of purpose be included on the + same "printed page" as the copyright notice for easier + identification within third-party archives. + + Copyright [yyyy] [name of copyright owner] Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBxx/README.md b/system/Drivers/CMSIS/Device/ST/STM32WBxx/README.md index 7827fa96de..3eabb779b7 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32WBxx/README.md +++ b/system/Drivers/CMSIS/Device/ST/STM32WBxx/README.md @@ -1,21 +1,19 @@ # STM32CubeWB CMSIS Device MCU Component -![latest tag](https://img.shields.io/github/v/tag/STMicroelectronics/cmsis_device_wb.svg?color=brightgreen) - ## Overview **STM32Cube** is an STMicroelectronics original initiative to ease the developers life by reducing efforts, time and cost. -**STM32Cube** covers the overall STM32 products portfolio. It includes a comprehensive embedded software platform delivered for each STM32 series. - * The CMSIS modules (core and device) corresponding to the ARM(tm) core implemented in this STM32 product. - * The STM32 HAL-LL drivers, an abstraction layer offering a set of APIs ensuring maximized portability across the STM32 portfolio. - * The BSP drivers of each evaluation, demonstration or nucleo board provided for this STM32 series. - * A consistent set of middleware libraries such as RTOS, USB, FatFS, graphics, touch sensing library... - * A full set of software projects (basic examples, applications, and demonstrations) for each board provided for this STM32 series. +**STM32Cube** covers the overall STM32 products portfolio. It includes a comprehensive embedded software platform, delivered for each STM32 series. + * The CMSIS modules (core and device) corresponding to the ARM(tm) core implemented in this STM32 product + * The STM32 HAL-LL drivers : an abstraction drivers layer, the API ensuring maximized portability across the STM32 portfolio + * The BSP Drivers of each evaluation or demonstration board provided by this STM32 series + * A consistent set of middlewares components such as RTOS, USB, FatFS, Graphics, STM32_TouchSensing_Library ... + * A full set of software projects (basic examples, applications or demonstrations) for each board provided by this STM32 series -Two models of publication are proposed for the STM32Cube embedded software: - * The monolithic **MCU Package**: all STM32Cube software modules of one STM32 series are present (Drivers, Middleware, Projects, Utilities) in the repository (usual name **STM32Cubexx**, xx corresponding to the STM32 series). - * The **MCU component**: each STM32Cube software module being part of the STM32Cube MCU Package, is delivered as an individual repository, allowing the user to select and get only the required software functions. +Two models of publication are proposed for the STM32Cube embedded software : + * The monolithic **MCU Package** : all STM32Cube software modules of one STM32 series are present (Drivers, Middlewares, Projects, Utilities) in the repo (usual name **STM32Cubexx**, xx corresponding to the STM32 series) + * The **MCU component** : progressively from November 2019, each STM32Cube software module being part of the STM32Cube MCU Package, will be delivered as an individual repo, allowing the user to select and get only the required software functions. ## Description @@ -40,10 +38,11 @@ Tag v1.5.0 | Tag v5.4.0_cm4 | Tag v1.8.0 Tag v1.7.0 | Tag v5.6.0_cm4 | Tag v1.10.0 Tag v1.8.0 | Tag v5.6.0_cm4 | Tag v1.11.0 Tag v1.9.0 | Tag v5.6.0_cm4 | Tag v1.12.0 +Tag v1.10.0 | Tag v5.6.0_cm4 | Tag v1.13.0 The full **STM32CubeWB** MCU package is available [here](https://github.com/STMicroelectronics/STM32CubeWB). ## Troubleshooting If you have any issue with the **Software content** of this repo, you can [file an issue on Github](https://github.com/STMicroelectronics/cmsis_device_wb/issues/new). -For any other question related to the product, the tools, the environment, you can submit a topic on the [ST Community/STM32 MCUs forum](https://community.st.com/s/topic/0TO0X000000BSqSWAW/stm32-mcus). +For any other question related to the product, the tools, the environment, you can submit a topic on the [ST Community/STM32 MCUs forum](https://community.st.com/s/group/0F90X000000AXsASAW/stm32-mcus). \ No newline at end of file diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBxx/Release_Notes.html b/system/Drivers/CMSIS/Device/ST/STM32WBxx/Release_Notes.html index 4964b92a9e..74db9dd912 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32WBxx/Release_Notes.html +++ b/system/Drivers/CMSIS/Device/ST/STM32WBxx/Release_Notes.html @@ -89,10 +89,25 @@

STM32WB15xx and STM32WB10xx

Update History

- +

Main Changes

    +
  • Update CMSIS devices drivers for all value lines not supporting SMPS
    • +
  • All source files and templates: update disclaimer to add reference to the new license agreement
    • +
  • Correct English spelling typos and remove non UTF-8 characters in comments
    • +
+

Supported Devices and boards

+
    +
  • STM32WB55xx, STM32WB5Mxx, STM32WB50xx, STM32WB35xx, STM32WB30xx, STM32WB15xx and STM32WB10xx devices.
    • +
+
+
+
+ +
+

Main Changes

+
  • Add atomic register access services:
    • 32-bit register access: ATOMIC_SET_BIT(), ATOMIC_CLEAR_BIT(), ATOMIC_MODIFY_REG()
      • @@ -105,7 +120,7 @@

      Main Changes

    • Add define LSI_STARTUP_TIME used in default IWDG timeout calculation (HAL_IWDG_DEFAULT_TIMEOUT)
    • Add define FLASH_ECCR_CPUID bits for new macro __HAL_FLASH_ECC_CPUID() macro
    -

    Supported Devices and boards

    +

    Supported Devices and boards

    • STM32WB55xx, STM32WB5Mxx, STM32WB50xx, STM32WB35xx, STM32WB30xx, STM32WB15xx and STM32WB10xx devices.
    @@ -114,7 +129,7 @@

    Supported Devices and boards

    -

    Main Changes

    +

    Main Changes

    Add support for STM32WB15xx and STM32WB10xx

    • Change how to adapt VTOR for user
      • @@ -125,7 +140,7 @@

      Development Toolchains and Compile
    • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.25
    • System Workbench STM32 (SW4STM32) toolchain V2.7

    -

    Supported Devices and boards

    +

    Supported Devices and boards

    • STM32WB55xx, STM32WB5Mxx, STM32WB50xx, STM32WB35xx, STM32WB30xx, STM32WB15xx and STM32WB10xx devices.
    @@ -134,7 +149,7 @@

    Supported Devices and boards

    -

    Main Changes

    +

    Main Changes

    Maintenance release

    Maintenance release for STM32WBxx devices (stm32wb55xx, stm32wb50xx, stm32wb35xx and stm32wb30xx devices)

    @@ -164,7 +179,7 @@

    Development Toolchains and Compi
  • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.25
  • System Workbench STM32 (SW4STM32) toolchain V2.7
    • -

    Supported Devices and boards

    +

    Supported Devices and boards

    • STM32WB55xx, STM32WB5Mxx, STM32WB50xx, STM32WB35xx and STM32WB30xx devices.
    @@ -173,7 +188,7 @@

    Supported Devices and boards

    -

    Main Changes

    +

    Main Changes

    Maintenance release

    Maintenance release for STM32WBxx devices (stm32wb55xx, stm32wb50xx, stm32wb35xx and stm32wb30xx devices)

    @@ -212,7 +227,7 @@

    Development Toolchains and Compi
  • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.25
  • System Workbench STM32 (SW4STM32) toolchain V2.7
    • -

    Supported Devices and boards

    +

    Supported Devices and boards

    • STM32WB55xx, STM32WB5Mxx, STM32WB50xx, STM32WB35xx and STM32WB30xx devices.
    @@ -221,7 +236,7 @@

    Supported Devices and boards

    -

    Main Changes

    +

    Main Changes

    Introduction of STM32WB35xx, STM32WB30xx and STM32WB5Mxx product

    This release introduce the support of STM32WB5Mxx, STM32WB35xx product and its value line STM32WB30xx.

    Added features:

    @@ -239,7 +254,7 @@

    Development Toolchains and Compi
  • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.25
  • System Workbench STM32 (SW4STM32) toolchain V2.7
    • -

    Supported Devices and boards

    +

    Supported Devices and boards

    • STM32WB55xx, STM32WB5Mxx, STM32WB50xx, STM32WB35xx and STM32WB30xx devices.
    @@ -248,7 +263,7 @@

    Supported Devices and boards

    -

    Main Changes

    +

    Main Changes

    Maintenance release for STM32WBxx devices (stm32wb55xx and stm32wb50xx devices)

    @@ -277,7 +292,7 @@

    Development Toolchains and Compi
  • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.25
  • System Workbench STM32 (SW4STM32) toolchain V2.7
    • -

    Supported Devices and boards

    +

    Supported Devices and boards

    • STM32WB55xx, STM32WB50xx devices
    @@ -286,7 +301,7 @@

    Supported Devices and boards

    -

    Main Changes

    +

    Main Changes

    Introduction of STM32WB50xx device

    First release for STM32WBxx CMSIS introducing stm32wb50xx devices.

    Contents

    @@ -297,7 +312,7 @@

    Development Toolchains and Compi
  • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.25
  • System Workbench STM32 (SW4STM32) toolchain V2.7
    • -

    Supported Devices and boards

    +

    Supported Devices and boards

    • STM32WB55xx and STM32WB50xx devices
    @@ -306,7 +321,7 @@

    Supported Devices and boards

    -

    Main Changes

    +

    Main Changes

    Maintenance release

    Maintenance release for STM32WBxx devices (stm32wb55xx devices)

    @@ -330,7 +345,7 @@

    Maintenance release

    -

    Main Changes

    +

    Main Changes

    First release

    Add support of STM32WB55xx.

    diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/linker/stm32wb10xx_flash_cm4.ld b/system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/linker/stm32wb10xx_flash_cm4.ld index 07be88948a..02f125bd8f 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/linker/stm32wb10xx_flash_cm4.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/linker/stm32wb10xx_flash_cm4.ld @@ -22,13 +22,12 @@ ***************************************************************************** ** @attention ** -**

    © Copyright (c) 2020 STMicroelectronics. -** All rights reserved.

    +** Copyright (c) 2020 STMicroelectronics. +** All rights reserved. ** -** This software component is licensed by ST under BSD 3-Clause license, -** the "License"; You may not use this file except in compliance with the -** License. You may obtain a copy of the License at: -** opensource.org/licenses/BSD-3-Clause +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. ** ***************************************************************************** */ @@ -137,7 +136,7 @@ SECTIONS . = ALIGN(4); .bss : { - /* This is used by the startup in order to initialize the .bss secion */ + /* This is used by the startup in order to initialize the .bss section */ _sbss = .; /* define a global symbol at bss start */ __bss_start__ = _sbss; *(.bss) diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/linker/stm32wb15xx_flash_cm4.ld b/system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/linker/stm32wb15xx_flash_cm4.ld index 07be88948a..02f125bd8f 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/linker/stm32wb15xx_flash_cm4.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/linker/stm32wb15xx_flash_cm4.ld @@ -22,13 +22,12 @@ ***************************************************************************** ** @attention ** -**

    © Copyright (c) 2020 STMicroelectronics. -** All rights reserved.

    +** Copyright (c) 2020 STMicroelectronics. +** All rights reserved. ** -** This software component is licensed by ST under BSD 3-Clause license, -** the "License"; You may not use this file except in compliance with the -** License. You may obtain a copy of the License at: -** opensource.org/licenses/BSD-3-Clause +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. ** ***************************************************************************** */ @@ -137,7 +136,7 @@ SECTIONS . = ALIGN(4); .bss : { - /* This is used by the startup in order to initialize the .bss secion */ + /* This is used by the startup in order to initialize the .bss section */ _sbss = .; /* define a global symbol at bss start */ __bss_start__ = _sbss; *(.bss) diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/linker/stm32wb30xx_flash_cm4.ld b/system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/linker/stm32wb30xx_flash_cm4.ld index e0094ba7e7..fa8aadbf21 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/linker/stm32wb30xx_flash_cm4.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/linker/stm32wb30xx_flash_cm4.ld @@ -15,30 +15,14 @@ ** of any kind. ** ***************************************************************************** +** @attention ** -**

    © COPYRIGHT(c) 2019 Ac6

    +** Copyright (c) 2019 STMicroelectronics. +** All rights reserved. ** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** 1. Redistributions of source code must retain the above copyright notice, -** this list of conditions and the following disclaimer. -** 2. Redistributions in binary form must reproduce the above copyright notice, -** this list of conditions and the following disclaimer in the documentation -** and/or other materials provided with the distribution. -** 3. Neither the name of Ac6 nor the names of its contributors -** may be used to endorse or promote products derived from this software -** without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. ** ***************************************************************************** */ @@ -145,7 +129,7 @@ SECTIONS . = ALIGN(4); .bss : { - /* This is used by the startup in order to initialize the .bss secion */ + /* This is used by the startup in order to initialize the .bss section */ _sbss = .; /* define a global symbol at bss start */ __bss_start__ = _sbss; *(.bss) diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/linker/stm32wb35xx_flash_cm4.ld b/system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/linker/stm32wb35xx_flash_cm4.ld index 761125c821..ba2fbf6770 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/linker/stm32wb35xx_flash_cm4.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/linker/stm32wb35xx_flash_cm4.ld @@ -15,30 +15,14 @@ ** of any kind. ** ***************************************************************************** +** @attention ** -**

    © COPYRIGHT(c) 2019 Ac6

    +** Copyright (c) 2019 STMicroelectronics. +** All rights reserved. ** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** 1. Redistributions of source code must retain the above copyright notice, -** this list of conditions and the following disclaimer. -** 2. Redistributions in binary form must reproduce the above copyright notice, -** this list of conditions and the following disclaimer in the documentation -** and/or other materials provided with the distribution. -** 3. Neither the name of Ac6 nor the names of its contributors -** may be used to endorse or promote products derived from this software -** without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. ** ***************************************************************************** */ @@ -145,7 +129,7 @@ SECTIONS . = ALIGN(4); .bss : { - /* This is used by the startup in order to initialize the .bss secion */ + /* This is used by the startup in order to initialize the .bss section */ _sbss = .; /* define a global symbol at bss start */ __bss_start__ = _sbss; *(.bss) diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/linker/stm32wb50xx_flash_cm4.ld b/system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/linker/stm32wb50xx_flash_cm4.ld index cad41e0355..4a8bd3f40f 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/linker/stm32wb50xx_flash_cm4.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/linker/stm32wb50xx_flash_cm4.ld @@ -15,30 +15,14 @@ ** of any kind. ** ***************************************************************************** +** @attention ** -**

    © COPYRIGHT(c) 2019 Ac6

    +** Copyright (c) 2019 STMicroelectronics. +** All rights reserved. ** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** 1. Redistributions of source code must retain the above copyright notice, -** this list of conditions and the following disclaimer. -** 2. Redistributions in binary form must reproduce the above copyright notice, -** this list of conditions and the following disclaimer in the documentation -** and/or other materials provided with the distribution. -** 3. Neither the name of Ac6 nor the names of its contributors -** may be used to endorse or promote products derived from this software -** without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. ** ***************************************************************************** */ @@ -145,7 +129,7 @@ SECTIONS . = ALIGN(4); .bss : { - /* This is used by the startup in order to initialize the .bss secion */ + /* This is used by the startup in order to initialize the .bss section */ _sbss = .; /* define a global symbol at bss start */ __bss_start__ = _sbss; *(.bss) diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/linker/stm32wb55xx_flash_cm4.ld b/system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/linker/stm32wb55xx_flash_cm4.ld index 840a6420b3..660f301612 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/linker/stm32wb55xx_flash_cm4.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/linker/stm32wb55xx_flash_cm4.ld @@ -15,30 +15,14 @@ ** of any kind. ** ***************************************************************************** +** @attention ** -**

    © COPYRIGHT(c) 2019 Ac6

    +** Copyright (c) 2019 STMicroelectronics. +** All rights reserved. ** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** 1. Redistributions of source code must retain the above copyright notice, -** this list of conditions and the following disclaimer. -** 2. Redistributions in binary form must reproduce the above copyright notice, -** this list of conditions and the following disclaimer in the documentation -** and/or other materials provided with the distribution. -** 3. Neither the name of Ac6 nor the names of its contributors -** may be used to endorse or promote products derived from this software -** without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. ** ***************************************************************************** */ @@ -145,7 +129,7 @@ SECTIONS . = ALIGN(4); .bss : { - /* This is used by the startup in order to initialize the .bss secion */ + /* This is used by the startup in order to initialize the .bss section */ _sbss = .; /* define a global symbol at bss start */ __bss_start__ = _sbss; *(.bss) diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/linker/stm32wb5mxx_flash_cm4.ld b/system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/linker/stm32wb5mxx_flash_cm4.ld index 514aa8631d..5da424e7cf 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/linker/stm32wb5mxx_flash_cm4.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/linker/stm32wb5mxx_flash_cm4.ld @@ -15,30 +15,14 @@ ** of any kind. ** ***************************************************************************** +** @attention ** -**

    © COPYRIGHT(c) 2019 Ac6

    +** Copyright (c) 2019 STMicroelectronics. +** All rights reserved. ** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** 1. Redistributions of source code must retain the above copyright notice, -** this list of conditions and the following disclaimer. -** 2. Redistributions in binary form must reproduce the above copyright notice, -** this list of conditions and the following disclaimer in the documentation -** and/or other materials provided with the distribution. -** 3. Neither the name of Ac6 nor the names of its contributors -** may be used to endorse or promote products derived from this software -** without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. ** ***************************************************************************** */ @@ -145,7 +129,7 @@ SECTIONS . = ALIGN(4); .bss : { - /* This is used by the startup in order to initialize the .bss secion */ + /* This is used by the startup in order to initialize the .bss section */ _sbss = .; /* define a global symbol at bss start */ __bss_start__ = _sbss; *(.bss) diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/startup_stm32wb10xx_cm4.s b/system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/startup_stm32wb10xx_cm4.s index 162fc770ff..3290ae89e7 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/startup_stm32wb10xx_cm4.s +++ b/system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/startup_stm32wb10xx_cm4.s @@ -92,7 +92,7 @@ LoopFillZerobss: Reset_Handler: ldr r0, =_estack mov sp, r0 /* set stack pointer */ -/* Call the clock system intitialization function.*/ +/* Call the clock system initialization function.*/ bl SystemInit /* Copy the data segment initializers from flash to SRAM */ @@ -384,4 +384,3 @@ g_pfnVectors: .weak DMAMUX1_OVR_IRQHandler .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/startup_stm32wb15xx_cm4.s b/system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/startup_stm32wb15xx_cm4.s index 94c25e27f3..851a8b2346 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/startup_stm32wb15xx_cm4.s +++ b/system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/startup_stm32wb15xx_cm4.s @@ -92,7 +92,7 @@ LoopFillZerobss: Reset_Handler: ldr r0, =_estack mov sp, r0 /* set stack pointer */ -/* Call the clock system intitialization function.*/ +/* Call the clock system initialization function.*/ bl SystemInit /* Copy the data segment initializers from flash to SRAM */ @@ -390,4 +390,3 @@ g_pfnVectors: .weak DMAMUX1_OVR_IRQHandler .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/startup_stm32wb30xx_cm4.s b/system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/startup_stm32wb30xx_cm4.s index 948fa78cc1..39f46ec925 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/startup_stm32wb30xx_cm4.s +++ b/system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/startup_stm32wb30xx_cm4.s @@ -92,7 +92,7 @@ LoopFillZerobss: Reset_Handler: ldr r0, =_estack mov sp, r0 /* set stack pointer */ -/* Call the clock system intitialization function.*/ +/* Call the clock system initialization function.*/ bl SystemInit /* Copy the data segment initializers from flash to SRAM */ @@ -381,4 +381,3 @@ g_pfnVectors: .weak DMAMUX1_OVR_IRQHandler .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/startup_stm32wb35xx_cm4.s b/system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/startup_stm32wb35xx_cm4.s index ec1f32445b..6edc0d44a9 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/startup_stm32wb35xx_cm4.s +++ b/system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/startup_stm32wb35xx_cm4.s @@ -92,7 +92,7 @@ LoopFillZerobss: Reset_Handler: ldr r0, =_estack mov sp, r0 /* set stack pointer */ -/* Call the clock system intitialization function.*/ +/* Call the clock system initialization function.*/ bl SystemInit /* Copy the data segment initializers from flash to SRAM */ @@ -429,4 +429,3 @@ g_pfnVectors: .weak DMAMUX1_OVR_IRQHandler .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/startup_stm32wb50xx_cm4.s b/system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/startup_stm32wb50xx_cm4.s index 7c49da886a..9430dfdff5 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/startup_stm32wb50xx_cm4.s +++ b/system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/startup_stm32wb50xx_cm4.s @@ -92,7 +92,7 @@ LoopFillZerobss: Reset_Handler: ldr r0, =_estack mov sp, r0 /* set stack pointer */ -/* Call the clock system intitialization function.*/ +/* Call the clock system initialization function.*/ bl SystemInit /* Copy the data segment initializers from flash to SRAM */ @@ -384,4 +384,3 @@ g_pfnVectors: .weak DMAMUX1_OVR_IRQHandler .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/startup_stm32wb55xx_cm4.s b/system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/startup_stm32wb55xx_cm4.s index c5c2b3fc3d..77c2e0551f 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/startup_stm32wb55xx_cm4.s +++ b/system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/startup_stm32wb55xx_cm4.s @@ -92,7 +92,7 @@ LoopFillZerobss: Reset_Handler: ldr r0, =_estack mov sp, r0 /* set stack pointer */ -/* Call the clock system intitialization function.*/ +/* Call the clock system initialization function.*/ bl SystemInit /* Copy the data segment initializers from flash to SRAM */ @@ -441,4 +441,3 @@ g_pfnVectors: .weak DMAMUX1_OVR_IRQHandler .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/startup_stm32wb5mxx_cm4.s b/system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/startup_stm32wb5mxx_cm4.s index 62a8c7ba77..c81490b5d9 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/startup_stm32wb5mxx_cm4.s +++ b/system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/startup_stm32wb5mxx_cm4.s @@ -92,7 +92,7 @@ LoopFillZerobss: Reset_Handler: ldr r0, =_estack mov sp, r0 /* set stack pointer */ -/* Call the clock system intitialization function.*/ +/* Call the clock system initialization function.*/ bl SystemInit /* Copy the data segment initializers from flash to SRAM */ @@ -441,4 +441,3 @@ g_pfnVectors: .weak DMAMUX1_OVR_IRQHandler .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/system_stm32wbxx.c b/system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/system_stm32wbxx.c index d0ff7d2d36..4bfa00f1f4 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/system_stm32wbxx.c +++ b/system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/system_stm32wbxx.c @@ -175,7 +175,7 @@ const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \ 4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL}; /* 0UL values are incorrect cases */ -#if defined(STM32WB55xx) || defined(STM32WB5Mxx) || defined(STM32WB35xx) || defined (STM32WB15xx) || defined (STM32WB10xx) +#if defined(STM32WB55xx) || defined(STM32WB5Mxx) || defined(STM32WB35xx) || defined (STM32WB15xx) const uint32_t SmpsPrescalerTable[4UL][6UL]={{1UL,3UL,2UL,2UL,1UL,2UL}, \ {2UL,6UL,4UL,3UL,2UL,4UL}, \ {4UL,12UL,8UL,6UL,4UL,8UL}, \ @@ -364,5 +364,3 @@ void SystemCoreClockUpdate(void) /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md b/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md index cb97ca1f93..ba828c59b5 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md +++ b/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md @@ -15,7 +15,7 @@ * STM32L5: 1.0.4 * STM32MP1: 1.5.0 * STM32U5: 1.0.0 - * STM32WB: 1.9.0 + * STM32WB: 1.10.0 * STM32WL: 1.1.0 Release notes of each STM32YYxx CMSIS available here: diff --git a/system/STM32WBxx/system_stm32wbxx.c b/system/STM32WBxx/system_stm32wbxx.c index e7d43cbe88..204ef800d7 100644 --- a/system/STM32WBxx/system_stm32wbxx.c +++ b/system/STM32WBxx/system_stm32wbxx.c @@ -157,7 +157,7 @@ const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \ 4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL}; /* 0UL values are incorrect cases */ -#if defined(STM32WB55xx) || defined(STM32WB5Mxx) || defined(STM32WB35xx) || defined (STM32WB15xx) || defined (STM32WB10xx) +#if defined(STM32WB55xx) || defined(STM32WB5Mxx) || defined(STM32WB35xx) || defined (STM32WB15xx) const uint32_t SmpsPrescalerTable[4UL][6UL]={{1UL,3UL,2UL,2UL,1UL,2UL}, \ {2UL,6UL,4UL,3UL,2UL,4UL}, \ {4UL,12UL,8UL,6UL,4UL,8UL}, \ @@ -346,5 +346,3 @@ void SystemCoreClockUpdate(void) /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/