+
+
+
+
diff --git a/system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/Templates/gcc/startup_stm32c011xx.s b/system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/Templates/gcc/startup_stm32c011xx.s
new file mode 100644
index 0000000000..6eed97f38e
--- /dev/null
+++ b/system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/Templates/gcc/startup_stm32c011xx.s
@@ -0,0 +1,256 @@
+/**
+ ******************************************************************************
+ * @file startup_stm32c011xx.s
+ * @author MCD Application Team
+ * @brief STM32C011xx devices vector table GCC toolchain.
+ * This module performs:
+ * - Set the initial SP
+ * - Set the initial PC == Reset_Handler,
+ * - Set the vector table entries with the exceptions ISR address,
+ * - Configure the clock system
+ * - Branches to main in the C library (which eventually
+ * calls main()).
+ * After Reset the Cortex-M0+ processor is in Thread mode,
+ * priority is Privileged, and the Stack is set to Main.
+ *******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2022 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ *******************************************************************************
+ */
+
+ .syntax unified
+ .cpu cortex-m0plus
+ .fpu softvfp
+ .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+ ldr r0, =_estack
+ mov sp, r0 /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+ movs r1, #0
+ b LoopCopyDataInit
+
+CopyDataInit:
+ ldr r3, =_sidata
+ ldr r3, [r3, r1]
+ str r3, [r0, r1]
+ adds r1, r1, #4
+
+LoopCopyDataInit:
+ ldr r0, =_sdata
+ ldr r3, =_edata
+ adds r2, r0, r1
+ cmp r2, r3
+ bcc CopyDataInit
+ ldr r2, =_sbss
+ b LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+ movs r3, #0
+ str r3, [r2]
+ adds r2, r2, #4
+
+
+LoopFillZerobss:
+ ldr r3, = _ebss
+ cmp r2, r3
+ bcc FillZerobss
+
+/* Call the clock system initialization function.*/
+ bl SystemInit
+/* Call static constructors */
+ bl __libc_init_array
+/* Call the application's entry point.*/
+ bl main
+
+LoopForever:
+ b LoopForever
+
+
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief This is the code that gets called when the processor receives an
+ * unexpected interrupt. This simply enters an infinite loop, preserving
+ * the system state for examination by a debugger.
+ *
+ * @param None
+ * @retval : None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ .size Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M0. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ .section .isr_vector,"a",%progbits
+ .type g_pfnVectors, %object
+ .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+ .word _estack
+ .word Reset_Handler
+ .word NMI_Handler
+ .word HardFault_Handler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word SVC_Handler
+ .word 0
+ .word 0
+ .word PendSV_Handler
+ .word SysTick_Handler
+ .word WWDG_IRQHandler /* Window WatchDog */
+ .word 0 /* reserved */
+ .word RTC_IRQHandler /* RTC through the EXTI line */
+ .word FLASH_IRQHandler /* FLASH */
+ .word RCC_IRQHandler /* RCC */
+ .word EXTI0_1_IRQHandler /* EXTI Line 0 and 1 */
+ .word EXTI2_3_IRQHandler /* EXTI Line 2 and 3 */
+ .word EXTI4_15_IRQHandler /* EXTI Line 4 to 15 */
+ .word 0 /* reserved */
+ .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */
+ .word DMA1_Channel2_3_IRQHandler /* DMA1 Channel 2 and Channel 3 */
+ .word DMAMUX1_IRQHandler /* DMAMUX1 */
+ .word ADC1_IRQHandler /* ADC1 */
+ .word TIM1_BRK_UP_TRG_COM_IRQHandler /* TIM1 Break, Update, Trigger and Commutation */
+ .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
+ .word 0 /* reserved */
+ .word TIM3_IRQHandler /* TIM3 */
+ .word 0 /* reserved */
+ .word 0 /* reserved */
+ .word TIM14_IRQHandler /* TIM14 */
+ .word 0 /* reserved */
+ .word TIM16_IRQHandler /* TIM16 */
+ .word TIM17_IRQHandler /* TIM17 */
+ .word I2C1_IRQHandler /* I2C1 */
+ .word 0 /* reserved */
+ .word SPI1_IRQHandler /* SPI1 */
+ .word 0 /* reserved */
+ .word USART1_IRQHandler /* USART1 */
+ .word USART2_IRQHandler /* USART2 */
+ .word 0 /* reserved */
+ .word 0 /* reserved */
+ .word 0 /* reserved */
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+ .weak NMI_Handler
+ .thumb_set NMI_Handler,Default_Handler
+
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler,Default_Handler
+
+ .weak SVC_Handler
+ .thumb_set SVC_Handler,Default_Handler
+
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler,Default_Handler
+
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler,Default_Handler
+
+ .weak WWDG_IRQHandler
+ .thumb_set WWDG_IRQHandler,Default_Handler
+
+ .weak RTC_IRQHandler
+ .thumb_set RTC_IRQHandler,Default_Handler
+
+ .weak FLASH_IRQHandler
+ .thumb_set FLASH_IRQHandler,Default_Handler
+
+ .weak RCC_IRQHandler
+ .thumb_set RCC_IRQHandler,Default_Handler
+
+ .weak EXTI0_1_IRQHandler
+ .thumb_set EXTI0_1_IRQHandler,Default_Handler
+
+ .weak EXTI2_3_IRQHandler
+ .thumb_set EXTI2_3_IRQHandler,Default_Handler
+
+ .weak EXTI4_15_IRQHandler
+ .thumb_set EXTI4_15_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel1_IRQHandler
+ .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel2_3_IRQHandler
+ .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler
+
+ .weak DMAMUX1_IRQHandler
+ .thumb_set DMAMUX1_IRQHandler,Default_Handler
+
+ .weak ADC1_IRQHandler
+ .thumb_set ADC1_IRQHandler,Default_Handler
+
+ .weak TIM1_BRK_UP_TRG_COM_IRQHandler
+ .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler
+
+ .weak TIM1_CC_IRQHandler
+ .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+ .weak TIM3_IRQHandler
+ .thumb_set TIM3_IRQHandler,Default_Handler
+
+ .weak TIM14_IRQHandler
+ .thumb_set TIM14_IRQHandler,Default_Handler
+
+ .weak TIM16_IRQHandler
+ .thumb_set TIM16_IRQHandler,Default_Handler
+
+ .weak TIM17_IRQHandler
+ .thumb_set TIM17_IRQHandler,Default_Handler
+
+ .weak I2C1_IRQHandler
+ .thumb_set I2C1_IRQHandler,Default_Handler
+
+ .weak SPI1_IRQHandler
+ .thumb_set SPI1_IRQHandler,Default_Handler
+
+ .weak USART1_IRQHandler
+ .thumb_set USART1_IRQHandler,Default_Handler
+
+ .weak USART2_IRQHandler
+ .thumb_set USART2_IRQHandler,Default_Handler
diff --git a/system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/Templates/gcc/startup_stm32c031xx.s b/system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/Templates/gcc/startup_stm32c031xx.s
new file mode 100644
index 0000000000..d18f844391
--- /dev/null
+++ b/system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/Templates/gcc/startup_stm32c031xx.s
@@ -0,0 +1,256 @@
+/**
+ ******************************************************************************
+ * @file startup_stm32c031xx.s
+ * @author MCD Application Team
+ * @brief STM32C031xx devices vector table GCC toolchain.
+ * This module performs:
+ * - Set the initial SP
+ * - Set the initial PC == Reset_Handler,
+ * - Set the vector table entries with the exceptions ISR address,
+ * - Configure the clock system
+ * - Branches to main in the C library (which eventually
+ * calls main()).
+ * After Reset the Cortex-M0+ processor is in Thread mode,
+ * priority is Privileged, and the Stack is set to Main.
+ *******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2022 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ *******************************************************************************
+ */
+
+ .syntax unified
+ .cpu cortex-m0plus
+ .fpu softvfp
+ .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+ ldr r0, =_estack
+ mov sp, r0 /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+ movs r1, #0
+ b LoopCopyDataInit
+
+CopyDataInit:
+ ldr r3, =_sidata
+ ldr r3, [r3, r1]
+ str r3, [r0, r1]
+ adds r1, r1, #4
+
+LoopCopyDataInit:
+ ldr r0, =_sdata
+ ldr r3, =_edata
+ adds r2, r0, r1
+ cmp r2, r3
+ bcc CopyDataInit
+ ldr r2, =_sbss
+ b LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+ movs r3, #0
+ str r3, [r2]
+ adds r2, r2, #4
+
+
+LoopFillZerobss:
+ ldr r3, = _ebss
+ cmp r2, r3
+ bcc FillZerobss
+
+/* Call the clock system initialization function.*/
+ bl SystemInit
+/* Call static constructors */
+ bl __libc_init_array
+/* Call the application's entry point.*/
+ bl main
+
+LoopForever:
+ b LoopForever
+
+
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief This is the code that gets called when the processor receives an
+ * unexpected interrupt. This simply enters an infinite loop, preserving
+ * the system state for examination by a debugger.
+ *
+ * @param None
+ * @retval : None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ .size Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M0. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ .section .isr_vector,"a",%progbits
+ .type g_pfnVectors, %object
+ .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+ .word _estack
+ .word Reset_Handler
+ .word NMI_Handler
+ .word HardFault_Handler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word SVC_Handler
+ .word 0
+ .word 0
+ .word PendSV_Handler
+ .word SysTick_Handler
+ .word WWDG_IRQHandler /* Window WatchDog */
+ .word 0 /* reserved */
+ .word RTC_IRQHandler /* RTC through the EXTI line */
+ .word FLASH_IRQHandler /* FLASH */
+ .word RCC_IRQHandler /* RCC */
+ .word EXTI0_1_IRQHandler /* EXTI Line 0 and 1 */
+ .word EXTI2_3_IRQHandler /* EXTI Line 2 and 3 */
+ .word EXTI4_15_IRQHandler /* EXTI Line 4 to 15 */
+ .word 0 /* reserved */
+ .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */
+ .word DMA1_Channel2_3_IRQHandler /* DMA1 Channel 2 and Channel 3 */
+ .word DMAMUX1_IRQHandler /* DMAMUX1 */
+ .word ADC1_IRQHandler /* ADC1 */
+ .word TIM1_BRK_UP_TRG_COM_IRQHandler /* TIM1 Break, Update, Trigger and Commutation */
+ .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
+ .word 0 /* reserved */
+ .word TIM3_IRQHandler /* TIM3 */
+ .word 0 /* reserved */
+ .word 0 /* reserved */
+ .word TIM14_IRQHandler /* TIM14 */
+ .word 0 /* reserved */
+ .word TIM16_IRQHandler /* TIM16 */
+ .word TIM17_IRQHandler /* TIM17 */
+ .word I2C1_IRQHandler /* I2C1 */
+ .word 0 /* reserved */
+ .word SPI1_IRQHandler /* SPI1 */
+ .word 0 /* reserved */
+ .word USART1_IRQHandler /* USART1 */
+ .word USART2_IRQHandler /* USART2 */
+ .word 0 /* reserved */
+ .word 0 /* reserved */
+ .word 0 /* reserved */
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+ .weak NMI_Handler
+ .thumb_set NMI_Handler,Default_Handler
+
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler,Default_Handler
+
+ .weak SVC_Handler
+ .thumb_set SVC_Handler,Default_Handler
+
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler,Default_Handler
+
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler,Default_Handler
+
+ .weak WWDG_IRQHandler
+ .thumb_set WWDG_IRQHandler,Default_Handler
+
+ .weak RTC_IRQHandler
+ .thumb_set RTC_IRQHandler,Default_Handler
+
+ .weak FLASH_IRQHandler
+ .thumb_set FLASH_IRQHandler,Default_Handler
+
+ .weak RCC_IRQHandler
+ .thumb_set RCC_IRQHandler,Default_Handler
+
+ .weak EXTI0_1_IRQHandler
+ .thumb_set EXTI0_1_IRQHandler,Default_Handler
+
+ .weak EXTI2_3_IRQHandler
+ .thumb_set EXTI2_3_IRQHandler,Default_Handler
+
+ .weak EXTI4_15_IRQHandler
+ .thumb_set EXTI4_15_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel1_IRQHandler
+ .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel2_3_IRQHandler
+ .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler
+
+ .weak DMAMUX1_IRQHandler
+ .thumb_set DMAMUX1_IRQHandler,Default_Handler
+
+ .weak ADC1_IRQHandler
+ .thumb_set ADC1_IRQHandler,Default_Handler
+
+ .weak TIM1_BRK_UP_TRG_COM_IRQHandler
+ .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler
+
+ .weak TIM1_CC_IRQHandler
+ .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+ .weak TIM3_IRQHandler
+ .thumb_set TIM3_IRQHandler,Default_Handler
+
+ .weak TIM14_IRQHandler
+ .thumb_set TIM14_IRQHandler,Default_Handler
+
+ .weak TIM16_IRQHandler
+ .thumb_set TIM16_IRQHandler,Default_Handler
+
+ .weak TIM17_IRQHandler
+ .thumb_set TIM17_IRQHandler,Default_Handler
+
+ .weak I2C1_IRQHandler
+ .thumb_set I2C1_IRQHandler,Default_Handler
+
+ .weak SPI1_IRQHandler
+ .thumb_set SPI1_IRQHandler,Default_Handler
+
+ .weak USART1_IRQHandler
+ .thumb_set USART1_IRQHandler,Default_Handler
+
+ .weak USART2_IRQHandler
+ .thumb_set USART2_IRQHandler,Default_Handler
diff --git a/system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/Templates/system_stm32c0xx.c b/system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/Templates/system_stm32c0xx.c
new file mode 100644
index 0000000000..f0e137f151
--- /dev/null
+++ b/system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/Templates/system_stm32c0xx.c
@@ -0,0 +1,228 @@
+/**
+ ******************************************************************************
+ * @file system_stm32c0xx.c
+ * @author MCD Application Team
+ * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Source File
+ *
+ * This file provides two functions and one global variable to be called from
+ * user application:
+ * - SystemInit(): This function is called at startup just after reset and
+ * before branch to main program. This call is made inside
+ * the "startup_stm32c0xx.s" file.
+ *
+ * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+ * by the user application to setup the SysTick
+ * timer or configure other parameters.
+ *
+ * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+ * be called whenever the core clock is changed
+ * during program execution.
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2022 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32c0xx_system
+ * @{
+ */
+
+/** @addtogroup STM32C0xx_System_Private_Includes
+ * @{
+ */
+
+#include "stm32c0xx.h"
+
+#if !defined (HSE_VALUE)
+#define HSE_VALUE (48000000UL) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined (HSI_VALUE)
+ #define HSI_VALUE (48000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+#if !defined (LSI_VALUE)
+ #define LSI_VALUE (32000UL) /*!< Value of LSI in Hz*/
+#endif /* LSI_VALUE */
+
+#if !defined (LSE_VALUE)
+ #define LSE_VALUE (32768UL) /*!< Value of LSE in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32C0xx_System_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32C0xx_System_Private_Defines
+ * @{
+ */
+
+/************************* Miscellaneous Configuration ************************/
+/*!< Uncomment the following line if you need to relocate your vector Table in
+ Internal SRAM. */
+//#define VECT_TAB_SRAM
+#define VECT_TAB_OFFSET 0x0U /*!< Vector Table base offset field.
+ This value must be a multiple of 0x100. */
+/******************************************************************************/
+/**
+ * @}
+ */
+
+/** @addtogroup STM32C0xx_System_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32C0xx_System_Private_Variables
+ * @{
+ */
+ /* The SystemCoreClock variable is updated in three ways:
+ 1) by calling CMSIS function SystemCoreClockUpdate()
+ 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+ 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+ Note: If you use this function to configure the system clock; then there
+ is no need to call the 2 first functions listed above, since SystemCoreClock
+ variable is updated automatically.
+ */
+ uint32_t SystemCoreClock = 48000000UL;
+
+ const uint32_t AHBPrescTable[16UL] = {0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL, 6UL, 7UL, 8UL, 9UL};
+ const uint32_t APBPrescTable[8UL] = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32C0xx_System_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32C0xx_System_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Setup the microcontroller system.
+ * @param None
+ * @retval None
+ */
+void SystemInit(void)
+{
+
+ /* Configure the Vector Table location add offset address ------------------*/
+#ifdef VECT_TAB_SRAM
+ SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+ SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+#endif
+}
+
+/**
+ * @brief Update SystemCoreClock variable according to Clock Register Values.
+ * The SystemCoreClock variable contains the core clock (HCLK), it can
+ * be used by the user application to setup the SysTick timer or configure
+ * other parameters.
+ *
+ * @note Each time the core clock (HCLK) changes, this function must be called
+ * to update SystemCoreClock variable value. Otherwise, any configuration
+ * based on this variable will be incorrect.
+ *
+ * @note - The system frequency computed by this function is not the real
+ * frequency in the chip. It is calculated based on the predefined
+ * constant and the selected clock source:
+ *
+ * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**) / HSI division factor
+ *
+ * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+ *
+ * - If SYSCLK source is LSI, SystemCoreClock will contain the LSI_VALUE
+ *
+ * - If SYSCLK source is LSE, SystemCoreClock will contain the LSE_VALUE
+ *
+ * (**) HSI_VALUE is a constant defined in stm32c0xx_hal_conf.h file (default value
+ * 48 MHz) but the real value may vary depending on the variations
+ * in voltage and temperature.
+ *
+ * (***) HSE_VALUE is a constant defined in stm32c0xx_hal_conf.h file (default value
+ * 48 MHz), user has to ensure that HSE_VALUE is same as the real
+ * frequency of the crystal used. Otherwise, this function may
+ * have wrong result.
+ *
+ * - The result of this function could be not correct when using fractional
+ * value for HSE crystal.
+ *
+ * @param None
+ * @retval None
+ */
+void SystemCoreClockUpdate(void)
+{
+ uint32_t tmp;
+ uint32_t hsidiv;
+
+ /* Get SYSCLK source -------------------------------------------------------*/
+ switch (RCC->CFGR & RCC_CFGR_SWS)
+ {
+ case RCC_CFGR_SWS_0: /* HSE used as system clock */
+ SystemCoreClock = HSE_VALUE;
+ break;
+
+ case (RCC_CFGR_SWS_1 | RCC_CFGR_SWS_0): /* LSI used as system clock */
+ SystemCoreClock = LSI_VALUE;
+ break;
+
+ case RCC_CFGR_SWS_2: /* LSE used as system clock */
+ SystemCoreClock = LSE_VALUE;
+ break;
+
+ case 0x00000000U: /* HSI used as system clock */
+ default: /* HSI used as system clock */
+ hsidiv = (1UL << ((READ_BIT(RCC->CR, RCC_CR_HSIDIV))>> RCC_CR_HSIDIV_Pos));
+ SystemCoreClock = (HSI_VALUE/hsidiv);
+ break;
+ }
+ /* Compute HCLK clock frequency --------------------------------------------*/
+ /* Get HCLK prescaler */
+ tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
+ /* HCLK clock frequency */
+ SystemCoreClock >>= tmp;
+}
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/system/Drivers/CMSIS/Device/ST/STM32C0xx/_htmresc/Add button.svg b/system/Drivers/CMSIS/Device/ST/STM32C0xx/_htmresc/Add button.svg
new file mode 100644
index 0000000000..c211545dad
--- /dev/null
+++ b/system/Drivers/CMSIS/Device/ST/STM32C0xx/_htmresc/Add button.svg
@@ -0,0 +1,2 @@
+
+
diff --git a/system/Drivers/CMSIS/Device/ST/STM32C0xx/_htmresc/Update.svg b/system/Drivers/CMSIS/Device/ST/STM32C0xx/_htmresc/Update.svg
new file mode 100644
index 0000000000..f88381f1e6
--- /dev/null
+++ b/system/Drivers/CMSIS/Device/ST/STM32C0xx/_htmresc/Update.svg
@@ -0,0 +1,2 @@
+
+
diff --git a/system/Drivers/CMSIS/Device/ST/STM32C0xx/_htmresc/favicon.png b/system/Drivers/CMSIS/Device/ST/STM32C0xx/_htmresc/favicon.png
new file mode 100644
index 0000000000..06713eec49
Binary files /dev/null and b/system/Drivers/CMSIS/Device/ST/STM32C0xx/_htmresc/favicon.png differ
diff --git a/system/Drivers/CMSIS/Device/ST/STM32C0xx/_htmresc/mini-st.css b/system/Drivers/CMSIS/Device/ST/STM32C0xx/_htmresc/mini-st.css
new file mode 100644
index 0000000000..3caf11c32e
--- /dev/null
+++ b/system/Drivers/CMSIS/Device/ST/STM32C0xx/_htmresc/mini-st.css
@@ -0,0 +1,1700 @@
+@charset "UTF-8";
+/*
+ Flavor name: Default (mini-default)
+ Author: Angelos Chalaris (chalarangelo@gmail.com)
+ Maintainers: Angelos Chalaris
+ mini.css version: v3.0.0-alpha.3
+*/
+/*
+ Browsers resets and base typography.
+*/
+/* Core module CSS variable definitions */
+:root {
+ --fore-color: #111;
+ --secondary-fore-color: #444;
+ --back-color: #f8f8f8;
+ --secondary-back-color: #f0f0f0;
+ --blockquote-color: #f57c00;
+ --pre-color: #1565c0;
+ --border-color: #aaa;
+ --secondary-border-color: #ddd;
+ --heading-ratio: 1.19;
+ --universal-margin: 0.5rem;
+ --universal-padding: 0.125rem;
+ --universal-border-radius: 0.125rem;
+ --a-link-color: #0277bd;
+ --a-visited-color: #01579b; }
+
+html {
+ font-size: 14px; }
+
+a, b, del, em, i, ins, q, span, strong, u {
+ font-size: 1em; }
+
+html, * {
+ font-family: -apple-system, BlinkMacSystemFont, "Segoe UI", Roboto, Ubuntu, "Helvetica Neue", Helvetica, sans-serif;
+ line-height: 1.4;
+ -webkit-text-size-adjust: 100%; }
+
+* {
+ font-size: 1rem; }
+
+body {
+ margin: 0;
+ color: var(--fore-color);
+ background: var(--back-color); }
+
+details {
+ display: block; }
+
+summary {
+ display: list-item; }
+
+abbr[title] {
+ border-bottom: none;
+ text-decoration: underline dotted; }
+
+input {
+ overflow: visible; }
+
+img {
+ max-width: 100%;
+ height: auto; }
+
+h1, h2, h3, h4, h5, h6 {
+ line-height: 1.2;
+ margin: calc(1.5 * var(--universal-margin)) var(--universal-margin);
+ font-weight: 500; }
+ h1 small, h2 small, h3 small, h4 small, h5 small, h6 small {
+ color: var(--secondary-fore-color);
+ display: block;
+ margin-top: -0.25rem; }
+
+h1 {
+ font-size: calc(1rem * var(--heading-ratio) * var(--heading-ratio) * var(--heading-ratio)); }
+
+h2 {
+ font-size: calc(1rem * var(--heading-ratio) * var(--heading-ratio); );
+ background: var(--mark-back-color);
+ font-weight: 600;
+ padding: 0.1em 0.5em 0.2em 0.5em;
+ color: var(--mark-fore-color); }
+
+h3 {
+ font-size: calc(1rem * var(--heading-ratio));
+ padding-left: calc(2 * var(--universal-margin));
+ /* background: var(--border-color); */
+ }
+
+h4 {
+ font-size: 1rem;);
+ padding-left: calc(4 * var(--universal-margin)); }
+
+h5 {
+ font-size: 1rem; }
+
+h6 {
+ font-size: calc(1rem / var(--heading-ratio)); }
+
+p {
+ margin: var(--universal-margin); }
+
+ol, ul {
+ margin: var(--universal-margin);
+ padding-left: calc(6 * var(--universal-margin)); }
+
+b, strong {
+ font-weight: 700; }
+
+hr {
+ box-sizing: content-box;
+ border: 0;
+ line-height: 1.25em;
+ margin: var(--universal-margin);
+ height: 0.0625rem;
+ background: linear-gradient(to right, transparent, var(--border-color) 20%, var(--border-color) 80%, transparent); }
+
+blockquote {
+ display: block;
+ position: relative;
+ font-style: italic;
+ color: var(--secondary-fore-color);
+ margin: var(--universal-margin);
+ padding: calc(3 * var(--universal-padding));
+ border: 0.0625rem solid var(--secondary-border-color);
+ border-left: 0.375rem solid var(--blockquote-color);
+ border-radius: 0 var(--universal-border-radius) var(--universal-border-radius) 0; }
+ blockquote:before {
+ position: absolute;
+ top: calc(0rem - var(--universal-padding));
+ left: 0;
+ font-family: sans-serif;
+ font-size: 3rem;
+ font-weight: 700;
+ content: "\201c";
+ color: var(--blockquote-color); }
+ blockquote[cite]:after {
+ font-style: normal;
+ font-size: 0.75em;
+ font-weight: 700;
+ content: "\a— " attr(cite);
+ white-space: pre; }
+
+code, kbd, pre, samp {
+ font-family: Menlo, Consolas, monospace;
+ font-size: 0.85em; }
+
+code {
+ background: var(--secondary-back-color);
+ border-radius: var(--universal-border-radius);
+ padding: calc(var(--universal-padding) / 4) calc(var(--universal-padding) / 2); }
+
+kbd {
+ background: var(--fore-color);
+ color: var(--back-color);
+ border-radius: var(--universal-border-radius);
+ padding: calc(var(--universal-padding) / 4) calc(var(--universal-padding) / 2); }
+
+pre {
+ overflow: auto;
+ background: var(--secondary-back-color);
+ padding: calc(1.5 * var(--universal-padding));
+ margin: var(--universal-margin);
+ border: 0.0625rem solid var(--secondary-border-color);
+ border-left: 0.25rem solid var(--pre-color);
+ border-radius: 0 var(--universal-border-radius) var(--universal-border-radius) 0; }
+
+sup, sub, code, kbd {
+ line-height: 0;
+ position: relative;
+ vertical-align: baseline; }
+
+small, sup, sub, figcaption {
+ font-size: 0.75em; }
+
+sup {
+ top: -0.5em; }
+
+sub {
+ bottom: -0.25em; }
+
+figure {
+ margin: var(--universal-margin); }
+
+figcaption {
+ color: var(--secondary-fore-color); }
+
+a {
+ text-decoration: none; }
+ a:link {
+ color: var(--a-link-color); }
+ a:visited {
+ color: var(--a-visited-color); }
+ a:hover, a:focus {
+ text-decoration: underline; }
+
+/*
+ Definitions for the grid system, cards and containers.
+*/
+.container {
+ margin: 0 auto;
+ padding: 0 calc(1.5 * var(--universal-padding)); }
+
+.row {
+ box-sizing: border-box;
+ display: flex;
+ flex: 0 1 auto;
+ flex-flow: row wrap; }
+
+.col-sm,
+[class^='col-sm-'],
+[class^='col-sm-offset-'],
+.row[class*='cols-sm-'] > * {
+ box-sizing: border-box;
+ flex: 0 0 auto;
+ padding: 0 calc(var(--universal-padding) / 2); }
+
+.col-sm,
+.row.cols-sm > * {
+ max-width: 100%;
+ flex-grow: 1;
+ flex-basis: 0; }
+
+.col-sm-1,
+.row.cols-sm-1 > * {
+ max-width: 8.3333333333%;
+ flex-basis: 8.3333333333%; }
+
+.col-sm-offset-0 {
+ margin-left: 0; }
+
+.col-sm-2,
+.row.cols-sm-2 > * {
+ max-width: 16.6666666667%;
+ flex-basis: 16.6666666667%; }
+
+.col-sm-offset-1 {
+ margin-left: 8.3333333333%; }
+
+.col-sm-3,
+.row.cols-sm-3 > * {
+ max-width: 25%;
+ flex-basis: 25%; }
+
+.col-sm-offset-2 {
+ margin-left: 16.6666666667%; }
+
+.col-sm-4,
+.row.cols-sm-4 > * {
+ max-width: 33.3333333333%;
+ flex-basis: 33.3333333333%; }
+
+.col-sm-offset-3 {
+ margin-left: 25%; }
+
+.col-sm-5,
+.row.cols-sm-5 > * {
+ max-width: 41.6666666667%;
+ flex-basis: 41.6666666667%; }
+
+.col-sm-offset-4 {
+ margin-left: 33.3333333333%; }
+
+.col-sm-6,
+.row.cols-sm-6 > * {
+ max-width: 50%;
+ flex-basis: 50%; }
+
+.col-sm-offset-5 {
+ margin-left: 41.6666666667%; }
+
+.col-sm-7,
+.row.cols-sm-7 > * {
+ max-width: 58.3333333333%;
+ flex-basis: 58.3333333333%; }
+
+.col-sm-offset-6 {
+ margin-left: 50%; }
+
+.col-sm-8,
+.row.cols-sm-8 > * {
+ max-width: 66.6666666667%;
+ flex-basis: 66.6666666667%; }
+
+.col-sm-offset-7 {
+ margin-left: 58.3333333333%; }
+
+.col-sm-9,
+.row.cols-sm-9 > * {
+ max-width: 75%;
+ flex-basis: 75%; }
+
+.col-sm-offset-8 {
+ margin-left: 66.6666666667%; }
+
+.col-sm-10,
+.row.cols-sm-10 > * {
+ max-width: 83.3333333333%;
+ flex-basis: 83.3333333333%; }
+
+.col-sm-offset-9 {
+ margin-left: 75%; }
+
+.col-sm-11,
+.row.cols-sm-11 > * {
+ max-width: 91.6666666667%;
+ flex-basis: 91.6666666667%; }
+
+.col-sm-offset-10 {
+ margin-left: 83.3333333333%; }
+
+.col-sm-12,
+.row.cols-sm-12 > * {
+ max-width: 100%;
+ flex-basis: 100%; }
+
+.col-sm-offset-11 {
+ margin-left: 91.6666666667%; }
+
+.col-sm-normal {
+ order: initial; }
+
+.col-sm-first {
+ order: -999; }
+
+.col-sm-last {
+ order: 999; }
+
+@media screen and (min-width: 500px) {
+ .col-md,
+ [class^='col-md-'],
+ [class^='col-md-offset-'],
+ .row[class*='cols-md-'] > * {
+ box-sizing: border-box;
+ flex: 0 0 auto;
+ padding: 0 calc(var(--universal-padding) / 2); }
+
+ .col-md,
+ .row.cols-md > * {
+ max-width: 100%;
+ flex-grow: 1;
+ flex-basis: 0; }
+
+ .col-md-1,
+ .row.cols-md-1 > * {
+ max-width: 8.3333333333%;
+ flex-basis: 8.3333333333%; }
+
+ .col-md-offset-0 {
+ margin-left: 0; }
+
+ .col-md-2,
+ .row.cols-md-2 > * {
+ max-width: 16.6666666667%;
+ flex-basis: 16.6666666667%; }
+
+ .col-md-offset-1 {
+ margin-left: 8.3333333333%; }
+
+ .col-md-3,
+ .row.cols-md-3 > * {
+ max-width: 25%;
+ flex-basis: 25%; }
+
+ .col-md-offset-2 {
+ margin-left: 16.6666666667%; }
+
+ .col-md-4,
+ .row.cols-md-4 > * {
+ max-width: 33.3333333333%;
+ flex-basis: 33.3333333333%; }
+
+ .col-md-offset-3 {
+ margin-left: 25%; }
+
+ .col-md-5,
+ .row.cols-md-5 > * {
+ max-width: 41.6666666667%;
+ flex-basis: 41.6666666667%; }
+
+ .col-md-offset-4 {
+ margin-left: 33.3333333333%; }
+
+ .col-md-6,
+ .row.cols-md-6 > * {
+ max-width: 50%;
+ flex-basis: 50%; }
+
+ .col-md-offset-5 {
+ margin-left: 41.6666666667%; }
+
+ .col-md-7,
+ .row.cols-md-7 > * {
+ max-width: 58.3333333333%;
+ flex-basis: 58.3333333333%; }
+
+ .col-md-offset-6 {
+ margin-left: 50%; }
+
+ .col-md-8,
+ .row.cols-md-8 > * {
+ max-width: 66.6666666667%;
+ flex-basis: 66.6666666667%; }
+
+ .col-md-offset-7 {
+ margin-left: 58.3333333333%; }
+
+ .col-md-9,
+ .row.cols-md-9 > * {
+ max-width: 75%;
+ flex-basis: 75%; }
+
+ .col-md-offset-8 {
+ margin-left: 66.6666666667%; }
+
+ .col-md-10,
+ .row.cols-md-10 > * {
+ max-width: 83.3333333333%;
+ flex-basis: 83.3333333333%; }
+
+ .col-md-offset-9 {
+ margin-left: 75%; }
+
+ .col-md-11,
+ .row.cols-md-11 > * {
+ max-width: 91.6666666667%;
+ flex-basis: 91.6666666667%; }
+
+ .col-md-offset-10 {
+ margin-left: 83.3333333333%; }
+
+ .col-md-12,
+ .row.cols-md-12 > * {
+ max-width: 100%;
+ flex-basis: 100%; }
+
+ .col-md-offset-11 {
+ margin-left: 91.6666666667%; }
+
+ .col-md-normal {
+ order: initial; }
+
+ .col-md-first {
+ order: -999; }
+
+ .col-md-last {
+ order: 999; } }
+@media screen and (min-width: 1280px) {
+ .col-lg,
+ [class^='col-lg-'],
+ [class^='col-lg-offset-'],
+ .row[class*='cols-lg-'] > * {
+ box-sizing: border-box;
+ flex: 0 0 auto;
+ padding: 0 calc(var(--universal-padding) / 2); }
+
+ .col-lg,
+ .row.cols-lg > * {
+ max-width: 100%;
+ flex-grow: 1;
+ flex-basis: 0; }
+
+ .col-lg-1,
+ .row.cols-lg-1 > * {
+ max-width: 8.3333333333%;
+ flex-basis: 8.3333333333%; }
+
+ .col-lg-offset-0 {
+ margin-left: 0; }
+
+ .col-lg-2,
+ .row.cols-lg-2 > * {
+ max-width: 16.6666666667%;
+ flex-basis: 16.6666666667%; }
+
+ .col-lg-offset-1 {
+ margin-left: 8.3333333333%; }
+
+ .col-lg-3,
+ .row.cols-lg-3 > * {
+ max-width: 25%;
+ flex-basis: 25%; }
+
+ .col-lg-offset-2 {
+ margin-left: 16.6666666667%; }
+
+ .col-lg-4,
+ .row.cols-lg-4 > * {
+ max-width: 33.3333333333%;
+ flex-basis: 33.3333333333%; }
+
+ .col-lg-offset-3 {
+ margin-left: 25%; }
+
+ .col-lg-5,
+ .row.cols-lg-5 > * {
+ max-width: 41.6666666667%;
+ flex-basis: 41.6666666667%; }
+
+ .col-lg-offset-4 {
+ margin-left: 33.3333333333%; }
+
+ .col-lg-6,
+ .row.cols-lg-6 > * {
+ max-width: 50%;
+ flex-basis: 50%; }
+
+ .col-lg-offset-5 {
+ margin-left: 41.6666666667%; }
+
+ .col-lg-7,
+ .row.cols-lg-7 > * {
+ max-width: 58.3333333333%;
+ flex-basis: 58.3333333333%; }
+
+ .col-lg-offset-6 {
+ margin-left: 50%; }
+
+ .col-lg-8,
+ .row.cols-lg-8 > * {
+ max-width: 66.6666666667%;
+ flex-basis: 66.6666666667%; }
+
+ .col-lg-offset-7 {
+ margin-left: 58.3333333333%; }
+
+ .col-lg-9,
+ .row.cols-lg-9 > * {
+ max-width: 75%;
+ flex-basis: 75%; }
+
+ .col-lg-offset-8 {
+ margin-left: 66.6666666667%; }
+
+ .col-lg-10,
+ .row.cols-lg-10 > * {
+ max-width: 83.3333333333%;
+ flex-basis: 83.3333333333%; }
+
+ .col-lg-offset-9 {
+ margin-left: 75%; }
+
+ .col-lg-11,
+ .row.cols-lg-11 > * {
+ max-width: 91.6666666667%;
+ flex-basis: 91.6666666667%; }
+
+ .col-lg-offset-10 {
+ margin-left: 83.3333333333%; }
+
+ .col-lg-12,
+ .row.cols-lg-12 > * {
+ max-width: 100%;
+ flex-basis: 100%; }
+
+ .col-lg-offset-11 {
+ margin-left: 91.6666666667%; }
+
+ .col-lg-normal {
+ order: initial; }
+
+ .col-lg-first {
+ order: -999; }
+
+ .col-lg-last {
+ order: 999; } }
+/* Card component CSS variable definitions */
+:root {
+ --card-back-color: #f8f8f8;
+ --card-fore-color: #111;
+ --card-border-color: #ddd; }
+
+.card {
+ display: flex;
+ flex-direction: column;
+ justify-content: space-between;
+ align-self: center;
+ position: relative;
+ width: 100%;
+ background: var(--card-back-color);
+ color: var(--card-fore-color);
+ border: 0.0625rem solid var(--card-border-color);
+ border-radius: var(--universal-border-radius);
+ margin: var(--universal-margin);
+ overflow: hidden; }
+ @media screen and (min-width: 320px) {
+ .card {
+ max-width: 320px; } }
+ .card > .sectione {
+ background: var(--card-back-color);
+ color: var(--card-fore-color);
+ box-sizing: border-box;
+ margin: 0;
+ border: 0;
+ border-radius: 0;
+ border-bottom: 0.0625rem solid var(--card-border-color);
+ padding: var(--universal-padding);
+ width: 100%; }
+ .card > .sectione.media {
+ height: 200px;
+ padding: 0;
+ -o-object-fit: cover;
+ object-fit: cover; }
+ .card > .sectione:last-child {
+ border-bottom: 0; }
+
+/*
+ Custom elements for card elements.
+*/
+@media screen and (min-width: 240px) {
+ .card.small {
+ max-width: 240px; } }
+@media screen and (min-width: 480px) {
+ .card.large {
+ max-width: 480px; } }
+.card.fluid {
+ max-width: 100%;
+ width: auto; }
+
+.card.warning {
+/* --card-back-color: #ffca28; */
+ --card-back-color: #e5b8b7;
+ --card-border-color: #e8b825; }
+
+.card.error {
+ --card-back-color: #b71c1c;
+ --card-fore-color: #f8f8f8;
+ --card-border-color: #a71a1a; }
+
+.card > .sectione.dark {
+ --card-back-color: #e0e0e0; }
+
+.card > .sectione.double-padded {
+ padding: calc(1.5 * var(--universal-padding)); }
+
+/*
+ Definitions for forms and input elements.
+*/
+/* Input_control module CSS variable definitions */
+:root {
+ --form-back-color: #f0f0f0;
+ --form-fore-color: #111;
+ --form-border-color: #ddd;
+ --input-back-color: #f8f8f8;
+ --input-fore-color: #111;
+ --input-border-color: #ddd;
+ --input-focus-color: #0288d1;
+ --input-invalid-color: #d32f2f;
+ --button-back-color: #e2e2e2;
+ --button-hover-back-color: #dcdcdc;
+ --button-fore-color: #212121;
+ --button-border-color: transparent;
+ --button-hover-border-color: transparent;
+ --button-group-border-color: rgba(124, 124, 124, 0.54); }
+
+form {
+ background: var(--form-back-color);
+ color: var(--form-fore-color);
+ border: 0.0625rem solid var(--form-border-color);
+ border-radius: var(--universal-border-radius);
+ margin: var(--universal-margin);
+ padding: calc(2 * var(--universal-padding)) var(--universal-padding); }
+
+fieldset {
+ border: 0.0625rem solid var(--form-border-color);
+ border-radius: var(--universal-border-radius);
+ margin: calc(var(--universal-margin) / 4);
+ padding: var(--universal-padding); }
+
+legend {
+ box-sizing: border-box;
+ display: table;
+ max-width: 100%;
+ white-space: normal;
+ font-weight: 700;
+ padding: calc(var(--universal-padding) / 2); }
+
+label {
+ padding: calc(var(--universal-padding) / 2) var(--universal-padding); }
+
+.input-group {
+ display: inline-block; }
+ .input-group.fluid {
+ display: flex;
+ align-items: center;
+ justify-content: center; }
+ .input-group.fluid > input {
+ max-width: 100%;
+ flex-grow: 1;
+ flex-basis: 0px; }
+ @media screen and (max-width: 499px) {
+ .input-group.fluid {
+ align-items: stretch;
+ flex-direction: column; } }
+ .input-group.vertical {
+ display: flex;
+ align-items: stretch;
+ flex-direction: column; }
+ .input-group.vertical > input {
+ max-width: 100%;
+ flex-grow: 1;
+ flex-basis: 0px; }
+
+[type="number"]::-webkit-inner-spin-button, [type="number"]::-webkit-outer-spin-button {
+ height: auto; }
+
+[type="search"] {
+ -webkit-appearance: textfield;
+ outline-offset: -2px; }
+
+[type="search"]::-webkit-search-cancel-button,
+[type="search"]::-webkit-search-decoration {
+ -webkit-appearance: none; }
+
+input:not([type]), [type="text"], [type="email"], [type="number"], [type="search"],
+[type="password"], [type="url"], [type="tel"], [type="checkbox"], [type="radio"], textarea, select {
+ box-sizing: border-box;
+ background: var(--input-back-color);
+ color: var(--input-fore-color);
+ border: 0.0625rem solid var(--input-border-color);
+ border-radius: var(--universal-border-radius);
+ margin: calc(var(--universal-margin) / 2);
+ padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); }
+
+input:not([type="button"]):not([type="submit"]):not([type="reset"]):hover, input:not([type="button"]):not([type="submit"]):not([type="reset"]):focus, textarea:hover, textarea:focus, select:hover, select:focus {
+ border-color: var(--input-focus-color);
+ box-shadow: none; }
+input:not([type="button"]):not([type="submit"]):not([type="reset"]):invalid, input:not([type="button"]):not([type="submit"]):not([type="reset"]):focus:invalid, textarea:invalid, textarea:focus:invalid, select:invalid, select:focus:invalid {
+ border-color: var(--input-invalid-color);
+ box-shadow: none; }
+input:not([type="button"]):not([type="submit"]):not([type="reset"])[readonly], textarea[readonly], select[readonly] {
+ background: var(--secondary-back-color); }
+
+select {
+ max-width: 100%; }
+
+option {
+ overflow: hidden;
+ text-overflow: ellipsis; }
+
+[type="checkbox"], [type="radio"] {
+ -webkit-appearance: none;
+ -moz-appearance: none;
+ appearance: none;
+ position: relative;
+ height: calc(1rem + var(--universal-padding) / 2);
+ width: calc(1rem + var(--universal-padding) / 2);
+ vertical-align: text-bottom;
+ padding: 0;
+ flex-basis: calc(1rem + var(--universal-padding) / 2) !important;
+ flex-grow: 0 !important; }
+ [type="checkbox"]:checked:before, [type="radio"]:checked:before {
+ position: absolute; }
+
+[type="checkbox"]:checked:before {
+ content: '\2713';
+ font-family: sans-serif;
+ font-size: calc(1rem + var(--universal-padding) / 2);
+ top: calc(0rem - var(--universal-padding));
+ left: calc(var(--universal-padding) / 4); }
+
+[type="radio"] {
+ border-radius: 100%; }
+ [type="radio"]:checked:before {
+ border-radius: 100%;
+ content: '';
+ top: calc(0.0625rem + var(--universal-padding) / 2);
+ left: calc(0.0625rem + var(--universal-padding) / 2);
+ background: var(--input-fore-color);
+ width: 0.5rem;
+ height: 0.5rem; }
+
+:placeholder-shown {
+ color: var(--input-fore-color); }
+
+::-ms-placeholder {
+ color: var(--input-fore-color);
+ opacity: 0.54; }
+
+button::-moz-focus-inner, [type="button"]::-moz-focus-inner, [type="reset"]::-moz-focus-inner, [type="submit"]::-moz-focus-inner {
+ border-style: none;
+ padding: 0; }
+
+button, html [type="button"], [type="reset"], [type="submit"] {
+ -webkit-appearance: button; }
+
+button {
+ overflow: visible;
+ text-transform: none; }
+
+button, [type="button"], [type="submit"], [type="reset"],
+a.button, label.button, .button,
+a[role="button"], label[role="button"], [role="button"] {
+ display: inline-block;
+ background: var(--button-back-color);
+ color: var(--button-fore-color);
+ border: 0.0625rem solid var(--button-border-color);
+ border-radius: var(--universal-border-radius);
+ padding: var(--universal-padding) calc(1.5 * var(--universal-padding));
+ margin: var(--universal-margin);
+ text-decoration: none;
+ cursor: pointer;
+ transition: background 0.3s; }
+ button:hover, button:focus, [type="button"]:hover, [type="button"]:focus, [type="submit"]:hover, [type="submit"]:focus, [type="reset"]:hover, [type="reset"]:focus,
+ a.button:hover,
+ a.button:focus, label.button:hover, label.button:focus, .button:hover, .button:focus,
+ a[role="button"]:hover,
+ a[role="button"]:focus, label[role="button"]:hover, label[role="button"]:focus, [role="button"]:hover, [role="button"]:focus {
+ background: var(--button-hover-back-color);
+ border-color: var(--button-hover-border-color); }
+
+input:disabled, input[disabled], textarea:disabled, textarea[disabled], select:disabled, select[disabled], button:disabled, button[disabled], .button:disabled, .button[disabled], [role="button"]:disabled, [role="button"][disabled] {
+ cursor: not-allowed;
+ opacity: 0.75; }
+
+.button-group {
+ display: flex;
+ border: 0.0625rem solid var(--button-group-border-color);
+ border-radius: var(--universal-border-radius);
+ margin: var(--universal-margin); }
+ .button-group > button, .button-group [type="button"], .button-group > [type="submit"], .button-group > [type="reset"], .button-group > .button, .button-group > [role="button"] {
+ margin: 0;
+ max-width: 100%;
+ flex: 1 1 auto;
+ text-align: center;
+ border: 0;
+ border-radius: 0;
+ box-shadow: none; }
+ .button-group > :not(:first-child) {
+ border-left: 0.0625rem solid var(--button-group-border-color); }
+ @media screen and (max-width: 499px) {
+ .button-group {
+ flex-direction: column; }
+ .button-group > :not(:first-child) {
+ border: 0;
+ border-top: 0.0625rem solid var(--button-group-border-color); } }
+
+/*
+ Custom elements for forms and input elements.
+*/
+button.primary, [type="button"].primary, [type="submit"].primary, [type="reset"].primary, .button.primary, [role="button"].primary {
+ --button-back-color: #1976d2;
+ --button-fore-color: #f8f8f8; }
+ button.primary:hover, button.primary:focus, [type="button"].primary:hover, [type="button"].primary:focus, [type="submit"].primary:hover, [type="submit"].primary:focus, [type="reset"].primary:hover, [type="reset"].primary:focus, .button.primary:hover, .button.primary:focus, [role="button"].primary:hover, [role="button"].primary:focus {
+ --button-hover-back-color: #1565c0; }
+
+button.secondary, [type="button"].secondary, [type="submit"].secondary, [type="reset"].secondary, .button.secondary, [role="button"].secondary {
+ --button-back-color: #d32f2f;
+ --button-fore-color: #f8f8f8; }
+ button.secondary:hover, button.secondary:focus, [type="button"].secondary:hover, [type="button"].secondary:focus, [type="submit"].secondary:hover, [type="submit"].secondary:focus, [type="reset"].secondary:hover, [type="reset"].secondary:focus, .button.secondary:hover, .button.secondary:focus, [role="button"].secondary:hover, [role="button"].secondary:focus {
+ --button-hover-back-color: #c62828; }
+
+button.tertiary, [type="button"].tertiary, [type="submit"].tertiary, [type="reset"].tertiary, .button.tertiary, [role="button"].tertiary {
+ --button-back-color: #308732;
+ --button-fore-color: #f8f8f8; }
+ button.tertiary:hover, button.tertiary:focus, [type="button"].tertiary:hover, [type="button"].tertiary:focus, [type="submit"].tertiary:hover, [type="submit"].tertiary:focus, [type="reset"].tertiary:hover, [type="reset"].tertiary:focus, .button.tertiary:hover, .button.tertiary:focus, [role="button"].tertiary:hover, [role="button"].tertiary:focus {
+ --button-hover-back-color: #277529; }
+
+button.inverse, [type="button"].inverse, [type="submit"].inverse, [type="reset"].inverse, .button.inverse, [role="button"].inverse {
+ --button-back-color: #212121;
+ --button-fore-color: #f8f8f8; }
+ button.inverse:hover, button.inverse:focus, [type="button"].inverse:hover, [type="button"].inverse:focus, [type="submit"].inverse:hover, [type="submit"].inverse:focus, [type="reset"].inverse:hover, [type="reset"].inverse:focus, .button.inverse:hover, .button.inverse:focus, [role="button"].inverse:hover, [role="button"].inverse:focus {
+ --button-hover-back-color: #111; }
+
+button.small, [type="button"].small, [type="submit"].small, [type="reset"].small, .button.small, [role="button"].small {
+ padding: calc(0.5 * var(--universal-padding)) calc(0.75 * var(--universal-padding));
+ margin: var(--universal-margin); }
+
+button.large, [type="button"].large, [type="submit"].large, [type="reset"].large, .button.large, [role="button"].large {
+ padding: calc(1.5 * var(--universal-padding)) calc(2 * var(--universal-padding));
+ margin: var(--universal-margin); }
+
+/*
+ Definitions for navigation elements.
+*/
+/* Navigation module CSS variable definitions */
+:root {
+ --header-back-color: #f8f8f8;
+ --header-hover-back-color: #f0f0f0;
+ --header-fore-color: #444;
+ --header-border-color: #ddd;
+ --nav-back-color: #f8f8f8;
+ --nav-hover-back-color: #f0f0f0;
+ --nav-fore-color: #444;
+ --nav-border-color: #ddd;
+ --nav-link-color: #0277bd;
+ --footer-fore-color: #444;
+ --footer-back-color: #f8f8f8;
+ --footer-border-color: #ddd;
+ --footer-link-color: #0277bd;
+ --drawer-back-color: #f8f8f8;
+ --drawer-hover-back-color: #f0f0f0;
+ --drawer-border-color: #ddd;
+ --drawer-close-color: #444; }
+
+header {
+ height: 3.1875rem;
+ background: var(--header-back-color);
+ color: var(--header-fore-color);
+ border-bottom: 0.0625rem solid var(--header-border-color);
+ padding: calc(var(--universal-padding) / 4) 0;
+ white-space: nowrap;
+ overflow-x: auto;
+ overflow-y: hidden; }
+ header.row {
+ box-sizing: content-box; }
+ header .logo {
+ color: var(--header-fore-color);
+ font-size: 1.75rem;
+ padding: var(--universal-padding) calc(2 * var(--universal-padding));
+ text-decoration: none; }
+ header button, header [type="button"], header .button, header [role="button"] {
+ box-sizing: border-box;
+ position: relative;
+ top: calc(0rem - var(--universal-padding) / 4);
+ height: calc(3.1875rem + var(--universal-padding) / 2);
+ background: var(--header-back-color);
+ line-height: calc(3.1875rem - var(--universal-padding) * 1.5);
+ text-align: center;
+ color: var(--header-fore-color);
+ border: 0;
+ border-radius: 0;
+ margin: 0;
+ text-transform: uppercase; }
+ header button:hover, header button:focus, header [type="button"]:hover, header [type="button"]:focus, header .button:hover, header .button:focus, header [role="button"]:hover, header [role="button"]:focus {
+ background: var(--header-hover-back-color); }
+
+nav {
+ background: var(--nav-back-color);
+ color: var(--nav-fore-color);
+ border: 0.0625rem solid var(--nav-border-color);
+ border-radius: var(--universal-border-radius);
+ margin: var(--universal-margin); }
+ nav * {
+ padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); }
+ nav a, nav a:visited {
+ display: block;
+ color: var(--nav-link-color);
+ border-radius: var(--universal-border-radius);
+ transition: background 0.3s; }
+ nav a:hover, nav a:focus, nav a:visited:hover, nav a:visited:focus {
+ text-decoration: none;
+ background: var(--nav-hover-back-color); }
+ nav .sublink-1 {
+ position: relative;
+ margin-left: calc(2 * var(--universal-padding)); }
+ nav .sublink-1:before {
+ position: absolute;
+ left: calc(var(--universal-padding) - 1 * var(--universal-padding));
+ top: -0.0625rem;
+ content: '';
+ height: 100%;
+ border: 0.0625rem solid var(--nav-border-color);
+ border-left: 0; }
+ nav .sublink-2 {
+ position: relative;
+ margin-left: calc(4 * var(--universal-padding)); }
+ nav .sublink-2:before {
+ position: absolute;
+ left: calc(var(--universal-padding) - 3 * var(--universal-padding));
+ top: -0.0625rem;
+ content: '';
+ height: 100%;
+ border: 0.0625rem solid var(--nav-border-color);
+ border-left: 0; }
+
+footer {
+ background: var(--footer-back-color);
+ color: var(--footer-fore-color);
+ border-top: 0.0625rem solid var(--footer-border-color);
+ padding: calc(2 * var(--universal-padding)) var(--universal-padding);
+ font-size: 0.875rem; }
+ footer a, footer a:visited {
+ color: var(--footer-link-color); }
+
+header.sticky {
+ position: -webkit-sticky;
+ position: sticky;
+ z-index: 1101;
+ top: 0; }
+
+footer.sticky {
+ position: -webkit-sticky;
+ position: sticky;
+ z-index: 1101;
+ bottom: 0; }
+
+.drawer-toggle:before {
+ display: inline-block;
+ position: relative;
+ vertical-align: bottom;
+ content: '\00a0\2261\00a0';
+ font-family: sans-serif;
+ font-size: 1.5em; }
+@media screen and (min-width: 500px) {
+ .drawer-toggle:not(.persistent) {
+ display: none; } }
+
+[type="checkbox"].drawer {
+ height: 1px;
+ width: 1px;
+ margin: -1px;
+ overflow: hidden;
+ position: absolute;
+ clip: rect(0 0 0 0);
+ -webkit-clip-path: inset(100%);
+ clip-path: inset(100%); }
+ [type="checkbox"].drawer + * {
+ display: block;
+ box-sizing: border-box;
+ position: fixed;
+ top: 0;
+ width: 320px;
+ height: 100vh;
+ overflow-y: auto;
+ background: var(--drawer-back-color);
+ border: 0.0625rem solid var(--drawer-border-color);
+ border-radius: 0;
+ margin: 0;
+ z-index: 1110;
+ right: -320px;
+ transition: right 0.3s; }
+ [type="checkbox"].drawer + * .drawer-close {
+ position: absolute;
+ top: var(--universal-margin);
+ right: var(--universal-margin);
+ z-index: 1111;
+ width: 2rem;
+ height: 2rem;
+ border-radius: var(--universal-border-radius);
+ padding: var(--universal-padding);
+ margin: 0;
+ cursor: pointer;
+ transition: background 0.3s; }
+ [type="checkbox"].drawer + * .drawer-close:before {
+ display: block;
+ content: '\00D7';
+ color: var(--drawer-close-color);
+ position: relative;
+ font-family: sans-serif;
+ font-size: 2rem;
+ line-height: 1;
+ text-align: center; }
+ [type="checkbox"].drawer + * .drawer-close:hover, [type="checkbox"].drawer + * .drawer-close:focus {
+ background: var(--drawer-hover-back-color); }
+ @media screen and (max-width: 320px) {
+ [type="checkbox"].drawer + * {
+ width: 100%; } }
+ [type="checkbox"].drawer:checked + * {
+ right: 0; }
+ @media screen and (min-width: 500px) {
+ [type="checkbox"].drawer:not(.persistent) + * {
+ position: static;
+ height: 100%;
+ z-index: 1100; }
+ [type="checkbox"].drawer:not(.persistent) + * .drawer-close {
+ display: none; } }
+
+/*
+ Definitions for the responsive table component.
+*/
+/* Table module CSS variable definitions. */
+:root {
+ --table-border-color: #aaa;
+ --table-border-separator-color: #666;
+ --table-head-back-color: #e6e6e6;
+ --table-head-fore-color: #111;
+ --table-body-back-color: #f8f8f8;
+ --table-body-fore-color: #111;
+ --table-body-alt-back-color: #eee; }
+
+table {
+ border-collapse: separate;
+ border-spacing: 0;
+ : margin: calc(1.5 * var(--universal-margin)) var(--universal-margin);
+ display: flex;
+ flex: 0 1 auto;
+ flex-flow: row wrap;
+ padding: var(--universal-padding);
+ padding-top: 0;
+ margin: calc(1.5 * var(--universal-margin)) var(--universal-margin); }
+ table caption {
+ font-size: 1.25 * rem;
+ margin: calc(2 * var(--universal-margin)) 0;
+ max-width: 100%;
+ flex: 0 0 100%;
+ text-align: left;}
+ table thead, table tbody {
+ display: flex;
+ flex-flow: row wrap;
+ border: 0.0625rem solid var(--table-border-color); }
+ table thead {
+ z-index: 999;
+ border-radius: var(--universal-border-radius) var(--universal-border-radius) 0 0;
+ border-bottom: 0.0625rem solid var(--table-border-separator-color); }
+ table tbody {
+ border-top: 0;
+ margin-top: calc(0 - var(--universal-margin));
+ border-radius: 0 0 var(--universal-border-radius) var(--universal-border-radius); }
+ table tr {
+ display: flex;
+ padding: 0; }
+ table th, table td {
+ padding: calc(0.5 * var(--universal-padding));
+ font-size: 0.9rem; }
+ table th {
+ text-align: left;
+ background: var(--table-head-back-color);
+ color: var(--table-head-fore-color); }
+ table td {
+ background: var(--table-body-back-color);
+ color: var(--table-body-fore-color);
+ border-top: 0.0625rem solid var(--table-border-color); }
+
+table:not(.horizontal) {
+ overflow: auto;
+ max-height: 850px; }
+ table:not(.horizontal) thead, table:not(.horizontal) tbody {
+ max-width: 100%;
+ flex: 0 0 100%; }
+ table:not(.horizontal) tr {
+ flex-flow: row wrap;
+ flex: 0 0 100%; }
+ table:not(.horizontal) th, table:not(.horizontal) td {
+ flex: 1 0 0%;
+ overflow: hidden;
+ text-overflow: ellipsis; }
+ table:not(.horizontal) thead {
+ position: sticky;
+ top: 0; }
+ table:not(.horizontal) tbody tr:first-child td {
+ border-top: 0; }
+
+table.horizontal {
+ border: 0; }
+ table.horizontal thead, table.horizontal tbody {
+ border: 0;
+ flex-flow: row nowrap; }
+ table.horizontal tbody {
+ overflow: auto;
+ justify-content: space-between;
+ flex: 1 0 0;
+ margin-left: calc( 4 * var(--universal-margin));
+ padding-bottom: calc(var(--universal-padding) / 4); }
+ table.horizontal tr {
+ flex-direction: column;
+ flex: 1 0 auto; }
+ table.horizontal th, table.horizontal td {
+ width: 100%;
+ border: 0;
+ border-bottom: 0.0625rem solid var(--table-border-color); }
+ table.horizontal th:not(:first-child), table.horizontal td:not(:first-child) {
+ border-top: 0; }
+ table.horizontal th {
+ text-align: right;
+ border-left: 0.0625rem solid var(--table-border-color);
+ border-right: 0.0625rem solid var(--table-border-separator-color); }
+ table.horizontal thead tr:first-child {
+ padding-left: 0; }
+ table.horizontal th:first-child, table.horizontal td:first-child {
+ border-top: 0.0625rem solid var(--table-border-color); }
+ table.horizontal tbody tr:last-child td {
+ border-right: 0.0625rem solid var(--table-border-color); }
+ table.horizontal tbody tr:last-child td:first-child {
+ border-top-right-radius: 0.25rem; }
+ table.horizontal tbody tr:last-child td:last-child {
+ border-bottom-right-radius: 0.25rem; }
+ table.horizontal thead tr:first-child th:first-child {
+ border-top-left-radius: 0.25rem; }
+ table.horizontal thead tr:first-child th:last-child {
+ border-bottom-left-radius: 0.25rem; }
+
+@media screen and (max-width: 499px) {
+ table, table.horizontal {
+ border-collapse: collapse;
+ border: 0;
+ width: 100%;
+ display: table; }
+ table thead, table th, table.horizontal thead, table.horizontal th {
+ border: 0;
+ height: 1px;
+ width: 1px;
+ margin: -1px;
+ overflow: hidden;
+ padding: 0;
+ position: absolute;
+ clip: rect(0 0 0 0);
+ -webkit-clip-path: inset(100%);
+ clip-path: inset(100%); }
+ table tbody, table.horizontal tbody {
+ border: 0;
+ display: table-row-group; }
+ table tr, table.horizontal tr {
+ display: block;
+ border: 0.0625rem solid var(--table-border-color);
+ border-radius: var(--universal-border-radius);
+ background: #fafafa;
+ padding: var(--universal-padding);
+ margin: var(--universal-margin);
+ margin-bottom: calc(2 * var(--universal-margin)); }
+ table th, table td, table.horizontal th, table.horizontal td {
+ width: auto; }
+ table td, table.horizontal td {
+ display: block;
+ border: 0;
+ text-align: right; }
+ table td:before, table.horizontal td:before {
+ content: attr(data-label);
+ float: left;
+ font-weight: 600; }
+ table th:first-child, table td:first-child, table.horizontal th:first-child, table.horizontal td:first-child {
+ border-top: 0; }
+ table tbody tr:last-child td, table.horizontal tbody tr:last-child td {
+ border-right: 0; } }
+:root {
+ --table-body-alt-back-color: #eee; }
+
+table tr:nth-of-type(2n) > td {
+ background: var(--table-body-alt-back-color); }
+
+@media screen and (max-width: 500px) {
+ table tr:nth-of-type(2n) {
+ background: var(--table-body-alt-back-color); } }
+:root {
+ --table-body-hover-back-color: #90caf9; }
+
+table.hoverable tr:hover, table.hoverable tr:hover > td, table.hoverable tr:focus, table.hoverable tr:focus > td {
+ background: var(--table-body-hover-back-color); }
+
+@media screen and (max-width: 500px) {
+ table.hoverable tr:hover, table.hoverable tr:hover > td, table.hoverable tr:focus, table.hoverable tr:focus > td {
+ background: var(--table-body-hover-back-color); } }
+/*
+ Definitions for contextual background elements, toasts and tooltips.
+*/
+/* Contextual module CSS variable definitions */
+:root {
+ --mark-back-color: #0277bd;
+ --mark-fore-color: #fafafa; }
+
+mark {
+ background: var(--mark-back-color);
+ color: var(--mark-fore-color);
+ font-size: 0.95em;
+ line-height: 1em;
+ border-radius: var(--universal-border-radius);
+ padding: calc(var(--universal-padding) / 4) calc(var(--universal-padding) / 2); }
+ mark.inline-block {
+ display: inline-block;
+ font-size: 1em;
+ line-height: 1.5;
+ padding: calc(var(--universal-padding) / 2) var(--universal-padding); }
+
+:root {
+ --toast-back-color: #424242;
+ --toast-fore-color: #fafafa; }
+
+.toast {
+ position: fixed;
+ bottom: calc(var(--universal-margin) * 3);
+ left: 50%;
+ transform: translate(-50%, -50%);
+ z-index: 1111;
+ color: var(--toast-fore-color);
+ background: var(--toast-back-color);
+ border-radius: calc(var(--universal-border-radius) * 16);
+ padding: var(--universal-padding) calc(var(--universal-padding) * 3); }
+
+:root {
+ --tooltip-back-color: #212121;
+ --tooltip-fore-color: #fafafa; }
+
+.tooltip {
+ position: relative;
+ display: inline-block; }
+ .tooltip:before, .tooltip:after {
+ position: absolute;
+ opacity: 0;
+ clip: rect(0 0 0 0);
+ -webkit-clip-path: inset(100%);
+ clip-path: inset(100%);
+ transition: all 0.3s;
+ z-index: 1010;
+ left: 50%; }
+ .tooltip:not(.bottom):before, .tooltip:not(.bottom):after {
+ bottom: 75%; }
+ .tooltip.bottom:before, .tooltip.bottom:after {
+ top: 75%; }
+ .tooltip:hover:before, .tooltip:hover:after, .tooltip:focus:before, .tooltip:focus:after {
+ opacity: 1;
+ clip: auto;
+ -webkit-clip-path: inset(0%);
+ clip-path: inset(0%); }
+ .tooltip:before {
+ content: '';
+ background: transparent;
+ border: var(--universal-margin) solid transparent;
+ left: calc(50% - var(--universal-margin)); }
+ .tooltip:not(.bottom):before {
+ border-top-color: #212121; }
+ .tooltip.bottom:before {
+ border-bottom-color: #212121; }
+ .tooltip:after {
+ content: attr(aria-label);
+ color: var(--tooltip-fore-color);
+ background: var(--tooltip-back-color);
+ border-radius: var(--universal-border-radius);
+ padding: var(--universal-padding);
+ white-space: nowrap;
+ transform: translateX(-50%); }
+ .tooltip:not(.bottom):after {
+ margin-bottom: calc(2 * var(--universal-margin)); }
+ .tooltip.bottom:after {
+ margin-top: calc(2 * var(--universal-margin)); }
+
+:root {
+ --modal-overlay-color: rgba(0, 0, 0, 0.45);
+ --modal-close-color: #444;
+ --modal-close-hover-color: #f0f0f0; }
+
+[type="checkbox"].modal {
+ height: 1px;
+ width: 1px;
+ margin: -1px;
+ overflow: hidden;
+ position: absolute;
+ clip: rect(0 0 0 0);
+ -webkit-clip-path: inset(100%);
+ clip-path: inset(100%); }
+ [type="checkbox"].modal + div {
+ position: fixed;
+ top: 0;
+ left: 0;
+ display: none;
+ width: 100vw;
+ height: 100vh;
+ background: var(--modal-overlay-color); }
+ [type="checkbox"].modal + div .card {
+ margin: 0 auto;
+ max-height: 50vh;
+ overflow: auto; }
+ [type="checkbox"].modal + div .card .modal-close {
+ position: absolute;
+ top: 0;
+ right: 0;
+ width: 1.75rem;
+ height: 1.75rem;
+ border-radius: var(--universal-border-radius);
+ padding: var(--universal-padding);
+ margin: 0;
+ cursor: pointer;
+ transition: background 0.3s; }
+ [type="checkbox"].modal + div .card .modal-close:before {
+ display: block;
+ content: '\00D7';
+ color: var(--modal-close-color);
+ position: relative;
+ font-family: sans-serif;
+ font-size: 1.75rem;
+ line-height: 1;
+ text-align: center; }
+ [type="checkbox"].modal + div .card .modal-close:hover, [type="checkbox"].modal + div .card .modal-close:focus {
+ background: var(--modal-close-hover-color); }
+ [type="checkbox"].modal:checked + div {
+ display: flex;
+ flex: 0 1 auto;
+ z-index: 1200; }
+ [type="checkbox"].modal:checked + div .card .modal-close {
+ z-index: 1211; }
+
+:root {
+ --collapse-label-back-color: #e8e8e8;
+ --collapse-label-fore-color: #212121;
+ --collapse-label-hover-back-color: #f0f0f0;
+ --collapse-selected-label-back-color: #ececec;
+ --collapse-border-color: #ddd;
+ --collapse-content-back-color: #fafafa;
+ --collapse-selected-label-border-color: #0277bd; }
+
+.collapse {
+ width: calc(100% - 2 * var(--universal-margin));
+ opacity: 1;
+ display: flex;
+ flex-direction: column;
+ margin: var(--universal-margin);
+ border-radius: var(--universal-border-radius); }
+ .collapse > [type="radio"], .collapse > [type="checkbox"] {
+ height: 1px;
+ width: 1px;
+ margin: -1px;
+ overflow: hidden;
+ position: absolute;
+ clip: rect(0 0 0 0);
+ -webkit-clip-path: inset(100%);
+ clip-path: inset(100%); }
+ .collapse > label {
+ flex-grow: 1;
+ display: inline-block;
+ height: 1.5rem;
+ cursor: pointer;
+ transition: background 0.3s;
+ color: var(--collapse-label-fore-color);
+ background: var(--collapse-label-back-color);
+ border: 0.0625rem solid var(--collapse-border-color);
+ padding: calc(1.5 * var(--universal-padding)); }
+ .collapse > label:hover, .collapse > label:focus {
+ background: var(--collapse-label-hover-back-color); }
+ .collapse > label + div {
+ flex-basis: auto;
+ height: 1px;
+ width: 1px;
+ margin: -1px;
+ overflow: hidden;
+ position: absolute;
+ clip: rect(0 0 0 0);
+ -webkit-clip-path: inset(100%);
+ clip-path: inset(100%);
+ transition: max-height 0.3s;
+ max-height: 1px; }
+ .collapse > :checked + label {
+ background: var(--collapse-selected-label-back-color);
+ border-bottom-color: var(--collapse-selected-label-border-color); }
+ .collapse > :checked + label + div {
+ box-sizing: border-box;
+ position: relative;
+ width: 100%;
+ height: auto;
+ overflow: auto;
+ margin: 0;
+ background: var(--collapse-content-back-color);
+ border: 0.0625rem solid var(--collapse-border-color);
+ border-top: 0;
+ padding: var(--universal-padding);
+ clip: auto;
+ -webkit-clip-path: inset(0%);
+ clip-path: inset(0%);
+ max-height: 850px; }
+ .collapse > label:not(:first-of-type) {
+ border-top: 0; }
+ .collapse > label:first-of-type {
+ border-radius: var(--universal-border-radius) var(--universal-border-radius) 0 0; }
+ .collapse > label:last-of-type:not(:first-of-type) {
+ border-radius: 0 0 var(--universal-border-radius) var(--universal-border-radius); }
+ .collapse > label:last-of-type:first-of-type {
+ border-radius: var(--universal-border-radius); }
+ .collapse > :checked:last-of-type:not(:first-of-type) + label {
+ border-radius: 0; }
+ .collapse > :checked:last-of-type + label + div {
+ border-radius: 0 0 var(--universal-border-radius) var(--universal-border-radius); }
+
+/*
+ Custom elements for contextual background elements, toasts and tooltips.
+*/
+mark.secondary {
+ --mark-back-color: #d32f2f; }
+
+mark.tertiary {
+ --mark-back-color: #308732; }
+
+mark.tag {
+ padding: calc(var(--universal-padding)/2) var(--universal-padding);
+ border-radius: 1em; }
+
+/*
+ Definitions for progress elements and spinners.
+*/
+/* Progess module CSS variable definitions */
+:root {
+ --progress-back-color: #ddd;
+ --progress-fore-color: #555; }
+
+progress {
+ display: block;
+ vertical-align: baseline;
+ -webkit-appearance: none;
+ -moz-appearance: none;
+ appearance: none;
+ height: 0.75rem;
+ width: calc(100% - 2 * var(--universal-margin));
+ margin: var(--universal-margin);
+ border: 0;
+ border-radius: calc(2 * var(--universal-border-radius));
+ background: var(--progress-back-color);
+ color: var(--progress-fore-color); }
+ progress::-webkit-progress-value {
+ background: var(--progress-fore-color);
+ border-top-left-radius: calc(2 * var(--universal-border-radius));
+ border-bottom-left-radius: calc(2 * var(--universal-border-radius)); }
+ progress::-webkit-progress-bar {
+ background: var(--progress-back-color); }
+ progress::-moz-progress-bar {
+ background: var(--progress-fore-color);
+ border-top-left-radius: calc(2 * var(--universal-border-radius));
+ border-bottom-left-radius: calc(2 * var(--universal-border-radius)); }
+ progress[value="1000"]::-webkit-progress-value {
+ border-radius: calc(2 * var(--universal-border-radius)); }
+ progress[value="1000"]::-moz-progress-bar {
+ border-radius: calc(2 * var(--universal-border-radius)); }
+ progress.inline {
+ display: inline-block;
+ vertical-align: middle;
+ width: 60%; }
+
+:root {
+ --spinner-back-color: #ddd;
+ --spinner-fore-color: #555; }
+
+@keyframes spinner-donut-anim {
+ 0% {
+ transform: rotate(0deg); }
+ 100% {
+ transform: rotate(360deg); } }
+.spinner {
+ display: inline-block;
+ margin: var(--universal-margin);
+ border: 0.25rem solid var(--spinner-back-color);
+ border-left: 0.25rem solid var(--spinner-fore-color);
+ border-radius: 50%;
+ width: 1.25rem;
+ height: 1.25rem;
+ animation: spinner-donut-anim 1.2s linear infinite; }
+
+/*
+ Custom elements for progress bars and spinners.
+*/
+progress.primary {
+ --progress-fore-color: #1976d2; }
+
+progress.secondary {
+ --progress-fore-color: #d32f2f; }
+
+progress.tertiary {
+ --progress-fore-color: #308732; }
+
+.spinner.primary {
+ --spinner-fore-color: #1976d2; }
+
+.spinner.secondary {
+ --spinner-fore-color: #d32f2f; }
+
+.spinner.tertiary {
+ --spinner-fore-color: #308732; }
+
+/*
+ Definitions for icons - powered by Feather (https://feathericons.com/).
+*/
+span[class^='icon-'] {
+ display: inline-block;
+ height: 1em;
+ width: 1em;
+ vertical-align: -0.125em;
+ background-size: contain;
+ margin: 0 calc(var(--universal-margin) / 4); }
+ span[class^='icon-'].secondary {
+ -webkit-filter: invert(25%);
+ filter: invert(25%); }
+ span[class^='icon-'].inverse {
+ -webkit-filter: invert(100%);
+ filter: invert(100%); }
+
+span.icon-alert {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='8' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='16' x2='12' y2='16'%3E%3C/line%3E%3C/svg%3E"); }
+span.icon-bookmark {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M19 21l-7-5-7 5V5a2 2 0 0 1 2-2h10a2 2 0 0 1 2 2z'%3E%3C/path%3E%3C/svg%3E"); }
+span.icon-calendar {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='4' width='18' height='18' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='16' y1='2' x2='16' y2='6'%3E%3C/line%3E%3Cline x1='8' y1='2' x2='8' y2='6'%3E%3C/line%3E%3Cline x1='3' y1='10' x2='21' y2='10'%3E%3C/line%3E%3C/svg%3E"); }
+span.icon-credit {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='1' y='4' width='22' height='16' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='1' y1='10' x2='23' y2='10'%3E%3C/line%3E%3C/svg%3E"); }
+span.icon-edit {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M20 14.66V20a2 2 0 0 1-2 2H4a2 2 0 0 1-2-2V6a2 2 0 0 1 2-2h5.34'%3E%3C/path%3E%3Cpolygon points='18 2 22 6 12 16 8 16 8 12 18 2'%3E%3C/polygon%3E%3C/svg%3E"); }
+span.icon-link {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M18 13v6a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2V8a2 2 0 0 1 2-2h6'%3E%3C/path%3E%3Cpolyline points='15 3 21 3 21 9'%3E%3C/polyline%3E%3Cline x1='10' y1='14' x2='21' y2='3'%3E%3C/line%3E%3C/svg%3E"); }
+span.icon-help {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M9.09 9a3 3 0 0 1 5.83 1c0 2-3 3-3 3'%3E%3C/path%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='17' x2='12' y2='17'%3E%3C/line%3E%3C/svg%3E"); }
+span.icon-home {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M3 9l9-7 9 7v11a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2z'%3E%3C/path%3E%3Cpolyline points='9 22 9 12 15 12 15 22'%3E%3C/polyline%3E%3C/svg%3E"); }
+span.icon-info {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='16' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='8' x2='12' y2='8'%3E%3C/line%3E%3C/svg%3E"); }
+span.icon-lock {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='11' width='18' height='11' rx='2' ry='2'%3E%3C/rect%3E%3Cpath d='M7 11V7a5 5 0 0 1 10 0v4'%3E%3C/path%3E%3C/svg%3E"); }
+span.icon-mail {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M4 4h16c1.1 0 2 .9 2 2v12c0 1.1-.9 2-2 2H4c-1.1 0-2-.9-2-2V6c0-1.1.9-2 2-2z'%3E%3C/path%3E%3Cpolyline points='22,6 12,13 2,6'%3E%3C/polyline%3E%3C/svg%3E"); }
+span.icon-location {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M21 10c0 7-9 13-9 13s-9-6-9-13a9 9 0 0 1 18 0z'%3E%3C/path%3E%3Ccircle cx='12' cy='10' r='3'%3E%3C/circle%3E%3C/svg%3E"); }
+span.icon-phone {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M22 16.92v3a2 2 0 0 1-2.18 2 19.79 19.79 0 0 1-8.63-3.07 19.5 19.5 0 0 1-6-6 19.79 19.79 0 0 1-3.07-8.67A2 2 0 0 1 4.11 2h3a2 2 0 0 1 2 1.72 12.84 12.84 0 0 0 .7 2.81 2 2 0 0 1-.45 2.11L8.09 9.91a16 16 0 0 0 6 6l1.27-1.27a2 2 0 0 1 2.11-.45 12.84 12.84 0 0 0 2.81.7A2 2 0 0 1 22 16.92z'%3E%3C/path%3E%3C/svg%3E"); }
+span.icon-rss {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M4 11a9 9 0 0 1 9 9'%3E%3C/path%3E%3Cpath d='M4 4a16 16 0 0 1 16 16'%3E%3C/path%3E%3Ccircle cx='5' cy='19' r='1'%3E%3C/circle%3E%3C/svg%3E"); }
+span.icon-search {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='11' cy='11' r='8'%3E%3C/circle%3E%3Cline x1='21' y1='21' x2='16.65' y2='16.65'%3E%3C/line%3E%3C/svg%3E"); }
+span.icon-settings {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='3'%3E%3C/circle%3E%3Cpath d='M19.4 15a1.65 1.65 0 0 0 .33 1.82l.06.06a2 2 0 0 1 0 2.83 2 2 0 0 1-2.83 0l-.06-.06a1.65 1.65 0 0 0-1.82-.33 1.65 1.65 0 0 0-1 1.51V21a2 2 0 0 1-2 2 2 2 0 0 1-2-2v-.09A1.65 1.65 0 0 0 9 19.4a1.65 1.65 0 0 0-1.82.33l-.06.06a2 2 0 0 1-2.83 0 2 2 0 0 1 0-2.83l.06-.06a1.65 1.65 0 0 0 .33-1.82 1.65 1.65 0 0 0-1.51-1H3a2 2 0 0 1-2-2 2 2 0 0 1 2-2h.09A1.65 1.65 0 0 0 4.6 9a1.65 1.65 0 0 0-.33-1.82l-.06-.06a2 2 0 0 1 0-2.83 2 2 0 0 1 2.83 0l.06.06a1.65 1.65 0 0 0 1.82.33H9a1.65 1.65 0 0 0 1-1.51V3a2 2 0 0 1 2-2 2 2 0 0 1 2 2v.09a1.65 1.65 0 0 0 1 1.51 1.65 1.65 0 0 0 1.82-.33l.06-.06a2 2 0 0 1 2.83 0 2 2 0 0 1 0 2.83l-.06.06a1.65 1.65 0 0 0-.33 1.82V9a1.65 1.65 0 0 0 1.51 1H21a2 2 0 0 1 2 2 2 2 0 0 1-2 2h-.09a1.65 1.65 0 0 0-1.51 1z'%3E%3C/path%3E%3C/svg%3E"); }
+span.icon-share {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='18' cy='5' r='3'%3E%3C/circle%3E%3Ccircle cx='6' cy='12' r='3'%3E%3C/circle%3E%3Ccircle cx='18' cy='19' r='3'%3E%3C/circle%3E%3Cline x1='8.59' y1='13.51' x2='15.42' y2='17.49'%3E%3C/line%3E%3Cline x1='15.41' y1='6.51' x2='8.59' y2='10.49'%3E%3C/line%3E%3C/svg%3E"); }
+span.icon-cart {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='9' cy='21' r='1'%3E%3C/circle%3E%3Ccircle cx='20' cy='21' r='1'%3E%3C/circle%3E%3Cpath d='M1 1h4l2.68 13.39a2 2 0 0 0 2 1.61h9.72a2 2 0 0 0 2-1.61L23 6H6'%3E%3C/path%3E%3C/svg%3E"); }
+span.icon-upload {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M21 15v4a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2v-4'%3E%3C/path%3E%3Cpolyline points='17 8 12 3 7 8'%3E%3C/polyline%3E%3Cline x1='12' y1='3' x2='12' y2='15'%3E%3C/line%3E%3C/svg%3E"); }
+span.icon-user {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M20 21v-2a4 4 0 0 0-4-4H8a4 4 0 0 0-4 4v2'%3E%3C/path%3E%3Ccircle cx='12' cy='7' r='4'%3E%3C/circle%3E%3C/svg%3E"); }
+
+/*
+ Definitions for utilities and helper classes.
+*/
+/* Utility module CSS variable definitions */
+:root {
+ --generic-border-color: rgba(0, 0, 0, 0.3);
+ --generic-box-shadow: 0 0.25rem 0.25rem 0 rgba(0, 0, 0, 0.125), 0 0.125rem 0.125rem -0.125rem rgba(0, 0, 0, 0.25); }
+
+.hidden {
+ display: none !important; }
+
+.visually-hidden {
+ position: absolute !important;
+ width: 1px !important;
+ height: 1px !important;
+ margin: -1px !important;
+ border: 0 !important;
+ padding: 0 !important;
+ clip: rect(0 0 0 0) !important;
+ -webkit-clip-path: inset(100%) !important;
+ clip-path: inset(100%) !important;
+ overflow: hidden !important; }
+
+.bordered {
+ border: 0.0625rem solid var(--generic-border-color) !important; }
+
+.rounded {
+ border-radius: var(--universal-border-radius) !important; }
+
+.circular {
+ border-radius: 50% !important; }
+
+.shadowed {
+ box-shadow: var(--generic-box-shadow) !important; }
+
+.responsive-margin {
+ margin: calc(var(--universal-margin) / 4) !important; }
+ @media screen and (min-width: 500px) {
+ .responsive-margin {
+ margin: calc(var(--universal-margin) / 2) !important; } }
+ @media screen and (min-width: 1280px) {
+ .responsive-margin {
+ margin: var(--universal-margin) !important; } }
+
+.responsive-padding {
+ padding: calc(var(--universal-padding) / 4) !important; }
+ @media screen and (min-width: 500px) {
+ .responsive-padding {
+ padding: calc(var(--universal-padding) / 2) !important; } }
+ @media screen and (min-width: 1280px) {
+ .responsive-padding {
+ padding: var(--universal-padding) !important; } }
+
+@media screen and (max-width: 499px) {
+ .hidden-sm {
+ display: none !important; } }
+@media screen and (min-width: 500px) and (max-width: 1279px) {
+ .hidden-md {
+ display: none !important; } }
+@media screen and (min-width: 1280px) {
+ .hidden-lg {
+ display: none !important; } }
+@media screen and (max-width: 499px) {
+ .visually-hidden-sm {
+ position: absolute !important;
+ width: 1px !important;
+ height: 1px !important;
+ margin: -1px !important;
+ border: 0 !important;
+ padding: 0 !important;
+ clip: rect(0 0 0 0) !important;
+ -webkit-clip-path: inset(100%) !important;
+ clip-path: inset(100%) !important;
+ overflow: hidden !important; } }
+@media screen and (min-width: 500px) and (max-width: 1279px) {
+ .visually-hidden-md {
+ position: absolute !important;
+ width: 1px !important;
+ height: 1px !important;
+ margin: -1px !important;
+ border: 0 !important;
+ padding: 0 !important;
+ clip: rect(0 0 0 0) !important;
+ -webkit-clip-path: inset(100%) !important;
+ clip-path: inset(100%) !important;
+ overflow: hidden !important; } }
+@media screen and (min-width: 1280px) {
+ .visually-hidden-lg {
+ position: absolute !important;
+ width: 1px !important;
+ height: 1px !important;
+ margin: -1px !important;
+ border: 0 !important;
+ padding: 0 !important;
+ clip: rect(0 0 0 0) !important;
+ -webkit-clip-path: inset(100%) !important;
+ clip-path: inset(100%) !important;
+ overflow: hidden !important; } }
+
+/*# sourceMappingURL=mini-default.css.map */
diff --git a/system/Drivers/CMSIS/Device/ST/STM32C0xx/_htmresc/mini-st_2020.css b/system/Drivers/CMSIS/Device/ST/STM32C0xx/_htmresc/mini-st_2020.css
new file mode 100644
index 0000000000..db8b406aa4
--- /dev/null
+++ b/system/Drivers/CMSIS/Device/ST/STM32C0xx/_htmresc/mini-st_2020.css
@@ -0,0 +1,1711 @@
+@charset "UTF-8";
+/*
+ Flavor name: Custom (mini-custom)
+ Generated online - https://minicss.org/flavors
+ mini.css version: v3.0.1
+*/
+/*
+ Browsers resets and base typography.
+*/
+/* Core module CSS variable definitions */
+:root {
+ --fore-color: #03234b;
+ --secondary-fore-color: #03234b;
+ --back-color: #ffffff;
+ --secondary-back-color: #ffffff;
+ --blockquote-color: #e6007e;
+ --pre-color: #e6007e;
+ --border-color: #3cb4e6;
+ --secondary-border-color: #3cb4e6;
+ --heading-ratio: 1.2;
+ --universal-margin: 0.5rem;
+ --universal-padding: 0.25rem;
+ --universal-border-radius: 0.075rem;
+ --background-margin: 1.5%;
+ --a-link-color: #3cb4e6;
+ --a-visited-color: #8c0078; }
+
+html {
+ font-size: 13.5px; }
+
+a, b, del, em, i, ins, q, span, strong, u {
+ font-size: 1em; }
+
+html, * {
+ font-family: -apple-system, BlinkMacSystemFont, Helvetica, arial, sans-serif;
+ line-height: 1.25;
+ -webkit-text-size-adjust: 100%; }
+
+* {
+ font-size: 1rem; }
+
+body {
+ margin: 0;
+ color: var(--fore-color);
+ @background: var(--back-color);
+ background: var(--back-color) linear-gradient(#ffd200, #ffd200) repeat-y left top;
+ background-size: var(--background-margin);
+ }
+
+details {
+ display: block; }
+
+summary {
+ display: list-item; }
+
+abbr[title] {
+ border-bottom: none;
+ text-decoration: underline dotted; }
+
+input {
+ overflow: visible; }
+
+img {
+ max-width: 100%;
+ height: auto; }
+
+h1, h2, h3, h4, h5, h6 {
+ line-height: 1.25;
+ margin: calc(1.5 * var(--universal-margin)) var(--universal-margin);
+ font-weight: 400; }
+ h1 small, h2 small, h3 small, h4 small, h5 small, h6 small {
+ color: var(--secondary-fore-color);
+ display: block;
+ margin-top: -0.25rem; }
+
+h1 {
+ font-size: calc(1rem * var(--heading-ratio) * var(--heading-ratio) * var(--heading-ratio)); }
+
+h2 {
+ font-size: calc(1rem * var(--heading-ratio) * var(--heading-ratio) );
+ border-style: none none solid none ;
+ border-width: thin;
+ border-color: var(--border-color); }
+h3 {
+ font-size: calc(1rem * var(--heading-ratio) ); }
+
+h4 {
+ font-size: calc(1rem * var(--heading-ratio)); }
+
+h5 {
+ font-size: 1rem; }
+
+h6 {
+ font-size: calc(1rem / var(--heading-ratio)); }
+
+p {
+ margin: var(--universal-margin); }
+
+ol, ul {
+ margin: var(--universal-margin);
+ padding-left: calc(3 * var(--universal-margin)); }
+
+b, strong {
+ font-weight: 700; }
+
+hr {
+ box-sizing: content-box;
+ border: 0;
+ line-height: 1.25em;
+ margin: var(--universal-margin);
+ height: 0.0714285714rem;
+ background: linear-gradient(to right, transparent, var(--border-color) 20%, var(--border-color) 80%, transparent); }
+
+blockquote {
+ display: block;
+ position: relative;
+ font-style: italic;
+ color: var(--secondary-fore-color);
+ margin: var(--universal-margin);
+ padding: calc(3 * var(--universal-padding));
+ border: 0.0714285714rem solid var(--secondary-border-color);
+ border-left: 0.3rem solid var(--blockquote-color);
+ border-radius: 0 var(--universal-border-radius) var(--universal-border-radius) 0; }
+ blockquote:before {
+ position: absolute;
+ top: calc(0rem - var(--universal-padding));
+ left: 0;
+ font-family: sans-serif;
+ font-size: 2rem;
+ font-weight: 800;
+ content: "\201c";
+ color: var(--blockquote-color); }
+ blockquote[cite]:after {
+ font-style: normal;
+ font-size: 0.75em;
+ font-weight: 700;
+ content: "\a— " attr(cite);
+ white-space: pre; }
+
+code, kbd, pre, samp {
+ font-family: Menlo, Consolas, monospace;
+ font-size: 0.85em; }
+
+code {
+ background: var(--secondary-back-color);
+ border-radius: var(--universal-border-radius);
+ padding: calc(var(--universal-padding) / 4) calc(var(--universal-padding) / 2); }
+
+kbd {
+ background: var(--fore-color);
+ color: var(--back-color);
+ border-radius: var(--universal-border-radius);
+ padding: calc(var(--universal-padding) / 4) calc(var(--universal-padding) / 2); }
+
+pre {
+ overflow: auto;
+ background: var(--secondary-back-color);
+ padding: calc(1.5 * var(--universal-padding));
+ margin: var(--universal-margin);
+ border: 0.0714285714rem solid var(--secondary-border-color);
+ border-left: 0.2857142857rem solid var(--pre-color);
+ border-radius: 0 var(--universal-border-radius) var(--universal-border-radius) 0; }
+
+sup, sub, code, kbd {
+ line-height: 0;
+ position: relative;
+ vertical-align: baseline; }
+
+small, sup, sub, figcaption {
+ font-size: 0.75em; }
+
+sup {
+ top: -0.5em; }
+
+sub {
+ bottom: -0.25em; }
+
+figure {
+ margin: var(--universal-margin); }
+
+figcaption {
+ color: var(--secondary-fore-color); }
+
+a {
+ text-decoration: none; }
+ a:link {
+ color: var(--a-link-color); }
+ a:visited {
+ color: var(--a-visited-color); }
+ a:hover, a:focus {
+ text-decoration: underline; }
+
+/*
+ Definitions for the grid system, cards and containers.
+*/
+.container {
+ margin: 0 auto;
+ padding: 0 calc(1.5 * var(--universal-padding)); }
+
+.row {
+ box-sizing: border-box;
+ display: flex;
+ flex: 0 1 auto;
+ flex-flow: row wrap;
+ margin: 0 0 0 var(--background-margin); }
+
+.col-sm,
+[class^='col-sm-'],
+[class^='col-sm-offset-'],
+.row[class*='cols-sm-'] > * {
+ box-sizing: border-box;
+ flex: 0 0 auto;
+ padding: 0 calc(var(--universal-padding) / 2); }
+
+.col-sm,
+.row.cols-sm > * {
+ max-width: 100%;
+ flex-grow: 1;
+ flex-basis: 0; }
+
+.col-sm-1,
+.row.cols-sm-1 > * {
+ max-width: 8.3333333333%;
+ flex-basis: 8.3333333333%; }
+
+.col-sm-offset-0 {
+ margin-left: 0; }
+
+.col-sm-2,
+.row.cols-sm-2 > * {
+ max-width: 16.6666666667%;
+ flex-basis: 16.6666666667%; }
+
+.col-sm-offset-1 {
+ margin-left: 8.3333333333%; }
+
+.col-sm-3,
+.row.cols-sm-3 > * {
+ max-width: 25%;
+ flex-basis: 25%; }
+
+.col-sm-offset-2 {
+ margin-left: 16.6666666667%; }
+
+.col-sm-4,
+.row.cols-sm-4 > * {
+ max-width: 33.3333333333%;
+ flex-basis: 33.3333333333%; }
+
+.col-sm-offset-3 {
+ margin-left: 25%; }
+
+.col-sm-5,
+.row.cols-sm-5 > * {
+ max-width: 41.6666666667%;
+ flex-basis: 41.6666666667%; }
+
+.col-sm-offset-4 {
+ margin-left: 33.3333333333%; }
+
+.col-sm-6,
+.row.cols-sm-6 > * {
+ max-width: 50%;
+ flex-basis: 50%; }
+
+.col-sm-offset-5 {
+ margin-left: 41.6666666667%; }
+
+.col-sm-7,
+.row.cols-sm-7 > * {
+ max-width: 58.3333333333%;
+ flex-basis: 58.3333333333%; }
+
+.col-sm-offset-6 {
+ margin-left: 50%; }
+
+.col-sm-8,
+.row.cols-sm-8 > * {
+ max-width: 66.6666666667%;
+ flex-basis: 66.6666666667%; }
+
+.col-sm-offset-7 {
+ margin-left: 58.3333333333%; }
+
+.col-sm-9,
+.row.cols-sm-9 > * {
+ max-width: 75%;
+ flex-basis: 75%; }
+
+.col-sm-offset-8 {
+ margin-left: 66.6666666667%; }
+
+.col-sm-10,
+.row.cols-sm-10 > * {
+ max-width: 83.3333333333%;
+ flex-basis: 83.3333333333%; }
+
+.col-sm-offset-9 {
+ margin-left: 75%; }
+
+.col-sm-11,
+.row.cols-sm-11 > * {
+ max-width: 91.6666666667%;
+ flex-basis: 91.6666666667%; }
+
+.col-sm-offset-10 {
+ margin-left: 83.3333333333%; }
+
+.col-sm-12,
+.row.cols-sm-12 > * {
+ max-width: 100%;
+ flex-basis: 100%; }
+
+.col-sm-offset-11 {
+ margin-left: 91.6666666667%; }
+
+.col-sm-normal {
+ order: initial; }
+
+.col-sm-first {
+ order: -999; }
+
+.col-sm-last {
+ order: 999; }
+
+@media screen and (min-width: 500px) {
+ .col-md,
+ [class^='col-md-'],
+ [class^='col-md-offset-'],
+ .row[class*='cols-md-'] > * {
+ box-sizing: border-box;
+ flex: 0 0 auto;
+ padding: 0 calc(var(--universal-padding) / 2); }
+
+ .col-md,
+ .row.cols-md > * {
+ max-width: 100%;
+ flex-grow: 1;
+ flex-basis: 0; }
+
+ .col-md-1,
+ .row.cols-md-1 > * {
+ max-width: 8.3333333333%;
+ flex-basis: 8.3333333333%; }
+
+ .col-md-offset-0 {
+ margin-left: 0; }
+
+ .col-md-2,
+ .row.cols-md-2 > * {
+ max-width: 16.6666666667%;
+ flex-basis: 16.6666666667%; }
+
+ .col-md-offset-1 {
+ margin-left: 8.3333333333%; }
+
+ .col-md-3,
+ .row.cols-md-3 > * {
+ max-width: 25%;
+ flex-basis: 25%; }
+
+ .col-md-offset-2 {
+ margin-left: 16.6666666667%; }
+
+ .col-md-4,
+ .row.cols-md-4 > * {
+ max-width: 33.3333333333%;
+ flex-basis: 33.3333333333%; }
+
+ .col-md-offset-3 {
+ margin-left: 25%; }
+
+ .col-md-5,
+ .row.cols-md-5 > * {
+ max-width: 41.6666666667%;
+ flex-basis: 41.6666666667%; }
+
+ .col-md-offset-4 {
+ margin-left: 33.3333333333%; }
+
+ .col-md-6,
+ .row.cols-md-6 > * {
+ max-width: 50%;
+ flex-basis: 50%; }
+
+ .col-md-offset-5 {
+ margin-left: 41.6666666667%; }
+
+ .col-md-7,
+ .row.cols-md-7 > * {
+ max-width: 58.3333333333%;
+ flex-basis: 58.3333333333%; }
+
+ .col-md-offset-6 {
+ margin-left: 50%; }
+
+ .col-md-8,
+ .row.cols-md-8 > * {
+ max-width: 66.6666666667%;
+ flex-basis: 66.6666666667%; }
+
+ .col-md-offset-7 {
+ margin-left: 58.3333333333%; }
+
+ .col-md-9,
+ .row.cols-md-9 > * {
+ max-width: 75%;
+ flex-basis: 75%; }
+
+ .col-md-offset-8 {
+ margin-left: 66.6666666667%; }
+
+ .col-md-10,
+ .row.cols-md-10 > * {
+ max-width: 83.3333333333%;
+ flex-basis: 83.3333333333%; }
+
+ .col-md-offset-9 {
+ margin-left: 75%; }
+
+ .col-md-11,
+ .row.cols-md-11 > * {
+ max-width: 91.6666666667%;
+ flex-basis: 91.6666666667%; }
+
+ .col-md-offset-10 {
+ margin-left: 83.3333333333%; }
+
+ .col-md-12,
+ .row.cols-md-12 > * {
+ max-width: 100%;
+ flex-basis: 100%; }
+
+ .col-md-offset-11 {
+ margin-left: 91.6666666667%; }
+
+ .col-md-normal {
+ order: initial; }
+
+ .col-md-first {
+ order: -999; }
+
+ .col-md-last {
+ order: 999; } }
+@media screen and (min-width: 1280px) {
+ .col-lg,
+ [class^='col-lg-'],
+ [class^='col-lg-offset-'],
+ .row[class*='cols-lg-'] > * {
+ box-sizing: border-box;
+ flex: 0 0 auto;
+ padding: 0 calc(var(--universal-padding) / 2); }
+
+ .col-lg,
+ .row.cols-lg > * {
+ max-width: 100%;
+ flex-grow: 1;
+ flex-basis: 0; }
+
+ .col-lg-1,
+ .row.cols-lg-1 > * {
+ max-width: 8.3333333333%;
+ flex-basis: 8.3333333333%; }
+
+ .col-lg-offset-0 {
+ margin-left: 0; }
+
+ .col-lg-2,
+ .row.cols-lg-2 > * {
+ max-width: 16.6666666667%;
+ flex-basis: 16.6666666667%; }
+
+ .col-lg-offset-1 {
+ margin-left: 8.3333333333%; }
+
+ .col-lg-3,
+ .row.cols-lg-3 > * {
+ max-width: 25%;
+ flex-basis: 25%; }
+
+ .col-lg-offset-2 {
+ margin-left: 16.6666666667%; }
+
+ .col-lg-4,
+ .row.cols-lg-4 > * {
+ max-width: 33.3333333333%;
+ flex-basis: 33.3333333333%; }
+
+ .col-lg-offset-3 {
+ margin-left: 25%; }
+
+ .col-lg-5,
+ .row.cols-lg-5 > * {
+ max-width: 41.6666666667%;
+ flex-basis: 41.6666666667%; }
+
+ .col-lg-offset-4 {
+ margin-left: 33.3333333333%; }
+
+ .col-lg-6,
+ .row.cols-lg-6 > * {
+ max-width: 50%;
+ flex-basis: 50%; }
+
+ .col-lg-offset-5 {
+ margin-left: 41.6666666667%; }
+
+ .col-lg-7,
+ .row.cols-lg-7 > * {
+ max-width: 58.3333333333%;
+ flex-basis: 58.3333333333%; }
+
+ .col-lg-offset-6 {
+ margin-left: 50%; }
+
+ .col-lg-8,
+ .row.cols-lg-8 > * {
+ max-width: 66.6666666667%;
+ flex-basis: 66.6666666667%; }
+
+ .col-lg-offset-7 {
+ margin-left: 58.3333333333%; }
+
+ .col-lg-9,
+ .row.cols-lg-9 > * {
+ max-width: 75%;
+ flex-basis: 75%; }
+
+ .col-lg-offset-8 {
+ margin-left: 66.6666666667%; }
+
+ .col-lg-10,
+ .row.cols-lg-10 > * {
+ max-width: 83.3333333333%;
+ flex-basis: 83.3333333333%; }
+
+ .col-lg-offset-9 {
+ margin-left: 75%; }
+
+ .col-lg-11,
+ .row.cols-lg-11 > * {
+ max-width: 91.6666666667%;
+ flex-basis: 91.6666666667%; }
+
+ .col-lg-offset-10 {
+ margin-left: 83.3333333333%; }
+
+ .col-lg-12,
+ .row.cols-lg-12 > * {
+ max-width: 100%;
+ flex-basis: 100%; }
+
+ .col-lg-offset-11 {
+ margin-left: 91.6666666667%; }
+
+ .col-lg-normal {
+ order: initial; }
+
+ .col-lg-first {
+ order: -999; }
+
+ .col-lg-last {
+ order: 999; } }
+/* Card component CSS variable definitions */
+:root {
+ --card-back-color: #3cb4e6;
+ --card-fore-color: #03234b;
+ --card-border-color: #03234b; }
+
+.card {
+ display: flex;
+ flex-direction: column;
+ justify-content: space-between;
+ align-self: center;
+ position: relative;
+ width: 100%;
+ background: var(--card-back-color);
+ color: var(--card-fore-color);
+ border: 0.0714285714rem solid var(--card-border-color);
+ border-radius: var(--universal-border-radius);
+ margin: var(--universal-margin);
+ overflow: hidden; }
+ @media screen and (min-width: 320px) {
+ .card {
+ max-width: 320px; } }
+ .card > .sectione {
+ background: var(--card-back-color);
+ color: var(--card-fore-color);
+ box-sizing: border-box;
+ margin: 0;
+ border: 0;
+ border-radius: 0;
+ border-bottom: 0.0714285714rem solid var(--card-border-color);
+ padding: var(--universal-padding);
+ width: 100%; }
+ .card > .sectione.media {
+ height: 200px;
+ padding: 0;
+ -o-object-fit: cover;
+ object-fit: cover; }
+ .card > .sectione:last-child {
+ border-bottom: 0; }
+
+/*
+ Custom elements for card elements.
+*/
+@media screen and (min-width: 240px) {
+ .card.small {
+ max-width: 240px; } }
+@media screen and (min-width: 480px) {
+ .card.large {
+ max-width: 480px; } }
+.card.fluid {
+ max-width: 100%;
+ width: auto; }
+
+.card.warning {
+ --card-back-color: #e5b8b7;
+ --card-fore-color: #3b234b;
+ --card-border-color: #8c0078; }
+
+.card.error {
+ --card-back-color: #464650;
+ --card-fore-color: #ffffff;
+ --card-border-color: #8c0078; }
+
+.card > .sectione.dark {
+ --card-back-color: #3b234b;
+ --card-fore-color: #ffffff; }
+
+.card > .sectione.double-padded {
+ padding: calc(1.5 * var(--universal-padding)); }
+
+/*
+ Definitions for forms and input elements.
+*/
+/* Input_control module CSS variable definitions */
+:root {
+ --form-back-color: #ffe97f;
+ --form-fore-color: #03234b;
+ --form-border-color: #3cb4e6;
+ --input-back-color: #ffffff;
+ --input-fore-color: #03234b;
+ --input-border-color: #3cb4e6;
+ --input-focus-color: #0288d1;
+ --input-invalid-color: #d32f2f;
+ --button-back-color: #e2e2e2;
+ --button-hover-back-color: #dcdcdc;
+ --button-fore-color: #212121;
+ --button-border-color: transparent;
+ --button-hover-border-color: transparent;
+ --button-group-border-color: rgba(124, 124, 124, 0.54); }
+
+form {
+ background: var(--form-back-color);
+ color: var(--form-fore-color);
+ border: 0.0714285714rem solid var(--form-border-color);
+ border-radius: var(--universal-border-radius);
+ margin: var(--universal-margin);
+ padding: calc(2 * var(--universal-padding)) var(--universal-padding); }
+
+fieldset {
+ border: 0.0714285714rem solid var(--form-border-color);
+ border-radius: var(--universal-border-radius);
+ margin: calc(var(--universal-margin) / 4);
+ padding: var(--universal-padding); }
+
+legend {
+ box-sizing: border-box;
+ display: table;
+ max-width: 100%;
+ white-space: normal;
+ font-weight: 500;
+ padding: calc(var(--universal-padding) / 2); }
+
+label {
+ padding: calc(var(--universal-padding) / 2) var(--universal-padding); }
+
+.input-group {
+ display: inline-block; }
+ .input-group.fluid {
+ display: flex;
+ align-items: center;
+ justify-content: center; }
+ .input-group.fluid > input {
+ max-width: 100%;
+ flex-grow: 1;
+ flex-basis: 0px; }
+ @media screen and (max-width: 499px) {
+ .input-group.fluid {
+ align-items: stretch;
+ flex-direction: column; } }
+ .input-group.vertical {
+ display: flex;
+ align-items: stretch;
+ flex-direction: column; }
+ .input-group.vertical > input {
+ max-width: 100%;
+ flex-grow: 1;
+ flex-basis: 0px; }
+
+[type="number"]::-webkit-inner-spin-button, [type="number"]::-webkit-outer-spin-button {
+ height: auto; }
+
+[type="search"] {
+ -webkit-appearance: textfield;
+ outline-offset: -2px; }
+
+[type="search"]::-webkit-search-cancel-button,
+[type="search"]::-webkit-search-decoration {
+ -webkit-appearance: none; }
+
+input:not([type]), [type="text"], [type="email"], [type="number"], [type="search"],
+[type="password"], [type="url"], [type="tel"], [type="checkbox"], [type="radio"], textarea, select {
+ box-sizing: border-box;
+ background: var(--input-back-color);
+ color: var(--input-fore-color);
+ border: 0.0714285714rem solid var(--input-border-color);
+ border-radius: var(--universal-border-radius);
+ margin: calc(var(--universal-margin) / 2);
+ padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); }
+
+input:not([type="button"]):not([type="submit"]):not([type="reset"]):hover, input:not([type="button"]):not([type="submit"]):not([type="reset"]):focus, textarea:hover, textarea:focus, select:hover, select:focus {
+ border-color: var(--input-focus-color);
+ box-shadow: none; }
+input:not([type="button"]):not([type="submit"]):not([type="reset"]):invalid, input:not([type="button"]):not([type="submit"]):not([type="reset"]):focus:invalid, textarea:invalid, textarea:focus:invalid, select:invalid, select:focus:invalid {
+ border-color: var(--input-invalid-color);
+ box-shadow: none; }
+input:not([type="button"]):not([type="submit"]):not([type="reset"])[readonly], textarea[readonly], select[readonly] {
+ background: var(--secondary-back-color); }
+
+select {
+ max-width: 100%; }
+
+option {
+ overflow: hidden;
+ text-overflow: ellipsis; }
+
+[type="checkbox"], [type="radio"] {
+ -webkit-appearance: none;
+ -moz-appearance: none;
+ appearance: none;
+ position: relative;
+ height: calc(1rem + var(--universal-padding) / 2);
+ width: calc(1rem + var(--universal-padding) / 2);
+ vertical-align: text-bottom;
+ padding: 0;
+ flex-basis: calc(1rem + var(--universal-padding) / 2) !important;
+ flex-grow: 0 !important; }
+ [type="checkbox"]:checked:before, [type="radio"]:checked:before {
+ position: absolute; }
+
+[type="checkbox"]:checked:before {
+ content: '\2713';
+ font-family: sans-serif;
+ font-size: calc(1rem + var(--universal-padding) / 2);
+ top: calc(0rem - var(--universal-padding));
+ left: calc(var(--universal-padding) / 4); }
+
+[type="radio"] {
+ border-radius: 100%; }
+ [type="radio"]:checked:before {
+ border-radius: 100%;
+ content: '';
+ top: calc(0.0714285714rem + var(--universal-padding) / 2);
+ left: calc(0.0714285714rem + var(--universal-padding) / 2);
+ background: var(--input-fore-color);
+ width: 0.5rem;
+ height: 0.5rem; }
+
+:placeholder-shown {
+ color: var(--input-fore-color); }
+
+::-ms-placeholder {
+ color: var(--input-fore-color);
+ opacity: 0.54; }
+
+button::-moz-focus-inner, [type="button"]::-moz-focus-inner, [type="reset"]::-moz-focus-inner, [type="submit"]::-moz-focus-inner {
+ border-style: none;
+ padding: 0; }
+
+button, html [type="button"], [type="reset"], [type="submit"] {
+ -webkit-appearance: button; }
+
+button {
+ overflow: visible;
+ text-transform: none; }
+
+button, [type="button"], [type="submit"], [type="reset"],
+a.button, label.button, .button,
+a[role="button"], label[role="button"], [role="button"] {
+ display: inline-block;
+ background: var(--button-back-color);
+ color: var(--button-fore-color);
+ border: 0.0714285714rem solid var(--button-border-color);
+ border-radius: var(--universal-border-radius);
+ padding: var(--universal-padding) calc(1.5 * var(--universal-padding));
+ margin: var(--universal-margin);
+ text-decoration: none;
+ cursor: pointer;
+ transition: background 0.3s; }
+ button:hover, button:focus, [type="button"]:hover, [type="button"]:focus, [type="submit"]:hover, [type="submit"]:focus, [type="reset"]:hover, [type="reset"]:focus,
+ a.button:hover,
+ a.button:focus, label.button:hover, label.button:focus, .button:hover, .button:focus,
+ a[role="button"]:hover,
+ a[role="button"]:focus, label[role="button"]:hover, label[role="button"]:focus, [role="button"]:hover, [role="button"]:focus {
+ background: var(--button-hover-back-color);
+ border-color: var(--button-hover-border-color); }
+
+input:disabled, input[disabled], textarea:disabled, textarea[disabled], select:disabled, select[disabled], button:disabled, button[disabled], .button:disabled, .button[disabled], [role="button"]:disabled, [role="button"][disabled] {
+ cursor: not-allowed;
+ opacity: 0.75; }
+
+.button-group {
+ display: flex;
+ border: 0.0714285714rem solid var(--button-group-border-color);
+ border-radius: var(--universal-border-radius);
+ margin: var(--universal-margin); }
+ .button-group > button, .button-group [type="button"], .button-group > [type="submit"], .button-group > [type="reset"], .button-group > .button, .button-group > [role="button"] {
+ margin: 0;
+ max-width: 100%;
+ flex: 1 1 auto;
+ text-align: center;
+ border: 0;
+ border-radius: 0;
+ box-shadow: none; }
+ .button-group > :not(:first-child) {
+ border-left: 0.0714285714rem solid var(--button-group-border-color); }
+ @media screen and (max-width: 499px) {
+ .button-group {
+ flex-direction: column; }
+ .button-group > :not(:first-child) {
+ border: 0;
+ border-top: 0.0714285714rem solid var(--button-group-border-color); } }
+
+/*
+ Custom elements for forms and input elements.
+*/
+button.primary, [type="button"].primary, [type="submit"].primary, [type="reset"].primary, .button.primary, [role="button"].primary {
+ --button-back-color: #1976d2;
+ --button-fore-color: #f8f8f8; }
+ button.primary:hover, button.primary:focus, [type="button"].primary:hover, [type="button"].primary:focus, [type="submit"].primary:hover, [type="submit"].primary:focus, [type="reset"].primary:hover, [type="reset"].primary:focus, .button.primary:hover, .button.primary:focus, [role="button"].primary:hover, [role="button"].primary:focus {
+ --button-hover-back-color: #1565c0; }
+
+button.secondary, [type="button"].secondary, [type="submit"].secondary, [type="reset"].secondary, .button.secondary, [role="button"].secondary {
+ --button-back-color: #d32f2f;
+ --button-fore-color: #f8f8f8; }
+ button.secondary:hover, button.secondary:focus, [type="button"].secondary:hover, [type="button"].secondary:focus, [type="submit"].secondary:hover, [type="submit"].secondary:focus, [type="reset"].secondary:hover, [type="reset"].secondary:focus, .button.secondary:hover, .button.secondary:focus, [role="button"].secondary:hover, [role="button"].secondary:focus {
+ --button-hover-back-color: #c62828; }
+
+button.tertiary, [type="button"].tertiary, [type="submit"].tertiary, [type="reset"].tertiary, .button.tertiary, [role="button"].tertiary {
+ --button-back-color: #308732;
+ --button-fore-color: #f8f8f8; }
+ button.tertiary:hover, button.tertiary:focus, [type="button"].tertiary:hover, [type="button"].tertiary:focus, [type="submit"].tertiary:hover, [type="submit"].tertiary:focus, [type="reset"].tertiary:hover, [type="reset"].tertiary:focus, .button.tertiary:hover, .button.tertiary:focus, [role="button"].tertiary:hover, [role="button"].tertiary:focus {
+ --button-hover-back-color: #277529; }
+
+button.inverse, [type="button"].inverse, [type="submit"].inverse, [type="reset"].inverse, .button.inverse, [role="button"].inverse {
+ --button-back-color: #212121;
+ --button-fore-color: #f8f8f8; }
+ button.inverse:hover, button.inverse:focus, [type="button"].inverse:hover, [type="button"].inverse:focus, [type="submit"].inverse:hover, [type="submit"].inverse:focus, [type="reset"].inverse:hover, [type="reset"].inverse:focus, .button.inverse:hover, .button.inverse:focus, [role="button"].inverse:hover, [role="button"].inverse:focus {
+ --button-hover-back-color: #111; }
+
+button.small, [type="button"].small, [type="submit"].small, [type="reset"].small, .button.small, [role="button"].small {
+ padding: calc(0.5 * var(--universal-padding)) calc(0.75 * var(--universal-padding));
+ margin: var(--universal-margin); }
+
+button.large, [type="button"].large, [type="submit"].large, [type="reset"].large, .button.large, [role="button"].large {
+ padding: calc(1.5 * var(--universal-padding)) calc(2 * var(--universal-padding));
+ margin: var(--universal-margin); }
+
+/*
+ Definitions for navigation elements.
+*/
+/* Navigation module CSS variable definitions */
+:root {
+ --header-back-color: #03234b;
+ --header-hover-back-color: #ffd200;
+ --header-fore-color: #ffffff;
+ --header-border-color: #3cb4e6;
+ --nav-back-color: #ffffff;
+ --nav-hover-back-color: #ffe97f;
+ --nav-fore-color: #e6007e;
+ --nav-border-color: #3cb4e6;
+ --nav-link-color: #3cb4e6;
+ --footer-fore-color: #ffffff;
+ --footer-back-color: #03234b;
+ --footer-border-color: #3cb4e6;
+ --footer-link-color: #3cb4e6;
+ --drawer-back-color: #ffffff;
+ --drawer-hover-back-color: #ffe97f;
+ --drawer-border-color: #3cb4e6;
+ --drawer-close-color: #e6007e; }
+
+header {
+ height: 2.75rem;
+ background: var(--header-back-color);
+ color: var(--header-fore-color);
+ border-bottom: 0.0714285714rem solid var(--header-border-color);
+ padding: calc(var(--universal-padding) / 4) 0;
+ white-space: nowrap;
+ overflow-x: auto;
+ overflow-y: hidden; }
+ header.row {
+ box-sizing: content-box; }
+ header .logo {
+ color: var(--header-fore-color);
+ font-size: 1.75rem;
+ padding: var(--universal-padding) calc(2 * var(--universal-padding));
+ text-decoration: none; }
+ header button, header [type="button"], header .button, header [role="button"] {
+ box-sizing: border-box;
+ position: relative;
+ top: calc(0rem - var(--universal-padding) / 4);
+ height: calc(3.1875rem + var(--universal-padding) / 2);
+ background: var(--header-back-color);
+ line-height: calc(3.1875rem - var(--universal-padding) * 1.5);
+ text-align: center;
+ color: var(--header-fore-color);
+ border: 0;
+ border-radius: 0;
+ margin: 0;
+ text-transform: uppercase; }
+ header button:hover, header button:focus, header [type="button"]:hover, header [type="button"]:focus, header .button:hover, header .button:focus, header [role="button"]:hover, header [role="button"]:focus {
+ background: var(--header-hover-back-color); }
+
+nav {
+ background: var(--nav-back-color);
+ color: var(--nav-fore-color);
+ border: 0.0714285714rem solid var(--nav-border-color);
+ border-radius: var(--universal-border-radius);
+ margin: var(--universal-margin); }
+ nav * {
+ padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); }
+ nav a, nav a:visited {
+ display: block;
+ color: var(--nav-link-color);
+ border-radius: var(--universal-border-radius);
+ transition: background 0.3s; }
+ nav a:hover, nav a:focus, nav a:visited:hover, nav a:visited:focus {
+ text-decoration: none;
+ background: var(--nav-hover-back-color); }
+ nav .sublink-1 {
+ position: relative;
+ margin-left: calc(2 * var(--universal-padding)); }
+ nav .sublink-1:before {
+ position: absolute;
+ left: calc(var(--universal-padding) - 1 * var(--universal-padding));
+ top: -0.0714285714rem;
+ content: '';
+ height: 100%;
+ border: 0.0714285714rem solid var(--nav-border-color);
+ border-left: 0; }
+ nav .sublink-2 {
+ position: relative;
+ margin-left: calc(4 * var(--universal-padding)); }
+ nav .sublink-2:before {
+ position: absolute;
+ left: calc(var(--universal-padding) - 3 * var(--universal-padding));
+ top: -0.0714285714rem;
+ content: '';
+ height: 100%;
+ border: 0.0714285714rem solid var(--nav-border-color);
+ border-left: 0; }
+
+footer {
+ background: var(--footer-back-color);
+ color: var(--footer-fore-color);
+ border-top: 0.0714285714rem solid var(--footer-border-color);
+ padding: calc(2 * var(--universal-padding)) var(--universal-padding);
+ font-size: 0.875rem; }
+ footer a, footer a:visited {
+ color: var(--footer-link-color); }
+
+header.sticky {
+ position: -webkit-sticky;
+ position: sticky;
+ z-index: 1101;
+ top: 0; }
+
+footer.sticky {
+ position: -webkit-sticky;
+ position: sticky;
+ z-index: 1101;
+ bottom: 0; }
+
+.drawer-toggle:before {
+ display: inline-block;
+ position: relative;
+ vertical-align: bottom;
+ content: '\00a0\2261\00a0';
+ font-family: sans-serif;
+ font-size: 1.5em; }
+@media screen and (min-width: 500px) {
+ .drawer-toggle:not(.persistent) {
+ display: none; } }
+
+[type="checkbox"].drawer {
+ height: 1px;
+ width: 1px;
+ margin: -1px;
+ overflow: hidden;
+ position: absolute;
+ clip: rect(0 0 0 0);
+ -webkit-clip-path: inset(100%);
+ clip-path: inset(100%); }
+ [type="checkbox"].drawer + * {
+ display: block;
+ box-sizing: border-box;
+ position: fixed;
+ top: 0;
+ width: 320px;
+ height: 100vh;
+ overflow-y: auto;
+ background: var(--drawer-back-color);
+ border: 0.0714285714rem solid var(--drawer-border-color);
+ border-radius: 0;
+ margin: 0;
+ z-index: 1110;
+ right: -320px;
+ transition: right 0.3s; }
+ [type="checkbox"].drawer + * .drawer-close {
+ position: absolute;
+ top: var(--universal-margin);
+ right: var(--universal-margin);
+ z-index: 1111;
+ width: 2rem;
+ height: 2rem;
+ border-radius: var(--universal-border-radius);
+ padding: var(--universal-padding);
+ margin: 0;
+ cursor: pointer;
+ transition: background 0.3s; }
+ [type="checkbox"].drawer + * .drawer-close:before {
+ display: block;
+ content: '\00D7';
+ color: var(--drawer-close-color);
+ position: relative;
+ font-family: sans-serif;
+ font-size: 2rem;
+ line-height: 1;
+ text-align: center; }
+ [type="checkbox"].drawer + * .drawer-close:hover, [type="checkbox"].drawer + * .drawer-close:focus {
+ background: var(--drawer-hover-back-color); }
+ @media screen and (max-width: 320px) {
+ [type="checkbox"].drawer + * {
+ width: 100%; } }
+ [type="checkbox"].drawer:checked + * {
+ right: 0; }
+ @media screen and (min-width: 500px) {
+ [type="checkbox"].drawer:not(.persistent) + * {
+ position: static;
+ height: 100%;
+ z-index: 1100; }
+ [type="checkbox"].drawer:not(.persistent) + * .drawer-close {
+ display: none; } }
+
+/*
+ Definitions for the responsive table component.
+*/
+/* Table module CSS variable definitions. */
+:root {
+ --table-border-color: #03234b;
+ --table-border-separator-color: #03234b;
+ --table-head-back-color: #03234b;
+ --table-head-fore-color: #ffffff;
+ --table-body-back-color: #ffffff;
+ --table-body-fore-color: #03234b;
+ --table-body-alt-back-color: #f4f4f4; }
+
+table {
+ border-collapse: separate;
+ border-spacing: 0;
+ margin: 0;
+ display: flex;
+ flex: 0 1 auto;
+ flex-flow: row wrap;
+ padding: var(--universal-padding);
+ padding-top: 0; }
+ table caption {
+ font-size: 1rem;
+ margin: calc(2 * var(--universal-margin)) 0;
+ max-width: 100%;
+ flex: 0 0 100%; }
+ table thead, table tbody {
+ display: flex;
+ flex-flow: row wrap;
+ border: 0.0714285714rem solid var(--table-border-color); }
+ table thead {
+ z-index: 999;
+ border-radius: var(--universal-border-radius) var(--universal-border-radius) 0 0;
+ border-bottom: 0.0714285714rem solid var(--table-border-separator-color); }
+ table tbody {
+ border-top: 0;
+ margin-top: calc(0 - var(--universal-margin));
+ border-radius: 0 0 var(--universal-border-radius) var(--universal-border-radius); }
+ table tr {
+ display: flex;
+ padding: 0; }
+ table th, table td {
+ padding: calc(0.5 * var(--universal-padding));
+ font-size: 0.9rem; }
+ table th {
+ text-align: left;
+ background: var(--table-head-back-color);
+ color: var(--table-head-fore-color); }
+ table td {
+ background: var(--table-body-back-color);
+ color: var(--table-body-fore-color);
+ border-top: 0.0714285714rem solid var(--table-border-color); }
+
+table:not(.horizontal) {
+ overflow: auto;
+ max-height: 100%; }
+ table:not(.horizontal) thead, table:not(.horizontal) tbody {
+ max-width: 100%;
+ flex: 0 0 100%; }
+ table:not(.horizontal) tr {
+ flex-flow: row wrap;
+ flex: 0 0 100%; }
+ table:not(.horizontal) th, table:not(.horizontal) td {
+ flex: 1 0 0%;
+ overflow: hidden;
+ text-overflow: ellipsis; }
+ table:not(.horizontal) thead {
+ position: sticky;
+ top: 0; }
+ table:not(.horizontal) tbody tr:first-child td {
+ border-top: 0; }
+
+table.horizontal {
+ border: 0; }
+ table.horizontal thead, table.horizontal tbody {
+ border: 0;
+ flex: .2 0 0;
+ flex-flow: row nowrap; }
+ table.horizontal tbody {
+ overflow: auto;
+ justify-content: space-between;
+ flex: .8 0 0;
+ margin-left: 0;
+ padding-bottom: calc(var(--universal-padding) / 4); }
+ table.horizontal tr {
+ flex-direction: column;
+ flex: 1 0 auto; }
+ table.horizontal th, table.horizontal td {
+ width: auto;
+ border: 0;
+ border-bottom: 0.0714285714rem solid var(--table-border-color); }
+ table.horizontal th:not(:first-child), table.horizontal td:not(:first-child) {
+ border-top: 0; }
+ table.horizontal th {
+ text-align: right;
+ border-left: 0.0714285714rem solid var(--table-border-color);
+ border-right: 0.0714285714rem solid var(--table-border-separator-color); }
+ table.horizontal thead tr:first-child {
+ padding-left: 0; }
+ table.horizontal th:first-child, table.horizontal td:first-child {
+ border-top: 0.0714285714rem solid var(--table-border-color); }
+ table.horizontal tbody tr:last-child td {
+ border-right: 0.0714285714rem solid var(--table-border-color); }
+ table.horizontal tbody tr:last-child td:first-child {
+ border-top-right-radius: 0.25rem; }
+ table.horizontal tbody tr:last-child td:last-child {
+ border-bottom-right-radius: 0.25rem; }
+ table.horizontal thead tr:first-child th:first-child {
+ border-top-left-radius: 0.25rem; }
+ table.horizontal thead tr:first-child th:last-child {
+ border-bottom-left-radius: 0.25rem; }
+
+@media screen and (max-width: 499px) {
+ table, table.horizontal {
+ border-collapse: collapse;
+ border: 0;
+ width: 100%;
+ display: table; }
+ table thead, table th, table.horizontal thead, table.horizontal th {
+ border: 0;
+ height: 1px;
+ width: 1px;
+ margin: -1px;
+ overflow: hidden;
+ padding: 0;
+ position: absolute;
+ clip: rect(0 0 0 0);
+ -webkit-clip-path: inset(100%);
+ clip-path: inset(100%); }
+ table tbody, table.horizontal tbody {
+ border: 0;
+ display: table-row-group; }
+ table tr, table.horizontal tr {
+ display: block;
+ border: 0.0714285714rem solid var(--table-border-color);
+ border-radius: var(--universal-border-radius);
+ background: #ffffff;
+ padding: var(--universal-padding);
+ margin: var(--universal-margin);
+ margin-bottom: calc(1 * var(--universal-margin)); }
+ table th, table td, table.horizontal th, table.horizontal td {
+ width: auto; }
+ table td, table.horizontal td {
+ display: block;
+ border: 0;
+ text-align: right; }
+ table td:before, table.horizontal td:before {
+ content: attr(data-label);
+ float: left;
+ font-weight: 600; }
+ table th:first-child, table td:first-child, table.horizontal th:first-child, table.horizontal td:first-child {
+ border-top: 0; }
+ table tbody tr:last-child td, table.horizontal tbody tr:last-child td {
+ border-right: 0; } }
+table tr:nth-of-type(2n) > td {
+ background: var(--table-body-alt-back-color); }
+
+@media screen and (max-width: 500px) {
+ table tr:nth-of-type(2n) {
+ background: var(--table-body-alt-back-color); } }
+:root {
+ --table-body-hover-back-color: #90caf9; }
+
+table.hoverable tr:hover, table.hoverable tr:hover > td, table.hoverable tr:focus, table.hoverable tr:focus > td {
+ background: var(--table-body-hover-back-color); }
+
+@media screen and (max-width: 500px) {
+ table.hoverable tr:hover, table.hoverable tr:hover > td, table.hoverable tr:focus, table.hoverable tr:focus > td {
+ background: var(--table-body-hover-back-color); } }
+/*
+ Definitions for contextual background elements, toasts and tooltips.
+*/
+/* Contextual module CSS variable definitions */
+:root {
+ --mark-back-color: #3cb4e6;
+ --mark-fore-color: #ffffff; }
+
+mark {
+ background: var(--mark-back-color);
+ color: var(--mark-fore-color);
+ font-size: 0.95em;
+ line-height: 1em;
+ border-radius: var(--universal-border-radius);
+ padding: calc(var(--universal-padding) / 4) var(--universal-padding); }
+ mark.inline-block {
+ display: inline-block;
+ font-size: 1em;
+ line-height: 1.4;
+ padding: calc(var(--universal-padding) / 2) var(--universal-padding); }
+
+:root {
+ --toast-back-color: #424242;
+ --toast-fore-color: #fafafa; }
+
+.toast {
+ position: fixed;
+ bottom: calc(var(--universal-margin) * 3);
+ left: 50%;
+ transform: translate(-50%, -50%);
+ z-index: 1111;
+ color: var(--toast-fore-color);
+ background: var(--toast-back-color);
+ border-radius: calc(var(--universal-border-radius) * 16);
+ padding: var(--universal-padding) calc(var(--universal-padding) * 3); }
+
+:root {
+ --tooltip-back-color: #212121;
+ --tooltip-fore-color: #fafafa; }
+
+.tooltip {
+ position: relative;
+ display: inline-block; }
+ .tooltip:before, .tooltip:after {
+ position: absolute;
+ opacity: 0;
+ clip: rect(0 0 0 0);
+ -webkit-clip-path: inset(100%);
+ clip-path: inset(100%);
+ transition: all 0.3s;
+ z-index: 1010;
+ left: 50%; }
+ .tooltip:not(.bottom):before, .tooltip:not(.bottom):after {
+ bottom: 75%; }
+ .tooltip.bottom:before, .tooltip.bottom:after {
+ top: 75%; }
+ .tooltip:hover:before, .tooltip:hover:after, .tooltip:focus:before, .tooltip:focus:after {
+ opacity: 1;
+ clip: auto;
+ -webkit-clip-path: inset(0%);
+ clip-path: inset(0%); }
+ .tooltip:before {
+ content: '';
+ background: transparent;
+ border: var(--universal-margin) solid transparent;
+ left: calc(50% - var(--universal-margin)); }
+ .tooltip:not(.bottom):before {
+ border-top-color: #212121; }
+ .tooltip.bottom:before {
+ border-bottom-color: #212121; }
+ .tooltip:after {
+ content: attr(aria-label);
+ color: var(--tooltip-fore-color);
+ background: var(--tooltip-back-color);
+ border-radius: var(--universal-border-radius);
+ padding: var(--universal-padding);
+ white-space: nowrap;
+ transform: translateX(-50%); }
+ .tooltip:not(.bottom):after {
+ margin-bottom: calc(2 * var(--universal-margin)); }
+ .tooltip.bottom:after {
+ margin-top: calc(2 * var(--universal-margin)); }
+
+:root {
+ --modal-overlay-color: rgba(0, 0, 0, 0.45);
+ --modal-close-color: #e6007e;
+ --modal-close-hover-color: #ffe97f; }
+
+[type="checkbox"].modal {
+ height: 1px;
+ width: 1px;
+ margin: -1px;
+ overflow: hidden;
+ position: absolute;
+ clip: rect(0 0 0 0);
+ -webkit-clip-path: inset(100%);
+ clip-path: inset(100%); }
+ [type="checkbox"].modal + div {
+ position: fixed;
+ top: 0;
+ left: 0;
+ display: none;
+ width: 100vw;
+ height: 100vh;
+ background: var(--modal-overlay-color); }
+ [type="checkbox"].modal + div .card {
+ margin: 0 auto;
+ max-height: 50vh;
+ overflow: auto; }
+ [type="checkbox"].modal + div .card .modal-close {
+ position: absolute;
+ top: 0;
+ right: 0;
+ width: 1.75rem;
+ height: 1.75rem;
+ border-radius: var(--universal-border-radius);
+ padding: var(--universal-padding);
+ margin: 0;
+ cursor: pointer;
+ transition: background 0.3s; }
+ [type="checkbox"].modal + div .card .modal-close:before {
+ display: block;
+ content: '\00D7';
+ color: var(--modal-close-color);
+ position: relative;
+ font-family: sans-serif;
+ font-size: 1.75rem;
+ line-height: 1;
+ text-align: center; }
+ [type="checkbox"].modal + div .card .modal-close:hover, [type="checkbox"].modal + div .card .modal-close:focus {
+ background: var(--modal-close-hover-color); }
+ [type="checkbox"].modal:checked + div {
+ display: flex;
+ flex: 0 1 auto;
+ z-index: 1200; }
+ [type="checkbox"].modal:checked + div .card .modal-close {
+ z-index: 1211; }
+
+:root {
+ --collapse-label-back-color: #03234b;
+ --collapse-label-fore-color: #ffffff;
+ --collapse-label-hover-back-color: #3cb4e6;
+ --collapse-selected-label-back-color: #3cb4e6;
+ --collapse-border-color: var(--collapse-label-back-color);
+ --collapse-selected-border-color: #ceecf8;
+ --collapse-content-back-color: #ffffff;
+ --collapse-selected-label-border-color: #3cb4e6; }
+
+.collapse {
+ width: calc(100% - 2 * var(--universal-margin));
+ opacity: 1;
+ display: flex;
+ flex-direction: column;
+ margin: var(--universal-margin);
+ border-radius: var(--universal-border-radius); }
+ .collapse > [type="radio"], .collapse > [type="checkbox"] {
+ height: 1px;
+ width: 1px;
+ margin: -1px;
+ overflow: hidden;
+ position: absolute;
+ clip: rect(0 0 0 0);
+ -webkit-clip-path: inset(100%);
+ clip-path: inset(100%); }
+ .collapse > label {
+ flex-grow: 1;
+ display: inline-block;
+ height: 1.25rem;
+ cursor: pointer;
+ transition: background 0.2s;
+ color: var(--collapse-label-fore-color);
+ background: var(--collapse-label-back-color);
+ border: 0.0714285714rem solid var(--collapse-selected-border-color);
+ padding: calc(1.25 * var(--universal-padding)); }
+ .collapse > label:hover, .collapse > label:focus {
+ background: var(--collapse-label-hover-back-color); }
+ .collapse > label + div {
+ flex-basis: auto;
+ height: 1px;
+ width: 1px;
+ margin: -1px;
+ overflow: hidden;
+ position: absolute;
+ clip: rect(0 0 0 0);
+ -webkit-clip-path: inset(100%);
+ clip-path: inset(100%);
+ transition: max-height 0.3s;
+ max-height: 1px; }
+ .collapse > :checked + label {
+ background: var(--collapse-selected-label-back-color);
+ border-color: var(--collapse-selected-label-border-color); }
+ .collapse > :checked + label + div {
+ box-sizing: border-box;
+ position: relative;
+ width: 100%;
+ height: auto;
+ overflow: auto;
+ margin: 0;
+ background: var(--collapse-content-back-color);
+ border: 0.0714285714rem solid var(--collapse-selected-border-color);
+ border-top: 0;
+ padding: var(--universal-padding);
+ clip: auto;
+ -webkit-clip-path: inset(0%);
+ clip-path: inset(0%);
+ max-height: 100%; }
+ .collapse > label:not(:first-of-type) {
+ border-top: 0; }
+ .collapse > label:first-of-type {
+ border-radius: var(--universal-border-radius) var(--universal-border-radius) 0 0; }
+ .collapse > label:last-of-type:not(:first-of-type) {
+ border-radius: 0 0 var(--universal-border-radius) var(--universal-border-radius); }
+ .collapse > label:last-of-type:first-of-type {
+ border-radius: var(--universal-border-radius); }
+ .collapse > :checked:last-of-type:not(:first-of-type) + label {
+ border-radius: 0; }
+ .collapse > :checked:last-of-type + label + div {
+ border-radius: 0 0 var(--universal-border-radius) var(--universal-border-radius); }
+
+/*
+ Custom elements for contextual background elements, toasts and tooltips.
+*/
+mark.tertiary {
+ --mark-back-color: #3cb4e6; }
+
+mark.tag {
+ padding: calc(var(--universal-padding)/2) var(--universal-padding);
+ border-radius: 1em; }
+
+/*
+ Definitions for progress elements and spinners.
+*/
+/* Progress module CSS variable definitions */
+:root {
+ --progress-back-color: #3cb4e6;
+ --progress-fore-color: #555; }
+
+progress {
+ display: block;
+ vertical-align: baseline;
+ -webkit-appearance: none;
+ -moz-appearance: none;
+ appearance: none;
+ height: 0.75rem;
+ width: calc(100% - 2 * var(--universal-margin));
+ margin: var(--universal-margin);
+ border: 0;
+ border-radius: calc(2 * var(--universal-border-radius));
+ background: var(--progress-back-color);
+ color: var(--progress-fore-color); }
+ progress::-webkit-progress-value {
+ background: var(--progress-fore-color);
+ border-top-left-radius: calc(2 * var(--universal-border-radius));
+ border-bottom-left-radius: calc(2 * var(--universal-border-radius)); }
+ progress::-webkit-progress-bar {
+ background: var(--progress-back-color); }
+ progress::-moz-progress-bar {
+ background: var(--progress-fore-color);
+ border-top-left-radius: calc(2 * var(--universal-border-radius));
+ border-bottom-left-radius: calc(2 * var(--universal-border-radius)); }
+ progress[value="1000"]::-webkit-progress-value {
+ border-radius: calc(2 * var(--universal-border-radius)); }
+ progress[value="1000"]::-moz-progress-bar {
+ border-radius: calc(2 * var(--universal-border-radius)); }
+ progress.inline {
+ display: inline-block;
+ vertical-align: middle;
+ width: 60%; }
+
+:root {
+ --spinner-back-color: #ddd;
+ --spinner-fore-color: #555; }
+
+@keyframes spinner-donut-anim {
+ 0% {
+ transform: rotate(0deg); }
+ 100% {
+ transform: rotate(360deg); } }
+.spinner {
+ display: inline-block;
+ margin: var(--universal-margin);
+ border: 0.25rem solid var(--spinner-back-color);
+ border-left: 0.25rem solid var(--spinner-fore-color);
+ border-radius: 50%;
+ width: 1.25rem;
+ height: 1.25rem;
+ animation: spinner-donut-anim 1.2s linear infinite; }
+
+/*
+ Custom elements for progress bars and spinners.
+*/
+progress.primary {
+ --progress-fore-color: #1976d2; }
+
+progress.secondary {
+ --progress-fore-color: #d32f2f; }
+
+progress.tertiary {
+ --progress-fore-color: #308732; }
+
+.spinner.primary {
+ --spinner-fore-color: #1976d2; }
+
+.spinner.secondary {
+ --spinner-fore-color: #d32f2f; }
+
+.spinner.tertiary {
+ --spinner-fore-color: #308732; }
+
+/*
+ Definitions for icons - powered by Feather (https://feathericons.com/).
+*/
+span[class^='icon-'] {
+ display: inline-block;
+ height: 1em;
+ width: 1em;
+ vertical-align: -0.125em;
+ background-size: contain;
+ margin: 0 calc(var(--universal-margin) / 4); }
+ span[class^='icon-'].secondary {
+ -webkit-filter: invert(25%);
+ filter: invert(25%); }
+ span[class^='icon-'].inverse {
+ -webkit-filter: invert(100%);
+ filter: invert(100%); }
+
+span.icon-alert {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='8' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='16' x2='12' y2='16'%3E%3C/line%3E%3C/svg%3E"); }
+span.icon-bookmark {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M19 21l-7-5-7 5V5a2 2 0 0 1 2-2h10a2 2 0 0 1 2 2z'%3E%3C/path%3E%3C/svg%3E"); }
+span.icon-calendar {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='4' width='18' height='18' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='16' y1='2' x2='16' y2='6'%3E%3C/line%3E%3Cline x1='8' y1='2' x2='8' y2='6'%3E%3C/line%3E%3Cline x1='3' y1='10' x2='21' y2='10'%3E%3C/line%3E%3C/svg%3E"); }
+span.icon-credit {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='1' y='4' width='22' height='16' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='1' y1='10' x2='23' y2='10'%3E%3C/line%3E%3C/svg%3E"); }
+span.icon-edit {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M20 14.66V20a2 2 0 0 1-2 2H4a2 2 0 0 1-2-2V6a2 2 0 0 1 2-2h5.34'%3E%3C/path%3E%3Cpolygon points='18 2 22 6 12 16 8 16 8 12 18 2'%3E%3C/polygon%3E%3C/svg%3E"); }
+span.icon-link {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M18 13v6a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2V8a2 2 0 0 1 2-2h6'%3E%3C/path%3E%3Cpolyline points='15 3 21 3 21 9'%3E%3C/polyline%3E%3Cline x1='10' y1='14' x2='21' y2='3'%3E%3C/line%3E%3C/svg%3E"); }
+span.icon-help {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M9.09 9a3 3 0 0 1 5.83 1c0 2-3 3-3 3'%3E%3C/path%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='17' x2='12' y2='17'%3E%3C/line%3E%3C/svg%3E"); }
+span.icon-home {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M3 9l9-7 9 7v11a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2z'%3E%3C/path%3E%3Cpolyline points='9 22 9 12 15 12 15 22'%3E%3C/polyline%3E%3C/svg%3E"); }
+span.icon-info {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='16' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='8' x2='12' y2='8'%3E%3C/line%3E%3C/svg%3E"); }
+span.icon-lock {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='11' width='18' height='11' rx='2' ry='2'%3E%3C/rect%3E%3Cpath d='M7 11V7a5 5 0 0 1 10 0v4'%3E%3C/path%3E%3C/svg%3E"); }
+span.icon-mail {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M4 4h16c1.1 0 2 .9 2 2v12c0 1.1-.9 2-2 2H4c-1.1 0-2-.9-2-2V6c0-1.1.9-2 2-2z'%3E%3C/path%3E%3Cpolyline points='22,6 12,13 2,6'%3E%3C/polyline%3E%3C/svg%3E"); }
+span.icon-location {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M21 10c0 7-9 13-9 13s-9-6-9-13a9 9 0 0 1 18 0z'%3E%3C/path%3E%3Ccircle cx='12' cy='10' r='3'%3E%3C/circle%3E%3C/svg%3E"); }
+span.icon-phone {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M22 16.92v3a2 2 0 0 1-2.18 2 19.79 19.79 0 0 1-8.63-3.07 19.5 19.5 0 0 1-6-6 19.79 19.79 0 0 1-3.07-8.67A2 2 0 0 1 4.11 2h3a2 2 0 0 1 2 1.72 12.84 12.84 0 0 0 .7 2.81 2 2 0 0 1-.45 2.11L8.09 9.91a16 16 0 0 0 6 6l1.27-1.27a2 2 0 0 1 2.11-.45 12.84 12.84 0 0 0 2.81.7A2 2 0 0 1 22 16.92z'%3E%3C/path%3E%3C/svg%3E"); }
+span.icon-rss {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M4 11a9 9 0 0 1 9 9'%3E%3C/path%3E%3Cpath d='M4 4a16 16 0 0 1 16 16'%3E%3C/path%3E%3Ccircle cx='5' cy='19' r='1'%3E%3C/circle%3E%3C/svg%3E"); }
+span.icon-search {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='11' cy='11' r='8'%3E%3C/circle%3E%3Cline x1='21' y1='21' x2='16.65' y2='16.65'%3E%3C/line%3E%3C/svg%3E"); }
+span.icon-settings {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='3'%3E%3C/circle%3E%3Cpath d='M19.4 15a1.65 1.65 0 0 0 .33 1.82l.06.06a2 2 0 0 1 0 2.83 2 2 0 0 1-2.83 0l-.06-.06a1.65 1.65 0 0 0-1.82-.33 1.65 1.65 0 0 0-1 1.51V21a2 2 0 0 1-2 2 2 2 0 0 1-2-2v-.09A1.65 1.65 0 0 0 9 19.4a1.65 1.65 0 0 0-1.82.33l-.06.06a2 2 0 0 1-2.83 0 2 2 0 0 1 0-2.83l.06-.06a1.65 1.65 0 0 0 .33-1.82 1.65 1.65 0 0 0-1.51-1H3a2 2 0 0 1-2-2 2 2 0 0 1 2-2h.09A1.65 1.65 0 0 0 4.6 9a1.65 1.65 0 0 0-.33-1.82l-.06-.06a2 2 0 0 1 0-2.83 2 2 0 0 1 2.83 0l.06.06a1.65 1.65 0 0 0 1.82.33H9a1.65 1.65 0 0 0 1-1.51V3a2 2 0 0 1 2-2 2 2 0 0 1 2 2v.09a1.65 1.65 0 0 0 1 1.51 1.65 1.65 0 0 0 1.82-.33l.06-.06a2 2 0 0 1 2.83 0 2 2 0 0 1 0 2.83l-.06.06a1.65 1.65 0 0 0-.33 1.82V9a1.65 1.65 0 0 0 1.51 1H21a2 2 0 0 1 2 2 2 2 0 0 1-2 2h-.09a1.65 1.65 0 0 0-1.51 1z'%3E%3C/path%3E%3C/svg%3E"); }
+span.icon-share {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='18' cy='5' r='3'%3E%3C/circle%3E%3Ccircle cx='6' cy='12' r='3'%3E%3C/circle%3E%3Ccircle cx='18' cy='19' r='3'%3E%3C/circle%3E%3Cline x1='8.59' y1='13.51' x2='15.42' y2='17.49'%3E%3C/line%3E%3Cline x1='15.41' y1='6.51' x2='8.59' y2='10.49'%3E%3C/line%3E%3C/svg%3E"); }
+span.icon-cart {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='9' cy='21' r='1'%3E%3C/circle%3E%3Ccircle cx='20' cy='21' r='1'%3E%3C/circle%3E%3Cpath d='M1 1h4l2.68 13.39a2 2 0 0 0 2 1.61h9.72a2 2 0 0 0 2-1.61L23 6H6'%3E%3C/path%3E%3C/svg%3E"); }
+span.icon-upload {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M21 15v4a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2v-4'%3E%3C/path%3E%3Cpolyline points='17 8 12 3 7 8'%3E%3C/polyline%3E%3Cline x1='12' y1='3' x2='12' y2='15'%3E%3C/line%3E%3C/svg%3E"); }
+span.icon-user {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M20 21v-2a4 4 0 0 0-4-4H8a4 4 0 0 0-4 4v2'%3E%3C/path%3E%3Ccircle cx='12' cy='7' r='4'%3E%3C/circle%3E%3C/svg%3E"); }
+
+/*
+ Definitions for STMicroelectronics icons (https://brandportal.st.com/document/26).
+*/
+span.icon-st-update {
+ background-image: url("Update.svg"); }
+span.icon-st-add {
+ background-image: url("Add button.svg"); }
+
+/*
+ Definitions for utilities and helper classes.
+*/
+/* Utility module CSS variable definitions */
+:root {
+ --generic-border-color: rgba(0, 0, 0, 0.3);
+ --generic-box-shadow: 0 0.2857142857rem 0.2857142857rem 0 rgba(0, 0, 0, 0.125), 0 0.1428571429rem 0.1428571429rem -0.1428571429rem rgba(0, 0, 0, 0.125); }
+
+.hidden {
+ display: none !important; }
+
+.visually-hidden {
+ position: absolute !important;
+ width: 1px !important;
+ height: 1px !important;
+ margin: -1px !important;
+ border: 0 !important;
+ padding: 0 !important;
+ clip: rect(0 0 0 0) !important;
+ -webkit-clip-path: inset(100%) !important;
+ clip-path: inset(100%) !important;
+ overflow: hidden !important; }
+
+.bordered {
+ border: 0.0714285714rem solid var(--generic-border-color) !important; }
+
+.rounded {
+ border-radius: var(--universal-border-radius) !important; }
+
+.circular {
+ border-radius: 50% !important; }
+
+.shadowed {
+ box-shadow: var(--generic-box-shadow) !important; }
+
+.responsive-margin {
+ margin: calc(var(--universal-margin) / 4) !important; }
+ @media screen and (min-width: 500px) {
+ .responsive-margin {
+ margin: calc(var(--universal-margin) / 2) !important; } }
+ @media screen and (min-width: 1280px) {
+ .responsive-margin {
+ margin: var(--universal-margin) !important; } }
+
+.responsive-padding {
+ padding: calc(var(--universal-padding) / 4) !important; }
+ @media screen and (min-width: 500px) {
+ .responsive-padding {
+ padding: calc(var(--universal-padding) / 2) !important; } }
+ @media screen and (min-width: 1280px) {
+ .responsive-padding {
+ padding: var(--universal-padding) !important; } }
+
+@media screen and (max-width: 499px) {
+ .hidden-sm {
+ display: none !important; } }
+@media screen and (min-width: 500px) and (max-width: 1279px) {
+ .hidden-md {
+ display: none !important; } }
+@media screen and (min-width: 1280px) {
+ .hidden-lg {
+ display: none !important; } }
+@media screen and (max-width: 499px) {
+ .visually-hidden-sm {
+ position: absolute !important;
+ width: 1px !important;
+ height: 1px !important;
+ margin: -1px !important;
+ border: 0 !important;
+ padding: 0 !important;
+ clip: rect(0 0 0 0) !important;
+ -webkit-clip-path: inset(100%) !important;
+ clip-path: inset(100%) !important;
+ overflow: hidden !important; } }
+@media screen and (min-width: 500px) and (max-width: 1279px) {
+ .visually-hidden-md {
+ position: absolute !important;
+ width: 1px !important;
+ height: 1px !important;
+ margin: -1px !important;
+ border: 0 !important;
+ padding: 0 !important;
+ clip: rect(0 0 0 0) !important;
+ -webkit-clip-path: inset(100%) !important;
+ clip-path: inset(100%) !important;
+ overflow: hidden !important; } }
+@media screen and (min-width: 1280px) {
+ .visually-hidden-lg {
+ position: absolute !important;
+ width: 1px !important;
+ height: 1px !important;
+ margin: -1px !important;
+ border: 0 !important;
+ padding: 0 !important;
+ clip: rect(0 0 0 0) !important;
+ -webkit-clip-path: inset(100%) !important;
+ clip-path: inset(100%) !important;
+ overflow: hidden !important; } }
+
+/*# sourceMappingURL=mini-custom.css.map */
+
+img[alt="ST logo"] { display: block; margin: auto; width: 75%; max-width: 250px; min-width: 71px; }
+img[alt="Cube logo"] { float: right; width: 30%; max-width: 10rem; min-width: 8rem; padding-right: 1rem;}
+
+.figure {
+ display: block;
+ margin-left: auto;
+ margin-right: auto;
+ text-align: center;
+}
\ No newline at end of file
diff --git a/system/Drivers/CMSIS/Device/ST/STM32C0xx/_htmresc/st_logo.png b/system/Drivers/CMSIS/Device/ST/STM32C0xx/_htmresc/st_logo.png
new file mode 100644
index 0000000000..8b80057fd3
Binary files /dev/null and b/system/Drivers/CMSIS/Device/ST/STM32C0xx/_htmresc/st_logo.png differ
diff --git a/system/Drivers/CMSIS/Device/ST/STM32C0xx/_htmresc/st_logo_2020.png b/system/Drivers/CMSIS/Device/ST/STM32C0xx/_htmresc/st_logo_2020.png
new file mode 100644
index 0000000000..d6cebb5ac7
Binary files /dev/null and b/system/Drivers/CMSIS/Device/ST/STM32C0xx/_htmresc/st_logo_2020.png differ
diff --git a/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md b/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md
index 31aba7a745..93937206ee 100644
--- a/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md
+++ b/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md
@@ -1,5 +1,6 @@
# STM32YYxx CMSIS version:
+ * STM32C0: 1.0.0
* STM32F0: 2.3.6
* STM32F1: 4.3.3
* STM32F2: 2.2.5
diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/system/Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
new file mode 100644
index 0000000000..a5d20a8fd6
--- /dev/null
+++ b/system/Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
@@ -0,0 +1,3982 @@
+/**
+ ******************************************************************************
+ * @file stm32_hal_legacy.h
+ * @author MCD Application Team
+ * @brief This file contains aliases definition for the STM32Cube HAL constants
+ * macros and functions maintained for legacy purpose.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32_HAL_LEGACY
+#define STM32_HAL_LEGACY
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define AES_FLAG_RDERR CRYP_FLAG_RDERR
+#define AES_FLAG_WRERR CRYP_FLAG_WRERR
+#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF
+#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR
+#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR
+#if defined(STM32U5)
+#define CRYP_DATATYPE_32B CRYP_NO_SWAP
+#define CRYP_DATATYPE_16B CRYP_HALFWORD_SWAP
+#define CRYP_DATATYPE_8B CRYP_BYTE_SWAP
+#define CRYP_DATATYPE_1B CRYP_BIT_SWAP
+#define CRYP_CCF_CLEAR CRYP_CLEAR_CCF
+#define CRYP_ERR_CLEAR CRYP_CLEAR_RWEIF
+#endif /* STM32U5 */
+/**
+ * @}
+ */
+
+/** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define ADC_RESOLUTION12b ADC_RESOLUTION_12B
+#define ADC_RESOLUTION10b ADC_RESOLUTION_10B
+#define ADC_RESOLUTION8b ADC_RESOLUTION_8B
+#define ADC_RESOLUTION6b ADC_RESOLUTION_6B
+#define OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN
+#define OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED
+#define EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV
+#define EOC_SEQ_CONV ADC_EOC_SEQ_CONV
+#define EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV
+#define REGULAR_GROUP ADC_REGULAR_GROUP
+#define INJECTED_GROUP ADC_INJECTED_GROUP
+#define REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP
+#define AWD_EVENT ADC_AWD_EVENT
+#define AWD1_EVENT ADC_AWD1_EVENT
+#define AWD2_EVENT ADC_AWD2_EVENT
+#define AWD3_EVENT ADC_AWD3_EVENT
+#define OVR_EVENT ADC_OVR_EVENT
+#define JQOVF_EVENT ADC_JQOVF_EVENT
+#define ALL_CHANNELS ADC_ALL_CHANNELS
+#define REGULAR_CHANNELS ADC_REGULAR_CHANNELS
+#define INJECTED_CHANNELS ADC_INJECTED_CHANNELS
+#define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR
+#define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT
+#define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1
+#define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2
+#define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4
+#define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6
+#define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8
+#define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO
+#define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2
+#define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO
+#define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4
+#define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO
+#define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11
+#define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1
+#define ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE
+#define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING
+#define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING
+#define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING
+#define ADC_SAMPLETIME_2CYCLE_5 ADC_SAMPLETIME_2CYCLES_5
+
+#define HAL_ADC_STATE_BUSY_REG HAL_ADC_STATE_REG_BUSY
+#define HAL_ADC_STATE_BUSY_INJ HAL_ADC_STATE_INJ_BUSY
+#define HAL_ADC_STATE_EOC_REG HAL_ADC_STATE_REG_EOC
+#define HAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC
+#define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL
+#define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL
+#define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1
+
+#if defined(STM32H7)
+#define ADC_CHANNEL_VBAT_DIV4 ADC_CHANNEL_VBAT
+#endif /* STM32H7 */
+
+#if defined(STM32U5)
+#define ADC_SAMPLETIME_5CYCLE ADC_SAMPLETIME_5CYCLES
+#define ADC_SAMPLETIME_391CYCLES_5 ADC_SAMPLETIME_391CYCLES
+#define ADC4_SAMPLETIME_160CYCLES_5 ADC4_SAMPLETIME_814CYCLES_5
+#endif /* STM32U5 */
+/**
+ * @}
+ */
+
+/** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE
+#define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE
+#define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1
+#define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2
+#define COMP_EXTI_LINE_COMP3_EVENT COMP_EXTI_LINE_COMP3
+#define COMP_EXTI_LINE_COMP4_EVENT COMP_EXTI_LINE_COMP4
+#define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5
+#define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6
+#define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7
+#if defined(STM32L0)
+#define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM input 1 for COMP1, LPTIM input 2 for COMP2 */
+#endif
+#define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR
+#if defined(STM32F373xC) || defined(STM32F378xx)
+#define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1
+#define COMP_OUTPUT_TIM3OCREFCLR COMP_OUTPUT_COMP1_TIM3OCREFCLR
+#endif /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32L0) || defined(STM32L4)
+#define COMP_WINDOWMODE_ENABLE COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON
+
+#define COMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1
+#define COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2
+#define COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3
+#define COMP_NONINVERTINGINPUT_IO4 COMP_INPUT_PLUS_IO4
+#define COMP_NONINVERTINGINPUT_IO5 COMP_INPUT_PLUS_IO5
+#define COMP_NONINVERTINGINPUT_IO6 COMP_INPUT_PLUS_IO6
+
+#define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT
+#define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT
+#define COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT
+#define COMP_INVERTINGINPUT_VREFINT COMP_INPUT_MINUS_VREFINT
+#define COMP_INVERTINGINPUT_DAC1_CH1 COMP_INPUT_MINUS_DAC1_CH1
+#define COMP_INVERTINGINPUT_DAC1_CH2 COMP_INPUT_MINUS_DAC1_CH2
+#define COMP_INVERTINGINPUT_DAC1 COMP_INPUT_MINUS_DAC1_CH1
+#define COMP_INVERTINGINPUT_DAC2 COMP_INPUT_MINUS_DAC1_CH2
+#define COMP_INVERTINGINPUT_IO1 COMP_INPUT_MINUS_IO1
+#if defined(STM32L0)
+/* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2), */
+/* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding */
+/* to the second dedicated IO (only for COMP2). */
+#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_DAC1_CH2
+#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO2
+#else
+#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_IO2
+#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO3
+#endif
+#define COMP_INVERTINGINPUT_IO4 COMP_INPUT_MINUS_IO4
+#define COMP_INVERTINGINPUT_IO5 COMP_INPUT_MINUS_IO5
+
+#define COMP_OUTPUTLEVEL_LOW COMP_OUTPUT_LEVEL_LOW
+#define COMP_OUTPUTLEVEL_HIGH COMP_OUTPUT_LEVEL_HIGH
+
+/* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose. */
+/* To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()". */
+#if defined(COMP_CSR_LOCK)
+#define COMP_FLAG_LOCK COMP_CSR_LOCK
+#elif defined(COMP_CSR_COMP1LOCK)
+#define COMP_FLAG_LOCK COMP_CSR_COMP1LOCK
+#elif defined(COMP_CSR_COMPxLOCK)
+#define COMP_FLAG_LOCK COMP_CSR_COMPxLOCK
+#endif
+
+#if defined(STM32L4)
+#define COMP_BLANKINGSRCE_TIM1OC5 COMP_BLANKINGSRC_TIM1_OC5_COMP1
+#define COMP_BLANKINGSRCE_TIM2OC3 COMP_BLANKINGSRC_TIM2_OC3_COMP1
+#define COMP_BLANKINGSRCE_TIM3OC3 COMP_BLANKINGSRC_TIM3_OC3_COMP1
+#define COMP_BLANKINGSRCE_TIM3OC4 COMP_BLANKINGSRC_TIM3_OC4_COMP2
+#define COMP_BLANKINGSRCE_TIM8OC5 COMP_BLANKINGSRC_TIM8_OC5_COMP2
+#define COMP_BLANKINGSRCE_TIM15OC1 COMP_BLANKINGSRC_TIM15_OC1_COMP2
+#define COMP_BLANKINGSRCE_NONE COMP_BLANKINGSRC_NONE
+#endif
+
+#if defined(STM32L0)
+#define COMP_MODE_HIGHSPEED COMP_POWERMODE_MEDIUMSPEED
+#define COMP_MODE_LOWSPEED COMP_POWERMODE_ULTRALOWPOWER
+#else
+#define COMP_MODE_HIGHSPEED COMP_POWERMODE_HIGHSPEED
+#define COMP_MODE_MEDIUMSPEED COMP_POWERMODE_MEDIUMSPEED
+#define COMP_MODE_LOWPOWER COMP_POWERMODE_LOWPOWER
+#define COMP_MODE_ULTRALOWPOWER COMP_POWERMODE_ULTRALOWPOWER
+#endif
+
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig
+#if defined(STM32U5)
+#define MPU_DEVICE_nGnRnE MPU_DEVICE_NGNRNE
+#define MPU_DEVICE_nGnRE MPU_DEVICE_NGNRE
+#define MPU_DEVICE_nGRE MPU_DEVICE_NGRE
+#endif /* STM32U5 */
+/**
+ * @}
+ */
+
+/** @defgroup CRC_Aliases CRC API aliases
+ * @{
+ */
+#if defined(STM32C0)
+#else
+#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for inter STM32 series compatibility */
+#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for inter STM32 series compatibility */
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE
+#define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define DAC1_CHANNEL_1 DAC_CHANNEL_1
+#define DAC1_CHANNEL_2 DAC_CHANNEL_2
+#define DAC2_CHANNEL_1 DAC_CHANNEL_1
+#define DAC_WAVE_NONE 0x00000000U
+#define DAC_WAVE_NOISE DAC_CR_WAVE1_0
+#define DAC_WAVE_TRIANGLE DAC_CR_WAVE1_1
+#define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE
+#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE
+#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE
+
+#if defined(STM32G4) || defined(STM32H7) || defined (STM32U5)
+#define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL
+#define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL
+#endif
+
+#if defined(STM32U5)
+#define DAC_TRIGGER_STOP_LPTIM1_OUT DAC_TRIGGER_STOP_LPTIM1_CH1
+#define DAC_TRIGGER_STOP_LPTIM3_OUT DAC_TRIGGER_STOP_LPTIM3_CH1
+#define DAC_TRIGGER_LPTIM1_OUT DAC_TRIGGER_LPTIM1_CH1
+#define DAC_TRIGGER_LPTIM3_OUT DAC_TRIGGER_LPTIM3_CH1
+#endif
+
+#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) || defined(STM32G4)
+#define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID
+#define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID
+#endif
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2
+#define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4
+#define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5
+#define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4
+#define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2
+#define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32
+#define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6
+#define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7
+#define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67
+#define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67
+#define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76
+#define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6
+#define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7
+#define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6
+
+#define IS_HAL_REMAPDMA IS_DMA_REMAP
+#define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE
+#define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE
+
+#if defined(STM32L4)
+
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI1 HAL_DMAMUX1_REQ_GEN_EXTI1
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI2 HAL_DMAMUX1_REQ_GEN_EXTI2
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI3 HAL_DMAMUX1_REQ_GEN_EXTI3
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI4 HAL_DMAMUX1_REQ_GEN_EXTI4
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI5 HAL_DMAMUX1_REQ_GEN_EXTI5
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI6 HAL_DMAMUX1_REQ_GEN_EXTI6
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI7 HAL_DMAMUX1_REQ_GEN_EXTI7
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI8 HAL_DMAMUX1_REQ_GEN_EXTI8
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI9 HAL_DMAMUX1_REQ_GEN_EXTI9
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI10 HAL_DMAMUX1_REQ_GEN_EXTI10
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI11 HAL_DMAMUX1_REQ_GEN_EXTI11
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI12 HAL_DMAMUX1_REQ_GEN_EXTI12
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI13 HAL_DMAMUX1_REQ_GEN_EXTI13
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI14 HAL_DMAMUX1_REQ_GEN_EXTI14
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI15 HAL_DMAMUX1_REQ_GEN_EXTI15
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH3_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT
+#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT
+#define HAL_DMAMUX1_REQUEST_GEN_DSI_TE HAL_DMAMUX1_REQ_GEN_DSI_TE
+#define HAL_DMAMUX1_REQUEST_GEN_DSI_EOT HAL_DMAMUX1_REQ_GEN_DSI_EOT
+#define HAL_DMAMUX1_REQUEST_GEN_DMA2D_EOT HAL_DMAMUX1_REQ_GEN_DMA2D_EOT
+#define HAL_DMAMUX1_REQUEST_GEN_LTDC_IT HAL_DMAMUX1_REQ_GEN_LTDC_IT
+
+#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT
+#define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING
+#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING
+#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING
+
+#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
+#define DMA_REQUEST_DCMI_PSSI DMA_REQUEST_DCMI
+#endif
+
+#endif /* STM32L4 */
+
+#if defined(STM32G0)
+#define DMA_REQUEST_DAC1_CHANNEL1 DMA_REQUEST_DAC1_CH1
+#define DMA_REQUEST_DAC1_CHANNEL2 DMA_REQUEST_DAC1_CH2
+#define DMA_REQUEST_TIM16_TRIG_COM DMA_REQUEST_TIM16_COM
+#define DMA_REQUEST_TIM17_TRIG_COM DMA_REQUEST_TIM17_COM
+
+#define LL_DMAMUX_REQ_TIM16_TRIG_COM LL_DMAMUX_REQ_TIM16_COM
+#define LL_DMAMUX_REQ_TIM17_TRIG_COM LL_DMAMUX_REQ_TIM17_COM
+#endif
+
+#if defined(STM32H7)
+
+#define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1
+#define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2
+
+#define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX
+#define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX
+
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT
+#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT
+#define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0
+#define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO HAL_DMAMUX1_REQ_GEN_TIM12_TRGO
+
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP HAL_DMAMUX2_REQ_GEN_I2C4_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP HAL_DMAMUX2_REQ_GEN_SPI6_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT HAL_DMAMUX2_REQ_GEN_COMP1_OUT
+#define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT HAL_DMAMUX2_REQ_GEN_COMP2_OUT
+#define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP HAL_DMAMUX2_REQ_GEN_RTC_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_EXTI0 HAL_DMAMUX2_REQ_GEN_EXTI0
+#define HAL_DMAMUX2_REQUEST_GEN_EXTI2 HAL_DMAMUX2_REQ_GEN_EXTI2
+#define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT HAL_DMAMUX2_REQ_GEN_SPI6_IT
+#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT
+#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT
+#define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT HAL_DMAMUX2_REQ_GEN_ADC3_IT
+#define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT
+#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT
+#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT
+
+#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT
+#define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING
+#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING
+#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING
+
+#define DFSDM_FILTER_EXT_TRIG_LPTIM1 DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT
+#define DFSDM_FILTER_EXT_TRIG_LPTIM2 DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT
+#define DFSDM_FILTER_EXT_TRIG_LPTIM3 DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT
+
+#define DAC_TRIGGER_LP1_OUT DAC_TRIGGER_LPTIM1_OUT
+#define DAC_TRIGGER_LP2_OUT DAC_TRIGGER_LPTIM2_OUT
+
+#endif /* STM32H7 */
+
+#if defined(STM32U5)
+#define GPDMA1_REQUEST_DCMI GPDMA1_REQUEST_DCMI_PSSI
+#endif /* STM32U5 */
+/**
+ * @}
+ */
+
+/** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE
+#define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD
+#define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD
+#define TYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD
+#define TYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS
+#define TYPEERASE_PAGES FLASH_TYPEERASE_PAGES
+#define TYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES
+#define TYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE
+#define WRPSTATE_DISABLE OB_WRPSTATE_DISABLE
+#define WRPSTATE_ENABLE OB_WRPSTATE_ENABLE
+#define HAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE
+#define OBEX_PCROP OPTIONBYTE_PCROP
+#define OBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG
+#define PCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE
+#define PCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE
+#define TYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE
+#define TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD
+#define TYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD
+#define TYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE
+#define TYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD
+#define TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD
+#define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE
+#define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD
+#define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD
+#define PAGESIZE FLASH_PAGE_SIZE
+#define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE
+#define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD
+#define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD
+#define VOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1
+#define VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2
+#define VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3
+#define VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4
+#define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST
+#define TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST
+#define WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA
+#define WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB
+#define WRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA
+#define WRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB
+#define IWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE
+#define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN
+#define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE
+#define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN
+#define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE
+#define FLASH_ERROR_RD HAL_FLASH_ERROR_RD
+#define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG
+#define FLASH_ERROR_PGP HAL_FLASH_ERROR_PGS
+#define FLASH_ERROR_WRP HAL_FLASH_ERROR_WRP
+#define FLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV
+#define FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR
+#define FLASH_ERROR_PROG HAL_FLASH_ERROR_PROG
+#define FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION
+#define FLASH_ERROR_PGA HAL_FLASH_ERROR_PGA
+#define FLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE
+#define FLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE
+#define FLASH_ERROR_PGS HAL_FLASH_ERROR_PGS
+#define FLASH_ERROR_MIS HAL_FLASH_ERROR_MIS
+#define FLASH_ERROR_FAST HAL_FLASH_ERROR_FAST
+#define FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR
+#define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO
+#define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION
+#define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS
+#define OB_WDG_SW OB_IWDG_SW
+#define OB_WDG_HW OB_IWDG_HW
+#define OB_SDADC12_VDD_MONITOR_SET OB_SDACD_VDD_MONITOR_SET
+#define OB_SDADC12_VDD_MONITOR_RESET OB_SDACD_VDD_MONITOR_RESET
+#define OB_RAM_PARITY_CHECK_SET OB_SRAM_PARITY_SET
+#define OB_RAM_PARITY_CHECK_RESET OB_SRAM_PARITY_RESET
+#define IS_OB_SDADC12_VDD_MONITOR IS_OB_SDACD_VDD_MONITOR
+#define OB_RDP_LEVEL0 OB_RDP_LEVEL_0
+#define OB_RDP_LEVEL1 OB_RDP_LEVEL_1
+#define OB_RDP_LEVEL2 OB_RDP_LEVEL_2
+#if defined(STM32G0) || defined(STM32C0)
+#define OB_BOOT_LOCK_DISABLE OB_BOOT_ENTRY_FORCED_NONE
+#define OB_BOOT_LOCK_ENABLE OB_BOOT_ENTRY_FORCED_FLASH
+#else
+#define OB_BOOT_ENTRY_FORCED_NONE OB_BOOT_LOCK_DISABLE
+#define OB_BOOT_ENTRY_FORCED_FLASH OB_BOOT_LOCK_ENABLE
+#endif
+#if defined(STM32H7)
+#define FLASH_FLAG_SNECCE_BANK1RR FLASH_FLAG_SNECCERR_BANK1
+#define FLASH_FLAG_DBECCE_BANK1RR FLASH_FLAG_DBECCERR_BANK1
+#define FLASH_FLAG_STRBER_BANK1R FLASH_FLAG_STRBERR_BANK1
+#define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2
+#define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2
+#define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2
+#define FLASH_FLAG_WDW FLASH_FLAG_WBNE
+#define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL
+#endif /* STM32H7 */
+#if defined(STM32U5)
+#define OB_USER_nRST_STOP OB_USER_NRST_STOP
+#define OB_USER_nRST_STDBY OB_USER_NRST_STDBY
+#define OB_USER_nRST_SHDW OB_USER_NRST_SHDW
+#define OB_USER_nSWBOOT0 OB_USER_NSWBOOT0
+#define OB_USER_nBOOT0 OB_USER_NBOOT0
+#define OB_nBOOT0_RESET OB_NBOOT0_RESET
+#define OB_nBOOT0_SET OB_NBOOT0_SET
+#endif /* STM32U5 */
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#if defined(STM32H7)
+#define __HAL_RCC_JPEG_CLK_ENABLE __HAL_RCC_JPGDECEN_CLK_ENABLE
+#define __HAL_RCC_JPEG_CLK_DISABLE __HAL_RCC_JPGDECEN_CLK_DISABLE
+#define __HAL_RCC_JPEG_FORCE_RESET __HAL_RCC_JPGDECRST_FORCE_RESET
+#define __HAL_RCC_JPEG_RELEASE_RESET __HAL_RCC_JPGDECRST_RELEASE_RESET
+#define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE
+#define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE
+#endif /* STM32H7 */
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9
+#define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1
+#define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2
+#define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3
+#if defined(STM32G4)
+
+#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SYSCFG_EnableIOSwitchBooster
+#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SYSCFG_DisableIOSwitchBooster
+#define HAL_SYSCFG_EnableIOAnalogSwitchVDD HAL_SYSCFG_EnableIOSwitchVDD
+#define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD
+#endif /* STM32G4 */
+
+/**
+ * @}
+ */
+
+
+/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose
+ * @{
+ */
+#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4)
+#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE
+#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE
+#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8
+#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16
+#elif defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4)
+#define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE
+#define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE
+#define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8
+#define FMC_NAND_MEM_BUS_WIDTH_16 FMC_NAND_PCC_MEM_BUS_WIDTH_16
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef
+#define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef
+/**
+ * @}
+ */
+
+/** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define GET_GPIO_SOURCE GPIO_GET_INDEX
+#define GET_GPIO_INDEX GPIO_GET_INDEX
+
+#if defined(STM32F4)
+#define GPIO_AF12_SDMMC GPIO_AF12_SDIO
+#define GPIO_AF12_SDMMC1 GPIO_AF12_SDIO
+#endif
+
+#if defined(STM32F7)
+#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1
+#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1
+#endif
+
+#if defined(STM32L4)
+#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1
+#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1
+#endif
+
+#if defined(STM32H7)
+#define GPIO_AF7_SDIO1 GPIO_AF7_SDMMC1
+#define GPIO_AF8_SDIO1 GPIO_AF8_SDMMC1
+#define GPIO_AF12_SDIO1 GPIO_AF12_SDMMC1
+#define GPIO_AF9_SDIO2 GPIO_AF9_SDMMC2
+#define GPIO_AF10_SDIO2 GPIO_AF10_SDMMC2
+#define GPIO_AF11_SDIO2 GPIO_AF11_SDMMC2
+
+#if defined (STM32H743xx) || defined (STM32H753xx) || defined (STM32H750xx) || defined (STM32H742xx) || \
+ defined (STM32H745xx) || defined (STM32H755xx) || defined (STM32H747xx) || defined (STM32H757xx)
+#define GPIO_AF10_OTG2_HS GPIO_AF10_OTG2_FS
+#define GPIO_AF10_OTG1_FS GPIO_AF10_OTG1_HS
+#define GPIO_AF12_OTG2_FS GPIO_AF12_OTG1_FS
+#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || STM32H757xx */
+#endif /* STM32H7 */
+
+#define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1
+#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1
+#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1
+
+#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) || defined(STM32WB) || defined(STM32U5)
+#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
+#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
+#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH
+#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
+#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7 || STM32WB || STM32U5*/
+
+#if defined(STM32L1)
+#define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW
+#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM
+#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH
+#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
+#endif /* STM32L1 */
+
+#if defined(STM32F0) || defined(STM32F3) || defined(STM32F1)
+#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
+#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
+#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH
+#endif /* STM32F0 || STM32F3 || STM32F1 */
+
+#define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1
+
+#if defined(STM32U5)
+#define GPIO_AF0_RTC_50Hz GPIO_AF0_RTC_50HZ
+#endif /* STM32U5 */
+/**
+ * @}
+ */
+
+/** @defgroup HAL_GTZC_Aliased_Defines HAL GTZC Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#if defined(STM32U5)
+#define GTZC_PERIPH_DCMI GTZC_PERIPH_DCMI_PSSI
+#endif /* STM32U5 */
+/**
+ * @}
+ */
+
+/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define HRTIM_TIMDELAYEDPROTECTION_DISABLED HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6
+#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7
+#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7
+
+#define __HAL_HRTIM_SetCounter __HAL_HRTIM_SETCOUNTER
+#define __HAL_HRTIM_GetCounter __HAL_HRTIM_GETCOUNTER
+#define __HAL_HRTIM_SetPeriod __HAL_HRTIM_SETPERIOD
+#define __HAL_HRTIM_GetPeriod __HAL_HRTIM_GETPERIOD
+#define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER
+#define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER
+#define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE
+#define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE
+
+#if defined(STM32G4)
+#define HAL_HRTIM_ExternalEventCounterConfig HAL_HRTIM_ExtEventCounterConfig
+#define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable
+#define HAL_HRTIM_ExternalEventCounterDisable HAL_HRTIM_ExtEventCounterDisable
+#define HAL_HRTIM_ExternalEventCounterReset HAL_HRTIM_ExtEventCounterReset
+#define HRTIM_TIMEEVENT_A HRTIM_EVENTCOUNTER_A
+#define HRTIM_TIMEEVENT_B HRTIM_EVENTCOUNTER_B
+#define HRTIM_TIMEEVENTRESETMODE_UNCONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_UNCONDITIONAL
+#define HRTIM_TIMEEVENTRESETMODE_CONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_CONDITIONAL
+#endif /* STM32G4 */
+
+#if defined(STM32H7)
+#define HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTSET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9
+
+#define HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9
+#endif /* STM32H7 */
+
+#if defined(STM32F3)
+/** @brief Constants defining available sources associated to external events.
+ */
+#define HRTIM_EVENTSRC_1 (0x00000000U)
+#define HRTIM_EVENTSRC_2 (HRTIM_EECR1_EE1SRC_0)
+#define HRTIM_EVENTSRC_3 (HRTIM_EECR1_EE1SRC_1)
+#define HRTIM_EVENTSRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0)
+
+/** @brief Constants defining the DLL calibration periods (in micro seconds)
+ */
+#define HRTIM_CALIBRATIONRATE_7300 0x00000000U
+#define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0)
+#define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1)
+#define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0)
+
+#endif /* STM32F3 */
+/**
+ * @}
+ */
+
+/** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE
+#define I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE
+#define I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE
+#define I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE
+#define I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE
+#define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE
+#define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE
+#define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE
+#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7)
+#define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX
+#define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX
+#define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX
+#define HAL_I2C_STATE_MASTER_BUSY_RX HAL_I2C_STATE_BUSY_RX
+#define HAL_I2C_STATE_SLAVE_BUSY_TX HAL_I2C_STATE_BUSY_TX
+#define HAL_I2C_STATE_SLAVE_BUSY_RX HAL_I2C_STATE_BUSY_RX
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE
+#define IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define KR_KEY_RELOAD IWDG_KEY_RELOAD
+#define KR_KEY_ENABLE IWDG_KEY_ENABLE
+#define KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE
+#define KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE
+/**
+ * @}
+ */
+
+/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION
+#define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CLOCKSAMPLETIME_2TRANSITIONS
+#define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CLOCKSAMPLETIME_4TRANSITIONS
+#define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CLOCKSAMPLETIME_8TRANSITIONS
+
+#define LPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISING
+#define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING
+#define LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING
+
+#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION
+#define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS
+#define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS
+#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS
+
+/* The following 3 definition have also been present in a temporary version of lptim.h */
+/* They need to be renamed also to the right name, just in case */
+#define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS
+#define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS
+#define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS
+
+
+/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define HAL_LPTIM_ReadCompare HAL_LPTIM_ReadCapturedValue
+/**
+ * @}
+ */
+
+#if defined(STM32U5)
+#define LPTIM_ISR_CC1 LPTIM_ISR_CC1IF
+#define LPTIM_ISR_CC2 LPTIM_ISR_CC2IF
+#define LPTIM_CHANNEL_ALL 0x00000000U
+#endif /* STM32U5 */
+/**
+ * @}
+ */
+
+/** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define HAL_NAND_Read_Page HAL_NAND_Read_Page_8b
+#define HAL_NAND_Write_Page HAL_NAND_Write_Page_8b
+#define HAL_NAND_Read_SpareArea HAL_NAND_Read_SpareArea_8b
+#define HAL_NAND_Write_SpareArea HAL_NAND_Write_SpareArea_8b
+
+#define NAND_AddressTypedef NAND_AddressTypeDef
+
+#define __ARRAY_ADDRESS ARRAY_ADDRESS
+#define __ADDR_1st_CYCLE ADDR_1ST_CYCLE
+#define __ADDR_2nd_CYCLE ADDR_2ND_CYCLE
+#define __ADDR_3rd_CYCLE ADDR_3RD_CYCLE
+#define __ADDR_4th_CYCLE ADDR_4TH_CYCLE
+/**
+ * @}
+ */
+
+/** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define NOR_StatusTypedef HAL_NOR_StatusTypeDef
+#define NOR_SUCCESS HAL_NOR_STATUS_SUCCESS
+#define NOR_ONGOING HAL_NOR_STATUS_ONGOING
+#define NOR_ERROR HAL_NOR_STATUS_ERROR
+#define NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT
+
+#define __NOR_WRITE NOR_WRITE
+#define __NOR_ADDR_SHIFT NOR_ADDR_SHIFT
+/**
+ * @}
+ */
+
+/** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0
+#define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1
+#define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2
+#define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3
+
+#define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0
+#define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1
+#define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2
+#define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3
+
+#define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0
+#define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1
+
+#define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0
+#define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1
+
+#define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0
+#define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1
+
+#define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1
+
+#define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO
+#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
+#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
+
+#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4)
+#define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID
+#define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID
+#endif
+
+#if defined(STM32L4) || defined(STM32L5)
+#define OPAMP_POWERMODE_NORMAL OPAMP_POWERMODE_NORMALPOWER
+#elif defined(STM32G4)
+#define OPAMP_POWERMODE_NORMAL OPAMP_POWERMODE_NORMALSPEED
+#endif
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS
+
+#if defined(STM32H7)
+#define I2S_IT_TXE I2S_IT_TXP
+#define I2S_IT_RXNE I2S_IT_RXP
+
+#define I2S_FLAG_TXE I2S_FLAG_TXP
+#define I2S_FLAG_RXNE I2S_FLAG_RXP
+#endif
+
+#if defined(STM32F7)
+#define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+/* Compact Flash-ATA registers description */
+#define CF_DATA ATA_DATA
+#define CF_SECTOR_COUNT ATA_SECTOR_COUNT
+#define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER
+#define CF_CYLINDER_LOW ATA_CYLINDER_LOW
+#define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH
+#define CF_CARD_HEAD ATA_CARD_HEAD
+#define CF_STATUS_CMD ATA_STATUS_CMD
+#define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE
+#define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA
+
+/* Compact Flash-ATA commands */
+#define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD
+#define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD
+#define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD
+#define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD
+
+#define PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef
+#define PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS
+#define PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING
+#define PCCARD_ERROR HAL_PCCARD_STATUS_ERROR
+#define PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT
+/**
+ * @}
+ */
+
+/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define FORMAT_BIN RTC_FORMAT_BIN
+#define FORMAT_BCD RTC_FORMAT_BCD
+
+#define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE
+#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE
+#define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
+#define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
+
+#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
+#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
+#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE
+#define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
+#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
+
+#define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT
+#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1
+#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1
+#define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2
+
+#define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE
+#define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1
+#define RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1
+
+#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT
+#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1
+#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1
+
+#if defined(STM32H7)
+#define RTC_TAMPCR_TAMPXE RTC_TAMPER_X
+#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT
+
+#define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1
+#define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2
+#define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3
+#define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMPALL
+#endif /* STM32H7 */
+
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE
+#define SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE
+
+#define SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE
+#define SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE
+#define SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE
+#define SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE
+
+#define SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE
+#define SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE
+
+#define SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE
+#define SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE
+#define SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE
+#define SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE
+#define SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE
+#define SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE
+#define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE
+#define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE
+#define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE
+#define SMBUS_PEC_DISABLED SMBUS_PEC_DISABLE
+#define SMBUS_PEC_ENABLED SMBUS_PEC_ENABLE
+#define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN
+/**
+ * @}
+ */
+
+/** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE
+#define SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE
+
+#define SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE
+#define SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE
+
+#define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE
+#define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE
+
+#if defined(STM32H7)
+
+#define SPI_FLAG_TXE SPI_FLAG_TXP
+#define SPI_FLAG_RXNE SPI_FLAG_RXP
+
+#define SPI_IT_TXE SPI_IT_TXP
+#define SPI_IT_RXNE SPI_IT_RXP
+
+#define SPI_FRLVL_EMPTY SPI_RX_FIFO_0PACKET
+#define SPI_FRLVL_QUARTER_FULL SPI_RX_FIFO_1PACKET
+#define SPI_FRLVL_HALF_FULL SPI_RX_FIFO_2PACKET
+#define SPI_FRLVL_FULL SPI_RX_FIFO_3PACKET
+
+#endif /* STM32H7 */
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define CCER_CCxE_MASK TIM_CCER_CCxE_MASK
+#define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK
+
+#define TIM_DMABase_CR1 TIM_DMABASE_CR1
+#define TIM_DMABase_CR2 TIM_DMABASE_CR2
+#define TIM_DMABase_SMCR TIM_DMABASE_SMCR
+#define TIM_DMABase_DIER TIM_DMABASE_DIER
+#define TIM_DMABase_SR TIM_DMABASE_SR
+#define TIM_DMABase_EGR TIM_DMABASE_EGR
+#define TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1
+#define TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2
+#define TIM_DMABase_CCER TIM_DMABASE_CCER
+#define TIM_DMABase_CNT TIM_DMABASE_CNT
+#define TIM_DMABase_PSC TIM_DMABASE_PSC
+#define TIM_DMABase_ARR TIM_DMABASE_ARR
+#define TIM_DMABase_RCR TIM_DMABASE_RCR
+#define TIM_DMABase_CCR1 TIM_DMABASE_CCR1
+#define TIM_DMABase_CCR2 TIM_DMABASE_CCR2
+#define TIM_DMABase_CCR3 TIM_DMABASE_CCR3
+#define TIM_DMABase_CCR4 TIM_DMABASE_CCR4
+#define TIM_DMABase_BDTR TIM_DMABASE_BDTR
+#define TIM_DMABase_DCR TIM_DMABASE_DCR
+#define TIM_DMABase_DMAR TIM_DMABASE_DMAR
+#define TIM_DMABase_OR1 TIM_DMABASE_OR1
+#define TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3
+#define TIM_DMABase_CCR5 TIM_DMABASE_CCR5
+#define TIM_DMABase_CCR6 TIM_DMABASE_CCR6
+#define TIM_DMABase_OR2 TIM_DMABASE_OR2
+#define TIM_DMABase_OR3 TIM_DMABASE_OR3
+#define TIM_DMABase_OR TIM_DMABASE_OR
+
+#define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE
+#define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1
+#define TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2
+#define TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3
+#define TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4
+#define TIM_EventSource_COM TIM_EVENTSOURCE_COM
+#define TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER
+#define TIM_EventSource_Break TIM_EVENTSOURCE_BREAK
+#define TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2
+
+#define TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER
+#define TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS
+#define TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS
+#define TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS
+#define TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS
+#define TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS
+#define TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS
+#define TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS
+#define TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS
+#define TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS
+#define TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS
+#define TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS
+#define TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS
+#define TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS
+#define TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS
+#define TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS
+#define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS
+#define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS
+
+#if defined(STM32L0)
+#define TIM22_TI1_GPIO1 TIM22_TI1_GPIO
+#define TIM22_TI1_GPIO2 TIM22_TI1_GPIO
+#endif
+
+#if defined(STM32F3)
+#define IS_TIM_HALL_INTERFACE_INSTANCE IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE
+#endif
+
+#if defined(STM32H7)
+#define TIM_TIM1_ETR_COMP1_OUT TIM_TIM1_ETR_COMP1
+#define TIM_TIM1_ETR_COMP2_OUT TIM_TIM1_ETR_COMP2
+#define TIM_TIM8_ETR_COMP1_OUT TIM_TIM8_ETR_COMP1
+#define TIM_TIM8_ETR_COMP2_OUT TIM_TIM8_ETR_COMP2
+#define TIM_TIM2_ETR_COMP1_OUT TIM_TIM2_ETR_COMP1
+#define TIM_TIM2_ETR_COMP2_OUT TIM_TIM2_ETR_COMP2
+#define TIM_TIM3_ETR_COMP1_OUT TIM_TIM3_ETR_COMP1
+#define TIM_TIM1_TI1_COMP1_OUT TIM_TIM1_TI1_COMP1
+#define TIM_TIM8_TI1_COMP2_OUT TIM_TIM8_TI1_COMP2
+#define TIM_TIM2_TI4_COMP1_OUT TIM_TIM2_TI4_COMP1
+#define TIM_TIM2_TI4_COMP2_OUT TIM_TIM2_TI4_COMP2
+#define TIM_TIM2_TI4_COMP1COMP2_OUT TIM_TIM2_TI4_COMP1_COMP2
+#define TIM_TIM3_TI1_COMP1_OUT TIM_TIM3_TI1_COMP1
+#define TIM_TIM3_TI1_COMP2_OUT TIM_TIM3_TI1_COMP2
+#define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2
+#endif
+
+#if defined(STM32U5) || defined(STM32MP2)
+#define OCREF_CLEAR_SELECT_Pos OCREF_CLEAR_SELECT_POS
+#define OCREF_CLEAR_SELECT_Msk OCREF_CLEAR_SELECT_MSK
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING
+#define TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING
+/**
+ * @}
+ */
+
+/** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE
+#define UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE
+#define UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE
+#define UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE
+
+#define __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE
+#define __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE
+
+#define __DIV_SAMPLING16 UART_DIV_SAMPLING16
+#define __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16
+#define __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16
+#define __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16
+
+#define __DIV_SAMPLING8 UART_DIV_SAMPLING8
+#define __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8
+#define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8
+#define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8
+
+#define __DIV_LPUART UART_DIV_LPUART
+
+#define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE
+#define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK
+
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define USART_CLOCK_DISABLED USART_CLOCK_DISABLE
+#define USART_CLOCK_ENABLED USART_CLOCK_ENABLE
+
+#define USARTNACK_ENABLED USART_NACK_ENABLE
+#define USARTNACK_DISABLED USART_NACK_DISABLE
+/**
+ * @}
+ */
+
+/** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define CFR_BASE WWDG_CFR_BASE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define CAN_FilterFIFO0 CAN_FILTER_FIFO0
+#define CAN_FilterFIFO1 CAN_FILTER_FIFO1
+#define CAN_IT_RQCP0 CAN_IT_TME
+#define CAN_IT_RQCP1 CAN_IT_TME
+#define CAN_IT_RQCP2 CAN_IT_TME
+#define INAK_TIMEOUT CAN_TIMEOUT_VALUE
+#define SLAK_TIMEOUT CAN_TIMEOUT_VALUE
+#define CAN_TXSTATUS_FAILED ((uint8_t)0x00U)
+#define CAN_TXSTATUS_OK ((uint8_t)0x01U)
+#define CAN_TXSTATUS_PENDING ((uint8_t)0x02U)
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define VLAN_TAG ETH_VLAN_TAG
+#define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD
+#define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD
+#define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD
+#define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK
+#define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK
+#define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK
+#define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK
+
+#define ETH_MMCCR 0x00000100U
+#define ETH_MMCRIR 0x00000104U
+#define ETH_MMCTIR 0x00000108U
+#define ETH_MMCRIMR 0x0000010CU
+#define ETH_MMCTIMR 0x00000110U
+#define ETH_MMCTGFSCCR 0x0000014CU
+#define ETH_MMCTGFMSCCR 0x00000150U
+#define ETH_MMCTGFCR 0x00000168U
+#define ETH_MMCRFCECR 0x00000194U
+#define ETH_MMCRFAECR 0x00000198U
+#define ETH_MMCRGUFCR 0x000001C4U
+
+#define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */
+#define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */
+#define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */
+#define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */
+#define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
+#define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
+#define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
+#define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input frame for transmission */
+#define ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U /* MAC MII transmit engine active */
+#define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */
+#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
+#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control activate threshold */
+#define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */
+#if defined(STM32F1)
+#else
+#define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */
+#define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */
+#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status (or time-stamp) */
+#endif
+#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and status */
+#define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */
+#define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */
+#define ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U /* MAC small FIFO read controller active */
+#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE 0x00000004U /* MAC small FIFO write controller active */
+#define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */
+#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define HAL_DCMI_ERROR_OVF HAL_DCMI_ERROR_OVR
+#define DCMI_IT_OVF DCMI_IT_OVR
+#define DCMI_FLAG_OVFRI DCMI_FLAG_OVRRI
+#define DCMI_FLAG_OVFMI DCMI_FLAG_OVRMI
+
+#define HAL_DCMI_ConfigCROP HAL_DCMI_ConfigCrop
+#define HAL_DCMI_EnableCROP HAL_DCMI_EnableCrop
+#define HAL_DCMI_DisableCROP HAL_DCMI_DisableCrop
+
+/**
+ * @}
+ */
+
+#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \
+ || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \
+ || defined(STM32H7)
+/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888
+#define DMA2D_RGB888 DMA2D_OUTPUT_RGB888
+#define DMA2D_RGB565 DMA2D_OUTPUT_RGB565
+#define DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555
+#define DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444
+
+#define CM_ARGB8888 DMA2D_INPUT_ARGB8888
+#define CM_RGB888 DMA2D_INPUT_RGB888
+#define CM_RGB565 DMA2D_INPUT_RGB565
+#define CM_ARGB1555 DMA2D_INPUT_ARGB1555
+#define CM_ARGB4444 DMA2D_INPUT_ARGB4444
+#define CM_L8 DMA2D_INPUT_L8
+#define CM_AL44 DMA2D_INPUT_AL44
+#define CM_AL88 DMA2D_INPUT_AL88
+#define CM_L4 DMA2D_INPUT_L4
+#define CM_A8 DMA2D_INPUT_A8
+#define CM_A4 DMA2D_INPUT_A4
+/**
+ * @}
+ */
+#endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 */
+
+#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \
+ || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \
+ || defined(STM32H7) || defined(STM32U5)
+/** @defgroup DMA2D_Aliases DMA2D API Aliases
+ * @{
+ */
+#define HAL_DMA2D_DisableCLUT HAL_DMA2D_CLUTLoading_Abort /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort
+ for compatibility with legacy code */
+/**
+ * @}
+ */
+
+#endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 || STM32U5 */
+
+/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback
+/**
+ * @}
+ */
+
+/** @defgroup HAL_DCACHE_Aliased_Functions HAL DCACHE Aliased Functions maintained for legacy purpose
+ * @{
+ */
+
+#if defined(STM32U5)
+#define HAL_DCACHE_CleanInvalidateByAddr HAL_DCACHE_CleanInvalidByAddr
+#define HAL_DCACHE_CleanInvalidateByAddr_IT HAL_DCACHE_CleanInvalidByAddr_IT
+#endif /* STM32U5 */
+
+/**
+ * @}
+ */
+
+#if !defined(STM32F2)
+/** @defgroup HASH_alias HASH API alias
+ * @{
+ */
+#define HAL_HASHEx_IRQHandler HAL_HASH_IRQHandler /*!< Redirection for compatibility with legacy code */
+/**
+ *
+ * @}
+ */
+#endif /* STM32F2 */
+/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef
+#define HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef
+#define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish
+#define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish
+#define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish
+#define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish
+
+/*HASH Algorithm Selection*/
+
+#define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1
+#define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224
+#define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256
+#define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5
+
+#define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH
+#define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC
+
+#define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY
+#define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY
+
+#if defined(STM32L4) || defined(STM32L5) || defined(STM32F2) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7)
+
+#define HAL_HASH_MD5_Accumulate HAL_HASH_MD5_Accmlt
+#define HAL_HASH_MD5_Accumulate_End HAL_HASH_MD5_Accmlt_End
+#define HAL_HASH_MD5_Accumulate_IT HAL_HASH_MD5_Accmlt_IT
+#define HAL_HASH_MD5_Accumulate_End_IT HAL_HASH_MD5_Accmlt_End_IT
+
+#define HAL_HASH_SHA1_Accumulate HAL_HASH_SHA1_Accmlt
+#define HAL_HASH_SHA1_Accumulate_End HAL_HASH_SHA1_Accmlt_End
+#define HAL_HASH_SHA1_Accumulate_IT HAL_HASH_SHA1_Accmlt_IT
+#define HAL_HASH_SHA1_Accumulate_End_IT HAL_HASH_SHA1_Accmlt_End_IT
+
+#define HAL_HASHEx_SHA224_Accumulate HAL_HASHEx_SHA224_Accmlt
+#define HAL_HASHEx_SHA224_Accumulate_End HAL_HASHEx_SHA224_Accmlt_End
+#define HAL_HASHEx_SHA224_Accumulate_IT HAL_HASHEx_SHA224_Accmlt_IT
+#define HAL_HASHEx_SHA224_Accumulate_End_IT HAL_HASHEx_SHA224_Accmlt_End_IT
+
+#define HAL_HASHEx_SHA256_Accumulate HAL_HASHEx_SHA256_Accmlt
+#define HAL_HASHEx_SHA256_Accumulate_End HAL_HASHEx_SHA256_Accmlt_End
+#define HAL_HASHEx_SHA256_Accumulate_IT HAL_HASHEx_SHA256_Accmlt_IT
+#define HAL_HASHEx_SHA256_Accumulate_End_IT HAL_HASHEx_SHA256_Accmlt_End_IT
+
+#endif /* STM32L4 || STM32L5 || STM32F2 || STM32F4 || STM32F7 || STM32H7 */
+/**
+ * @}
+ */
+
+/** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode
+#define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode
+#define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode
+#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode
+#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode
+#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode
+#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd\
+ )==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
+#define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect
+#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())
+#if defined(STM32L0)
+#else
+#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())
+#endif
+#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
+#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd\
+ )==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
+#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ)
+#define HAL_EnableSRDomainDBGStopMode HAL_EnableDomain3DBGStopMode
+#define HAL_DisableSRDomainDBGStopMode HAL_DisableDomain3DBGStopMode
+#define HAL_EnableSRDomainDBGStandbyMode HAL_EnableDomain3DBGStandbyMode
+#define HAL_DisableSRDomainDBGStandbyMode HAL_DisableDomain3DBGStandbyMode
+#endif /* STM32H7A3xx || STM32H7B3xx || STM32H7B0xx || STM32H7A3xxQ || STM32H7B3xxQ || STM32H7B0xxQ */
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram
+#define FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown
+#define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown
+#define HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock
+#define HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock
+#define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase
+#define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter
+#define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter
+#define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter
+#define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter
+
+#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd\
+ )==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
+
+#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1)
+#define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT
+#define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT
+#define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT
+#define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT
+#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */
+#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1)
+#define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA
+#define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA
+#define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA
+#define HAL_I2C_Slave_Sequential_Receive_DMA HAL_I2C_Slave_Seq_Receive_DMA
+#endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */
+
+#if defined(STM32F4)
+#define HAL_FMPI2C_Master_Sequential_Transmit_IT HAL_FMPI2C_Master_Seq_Transmit_IT
+#define HAL_FMPI2C_Master_Sequential_Receive_IT HAL_FMPI2C_Master_Seq_Receive_IT
+#define HAL_FMPI2C_Slave_Sequential_Transmit_IT HAL_FMPI2C_Slave_Seq_Transmit_IT
+#define HAL_FMPI2C_Slave_Sequential_Receive_IT HAL_FMPI2C_Slave_Seq_Receive_IT
+#define HAL_FMPI2C_Master_Sequential_Transmit_DMA HAL_FMPI2C_Master_Seq_Transmit_DMA
+#define HAL_FMPI2C_Master_Sequential_Receive_DMA HAL_FMPI2C_Master_Seq_Receive_DMA
+#define HAL_FMPI2C_Slave_Sequential_Transmit_DMA HAL_FMPI2C_Slave_Seq_Transmit_DMA
+#define HAL_FMPI2C_Slave_Sequential_Receive_DMA HAL_FMPI2C_Slave_Seq_Receive_DMA
+#endif /* STM32F4 */
+/**
+ * @}
+ */
+
+/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose
+ * @{
+ */
+
+#if defined(STM32G0)
+#define HAL_PWR_ConfigPVD HAL_PWREx_ConfigPVD
+#define HAL_PWR_EnablePVD HAL_PWREx_EnablePVD
+#define HAL_PWR_DisablePVD HAL_PWREx_DisablePVD
+#define HAL_PWR_PVD_IRQHandler HAL_PWREx_PVD_IRQHandler
+#endif
+#define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD
+#define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg
+#define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown
+#define HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor
+#define HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg
+#define HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown
+#define HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor
+#define HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler
+#define HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD
+#define HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler
+#define HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback
+#define HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive
+#define HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive
+#define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC
+#define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC
+#define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM
+
+#define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL
+#define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING
+#define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING
+#define PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING
+#define PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING
+#define PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING
+#define PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING
+
+#define CR_OFFSET_BB PWR_CR_OFFSET_BB
+#define CSR_OFFSET_BB PWR_CSR_OFFSET_BB
+#define PMODE_BIT_NUMBER VOS_BIT_NUMBER
+#define CR_PMODE_BB CR_VOS_BB
+
+#define DBP_BitNumber DBP_BIT_NUMBER
+#define PVDE_BitNumber PVDE_BIT_NUMBER
+#define PMODE_BitNumber PMODE_BIT_NUMBER
+#define EWUP_BitNumber EWUP_BIT_NUMBER
+#define FPDS_BitNumber FPDS_BIT_NUMBER
+#define ODEN_BitNumber ODEN_BIT_NUMBER
+#define ODSWEN_BitNumber ODSWEN_BIT_NUMBER
+#define MRLVDS_BitNumber MRLVDS_BIT_NUMBER
+#define LPLVDS_BitNumber LPLVDS_BIT_NUMBER
+#define BRE_BitNumber BRE_BIT_NUMBER
+
+#define PWR_MODE_EVT PWR_PVD_MODE_NORMAL
+
+#if defined (STM32U5)
+#define PWR_SRAM1_PAGE1_STOP_RETENTION PWR_SRAM1_PAGE1_STOP
+#define PWR_SRAM1_PAGE2_STOP_RETENTION PWR_SRAM1_PAGE2_STOP
+#define PWR_SRAM1_PAGE3_STOP_RETENTION PWR_SRAM1_PAGE3_STOP
+#define PWR_SRAM1_PAGE4_STOP_RETENTION PWR_SRAM1_PAGE4_STOP
+#define PWR_SRAM1_PAGE5_STOP_RETENTION PWR_SRAM1_PAGE5_STOP
+#define PWR_SRAM1_PAGE6_STOP_RETENTION PWR_SRAM1_PAGE6_STOP
+#define PWR_SRAM1_PAGE7_STOP_RETENTION PWR_SRAM1_PAGE7_STOP
+#define PWR_SRAM1_PAGE8_STOP_RETENTION PWR_SRAM1_PAGE8_STOP
+#define PWR_SRAM1_PAGE9_STOP_RETENTION PWR_SRAM1_PAGE9_STOP
+#define PWR_SRAM1_PAGE10_STOP_RETENTION PWR_SRAM1_PAGE10_STOP
+#define PWR_SRAM1_PAGE11_STOP_RETENTION PWR_SRAM1_PAGE11_STOP
+#define PWR_SRAM1_PAGE12_STOP_RETENTION PWR_SRAM1_PAGE12_STOP
+#define PWR_SRAM1_FULL_STOP_RETENTION PWR_SRAM1_FULL_STOP
+
+#define PWR_SRAM2_PAGE1_STOP_RETENTION PWR_SRAM2_PAGE1_STOP
+#define PWR_SRAM2_PAGE2_STOP_RETENTION PWR_SRAM2_PAGE2_STOP
+#define PWR_SRAM2_FULL_STOP_RETENTION PWR_SRAM2_FULL_STOP
+
+#define PWR_SRAM3_PAGE1_STOP_RETENTION PWR_SRAM3_PAGE1_STOP
+#define PWR_SRAM3_PAGE2_STOP_RETENTION PWR_SRAM3_PAGE2_STOP
+#define PWR_SRAM3_PAGE3_STOP_RETENTION PWR_SRAM3_PAGE3_STOP
+#define PWR_SRAM3_PAGE4_STOP_RETENTION PWR_SRAM3_PAGE4_STOP
+#define PWR_SRAM3_PAGE5_STOP_RETENTION PWR_SRAM3_PAGE5_STOP
+#define PWR_SRAM3_PAGE6_STOP_RETENTION PWR_SRAM3_PAGE6_STOP
+#define PWR_SRAM3_PAGE7_STOP_RETENTION PWR_SRAM3_PAGE7_STOP
+#define PWR_SRAM3_PAGE8_STOP_RETENTION PWR_SRAM3_PAGE8_STOP
+#define PWR_SRAM3_PAGE9_STOP_RETENTION PWR_SRAM3_PAGE9_STOP
+#define PWR_SRAM3_PAGE10_STOP_RETENTION PWR_SRAM3_PAGE10_STOP
+#define PWR_SRAM3_PAGE11_STOP_RETENTION PWR_SRAM3_PAGE11_STOP
+#define PWR_SRAM3_PAGE12_STOP_RETENTION PWR_SRAM3_PAGE12_STOP
+#define PWR_SRAM3_PAGE13_STOP_RETENTION PWR_SRAM3_PAGE13_STOP
+#define PWR_SRAM3_FULL_STOP_RETENTION PWR_SRAM3_FULL_STOP
+
+#define PWR_SRAM4_FULL_STOP_RETENTION PWR_SRAM4_FULL_STOP
+
+#define PWR_SRAM5_PAGE1_STOP_RETENTION PWR_SRAM5_PAGE1_STOP
+#define PWR_SRAM5_PAGE2_STOP_RETENTION PWR_SRAM5_PAGE2_STOP
+#define PWR_SRAM5_PAGE3_STOP_RETENTION PWR_SRAM5_PAGE3_STOP
+#define PWR_SRAM5_PAGE4_STOP_RETENTION PWR_SRAM5_PAGE4_STOP
+#define PWR_SRAM5_PAGE5_STOP_RETENTION PWR_SRAM5_PAGE5_STOP
+#define PWR_SRAM5_PAGE6_STOP_RETENTION PWR_SRAM5_PAGE6_STOP
+#define PWR_SRAM5_PAGE7_STOP_RETENTION PWR_SRAM5_PAGE7_STOP
+#define PWR_SRAM5_PAGE8_STOP_RETENTION PWR_SRAM5_PAGE8_STOP
+#define PWR_SRAM5_PAGE9_STOP_RETENTION PWR_SRAM5_PAGE9_STOP
+#define PWR_SRAM5_PAGE10_STOP_RETENTION PWR_SRAM5_PAGE10_STOP
+#define PWR_SRAM5_PAGE11_STOP_RETENTION PWR_SRAM5_PAGE11_STOP
+#define PWR_SRAM5_PAGE12_STOP_RETENTION PWR_SRAM5_PAGE12_STOP
+#define PWR_SRAM5_PAGE13_STOP_RETENTION PWR_SRAM5_PAGE13_STOP
+#define PWR_SRAM5_FULL_STOP_RETENTION PWR_SRAM5_FULL_STOP
+
+#define PWR_ICACHE_FULL_STOP_RETENTION PWR_ICACHE_FULL_STOP
+#define PWR_DCACHE1_FULL_STOP_RETENTION PWR_DCACHE1_FULL_STOP
+#define PWR_DCACHE2_FULL_STOP_RETENTION PWR_DCACHE2_FULL_STOP
+#define PWR_DMA2DRAM_FULL_STOP_RETENTION PWR_DMA2DRAM_FULL_STOP
+#define PWR_PERIPHRAM_FULL_STOP_RETENTION PWR_PERIPHRAM_FULL_STOP
+#define PWR_PKA32RAM_FULL_STOP_RETENTION PWR_PKA32RAM_FULL_STOP
+#define PWR_GRAPHICPRAM_FULL_STOP_RETENTION PWR_GRAPHICPRAM_FULL_STOP
+#define PWR_DSIRAM_FULL_STOP_RETENTION PWR_DSIRAM_FULL_STOP
+
+#define PWR_SRAM2_PAGE1_STANDBY_RETENTION PWR_SRAM2_PAGE1_STANDBY
+#define PWR_SRAM2_PAGE2_STANDBY_RETENTION PWR_SRAM2_PAGE2_STANDBY
+#define PWR_SRAM2_FULL_STANDBY_RETENTION PWR_SRAM2_FULL_STANDBY
+
+#define PWR_SRAM1_FULL_RUN_RETENTION PWR_SRAM1_FULL_RUN
+#define PWR_SRAM2_FULL_RUN_RETENTION PWR_SRAM2_FULL_RUN
+#define PWR_SRAM3_FULL_RUN_RETENTION PWR_SRAM3_FULL_RUN
+#define PWR_SRAM4_FULL_RUN_RETENTION PWR_SRAM4_FULL_RUN
+#define PWR_SRAM5_FULL_RUN_RETENTION PWR_SRAM5_FULL_RUN
+
+#define PWR_ALL_RAM_RUN_RETENTION_MASK PWR_ALL_RAM_RUN_MASK
+#endif
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT
+#define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback
+#define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback
+/**
+ * @}
+ */
+
+/** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo
+/**
+ * @}
+ */
+
+/** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt
+#define HAL_TIM_DMAError TIM_DMAError
+#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt
+#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt
+#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4)
+#define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro
+#define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT
+#define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback
+#define HAL_TIMEx_ConfigCommutationEvent HAL_TIMEx_ConfigCommutEvent
+#define HAL_TIMEx_ConfigCommutationEvent_IT HAL_TIMEx_ConfigCommutEvent_IT
+#define HAL_TIMEx_ConfigCommutationEvent_DMA HAL_TIMEx_ConfigCommutEvent_DMA
+#endif /* STM32H7 || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 */
+/**
+ * @}
+ */
+
+/** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback
+/**
+ * @}
+ */
+
+/** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback
+#define HAL_LTDC_Relaod HAL_LTDC_Reload
+#define HAL_LTDC_StructInitFromVideoConfig HAL_LTDCEx_StructInitFromVideoConfig
+#define HAL_LTDC_StructInitFromAdaptedCommandConfig HAL_LTDCEx_StructInitFromAdaptedCommandConfig
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros ------------------------------------------------------------*/
+
+/** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define AES_IT_CC CRYP_IT_CC
+#define AES_IT_ERR CRYP_IT_ERR
+#define AES_FLAG_CCF CRYP_FLAG_CCF
+/**
+ * @}
+ */
+
+/** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE
+#define __HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH
+#define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH
+#define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM
+#define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC
+#define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM
+#define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC
+#define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI
+#define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK
+#define __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG
+#define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG
+#define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE
+#define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE
+#define __HAL_SYSCFG_SRAM2_WRP_ENABLE __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE
+
+#define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY
+#define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48
+#define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS
+#define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER
+#define CMP_PD_BitNumber CMP_PD_BIT_NUMBER
+
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __ADC_ENABLE __HAL_ADC_ENABLE
+#define __ADC_DISABLE __HAL_ADC_DISABLE
+#define __HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS
+#define __HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS
+#define __HAL_ADC_IS_ENABLED ADC_IS_ENABLE
+#define __ADC_IS_ENABLED ADC_IS_ENABLE
+#define __HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR
+#define __HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED
+#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED
+#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULAR
+#define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTED
+#define __HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING
+#define __HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE
+
+#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION
+#define __HAL_ADC_JSQR_RK ADC_JSQR_RK
+#define __HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT
+#define __HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR
+#define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION
+#define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE
+#define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS
+#define __HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS
+#define __HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM
+#define __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT
+#define __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS
+#define __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN
+#define __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ
+#define __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET
+#define __HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET
+#define __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL
+#define __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL
+#define __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET
+#define __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET
+#define __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD
+
+#define __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION
+#define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTION
+#define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION
+#define __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER
+#define __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI
+#define __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE
+#define __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE
+#define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER
+#define __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER
+#define __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE
+
+#define __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT
+#define __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT
+#define __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL
+#define __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM
+#define __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET
+#define __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE
+#define __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE
+#define __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER
+
+#define __HAL_ADC_SQR1 ADC_SQR1
+#define __HAL_ADC_SMPR1 ADC_SMPR1
+#define __HAL_ADC_SMPR2 ADC_SMPR2
+#define __HAL_ADC_SQR3_RK ADC_SQR3_RK
+#define __HAL_ADC_SQR2_RK ADC_SQR2_RK
+#define __HAL_ADC_SQR1_RK ADC_SQR1_RK
+#define __HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS
+#define __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS
+#define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV
+#define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection
+#define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq
+#define __HAL_ADC_JSQR ADC_JSQR
+
+#define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL
+#define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS
+#define __HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF
+#define __HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT
+#define __HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS
+#define __HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN
+#define __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR
+#define __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT
+#define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT
+#define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT
+#define IS_DAC_GENERATE_WAVE IS_DAC_WAVE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1
+#define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1
+#define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2
+#define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2
+#define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3
+#define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3
+#define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4
+#define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4
+#define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5
+#define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5
+#define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6
+#define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6
+#define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7
+#define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7
+#define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8
+#define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8
+
+#define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9
+#define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9
+#define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10
+#define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10
+#define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11
+#define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11
+#define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12
+#define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12
+#define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13
+#define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13
+#define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14
+#define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14
+#define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2
+#define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2
+
+
+#define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15
+#define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15
+#define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16
+#define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16
+#define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17
+#define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17
+#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC
+#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC
+#if defined(STM32H7)
+#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1
+#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1
+#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1
+#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1
+#else
+#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG
+#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG
+#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG
+#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG
+#endif /* STM32H7 */
+#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT
+#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT
+#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT
+#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT
+#define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT
+#define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT
+#define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1
+#define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1
+#define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1
+#define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1
+#define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2
+#define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#if defined(STM32F3)
+#define COMP_START __HAL_COMP_ENABLE
+#define COMP_STOP __HAL_COMP_DISABLE
+#define COMP_LOCK __HAL_COMP_LOCK
+
+#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
+ __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
+ __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
+ __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
+ __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
+ __HAL_COMP_COMP6_EXTI_ENABLE_IT())
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
+ __HAL_COMP_COMP6_EXTI_DISABLE_IT())
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
+ __HAL_COMP_COMP6_EXTI_GET_FLAG())
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
+ __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
+# endif
+# if defined(STM32F302xE) || defined(STM32F302xC)
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
+ __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
+ __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
+ __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
+ __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
+ __HAL_COMP_COMP6_EXTI_ENABLE_IT())
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
+ __HAL_COMP_COMP6_EXTI_DISABLE_IT())
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
+ __HAL_COMP_COMP6_EXTI_GET_FLAG())
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
+ __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
+# endif
+# if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \
+ __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \
+ __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \
+ __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \
+ __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \
+ __HAL_COMP_COMP7_EXTI_ENABLE_IT())
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \
+ __HAL_COMP_COMP7_EXTI_DISABLE_IT())
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \
+ __HAL_COMP_COMP7_EXTI_GET_FLAG())
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \
+ __HAL_COMP_COMP7_EXTI_CLEAR_FLAG())
+# endif
+# if defined(STM32F373xC) ||defined(STM32F378xx)
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
+ __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
+ __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
+ __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
+ __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
+ __HAL_COMP_COMP2_EXTI_ENABLE_IT())
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
+ __HAL_COMP_COMP2_EXTI_DISABLE_IT())
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
+ __HAL_COMP_COMP2_EXTI_GET_FLAG())
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
+ __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
+# endif
+#else
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
+ __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
+ __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
+ __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
+ __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
+ __HAL_COMP_COMP2_EXTI_ENABLE_IT())
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
+ __HAL_COMP_COMP2_EXTI_DISABLE_IT())
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
+ __HAL_COMP_COMP2_EXTI_GET_FLAG())
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
+ __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
+#endif
+
+#define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE
+
+#if defined(STM32L0) || defined(STM32L4)
+/* Note: On these STM32 families, the only argument of this macro */
+/* is COMP_FLAG_LOCK. */
+/* This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle */
+/* argument. */
+#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_COMP_IS_LOCKED(__HANDLE__))
+#endif
+/**
+ * @}
+ */
+
+#if defined(STM32L0) || defined(STM32L4)
+/** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
+#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
+/**
+ * @}
+ */
+#endif
+
+/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \
+ ((WAVE) == DAC_WAVE_NOISE)|| \
+ ((WAVE) == DAC_WAVE_TRIANGLE))
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define IS_WRPAREA IS_OB_WRPAREA
+#define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM
+#define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM
+#define IS_TYPEERASE IS_FLASH_TYPEERASE
+#define IS_NBSECTORS IS_FLASH_NBSECTORS
+#define IS_OB_WDG_SOURCE IS_OB_IWDG_SOURCE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define __HAL_I2C_RESET_CR2 I2C_RESET_CR2
+#define __HAL_I2C_GENERATE_START I2C_GENERATE_START
+#if defined(STM32F1)
+#define __HAL_I2C_FREQ_RANGE I2C_FREQRANGE
+#else
+#define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE
+#endif /* STM32F1 */
+#define __HAL_I2C_RISE_TIME I2C_RISE_TIME
+#define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD
+#define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST
+#define __HAL_I2C_SPEED I2C_SPEED
+#define __HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE
+#define __HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ
+#define __HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS
+#define __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE
+#define __HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ
+#define __HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB
+#define __HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB
+#define __HAL_I2C_FREQRANGE I2C_FREQRANGE
+/**
+ * @}
+ */
+
+/** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE
+#define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT
+
+#if defined(STM32H7)
+#define __HAL_I2S_CLEAR_FREFLAG __HAL_I2S_CLEAR_TIFREFLAG
+#endif
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define __IRDA_DISABLE __HAL_IRDA_DISABLE
+#define __IRDA_ENABLE __HAL_IRDA_ENABLE
+
+#define __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE
+#define __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION
+#define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE
+#define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION
+
+#define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE
+
+
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS
+#define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define __HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT
+#define __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT
+#define __HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE
+
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __OPAMP_CSR_OPAXPD OPAMP_CSR_OPAXPD
+#define __OPAMP_CSR_S3SELX OPAMP_CSR_S3SELX
+#define __OPAMP_CSR_S4SELX OPAMP_CSR_S4SELX
+#define __OPAMP_CSR_S5SELX OPAMP_CSR_S5SELX
+#define __OPAMP_CSR_S6SELX OPAMP_CSR_S6SELX
+#define __OPAMP_CSR_OPAXCAL_L OPAMP_CSR_OPAXCAL_L
+#define __OPAMP_CSR_OPAXCAL_H OPAMP_CSR_OPAXCAL_H
+#define __OPAMP_CSR_OPAXLPM OPAMP_CSR_OPAXLPM
+#define __OPAMP_CSR_ALL_SWITCHES OPAMP_CSR_ALL_SWITCHES
+#define __OPAMP_CSR_ANAWSELX OPAMP_CSR_ANAWSELX
+#define __OPAMP_CSR_OPAXCALOUT OPAMP_CSR_OPAXCALOUT
+#define __OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION
+#define __OPAMP_OFFSET_TRIM_SET OPAMP_OFFSET_TRIM_SET
+
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
+#define __HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
+#define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
+#define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
+#define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
+#define __HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE
+#define __HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE
+#define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE
+#define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE
+#define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE
+#define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE
+#define __HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine
+#define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine
+#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig
+#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig
+#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0)
+#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
+#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
+#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
+#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
+#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
+#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
+#define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0)
+#define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0)
+#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention
+#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention
+#define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2
+#define __HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2
+#define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE
+#define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB
+#define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB
+
+#if defined (STM32F4)
+#define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT()
+#define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT()
+#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG()
+#define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG()
+#define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT()
+#else
+#define __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG
+#define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT
+#define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT
+#define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT
+#define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG
+#endif /* STM32F4 */
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose
+ * @{
+ */
+
+#define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI
+#define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI
+
+#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback
+#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd\
+ )==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
+
+#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE
+#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE
+#define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE
+#define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE
+#define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET
+#define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET
+#define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE
+#define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE
+#define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET
+#define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET
+#define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE
+#define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE
+#define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE
+#define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE
+#define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET
+#define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET
+#define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE
+#define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE
+#define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET
+#define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET
+#define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE
+#define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE
+#define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE
+#define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE
+#define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET
+#define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET
+#define __CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE
+#define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE
+#define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE
+#define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE
+#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET
+#define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET
+#define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE
+#define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE
+#define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET
+#define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET
+#define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET
+#define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET
+#define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET
+#define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET
+#define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET
+#define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET
+#define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET
+#define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET
+#define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET
+#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET
+#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET
+#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET
+#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE
+#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE
+#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET
+#define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET
+#define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
+#define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
+#define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE
+#define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE
+#define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
+#define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
+#define __CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
+#define __CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
+#define __CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
+#define __CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
+#define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE
+#define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE
+#define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET
+#define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET
+#define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE
+#define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE
+#define __COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE
+#define __COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE
+#define __COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET
+#define __COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET
+#define __COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE
+#define __COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLE
+#define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET
+#define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET
+#define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE
+#define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE
+#define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE
+#define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE
+#define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET
+#define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET
+#define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE
+#define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE
+#define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET
+#define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET
+#define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE
+#define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE
+#define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE
+#define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE
+#define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET
+#define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET
+#define __DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLE
+#define __DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLE
+#define __DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESET
+#define __DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESET
+#define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE
+#define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE
+#define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE
+#define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE
+#define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET
+#define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET
+#define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE
+#define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE
+#define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE
+#define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE
+#define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET
+#define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET
+#define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE
+#define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE
+#define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE
+#define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE
+#define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET
+#define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET
+#define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE
+#define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE
+#define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET
+#define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET
+#define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE
+#define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE
+#define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE
+#define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE
+#define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE
+#define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE
+#define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE
+#define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE
+#define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE
+#define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE
+#define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET
+#define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET
+#define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE
+#define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE
+#define __FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESET
+#define __FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESET
+#define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE
+#define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE
+#define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE
+#define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE
+#define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE
+#define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE
+#define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET
+#define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET
+#define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE
+#define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE
+#define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE
+#define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE
+#define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE
+#define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE
+#define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET
+#define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET
+#define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE
+#define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE
+#define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE
+#define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE
+#define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET
+#define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET
+#define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE
+#define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE
+#define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE
+#define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE
+#define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET
+#define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET
+#define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE
+#define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE
+#define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE
+#define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE
+#define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET
+#define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET
+#define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE
+#define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE
+#define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE
+#define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE
+#define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET
+#define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET
+#define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE
+#define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE
+#define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE
+#define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE
+#define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET
+#define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET
+#define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE
+#define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE
+#define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE
+#define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE
+#define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET
+#define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET
+#define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE
+#define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE
+#define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE
+#define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE
+#define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET
+#define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET
+#define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE
+#define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE
+#define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE
+#define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE
+#define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET
+#define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET
+#define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE
+#define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE
+#define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE
+#define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE
+#define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET
+#define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET
+#define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE
+#define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE
+#define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE
+#define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE
+#define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET
+#define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET
+#define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE
+#define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE
+#define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE
+#define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE
+#define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET
+#define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET
+#define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE
+#define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE
+#define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE
+#define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE
+#define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET
+#define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET
+#define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE
+#define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE
+#define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE
+#define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE
+#define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET
+#define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET
+#define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE
+#define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE
+#define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE
+#define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE
+#define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET
+#define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET
+#define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE
+#define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE
+#define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE
+#define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE
+#define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET
+#define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET
+#define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE
+#define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE
+#define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE
+#define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE
+#define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET
+#define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET
+#define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE
+#define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE
+#define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE
+#define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE
+#define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET
+#define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET
+#define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE
+#define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE
+#define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE
+#define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE
+#define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET
+#define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET
+
+#if defined(STM32WB)
+#define __HAL_RCC_QSPI_CLK_DISABLE __HAL_RCC_QUADSPI_CLK_DISABLE
+#define __HAL_RCC_QSPI_CLK_ENABLE __HAL_RCC_QUADSPI_CLK_ENABLE
+#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE
+#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE
+#define __HAL_RCC_QSPI_FORCE_RESET __HAL_RCC_QUADSPI_FORCE_RESET
+#define __HAL_RCC_QSPI_RELEASE_RESET __HAL_RCC_QUADSPI_RELEASE_RESET
+#define __HAL_RCC_QSPI_IS_CLK_ENABLED __HAL_RCC_QUADSPI_IS_CLK_ENABLED
+#define __HAL_RCC_QSPI_IS_CLK_DISABLED __HAL_RCC_QUADSPI_IS_CLK_DISABLED
+#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED
+#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED
+#define QSPI_IRQHandler QUADSPI_IRQHandler
+#endif /* __HAL_RCC_QUADSPI_CLK_ENABLE */
+
+#define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE
+#define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE
+#define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE
+#define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE
+#define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET
+#define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET
+#define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE
+#define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE
+#define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE
+#define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE
+#define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET
+#define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET
+#define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE
+#define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE
+#define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE
+#define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE
+#define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET
+#define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET
+#define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
+#define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
+#define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE
+#define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE
+#define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE
+#define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE
+#define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET
+#define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET
+#define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE
+#define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE
+#define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE
+#define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE
+#define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET
+#define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET
+#define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE
+#define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE
+#define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE
+#define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE
+#define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET
+#define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET
+#define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE
+#define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE
+#define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE
+#define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE
+#define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET
+#define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET
+#define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE
+#define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE
+#define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE
+#define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE
+#define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE
+#define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE
+#define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE
+#define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE
+#define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE
+#define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE
+#define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET
+#define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET
+#define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE
+#define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE
+#define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE
+#define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE
+#define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET
+#define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET
+#define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE
+#define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE
+#define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE
+#define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE
+#define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET
+#define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET
+#define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE
+#define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE
+#define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET
+#define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET
+#define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE
+#define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE
+#define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET
+#define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET
+#define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE
+#define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE
+#define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET
+#define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET
+#define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE
+#define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE
+#define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET
+#define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET
+#define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE
+#define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE
+#define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET
+#define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET
+#define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE
+#define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE
+#define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE
+#define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE
+#define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET
+#define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET
+#define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE
+#define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE
+#define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE
+#define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE
+#define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET
+#define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET
+#define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE
+#define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE
+#define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE
+#define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE
+#define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET
+#define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET
+#define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE
+#define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE
+#define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE
+#define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE
+#define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET
+#define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET
+#define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE
+#define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE
+#define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE
+#define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE
+#define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET
+#define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET
+#define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE
+#define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE
+#define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE
+#define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE
+#define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET
+#define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET
+#define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE
+#define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE
+#define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE
+#define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE
+#define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET
+#define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET
+#define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE
+#define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE
+#define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE
+#define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE
+#define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET
+#define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET
+#define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE
+#define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE
+#define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE
+#define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE
+#define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET
+#define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET
+#define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE
+#define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE
+#define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE
+#define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE
+#define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET
+#define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET
+#define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE
+#define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE
+#define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET
+#define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET
+#define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE
+#define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE
+#define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE
+#define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE
+#define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET
+#define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET
+#define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE
+#define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE
+#define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE
+#define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE
+#define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET
+#define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET
+#define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE
+#define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE
+#define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE
+#define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE
+#define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET
+#define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET
+#define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE
+#define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE
+#define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE
+#define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE
+#define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET
+#define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET
+#define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE
+#define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE
+#define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE
+#define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE
+#define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET
+#define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET
+#define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE
+#define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE
+#define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE
+#define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE
+#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET
+#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET
+#define __USART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE
+#define __USART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE
+#define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE
+#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE
+#define __USART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET
+#define __USART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET
+#define __USART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE
+#define __USART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE
+#define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE
+#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE
+#define __USART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET
+#define __USART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET
+#define __USART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE
+#define __USART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE
+#define __USART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET
+#define __USART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET
+#define __USART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE
+#define __USART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE
+#define __USART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET
+#define __USART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET
+#define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE
+#define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE
+#define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET
+#define __USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE
+#define __USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE
+#define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE
+#define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE
+#define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET
+
+#if defined(STM32H7)
+#define __HAL_RCC_WWDG_CLK_DISABLE __HAL_RCC_WWDG1_CLK_DISABLE
+#define __HAL_RCC_WWDG_CLK_ENABLE __HAL_RCC_WWDG1_CLK_ENABLE
+#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE
+#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE
+
+#define __HAL_RCC_WWDG_FORCE_RESET ((void)0U) /* Not available on the STM32H7*/
+#define __HAL_RCC_WWDG_RELEASE_RESET ((void)0U) /* Not available on the STM32H7*/
+
+
+#define __HAL_RCC_WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG1_IS_CLK_ENABLED
+#define __HAL_RCC_WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG1_IS_CLK_DISABLED
+#endif
+
+#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE
+#define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE
+#define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE
+#define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE
+#define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET
+#define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET
+
+#define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE
+#define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE
+#define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET
+#define __TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET
+#define __TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE
+#define __TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE
+#define __TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE
+#define __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE
+#define __TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET
+#define __TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET
+#define __TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE
+#define __TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE
+#define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE
+#define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE
+#define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE
+#define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE
+#define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET
+#define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET
+#define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE
+#define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE
+
+#define __USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET
+#define __USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET
+#define __USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE
+#define __USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE
+#define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE
+#define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE
+#define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE
+#define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE
+#define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE
+#define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE
+#define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE
+#define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE
+#define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE
+#define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE
+#define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE
+#define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE
+#define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE
+#define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE
+#define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE
+#define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET
+#define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET
+#define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE
+#define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE
+#define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE
+#define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE
+#define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE
+#define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET
+#define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET
+#define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE
+#define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE
+#define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE
+#define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE
+#define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET
+#define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET
+#define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE
+#define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE
+#define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE
+#define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE
+#define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET
+#define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET
+#define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE
+#define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE
+#define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE
+#define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE
+#define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE
+#define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE
+#define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE
+#define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE
+#define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE
+#define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE
+#define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE
+#define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE
+#define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE
+#define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE
+#define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE
+#define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE
+#define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE
+#define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE
+#define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE
+#define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE
+#define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE
+#define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET
+#define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET
+#define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE
+#define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE
+#define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE
+#define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE
+#define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET
+#define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET
+#define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE
+#define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE
+#define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE
+#define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE
+#define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET
+#define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET
+#define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE
+#define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE
+#define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE
+#define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE
+#define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET
+#define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET
+#define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE
+#define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE
+#define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE
+#define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE
+#define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET
+#define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE
+#define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE
+#define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE
+#define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE
+#define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE
+#define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE
+#define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET
+#define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET
+#define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE
+#define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE
+#define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE
+#define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE
+#define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET
+#define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET
+#define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE
+#define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE
+#define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE
+#define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE
+#define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET
+#define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET
+#define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE
+#define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE
+#define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
+#define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
+#define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET
+#define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET
+#define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
+#define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
+#define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
+#define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
+#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED
+#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED
+#define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET
+#define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET
+#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
+#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
+#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED
+#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED
+#define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE
+#define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE
+#define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE
+#define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE
+#define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE
+#define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE
+#define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE
+#define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE
+#define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE
+#define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET
+#define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET
+#define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE
+#define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE
+#define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET
+#define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET
+#define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
+#define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
+#define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE
+#define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE
+#define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET
+#define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET
+#define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE
+#define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE
+
+/* alias define maintained for legacy */
+#define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET
+#define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET
+
+#define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
+#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
+#define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE
+#define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE
+#define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE
+#define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE
+#define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE
+#define __TIM18_CLK_DISABLE __HAL_RCC_TIM18_CLK_DISABLE
+#define __TIM19_CLK_ENABLE __HAL_RCC_TIM19_CLK_ENABLE
+#define __TIM19_CLK_DISABLE __HAL_RCC_TIM19_CLK_DISABLE
+#define __TIM20_CLK_ENABLE __HAL_RCC_TIM20_CLK_ENABLE
+#define __TIM20_CLK_DISABLE __HAL_RCC_TIM20_CLK_DISABLE
+#define __HRTIM1_CLK_ENABLE __HAL_RCC_HRTIM1_CLK_ENABLE
+#define __HRTIM1_CLK_DISABLE __HAL_RCC_HRTIM1_CLK_DISABLE
+#define __SDADC1_CLK_ENABLE __HAL_RCC_SDADC1_CLK_ENABLE
+#define __SDADC2_CLK_ENABLE __HAL_RCC_SDADC2_CLK_ENABLE
+#define __SDADC3_CLK_ENABLE __HAL_RCC_SDADC3_CLK_ENABLE
+#define __SDADC1_CLK_DISABLE __HAL_RCC_SDADC1_CLK_DISABLE
+#define __SDADC2_CLK_DISABLE __HAL_RCC_SDADC2_CLK_DISABLE
+#define __SDADC3_CLK_DISABLE __HAL_RCC_SDADC3_CLK_DISABLE
+
+#define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
+#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
+#define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET
+#define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET
+#define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET
+#define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET
+#define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET
+#define __TIM18_RELEASE_RESET __HAL_RCC_TIM18_RELEASE_RESET
+#define __TIM19_FORCE_RESET __HAL_RCC_TIM19_FORCE_RESET
+#define __TIM19_RELEASE_RESET __HAL_RCC_TIM19_RELEASE_RESET
+#define __TIM20_FORCE_RESET __HAL_RCC_TIM20_FORCE_RESET
+#define __TIM20_RELEASE_RESET __HAL_RCC_TIM20_RELEASE_RESET
+#define __HRTIM1_FORCE_RESET __HAL_RCC_HRTIM1_FORCE_RESET
+#define __HRTIM1_RELEASE_RESET __HAL_RCC_HRTIM1_RELEASE_RESET
+#define __SDADC1_FORCE_RESET __HAL_RCC_SDADC1_FORCE_RESET
+#define __SDADC2_FORCE_RESET __HAL_RCC_SDADC2_FORCE_RESET
+#define __SDADC3_FORCE_RESET __HAL_RCC_SDADC3_FORCE_RESET
+#define __SDADC1_RELEASE_RESET __HAL_RCC_SDADC1_RELEASE_RESET
+#define __SDADC2_RELEASE_RESET __HAL_RCC_SDADC2_RELEASE_RESET
+#define __SDADC3_RELEASE_RESET __HAL_RCC_SDADC3_RELEASE_RESET
+
+#define __ADC1_IS_CLK_ENABLED __HAL_RCC_ADC1_IS_CLK_ENABLED
+#define __ADC1_IS_CLK_DISABLED __HAL_RCC_ADC1_IS_CLK_DISABLED
+#define __ADC12_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED
+#define __ADC12_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED
+#define __ADC34_IS_CLK_ENABLED __HAL_RCC_ADC34_IS_CLK_ENABLED
+#define __ADC34_IS_CLK_DISABLED __HAL_RCC_ADC34_IS_CLK_DISABLED
+#define __CEC_IS_CLK_ENABLED __HAL_RCC_CEC_IS_CLK_ENABLED
+#define __CEC_IS_CLK_DISABLED __HAL_RCC_CEC_IS_CLK_DISABLED
+#define __CRC_IS_CLK_ENABLED __HAL_RCC_CRC_IS_CLK_ENABLED
+#define __CRC_IS_CLK_DISABLED __HAL_RCC_CRC_IS_CLK_DISABLED
+#define __DAC1_IS_CLK_ENABLED __HAL_RCC_DAC1_IS_CLK_ENABLED
+#define __DAC1_IS_CLK_DISABLED __HAL_RCC_DAC1_IS_CLK_DISABLED
+#define __DAC2_IS_CLK_ENABLED __HAL_RCC_DAC2_IS_CLK_ENABLED
+#define __DAC2_IS_CLK_DISABLED __HAL_RCC_DAC2_IS_CLK_DISABLED
+#define __DMA1_IS_CLK_ENABLED __HAL_RCC_DMA1_IS_CLK_ENABLED
+#define __DMA1_IS_CLK_DISABLED __HAL_RCC_DMA1_IS_CLK_DISABLED
+#define __DMA2_IS_CLK_ENABLED __HAL_RCC_DMA2_IS_CLK_ENABLED
+#define __DMA2_IS_CLK_DISABLED __HAL_RCC_DMA2_IS_CLK_DISABLED
+#define __FLITF_IS_CLK_ENABLED __HAL_RCC_FLITF_IS_CLK_ENABLED
+#define __FLITF_IS_CLK_DISABLED __HAL_RCC_FLITF_IS_CLK_DISABLED
+#define __FMC_IS_CLK_ENABLED __HAL_RCC_FMC_IS_CLK_ENABLED
+#define __FMC_IS_CLK_DISABLED __HAL_RCC_FMC_IS_CLK_DISABLED
+#define __GPIOA_IS_CLK_ENABLED __HAL_RCC_GPIOA_IS_CLK_ENABLED
+#define __GPIOA_IS_CLK_DISABLED __HAL_RCC_GPIOA_IS_CLK_DISABLED
+#define __GPIOB_IS_CLK_ENABLED __HAL_RCC_GPIOB_IS_CLK_ENABLED
+#define __GPIOB_IS_CLK_DISABLED __HAL_RCC_GPIOB_IS_CLK_DISABLED
+#define __GPIOC_IS_CLK_ENABLED __HAL_RCC_GPIOC_IS_CLK_ENABLED
+#define __GPIOC_IS_CLK_DISABLED __HAL_RCC_GPIOC_IS_CLK_DISABLED
+#define __GPIOD_IS_CLK_ENABLED __HAL_RCC_GPIOD_IS_CLK_ENABLED
+#define __GPIOD_IS_CLK_DISABLED __HAL_RCC_GPIOD_IS_CLK_DISABLED
+#define __GPIOE_IS_CLK_ENABLED __HAL_RCC_GPIOE_IS_CLK_ENABLED
+#define __GPIOE_IS_CLK_DISABLED __HAL_RCC_GPIOE_IS_CLK_DISABLED
+#define __GPIOF_IS_CLK_ENABLED __HAL_RCC_GPIOF_IS_CLK_ENABLED
+#define __GPIOF_IS_CLK_DISABLED __HAL_RCC_GPIOF_IS_CLK_DISABLED
+#define __GPIOG_IS_CLK_ENABLED __HAL_RCC_GPIOG_IS_CLK_ENABLED
+#define __GPIOG_IS_CLK_DISABLED __HAL_RCC_GPIOG_IS_CLK_DISABLED
+#define __GPIOH_IS_CLK_ENABLED __HAL_RCC_GPIOH_IS_CLK_ENABLED
+#define __GPIOH_IS_CLK_DISABLED __HAL_RCC_GPIOH_IS_CLK_DISABLED
+#define __HRTIM1_IS_CLK_ENABLED __HAL_RCC_HRTIM1_IS_CLK_ENABLED
+#define __HRTIM1_IS_CLK_DISABLED __HAL_RCC_HRTIM1_IS_CLK_DISABLED
+#define __I2C1_IS_CLK_ENABLED __HAL_RCC_I2C1_IS_CLK_ENABLED
+#define __I2C1_IS_CLK_DISABLED __HAL_RCC_I2C1_IS_CLK_DISABLED
+#define __I2C2_IS_CLK_ENABLED __HAL_RCC_I2C2_IS_CLK_ENABLED
+#define __I2C2_IS_CLK_DISABLED __HAL_RCC_I2C2_IS_CLK_DISABLED
+#define __I2C3_IS_CLK_ENABLED __HAL_RCC_I2C3_IS_CLK_ENABLED
+#define __I2C3_IS_CLK_DISABLED __HAL_RCC_I2C3_IS_CLK_DISABLED
+#define __PWR_IS_CLK_ENABLED __HAL_RCC_PWR_IS_CLK_ENABLED
+#define __PWR_IS_CLK_DISABLED __HAL_RCC_PWR_IS_CLK_DISABLED
+#define __SYSCFG_IS_CLK_ENABLED __HAL_RCC_SYSCFG_IS_CLK_ENABLED
+#define __SYSCFG_IS_CLK_DISABLED __HAL_RCC_SYSCFG_IS_CLK_DISABLED
+#define __SPI1_IS_CLK_ENABLED __HAL_RCC_SPI1_IS_CLK_ENABLED
+#define __SPI1_IS_CLK_DISABLED __HAL_RCC_SPI1_IS_CLK_DISABLED
+#define __SPI2_IS_CLK_ENABLED __HAL_RCC_SPI2_IS_CLK_ENABLED
+#define __SPI2_IS_CLK_DISABLED __HAL_RCC_SPI2_IS_CLK_DISABLED
+#define __SPI3_IS_CLK_ENABLED __HAL_RCC_SPI3_IS_CLK_ENABLED
+#define __SPI3_IS_CLK_DISABLED __HAL_RCC_SPI3_IS_CLK_DISABLED
+#define __SPI4_IS_CLK_ENABLED __HAL_RCC_SPI4_IS_CLK_ENABLED
+#define __SPI4_IS_CLK_DISABLED __HAL_RCC_SPI4_IS_CLK_DISABLED
+#define __SDADC1_IS_CLK_ENABLED __HAL_RCC_SDADC1_IS_CLK_ENABLED
+#define __SDADC1_IS_CLK_DISABLED __HAL_RCC_SDADC1_IS_CLK_DISABLED
+#define __SDADC2_IS_CLK_ENABLED __HAL_RCC_SDADC2_IS_CLK_ENABLED
+#define __SDADC2_IS_CLK_DISABLED __HAL_RCC_SDADC2_IS_CLK_DISABLED
+#define __SDADC3_IS_CLK_ENABLED __HAL_RCC_SDADC3_IS_CLK_ENABLED
+#define __SDADC3_IS_CLK_DISABLED __HAL_RCC_SDADC3_IS_CLK_DISABLED
+#define __SRAM_IS_CLK_ENABLED __HAL_RCC_SRAM_IS_CLK_ENABLED
+#define __SRAM_IS_CLK_DISABLED __HAL_RCC_SRAM_IS_CLK_DISABLED
+#define __TIM1_IS_CLK_ENABLED __HAL_RCC_TIM1_IS_CLK_ENABLED
+#define __TIM1_IS_CLK_DISABLED __HAL_RCC_TIM1_IS_CLK_DISABLED
+#define __TIM2_IS_CLK_ENABLED __HAL_RCC_TIM2_IS_CLK_ENABLED
+#define __TIM2_IS_CLK_DISABLED __HAL_RCC_TIM2_IS_CLK_DISABLED
+#define __TIM3_IS_CLK_ENABLED __HAL_RCC_TIM3_IS_CLK_ENABLED
+#define __TIM3_IS_CLK_DISABLED __HAL_RCC_TIM3_IS_CLK_DISABLED
+#define __TIM4_IS_CLK_ENABLED __HAL_RCC_TIM4_IS_CLK_ENABLED
+#define __TIM4_IS_CLK_DISABLED __HAL_RCC_TIM4_IS_CLK_DISABLED
+#define __TIM5_IS_CLK_ENABLED __HAL_RCC_TIM5_IS_CLK_ENABLED
+#define __TIM5_IS_CLK_DISABLED __HAL_RCC_TIM5_IS_CLK_DISABLED
+#define __TIM6_IS_CLK_ENABLED __HAL_RCC_TIM6_IS_CLK_ENABLED
+#define __TIM6_IS_CLK_DISABLED __HAL_RCC_TIM6_IS_CLK_DISABLED
+#define __TIM7_IS_CLK_ENABLED __HAL_RCC_TIM7_IS_CLK_ENABLED
+#define __TIM7_IS_CLK_DISABLED __HAL_RCC_TIM7_IS_CLK_DISABLED
+#define __TIM8_IS_CLK_ENABLED __HAL_RCC_TIM8_IS_CLK_ENABLED
+#define __TIM8_IS_CLK_DISABLED __HAL_RCC_TIM8_IS_CLK_DISABLED
+#define __TIM12_IS_CLK_ENABLED __HAL_RCC_TIM12_IS_CLK_ENABLED
+#define __TIM12_IS_CLK_DISABLED __HAL_RCC_TIM12_IS_CLK_DISABLED
+#define __TIM13_IS_CLK_ENABLED __HAL_RCC_TIM13_IS_CLK_ENABLED
+#define __TIM13_IS_CLK_DISABLED __HAL_RCC_TIM13_IS_CLK_DISABLED
+#define __TIM14_IS_CLK_ENABLED __HAL_RCC_TIM14_IS_CLK_ENABLED
+#define __TIM14_IS_CLK_DISABLED __HAL_RCC_TIM14_IS_CLK_DISABLED
+#define __TIM15_IS_CLK_ENABLED __HAL_RCC_TIM15_IS_CLK_ENABLED
+#define __TIM15_IS_CLK_DISABLED __HAL_RCC_TIM15_IS_CLK_DISABLED
+#define __TIM16_IS_CLK_ENABLED __HAL_RCC_TIM16_IS_CLK_ENABLED
+#define __TIM16_IS_CLK_DISABLED __HAL_RCC_TIM16_IS_CLK_DISABLED
+#define __TIM17_IS_CLK_ENABLED __HAL_RCC_TIM17_IS_CLK_ENABLED
+#define __TIM17_IS_CLK_DISABLED __HAL_RCC_TIM17_IS_CLK_DISABLED
+#define __TIM18_IS_CLK_ENABLED __HAL_RCC_TIM18_IS_CLK_ENABLED
+#define __TIM18_IS_CLK_DISABLED __HAL_RCC_TIM18_IS_CLK_DISABLED
+#define __TIM19_IS_CLK_ENABLED __HAL_RCC_TIM19_IS_CLK_ENABLED
+#define __TIM19_IS_CLK_DISABLED __HAL_RCC_TIM19_IS_CLK_DISABLED
+#define __TIM20_IS_CLK_ENABLED __HAL_RCC_TIM20_IS_CLK_ENABLED
+#define __TIM20_IS_CLK_DISABLED __HAL_RCC_TIM20_IS_CLK_DISABLED
+#define __TSC_IS_CLK_ENABLED __HAL_RCC_TSC_IS_CLK_ENABLED
+#define __TSC_IS_CLK_DISABLED __HAL_RCC_TSC_IS_CLK_DISABLED
+#define __UART4_IS_CLK_ENABLED __HAL_RCC_UART4_IS_CLK_ENABLED
+#define __UART4_IS_CLK_DISABLED __HAL_RCC_UART4_IS_CLK_DISABLED
+#define __UART5_IS_CLK_ENABLED __HAL_RCC_UART5_IS_CLK_ENABLED
+#define __UART5_IS_CLK_DISABLED __HAL_RCC_UART5_IS_CLK_DISABLED
+#define __USART1_IS_CLK_ENABLED __HAL_RCC_USART1_IS_CLK_ENABLED
+#define __USART1_IS_CLK_DISABLED __HAL_RCC_USART1_IS_CLK_DISABLED
+#define __USART2_IS_CLK_ENABLED __HAL_RCC_USART2_IS_CLK_ENABLED
+#define __USART2_IS_CLK_DISABLED __HAL_RCC_USART2_IS_CLK_DISABLED
+#define __USART3_IS_CLK_ENABLED __HAL_RCC_USART3_IS_CLK_ENABLED
+#define __USART3_IS_CLK_DISABLED __HAL_RCC_USART3_IS_CLK_DISABLED
+#define __USB_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED
+#define __USB_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED
+#define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED
+#define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED
+
+#if defined(STM32L1)
+#define __HAL_RCC_CRYP_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE
+#define __HAL_RCC_CRYP_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE
+#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE
+#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE
+#define __HAL_RCC_CRYP_FORCE_RESET __HAL_RCC_AES_FORCE_RESET
+#define __HAL_RCC_CRYP_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET
+#endif /* STM32L1 */
+
+#if defined(STM32F4)
+#define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET
+#define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET
+#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
+#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
+#define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
+#define __HAL_RCC_SDMMC1_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
+#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED __HAL_RCC_SDIO_IS_CLK_ENABLED
+#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED __HAL_RCC_SDIO_IS_CLK_DISABLED
+#define Sdmmc1ClockSelection SdioClockSelection
+#define RCC_PERIPHCLK_SDMMC1 RCC_PERIPHCLK_SDIO
+#define RCC_SDMMC1CLKSOURCE_CLK48 RCC_SDIOCLKSOURCE_CK48
+#define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_SDIOCLKSOURCE_SYSCLK
+#define __HAL_RCC_SDMMC1_CONFIG __HAL_RCC_SDIO_CONFIG
+#define __HAL_RCC_GET_SDMMC1_SOURCE __HAL_RCC_GET_SDIO_SOURCE
+#endif
+
+#if defined(STM32F7) || defined(STM32L4)
+#define __HAL_RCC_SDIO_FORCE_RESET __HAL_RCC_SDMMC1_FORCE_RESET
+#define __HAL_RCC_SDIO_RELEASE_RESET __HAL_RCC_SDMMC1_RELEASE_RESET
+#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE
+#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE
+#define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE
+#define __HAL_RCC_SDIO_CLK_DISABLE __HAL_RCC_SDMMC1_CLK_DISABLE
+#define __HAL_RCC_SDIO_IS_CLK_ENABLED __HAL_RCC_SDMMC1_IS_CLK_ENABLED
+#define __HAL_RCC_SDIO_IS_CLK_DISABLED __HAL_RCC_SDMMC1_IS_CLK_DISABLED
+#define SdioClockSelection Sdmmc1ClockSelection
+#define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1
+#define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG
+#define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE
+#endif
+
+#if defined(STM32F7)
+#define RCC_SDIOCLKSOURCE_CLK48 RCC_SDMMC1CLKSOURCE_CLK48
+#define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK
+#endif
+
+#if defined(STM32H7)
+#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_ENABLE()
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE()
+#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_DISABLE()
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE()
+#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() __HAL_RCC_USB1_OTG_HS_FORCE_RESET()
+#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() __HAL_RCC_USB1_OTG_HS_RELEASE_RESET()
+#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE()
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE()
+#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE()
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE()
+
+#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_ENABLE()
+#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE()
+#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_DISABLE()
+#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE()
+#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() __HAL_RCC_USB2_OTG_FS_FORCE_RESET()
+#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() __HAL_RCC_USB2_OTG_FS_RELEASE_RESET()
+#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE()
+#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE()
+#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE()
+#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE()
+#endif
+
+#define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG
+#define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG
+
+#define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE
+
+#define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE
+#define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE
+#define IS_RCC_SYSCLK_DIV IS_RCC_HCLK
+#define IS_RCC_HCLK_DIV IS_RCC_PCLK
+#define IS_RCC_PERIPHCLK IS_RCC_PERIPHCLOCK
+
+#define RCC_IT_HSI14 RCC_IT_HSI14RDY
+
+#define RCC_IT_CSSLSE RCC_IT_LSECSS
+#define RCC_IT_CSSHSE RCC_IT_CSS
+
+#define RCC_PLLMUL_3 RCC_PLL_MUL3
+#define RCC_PLLMUL_4 RCC_PLL_MUL4
+#define RCC_PLLMUL_6 RCC_PLL_MUL6
+#define RCC_PLLMUL_8 RCC_PLL_MUL8
+#define RCC_PLLMUL_12 RCC_PLL_MUL12
+#define RCC_PLLMUL_16 RCC_PLL_MUL16
+#define RCC_PLLMUL_24 RCC_PLL_MUL24
+#define RCC_PLLMUL_32 RCC_PLL_MUL32
+#define RCC_PLLMUL_48 RCC_PLL_MUL48
+
+#define RCC_PLLDIV_2 RCC_PLL_DIV2
+#define RCC_PLLDIV_3 RCC_PLL_DIV3
+#define RCC_PLLDIV_4 RCC_PLL_DIV4
+
+#define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE
+#define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG
+#define RCC_MCO_NODIV RCC_MCODIV_1
+#define RCC_MCO_DIV1 RCC_MCODIV_1
+#define RCC_MCO_DIV2 RCC_MCODIV_2
+#define RCC_MCO_DIV4 RCC_MCODIV_4
+#define RCC_MCO_DIV8 RCC_MCODIV_8
+#define RCC_MCO_DIV16 RCC_MCODIV_16
+#define RCC_MCO_DIV32 RCC_MCODIV_32
+#define RCC_MCO_DIV64 RCC_MCODIV_64
+#define RCC_MCO_DIV128 RCC_MCODIV_128
+#define RCC_MCOSOURCE_NONE RCC_MCO1SOURCE_NOCLOCK
+#define RCC_MCOSOURCE_LSI RCC_MCO1SOURCE_LSI
+#define RCC_MCOSOURCE_LSE RCC_MCO1SOURCE_LSE
+#define RCC_MCOSOURCE_SYSCLK RCC_MCO1SOURCE_SYSCLK
+#define RCC_MCOSOURCE_HSI RCC_MCO1SOURCE_HSI
+#define RCC_MCOSOURCE_HSI14 RCC_MCO1SOURCE_HSI14
+#define RCC_MCOSOURCE_HSI48 RCC_MCO1SOURCE_HSI48
+#define RCC_MCOSOURCE_HSE RCC_MCO1SOURCE_HSE
+#define RCC_MCOSOURCE_PLLCLK_DIV1 RCC_MCO1SOURCE_PLLCLK
+#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
+#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
+
+#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL) || defined(STM32C0)
+#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE
+#else
+#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
+#endif
+
+#define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1
+#define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL
+#define RCC_USBCLK_MSI RCC_USBCLKSOURCE_MSI
+#define RCC_USBCLKSOURCE_PLLCLK RCC_USBCLKSOURCE_PLL
+#define RCC_USBPLLCLK_DIV1 RCC_USBCLKSOURCE_PLL
+#define RCC_USBPLLCLK_DIV1_5 RCC_USBCLKSOURCE_PLL_DIV1_5
+#define RCC_USBPLLCLK_DIV2 RCC_USBCLKSOURCE_PLL_DIV2
+#define RCC_USBPLLCLK_DIV3 RCC_USBCLKSOURCE_PLL_DIV3
+
+#define HSION_BitNumber RCC_HSION_BIT_NUMBER
+#define HSION_BITNUMBER RCC_HSION_BIT_NUMBER
+#define HSEON_BitNumber RCC_HSEON_BIT_NUMBER
+#define HSEON_BITNUMBER RCC_HSEON_BIT_NUMBER
+#define MSION_BITNUMBER RCC_MSION_BIT_NUMBER
+#define CSSON_BitNumber RCC_CSSON_BIT_NUMBER
+#define CSSON_BITNUMBER RCC_CSSON_BIT_NUMBER
+#define PLLON_BitNumber RCC_PLLON_BIT_NUMBER
+#define PLLON_BITNUMBER RCC_PLLON_BIT_NUMBER
+#define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER
+#define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER
+#define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER
+#define RTCEN_BITNUMBER RCC_RTCEN_BIT_NUMBER
+#define BDRST_BitNumber RCC_BDRST_BIT_NUMBER
+#define BDRST_BITNUMBER RCC_BDRST_BIT_NUMBER
+#define RTCRST_BITNUMBER RCC_RTCRST_BIT_NUMBER
+#define LSION_BitNumber RCC_LSION_BIT_NUMBER
+#define LSION_BITNUMBER RCC_LSION_BIT_NUMBER
+#define LSEON_BitNumber RCC_LSEON_BIT_NUMBER
+#define LSEON_BITNUMBER RCC_LSEON_BIT_NUMBER
+#define LSEBYP_BITNUMBER RCC_LSEBYP_BIT_NUMBER
+#define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER
+#define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER
+#define RMVF_BitNumber RCC_RMVF_BIT_NUMBER
+#define RMVF_BITNUMBER RCC_RMVF_BIT_NUMBER
+#define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER
+#define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS
+#define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS
+#define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS
+#define BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS
+#define DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE
+#define LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE
+
+#define CR_HSION_BB RCC_CR_HSION_BB
+#define CR_CSSON_BB RCC_CR_CSSON_BB
+#define CR_PLLON_BB RCC_CR_PLLON_BB
+#define CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB
+#define CR_MSION_BB RCC_CR_MSION_BB
+#define CSR_LSION_BB RCC_CSR_LSION_BB
+#define CSR_LSEON_BB RCC_CSR_LSEON_BB
+#define CSR_LSEBYP_BB RCC_CSR_LSEBYP_BB
+#define CSR_RTCEN_BB RCC_CSR_RTCEN_BB
+#define CSR_RTCRST_BB RCC_CSR_RTCRST_BB
+#define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB
+#define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB
+#define BDCR_BDRST_BB RCC_BDCR_BDRST_BB
+#define CR_HSEON_BB RCC_CR_HSEON_BB
+#define CSR_RMVF_BB RCC_CSR_RMVF_BB
+#define CR_PLLSAION_BB RCC_CR_PLLSAION_BB
+#define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB
+
+#define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE
+#define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE
+#define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE
+#define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE
+#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE __HAL_RCC_CRS_RELOADVALUE_CALCULATE
+
+#define __HAL_RCC_GET_IT_SOURCE __HAL_RCC_GET_IT
+
+#define RCC_CRS_SYNCWARM RCC_CRS_SYNCWARN
+#define RCC_CRS_TRIMOV RCC_CRS_TRIMOVF
+
+#define RCC_PERIPHCLK_CK48 RCC_PERIPHCLK_CLK48
+#define RCC_CK48CLKSOURCE_PLLQ RCC_CLK48CLKSOURCE_PLLQ
+#define RCC_CK48CLKSOURCE_PLLSAIP RCC_CLK48CLKSOURCE_PLLSAIP
+#define RCC_CK48CLKSOURCE_PLLI2SQ RCC_CLK48CLKSOURCE_PLLI2SQ
+#define IS_RCC_CK48CLKSOURCE IS_RCC_CLK48CLKSOURCE
+#define RCC_SDIOCLKSOURCE_CK48 RCC_SDIOCLKSOURCE_CLK48
+
+#define __HAL_RCC_DFSDM_CLK_ENABLE __HAL_RCC_DFSDM1_CLK_ENABLE
+#define __HAL_RCC_DFSDM_CLK_DISABLE __HAL_RCC_DFSDM1_CLK_DISABLE
+#define __HAL_RCC_DFSDM_IS_CLK_ENABLED __HAL_RCC_DFSDM1_IS_CLK_ENABLED
+#define __HAL_RCC_DFSDM_IS_CLK_DISABLED __HAL_RCC_DFSDM1_IS_CLK_DISABLED
+#define __HAL_RCC_DFSDM_FORCE_RESET __HAL_RCC_DFSDM1_FORCE_RESET
+#define __HAL_RCC_DFSDM_RELEASE_RESET __HAL_RCC_DFSDM1_RELEASE_RESET
+#define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE
+#define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE
+#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED
+#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED
+#define DfsdmClockSelection Dfsdm1ClockSelection
+#define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1
+#define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2
+#define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK
+#define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG
+#define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE
+#define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2
+#define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1
+#define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1
+#define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1
+
+#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1
+#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2
+#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM2AUDIOCLKSOURCE_I2S1
+#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM2AUDIOCLKSOURCE_I2S2
+#define RCC_DFSDM1CLKSOURCE_APB2 RCC_DFSDM1CLKSOURCE_PCLK2
+#define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2
+#define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1
+#if defined(STM32U5)
+#define MSIKPLLModeSEL RCC_MSIKPLL_MODE_SEL
+#define MSISPLLModeSEL RCC_MSISPLL_MODE_SEL
+#define __HAL_RCC_AHB21_CLK_DISABLE __HAL_RCC_AHB2_1_CLK_DISABLE
+#define __HAL_RCC_AHB22_CLK_DISABLE __HAL_RCC_AHB2_2_CLK_DISABLE
+#define __HAL_RCC_AHB1_CLK_Disable_Clear __HAL_RCC_AHB1_CLK_ENABLE
+#define __HAL_RCC_AHB21_CLK_Disable_Clear __HAL_RCC_AHB2_1_CLK_ENABLE
+#define __HAL_RCC_AHB22_CLK_Disable_Clear __HAL_RCC_AHB2_2_CLK_ENABLE
+#define __HAL_RCC_AHB3_CLK_Disable_Clear __HAL_RCC_AHB3_CLK_ENABLE
+#define __HAL_RCC_APB1_CLK_Disable_Clear __HAL_RCC_APB1_CLK_ENABLE
+#define __HAL_RCC_APB2_CLK_Disable_Clear __HAL_RCC_APB2_CLK_ENABLE
+#define __HAL_RCC_APB3_CLK_Disable_Clear __HAL_RCC_APB3_CLK_ENABLE
+#define IS_RCC_MSIPLLModeSelection IS_RCC_MSIPLLMODE_SELECT
+#define RCC_PERIPHCLK_CLK48 RCC_PERIPHCLK_ICLK
+#define RCC_CLK48CLKSOURCE_HSI48 RCC_ICLK_CLKSOURCE_HSI48
+#define RCC_CLK48CLKSOURCE_PLL2 RCC_ICLK_CLKSOURCE_PLL2
+#define RCC_CLK48CLKSOURCE_PLL1 RCC_ICLK_CLKSOURCE_PLL1
+#define RCC_CLK48CLKSOURCE_MSIK RCC_ICLK_CLKSOURCE_MSIK
+#define __HAL_RCC_ADC1_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
+#define __HAL_RCC_ADC1_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
+#define __HAL_RCC_ADC1_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED
+#define __HAL_RCC_ADC1_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED
+#define __HAL_RCC_ADC1_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
+#define __HAL_RCC_ADC1_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
+#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC12_CLK_SLEEP_ENABLE
+#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC12_CLK_SLEEP_DISABLE
+#endif
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit)
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || defined (STM32C0)
+#else
+#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
+#endif
+#define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT
+#define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT
+
+#if defined (STM32F1)
+#define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG()
+
+#define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT()
+
+#define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_DISABLE_IT()
+
+#define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GET_FLAG()
+
+#define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT()
+#else
+#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \
+ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()))
+#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \
+ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()))
+#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \
+ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()))
+#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \
+ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()))
+#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \
+ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
+#endif /* STM32F1 */
+
+#define IS_ALARM IS_RTC_ALARM
+#define IS_ALARM_MASK IS_RTC_ALARM_MASK
+#define IS_TAMPER IS_RTC_TAMPER
+#define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE
+#define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER
+#define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT
+#define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE
+#define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION
+#define IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE
+#define IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ
+#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION
+#define IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER
+#define IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK
+#define IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER
+
+#define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE
+#define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE
+
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_SD_Aliased_Macros HAL SD/MMC Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE
+#define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS
+
+#if !defined(STM32F1) && !defined(STM32F2) && !defined(STM32F4) && !defined(STM32F7) && !defined(STM32L1)
+#define eMMC_HIGH_VOLTAGE_RANGE EMMC_HIGH_VOLTAGE_RANGE
+#define eMMC_DUAL_VOLTAGE_RANGE EMMC_DUAL_VOLTAGE_RANGE
+#define eMMC_LOW_VOLTAGE_RANGE EMMC_LOW_VOLTAGE_RANGE
+
+#define SDMMC_NSpeed_CLK_DIV SDMMC_NSPEED_CLK_DIV
+#define SDMMC_HSpeed_CLK_DIV SDMMC_HSPEED_CLK_DIV
+#endif
+
+#if defined(STM32F4) || defined(STM32F2)
+#define SD_SDMMC_DISABLED SD_SDIO_DISABLED
+#define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY
+#define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED
+#define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION
+#define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND
+#define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT
+#define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED
+#define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE
+#define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE
+#define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE
+#define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL
+#define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT
+#define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT
+#define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG
+#define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG
+#define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT
+#define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT
+#define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS
+#define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT
+#define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND
+/* alias CMSIS */
+#define SDMMC1_IRQn SDIO_IRQn
+#define SDMMC1_IRQHandler SDIO_IRQHandler
+#endif
+
+#if defined(STM32F7) || defined(STM32L4)
+#define SD_SDIO_DISABLED SD_SDMMC_DISABLED
+#define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY
+#define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED
+#define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION
+#define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND
+#define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT
+#define SD_CMD_SDIO_RW_EXTENDED SD_CMD_SDMMC_RW_EXTENDED
+#define __HAL_SD_SDIO_ENABLE __HAL_SD_SDMMC_ENABLE
+#define __HAL_SD_SDIO_DISABLE __HAL_SD_SDMMC_DISABLE
+#define __HAL_SD_SDIO_DMA_ENABLE __HAL_SD_SDMMC_DMA_ENABLE
+#define __HAL_SD_SDIO_DMA_DISABL __HAL_SD_SDMMC_DMA_DISABLE
+#define __HAL_SD_SDIO_ENABLE_IT __HAL_SD_SDMMC_ENABLE_IT
+#define __HAL_SD_SDIO_DISABLE_IT __HAL_SD_SDMMC_DISABLE_IT
+#define __HAL_SD_SDIO_GET_FLAG __HAL_SD_SDMMC_GET_FLAG
+#define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG
+#define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT
+#define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT
+#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS
+#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT
+#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND
+/* alias CMSIS for compatibilities */
+#define SDIO_IRQn SDMMC1_IRQn
+#define SDIO_IRQHandler SDMMC1_IRQHandler
+#endif
+
+#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) || defined(STM32L4) || defined(STM32H7)
+#define HAL_SD_CardCIDTypedef HAL_SD_CardCIDTypeDef
+#define HAL_SD_CardCSDTypedef HAL_SD_CardCSDTypeDef
+#define HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef
+#define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef
+#endif
+
+#if defined(STM32H7) || defined(STM32L5)
+#define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback HAL_MMCEx_Read_DMADoubleBuf0CpltCallback
+#define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback HAL_MMCEx_Read_DMADoubleBuf1CpltCallback
+#define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback HAL_MMCEx_Write_DMADoubleBuf0CpltCallback
+#define HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback HAL_MMCEx_Write_DMADoubleBuf1CpltCallback
+#define HAL_SDEx_Read_DMADoubleBuffer0CpltCallback HAL_SDEx_Read_DMADoubleBuf0CpltCallback
+#define HAL_SDEx_Read_DMADoubleBuffer1CpltCallback HAL_SDEx_Read_DMADoubleBuf1CpltCallback
+#define HAL_SDEx_Write_DMADoubleBuffer0CpltCallback HAL_SDEx_Write_DMADoubleBuf0CpltCallback
+#define HAL_SDEx_Write_DMADoubleBuffer1CpltCallback HAL_SDEx_Write_DMADoubleBuf1CpltCallback
+#define HAL_SD_DriveTransciver_1_8V_Callback HAL_SD_DriveTransceiver_1_8V_Callback
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT
+#define __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT
+#define __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE
+#define __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE
+#define __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE
+#define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE
+
+#define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE
+#define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE
+
+#define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1
+#define __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2
+#define __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START
+#define __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH
+#define __HAL_SMBUS_GET_DIR SMBUS_GET_DIR
+#define __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE
+#define __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE
+#define __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED
+/**
+ * @}
+ */
+
+/** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define __HAL_SPI_1LINE_TX SPI_1LINE_TX
+#define __HAL_SPI_1LINE_RX SPI_1LINE_RX
+#define __HAL_SPI_RESET_CRC SPI_RESET_CRC
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE
+#define __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION
+#define __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE
+#define __UART_MASK_COMPUTATION UART_MASK_COMPUTATION
+
+#define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD
+
+#define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE
+#define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE
+
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define __USART_ENABLE_IT __HAL_USART_ENABLE_IT
+#define __USART_DISABLE_IT __HAL_USART_DISABLE_IT
+#define __USART_ENABLE __HAL_USART_ENABLE
+#define __USART_DISABLE __HAL_USART_DISABLE
+
+#define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
+#define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
+
+#if defined(STM32F0) || defined(STM32F3) || defined(STM32F7)
+#define USART_OVERSAMPLING_16 0x00000000U
+#define USART_OVERSAMPLING_8 USART_CR1_OVER8
+
+#define IS_USART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == USART_OVERSAMPLING_16) || \
+ ((__SAMPLING__) == USART_OVERSAMPLING_8))
+#endif /* STM32F0 || STM32F3 || STM32F7 */
+/**
+ * @}
+ */
+
+/** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE
+
+#define USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE
+#define USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE
+#define USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE
+#define USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE
+
+#define USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE
+#define USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE
+#define USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE
+#define USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE
+
+#define __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT
+#define __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT
+#define __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG
+#define __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG
+#define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE
+#define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
+
+#define __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT
+#define __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT
+#define __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG
+#define __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG
+#define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE
+#define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
+#define __HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT
+
+#define __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT
+#define __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT
+#define __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG
+#define __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG
+#define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE
+#define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
+#define __HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT
+
+#define HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup
+#define HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup
+
+#define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo
+#define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo
+/**
+ * @}
+ */
+
+/** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE
+#define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE
+
+#define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE
+#define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT
+
+#define __HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE
+
+#define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN
+#define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER
+#define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER
+#define __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER
+#define __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD
+#define __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD
+#define __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION
+#define __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION
+#define __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER
+#define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER
+#define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE
+#define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE
+
+#define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1
+/**
+ * @}
+ */
+
+/** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT
+#define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT
+#define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG
+#define __HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG
+#define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER
+#define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER
+#define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER
+
+#define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE
+#define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE
+#define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE
+/**
+ * @}
+ */
+
+/** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __HAL_LTDC_LAYER LTDC_LAYER
+#define __HAL_LTDC_RELOAD_CONFIG __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG
+/**
+ * @}
+ */
+
+/** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE
+#define SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE
+#define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE
+#define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE
+#define SAI_STREOMODE SAI_STEREOMODE
+#define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY
+#define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL
+#define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL
+#define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL
+#define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL
+#define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL
+#define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE
+#define SAI_SYNCHRONOUS_EXT SAI_SYNCHRONOUS_EXT_SAI1
+#define SAI_SYNCEXT_IN_ENABLE SAI_SYNCEXT_OUTBLOCKA_ENABLE
+/**
+ * @}
+ */
+
+/** @defgroup HAL_SPDIFRX_Aliased_Macros HAL SPDIFRX Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#if defined(STM32H7)
+#define HAL_SPDIFRX_ReceiveControlFlow HAL_SPDIFRX_ReceiveCtrlFlow
+#define HAL_SPDIFRX_ReceiveControlFlow_IT HAL_SPDIFRX_ReceiveCtrlFlow_IT
+#define HAL_SPDIFRX_ReceiveControlFlow_DMA HAL_SPDIFRX_ReceiveCtrlFlow_DMA
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup HAL_HRTIM_Aliased_Functions HAL HRTIM Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#if defined (STM32H7) || defined (STM32G4) || defined (STM32F3)
+#define HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT
+#define HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA
+#define HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart
+#define HAL_HRTIM_WaveformCounterStop_IT HAL_HRTIM_WaveformCountStop_IT
+#define HAL_HRTIM_WaveformCounterStop_DMA HAL_HRTIM_WaveformCountStop_DMA
+#define HAL_HRTIM_WaveformCounterStop HAL_HRTIM_WaveformCountStop
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#if defined (STM32L4) || defined (STM32F4) || defined (STM32F7) || defined(STM32H7)
+#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE
+#endif /* STM32L4 || STM32F4 || STM32F7 */
+/**
+ * @}
+ */
+
+/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32_HAL_LEGACY */
diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32_assert_template.h b/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32_assert_template.h
new file mode 100644
index 0000000000..8efa2dbc22
--- /dev/null
+++ b/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32_assert_template.h
@@ -0,0 +1,53 @@
+/**
+ ******************************************************************************
+ * @file stm32_assert.h
+ * @author MCD Application Team
+ * @brief STM32 assert template file.
+ * This file should be copied to the application folder and renamed
+ * to stm32_assert.h.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2022 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32_ASSERT_H
+#define STM32_ASSERT_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Includes ------------------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+#ifdef USE_FULL_ASSERT
+/**
+ * @brief The assert_param macro is used for functions parameters check.
+ * @param expr: If expr is false, it calls assert_failed function
+ * which reports the name of the source file and the source
+ * line number of the call that failed.
+ * If expr is true, it returns no value.
+ * @retval None
+ */
+#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+void assert_failed(uint8_t *file, uint32_t line);
+#else
+#define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32_ASSERT_H */
diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h b/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h
new file mode 100644
index 0000000000..525836c40c
--- /dev/null
+++ b/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h
@@ -0,0 +1,582 @@
+/**
+ ******************************************************************************
+ * @file stm32c0xx_hal.h
+ * @author MCD Application Team
+ * @brief This file contains all the functions prototypes for the HAL
+ * module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2022 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32C0xx_HAL_H
+#define STM32C0xx_HAL_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32c0xx_ll_system.h"
+#include "stm32c0xx_hal_conf.h"
+
+/** @addtogroup STM32C0xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup HAL HAL
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup HAL_Exported_Constants HAL Exported Constants
+ * @{
+ */
+
+/** @defgroup HAL_TICK_FREQ Tick Frequency
+ * @{
+ */
+
+#define HAL_TICK_FREQ_10HZ 100U
+#define HAL_TICK_FREQ_100HZ 10U
+#define HAL_TICK_FREQ_1KHZ 1U
+#define HAL_TICK_FREQ_DEFAULT HAL_TICK_FREQ_1KHZ
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_BIND Bind Pin config
+ * @{
+ */
+
+#if (DEV_ID == 0x443UL)
+#define HAL_BIND_SO8_PIN1_PB7 LL_PINMUX_SO8_PIN1_PB7 /*!< STM32C011 SO8 package, Pin1 assigned to GPIO PB7 */
+#define HAL_BIND_SO8_PIN1_PC14 LL_PINMUX_SO8_PIN1_PC14 /*!< STM32C011 SO8 package, Pin1 assigned to GPIO PC14 */
+#define HAL_BIND_SO8_PIN4_PF2 LL_PINMUX_SO8_PIN4_PF2 /*!< STM32C011 SO8 package, Pin4 assigned to GPIO PF2 */
+#define HAL_BIND_SO8_PIN4_PA0 LL_PINMUX_SO8_PIN4_PA0 /*!< STM32C011 SO8 package, Pin4 assigned to GPIO PA0 */
+#define HAL_BIND_SO8_PIN4_PA1 LL_PINMUX_SO8_PIN4_PA1 /*!< STM32C011 SO8 package, Pin4 assigned to GPIO PA1 */
+#define HAL_BIND_SO8_PIN4_PA2 LL_PINMUX_SO8_PIN4_PA2 /*!< STM32C011 SO8 package, Pin4 assigned to GPIO PA2 */
+#define HAL_BIND_SO8_PIN5_PA8 LL_PINMUX_SO8_PIN5_PA8 /*!< STM32C011 SO8 package, Pin5 assigned to GPIO PA8*/
+#define HAL_BIND_SO8_PIN5_PA11 LL_PINMUX_SO8_PIN5_PA11 /*!< STM32C011 SO8 package, Pin5 assigned to GPIO PA11 */
+#define HAL_BIND_SO8_PIN8_PA14 LL_PINMUX_SO8_PIN8_PA14 /*!< STM32C011 SO8 package, Pin8 assigned to GPIO PA14 */
+#define HAL_BIND_SO8_PIN8_PB6 LL_PINMUX_SO8_PIN8_PB6 /*!< STM32C011 SO8 package, Pin8 assigned to GPIO PB6 */
+#define HAL_BIND_SO8_PIN8_PC15 LL_PINMUX_SO8_PIN8_PC15 /*!< STM32C011 SO8 package, Pin8 assigned to GPIO PC15 */
+#define HAL_BIND_WLCSP12_PINE2_PA7 LL_PINMUX_WLCSP12_PINE2_PA7 /*!< STM32C011 WLCSP12 package, PinE2 assigned to GPIO PA7 */
+#define HAL_BIND_WLCSP12_PINE2_PA12 LL_PINMUX_WLCSP12_PINE2_PA12 /*!< STM32C011 WLCSP12 package, PinE2 assigned to GPIO PA12*/
+#define HAL_BIND_WLCSP12_PINF1_PA3 LL_PINMUX_WLCSP12_PINF1_PA3 /*!< STM32C011 WLCSP12 package, PinF1 assigned to GPIO PA3 */
+#define HAL_BIND_WLCSP12_PINF1_PA4 LL_PINMUX_WLCSP12_PINF1_PA4 /*!< STM32C011 WLCSP12 package, PinF1 assigned to GPIO PA4 */
+#define HAL_BIND_WLCSP12_PINF1_PA5 LL_PINMUX_WLCSP12_PINF1_PA5 /*!< STM32C011 WLCSP12 package, PinF1 assigned to GPIO PA5 */
+#define HAL_BIND_WLCSP12_PINF1_PA6 LL_PINMUX_WLCSP12_PINF1_PA6 /*!< STM32C011 WLCSP12 package, PinF1 assigned to GPIO PA6 */
+#elif (DEV_ID == 0x453UL)
+#define HAL_BIND_WLCSP14_PINF2_PA1 LL_PINMUX_WLCSP14_PINF2_PA1 /*!< STM32C031 WLCSP14 package, PinF2 assigned to GPIO PA1 */
+#define HAL_BIND_WLCSP14_PINF2_PA2 LL_PINMUX_WLCSP14_PINF2_PA2 /*!< STM32C031 WLCSP14 package, PinF2 assigned to GPIO PA2 */
+#define HAL_BIND_WLCSP14_PING3_PF2 LL_PINMUX_WLCSP14_PING3_PF2 /*!< STM32C031 WLCSP14 package, PinG3 assigned to GPIO PF2 */
+#define HAL_BIND_WLCSP14_PING3_PA0 LL_PINMUX_WLCSP14_PING3_PA0 /*!< STM32C031 WLCSP14 package, PinG3 assigned to GPIO PA0 */
+#define HAL_BIND_WLCSP14_PINJ1_PA8 LL_PINMUX_WLCSP14_PINJ1_PA8 /*!< STM32C031 WLCSP14 package, PinJ1 assigned to GPIO PA8 */
+#define HAL_BIND_WLCSP14_PINJ1_PA11 LL_PINMUX_WLCSP14_PINJ1_PA11 /*!< STM32C031 WLCSP14 package, PinJ1 assigned to GPIO PA11 */
+#define HAL_BIND_WLCSP14_PINH2_PA5 LL_PINMUX_WLCSP14_PINH2_PA5 /*!< STM32C031 WLCSP14 package, PinH2 assigned to GPIO PA5 */
+#define HAL_BIND_WLCSP14_PINH2_PA6 LL_PINMUX_WLCSP14_PINH2_PA6 /*!< STM32C031 WLCSP14 package, PinH2 assigned to GPIO PA6 */
+#define HAL_BIND_WLCSP14_PING1_PA7 LL_PINMUX_WLCSP14_PING1_PA7 /*!< STM32C031 WLCSP14 package, PinG1 assigned to GPIO PA7 */
+#define HAL_BIND_WLCSP14_PING1_PA12 LL_PINMUX_WLCSP14_PING1_PA12 /*!< STM32C031 WLCSP14 package, PinG1 assigned to GPIO PA12 */
+#define HAL_BIND_WLCSP14_PINJ3_PA3 LL_PINMUX_WLCSP14_PINJ3_PA3 /*!< STM32C031 WLCSP14 package, PinJ3 assigned to GPIO PA3 */
+#define HAL_BIND_WLCSP14_PINJ3_PA4 LL_PINMUX_WLCSP14_PINJ3_PA4 /*!< STM32C031 WLCSP14 package, PinJ3 assigned to GPIO PA4 */
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup SYSCFG_Exported_Constants SYSCFG Exported Constants
+ * @{
+ */
+
+/** @defgroup SYSCFG_BootMode Boot Mode
+ * @{
+ */
+#define SYSCFG_BOOT_MAINFLASH 0x00000000U /*!< Main Flash memory mapped at 0x0000 0000 */
+#define SYSCFG_BOOT_SYSTEMFLASH SYSCFG_CFGR1_MEM_MODE_0 /*!< System Flash memory mapped at 0x0000 0000 */
+#define SYSCFG_BOOT_SRAM (SYSCFG_CFGR1_MEM_MODE_1 | SYSCFG_CFGR1_MEM_MODE_0) /*!< Embedded SRAM mapped at 0x0000 0000 */
+
+/**
+ * @}
+ */
+
+/** @defgroup SYSCFG_Break Break
+ * @{
+ */
+#define SYSCFG_BREAK_LOCKUP SYSCFG_CFGR2_CLL /*!< Enables and locks the LOCKUP output of CortexM0+ with Break Input of TIM1/16/17 */
+/**
+ * @}
+ */
+
+/** @defgroup HAL_Pin_remapping Pin remapping
+ * @{
+ */
+#define SYSCFG_REMAP_PA11 SYSCFG_CFGR1_PA11_RMP /*!< PA11 pad behaves digitally as PA9 GPIO pin */
+#define SYSCFG_REMAP_PA12 SYSCFG_CFGR1_PA12_RMP /*!< PA12 pad behaves digitally as PA10 GPIO pin */
+/**
+ * @}
+ */
+
+/** @defgroup HAL_IR_ENV_SEL IR Modulation Envelope signal selection
+ * @{
+ */
+#define HAL_SYSCFG_IRDA_ENV_SEL_TIM16 (SYSCFG_CFGR1_IR_MOD_0 & SYSCFG_CFGR1_IR_MOD_1) /*!< 00: Timer16 is selected as IR Modulation envelope source */
+#define HAL_SYSCFG_IRDA_ENV_SEL_USART1 (SYSCFG_CFGR1_IR_MOD_0) /*!< 01: USART1 is selected as IR Modulation envelope source */
+#define HAL_SYSCFG_IRDA_ENV_SEL_USART2 (SYSCFG_CFGR1_IR_MOD_1) /*!< 10: USART2 is selected as IR Modulation envelope source */
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_IR_POL_SEL IR output polarity selection
+ * @{
+ */
+#define HAL_SYSCFG_IRDA_POLARITY_NOT_INVERTED 0x00000000U /*!< 00: IR output polarity not inverted */
+#define HAL_SYSCFG_IRDA_POLARITY_INVERTED SYSCFG_CFGR1_IR_POL /*!< 01: IR output polarity inverted */
+
+/**
+ * @}
+ */
+/** @defgroup SYSCFG_FastModePlus_GPIO Fast mode Plus on GPIO
+ * @{
+ */
+
+/** @brief Fast mode Plus driving capability on a specific GPIO
+ */
+#define SYSCFG_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< Enable Fast mode Plus on PB6 */
+#define SYSCFG_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< Enable Fast mode Plus on PB7 */
+#define SYSCFG_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< Enable Fast mode Plus on PB8 */
+#define SYSCFG_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast mode Plus on PB9 */
+#define SYSCFG_FASTMODEPLUS_PA9 SYSCFG_CFGR1_I2C_PA9_FMP /*!< Enable Fast mode Plus on PA9 */
+#define SYSCFG_FASTMODEPLUS_PA10 SYSCFG_CFGR1_I2C_PA10_FMP /*!< Enable Fast mode Plus on PA10 */
+#define SYSCFG_FASTMODEPLUS_PC14 SYSCFG_CFGR1_I2C_PC14_FMP /*!< Enable Fast mode Plus on PC14 */
+/**
+ * @}
+ */
+
+/** @defgroup SYSCFG_FastModePlus_I2Cx Fast mode Plus driving capability activation for I2Cx
+ * @{
+ */
+
+/** @brief Fast mode Plus driving capability on a specific GPIO
+ */
+#define SYSCFG_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP /*!< Enable Fast mode Plus on I2C1 */
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_ISR_Wrapper HAL ISR Wrapper
+ * @brief ISR Wrapper
+ * @{
+ */
+#define HAL_SYSCFG_ITLINE0 0x00000000U /*!< Internal define for macro handling */
+#define HAL_SYSCFG_ITLINE2 0x00000002U /*!< Internal define for macro handling */
+#define HAL_SYSCFG_ITLINE3 0x00000003U /*!< Internal define for macro handling */
+#define HAL_SYSCFG_ITLINE4 0x00000004U /*!< Internal define for macro handling */
+#define HAL_SYSCFG_ITLINE5 0x00000005U /*!< Internal define for macro handling */
+#define HAL_SYSCFG_ITLINE6 0x00000006U /*!< Internal define for macro handling */
+#define HAL_SYSCFG_ITLINE7 0x00000007U /*!< Internal define for macro handling */
+#define HAL_SYSCFG_ITLINE9 0x00000009U /*!< Internal define for macro handling */
+#define HAL_SYSCFG_ITLINE10 0x0000000AU /*!< Internal define for macro handling */
+#define HAL_SYSCFG_ITLINE11 0x0000000BU /*!< Internal define for macro handling */
+#define HAL_SYSCFG_ITLINE12 0x0000000CU /*!< Internal define for macro handling */
+#define HAL_SYSCFG_ITLINE13 0x0000000DU /*!< Internal define for macro handling */
+#define HAL_SYSCFG_ITLINE14 0x0000000EU /*!< Internal define for macro handling */
+#define HAL_SYSCFG_ITLINE16 0x00000010U /*!< Internal define for macro handling */
+#define HAL_SYSCFG_ITLINE19 0x00000013U /*!< Internal define for macro handling */
+#define HAL_SYSCFG_ITLINE21 0x00000015U /*!< Internal define for macro handling */
+#define HAL_SYSCFG_ITLINE22 0x00000016U /*!< Internal define for macro handling */
+#define HAL_SYSCFG_ITLINE23 0x00000017U /*!< Internal define for macro handling */
+#define HAL_SYSCFG_ITLINE25 0x00000019U /*!< Internal define for macro handling */
+#define HAL_SYSCFG_ITLINE27 0x0000001BU /*!< Internal define for macro handling */
+#define HAL_SYSCFG_ITLINE28 0x0000001CU /*!< Internal define for macro handling */
+
+#define HAL_ITLINE_WWDG ((HAL_SYSCFG_ITLINE0 << 0x18U) | SYSCFG_ITLINE0_SR_WWDG) /*!< WWDG Interrupt */
+#define HAL_ITLINE_RTC ((HAL_SYSCFG_ITLINE2 << 0x18U) | SYSCFG_ITLINE2_SR_RTC) /*!< RTC Interrupt */
+#define HAL_ITLINE_FLASH_ITF ((HAL_SYSCFG_ITLINE3 << 0x18U) | SYSCFG_ITLINE3_SR_FLASH_ITF) /*!< Flash ITF Interrupt */
+#define HAL_ITLINE_CLK_CTRL ((HAL_SYSCFG_ITLINE4 << 0x18U) | SYSCFG_ITLINE4_SR_CLK_CTRL) /*!< CLK Control Interrupt */
+#define HAL_ITLINE_EXTI0 ((HAL_SYSCFG_ITLINE5 << 0x18U) | SYSCFG_ITLINE5_SR_EXTI0) /*!< External Interrupt 0 */
+#define HAL_ITLINE_EXTI1 ((HAL_SYSCFG_ITLINE5 << 0x18U) | SYSCFG_ITLINE5_SR_EXTI1) /*!< External Interrupt 1 */
+#define HAL_ITLINE_EXTI2 ((HAL_SYSCFG_ITLINE6 << 0x18U) | SYSCFG_ITLINE6_SR_EXTI2) /*!< External Interrupt 2 */
+#define HAL_ITLINE_EXTI3 ((HAL_SYSCFG_ITLINE6 << 0x18U) | SYSCFG_ITLINE6_SR_EXTI3) /*!< External Interrupt 3 */
+#define HAL_ITLINE_EXTI4 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI4) /*!< EXTI4 Interrupt */
+#define HAL_ITLINE_EXTI5 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI5) /*!< EXTI5 Interrupt */
+#define HAL_ITLINE_EXTI6 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI6) /*!< EXTI6 Interrupt */
+#define HAL_ITLINE_EXTI7 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI7) /*!< EXTI7 Interrupt */
+#define HAL_ITLINE_EXTI8 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI8) /*!< EXTI8 Interrupt */
+#define HAL_ITLINE_EXTI9 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI9) /*!< EXTI9 Interrupt */
+#define HAL_ITLINE_EXTI10 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI10) /*!< EXTI10 Interrupt */
+#define HAL_ITLINE_EXTI11 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI11) /*!< EXTI11 Interrupt */
+#define HAL_ITLINE_EXTI12 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI12) /*!< EXTI12 Interrupt */
+#define HAL_ITLINE_EXTI13 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI13) /*!< EXTI13 Interrupt */
+#define HAL_ITLINE_EXTI14 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI14) /*!< EXTI14 Interrupt */
+#define HAL_ITLINE_EXTI15 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI15) /*!< EXTI15 Interrupt */
+#define HAL_ITLINE_DMA1_CH1 ((HAL_SYSCFG_ITLINE9 << 0x18U) | SYSCFG_ITLINE9_SR_DMA1_CH1) /*!< DMA1 Channel 1 Interrupt */
+#define HAL_ITLINE_DMA1_CH2 ((HAL_SYSCFG_ITLINE10 << 0x18U) | SYSCFG_ITLINE10_SR_DMA1_CH2) /*!< DMA1 Channel 2 Interrupt */
+#define HAL_ITLINE_DMA1_CH3 ((HAL_SYSCFG_ITLINE10 << 0x18U) | SYSCFG_ITLINE10_SR_DMA1_CH3) /*!< DMA1 Channel 3 Interrupt */
+#define HAL_ITLINE_DMAMUX ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMAMUX) /*!< DMAMUX Interrupt */
+#define HAL_ITLINE_ADC ((HAL_SYSCFG_ITLINE12 << 0x18U) | SYSCFG_ITLINE12_SR_ADC) /*!< ADC Interrupt */
+#define HAL_ITLINE_TIM1_BRK ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_BRK) /*!< TIM1 BRK Interrupt */
+#define HAL_ITLINE_TIM1_UPD ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_UPD) /*!< TIM1 UPD Interrupt */
+#define HAL_ITLINE_TIM1_TRG ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_TRG) /*!< TIM1 TRG Interrupt */
+#define HAL_ITLINE_TIM1_CCU ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_CCU) /*!< TIM1 CCU Interrupt */
+#define HAL_ITLINE_TIM3 ((HAL_SYSCFG_ITLINE16 << 0x18U) | SYSCFG_ITLINE16_SR_TIM3_GLB) /*!< TIM3 Interrupt */
+#define HAL_ITLINE_TIM14 ((HAL_SYSCFG_ITLINE19 << 0x18U) | SYSCFG_ITLINE19_SR_TIM14_GLB) /*!< TIM14 Interrupt */
+#define HAL_ITLINE_TIM16 ((HAL_SYSCFG_ITLINE21 << 0x18U) | SYSCFG_ITLINE21_SR_TIM16_GLB) /*!< TIM16 Interrupt */
+#define HAL_ITLINE_TIM17 ((HAL_SYSCFG_ITLINE22 << 0x18U) | SYSCFG_ITLINE22_SR_TIM17_GLB) /*!< TIM17 Interrupt */
+#define HAL_ITLINE_I2C1 ((HAL_SYSCFG_ITLINE23 << 0x18U) | SYSCFG_ITLINE23_SR_I2C1_GLB) /*!< I2C1 Interrupt */
+#define HAL_ITLINE_SPI1 ((HAL_SYSCFG_ITLINE25 << 0x18U) | SYSCFG_ITLINE25_SR_SPI1) /*!< SPI1 Interrupt */
+#define HAL_ITLINE_USART1 ((HAL_SYSCFG_ITLINE27 << 0x18U) | SYSCFG_ITLINE27_SR_USART1_GLB) /*!< USART1 GLB Interrupt */
+#define HAL_ITLINE_USART2 ((HAL_SYSCFG_ITLINE28 << 0x18U) | SYSCFG_ITLINE28_SR_USART2_GLB) /*!< USART2 GLB Interrupt */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup HAL_Exported_Macros HAL Exported Macros
+ * @{
+ */
+
+/** @defgroup DBG_Exported_Macros DBG Exported Macros
+ * @{
+ */
+
+/** @brief Freeze and Unfreeze Peripherals in Debug mode
+ */
+
+#if defined(DBG_APB_FZ1_DBG_TIM3_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM3_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM3_STOP)
+#endif
+
+#if defined(DBG_APB_FZ1_DBG_RTC_STOP)
+#define __HAL_DBGMCU_FREEZE_RTC() SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_RTC_STOP)
+#define __HAL_DBGMCU_UNFREEZE_RTC() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_RTC_STOP)
+#endif
+
+#if defined(DBG_APB_FZ1_DBG_WWDG_STOP)
+#define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_WWDG_STOP)
+#define __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_WWDG_STOP)
+#endif
+
+#if defined(DBG_APB_FZ1_DBG_IWDG_STOP)
+#define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_IWDG_STOP)
+#define __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_IWDG_STOP)
+#endif
+
+#if defined(DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP)
+#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP)
+#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP)
+#endif
+
+#if defined(DBG_APB_FZ2_DBG_TIM1_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM1() SET_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM1_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM1_STOP)
+#endif
+
+#if defined(DBG_APB_FZ2_DBG_TIM14_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM14() SET_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM14_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM14() CLEAR_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM14_STOP)
+#endif
+
+#if defined(DBG_APB_FZ2_DBG_TIM16_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM16() SET_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM16_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM16() CLEAR_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM16_STOP)
+#endif
+
+#if defined(DBG_APB_FZ2_DBG_TIM17_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM17() SET_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM17_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM17() CLEAR_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM17_STOP)
+#endif
+
+/**
+ * @}
+ */
+
+/** @defgroup SYSCFG_Exported_Macros SYSCFG Exported Macros
+ * @{
+ */
+
+/**
+ * @brief ISR wrapper check
+ * @note Allow to determine interrupt source per line.
+ */
+#define __HAL_GET_PENDING_IT(__SOURCE__) (SYSCFG->IT_LINE_SR[((__SOURCE__) >> 0x18U)] & ((__SOURCE__) & 0x00FFFFFF))
+
+/** @brief Main Flash memory mapped at 0x00000000
+ */
+#define __HAL_SYSCFG_REMAPMEMORY_FLASH() CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE)
+
+/** @brief System Flash memory mapped at 0x00000000
+ */
+#define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE, SYSCFG_CFGR1_MEM_MODE_0)
+
+/** @brief Embedded SRAM mapped at 0x00000000
+ */
+#define __HAL_SYSCFG_REMAPMEMORY_SRAM() \
+ MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE, (SYSCFG_CFGR1_MEM_MODE_1|SYSCFG_CFGR1_MEM_MODE_0))
+
+/**
+ * @brief Return the boot mode as configured by user.
+ * @retval The boot mode as configured by user. The returned value can be one
+ * of the following values @ref SYSCFG_BootMode
+ */
+#define __HAL_SYSCFG_GET_BOOT_MODE() READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE)
+
+/** @brief SYSCFG Break Cortex-M0+ Lockup lock.
+ * Enables and locks the connection of Cortex-M0+ LOCKUP (Hardfault) output to TIM1/16/17 Break input
+ * @note The selected configuration is locked and can be unlocked only by system reset.
+ */
+#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL)
+
+/** @brief Fast-mode Plus driving capability enable/disable macros
+ * @param __FASTMODEPLUS__ This parameter can be a value of @ref SYSCFG_FastModePlus_GPIO
+ */
+#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
+ SET_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\
+ }while(0U)
+
+#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
+ CLEAR_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\
+ }while(0U)
+
+
+/** @brief selection of the modulation envelope signal macro, using bits [7:6] of SYSCFG_CFGR1 register
+ * @param __SOURCE__ This parameter can be a value of @ref HAL_IR_ENV_SEL
+ */
+#define __HAL_SYSCFG_IRDA_ENV_SELECTION(__SOURCE__) do {assert_param(IS_HAL_SYSCFG_IRDA_ENV_SEL((__SOURCE__)));\
+ CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_IR_MOD);\
+ SET_BIT(SYSCFG->CFGR1, (__SOURCE__));\
+ }while(0U)
+
+#define __HAL_SYSCFG_GET_IRDA_ENV_SELECTION() ((SYSCFG->CFGR1) & 0x000000C0U)
+
+/** @brief IROut Polarity Selection, using bit[5] of SYSCFG_CFGR1 register
+ * @param __SEL__ This parameter can be a value of @ref HAL_IR_POL_SEL
+ */
+#define __HAL_SYSCFG_IRDA_OUT_POLARITY_SELECTION(__SEL__) do { assert_param(IS_HAL_SYSCFG_IRDA_POL_SEL((__SEL__)));\
+ CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_IR_POL);\
+ SET_BIT(SYSCFG->CFGR1,(__SEL__));\
+ }while(0U)
+
+/**
+ * @brief Return the IROut Polarity mode as configured by user.
+ * @retval The IROut polarity as configured by user. The returned value can be one
+ * of @ref HAL_IR_POL_SEL
+ */
+#define __HAL_SYSCFG_GET_POLARITY() READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_IR_POL)
+
+/** @brief Break input to TIM1/16/17 capability enable/disable macros
+ * @param __BREAK__ This parameter can be a value of @ref SYSCFG_Break
+ */
+#define __HAL_SYSCFG_BREAK_ENABLE(__BREAK__) do {assert_param(IS_SYSCFG_BREAK_CONFIG((__BREAK__)));\
+ SET_BIT(SYSCFG->CFGR2, (__BREAK__));\
+ }while(0U)
+
+#define __HAL_SYSCFG_BREAK_DISABLE(__BREAK__) do {assert_param(IS_SYSCFG_BREAK_CONFIG((__BREAK__)));\
+ CLEAR_BIT(SYSCFG->CFGR2, (__BREAK__));\
+ }while(0U)
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup SYSCFG_Private_Macros SYSCFG Private Macros
+ * @{
+ */
+
+#define IS_SYSCFG_BREAK_CONFIG(__CONFIG__) ((__CONFIG__) == SYSCFG_BREAK_LOCKUP)
+
+#define IS_HAL_SYSCFG_IRDA_ENV_SEL(SEL) (((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_TIM16) || \
+ ((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_USART1) || \
+ ((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_USART2))
+
+#define IS_HAL_SYSCFG_IRDA_POL_SEL(SEL) (((SEL) == HAL_SYSCFG_IRDA_POLARITY_NOT_INVERTED) || \
+ ((SEL) == HAL_SYSCFG_IRDA_POLARITY_INVERTED))
+
+
+#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PC14) == SYSCFG_FASTMODEPLUS_PC14) || \
+ (((__PIN__) & SYSCFG_FASTMODEPLUS_PA9) == SYSCFG_FASTMODEPLUS_PA9) || \
+ (((__PIN__) & SYSCFG_FASTMODEPLUS_PA10) == SYSCFG_FASTMODEPLUS_PA10) || \
+ (((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
+ (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \
+ (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \
+ (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9))
+
+#define IS_HAL_REMAP_PIN(RMP) (((RMP) == SYSCFG_REMAP_PA11) || \
+ ((RMP) == SYSCFG_REMAP_PA12) || \
+ ((RMP) == (SYSCFG_REMAP_PA11 | SYSCFG_REMAP_PA12)))
+#if (DEV_ID == 0x443UL)
+#define IS_HAL_SYSCFG_PINBINDING(PIN) (((PIN) == HAL_BIND_SO8_PIN1_PB7) || \
+ ((PIN) == HAL_BIND_SO8_PIN1_PC14) || \
+ ((PIN) == HAL_BIND_SO8_PIN4_PF2) || \
+ ((PIN) == HAL_BIND_SO8_PIN4_PA0) || \
+ ((PIN) == HAL_BIND_SO8_PIN4_PA1) || \
+ ((PIN) == HAL_BIND_SO8_PIN4_PA2) || \
+ ((PIN) == HAL_BIND_SO8_PIN5_PA8) || \
+ ((PIN) == HAL_BIND_SO8_PIN5_PA11) || \
+ ((PIN) == HAL_BIND_SO8_PIN8_PA14) || \
+ ((PIN) == HAL_BIND_SO8_PIN8_PB6) || \
+ ((PIN) == HAL_BIND_SO8_PIN8_PC15) || \
+ ((PIN) == HAL_BIND_WLCSP12_PINE2_PA7) || \
+ ((PIN) == HAL_BIND_WLCSP12_PINE2_PA12) || \
+ ((PIN) == HAL_BIND_WLCSP12_PINF1_PA3) || \
+ ((PIN) == HAL_BIND_WLCSP12_PINF1_PA4) || \
+ ((PIN) == HAL_BIND_WLCSP12_PINF1_PA5) || \
+ ((PIN) == HAL_BIND_WLCSP12_PINF1_PA6))
+#elif (DEV_ID == 0x453UL)
+#define IS_HAL_SYSCFG_PINBINDING(PIN) (((PIN) == HAL_BIND_WLCSP14_PINF2_PA1) || \
+ ((PIN) == HAL_BIND_WLCSP14_PINF2_PA2) || \
+ ((PIN) == HAL_BIND_WLCSP14_PING3_PF2) || \
+ ((PIN) == HAL_BIND_WLCSP14_PING3_PA0) || \
+ ((PIN) == HAL_BIND_WLCSP14_PINJ1_PA8) || \
+ ((PIN) == HAL_BIND_WLCSP14_PINJ1_PA11) || \
+ ((PIN) == HAL_BIND_WLCSP14_PINH2_PA5) || \
+ ((PIN) == HAL_BIND_WLCSP14_PINH2_PA6) || \
+ ((PIN) == HAL_BIND_WLCSP14_PING1_PA7) || \
+ ((PIN) == HAL_BIND_WLCSP14_PING1_PA12)|| \
+ ((PIN) == HAL_BIND_WLCSP14_PINJ3_PA3) || \
+ ((PIN) == HAL_BIND_WLCSP14_PINJ3_PA4))
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup HAL_Private_Macros HAL Private Macros
+ * @{
+ */
+#define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || \
+ ((FREQ) == HAL_TICK_FREQ_100HZ) || \
+ ((FREQ) == HAL_TICK_FREQ_1KHZ))
+/**
+ * @}
+ */
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup HAL_Exported_Functions HAL Exported Functions
+ * @{
+ */
+
+/** @defgroup HAL_Exported_Functions_Group1 HAL Initialization and Configuration functions
+ * @{
+ */
+
+/* Initialization and Configuration functions ******************************/
+HAL_StatusTypeDef HAL_Init(void);
+HAL_StatusTypeDef HAL_DeInit(void);
+void HAL_MspInit(void);
+void HAL_MspDeInit(void);
+HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority);
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_Exported_Functions_Group2 HAL Control functions
+ * @{
+ */
+
+/* Peripheral Control functions ************************************************/
+void HAL_IncTick(void);
+void HAL_Delay(uint32_t Delay);
+uint32_t HAL_GetTick(void);
+uint32_t HAL_GetTickPrio(void);
+HAL_StatusTypeDef HAL_SetTickFreq(uint32_t Freq);
+uint32_t HAL_GetTickFreq(void);
+void HAL_SuspendTick(void);
+void HAL_ResumeTick(void);
+uint32_t HAL_GetHalVersion(void);
+uint32_t HAL_GetREVID(void);
+uint32_t HAL_GetDEVID(void);
+uint32_t HAL_GetUIDw0(void);
+uint32_t HAL_GetUIDw1(void);
+uint32_t HAL_GetUIDw2(void);
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_Exported_Functions_Group3 DBGMCU Control functions
+ * @{
+ */
+
+/* DBGMCU Peripheral Control functions *****************************************/
+void HAL_DBGMCU_EnableDBGStopMode(void);
+void HAL_DBGMCU_DisableDBGStopMode(void);
+void HAL_DBGMCU_EnableDBGStandbyMode(void);
+void HAL_DBGMCU_DisableDBGStandbyMode(void);
+
+/**
+ * @}
+ */
+
+/* Exported variables ---------------------------------------------------------*/
+/** @addtogroup HAL_Exported_Variables
+ * @{
+ */
+extern __IO uint32_t uwTick;
+extern uint32_t uwTickPrio;
+extern uint32_t uwTickFreq;
+/**
+ * @}
+ */
+
+/** @defgroup HAL_Exported_Functions_Group4 SYSCFG configuration functions
+ * @{
+ */
+
+/* SYSCFG Control functions ****************************************************/
+
+void HAL_SYSCFG_EnableIOAnalogSwitchBooster(void);
+void HAL_SYSCFG_DisableIOAnalogSwitchBooster(void);
+void HAL_SYSCFG_EnableRemap(uint32_t PinRemap);
+void HAL_SYSCFG_DisableRemap(uint32_t PinRemap);
+void HAL_SYSCFG_SetPinBinding(uint32_t pin_binding);
+uint32_t HAL_SYSCFG_GetPinBinding(void);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32C0xx_HAL_H */
diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h b/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h
new file mode 100644
index 0000000000..b501f7ec1c
--- /dev/null
+++ b/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h
@@ -0,0 +1,1723 @@
+/**
+ ******************************************************************************
+ * @file stm32c0xx_hal_adc.h
+ * @author MCD Application Team
+ * @brief Header file of ADC HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2022 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32C0xx_HAL_ADC_H
+#define STM32C0xx_HAL_ADC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32c0xx_hal_def.h"
+
+/* Include low level driver */
+#include "stm32c0xx_ll_adc.h"
+
+/** @addtogroup STM32C0xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup ADC
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup ADC_Exported_Types ADC Exported Types
+ * @{
+ */
+
+/**
+ * @brief ADC group regular oversampling structure definition
+ */
+typedef struct
+{
+ uint32_t Ratio; /*!< Configures the oversampling ratio.
+ This parameter can be a value of @ref ADC_HAL_EC_OVS_RATIO */
+
+ uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler.
+ This parameter can be a value of @ref ADC_HAL_EC_OVS_SHIFT */
+
+ uint32_t TriggeredMode; /*!< Selects the regular triggered oversampling mode.
+ This parameter can be a value of @ref ADC_HAL_EC_OVS_DISCONT_MODE */
+
+} ADC_OversamplingTypeDef;
+
+/**
+ * @brief Structure definition of ADC instance and ADC group regular.
+ * @note Parameters of this structure are shared within 2 scopes:
+ * - Scope entire ADC (differentiation done for compatibility with some other STM32 series featuring ADC groups regular and injected): ClockPrescaler, Resolution, DataAlign,
+ * ScanConvMode, EOCSelection, LowPowerAutoWait.
+ * - Scope ADC group regular: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode,
+ * ExternalTrigConv, ExternalTrigConvEdge, DMAContinuousRequests, Overrun, OversamplingMode, Oversampling.
+ * @note The setting of these parameters by function HAL_ADC_Init() is conditioned to ADC state.
+ * ADC state can be either:
+ * - For all parameters: ADC disabled
+ * - For all parameters except 'ClockPrescaler' and 'Resolution': ADC enabled without conversion on going on group regular.
+ * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
+ * without error reporting (as it can be the expected behavior in case of intended action to update another parameter
+ * (which fulfills the ADC state condition) on the fly).
+ */
+typedef struct
+{
+ uint32_t ClockPrescaler; /*!< Select ADC clock source (synchronous clock derived from APB clock or asynchronous clock derived from system clock or PLL (Refer to reference manual for list of clocks available)) and clock prescaler.
+ This parameter can be a value of @ref ADC_HAL_EC_COMMON_CLOCK_SOURCE.
+ Note: The ADC clock configuration is common to all ADC instances.
+ Note: In case of synchronous clock mode based on HCLK/1, the configuration must be enabled only
+ if the system clock has a 50% duty clock cycle (APB prescaler configured inside RCC
+ must be bypassed and PCLK clock must have 50% duty cycle). Refer to reference manual for details.
+ Note: In case of usage of asynchronous clock, the selected clock must be preliminarily enabled at RCC top level.
+ Note: This parameter can be modified only if all ADC instances are disabled. */
+
+ uint32_t Resolution; /*!< Configure the ADC resolution.
+ This parameter can be a value of @ref ADC_HAL_EC_RESOLUTION */
+
+ uint32_t DataAlign; /*!< Specify ADC data alignment in conversion data register (right or left).
+ Refer to reference manual for alignments formats versus resolutions.
+ This parameter can be a value of @ref ADC_HAL_EC_DATA_ALIGN */
+
+ uint32_t ScanConvMode; /*!< Configure the sequencer of ADC group regular.
+ On this STM32 series, ADC group regular sequencer both modes "fully configurable" or "not fully configurable" are
+ available:
+ - sequencer configured to fully configurable:
+ sequencer length and each rank affectation to a channel are configurable.
+ - Sequence length: Set number of ranks in the scan sequence.
+ - Sequence direction: Unless specified in parameters, sequencer
+ scan direction is forward (from rank 1 to rank n).
+ - sequencer configured to not fully configurable:
+ sequencer length and each rank affectation to a channel are fixed by channel HW number.
+ - Sequence length: Number of ranks in the scan sequence is
+ defined by number of channels set in the sequence,
+ rank of each channel is fixed by channel HW number.
+ (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
+ - Sequence direction: Unless specified in parameters, sequencer
+ scan direction is forward (from lowest channel number to
+ highest channel number).
+ This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts.
+ Sequencer is automatically enabled if several channels are set (sequencer cannot be disabled, as it can be the case on other STM32 devices):
+ If only 1 channel is set: Conversion is performed in single mode.
+ If several channels are set: Conversions are performed in sequence mode.
+ This parameter can be a value of @ref ADC_Scan_mode */
+
+ uint32_t EOCSelection; /*!< Specify which EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of unitary conversion or end of sequence conversions.
+ This parameter can be a value of @ref ADC_EOCSelection. */
+
+ FunctionalState LowPowerAutoWait; /*!< Select the dynamic low power Auto Delay: new conversion start only when the previous
+ conversion (for ADC group regular) has been retrieved by user software,
+ using function HAL_ADC_GetValue().
+ This feature automatically adapts the frequency of ADC conversions triggers to the speed of the system that reads the data. Moreover, this avoids risk of overrun
+ for low frequency applications.
+ This parameter can be set to ENABLE or DISABLE.
+ Note: It is not recommended to use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since these modes have to clear immediately the EOC flag (by CPU to free the IRQ pending event or by DMA).
+ Auto wait will work but fort a very short time, discarding its intended benefit (except specific case of high load of CPU or DMA transfers which can justify usage of auto wait).
+ Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, when ADC conversion data is needed:
+ use HAL_ADC_PollForConversion() to ensure that conversion is completed and HAL_ADC_GetValue() to retrieve conversion result and trig another conversion start. */
+
+ FunctionalState LowPowerAutoPowerOff; /*!< Select the auto-off mode: the ADC automatically powers-off after a conversion and automatically wakes-up when a new conversion is triggered (with startup time between trigger and start of sampling).
+ This feature can be combined with automatic wait mode (parameter 'LowPowerAutoWait').
+ This parameter can be set to ENABLE or DISABLE.
+ Note: If enabled, this feature also turns off the ADC dedicated 14 MHz RC oscillator (HSI14) */
+
+ FunctionalState ContinuousConvMode; /*!< Specify whether the conversion is performed in single mode (one conversion) or continuous mode for ADC group regular,
+ after the first ADC conversion start trigger occurred (software start or external trigger).
+ This parameter can be set to ENABLE or DISABLE. */
+
+ uint32_t NbrOfConversion; /*!< Specify the number of ranks that will be converted within the regular group sequencer.
+ This parameter is dependent on ScanConvMode:
+ - sequencer configured to fully configurable:
+ Number of ranks in the scan sequence is configurable using this parameter.
+ Note: After the first call of 'HAL_ADC_Init()', each rank corresponding to parameter "NbrOfConversion" must be set using 'HAL_ADC_ConfigChannel()'.
+ Afterwards, when all needed sequencer ranks are set, parameter 'NbrOfConversion' can be updated without modifying configuration of sequencer ranks
+ (sequencer ranks above 'NbrOfConversion' are discarded).
+ - sequencer configured to not fully configurable:
+ Number of ranks in the scan sequence is defined by number of channels set in the sequence. This parameter is discarded.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 8.
+ Note: This parameter must be modified when no conversion is on going on regular group (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). */
+
+ FunctionalState DiscontinuousConvMode; /*!< Specify whether the conversions sequence of ADC group regular is performed in Complete-sequence/Discontinuous-sequence
+ (main sequence subdivided in successive parts).
+ Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
+ Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
+ This parameter can be set to ENABLE or DISABLE.
+ Note: On this STM32 series, ADC group regular number of discontinuous ranks increment is fixed to one-by-one. */
+
+ uint32_t ExternalTrigConv; /*!< Select the external event source used to trigger ADC group regular conversion start.
+ If set to ADC_SOFTWARE_START, external triggers are disabled and software trigger is used instead.
+ This parameter can be a value of @ref ADC_regular_external_trigger_source.
+ Caution: external trigger source is common to all ADC instances. */
+
+ uint32_t ExternalTrigConvEdge; /*!< Select the external event edge used to trigger ADC group regular conversion start.
+ If trigger source is set to ADC_SOFTWARE_START, this parameter is discarded.
+ This parameter can be a value of @ref ADC_regular_external_trigger_edge */
+
+ FunctionalState DMAContinuousRequests; /*!< Specify whether the DMA requests are performed in one shot mode (DMA transfer stops when number of conversions is reached)
+ or in continuous mode (DMA transfer unlimited, whatever number of conversions).
+ This parameter can be set to ENABLE or DISABLE.
+ Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached. */
+
+ uint32_t Overrun; /*!< Select the behavior in case of overrun: data overwritten or preserved (default).
+ This parameter can be a value of @ref ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR.
+ Note: In case of overrun set to data preserved and usage with programming model with interruption (HAL_Start_IT()): ADC IRQ handler has to clear
+ end of conversion flags, this induces the release of the preserved data. If needed, this data can be saved in function
+ HAL_ADC_ConvCpltCallback(), placed in user program code (called before end of conversion flags clear).
+ Note: Error reporting with respect to the conversion mode:
+ - Usage with ADC conversion by polling for event or interruption: Error is reported only if overrun is set to data preserved. If overrun is set to data
+ overwritten, user can willingly not read all the converted data, this is not considered as an erroneous case.
+ - Usage with ADC conversion by DMA: Error is reported whatever overrun setting (DMA is expected to process all data from data register). */
+
+ uint32_t SamplingTimeCommon1; /*!< Set sampling time common to a group of channels.
+ Unit: ADC clock cycles
+ Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits).
+ Note: On this STM32 family, two different sampling time settings are available, each channel can use one of these two settings. On some other STM32 devices, this parameter in channel wise and is located into ADC channel initialization structure.
+ This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME
+ Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
+ sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
+ Refer to device datasheet for timings values, parameters TS_vrefint, TS_vbat, TS_temp (values rough order: few tens of microseconds). */
+
+ uint32_t SamplingTimeCommon2; /*!< Set sampling time common to a group of channels, second common setting possible.
+ Unit: ADC clock cycles
+ Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits).
+ Note: On this STM32 family, two different sampling time settings are available, each channel can use one of these two settings. On some other STM32 devices, this parameter in channel wise and is located into ADC channel initialization structure.
+ This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME
+ Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
+ sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
+ Refer to device datasheet for timings values, parameters TS_vrefint, TS_vbat, TS_temp (values rough order: few tens of microseconds). */
+
+ FunctionalState OversamplingMode; /*!< Specify whether the oversampling feature is enabled or disabled.
+ This parameter can be set to ENABLE or DISABLE.
+ Note: This parameter can be modified only if there is no conversion is ongoing on ADC group regular. */
+
+ ADC_OversamplingTypeDef Oversampling; /*!< Specify the Oversampling parameters.
+ Caution: this setting overwrites the previous oversampling configuration if oversampling is already enabled. */
+
+ uint32_t TriggerFrequencyMode; /*!< Set ADC trigger frequency mode.
+ This parameter can be a value of @ref ADC_HAL_EC_REG_TRIGGER_FREQ.
+ Note: ADC trigger frequency mode must be set to low frequency when
+ a duration is exceeded before ADC conversion start trigger event
+ (between ADC enable and ADC conversion start trigger event
+ or between two ADC conversion start trigger event).
+ Duration value: Refer to device datasheet, parameter "tIdle".
+ Note: When ADC trigger frequency mode is set to low frequency,
+ some rearm cycles are inserted before performing ADC conversion
+ start, inducing a delay of 2 ADC clock cycles. */
+
+} ADC_InitTypeDef;
+
+/**
+ * @brief Structure definition of ADC channel for regular group
+ * @note The setting of these parameters by function HAL_ADC_ConfigChannel() is conditioned to ADC state.
+ * ADC state can be either:
+ * - For all parameters: ADC disabled or enabled without conversion on going on regular group.
+ * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
+ * without error reporting (as it can be the expected behavior in case of intended action to update another parameter (which fulfills the ADC state condition)
+ * on the fly).
+ */
+typedef struct
+{
+ uint32_t Channel; /*!< Specify the channel to configure into ADC regular group.
+ This parameter can be a value of @ref ADC_HAL_EC_CHANNEL
+ Note: Depending on devices and ADC instances, some channels may not be available on device package pins. Refer to device datasheet for channels availability. */
+
+ uint32_t Rank; /*!< Add or remove the channel from ADC regular group sequencer and specify its conversion rank.
+ This parameter is dependent on ScanConvMode:
+ - sequencer configured to fully configurable:
+ Channels ordering into each rank of scan sequence:
+ whatever channel can be placed into whatever rank.
+ - sequencer configured to not fully configurable:
+ rank of each channel is fixed by channel HW number.
+ (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
+ Despite the channel rank is fixed, this parameter allow an additional possibility: to remove the selected rank (selected channel) from sequencer.
+ This parameter can be a value of @ref ADC_HAL_EC_REG_SEQ_RANKS */
+
+ uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel.
+ Unit: ADC clock cycles
+ Conversion time is the addition of sampling time and processing time
+ (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits).
+ This parameter can be a value of @ref ADC_HAL_EC_SAMPLINGTIME_COMMON
+ Note: On this STM32 family, two different sampling time settings are available (refer to parameters "SamplingTimeCommon1" and "SamplingTimeCommon2"), each channel can use one of these two settings.
+
+ Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
+ sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
+ Refer to device datasheet for timings values. */
+
+} ADC_ChannelConfTypeDef;
+
+/**
+ * @brief Structure definition of ADC analog watchdog
+ * @note The setting of these parameters by function HAL_ADC_AnalogWDGConfig() is conditioned to ADC state.
+ * ADC state can be either:
+ * - For all parameters except 'HighThreshold', 'LowThreshold': ADC disabled or ADC enabled without conversion on going on ADC groups regular.
+ * - For parameters 'HighThreshold', 'LowThreshold': ADC enabled with conversion on going on regular.
+ */
+typedef struct
+{
+ uint32_t WatchdogNumber; /*!< Select which ADC analog watchdog is monitoring the selected channel.
+ For Analog Watchdog 1: Only 1 channel can be monitored (or overall group of channels by setting parameter 'WatchdogMode')
+ For Analog Watchdog 2 and 3: Several channels can be monitored (by successive calls of 'HAL_ADC_AnalogWDGConfig()' for each channel)
+ This parameter can be a value of @ref ADC_HAL_EC_AWD_NUMBER. */
+
+ uint32_t WatchdogMode; /*!< Configure the ADC analog watchdog mode: single/all/none channels.
+ For Analog Watchdog 1: Configure the ADC analog watchdog mode: single channel or all channels, ADC group regular.
+ For Analog Watchdog 2 and 3: Several channels can be monitored by applying successively the AWD init structure.
+ This parameter can be a value of @ref ADC_analog_watchdog_mode. */
+
+ uint32_t Channel; /*!< Select which ADC channel to monitor by analog watchdog.
+ For Analog Watchdog 1: this parameter has an effect only if parameter 'WatchdogMode' is configured on single channel (only 1 channel can be monitored).
+ For Analog Watchdog 2 and 3: Several channels can be monitored. To use this feature, call successively the function HAL_ADC_AnalogWDGConfig() for each channel to be added (or removed with value 'ADC_ANALOGWATCHDOG_NONE').
+ This parameter can be a value of @ref ADC_HAL_EC_CHANNEL. */
+
+ FunctionalState ITMode; /*!< Specify whether the analog watchdog is configured in interrupt or polling mode.
+ This parameter can be set to ENABLE or DISABLE */
+
+ uint32_t HighThreshold; /*!< Configure the ADC analog watchdog High threshold value.
+ Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number
+ between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively.
+ Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits
+ the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored.
+ Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are
+ impacted: the comparison of analog watchdog thresholds is done on
+ oversampling final computation (after ratio and shift application):
+ ADC data register bitfield [15:4] (12 most significant bits). */
+
+ uint32_t LowThreshold; /*!< Configures the ADC analog watchdog Low threshold value.
+ Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number
+ between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively.
+ Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits
+ the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored.
+ Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are
+ impacted: the comparison of analog watchdog thresholds is done on
+ oversampling final computation (after ratio and shift application):
+ ADC data register bitfield [15:4] (12 most significant bits). */
+} ADC_AnalogWDGConfTypeDef;
+
+/** @defgroup ADC_States ADC States
+ * @{
+ */
+
+/**
+ * @brief HAL ADC state machine: ADC states definition (bitfields)
+ * @note ADC state machine is managed by bitfields, state must be compared
+ * with bit by bit.
+ * For example:
+ * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_REG_BUSY) != 0UL) "
+ * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) "
+ */
+/* States of ADC global scope */
+#define HAL_ADC_STATE_RESET (0x00000000UL) /*!< ADC not yet initialized or disabled */
+#define HAL_ADC_STATE_READY (0x00000001UL) /*!< ADC peripheral ready for use */
+#define HAL_ADC_STATE_BUSY_INTERNAL (0x00000002UL) /*!< ADC is busy due to an internal process (initialization, calibration) */
+#define HAL_ADC_STATE_TIMEOUT (0x00000004UL) /*!< TimeOut occurrence */
+
+/* States of ADC errors */
+#define HAL_ADC_STATE_ERROR_INTERNAL (0x00000010UL) /*!< Internal error occurrence */
+#define HAL_ADC_STATE_ERROR_CONFIG (0x00000020UL) /*!< Configuration error occurrence */
+#define HAL_ADC_STATE_ERROR_DMA (0x00000040UL) /*!< DMA error occurrence */
+
+/* States of ADC group regular */
+#define HAL_ADC_STATE_REG_BUSY (0x00000100UL) /*!< A conversion on ADC group regular is ongoing or can occur (either by continuous mode,
+ external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
+#define HAL_ADC_STATE_REG_EOC (0x00000200UL) /*!< Conversion data available on group regular */
+#define HAL_ADC_STATE_REG_OVR (0x00000400UL) /*!< Overrun occurrence */
+#define HAL_ADC_STATE_REG_EOSMP (0x00000800UL) /*!< Not available on this STM32 series: End Of Sampling flag raised */
+
+/* States of ADC group injected */
+#define HAL_ADC_STATE_INJ_BUSY (0x00001000UL) /*!< Not available on this STM32 series: A conversion on group injected is ongoing or can occur (either by auto-injection mode,
+ external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available))*/
+#define HAL_ADC_STATE_INJ_EOC (0x00002000UL) /*!< Not available on this STM32 series: Conversion data available on group injected */
+#define HAL_ADC_STATE_INJ_JQOVF (0x00004000UL) /*!< Not available on this STM32 series: Injected queue overflow occurrence */
+
+/* States of ADC analog watchdogs */
+#define HAL_ADC_STATE_AWD1 (0x00010000UL) /*!< Out-of-window occurrence of ADC analog watchdog 1 */
+#define HAL_ADC_STATE_AWD2 (0x00020000UL) /*!< Not available on this STM32 series: Out-of-window occurrence of ADC analog watchdog 2 */
+#define HAL_ADC_STATE_AWD3 (0x00040000UL) /*!< Not available on this STM32 series: Out-of-window occurrence of ADC analog watchdog 3 */
+
+/* States of ADC multi-mode */
+#define HAL_ADC_STATE_MULTIMODE_SLAVE (0x00100000UL) /*!< Not available on this STM32 series: ADC in multimode slave state, controlled by another ADC master (when feature available) */
+
+
+/**
+ * @}
+ */
+
+/**
+ * @brief ADC handle Structure definition
+ */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+typedef struct __ADC_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+{
+ ADC_TypeDef *Instance; /*!< Register base address */
+ ADC_InitTypeDef Init; /*!< ADC initialization parameters and regular conversions setting */
+ DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */
+ HAL_LockTypeDef Lock; /*!< ADC locking object */
+ __IO uint32_t State; /*!< ADC communication state (bitmap of ADC states) */
+ __IO uint32_t ErrorCode; /*!< ADC Error code */
+
+ uint32_t ADCGroupRegularSequencerRanks; /*!< ADC group regular sequencer memorization of ranks setting, used in mode "fully configurable" (refer to parameter 'ScanConvMode') */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+ void (* ConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion complete callback */
+ void (* ConvHalfCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion DMA half-transfer callback */
+ void (* LevelOutOfWindowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 1 callback */
+ void (* ErrorCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC error callback */
+ void (* LevelOutOfWindow2Callback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 2 callback */
+ void (* LevelOutOfWindow3Callback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 3 callback */
+ void (* EndOfSamplingCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC end of sampling callback */
+ void (* MspInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp Init callback */
+ void (* MspDeInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp DeInit callback */
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+} ADC_HandleTypeDef;
+
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+/**
+ * @brief HAL ADC Callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_ADC_CONVERSION_COMPLETE_CB_ID = 0x00U, /*!< ADC conversion complete callback ID */
+ HAL_ADC_CONVERSION_HALF_CB_ID = 0x01U, /*!< ADC conversion DMA half-transfer callback ID */
+ HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID = 0x02U, /*!< ADC analog watchdog 1 callback ID */
+ HAL_ADC_ERROR_CB_ID = 0x03U, /*!< ADC error callback ID */
+ HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID = 0x06U, /*!< ADC analog watchdog 2 callback ID */
+ HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID = 0x07U, /*!< ADC analog watchdog 3 callback ID */
+ HAL_ADC_END_OF_SAMPLING_CB_ID = 0x08U, /*!< ADC end of sampling callback ID */
+ HAL_ADC_MSPINIT_CB_ID = 0x09U, /*!< ADC Msp Init callback ID */
+ HAL_ADC_MSPDEINIT_CB_ID = 0x0AU /*!< ADC Msp DeInit callback ID */
+} HAL_ADC_CallbackIDTypeDef;
+
+/**
+ * @brief HAL ADC Callback pointer definition
+ */
+typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to a ADC callback function */
+
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup ADC_Exported_Constants ADC Exported Constants
+ * @{
+ */
+
+/** @defgroup ADC_Error_Code ADC Error Code
+ * @{
+ */
+#define HAL_ADC_ERROR_NONE (0x00U) /*!< No error */
+#define HAL_ADC_ERROR_INTERNAL (0x01U) /*!< ADC peripheral internal error (problem of clocking,
+ enable/disable, erroneous state, ...) */
+#define HAL_ADC_ERROR_OVR (0x02U) /*!< Overrun error */
+#define HAL_ADC_ERROR_DMA (0x04U) /*!< DMA transfer error */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+#define HAL_ADC_ERROR_INVALID_CALLBACK (0x10U) /*!< Invalid Callback error */
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_HAL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source
+ * @{
+ */
+#define ADC_CLOCK_SYNC_PCLK_DIV1 (LL_ADC_CLOCK_SYNC_PCLK_DIV1) /*!< ADC synchronous clock derived from AHB clock without prescaler. This configuration must be enabled only if PCLK has a 50% duty clock cycle (APB prescaler configured inside the RCC must be bypassed and the system clock must by 50% duty cycle) */
+#define ADC_CLOCK_SYNC_PCLK_DIV2 (LL_ADC_CLOCK_SYNC_PCLK_DIV2) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 2 */
+#define ADC_CLOCK_SYNC_PCLK_DIV4 (LL_ADC_CLOCK_SYNC_PCLK_DIV4) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 4 */
+
+#define ADC_CLOCK_ASYNC_DIV1 (LL_ADC_CLOCK_ASYNC_DIV1) /*!< ADC asynchronous clock without prescaler */
+#define ADC_CLOCK_ASYNC_DIV2 (LL_ADC_CLOCK_ASYNC_DIV2) /*!< ADC asynchronous clock with prescaler division by 2 */
+#define ADC_CLOCK_ASYNC_DIV4 (LL_ADC_CLOCK_ASYNC_DIV4) /*!< ADC asynchronous clock with prescaler division by 4 */
+#define ADC_CLOCK_ASYNC_DIV6 (LL_ADC_CLOCK_ASYNC_DIV6) /*!< ADC asynchronous clock with prescaler division by 6 */
+#define ADC_CLOCK_ASYNC_DIV8 (LL_ADC_CLOCK_ASYNC_DIV8) /*!< ADC asynchronous clock with prescaler division by 8 */
+#define ADC_CLOCK_ASYNC_DIV10 (LL_ADC_CLOCK_ASYNC_DIV10) /*!< ADC asynchronous clock with prescaler division by 10 */
+#define ADC_CLOCK_ASYNC_DIV12 (LL_ADC_CLOCK_ASYNC_DIV12) /*!< ADC asynchronous clock with prescaler division by 12 */
+#define ADC_CLOCK_ASYNC_DIV16 (LL_ADC_CLOCK_ASYNC_DIV16) /*!< ADC asynchronous clock with prescaler division by 16 */
+#define ADC_CLOCK_ASYNC_DIV32 (LL_ADC_CLOCK_ASYNC_DIV32) /*!< ADC asynchronous clock with prescaler division by 32 */
+#define ADC_CLOCK_ASYNC_DIV64 (LL_ADC_CLOCK_ASYNC_DIV64) /*!< ADC asynchronous clock with prescaler division by 64 */
+#define ADC_CLOCK_ASYNC_DIV128 (LL_ADC_CLOCK_ASYNC_DIV128) /*!< ADC asynchronous clock with prescaler division by 128 */
+#define ADC_CLOCK_ASYNC_DIV256 (LL_ADC_CLOCK_ASYNC_DIV256) /*!< ADC asynchronous clock with prescaler division by 256 */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_HAL_EC_RESOLUTION ADC instance - Resolution
+ * @{
+ */
+#define ADC_RESOLUTION_12B (LL_ADC_RESOLUTION_12B) /*!< ADC resolution 12 bits */
+#define ADC_RESOLUTION_10B (LL_ADC_RESOLUTION_10B) /*!< ADC resolution 10 bits */
+#define ADC_RESOLUTION_8B (LL_ADC_RESOLUTION_8B) /*!< ADC resolution 8 bits */
+#define ADC_RESOLUTION_6B (LL_ADC_RESOLUTION_6B) /*!< ADC resolution 6 bits */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_HAL_EC_DATA_ALIGN ADC conversion data alignment
+ * @{
+ */
+#define ADC_DATAALIGN_RIGHT (LL_ADC_DATA_ALIGN_RIGHT)/*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/
+#define ADC_DATAALIGN_LEFT (LL_ADC_DATA_ALIGN_LEFT) /*!< ADC conversion data alignment: left aligned (alignment on data register MSB bit 15)*/
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Scan_mode ADC sequencer scan mode
+ * @{
+ */
+/* Note: On this STM32 family, ADC group regular sequencer both modes */
+/* "fully configurable" or "not fully configurable" are */
+/* available. */
+/* Scan mode values must be compatible with other STM32 devices having */
+/* a configurable sequencer. */
+/* Scan direction setting values are defined by taking in account */
+/* already defined values for other STM32 devices: */
+/* ADC_SCAN_DISABLE (0x00000000UL) */
+/* ADC_SCAN_ENABLE (0x00000001UL) */
+/* Sequencer fully configurable with only rank 1 enabled is considered */
+/* as default setting equivalent to scan enable. */
+/* In case of migration from another STM32 device, the user will be */
+/* warned of change of setting choices with assert check. */
+#define ADC_SCAN_DISABLE (0x00000000UL) /*!< Sequencer set to fully configurable: only the rank 1 is enabled (no scan sequence on several ranks) */
+#define ADC_SCAN_ENABLE (ADC_CFGR1_CHSELRMOD) /*!< Sequencer set to fully configurable: sequencer length and each rank affectation to a channel are configurable. */
+
+#define ADC_SCAN_SEQ_FIXED (ADC_SCAN_SEQ_FIXED_INT) /*!< Sequencer set to not fully configurable: sequencer length and each rank affectation to a channel are fixed by channel HW number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). Scan direction forward: from channel 0 to channel 18 */
+#define ADC_SCAN_SEQ_FIXED_BACKWARD (ADC_SCAN_SEQ_FIXED_INT | ADC_CFGR1_SCANDIR) /*!< Sequencer set to not fully configurable: sequencer length and each rank affectation to a channel are fixed by channel HW number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). Scan direction backward: from channel 18 to channel 0 */
+
+#define ADC_SCAN_DIRECTION_FORWARD (ADC_SCAN_SEQ_FIXED) /* For compatibility with other STM32 devices */
+#define ADC_SCAN_DIRECTION_BACKWARD (ADC_SCAN_SEQ_FIXED_BACKWARD) /* For compatibility with other STM32 devices */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_regular_external_trigger_source ADC group regular trigger source
+ * @{
+ */
+/* ADC group regular trigger sources for all ADC instances */
+#define ADC_SOFTWARE_START (LL_ADC_REG_TRIG_SOFTWARE) /*!< ADC group regular conversion trigger internal: SW start. */
+#define ADC_EXTERNALTRIG_T1_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIG_T1_CC4 (LL_ADC_REG_TRIG_EXT_TIM1_CH4) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#if defined(TIM2)
+#define ADC_EXTERNALTRIG_T2_TRGO (LL_ADC_REG_TRIG_EXT_TIM2_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
+#endif
+#define ADC_EXTERNALTRIG_T3_TRGO (LL_ADC_REG_TRIG_EXT_TIM3_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM3 TRGO. Trigger edge set to rising edge (default setting). */
+#if defined(TIM4)
+#define ADC_EXTERNALTRIG_T4_TRGO (LL_ADC_REG_TRIG_EXT_TIM4_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM4 TRGO. Trigger edge set to rising edge (default setting). */
+#endif
+#if defined(TIM6)
+#define ADC_EXTERNALTRIG_T6_TRGO (LL_ADC_REG_TRIG_EXT_TIM6_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM6 TRGO. Trigger edge set to rising edge (default setting). */
+#endif
+#if defined(TIM15)
+#define ADC_EXTERNALTRIG_T15_TRGO (LL_ADC_REG_TRIG_EXT_TIM15_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM15 TRGO. Trigger edge set to rising edge (default setting). */
+#endif
+#define ADC_EXTERNALTRIG_EXT_IT11 (LL_ADC_REG_TRIG_EXT_EXTI_LINE11) /*!< ADC group regular conversion trigger from external peripheral: external interrupt line 11. Trigger edge set to rising edge (default setting). */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_regular_external_trigger_edge ADC group regular trigger edge (when external trigger is selected)
+ * @{
+ */
+#define ADC_EXTERNALTRIGCONVEDGE_NONE (0x00000000UL) /*!< Regular conversions hardware trigger detection disabled */
+#define ADC_EXTERNALTRIGCONVEDGE_RISING (LL_ADC_REG_TRIG_EXT_RISING) /*!< ADC group regular conversion trigger polarity set to rising edge */
+#define ADC_EXTERNALTRIGCONVEDGE_FALLING (LL_ADC_REG_TRIG_EXT_FALLING) /*!< ADC group regular conversion trigger polarity set to falling edge */
+#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING (LL_ADC_REG_TRIG_EXT_RISINGFALLING) /*!< ADC group regular conversion trigger polarity set to both rising and falling edges */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_EOCSelection ADC sequencer end of unitary conversion or sequence conversions
+ * @{
+ */
+#define ADC_EOC_SINGLE_CONV (ADC_ISR_EOC) /*!< End of unitary conversion flag */
+#define ADC_EOC_SEQ_CONV (ADC_ISR_EOS) /*!< End of sequence conversions flag */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data
+ * @{
+ */
+#define ADC_OVR_DATA_PRESERVED (LL_ADC_REG_OVR_DATA_PRESERVED) /*!< ADC group regular behavior in case of overrun: data preserved */
+#define ADC_OVR_DATA_OVERWRITTEN (LL_ADC_REG_OVR_DATA_OVERWRITTEN) /*!< ADC group regular behavior in case of overrun: data overwritten */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_HAL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks
+ * @{
+ */
+#define ADC_RANK_CHANNEL_NUMBER (0x00000001U) /*!< Setting relevant if parameter "ScanConvMode" is set to sequencer not fully configurable: Enable the rank of the selected channels. Number of ranks in the sequence is defined by number of channels enabled, rank of each channel is defined by channel number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...) */
+#define ADC_RANK_NONE (0x00000002U) /*!< Setting relevant if parameter "ScanConvMode" is set to sequencer not fully configurable: Disable the selected rank (selected channel) from sequencer */
+
+#define ADC_REGULAR_RANK_1 (LL_ADC_REG_RANK_1) /*!< ADC group regular sequencer rank 1 */
+#define ADC_REGULAR_RANK_2 (LL_ADC_REG_RANK_2) /*!< ADC group regular sequencer rank 2 */
+#define ADC_REGULAR_RANK_3 (LL_ADC_REG_RANK_3) /*!< ADC group regular sequencer rank 3 */
+#define ADC_REGULAR_RANK_4 (LL_ADC_REG_RANK_4) /*!< ADC group regular sequencer rank 4 */
+#define ADC_REGULAR_RANK_5 (LL_ADC_REG_RANK_5) /*!< ADC group regular sequencer rank 5 */
+#define ADC_REGULAR_RANK_6 (LL_ADC_REG_RANK_6) /*!< ADC group regular sequencer rank 6 */
+#define ADC_REGULAR_RANK_7 (LL_ADC_REG_RANK_7) /*!< ADC group regular sequencer rank 7 */
+#define ADC_REGULAR_RANK_8 (LL_ADC_REG_RANK_8) /*!< ADC group regular sequencer rank 8 */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_HAL_EC_SAMPLINGTIME_COMMON ADC instance - Sampling time common to a group of channels
+ * @{
+ */
+#define ADC_SAMPLINGTIME_COMMON_1 (LL_ADC_SAMPLINGTIME_COMMON_1) /*!< Set sampling time common to a group of channels: sampling time nb 1 */
+#define ADC_SAMPLINGTIME_COMMON_2 (LL_ADC_SAMPLINGTIME_COMMON_2) /*!< Set sampling time common to a group of channels: sampling time nb 2 */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_HAL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time
+ * @{
+ */
+#define ADC_SAMPLETIME_1CYCLE_5 (LL_ADC_SAMPLINGTIME_1CYCLE_5) /*!< Sampling time 1.5 ADC clock cycle */
+#define ADC_SAMPLETIME_3CYCLES_5 (LL_ADC_SAMPLINGTIME_3CYCLES_5) /*!< Sampling time 3.5 ADC clock cycles */
+#define ADC_SAMPLETIME_7CYCLES_5 (LL_ADC_SAMPLINGTIME_7CYCLES_5) /*!< Sampling time 7.5 ADC clock cycles */
+#define ADC_SAMPLETIME_12CYCLES_5 (LL_ADC_SAMPLINGTIME_12CYCLES_5) /*!< Sampling time 12.5 ADC clock cycles */
+#define ADC_SAMPLETIME_19CYCLES_5 (LL_ADC_SAMPLINGTIME_19CYCLES_5) /*!< Sampling time 19.5 ADC clock cycles */
+#define ADC_SAMPLETIME_39CYCLES_5 (LL_ADC_SAMPLINGTIME_39CYCLES_5) /*!< Sampling time 39.5 ADC clock cycles */
+#define ADC_SAMPLETIME_79CYCLES_5 (LL_ADC_SAMPLINGTIME_79CYCLES_5) /*!< Sampling time 79.5 ADC clock cycles */
+#define ADC_SAMPLETIME_160CYCLES_5 (LL_ADC_SAMPLINGTIME_160CYCLES_5) /*!< Sampling time 160.5 ADC clock cycles */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_HAL_EC_CHANNEL ADC instance - Channel number
+ * @{
+ */
+#define ADC_CHANNEL_0 (LL_ADC_CHANNEL_0) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 */
+#define ADC_CHANNEL_1 (LL_ADC_CHANNEL_1) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 */
+#define ADC_CHANNEL_2 (LL_ADC_CHANNEL_2) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 */
+#define ADC_CHANNEL_3 (LL_ADC_CHANNEL_3) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3 */
+#define ADC_CHANNEL_4 (LL_ADC_CHANNEL_4) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4 */
+#define ADC_CHANNEL_5 (LL_ADC_CHANNEL_5) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5 */
+#define ADC_CHANNEL_6 (LL_ADC_CHANNEL_6) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6 */
+#define ADC_CHANNEL_7 (LL_ADC_CHANNEL_7) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7 */
+#define ADC_CHANNEL_8 (LL_ADC_CHANNEL_8) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8 */
+#define ADC_CHANNEL_9 (LL_ADC_CHANNEL_9) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9 */
+#define ADC_CHANNEL_10 (LL_ADC_CHANNEL_10) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */
+#define ADC_CHANNEL_11 (LL_ADC_CHANNEL_11) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */
+#define ADC_CHANNEL_12 (LL_ADC_CHANNEL_12) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */
+#define ADC_CHANNEL_13 (LL_ADC_CHANNEL_13) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */
+#define ADC_CHANNEL_14 (LL_ADC_CHANNEL_14) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */
+#define ADC_CHANNEL_15 (LL_ADC_CHANNEL_15) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */
+#define ADC_CHANNEL_16 (LL_ADC_CHANNEL_16) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */
+#define ADC_CHANNEL_17 (LL_ADC_CHANNEL_17) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */
+#define ADC_CHANNEL_18 (LL_ADC_CHANNEL_18) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */
+#define ADC_CHANNEL_19 (LL_ADC_CHANNEL_19) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN19 */
+#define ADC_CHANNEL_20 (LL_ADC_CHANNEL_20) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN20 */
+#define ADC_CHANNEL_21 (LL_ADC_CHANNEL_21) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN21 */
+#define ADC_CHANNEL_22 (LL_ADC_CHANNEL_22) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN22 */
+#define ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_VREFINT) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. */
+#define ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_TEMPSENSOR) /*!< ADC internal channel connected to Temperature sensor. */
+#define ADC_CHANNEL_VDDA (LL_ADC_CHANNEL_VDDA) /*!< ADC internal channel connected to VDDA */
+#define ADC_CHANNEL_VSSA (LL_ADC_CHANNEL_VSSA) /*!< ADC internal channel connected to VSSA */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_HAL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number
+ * @{
+ */
+#define ADC_ANALOGWATCHDOG_1 (LL_ADC_AWD1) /*!< ADC analog watchdog number 1 */
+#define ADC_ANALOGWATCHDOG_2 (LL_ADC_AWD2) /*!< ADC analog watchdog number 2 */
+#define ADC_ANALOGWATCHDOG_3 (LL_ADC_AWD3) /*!< ADC analog watchdog number 3 */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_analog_watchdog_mode ADC Analog Watchdog Mode
+ * @{
+ */
+#define ADC_ANALOGWATCHDOG_NONE (0x00000000UL) /*!< No analog watchdog selected */
+#define ADC_ANALOGWATCHDOG_SINGLE_REG (ADC_CFGR1_AWD1SGL | ADC_CFGR1_AWD1EN) /*!< Analog watchdog applied to a regular group single channel */
+#define ADC_ANALOGWATCHDOG_ALL_REG (ADC_CFGR1_AWD1EN) /*!< Analog watchdog applied to regular group all channels */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_HAL_EC_OVS_RATIO Oversampling - Ratio
+ * @{
+ */
+#define ADC_OVERSAMPLING_RATIO_2 (LL_ADC_OVS_RATIO_2) /*!< ADC oversampling ratio of 2 (2 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
+#define ADC_OVERSAMPLING_RATIO_4 (LL_ADC_OVS_RATIO_4) /*!< ADC oversampling ratio of 4 (4 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
+#define ADC_OVERSAMPLING_RATIO_8 (LL_ADC_OVS_RATIO_8) /*!< ADC oversampling ratio of 8 (8 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
+#define ADC_OVERSAMPLING_RATIO_16 (LL_ADC_OVS_RATIO_16) /*!< ADC oversampling ratio of 16 (16 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
+#define ADC_OVERSAMPLING_RATIO_32 (LL_ADC_OVS_RATIO_32) /*!< ADC oversampling ratio of 32 (32 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
+#define ADC_OVERSAMPLING_RATIO_64 (LL_ADC_OVS_RATIO_64) /*!< ADC oversampling ratio of 64 (64 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
+#define ADC_OVERSAMPLING_RATIO_128 (LL_ADC_OVS_RATIO_128) /*!< ADC oversampling ratio of 128 (128 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
+#define ADC_OVERSAMPLING_RATIO_256 (LL_ADC_OVS_RATIO_256) /*!< ADC oversampling ratio of 256 (256 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_HAL_EC_OVS_SHIFT Oversampling - Data shift
+ * @{
+ */
+#define ADC_RIGHTBITSHIFT_NONE (LL_ADC_OVS_SHIFT_NONE) /*!< ADC oversampling no shift (sum of the ADC conversions data is not divided to result as the ADC oversampling conversion data) */
+#define ADC_RIGHTBITSHIFT_1 (LL_ADC_OVS_SHIFT_RIGHT_1) /*!< ADC oversampling shift of 1 (sum of the ADC conversions data is divided by 2 to result as the ADC oversampling conversion data) */
+#define ADC_RIGHTBITSHIFT_2 (LL_ADC_OVS_SHIFT_RIGHT_2) /*!< ADC oversampling shift of 2 (sum of the ADC conversions data is divided by 4 to result as the ADC oversampling conversion data) */
+#define ADC_RIGHTBITSHIFT_3 (LL_ADC_OVS_SHIFT_RIGHT_3) /*!< ADC oversampling shift of 3 (sum of the ADC conversions data is divided by 8 to result as the ADC oversampling conversion data) */
+#define ADC_RIGHTBITSHIFT_4 (LL_ADC_OVS_SHIFT_RIGHT_4) /*!< ADC oversampling shift of 4 (sum of the ADC conversions data is divided by 16 to result as the ADC oversampling conversion data) */
+#define ADC_RIGHTBITSHIFT_5 (LL_ADC_OVS_SHIFT_RIGHT_5) /*!< ADC oversampling shift of 5 (sum of the ADC conversions data is divided by 32 to result as the ADC oversampling conversion data) */
+#define ADC_RIGHTBITSHIFT_6 (LL_ADC_OVS_SHIFT_RIGHT_6) /*!< ADC oversampling shift of 6 (sum of the ADC conversions data is divided by 64 to result as the ADC oversampling conversion data) */
+#define ADC_RIGHTBITSHIFT_7 (LL_ADC_OVS_SHIFT_RIGHT_7) /*!< ADC oversampling shift of 7 (sum of the ADC conversions data is divided by 128 to result as the ADC oversampling conversion data) */
+#define ADC_RIGHTBITSHIFT_8 (LL_ADC_OVS_SHIFT_RIGHT_8) /*!< ADC oversampling shift of 8 (sum of the ADC conversions data is divided by 256 to result as the ADC oversampling conversion data) */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_HAL_EC_OVS_DISCONT_MODE Oversampling - Discontinuous mode
+ * @{
+ */
+#define ADC_TRIGGEREDMODE_SINGLE_TRIGGER (LL_ADC_OVS_REG_CONT) /*!< ADC oversampling discontinuous mode: continuous mode (all conversions of oversampling ratio are done from 1 trigger) */
+#define ADC_TRIGGEREDMODE_MULTI_TRIGGER (LL_ADC_OVS_REG_DISCONT) /*!< ADC oversampling discontinuous mode: discontinuous mode (each conversion of oversampling ratio needs a trigger) */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_HAL_EC_REG_TRIGGER_FREQ ADC group regular - Trigger frequency mode
+ * @{
+ */
+#define ADC_TRIGGER_FREQ_HIGH (LL_ADC_TRIGGER_FREQ_HIGH) /*!< ADC trigger frequency mode set to high frequency. Note: ADC trigger frequency mode must be set to low frequency when a duration is exceeded before ADC conversion start trigger event (between ADC enable and ADC conversion start trigger event or between two ADC conversion start trigger event). Duration value: Refer to device datasheet, parameter "tIdle". */
+#define ADC_TRIGGER_FREQ_LOW (LL_ADC_TRIGGER_FREQ_LOW) /*!< ADC trigger frequency mode set to low frequency. Note: ADC trigger frequency mode must be set to low frequency when a duration is exceeded before ADC conversion start trigger event (between ADC enable and ADC conversion start trigger event or between two ADC conversion start trigger event). Duration value: Refer to device datasheet, parameter "tIdle". */
+/**
+ * @}
+ */
+
+
+/** @defgroup ADC_Event_type ADC Event type
+ * @{
+ */
+#define ADC_EOSMP_EVENT (ADC_FLAG_EOSMP) /*!< ADC End of Sampling event */
+#define ADC_AWD1_EVENT (ADC_FLAG_AWD1) /*!< ADC Analog watchdog 1 event (main analog watchdog, present on all STM32 series) */
+#define ADC_AWD2_EVENT (ADC_FLAG_AWD2) /*!< ADC Analog watchdog 2 event (additional analog watchdog, not present on all STM32 series) */
+#define ADC_AWD3_EVENT (ADC_FLAG_AWD3) /*!< ADC Analog watchdog 3 event (additional analog watchdog, not present on all STM32 series) */
+#define ADC_OVR_EVENT (ADC_FLAG_OVR) /*!< ADC overrun event */
+/**
+ * @}
+ */
+#define ADC_AWD_EVENT ADC_AWD1_EVENT /*!< ADC Analog watchdog 1 event: Naming for compatibility with other STM32 devices having only one analog watchdog */
+
+/** @defgroup ADC_interrupts_definition ADC interrupts definition
+ * @{
+ */
+#define ADC_IT_RDY ADC_IER_ADRDYIE /*!< ADC Ready interrupt source */
+#define ADC_IT_CCRDY ADC_IER_CCRDYIE /*!< ADC channel configuration ready interrupt source */
+#define ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC End of sampling interrupt source */
+#define ADC_IT_EOC ADC_IER_EOCIE /*!< ADC End of regular conversion interrupt source */
+#define ADC_IT_EOS ADC_IER_EOSIE /*!< ADC End of regular sequence of conversions interrupt source */
+#define ADC_IT_OVR ADC_IER_OVRIE /*!< ADC overrun interrupt source */
+#define ADC_IT_AWD1 ADC_IER_AWD1IE /*!< ADC Analog watchdog 1 interrupt source (main analog watchdog) */
+#define ADC_IT_AWD2 ADC_IER_AWD2IE /*!< ADC Analog watchdog 2 interrupt source (additional analog watchdog) */
+#define ADC_IT_AWD3 ADC_IER_AWD3IE /*!< ADC Analog watchdog 3 interrupt source (additional analog watchdog) */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_flags_definition ADC flags definition
+ * @{
+ */
+#define ADC_FLAG_RDY ADC_ISR_ADRDY /*!< ADC Ready flag */
+#define ADC_FLAG_CCRDY ADC_ISR_CCRDY /*!< ADC channel configuration ready flag */
+#define ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC End of Sampling flag */
+#define ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC End of Regular Conversion flag */
+#define ADC_FLAG_EOS ADC_ISR_EOS /*!< ADC End of Regular sequence of Conversions flag */
+#define ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC overrun flag */
+#define ADC_FLAG_AWD1 ADC_ISR_AWD1 /*!< ADC Analog watchdog 1 flag */
+#define ADC_FLAG_AWD2 ADC_ISR_AWD2 /*!< ADC Analog watchdog 2 flag */
+#define ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC Analog watchdog 3 flag */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+
+/** @defgroup ADC_Private_Macros ADC Private Macros
+ * @{
+ */
+/* Macro reserved for internal HAL driver usage, not intended to be used in */
+/* code of final user. */
+
+/**
+ * @brief Test if conversion trigger of regular group is software start
+ * or external trigger.
+ * @param __HANDLE__ ADC handle
+ * @retval SET (software start) or RESET (external trigger)
+ */
+#define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \
+ (((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_EXTEN) == 0UL)
+
+/**
+ * @brief Return resolution bits in CFGR1 register RES[1:0] field.
+ * @param __HANDLE__ ADC handle
+ * @retval Value of bitfield RES in CFGR1 register.
+ */
+#define ADC_GET_RESOLUTION(__HANDLE__) \
+ (LL_ADC_GetResolution((__HANDLE__)->Instance))
+
+/**
+ * @brief Clear ADC error code (set it to no error code "HAL_ADC_ERROR_NONE").
+ * @param __HANDLE__ ADC handle
+ * @retval None
+ */
+#define ADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
+
+/**
+ * @brief Simultaneously clear and set specific bits of the handle State.
+ * @note ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(),
+ * the first parameter is the ADC handle State, the second parameter is the
+ * bit field to clear, the third and last parameter is the bit field to set.
+ * @retval None
+ */
+#define ADC_STATE_CLR_SET MODIFY_REG
+
+/**
+ * @brief Enable ADC discontinuous conversion mode for regular group
+ * @param _REG_DISCONTINUOUS_MODE_: Regular discontinuous mode.
+ * @retval None
+ */
+#define ADC_CFGR1_REG_DISCCONTINUOUS(_REG_DISCONTINUOUS_MODE_) \
+ ((_REG_DISCONTINUOUS_MODE_) << 16U)
+
+/**
+ * @brief Enable the ADC auto off mode.
+ * @param _AUTOOFF_ Auto off bit enable or disable.
+ * @retval None
+ */
+#define ADC_CFGR1_AUTOOFF(_AUTOOFF_) \
+ ((_AUTOOFF_) << 15U)
+
+/**
+ * @brief Enable the ADC auto delay mode.
+ * @param _AUTOWAIT_ Auto delay bit enable or disable.
+ * @retval None
+ */
+#define ADC_CFGR1_AUTOWAIT(_AUTOWAIT_) \
+ ((_AUTOWAIT_) << 14U)
+
+/**
+ * @brief Enable ADC continuous conversion mode.
+ * @param _CONTINUOUS_MODE_ Continuous mode.
+ * @retval None
+ */
+#define ADC_CFGR1_CONTINUOUS(_CONTINUOUS_MODE_) \
+ ((_CONTINUOUS_MODE_) << 13U)
+
+/**
+ * @brief Enable ADC overrun mode.
+ * @param _OVERRUN_MODE_ Overrun mode.
+ * @retval Overrun bit setting to be programmed into CFGR register
+ */
+/* Note: Bit ADC_CFGR1_OVRMOD not used directly in constant */
+/* "ADC_OVR_DATA_OVERWRITTEN" to have this case defined to 0x00, to set it */
+/* as the default case to be compliant with other STM32 devices. */
+#define ADC_CFGR1_OVERRUN(_OVERRUN_MODE_) \
+ ( ( (_OVERRUN_MODE_) != (ADC_OVR_DATA_PRESERVED) \
+ )? (ADC_CFGR1_OVRMOD) : (0x00000000UL) \
+ )
+
+/**
+ * @brief Set ADC scan mode with differentiation of sequencer setting
+ * fixed or configurable
+ * @param _SCAN_MODE_ Scan conversion mode.
+ * @retval None
+ */
+/* Note: Scan mode set using this macro (instead of parameter direct set) */
+/* due to different modes on other STM32 devices: */
+/* if scan mode is disabled, sequencer is set to fully configurable */
+/* with setting of only rank 1 enabled afterwards. */
+#define ADC_SCAN_SEQ_MODE(_SCAN_MODE_) \
+ ( (((_SCAN_MODE_) & ADC_SCAN_SEQ_FIXED_INT) != 0UL \
+ )? \
+ ((_SCAN_MODE_) & (~ADC_SCAN_SEQ_FIXED_INT)) \
+ : \
+ (ADC_CFGR1_CHSELRMOD) \
+ )
+
+/**
+ * @brief Enable the ADC DMA continuous request.
+ * @param _DMACONTREQ_MODE_: DMA continuous request mode.
+ * @retval None
+ */
+#define ADC_CFGR1_DMACONTREQ(_DMACONTREQ_MODE_) \
+ ((_DMACONTREQ_MODE_) << 1U)
+
+/**
+ * @brief Shift the AWD threshold in function of the selected ADC resolution.
+ * Thresholds have to be left-aligned on bit 11, the LSB (right bits) are set to 0.
+ * If resolution 12 bits, no shift.
+ * If resolution 10 bits, shift of 2 ranks on the left.
+ * If resolution 8 bits, shift of 4 ranks on the left.
+ * If resolution 6 bits, shift of 6 ranks on the left.
+ * therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2))
+ * @param __HANDLE__ ADC handle
+ * @param _Threshold_ Value to be shifted
+ * @retval None
+ */
+#define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, _Threshold_) \
+ ((_Threshold_) << ((((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_RES) >> 3U)*2U))
+
+#define IS_ADC_CLOCKPRESCALER(ADC_CLOCK) (((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV1) ||\
+ ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV2) ||\
+ ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV4) ||\
+ ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV1 ) ||\
+ ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV2 ) ||\
+ ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV4 ) ||\
+ ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV6 ) ||\
+ ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV8 ) ||\
+ ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV10 ) ||\
+ ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV12 ) ||\
+ ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV16 ) ||\
+ ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV32 ) ||\
+ ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV64 ) ||\
+ ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV128 ) ||\
+ ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV256))
+
+#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_12B) || \
+ ((RESOLUTION) == ADC_RESOLUTION_10B) || \
+ ((RESOLUTION) == ADC_RESOLUTION_8B) || \
+ ((RESOLUTION) == ADC_RESOLUTION_6B) )
+
+#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \
+ ((ALIGN) == ADC_DATAALIGN_LEFT) )
+
+#define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DISABLE) || \
+ ((SCAN_MODE) == ADC_SCAN_ENABLE) || \
+ ((SCAN_MODE) == ADC_SCAN_SEQ_FIXED) || \
+ ((SCAN_MODE) == ADC_SCAN_SEQ_FIXED_BACKWARD) )
+
+#define IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \
+ ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \
+ ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \
+ ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING) )
+
+#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIG_T1_TRGO2) || \
+ ((REGTRIG) == ADC_EXTERNALTRIG_T1_CC4) || \
+ ((REGTRIG) == ADC_EXTERNALTRIG_T3_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIG_EXT_IT11) || \
+ ((REGTRIG) == ADC_SOFTWARE_START))
+
+#define IS_ADC_EOC_SELECTION(EOC_SELECTION) (((EOC_SELECTION) == ADC_EOC_SINGLE_CONV) || \
+ ((EOC_SELECTION) == ADC_EOC_SEQ_CONV))
+
+#define IS_ADC_OVERRUN(OVR) (((OVR) == ADC_OVR_DATA_PRESERVED) || \
+ ((OVR) == ADC_OVR_DATA_OVERWRITTEN) )
+
+#define IS_ADC_REGULAR_RANK_SEQ_FIXED(RANK) (((RANK) == ADC_RANK_CHANNEL_NUMBER) || \
+ ((RANK) == ADC_RANK_NONE) )
+
+#define IS_ADC_REGULAR_RANK(RANK) (((RANK) == ADC_REGULAR_RANK_1 ) || \
+ ((RANK) == ADC_REGULAR_RANK_2 ) || \
+ ((RANK) == ADC_REGULAR_RANK_3 ) || \
+ ((RANK) == ADC_REGULAR_RANK_4 ) || \
+ ((RANK) == ADC_REGULAR_RANK_5 ) || \
+ ((RANK) == ADC_REGULAR_RANK_6 ) || \
+ ((RANK) == ADC_REGULAR_RANK_7 ) || \
+ ((RANK) == ADC_REGULAR_RANK_8 ) )
+
+#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) || \
+ ((CHANNEL) == ADC_CHANNEL_1) || \
+ ((CHANNEL) == ADC_CHANNEL_2) || \
+ ((CHANNEL) == ADC_CHANNEL_3) || \
+ ((CHANNEL) == ADC_CHANNEL_4) || \
+ ((CHANNEL) == ADC_CHANNEL_5) || \
+ ((CHANNEL) == ADC_CHANNEL_6) || \
+ ((CHANNEL) == ADC_CHANNEL_7) || \
+ ((CHANNEL) == ADC_CHANNEL_8) || \
+ ((CHANNEL) == ADC_CHANNEL_9) || \
+ ((CHANNEL) == ADC_CHANNEL_10) || \
+ ((CHANNEL) == ADC_CHANNEL_11) || \
+ ((CHANNEL) == ADC_CHANNEL_12) || \
+ ((CHANNEL) == ADC_CHANNEL_13) || \
+ ((CHANNEL) == ADC_CHANNEL_14) || \
+ ((CHANNEL) == ADC_CHANNEL_15) || \
+ ((CHANNEL) == ADC_CHANNEL_16) || \
+ ((CHANNEL) == ADC_CHANNEL_17) || \
+ ((CHANNEL) == ADC_CHANNEL_18) || \
+ ((CHANNEL) == ADC_CHANNEL_19) || \
+ ((CHANNEL) == ADC_CHANNEL_20) || \
+ ((CHANNEL) == ADC_CHANNEL_21) || \
+ ((CHANNEL) == ADC_CHANNEL_22) || \
+ ((CHANNEL) == ADC_CHANNEL_TEMPSENSOR) || \
+ ((CHANNEL) == ADC_CHANNEL_VREFINT) || \
+ ((CHANNEL) == ADC_CHANNEL_VDDA) || \
+ ((CHANNEL) == ADC_CHANNEL_VSSA) )
+
+#define IS_ADC_SAMPLING_TIME_COMMON(SAMPLING_TIME_COMMON) (((SAMPLING_TIME_COMMON) == ADC_SAMPLINGTIME_COMMON_1) || \
+ ((SAMPLING_TIME_COMMON) == ADC_SAMPLINGTIME_COMMON_2) )
+
+#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_1CYCLE_5) || \
+ ((TIME) == ADC_SAMPLETIME_3CYCLES_5) || \
+ ((TIME) == ADC_SAMPLETIME_7CYCLES_5) || \
+ ((TIME) == ADC_SAMPLETIME_12CYCLES_5) || \
+ ((TIME) == ADC_SAMPLETIME_19CYCLES_5) || \
+ ((TIME) == ADC_SAMPLETIME_39CYCLES_5) || \
+ ((TIME) == ADC_SAMPLETIME_79CYCLES_5) || \
+ ((TIME) == ADC_SAMPLETIME_160CYCLES_5) )
+
+#define IS_ADC_ANALOG_WATCHDOG_NUMBER(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_1) || \
+ ((WATCHDOG) == ADC_ANALOGWATCHDOG_2) || \
+ ((WATCHDOG) == ADC_ANALOGWATCHDOG_3) )
+
+#define IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE) || \
+ ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \
+ ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG) )
+
+#define IS_ADC_TRIGGER_FREQ(TRIGGER_FREQ) (((TRIGGER_FREQ) == LL_ADC_TRIGGER_FREQ_HIGH) || \
+ ((TRIGGER_FREQ) == LL_ADC_TRIGGER_FREQ_LOW) )
+
+#define IS_ADC_EVENT_TYPE(EVENT) (((EVENT) == ADC_EOSMP_EVENT) || \
+ ((EVENT) == ADC_AWD1_EVENT) || \
+ ((EVENT) == ADC_AWD2_EVENT) || \
+ ((EVENT) == ADC_AWD3_EVENT) || \
+ ((EVENT) == ADC_OVR_EVENT) )
+
+/**
+ * @brief Verify that a given value is aligned with the ADC resolution range.
+ * @param __RESOLUTION__ ADC resolution (12, 10, 8 or 6 bits).
+ * @param __ADC_VALUE__ value checked against the resolution.
+ * @retval SET (__ADC_VALUE__ in line with __RESOLUTION__) or RESET (__ADC_VALUE__ not in line with __RESOLUTION__)
+ */
+#define IS_ADC_RANGE(__RESOLUTION__, __ADC_VALUE__) \
+ ((__ADC_VALUE__) <= __LL_ADC_DIGITAL_SCALE(__RESOLUTION__))
+
+/** @defgroup ADC_regular_nb_conv_verification ADC Regular Conversion Number Verification
+ * @{
+ */
+#define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= 1UL) && ((LENGTH) <= 8UL))
+/**
+ * @}
+ */
+
+
+/* Private constants ---------------------------------------------------------*/
+
+/** @defgroup ADC_Private_Constants ADC Private Constants
+ * @{
+ */
+
+/* Combination of all post-conversion flags bits: EOC/EOS, OVR, AWD */
+#define ADC_FLAG_POSTCONV_ALL (ADC_FLAG_AWD | ADC_FLAG_OVR | ADC_FLAG_EOS | ADC_FLAG_EOC)
+
+#define ADC_SCAN_SEQ_FIXED_INT 0x80000000U /* Internal definition to differentiate sequencer setting fixed or configurable */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @defgroup ADC_Exported_Macros ADC Exported Macros
+ * @{
+ */
+/* Macro for internal HAL driver usage, and possibly can be used into code of */
+/* final user. */
+
+/** @defgroup ADC_HAL_EM_HANDLE_IT_FLAG HAL ADC macro to manage HAL ADC handle, IT and flags.
+ * @{
+ */
+
+/** @brief Reset ADC handle state.
+ * @param __HANDLE__ ADC handle
+ * @retval None
+ */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \
+ do{ \
+ (__HANDLE__)->State = HAL_ADC_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0)
+#else
+#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \
+ ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
+/**
+ * @brief Enable ADC interrupt.
+ * @param __HANDLE__ ADC handle
+ * @param __INTERRUPT__ ADC Interrupt
+ * This parameter can be one of the following values:
+ * @arg @ref ADC_IT_RDY ADC Ready interrupt source
+ * @arg @ref ADC_IT_CCRDY ADC channel configuration ready interrupt source
+ * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source
+ * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source
+ * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source
+ * @arg @ref ADC_IT_OVR ADC overrun interrupt source
+ * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog)
+ * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog)
+ * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog)
+ * @retval None
+ */
+#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
+ (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
+
+/**
+ * @brief Disable ADC interrupt.
+ * @param __HANDLE__ ADC handle
+ * @param __INTERRUPT__ ADC Interrupt
+ * This parameter can be one of the following values:
+ * @arg @ref ADC_IT_RDY ADC Ready interrupt source
+ * @arg @ref ADC_IT_CCRDY ADC channel configuration ready interrupt source
+ * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source
+ * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source
+ * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source
+ * @arg @ref ADC_IT_OVR ADC overrun interrupt source
+ * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog)
+ * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog)
+ * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog)
+ * @retval None
+ */
+#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \
+ (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
+
+/** @brief Checks if the specified ADC interrupt source is enabled or disabled.
+ * @param __HANDLE__ ADC handle
+ * @param __INTERRUPT__ ADC interrupt source to check
+ * This parameter can be one of the following values:
+ * @arg @ref ADC_IT_RDY ADC Ready interrupt source
+ * @arg @ref ADC_IT_CCRDY ADC channel configuration ready interrupt source
+ * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source
+ * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source
+ * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source
+ * @arg @ref ADC_IT_OVR ADC overrun interrupt source
+ * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog)
+ * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog)
+ * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog)
+ * @retval State of interruption (SET or RESET)
+ */
+#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
+ (((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__))
+
+/**
+ * @brief Check whether the specified ADC flag is set or not.
+ * @param __HANDLE__ ADC handle
+ * @param __FLAG__ ADC flag
+ * This parameter can be one of the following values:
+ * @arg @ref ADC_FLAG_RDY ADC Ready flag
+ * @arg @ref ADC_FLAG_CCRDY ADC channel configuration ready flag
+ * @arg @ref ADC_FLAG_EOSMP ADC End of Sampling flag
+ * @arg @ref ADC_FLAG_EOC ADC End of Regular Conversion flag
+ * @arg @ref ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag
+ * @arg @ref ADC_FLAG_OVR ADC overrun flag
+ * @arg @ref ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog)
+ * @arg @ref ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog)
+ * @arg @ref ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog)
+ * @retval State of flag (TRUE or FALSE).
+ */
+#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \
+ ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__))
+
+/**
+ * @brief Clear the specified ADC flag.
+ * @param __HANDLE__ ADC handle
+ * @param __FLAG__ ADC flag
+ * This parameter can be one of the following values:
+ * @arg @ref ADC_FLAG_RDY ADC Ready flag
+ * @arg @ref ADC_FLAG_CCRDY ADC channel configuration ready flag
+ * @arg @ref ADC_FLAG_EOSMP ADC End of Sampling flag
+ * @arg @ref ADC_FLAG_EOC ADC End of Regular Conversion flag
+ * @arg @ref ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag
+ * @arg @ref ADC_FLAG_OVR ADC overrun flag
+ * @arg @ref ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog)
+ * @arg @ref ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog)
+ * @arg @ref ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog)
+ * @retval None
+ */
+/* Note: bit cleared bit by writing 1 (writing 0 has no effect on any bit of register ISR) */
+#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) \
+ (((__HANDLE__)->Instance->ISR) = (__FLAG__))
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_HAL_EM_HELPER_MACRO HAL ADC helper macro
+ * @{
+ */
+
+/**
+ * @brief Helper macro to get ADC channel number in decimal format
+ * from literals ADC_CHANNEL_x.
+ * @note Example:
+ * __HAL_ADC_CHANNEL_TO_DECIMAL_NB(ADC_CHANNEL_4)
+ * will return decimal number "4".
+ * @note The input can be a value from functions where a channel
+ * number is returned, either defined with number
+ * or with bitfield (only one bit must be set).
+ * @param __CHANNEL__ This parameter can be one of the following values:
+ * @arg @ref ADC_CHANNEL_0
+ * @arg @ref ADC_CHANNEL_1
+ * @arg @ref ADC_CHANNEL_2
+ * @arg @ref ADC_CHANNEL_3
+ * @arg @ref ADC_CHANNEL_4
+ * @arg @ref ADC_CHANNEL_5
+ * @arg @ref ADC_CHANNEL_6
+ * @arg @ref ADC_CHANNEL_7
+ * @arg @ref ADC_CHANNEL_8 (1)
+ * @arg @ref ADC_CHANNEL_9 (1)
+ * @arg @ref ADC_CHANNEL_10
+ * @arg @ref ADC_CHANNEL_11
+ * @arg @ref ADC_CHANNEL_12
+ * @arg @ref ADC_CHANNEL_13
+ * @arg @ref ADC_CHANNEL_14
+ * @arg @ref ADC_CHANNEL_15 (1)
+ * @arg @ref ADC_CHANNEL_16 (1)
+ * @arg @ref ADC_CHANNEL_17 (3)
+ * @arg @ref ADC_CHANNEL_18 (3)
+ * @arg @ref ADC_CHANNEL_19 (3)
+ * @arg @ref ADC_CHANNEL_20 (3)
+ * @arg @ref ADC_CHANNEL_21 (3)
+ * @arg @ref ADC_CHANNEL_22 (3)
+ * @arg @ref ADC_CHANNEL_VREFINT (2)
+ * @arg @ref ADC_CHANNEL_TEMPSENSOR (2)
+ * @arg @ref ADC_CHANNEL_VDDA (2)
+ * @arg @ref ADC_CHANNEL_VSSA (2)
+ *
+ * (1) On STM32C0, parameter can be set in ADC group sequencer
+ * only if sequencer is set in mode "not fully configurable",
+ * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().\n
+ * (2) For ADC channel read back from ADC register,
+ * comparison with internal channel parameter to be done
+ * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
+ * (3) ADC channels available on STM32C031xx device only.
+ * @retval Value between Min_Data=0 and Max_Data=18
+ */
+#define __HAL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
+ __LL_ADC_CHANNEL_TO_DECIMAL_NB((__CHANNEL__))
+
+/**
+ * @brief Helper macro to get ADC channel in literal format ADC_CHANNEL_x
+ * from number in decimal format.
+ * @note Example:
+ * __HAL_ADC_DECIMAL_NB_TO_CHANNEL(4)
+ * will return a data equivalent to "ADC_CHANNEL_4".
+ * @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18
+ * @retval Returned value can be one of the following values:
+ * @arg @ref ADC_CHANNEL_0
+ * @arg @ref ADC_CHANNEL_1
+ * @arg @ref ADC_CHANNEL_2
+ * @arg @ref ADC_CHANNEL_3
+ * @arg @ref ADC_CHANNEL_4
+ * @arg @ref ADC_CHANNEL_5
+ * @arg @ref ADC_CHANNEL_6
+ * @arg @ref ADC_CHANNEL_7
+ * @arg @ref ADC_CHANNEL_8 (1)
+ * @arg @ref ADC_CHANNEL_9 (1)
+ * @arg @ref ADC_CHANNEL_10
+ * @arg @ref ADC_CHANNEL_11
+ * @arg @ref ADC_CHANNEL_12
+ * @arg @ref ADC_CHANNEL_13
+ * @arg @ref ADC_CHANNEL_14
+ * @arg @ref ADC_CHANNEL_15 (1)
+ * @arg @ref ADC_CHANNEL_16 (1)
+ * @arg @ref ADC_CHANNEL_17 (3)
+ * @arg @ref ADC_CHANNEL_18 (3)
+ * @arg @ref ADC_CHANNEL_19 (3)
+ * @arg @ref ADC_CHANNEL_20 (3)
+ * @arg @ref ADC_CHANNEL_21 (3)
+ * @arg @ref ADC_CHANNEL_22 (3)
+ * @arg @ref ADC_CHANNEL_VREFINT (2)
+ * @arg @ref ADC_CHANNEL_TEMPSENSOR (2)
+ * @arg @ref ADC_CHANNEL_VDDA (2)
+ * @arg @ref ADC_CHANNEL_VSSA (2)
+ *
+ * (1) On STM32C0, parameter can be set in ADC group sequencer
+ * only if sequencer is set in mode "not fully configurable",
+ * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().\n
+ * (2) For ADC channel read back from ADC register,
+ * comparison with internal channel parameter to be done
+ * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
+ * (3) ADC channels available on STM32C031xx device only.
+ */
+#define __HAL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
+ __LL_ADC_DECIMAL_NB_TO_CHANNEL((__DECIMAL_NB__))
+
+/**
+ * @brief Helper macro to determine whether the selected channel
+ * corresponds to literal definitions of driver.
+ * @note The different literal definitions of ADC channels are:
+ * - ADC internal channel:
+ * ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ...
+ * - ADC external channel (channel connected to a GPIO pin):
+ * ADC_CHANNEL_1, ADC_CHANNEL_2, ...
+ * @note The channel parameter must be a value defined from literal
+ * definition of a ADC internal channel (ADC_CHANNEL_VREFINT,
+ * ADC_CHANNEL_TEMPSENSOR, ...),
+ * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...),
+ * must not be a value from functions where a channel number is
+ * returned from ADC registers,
+ * because internal and external channels share the same channel
+ * number in ADC registers. The differentiation is made only with
+ * parameters definitions of driver.
+ * @param __CHANNEL__ This parameter can be one of the following values:
+ * @arg @ref ADC_CHANNEL_0
+ * @arg @ref ADC_CHANNEL_1
+ * @arg @ref ADC_CHANNEL_2
+ * @arg @ref ADC_CHANNEL_3
+ * @arg @ref ADC_CHANNEL_4
+ * @arg @ref ADC_CHANNEL_5
+ * @arg @ref ADC_CHANNEL_6
+ * @arg @ref ADC_CHANNEL_7
+ * @arg @ref ADC_CHANNEL_8 (1)
+ * @arg @ref ADC_CHANNEL_9 (1)
+ * @arg @ref ADC_CHANNEL_10
+ * @arg @ref ADC_CHANNEL_11
+ * @arg @ref ADC_CHANNEL_12
+ * @arg @ref ADC_CHANNEL_13
+ * @arg @ref ADC_CHANNEL_14
+ * @arg @ref ADC_CHANNEL_15 (1)
+ * @arg @ref ADC_CHANNEL_16 (1)
+ * @arg @ref ADC_CHANNEL_17 (3)
+ * @arg @ref ADC_CHANNEL_18 (3)
+ * @arg @ref ADC_CHANNEL_19 (3)
+ * @arg @ref ADC_CHANNEL_20 (3)
+ * @arg @ref ADC_CHANNEL_21 (3)
+ * @arg @ref ADC_CHANNEL_22 (3)
+ * @arg @ref ADC_CHANNEL_VREFINT (2)
+ * @arg @ref ADC_CHANNEL_TEMPSENSOR (2)
+ * @arg @ref ADC_CHANNEL_VDDA (2)
+ * @arg @ref ADC_CHANNEL_VSSA (2)
+ *
+ * (1) On STM32C0, parameter can be set in ADC group sequencer
+ * only if sequencer is set in mode "not fully configurable",
+ * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().\n
+ * (2) For ADC channel read back from ADC register,
+ * comparison with internal channel parameter to be done
+ * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
+ * (3) ADC channels available on STM32C031xx device only.
+ * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin).
+ * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.
+ */
+#define __HAL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \
+ __LL_ADC_IS_CHANNEL_INTERNAL((__CHANNEL__))
+
+/**
+ * @brief Helper macro to convert a channel defined from parameter
+ * definition of a ADC internal channel (ADC_CHANNEL_VREFINT,
+ * ADC_CHANNEL_TEMPSENSOR, ...),
+ * to its equivalent parameter definition of a ADC external channel
+ * (ADC_CHANNEL_1, ADC_CHANNEL_2, ...).
+ * @note The channel parameter can be, additionally to a value
+ * defined from parameter definition of a ADC internal channel
+ * (ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ...),
+ * a value defined from parameter definition of
+ * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...)
+ * or a value from functions where a channel number is returned
+ * from ADC registers.
+ * @param __CHANNEL__ This parameter can be one of the following values:
+ * @arg @ref ADC_CHANNEL_0
+ * @arg @ref ADC_CHANNEL_1
+ * @arg @ref ADC_CHANNEL_2
+ * @arg @ref ADC_CHANNEL_3
+ * @arg @ref ADC_CHANNEL_4
+ * @arg @ref ADC_CHANNEL_5
+ * @arg @ref ADC_CHANNEL_6
+ * @arg @ref ADC_CHANNEL_7
+ * @arg @ref ADC_CHANNEL_8 (1)
+ * @arg @ref ADC_CHANNEL_9 (1)
+ * @arg @ref ADC_CHANNEL_10
+ * @arg @ref ADC_CHANNEL_11
+ * @arg @ref ADC_CHANNEL_12
+ * @arg @ref ADC_CHANNEL_13
+ * @arg @ref ADC_CHANNEL_14
+ * @arg @ref ADC_CHANNEL_15 (1)
+ * @arg @ref ADC_CHANNEL_16 (1)
+ * @arg @ref ADC_CHANNEL_17 (3)
+ * @arg @ref ADC_CHANNEL_18 (3)
+ * @arg @ref ADC_CHANNEL_19 (3)
+ * @arg @ref ADC_CHANNEL_20 (3)
+ * @arg @ref ADC_CHANNEL_21 (3)
+ * @arg @ref ADC_CHANNEL_22 (3)
+ * @arg @ref ADC_CHANNEL_VREFINT (2)
+ * @arg @ref ADC_CHANNEL_TEMPSENSOR (2)
+ * @arg @ref ADC_CHANNEL_VDDA (2)
+ * @arg @ref ADC_CHANNEL_VSSA (2)
+ *
+ * (1) On STM32C0, parameter can be set in ADC group sequencer
+ * only if sequencer is set in mode "not fully configurable",
+ * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().\n
+ * (2) For ADC channel read back from ADC register,
+ * comparison with internal channel parameter to be done
+ * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
+ * (3) ADC channels available on STM32C031xx device only.
+ * @retval Returned value can be one of the following values:
+ * @arg @ref ADC_CHANNEL_0
+ * @arg @ref ADC_CHANNEL_1
+ * @arg @ref ADC_CHANNEL_2
+ * @arg @ref ADC_CHANNEL_3
+ * @arg @ref ADC_CHANNEL_4
+ * @arg @ref ADC_CHANNEL_5
+ * @arg @ref ADC_CHANNEL_6
+ * @arg @ref ADC_CHANNEL_7
+ * @arg @ref ADC_CHANNEL_8
+ * @arg @ref ADC_CHANNEL_9
+ * @arg @ref ADC_CHANNEL_10
+ * @arg @ref ADC_CHANNEL_11
+ * @arg @ref ADC_CHANNEL_12
+ * @arg @ref ADC_CHANNEL_13
+ * @arg @ref ADC_CHANNEL_14
+ * @arg @ref ADC_CHANNEL_15
+ * @arg @ref ADC_CHANNEL_16
+ * @arg @ref ADC_CHANNEL_17
+ * @arg @ref ADC_CHANNEL_18
+ * @arg @ref ADC_CHANNEL_19
+ * @arg @ref ADC_CHANNEL_20
+ * @arg @ref ADC_CHANNEL_21
+ * @arg @ref ADC_CHANNEL_22
+ */
+#define __HAL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \
+ __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL((__CHANNEL__))
+
+/**
+ * @brief Helper macro to determine whether the internal channel
+ * selected is available on the ADC instance selected.
+ * @note The channel parameter must be a value defined from parameter
+ * definition of a ADC internal channel (ADC_CHANNEL_VREFINT,
+ * ADC_CHANNEL_TEMPSENSOR, ...),
+ * must not be a value defined from parameter definition of
+ * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...)
+ * or a value from functions where a channel number is
+ * returned from ADC registers,
+ * because internal and external channels share the same channel
+ * number in ADC registers. The differentiation is made only with
+ * parameters definitions of driver.
+ * @param __ADC_INSTANCE__ ADC instance
+ * @param __CHANNEL__ This parameter can be one of the following values:
+ * @arg @ref ADC_CHANNEL_VREFINT
+ * @arg @ref ADC_CHANNEL_TEMPSENSOR
+ * @arg @ref ADC_CHANNEL_VDDA
+ * @arg @ref ADC_CHANNEL_VSSA
+ * @retval Value "0" if the internal channel selected is not available on the ADC instance selected.
+ * Value "1" if the internal channel selected is available on the ADC instance selected.
+ */
+#define __HAL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
+ __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE((__ADC_INSTANCE__), (__CHANNEL__))
+
+/**
+ * @brief Helper macro to select the ADC common instance
+ * to which is belonging the selected ADC instance.
+ * @note ADC common register instance can be used for:
+ * - Set parameters common to several ADC instances
+ * - Multimode (for devices with several ADC instances)
+ * Refer to functions having argument "ADCxy_COMMON" as parameter.
+ * @param __ADCx__ ADC instance
+ * @retval ADC common register instance
+ */
+#define __HAL_ADC_COMMON_INSTANCE(__ADCx__) \
+ __LL_ADC_COMMON_INSTANCE((__ADCx__))
+
+/**
+ * @brief Helper macro to check if all ADC instances sharing the same
+ * ADC common instance are disabled.
+ * @note This check is required by functions with setting conditioned to
+ * ADC state:
+ * All ADC instances of the ADC common group must be disabled.
+ * Refer to functions having argument "ADCxy_COMMON" as parameter.
+ * @note On devices with only 1 ADC common instance, parameter of this macro
+ * is useless and can be ignored (parameter kept for compatibility
+ * with devices featuring several ADC common instances).
+ * @param __ADCXY_COMMON__ ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval Value "0" if all ADC instances sharing the same ADC common instance
+ * are disabled.
+ * Value "1" if at least one ADC instance sharing the same ADC common instance
+ * is enabled.
+ */
+#define __HAL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
+ __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE((__ADCXY_COMMON__))
+
+/**
+ * @brief Helper macro to define the ADC conversion data full-scale digital
+ * value corresponding to the selected ADC resolution.
+ * @note ADC conversion data full-scale corresponds to voltage range
+ * determined by analog voltage references Vref+ and Vref-
+ * (refer to reference manual).
+ * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
+ * @arg @ref ADC_RESOLUTION_12B
+ * @arg @ref ADC_RESOLUTION_10B
+ * @arg @ref ADC_RESOLUTION_8B
+ * @arg @ref ADC_RESOLUTION_6B
+ * @retval ADC conversion data full-scale digital value
+ */
+#define __HAL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
+ __LL_ADC_DIGITAL_SCALE((__ADC_RESOLUTION__))
+
+/**
+ * @brief Helper macro to convert the ADC conversion data from
+ * a resolution to another resolution.
+ * @param __DATA__ ADC conversion data to be converted
+ * @param __ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted
+ * This parameter can be one of the following values:
+ * @arg @ref ADC_RESOLUTION_12B
+ * @arg @ref ADC_RESOLUTION_10B
+ * @arg @ref ADC_RESOLUTION_8B
+ * @arg @ref ADC_RESOLUTION_6B
+ * @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion
+ * This parameter can be one of the following values:
+ * @arg @ref ADC_RESOLUTION_12B
+ * @arg @ref ADC_RESOLUTION_10B
+ * @arg @ref ADC_RESOLUTION_8B
+ * @arg @ref ADC_RESOLUTION_6B
+ * @retval ADC conversion data to the requested resolution
+ */
+#define __HAL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\
+ __ADC_RESOLUTION_CURRENT__,\
+ __ADC_RESOLUTION_TARGET__) \
+__LL_ADC_CONVERT_DATA_RESOLUTION((__DATA__),\
+ (__ADC_RESOLUTION_CURRENT__),\
+ (__ADC_RESOLUTION_TARGET__))
+
+/**
+ * @brief Helper macro to calculate the voltage (unit: mVolt)
+ * corresponding to a ADC conversion data (unit: digital value).
+ * @note Analog reference voltage (Vref+) must be either known from
+ * user board environment or can be calculated using ADC measurement
+ * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
+ * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
+ * @param __ADC_DATA__ ADC conversion data (resolution 12 bits)
+ * (unit: digital value).
+ * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
+ * @arg @ref ADC_RESOLUTION_12B
+ * @arg @ref ADC_RESOLUTION_10B
+ * @arg @ref ADC_RESOLUTION_8B
+ * @arg @ref ADC_RESOLUTION_6B
+ * @retval ADC conversion data equivalent voltage value (unit: mVolt)
+ */
+#define __HAL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
+ __ADC_DATA__,\
+ __ADC_RESOLUTION__) \
+__LL_ADC_CALC_DATA_TO_VOLTAGE((__VREFANALOG_VOLTAGE__),\
+ (__ADC_DATA__),\
+ (__ADC_RESOLUTION__))
+
+/**
+ * @brief Helper macro to calculate analog reference voltage (Vref+)
+ * (unit: mVolt) from ADC conversion data of internal voltage
+ * reference VrefInt.
+ * @note Computation is using VrefInt calibration value
+ * stored in system memory for each device during production.
+ * @note This voltage depends on user board environment: voltage level
+ * connected to pin Vref+.
+ * On devices with small package, the pin Vref+ is not present
+ * and internally bonded to pin Vdda.
+ * @note On this STM32 series, calibration data of internal voltage reference
+ * VrefInt corresponds to a resolution of 12 bits,
+ * this is the recommended ADC resolution to convert voltage of
+ * internal voltage reference VrefInt.
+ * Otherwise, this macro performs the processing to scale
+ * ADC conversion data to 12 bits.
+ * @param __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits)
+ * of internal voltage reference VrefInt (unit: digital value).
+ * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
+ * @arg @ref ADC_RESOLUTION_12B
+ * @arg @ref ADC_RESOLUTION_10B
+ * @arg @ref ADC_RESOLUTION_8B
+ * @arg @ref ADC_RESOLUTION_6B
+ * @retval Analog reference voltage (unit: mV)
+ */
+#define __HAL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\
+ __ADC_RESOLUTION__) \
+__LL_ADC_CALC_VREFANALOG_VOLTAGE((__VREFINT_ADC_DATA__),\
+ (__ADC_RESOLUTION__))
+
+/**
+ * @brief Helper macro to calculate the temperature (unit: degree Celsius)
+ * from ADC conversion data of internal temperature sensor.
+ * @note Computation is using temperature sensor typical values
+ * (refer to device datasheet).
+ * @note Calculation formula:
+ * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV)
+ * / Avg_Slope + CALx_TEMP
+ * with TS_ADC_DATA = temperature sensor raw data measured by ADC
+ * (unit: digital value)
+ * Avg_Slope = temperature sensor slope
+ * (unit: uV/Degree Celsius)
+ * TS_TYP_CALx_VOLT = temperature sensor digital value at
+ * temperature CALx_TEMP (unit: mV)
+ * Caution: Calculation relevancy under reserve the temperature sensor
+ * of the current device has characteristics in line with
+ * datasheet typical values.
+ * @note: On this STM32 series, calibtation parameter TS_CAL1 can be used
+ * to improve calculation accuracy.
+ * Refer to @ref TEMPSENSOR_CAL1_ADDR.
+ * @note As calculation input, the analog reference voltage (Vref+) must be
+ * defined as it impacts the ADC LSB equivalent voltage.
+ * @note Analog reference voltage (Vref+) must be either known from
+ * user board environment or can be calculated using ADC measurement
+ * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
+ * @note ADC measurement data must correspond to a resolution of 12bits
+ * (full scale digital value 4095). If not the case, the data must be
+ * preliminarily rescaled to an equivalent resolution of 12 bits.
+ * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius).
+ * On STM32C0, refer to device datasheet parameter "Avg_Slope".
+ * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV).
+ * On STM32C0, refer to device datasheet parameter "V30" (corresponding to TS_CAL1).
+ * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV)
+ * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit: mV)
+ * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value).
+ * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured.
+ * This parameter can be one of the following values:
+ * @arg @ref ADC_RESOLUTION_12B
+ * @arg @ref ADC_RESOLUTION_10B
+ * @arg @ref ADC_RESOLUTION_8B
+ * @arg @ref ADC_RESOLUTION_6B
+ * @retval Temperature (unit: degree Celsius)
+ */
+#define __HAL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\
+ __TEMPSENSOR_TYP_CALX_V__,\
+ __TEMPSENSOR_CALX_TEMP__,\
+ __VREFANALOG_VOLTAGE__,\
+ __TEMPSENSOR_ADC_DATA__,\
+ __ADC_RESOLUTION__) \
+__LL_ADC_CALC_TEMPERATURE_TYP_PARAMS((__TEMPSENSOR_TYP_AVGSLOPE__),\
+ (__TEMPSENSOR_TYP_CALX_V__),\
+ (__TEMPSENSOR_CALX_TEMP__),\
+ (__VREFANALOG_VOLTAGE__),\
+ (__TEMPSENSOR_ADC_DATA__),\
+ (__ADC_RESOLUTION__))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Include ADC HAL Extended module */
+#include "stm32c0xx_hal_adc_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup ADC_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup ADC_Exported_Functions_Group1
+ * @brief Initialization and Configuration functions
+ * @{
+ */
+/* Initialization and de-initialization functions ****************************/
+HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
+void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc);
+void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc);
+
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+/* Callbacks Register/UnRegister functions ***********************************/
+HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID,
+ pADC_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_Exported_Functions_Group2
+ * @brief IO operation functions
+ * @{
+ */
+/* IO operation functions *****************************************************/
+
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout);
+HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout);
+
+/* Non-blocking mode: Interruption */
+HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc);
+
+/* Non-blocking mode: DMA */
+HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length);
+HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc);
+
+/* ADC retrieve conversion value intended to be used with polling or interruption */
+uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef *hadc);
+
+/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */
+void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc);
+void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc);
+void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc);
+void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef *hadc);
+void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_Exported_Functions_Group3 Peripheral Control functions
+ * @brief Peripheral Control functions
+ * @{
+ */
+/* Peripheral Control functions ***********************************************/
+HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig);
+HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *AnalogWDGConfig);
+
+/**
+ * @}
+ */
+
+/* Peripheral State functions *************************************************/
+/** @addtogroup ADC_Exported_Functions_Group4
+ * @{
+ */
+uint32_t HAL_ADC_GetState(ADC_HandleTypeDef *hadc);
+uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* STM32C0xx_HAL_ADC_H */
diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h b/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h
new file mode 100644
index 0000000000..e60ae852b6
--- /dev/null
+++ b/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h
@@ -0,0 +1,185 @@
+/**
+ ******************************************************************************
+ * @file stm32c0xx_hal_adc_ex.h
+ * @author MCD Application Team
+ * @brief Header file of ADC HAL extended module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2022 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32C0xx_HAL_ADC_EX_H
+#define STM32C0xx_HAL_ADC_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32c0xx_hal_def.h"
+
+/** @addtogroup STM32C0xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup ADCEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup ADCEx_Exported_Types ADC Extended Exported Types
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup ADCEx_Exported_Constants ADC Extended Exported Constants
+ * @{
+ */
+
+/** @defgroup ADC_HAL_EC_GROUPS ADC instance - Groups
+ * @{
+ */
+#define ADC_REGULAR_GROUP (LL_ADC_GROUP_REGULAR) /*!< ADC group regular (available on all STM32 devices) */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+
+/** @defgroup ADCEx_Private_Macro_internal_HAL_driver ADC Extended Private Macros
+ * @{
+ */
+/* Macro reserved for internal HAL driver usage, not intended to be used in */
+/* code of final user. */
+
+/**
+ * @brief Check whether or not ADC is independent.
+ * @param __HANDLE__ ADC handle.
+ * @note When multimode feature is not available, the macro always returns SET.
+ * @retval SET (ADC is independent) or RESET (ADC is not).
+ */
+#define ADC_IS_INDEPENDENT(__HANDLE__) (SET)
+
+
+/**
+ * @brief Calibration factor size verification (7 bits maximum).
+ * @param __CALIBRATION_FACTOR__ Calibration factor value.
+ * @retval SET (__CALIBRATION_FACTOR__ is within the authorized size) or RESET (__CALIBRATION_FACTOR__ is too large)
+ */
+#define IS_ADC_CALFACT(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) <= (0x7FU))
+
+/**
+ * @brief Verify the ADC oversampling ratio.
+ * @param __RATIO__ programmed ADC oversampling ratio.
+ * @retval SET (__RATIO__ is a valid value) or RESET (__RATIO__ is invalid)
+ */
+#define IS_ADC_OVERSAMPLING_RATIO(__RATIO__) (((__RATIO__) == ADC_OVERSAMPLING_RATIO_2 ) || \
+ ((__RATIO__) == ADC_OVERSAMPLING_RATIO_4 ) || \
+ ((__RATIO__) == ADC_OVERSAMPLING_RATIO_8 ) || \
+ ((__RATIO__) == ADC_OVERSAMPLING_RATIO_16 ) || \
+ ((__RATIO__) == ADC_OVERSAMPLING_RATIO_32 ) || \
+ ((__RATIO__) == ADC_OVERSAMPLING_RATIO_64 ) || \
+ ((__RATIO__) == ADC_OVERSAMPLING_RATIO_128 ) || \
+ ((__RATIO__) == ADC_OVERSAMPLING_RATIO_256 ))
+
+/**
+ * @brief Verify the ADC oversampling shift.
+ * @param __SHIFT__ programmed ADC oversampling shift.
+ * @retval SET (__SHIFT__ is a valid value) or RESET (__SHIFT__ is invalid)
+ */
+#define IS_ADC_RIGHT_BIT_SHIFT(__SHIFT__) (((__SHIFT__) == ADC_RIGHTBITSHIFT_NONE) || \
+ ((__SHIFT__) == ADC_RIGHTBITSHIFT_1 ) || \
+ ((__SHIFT__) == ADC_RIGHTBITSHIFT_2 ) || \
+ ((__SHIFT__) == ADC_RIGHTBITSHIFT_3 ) || \
+ ((__SHIFT__) == ADC_RIGHTBITSHIFT_4 ) || \
+ ((__SHIFT__) == ADC_RIGHTBITSHIFT_5 ) || \
+ ((__SHIFT__) == ADC_RIGHTBITSHIFT_6 ) || \
+ ((__SHIFT__) == ADC_RIGHTBITSHIFT_7 ) || \
+ ((__SHIFT__) == ADC_RIGHTBITSHIFT_8 ))
+
+/**
+ * @brief Verify the ADC oversampling triggered mode.
+ * @param __MODE__ programmed ADC oversampling triggered mode.
+ * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+ */
+#define IS_ADC_TRIGGERED_OVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_TRIGGEREDMODE_SINGLE_TRIGGER) || \
+ ((__MODE__) == ADC_TRIGGEREDMODE_MULTI_TRIGGER) )
+
+
+/**
+ * @}
+ */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup ADCEx_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup ADCEx_Exported_Functions_Group1
+ * @{
+ */
+/* IO operation functions *****************************************************/
+
+/* ADC calibration */
+HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc);
+uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t CalibrationFactor);
+
+/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */
+void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef *hadc);
+void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef *hadc);
+void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef *hadc);
+void HAL_ADCEx_ChannelConfigReadyCallback(ADC_HandleTypeDef *hadc);
+
+/**
+ * @}
+ */
+
+/** @addtogroup ADCEx_Exported_Functions_Group2
+ * @{
+ */
+/* Peripheral Control functions ***********************************************/
+HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef *hadc);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32C0xx_HAL_ADC_EX_H */
diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_conf_template.h b/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_conf_template.h
new file mode 100644
index 0000000000..ba22efb5bd
--- /dev/null
+++ b/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_conf_template.h
@@ -0,0 +1,270 @@
+/**
+ ******************************************************************************
+ * @file stm32c0xx_hal_conf.h
+ * @author MCD Application Team
+ * @brief HAL configuration template file.
+ * This file should be copied to the application folder and renamed
+ * to stm32c0xx_hal_conf.h.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2022 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32C0xx_HAL_CONF_H
+#define STM32C0xx_HAL_CONF_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+ * @brief This is the list of modules to be used in the HAL driver
+ */
+#define HAL_MODULE_ENABLED
+#define HAL_ADC_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_CRC_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_I2C_MODULE_ENABLED
+#define HAL_I2S_MODULE_ENABLED
+#define HAL_IRDA_MODULE_ENABLED
+#define HAL_IWDG_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+#define HAL_RTC_MODULE_ENABLED
+#define HAL_SMARTCARD_MODULE_ENABLED
+#define HAL_SMBUS_MODULE_ENABLED
+#define HAL_SPI_MODULE_ENABLED
+#define HAL_TIM_MODULE_ENABLED
+#define HAL_UART_MODULE_ENABLED
+#define HAL_USART_MODULE_ENABLED
+#define HAL_WWDG_MODULE_ENABLED
+
+/* ########################## Register Callbacks selection ############################## */
+/**
+ * @brief Set below the peripheral configuration to "1U" to add the support
+ * of HAL callback registration/unregistration feature for the HAL
+ * driver(s). This allows user application to provide specific callback
+ * functions thanks to HAL_PPP_RegisterCallback() rather than overwriting
+ * the default weak callback functions (see each stm32c0xx_hal_ppp.h file
+ * for possible callback identifiers defined in HAL_PPP_CallbackIDTypeDef
+ * for each PPP peripheral).
+ */
+#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */
+#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */
+#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */
+#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */
+#define USE_HAL_IWDG_REGISTER_CALLBACKS 0U /* IWDG register callback disabled */
+#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */
+#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */
+#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */
+#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */
+#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */
+#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */
+#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */
+#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+ * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+ * This value is used by the RCC HAL module to compute the system frequency
+ * (when HSE is used as system clock source, directly or through the PLL).
+ */
+#if !defined (HSE_VALUE)
+#define HSE_VALUE (48000000U) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined (HSE_STARTUP_TIMEOUT)
+#define HSE_STARTUP_TIMEOUT (100UL) /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+ * @brief Internal High Speed oscillator (HSI) value.
+ * This value is used by the RCC HAL module to compute the system frequency
+ * (when HSI is used as system clock source, directly or through the PLL).
+ */
+#if !defined (HSI_VALUE)
+#define HSI_VALUE (48000000U) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+ * @brief Internal Low Speed oscillator (LSI) value.
+ */
+#if !defined (LSI_VALUE)
+#define LSI_VALUE (32000UL) /*!< LSI Typical Value in Hz*/
+#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
+The real value may vary depending on the variations
+in voltage and temperature.*/
+#if !defined (LSI_STARTUP_TIME)
+#define LSI_STARTUP_TIME 130UL /*!< Time out for LSI start up, in ms */
+#endif /* LSI_STARTUP_TIME */
+/**
+ * @brief External Low Speed oscillator (LSE) value.
+ * This value is used by the UART, RTC HAL module to compute the system frequency
+ */
+#if !defined (LSE_VALUE)
+#define LSE_VALUE (32768UL) /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+#if !defined (LSE_STARTUP_TIMEOUT)
+#define LSE_STARTUP_TIMEOUT (5000UL) /*!< Time out for LSE start up, in ms */
+#endif /* LSE_STARTUP_TIMEOUT */
+
+/**
+ * @brief External clock source for I2S1 peripheral
+ * This value is used by the RCC HAL module to compute the I2S1 clock source
+ * frequency.
+ */
+#if !defined (EXTERNAL_I2S1_CLOCK_VALUE)
+#define EXTERNAL_I2S1_CLOCK_VALUE (48000UL) /*!< Value of the I2S1 External clock source in Hz*/
+#endif /* EXTERNAL_I2S1_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+ === you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+ * @brief This is the HAL system configuration section
+ */
+#define VDD_VALUE (3300UL) /*!< Value of VDD in mv */
+#define TICK_INT_PRIORITY ((1UL<<__NVIC_PRIO_BITS) - 1UL) /*!< tick interrupt priority */
+#define USE_RTOS 0U
+#define PREFETCH_ENABLE 1U
+#define INSTRUCTION_CACHE_ENABLE 1U
+
+
+/* ########################## Assert Selection ############################## */
+/**
+ * @brief Uncomment the line below to expanse the "assert_param" macro in the
+ * HAL drivers code
+ */
+/* #define USE_FULL_ASSERT 1U */
+
+/* Includes ------------------------------------------------------------------*/
+/**
+ * @brief Include modules header file
+ */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+#include "stm32c0xx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+#include "stm32c0xx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+#include "stm32c0xx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+#include "stm32c0xx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+#include "stm32c0xx_hal_adc.h"
+#include "stm32c0xx_hal_adc_ex.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+#include "stm32c0xx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+#include "stm32c0xx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+#include "stm32c0xx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+#include "stm32c0xx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+#include "stm32c0xx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+#include "stm32c0xx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+#include "stm32c0xx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+#include "stm32c0xx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+#include "stm32c0xx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+#include "stm32c0xx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+#include "stm32c0xx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+#include "stm32c0xx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+#include "stm32c0xx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+#include "stm32c0xx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+#include "stm32c0xx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+#include "stm32c0xx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef USE_FULL_ASSERT
+/**
+ * @brief The assert_param macro is used for functions parameters check.
+ * @param expr If expr is false, it calls assert_failed function
+ * which reports the name of the source file and the source
+ * line number of the call that failed.
+ * If expr is true, it returns no value.
+ * @retval None
+ */
+#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+void assert_failed(uint8_t *file, uint32_t line);
+#else
+#define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32C0xx_HAL_CONF_H */
diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h b/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h
new file mode 100644
index 0000000000..9316a6fe34
--- /dev/null
+++ b/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h
@@ -0,0 +1,365 @@
+/**
+ ******************************************************************************
+ * @file stm32c0xx_hal_cortex.h
+ * @author MCD Application Team
+ * @brief Header file of CORTEX HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2022 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32C0xx_HAL_CORTEX_H
+#define STM32C0xx_HAL_CORTEX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32c0xx_hal_def.h"
+
+/** @addtogroup STM32C0xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup CORTEX CORTEX
+ * @brief CORTEX HAL module driver
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup CORTEX_Exported_Types CORTEX Exported Types
+ * @{
+ */
+
+#if (__MPU_PRESENT == 1)
+/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
+ * @brief MPU Region initialization structure
+ * @{
+ */
+typedef struct
+{
+ uint8_t Enable; /*!< Specifies the status of the region.
+ This parameter can be a value of @ref CORTEX_MPU_Region_Enable */
+ uint8_t Number; /*!< Specifies the number of the region to protect.
+ This parameter can be a value of @ref CORTEX_MPU_Region_Number */
+ uint32_t BaseAddress; /*!< Specifies the base address of the region to protect.
+ */
+ uint8_t Size; /*!< Specifies the size of the region to protect.
+ This parameter can be a value of @ref CORTEX_MPU_Region_Size */
+ uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable.
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
+ uint8_t TypeExtField; /*!< Specifies the TEX field level.
+ This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */
+ uint8_t AccessPermission; /*!< Specifies the region access permission type.
+ This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */
+ uint8_t DisableExec; /*!< Specifies the instruction access status.
+ This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */
+ uint8_t IsShareable; /*!< Specifies the shareability status of the protected region.
+ This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */
+ uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected.
+ This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */
+ uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region.
+ This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */
+} MPU_Region_InitTypeDef;
+/**
+ * @}
+ */
+#endif /* __MPU_PRESENT */
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants
+ * @{
+ */
+
+/** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source
+ * @{
+ */
+#define SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U
+#define SYSTICK_CLKSOURCE_HCLK 0x00000004U
+
+/**
+ * @}
+ */
+
+#if (__MPU_PRESENT == 1)
+/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control CORTEX MPU HFNMI and PRIVILEGED Access control
+ * @{
+ */
+#define MPU_HFNMI_PRIVDEF_NONE 0x00000000U
+#define MPU_HARDFAULT_NMI (MPU_CTRL_HFNMIENA_Msk)
+#define MPU_PRIVILEGED_DEFAULT (MPU_CTRL_PRIVDEFENA_Msk)
+#define MPU_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk)
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
+ * @{
+ */
+#define MPU_REGION_ENABLE ((uint8_t)0x01)
+#define MPU_REGION_DISABLE ((uint8_t)0x00)
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
+ * @{
+ */
+#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00)
+#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01)
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
+ * @{
+ */
+#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01)
+#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00)
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable
+ * @{
+ */
+#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01)
+#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00)
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable
+ * @{
+ */
+#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01)
+#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00)
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_TEX_Levels CORTEX MPU TEX Levels
+ * @{
+ */
+#define MPU_TEX_LEVEL0 ((uint8_t)0x00)
+#define MPU_TEX_LEVEL1 ((uint8_t)0x01)
+#define MPU_TEX_LEVEL2 ((uint8_t)0x02)
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size
+ * @{
+ */
+#define MPU_REGION_SIZE_256B ((uint8_t)0x07)
+#define MPU_REGION_SIZE_512B ((uint8_t)0x08)
+#define MPU_REGION_SIZE_1KB ((uint8_t)0x09)
+#define MPU_REGION_SIZE_2KB ((uint8_t)0x0A)
+#define MPU_REGION_SIZE_4KB ((uint8_t)0x0B)
+#define MPU_REGION_SIZE_8KB ((uint8_t)0x0C)
+#define MPU_REGION_SIZE_16KB ((uint8_t)0x0D)
+#define MPU_REGION_SIZE_32KB ((uint8_t)0x0E)
+#define MPU_REGION_SIZE_64KB ((uint8_t)0x0F)
+#define MPU_REGION_SIZE_128KB ((uint8_t)0x10)
+#define MPU_REGION_SIZE_256KB ((uint8_t)0x11)
+#define MPU_REGION_SIZE_512KB ((uint8_t)0x12)
+#define MPU_REGION_SIZE_1MB ((uint8_t)0x13)
+#define MPU_REGION_SIZE_2MB ((uint8_t)0x14)
+#define MPU_REGION_SIZE_4MB ((uint8_t)0x15)
+#define MPU_REGION_SIZE_8MB ((uint8_t)0x16)
+#define MPU_REGION_SIZE_16MB ((uint8_t)0x17)
+#define MPU_REGION_SIZE_32MB ((uint8_t)0x18)
+#define MPU_REGION_SIZE_64MB ((uint8_t)0x19)
+#define MPU_REGION_SIZE_128MB ((uint8_t)0x1A)
+#define MPU_REGION_SIZE_256MB ((uint8_t)0x1B)
+#define MPU_REGION_SIZE_512MB ((uint8_t)0x1C)
+#define MPU_REGION_SIZE_1GB ((uint8_t)0x1D)
+#define MPU_REGION_SIZE_2GB ((uint8_t)0x1E)
+#define MPU_REGION_SIZE_4GB ((uint8_t)0x1F)
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes
+ * @{
+ */
+#define MPU_REGION_NO_ACCESS ((uint8_t)0x00)
+#define MPU_REGION_PRIV_RW ((uint8_t)0x01)
+#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02)
+#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03)
+#define MPU_REGION_PRIV_RO ((uint8_t)0x05)
+#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06)
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
+ * @{
+ */
+#define MPU_REGION_NUMBER0 ((uint8_t)0x00)
+#define MPU_REGION_NUMBER1 ((uint8_t)0x01)
+#define MPU_REGION_NUMBER2 ((uint8_t)0x02)
+#define MPU_REGION_NUMBER3 ((uint8_t)0x03)
+#define MPU_REGION_NUMBER4 ((uint8_t)0x04)
+#define MPU_REGION_NUMBER5 ((uint8_t)0x05)
+#define MPU_REGION_NUMBER6 ((uint8_t)0x06)
+#define MPU_REGION_NUMBER7 ((uint8_t)0x07)
+/**
+ * @}
+ */
+#endif /* __MPU_PRESENT */
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
+ * @{
+ */
+
+/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and Configuration functions
+ * @brief Initialization and Configuration functions
+ * @{
+ */
+/* Initialization and Configuration functions *****************************/
+void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
+void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
+void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
+void HAL_NVIC_SystemReset(void);
+uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
+ * @brief Cortex control functions
+ * @{
+ */
+/* Peripheral Control functions *************************************************/
+uint32_t HAL_NVIC_GetPriority(IRQn_Type IRQn);
+uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
+void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
+void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
+void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
+void HAL_SYSTICK_IRQHandler(void);
+void HAL_SYSTICK_Callback(void);
+
+#if (__MPU_PRESENT == 1U)
+void HAL_MPU_Enable(uint32_t MPU_Control);
+void HAL_MPU_Disable(void);
+void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
+#endif /* __MPU_PRESENT */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup CORTEX_Private_Macros CORTEX Private Macros
+ * @{
+ */
+#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x4U)
+
+#define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) > SysTick_IRQn)
+
+#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
+ ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
+
+#if (__MPU_PRESENT == 1)
+#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \
+ ((STATE) == MPU_REGION_DISABLE))
+
+#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
+ ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
+
+#define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \
+ ((STATE) == MPU_ACCESS_NOT_SHAREABLE))
+
+#define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \
+ ((STATE) == MPU_ACCESS_NOT_CACHEABLE))
+
+#define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \
+ ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
+
+#define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \
+ ((TYPE) == MPU_TEX_LEVEL1) || \
+ ((TYPE) == MPU_TEX_LEVEL2))
+
+#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \
+ ((TYPE) == MPU_REGION_PRIV_RW) || \
+ ((TYPE) == MPU_REGION_PRIV_RW_URO) || \
+ ((TYPE) == MPU_REGION_FULL_ACCESS) || \
+ ((TYPE) == MPU_REGION_PRIV_RO) || \
+ ((TYPE) == MPU_REGION_PRIV_RO_URO))
+
+#define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \
+ ((NUMBER) == MPU_REGION_NUMBER1) || \
+ ((NUMBER) == MPU_REGION_NUMBER2) || \
+ ((NUMBER) == MPU_REGION_NUMBER3) || \
+ ((NUMBER) == MPU_REGION_NUMBER4) || \
+ ((NUMBER) == MPU_REGION_NUMBER5) || \
+ ((NUMBER) == MPU_REGION_NUMBER6) || \
+ ((NUMBER) == MPU_REGION_NUMBER7))
+
+#define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_256B) || \
+ ((SIZE) == MPU_REGION_SIZE_512B) || \
+ ((SIZE) == MPU_REGION_SIZE_1KB) || \
+ ((SIZE) == MPU_REGION_SIZE_2KB) || \
+ ((SIZE) == MPU_REGION_SIZE_4KB) || \
+ ((SIZE) == MPU_REGION_SIZE_8KB) || \
+ ((SIZE) == MPU_REGION_SIZE_16KB) || \
+ ((SIZE) == MPU_REGION_SIZE_32KB))
+
+#define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FFU)
+#endif /* __MPU_PRESENT */
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32C0xx_HAL_CORTEX_H */
diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_crc.h b/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_crc.h
new file mode 100644
index 0000000000..cf4e879bcf
--- /dev/null
+++ b/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_crc.h
@@ -0,0 +1,342 @@
+/**
+ ******************************************************************************
+ * @file stm32c0xx_hal_crc.h
+ * @author MCD Application Team
+ * @brief Header file of CRC HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2022 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32C0xx_HAL_CRC_H
+#define STM32C0xx_HAL_CRC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32c0xx_hal_def.h"
+
+/** @addtogroup STM32C0xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup CRC
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup CRC_Exported_Types CRC Exported Types
+ * @{
+ */
+
+/**
+ * @brief CRC HAL State Structure definition
+ */
+typedef enum
+{
+ HAL_CRC_STATE_RESET = 0x00U, /*!< CRC not yet initialized or disabled */
+ HAL_CRC_STATE_READY = 0x01U, /*!< CRC initialized and ready for use */
+ HAL_CRC_STATE_BUSY = 0x02U, /*!< CRC internal process is ongoing */
+ HAL_CRC_STATE_TIMEOUT = 0x03U, /*!< CRC timeout state */
+ HAL_CRC_STATE_ERROR = 0x04U /*!< CRC error state */
+} HAL_CRC_StateTypeDef;
+
+/**
+ * @brief CRC Init Structure definition
+ */
+typedef struct
+{
+ uint8_t DefaultPolynomialUse; /*!< This parameter is a value of @ref CRC_Default_Polynomial and indicates if default polynomial is used.
+ If set to DEFAULT_POLYNOMIAL_ENABLE, resort to default
+ X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 +
+ X^4 + X^2+ X +1.
+ In that case, there is no need to set GeneratingPolynomial field.
+ If otherwise set to DEFAULT_POLYNOMIAL_DISABLE, GeneratingPolynomial and
+ CRCLength fields must be set. */
+
+ uint8_t DefaultInitValueUse; /*!< This parameter is a value of @ref CRC_Default_InitValue_Use and indicates if default init value is used.
+ If set to DEFAULT_INIT_VALUE_ENABLE, resort to default
+ 0xFFFFFFFF value. In that case, there is no need to set InitValue field. If
+ otherwise set to DEFAULT_INIT_VALUE_DISABLE, InitValue field must be set. */
+
+ uint32_t GeneratingPolynomial; /*!< Set CRC generating polynomial as a 7, 8, 16 or 32-bit long value for a polynomial degree
+ respectively equal to 7, 8, 16 or 32. This field is written in normal,
+ representation e.g., for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1
+ is written 0x65. No need to specify it if DefaultPolynomialUse is set to
+ DEFAULT_POLYNOMIAL_ENABLE. */
+
+ uint32_t CRCLength; /*!< This parameter is a value of @ref CRC_Polynomial_Sizes and indicates CRC length.
+ Value can be either one of
+ @arg @ref CRC_POLYLENGTH_32B (32-bit CRC),
+ @arg @ref CRC_POLYLENGTH_16B (16-bit CRC),
+ @arg @ref CRC_POLYLENGTH_8B (8-bit CRC),
+ @arg @ref CRC_POLYLENGTH_7B (7-bit CRC). */
+
+ uint32_t InitValue; /*!< Init value to initiate CRC computation. No need to specify it if DefaultInitValueUse
+ is set to DEFAULT_INIT_VALUE_ENABLE. */
+
+ uint32_t InputDataInversionMode; /*!< This parameter is a value of @ref CRCEx_Input_Data_Inversion and specifies input data inversion mode.
+ Can be either one of the following values
+ @arg @ref CRC_INPUTDATA_INVERSION_NONE no input data inversion
+ @arg @ref CRC_INPUTDATA_INVERSION_BYTE byte-wise inversion, 0x1A2B3C4D
+ becomes 0x58D43CB2
+ @arg @ref CRC_INPUTDATA_INVERSION_HALFWORD halfword-wise inversion,
+ 0x1A2B3C4D becomes 0xD458B23C
+ @arg @ref CRC_INPUTDATA_INVERSION_WORD word-wise inversion, 0x1A2B3C4D
+ becomes 0xB23CD458 */
+
+ uint32_t OutputDataInversionMode; /*!< This parameter is a value of @ref CRCEx_Output_Data_Inversion and specifies output data (i.e. CRC) inversion mode.
+ Can be either
+ @arg @ref CRC_OUTPUTDATA_INVERSION_DISABLE no CRC inversion,
+ @arg @ref CRC_OUTPUTDATA_INVERSION_ENABLE CRC 0x11223344 is converted
+ into 0x22CC4488 */
+} CRC_InitTypeDef;
+
+/**
+ * @brief CRC Handle Structure definition
+ */
+typedef struct
+{
+ CRC_TypeDef *Instance; /*!< Register base address */
+
+ CRC_InitTypeDef Init; /*!< CRC configuration parameters */
+
+ HAL_LockTypeDef Lock; /*!< CRC Locking object */
+
+ __IO HAL_CRC_StateTypeDef State; /*!< CRC communication state */
+
+ uint32_t InputDataFormat; /*!< This parameter is a value of @ref CRC_Input_Buffer_Format and specifies input data format.
+ Can be either
+ @arg @ref CRC_INPUTDATA_FORMAT_BYTES input data is a stream of bytes
+ (8-bit data)
+ @arg @ref CRC_INPUTDATA_FORMAT_HALFWORDS input data is a stream of
+ half-words (16-bit data)
+ @arg @ref CRC_INPUTDATA_FORMAT_WORDS input data is a stream of words
+ (32-bit data)
+
+ Note that constant CRC_INPUT_FORMAT_UNDEFINED is defined but an initialization
+ error must occur if InputBufferFormat is not one of the three values listed
+ above */
+} CRC_HandleTypeDef;
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup CRC_Exported_Constants CRC Exported Constants
+ * @{
+ */
+
+/** @defgroup CRC_Default_Polynomial_Value Default CRC generating polynomial
+ * @{
+ */
+#define DEFAULT_CRC32_POLY 0x04C11DB7U /*!< X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2+ X +1 */
+/**
+ * @}
+ */
+
+/** @defgroup CRC_Default_InitValue Default CRC computation initialization value
+ * @{
+ */
+#define DEFAULT_CRC_INITVALUE 0xFFFFFFFFU /*!< Initial CRC default value */
+/**
+ * @}
+ */
+
+/** @defgroup CRC_Default_Polynomial Indicates whether or not default polynomial is used
+ * @{
+ */
+#define DEFAULT_POLYNOMIAL_ENABLE ((uint8_t)0x00U) /*!< Enable default generating polynomial 0x04C11DB7 */
+#define DEFAULT_POLYNOMIAL_DISABLE ((uint8_t)0x01U) /*!< Disable default generating polynomial 0x04C11DB7 */
+/**
+ * @}
+ */
+
+/** @defgroup CRC_Default_InitValue_Use Indicates whether or not default init value is used
+ * @{
+ */
+#define DEFAULT_INIT_VALUE_ENABLE ((uint8_t)0x00U) /*!< Enable initial CRC default value */
+#define DEFAULT_INIT_VALUE_DISABLE ((uint8_t)0x01U) /*!< Disable initial CRC default value */
+/**
+ * @}
+ */
+
+/** @defgroup CRC_Polynomial_Sizes Polynomial sizes to configure the peripheral
+ * @{
+ */
+#define CRC_POLYLENGTH_32B 0x00000000U /*!< Resort to a 32-bit long generating polynomial */
+#define CRC_POLYLENGTH_16B CRC_CR_POLYSIZE_0 /*!< Resort to a 16-bit long generating polynomial */
+#define CRC_POLYLENGTH_8B CRC_CR_POLYSIZE_1 /*!< Resort to a 8-bit long generating polynomial */
+#define CRC_POLYLENGTH_7B CRC_CR_POLYSIZE /*!< Resort to a 7-bit long generating polynomial */
+/**
+ * @}
+ */
+
+/** @defgroup CRC_Polynomial_Size_Definitions CRC polynomial possible sizes actual definitions
+ * @{
+ */
+#define HAL_CRC_LENGTH_32B 32U /*!< 32-bit long CRC */
+#define HAL_CRC_LENGTH_16B 16U /*!< 16-bit long CRC */
+#define HAL_CRC_LENGTH_8B 8U /*!< 8-bit long CRC */
+#define HAL_CRC_LENGTH_7B 7U /*!< 7-bit long CRC */
+/**
+ * @}
+ */
+
+/** @defgroup CRC_Input_Buffer_Format Input Buffer Format
+ * @{
+ */
+/* WARNING: CRC_INPUT_FORMAT_UNDEFINED is created for reference purposes but
+ * an error is triggered in HAL_CRC_Init() if InputDataFormat field is set
+ * to CRC_INPUT_FORMAT_UNDEFINED: the format MUST be defined by the user for
+ * the CRC APIs to provide a correct result */
+#define CRC_INPUTDATA_FORMAT_UNDEFINED 0x00000000U /*!< Undefined input data format */
+#define CRC_INPUTDATA_FORMAT_BYTES 0x00000001U /*!< Input data in byte format */
+#define CRC_INPUTDATA_FORMAT_HALFWORDS 0x00000002U /*!< Input data in half-word format */
+#define CRC_INPUTDATA_FORMAT_WORDS 0x00000003U /*!< Input data in word format */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup CRC_Exported_Macros CRC Exported Macros
+ * @{
+ */
+
+/** @brief Reset CRC handle state.
+ * @param __HANDLE__ CRC handle.
+ * @retval None
+ */
+#define __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRC_STATE_RESET)
+
+/**
+ * @brief Reset CRC Data Register.
+ * @param __HANDLE__ CRC handle
+ * @retval None
+ */
+#define __HAL_CRC_DR_RESET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET)
+
+/**
+ * @brief Set CRC INIT non-default value
+ * @param __HANDLE__ CRC handle
+ * @param __INIT__ 32-bit initial value
+ * @retval None
+ */
+#define __HAL_CRC_INITIALCRCVALUE_CONFIG(__HANDLE__, __INIT__) ((__HANDLE__)->Instance->INIT = (__INIT__))
+
+/**
+ * @brief Store data in the Independent Data (ID) register.
+ * @param __HANDLE__ CRC handle
+ * @param __VALUE__ Value to be stored in the ID register
+ * @note Refer to the Reference Manual to get the authorized __VALUE__ length in bits
+ * @retval None
+ */
+#define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (WRITE_REG((__HANDLE__)->Instance->IDR, (__VALUE__)))
+
+/**
+ * @brief Return the data stored in the Independent Data (ID) register.
+ * @param __HANDLE__ CRC handle
+ * @note Refer to the Reference Manual to get the authorized __VALUE__ length in bits
+ * @retval Value of the ID register
+ */
+#define __HAL_CRC_GET_IDR(__HANDLE__) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR)
+/**
+ * @}
+ */
+
+
+/* Private macros --------------------------------------------------------*/
+/** @defgroup CRC_Private_Macros CRC Private Macros
+ * @{
+ */
+
+#define IS_DEFAULT_POLYNOMIAL(DEFAULT) (((DEFAULT) == DEFAULT_POLYNOMIAL_ENABLE) || \
+ ((DEFAULT) == DEFAULT_POLYNOMIAL_DISABLE))
+
+#define IS_DEFAULT_INIT_VALUE(VALUE) (((VALUE) == DEFAULT_INIT_VALUE_ENABLE) || \
+ ((VALUE) == DEFAULT_INIT_VALUE_DISABLE))
+
+#define IS_CRC_POL_LENGTH(LENGTH) (((LENGTH) == CRC_POLYLENGTH_32B) || \
+ ((LENGTH) == CRC_POLYLENGTH_16B) || \
+ ((LENGTH) == CRC_POLYLENGTH_8B) || \
+ ((LENGTH) == CRC_POLYLENGTH_7B))
+
+#define IS_CRC_INPUTDATA_FORMAT(FORMAT) (((FORMAT) == CRC_INPUTDATA_FORMAT_BYTES) || \
+ ((FORMAT) == CRC_INPUTDATA_FORMAT_HALFWORDS) || \
+ ((FORMAT) == CRC_INPUTDATA_FORMAT_WORDS))
+
+/**
+ * @}
+ */
+
+/* Include CRC HAL Extended module */
+#include "stm32c0xx_hal_crc_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup CRC_Exported_Functions CRC Exported Functions
+ * @{
+ */
+
+/* Initialization and de-initialization functions ****************************/
+/** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc);
+HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc);
+void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc);
+void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc);
+/**
+ * @}
+ */
+
+/* Peripheral Control functions ***********************************************/
+/** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions
+ * @{
+ */
+uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
+uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
+/**
+ * @}
+ */
+
+/* Peripheral State and Error functions ***************************************/
+/** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions
+ * @{
+ */
+HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32C0xx_HAL_CRC_H */
diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_crc_ex.h b/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_crc_ex.h
new file mode 100644
index 0000000000..8cd65db879
--- /dev/null
+++ b/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_crc_ex.h
@@ -0,0 +1,150 @@
+/**
+ ******************************************************************************
+ * @file stm32c0xx_hal_crc_ex.h
+ * @author MCD Application Team
+ * @brief Header file of CRC HAL extended module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2022 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32C0xx_HAL_CRC_EX_H
+#define STM32C0xx_HAL_CRC_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32c0xx_hal_def.h"
+
+/** @addtogroup STM32C0xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup CRCEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup CRCEx_Exported_Constants CRC Extended Exported Constants
+ * @{
+ */
+
+/** @defgroup CRCEx_Input_Data_Inversion Input Data Inversion Modes
+ * @{
+ */
+#define CRC_INPUTDATA_INVERSION_NONE 0x00000000U /*!< No input data inversion */
+#define CRC_INPUTDATA_INVERSION_BYTE CRC_CR_REV_IN_0 /*!< Byte-wise input data inversion */
+#define CRC_INPUTDATA_INVERSION_HALFWORD CRC_CR_REV_IN_1 /*!< HalfWord-wise input data inversion */
+#define CRC_INPUTDATA_INVERSION_WORD CRC_CR_REV_IN /*!< Word-wise input data inversion */
+/**
+ * @}
+ */
+
+/** @defgroup CRCEx_Output_Data_Inversion Output Data Inversion Modes
+ * @{
+ */
+#define CRC_OUTPUTDATA_INVERSION_DISABLE 0x00000000U /*!< No output data inversion */
+#define CRC_OUTPUTDATA_INVERSION_ENABLE CRC_CR_REV_OUT /*!< Bit-wise output data inversion */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup CRCEx_Exported_Macros CRC Extended Exported Macros
+ * @{
+ */
+
+/**
+ * @brief Set CRC output reversal
+ * @param __HANDLE__ CRC handle
+ * @retval None
+ */
+#define __HAL_CRC_OUTPUTREVERSAL_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_REV_OUT)
+
+/**
+ * @brief Unset CRC output reversal
+ * @param __HANDLE__ CRC handle
+ * @retval None
+ */
+#define __HAL_CRC_OUTPUTREVERSAL_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(CRC_CR_REV_OUT))
+
+/**
+ * @brief Set CRC non-default polynomial
+ * @param __HANDLE__ CRC handle
+ * @param __POLYNOMIAL__ 7, 8, 16 or 32-bit polynomial
+ * @retval None
+ */
+#define __HAL_CRC_POLYNOMIAL_CONFIG(__HANDLE__, __POLYNOMIAL__) ((__HANDLE__)->Instance->POL = (__POLYNOMIAL__))
+
+/**
+ * @}
+ */
+
+/* Private macros --------------------------------------------------------*/
+/** @defgroup CRCEx_Private_Macros CRC Extended Private Macros
+ * @{
+ */
+
+#define IS_CRC_INPUTDATA_INVERSION_MODE(MODE) (((MODE) == CRC_INPUTDATA_INVERSION_NONE) || \
+ ((MODE) == CRC_INPUTDATA_INVERSION_BYTE) || \
+ ((MODE) == CRC_INPUTDATA_INVERSION_HALFWORD) || \
+ ((MODE) == CRC_INPUTDATA_INVERSION_WORD))
+
+#define IS_CRC_OUTPUTDATA_INVERSION_MODE(MODE) (((MODE) == CRC_OUTPUTDATA_INVERSION_DISABLE) || \
+ ((MODE) == CRC_OUTPUTDATA_INVERSION_ENABLE))
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup CRCEx_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup CRCEx_Exported_Functions_Group1
+ * @{
+ */
+/* Initialization and de-initialization functions ****************************/
+HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength);
+HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode);
+HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32C0xx_HAL_CRC_EX_H */
diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h b/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h
new file mode 100644
index 0000000000..9ce6a0e991
--- /dev/null
+++ b/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_def.h
@@ -0,0 +1,197 @@
+/**
+ ******************************************************************************
+ * @file stm32c0xx_hal_def.h
+ * @author MCD Application Team
+ * @brief This file contains HAL common defines, enumeration, macros and
+ * structures definitions.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2022 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32C0xx_HAL_DEF
+#define STM32C0xx_HAL_DEF
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32c0xx.h"
+#include "Legacy/stm32_hal_legacy.h" /* Aliases file for old names compatibility */
+#include
+
+
+
+
+Release Notes for STM32C0xx CMSIS
+Copyright © 2022 STMicroelectronics
+
+
+
+Update History
+
+
+
+
+
+Main Changes
+First official release version of bits and registers definition aligned with STM32C0 reference manual
+
+
+
+
+
+
+
diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c
new file mode 100644
index 0000000000..f8bf366e23
--- /dev/null
+++ b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c
@@ -0,0 +1,633 @@
+/**
+ ******************************************************************************
+ * @file stm32c0xx_hal.c
+ * @author MCD Application Team
+ * @brief HAL module driver.
+ * This is the common part of the HAL initialization
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2022 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ The common HAL driver contains a set of generic and common APIs that can be
+ used by the PPP peripheral drivers and the user to start using the HAL.
+ [..]
+ The HAL contains two APIs' categories:
+ (+) Common HAL APIs
+ (+) Services HAL APIs
+
+ @endverbatim
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32c0xx_hal.h"
+
+/** @addtogroup STM32C0xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup HAL
+ * @brief HAL module driver
+ * @{
+ */
+
+#ifdef HAL_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/** @defgroup HAL_Private_Constants HAL Private Constants
+ * @{
+ */
+/**
+ * @brief STM32C0xx HAL Driver version number
+ */
+#define __STM32C0xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */
+#define __STM32C0xx_HAL_VERSION_SUB1 (0x00U) /*!< [23:16] sub1 version */
+#define __STM32C0xx_HAL_VERSION_SUB2 (0x01U) /*!< [15:8] sub2 version */
+#define __STM32C0xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */
+#define __STM32C0xx_HAL_VERSION ((__STM32C0xx_HAL_VERSION_MAIN << 24U)\
+ |(__STM32C0xx_HAL_VERSION_SUB1 << 16U)\
+ |(__STM32C0xx_HAL_VERSION_SUB2 << 8U )\
+ |(__STM32C0xx_HAL_VERSION_RC))
+
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Exported variables ---------------------------------------------------------*/
+/** @defgroup HAL_Exported_Variables HAL Exported Variables
+ * @{
+ */
+__IO uint32_t uwTick;
+uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS); /* Invalid PRIO */
+uint32_t uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */
+/**
+ * @}
+ */
+
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup HAL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup HAL_Exported_Functions_Group1
+ * @brief HAL Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### HAL Initialization and Configuration functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Initialize the Flash interface the NVIC allocation and initial time base
+ clock configuration.
+ (+) De-initialize common part of the HAL.
+ (+) Configure the time base source to have 1ms time base with a dedicated
+ Tick interrupt priority.
+ (++) SysTick timer is used by default as source of time base, but user
+ can eventually implement his proper time base source (a general purpose
+ timer for example or other time source), keeping in mind that Time base
+ duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and
+ handled in milliseconds basis.
+ (++) Time base configuration function (HAL_InitTick ()) is called automatically
+ at the beginning of the program after reset by HAL_Init() or at any time
+ when clock is configured, by HAL_RCC_ClockConfig().
+ (++) Source of time base is configured to generate interrupts at regular
+ time intervals. Care must be taken if HAL_Delay() is called from a
+ peripheral ISR process, the Tick interrupt line must have higher priority
+ (numerically lower) than the peripheral interrupt. Otherwise the caller
+ ISR process will be blocked.
+ (++) functions affecting time base configurations are declared as __weak
+ to make override possible in case of other implementations in user file.
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configure the Flash prefetch and the Instruction cache,
+ * the time base source, NVIC and any required global low level hardware
+ * by calling the HAL_MspInit() callback function to be optionally defined in user file
+ * stm32c0xx_hal_msp.c.
+ *
+ * @note HAL_Init() function is called at the beginning of program after reset and before
+ * the clock configuration.
+ *
+ * @note In the default implementation the System Timer (Systick) is used as source of time base.
+ * The Systick configuration is based on HSI clock, as HSI is the clock
+ * used after a system Reset.
+ * Once done, time base tick starts incrementing: the tick variable counter is incremented
+ * each 1ms in the SysTick_Handler() interrupt handler.
+ *
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_Init(void)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Configure Flash prefetch, Instruction cache */
+ /* Default configuration at reset is: */
+ /* - Prefetch disabled */
+ /* - Instruction cache enabled */
+
+#if (INSTRUCTION_CACHE_ENABLE == 0U)
+ __HAL_FLASH_INSTRUCTION_CACHE_DISABLE();
+#endif /* INSTRUCTION_CACHE_ENABLE */
+
+#if (PREFETCH_ENABLE != 0U)
+ __HAL_FLASH_PREFETCH_BUFFER_ENABLE();
+#endif /* PREFETCH_ENABLE */
+
+ /* Use SysTick as time base source and configure 1ms tick (default clock after Reset is HSI) */
+ if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
+ {
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Init the low level hardware */
+ HAL_MspInit();
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief This function de-Initializes common part of the HAL and stops the source of time base.
+ * @note This function is optional.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DeInit(void)
+{
+ /* Reset of all peripherals */
+ __HAL_RCC_APB1_FORCE_RESET();
+ __HAL_RCC_APB1_RELEASE_RESET();
+
+ __HAL_RCC_APB2_FORCE_RESET();
+ __HAL_RCC_APB2_RELEASE_RESET();
+
+ __HAL_RCC_AHB_FORCE_RESET();
+ __HAL_RCC_AHB_RELEASE_RESET();
+
+ __HAL_RCC_IOP_FORCE_RESET();
+ __HAL_RCC_IOP_RELEASE_RESET();
+
+ /* De-Init the low level hardware */
+ HAL_MspDeInit();
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initialize the MSP.
+ * @retval None
+ */
+__weak void HAL_MspInit(void)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes the MSP.
+ * @retval None
+ */
+__weak void HAL_MspDeInit(void)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief This function configures the source of the time base:
+ * The time source is configured to have 1ms time base with a dedicated
+ * Tick interrupt priority.
+ * @note This function is called automatically at the beginning of program after
+ * reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig().
+ * @note In the default implementation, SysTick timer is the source of time base.
+ * It is used to generate interrupts at regular time intervals.
+ * Care must be taken if HAL_Delay() is called from a peripheral ISR process,
+ * The SysTick interrupt must have higher priority (numerically lower)
+ * than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
+ * The function is declared as __weak to be overwritten in case of other
+ * implementation in user file.
+ * @param TickPriority Tick interrupt priority.
+ * @retval HAL status
+ */
+__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (uwTickFreq != 0U)
+ {
+ /*Configure the SysTick to have interrupt in 1ms time basis*/
+ if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) == 0U)
+ {
+ /* Configure the SysTick IRQ priority */
+ if (TickPriority < (1UL << __NVIC_PRIO_BITS))
+ {
+ HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
+ uwTickPrio = TickPriority;
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup HAL_Exported_Functions_Group2
+ * @brief HAL Control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### HAL Control functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Provide a tick value in millisecond
+ (+) Provide a blocking delay in millisecond
+ (+) Suspend the time base source interrupt
+ (+) Resume the time base source interrupt
+ (+) Get the HAL API driver version
+ (+) Get the device identifier
+ (+) Get the device revision identifier
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief This function is called to increment a global variable "uwTick"
+ * used as application time base.
+ * @note In the default implementation, this variable is incremented each 1ms
+ * in SysTick ISR.
+ * @note This function is declared as __weak to be overwritten in case of other
+ * implementations in user file.
+ * @retval None
+ */
+__weak void HAL_IncTick(void)
+{
+ uwTick += uwTickFreq;
+}
+
+/**
+ * @brief Provides a tick value in millisecond.
+ * @note This function is declared as __weak to be overwritten in case of other
+ * implementations in user file.
+ * @retval tick value
+ */
+__weak uint32_t HAL_GetTick(void)
+{
+ return uwTick;
+}
+
+/**
+ * @brief This function returns a tick priority.
+ * @retval tick priority
+ */
+uint32_t HAL_GetTickPrio(void)
+{
+ return uwTickPrio;
+}
+
+/**
+ * @brief Set new tick Freq.
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_SetTickFreq(uint32_t Freq)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ assert_param(IS_TICKFREQ(Freq));
+
+ if (uwTickFreq != Freq)
+ {
+ /* Apply the new tick Freq */
+ status = HAL_InitTick(uwTickPrio);
+
+ if (status == HAL_OK)
+ {
+ uwTickFreq = Freq;
+ }
+ }
+
+ return status;
+}
+
+/**
+ * @brief return tick frequency.
+ * @retval tick period in Hz
+ */
+uint32_t HAL_GetTickFreq(void)
+{
+ return uwTickFreq;
+}
+
+/**
+ * @brief This function provides minimum delay (in milliseconds) based
+ * on variable incremented.
+ * @note In the default implementation , SysTick timer is the source of time base.
+ * It is used to generate interrupts at regular time intervals where uwTick
+ * is incremented.
+ * @note This function is declared as __weak to be overwritten in case of other
+ * implementations in user file.
+ * @param Delay specifies the delay time length, in milliseconds.
+ * @retval None
+ */
+__weak void HAL_Delay(uint32_t Delay)
+{
+ uint32_t tickstart = HAL_GetTick();
+ uint32_t wait = Delay;
+
+ /* Add a freq to guarantee minimum wait */
+ if (wait < HAL_MAX_DELAY)
+ {
+ wait += (uint32_t)(uwTickFreq);
+ }
+
+ while ((HAL_GetTick() - tickstart) < wait)
+ {
+ }
+}
+
+/**
+ * @brief Suspend Tick increment.
+ * @note In the default implementation , SysTick timer is the source of time base. It is
+ * used to generate interrupts at regular time intervals. Once HAL_SuspendTick()
+ * is called, the SysTick interrupt will be disabled and so Tick increment
+ * is suspended.
+ * @note This function is declared as __weak to be overwritten in case of other
+ * implementations in user file.
+ * @retval None
+ */
+__weak void HAL_SuspendTick(void)
+{
+ /* Disable SysTick Interrupt */
+ CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
+}
+
+/**
+ * @brief Resume Tick increment.
+ * @note In the default implementation , SysTick timer is the source of time base. It is
+ * used to generate interrupts at regular time intervals. Once HAL_ResumeTick()
+ * is called, the SysTick interrupt will be enabled and so Tick increment
+ * is resumed.
+ * @note This function is declared as __weak to be overwritten in case of other
+ * implementations in user file.
+ * @retval None
+ */
+__weak void HAL_ResumeTick(void)
+{
+ /* Enable SysTick Interrupt */
+ SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
+}
+
+/**
+ * @brief Returns the HAL revision
+ * @retval version : 0xXYZR (8bits for each decimal, R for RC)
+ */
+uint32_t HAL_GetHalVersion(void)
+{
+ return __STM32C0xx_HAL_VERSION;
+}
+
+/**
+ * @brief Returns the device revision identifier.
+ * @retval Device revision identifier
+ */
+uint32_t HAL_GetREVID(void)
+{
+ return ((DBG->IDCODE & DBG_IDCODE_REV_ID) >> 16U);
+}
+
+/**
+ * @brief Returns the device identifier.
+ * @retval Device identifier
+ */
+uint32_t HAL_GetDEVID(void)
+{
+ return ((DBG->IDCODE) & DBG_IDCODE_DEV_ID);
+}
+
+/**
+ * @brief Returns first word of the unique device identifier (UID based on 96 bits)
+ * @retval Device identifier
+ */
+uint32_t HAL_GetUIDw0(void)
+{
+ return (READ_REG(*((uint32_t *)UID_BASE)));
+}
+
+/**
+ * @brief Returns second word of the unique device identifier (UID based on 96 bits)
+ * @retval Device identifier
+ */
+uint32_t HAL_GetUIDw1(void)
+{
+ return (READ_REG(*((uint32_t *)(UID_BASE + 4U))));
+}
+
+/**
+ * @brief Returns third word of the unique device identifier (UID based on 96 bits)
+ * @retval Device identifier
+ */
+uint32_t HAL_GetUIDw2(void)
+{
+ return (READ_REG(*((uint32_t *)(UID_BASE + 8U))));
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup HAL_Exported_Functions_Group3
+ * @brief HAL Debug functions
+ *
+@verbatim
+ ===============================================================================
+ ##### HAL Debug functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Enable/Disable Debug module during STOP mode
+ (+) Enable/Disable Debug module during STANDBY mode
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enable the Debug Module during STOP mode
+ * @retval None
+ */
+void HAL_DBGMCU_EnableDBGStopMode(void)
+{
+ SET_BIT(DBG->CR, DBG_CR_DBG_STOP);
+}
+
+/**
+ * @brief Disable the Debug Module during STOP mode
+ * @retval None
+ */
+void HAL_DBGMCU_DisableDBGStopMode(void)
+{
+ CLEAR_BIT(DBG->CR, DBG_CR_DBG_STOP);
+}
+
+/**
+ * @brief Enable the Debug Module during STANDBY mode
+ * @retval None
+ */
+void HAL_DBGMCU_EnableDBGStandbyMode(void)
+{
+ SET_BIT(DBG->CR, DBG_CR_DBG_STANDBY);
+}
+
+/**
+ * @brief Disable the Debug Module during STANDBY mode
+ * @retval None
+ */
+void HAL_DBGMCU_DisableDBGStandbyMode(void)
+{
+ CLEAR_BIT(DBG->CR, DBG_CR_DBG_STANDBY);
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup HAL_Exported_Functions_Group4
+ * @brief SYSCFG configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### HAL SYSCFG configuration functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Enable/Disable Pin remap
+ (+) Enable/Disable the I/O analog switch voltage booster
+@endverbatim
+ * @{
+ */
+
+
+/**
+ * @brief Enable the I/O analog switch voltage booster
+ * @retval None
+ */
+void HAL_SYSCFG_EnableIOAnalogSwitchBooster(void)
+{
+ SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN);
+}
+
+/**
+ * @brief Disable the I/O analog switch voltage booster
+ * @retval None
+ */
+void HAL_SYSCFG_DisableIOAnalogSwitchBooster(void)
+{
+ CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN);
+}
+
+/**
+ * @brief Enable the remap on PA11_PA12
+ * @param PinRemap specifies which pins have to be remapped
+ * This parameter can be any combination of the following values:
+ * @arg @ref SYSCFG_REMAP_PA11
+ * @arg @ref SYSCFG_REMAP_PA12
+ * @retval None
+ */
+void HAL_SYSCFG_EnableRemap(uint32_t PinRemap)
+{
+ /* Check the parameter */
+ assert_param(IS_HAL_REMAP_PIN(PinRemap));
+ SET_BIT(SYSCFG->CFGR1, PinRemap);
+}
+
+/**
+ * @brief Disable the remap on PA11_PA12
+ * @param PinRemap specifies which pins will behave normally
+ * This parameter can be any combination of the following values:
+ * @arg @ref SYSCFG_REMAP_PA11
+ * @arg @ref SYSCFG_REMAP_PA12
+ * @retval None
+ */
+void HAL_SYSCFG_DisableRemap(uint32_t PinRemap)
+{
+ /* Check the parameter */
+ assert_param(IS_HAL_REMAP_PIN(PinRemap));
+ CLEAR_BIT(SYSCFG->CFGR1, PinRemap);
+}
+/**
+ * @brief Set Pin Binding
+ * @param pin_binding specifies which pin will bind a specific GPIO
+ * for each die package
+ * This parameter can be any combination of HAL_BIND_xx defines
+ * @retval None
+ */
+void HAL_SYSCFG_SetPinBinding(uint32_t pin_binding)
+{
+ /* Check the parameter */
+ assert_param(IS_HAL_SYSCFG_PINBINDING(pin_binding));
+ LL_SYSCFG_ConfigPinMux(pin_binding);
+}
+
+/**
+ * @brief return Pin Binding configuration
+ * @retval PinMux configuration
+ */
+uint32_t HAL_SYSCFG_GetPinBinding(void)
+{
+ return LL_SYSCFG_GetConfigPinMux();
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c
new file mode 100644
index 0000000000..83dd09f17a
--- /dev/null
+++ b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c
@@ -0,0 +1,3004 @@
+/**
+ ******************************************************************************
+ * @file stm32c0xx_hal_adc.c
+ * @author MCD Application Team
+ * @brief This file provides firmware functions to manage the following
+ * functionalities of the Analog to Digital Converter (ADC)
+ * peripheral:
+ * + Initialization and de-initialization functions
+ * ++ Initialization and Configuration of ADC
+ * + Operation functions
+ * ++ Start, stop, get result of conversions of regular
+ * group, using 3 possible modes: polling, interruption or DMA.
+ * + Control functions
+ * ++ Channels configuration on regular group
+ * ++ Analog Watchdog configuration
+ * + State functions
+ * ++ ADC state machine management
+ * ++ Interrupts and flags management
+ * Other functions (extended functions) are available in file
+ * "stm32c0xx_hal_adc_ex.c".
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2022 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### ADC peripheral features #####
+ ==============================================================================
+ [..]
+ (+) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution.
+
+ (+) Interrupt generation at the end of regular conversion and in case of
+ analog watchdog or overrun events.
+
+ (+) Single and continuous conversion modes.
+
+ (+) Scan mode for conversion of several channels sequentially.
+
+ (+) Data alignment with in-built data coherency.
+
+ (+) Programmable sampling time (common to group of channels)
+
+ (+) External trigger (timer or EXTI) with configurable polarity
+
+ (+) DMA request generation for transfer of conversions data of regular group.
+
+ (+) ADC calibration
+
+ (+) ADC conversion of regular group.
+
+ (+) ADC supply requirements: 1.62 V to 3.6 V.
+
+ (+) ADC input range: from Vref- (connected to Vssa) to Vref+ (connected to
+ Vdda or to an external voltage reference).
+
+
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+
+ *** Configuration of top level parameters related to ADC ***
+ ============================================================
+ [..]
+
+ (#) Enable the ADC interface
+ (++) As prerequisite, ADC clock must be configured at RCC top level.
+ Caution: On STM32C0, ADC clock frequency max is 35MHz (refer
+ to device datasheet).
+ Therefore, ADC clock source from RCC and ADC clock
+ prescaler must be configured to remain below
+ this maximum frequency.
+
+ (++) Two clock settings are mandatory:
+ (+++) ADC clock (core clock, also possibly conversion clock).
+
+ (+++) ADC clock (conversions clock).
+ Four possible clock sources: synchronous clock from APB clock (same as ADC core clock)
+ or asynchronous clock from RCC level: SYSCLK, HSI48.
+
+ (+++) Example:
+ Into HAL_ADC_MspInit() (recommended code location) or with
+ other device clock parameters configuration:
+ (+++) __HAL_RCC_ADC_CLK_ENABLE(); (mandatory: core clock)
+
+ (++) ADC clock source and clock prescaler are configured at ADC level with
+ parameter "ClockPrescaler" using function HAL_ADC_Init().
+
+ (#) ADC pins configuration
+ (++) Enable the clock for the ADC GPIOs
+ using macro __HAL_RCC_GPIOx_CLK_ENABLE()
+ (++) Configure these ADC pins in analog mode
+ using function HAL_GPIO_Init()
+
+ (#) Optionally, in case of usage of ADC with interruptions:
+ (++) Configure the NVIC for ADC
+ using function HAL_NVIC_EnableIRQ(ADCx_IRQn)
+ (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler()
+ into the function of corresponding ADC interruption vector
+ ADCx_IRQHandler().
+
+ (#) Optionally, in case of usage of DMA:
+ (++) Configure the DMA (DMA channel, mode normal or circular, ...)
+ using function HAL_DMA_Init().
+ (++) Configure the NVIC for DMA
+ using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)
+ (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler()
+ into the function of corresponding DMA interruption vector
+ DMAx_Channelx_IRQHandler().
+
+ *** Configuration of ADC, group regular, channels parameters ***
+ ================================================================
+ [..]
+
+ (#) Configure the ADC parameters (resolution, data alignment, ...)
+ and regular group parameters (conversion trigger, sequencer, ...)
+ using function HAL_ADC_Init().
+
+ (#) Configure the channels for regular group parameters (channel number,
+ channel rank into sequencer, ..., into regular group)
+ using function HAL_ADC_ConfigChannel().
+
+ (#) Optionally, configure the analog watchdog parameters (channels
+ monitored, thresholds, ...)
+ using function HAL_ADC_AnalogWDGConfig().
+
+ *** Execution of ADC conversions ***
+ ====================================
+ [..]
+
+ (#) Optionally, perform an automatic ADC calibration to improve the
+ conversion accuracy
+ using function HAL_ADCEx_Calibration_Start().
+
+ (#) ADC driver can be used among three modes: polling, interruption,
+ transfer by DMA.
+
+ (++) ADC conversion by polling:
+ (+++) Activate the ADC peripheral and start conversions
+ using function HAL_ADC_Start()
+ (+++) Wait for ADC conversion completion
+ using function HAL_ADC_PollForConversion()
+ (+++) Retrieve conversion results
+ using function HAL_ADC_GetValue()
+ (+++) Stop conversion and disable the ADC peripheral
+ using function HAL_ADC_Stop()
+
+ (++) ADC conversion by interruption:
+ (+++) Activate the ADC peripheral and start conversions
+ using function HAL_ADC_Start_IT()
+ (+++) Wait for ADC conversion completion by call of function
+ HAL_ADC_ConvCpltCallback()
+ (this function must be implemented in user program)
+ (+++) Retrieve conversion results
+ using function HAL_ADC_GetValue()
+ (+++) Stop conversion and disable the ADC peripheral
+ using function HAL_ADC_Stop_IT()
+
+ (++) ADC conversion with transfer by DMA:
+ (+++) Activate the ADC peripheral and start conversions
+ using function HAL_ADC_Start_DMA()
+ (+++) Wait for ADC conversion completion by call of function
+ HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback()
+ (these functions must be implemented in user program)
+ (+++) Conversion results are automatically transferred by DMA into
+ destination variable address.
+ (+++) Stop conversion and disable the ADC peripheral
+ using function HAL_ADC_Stop_DMA()
+
+ [..]
+
+ (@) Callback functions must be implemented in user program:
+ (+@) HAL_ADC_ErrorCallback()
+ (+@) HAL_ADC_LevelOutOfWindowCallback() (callback of analog watchdog)
+ (+@) HAL_ADC_ConvCpltCallback()
+ (+@) HAL_ADC_ConvHalfCpltCallback
+
+ *** Deinitialization of ADC ***
+ ============================================================
+ [..]
+
+ (#) Disable the ADC interface
+ (++) ADC clock can be hard reset and disabled at RCC top level.
+ (++) Hard reset of ADC peripherals
+ using macro __ADCx_FORCE_RESET(), __ADCx_RELEASE_RESET().
+ (++) ADC clock disable
+ using the equivalent macro/functions as configuration step.
+ (+++) Example:
+ Into HAL_ADC_MspDeInit() (recommended code location) or with
+ other device clock parameters configuration:
+ (+++) RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSI14;
+ (+++) RCC_OscInitStructure.HSI14State = RCC_HSI14_OFF; (if not used for system clock)
+ (+++) HAL_RCC_OscConfig(&RCC_OscInitStructure);
+
+ (#) ADC pins configuration
+ (++) Disable the clock for the ADC GPIOs
+ using macro __HAL_RCC_GPIOx_CLK_DISABLE()
+
+ (#) Optionally, in case of usage of ADC with interruptions:
+ (++) Disable the NVIC for ADC
+ using function HAL_NVIC_EnableIRQ(ADCx_IRQn)
+
+ (#) Optionally, in case of usage of DMA:
+ (++) Deinitialize the DMA
+ using function HAL_DMA_Init().
+ (++) Disable the NVIC for DMA
+ using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)
+
+ [..]
+
+ *** Callback registration ***
+ =============================================
+ [..]
+
+ The compilation flag USE_HAL_ADC_REGISTER_CALLBACKS, when set to 1,
+ allows the user to configure dynamically the driver callbacks.
+ Use Functions @ref HAL_ADC_RegisterCallback()
+ to register an interrupt callback.
+ [..]
+
+ Function @ref HAL_ADC_RegisterCallback() allows to register following callbacks:
+ (+) ConvCpltCallback : ADC conversion complete callback
+ (+) ConvHalfCpltCallback : ADC conversion DMA half-transfer callback
+ (+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback
+ (+) ErrorCallback : ADC error callback
+ (+) LevelOutOfWindow2Callback : ADC analog watchdog 2 callback
+ (+) LevelOutOfWindow3Callback : ADC analog watchdog 3 callback
+ (+) EndOfSamplingCallback : ADC end of sampling callback
+ (+) MspInitCallback : ADC Msp Init callback
+ (+) MspDeInitCallback : ADC Msp DeInit callback
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+ [..]
+
+ Use function @ref HAL_ADC_UnRegisterCallback to reset a callback to the default
+ weak function.
+ [..]
+
+ @ref HAL_ADC_UnRegisterCallback takes as parameters the HAL peripheral handle,
+ and the Callback ID.
+ This function allows to reset following callbacks:
+ (+) ConvCpltCallback : ADC conversion complete callback
+ (+) ConvHalfCpltCallback : ADC conversion DMA half-transfer callback
+ (+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback
+ (+) ErrorCallback : ADC error callback
+ (+) LevelOutOfWindow2Callback : ADC analog watchdog 2 callback
+ (+) LevelOutOfWindow3Callback : ADC analog watchdog 3 callback
+ (+) EndOfSamplingCallback : ADC end of sampling callback
+ (+) MspInitCallback : ADC Msp Init callback
+ (+) MspDeInitCallback : ADC Msp DeInit callback
+ [..]
+
+ By default, after the @ref HAL_ADC_Init() and when the state is @ref HAL_ADC_STATE_RESET
+ all callbacks are set to the corresponding weak functions:
+ examples @ref HAL_ADC_ConvCpltCallback(), @ref HAL_ADC_ErrorCallback().
+ Exception done for MspInit and MspDeInit functions that are
+ reset to the legacy weak functions in the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit() only when
+ these callbacks are null (not registered beforehand).
+ [..]
+
+ If MspInit or MspDeInit are not null, the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit()
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
+ [..]
+
+ Callbacks can be registered/unregistered in @ref HAL_ADC_STATE_READY state only.
+ Exception done MspInit/MspDeInit functions that can be registered/unregistered
+ in @ref HAL_ADC_STATE_READY or @ref HAL_ADC_STATE_RESET state,
+ thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+ [..]
+
+ Then, the user first registers the MspInit/MspDeInit user callbacks
+ using @ref HAL_ADC_RegisterCallback() before calling @ref HAL_ADC_DeInit()
+ or @ref HAL_ADC_Init() function.
+ [..]
+
+ When the compilation flag USE_HAL_ADC_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registration feature is not available and all callbacks
+ are set to the corresponding weak functions.
+
+ @endverbatim
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32c0xx_hal.h"
+
+/** @addtogroup STM32C0xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup ADC ADC
+ * @brief ADC HAL module driver
+ * @{
+ */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/** @defgroup ADC_Private_Constants ADC Private Constants
+ * @{
+ */
+
+/* Fixed timeout values for ADC calibration, enable settling time, disable */
+/* settling time. */
+/* Values defined to be higher than worst cases: low clock frequency, */
+/* maximum prescaler. */
+/* Ex of profile low frequency : Clock source at 0.1 MHz, ADC clock */
+/* prescaler 4, sampling time 7.5 ADC clock cycles, resolution 12 bits. */
+/* Unit: ms */
+#define ADC_ENABLE_TIMEOUT (2UL)
+#define ADC_DISABLE_TIMEOUT (2UL)
+#define ADC_STOP_CONVERSION_TIMEOUT (2UL)
+#define ADC_CHANNEL_CONF_RDY_TIMEOUT (1UL)
+
+/* Register CHSELR bits corresponding to ranks 2 to 8 . */
+#define ADC_CHSELR_SQ2_TO_SQ8 (ADC_CHSELR_SQ2 | ADC_CHSELR_SQ3 | ADC_CHSELR_SQ4 | \
+ ADC_CHSELR_SQ5 | ADC_CHSELR_SQ6 | ADC_CHSELR_SQ7 | ADC_CHSELR_SQ8)
+
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup ADC_Private_Functions ADC Private Functions
+ * @{
+ */
+static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma);
+static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma);
+static void ADC_DMAError(DMA_HandleTypeDef *hdma);
+/**
+ * @}
+ */
+
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup ADC_Exported_Functions ADC Exported Functions
+ * @{
+ */
+
+/** @defgroup ADC_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief ADC Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Initialize and configure the ADC.
+ (+) De-initialize the ADC.
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initialize the ADC peripheral and regular group according to
+ * parameters specified in structure "ADC_InitTypeDef".
+ * @note As prerequisite, ADC clock must be configured at RCC top level
+ * (refer to description of RCC configuration for ADC
+ * in header of this file).
+ * @note Possibility to update parameters on the fly:
+ * This function initializes the ADC MSP (HAL_ADC_MspInit()) only when
+ * coming from ADC state reset. Following calls to this function can
+ * be used to reconfigure some parameters of ADC_InitTypeDef
+ * structure on the fly, without modifying MSP configuration. If ADC
+ * MSP has to be modified again, HAL_ADC_DeInit() must be called
+ * before HAL_ADC_Init().
+ * The setting of these parameters is conditioned to ADC state.
+ * For parameters constraints, see comments of structure
+ * "ADC_InitTypeDef".
+ * @note This function configures the ADC within 2 scopes: scope of entire
+ * ADC and scope of regular group. For parameters details, see comments
+ * of structure "ADC_InitTypeDef".
+ * @param hadc ADC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+ uint32_t tmpCFGR1 = 0UL;
+ uint32_t tmpCFGR2 = 0UL;
+ uint32_t tmp_adc_reg_is_conversion_on_going;
+ __IO uint32_t wait_loop_index = 0UL;
+
+ /* Check ADC handle */
+ if (hadc == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler));
+ assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution));
+ assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign));
+ assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode));
+ assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
+ assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
+ assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv));
+ assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));
+ assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
+ assert_param(IS_ADC_OVERRUN(hadc->Init.Overrun));
+ assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoWait));
+ assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoPowerOff));
+ assert_param(IS_ADC_SAMPLE_TIME(hadc->Init.SamplingTimeCommon1));
+ assert_param(IS_ADC_SAMPLE_TIME(hadc->Init.SamplingTimeCommon2));
+ assert_param(IS_FUNCTIONAL_STATE(hadc->Init.OversamplingMode));
+
+ assert_param(IS_ADC_TRIGGER_FREQ(hadc->Init.TriggerFrequencyMode));
+
+ if (hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
+ {
+ assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode));
+
+ if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE)
+ {
+ assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion));
+ }
+ }
+
+ /* ADC group regular discontinuous mode can be enabled only if */
+ /* continuous mode is disabled. */
+ assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (hadc->Init.ContinuousConvMode == ENABLE)));
+
+ /* Actions performed only if ADC is coming from state reset: */
+ /* - Initialization of ADC MSP */
+ if (hadc->State == HAL_ADC_STATE_RESET)
+ {
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+ /* Init the ADC Callback settings */
+ hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback; /* Legacy weak callback */
+ hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback; /* Legacy weak callback */
+ hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback; /* Legacy weak callback */
+ hadc->ErrorCallback = HAL_ADC_ErrorCallback; /* Legacy weak callback */
+ hadc->LevelOutOfWindow2Callback = HAL_ADCEx_LevelOutOfWindow2Callback; /* Legacy weak callback */
+ hadc->LevelOutOfWindow3Callback = HAL_ADCEx_LevelOutOfWindow3Callback; /* Legacy weak callback */
+ hadc->EndOfSamplingCallback = HAL_ADCEx_EndOfSamplingCallback; /* Legacy weak callback */
+
+ if (hadc->MspInitCallback == NULL)
+ {
+ hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */
+ }
+
+ /* Init the low level hardware */
+ hadc->MspInitCallback(hadc);
+#else
+ /* Init the low level hardware */
+ HAL_ADC_MspInit(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
+ /* Set ADC error code to none */
+ ADC_CLEAR_ERRORCODE(hadc);
+
+ /* Initialize Lock */
+ hadc->Lock = HAL_UNLOCKED;
+ }
+
+ if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL)
+ {
+ /* Enable ADC internal voltage regulator */
+ LL_ADC_EnableInternalRegulator(hadc->Instance);
+
+ /* Delay for ADC stabilization time */
+ /* Wait loop initialization and execution */
+ /* Note: Variable divided by 2 to compensate partially */
+ /* CPU processing cycles, scaling in us split to not */
+ /* exceed 32 bits register capacity and handle low frequency. */
+ wait_loop_index = ((LL_ADC_DELAY_INTERNAL_REGUL_STAB_US / 10UL) * (SystemCoreClock / (100000UL * 2UL)));
+ while (wait_loop_index != 0UL)
+ {
+ wait_loop_index--;
+ }
+ }
+
+ /* Verification that ADC voltage regulator is correctly enabled, whether */
+ /* or not ADC is coming from state reset (if any potential problem of */
+ /* clocking, voltage regulator would not be enabled). */
+ if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL)
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+ /* Set ADC error code to ADC peripheral internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+
+ tmp_hal_status = HAL_ERROR;
+ }
+
+ /* Configuration of ADC parameters if previous preliminary actions are */
+ /* correctly completed and if there is no conversion on going on regular */
+ /* group (ADC may already be enabled at this point if HAL_ADC_Init() is */
+ /* called to update a parameter on the fly). */
+ tmp_adc_reg_is_conversion_on_going = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
+
+ if (((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
+ && (tmp_adc_reg_is_conversion_on_going == 0UL)
+ )
+ {
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY,
+ HAL_ADC_STATE_BUSY_INTERNAL);
+
+ /* Configuration of common ADC parameters */
+
+ /* Parameters update conditioned to ADC state: */
+ /* Parameters that can be updated only when ADC is disabled: */
+ /* - Internal voltage regulator (no parameter in HAL ADC init structure) */
+ /* - Clock configuration */
+ /* - ADC resolution */
+ /* - Oversampling */
+ /* - discontinuous mode */
+ /* - LowPowerAutoWait mode */
+ /* - LowPowerAutoPowerOff mode */
+ /* - continuous conversion mode */
+ /* - overrun */
+ /* - external trigger to start conversion */
+ /* - external trigger polarity */
+ /* - data alignment */
+ /* - resolution */
+ /* - scan direction */
+ /* - DMA continuous request */
+ /* - Trigger frequency mode */
+ /* Note: If low power mode AutoPowerOff is enabled, ADC enable */
+ /* and disable phases are performed automatically by hardware */
+ /* (in this case, flag ADC_FLAG_RDY is not set). */
+ if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
+ {
+ /* Some parameters of this register are not reset, since they are set */
+ /* by other functions and must be kept in case of usage of this */
+ /* function on the fly (update of a parameter of ADC_InitTypeDef */
+ /* without needing to reconfigure all other ADC groups/channels */
+ /* parameters): */
+ /* - internal measurement paths: temperature sensor, Vref */
+ /* (set into HAL_ADC_ConfigChannel() ) */
+
+ tmpCFGR1 |= (hadc->Init.Resolution |
+ ADC_CFGR1_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) |
+ ADC_CFGR1_AUTOOFF((uint32_t)hadc->Init.LowPowerAutoPowerOff) |
+ ADC_CFGR1_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) |
+ ADC_CFGR1_OVERRUN(hadc->Init.Overrun) |
+ hadc->Init.DataAlign |
+ ADC_SCAN_SEQ_MODE(hadc->Init.ScanConvMode) |
+ ADC_CFGR1_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests));
+
+ /* Update setting of discontinuous mode only if continuous mode is disabled */
+ if (hadc->Init.DiscontinuousConvMode == ENABLE)
+ {
+ if (hadc->Init.ContinuousConvMode == DISABLE)
+ {
+ /* Enable the selected ADC group regular discontinuous mode */
+ tmpCFGR1 |= ADC_CFGR1_DISCEN;
+ }
+ else
+ {
+ /* ADC regular group discontinuous was intended to be enabled, */
+ /* but ADC regular group modes continuous and sequencer discontinuous */
+ /* cannot be enabled simultaneously. */
+
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+ /* Set ADC error code to ADC peripheral internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+ }
+ }
+
+ /* Enable external trigger if trigger selection is different of software */
+ /* start. */
+ /* Note: This configuration keeps the hardware feature of parameter */
+ /* ExternalTrigConvEdge "trigger edge none" equivalent to */
+ /* software start. */
+ if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
+ {
+ tmpCFGR1 |= ((hadc->Init.ExternalTrigConv & ADC_CFGR1_EXTSEL) |
+ hadc->Init.ExternalTrigConvEdge);
+ }
+
+ /* Update ADC configuration register with previous settings */
+ MODIFY_REG(hadc->Instance->CFGR1,
+ ADC_CFGR1_RES |
+ ADC_CFGR1_DISCEN |
+ ADC_CFGR1_AUTOFF |
+ ADC_CFGR1_WAIT |
+ ADC_CFGR1_CONT |
+ ADC_CFGR1_OVRMOD |
+ ADC_CFGR1_EXTSEL |
+ ADC_CFGR1_EXTEN |
+ ADC_CFGR1_ALIGN |
+ ADC_CFGR1_SCANDIR |
+ ADC_CFGR1_DMACFG,
+ tmpCFGR1);
+
+ tmpCFGR2 |= ((hadc->Init.ClockPrescaler & ADC_CFGR2_CKMODE) |
+ hadc->Init.TriggerFrequencyMode
+ );
+
+ if (hadc->Init.OversamplingMode == ENABLE)
+ {
+ tmpCFGR2 |= (ADC_CFGR2_OVSE |
+ (hadc->Init.ClockPrescaler & ADC_CFGR2_CKMODE) |
+ hadc->Init.Oversampling.Ratio |
+ hadc->Init.Oversampling.RightBitShift |
+ hadc->Init.Oversampling.TriggeredMode
+ );
+ }
+
+ MODIFY_REG(hadc->Instance->CFGR2,
+ ADC_CFGR2_CKMODE |
+ ADC_CFGR2_LFTRIG |
+ ADC_CFGR2_OVSE |
+ ADC_CFGR2_OVSR |
+ ADC_CFGR2_OVSS |
+ ADC_CFGR2_TOVS,
+ tmpCFGR2);
+
+ /* Configuration of ADC clock mode: asynchronous clock source */
+ /* with selectable prescaler. */
+ if (((hadc->Init.ClockPrescaler) != ADC_CLOCK_SYNC_PCLK_DIV1) &&
+ ((hadc->Init.ClockPrescaler) != ADC_CLOCK_SYNC_PCLK_DIV2) &&
+ ((hadc->Init.ClockPrescaler) != ADC_CLOCK_SYNC_PCLK_DIV4))
+ {
+ MODIFY_REG(ADC1_COMMON->CCR,
+ ADC_CCR_PRESC,
+ hadc->Init.ClockPrescaler & ADC_CCR_PRESC);
+ }
+ }
+
+ /* Channel sampling time configuration */
+ LL_ADC_SetSamplingTimeCommonChannels(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_1, hadc->Init.SamplingTimeCommon1);
+ LL_ADC_SetSamplingTimeCommonChannels(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_2, hadc->Init.SamplingTimeCommon2);
+
+ /* Configuration of regular group sequencer: */
+ /* - if scan mode is disabled, regular channels sequence length is set to */
+ /* 0x00: 1 channel converted (channel on regular rank 1) */
+ /* Parameter "NbrOfConversion" is discarded. */
+ /* Note: Scan mode is not present by hardware on this device, but */
+ /* emulated by software for alignment over all STM32 devices. */
+ /* - if scan mode is enabled, regular channels sequence length is set to */
+ /* parameter "NbrOfConversion". */
+ /* Channels must be configured into each rank using function */
+ /* "HAL_ADC_ConfigChannel()". */
+ if (hadc->Init.ScanConvMode == ADC_SCAN_DISABLE)
+ {
+ /* Set sequencer scan length by clearing ranks above rank 1 */
+ /* and do not modify rank 1 value. */
+ SET_BIT(hadc->Instance->CHSELR,
+ ADC_CHSELR_SQ2_TO_SQ8);
+ }
+ else if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE)
+ {
+ /* Count number of ranks available in HAL ADC handle variable */
+ uint32_t ADCGroupRegularSequencerRanksCount;
+
+ /* Parse all ranks from 1 to 8 */
+ for (ADCGroupRegularSequencerRanksCount = 0UL; ADCGroupRegularSequencerRanksCount < (8UL); ADCGroupRegularSequencerRanksCount++)
+ {
+ /* Check each sequencer rank until value of end of sequence */
+ if (((hadc->ADCGroupRegularSequencerRanks >> (ADCGroupRegularSequencerRanksCount * 4UL)) & ADC_CHSELR_SQ1) ==
+ ADC_CHSELR_SQ1)
+ {
+ break;
+ }
+ }
+
+ if (ADCGroupRegularSequencerRanksCount == 1UL)
+ {
+ /* Set ADC group regular sequencer: */
+ /* Set sequencer scan length by clearing ranks above rank 1 */
+ /* and do not modify rank 1 value. */
+ SET_BIT(hadc->Instance->CHSELR,
+ ADC_CHSELR_SQ2_TO_SQ8);
+ }
+ else
+ {
+ /* Set ADC group regular sequencer: */
+ /* - Set ADC group regular sequencer to value memorized */
+ /* in HAL ADC handle */
+ /* Note: This value maybe be initialized at a unknown value, */
+ /* therefore after the first call of "HAL_ADC_Init()", */
+ /* each rank corresponding to parameter "NbrOfConversion" */
+ /* must be set using "HAL_ADC_ConfigChannel()". */
+ /* - Set sequencer scan length by clearing ranks above maximum rank */
+ /* and do not modify other ranks value. */
+ MODIFY_REG(hadc->Instance->CHSELR,
+ ADC_CHSELR_SQ_ALL,
+ (ADC_CHSELR_SQ2_TO_SQ8 << (((hadc->Init.NbrOfConversion - 1UL) * ADC_REGULAR_RANK_2) & 0x1FUL)) | (hadc->ADCGroupRegularSequencerRanks)
+ );
+ }
+ }
+
+ /* Check back that ADC registers have effectively been configured to */
+ /* ensure of no potential problem of ADC core peripheral clocking. */
+ if (LL_ADC_GetSamplingTimeCommonChannels(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_1)
+ == hadc->Init.SamplingTimeCommon1)
+ {
+ /* Set ADC error code to none */
+ ADC_CLEAR_ERRORCODE(hadc);
+
+ /* Set the ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_BUSY_INTERNAL,
+ HAL_ADC_STATE_READY);
+ }
+ else
+ {
+ /* Update ADC state machine to error */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_BUSY_INTERNAL,
+ HAL_ADC_STATE_ERROR_INTERNAL);
+
+ /* Set ADC error code to ADC peripheral internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+
+ tmp_hal_status = HAL_ERROR;
+ }
+
+ }
+ else
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+ tmp_hal_status = HAL_ERROR;
+ }
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+
+/**
+ * @brief Deinitialize the ADC peripheral registers to their default reset
+ * values, with deinitialization of the ADC MSP.
+ * @note For devices with several ADCs: reset of ADC common registers is done
+ * only if all ADCs sharing the same common group are disabled.
+ * (function "HAL_ADC_MspDeInit()" is also called under the same conditions:
+ * all ADC instances use the same core clock at RCC level, disabling
+ * the core clock reset all ADC instances).
+ * If this is not the case, reset of these common parameters reset is
+ * bypassed without error reporting: it can be the intended behavior in
+ * case of reset of a single ADC while the other ADCs sharing the same
+ * common group is still running.
+ * @note By default, HAL_ADC_DeInit() set ADC in mode deep power-down:
+ * this saves more power by reducing leakage currents
+ * and is particularly interesting before entering MCU low-power modes.
+ * @param hadc ADC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status;
+
+ /* Check ADC handle */
+ if (hadc == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL);
+
+ /* Stop potential conversion on going, on regular group */
+ tmp_hal_status = ADC_ConversionStop(hadc);
+
+ /* Disable ADC peripheral if conversions are effectively stopped */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Disable the ADC peripheral */
+ tmp_hal_status = ADC_Disable(hadc);
+
+ /* Check if ADC is effectively disabled */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Change ADC state */
+ hadc->State = HAL_ADC_STATE_READY;
+ }
+
+ /* Disable ADC internal voltage regulator */
+ LL_ADC_DisableInternalRegulator(hadc->Instance);
+ }
+
+ /* Note: HAL ADC deInit is done independently of ADC conversion stop */
+ /* and disable return status. In case of status fail, attempt to */
+ /* perform deinitialization anyway and it is up user code in */
+ /* in HAL_ADC_MspDeInit() to reset the ADC peripheral using */
+ /* system RCC hard reset. */
+
+ /* ========== Reset ADC registers ========== */
+
+ /* Reset register IER */
+ __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_AWD3 | ADC_IT_AWD2 |
+ ADC_IT_AWD1 | ADC_IT_OVR |
+ ADC_IT_EOS | ADC_IT_EOC |
+ ADC_IT_EOSMP | ADC_IT_RDY));
+
+ /* Reset register ISR */
+ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD3 | ADC_FLAG_AWD2 |
+ ADC_FLAG_AWD1 | ADC_FLAG_OVR |
+ ADC_FLAG_EOS | ADC_FLAG_EOC |
+ ADC_FLAG_EOSMP | ADC_FLAG_RDY));
+
+ /* Reset register CR */
+ /* Bits ADC_CR_ADCAL, ADC_CR_ADSTP, ADC_CR_ADSTART are in access mode */
+ /* "read-set": no direct reset applicable. */
+
+ /* Reset register CFGR1 */
+ hadc->Instance->CFGR1 &= ~(ADC_CFGR1_AWD1CH | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL | ADC_CFGR1_DISCEN |
+ ADC_CFGR1_AUTOFF | ADC_CFGR1_WAIT | ADC_CFGR1_CONT | ADC_CFGR1_OVRMOD |
+ ADC_CFGR1_EXTEN | ADC_CFGR1_EXTSEL | ADC_CFGR1_ALIGN | ADC_CFGR1_RES |
+ ADC_CFGR1_SCANDIR | ADC_CFGR1_DMACFG | ADC_CFGR1_DMAEN);
+
+ /* Reset register CFGR2 */
+ /* Note: Update of ADC clock mode is conditioned to ADC state disabled: */
+ /* already done above. */
+ hadc->Instance->CFGR2 &= ~ADC_CFGR2_CKMODE;
+
+ /* Reset register SMPR */
+ hadc->Instance->SMPR &= ~ADC_SMPR_SMP1;
+
+ /* Reset register TR1 */
+ hadc->Instance->TR1 &= ~(ADC_TR1_HT1 | ADC_TR1_LT1);
+
+ /* Reset register CHSELR */
+ hadc->Instance->CHSELR &= ~(ADC_CHSELR_SQ_ALL);
+
+ /* Reset register DR */
+ /* bits in access mode read only, no direct reset applicable */
+
+ /* Reset register CCR */
+ ADC1_COMMON->CCR &= ~(ADC_CCR_TSEN | ADC_CCR_VREFEN | ADC_CCR_PRESC);
+
+ /* ========== Hard reset ADC peripheral ========== */
+ /* Performs a global reset of the entire ADC peripheral: ADC state is */
+ /* forced to a similar state after device power-on. */
+ /* If needed, copy-paste and uncomment the following reset code into */
+ /* function "void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc)": */
+ /* */
+ /* __HAL_RCC_ADC1_FORCE_RESET() */
+ /* __HAL_RCC_ADC1_RELEASE_RESET() */
+
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+ if (hadc->MspDeInitCallback == NULL)
+ {
+ hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */
+ }
+
+ /* DeInit the low level hardware */
+ hadc->MspDeInitCallback(hadc);
+#else
+ /* DeInit the low level hardware */
+ HAL_ADC_MspDeInit(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
+ /* Reset HAL ADC handle variable */
+ hadc->ADCGroupRegularSequencerRanks = 0x00000000UL;
+
+ /* Set ADC error code to none */
+ ADC_CLEAR_ERRORCODE(hadc);
+
+ /* Set ADC state */
+ hadc->State = HAL_ADC_STATE_RESET;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+
+/**
+ * @brief Initialize the ADC MSP.
+ * @param hadc ADC handle
+ * @retval None
+ */
+__weak void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hadc);
+
+ /* NOTE : This function should not be modified. When the callback is needed,
+ function HAL_ADC_MspInit must be implemented in the user file.
+ */
+}
+
+/**
+ * @brief DeInitialize the ADC MSP.
+ * @param hadc ADC handle
+ * @note All ADC instances use the same core clock at RCC level, disabling
+ * the core clock reset all ADC instances).
+ * @retval None
+ */
+__weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hadc);
+
+ /* NOTE : This function should not be modified. When the callback is needed,
+ function HAL_ADC_MspDeInit must be implemented in the user file.
+ */
+}
+
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a User ADC Callback
+ * To be used instead of the weak predefined callback
+ * @param hadc Pointer to a ADC_HandleTypeDef structure that contains
+ * the configuration information for the specified ADC.
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion complete callback ID
+ * @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion DMA half-transfer callback ID
+ * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog 1 callback ID
+ * @arg @ref HAL_ADC_ERROR_CB_ID ADC error callback ID
+ * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID ADC analog watchdog 2 callback ID
+ * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID ADC analog watchdog 3 callback ID
+ * @arg @ref HAL_ADC_END_OF_SAMPLING_CB_ID ADC end of sampling callback ID
+ * @arg @ref HAL_ADC_MSPINIT_CB_ID ADC Msp Init callback ID
+ * @arg @ref HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit callback ID
+ * @arg @ref HAL_ADC_MSPINIT_CB_ID MspInit callback ID
+ * @arg @ref HAL_ADC_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @param pCallback pointer to the Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID,
+ pADC_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+
+ if ((hadc->State & HAL_ADC_STATE_READY) != 0UL)
+ {
+ switch (CallbackID)
+ {
+ case HAL_ADC_CONVERSION_COMPLETE_CB_ID :
+ hadc->ConvCpltCallback = pCallback;
+ break;
+
+ case HAL_ADC_CONVERSION_HALF_CB_ID :
+ hadc->ConvHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID :
+ hadc->LevelOutOfWindowCallback = pCallback;
+ break;
+
+ case HAL_ADC_ERROR_CB_ID :
+ hadc->ErrorCallback = pCallback;
+ break;
+
+ case HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID :
+ hadc->LevelOutOfWindow2Callback = pCallback;
+ break;
+
+ case HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID :
+ hadc->LevelOutOfWindow3Callback = pCallback;
+ break;
+
+ case HAL_ADC_END_OF_SAMPLING_CB_ID :
+ hadc->EndOfSamplingCallback = pCallback;
+ break;
+
+ case HAL_ADC_MSPINIT_CB_ID :
+ hadc->MspInitCallback = pCallback;
+ break;
+
+ case HAL_ADC_MSPDEINIT_CB_ID :
+ hadc->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_ADC_STATE_RESET == hadc->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_ADC_MSPINIT_CB_ID :
+ hadc->MspInitCallback = pCallback;
+ break;
+
+ case HAL_ADC_MSPDEINIT_CB_ID :
+ hadc->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Unregister a ADC Callback
+ * ADC callback is redirected to the weak predefined callback
+ * @param hadc Pointer to a ADC_HandleTypeDef structure that contains
+ * the configuration information for the specified ADC.
+ * @param CallbackID ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion complete callback ID
+ * @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion DMA half-transfer callback ID
+ * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog 1 callback ID
+ * @arg @ref HAL_ADC_ERROR_CB_ID ADC error callback ID
+ * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID ADC analog watchdog 2 callback ID
+ * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID ADC analog watchdog 3 callback ID
+ * @arg @ref HAL_ADC_END_OF_SAMPLING_CB_ID ADC end of sampling callback ID
+ * @arg @ref HAL_ADC_MSPINIT_CB_ID ADC Msp Init callback ID
+ * @arg @ref HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit callback ID
+ * @arg @ref HAL_ADC_MSPINIT_CB_ID MspInit callback ID
+ * @arg @ref HAL_ADC_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if ((hadc->State & HAL_ADC_STATE_READY) != 0)
+ {
+ switch (CallbackID)
+ {
+ case HAL_ADC_CONVERSION_COMPLETE_CB_ID :
+ hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback;
+ break;
+
+ case HAL_ADC_CONVERSION_HALF_CB_ID :
+ hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback;
+ break;
+
+ case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID :
+ hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback;
+ break;
+
+ case HAL_ADC_ERROR_CB_ID :
+ hadc->ErrorCallback = HAL_ADC_ErrorCallback;
+ break;
+
+ case HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID :
+ hadc->LevelOutOfWindow2Callback = HAL_ADCEx_LevelOutOfWindow2Callback;
+ break;
+
+ case HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID :
+ hadc->LevelOutOfWindow3Callback = HAL_ADCEx_LevelOutOfWindow3Callback;
+ break;
+
+ case HAL_ADC_END_OF_SAMPLING_CB_ID :
+ hadc->EndOfSamplingCallback = HAL_ADCEx_EndOfSamplingCallback;
+ break;
+
+ case HAL_ADC_MSPINIT_CB_ID :
+ hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */
+ break;
+
+ case HAL_ADC_MSPDEINIT_CB_ID :
+ hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */
+ break;
+
+ default :
+ /* Update the error code */
+ hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_ADC_STATE_RESET == hadc->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_ADC_MSPINIT_CB_ID :
+ hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */
+ break;
+
+ case HAL_ADC_MSPDEINIT_CB_ID :
+ hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */
+ break;
+
+ default :
+ /* Update the error code */
+ hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ return status;
+}
+
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Exported_Functions_Group2 ADC Input and Output operation functions
+ * @brief ADC IO operation functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Start conversion of regular group.
+ (+) Stop conversion of regular group.
+ (+) Poll for conversion complete on regular group.
+ (+) Poll for conversion event.
+ (+) Get result of regular channel conversion.
+ (+) Start conversion of regular group and enable interruptions.
+ (+) Stop conversion of regular group and disable interruptions.
+ (+) Handle ADC interrupt request
+ (+) Start conversion of regular group and enable DMA transfer.
+ (+) Stop conversion of regular group and disable ADC DMA transfer.
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enable ADC, start conversion of regular group.
+ * @note Interruptions enabled in this function: None.
+ * @param hadc ADC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Perform ADC enable and conversion start if no conversion is on going */
+ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
+ {
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Enable the ADC peripheral */
+ tmp_hal_status = ADC_Enable(hadc);
+
+ /* Start conversion if ADC is effectively enabled */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Set ADC state */
+ /* - Clear state bitfield related to regular group conversion results */
+ /* - Set state bitfield related to regular operation */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
+ HAL_ADC_STATE_REG_BUSY);
+
+ /* Set ADC error code */
+ /* Reset all ADC error code fields */
+ ADC_CLEAR_ERRORCODE(hadc);
+
+ /* Clear ADC group regular conversion flag and overrun flag */
+ /* (To ensure of no unknown state from potential previous ADC operations) */
+ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
+
+ /* Process unlocked */
+ /* Unlock before starting ADC conversions: in case of potential */
+ /* interruption, to let the process to ADC IRQ Handler. */
+ __HAL_UNLOCK(hadc);
+
+ /* Enable conversion of regular group. */
+ /* If software start has been selected, conversion starts immediately. */
+ /* If external trigger has been selected, conversion will start at next */
+ /* trigger event. */
+ /* Start ADC group regular conversion */
+ LL_ADC_REG_StartConversion(hadc->Instance);
+ }
+ else
+ {
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+ }
+ }
+ else
+ {
+ tmp_hal_status = HAL_BUSY;
+ }
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+
+/**
+ * @brief Stop ADC conversion of regular group (and injected channels in
+ * case of auto_injection mode), disable ADC peripheral.
+ * @note: ADC peripheral disable is forcing stop of potential
+ * conversion on injected group. If injected group is under use, it
+ * should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
+ * @param hadc ADC handle
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* 1. Stop potential conversion on going, on ADC group regular */
+ tmp_hal_status = ADC_ConversionStop(hadc);
+
+ /* Disable ADC peripheral if conversions are effectively stopped */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* 2. Disable the ADC peripheral */
+ tmp_hal_status = ADC_Disable(hadc);
+
+ /* Check if ADC is effectively disabled */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY,
+ HAL_ADC_STATE_READY);
+ }
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+
+/**
+ * @brief Wait for regular group conversion to be completed.
+ * @note ADC conversion flags EOS (end of sequence) and EOC (end of
+ * conversion) are cleared by this function, with an exception:
+ * if low power feature "LowPowerAutoWait" is enabled, flags are
+ * not cleared to not interfere with this feature until data register
+ * is read using function HAL_ADC_GetValue().
+ * @note This function cannot be used in a particular setup: ADC configured
+ * in DMA mode and polling for end of each conversion (ADC init
+ * parameter "EOCSelection" set to ADC_EOC_SINGLE_CONV).
+ * In this case, DMA resets the flag EOC and polling cannot be
+ * performed on each conversion. Nevertheless, polling can still
+ * be performed on the complete sequence (ADC init
+ * parameter "EOCSelection" set to ADC_EOC_SEQ_CONV).
+ * @param hadc ADC handle
+ * @param Timeout Timeout value in millisecond.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout)
+{
+ uint32_t tickstart;
+ uint32_t tmp_Flag_End;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* If end of conversion selected to end of sequence conversions */
+ if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV)
+ {
+ tmp_Flag_End = ADC_FLAG_EOS;
+ }
+ /* If end of conversion selected to end of unitary conversion */
+ else /* ADC_EOC_SINGLE_CONV */
+ {
+ /* Verification that ADC configuration is compliant with polling for */
+ /* each conversion: */
+ /* Particular case is ADC configured in DMA mode and ADC sequencer with */
+ /* several ranks and polling for end of each conversion. */
+ /* For code simplicity sake, this particular case is generalized to */
+ /* ADC configured in DMA mode and and polling for end of each conversion. */
+ if ((hadc->Instance->CFGR1 & ADC_CFGR1_DMAEN) != 0UL)
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+ return HAL_ERROR;
+ }
+ else
+ {
+ tmp_Flag_End = (ADC_FLAG_EOC);
+ }
+ }
+
+ /* Get tick count */
+ tickstart = HAL_GetTick();
+
+ /* Wait until End of unitary conversion or sequence conversions flag is raised */
+ while ((hadc->Instance->ISR & tmp_Flag_End) == 0UL)
+ {
+ /* Check if timeout is disabled (set to infinite wait) */
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL))
+ {
+ /* Update ADC state machine to timeout */
+ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Update ADC state machine */
+ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
+
+ /* Determine whether any further conversion upcoming on group regular */
+ /* by external trigger, continuous mode or scan sequence on going. */
+ if ((LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL)
+ && (hadc->Init.ContinuousConvMode == DISABLE)
+ )
+ {
+ /* Check whether end of sequence is reached */
+ if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS))
+ {
+ /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */
+ /* ADSTART==0 (no conversion on going) */
+ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
+ {
+ /* Disable ADC end of single conversion interrupt on group regular */
+ /* Note: Overrun interrupt was enabled with EOC interrupt in */
+ /* HAL_Start_IT(), but is not disabled here because can be used */
+ /* by overrun IRQ process below. */
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS);
+
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY,
+ HAL_ADC_STATE_READY);
+ }
+ else
+ {
+ /* Change ADC state to error state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+ /* Set ADC error code to ADC peripheral internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+ }
+ }
+ }
+
+ /* Clear end of conversion flag of regular group if low power feature */
+ /* "LowPowerAutoWait " is disabled, to not interfere with this feature */
+ /* until data register is read using function HAL_ADC_GetValue(). */
+ if (hadc->Init.LowPowerAutoWait == DISABLE)
+ {
+ /* Clear regular group conversion flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS));
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Poll for ADC event.
+ * @param hadc ADC handle
+ * @param EventType the ADC event type.
+ * This parameter can be one of the following values:
+ * @arg @ref ADC_EOSMP_EVENT ADC End of Sampling event
+ * @arg @ref ADC_AWD1_EVENT ADC Analog watchdog 1 event (main analog watchdog, present on all STM32 devices)
+ * @arg @ref ADC_AWD2_EVENT ADC Analog watchdog 2 event (additional analog watchdog, not present on all STM32 families)
+ * @arg @ref ADC_AWD3_EVENT ADC Analog watchdog 3 event (additional analog watchdog, not present on all STM32 families)
+ * @arg @ref ADC_OVR_EVENT ADC Overrun event
+ * @param Timeout Timeout value in millisecond.
+ * @note The relevant flag is cleared if found to be set, except for ADC_FLAG_OVR.
+ * Indeed, the latter is reset only if hadc->Init.Overrun field is set
+ * to ADC_OVR_DATA_OVERWRITTEN. Otherwise, data register may be potentially overwritten
+ * by a new converted data as soon as OVR is cleared.
+ * To reset OVR flag once the preserved data is retrieved, the user can resort
+ * to macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout)
+{
+ uint32_t tickstart;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ assert_param(IS_ADC_EVENT_TYPE(EventType));
+
+ /* Get tick count */
+ tickstart = HAL_GetTick();
+
+ /* Check selected event flag */
+ while (__HAL_ADC_GET_FLAG(hadc, EventType) == 0UL)
+ {
+ /* Check if timeout is disabled (set to infinite wait) */
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL))
+ {
+ /* Update ADC state machine to timeout */
+ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ switch (EventType)
+ {
+ /* End Of Sampling event */
+ case ADC_EOSMP_EVENT:
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOSMP);
+
+ /* Clear the End Of Sampling flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP);
+
+ break;
+
+ /* Analog watchdog (level out of window) event */
+ /* Note: In case of several analog watchdog enabled, if needed to know */
+ /* which one triggered and on which ADCx, test ADC state of analog watchdog */
+ /* flags HAL_ADC_STATE_AWD1/2/3 using function "HAL_ADC_GetState()". */
+ /* For example: */
+ /* " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) " */
+ /* " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD2) != 0UL) " */
+ /* " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD3) != 0UL) " */
+
+ /* Check analog watchdog 1 flag */
+ case ADC_AWD_EVENT:
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
+
+ /* Clear ADC analog watchdog flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1);
+
+ break;
+
+ /* Check analog watchdog 2 flag */
+ case ADC_AWD2_EVENT:
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_AWD2);
+
+ /* Clear ADC analog watchdog flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2);
+
+ break;
+
+ /* Check analog watchdog 3 flag */
+ case ADC_AWD3_EVENT:
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_AWD3);
+
+ /* Clear ADC analog watchdog flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3);
+
+ break;
+
+ /* Overrun event */
+ default: /* Case ADC_OVR_EVENT */
+ /* If overrun is set to overwrite previous data, overrun event is not */
+ /* considered as an error. */
+ /* (cf ref manual "Managing conversions without using the DMA and without */
+ /* overrun ") */
+ if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
+ {
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
+
+ /* Set ADC error code to overrun */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
+ }
+ else
+ {
+ /* Clear ADC Overrun flag only if Overrun is set to ADC_OVR_DATA_OVERWRITTEN
+ otherwise, data register is potentially overwritten by new converted data as soon
+ as OVR is cleared. */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
+ }
+ break;
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Enable ADC, start conversion of regular group with interruption.
+ * @note Interruptions enabled in this function according to initialization
+ * setting : EOC (end of conversion), EOS (end of sequence),
+ * OVR overrun.
+ * Each of these interruptions has its dedicated callback function.
+ * @note To guarantee a proper reset of all interruptions once all the needed
+ * conversions are obtained, HAL_ADC_Stop_IT() must be called to ensure
+ * a correct stop of the IT-based conversions.
+ * @note By default, HAL_ADC_Start_IT() does not enable the End Of Sampling
+ * interruption. If required (e.g. in case of oversampling with trigger
+ * mode), the user must:
+ * 1. first clear the EOSMP flag if set with macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP)
+ * 2. then enable the EOSMP interrupt with macro __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOSMP)
+ * before calling HAL_ADC_Start_IT().
+ * @param hadc ADC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Perform ADC enable and conversion start if no conversion is on going */
+ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
+ {
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Enable the ADC peripheral */
+ tmp_hal_status = ADC_Enable(hadc);
+
+ /* Start conversion if ADC is effectively enabled */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Set ADC state */
+ /* - Clear state bitfield related to regular group conversion results */
+ /* - Set state bitfield related to regular operation */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
+ HAL_ADC_STATE_REG_BUSY);
+
+
+ /* Set ADC error code */
+ /* Reset all ADC error code fields */
+ ADC_CLEAR_ERRORCODE(hadc);
+
+ /* Clear ADC group regular conversion flag and overrun flag */
+ /* (To ensure of no unknown state from potential previous ADC operations) */
+ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
+
+ /* Process unlocked */
+ /* Unlock before starting ADC conversions: in case of potential */
+ /* interruption, to let the process to ADC IRQ Handler. */
+ __HAL_UNLOCK(hadc);
+
+ /* Disable all interruptions before enabling the desired ones */
+ __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
+
+ /* Enable ADC end of conversion interrupt */
+ switch (hadc->Init.EOCSelection)
+ {
+ case ADC_EOC_SEQ_CONV:
+ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOS);
+ break;
+ /* case ADC_EOC_SINGLE_CONV */
+ default:
+ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOC);
+ break;
+ }
+
+ /* Enable ADC overrun interrupt */
+ /* If hadc->Init.Overrun is set to ADC_OVR_DATA_PRESERVED, only then is
+ ADC_IT_OVR enabled; otherwise data overwrite is considered as normal
+ behavior and no CPU time is lost for a non-processed interruption */
+ if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
+ {
+ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
+ }
+
+ /* Enable conversion of regular group. */
+ /* If software start has been selected, conversion starts immediately. */
+ /* If external trigger has been selected, conversion will start at next */
+ /* trigger event. */
+ /* Start ADC group regular conversion */
+ LL_ADC_REG_StartConversion(hadc->Instance);
+ }
+ else
+ {
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+ }
+
+ }
+ else
+ {
+ tmp_hal_status = HAL_BUSY;
+ }
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+
+/**
+ * @brief Stop ADC conversion of regular group (and injected group in
+ * case of auto_injection mode), disable interrution of
+ * end-of-conversion, disable ADC peripheral.
+ * @param hadc ADC handle
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* 1. Stop potential conversion on going, on ADC group regular */
+ tmp_hal_status = ADC_ConversionStop(hadc);
+
+ /* Disable ADC peripheral if conversions are effectively stopped */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Disable ADC end of conversion interrupt for regular group */
+ /* Disable ADC overrun interrupt */
+ __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
+
+ /* 2. Disable the ADC peripheral */
+ tmp_hal_status = ADC_Disable(hadc);
+
+ /* Check if ADC is effectively disabled */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY,
+ HAL_ADC_STATE_READY);
+ }
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+
+/**
+ * @brief Enable ADC, start conversion of regular group and transfer result through DMA.
+ * @note Interruptions enabled in this function:
+ * overrun (if applicable), DMA half transfer, DMA transfer complete.
+ * Each of these interruptions has its dedicated callback function.
+ * @param hadc ADC handle
+ * @param pData Destination Buffer address.
+ * @param Length Number of data to be transferred from ADC peripheral to memory
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length)
+{
+ HAL_StatusTypeDef tmp_hal_status;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Perform ADC enable and conversion start if no conversion is on going */
+ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
+ {
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Specific case for first call occurrence of this function (DMA transfer */
+ /* not activated and ADC disabled), DMA transfer must be activated */
+ /* with ADC disabled. */
+ if ((hadc->Instance->CFGR1 & ADC_CFGR1_DMAEN) == 0UL)
+ {
+ if (LL_ADC_IsEnabled(hadc->Instance) != 0UL)
+ {
+ /* Disable ADC */
+ LL_ADC_Disable(hadc->Instance);
+ }
+
+ /* Enable ADC DMA mode */
+ hadc->Instance->CFGR1 |= ADC_CFGR1_DMAEN;
+ }
+
+ /* Enable the ADC peripheral */
+ tmp_hal_status = ADC_Enable(hadc);
+
+ /* Start conversion if ADC is effectively enabled */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Set ADC state */
+ /* - Clear state bitfield related to regular group conversion results */
+ /* - Set state bitfield related to regular operation */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
+ HAL_ADC_STATE_REG_BUSY);
+
+ /* Set ADC error code */
+ /* Reset all ADC error code fields */
+ ADC_CLEAR_ERRORCODE(hadc);
+
+ /* Set the DMA transfer complete callback */
+ hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
+
+ /* Set the DMA half transfer complete callback */
+ hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
+
+ /* Set the DMA error callback */
+ hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
+
+
+ /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */
+ /* start (in case of SW start): */
+
+ /* Clear regular group conversion flag and overrun flag */
+ /* (To ensure of no unknown state from potential previous ADC */
+ /* operations) */
+ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
+
+ /* Process unlocked */
+ /* Unlock before starting ADC conversions: in case of potential */
+ /* interruption, to let the process to ADC IRQ Handler. */
+ __HAL_UNLOCK(hadc);
+
+ /* Enable ADC overrun interrupt */
+ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
+
+ /* Start the DMA channel */
+ tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
+
+ /* Enable conversion of regular group. */
+ /* If software start has been selected, conversion starts immediately. */
+ /* If external trigger has been selected, conversion will start at next */
+ /* trigger event. */
+ /* Start ADC group regular conversion */
+ LL_ADC_REG_StartConversion(hadc->Instance);
+ }
+ }
+ else
+ {
+ tmp_hal_status = HAL_BUSY;
+ }
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+
+/**
+ * @brief Stop ADC conversion of regular group (and injected group in
+ * case of auto_injection mode), disable ADC DMA transfer, disable
+ * ADC peripheral.
+ * @param hadc ADC handle
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* 1. Stop potential ADC group regular conversion on going */
+ tmp_hal_status = ADC_ConversionStop(hadc);
+
+ /* Disable ADC peripheral if conversions are effectively stopped */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Disable the DMA channel (in case of DMA in circular mode or stop */
+ /* while DMA transfer is on going) */
+ if (hadc->DMA_Handle->State == HAL_DMA_STATE_BUSY)
+ {
+ tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
+
+ /* Check if DMA channel effectively disabled */
+ if (tmp_hal_status != HAL_OK)
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
+ }
+ }
+
+ /* Disable ADC overrun interrupt */
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
+
+ /* 2. Disable the ADC peripheral */
+ /* Update "tmp_hal_status" only if DMA channel disabling passed, */
+ /* to keep in memory a potential failing status. */
+ if (tmp_hal_status == HAL_OK)
+ {
+ tmp_hal_status = ADC_Disable(hadc);
+ }
+ else
+ {
+ (void)ADC_Disable(hadc);
+ }
+
+ /* Check if ADC is effectively disabled */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY,
+ HAL_ADC_STATE_READY);
+ }
+
+ /* Disable ADC DMA (ADC DMA configuration of continuous requests is kept) */
+ CLEAR_BIT(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN);
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+
+/**
+ * @brief Get ADC regular group conversion result.
+ * @note Reading register DR automatically clears ADC flag EOC
+ * (ADC group regular end of unitary conversion).
+ * @note This function does not clear ADC flag EOS
+ * (ADC group regular end of sequence conversion).
+ * Occurrence of flag EOS rising:
+ * - If sequencer is composed of 1 rank, flag EOS is equivalent
+ * to flag EOC.
+ * - If sequencer is composed of several ranks, during the scan
+ * sequence flag EOC only is raised, at the end of the scan sequence
+ * both flags EOC and EOS are raised.
+ * To clear this flag, either use function:
+ * in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
+ * model polling: @ref HAL_ADC_PollForConversion()
+ * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS).
+ * @param hadc ADC handle
+ * @retval ADC group regular conversion data
+ */
+uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef *hadc)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Note: EOC flag is not cleared here by software because automatically */
+ /* cleared by hardware when reading register DR. */
+
+ /* Return ADC converted value */
+ return hadc->Instance->DR;
+}
+
+/**
+ * @brief Handle ADC interrupt request.
+ * @param hadc ADC handle
+ * @retval None
+ */
+void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc)
+{
+ uint32_t overrun_error = 0UL; /* flag set if overrun occurrence has to be considered as an error */
+ uint32_t tmp_isr = hadc->Instance->ISR;
+ uint32_t tmp_ier = hadc->Instance->IER;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
+
+ /* ========== Check End of Sampling flag for ADC group regular ========== */
+ if (((tmp_isr & ADC_FLAG_EOSMP) == ADC_FLAG_EOSMP) && ((tmp_ier & ADC_IT_EOSMP) == ADC_IT_EOSMP))
+ {
+ /* Update state machine on end of sampling status if not in error state */
+ if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
+ {
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOSMP);
+ }
+
+ /* End Of Sampling callback */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+ hadc->EndOfSamplingCallback(hadc);
+#else
+ HAL_ADCEx_EndOfSamplingCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
+ /* Clear regular group conversion flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP);
+ }
+
+ /* ====== Check ADC group regular end of unitary conversion sequence conversions ===== */
+ if ((((tmp_isr & ADC_FLAG_EOC) == ADC_FLAG_EOC) && ((tmp_ier & ADC_IT_EOC) == ADC_IT_EOC)) ||
+ (((tmp_isr & ADC_FLAG_EOS) == ADC_FLAG_EOS) && ((tmp_ier & ADC_IT_EOS) == ADC_IT_EOS)))
+ {
+ /* Update state machine on conversion status if not in error state */
+ if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
+ {
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
+ }
+
+ /* Determine whether any further conversion upcoming on group regular */
+ /* by external trigger, continuous mode or scan sequence on going */
+ /* to disable interruption. */
+ if ((LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL)
+ && (hadc->Init.ContinuousConvMode == DISABLE)
+ )
+ {
+ /* If End of Sequence is reached, disable interrupts */
+ if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS))
+ {
+ /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */
+ /* ADSTART==0 (no conversion on going) */
+ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
+ {
+ /* Disable ADC end of single conversion interrupt on group regular */
+ /* Note: Overrun interrupt was enabled with EOC interrupt in */
+ /* HAL_Start_IT(), but is not disabled here because can be used */
+ /* by overrun IRQ process below. */
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS);
+
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY,
+ HAL_ADC_STATE_READY);
+ }
+ else
+ {
+ /* Change ADC state to error state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+ /* Set ADC error code to ADC peripheral internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+ }
+ }
+ }
+
+ /* Conversion complete callback */
+ /* Note: Into callback function "HAL_ADC_ConvCpltCallback()", */
+ /* to determine if conversion has been triggered from EOC or EOS, */
+ /* possibility to use: */
+ /* " if ( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_EOS)) " */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+ hadc->ConvCpltCallback(hadc);
+#else
+ HAL_ADC_ConvCpltCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
+ /* Clear regular group conversion flag */
+ /* Note: in case of overrun set to ADC_OVR_DATA_PRESERVED, end of */
+ /* conversion flags clear induces the release of the preserved data.*/
+ /* Therefore, if the preserved data value is needed, it must be */
+ /* read preliminarily into HAL_ADC_ConvCpltCallback(). */
+ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS));
+ }
+
+ /* ========== Check Analog watchdog 1 flag ========== */
+ if (((tmp_isr & ADC_FLAG_AWD1) == ADC_FLAG_AWD1) && ((tmp_ier & ADC_IT_AWD1) == ADC_IT_AWD1))
+ {
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
+
+ /* Level out of window 1 callback */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+ hadc->LevelOutOfWindowCallback(hadc);
+#else
+ HAL_ADC_LevelOutOfWindowCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
+ /* Clear ADC analog watchdog flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1);
+ }
+
+ /* ========== Check analog watchdog 2 flag ========== */
+ if (((tmp_isr & ADC_FLAG_AWD2) == ADC_FLAG_AWD2) && ((tmp_ier & ADC_IT_AWD2) == ADC_IT_AWD2))
+ {
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_AWD2);
+
+ /* Level out of window 2 callback */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+ hadc->LevelOutOfWindow2Callback(hadc);
+#else
+ HAL_ADCEx_LevelOutOfWindow2Callback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
+ /* Clear ADC analog watchdog flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2);
+ }
+
+ /* ========== Check analog watchdog 3 flag ========== */
+ if (((tmp_isr & ADC_FLAG_AWD3) == ADC_FLAG_AWD3) && ((tmp_ier & ADC_IT_AWD3) == ADC_IT_AWD3))
+ {
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_AWD3);
+
+ /* Level out of window 3 callback */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+ hadc->LevelOutOfWindow3Callback(hadc);
+#else
+ HAL_ADCEx_LevelOutOfWindow3Callback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
+ /* Clear ADC analog watchdog flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3);
+ }
+ /* ========== Check Overrun flag ========== */
+ if (((tmp_isr & ADC_FLAG_OVR) == ADC_FLAG_OVR) && ((tmp_ier & ADC_IT_OVR) == ADC_IT_OVR))
+ {
+ /* If overrun is set to overwrite previous data (default setting), */
+ /* overrun event is not considered as an error. */
+ /* (cf ref manual "Managing conversions without using the DMA and without */
+ /* overrun ") */
+ /* Exception for usage with DMA overrun event always considered as an */
+ /* error. */
+ if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
+ {
+ overrun_error = 1UL;
+ }
+ else
+ {
+ /* Check DMA configuration */
+ if (LL_ADC_REG_GetDMATransfer(hadc->Instance) != LL_ADC_REG_DMA_TRANSFER_NONE)
+ {
+ overrun_error = 1UL;
+ }
+ }
+
+ if (overrun_error == 1UL)
+ {
+ /* Change ADC state to error state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
+
+ /* Set ADC error code to overrun */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
+
+ /* Error callback */
+ /* Note: In case of overrun, ADC conversion data is preserved until */
+ /* flag OVR is reset. */
+ /* Therefore, old ADC conversion data can be retrieved in */
+ /* function "HAL_ADC_ErrorCallback()". */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+ hadc->ErrorCallback(hadc);
+#else
+ HAL_ADC_ErrorCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+ }
+
+ /* Clear ADC overrun flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
+ }
+
+ /* ========== Check channel configuration ready flag ========== */
+ if (((tmp_isr & ADC_FLAG_CCRDY) == ADC_FLAG_CCRDY) && ((tmp_ier & ADC_IT_CCRDY) == ADC_IT_CCRDY))
+ {
+ /* Level out of window 1 callback */
+ HAL_ADCEx_ChannelConfigReadyCallback(hadc);
+
+ /* Clear ADC analog watchdog flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_CCRDY);
+ }
+}
+
+/**
+ * @brief Conversion complete callback in non-blocking mode.
+ * @param hadc ADC handle
+ * @retval None
+ */
+__weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hadc);
+
+ /* NOTE : This function should not be modified. When the callback is needed,
+ function HAL_ADC_ConvCpltCallback must be implemented in the user file.
+ */
+}
+
+/**
+ * @brief Conversion DMA half-transfer callback in non-blocking mode.
+ * @param hadc ADC handle
+ * @retval None
+ */
+__weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hadc);
+
+ /* NOTE : This function should not be modified. When the callback is needed,
+ function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file.
+ */
+}
+
+/**
+ * @brief Analog watchdog 1 callback in non-blocking mode.
+ * @param hadc ADC handle
+ * @retval None
+ */
+__weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef *hadc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hadc);
+
+ /* NOTE : This function should not be modified. When the callback is needed,
+ function HAL_ADC_LevelOutOfWindowCallback must be implemented in the user file.
+ */
+}
+
+/**
+ * @brief ADC error callback in non-blocking mode
+ * (ADC conversion with interruption or transfer by DMA).
+ * @note In case of error due to overrun when using ADC with DMA transfer
+ * (HAL ADC handle parameter "ErrorCode" to state "HAL_ADC_ERROR_OVR"):
+ * - Reinitialize the DMA using function "HAL_ADC_Stop_DMA()".
+ * - If needed, restart a new ADC conversion using function
+ * "HAL_ADC_Start_DMA()"
+ * (this function is also clearing overrun flag)
+ * @param hadc ADC handle
+ * @retval None
+ */
+__weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hadc);
+
+ /* NOTE : This function should not be modified. When the callback is needed,
+ function HAL_ADC_ErrorCallback must be implemented in the user file.
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions
+ * @brief Peripheral Control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Configure channels on regular group
+ (+) Configure the analog watchdog
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configure a channel to be assigned to ADC group regular.
+ * @note In case of usage of internal measurement channels:
+ * VrefInt/TempSensor.
+ * These internal paths can be disabled using function
+ * HAL_ADC_DeInit().
+ * @note Possibility to update parameters on the fly:
+ * This function initializes channel into ADC group regular,
+ * following calls to this function can be used to reconfigure
+ * some parameters of structure "ADC_ChannelConfTypeDef" on the fly,
+ * without resetting the ADC.
+ * The setting of these parameters is conditioned to ADC state:
+ * Refer to comments of structure "ADC_ChannelConfTypeDef".
+ * @param hadc ADC handle
+ * @param sConfig Structure of ADC channel assigned to ADC group regular.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+ uint32_t tmp_config_internal_channel;
+ __IO uint32_t wait_loop_index = 0UL;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ assert_param(IS_ADC_CHANNEL(sConfig->Channel));
+ assert_param(IS_ADC_SAMPLING_TIME_COMMON(sConfig->SamplingTime));
+
+ if ((hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED) ||
+ (hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED_BACKWARD))
+ {
+ assert_param(IS_ADC_REGULAR_RANK_SEQ_FIXED(sConfig->Rank));
+ }
+ else
+ {
+ assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion));
+
+ assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Parameters update conditioned to ADC state: */
+ /* Parameters that can be updated when ADC is disabled or enabled without */
+ /* conversion on going on regular group: */
+ /* - Channel number */
+ /* - Channel sampling time */
+ /* - Management of internal measurement channels: VrefInt/TempSensor */
+ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
+ {
+ /* Configure channel: depending on rank setting, add it or remove it from */
+ /* ADC sequencer. */
+ /* If sequencer set to not fully configurable with channel rank set to */
+ /* none, remove the channel from the sequencer. */
+ /* Otherwise (sequencer set to fully configurable or to to not fully */
+ /* configurable with channel rank to be set), configure the selected */
+ /* channel. */
+ if (sConfig->Rank != ADC_RANK_NONE)
+ {
+ /* Regular sequence configuration */
+ /* Note: ADC channel configuration requires few ADC clock cycles */
+ /* to be ready. Processing of ADC settings in this function */
+ /* induce that a specific wait time is not necessary. */
+ /* For more details on ADC channel configuration ready, */
+ /* refer to function "LL_ADC_IsActiveFlag_CCRDY()". */
+ if ((hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED) ||
+ (hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED_BACKWARD))
+ {
+ /* Sequencer set to not fully configurable: */
+ /* Set the channel by enabling the corresponding bitfield. */
+ LL_ADC_REG_SetSequencerChAdd(hadc->Instance, sConfig->Channel);
+ }
+ else
+ {
+ /* Sequencer set to fully configurable: */
+ /* Set the channel by entering it into the selected rank. */
+
+ /* Memorize the channel set into variable in HAL ADC handle */
+ MODIFY_REG(hadc->ADCGroupRegularSequencerRanks,
+ ADC_CHSELR_SQ1 << (sConfig->Rank & 0x1FUL),
+ __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel) << (sConfig->Rank & 0x1FUL));
+
+ /* If the selected rank is below ADC group regular sequencer length, */
+ /* apply the configuration in ADC register. */
+ /* Note: Otherwise, configuration is not applied. */
+ /* To apply it, parameter'NbrOfConversion' must be increased. */
+ if (((sConfig->Rank >> 2UL) + 1UL) <= hadc->Init.NbrOfConversion)
+ {
+ LL_ADC_REG_SetSequencerRanks(hadc->Instance, sConfig->Rank, sConfig->Channel);
+ }
+ }
+
+ /* Set sampling time of the selected ADC channel */
+ LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfig->Channel, sConfig->SamplingTime);
+
+ /* Management of internal measurement channels: VrefInt/TempSensor */
+ /* internal measurement paths enable: If internal channel selected, */
+ /* enable dedicated internal buffers and path. */
+ /* Note: these internal measurement paths can be disabled using */
+ /* HAL_ADC_DeInit() or removing the channel from sequencer with */
+ /* channel configuration parameter "Rank". */
+ if (__LL_ADC_IS_CHANNEL_INTERNAL(sConfig->Channel))
+ {
+ tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
+
+ /* If the requested internal measurement path has already been enabled, */
+ /* bypass the configuration processing. */
+ if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) &&
+ ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL))
+ {
+ LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
+ LL_ADC_PATH_INTERNAL_TEMPSENSOR | tmp_config_internal_channel);
+
+ /* Delay for temperature sensor stabilization time */
+ /* Wait loop initialization and execution */
+ /* Note: Variable divided by 2 to compensate partially */
+ /* CPU processing cycles, scaling in us split to not */
+ /* exceed 32 bits register capacity and handle low frequency. */
+ wait_loop_index = (((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * (SystemCoreClock / (100000UL * 2UL))) + 1UL);
+ while (wait_loop_index != 0UL)
+ {
+ wait_loop_index--;
+ }
+ }
+ else if ((sConfig->Channel == ADC_CHANNEL_VREFINT) &&
+ ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL))
+ {
+ LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
+ LL_ADC_PATH_INTERNAL_VREFINT | tmp_config_internal_channel);
+ }
+ else
+ {
+ /* nothing to do */
+ }
+ }
+ }
+ else
+ {
+ /* Regular sequencer configuration */
+ /* Note: Case of sequencer set to fully configurable: */
+ /* Sequencer rank cannot be disabled, only affected to */
+ /* another channel. */
+ /* To remove a rank, use parameter 'NbrOfConversion". */
+ if ((hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED) ||
+ (hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED_BACKWARD))
+ {
+ /* Sequencer set to not fully configurable: */
+ /* Reset the channel by disabling the corresponding bitfield. */
+ LL_ADC_REG_SetSequencerChRem(hadc->Instance, sConfig->Channel);
+ }
+
+ /* Management of internal measurement channels: VrefInt/TempSensor. */
+ /* If internal channel selected, enable dedicated internal buffers and */
+ /* paths. */
+ if (__LL_ADC_IS_CHANNEL_INTERNAL(sConfig->Channel))
+ {
+ tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
+
+ if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
+ {
+ LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
+ ~LL_ADC_PATH_INTERNAL_TEMPSENSOR & tmp_config_internal_channel);
+ }
+ else if (sConfig->Channel == ADC_CHANNEL_VREFINT)
+ {
+ LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
+ ~LL_ADC_PATH_INTERNAL_VREFINT & tmp_config_internal_channel);
+ }
+ else
+ {
+ /* nothing to do */
+ }
+ }
+ }
+ }
+
+ /* If a conversion is on going on regular group, no update on regular */
+ /* channel could be done on neither of the channel configuration structure */
+ /* parameters. */
+ else
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+ tmp_hal_status = HAL_ERROR;
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+
+/**
+ * @brief Configure the analog watchdog.
+ * @note Possibility to update parameters on the fly:
+ * This function initializes the selected analog watchdog, successive
+ * calls to this function can be used to reconfigure some parameters
+ * of structure "ADC_AnalogWDGConfTypeDef" on the fly, without resetting
+ * the ADC.
+ * The setting of these parameters is conditioned to ADC state.
+ * For parameters constraints, see comments of structure
+ * "ADC_AnalogWDGConfTypeDef".
+ * @note On this STM32 series, analog watchdog thresholds can be modified
+ * while ADC conversion is on going.
+ * In this case, some constraints must be taken into account:
+ * the programmed threshold values are effective from the next
+ * ADC EOC (end of unitary conversion).
+ * Considering that registers write delay may happen due to
+ * bus activity, this might cause an uncertainty on the
+ * effective timing of the new programmed threshold values.
+ * @param hadc ADC handle
+ * @param AnalogWDGConfig Structure of ADC analog watchdog configuration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *AnalogWDGConfig)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+ uint32_t tmpAWDHighThresholdShifted;
+ uint32_t tmpAWDLowThresholdShifted;
+ uint32_t backup_setting_adc_enable_state = 0UL;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ assert_param(IS_ADC_ANALOG_WATCHDOG_NUMBER(AnalogWDGConfig->WatchdogNumber));
+ assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(AnalogWDGConfig->WatchdogMode));
+ assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode));
+
+ if (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG)
+ {
+ assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel));
+ }
+
+ /* Verify thresholds range */
+ if (hadc->Init.OversamplingMode == ENABLE)
+ {
+ /* Case of oversampling enabled: depending on ratio and shift configuration,
+ analog watchdog thresholds can be higher than ADC resolution.
+ Verify if thresholds are within maximum thresholds range. */
+ assert_param(IS_ADC_RANGE(ADC_RESOLUTION_12B, AnalogWDGConfig->HighThreshold));
+ assert_param(IS_ADC_RANGE(ADC_RESOLUTION_12B, AnalogWDGConfig->LowThreshold));
+ }
+ else
+ {
+ /* Verify if thresholds are within the selected ADC resolution */
+ assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->HighThreshold));
+ assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->LowThreshold));
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Parameters update conditioned to ADC state: */
+ /* Parameters that can be updated when ADC is disabled or enabled without */
+ /* conversion on going on ADC group regular: */
+ /* - Analog watchdog channels */
+ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
+ {
+ /* Analog watchdog configuration */
+ if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_1)
+ {
+ /* Constraint of ADC on this STM32 series: ADC must be disable
+ to modify bitfields of register ADC_CFGR1 */
+ if (LL_ADC_IsEnabled(hadc->Instance) != 0UL)
+ {
+ backup_setting_adc_enable_state = 1UL;
+ tmp_hal_status = ADC_Disable(hadc);
+
+ /* Check if ADC is effectively disabled */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY,
+ HAL_ADC_STATE_READY);
+ }
+ }
+
+ /* Configuration of analog watchdog: */
+ /* - Set the analog watchdog enable mode: one or overall group of */
+ /* channels. */
+ switch (AnalogWDGConfig->WatchdogMode)
+ {
+ case ADC_ANALOGWATCHDOG_SINGLE_REG:
+ LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1,
+ __LL_ADC_ANALOGWD_CHANNEL_GROUP(AnalogWDGConfig->Channel, LL_ADC_GROUP_REGULAR));
+ break;
+
+ case ADC_ANALOGWATCHDOG_ALL_REG:
+ LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_ALL_CHANNELS_REG);
+ break;
+
+ default: /* ADC_ANALOGWATCHDOG_NONE */
+ LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_DISABLE);
+ break;
+ }
+
+ if (backup_setting_adc_enable_state == 1UL)
+ {
+ tmp_hal_status = ADC_Enable(hadc);
+ }
+
+ /* Update state, clear previous result related to AWD1 */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD1);
+
+ /* Clear flag ADC analog watchdog */
+ /* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready */
+ /* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent() */
+ /* (in case left enabled by previous ADC operations). */
+ LL_ADC_ClearFlag_AWD1(hadc->Instance);
+
+ /* Configure ADC analog watchdog interrupt */
+ if (AnalogWDGConfig->ITMode == ENABLE)
+ {
+ LL_ADC_EnableIT_AWD1(hadc->Instance);
+ }
+ else
+ {
+ LL_ADC_DisableIT_AWD1(hadc->Instance);
+ }
+ }
+ /* Case of ADC_ANALOGWATCHDOG_2 or ADC_ANALOGWATCHDOG_3 */
+ else
+ {
+ switch (AnalogWDGConfig->WatchdogMode)
+ {
+ case ADC_ANALOGWATCHDOG_SINGLE_REG:
+ /* Update AWD by bitfield to keep the possibility to monitor */
+ /* several channels by successive calls of this function. */
+ if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2)
+ {
+ SET_BIT(hadc->Instance->AWD2CR, (1UL << __LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDGConfig->Channel)));
+ }
+ else
+ {
+ SET_BIT(hadc->Instance->AWD3CR, (1UL << __LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDGConfig->Channel)));
+ }
+ break;
+
+ case ADC_ANALOGWATCHDOG_ALL_REG:
+ LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, AnalogWDGConfig->WatchdogNumber, LL_ADC_AWD_ALL_CHANNELS_REG);
+ break;
+
+ default: /* ADC_ANALOGWATCHDOG_NONE */
+ LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, AnalogWDGConfig->WatchdogNumber, LL_ADC_AWD_DISABLE);
+ break;
+ }
+
+ if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2)
+ {
+ /* Update state, clear previous result related to AWD2 */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD2);
+
+ /* Clear flag ADC analog watchdog */
+ /* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready */
+ /* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent() */
+ /* (in case left enabled by previous ADC operations). */
+ LL_ADC_ClearFlag_AWD2(hadc->Instance);
+
+ /* Configure ADC analog watchdog interrupt */
+ if (AnalogWDGConfig->ITMode == ENABLE)
+ {
+ LL_ADC_EnableIT_AWD2(hadc->Instance);
+ }
+ else
+ {
+ LL_ADC_DisableIT_AWD2(hadc->Instance);
+ }
+ }
+ /* (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_3) */
+ else
+ {
+ /* Update state, clear previous result related to AWD3 */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD3);
+
+ /* Clear flag ADC analog watchdog */
+ /* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready */
+ /* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent() */
+ /* (in case left enabled by previous ADC operations). */
+ LL_ADC_ClearFlag_AWD3(hadc->Instance);
+
+ /* Configure ADC analog watchdog interrupt */
+ if (AnalogWDGConfig->ITMode == ENABLE)
+ {
+ LL_ADC_EnableIT_AWD3(hadc->Instance);
+ }
+ else
+ {
+ LL_ADC_DisableIT_AWD3(hadc->Instance);
+ }
+ }
+ }
+
+ }
+
+ /* Analog watchdog thresholds configuration */
+ if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_1)
+ {
+ /* Shift the offset with respect to the selected ADC resolution: */
+ /* Thresholds have to be left-aligned on bit 11, the LSB (right bits) */
+ /* are set to 0. */
+ tmpAWDHighThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold);
+ tmpAWDLowThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold);
+ }
+ /* Case of ADC_ANALOGWATCHDOG_2 and ADC_ANALOGWATCHDOG_3 */
+ else
+ {
+ /* No need to shift the offset with respect to the selected ADC resolution: */
+ /* Thresholds have to be left-aligned on bit 11, the LSB (right bits) */
+ /* are set to 0. */
+ tmpAWDHighThresholdShifted = AnalogWDGConfig->HighThreshold;
+ tmpAWDLowThresholdShifted = AnalogWDGConfig->LowThreshold;
+ }
+
+ /* Set ADC analog watchdog thresholds value of both thresholds high and low */
+ LL_ADC_ConfigAnalogWDThresholds(hadc->Instance, AnalogWDGConfig->WatchdogNumber, tmpAWDHighThresholdShifted,
+ tmpAWDLowThresholdShifted);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions
+ * @brief ADC Peripheral State functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral state and errors functions #####
+ ===============================================================================
+ [..]
+ This subsection provides functions to get in run-time the status of the
+ peripheral.
+ (+) Check the ADC state
+ (+) Check the ADC error code
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the ADC handle state.
+ * @note ADC state machine is managed by bitfields, ADC status must be
+ * compared with states bits.
+ * For example:
+ * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_REG_BUSY) != 0UL) "
+ * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) "
+ * @param hadc ADC handle
+ * @retval ADC handle state (bitfield on 32 bits)
+ */
+uint32_t HAL_ADC_GetState(ADC_HandleTypeDef *hadc)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Return ADC handle state */
+ return hadc->State;
+}
+
+/**
+ * @brief Return the ADC error code.
+ * @param hadc ADC handle
+ * @retval ADC error code (bitfield on 32 bits)
+ */
+uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ return hadc->ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Private_Functions ADC Private Functions
+ * @{
+ */
+
+/**
+ * @brief Stop ADC conversion.
+ * @note Prerequisite condition to use this function: ADC conversions must be
+ * stopped to disable the ADC.
+ * @param hadc ADC handle
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc)
+{
+ uint32_t tickstart;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Verification if ADC is not already stopped on regular group to bypass */
+ /* this function if not needed. */
+ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) != 0UL)
+ {
+ /* Stop potential conversion on going on regular group */
+ /* Software is allowed to set ADSTP only when ADSTART=1 and ADDIS=0 */
+ if (LL_ADC_IsDisableOngoing(hadc->Instance) == 0UL)
+ {
+ /* Stop ADC group regular conversion */
+ LL_ADC_REG_StopConversion(hadc->Instance);
+ }
+
+ /* Wait for conversion effectively stopped */
+ /* Get tick count */
+ tickstart = HAL_GetTick();
+
+ while ((hadc->Instance->CR & ADC_CR_ADSTART) != 0UL)
+ {
+ if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+ /* Set ADC error code to ADC peripheral internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+
+ return HAL_ERROR;
+ }
+ }
+
+ }
+
+ /* Return HAL status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Enable the selected ADC.
+ * @note Prerequisite condition to use this function: ADC must be disabled
+ * and voltage regulator must be enabled (done into HAL_ADC_Init()).
+ * @param hadc ADC handle
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc)
+{
+ uint32_t tickstart;
+ __IO uint32_t wait_loop_index = 0UL;
+
+ /* ADC enable and wait for ADC ready (in case of ADC is disabled or */
+ /* enabling phase not yet completed: flag ADC ready not yet set). */
+ /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */
+ /* causes: ADC clock not running, ...). */
+ if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
+ {
+ /* Check if conditions to enable the ADC are fulfilled */
+ if ((hadc->Instance->CR & (ADC_CR_ADCAL | ADC_CR_ADSTP | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN)) != 0UL)
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+ /* Set ADC error code to ADC peripheral internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+
+ return HAL_ERROR;
+ }
+
+ /* Enable the ADC peripheral */
+ LL_ADC_Enable(hadc->Instance);
+
+ if ((LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) & LL_ADC_PATH_INTERNAL_TEMPSENSOR) != 0UL)
+ {
+ /* Delay for temperature sensor buffer stabilization time */
+ /* Wait loop initialization and execution */
+ /* Note: Variable divided by 2 to compensate partially */
+ /* CPU processing cycles, scaling in us split to not */
+ /* exceed 32 bits register capacity and handle low frequency. */
+ wait_loop_index = (((LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US / 10UL) * (SystemCoreClock / (100000UL * 2UL))) + 1UL);
+ while (wait_loop_index != 0UL)
+ {
+ wait_loop_index--;
+ }
+ }
+
+ /* If low power mode AutoPowerOff is enabled, power-on/off phases are */
+ /* performed automatically by hardware and flag ADC ready is not set. */
+ if (hadc->Init.LowPowerAutoPowerOff != ENABLE)
+ {
+ /* Wait for ADC effectively enabled */
+ tickstart = HAL_GetTick();
+
+ while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL)
+ {
+ /* If ADEN bit is set less than 4 ADC clock cycles after the ADCAL bit
+ has been cleared (after a calibration), ADEN bit is reset by the
+ calibration logic.
+ The workaround is to continue setting ADEN until ADRDY is becomes 1.
+ Additionally, ADC_ENABLE_TIMEOUT is defined to encompass this
+ 4 ADC clock cycle duration */
+ /* Note: Test of ADC enabled required due to hardware constraint to */
+ /* not enable ADC if already enabled. */
+ if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
+ {
+ LL_ADC_Enable(hadc->Instance);
+ }
+
+ if ((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT)
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+ /* Set ADC error code to ADC peripheral internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+
+ return HAL_ERROR;
+ }
+ }
+ }
+ }
+
+ /* Return HAL status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Disable the selected ADC.
+ * @note Prerequisite condition to use this function: ADC conversions must be
+ * stopped.
+ * @param hadc ADC handle
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc)
+{
+ uint32_t tickstart;
+ const uint32_t tmp_adc_is_disable_on_going = LL_ADC_IsDisableOngoing(hadc->Instance);
+
+ /* Verification if ADC is not already disabled: */
+ /* Note: forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already */
+ /* disabled. */
+ if ((LL_ADC_IsEnabled(hadc->Instance) != 0UL)
+ && (tmp_adc_is_disable_on_going == 0UL)
+ )
+ {
+ /* Check if conditions to disable the ADC are fulfilled */
+ if ((hadc->Instance->CR & (ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN)
+ {
+ /* Disable the ADC peripheral */
+ LL_ADC_Disable(hadc->Instance);
+ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOSMP | ADC_FLAG_RDY));
+ }
+ else
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+ /* Set ADC error code to ADC peripheral internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+
+ return HAL_ERROR;
+ }
+
+ /* Wait for ADC effectively disabled */
+ /* Get tick count */
+ tickstart = HAL_GetTick();
+
+ while ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL)
+ {
+ if ((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT)
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+ /* Set ADC error code to ADC peripheral internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+
+ return HAL_ERROR;
+ }
+ }
+ }
+
+ /* Return HAL status */
+ return HAL_OK;
+}
+
+/**
+ * @brief DMA transfer complete callback.
+ * @param hdma pointer to DMA handle.
+ * @retval None
+ */
+static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
+{
+ /* Retrieve ADC handle corresponding to current DMA handle */
+ ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ /* Update state machine on conversion status if not in error state */
+ if ((hadc->State & (HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) == 0UL)
+ {
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
+
+ /* Determine whether any further conversion upcoming on group regular */
+ /* by external trigger, continuous mode or scan sequence on going */
+ /* to disable interruption. */
+ if ((LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL)
+ && (hadc->Init.ContinuousConvMode == DISABLE)
+ )
+ {
+ /* If End of Sequence is reached, disable interrupts */
+ if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS))
+ {
+ /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */
+ /* ADSTART==0 (no conversion on going) */
+ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
+ {
+ /* Disable ADC end of single conversion interrupt on group regular */
+ /* Note: Overrun interrupt was enabled with EOC interrupt in */
+ /* HAL_Start_IT(), but is not disabled here because can be used */
+ /* by overrun IRQ process below. */
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS);
+
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY,
+ HAL_ADC_STATE_READY);
+ }
+ else
+ {
+ /* Change ADC state to error state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+ /* Set ADC error code to ADC peripheral internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+ }
+ }
+ }
+
+ /* Conversion complete callback */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+ hadc->ConvCpltCallback(hadc);
+#else
+ HAL_ADC_ConvCpltCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+ }
+ else /* DMA and-or internal error occurred */
+ {
+ if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) != 0UL)
+ {
+ /* Call HAL ADC Error Callback function */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+ hadc->ErrorCallback(hadc);
+#else
+ HAL_ADC_ErrorCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+ }
+ else
+ {
+ /* Call ADC DMA error callback */
+ hadc->DMA_Handle->XferErrorCallback(hdma);
+ }
+ }
+}
+
+/**
+ * @brief DMA half transfer complete callback.
+ * @param hdma pointer to DMA handle.
+ * @retval None
+ */
+static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)
+{
+ /* Retrieve ADC handle corresponding to current DMA handle */
+ ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ /* Half conversion callback */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+ hadc->ConvHalfCpltCallback(hadc);
+#else
+ HAL_ADC_ConvHalfCpltCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief DMA error callback.
+ * @param hdma pointer to DMA handle.
+ * @retval None
+ */
+static void ADC_DMAError(DMA_HandleTypeDef *hdma)
+{
+ /* Retrieve ADC handle corresponding to current DMA handle */
+ ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
+
+ /* Set ADC error code to DMA error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA);
+
+ /* Error callback */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+ hadc->ErrorCallback(hadc);
+#else
+ HAL_ADC_ErrorCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+}
+
+/**
+ * @}
+ */
+
+#endif /* HAL_ADC_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc_ex.c b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc_ex.c
new file mode 100644
index 0000000000..95adee1c0c
--- /dev/null
+++ b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc_ex.c
@@ -0,0 +1,392 @@
+/**
+ ******************************************************************************
+ * @file stm32c0xx_hal_adc_ex.c
+ * @author MCD Application Team
+ * @brief This file provides firmware functions to manage the following
+ * functionalities of the Analog to Digital Converter (ADC)
+ * peripheral:
+ * + Operation functions
+ * ++ Calibration
+ * +++ ADC automatic self-calibration
+ * +++ Calibration factors get or set
+ * Other functions (generic functions) are available in file
+ * "stm32c0xx_hal_adc.c".
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2022 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ [..]
+ (@) Sections "ADC peripheral features" and "How to use this driver" are
+ available in file of generic functions "stm32c0xx_hal_adc.c".
+ [..]
+ @endverbatim
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32c0xx_hal.h"
+
+/** @addtogroup STM32C0xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup ADCEx ADCEx
+ * @brief ADC Extended HAL module driver
+ * @{
+ */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/** @defgroup ADCEx_Private_Constants ADC Extended Private Constants
+ * @{
+ */
+
+/* Fixed timeout value for ADC calibration. */
+/* Values defined to be higher than worst cases: maximum ratio between ADC */
+/* and CPU clock frequencies. */
+/* Example of profile low frequency : ADC frequency at 31.25kHz (ADC clock */
+/* source 8MHz, ADC clock prescaler 256), CPU frequency 48MHz. */
+/* Calibration time max = 116 / fADC (refer to datasheet) */
+/* = 178 176 CPU cycles */
+#define ADC_CALIBRATION_TIMEOUT (178176UL) /*!< ADC calibration time-out value (unit: CPU cycles) */
+#define ADC_DISABLE_TIMEOUT (2UL)
+
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup ADCEx_Exported_Functions ADC Extended Exported Functions
+ * @{
+ */
+
+/** @defgroup ADCEx_Exported_Functions_Group1 Extended Input and Output operation functions
+ * @brief Extended IO operation functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+
+ (+) Perform the ADC self-calibration.
+ (+) Get calibration factors.
+ (+) Set calibration factors.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Perform an ADC automatic self-calibration
+ * Calibration prerequisite: ADC must be disabled (execute this
+ * function before HAL_ADC_Start() or after HAL_ADC_Stop() ).
+ * @note Calibration factor can be read after calibration, using function
+ * HAL_ADC_GetValue() (value on 7 bits: from DR[6;0]).
+ * @param hadc ADC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status;
+ __IO uint32_t wait_loop_index = 0UL;
+ uint32_t backup_setting_adc_dma_transfer; /* Note: Variable not declared as volatile because register read is already declared as volatile */
+ uint32_t calibration_index;
+ uint32_t calibration_factor_accumulated = 0;
+ uint32_t tickstart;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Calibration prerequisite: ADC must be disabled. */
+
+ /* Disable the ADC (if not already disabled) */
+ tmp_hal_status = ADC_Disable(hadc);
+
+ /* Check if ADC is effectively disabled */
+ if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
+ {
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY,
+ HAL_ADC_STATE_BUSY_INTERNAL);
+
+ /* Disable ADC DMA transfer request during calibration */
+ /* Note: Specificity of this STM32 series: Calibration factor is */
+ /* available in data register and also transferred by DMA. */
+ /* To not insert ADC calibration factor among ADC conversion data */
+ /* in array variable, DMA transfer must be disabled during */
+ /* calibration. */
+ backup_setting_adc_dma_transfer = READ_BIT(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG);
+ CLEAR_BIT(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG);
+
+ /* ADC calibration procedure */
+ /* Note: Perform an averaging of 8 calibrations for optimized accuracy */
+ for (calibration_index = 0UL; calibration_index < 8UL; calibration_index++)
+ {
+ /* Start ADC calibration */
+ LL_ADC_StartCalibration(hadc->Instance);
+
+ /* Wait for calibration completion */
+ while (LL_ADC_IsCalibrationOnGoing(hadc->Instance) != 0UL)
+ {
+ wait_loop_index++;
+ if (wait_loop_index >= ADC_CALIBRATION_TIMEOUT)
+ {
+ /* Update ADC state machine to error */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_BUSY_INTERNAL,
+ HAL_ADC_STATE_ERROR_INTERNAL);
+
+ __HAL_UNLOCK(hadc);
+
+ return HAL_ERROR;
+ }
+ }
+
+ calibration_factor_accumulated += LL_ADC_GetCalibrationFactor(hadc->Instance);
+ }
+ /* Compute average */
+ calibration_factor_accumulated /= calibration_index;
+ /* Apply calibration factor */
+ LL_ADC_Enable(hadc->Instance);
+ LL_ADC_SetCalibrationFactor(hadc->Instance, calibration_factor_accumulated);
+ LL_ADC_Disable(hadc->Instance);
+
+ /* Wait for ADC effectively disabled before changing configuration */
+ /* Get tick count */
+ tickstart = HAL_GetTick();
+
+ while (LL_ADC_IsEnabled(hadc->Instance) != 0UL)
+ {
+ if ((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT)
+ {
+ /* New check to avoid false timeout detection in case of preemption */
+ if (LL_ADC_IsEnabled(hadc->Instance) != 0UL)
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+ /* Set ADC error code to ADC peripheral internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+
+ return HAL_ERROR;
+ }
+ }
+ }
+
+ /* Restore ADC DMA transfer request after calibration */
+ SET_BIT(hadc->Instance->CFGR1, backup_setting_adc_dma_transfer);
+
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_BUSY_INTERNAL,
+ HAL_ADC_STATE_READY);
+ }
+ else
+ {
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+ /* Note: No need to update variable "tmp_hal_status" here: already set */
+ /* to state "HAL_ERROR" by function disabling the ADC. */
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+
+/**
+ * @brief Get the calibration factor.
+ * @param hadc ADC handle.
+ * @retval Calibration value.
+ */
+uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef *hadc)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Return the selected ADC calibration value */
+ return ((hadc->Instance->CALFACT) & 0x0000007FU);
+}
+
+/**
+ * @brief Set the calibration factor to overwrite automatic conversion result.
+ * ADC must be enabled and no conversion is ongoing.
+ * @param hadc ADC handle
+ * @param CalibrationFactor Calibration factor (coded on 7 bits maximum)
+ * @retval HAL state
+ */
+HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t CalibrationFactor)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+ uint32_t tmp_adc_is_conversion_on_going_regular;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ assert_param(IS_ADC_CALFACT(CalibrationFactor));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Verification of hardware constraints before modifying the calibration */
+ /* factors register: ADC must be enabled, no conversion on going. */
+ tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
+
+ if ((LL_ADC_IsEnabled(hadc->Instance) != 0UL)
+ && (tmp_adc_is_conversion_on_going_regular == 0UL)
+ )
+ {
+ hadc->Instance->CALFACT &= ~ADC_CALFACT_CALFACT;
+ hadc->Instance->CALFACT |= CalibrationFactor;
+ }
+ else
+ {
+ /* Update ADC state machine */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+ /* Update ADC error code */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+
+ /* Update ADC state machine to error */
+ tmp_hal_status = HAL_ERROR;
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+
+/**
+ * @brief Analog watchdog 2 callback in non-blocking mode.
+ * @param hadc ADC handle
+ * @retval None
+ */
+__weak void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef *hadc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hadc);
+
+ /* NOTE : This function should not be modified. When the callback is needed,
+ function HAL_ADCEx_LevelOutOfWindow2Callback must be implemented in the user file.
+ */
+}
+
+/**
+ * @brief Analog watchdog 3 callback in non-blocking mode.
+ * @param hadc ADC handle
+ * @retval None
+ */
+__weak void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef *hadc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hadc);
+
+ /* NOTE : This function should not be modified. When the callback is needed,
+ function HAL_ADCEx_LevelOutOfWindow3Callback must be implemented in the user file.
+ */
+}
+
+
+/**
+ * @brief End Of Sampling callback in non-blocking mode.
+ * @param hadc ADC handle
+ * @retval None
+ */
+__weak void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef *hadc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hadc);
+
+ /* NOTE : This function should not be modified. When the callback is needed,
+ function HAL_ADCEx_EndOfSamplingCallback must be implemented in the user file.
+ */
+}
+
+/**
+ * @brief ADC channel configuration ready callback in non-blocking mode.
+ * @param hadc ADC handle
+ * @retval None
+ */
+__weak void HAL_ADCEx_ChannelConfigReadyCallback(ADC_HandleTypeDef *hadc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hadc);
+
+ /* NOTE : This function should not be modified. When the callback is needed,
+ function HAL_ADCEx_ChannelConfigReadyCallback must be implemented in the user file.
+ */
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @brief Disable ADC voltage regulator.
+ * @note Disabling voltage regulator allows to save power. This operation can
+ * be carried out only when ADC is disabled.
+ * @note To enable again the voltage regulator, the user is expected to
+ * resort to HAL_ADC_Init() API.
+ * @param hadc ADC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef *hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Setting of this feature is conditioned to ADC state: ADC must be ADC disabled */
+ if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
+ {
+ LL_ADC_DisableInternalRegulator(hadc->Instance);
+ tmp_hal_status = HAL_OK;
+ }
+ else
+ {
+ tmp_hal_status = HAL_ERROR;
+ }
+
+ return tmp_hal_status;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_ADC_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c
new file mode 100644
index 0000000000..093366716c
--- /dev/null
+++ b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c
@@ -0,0 +1,423 @@
+/**
+ ******************************************************************************
+ * @file stm32c0xx_hal_cortex.c
+ * @author MCD Application Team
+ * @brief CORTEX HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the CORTEX:
+ * + Initialization and Configuration functions
+ * + Peripheral Control functions
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2022 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ *** How to configure Interrupts using CORTEX HAL driver ***
+ ===========================================================
+ [..]
+ This section provides functions allowing to configure the NVIC interrupts (IRQ).
+ The Cortex M0+ exceptions are managed by CMSIS functions.
+ (#) Enable and Configure the priority of the selected IRQ Channels.
+ The priority can be 0..3.
+
+ -@- Lower priority values gives higher priority.
+ -@- Priority Order:
+ (#@) Lowest priority.
+ (#@) Lowest hardware priority (IRQn position).
+
+ (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority()
+
+ (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ()
+
+ -@- Negative value of IRQn_Type are not allowed.
+
+ *** How to configure Systick using CORTEX HAL driver ***
+ ========================================================
+ [..]
+ Setup SysTick Timer for time base.
+
+ (+) The HAL_SYSTICK_Config()function calls the SysTick_Config() function which
+ is a CMSIS function that:
+ (++) Configures the SysTick Reload register with value passed as function parameter.
+ (++) Configures the SysTick IRQ priority to the lowest value (0x03).
+ (++) Resets the SysTick Counter register.
+ (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
+ (++) Enables the SysTick Interrupt.
+ (++) Starts the SysTick Counter.
+
+ (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
+ __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
+ HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined
+ inside the stm32c0xx_hal_cortex.h file.
+
+ (+) You can change the SysTick IRQ priority by calling the
+ HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
+ call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.
+
+ (+) To adjust the SysTick time base, use the following formula:
+
+ Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s)
+ (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
+ (++) Reload Value should not exceed 0xFFFFFF
+
+ @endverbatim
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32c0xx_hal.h"
+
+/** @addtogroup STM32C0xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup CORTEX
+ * @{
+ */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup CORTEX_Exported_Functions
+ * @{
+ */
+
+
+/** @addtogroup CORTEX_Exported_Functions_Group1
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Initialization and Configuration functions #####
+ ==============================================================================
+ [..]
+ This section provides the CORTEX HAL driver functions allowing to configure Interrupts
+ Systick functionalities
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Sets the priority of an interrupt.
+ * @param IRQn External interrupt number .
+ * This parameter can be an enumerator of IRQn_Type enumeration
+ * (For the complete STM32 Devices IRQ Channels list, please refer to stm32c0xx.h file)
+ * @param PreemptPriority The preemption priority for the IRQn channel.
+ * This parameter can be a value between 0 and 3.
+ * A lower priority value indicates a higher priority
+ * @param SubPriority the subpriority level for the IRQ channel.
+ * with stm32c0xx devices, this parameter is a dummy value and it is ignored, because
+ * no subpriority supported in Cortex M0+ based products.
+ * @retval None
+ */
+void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(SubPriority);
+ /* Check the parameters */
+ assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
+ NVIC_SetPriority(IRQn, PreemptPriority);
+}
+
+/**
+ * @brief Enable a device specific interrupt in the NVIC interrupt controller.
+ * @param IRQn External interrupt number.
+ * This parameter can be an enumerator of IRQn_Type enumeration
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate
+ * CMSIS device file (stm32c0xxxx.h))
+ * @retval None
+ */
+void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ /* Check the parameters */
+ assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+
+ /* Enable interrupt */
+ NVIC_EnableIRQ(IRQn);
+}
+
+/**
+ * @brief Disable a device specific interrupt in the NVIC interrupt controller.
+ * @param IRQn External interrupt number.
+ * This parameter can be an enumerator of IRQn_Type enumeration
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate
+ * CMSIS device file (stm32c0xxxx.h))
+ * @retval None
+ */
+void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ /* Check the parameters */
+ assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+
+ /* Disable interrupt */
+ NVIC_DisableIRQ(IRQn);
+}
+
+/**
+ * @brief Initiate a system reset request to reset the MCU.
+ * @retval None
+ */
+void HAL_NVIC_SystemReset(void)
+{
+ /* System Reset */
+ NVIC_SystemReset();
+}
+
+/**
+ * @brief Initialize the System Timer with interrupt enabled and start the System Tick Timer (SysTick):
+ * Counter is in free running mode to generate periodic interrupts.
+ * @param TicksNumb Specifies the ticks Number of ticks between two interrupts.
+ * @retval status: - 0 Function succeeded.
+ * - 1 Function failed.
+ */
+uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
+{
+ return SysTick_Config(TicksNumb);
+}
+/**
+ * @}
+ */
+
+/** @addtogroup CORTEX_Exported_Functions_Group2
+ * @brief Cortex control functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral Control functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control the CORTEX
+ (NVIC, SYSTICK, MPU) functionalities.
+
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Get the priority of an interrupt.
+ * @param IRQn External interrupt number.
+ * This parameter can be an enumerator of IRQn_Type enumeration
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate
+ * CMSIS device file (stm32c0xxxx.h))
+ * @retval None
+ */
+uint32_t HAL_NVIC_GetPriority(IRQn_Type IRQn)
+{
+ /* Get priority for Cortex-M system or device specific interrupts */
+ return NVIC_GetPriority(IRQn);
+}
+
+/**
+ * @brief Set Pending bit of an external interrupt.
+ * @param IRQn External interrupt number
+ * This parameter can be an enumerator of IRQn_Type enumeration
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate
+ * CMSIS device file (stm32c0xxxx.h))
+ * @retval None
+ */
+void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ /* Check the parameters */
+ assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+
+ /* Set interrupt pending */
+ NVIC_SetPendingIRQ(IRQn);
+}
+
+/**
+ * @brief Get Pending Interrupt (read the pending register in the NVIC
+ * and return the pending bit for the specified interrupt).
+ * @param IRQn External interrupt number.
+ * This parameter can be an enumerator of IRQn_Type enumeration
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate
+ * CMSIS device file (stm32c0xxxx.h))
+ * @retval status: - 0 Interrupt status is not pending.
+ * - 1 Interrupt status is pending.
+ */
+uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ /* Check the parameters */
+ assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+
+ /* Return 1 if pending else 0 */
+ return NVIC_GetPendingIRQ(IRQn);
+}
+
+/**
+ * @brief Clear the pending bit of an external interrupt.
+ * @param IRQn External interrupt number.
+ * This parameter can be an enumerator of IRQn_Type enumeration
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate
+ * CMSIS device file (stm32c0xxxx.h))
+ * @retval None
+ */
+void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ /* Check the parameters */
+ assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+
+ /* Clear pending interrupt */
+ NVIC_ClearPendingIRQ(IRQn);
+}
+
+/**
+ * @brief Configure the SysTick clock source.
+ * @param CLKSource specifies the SysTick clock source.
+ * This parameter can be one of the following values:
+ * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
+ * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
+ * @retval None
+ */
+void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
+{
+ /* Check the parameters */
+ assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
+ if (CLKSource == SYSTICK_CLKSOURCE_HCLK)
+ {
+ SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
+ }
+ else
+ {
+ SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;
+ }
+}
+
+/**
+ * @brief Handle SYSTICK interrupt request.
+ * @retval None
+ */
+void HAL_SYSTICK_IRQHandler(void)
+{
+ HAL_SYSTICK_Callback();
+}
+
+/**
+ * @brief SYSTICK callback.
+ * @retval None
+ */
+__weak void HAL_SYSTICK_Callback(void)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SYSTICK_Callback could be implemented in the user file
+ */
+}
+
+#if (__MPU_PRESENT == 1U)
+/**
+ * @brief Enable the MPU.
+ * @param MPU_Control Specifies the control mode of the MPU during hard fault,
+ * NMI, FAULTMASK and privileged access to the default memory
+ * This parameter can be one of the following values:
+ * @arg MPU_HFNMI_PRIVDEF_NONE
+ * @arg MPU_HARDFAULT_NMI
+ * @arg MPU_PRIVILEGED_DEFAULT
+ * @arg MPU_HFNMI_PRIVDEF
+ * @retval None
+ */
+void HAL_MPU_Enable(uint32_t MPU_Control)
+{
+ /* Enable the MPU */
+ MPU->CTRL = (MPU_Control | MPU_CTRL_ENABLE_Msk);
+
+ /* Ensure MPU setting take effects */
+ __DSB();
+ __ISB();
+}
+
+
+/**
+ * @brief Disable the MPU.
+ * @retval None
+ */
+void HAL_MPU_Disable(void)
+{
+ /* Make sure outstanding transfers are done */
+ __DMB();
+
+ /* Disable the MPU and clear the control register*/
+ MPU->CTRL = 0;
+}
+
+
+/**
+ * @brief Initialize and configure the Region and the memory to be protected.
+ * @param MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains
+ * the initialization and configuration information.
+ * @retval None
+ */
+void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
+{
+ /* Check the parameters */
+ assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));
+ assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));
+
+ /* Set the Region number */
+ MPU->RNR = MPU_Init->Number;
+
+ if ((MPU_Init->Enable) != 0U)
+ {
+ /* Check the parameters */
+ assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
+ assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
+ assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
+ assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
+ assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
+ assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
+ assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
+ assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
+
+ MPU->RBAR = MPU_Init->BaseAddress;
+ MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) |
+ ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) |
+ ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) |
+ ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) |
+ ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) |
+ ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) |
+ ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) |
+ ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) |
+ ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos);
+ }
+ else
+ {
+ MPU->RBAR = 0x00U;
+ MPU->RASR = 0x00U;
+ }
+}
+#endif /* __MPU_PRESENT */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_crc.c b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_crc.c
new file mode 100644
index 0000000000..716a0eb60e
--- /dev/null
+++ b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_crc.c
@@ -0,0 +1,516 @@
+/**
+ ******************************************************************************
+ * @file stm32c0xx_hal_crc.c
+ * @author MCD Application Team
+ * @brief CRC HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Cyclic Redundancy Check (CRC) peripheral:
+ * + Initialization and de-initialization functions
+ * + Peripheral Control functions
+ * + Peripheral State functions
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2022 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ===============================================================================
+ ##### How to use this driver #####
+ ===============================================================================
+ [..]
+ (+) Enable CRC AHB clock using __HAL_RCC_CRC_CLK_ENABLE();
+ (+) Initialize CRC calculator
+ (++) specify generating polynomial (peripheral default or non-default one)
+ (++) specify initialization value (peripheral default or non-default one)
+ (++) specify input data format
+ (++) specify input or output data inversion mode if any
+ (+) Use HAL_CRC_Accumulate() function to compute the CRC value of the
+ input data buffer starting with the previously computed CRC as
+ initialization value
+ (+) Use HAL_CRC_Calculate() function to compute the CRC value of the
+ input data buffer starting with the defined initialization value
+ (default or non-default) to initiate CRC calculation
+
+ @endverbatim
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32c0xx_hal.h"
+
+/** @addtogroup STM32C0xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup CRC CRC
+ * @brief CRC HAL module driver.
+ * @{
+ */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup CRC_Private_Functions CRC Private Functions
+ * @{
+ */
+static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength);
+static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength);
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup CRC_Exported_Functions CRC Exported Functions
+ * @{
+ */
+
+/** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions.
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Initialize the CRC according to the specified parameters
+ in the CRC_InitTypeDef and create the associated handle
+ (+) DeInitialize the CRC peripheral
+ (+) Initialize the CRC MSP (MCU Specific Package)
+ (+) DeInitialize the CRC MSP
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initialize the CRC according to the specified
+ * parameters in the CRC_InitTypeDef and create the associated handle.
+ * @param hcrc CRC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc)
+{
+ /* Check the CRC handle allocation */
+ if (hcrc == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));
+
+ if (hcrc->State == HAL_CRC_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hcrc->Lock = HAL_UNLOCKED;
+ /* Init the low level hardware */
+ HAL_CRC_MspInit(hcrc);
+ }
+
+ hcrc->State = HAL_CRC_STATE_BUSY;
+
+ /* check whether or not non-default generating polynomial has been
+ * picked up by user */
+ assert_param(IS_DEFAULT_POLYNOMIAL(hcrc->Init.DefaultPolynomialUse));
+ if (hcrc->Init.DefaultPolynomialUse == DEFAULT_POLYNOMIAL_ENABLE)
+ {
+ /* initialize peripheral with default generating polynomial */
+ WRITE_REG(hcrc->Instance->POL, DEFAULT_CRC32_POLY);
+ MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, CRC_POLYLENGTH_32B);
+ }
+ else
+ {
+ /* initialize CRC peripheral with generating polynomial defined by user */
+ if (HAL_CRCEx_Polynomial_Set(hcrc, hcrc->Init.GeneratingPolynomial, hcrc->Init.CRCLength) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ }
+
+ /* check whether or not non-default CRC initial value has been
+ * picked up by user */
+ assert_param(IS_DEFAULT_INIT_VALUE(hcrc->Init.DefaultInitValueUse));
+ if (hcrc->Init.DefaultInitValueUse == DEFAULT_INIT_VALUE_ENABLE)
+ {
+ WRITE_REG(hcrc->Instance->INIT, DEFAULT_CRC_INITVALUE);
+ }
+ else
+ {
+ WRITE_REG(hcrc->Instance->INIT, hcrc->Init.InitValue);
+ }
+
+
+ /* set input data inversion mode */
+ assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(hcrc->Init.InputDataInversionMode));
+ MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, hcrc->Init.InputDataInversionMode);
+
+ /* set output data inversion mode */
+ assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(hcrc->Init.OutputDataInversionMode));
+ MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, hcrc->Init.OutputDataInversionMode);
+
+ /* makes sure the input data format (bytes, halfwords or words stream)
+ * is properly specified by user */
+ assert_param(IS_CRC_INPUTDATA_FORMAT(hcrc->InputDataFormat));
+
+ /* Change CRC peripheral state */
+ hcrc->State = HAL_CRC_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitialize the CRC peripheral.
+ * @param hcrc CRC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc)
+{
+ /* Check the CRC handle allocation */
+ if (hcrc == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));
+
+ /* Check the CRC peripheral state */
+ if (hcrc->State == HAL_CRC_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Change CRC peripheral state */
+ hcrc->State = HAL_CRC_STATE_BUSY;
+
+ /* Reset CRC calculation unit */
+ __HAL_CRC_DR_RESET(hcrc);
+
+ /* Reset IDR register content */
+ CLEAR_BIT(hcrc->Instance->IDR, CRC_IDR_IDR);
+
+ /* DeInit the low level hardware */
+ HAL_CRC_MspDeInit(hcrc);
+
+ /* Change CRC peripheral state */
+ hcrc->State = HAL_CRC_STATE_RESET;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcrc);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the CRC MSP.
+ * @param hcrc CRC handle
+ * @retval None
+ */
+__weak void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcrc);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_CRC_MspInit can be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitialize the CRC MSP.
+ * @param hcrc CRC handle
+ * @retval None
+ */
+__weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcrc);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_CRC_MspDeInit can be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions
+ * @brief management functions.
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
+ using combination of the previous CRC value and the new one.
+
+ [..] or
+
+ (+) compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
+ independently of the previous CRC value.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
+ * starting with the previously computed CRC as initialization value.
+ * @param hcrc CRC handle
+ * @param pBuffer pointer to the input data buffer, exact input data format is
+ * provided by hcrc->InputDataFormat.
+ * @param BufferLength input data buffer length (number of bytes if pBuffer
+ * type is * uint8_t, number of half-words if pBuffer type is * uint16_t,
+ * number of words if pBuffer type is * uint32_t).
+ * @note By default, the API expects a uint32_t pointer as input buffer parameter.
+ * Input buffer pointers with other types simply need to be cast in uint32_t
+ * and the API will internally adjust its input data processing based on the
+ * handle field hcrc->InputDataFormat.
+ * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
+ */
+uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
+{
+ uint32_t index; /* CRC input data buffer index */
+ uint32_t temp = 0U; /* CRC output (read from hcrc->Instance->DR register) */
+
+ /* Change CRC peripheral state */
+ hcrc->State = HAL_CRC_STATE_BUSY;
+
+ switch (hcrc->InputDataFormat)
+ {
+ case CRC_INPUTDATA_FORMAT_WORDS:
+ /* Enter Data to the CRC calculator */
+ for (index = 0U; index < BufferLength; index++)
+ {
+ hcrc->Instance->DR = pBuffer[index];
+ }
+ temp = hcrc->Instance->DR;
+ break;
+
+ case CRC_INPUTDATA_FORMAT_BYTES:
+ temp = CRC_Handle_8(hcrc, (uint8_t *)pBuffer, BufferLength);
+ break;
+
+ case CRC_INPUTDATA_FORMAT_HALFWORDS:
+ temp = CRC_Handle_16(hcrc, (uint16_t *)(void *)pBuffer, BufferLength); /* Derogation MisraC2012 R.11.5 */
+ break;
+ default:
+ break;
+ }
+
+ /* Change CRC peripheral state */
+ hcrc->State = HAL_CRC_STATE_READY;
+
+ /* Return the CRC computed value */
+ return temp;
+}
+
+/**
+ * @brief Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
+ * starting with hcrc->Instance->INIT as initialization value.
+ * @param hcrc CRC handle
+ * @param pBuffer pointer to the input data buffer, exact input data format is
+ * provided by hcrc->InputDataFormat.
+ * @param BufferLength input data buffer length (number of bytes if pBuffer
+ * type is * uint8_t, number of half-words if pBuffer type is * uint16_t,
+ * number of words if pBuffer type is * uint32_t).
+ * @note By default, the API expects a uint32_t pointer as input buffer parameter.
+ * Input buffer pointers with other types simply need to be cast in uint32_t
+ * and the API will internally adjust its input data processing based on the
+ * handle field hcrc->InputDataFormat.
+ * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
+ */
+uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
+{
+ uint32_t index; /* CRC input data buffer index */
+ uint32_t temp = 0U; /* CRC output (read from hcrc->Instance->DR register) */
+
+ /* Change CRC peripheral state */
+ hcrc->State = HAL_CRC_STATE_BUSY;
+
+ /* Reset CRC Calculation Unit (hcrc->Instance->INIT is
+ * written in hcrc->Instance->DR) */
+ __HAL_CRC_DR_RESET(hcrc);
+
+ switch (hcrc->InputDataFormat)
+ {
+ case CRC_INPUTDATA_FORMAT_WORDS:
+ /* Enter 32-bit input data to the CRC calculator */
+ for (index = 0U; index < BufferLength; index++)
+ {
+ hcrc->Instance->DR = pBuffer[index];
+ }
+ temp = hcrc->Instance->DR;
+ break;
+
+ case CRC_INPUTDATA_FORMAT_BYTES:
+ /* Specific 8-bit input data handling */
+ temp = CRC_Handle_8(hcrc, (uint8_t *)pBuffer, BufferLength);
+ break;
+
+ case CRC_INPUTDATA_FORMAT_HALFWORDS:
+ /* Specific 16-bit input data handling */
+ temp = CRC_Handle_16(hcrc, (uint16_t *)(void *)pBuffer, BufferLength); /* Derogation MisraC2012 R.11.5 */
+ break;
+
+ default:
+ break;
+ }
+
+ /* Change CRC peripheral state */
+ hcrc->State = HAL_CRC_STATE_READY;
+
+ /* Return the CRC computed value */
+ return temp;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions
+ * @brief Peripheral State functions.
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral State functions #####
+ ===============================================================================
+ [..]
+ This subsection permits to get in run-time the status of the peripheral.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the CRC handle state.
+ * @param hcrc CRC handle
+ * @retval HAL state
+ */
+HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc)
+{
+ /* Return CRC handle state */
+ return hcrc->State;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup CRC_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Enter 8-bit input data to the CRC calculator.
+ * Specific data handling to optimize processing time.
+ * @param hcrc CRC handle
+ * @param pBuffer pointer to the input data buffer
+ * @param BufferLength input data buffer length
+ * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
+ */
+static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength)
+{
+ uint32_t i; /* input data buffer index */
+ uint16_t data;
+ __IO uint16_t *pReg;
+
+ /* Processing time optimization: 4 bytes are entered in a row with a single word write,
+ * last bytes must be carefully fed to the CRC calculator to ensure a correct type
+ * handling by the peripheral */
+ for (i = 0U; i < (BufferLength / 4U); i++)
+ {
+ hcrc->Instance->DR = ((uint32_t)pBuffer[4U * i] << 24U) | \
+ ((uint32_t)pBuffer[(4U * i) + 1U] << 16U) | \
+ ((uint32_t)pBuffer[(4U * i) + 2U] << 8U) | \
+ (uint32_t)pBuffer[(4U * i) + 3U];
+ }
+ /* last bytes specific handling */
+ if ((BufferLength % 4U) != 0U)
+ {
+ if ((BufferLength % 4U) == 1U)
+ {
+ *(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[4U * i]; /* Derogation MisraC2012 R.11.5 */
+ }
+ if ((BufferLength % 4U) == 2U)
+ {
+ data = ((uint16_t)(pBuffer[4U * i]) << 8U) | (uint16_t)pBuffer[(4U * i) + 1U];
+ pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); /* Derogation MisraC2012 R.11.5 */
+ *pReg = data;
+ }
+ if ((BufferLength % 4U) == 3U)
+ {
+ data = ((uint16_t)(pBuffer[4U * i]) << 8U) | (uint16_t)pBuffer[(4U * i) + 1U];
+ pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); /* Derogation MisraC2012 R.11.5 */
+ *pReg = data;
+
+ *(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[(4U * i) + 2U]; /* Derogation MisraC2012 R.11.5 */
+ }
+ }
+
+ /* Return the CRC computed value */
+ return hcrc->Instance->DR;
+}
+
+/**
+ * @brief Enter 16-bit input data to the CRC calculator.
+ * Specific data handling to optimize processing time.
+ * @param hcrc CRC handle
+ * @param pBuffer pointer to the input data buffer
+ * @param BufferLength input data buffer length
+ * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
+ */
+static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength)
+{
+ uint32_t i; /* input data buffer index */
+ __IO uint16_t *pReg;
+
+ /* Processing time optimization: 2 HalfWords are entered in a row with a single word write,
+ * in case of odd length, last HalfWord must be carefully fed to the CRC calculator to ensure
+ * a correct type handling by the peripheral */
+ for (i = 0U; i < (BufferLength / 2U); i++)
+ {
+ hcrc->Instance->DR = ((uint32_t)pBuffer[2U * i] << 16U) | (uint32_t)pBuffer[(2U * i) + 1U];
+ }
+ if ((BufferLength % 2U) != 0U)
+ {
+ pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); /* Derogation MisraC2012 R.11.5 */
+ *pReg = pBuffer[2U * i];
+ }
+
+ /* Return the CRC computed value */
+ return hcrc->Instance->DR;
+}
+
+/**
+ * @}
+ */
+
+#endif /* HAL_CRC_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_crc_ex.c b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_crc_ex.c
new file mode 100644
index 0000000000..e735dc957b
--- /dev/null
+++ b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_crc_ex.c
@@ -0,0 +1,223 @@
+/**
+ ******************************************************************************
+ * @file stm32c0xx_hal_crc_ex.c
+ * @author MCD Application Team
+ * @brief Extended CRC HAL module driver.
+ * This file provides firmware functions to manage the extended
+ * functionalities of the CRC peripheral.
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2022 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+================================================================================
+ ##### How to use this driver #####
+================================================================================
+ [..]
+ (+) Set user-defined generating polynomial through HAL_CRCEx_Polynomial_Set()
+ (+) Configure Input or Output data inversion
+
+ @endverbatim
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32c0xx_hal.h"
+
+/** @addtogroup STM32C0xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup CRCEx CRCEx
+ * @brief CRC Extended HAL module driver
+ * @{
+ */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup CRCEx_Exported_Functions CRC Extended Exported Functions
+ * @{
+ */
+
+/** @defgroup CRCEx_Exported_Functions_Group1 Extended Initialization/de-initialization functions
+ * @brief Extended Initialization and Configuration functions.
+ *
+@verbatim
+ ===============================================================================
+ ##### Extended configuration functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Configure the generating polynomial
+ (+) Configure the input data inversion
+ (+) Configure the output data inversion
+
+@endverbatim
+ * @{
+ */
+
+
+/**
+ * @brief Initialize the CRC polynomial if different from default one.
+ * @param hcrc CRC handle
+ * @param Pol CRC generating polynomial (7, 8, 16 or 32-bit long).
+ * This parameter is written in normal representation, e.g.
+ * @arg for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65
+ * @arg for a polynomial of degree 16, X^16 + X^12 + X^5 + 1 is written 0x1021
+ * @param PolyLength CRC polynomial length.
+ * This parameter can be one of the following values:
+ * @arg @ref CRC_POLYLENGTH_7B 7-bit long CRC (generating polynomial of degree 7)
+ * @arg @ref CRC_POLYLENGTH_8B 8-bit long CRC (generating polynomial of degree 8)
+ * @arg @ref CRC_POLYLENGTH_16B 16-bit long CRC (generating polynomial of degree 16)
+ * @arg @ref CRC_POLYLENGTH_32B 32-bit long CRC (generating polynomial of degree 32)
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t msb = 31U; /* polynomial degree is 32 at most, so msb is initialized to max value */
+
+ /* Check the parameters */
+ assert_param(IS_CRC_POL_LENGTH(PolyLength));
+
+ /* check polynomial definition vs polynomial size:
+ * polynomial length must be aligned with polynomial
+ * definition. HAL_ERROR is reported if Pol degree is
+ * larger than that indicated by PolyLength.
+ * Look for MSB position: msb will contain the degree of
+ * the second to the largest polynomial member. E.g., for
+ * X^7 + X^6 + X^5 + X^2 + 1, msb = 6. */
+ while ((msb-- > 0U) && ((Pol & ((uint32_t)(0x1U) << (msb & 0x1FU))) == 0U))
+ {
+ }
+
+ switch (PolyLength)
+ {
+ case CRC_POLYLENGTH_7B:
+ if (msb >= HAL_CRC_LENGTH_7B)
+ {
+ status = HAL_ERROR;
+ }
+ break;
+ case CRC_POLYLENGTH_8B:
+ if (msb >= HAL_CRC_LENGTH_8B)
+ {
+ status = HAL_ERROR;
+ }
+ break;
+ case CRC_POLYLENGTH_16B:
+ if (msb >= HAL_CRC_LENGTH_16B)
+ {
+ status = HAL_ERROR;
+ }
+ break;
+
+ case CRC_POLYLENGTH_32B:
+ /* no polynomial definition vs. polynomial length issue possible */
+ break;
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+ if (status == HAL_OK)
+ {
+ /* set generating polynomial */
+ WRITE_REG(hcrc->Instance->POL, Pol);
+
+ /* set generating polynomial size */
+ MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, PolyLength);
+ }
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Set the Reverse Input data mode.
+ * @param hcrc CRC handle
+ * @param InputReverseMode Input Data inversion mode.
+ * This parameter can be one of the following values:
+ * @arg @ref CRC_INPUTDATA_INVERSION_NONE no change in bit order (default value)
+ * @arg @ref CRC_INPUTDATA_INVERSION_BYTE Byte-wise bit reversal
+ * @arg @ref CRC_INPUTDATA_INVERSION_HALFWORD HalfWord-wise bit reversal
+ * @arg @ref CRC_INPUTDATA_INVERSION_WORD Word-wise bit reversal
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode)
+{
+ /* Check the parameters */
+ assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(InputReverseMode));
+
+ /* Change CRC peripheral state */
+ hcrc->State = HAL_CRC_STATE_BUSY;
+
+ /* set input data inversion mode */
+ MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, InputReverseMode);
+ /* Change CRC peripheral state */
+ hcrc->State = HAL_CRC_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Set the Reverse Output data mode.
+ * @param hcrc CRC handle
+ * @param OutputReverseMode Output Data inversion mode.
+ * This parameter can be one of the following values:
+ * @arg @ref CRC_OUTPUTDATA_INVERSION_DISABLE no CRC inversion (default value)
+ * @arg @ref CRC_OUTPUTDATA_INVERSION_ENABLE bit-level inversion (e.g. for a 8-bit CRC: 0xB5 becomes 0xAD)
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode)
+{
+ /* Check the parameters */
+ assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(OutputReverseMode));
+
+ /* Change CRC peripheral state */
+ hcrc->State = HAL_CRC_STATE_BUSY;
+
+ /* set output data inversion mode */
+ MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, OutputReverseMode);
+
+ /* Change CRC peripheral state */
+ hcrc->State = HAL_CRC_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+
+
+
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+
+#endif /* HAL_CRC_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c
new file mode 100644
index 0000000000..17731b4916
--- /dev/null
+++ b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c
@@ -0,0 +1,1079 @@
+/**
+ ******************************************************************************
+ * @file stm32c0xx_hal_dma.c
+ * @author MCD Application Team
+ * @brief DMA HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Direct Memory Access (DMA) peripheral:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral State and errors functions
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2022 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ (#) Enable and configure the peripheral to be connected to the DMA Channel
+ (except for internal SRAM / FLASH memories: no initialization is
+ necessary). Please refer to the Reference manual for connection between peripherals
+ and DMA requests.
+
+ (#) For a given Channel, program the required configuration through the following parameters:
+ Channel request, Transfer Direction, Source and Destination data formats,
+ Circular or Normal mode, Channel Priority level, Source and Destination Increment mode
+ using HAL_DMA_Init() function.
+
+ Prior to HAL_DMA_Init the CLK shall be enabled for both DMA & DMAMUX
+ thanks to:
+ DMA1 : __HAL_RCC_DMA1_CLK_ENABLE();
+
+ (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error
+ detection.
+
+ (#) Use HAL_DMA_Abort() function to abort the current transfer
+
+ -@- In Memory-to-Memory transfer mode, Circular mode is not allowed.
+ *** Polling mode IO operation ***
+ =================================
+ [..]
+ (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source
+ address and destination address and the Length of data to be transferred
+ (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this
+ case a fixed Timeout can be configured by User depending from his application.
+
+ *** Interrupt mode IO operation ***
+ ===================================
+ [..]
+ (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
+ (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
+ (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of
+ Source address and destination address and the Length of data to be transferred.
+ In this case the DMA interrupt is configured
+ (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
+ (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can
+ add his own function by customization of function pointer XferCpltCallback and
+ XferErrorCallback (i.e. a member of DMA handle structure).
+
+ *** DMA HAL driver macros list ***
+ =============================================
+ [..]
+ Below the list of most used macros in DMA HAL driver.
+
+ (+) __HAL_DMA_ENABLE: Enable the specified DMA Channel.
+ (+) __HAL_DMA_DISABLE: Disable the specified DMA Channel.
+ (+) __HAL_DMA_GET_FLAG: Get the DMA Channel pending flags.
+ (+) __HAL_DMA_CLEAR_FLAG: Clear the DMA Channel pending flags.
+ (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Channel interrupts.
+ (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Channel interrupts.
+ (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Channel interrupt has occurred or not.
+
+ [..]
+ (@) You can refer to the DMA HAL driver header file for more useful macros
+
+ @endverbatim
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32c0xx_hal.h"
+
+/** @addtogroup STM32C0xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup DMA DMA
+ * @brief DMA HAL module driver
+ * @{
+ */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+
+/** @defgroup DMA_Private_Functions DMA Private Functions
+ * @{
+ */
+static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
+static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma);
+static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma);
+
+/**
+ * @}
+ */
+
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup DMA_Exported_Functions DMA Exported Functions
+ * @{
+ */
+
+/** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and de-initialization functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..]
+ This section provides functions allowing to initialize the DMA Channel source
+ and destination addresses, incrementation and data sizes, transfer direction,
+ circular/normal mode selection, memory-to-memory mode selection and Channel priority value.
+ [..]
+ The HAL_DMA_Init() function follows the DMA configuration procedures as described in
+ reference manual.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initialize the DMA according to the specified
+ * parameters in the DMA_InitTypeDef and initialize the associated handle.
+ * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Channel.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
+{
+ /* Check the DMA handle allocation */
+ if (hdma == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
+ assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));
+ assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc));
+ assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc));
+ assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));
+ assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));
+ assert_param(IS_DMA_MODE(hdma->Init.Mode));
+ assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
+
+ /* calculation of the channel index */
+ hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - \
+ (uint32_t)DMA1_Channel1)) << 2U;
+
+ /* Change DMA peripheral state */
+ hdma->State = HAL_DMA_STATE_BUSY;
+
+ /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR and MEM2MEM bits */
+ CLEAR_BIT(hdma->Instance->CCR, (DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \
+ DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | \
+ DMA_CCR_DIR | DMA_CCR_MEM2MEM));
+
+ /* Set the DMA Channel configuration */
+ SET_BIT(hdma->Instance->CCR, (hdma->Init.Direction | \
+ hdma->Init.PeriphInc | hdma->Init.MemInc | \
+ hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | \
+ hdma->Init.Mode | hdma->Init.Priority));
+
+ /* Initialize parameters for DMAMUX channel :
+ DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask
+ */
+ DMA_CalcDMAMUXChannelBaseAndMask(hdma);
+
+ if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)
+ {
+ /* if memory to memory force the request to 0*/
+ hdma->Init.Request = DMA_REQUEST_MEM2MEM;
+ }
+
+ /* Set peripheral request to DMAMUX channel */
+ hdma->DMAmuxChannel->CCR = (hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID);
+
+ /* Clear the DMAMUX synchro overrun flag */
+ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
+
+ if (((hdma->Init.Request > 0UL) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3)))
+ {
+ /* Initialize parameters for DMAMUX request generator :
+ DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask
+ */
+ DMA_CalcDMAMUXRequestGenBaseAndMask(hdma);
+
+ /* Reset the DMAMUX request generator register*/
+ hdma->DMAmuxRequestGen->RGCR = 0U;
+
+ /* Clear the DMAMUX request generator overrun flag */
+ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
+ }
+ else
+ {
+ hdma->DMAmuxRequestGen = 0U;
+ hdma->DMAmuxRequestGenStatus = 0U;
+ hdma->DMAmuxRequestGenStatusMask = 0U;
+ }
+
+ /* Initialize the error code */
+ hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+
+ /* Initialize the DMA state*/
+ hdma->State = HAL_DMA_STATE_READY;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hdma);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitialize the DMA peripheral.
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Channel.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
+{
+ /* Check the DMA handle allocation */
+ if (NULL == hdma)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
+
+ /* Disable the selected DMA Channelx */
+ __HAL_DMA_DISABLE(hdma);
+
+ /* calculation of the channel index */
+ hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - \
+ (uint32_t)DMA1_Channel1)) << 2U;
+
+ /* Reset DMA Channel control register */
+ hdma->Instance->CCR = 0U;
+
+ /* Clear all flags */
+ __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_GI1 << (hdma->ChannelIndex & 0x1cU)));
+
+ /* Initialize parameters for DMAMUX channel :
+ DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask */
+
+ DMA_CalcDMAMUXChannelBaseAndMask(hdma);
+
+ /* Reset the DMAMUX channel that corresponds to the DMA channel */
+ hdma->DMAmuxChannel->CCR = 0U;
+
+ /* Clear the DMAMUX synchro overrun flag */
+ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
+
+ /* Reset Request generator parameters if any */
+ if (((hdma->Init.Request > 0UL) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3)))
+ {
+ /* Initialize parameters for DMAMUX request generator :
+ DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask
+ */
+ DMA_CalcDMAMUXRequestGenBaseAndMask(hdma);
+
+ /* Reset the DMAMUX request generator register*/
+ hdma->DMAmuxRequestGen->RGCR = 0U;
+
+ /* Clear the DMAMUX request generator overrun flag */
+ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
+ }
+
+ /* Clean callbacks */
+ hdma->XferCpltCallback = NULL;
+ hdma->XferHalfCpltCallback = NULL;
+ hdma->XferErrorCallback = NULL;
+ hdma->XferAbortCallback = NULL;
+
+ hdma->DMAmuxRequestGen = 0U;
+ hdma->DMAmuxRequestGenStatus = 0U;
+ hdma->DMAmuxRequestGenStatusMask = 0U;
+
+ /* Initialize the error code */
+ hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+
+ /* Initialize the DMA state */
+ hdma->State = HAL_DMA_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hdma);
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions
+ * @brief Input and Output operation functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Configure the source, destination address and data length and Start DMA transfer
+ (+) Configure the source, destination address and data length and
+ Start DMA transfer with interrupt
+ (+) Abort DMA transfer
+ (+) Poll for transfer complete
+ (+) Handle DMA interrupt request
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Start the DMA Transfer.
+ * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Channel.
+ * @param SrcAddress The source memory Buffer address
+ * @param DstAddress The destination memory Buffer address
+ * @param DataLength The length of data to be transferred from source to destination
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_DMA_BUFFER_SIZE(DataLength));
+
+ /* Process locked */
+ __HAL_LOCK(hdma);
+
+ if (HAL_DMA_STATE_READY == hdma->State)
+ {
+ /* Change DMA peripheral state */
+ hdma->State = HAL_DMA_STATE_BUSY;
+ hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+
+ /* Disable the peripheral */
+ __HAL_DMA_DISABLE(hdma);
+
+ /* Configure the source, destination address and the data length & clear flags*/
+ DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
+
+ /* Enable the Peripheral */
+ __HAL_DMA_ENABLE(hdma);
+ }
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
+ status = HAL_BUSY;
+ }
+
+ /* Process locked */
+ __HAL_UNLOCK(hdma);
+
+ return status;
+}
+
+/**
+ * @brief Start the DMA Transfer with interrupt enabled.
+ * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Channel.
+ * @param SrcAddress The source memory Buffer address
+ * @param DstAddress The destination memory Buffer address
+ * @param DataLength The length of data to be transferred from source to destination
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress,
+ uint32_t DataLength)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_DMA_BUFFER_SIZE(DataLength));
+
+ /* Process locked */
+ __HAL_LOCK(hdma);
+
+ if (HAL_DMA_STATE_READY == hdma->State)
+ {
+ /* Change DMA peripheral state */
+ hdma->State = HAL_DMA_STATE_BUSY;
+ hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+
+ /* Disable the peripheral */
+ __HAL_DMA_DISABLE(hdma);
+
+ /* Configure the source, destination address and the data length & clear flags*/
+ DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
+
+ /* Enable the transfer complete interrupt */
+ /* Enable the transfer Error interrupt */
+ if (NULL != hdma->XferHalfCpltCallback)
+ {
+ /* Enable the Half transfer complete interrupt as well */
+ __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
+ }
+ else
+ {
+ __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
+ __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE));
+ }
+
+ /* Check if DMAMUX Synchronization is enabled*/
+ if ((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U)
+ {
+ /* Enable DMAMUX sync overrun IT*/
+ hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE;
+ }
+
+ if (hdma->DMAmuxRequestGen != 0U)
+ {
+ /* if using DMAMUX request generator, enable the DMAMUX request generator overrun IT*/
+ /* enable the request gen overrun IT*/
+ hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE;
+ }
+
+ /* Enable the Peripheral */
+ __HAL_DMA_ENABLE(hdma);
+ }
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
+
+ /* Remain BUSY */
+ status = HAL_BUSY;
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdma);
+
+ return status;
+}
+
+/**
+ * @brief Abort the DMA Transfer.
+ * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Channel.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
+{
+ /* Check the DMA peripheral handle */
+ if (NULL == hdma)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the DMA peripheral state */
+ if (hdma->State != HAL_DMA_STATE_BUSY)
+ {
+ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
+
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Disable DMA IT */
+ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
+
+ /* disable the DMAMUX sync overrun IT*/
+ hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
+
+ /* Disable the channel */
+ __HAL_DMA_DISABLE(hdma);
+
+ /* Clear all flags */
+ __HAL_DMA_CLEAR_FLAG(hdma, ((DMA_FLAG_GI1) << (hdma->ChannelIndex & 0x1cU)));
+
+ /* Clear the DMAMUX synchro overrun flag */
+ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
+
+ if (hdma->DMAmuxRequestGen != 0U)
+ {
+ /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/
+ /* disable the request gen overrun IT*/
+ hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
+
+ /* Clear the DMAMUX request generator overrun flag */
+ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
+ }
+
+ /* Change the DMA state */
+ hdma->State = HAL_DMA_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Aborts the DMA Transfer in Interrupt mode.
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Stream.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process Unlocked/locked */
+ __HAL_UNLOCK(hdma);
+ __HAL_LOCK(hdma);
+
+ if (HAL_DMA_STATE_BUSY != hdma->State)
+ {
+ /* no transfer ongoing */
+ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
+
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Disable DMA IT */
+ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
+
+ /* Disable the channel */
+ __HAL_DMA_DISABLE(hdma);
+
+ /* disable the DMAMUX sync overrun IT*/
+ hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
+
+ /* Clear all flags */
+ __HAL_DMA_CLEAR_FLAG(hdma, ((DMA_FLAG_GI1) << (hdma->ChannelIndex & 0x1cU)));
+
+ /* Clear the DMAMUX synchro overrun flag */
+ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
+
+ if (hdma->DMAmuxRequestGen != 0U)
+ {
+ /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/
+ /* disable the request gen overrun IT*/
+ hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
+
+ /* Clear the DMAMUX request generator overrun flag */
+ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
+ }
+
+ /* Change the DMA state */
+ hdma->State = HAL_DMA_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
+
+ /* Call User Abort callback */
+ if (hdma->XferAbortCallback != NULL)
+ {
+ hdma->XferAbortCallback(hdma);
+ }
+ }
+ return status;
+}
+
+/**
+ * @brief Polling for transfer complete.
+ * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Channel.
+ * @param CompleteLevel Specifies the DMA level complete.
+ * @param Timeout Timeout duration.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel,
+ uint32_t Timeout)
+{
+ uint32_t temp;
+ uint32_t tickstart;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdma);
+
+ if (HAL_DMA_STATE_BUSY != hdma->State)
+ {
+ /* no transfer ongoing */
+ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
+ __HAL_UNLOCK(hdma);
+ return HAL_ERROR;
+ }
+
+ /* Polling mode not supported in circular mode */
+ if ((hdma->Instance->CCR & DMA_CCR_CIRC) != 0U)
+ {
+ hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
+ return HAL_ERROR;
+ }
+
+ /* Get the level transfer complete flag */
+ if (HAL_DMA_FULL_TRANSFER == CompleteLevel)
+ {
+ /* Transfer Complete flag */
+ temp = DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1cU);
+ }
+ else
+ {
+ /* Half Transfer Complete flag */
+ temp = DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1cU);
+ }
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while (0U == __HAL_DMA_GET_FLAG(hdma, temp))
+ {
+ if (0U != __HAL_DMA_GET_FLAG(hdma, (DMA_FLAG_TE1 << (hdma->ChannelIndex & 0x1cU))))
+ {
+ /* When a DMA transfer error occurs */
+ /* A hardware clear of its EN bits is performed */
+ /* Clear all flags */
+ __HAL_DMA_CLEAR_FLAG(hdma, ((DMA_FLAG_GI1) << (hdma->ChannelIndex & 0x1cU)));
+
+ /* Update error code */
+ hdma->ErrorCode = HAL_DMA_ERROR_TE;
+
+ /* Change the DMA state */
+ hdma->State = HAL_DMA_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
+
+ return HAL_ERROR;
+ }
+ /* Check for the Timeout */
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+ {
+ /* Update error code */
+ hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
+
+ /* Change the DMA state */
+ hdma->State = HAL_DMA_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
+
+ return HAL_ERROR;
+ }
+ }
+ }
+
+ /*Check for DMAMUX Request generator (if used) overrun status */
+ if (hdma->DMAmuxRequestGen != 0U)
+ {
+ /* if using DMAMUX request generator Check for DMAMUX request generator overrun */
+ if ((hdma->DMAmuxRequestGenStatus->RGSR & hdma->DMAmuxRequestGenStatusMask) != 0U)
+ {
+ /* Disable the request gen overrun interrupt */
+ hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE;
+
+ /* Clear the DMAMUX request generator overrun flag */
+ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
+
+ /* Update error code */
+ hdma->ErrorCode |= HAL_DMA_ERROR_REQGEN;
+ }
+ }
+
+ /* Check for DMAMUX Synchronization overrun */
+ if ((hdma->DMAmuxChannelStatus->CSR & hdma->DMAmuxChannelStatusMask) != 0U)
+ {
+ /* Clear the DMAMUX synchro overrun flag */
+ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
+
+ /* Update error code */
+ hdma->ErrorCode |= HAL_DMA_ERROR_SYNC;
+ }
+
+ if (HAL_DMA_FULL_TRANSFER == CompleteLevel)
+ {
+ /* Clear the transfer complete flag */
+ __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1cU)));
+
+ /* The selected Channelx EN bit is cleared (DMA is disabled and
+ all transfers are complete) */
+ hdma->State = HAL_DMA_STATE_READY;
+ }
+ else
+ {
+ /* Clear the half transfer complete flag */
+ __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1cU)));
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdma);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle DMA interrupt request.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Channel.
+ * @retval None
+ */
+void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
+{
+ uint32_t flag_it = DMA1->ISR;
+ uint32_t source_it = hdma->Instance->CCR;
+
+ /* Half Transfer Complete Interrupt management ******************************/
+ if (((flag_it & (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1cU))) != 0U) && ((source_it & DMA_IT_HT) != 0U))
+ {
+ /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
+ if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
+ {
+ /* Disable the half transfer interrupt */
+ __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
+ }
+ /* Clear the half transfer complete flag */
+ __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1cU)));
+
+ /* DMA peripheral state is not updated in Half Transfer */
+ /* but in Transfer Complete case */
+
+ if (hdma->XferHalfCpltCallback != NULL)
+ {
+ /* Half transfer callback */
+ hdma->XferHalfCpltCallback(hdma);
+ }
+ }
+
+ /* Transfer Complete Interrupt management ***********************************/
+ else if ((0U != (flag_it & (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1cU)))) && (0U != (source_it & DMA_IT_TC)))
+ {
+ if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
+ {
+ /* Disable the transfer complete and error interrupt */
+ __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC);
+
+ /* Change the DMA state */
+ hdma->State = HAL_DMA_STATE_READY;
+ }
+ /* Clear the transfer complete flag */
+ __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1cU)));
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
+
+ if (hdma->XferCpltCallback != NULL)
+ {
+ /* Transfer complete callback */
+ hdma->XferCpltCallback(hdma);
+ }
+ }
+
+ /* Transfer Error Interrupt management **************************************/
+ else if (((flag_it & (DMA_FLAG_TE1 << (hdma->ChannelIndex & 0x1cU))) != 0U) && ((source_it & DMA_IT_TE) != 0U))
+ {
+ /* When a DMA transfer error occurs */
+ /* A hardware clear of its EN bits is performed */
+ /* Disable ALL DMA IT */
+ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
+
+ /* Clear all flags */
+ __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_GI1 << (hdma->ChannelIndex & 0x1cU)));
+
+ /* Update error code */
+ hdma->ErrorCode = HAL_DMA_ERROR_TE;
+
+ /* Change the DMA state */
+ hdma->State = HAL_DMA_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
+
+ if (hdma->XferErrorCallback != NULL)
+ {
+ /* Transfer error callback */
+ hdma->XferErrorCallback(hdma);
+ }
+ }
+ else
+ {
+ /* Nothing To Do */
+ }
+ return;
+}
+
+/**
+ * @brief Register callbacks
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Stream.
+ * @param CallbackID User Callback identifier
+ * a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
+ * @param pCallback pointer to private callback function which has pointer to
+ * a DMA_HandleTypeDef structure as parameter.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID,
+ void (* pCallback)(DMA_HandleTypeDef *_hdma))
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hdma);
+
+ if (HAL_DMA_STATE_READY == hdma->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_DMA_XFER_CPLT_CB_ID:
+ hdma->XferCpltCallback = pCallback;
+ break;
+
+ case HAL_DMA_XFER_HALFCPLT_CB_ID:
+ hdma->XferHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_DMA_XFER_ERROR_CB_ID:
+ hdma->XferErrorCallback = pCallback;
+ break;
+
+ case HAL_DMA_XFER_ABORT_CB_ID:
+ hdma->XferAbortCallback = pCallback;
+ break;
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hdma);
+
+ return status;
+}
+
+/**
+ * @brief UnRegister callbacks
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Stream.
+ * @param CallbackID User Callback identifier
+ * a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hdma);
+
+ if (HAL_DMA_STATE_READY == hdma->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_DMA_XFER_CPLT_CB_ID:
+ hdma->XferCpltCallback = NULL;
+ break;
+
+ case HAL_DMA_XFER_HALFCPLT_CB_ID:
+ hdma->XferHalfCpltCallback = NULL;
+ break;
+
+ case HAL_DMA_XFER_ERROR_CB_ID:
+ hdma->XferErrorCallback = NULL;
+ break;
+
+ case HAL_DMA_XFER_ABORT_CB_ID:
+ hdma->XferAbortCallback = NULL;
+ break;
+
+ case HAL_DMA_XFER_ALL_CB_ID:
+ hdma->XferCpltCallback = NULL;
+ hdma->XferHalfCpltCallback = NULL;
+ hdma->XferErrorCallback = NULL;
+ hdma->XferAbortCallback = NULL;
+ break;
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hdma);
+
+ return status;
+}
+
+/**
+ * @}
+ */
+
+
+
+/** @defgroup DMA_Exported_Functions_Group3 Peripheral State and Errors functions
+ * @brief Peripheral State and Errors functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral State and Errors functions #####
+ ===============================================================================
+ [..]
+ This subsection provides functions allowing to
+ (+) Check the DMA state
+ (+) Get error code
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the DMA handle state.
+ * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Channel.
+ * @retval HAL state
+ */
+HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
+{
+ /* Return DMA handle state */
+ return hdma->State;
+}
+
+/**
+ * @brief Return the DMA error code.
+ * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Channel.
+ * @retval DMA Error Code
+ */
+uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
+{
+ return hdma->ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Sets the DMA Transfer parameter.
+ * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Channel.
+ * @param SrcAddress The source memory Buffer address
+ * @param DstAddress The destination memory Buffer address
+ * @param DataLength The length of data to be transferred from source to destination
+ * @retval HAL status
+ */
+static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
+{
+ /* Clear the DMAMUX synchro overrun flag */
+ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
+
+ if (hdma->DMAmuxRequestGen != 0U)
+ {
+ /* Clear the DMAMUX request generator overrun flag */
+ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
+ }
+
+ /* Clear all flags */
+ __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_GI1 << (hdma->ChannelIndex & 0x1cU)));
+
+ /* Configure DMA Channel data length */
+ hdma->Instance->CNDTR = DataLength;
+
+ /* Peripheral to Memory */
+ if ((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
+ {
+ /* Configure DMA Channel destination address */
+ hdma->Instance->CPAR = DstAddress;
+
+ /* Configure DMA Channel source address */
+ hdma->Instance->CMAR = SrcAddress;
+ }
+ /* Memory to Peripheral */
+ else
+ {
+ /* Configure DMA Channel source address */
+ hdma->Instance->CPAR = SrcAddress;
+
+ /* Configure DMA Channel destination address */
+ hdma->Instance->CMAR = DstAddress;
+ }
+}
+
+/**
+ * @brief Updates the DMA handle with the DMAMUX channel and status mask depending on stream number
+ * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Stream.
+ * @retval None
+ */
+static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma)
+{
+ uint32_t channel_number;
+
+ channel_number = (((uint32_t)hdma->Instance & 0xFFU) - 8U) / 20U;
+ hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)(uint32_t)((uint32_t)DMAMUX1_Channel0 + \
+ ((hdma->ChannelIndex >> 2U) * \
+ ((uint32_t)DMAMUX1_Channel1 - \
+ (uint32_t)DMAMUX1_Channel0)));
+ hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus;
+ hdma->DMAmuxChannelStatusMask = 1UL << (channel_number & 0x1cU);
+}
+
+/**
+ * @brief Updates the DMA handle with the DMAMUX request generator params
+ * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Stream.
+ * @retval None
+ */
+
+static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma)
+{
+ uint32_t request = hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID;
+
+ /* DMA Channels are connected to DMAMUX1 request generator blocks*/
+ hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_RequestGenerator0) + \
+ ((request - 1U) * 4U)));
+
+ hdma->DMAmuxRequestGenStatus = DMAMUX1_RequestGenStatus;
+
+ /* here "Request" is either DMA_REQUEST_GENERATOR0 to 4, i.e. <= 4*/
+ hdma->DMAmuxRequestGenStatusMask = 1UL << ((request - 1U) & 0x3U);
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_DMA_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.c b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.c
new file mode 100644
index 0000000000..1df7b617ee
--- /dev/null
+++ b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.c
@@ -0,0 +1,298 @@
+/**
+ ******************************************************************************
+ * @file stm32c0xx_hal_dma_ex.c
+ * @author MCD Application Team
+ * @brief DMA Extension HAL module driver
+ * This file provides firmware functions to manage the following
+ * functionalities of the DMA Extension peripheral:
+ * + Extended features functions
+ *
+ @verbatim
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2022 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ The DMA Extension HAL driver can be used as follows:
+
+ (+) Configure the DMA_MUX Synchronization Block using HAL_DMAEx_ConfigMuxSync function.
+ (+) Configure the DMA_MUX Request Generator Block using HAL_DMAEx_ConfigMuxRequestGenerator function.
+ Functions HAL_DMAEx_EnableMuxRequestGenerator and HAL_DMAEx_DisableMuxRequestGenerator can then be used
+ to respectively enable/disable the request generator.
+
+ (+) To handle the DMAMUX Interrupts, the function HAL_DMAEx_MUX_IRQHandler should be called from
+ the DMAMUX IRQ handler i.e DMAMUX1_OVR_IRQHandler.
+ As only one interrupt line is available for all DMAMUX channels and request generators , HAL_DMAEx_MUX_IRQHandler
+ should be called with, as parameter, the appropriate DMA handle as many as used DMAs in the user project
+ (exception done if a given DMA is not using the DMAMUX SYNC block neither a request generator)
+
+ @endverbatim
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32c0xx_hal.h"
+
+/** @addtogroup STM32C0xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup DMAEx DMAEx
+ * @brief DMA Extended HAL module driver
+ * @{
+ */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private Constants ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+
+/** @defgroup DMAEx_Exported_Functions DMAEx Exported Functions
+ * @{
+ */
+
+/** @defgroup DMAEx_Exported_Functions_Group1 DMAEx Extended features functions
+ * @brief Extended features functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Extended features functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+
+ (+) Configure the DMA_MUX Synchronization Block using HAL_DMAEx_ConfigMuxSync function.
+ (+) Configure the DMA_MUX Request Generator Block using HAL_DMAEx_ConfigMuxRequestGenerator function.
+ Functions HAL_DMAEx_EnableMuxRequestGenerator and HAL_DMAEx_DisableMuxRequestGenerator can then be used
+ to respectively enable/disable the request generator.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configure the DMAMUX synchronization parameters for a given DMA channel (instance).
+ * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA channel.
+ * @param pSyncConfig Pointer to HAL_DMA_MuxSyncConfigTypeDef : contains the DMAMUX synchronization parameters
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig)
+{
+ /* Check the parameters */
+ assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
+
+ assert_param(IS_DMAMUX_SYNC_SIGNAL_ID(pSyncConfig->SyncSignalID));
+
+ assert_param(IS_DMAMUX_SYNC_POLARITY(pSyncConfig-> SyncPolarity));
+ assert_param(IS_DMAMUX_SYNC_STATE(pSyncConfig->SyncEnable));
+ assert_param(IS_DMAMUX_SYNC_EVENT(pSyncConfig->EventEnable));
+ assert_param(IS_DMAMUX_SYNC_REQUEST_NUMBER(pSyncConfig->RequestNumber));
+
+ /*Check if the DMA state is ready */
+ if (hdma->State == HAL_DMA_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hdma);
+
+ /* Set the new synchronization parameters (and keep the request ID filled during the Init)*/
+ MODIFY_REG(hdma->DMAmuxChannel->CCR, \
+ (~DMAMUX_CxCR_DMAREQ_ID), \
+ ((pSyncConfig->SyncSignalID) << DMAMUX_CxCR_SYNC_ID_Pos) | ((pSyncConfig->RequestNumber - 1U) << \
+ DMAMUX_CxCR_NBREQ_Pos) | \
+ pSyncConfig->SyncPolarity | \
+ ((uint32_t)pSyncConfig->SyncEnable << \
+ DMAMUX_CxCR_SE_Pos) | \
+ ((uint32_t)pSyncConfig->EventEnable << \
+ DMAMUX_CxCR_EGE_Pos));
+
+ /* Process UnLocked */
+ __HAL_UNLOCK(hdma);
+
+ return HAL_OK;
+ }
+ else
+ {
+ /*DMA State not Ready*/
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Configure the DMAMUX request generator block used by the given DMA channel (instance).
+ * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA channel.
+ * @param pRequestGeneratorConfig Pointer to HAL_DMA_MuxRequestGeneratorConfigTypeDef :
+ * contains the request generator parameters.
+ *
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator(DMA_HandleTypeDef *hdma,
+ HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig)
+{
+ /* Check the parameters */
+ assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
+
+ assert_param(IS_DMAMUX_REQUEST_GEN_SIGNAL_ID(pRequestGeneratorConfig->SignalID));
+ assert_param(IS_DMAMUX_REQUEST_GEN_POLARITY(pRequestGeneratorConfig->Polarity));
+ assert_param(IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(pRequestGeneratorConfig->RequestNumber));
+
+ /* check if the DMA state is ready
+ and DMA is using a DMAMUX request generator block
+ */
+ if ((hdma->State == HAL_DMA_STATE_READY) && (hdma->DMAmuxRequestGen != 0U))
+ {
+ /* Process Locked */
+ __HAL_LOCK(hdma);
+
+ /* Set the request generator new parameters*/
+ hdma->DMAmuxRequestGen->RGCR = pRequestGeneratorConfig->SignalID | \
+ ((pRequestGeneratorConfig->RequestNumber - 1U) << DMAMUX_RGxCR_GNBREQ_Pos) | \
+ pRequestGeneratorConfig->Polarity;
+ /* Process UnLocked */
+ __HAL_UNLOCK(hdma);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Enable the DMAMUX request generator block used by the given DMA channel (instance).
+ * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA channel.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator(DMA_HandleTypeDef *hdma)
+{
+ /* Check the parameters */
+ assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
+
+ /* check if the DMA state is ready
+ and DMA is using a DMAMUX request generator block
+ */
+ if ((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != 0))
+ {
+
+ /* Enable the request generator*/
+ hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_GE;
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Disable the DMAMUX request generator block used by the given DMA channel (instance).
+ * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA channel.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator(DMA_HandleTypeDef *hdma)
+{
+ /* Check the parameters */
+ assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
+
+ /* check if the DMA state is ready
+ and DMA is using a DMAMUX request generator block
+ */
+ if ((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != 0))
+ {
+
+ /* Disable the request generator*/
+ hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_GE;
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Handles DMAMUX interrupt request.
+ * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA channel.
+ * @retval None
+ */
+void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma)
+{
+ /* Check for DMAMUX Synchronization overrun */
+ if ((hdma->DMAmuxChannelStatus->CSR & hdma->DMAmuxChannelStatusMask) != 0U)
+ {
+ /* Disable the synchro overrun interrupt */
+ hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
+
+ /* Clear the DMAMUX synchro overrun flag */
+ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
+
+ /* Update error code */
+ hdma->ErrorCode |= HAL_DMA_ERROR_SYNC;
+
+ if (hdma->XferErrorCallback != NULL)
+ {
+ /* Transfer error callback */
+ hdma->XferErrorCallback(hdma);
+ }
+ }
+
+ if (hdma->DMAmuxRequestGen != 0)
+ {
+ /* if using a DMAMUX request generator block Check for DMAMUX request generator overrun */
+ if ((hdma->DMAmuxRequestGenStatus->RGSR & hdma->DMAmuxRequestGenStatusMask) != 0U)
+ {
+ /* Disable the request gen overrun interrupt */
+ hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
+
+ /* Clear the DMAMUX request generator overrun flag */
+ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
+
+ /* Update error code */
+ hdma->ErrorCode |= HAL_DMA_ERROR_REQGEN;
+
+ if (hdma->XferErrorCallback != NULL)
+ {
+ /* Transfer error callback */
+ hdma->XferErrorCallback(hdma);
+ }
+ }
+ }
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_DMA_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.c b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.c
new file mode 100644
index 0000000000..a0b65f4377
--- /dev/null
+++ b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.c
@@ -0,0 +1,667 @@
+/**
+ ******************************************************************************
+ * @file stm32c0xx_hal_exti.c
+ * @author MCD Application Team
+ * @brief EXTI HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the General Purpose Input/Output (EXTI) peripheral:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2022 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### EXTI Peripheral features #####
+ ==============================================================================
+ [..]
+ (+) Each Exti line can be configured within this driver.
+
+ (+) Exti line can be configured in 3 different modes
+ (++) Interrupt
+ (++) Event
+ (++) Both of them
+
+ (+) Configurable Exti lines can be configured with 3 different triggers
+ (++) Rising
+ (++) Falling
+ (++) Both of them
+
+ (+) When set in interrupt mode, configurable Exti lines have two diffenrents
+ interrupt pending registers which allow to distinguish which transition
+ occurs:
+ (++) Rising edge pending interrupt
+ (++) Falling
+
+ (+) Exti lines 0 to 15 are linked to gpio pin number 0 to 15. Gpio port can
+ be selected through multiplexer.
+
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+
+ (#) Configure the EXTI line using HAL_EXTI_SetConfigLine().
+ (++) Choose the interrupt line number by setting "Line" member from
+ EXTI_ConfigTypeDef structure.
+ (++) Configure the interrupt and/or event mode using "Mode" member from
+ EXTI_ConfigTypeDef structure.
+ (++) For configurable lines, configure rising and/or falling trigger
+ "Trigger" member from EXTI_ConfigTypeDef structure.
+ (++) For Exti lines linked to gpio, choose gpio port using "GPIOSel"
+ member from GPIO_InitTypeDef structure.
+
+ (#) Get current Exti configuration of a dedicated line using
+ HAL_EXTI_GetConfigLine().
+ (++) Provide exiting handle as parameter.
+ (++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter.
+
+ (#) Clear Exti configuration of a dedicated line using HAL_EXTI_GetConfigLine().
+ (++) Provide exiting handle as parameter.
+
+ (#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback().
+ (++) Provide exiting handle as first parameter.
+ (++) Provide which callback will be registered using one value from
+ EXTI_CallbackIDTypeDef.
+ (++) Provide callback function pointer.
+
+ (#) Get interrupt pending bit using HAL_EXTI_GetPending().
+
+ (#) Clear interrupt pending bit using HAL_EXTI_GetPending().
+
+ (#) Generate software interrupt using HAL_EXTI_GenerateSWI().
+
+ @endverbatim
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32c0xx_hal.h"
+
+/** @addtogroup STM32C0xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup EXTI
+ * @{
+ */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private defines ------------------------------------------------------------*/
+/** @defgroup EXTI_Private_Constants EXTI Private Constants
+ * @{
+ */
+#define EXTI_MODE_OFFSET 0x04u /* 0x10: offset between CPU IMR/EMR registers */
+#define EXTI_CONFIG_OFFSET 0x08u /* 0x20: offset between CPU Rising/Falling configuration registers */
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup EXTI_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup EXTI_Exported_Functions_Group1
+ * @brief Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Configuration functions #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Set configuration of a dedicated Exti line.
+ * @param hexti Exti handle.
+ * @param pExtiConfig Pointer on EXTI configuration to be set.
+ * @retval HAL Status.
+ */
+HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
+{
+ __IO uint32_t *regaddr;
+ uint32_t regval;
+ uint32_t linepos;
+ uint32_t maskline;
+ uint32_t offset;
+
+ /* Check null pointer */
+ if ((hexti == NULL) || (pExtiConfig == NULL))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_EXTI_LINE(pExtiConfig->Line));
+ assert_param(IS_EXTI_MODE(pExtiConfig->Mode));
+
+ /* Assign line number to handle */
+ hexti->Line = pExtiConfig->Line;
+
+ /* compute line register offset and line mask */
+ offset = ((pExtiConfig->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
+ linepos = (pExtiConfig->Line & EXTI_PIN_MASK);
+ maskline = (1UL << linepos);
+
+ /* Configure triggers for configurable lines */
+ if ((pExtiConfig->Line & EXTI_CONFIG) != 0U)
+ {
+ assert_param(IS_EXTI_TRIGGER(pExtiConfig->Trigger));
+
+ /* Configure rising trigger */
+ regaddr = (__IO uint32_t *)(&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset));
+ regval = *regaddr;
+
+ /* Mask or set line */
+ if ((pExtiConfig->Trigger & EXTI_TRIGGER_RISING) != 0U)
+ {
+ regval |= maskline;
+ }
+ else
+ {
+ regval &= ~maskline;
+ }
+
+ /* Store rising trigger mode */
+ *regaddr = regval;
+
+ /* Configure falling trigger */
+ regaddr = (__IO uint32_t *)(&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset));
+ regval = *regaddr;
+
+ /* Mask or set line */
+ if ((pExtiConfig->Trigger & EXTI_TRIGGER_FALLING) != 0U)
+ {
+ regval |= maskline;
+ }
+ else
+ {
+ regval &= ~maskline;
+ }
+
+ /* Store falling trigger mode */
+ *regaddr = regval;
+
+ /* Configure gpio port selection in case of gpio exti line */
+ if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO)
+ {
+ assert_param(IS_EXTI_GPIO_PORT(pExtiConfig->GPIOSel));
+ assert_param(IS_EXTI_GPIO_PIN(linepos));
+
+ regval = EXTI->EXTICR[(linepos >> 2U) & 0x03UL];
+ regval &= ~(EXTI_EXTICR1_EXTI0 << (EXTI_EXTICR1_EXTI1_Pos * (linepos & 0x03U)));
+ regval |= (pExtiConfig->GPIOSel << (EXTI_EXTICR1_EXTI1_Pos * (linepos & 0x03U)));
+ EXTI->EXTICR[(linepos >> 2U) & 0x03UL] = regval;
+ }
+ }
+
+ /* Configure interrupt mode : read current mode */
+ regaddr = (__IO uint32_t *)(&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset));
+ regval = *regaddr;
+
+ /* Mask or set line */
+ if ((pExtiConfig->Mode & EXTI_MODE_INTERRUPT) != 0U)
+ {
+ regval |= maskline;
+ }
+ else
+ {
+ regval &= ~maskline;
+ }
+
+ /* Store interrupt mode */
+ *regaddr = regval;
+
+ /* Configure event mode : read current mode */
+ regaddr = (__IO uint32_t *)(&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset));
+ regval = *regaddr;
+
+ /* Mask or set line */
+ if ((pExtiConfig->Mode & EXTI_MODE_EVENT) != 0U)
+ {
+ regval |= maskline;
+ }
+ else
+ {
+ regval &= ~maskline;
+ }
+
+ /* Store event mode */
+ *regaddr = regval;
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Get configuration of a dedicated Exti line.
+ * @param hexti Exti handle.
+ * @param pExtiConfig Pointer on structure to store Exti configuration.
+ * @retval HAL Status.
+ */
+HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
+{
+ __IO uint32_t *regaddr;
+ uint32_t regval;
+ uint32_t linepos;
+ uint32_t maskline;
+ uint32_t offset;
+
+ /* Check null pointer */
+ if ((hexti == NULL) || (pExtiConfig == NULL))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameter */
+ assert_param(IS_EXTI_LINE(hexti->Line));
+
+ /* Store handle line number to configiguration structure */
+ pExtiConfig->Line = hexti->Line;
+
+ /* compute line register offset and line mask */
+ offset = ((pExtiConfig->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
+ linepos = (pExtiConfig->Line & EXTI_PIN_MASK);
+ maskline = (1UL << linepos);
+
+ /* 1] Get core mode : interrupt */
+ regaddr = (__IO uint32_t *)(&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset));
+ regval = *regaddr;
+
+ /* Check if selected line is enable */
+ if ((regval & maskline) != 0U)
+ {
+ pExtiConfig->Mode = EXTI_MODE_INTERRUPT;
+ }
+ else
+ {
+ pExtiConfig->Mode = EXTI_MODE_NONE;
+ }
+
+ /* Get event mode */
+ regaddr = (__IO uint32_t *)(&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset));
+ regval = *regaddr;
+
+ /* Check if selected line is enable */
+ if ((regval & maskline) != 0U)
+ {
+ pExtiConfig->Mode |= EXTI_MODE_EVENT;
+ }
+
+ /* 2] Get trigger for configurable lines : rising */
+ if ((pExtiConfig->Line & EXTI_CONFIG) != 0U)
+ {
+ regaddr = (__IO uint32_t *)(&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset));
+ regval = *regaddr;
+
+ /* Get default Trigger and GPIOSel configuration */
+ pExtiConfig->Trigger = EXTI_TRIGGER_NONE;
+ pExtiConfig->GPIOSel = 0x00u;
+
+ /* Check if configuration of selected line is enable */
+ if ((regval & maskline) != 0U)
+ {
+ pExtiConfig->Trigger = EXTI_TRIGGER_RISING;
+ }
+
+ /* Get falling configuration */
+ regaddr = (__IO uint32_t *)(&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset));
+ regval = *regaddr;
+
+ /* Check if configuration of selected line is enable */
+ if ((regval & maskline) != 0U)
+ {
+ pExtiConfig->Trigger |= EXTI_TRIGGER_FALLING;
+ }
+
+ /* Get Gpio port selection for gpio lines */
+ if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO)
+ {
+ assert_param(IS_EXTI_GPIO_PIN(linepos));
+
+ regval = EXTI->EXTICR[(linepos >> 2U) & 0x03UL];
+ pExtiConfig->GPIOSel = ((regval << (EXTI_EXTICR1_EXTI1_Pos * (3U - (linepos & 0x03U)))) >> 24U);
+ }
+ }
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Clear whole configuration of a dedicated Exti line.
+ * @param hexti Exti handle.
+ * @retval HAL Status.
+ */
+HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti)
+{
+ __IO uint32_t *regaddr;
+ uint32_t regval;
+ uint32_t linepos;
+ uint32_t maskline;
+ uint32_t offset;
+
+ /* Check null pointer */
+ if (hexti == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameter */
+ assert_param(IS_EXTI_LINE(hexti->Line));
+
+ /* compute line register offset and line mask */
+ offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
+ linepos = (hexti->Line & EXTI_PIN_MASK);
+ maskline = (1UL << linepos);
+
+ /* 1] Clear interrupt mode */
+ regaddr = (__IO uint32_t *)(&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset));
+ regval = (*regaddr & ~maskline);
+ *regaddr = regval;
+
+ /* 2] Clear event mode */
+ regaddr = (__IO uint32_t *)(&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset));
+ regval = (*regaddr & ~maskline);
+ *regaddr = regval;
+
+ /* 3] Clear triggers in case of configurable lines */
+ if ((hexti->Line & EXTI_CONFIG) != 0U)
+ {
+ regaddr = (__IO uint32_t *)(&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset));
+ regval = (*regaddr & ~maskline);
+ *regaddr = regval;
+
+ regaddr = (__IO uint32_t *)(&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset));
+ regval = (*regaddr & ~maskline);
+ *regaddr = regval;
+
+ /* Get Gpio port selection for gpio lines */
+ if ((hexti->Line & EXTI_GPIO) == EXTI_GPIO)
+ {
+ assert_param(IS_EXTI_GPIO_PIN(linepos));
+
+ regval = EXTI->EXTICR[(linepos >> 2U) & 0x03UL];
+ regval &= ~(EXTI_EXTICR1_EXTI0 << (EXTI_EXTICR1_EXTI1_Pos * (linepos & 0x03U)));
+ EXTI->EXTICR[(linepos >> 2U) & 0x03UL] = regval;
+ }
+ }
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Register callback for a dedicaated Exti line.
+ * @param hexti Exti handle.
+ * @param CallbackID User callback identifier.
+ * This parameter can be one of @arg @ref EXTI_CallbackIDTypeDef values.
+ * @param pPendingCbfn function pointer to be stored as callback.
+ * @retval HAL Status.
+ */
+HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID,
+ void (*pPendingCbfn)(void))
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ switch (CallbackID)
+ {
+ case HAL_EXTI_COMMON_CB_ID:
+ hexti->RisingCallback = pPendingCbfn;
+ hexti->FallingCallback = pPendingCbfn;
+ break;
+
+ case HAL_EXTI_RISING_CB_ID:
+ hexti->RisingCallback = pPendingCbfn;
+ break;
+
+ case HAL_EXTI_FALLING_CB_ID:
+ hexti->FallingCallback = pPendingCbfn;
+ break;
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ return status;
+}
+
+
+/**
+ * @brief Store line number as handle private field.
+ * @param hexti Exti handle.
+ * @param ExtiLine Exti line number.
+ * This parameter can be from 0 to @ref EXTI_LINE_NB.
+ * @retval HAL Status.
+ */
+HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine)
+{
+ /* Check the parameters */
+ assert_param(IS_EXTI_LINE(ExtiLine));
+
+ /* Check null pointer */
+ if (hexti == NULL)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Store line number as handle private field */
+ hexti->Line = ExtiLine;
+
+ return HAL_OK;
+ }
+}
+
+
+/**
+ * @}
+ */
+
+/** @addtogroup EXTI_Exported_Functions_Group2
+ * @brief EXTI IO functions.
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Handle EXTI interrupt request.
+ * @param hexti Exti handle.
+ * @retval none.
+ */
+void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti)
+{
+ __IO uint32_t *regaddr;
+ uint32_t regval;
+ uint32_t maskline;
+ uint32_t offset;
+
+ /* Compute line register offset and line mask */
+ offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
+ maskline = (1UL << (hexti->Line & EXTI_PIN_MASK));
+
+ /* Get rising edge pending bit */
+ regaddr = (__IO uint32_t *)(&EXTI->RPR1 + (EXTI_CONFIG_OFFSET * offset));
+ regval = (*regaddr & maskline);
+
+ if (regval != 0U)
+ {
+ /* Clear pending bit */
+ *regaddr = maskline;
+
+ /* Call rising callback */
+ if (hexti->RisingCallback != NULL)
+ {
+ hexti->RisingCallback();
+ }
+ }
+
+ /* Get falling edge pending bit */
+ regaddr = (__IO uint32_t *)(&EXTI->FPR1 + (EXTI_CONFIG_OFFSET * offset));
+ regval = (*regaddr & maskline);
+
+ if (regval != 0U)
+ {
+ /* Clear pending bit */
+ *regaddr = maskline;
+
+ /* Call rising callback */
+ if (hexti->FallingCallback != NULL)
+ {
+ hexti->FallingCallback();
+ }
+ }
+}
+
+
+/**
+ * @brief Get interrupt pending bit of a dedicated line.
+ * @param hexti Exti handle.
+ * @param Edge Specify which pending edge as to be checked.
+ * This parameter can be one of the following values:
+ * @arg @ref EXTI_TRIGGER_RISING
+ * @arg @ref EXTI_TRIGGER_FALLING
+ * @retval 1 if interrupt is pending else 0.
+ */
+uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
+{
+ __IO uint32_t *regaddr;
+ uint32_t regval;
+ uint32_t linepos;
+ uint32_t maskline;
+ uint32_t offset;
+
+ /* Check the parameters */
+ assert_param(IS_EXTI_LINE(hexti->Line));
+ assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
+ assert_param(IS_EXTI_PENDING_EDGE(Edge));
+
+ /* compute line register offset and line mask */
+ offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
+ linepos = (hexti->Line & EXTI_PIN_MASK);
+ maskline = (1UL << linepos);
+
+ if (Edge != EXTI_TRIGGER_RISING)
+ {
+ /* Get falling edge pending bit */
+ regaddr = (__IO uint32_t *)(&EXTI->FPR1 + (EXTI_CONFIG_OFFSET * offset));
+ }
+ else
+ {
+ /* Get rising edge pending bit */
+ regaddr = (__IO uint32_t *)(&EXTI->RPR1 + (EXTI_CONFIG_OFFSET * offset));
+ }
+
+ /* return 1 if bit is set else 0 */
+ regval = ((*regaddr & maskline) >> linepos);
+ return regval;
+}
+
+
+/**
+ * @brief Clear interrupt pending bit of a dedicated line.
+ * @param hexti Exti handle.
+ * @param Edge Specify which pending edge as to be clear.
+ * This parameter can be one of the following values:
+ * @arg @ref EXTI_TRIGGER_RISING
+ * @arg @ref EXTI_TRIGGER_FALLING
+ * @retval None.
+ */
+void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
+{
+ __IO uint32_t *regaddr;
+ uint32_t maskline;
+ uint32_t offset;
+
+ /* Check the parameters */
+ assert_param(IS_EXTI_LINE(hexti->Line));
+ assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
+ assert_param(IS_EXTI_PENDING_EDGE(Edge));
+
+ /* compute line register offset and line mask */
+ offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
+ maskline = (1UL << (hexti->Line & EXTI_PIN_MASK));
+
+ if (Edge != EXTI_TRIGGER_RISING)
+ {
+ /* Get falling edge pending register address */
+ regaddr = (__IO uint32_t *)(&EXTI->FPR1 + (EXTI_CONFIG_OFFSET * offset));
+ }
+ else
+ {
+ /* Get falling edge pending register address */
+ regaddr = (__IO uint32_t *)(&EXTI->RPR1 + (EXTI_CONFIG_OFFSET * offset));
+ }
+
+ /* Clear Pending bit */
+ *regaddr = maskline;
+}
+
+
+/**
+ * @brief Generate a software interrupt for a dedicated line.
+ * @param hexti Exti handle.
+ * @retval None.
+ */
+void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti)
+{
+ __IO uint32_t *regaddr;
+ uint32_t maskline;
+ uint32_t offset;
+
+ /* Check the parameters */
+ assert_param(IS_EXTI_LINE(hexti->Line));
+ assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
+
+ /* compute line register offset and line mask */
+ offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
+ maskline = (1UL << (hexti->Line & EXTI_PIN_MASK));
+
+ regaddr = (__IO uint32_t *)(&EXTI->SWIER1 + (EXTI_CONFIG_OFFSET * offset));
+ *regaddr = maskline;
+}
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_EXTI_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c
new file mode 100644
index 0000000000..06d799e002
--- /dev/null
+++ b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c
@@ -0,0 +1,699 @@
+/**
+ ******************************************************************************
+ * @file stm32c0xx_hal_flash.c
+ * @author MCD Application Team
+ * @brief FLASH HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the internal FLASH memory:
+ * + Program operations functions
+ * + Memory Control functions
+ * + Peripheral Errors functions
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2022 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### FLASH peripheral features #####
+ ==============================================================================
+
+ [..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses
+ to the Flash memory. It implements the erase and program Flash memory operations
+ and the read and write protection mechanisms.
+
+ [..] The Flash memory interface accelerates code execution with a system of instruction
+ prefetch and cache lines.
+
+ [..] The FLASH main features are:
+ (+) Flash memory read operations
+ (+) Flash memory program/erase operations
+ (+) Read / write protections
+ (+) Option bytes programming
+ (+) Prefetch on I-Code
+ (+) 32 cache lines of 4*64 bits on I-Code
+
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ This driver provides functions and macros to configure and program the FLASH
+ memory of all STM32C0xx devices.
+
+ (#) Flash Memory IO Programming functions:
+ (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and
+ HAL_FLASH_Lock() functions
+ (++) Program functions: double word and fast program (full row programming)
+ (++) There are two modes of programming:
+ (+++) Polling mode using HAL_FLASH_Program() function
+ (+++) Interrupt mode using HAL_FLASH_Program_IT() function
+
+ (#) Interrupts and flags management functions:
+ (++) Handle FLASH interrupts by calling HAL_FLASH_IRQHandler()
+ (++) Callback functions are called when the flash operations are finished :
+ HAL_FLASH_EndOfOperationCallback() when everything is ok, otherwise
+ HAL_FLASH_OperationErrorCallback()
+ (++) Get error flag status by calling HAL_GetError()
+
+ (#) Option bytes management functions :
+ (++) Lock and Unlock the option bytes using HAL_FLASH_OB_Unlock() and
+ HAL_FLASH_OB_Lock() functions
+ (++) Launch the reload of the option bytes using HAL_FLASH_OB_Launch() function.
+ In this case, a reset is generated
+
+ [..]
+ In addition to these functions, this driver includes a set of macros allowing
+ to handle the following operations:
+ (+) Set the latency
+ (+) Enable/Disable the prefetch buffer
+ (+) Enable/Disable the Instruction cache
+ (+) Reset the Instruction cache
+ (+) Enable/Disable the Flash power-down during low-power modes
+ (+) Enable/Disable the Flash interrupts
+ (+) Monitor the Flash flags status
+
+ @endverbatim
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32c0xx_hal.h"
+
+/** @addtogroup STM32C0xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup FLASH FLASH
+ * @brief FLASH HAL module driver
+ * @{
+ */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private defines -----------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup FLASH_Private_Variables FLASH Private Variables
+ * @{
+ */
+/**
+ * @brief Variable used for Program/Erase sectors under interruption
+ */
+FLASH_ProcessTypeDef pFlash = {.Lock = HAL_UNLOCKED, \
+ .ErrorCode = HAL_FLASH_ERROR_NONE, \
+ .ProcedureOnGoing = FLASH_TYPENONE, \
+ .Address = 0U, \
+ .Page = 0U, \
+ .NbPagesToErase = 0U
+ };
+/**
+ * @}
+ */
+
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup FLASH_Private_Functions FLASH Private Functions
+ * @{
+ */
+static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data);
+static void FLASH_Program_Fast(uint32_t Address, uint32_t DataAddress);
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup FLASH_Exported_Functions FLASH Exported Functions
+ * @{
+ */
+
+/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions
+ * @brief Programming operation functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Programming operation functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the FLASH
+ program operations.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Program double word or fast program of a row at a specified address.
+ * @param TypeProgram Indicate the way to program at a specified address.
+ * This parameter can be a value of @ref FLASH_Type_Program
+ * @param Address Specifies the address to be programmed.
+ * @param Data Specifies the data to be programmed
+ * This parameter is the data for the double word program and the address where
+ * are stored the data for the row fast program.
+ *
+ * @retval HAL_StatusTypeDef HAL Status
+ */
+HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
+{
+ HAL_StatusTypeDef status;
+
+ /* Check the parameters */
+ assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
+ assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));
+
+ /* Process Locked */
+ __HAL_LOCK(&pFlash);
+
+ /* Reset error code */
+ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
+
+ if (status == HAL_OK)
+ {
+ if (TypeProgram == FLASH_TYPEPROGRAM_DOUBLEWORD)
+ {
+ /* Check the parameters */
+ assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));
+
+ /* Program double-word (64-bit) at a specified address */
+ FLASH_Program_DoubleWord(Address, Data);
+ }
+ else
+ {
+ /* Check the parameters */
+ assert_param(IS_FLASH_FAST_PROGRAM_ADDRESS(Address));
+
+ /* Fast program a 32 row double-word (64-bit) at a specified address */
+ FLASH_Program_Fast(Address, (uint32_t)Data);
+ }
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
+
+ /* If the program operation is completed, disable the PG or FSTPG Bit */
+ CLEAR_BIT(FLASH->CR, TypeProgram);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(&pFlash);
+
+ /* return status */
+ return status;
+}
+
+/**
+ * @brief Program double word or fast program of a row at a specified address with interrupt enabled.
+ * @param TypeProgram Indicate the way to program at a specified address.
+ * This parameter can be a value of @ref FLASH_Type_Program
+ * @param Address Specifies the address to be programmed.
+ * @param Data Specifies the data to be programmed
+ * This parameter is the data for the double word program and the address where
+ * are stored the data for the row fast program.
+ *
+ * @retval HAL Status
+ */
+HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
+{
+ HAL_StatusTypeDef status;
+
+ /* Check the parameters */
+ assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
+ assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));
+
+ /* Process Locked */
+ __HAL_LOCK(&pFlash);
+
+ /* Reset error code */
+ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
+
+ if (status != HAL_OK)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(&pFlash);
+ }
+ else
+ {
+ /* Set internal variables used by the IRQ handler */
+ pFlash.ProcedureOnGoing = TypeProgram;
+ pFlash.Address = Address;
+
+ /* Enable End of Operation and Error interrupts */
+ __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_OPERR);
+
+ if (TypeProgram == FLASH_TYPEPROGRAM_DOUBLEWORD)
+ {
+ /* Check the parameters */
+ assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));
+
+ /* Program double-word (64-bit) at a specified address */
+ FLASH_Program_DoubleWord(Address, Data);
+ }
+ else
+ {
+ /* Check the parameters */
+ assert_param(IS_FLASH_FAST_PROGRAM_ADDRESS(Address));
+
+ /* Fast program a 32 row double-word (64-bit) at a specified address */
+ FLASH_Program_Fast(Address, (uint32_t)Data);
+ }
+ }
+
+ /* return status */
+ return status;
+}
+
+/**
+ * @brief Handle FLASH interrupt request.
+ * @retval None
+ */
+void HAL_FLASH_IRQHandler(void)
+{
+ uint32_t param = 0xFFFFFFFFU;
+ uint32_t error;
+
+ /* Save flash errors */
+ error = (FLASH->SR & FLASH_FLAG_SR_ERROR);
+
+ CLEAR_BIT(FLASH->CR, pFlash.ProcedureOnGoing);
+
+ /* A] Set parameter for user or error callbacks */
+ /* check operation was a program or erase */
+ if ((pFlash.ProcedureOnGoing & (FLASH_TYPEPROGRAM_DOUBLEWORD | FLASH_TYPEPROGRAM_FAST)) != 0x00U)
+ {
+ /* return address being programmed */
+ param = pFlash.Address;
+ }
+ else if ((pFlash.ProcedureOnGoing & (FLASH_TYPEERASE_MASS | FLASH_TYPEERASE_PAGES)) != 0x00U)
+ {
+ /* return page number being erased (0 for mass erase) */
+ param = pFlash.Page;
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+
+ /* B] Check errors */
+ if (error != 0x00U)
+ {
+ /*Save the error code*/
+ pFlash.ErrorCode |= error;
+
+ /* clear error flags */
+ __HAL_FLASH_CLEAR_FLAG(error);
+
+ /*Stop the procedure ongoing*/
+ pFlash.ProcedureOnGoing = FLASH_TYPENONE;
+
+ /* Error callback */
+ HAL_FLASH_OperationErrorCallback(param);
+ }
+
+ /* C] Check FLASH End of Operation flag */
+ if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP) != 0x00U)
+ {
+ /* Clear FLASH End of Operation pending bit */
+ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
+
+ if (pFlash.ProcedureOnGoing == FLASH_TYPEERASE_PAGES)
+ {
+ /* Nb of pages to erased can be decreased */
+ pFlash.NbPagesToErase--;
+
+ /* Check if there are still pages to erase*/
+ if (pFlash.NbPagesToErase != 0x00U)
+ {
+ /* Increment page number */
+ pFlash.Page++;
+ FLASH_PageErase(pFlash.Page);
+ }
+ else
+ {
+ /* No more pages to erase: stop erase pages procedure */
+ pFlash.ProcedureOnGoing = FLASH_TYPENONE;
+ }
+ }
+ else
+ {
+ /*Stop the ongoing procedure */
+ pFlash.ProcedureOnGoing = FLASH_TYPENONE;
+ }
+
+ /* User callback */
+ HAL_FLASH_EndOfOperationCallback(param);
+ }
+
+ if (pFlash.ProcedureOnGoing == FLASH_TYPENONE)
+ {
+ /* Disable End of Operation and Error interrupts */
+ __HAL_FLASH_DISABLE_IT(FLASH_IT_EOP | FLASH_IT_OPERR);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(&pFlash);
+ }
+}
+
+/**
+ * @brief FLASH end of operation interrupt callback.
+ * @param ReturnValue The value saved in this parameter depends on the ongoing procedure
+ * Mass Erase: 0
+ * Page Erase: Page which has been erased
+ * Program: Address which was selected for data program
+ * @retval None
+ */
+__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(ReturnValue);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_FLASH_EndOfOperationCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief FLASH operation error interrupt callback.
+ * @param ReturnValue The value saved in this parameter depends on the ongoing procedure
+ * Mass Erase: 0
+ * Page Erase: Page number which returned an error
+ * Program: Address which was selected for data program
+ * @retval None
+ */
+__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(ReturnValue);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_FLASH_OperationErrorCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions
+ * @brief Management functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control the FLASH
+ memory operations.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Unlock the FLASH control register access.
+ * @retval HAL Status
+ */
+HAL_StatusTypeDef HAL_FLASH_Unlock(void)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (READ_BIT(FLASH->CR, FLASH_CR_LOCK) != 0x00U)
+ {
+ /* Authorize the FLASH Registers access */
+ WRITE_REG(FLASH->KEYR, FLASH_KEY1);
+ WRITE_REG(FLASH->KEYR, FLASH_KEY2);
+
+ /* verify Flash is unlock */
+ if (READ_BIT(FLASH->CR, FLASH_CR_LOCK) != 0x00U)
+ {
+ status = HAL_ERROR;
+ }
+ }
+
+ return status;
+}
+
+/**
+ * @brief Lock the FLASH control register access.
+ * @retval HAL Status
+ */
+HAL_StatusTypeDef HAL_FLASH_Lock(void)
+{
+ HAL_StatusTypeDef status = HAL_ERROR;
+
+ /* Set the LOCK Bit to lock the FLASH Registers access */
+ SET_BIT(FLASH->CR, FLASH_CR_LOCK);
+
+ /* verify Flash is locked */
+ if (READ_BIT(FLASH->CR, FLASH_CR_LOCK) != 0x00u)
+ {
+ status = HAL_OK;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Unlock the FLASH Option Bytes Registers access.
+ * @retval HAL Status
+ */
+HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void)
+{
+ HAL_StatusTypeDef status = HAL_ERROR;
+
+ if (READ_BIT(FLASH->CR, FLASH_CR_OPTLOCK) != 0x00U)
+ {
+ /* Authorizes the Option Byte register programming */
+ WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY1);
+ WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY2);
+
+ /* verify option bytes are unlocked */
+ if (READ_BIT(FLASH->CR, FLASH_CR_OPTLOCK) == 0x00U)
+ {
+ status = HAL_OK;
+ }
+ }
+
+ return status;
+}
+
+/**
+ * @brief Lock the FLASH Option Bytes Registers access.
+ * @retval HAL Status
+ */
+HAL_StatusTypeDef HAL_FLASH_OB_Lock(void)
+{
+ HAL_StatusTypeDef status = HAL_ERROR;
+
+ /* Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access */
+ SET_BIT(FLASH->CR, FLASH_CR_OPTLOCK);
+
+ /* verify option bytes are locked */
+ if (READ_BIT(FLASH->CR, FLASH_CR_OPTLOCK) != 0x00u)
+ {
+ status = HAL_OK;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Launch the option byte loading.
+ * @retval HAL Status
+ */
+HAL_StatusTypeDef HAL_FLASH_OB_Launch(void)
+{
+ /* Set the bit to force the option byte reloading */
+ SET_BIT(FLASH->CR, FLASH_CR_OBL_LAUNCH);
+
+ /* We should not reach here : Option byte launch generates Option byte reset
+ so return error */
+ return HAL_ERROR;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Exported_Functions_Group3 Peripheral State and Errors functions
+ * @brief Peripheral Errors functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Errors functions #####
+ ===============================================================================
+ [..]
+ This subsection permits to get in run-time Errors of the FLASH peripheral.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Get the specific FLASH error flag.
+ * @retval FLASH_ErrorCode The returned value can be
+ * @arg @ref HAL_FLASH_ERROR_NONE No error set
+ * @arg @ref HAL_FLASH_ERROR_OP FLASH Operation error
+ * @arg @ref HAL_FLASH_ERROR_PROG FLASH Programming error
+ * @arg @ref HAL_FLASH_ERROR_WRP FLASH Write protection error
+ * @arg @ref HAL_FLASH_ERROR_PGA FLASH Programming alignment error
+ * @arg @ref HAL_FLASH_ERROR_SIZ FLASH Size error
+ * @arg @ref HAL_FLASH_ERROR_PGS FLASH Programming sequence error
+ * @arg @ref HAL_FLASH_ERROR_MIS FLASH Fast programming data miss error
+ * @arg @ref HAL_FLASH_ERROR_FAST FLASH Fast programming error
+ * @arg @ref HAL_FLASH_ERROR_RD FLASH Read Protection error (PCROP)
+ * @arg @ref HAL_FLASH_ERROR_OPTV FLASH Option validity error
+ */
+uint32_t HAL_FLASH_GetError(void)
+{
+ return pFlash.ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+
+/** @addtogroup FLASH_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Wait for a FLASH operation to complete.
+ * @param Timeout maximum flash operation timeout
+ * @retval HAL_StatusTypeDef HAL Status
+ */
+HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
+{
+ uint32_t error;
+ /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.
+ Even if the FLASH operation fails, the BUSY flag will be reset and an error
+ flag will be set */
+ uint32_t timeout = HAL_GetTick() + Timeout;
+
+ /* Wait if any operation is ongoing */
+ while (__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY) != 0x00U)
+ {
+ if (HAL_GetTick() >= timeout)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* check flash errors */
+ error = (FLASH->SR & FLASH_FLAG_SR_ERROR);
+
+ /* clear error flags */
+ __HAL_FLASH_CLEAR_FLAG(error);
+
+ if (error != 0x00U)
+ {
+ /*Save the error code*/
+ pFlash.ErrorCode = error;
+
+ return HAL_ERROR;
+ }
+
+ /* Wait for control register to be written */
+ timeout = HAL_GetTick() + Timeout;
+
+ while (__HAL_FLASH_GET_FLAG(FLASH_FLAG_CFGBSY) != 0x00U)
+ {
+ if (HAL_GetTick() >= timeout)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Program double-word (64-bit) at a specified address.
+ * @param Address Specifies the address to be programmed.
+ * @param Data Specifies the data to be programmed.
+ * @retval None
+ */
+static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data)
+{
+ /* Set PG bit */
+ SET_BIT(FLASH->CR, FLASH_CR_PG);
+
+ /* Program first word */
+ *(uint32_t *)Address = (uint32_t)Data;
+
+ /* Barrier to ensure programming is performed in 2 steps, in right order
+ (independently of compiler optimization behavior) */
+ __ISB();
+
+ /* Program second word */
+ *(uint32_t *)(Address + 4U) = (uint32_t)(Data >> 32U);
+}
+
+/**
+ * @brief Fast program a 32 row double-word (64-bit) at a specified address.
+ * @param Address Specifies the address to be programmed.
+ * @param DataAddress Specifies the address where the data are stored.
+ * @retval None
+ */
+static __RAM_FUNC void FLASH_Program_Fast(uint32_t Address, uint32_t DataAddress)
+{
+ uint8_t index = 0;
+ uint32_t dest = Address;
+ uint32_t src = DataAddress;
+ uint32_t primask_bit;
+
+ /* Set FSTPG bit */
+ SET_BIT(FLASH->CR, FLASH_CR_FSTPG);
+
+ /* Enter critical section: row programming should not be longer than 7 ms */
+ primask_bit = __get_PRIMASK();
+ __disable_irq();
+
+ /* Fast Program : 64 words */
+ while (index < 64U)
+ {
+ *(uint32_t *)dest = *(uint32_t *)src;
+ src += 4U;
+ dest += 4U;
+ index++;
+ }
+
+ /* wait for BSY1 in order to be sure that flash operation is ended befoire
+ allowing prefetch in flash. Timeout does not return status, as it will
+ be anyway done later */
+ while ((FLASH->SR & FLASH_SR_BSY1) != 0x00U)
+ {
+ }
+
+ /* Exit critical section: restore previous priority mask */
+ __set_PRIMASK(primask_bit);
+}
+
+/**
+ * @}
+ */
+
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c
new file mode 100644
index 0000000000..82a46b7af1
--- /dev/null
+++ b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c
@@ -0,0 +1,866 @@
+/**
+ ******************************************************************************
+ * @file stm32c0xx_hal_flash_ex.c
+ * @author MCD Application Team
+ * @brief Extended FLASH HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the FLASH extended peripheral:
+ * + Extended programming operations functions
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2022 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### Flash Extended features #####
+ ==============================================================================
+
+ [..] Comparing to other previous devices, the FLASH interface for STM32C0xx
+ devices contains the following additional features
+
+ (+) Capacity up to 128 Kbytes with single bank architecture supporting read-while-write
+ capability (RWW)
+ (+) Single bank memory organization
+ (+) PCROP protection
+
+ ##### How to use this driver #####
+ ==============================================================================
+ [..] This driver provides functions to configure and program the FLASH memory
+ of all STM32C0xx devices. It includes
+ (#) Flash Memory Erase functions:
+ (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and
+ HAL_FLASH_Lock() functions
+ (++) Erase function: Erase page, erase all sectors
+ (++) There are two modes of erase :
+ (+++) Polling Mode using HAL_FLASHEx_Erase()
+ (+++) Interrupt Mode using HAL_FLASHEx_Erase_IT()
+
+ (#) Option Bytes Programming function: Use HAL_FLASHEx_OBProgram() to :
+ (++) Set/Reset the write protection
+ (++) Set the Read protection Level
+ (++) Program the user Option Bytes
+ (++) Configure the PCROP protection
+ (++) Set Securable memory area and boot entry point
+
+ (#) Get Option Bytes Configuration function: Use HAL_FLASHEx_OBGetConfig() to :
+ (++) Get the value of a write protection area
+ (++) Know if the read protection is activated
+ (++) Get the value of the user Option Bytes
+ (++) Get Securable memory area and boot entry point information
+
+ (#) Enable or disable debugger usage using HAL_FLASHEx_EnableDebugger and
+ HAL_FLASHEx_DisableDebugger.
+
+ (#) Check is flash content is empty or not using HAL_FLASHEx_FlashEmptyCheck.
+ and modify this setting (for flash loader purpose e.g.) using
+ HAL_FLASHEx_ForceFlashEmpty.
+
+ (#) Enable securable memory area protectionusing HAL_FLASHEx_EnableSecMemProtection
+
+ @endverbatim
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32c0xx_hal.h"
+
+/** @addtogroup STM32C0xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup FLASHEx FLASHEx
+ * @brief FLASH Extended HAL module driver
+ * @{
+ */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions
+ * @{
+ */
+static void FLASH_MassErase(void);
+void FLASH_FlushCaches(void);
+static void FLASH_OB_WRPConfig(uint32_t WRPArea, uint32_t WRPStartOffset, uint32_t WRDPEndOffset);
+static void FLASH_OB_OptrConfig(uint32_t UserType, uint32_t UserConfig, uint32_t RDPLevel);
+static void FLASH_OB_PCROP1AConfig(uint32_t PCROPConfig, uint32_t PCROP1AStartAddr, uint32_t PCROP1AEndAddr);
+static void FLASH_OB_PCROP1BConfig(uint32_t PCROP1BStartAddr, uint32_t PCROP1BEndAddr);
+static void FLASH_OB_SecMemConfig(uint32_t BootEntry, uint32_t SecSize);
+static void FLASH_OB_GetWRP(uint32_t WRPArea, uint32_t *WRPStartOffset, uint32_t *WRDPEndOffset);
+static uint32_t FLASH_OB_GetRDP(void);
+static uint32_t FLASH_OB_GetUser(void);
+static void FLASH_OB_GetPCROP1A(uint32_t *PCROPConfig, uint32_t *PCROP1AStartAddr, uint32_t *PCROP1AEndAddr);
+static void FLASH_OB_GetPCROP1B(uint32_t *PCROP1BStartAddr, uint32_t *PCROP1BEndAddr);
+static void FLASH_OB_GetSecMem(uint32_t *BootEntry, uint32_t *SecSize);
+/**
+ * @}
+ */
+
+/* Exported functions -------------------------------------------------------*/
+/** @defgroup FLASHEx_Exported_Functions FLASH Extended Exported Functions
+ * @{
+ */
+
+/** @defgroup FLASHEx_Exported_Functions_Group1 Extended IO operation functions
+ * @brief Extended IO operation functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Extended programming operation functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the Extended FLASH
+ programming operations Operations.
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Perform a mass erase or erase the specified FLASH memory pages.
+ * @param[in] pEraseInit Pointer to an @ref FLASH_EraseInitTypeDef structure that
+ * contains the configuration information for the erasing.
+ * @param[out] PageError Pointer to variable that contains the configuration
+ * information on faulty page in case of error (0xFFFFFFFF means that all
+ * the pages have been correctly erased)
+ * @retval HAL Status
+ */
+HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError)
+{
+ HAL_StatusTypeDef status;
+ uint32_t index;
+
+ /* Check the parameters */
+ assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
+
+ /* Process Locked */
+ __HAL_LOCK(&pFlash);
+
+ /* Reset error code */
+ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
+
+ if (status == HAL_OK)
+ {
+ if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASS)
+ {
+ /* Mass erase to be done */
+ FLASH_MassErase();
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
+ }
+ else
+ {
+ /*Initialization of PageError variable*/
+ *PageError = 0xFFFFFFFFU;
+
+ for (index = pEraseInit->Page; index < (pEraseInit->Page + pEraseInit->NbPages); index++)
+ {
+ /* Start erase page */
+ FLASH_PageErase(index);
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
+
+ if (status != HAL_OK)
+ {
+ /* In case of error, stop erase procedure and return the faulty address */
+ *PageError = index;
+ break;
+ }
+ }
+
+ /* If operation is completed or interrupted, disable the Page Erase Bit */
+ CLEAR_BIT(FLASH->CR, FLASH_CR_PER);
+ }
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(&pFlash);
+
+ /* return status */
+ return status;
+}
+
+
+/**
+ * @brief Perform a mass erase or erase the specified FLASH memory pages with interrupt enabled.
+ * @param pEraseInit Pointer to an @ref FLASH_EraseInitTypeDef structure that
+ * contains the configuration information for the erasing.
+ * @retval HAL Status
+ */
+HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
+{
+ HAL_StatusTypeDef status;
+
+ /* Check the parameters */
+ assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
+
+ /* Process Locked */
+ __HAL_LOCK(&pFlash);
+
+ /* Reset error code */
+ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
+
+ /* save procedure for interrupt treatment */
+ pFlash.ProcedureOnGoing = pEraseInit->TypeErase;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
+
+ if (status != HAL_OK)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(&pFlash);
+ }
+ else
+ {
+ /* Enable End of Operation and Error interrupts */
+ __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_OPERR);
+
+ if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASS)
+ {
+ /* Set Page to 0 for Interrupt callback management */
+ pFlash.Page = 0;
+
+ /* Proceed to Mass Erase */
+ FLASH_MassErase();
+ }
+ else
+ {
+ /* Erase by page to be done */
+ pFlash.NbPagesToErase = pEraseInit->NbPages;
+ pFlash.Page = pEraseInit->Page;
+
+ /*Erase 1st page and wait for IT */
+ FLASH_PageErase(pEraseInit->Page);
+ }
+ }
+
+ /* return status */
+ return status;
+}
+
+/**
+ * @brief Program Option bytes.
+ * @param pOBInit Pointer to an @ref FLASH_OBProgramInitTypeDef structure that
+ * contains the configuration information for the programming.
+ * @note To configure any option bytes, the option lock bit OPTLOCK must be
+ * cleared with the call of @ref HAL_FLASH_OB_Unlock() function.
+ * @note New option bytes configuration will be taken into account only
+ * - after an option bytes launch through the call of @ref HAL_FLASH_OB_Launch()
+ * - a Power On Reset
+ * - an exit from Standby or Shutdown mode.
+ * @retval HAL Status
+ */
+HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)
+{
+ uint32_t optr;
+ HAL_StatusTypeDef status;
+
+ /* Check the parameters */
+ assert_param(IS_OPTIONBYTE(pOBInit->OptionType));
+
+ /* Process Locked */
+ __HAL_LOCK(&pFlash);
+
+ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
+
+ /* Write protection configuration */
+ if ((pOBInit->OptionType & OPTIONBYTE_WRP) != 0x00U)
+ {
+ /* Configure of Write protection on the selected area */
+ FLASH_OB_WRPConfig(pOBInit->WRPArea, pOBInit->WRPStartOffset, pOBInit->WRPEndOffset);
+ }
+
+ /* Option register */
+ if ((pOBInit->OptionType & (OPTIONBYTE_RDP | OPTIONBYTE_USER)) == (OPTIONBYTE_RDP | OPTIONBYTE_USER))
+ {
+ /* Fully modify OPTR register with RDP & user data */
+ FLASH_OB_OptrConfig(pOBInit->USERType, pOBInit->USERConfig, pOBInit->RDPLevel);
+ }
+ else if ((pOBInit->OptionType & OPTIONBYTE_RDP) != 0x00U)
+ {
+ /* Only modify RDP so get current user data */
+ optr = FLASH_OB_GetUser();
+ FLASH_OB_OptrConfig(optr, optr, pOBInit->RDPLevel);
+ }
+ else if ((pOBInit->OptionType & OPTIONBYTE_USER) != 0x00U)
+ {
+ /* Only modify user so get current RDP level */
+ optr = FLASH_OB_GetRDP();
+ FLASH_OB_OptrConfig(pOBInit->USERType, pOBInit->USERConfig, optr);
+ }
+ else
+ {
+ /* nothing to do */
+ }
+
+ /* PCROP Configuration */
+ if ((pOBInit->OptionType & OPTIONBYTE_PCROP) != 0x00U)
+ {
+ /* Check the parameters */
+ assert_param(IS_OB_PCROP_CONFIG(pOBInit->PCROPConfig));
+
+ if ((pOBInit->PCROPConfig & (OB_PCROP_ZONE_A | OB_PCROP_RDP_ERASE)) != 0x00U)
+ {
+ /* Configure the 1A Proprietary code readout protection */
+ FLASH_OB_PCROP1AConfig(pOBInit->PCROPConfig, pOBInit->PCROP1AStartAddr, pOBInit->PCROP1AEndAddr);
+ }
+
+ if ((pOBInit->PCROPConfig & OB_PCROP_ZONE_B) != 0x00U)
+ {
+ /* Configure the 1B Proprietary code readout protection */
+ FLASH_OB_PCROP1BConfig(pOBInit->PCROP1BStartAddr, pOBInit->PCROP1BEndAddr);
+ }
+ }
+
+ /* Securable Memory Area Configuration */
+ if ((pOBInit->OptionType & OPTIONBYTE_SEC) != 0x00U)
+ {
+ /* Configure the securable memory area protection */
+ FLASH_OB_SecMemConfig(pOBInit->BootEntryPoint, pOBInit->SecSize);
+ }
+
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
+
+ if (status == HAL_OK)
+ {
+ /* Set OPTSTRT Bit */
+ SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
+
+ /* If the option byte program operation is completed, disable the OPTSTRT Bit */
+ CLEAR_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(&pFlash);
+
+ /* return status */
+ return status;
+}
+
+/**
+ * @brief Get the Option bytes configuration.
+ * @note warning: this API only read flash register, it does not reflect any
+ * change that would have been programmed between previous Option byte
+ * loading and current call.
+ * @param pOBInit Pointer to an @ref FLASH_OBProgramInitTypeDef structure that contains the
+ * configuration information. The fields pOBInit->WRPArea and
+ * pOBInit->PCROPConfig should indicate which area is requested
+ * for the WRP and PCROP.
+ * @retval None
+ */
+void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)
+{
+ pOBInit->OptionType = OPTIONBYTE_ALL;
+
+ /* Get write protection on the selected area */
+ FLASH_OB_GetWRP(pOBInit->WRPArea, &(pOBInit->WRPStartOffset), &(pOBInit->WRPEndOffset));
+
+ /* Get Read protection level */
+ pOBInit->RDPLevel = FLASH_OB_GetRDP();
+
+ /* Get the user option bytes */
+ pOBInit->USERConfig = FLASH_OB_GetUser();
+ pOBInit->USERType = OB_USER_ALL;
+
+ /* Get the Proprietary code readout protection */
+ FLASH_OB_GetPCROP1A(&(pOBInit->PCROPConfig), &(pOBInit->PCROP1AStartAddr), &(pOBInit->PCROP1AEndAddr));
+ FLASH_OB_GetPCROP1B(&(pOBInit->PCROP1BStartAddr), &(pOBInit->PCROP1BEndAddr));
+ pOBInit->PCROPConfig |= (OB_PCROP_ZONE_A | OB_PCROP_ZONE_B);
+
+ /* Get the Securable Memory Area protection */
+ FLASH_OB_GetSecMem(&(pOBInit->BootEntryPoint), &(pOBInit->SecSize));
+}
+
+/**
+ * @brief Enable Debugger.
+ * @note After calling this API, flash interface allow debugger intrusion.
+ * @retval None
+ */
+void HAL_FLASHEx_EnableDebugger(void)
+{
+ FLASH->ACR |= FLASH_ACR_DBG_SWEN;
+}
+
+/**
+ * @brief Disable Debugger.
+ * @note After calling this API, Debugger is disabled: it is no more possible to
+ * break, see CPU register, etc...
+ * @retval None
+ */
+void HAL_FLASHEx_DisableDebugger(void)
+{
+ FLASH->ACR &= ~FLASH_ACR_DBG_SWEN;
+}
+
+/**
+ * @brief Flash Empty check
+ * @note This API checks if first location in Flash is programmed or not.
+ * This check is done once by Option Byte Loader.
+ * @retval 0 if 1st location is not programmed else
+ */
+uint32_t HAL_FLASHEx_FlashEmptyCheck(void)
+{
+ return ((FLASH->ACR & FLASH_ACR_PROGEMPTY));
+}
+
+
+/**
+ * @brief Force Empty check value.
+ * @note Allows to modify program empty check value in order to force this
+ * infrmation in Flash Interface, for all next reset that do not launch
+ * Option Byte Loader.
+ * @param FlashEmpty this parameter can be a value of @ref FLASHEx_Empty_Check
+ * @retval None
+ */
+void HAL_FLASHEx_ForceFlashEmpty(uint32_t FlashEmpty)
+{
+ uint32_t acr;
+ assert_param(IS_FLASH_EMPTY_CHECK(FlashEmpty));
+
+ acr = (FLASH->ACR & ~FLASH_ACR_PROGEMPTY);
+ FLASH->ACR = (acr | FlashEmpty);
+}
+
+/**
+ * @brief Securable memory area protection enable
+ * @param Bank Select Bank to be secured. On C0, there is only 1 bank so
+ * parameter has to be set to 0.
+ * @note This API locks Securable memory area which is defined in SEC_SIZE option byte
+ * (that can be retrieved calling HAL_FLASHEx_OBGetConfig API and checking
+ * Secsize).
+ * @note SEC_PROT bit can only be set, it will be reset by system reset.
+ * @retval None
+ */
+void HAL_FLASHEx_EnableSecMemProtection(uint32_t Bank)
+{
+ assert_param(IS_FLASH_BANK(Bank));
+ FLASH->CR |= FLASH_CR_SEC_PROT;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @addtogroup FLASHEx_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Mass erase of FLASH memory.
+ * @retval None
+ */
+static void FLASH_MassErase(void)
+{
+ /* Set the Mass Erase Bit and start bit */
+ FLASH->CR |= (FLASH_CR_STRT | FLASH_CR_MER1);
+}
+
+/**
+ * @brief Erase the specified FLASH memory page.
+ * @param Page FLASH page to erase
+ * This parameter must be a value between 0 and (max number of pages in Flash - 1)
+ * @retval None
+ */
+void FLASH_PageErase(uint32_t Page)
+{
+ uint32_t tmp;
+
+ /* Check the parameters */
+ assert_param(IS_FLASH_PAGE(Page));
+
+ /* Get configuration register, then clear page number */
+ tmp = (FLASH->CR & ~FLASH_CR_PNB);
+
+ /* Set page number, Page Erase bit & Start bit */
+ FLASH->CR = (tmp | (FLASH_CR_STRT | (Page << FLASH_CR_PNB_Pos) | FLASH_CR_PER));
+}
+
+/**
+ * @brief Flush the instruction cache.
+ * @retval None
+ */
+void FLASH_FlushCaches(void)
+{
+ /* Flush instruction cache */
+ if (READ_BIT(FLASH->ACR, FLASH_ACR_ICEN) != 0U)
+ {
+ /* Disable instruction cache */
+ __HAL_FLASH_INSTRUCTION_CACHE_DISABLE();
+ /* Reset instruction cache */
+ __HAL_FLASH_INSTRUCTION_CACHE_RESET();
+ /* Enable instruction cache */
+ __HAL_FLASH_INSTRUCTION_CACHE_ENABLE();
+ }
+}
+
+
+/**
+ * @brief Configure the write protection of the desired pages.
+ * @note When WRP is active in a zone, it cannot be erased or programmed.
+ * Consequently, a software mass erase cannot be performed if one zone
+ * is write-protected.
+ * @note When the memory read protection level is selected (RDP level = 1),
+ * it is not possible to program or erase Flash memory if the CPU debug
+ * features are connected (JTAG or single wire) or boot code is being
+ * executed from RAM or System flash, even if WRP is not activated.
+ * @param WRPArea Specifies the area to be configured.
+ * This parameter can be one of the following values:
+ * @arg @ref OB_WRPAREA_ZONE_A Flash Zone A
+ * @arg @ref OB_WRPAREA_ZONE_B Flash Zone B
+ * @param WRPStartOffset Specifies the start page of the write protected area
+ * This parameter can be page number between 0 and (max number of pages in the Flash - 1)
+ * @param WRDPEndOffset Specifies the end page of the write protected area
+ * This parameter can be page number between WRPStartOffset and (max number of pages in the Flash - 1)
+ * @retval None
+ */
+static void FLASH_OB_WRPConfig(uint32_t WRPArea, uint32_t WRPStartOffset, uint32_t WRDPEndOffset)
+{
+ /* Check the parameters */
+ assert_param(IS_OB_WRPAREA(WRPArea));
+ assert_param(IS_FLASH_PAGE(WRPStartOffset));
+ assert_param(IS_FLASH_PAGE(WRDPEndOffset));
+
+ /* Configure the write protected area */
+ if (WRPArea != OB_WRPAREA_ZONE_A)
+ {
+ FLASH->WRP1BR = ((WRDPEndOffset << FLASH_WRP1AR_WRP1A_END_Pos) | WRPStartOffset);
+ }
+ else
+ {
+ FLASH->WRP1AR = ((WRDPEndOffset << FLASH_WRP1BR_WRP1B_END_Pos) | WRPStartOffset);
+ }
+}
+
+/**
+ * @brief Set user & RDP configuration
+ * @note !!! Warning : When enabling OB_RDP level 2 it is no more possible
+ * to go back to level 1 or 0 !!!
+ * @param UserType The FLASH User Option Bytes to be modified.
+ * This parameter can be a combination of @ref FLASH_OB_USER_Type
+ * @param UserConfig The FLASH User Option Bytes values.
+ * This parameter can be a combination of:
+ * @arg @ref FLASH_OB_USER_BOR_LEVEL,
+ * @arg @ref FLASH_OB_USER_nRST_STOP,
+ * @arg @ref FLASH_OB_USER_nRST_STANDBY,
+ * @arg @ref FLASH_OB_USER_nRST_SHUTDOWN,
+ * @arg @ref FLASH_OB_USER_IWDG_SW,
+ * @arg @ref FLASH_OB_USER_IWDG_STOP,
+ * @arg @ref FLASH_OB_USER_IWDG_STANDBY,
+ * @arg @ref FLASH_OB_USER_WWDG_SW,
+ * @arg @ref FLASH_OB_USER_SRAM_PARITY,
+ * @arg @ref FLASH_OB_USER_nBOOT_SEL,
+ * @arg @ref FLASH_OB_USER_nBOOT1,
+ * @arg @ref FLASH_OB_USER_nBOOT0,
+ * @arg @ref FLASH_OB_USER_INPUT_RESET_HOLDER
+ * @param RDPLevel specifies the read protection level.
+ * This parameter can be one of the following values:
+ * @arg @ref OB_RDP_LEVEL_0 No protection
+ * @arg @ref OB_RDP_LEVEL_1 Memory Read protection
+ * @arg @ref OB_RDP_LEVEL_2 Full chip protection
+ * @retval None
+ */
+static void FLASH_OB_OptrConfig(uint32_t UserType, uint32_t UserConfig, uint32_t RDPLevel)
+{
+ uint32_t optr;
+
+ /* Check the parameters */
+ assert_param(IS_OB_USER_TYPE(UserType));
+ assert_param(IS_OB_USER_CONFIG(UserType, UserConfig));
+ assert_param(IS_OB_RDP_LEVEL(RDPLevel));
+
+ /* Configure the RDP level in the option bytes register */
+ optr = FLASH->OPTR;
+ optr &= ~(UserType | FLASH_OPTR_RDP);
+ FLASH->OPTR = (optr | UserConfig | RDPLevel);
+}
+
+/**
+ * @brief Configure the 1A Proprietary code readout protection & erase configuration on RDP regression.
+ * @note It is recommended to align PCROP zone with page granularity when using PCROP_RDP or avoid
+ * having some executable code in a page where PCROP zone starts or ends.
+ * @note Minimum PCROP area size is 2 times the chosen granularity: PCROPA_STRT and PCROPA_END.
+ * So if the requirement is to be able to read-protect 1KB areas, the ROP granularity
+ * has to be set to 512 Bytes
+ * @param PCROPConfig specifies the erase configuration (OB_PCROP_RDP_NOT_ERASE or OB_PCROP_RDP_ERASE)
+ * on RDP level 1 regression.
+ * @param PCROP1AStartAddr Specifies the Zone 1A Start address of the Proprietary code readout protection
+ * This parameter can be an address between begin and end of the flash
+ * @param PCROP1AEndAddr Specifies the Zone 1A end address of the Proprietary code readout protection
+ * This parameter can be an address between PCROP1AStartAddr and end of the flash
+ * @retval None
+ */
+static void FLASH_OB_PCROP1AConfig(uint32_t PCROPConfig, uint32_t PCROP1AStartAddr, uint32_t PCROP1AEndAddr)
+{
+ uint32_t startoffset;
+ uint32_t endoffset;
+ uint32_t pcrop1aend;
+
+ /* Check the parameters */
+ assert_param(IS_OB_PCROP_CONFIG(PCROPConfig));
+ assert_param(IS_FLASH_MAIN_MEM_ADDRESS(PCROP1AStartAddr));
+ assert_param(IS_FLASH_MAIN_MEM_ADDRESS(PCROP1AEndAddr));
+
+ /* get pcrop 1A end register */
+ pcrop1aend = FLASH->PCROP1AER;
+
+ /* Configure the Proprietary code readout protection offset */
+ if ((PCROPConfig & OB_PCROP_ZONE_A) != 0x00U)
+ {
+ /* Compute offset depending on pcrop granularity */
+ startoffset = ((PCROP1AStartAddr - FLASH_BASE) >> FLASH_PCROP_GRANULARITY_OFFSET);
+ endoffset = ((PCROP1AEndAddr - FLASH_BASE) >> FLASH_PCROP_GRANULARITY_OFFSET);
+
+ /* Set Zone A start offset */
+ FLASH->PCROP1ASR = startoffset;
+
+ /* Set Zone A end offset */
+ pcrop1aend &= ~FLASH_PCROP1AER_PCROP1A_END;
+ pcrop1aend |= endoffset;
+ }
+
+ /* Set RDP erase protection if needed. This bit is only set & will be reset by mass erase */
+ if ((PCROPConfig & OB_PCROP_RDP_ERASE) != 0x00U)
+ {
+ pcrop1aend |= FLASH_PCROP1AER_PCROP_RDP;
+ }
+
+ /* set 1A End register */
+ FLASH->PCROP1AER = pcrop1aend;
+}
+
+/**
+ * @brief Configure the 1B Proprietary code readout protection.
+ * @note It is recommended to align PCROP zone with page granularity when using PCROP_RDP or avoid
+ * having some executable code in a page where PCROP zone starts or ends.
+ * @note Minimum PCROP area size is 2 times the chosen granularity: PCROPA_STRT and PCROPA_END.
+ * So if the requirement is to be able to read-protect 1KB areas, the ROP granularity
+ * has to be set to 512 Bytes
+ * @param PCROP1BStartAddr Specifies the Zone 1B Start address of the Proprietary code readout protection
+ * This parameter can be an address between begin and end of the flash
+ * @param PCROP1BEndAddr Specifies the Zone 1B end address of the Proprietary code readout protection
+ * This parameter can be an address between PCROP1BStartAddr and end of the flash
+ * @retval None
+ */
+static void FLASH_OB_PCROP1BConfig(uint32_t PCROP1BStartAddr, uint32_t PCROP1BEndAddr)
+{
+ uint32_t startoffset;
+ uint32_t endoffset;
+
+ /* Check the parameters */
+ assert_param(IS_FLASH_MAIN_MEM_ADDRESS(PCROP1BStartAddr));
+ assert_param(IS_FLASH_MAIN_MEM_ADDRESS(PCROP1BEndAddr));
+
+ /* Configure the Proprietary code readout protection offset */
+ startoffset = ((PCROP1BStartAddr - FLASH_BASE) >> FLASH_PCROP_GRANULARITY_OFFSET);
+ endoffset = ((PCROP1BEndAddr - FLASH_BASE) >> FLASH_PCROP_GRANULARITY_OFFSET);
+
+ /* Set Zone B start offset */
+ FLASH->PCROP1BSR = startoffset;
+ /* Set Zone B end offset */
+ FLASH->PCROP1BER = endoffset;
+}
+
+/**
+ * @brief Configure Securable Memory area feature.
+ * @param BootEntry specifies if boot scheme is forced to Flash (System or user) or not
+ * This parameter can be one of the following values:
+ * @arg @ref OB_BOOT_ENTRY_FORCED_NONE No boot entry forced
+ * @arg @ref OB_BOOT_ENTRY_FORCED_FLASH FLash selected as unique entry boot
+ * @param SecSize specifies number of pages to protect as securable memory area, starting from
+ * beginning of the Flash (page 0).
+ * @retval None
+ */
+static void FLASH_OB_SecMemConfig(uint32_t BootEntry, uint32_t SecSize)
+{
+ uint32_t secmem;
+
+ /* Check the parameters */
+ assert_param(IS_OB_SEC_BOOT_LOCK(BootEntry));
+ assert_param(IS_OB_SEC_SIZE(SecSize));
+
+ /* Set securable memory area configuration */
+ secmem = (FLASH->SECR & ~(FLASH_SECR_BOOT_LOCK | FLASH_SECR_SEC_SIZE));
+ FLASH->SECR = (secmem | BootEntry | SecSize);
+}
+
+/**
+ * @brief Return the FLASH Write Protection Option Bytes value.
+ * @param[in] WRPArea Specifies the area to be returned.
+ * This parameter can be one of the following values:
+ * @arg @ref OB_WRPAREA_ZONE_A Flash Zone A
+ * @arg @ref OB_WRPAREA_ZONE_B Flash Zone B
+ * @param[out] WRPStartOffset Specifies the address where to copied the start page
+ * of the write protected area
+ * @param[out] WRDPEndOffset Dpecifies the address where to copied the end page of
+ * the write protected area
+ * @retval None
+ */
+static void FLASH_OB_GetWRP(uint32_t WRPArea, uint32_t *WRPStartOffset, uint32_t *WRDPEndOffset)
+{
+ /* Check the parameters */
+ assert_param(IS_OB_WRPAREA(WRPArea));
+
+ /* Get the configuration of the write protected area */
+ if (WRPArea == OB_WRPAREA_ZONE_A)
+ {
+ *WRPStartOffset = READ_BIT(FLASH->WRP1AR, FLASH_WRP1AR_WRP1A_STRT);
+ *WRDPEndOffset = (READ_BIT(FLASH->WRP1AR, FLASH_WRP1AR_WRP1A_END) >> FLASH_WRP1AR_WRP1A_END_Pos);
+ }
+ else
+ {
+ *WRPStartOffset = READ_BIT(FLASH->WRP1BR, FLASH_WRP1BR_WRP1B_STRT);
+ *WRDPEndOffset = (READ_BIT(FLASH->WRP1BR, FLASH_WRP1BR_WRP1B_END) >> FLASH_WRP1BR_WRP1B_END_Pos);
+ }
+}
+
+/**
+ * @brief Return the FLASH Read Protection level.
+ * @retval FLASH ReadOut Protection Status:
+ * This return value can be one of the following values:
+ * @arg @ref OB_RDP_LEVEL_0 No protection
+ * @arg @ref OB_RDP_LEVEL_1 Read protection of the memory
+ * @arg @ref OB_RDP_LEVEL_2 Full chip protection
+ */
+static uint32_t FLASH_OB_GetRDP(void)
+{
+ uint32_t rdplvl = READ_BIT(FLASH->OPTR, FLASH_OPTR_RDP);
+
+ if ((rdplvl != OB_RDP_LEVEL_0) && (rdplvl != OB_RDP_LEVEL_2))
+ {
+ return (OB_RDP_LEVEL_1);
+ }
+ else
+ {
+ return rdplvl;
+ }
+}
+
+/**
+ * @brief Return the FLASH User Option Byte value.
+ * @retval The FLASH User Option Bytes values. It will be a combination of all the following values:
+ * @ref FLASH_OB_USER_BOR_LEVEL,
+ * @ref FLASH_OB_USER_nRST_STOP,
+ * @ref FLASH_OB_USER_nRST_STANDBY,
+ * @ref FLASH_OB_USER_nRST_SHUTDOWN,
+ * @ref FLASH_OB_USER_IWDG_SW,
+ * @ref FLASH_OB_USER_IWDG_STOP,
+ * @ref FLASH_OB_USER_IWDG_STANDBY,
+ * @ref FLASH_OB_USER_WWDG_SW,
+ * @ref FLASH_OB_USER_SRAM_PARITY,
+ * @ref FLASH_OB_USER_nBOOT_SEL,
+ * @ref FLASH_OB_USER_nBOOT1,
+ * @ref FLASH_OB_USER_nBOOT0,
+ * @ref FLASH_OB_USER_INPUT_RESET_HOLDER
+ */
+static uint32_t FLASH_OB_GetUser(void)
+{
+ uint32_t user = ((FLASH->OPTR & ~FLASH_OPTR_RDP) & OB_USER_ALL);
+ return user;
+}
+
+/**
+ * @brief Return the FLASH PCROP Protection Option Bytes value.
+ * @param PCROPConfig [out] specifies the configuration of PCROP_RDP option.
+ * @param PCROP1AStartAddr [out] Specifies the address where to copied the start address
+ * of the 1A Proprietary code readout protection
+ * @param PCROP1AEndAddr [out] Specifies the address where to copied the end address of
+ * the 1A Proprietary code readout protection
+ * @retval None
+ */
+static void FLASH_OB_GetPCROP1A(uint32_t *PCROPConfig, uint32_t *PCROP1AStartAddr, uint32_t *PCROP1AEndAddr)
+{
+ uint32_t pcrop;
+
+ pcrop = (FLASH->PCROP1ASR & FLASH_PCROP1ASR_PCROP1A_STRT);
+ *PCROP1AStartAddr = (pcrop << FLASH_PCROP_GRANULARITY_OFFSET);
+ *PCROP1AStartAddr += FLASH_BASE;
+
+ pcrop = FLASH->PCROP1AER;
+ *PCROP1AEndAddr = ((pcrop & FLASH_PCROP1AER_PCROP1A_END) << FLASH_PCROP_GRANULARITY_OFFSET);
+ *PCROP1AEndAddr += (FLASH_BASE + FLASH_PCROP_GRANULARITY - 1U);
+
+ *PCROPConfig &= ~OB_PCROP_RDP_ERASE;
+ *PCROPConfig |= (pcrop & FLASH_PCROP1AER_PCROP_RDP);
+}
+
+
+/**
+ * @brief Return the FLASH PCROP Protection Option Bytes value.
+ * @param PCROP1BStartAddr [out] Specifies the address where to copied the start address
+ * of the 1B Proprietary code readout protection
+ * @param PCROP1BEndAddr [out] Specifies the address where to copied the end address of
+ * the 1B Proprietary code readout protection
+ * @retval None
+ */
+static void FLASH_OB_GetPCROP1B(uint32_t *PCROP1BStartAddr, uint32_t *PCROP1BEndAddr)
+{
+ uint32_t pcrop;
+
+ pcrop = (FLASH->PCROP1BSR & FLASH_PCROP1BSR_PCROP1B_STRT);
+ *PCROP1BStartAddr = (pcrop << FLASH_PCROP_GRANULARITY_OFFSET);
+ *PCROP1BStartAddr += FLASH_BASE;
+
+ pcrop = (FLASH->PCROP1BER & FLASH_PCROP1BER_PCROP1B_END);
+ *PCROP1BEndAddr = (pcrop << FLASH_PCROP_GRANULARITY_OFFSET);
+ *PCROP1BEndAddr += (FLASH_BASE + FLASH_PCROP_GRANULARITY - 1U);
+}
+
+/**
+ * @brief Return the FLASH Securable memory area protection Option Bytes value.
+ * @param BootEntry specifies boot scheme configuration
+ * @param SecSize specifies number of pages to protect as secure memory area, starting from
+ * beginning of the Flash (page 0).
+ * @retval None
+ */
+static void FLASH_OB_GetSecMem(uint32_t *BootEntry, uint32_t *SecSize)
+{
+ uint32_t secmem = FLASH->SECR;
+
+ *BootEntry = (secmem & FLASH_SECR_BOOT_LOCK);
+ *SecSize = (secmem & FLASH_SECR_SEC_SIZE);
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.c b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.c
new file mode 100644
index 0000000000..97d43b512d
--- /dev/null
+++ b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.c
@@ -0,0 +1,557 @@
+/**
+ ******************************************************************************
+ * @file stm32c0xx_hal_gpio.c
+ * @author MCD Application Team
+ * @brief GPIO HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the General Purpose Input/Output (GPIO) peripheral:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2022 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### GPIO Peripheral features #####
+ ==============================================================================
+ [..]
+ (+) Each port bit of the general-purpose I/O (GPIO) ports can be individually
+ configured by software in several modes:
+ (++) Input mode
+ (++) Analog mode
+ (++) Output mode
+ (++) Alternate function mode
+ (++) External interrupt/event lines
+
+ (+) During and just after reset, the alternate functions and external interrupt
+ lines are not active and the I/O ports are configured in input floating mode.
+
+ (+) All GPIO pins have weak internal pull-up and pull-down resistors, which can be
+ activated or not.
+
+ (+) In Output or Alternate mode, each IO can be configured on open-drain or push-pull
+ type and the IO speed can be selected depending on the VDD value.
+
+ (+) The microcontroller IO pins are connected to onboard peripherals/modules through a
+ multiplexer that allows only one peripheral alternate function (AF) connected
+ to an IO pin at a time. In this way, there can be no conflict between peripherals
+ sharing the same IO pin.
+
+ (+) All ports have external interrupt/event capability. To use external interrupt
+ lines, the port must be configured in input mode. All available GPIO pins are
+ connected to the 16 external interrupt/event lines from EXTI0 to EXTI15.
+
+ (+) The external interrupt/event controller consists of up to 28 edge detectors
+ (16 lines are connected to GPIO) for generating event/interrupt requests (each
+ input line can be independently configured to select the type (interrupt or event)
+ and the corresponding trigger event (rising or falling or both). Each line can
+ also be masked independently.
+
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ (#) Enable the GPIO AHB clock using the following function: __HAL_RCC_GPIOx_CLK_ENABLE().
+
+ (#) Configure the GPIO pin(s) using HAL_GPIO_Init().
+ (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure
+ (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef
+ structure.
+ (++) In case of Output or alternate function mode selection: the speed is
+ configured through "Speed" member from GPIO_InitTypeDef structure.
+ (++) In alternate mode is selection, the alternate function connected to the IO
+ is configured through "Alternate" member from GPIO_InitTypeDef structure.
+ (++) Analog mode is required when a pin is to be used as ADC channel
+ or DAC output.
+ (++) In case of external interrupt/event selection the "Mode" member from
+ GPIO_InitTypeDef structure select the type (interrupt or event) and
+ the corresponding trigger event (rising or falling or both).
+
+ (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority
+ mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using
+ HAL_NVIC_EnableIRQ().
+
+ (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin().
+
+ (#) To set/reset the level of a pin configured in output mode use
+ HAL_GPIO_WritePin()/HAL_GPIO_TogglePin().
+
+ (#) To lock pin configuration until next reset use HAL_GPIO_LockPin().
+
+ (#) During and just after reset, the alternate functions are not
+ active and the GPIO pins are configured in input floating mode (except JTAG
+ pins).
+
+ (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose
+ (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has
+ priority over the GPIO function.
+
+ (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as
+ general purpose PF0 and PF1, respectively, when the HSE oscillator is off.
+ The HSE has priority over the GPIO function.
+
+ @endverbatim
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32c0xx_hal.h"
+
+/** @addtogroup STM32C0xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup GPIO GPIO
+ * @brief GPIO HAL module driver
+ * @{
+ */
+#ifdef HAL_GPIO_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private defines -----------------------------------------------------------*/
+/** @defgroup GPIO_Private_Defines GPIO Private Defines
+ * @{
+ */
+#define GPIO_MODE (0x00000003U)
+#define EXTI_MODE (0x10000000U)
+#define GPIO_MODE_IT (0x00010000U)
+#define GPIO_MODE_EVT (0x00020000U)
+#define RISING_EDGE (0x00100000U)
+#define FALLING_EDGE (0x00200000U)
+#define GPIO_OUTPUT_TYPE (0x00000010U)
+#define GPIO_NUMBER (16U)
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup GPIO_Private_Macros GPIO Private Macros
+ * @{
+ */
+/**
+ * @}
+ */
+
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup GPIO_Exported_Functions GPIO Exported Functions
+ * @{
+ */
+
+/** @defgroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initialize the GPIOx peripheral according to the specified parameters in the GPIO_Init.
+ * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32C0xx family
+ * @param pGPIO_Init pointer to a GPIO_InitTypeDef structure that contains
+ * the configuration information for the specified GPIO peripheral.
+ * @retval None
+ */
+void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, const GPIO_InitTypeDef *pGPIO_Init)
+{
+ uint32_t tmp;
+ uint32_t iocurrent;
+ uint32_t position = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+ assert_param(IS_GPIO_PIN(pGPIO_Init->Pin));
+ assert_param(IS_GPIO_MODE(pGPIO_Init->Mode));
+
+ /* Configure the port pins */
+ while (((pGPIO_Init->Pin) >> position) != 0U)
+ {
+ /* Get current io position */
+ iocurrent = (pGPIO_Init->Pin) & (1UL << position);
+
+ if (iocurrent != 0U)
+ {
+ /*--------------------- GPIO Mode Configuration ------------------------*/
+ /* In case of Alternate function mode selection */
+ if ((pGPIO_Init->Mode == GPIO_MODE_AF_PP) || (pGPIO_Init->Mode == GPIO_MODE_AF_OD))
+ {
+ /* Check the Alternate function parameters */
+ assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
+ assert_param(IS_GPIO_AF(pGPIO_Init->Alternate));
+
+ /* Configure Alternate function mapped with the current IO */
+ tmp = GPIOx->AFR[position >> 3U];
+ tmp &= ~(0xFUL << ((position & 0x07U) * 4U)) ;
+ tmp |= ((pGPIO_Init->Alternate & 0x0FUL) << ((position & 0x07U) * 4U));
+ GPIOx->AFR[position >> 3U] = tmp;
+ }
+
+ /* Configure IO Direction mode (Input, Output, Alternate or Analog) */
+ tmp = GPIOx->MODER;
+ tmp &= ~(GPIO_MODER_MODE0 << (position * 2U));
+ tmp |= ((pGPIO_Init->Mode & GPIO_MODE) << (position * 2U));
+ GPIOx->MODER = tmp;
+
+ /* In case of Output or Alternate function mode selection */
+ if ((pGPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (pGPIO_Init->Mode == GPIO_MODE_AF_PP) ||
+ (pGPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (pGPIO_Init->Mode == GPIO_MODE_AF_OD))
+ {
+ /* Check the Speed parameter */
+ assert_param(IS_GPIO_SPEED(pGPIO_Init->Speed));
+
+ /* Configure the IO Speed */
+ tmp = GPIOx->OSPEEDR;
+ tmp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U));
+ tmp |= (pGPIO_Init->Speed << (position * 2U));
+ GPIOx->OSPEEDR = tmp;
+
+ /* Configure the IO Output Type */
+ tmp = GPIOx->OTYPER;
+ tmp &= ~(GPIO_OTYPER_OT0 << position) ;
+ tmp |= (((pGPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4U) << position);
+ GPIOx->OTYPER = tmp;
+ }
+
+ if (pGPIO_Init->Mode != GPIO_MODE_ANALOG)
+ {
+ /* Check the Pull parameters */
+ assert_param(IS_GPIO_PULL(pGPIO_Init->Pull));
+
+ /* Activate the Pull-up or Pull down resistor for the current IO */
+ tmp = GPIOx->PUPDR;
+ tmp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U));
+ tmp |= ((pGPIO_Init->Pull) << (position * 2U));
+ GPIOx->PUPDR = tmp;
+ }
+
+ /*--------------------- EXTI Mode Configuration ------------------------*/
+ /* Configure the External Interrupt or event for the current IO */
+ if ((pGPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
+ {
+ tmp = EXTI->EXTICR[position >> 2U];
+ tmp &= ~((0x0FUL) << (8U * (position & 0x03U)));
+ tmp |= (GPIO_GET_INDEX(GPIOx) << (8U * (position & 0x03U)));
+ EXTI->EXTICR[position >> 2U] = tmp;
+
+ /* Clear EXTI line configuration */
+ tmp = EXTI->IMR1;
+ tmp &= ~((uint32_t)iocurrent);
+ if ((pGPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
+ {
+ tmp |= iocurrent;
+ }
+ EXTI->IMR1 = tmp;
+
+ tmp = EXTI->EMR1;
+ tmp &= ~((uint32_t)iocurrent);
+ if ((pGPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
+ {
+ tmp |= iocurrent;
+ }
+ EXTI->EMR1 = tmp;
+
+ /* Clear Rising Falling edge configuration */
+ tmp = EXTI->RTSR1;
+ tmp &= ~((uint32_t)iocurrent);
+ if ((pGPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
+ {
+ tmp |= iocurrent;
+ }
+ EXTI->RTSR1 = tmp;
+
+ tmp = EXTI->FTSR1;
+ tmp &= ~((uint32_t)iocurrent);
+ if ((pGPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
+ {
+ tmp |= iocurrent;
+ }
+ EXTI->FTSR1 = tmp;
+ }
+ }
+
+ position++;
+ }
+}
+
+/**
+ * @brief De-initialize the GPIOx peripheral registers to their default reset values.
+ * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32C0xx family
+ * @param GPIO_Pin specifies the port bit to be written.
+ * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+ * @retval None
+ */
+void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
+{
+ uint32_t tmp;
+ uint32_t iocurrent;
+ uint32_t position = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+ assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+ /* Configure the port pins */
+ while ((GPIO_Pin >> position) != 0U)
+ {
+ /* Get current io position */
+ iocurrent = (GPIO_Pin) & (1UL << position);
+
+ if (iocurrent != 0U)
+ {
+ /*------------------------- EXTI Mode Configuration --------------------*/
+ /* Clear the External Interrupt or Event for the current IO */
+ tmp = EXTI->EXTICR[position >> 2U];
+ tmp &= ((0x0FUL) << (8U * (position & 0x03U)));
+ if (tmp == (GPIO_GET_INDEX(GPIOx) << (8U * (position & 0x03U))))
+ {
+ /* Clear EXTI line configuration */
+ EXTI->IMR1 &= ~(iocurrent);
+ EXTI->EMR1 &= ~(iocurrent);
+
+ /* Clear Rising Falling edge configuration */
+ EXTI->RTSR1 &= ~(iocurrent);
+ EXTI->FTSR1 &= ~(iocurrent);
+
+ tmp = (0x0FUL) << (8U * (position & 0x03U));
+ EXTI->EXTICR[position >> 2U] &= ~tmp;
+ }
+
+ /*------------------------- GPIO Mode Configuration --------------------*/
+ /* Configure IO in Analog Mode */
+ GPIOx->MODER |= (GPIO_MODER_MODE0 << (position * 2U));
+
+ /* Configure the default Alternate Function in current IO */
+ GPIOx->AFR[position >> 3U] &= ~(0x0FUL << ((position & 0x07U) * 4U)) ;
+
+ /* Configure the default value for IO Speed */
+ GPIOx->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U));
+
+ /* Configure the default value IO Output Type */
+ GPIOx->OTYPER &= ~(GPIO_OTYPER_OT0 << position);
+
+ /* Deactivate the Pull-up and Pull-down resistor for the current IO */
+ GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (position * 2U));
+ }
+
+ position++;
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup GPIO_Exported_Functions_Group2
+ * @brief GPIO Read, Write, Toggle, Lock and EXTI management functions.
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Read the specified input port pin.
+ * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32C0xx family
+ * @param GPIO_Pin specifies the port bit to read.
+ * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+ * @retval The input port pin value.
+ */
+GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
+{
+ GPIO_PinState bitstatus;
+
+ /* Check the parameters */
+ assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+ if ((GPIOx->IDR & GPIO_Pin) != 0U)
+ {
+ bitstatus = GPIO_PIN_SET;
+ }
+ else
+ {
+ bitstatus = GPIO_PIN_RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Set or clear the selected data port bit.
+ *
+ * @note This function uses GPIOx_BSRR and GPIOx_BRR registers to allow atomic read/modify
+ * accesses. In this way, there is no risk of an IRQ occurring between
+ * the read and the modify access.
+ *
+ * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32C0xx family
+ * @param GPIO_Pin specifies the port bit to be written.
+ * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+ * @param PinState specifies the value to be written to the selected bit.
+ * This parameter can be one of the GPIO_PinState enum values:
+ * @arg GPIO_PIN_RESET: to clear the port pin
+ * @arg GPIO_PIN_SET: to set the port pin
+ * @retval None
+ */
+void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
+{
+ /* Check the parameters */
+ assert_param(IS_GPIO_PIN(GPIO_Pin));
+ assert_param(IS_GPIO_PIN_ACTION(PinState));
+
+ if (PinState != GPIO_PIN_RESET)
+ {
+ GPIOx->BSRR = (uint32_t)GPIO_Pin;
+ }
+ else
+ {
+ GPIOx->BRR = (uint32_t)GPIO_Pin;
+ }
+}
+
+/**
+ * @brief Toggle the specified GPIO pin.
+ * @param GPIOx: where x can be (A..I) to select the GPIO peripheral for STM32C0 family
+ * @param GPIO_Pin: specifies the pin to be toggled.
+ * @retval None
+ */
+void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
+{
+ uint32_t odr;
+
+ /* Check the parameters */
+ assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+ /* get current Output Data Register value */
+ odr = GPIOx->ODR;
+
+ /* Set selected pins that were at low level, and reset ones that were high */
+ GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin);
+}
+
+/**
+ * @brief Lock GPIO Pins configuration registers.
+ * @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,
+ * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
+ * @note The configuration of the locked GPIO pins can no longer be modified
+ * until the next reset.
+ * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32C0xx family
+ * @param GPIO_Pin specifies the port bits to be locked.
+ * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+ * @retval None
+ */
+HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
+{
+ __IO uint32_t tmp = GPIO_LCKR_LCKK;
+
+ /* Check the parameters */
+ assert_param(IS_GPIO_LOCK_INSTANCE(GPIOx));
+ assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+ /* Apply lock key write sequence */
+ tmp |= GPIO_Pin;
+ /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
+ GPIOx->LCKR = tmp;
+ /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */
+ GPIOx->LCKR = GPIO_Pin;
+ /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
+ GPIOx->LCKR = tmp;
+ /* Read LCKK bit*/
+ tmp = GPIOx->LCKR;
+
+ /* read again in order to confirm lock is active */
+ if ((GPIOx->LCKR & GPIO_LCKR_LCKK) != GPIO_LCKR_LCKK)
+ {
+ return HAL_ERROR;
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle EXTI interrupt request.
+ * @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line.
+ * @retval None
+ */
+void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
+{
+ /* EXTI line interrupt detected */
+ if (__HAL_GPIO_EXTI_GET_RISING_IT(GPIO_Pin) != 0U)
+ {
+ __HAL_GPIO_EXTI_CLEAR_RISING_IT(GPIO_Pin);
+ HAL_GPIO_EXTI_Rising_Callback(GPIO_Pin);
+ }
+
+ if (__HAL_GPIO_EXTI_GET_FALLING_IT(GPIO_Pin) != 0U)
+ {
+ __HAL_GPIO_EXTI_CLEAR_FALLING_IT(GPIO_Pin);
+ HAL_GPIO_EXTI_Falling_Callback(GPIO_Pin);
+ }
+}
+
+/**
+ * @brief EXTI line detection callback.
+ * @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line.
+ * @retval None
+ */
+__weak void HAL_GPIO_EXTI_Rising_Callback(uint16_t GPIO_Pin)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(GPIO_Pin);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_GPIO_EXTI_Rising_Callback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief EXTI line detection callback.
+ * @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line.
+ * @retval None
+ */
+__weak void HAL_GPIO_EXTI_Falling_Callback(uint16_t GPIO_Pin)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(GPIO_Pin);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_GPIO_EXTI_Falling_Callback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+#endif /* HAL_GPIO_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_i2c.c b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_i2c.c
new file mode 100644
index 0000000000..742a5bc2f9
--- /dev/null
+++ b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_i2c.c
@@ -0,0 +1,6884 @@
+/**
+ ******************************************************************************
+ * @file stm32c0xx_hal_i2c.c
+ * @author MCD Application Team
+ * @brief I2C HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Inter Integrated Circuit (I2C) peripheral:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral State and Errors functions
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2022 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ The I2C HAL driver can be used as follows:
+
+ (#) Declare a I2C_HandleTypeDef handle structure, for example:
+ I2C_HandleTypeDef hi2c;
+
+ (#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API:
+ (##) Enable the I2Cx interface clock
+ (##) I2C pins configuration
+ (+++) Enable the clock for the I2C GPIOs
+ (+++) Configure I2C pins as alternate function open-drain
+ (##) NVIC configuration if you need to use interrupt process
+ (+++) Configure the I2Cx interrupt priority
+ (+++) Enable the NVIC I2C IRQ Channel
+ (##) DMA Configuration if you need to use DMA process
+ (+++) Declare a DMA_HandleTypeDef handle structure for
+ the transmit or receive channel
+ (+++) Enable the DMAx interface clock using
+ (+++) Configure the DMA handle parameters
+ (+++) Configure the DMA Tx or Rx channel
+ (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle
+ (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on
+ the DMA Tx or Rx channel
+
+ (#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addressing mode,
+ Own Address2, Own Address2 Mask, General call and Nostretch mode in the hi2c Init structure.
+
+ (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware
+ (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit(&hi2c) API.
+
+ (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady()
+
+ (#) For I2C IO and IO MEM operations, three operation modes are available within this driver :
+
+ *** Polling mode IO operation ***
+ =================================
+ [..]
+ (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit()
+ (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive()
+ (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit()
+ (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive()
+
+ *** Polling mode IO MEM operation ***
+ =====================================
+ [..]
+ (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write()
+ (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read()
+
+
+ *** Interrupt mode IO operation ***
+ ===================================
+ [..]
+ (+) Transmit in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Transmit_IT()
+ (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and users can
+ add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
+ (+) Receive in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Receive_IT()
+ (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can
+ add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
+ (+) Transmit in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Transmit_IT()
+ (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and users can
+ add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
+ (+) Receive in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Receive_IT()
+ (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can
+ add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
+ (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
+ add their own code by customization of function pointer HAL_I2C_ErrorCallback()
+ (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
+ (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can
+ add their own code by customization of function pointer HAL_I2C_AbortCpltCallback()
+ (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
+ This action will inform Master to generate a Stop condition to discard the communication.
+
+
+ *** Interrupt mode or DMA mode IO sequential operation ***
+ ==========================================================
+ [..]
+ (@) These interfaces allow to manage a sequential transfer with a repeated start condition
+ when a direction change during transfer
+ [..]
+ (+) A specific option field manage the different steps of a sequential transfer
+ (+) Option field values are defined through I2C_XFEROPTIONS and are listed below:
+ (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functional is same as associated interfaces in
+ no sequential mode
+ (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address
+ and data to transfer without a final stop condition
+ (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with
+ start condition, address and data to transfer without a final stop condition,
+ an then permit a call the same master sequential interface several times
+ (like HAL_I2C_Master_Seq_Transmit_IT() then HAL_I2C_Master_Seq_Transmit_IT()
+ or HAL_I2C_Master_Seq_Transmit_DMA() then HAL_I2C_Master_Seq_Transmit_DMA())
+ (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address
+ and with new data to transfer if the direction change or manage only the new data to
+ transfer
+ if no direction change and without a final stop condition in both cases
+ (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address
+ and with new data to transfer if the direction change or manage only the new data to
+ transfer
+ if no direction change and with a final stop condition in both cases
+ (++) I2C_LAST_FRAME_NO_STOP: Sequential usage (Master only), this option allow to manage a restart condition
+ after several call of the same master sequential interface several times
+ (link with option I2C_FIRST_AND_NEXT_FRAME).
+ Usage can, transfer several bytes one by one using
+ HAL_I2C_Master_Seq_Transmit_IT
+ or HAL_I2C_Master_Seq_Receive_IT
+ or HAL_I2C_Master_Seq_Transmit_DMA
+ or HAL_I2C_Master_Seq_Receive_DMA
+ with option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME.
+ Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or
+ Receive sequence permit to call the opposite interface Receive or Transmit
+ without stopping the communication and so generate a restart condition.
+ (++) I2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart condition after
+ each call of the same master sequential
+ interface.
+ Usage can, transfer several bytes one by one with a restart with slave address between
+ each bytes using
+ HAL_I2C_Master_Seq_Transmit_IT
+ or HAL_I2C_Master_Seq_Receive_IT
+ or HAL_I2C_Master_Seq_Transmit_DMA
+ or HAL_I2C_Master_Seq_Receive_DMA
+ with option I2C_FIRST_FRAME then I2C_OTHER_FRAME.
+ Then usage of this option I2C_OTHER_AND_LAST_FRAME at the last frame to help automatic
+ generation of STOP condition.
+
+ (+) Different sequential I2C interfaces are listed below:
+ (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using
+ HAL_I2C_Master_Seq_Transmit_IT() or using HAL_I2C_Master_Seq_Transmit_DMA()
+ (+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and
+ users can add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
+ (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using
+ HAL_I2C_Master_Seq_Receive_IT() or using HAL_I2C_Master_Seq_Receive_DMA()
+ (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can
+ add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
+ (++) Abort a master IT or DMA I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
+ (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can
+ add their own code by customization of function pointer HAL_I2C_AbortCpltCallback()
+ (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT()
+ HAL_I2C_DisableListen_IT()
+ (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and users can
+ add their own code to check the Address Match Code and the transmission direction request by master
+ (Write/Read).
+ (+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and users can
+ add their own code by customization of function pointer HAL_I2C_ListenCpltCallback()
+ (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using
+ HAL_I2C_Slave_Seq_Transmit_IT() or using HAL_I2C_Slave_Seq_Transmit_DMA()
+ (+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and
+ users can add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
+ (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using
+ HAL_I2C_Slave_Seq_Receive_IT() or using HAL_I2C_Slave_Seq_Receive_DMA()
+ (+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can
+ add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
+ (++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
+ add their own code by customization of function pointer HAL_I2C_ErrorCallback()
+ (++) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
+ This action will inform Master to generate a Stop condition to discard the communication.
+
+ *** Interrupt mode IO MEM operation ***
+ =======================================
+ [..]
+ (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using
+ HAL_I2C_Mem_Write_IT()
+ (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and users can
+ add their own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
+ (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using
+ HAL_I2C_Mem_Read_IT()
+ (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and users can
+ add their own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
+ (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
+ add their own code by customization of function pointer HAL_I2C_ErrorCallback()
+
+ *** DMA mode IO operation ***
+ ==============================
+ [..]
+ (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using
+ HAL_I2C_Master_Transmit_DMA()
+ (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and users can
+ add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
+ (+) Receive in master mode an amount of data in non-blocking mode (DMA) using
+ HAL_I2C_Master_Receive_DMA()
+ (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can
+ add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
+ (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using
+ HAL_I2C_Slave_Transmit_DMA()
+ (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and users can
+ add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
+ (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using
+ HAL_I2C_Slave_Receive_DMA()
+ (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can
+ add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
+ (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
+ add their own code by customization of function pointer HAL_I2C_ErrorCallback()
+ (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
+ (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can
+ add their own code by customization of function pointer HAL_I2C_AbortCpltCallback()
+ (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
+ This action will inform Master to generate a Stop condition to discard the communication.
+
+ *** DMA mode IO MEM operation ***
+ =================================
+ [..]
+ (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using
+ HAL_I2C_Mem_Write_DMA()
+ (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and users can
+ add their own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
+ (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using
+ HAL_I2C_Mem_Read_DMA()
+ (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and users can
+ add their own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
+ (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
+ add their own code by customization of function pointer HAL_I2C_ErrorCallback()
+
+
+ *** I2C HAL driver macros list ***
+ ==================================
+ [..]
+ Below the list of most used macros in I2C HAL driver.
+
+ (+) __HAL_I2C_ENABLE: Enable the I2C peripheral
+ (+) __HAL_I2C_DISABLE: Disable the I2C peripheral
+ (+) __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode
+ (+) __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not
+ (+) __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag
+ (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt
+ (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt
+
+ *** Callback registration ***
+ =============================================
+ [..]
+ The compilation flag USE_HAL_I2C_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+ Use Functions HAL_I2C_RegisterCallback() or HAL_I2C_RegisterAddrCallback()
+ to register an interrupt callback.
+ [..]
+ Function HAL_I2C_RegisterCallback() allows to register following callbacks:
+ (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
+ (+) MasterRxCpltCallback : callback for Master reception end of transfer.
+ (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer.
+ (+) SlaveRxCpltCallback : callback for Slave reception end of transfer.
+ (+) ListenCpltCallback : callback for end of listen mode.
+ (+) MemTxCpltCallback : callback for Memory transmission end of transfer.
+ (+) MemRxCpltCallback : callback for Memory reception end of transfer.
+ (+) ErrorCallback : callback for error detection.
+ (+) AbortCpltCallback : callback for abort completion process.
+ (+) MspInitCallback : callback for Msp Init.
+ (+) MspDeInitCallback : callback for Msp DeInit.
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+ [..]
+ For specific callback AddrCallback use dedicated register callbacks : HAL_I2C_RegisterAddrCallback().
+ [..]
+ Use function HAL_I2C_UnRegisterCallback to reset a callback to the default
+ weak function.
+ HAL_I2C_UnRegisterCallback takes as parameters the HAL peripheral handle,
+ and the Callback ID.
+ This function allows to reset following callbacks:
+ (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
+ (+) MasterRxCpltCallback : callback for Master reception end of transfer.
+ (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer.
+ (+) SlaveRxCpltCallback : callback for Slave reception end of transfer.
+ (+) ListenCpltCallback : callback for end of listen mode.
+ (+) MemTxCpltCallback : callback for Memory transmission end of transfer.
+ (+) MemRxCpltCallback : callback for Memory reception end of transfer.
+ (+) ErrorCallback : callback for error detection.
+ (+) AbortCpltCallback : callback for abort completion process.
+ (+) MspInitCallback : callback for Msp Init.
+ (+) MspDeInitCallback : callback for Msp DeInit.
+ [..]
+ For callback AddrCallback use dedicated register callbacks : HAL_I2C_UnRegisterAddrCallback().
+ [..]
+ By default, after the HAL_I2C_Init() and when the state is HAL_I2C_STATE_RESET
+ all callbacks are set to the corresponding weak functions:
+ examples HAL_I2C_MasterTxCpltCallback(), HAL_I2C_MasterRxCpltCallback().
+ Exception done for MspInit and MspDeInit functions that are
+ reset to the legacy weak functions in the HAL_I2C_Init()/ HAL_I2C_DeInit() only when
+ these callbacks are null (not registered beforehand).
+ If MspInit or MspDeInit are not null, the HAL_I2C_Init()/ HAL_I2C_DeInit()
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
+ [..]
+ Callbacks can be registered/unregistered in HAL_I2C_STATE_READY state only.
+ Exception done MspInit/MspDeInit functions that can be registered/unregistered
+ in HAL_I2C_STATE_READY or HAL_I2C_STATE_RESET state,
+ thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+ Then, the user first registers the MspInit/MspDeInit user callbacks
+ using HAL_I2C_RegisterCallback() before calling HAL_I2C_DeInit()
+ or HAL_I2C_Init() function.
+ [..]
+ When the compilation flag USE_HAL_I2C_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registration feature is not available and all callbacks
+ are set to the corresponding weak functions.
+
+ [..]
+ (@) You can refer to the I2C HAL driver header file for more useful macros
+
+ @endverbatim
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32c0xx_hal.h"
+
+/** @addtogroup STM32C0xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup I2C I2C
+ * @brief I2C HAL module driver
+ * @{
+ */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/** @defgroup I2C_Private_Define I2C Private Define
+ * @{
+ */
+#define TIMING_CLEAR_MASK (0xF0FFFFFFU) /*!< I2C TIMING clear register Mask */
+#define I2C_TIMEOUT_ADDR (10000U) /*!< 10 s */
+#define I2C_TIMEOUT_BUSY (25U) /*!< 25 ms */
+#define I2C_TIMEOUT_DIR (25U) /*!< 25 ms */
+#define I2C_TIMEOUT_RXNE (25U) /*!< 25 ms */
+#define I2C_TIMEOUT_STOPF (25U) /*!< 25 ms */
+#define I2C_TIMEOUT_TC (25U) /*!< 25 ms */
+#define I2C_TIMEOUT_TCR (25U) /*!< 25 ms */
+#define I2C_TIMEOUT_TXIS (25U) /*!< 25 ms */
+#define I2C_TIMEOUT_FLAG (25U) /*!< 25 ms */
+
+#define MAX_NBYTE_SIZE 255U
+#define SLAVE_ADDR_SHIFT 7U
+#define SLAVE_ADDR_MSK 0x06U
+
+/* Private define for @ref PreviousState usage */
+#define I2C_STATE_MSK ((uint32_t)((uint32_t)((uint32_t)HAL_I2C_STATE_BUSY_TX | \
+ (uint32_t)HAL_I2C_STATE_BUSY_RX) & \
+ (uint32_t)(~((uint32_t)HAL_I2C_STATE_READY))))
+/*!< Mask State define, keep only RX and TX bits */
+#define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE))
+/*!< Default Value */
+#define I2C_STATE_MASTER_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \
+ (uint32_t)HAL_I2C_MODE_MASTER))
+/*!< Master Busy TX, combinaison of State LSB and Mode enum */
+#define I2C_STATE_MASTER_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \
+ (uint32_t)HAL_I2C_MODE_MASTER))
+/*!< Master Busy RX, combinaison of State LSB and Mode enum */
+#define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \
+ (uint32_t)HAL_I2C_MODE_SLAVE))
+/*!< Slave Busy TX, combinaison of State LSB and Mode enum */
+#define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \
+ (uint32_t)HAL_I2C_MODE_SLAVE))
+/*!< Slave Busy RX, combinaison of State LSB and Mode enum */
+#define I2C_STATE_MEM_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \
+ (uint32_t)HAL_I2C_MODE_MEM))
+/*!< Memory Busy TX, combinaison of State LSB and Mode enum */
+#define I2C_STATE_MEM_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \
+ (uint32_t)HAL_I2C_MODE_MEM))
+/*!< Memory Busy RX, combinaison of State LSB and Mode enum */
+
+
+/* Private define to centralize the enable/disable of Interrupts */
+#define I2C_XFER_TX_IT (uint16_t)(0x0001U) /*!< Bit field can be combinated with
+ @ref I2C_XFER_LISTEN_IT */
+#define I2C_XFER_RX_IT (uint16_t)(0x0002U) /*!< Bit field can be combinated with
+ @ref I2C_XFER_LISTEN_IT */
+#define I2C_XFER_LISTEN_IT (uint16_t)(0x8000U) /*!< Bit field can be combinated with @ref I2C_XFER_TX_IT
+ and @ref I2C_XFER_RX_IT */
+
+#define I2C_XFER_ERROR_IT (uint16_t)(0x0010U) /*!< Bit definition to manage addition of global Error
+ and NACK treatment */
+#define I2C_XFER_CPLT_IT (uint16_t)(0x0020U) /*!< Bit definition to manage only STOP evenement */
+#define I2C_XFER_RELOAD_IT (uint16_t)(0x0040U) /*!< Bit definition to manage only Reload of NBYTE */
+
+/* Private define Sequential Transfer Options default/reset value */
+#define I2C_NO_OPTION_FRAME (0xFFFF0000U)
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Macro to get remaining data to transfer on DMA side */
+#define I2C_GET_DMA_REMAIN_DATA(__HANDLE__) __HAL_DMA_GET_COUNTER(__HANDLE__)
+
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+
+/** @defgroup I2C_Private_Functions I2C Private Functions
+ * @{
+ */
+/* Private functions to handle DMA transfer */
+static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma);
+static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma);
+static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma);
+static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma);
+static void I2C_DMAError(DMA_HandleTypeDef *hdma);
+static void I2C_DMAAbort(DMA_HandleTypeDef *hdma);
+
+/* Private functions to handle IT transfer */
+static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
+static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c);
+static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c);
+static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
+static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
+static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
+static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode);
+
+/* Private functions to handle IT transfer */
+static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
+ uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
+ uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
+ uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
+ uint32_t Tickstart);
+
+/* Private functions for I2C transfer IRQ handler */
+static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
+ uint32_t ITSources);
+static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
+ uint32_t ITSources);
+static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
+ uint32_t ITSources);
+static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
+ uint32_t ITSources);
+
+/* Private functions to handle flags during polling transfer */
+static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status,
+ uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
+ uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
+ uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
+ uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
+ uint32_t Tickstart);
+
+/* Private functions to centralize the enable/disable of Interrupts */
+static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
+static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
+
+/* Private function to treat different error callback */
+static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c);
+
+/* Private function to flush TXDR register */
+static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c);
+
+/* Private function to handle start, restart or stop a transfer */
+static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode,
+ uint32_t Request);
+
+/* Private function to Convert Specific options */
+static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c);
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup I2C_Exported_Functions I2C Exported Functions
+ * @{
+ */
+
+/** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..] This subsection provides a set of functions allowing to initialize and
+ deinitialize the I2Cx peripheral:
+
+ (+) User must Implement HAL_I2C_MspInit() function in which he configures
+ all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
+
+ (+) Call the function HAL_I2C_Init() to configure the selected device with
+ the selected configuration:
+ (++) Clock Timing
+ (++) Own Address 1
+ (++) Addressing mode (Master, Slave)
+ (++) Dual Addressing mode
+ (++) Own Address 2
+ (++) Own Address 2 Mask
+ (++) General call mode
+ (++) Nostretch mode
+
+ (+) Call the function HAL_I2C_DeInit() to restore the default configuration
+ of the selected I2Cx peripheral.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the I2C according to the specified parameters
+ * in the I2C_InitTypeDef and initialize the associated handle.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
+{
+ /* Check the I2C handle allocation */
+ if (hi2c == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
+ assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1));
+ assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode));
+ assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode));
+ assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
+ assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks));
+ assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
+ assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
+
+ if (hi2c->State == HAL_I2C_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hi2c->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ /* Init the I2C Callback settings */
+ hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */
+ hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */
+ hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */
+ hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */
+ hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback */
+ hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback */
+ hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback */
+ hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback */
+ hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
+ hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */
+
+ if (hi2c->MspInitCallback == NULL)
+ {
+ hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */
+ }
+
+ /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
+ hi2c->MspInitCallback(hi2c);
+#else
+ /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
+ HAL_I2C_MspInit(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+ }
+
+ hi2c->State = HAL_I2C_STATE_BUSY;
+
+ /* Disable the selected I2C peripheral */
+ __HAL_I2C_DISABLE(hi2c);
+
+ /*---------------------------- I2Cx TIMINGR Configuration ------------------*/
+ /* Configure I2Cx: Frequency range */
+ hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK;
+
+ /*---------------------------- I2Cx OAR1 Configuration ---------------------*/
+ /* Disable Own Address1 before set the Own Address1 configuration */
+ hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
+
+ /* Configure I2Cx: Own Address1 and ack own address1 mode */
+ if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
+ {
+ hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1);
+ }
+ else /* I2C_ADDRESSINGMODE_10BIT */
+ {
+ hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1);
+ }
+
+ /*---------------------------- I2Cx CR2 Configuration ----------------------*/
+ /* Configure I2Cx: Addressing Master mode */
+ if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
+ {
+ hi2c->Instance->CR2 = (I2C_CR2_ADD10);
+ }
+ /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */
+ hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
+
+ /*---------------------------- I2Cx OAR2 Configuration ---------------------*/
+ /* Disable Own Address2 before set the Own Address2 configuration */
+ hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE;
+
+ /* Configure I2Cx: Dual mode and Own Address2 */
+ hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \
+ (hi2c->Init.OwnAddress2Masks << 8));
+
+ /*---------------------------- I2Cx CR1 Configuration ----------------------*/
+ /* Configure I2Cx: Generalcall and NoStretch mode */
+ hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode);
+
+ /* Enable the selected I2C peripheral */
+ __HAL_I2C_ENABLE(hi2c);
+
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->PreviousState = I2C_STATE_NONE;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitialize the I2C peripheral.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
+{
+ /* Check the I2C handle allocation */
+ if (hi2c == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
+
+ hi2c->State = HAL_I2C_STATE_BUSY;
+
+ /* Disable the I2C Peripheral Clock */
+ __HAL_I2C_DISABLE(hi2c);
+
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ if (hi2c->MspDeInitCallback == NULL)
+ {
+ hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */
+ }
+
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+ hi2c->MspDeInitCallback(hi2c);
+#else
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+ HAL_I2C_MspDeInit(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ hi2c->State = HAL_I2C_STATE_RESET;
+ hi2c->PreviousState = I2C_STATE_NONE;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initialize the I2C MSP.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval None
+ */
+__weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2c);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_I2C_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitialize the I2C MSP.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval None
+ */
+__weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2c);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_I2C_MspDeInit could be implemented in the user file
+ */
+}
+
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a User I2C Callback
+ * To be used instead of the weak predefined callback
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
+ * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
+ * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
+ * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
+ * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
+ * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID
+ * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID
+ * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID
+ * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID
+ * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID
+ * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @param pCallback pointer to the Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID,
+ pI2C_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+ /* Process locked */
+ __HAL_LOCK(hi2c);
+
+ if (HAL_I2C_STATE_READY == hi2c->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_I2C_MASTER_TX_COMPLETE_CB_ID :
+ hi2c->MasterTxCpltCallback = pCallback;
+ break;
+
+ case HAL_I2C_MASTER_RX_COMPLETE_CB_ID :
+ hi2c->MasterRxCpltCallback = pCallback;
+ break;
+
+ case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID :
+ hi2c->SlaveTxCpltCallback = pCallback;
+ break;
+
+ case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID :
+ hi2c->SlaveRxCpltCallback = pCallback;
+ break;
+
+ case HAL_I2C_LISTEN_COMPLETE_CB_ID :
+ hi2c->ListenCpltCallback = pCallback;
+ break;
+
+ case HAL_I2C_MEM_TX_COMPLETE_CB_ID :
+ hi2c->MemTxCpltCallback = pCallback;
+ break;
+
+ case HAL_I2C_MEM_RX_COMPLETE_CB_ID :
+ hi2c->MemRxCpltCallback = pCallback;
+ break;
+
+ case HAL_I2C_ERROR_CB_ID :
+ hi2c->ErrorCallback = pCallback;
+ break;
+
+ case HAL_I2C_ABORT_CB_ID :
+ hi2c->AbortCpltCallback = pCallback;
+ break;
+
+ case HAL_I2C_MSPINIT_CB_ID :
+ hi2c->MspInitCallback = pCallback;
+ break;
+
+ case HAL_I2C_MSPDEINIT_CB_ID :
+ hi2c->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_I2C_STATE_RESET == hi2c->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_I2C_MSPINIT_CB_ID :
+ hi2c->MspInitCallback = pCallback;
+ break;
+
+ case HAL_I2C_MSPDEINIT_CB_ID :
+ hi2c->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hi2c);
+ return status;
+}
+
+/**
+ * @brief Unregister an I2C Callback
+ * I2C callback is redirected to the weak predefined callback
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param CallbackID ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
+ * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
+ * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
+ * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
+ * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
+ * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID
+ * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID
+ * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID
+ * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID
+ * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID
+ * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hi2c);
+
+ if (HAL_I2C_STATE_READY == hi2c->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_I2C_MASTER_TX_COMPLETE_CB_ID :
+ hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */
+ break;
+
+ case HAL_I2C_MASTER_RX_COMPLETE_CB_ID :
+ hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */
+ break;
+
+ case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID :
+ hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */
+ break;
+
+ case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID :
+ hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */
+ break;
+
+ case HAL_I2C_LISTEN_COMPLETE_CB_ID :
+ hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback */
+ break;
+
+ case HAL_I2C_MEM_TX_COMPLETE_CB_ID :
+ hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback */
+ break;
+
+ case HAL_I2C_MEM_RX_COMPLETE_CB_ID :
+ hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback */
+ break;
+
+ case HAL_I2C_ERROR_CB_ID :
+ hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback */
+ break;
+
+ case HAL_I2C_ABORT_CB_ID :
+ hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
+ break;
+
+ case HAL_I2C_MSPINIT_CB_ID :
+ hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */
+ break;
+
+ case HAL_I2C_MSPDEINIT_CB_ID :
+ hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */
+ break;
+
+ default :
+ /* Update the error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_I2C_STATE_RESET == hi2c->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_I2C_MSPINIT_CB_ID :
+ hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */
+ break;
+
+ case HAL_I2C_MSPDEINIT_CB_ID :
+ hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */
+ break;
+
+ default :
+ /* Update the error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hi2c);
+ return status;
+}
+
+/**
+ * @brief Register the Slave Address Match I2C Callback
+ * To be used instead of the weak HAL_I2C_AddrCallback() predefined callback
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param pCallback pointer to the Address Match Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+ /* Process locked */
+ __HAL_LOCK(hi2c);
+
+ if (HAL_I2C_STATE_READY == hi2c->State)
+ {
+ hi2c->AddrCallback = pCallback;
+ }
+ else
+ {
+ /* Update the error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hi2c);
+ return status;
+}
+
+/**
+ * @brief UnRegister the Slave Address Match I2C Callback
+ * Info Ready I2C Callback is redirected to the weak HAL_I2C_AddrCallback() predefined callback
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hi2c);
+
+ if (HAL_I2C_STATE_READY == hi2c->State)
+ {
+ hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */
+ }
+ else
+ {
+ /* Update the error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hi2c);
+ return status;
+}
+
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+/** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions
+ * @brief Data transfers functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the I2C data
+ transfers.
+
+ (#) There are two modes of transfer:
+ (++) Blocking mode : The communication is performed in the polling mode.
+ The status of all data processing is returned by the same function
+ after finishing transfer.
+ (++) No-Blocking mode : The communication is performed using Interrupts
+ or DMA. These functions return the status of the transfer startup.
+ The end of the data processing will be indicated through the
+ dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when
+ using DMA mode.
+
+ (#) Blocking mode functions are :
+ (++) HAL_I2C_Master_Transmit()
+ (++) HAL_I2C_Master_Receive()
+ (++) HAL_I2C_Slave_Transmit()
+ (++) HAL_I2C_Slave_Receive()
+ (++) HAL_I2C_Mem_Write()
+ (++) HAL_I2C_Mem_Read()
+ (++) HAL_I2C_IsDeviceReady()
+
+ (#) No-Blocking mode functions with Interrupt are :
+ (++) HAL_I2C_Master_Transmit_IT()
+ (++) HAL_I2C_Master_Receive_IT()
+ (++) HAL_I2C_Slave_Transmit_IT()
+ (++) HAL_I2C_Slave_Receive_IT()
+ (++) HAL_I2C_Mem_Write_IT()
+ (++) HAL_I2C_Mem_Read_IT()
+ (++) HAL_I2C_Master_Seq_Transmit_IT()
+ (++) HAL_I2C_Master_Seq_Receive_IT()
+ (++) HAL_I2C_Slave_Seq_Transmit_IT()
+ (++) HAL_I2C_Slave_Seq_Receive_IT()
+ (++) HAL_I2C_EnableListen_IT()
+ (++) HAL_I2C_DisableListen_IT()
+ (++) HAL_I2C_Master_Abort_IT()
+
+ (#) No-Blocking mode functions with DMA are :
+ (++) HAL_I2C_Master_Transmit_DMA()
+ (++) HAL_I2C_Master_Receive_DMA()
+ (++) HAL_I2C_Slave_Transmit_DMA()
+ (++) HAL_I2C_Slave_Receive_DMA()
+ (++) HAL_I2C_Mem_Write_DMA()
+ (++) HAL_I2C_Mem_Read_DMA()
+ (++) HAL_I2C_Master_Seq_Transmit_DMA()
+ (++) HAL_I2C_Master_Seq_Receive_DMA()
+ (++) HAL_I2C_Slave_Seq_Transmit_DMA()
+ (++) HAL_I2C_Slave_Seq_Receive_DMA()
+
+ (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
+ (++) HAL_I2C_MasterTxCpltCallback()
+ (++) HAL_I2C_MasterRxCpltCallback()
+ (++) HAL_I2C_SlaveTxCpltCallback()
+ (++) HAL_I2C_SlaveRxCpltCallback()
+ (++) HAL_I2C_MemTxCpltCallback()
+ (++) HAL_I2C_MemRxCpltCallback()
+ (++) HAL_I2C_AddrCallback()
+ (++) HAL_I2C_ListenCpltCallback()
+ (++) HAL_I2C_ErrorCallback()
+ (++) HAL_I2C_AbortCpltCallback()
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Transmits in master mode an amount of data in blocking mode.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress Target device address: The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+ uint16_t Size, uint32_t Timeout)
+{
+ uint32_t tickstart;
+
+ if (hi2c->State == HAL_I2C_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ hi2c->State = HAL_I2C_STATE_BUSY_TX;
+ hi2c->Mode = HAL_I2C_MODE_MASTER;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferISR = NULL;
+
+ /* Send Slave Address */
+ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
+ I2C_GENERATE_START_WRITE);
+ }
+ else
+ {
+ hi2c->XferSize = hi2c->XferCount;
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+ I2C_GENERATE_START_WRITE);
+ }
+
+ while (hi2c->XferCount > 0U)
+ {
+ /* Wait until TXIS flag is set */
+ if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ /* Write data to TXDR */
+ hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
+
+ hi2c->XferCount--;
+ hi2c->XferSize--;
+
+ if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
+ {
+ /* Wait until TCR flag is set */
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
+ I2C_NO_STARTSTOP);
+ }
+ else
+ {
+ hi2c->XferSize = hi2c->XferCount;
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+ I2C_NO_STARTSTOP);
+ }
+ }
+ }
+
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+ /* Wait until STOPF flag is set */
+ if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Clear STOP Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+ /* Clear Configuration Register 2 */
+ I2C_RESET_CR2(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receives in master mode an amount of data in blocking mode.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress Target device address: The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+ uint16_t Size, uint32_t Timeout)
+{
+ uint32_t tickstart;
+
+ if (hi2c->State == HAL_I2C_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ hi2c->State = HAL_I2C_STATE_BUSY_RX;
+ hi2c->Mode = HAL_I2C_MODE_MASTER;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferISR = NULL;
+
+ /* Send Slave Address */
+ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
+ I2C_GENERATE_START_READ);
+ }
+ else
+ {
+ hi2c->XferSize = hi2c->XferCount;
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+ I2C_GENERATE_START_READ);
+ }
+
+ while (hi2c->XferCount > 0U)
+ {
+ /* Wait until RXNE flag is set */
+ if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Read data from RXDR */
+ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
+
+ hi2c->XferSize--;
+ hi2c->XferCount--;
+
+ if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
+ {
+ /* Wait until TCR flag is set */
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
+ I2C_NO_STARTSTOP);
+ }
+ else
+ {
+ hi2c->XferSize = hi2c->XferCount;
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+ I2C_NO_STARTSTOP);
+ }
+ }
+ }
+
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+ /* Wait until STOPF flag is set */
+ if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Clear STOP Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+ /* Clear Configuration Register 2 */
+ I2C_RESET_CR2(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Transmits in slave mode an amount of data in blocking mode.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
+ uint32_t Timeout)
+{
+ uint32_t tickstart;
+
+ if (hi2c->State == HAL_I2C_STATE_READY)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+ return HAL_ERROR;
+ }
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+
+ hi2c->State = HAL_I2C_STATE_BUSY_TX;
+ hi2c->Mode = HAL_I2C_MODE_SLAVE;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferISR = NULL;
+
+ /* Enable Address Acknowledge */
+ hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+ /* Wait until ADDR flag is set */
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;
+ return HAL_ERROR;
+ }
+
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+
+ /* If 10bit addressing mode is selected */
+ if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
+ {
+ /* Wait until ADDR flag is set */
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;
+ return HAL_ERROR;
+ }
+
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+ }
+
+ /* Wait until DIR flag is set Transmitter mode */
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, Timeout, tickstart) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;
+ return HAL_ERROR;
+ }
+
+ while (hi2c->XferCount > 0U)
+ {
+ /* Wait until TXIS flag is set */
+ if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;
+ return HAL_ERROR;
+ }
+
+ /* Write data to TXDR */
+ hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
+
+ hi2c->XferCount--;
+ }
+
+ /* Wait until AF flag is set */
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;
+ return HAL_ERROR;
+ }
+
+ /* Flush TX register */
+ I2C_Flush_TXDR(hi2c);
+
+ /* Clear AF flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+ /* Wait until STOP flag is set */
+ if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+ return HAL_ERROR;
+ }
+
+ /* Clear STOP flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+ /* Wait until BUSY flag is reset */
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;
+ return HAL_ERROR;
+ }
+
+ /* Disable Address Acknowledge */
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive in slave mode an amount of data in blocking mode
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
+ uint32_t Timeout)
+{
+ uint32_t tickstart;
+
+ if (hi2c->State == HAL_I2C_STATE_READY)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+ return HAL_ERROR;
+ }
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+
+ hi2c->State = HAL_I2C_STATE_BUSY_RX;
+ hi2c->Mode = HAL_I2C_MODE_SLAVE;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferSize = hi2c->XferCount;
+ hi2c->XferISR = NULL;
+
+ /* Enable Address Acknowledge */
+ hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+ /* Wait until ADDR flag is set */
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;
+ return HAL_ERROR;
+ }
+
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+
+ /* Wait until DIR flag is reset Receiver mode */
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, Timeout, tickstart) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;
+ return HAL_ERROR;
+ }
+
+ while (hi2c->XferCount > 0U)
+ {
+ /* Wait until RXNE flag is set */
+ if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+ /* Store Last receive data if any */
+ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
+ {
+ /* Read data from RXDR */
+ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
+
+ hi2c->XferCount--;
+ hi2c->XferSize--;
+ }
+
+ return HAL_ERROR;
+ }
+
+ /* Read data from RXDR */
+ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
+
+ hi2c->XferCount--;
+ hi2c->XferSize--;
+ }
+
+ /* Wait until STOP flag is set */
+ if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;
+ return HAL_ERROR;
+ }
+
+ /* Clear STOP flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+ /* Wait until BUSY flag is reset */
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;
+ return HAL_ERROR;
+ }
+
+ /* Disable Address Acknowledge */
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress Target device address: The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+ uint16_t Size)
+{
+ uint32_t xfermode;
+
+ if (hi2c->State == HAL_I2C_STATE_READY)
+ {
+ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_BUSY_TX;
+ hi2c->Mode = HAL_I2C_MODE_MASTER;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ hi2c->XferISR = I2C_Master_ISR_IT;
+
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ xfermode = I2C_RELOAD_MODE;
+ }
+ else
+ {
+ hi2c->XferSize = hi2c->XferCount;
+ xfermode = I2C_AUTOEND_MODE;
+ }
+
+ /* Send Slave Address */
+ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+
+ /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+ /* possible to enable all of these */
+ /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
+ I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive in master mode an amount of data in non-blocking mode with Interrupt
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress Target device address: The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+ uint16_t Size)
+{
+ uint32_t xfermode;
+
+ if (hi2c->State == HAL_I2C_STATE_READY)
+ {
+ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_BUSY_RX;
+ hi2c->Mode = HAL_I2C_MODE_MASTER;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ hi2c->XferISR = I2C_Master_ISR_IT;
+
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ xfermode = I2C_RELOAD_MODE;
+ }
+ else
+ {
+ hi2c->XferSize = hi2c->XferCount;
+ xfermode = I2C_AUTOEND_MODE;
+ }
+
+ /* Send Slave Address */
+ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+
+ /* Enable ERR, TC, STOP, NACK, RXI interrupt */
+ /* possible to enable all of these */
+ /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
+ I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Transmit in slave mode an amount of data in non-blocking mode with Interrupt
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
+{
+ if (hi2c->State == HAL_I2C_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_BUSY_TX;
+ hi2c->Mode = HAL_I2C_MODE_SLAVE;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Enable Address Acknowledge */
+ hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferSize = hi2c->XferCount;
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ hi2c->XferISR = I2C_Slave_ISR_IT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+
+ /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+ /* possible to enable all of these */
+ /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
+ I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
+{
+ if (hi2c->State == HAL_I2C_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_BUSY_RX;
+ hi2c->Mode = HAL_I2C_MODE_SLAVE;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Enable Address Acknowledge */
+ hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferSize = hi2c->XferCount;
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ hi2c->XferISR = I2C_Slave_ISR_IT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+
+ /* Enable ERR, TC, STOP, NACK, RXI interrupt */
+ /* possible to enable all of these */
+ /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
+ I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Transmit in master mode an amount of data in non-blocking mode with DMA
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress Target device address: The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+ uint16_t Size)
+{
+ uint32_t xfermode;
+ HAL_StatusTypeDef dmaxferstatus;
+
+ if (hi2c->State == HAL_I2C_STATE_READY)
+ {
+ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_BUSY_TX;
+ hi2c->Mode = HAL_I2C_MODE_MASTER;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ hi2c->XferISR = I2C_Master_ISR_DMA;
+
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ xfermode = I2C_RELOAD_MODE;
+ }
+ else
+ {
+ hi2c->XferSize = hi2c->XferCount;
+ xfermode = I2C_AUTOEND_MODE;
+ }
+
+ if (hi2c->XferSize > 0U)
+ {
+ if (hi2c->hdmatx != NULL)
+ {
+ /* Set the I2C DMA transfer complete callback */
+ hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
+
+ /* Set the DMA error callback */
+ hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
+
+ /* Set the unused DMA callbacks to NULL */
+ hi2c->hdmatx->XferHalfCpltCallback = NULL;
+ hi2c->hdmatx->XferAbortCallback = NULL;
+
+ /* Enable the DMA channel */
+ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
+ hi2c->XferSize);
+ }
+ else
+ {
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
+
+ if (dmaxferstatus == HAL_OK)
+ {
+ /* Send Slave Address */
+ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE);
+
+ /* Update XferCount value */
+ hi2c->XferCount -= hi2c->XferSize;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+ /* Enable ERR and NACK interrupts */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
+
+ /* Enable DMA Request */
+ hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+ }
+ else
+ {
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ /* Update Transfer ISR function pointer */
+ hi2c->XferISR = I2C_Master_ISR_IT;
+
+ /* Send Slave Address */
+ /* Set NBYTES to write and generate START condition */
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+ I2C_GENERATE_START_WRITE);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+ /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+ /* possible to enable all of these */
+ /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
+ I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
+ }
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive in master mode an amount of data in non-blocking mode with DMA
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress Target device address: The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+ uint16_t Size)
+{
+ uint32_t xfermode;
+ HAL_StatusTypeDef dmaxferstatus;
+
+ if (hi2c->State == HAL_I2C_STATE_READY)
+ {
+ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_BUSY_RX;
+ hi2c->Mode = HAL_I2C_MODE_MASTER;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ hi2c->XferISR = I2C_Master_ISR_DMA;
+
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ xfermode = I2C_RELOAD_MODE;
+ }
+ else
+ {
+ hi2c->XferSize = hi2c->XferCount;
+ xfermode = I2C_AUTOEND_MODE;
+ }
+
+ if (hi2c->XferSize > 0U)
+ {
+ if (hi2c->hdmarx != NULL)
+ {
+ /* Set the I2C DMA transfer complete callback */
+ hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
+
+ /* Set the DMA error callback */
+ hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
+
+ /* Set the unused DMA callbacks to NULL */
+ hi2c->hdmarx->XferHalfCpltCallback = NULL;
+ hi2c->hdmarx->XferAbortCallback = NULL;
+
+ /* Enable the DMA channel */
+ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
+ hi2c->XferSize);
+ }
+ else
+ {
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
+
+ if (dmaxferstatus == HAL_OK)
+ {
+ /* Send Slave Address */
+ /* Set NBYTES to read and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
+
+ /* Update XferCount value */
+ hi2c->XferCount -= hi2c->XferSize;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+ /* Enable ERR and NACK interrupts */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
+
+ /* Enable DMA Request */
+ hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+ }
+ else
+ {
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ /* Update Transfer ISR function pointer */
+ hi2c->XferISR = I2C_Master_ISR_IT;
+
+ /* Send Slave Address */
+ /* Set NBYTES to read and generate START condition */
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+ I2C_GENERATE_START_READ);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+ /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+ /* possible to enable all of these */
+ /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
+ I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
+ }
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Transmit in slave mode an amount of data in non-blocking mode with DMA
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
+{
+ HAL_StatusTypeDef dmaxferstatus;
+
+ if (hi2c->State == HAL_I2C_STATE_READY)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+ return HAL_ERROR;
+ }
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_BUSY_TX;
+ hi2c->Mode = HAL_I2C_MODE_SLAVE;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferSize = hi2c->XferCount;
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ hi2c->XferISR = I2C_Slave_ISR_DMA;
+
+ if (hi2c->hdmatx != NULL)
+ {
+ /* Set the I2C DMA transfer complete callback */
+ hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;
+
+ /* Set the DMA error callback */
+ hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
+
+ /* Set the unused DMA callbacks to NULL */
+ hi2c->hdmatx->XferHalfCpltCallback = NULL;
+ hi2c->hdmatx->XferAbortCallback = NULL;
+
+ /* Enable the DMA channel */
+ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
+ hi2c->XferSize);
+ }
+ else
+ {
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_LISTEN;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
+
+ if (dmaxferstatus == HAL_OK)
+ {
+ /* Enable Address Acknowledge */
+ hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+ /* Enable ERR, STOP, NACK, ADDR interrupts */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
+
+ /* Enable DMA Request */
+ hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+ }
+ else
+ {
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_LISTEN;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive in slave mode an amount of data in non-blocking mode with DMA
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
+{
+ HAL_StatusTypeDef dmaxferstatus;
+
+ if (hi2c->State == HAL_I2C_STATE_READY)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+ return HAL_ERROR;
+ }
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_BUSY_RX;
+ hi2c->Mode = HAL_I2C_MODE_SLAVE;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferSize = hi2c->XferCount;
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ hi2c->XferISR = I2C_Slave_ISR_DMA;
+
+ if (hi2c->hdmarx != NULL)
+ {
+ /* Set the I2C DMA transfer complete callback */
+ hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt;
+
+ /* Set the DMA error callback */
+ hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
+
+ /* Set the unused DMA callbacks to NULL */
+ hi2c->hdmarx->XferHalfCpltCallback = NULL;
+ hi2c->hdmarx->XferAbortCallback = NULL;
+
+ /* Enable the DMA channel */
+ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
+ hi2c->XferSize);
+ }
+ else
+ {
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_LISTEN;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
+
+ if (dmaxferstatus == HAL_OK)
+ {
+ /* Enable Address Acknowledge */
+ hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+ /* Enable ERR, STOP, NACK, ADDR interrupts */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
+
+ /* Enable DMA Request */
+ hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+ }
+ else
+ {
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_LISTEN;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+/**
+ * @brief Write an amount of data in blocking mode to a specific memory address
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress Target device address: The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @param MemAddress Internal memory address
+ * @param MemAddSize Size of internal memory address
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
+ uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ uint32_t tickstart;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+
+ if (hi2c->State == HAL_I2C_STATE_READY)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ hi2c->State = HAL_I2C_STATE_BUSY_TX;
+ hi2c->Mode = HAL_I2C_MODE_MEM;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferISR = NULL;
+
+ /* Send Slave Address and Memory Address */
+ if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_ERROR;
+ }
+
+ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+ }
+ else
+ {
+ hi2c->XferSize = hi2c->XferCount;
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+ }
+
+ do
+ {
+ /* Wait until TXIS flag is set */
+ if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Write data to TXDR */
+ hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
+
+ hi2c->XferCount--;
+ hi2c->XferSize--;
+
+ if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
+ {
+ /* Wait until TCR flag is set */
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
+ I2C_NO_STARTSTOP);
+ }
+ else
+ {
+ hi2c->XferSize = hi2c->XferCount;
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+ I2C_NO_STARTSTOP);
+ }
+ }
+
+ } while (hi2c->XferCount > 0U);
+
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+ /* Wait until STOPF flag is reset */
+ if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Clear STOP Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+ /* Clear Configuration Register 2 */
+ I2C_RESET_CR2(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Read an amount of data in blocking mode from a specific memory address
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress Target device address: The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @param MemAddress Internal memory address
+ * @param MemAddSize Size of internal memory address
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
+ uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ uint32_t tickstart;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+
+ if (hi2c->State == HAL_I2C_STATE_READY)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ hi2c->State = HAL_I2C_STATE_BUSY_RX;
+ hi2c->Mode = HAL_I2C_MODE_MEM;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferISR = NULL;
+
+ /* Send Slave Address and Memory Address */
+ if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_ERROR;
+ }
+
+ /* Send Slave Address */
+ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
+ I2C_GENERATE_START_READ);
+ }
+ else
+ {
+ hi2c->XferSize = hi2c->XferCount;
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+ I2C_GENERATE_START_READ);
+ }
+
+ do
+ {
+ /* Wait until RXNE flag is set */
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Read data from RXDR */
+ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
+
+ hi2c->XferSize--;
+ hi2c->XferCount--;
+
+ if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
+ {
+ /* Wait until TCR flag is set */
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t) hi2c->XferSize, I2C_RELOAD_MODE,
+ I2C_NO_STARTSTOP);
+ }
+ else
+ {
+ hi2c->XferSize = hi2c->XferCount;
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+ I2C_NO_STARTSTOP);
+ }
+ }
+ } while (hi2c->XferCount > 0U);
+
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+ /* Wait until STOPF flag is reset */
+ if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Clear STOP Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+ /* Clear Configuration Register 2 */
+ I2C_RESET_CR2(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+/**
+ * @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory address
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress Target device address: The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @param MemAddress Internal memory address
+ * @param MemAddSize Size of internal memory address
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
+ uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
+{
+ uint32_t tickstart;
+ uint32_t xfermode;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+
+ if (hi2c->State == HAL_I2C_STATE_READY)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+ return HAL_ERROR;
+ }
+
+ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+
+ hi2c->State = HAL_I2C_STATE_BUSY_TX;
+ hi2c->Mode = HAL_I2C_MODE_MEM;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ hi2c->XferISR = I2C_Master_ISR_IT;
+
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ xfermode = I2C_RELOAD_MODE;
+ }
+ else
+ {
+ hi2c->XferSize = hi2c->XferCount;
+ xfermode = I2C_AUTOEND_MODE;
+ }
+
+ /* Send Slave Address and Memory Address */
+ if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart)
+ != HAL_OK)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_ERROR;
+ }
+
+ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+
+ /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+ /* possible to enable all of these */
+ /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
+ I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory address
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress Target device address: The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @param MemAddress Internal memory address
+ * @param MemAddSize Size of internal memory address
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
+ uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
+{
+ uint32_t tickstart;
+ uint32_t xfermode;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+
+ if (hi2c->State == HAL_I2C_STATE_READY)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+ return HAL_ERROR;
+ }
+
+ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+
+ hi2c->State = HAL_I2C_STATE_BUSY_RX;
+ hi2c->Mode = HAL_I2C_MODE_MEM;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ hi2c->XferISR = I2C_Master_ISR_IT;
+
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ xfermode = I2C_RELOAD_MODE;
+ }
+ else
+ {
+ hi2c->XferSize = hi2c->XferCount;
+ xfermode = I2C_AUTOEND_MODE;
+ }
+
+ /* Send Slave Address and Memory Address */
+ if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_ERROR;
+ }
+
+ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+
+ /* Enable ERR, TC, STOP, NACK, RXI interrupt */
+ /* possible to enable all of these */
+ /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
+ I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+/**
+ * @brief Write an amount of data in non-blocking mode with DMA to a specific memory address
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress Target device address: The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @param MemAddress Internal memory address
+ * @param MemAddSize Size of internal memory address
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
+ uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
+{
+ uint32_t tickstart;
+ uint32_t xfermode;
+ HAL_StatusTypeDef dmaxferstatus;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+
+ if (hi2c->State == HAL_I2C_STATE_READY)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+ return HAL_ERROR;
+ }
+
+ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+
+ hi2c->State = HAL_I2C_STATE_BUSY_TX;
+ hi2c->Mode = HAL_I2C_MODE_MEM;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ hi2c->XferISR = I2C_Master_ISR_DMA;
+
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ xfermode = I2C_RELOAD_MODE;
+ }
+ else
+ {
+ hi2c->XferSize = hi2c->XferCount;
+ xfermode = I2C_AUTOEND_MODE;
+ }
+
+ /* Send Slave Address and Memory Address */
+ if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart)
+ != HAL_OK)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_ERROR;
+ }
+
+
+ if (hi2c->hdmatx != NULL)
+ {
+ /* Set the I2C DMA transfer complete callback */
+ hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
+
+ /* Set the DMA error callback */
+ hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
+
+ /* Set the unused DMA callbacks to NULL */
+ hi2c->hdmatx->XferHalfCpltCallback = NULL;
+ hi2c->hdmatx->XferAbortCallback = NULL;
+
+ /* Enable the DMA channel */
+ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
+ hi2c->XferSize);
+ }
+ else
+ {
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
+
+ if (dmaxferstatus == HAL_OK)
+ {
+ /* Send Slave Address */
+ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
+
+ /* Update XferCount value */
+ hi2c->XferCount -= hi2c->XferSize;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+ /* Enable ERR and NACK interrupts */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
+
+ /* Enable DMA Request */
+ hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+ }
+ else
+ {
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Reads an amount of data in non-blocking mode with DMA from a specific memory address.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress Target device address: The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @param MemAddress Internal memory address
+ * @param MemAddSize Size of internal memory address
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be read
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
+ uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
+{
+ uint32_t tickstart;
+ uint32_t xfermode;
+ HAL_StatusTypeDef dmaxferstatus;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+
+ if (hi2c->State == HAL_I2C_STATE_READY)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+ return HAL_ERROR;
+ }
+
+ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+
+ hi2c->State = HAL_I2C_STATE_BUSY_RX;
+ hi2c->Mode = HAL_I2C_MODE_MEM;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ hi2c->XferISR = I2C_Master_ISR_DMA;
+
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ xfermode = I2C_RELOAD_MODE;
+ }
+ else
+ {
+ hi2c->XferSize = hi2c->XferCount;
+ xfermode = I2C_AUTOEND_MODE;
+ }
+
+ /* Send Slave Address and Memory Address */
+ if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_ERROR;
+ }
+
+ if (hi2c->hdmarx != NULL)
+ {
+ /* Set the I2C DMA transfer complete callback */
+ hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
+
+ /* Set the DMA error callback */
+ hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
+
+ /* Set the unused DMA callbacks to NULL */
+ hi2c->hdmarx->XferHalfCpltCallback = NULL;
+ hi2c->hdmarx->XferAbortCallback = NULL;
+
+ /* Enable the DMA channel */
+ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
+ hi2c->XferSize);
+ }
+ else
+ {
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
+
+ if (dmaxferstatus == HAL_OK)
+ {
+ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
+
+ /* Update XferCount value */
+ hi2c->XferCount -= hi2c->XferSize;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+ /* Enable ERR and NACK interrupts */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
+
+ /* Enable DMA Request */
+ hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+ }
+ else
+ {
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Checks if target device is ready for communication.
+ * @note This function is used with Memory devices
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress Target device address: The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @param Trials Number of trials
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials,
+ uint32_t Timeout)
+{
+ uint32_t tickstart;
+
+ __IO uint32_t I2C_Trials = 0UL;
+
+ FlagStatus tmp1;
+ FlagStatus tmp2;
+
+ if (hi2c->State == HAL_I2C_STATE_READY)
+ {
+ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_BUSY;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ do
+ {
+ /* Generate Start */
+ hi2c->Instance->CR2 = I2C_GENERATE_START(hi2c->Init.AddressingMode, DevAddress);
+
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+ /* Wait until STOPF flag is set or a NACK flag is set*/
+ tickstart = HAL_GetTick();
+
+ tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF);
+ tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
+
+ while ((tmp1 == RESET) && (tmp2 == RESET))
+ {
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+ {
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
+ }
+
+ tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF);
+ tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
+ }
+
+ /* Check if the NACKF flag has not been set */
+ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET)
+ {
+ /* Wait until STOPF flag is reset */
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Clear STOP Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+ /* Device is ready */
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ /* Wait until STOPF flag is reset */
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Clear NACK Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+ /* Clear STOP Flag, auto generated with autoend*/
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+ }
+
+ /* Check if the maximum allowed number of trials has been reached */
+ if (I2C_Trials == Trials)
+ {
+ /* Generate Stop */
+ hi2c->Instance->CR2 |= I2C_CR2_STOP;
+
+ /* Wait until STOPF flag is reset */
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Clear STOP Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+ }
+
+ /* Increment Trials */
+ I2C_Trials++;
+ } while (I2C_Trials < Trials);
+
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt.
+ * @note This interface allow to manage repeated start condition when a direction change during transfer
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress Target device address: The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+ uint16_t Size, uint32_t XferOptions)
+{
+ uint32_t xfermode;
+ uint32_t xferrequest = I2C_GENERATE_START_WRITE;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+ if (hi2c->State == HAL_I2C_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_BUSY_TX;
+ hi2c->Mode = HAL_I2C_MODE_MASTER;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferOptions = XferOptions;
+ hi2c->XferISR = I2C_Master_ISR_IT;
+
+ /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ xfermode = I2C_RELOAD_MODE;
+ }
+ else
+ {
+ hi2c->XferSize = hi2c->XferCount;
+ xfermode = hi2c->XferOptions;
+ }
+
+ /* If transfer direction not change and there is no request to start another frame,
+ do not generate Restart Condition */
+ /* Mean Previous state is same as current state */
+ if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && \
+ (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
+ {
+ xferrequest = I2C_NO_STARTSTOP;
+ }
+ else
+ {
+ /* Convert OTHER_xxx XferOptions if any */
+ I2C_ConvertOtherXferOptions(hi2c);
+
+ /* Update xfermode accordingly if no reload is necessary */
+ if (hi2c->XferCount <= MAX_NBYTE_SIZE)
+ {
+ xfermode = hi2c->XferOptions;
+ }
+ }
+
+ /* Send Slave Address and set NBYTES to write */
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with DMA.
+ * @note This interface allow to manage repeated start condition when a direction change during transfer
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress Target device address: The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+ uint16_t Size, uint32_t XferOptions)
+{
+ uint32_t xfermode;
+ uint32_t xferrequest = I2C_GENERATE_START_WRITE;
+ HAL_StatusTypeDef dmaxferstatus;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+ if (hi2c->State == HAL_I2C_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_BUSY_TX;
+ hi2c->Mode = HAL_I2C_MODE_MASTER;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferOptions = XferOptions;
+ hi2c->XferISR = I2C_Master_ISR_DMA;
+
+ /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ xfermode = I2C_RELOAD_MODE;
+ }
+ else
+ {
+ hi2c->XferSize = hi2c->XferCount;
+ xfermode = hi2c->XferOptions;
+ }
+
+ /* If transfer direction not change and there is no request to start another frame,
+ do not generate Restart Condition */
+ /* Mean Previous state is same as current state */
+ if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && \
+ (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
+ {
+ xferrequest = I2C_NO_STARTSTOP;
+ }
+ else
+ {
+ /* Convert OTHER_xxx XferOptions if any */
+ I2C_ConvertOtherXferOptions(hi2c);
+
+ /* Update xfermode accordingly if no reload is necessary */
+ if (hi2c->XferCount <= MAX_NBYTE_SIZE)
+ {
+ xfermode = hi2c->XferOptions;
+ }
+ }
+
+ if (hi2c->XferSize > 0U)
+ {
+ if (hi2c->hdmatx != NULL)
+ {
+ /* Set the I2C DMA transfer complete callback */
+ hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
+
+ /* Set the DMA error callback */
+ hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
+
+ /* Set the unused DMA callbacks to NULL */
+ hi2c->hdmatx->XferHalfCpltCallback = NULL;
+ hi2c->hdmatx->XferAbortCallback = NULL;
+
+ /* Enable the DMA channel */
+ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
+ hi2c->XferSize);
+ }
+ else
+ {
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
+
+ if (dmaxferstatus == HAL_OK)
+ {
+ /* Send Slave Address and set NBYTES to write */
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
+
+ /* Update XferCount value */
+ hi2c->XferCount -= hi2c->XferSize;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+ /* Enable ERR and NACK interrupts */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
+
+ /* Enable DMA Request */
+ hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+ }
+ else
+ {
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ /* Update Transfer ISR function pointer */
+ hi2c->XferISR = I2C_Master_ISR_IT;
+
+ /* Send Slave Address */
+ /* Set NBYTES to write and generate START condition */
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+ I2C_GENERATE_START_WRITE);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+ /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+ /* possible to enable all of these */
+ /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
+ I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
+ }
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt
+ * @note This interface allow to manage repeated start condition when a direction change during transfer
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress Target device address: The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+ uint16_t Size, uint32_t XferOptions)
+{
+ uint32_t xfermode;
+ uint32_t xferrequest = I2C_GENERATE_START_READ;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+ if (hi2c->State == HAL_I2C_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_BUSY_RX;
+ hi2c->Mode = HAL_I2C_MODE_MASTER;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferOptions = XferOptions;
+ hi2c->XferISR = I2C_Master_ISR_IT;
+
+ /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ xfermode = I2C_RELOAD_MODE;
+ }
+ else
+ {
+ hi2c->XferSize = hi2c->XferCount;
+ xfermode = hi2c->XferOptions;
+ }
+
+ /* If transfer direction not change and there is no request to start another frame,
+ do not generate Restart Condition */
+ /* Mean Previous state is same as current state */
+ if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && \
+ (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
+ {
+ xferrequest = I2C_NO_STARTSTOP;
+ }
+ else
+ {
+ /* Convert OTHER_xxx XferOptions if any */
+ I2C_ConvertOtherXferOptions(hi2c);
+
+ /* Update xfermode accordingly if no reload is necessary */
+ if (hi2c->XferCount <= MAX_NBYTE_SIZE)
+ {
+ xfermode = hi2c->XferOptions;
+ }
+ }
+
+ /* Send Slave Address and set NBYTES to read */
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with DMA
+ * @note This interface allow to manage repeated start condition when a direction change during transfer
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress Target device address: The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+ uint16_t Size, uint32_t XferOptions)
+{
+ uint32_t xfermode;
+ uint32_t xferrequest = I2C_GENERATE_START_READ;
+ HAL_StatusTypeDef dmaxferstatus;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+ if (hi2c->State == HAL_I2C_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_BUSY_RX;
+ hi2c->Mode = HAL_I2C_MODE_MASTER;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferOptions = XferOptions;
+ hi2c->XferISR = I2C_Master_ISR_DMA;
+
+ /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ xfermode = I2C_RELOAD_MODE;
+ }
+ else
+ {
+ hi2c->XferSize = hi2c->XferCount;
+ xfermode = hi2c->XferOptions;
+ }
+
+ /* If transfer direction not change and there is no request to start another frame,
+ do not generate Restart Condition */
+ /* Mean Previous state is same as current state */
+ if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && \
+ (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
+ {
+ xferrequest = I2C_NO_STARTSTOP;
+ }
+ else
+ {
+ /* Convert OTHER_xxx XferOptions if any */
+ I2C_ConvertOtherXferOptions(hi2c);
+
+ /* Update xfermode accordingly if no reload is necessary */
+ if (hi2c->XferCount <= MAX_NBYTE_SIZE)
+ {
+ xfermode = hi2c->XferOptions;
+ }
+ }
+
+ if (hi2c->XferSize > 0U)
+ {
+ if (hi2c->hdmarx != NULL)
+ {
+ /* Set the I2C DMA transfer complete callback */
+ hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
+
+ /* Set the DMA error callback */
+ hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
+
+ /* Set the unused DMA callbacks to NULL */
+ hi2c->hdmarx->XferHalfCpltCallback = NULL;
+ hi2c->hdmarx->XferAbortCallback = NULL;
+
+ /* Enable the DMA channel */
+ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
+ hi2c->XferSize);
+ }
+ else
+ {
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
+
+ if (dmaxferstatus == HAL_OK)
+ {
+ /* Send Slave Address and set NBYTES to read */
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
+
+ /* Update XferCount value */
+ hi2c->XferCount -= hi2c->XferSize;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+ /* Enable ERR and NACK interrupts */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
+
+ /* Enable DMA Request */
+ hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+ }
+ else
+ {
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ /* Update Transfer ISR function pointer */
+ hi2c->XferISR = I2C_Master_ISR_IT;
+
+ /* Send Slave Address */
+ /* Set NBYTES to read and generate START condition */
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+ I2C_GENERATE_START_READ);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+ /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+ /* possible to enable all of these */
+ /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
+ I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
+ }
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with Interrupt
+ * @note This interface allow to manage repeated start condition when a direction change during transfer
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
+ uint32_t XferOptions)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+ if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+ return HAL_ERROR;
+ }
+
+ /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
+ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
+ /* and then toggle the HAL slave RX state to TX state */
+ if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
+ {
+ /* Disable associated Interrupts */
+ I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
+
+ /* Abort DMA Xfer if any */
+ if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
+ {
+ hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+
+ if (hi2c->hdmarx != NULL)
+ {
+ /* Set the I2C DMA Abort callback :
+ will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+ hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
+
+ /* Abort DMA RX */
+ if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
+ {
+ /* Call Directly XferAbortCallback function in case of error */
+ hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
+ }
+ }
+ }
+ }
+
+ hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN;
+ hi2c->Mode = HAL_I2C_MODE_SLAVE;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Enable Address Acknowledge */
+ hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferSize = hi2c->XferCount;
+ hi2c->XferOptions = XferOptions;
+ hi2c->XferISR = I2C_Slave_ISR_IT;
+
+ if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE)
+ {
+ /* Clear ADDR flag after prepare the transfer parameters */
+ /* This action will generate an acknowledge to the Master */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+ /* REnable ADDR interrupt */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with DMA
+ * @note This interface allow to manage repeated start condition when a direction change during transfer
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
+ uint32_t XferOptions)
+{
+ HAL_StatusTypeDef dmaxferstatus;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+ if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
+ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
+
+ /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
+ /* and then toggle the HAL slave RX state to TX state */
+ if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
+ {
+ /* Disable associated Interrupts */
+ I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
+
+ if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
+ {
+ /* Abort DMA Xfer if any */
+ if (hi2c->hdmarx != NULL)
+ {
+ hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+
+ /* Set the I2C DMA Abort callback :
+ will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+ hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
+
+ /* Abort DMA RX */
+ if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
+ {
+ /* Call Directly XferAbortCallback function in case of error */
+ hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
+ }
+ }
+ }
+ }
+ else if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
+ {
+ if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
+ {
+ hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+
+ /* Abort DMA Xfer if any */
+ if (hi2c->hdmatx != NULL)
+ {
+ /* Set the I2C DMA Abort callback :
+ will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+ hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
+
+ /* Abort DMA TX */
+ if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
+ {
+ /* Call Directly XferAbortCallback function in case of error */
+ hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
+ }
+ }
+ }
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+
+ hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN;
+ hi2c->Mode = HAL_I2C_MODE_SLAVE;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Enable Address Acknowledge */
+ hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferSize = hi2c->XferCount;
+ hi2c->XferOptions = XferOptions;
+ hi2c->XferISR = I2C_Slave_ISR_DMA;
+
+ if (hi2c->hdmatx != NULL)
+ {
+ /* Set the I2C DMA transfer complete callback */
+ hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;
+
+ /* Set the DMA error callback */
+ hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
+
+ /* Set the unused DMA callbacks to NULL */
+ hi2c->hdmatx->XferHalfCpltCallback = NULL;
+ hi2c->hdmatx->XferAbortCallback = NULL;
+
+ /* Enable the DMA channel */
+ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
+ hi2c->XferSize);
+ }
+ else
+ {
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_LISTEN;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
+
+ if (dmaxferstatus == HAL_OK)
+ {
+ /* Update XferCount value */
+ hi2c->XferCount -= hi2c->XferSize;
+
+ /* Reset XferSize */
+ hi2c->XferSize = 0;
+ }
+ else
+ {
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_LISTEN;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
+
+ if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE)
+ {
+ /* Clear ADDR flag after prepare the transfer parameters */
+ /* This action will generate an acknowledge to the Master */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Enable DMA Request */
+ hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+ /* Enable ERR, STOP, NACK, ADDR interrupts */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with Interrupt
+ * @note This interface allow to manage repeated start condition when a direction change during transfer
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
+ uint32_t XferOptions)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+ if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+ return HAL_ERROR;
+ }
+
+ /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
+ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
+ /* and then toggle the HAL slave TX state to RX state */
+ if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
+ {
+ /* Disable associated Interrupts */
+ I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
+
+ if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
+ {
+ hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+
+ /* Abort DMA Xfer if any */
+ if (hi2c->hdmatx != NULL)
+ {
+ /* Set the I2C DMA Abort callback :
+ will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+ hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
+
+ /* Abort DMA TX */
+ if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
+ {
+ /* Call Directly XferAbortCallback function in case of error */
+ hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
+ }
+ }
+ }
+ }
+
+ hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN;
+ hi2c->Mode = HAL_I2C_MODE_SLAVE;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Enable Address Acknowledge */
+ hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferSize = hi2c->XferCount;
+ hi2c->XferOptions = XferOptions;
+ hi2c->XferISR = I2C_Slave_ISR_IT;
+
+ if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT)
+ {
+ /* Clear ADDR flag after prepare the transfer parameters */
+ /* This action will generate an acknowledge to the Master */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+ /* REnable ADDR interrupt */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with DMA
+ * @note This interface allow to manage repeated start condition when a direction change during transfer
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
+ uint32_t XferOptions)
+{
+ HAL_StatusTypeDef dmaxferstatus;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+ if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+ return HAL_ERROR;
+ }
+
+ /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
+ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
+ /* and then toggle the HAL slave TX state to RX state */
+ if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
+ {
+ /* Disable associated Interrupts */
+ I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
+
+ if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
+ {
+ /* Abort DMA Xfer if any */
+ if (hi2c->hdmatx != NULL)
+ {
+ hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+
+ /* Set the I2C DMA Abort callback :
+ will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+ hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
+
+ /* Abort DMA TX */
+ if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
+ {
+ /* Call Directly XferAbortCallback function in case of error */
+ hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
+ }
+ }
+ }
+ }
+ else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
+ {
+ if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
+ {
+ hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+
+ /* Abort DMA Xfer if any */
+ if (hi2c->hdmarx != NULL)
+ {
+ /* Set the I2C DMA Abort callback :
+ will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+ hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
+
+ /* Abort DMA RX */
+ if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
+ {
+ /* Call Directly XferAbortCallback function in case of error */
+ hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
+ }
+ }
+ }
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+
+ hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN;
+ hi2c->Mode = HAL_I2C_MODE_SLAVE;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Enable Address Acknowledge */
+ hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferSize = hi2c->XferCount;
+ hi2c->XferOptions = XferOptions;
+ hi2c->XferISR = I2C_Slave_ISR_DMA;
+
+ if (hi2c->hdmarx != NULL)
+ {
+ /* Set the I2C DMA transfer complete callback */
+ hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt;
+
+ /* Set the DMA error callback */
+ hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
+
+ /* Set the unused DMA callbacks to NULL */
+ hi2c->hdmarx->XferHalfCpltCallback = NULL;
+ hi2c->hdmarx->XferAbortCallback = NULL;
+
+ /* Enable the DMA channel */
+ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR,
+ (uint32_t)pData, hi2c->XferSize);
+ }
+ else
+ {
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_LISTEN;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
+
+ if (dmaxferstatus == HAL_OK)
+ {
+ /* Update XferCount value */
+ hi2c->XferCount -= hi2c->XferSize;
+
+ /* Reset XferSize */
+ hi2c->XferSize = 0;
+ }
+ else
+ {
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_LISTEN;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
+
+ if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT)
+ {
+ /* Clear ADDR flag after prepare the transfer parameters */
+ /* This action will generate an acknowledge to the Master */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Enable DMA Request */
+ hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+ /* REnable ADDR interrupt */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Enable the Address listen mode with Interrupt.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c)
+{
+ if (hi2c->State == HAL_I2C_STATE_READY)
+ {
+ hi2c->State = HAL_I2C_STATE_LISTEN;
+ hi2c->XferISR = I2C_Slave_ISR_IT;
+
+ /* Enable the Address Match interrupt */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Disable the Address listen mode with Interrupt.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c)
+{
+ /* Declaration of tmp to prevent undefined behavior of volatile usage */
+ uint32_t tmp;
+
+ /* Disable Address listen mode only if a transfer is not ongoing */
+ if (hi2c->State == HAL_I2C_STATE_LISTEN)
+ {
+ tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK;
+ hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode);
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+ hi2c->XferISR = NULL;
+
+ /* Disable the Address Match interrupt */
+ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Abort a master I2C IT or DMA process communication with Interrupt.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress Target device address: The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
+{
+ if (hi2c->Mode == HAL_I2C_MODE_MASTER)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ /* Disable Interrupts and Store Previous state */
+ if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
+ {
+ I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
+ hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
+ }
+ else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
+ {
+ I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
+ hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
+ }
+ else
+ {
+ /* Do nothing */
+ }
+
+ /* Set State at HAL_I2C_STATE_ABORT */
+ hi2c->State = HAL_I2C_STATE_ABORT;
+
+ /* Set NBYTES to 1 to generate a dummy read on I2C peripheral */
+ /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */
+ I2C_TransferConfig(hi2c, DevAddress, 1, I2C_AUTOEND_MODE, I2C_GENERATE_STOP);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
+
+ return HAL_OK;
+ }
+ else
+ {
+ /* Wrong usage of abort function */
+ /* This function should be used only in case of abort monitored by master device */
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
+ * @{
+ */
+
+/**
+ * @brief This function handles I2C event interrupt request.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval None
+ */
+void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c)
+{
+ /* Get current IT Flags and IT sources value */
+ uint32_t itflags = READ_REG(hi2c->Instance->ISR);
+ uint32_t itsources = READ_REG(hi2c->Instance->CR1);
+
+ /* I2C events treatment -------------------------------------*/
+ if (hi2c->XferISR != NULL)
+ {
+ hi2c->XferISR(hi2c, itflags, itsources);
+ }
+}
+
+/**
+ * @brief This function handles I2C error interrupt request.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval None
+ */
+void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
+{
+ uint32_t itflags = READ_REG(hi2c->Instance->ISR);
+ uint32_t itsources = READ_REG(hi2c->Instance->CR1);
+ uint32_t tmperror;
+
+ /* I2C Bus error interrupt occurred ------------------------------------*/
+ if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_BERR) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_BERR;
+
+ /* Clear BERR flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
+ }
+
+ /* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/
+ if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_OVR) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_OVR;
+
+ /* Clear OVR flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
+ }
+
+ /* I2C Arbitration Loss error interrupt occurred -------------------------------------*/
+ if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_ARLO) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO;
+
+ /* Clear ARLO flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
+ }
+
+ /* Store current volatile hi2c->ErrorCode, misra rule */
+ tmperror = hi2c->ErrorCode;
+
+ /* Call the Error Callback in case of Error detected */
+ if ((tmperror & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) != HAL_I2C_ERROR_NONE)
+ {
+ I2C_ITError(hi2c, tmperror);
+ }
+}
+
+/**
+ * @brief Master Tx Transfer completed callback.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval None
+ */
+__weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2c);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_I2C_MasterTxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Master Rx Transfer completed callback.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval None
+ */
+__weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2c);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_I2C_MasterRxCpltCallback could be implemented in the user file
+ */
+}
+
+/** @brief Slave Tx Transfer completed callback.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval None
+ */
+__weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2c);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Slave Rx Transfer completed callback.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval None
+ */
+__weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2c);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Slave Address Match callback.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XFERDIRECTION
+ * @param AddrMatchCode Address Match Code
+ * @retval None
+ */
+__weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2c);
+ UNUSED(TransferDirection);
+ UNUSED(AddrMatchCode);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_I2C_AddrCallback() could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Listen Complete callback.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval None
+ */
+__weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2c);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_I2C_ListenCpltCallback() could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Memory Tx Transfer completed callback.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval None
+ */
+__weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2c);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_I2C_MemTxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Memory Rx Transfer completed callback.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval None
+ */
+__weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2c);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_I2C_MemRxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief I2C error callback.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval None
+ */
+__weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2c);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_I2C_ErrorCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief I2C abort callback.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval None
+ */
+__weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2c);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_I2C_AbortCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
+ * @brief Peripheral State, Mode and Error functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral State, Mode and Error functions #####
+ ===============================================================================
+ [..]
+ This subsection permit to get in run-time the status of the peripheral
+ and the data flow.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the I2C handle state.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval HAL state
+ */
+HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c)
+{
+ /* Return I2C handle state */
+ return hi2c->State;
+}
+
+/**
+ * @brief Returns the I2C Master, Slave, Memory or no mode.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
+ * @retval HAL mode
+ */
+HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c)
+{
+ return hi2c->Mode;
+}
+
+/**
+ * @brief Return the I2C error code.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval I2C Error Code
+ */
+uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c)
+{
+ return hi2c->ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with Interrupt.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param ITFlags Interrupt flags to handle.
+ * @param ITSources Interrupt sources enabled.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
+ uint32_t ITSources)
+{
+ uint16_t devaddress;
+ uint32_t tmpITFlags = ITFlags;
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
+ {
+ /* Clear NACK Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+ /* Set corresponding Error Code */
+ /* No need to generate STOP, it is automatically done */
+ /* Error callback will be send during stop flag treatment */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+
+ /* Flush TX register */
+ I2C_Flush_TXDR(hi2c);
+ }
+ else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
+ {
+ /* Remove RXNE flag on temporary variable as read done */
+ tmpITFlags &= ~I2C_FLAG_RXNE;
+
+ /* Read data from RXDR */
+ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
+
+ hi2c->XferSize--;
+ hi2c->XferCount--;
+ }
+ else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
+ {
+ /* Write data to TXDR */
+ hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
+
+ hi2c->XferSize--;
+ hi2c->XferCount--;
+ }
+ else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+ {
+ if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
+ {
+ devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD);
+
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+ }
+ else
+ {
+ hi2c->XferSize = hi2c->XferCount;
+ if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
+ {
+ I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize,
+ hi2c->XferOptions, I2C_NO_STARTSTOP);
+ }
+ else
+ {
+ I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize,
+ I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+ }
+ }
+ }
+ else
+ {
+ /* Call TxCpltCallback() if no stop mode is set */
+ if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
+ {
+ /* Call I2C Master Sequential complete process */
+ I2C_ITMasterSeqCplt(hi2c);
+ }
+ else
+ {
+ /* Wrong size Status regarding TCR flag event */
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
+ }
+ }
+ }
+ else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+ {
+ if (hi2c->XferCount == 0U)
+ {
+ if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
+ {
+ /* Generate a stop condition in case of no transfer option */
+ if (hi2c->XferOptions == I2C_NO_OPTION_FRAME)
+ {
+ /* Generate Stop */
+ hi2c->Instance->CR2 |= I2C_CR2_STOP;
+ }
+ else
+ {
+ /* Call I2C Master Sequential complete process */
+ I2C_ITMasterSeqCplt(hi2c);
+ }
+ }
+ }
+ else
+ {
+ /* Wrong size Status regarding TC flag event */
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
+ }
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+
+ if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
+ {
+ /* Call I2C Master complete process */
+ I2C_ITMasterCplt(hi2c, tmpITFlags);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param ITFlags Interrupt flags to handle.
+ * @param ITSources Interrupt sources enabled.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
+ uint32_t ITSources)
+{
+ uint32_t tmpoptions = hi2c->XferOptions;
+ uint32_t tmpITFlags = ITFlags;
+
+ /* Process locked */
+ __HAL_LOCK(hi2c);
+
+ /* Check if STOPF is set */
+ if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
+ {
+ /* Call I2C Slave complete process */
+ I2C_ITSlaveCplt(hi2c, tmpITFlags);
+ }
+
+ if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
+ {
+ /* Check that I2C transfer finished */
+ /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
+ /* Mean XferCount == 0*/
+ /* So clear Flag NACKF only */
+ if (hi2c->XferCount == 0U)
+ {
+ if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME))
+ /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for
+ Warning[Pa134]: left and right operands are identical */
+ {
+ /* Call I2C Listen complete process */
+ I2C_ITListenCplt(hi2c, tmpITFlags);
+ }
+ else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME))
+ {
+ /* Clear NACK Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+ /* Flush TX register */
+ I2C_Flush_TXDR(hi2c);
+
+ /* Last Byte is Transmitted */
+ /* Call I2C Slave Sequential complete process */
+ I2C_ITSlaveSeqCplt(hi2c);
+ }
+ else
+ {
+ /* Clear NACK Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+ }
+ }
+ else
+ {
+ /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
+ /* Clear NACK Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+ /* Set ErrorCode corresponding to a Non-Acknowledge */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+
+ if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME))
+ {
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ I2C_ITError(hi2c, hi2c->ErrorCode);
+ }
+ }
+ }
+ else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
+ {
+ if (hi2c->XferCount > 0U)
+ {
+ /* Read data from RXDR */
+ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
+
+ hi2c->XferSize--;
+ hi2c->XferCount--;
+ }
+
+ if ((hi2c->XferCount == 0U) && \
+ (tmpoptions != I2C_NO_OPTION_FRAME))
+ {
+ /* Call I2C Slave Sequential complete process */
+ I2C_ITSlaveSeqCplt(hi2c);
+ }
+ }
+ else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_ADDR) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET))
+ {
+ I2C_ITAddrCplt(hi2c, tmpITFlags);
+ }
+ else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
+ {
+ /* Write data to TXDR only if XferCount not reach "0" */
+ /* A TXIS flag can be set, during STOP treatment */
+ /* Check if all Data have already been sent */
+ /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */
+ if (hi2c->XferCount > 0U)
+ {
+ /* Write data to TXDR */
+ hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
+
+ hi2c->XferCount--;
+ hi2c->XferSize--;
+ }
+ else
+ {
+ if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME))
+ {
+ /* Last Byte is Transmitted */
+ /* Call I2C Slave Sequential complete process */
+ I2C_ITSlaveSeqCplt(hi2c);
+ }
+ }
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with DMA.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param ITFlags Interrupt flags to handle.
+ * @param ITSources Interrupt sources enabled.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
+ uint32_t ITSources)
+{
+ uint16_t devaddress;
+ uint32_t xfermode;
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
+ {
+ /* Clear NACK Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+ /* Set corresponding Error Code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+
+ /* No need to generate STOP, it is automatically done */
+ /* But enable STOP interrupt, to treat it */
+ /* Error callback will be send during stop flag treatment */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
+
+ /* Flush TX register */
+ I2C_Flush_TXDR(hi2c);
+ }
+ else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+ {
+ /* Disable TC interrupt */
+ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_TCI);
+
+ if (hi2c->XferCount != 0U)
+ {
+ /* Recover Slave address */
+ devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD);
+
+ /* Prepare the new XferSize to transfer */
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ xfermode = I2C_RELOAD_MODE;
+ }
+ else
+ {
+ hi2c->XferSize = hi2c->XferCount;
+ if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
+ {
+ xfermode = hi2c->XferOptions;
+ }
+ else
+ {
+ xfermode = I2C_AUTOEND_MODE;
+ }
+ }
+
+ /* Set the new XferSize in Nbytes register */
+ I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
+
+ /* Update XferCount value */
+ hi2c->XferCount -= hi2c->XferSize;
+
+ /* Enable DMA Request */
+ if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
+ {
+ hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+ }
+ else
+ {
+ hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+ }
+ }
+ else
+ {
+ /* Call TxCpltCallback() if no stop mode is set */
+ if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
+ {
+ /* Call I2C Master Sequential complete process */
+ I2C_ITMasterSeqCplt(hi2c);
+ }
+ else
+ {
+ /* Wrong size Status regarding TCR flag event */
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
+ }
+ }
+ }
+ else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+ {
+ if (hi2c->XferCount == 0U)
+ {
+ if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
+ {
+ /* Generate a stop condition in case of no transfer option */
+ if (hi2c->XferOptions == I2C_NO_OPTION_FRAME)
+ {
+ /* Generate Stop */
+ hi2c->Instance->CR2 |= I2C_CR2_STOP;
+ }
+ else
+ {
+ /* Call I2C Master Sequential complete process */
+ I2C_ITMasterSeqCplt(hi2c);
+ }
+ }
+ }
+ else
+ {
+ /* Wrong size Status regarding TC flag event */
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
+ }
+ }
+ else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
+ {
+ /* Call I2C Master complete process */
+ I2C_ITMasterCplt(hi2c, ITFlags);
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param ITFlags Interrupt flags to handle.
+ * @param ITSources Interrupt sources enabled.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
+ uint32_t ITSources)
+{
+ uint32_t tmpoptions = hi2c->XferOptions;
+ uint32_t treatdmanack = 0U;
+ HAL_I2C_StateTypeDef tmpstate;
+
+ /* Process locked */
+ __HAL_LOCK(hi2c);
+
+ /* Check if STOPF is set */
+ if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
+ {
+ /* Call I2C Slave complete process */
+ I2C_ITSlaveCplt(hi2c, ITFlags);
+ }
+
+ if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
+ {
+ /* Check that I2C transfer finished */
+ /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
+ /* Mean XferCount == 0 */
+ /* So clear Flag NACKF only */
+ if ((I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) ||
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET))
+ {
+ /* Split check of hdmarx, for MISRA compliance */
+ if (hi2c->hdmarx != NULL)
+ {
+ if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET)
+ {
+ if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx) == 0U)
+ {
+ treatdmanack = 1U;
+ }
+ }
+ }
+
+ /* Split check of hdmatx, for MISRA compliance */
+ if (hi2c->hdmatx != NULL)
+ {
+ if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET)
+ {
+ if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx) == 0U)
+ {
+ treatdmanack = 1U;
+ }
+ }
+ }
+
+ if (treatdmanack == 1U)
+ {
+ if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME))
+ /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for
+ Warning[Pa134]: left and right operands are identical */
+ {
+ /* Call I2C Listen complete process */
+ I2C_ITListenCplt(hi2c, ITFlags);
+ }
+ else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME))
+ {
+ /* Clear NACK Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+ /* Flush TX register */
+ I2C_Flush_TXDR(hi2c);
+
+ /* Last Byte is Transmitted */
+ /* Call I2C Slave Sequential complete process */
+ I2C_ITSlaveSeqCplt(hi2c);
+ }
+ else
+ {
+ /* Clear NACK Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+ }
+ }
+ else
+ {
+ /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
+ /* Clear NACK Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+ /* Set ErrorCode corresponding to a Non-Acknowledge */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+
+ /* Store current hi2c->State, solve MISRA2012-Rule-13.5 */
+ tmpstate = hi2c->State;
+
+ if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME))
+ {
+ if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN))
+ {
+ hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
+ }
+ else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
+ {
+ hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
+ }
+ else
+ {
+ /* Do nothing */
+ }
+
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ I2C_ITError(hi2c, hi2c->ErrorCode);
+ }
+ }
+ }
+ else
+ {
+ /* Only Clear NACK Flag, no DMA treatment is pending */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+ }
+ }
+ else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_ADDR) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET))
+ {
+ I2C_ITAddrCplt(hi2c, ITFlags);
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Master sends target device address followed by internal memory address for write request.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress Target device address: The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @param MemAddress Internal memory address
+ * @param MemAddSize Size of internal memory address
+ * @param Timeout Timeout duration
+ * @param Tickstart Tick start value
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
+ uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
+ uint32_t Tickstart)
+{
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
+
+ /* Wait until TXIS flag is set */
+ if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /* If Memory address size is 8Bit */
+ if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
+ {
+ /* Send Memory Address */
+ hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
+ }
+ /* If Memory address size is 16Bit */
+ else
+ {
+ /* Send MSB of Memory Address */
+ hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
+
+ /* Wait until TXIS flag is set */
+ if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Send LSB of Memory Address */
+ hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
+ }
+
+ /* Wait until TCR flag is set */
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Master sends target device address followed by internal memory address for read request.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress Target device address: The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @param MemAddress Internal memory address
+ * @param MemAddSize Size of internal memory address
+ * @param Timeout Timeout duration
+ * @param Tickstart Tick start value
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
+ uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
+ uint32_t Tickstart)
+{
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
+
+ /* Wait until TXIS flag is set */
+ if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /* If Memory address size is 8Bit */
+ if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
+ {
+ /* Send Memory Address */
+ hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
+ }
+ /* If Memory address size is 16Bit */
+ else
+ {
+ /* Send MSB of Memory Address */
+ hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
+
+ /* Wait until TXIS flag is set */
+ if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Send LSB of Memory Address */
+ hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
+ }
+
+ /* Wait until TC flag is set */
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief I2C Address complete process callback.
+ * @param hi2c I2C handle.
+ * @param ITFlags Interrupt flags to handle.
+ * @retval None
+ */
+static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
+{
+ uint8_t transferdirection;
+ uint16_t slaveaddrcode;
+ uint16_t ownadd1code;
+ uint16_t ownadd2code;
+
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(ITFlags);
+
+ /* In case of Listen state, need to inform upper layer of address match code event */
+ if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
+ {
+ transferdirection = I2C_GET_DIR(hi2c);
+ slaveaddrcode = I2C_GET_ADDR_MATCH(hi2c);
+ ownadd1code = I2C_GET_OWN_ADDRESS1(hi2c);
+ ownadd2code = I2C_GET_OWN_ADDRESS2(hi2c);
+
+ /* If 10bits addressing mode is selected */
+ if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
+ {
+ if ((slaveaddrcode & SLAVE_ADDR_MSK) == ((ownadd1code >> SLAVE_ADDR_SHIFT) & SLAVE_ADDR_MSK))
+ {
+ slaveaddrcode = ownadd1code;
+ hi2c->AddrEventCount++;
+ if (hi2c->AddrEventCount == 2U)
+ {
+ /* Reset Address Event counter */
+ hi2c->AddrEventCount = 0U;
+
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Call Slave Addr callback */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode);
+#else
+ HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+ }
+ }
+ else
+ {
+ slaveaddrcode = ownadd2code;
+
+ /* Disable ADDR Interrupts */
+ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Call Slave Addr callback */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode);
+#else
+ HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+ }
+ }
+ /* else 7 bits addressing mode is selected */
+ else
+ {
+ /* Disable ADDR Interrupts */
+ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Call Slave Addr callback */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode);
+#else
+ HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+ }
+ }
+ /* Else clear address flag only */
+ else
+ {
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ }
+}
+
+/**
+ * @brief I2C Master sequential complete process.
+ * @param hi2c I2C handle.
+ * @retval None
+ */
+static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c)
+{
+ /* Reset I2C handle mode */
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* No Generate Stop, to permit restart mode */
+ /* The stop will be done at the end of transfer, when I2C_AUTOEND_MODE enable */
+ if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
+ {
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
+ hi2c->XferISR = NULL;
+
+ /* Disable Interrupts */
+ I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ hi2c->MasterTxCpltCallback(hi2c);
+#else
+ HAL_I2C_MasterTxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+ }
+ /* hi2c->State == HAL_I2C_STATE_BUSY_RX */
+ else
+ {
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
+ hi2c->XferISR = NULL;
+
+ /* Disable Interrupts */
+ I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ hi2c->MasterRxCpltCallback(hi2c);
+#else
+ HAL_I2C_MasterRxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+ }
+}
+
+/**
+ * @brief I2C Slave sequential complete process.
+ * @param hi2c I2C handle.
+ * @retval None
+ */
+static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c)
+{
+ uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1);
+
+ /* Reset I2C handle mode */
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* If a DMA is ongoing, Update handle size context */
+ if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET)
+ {
+ /* Disable DMA Request */
+ hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+ }
+ else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET)
+ {
+ /* Disable DMA Request */
+ hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+ }
+ else
+ {
+ /* Do nothing */
+ }
+
+ if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
+ {
+ /* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */
+ hi2c->State = HAL_I2C_STATE_LISTEN;
+ hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
+
+ /* Disable Interrupts */
+ I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ hi2c->SlaveTxCpltCallback(hi2c);
+#else
+ HAL_I2C_SlaveTxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+ }
+
+ else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
+ {
+ /* Remove HAL_I2C_STATE_SLAVE_BUSY_RX, keep only HAL_I2C_STATE_LISTEN */
+ hi2c->State = HAL_I2C_STATE_LISTEN;
+ hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
+
+ /* Disable Interrupts */
+ I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ hi2c->SlaveRxCpltCallback(hi2c);
+#else
+ HAL_I2C_SlaveRxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+}
+
+/**
+ * @brief I2C Master complete process.
+ * @param hi2c I2C handle.
+ * @param ITFlags Interrupt flags to handle.
+ * @retval None
+ */
+static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
+{
+ uint32_t tmperror;
+ uint32_t tmpITFlags = ITFlags;
+ __IO uint32_t tmpreg;
+
+ /* Clear STOP Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+ /* Disable Interrupts and Store Previous state */
+ if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
+ {
+ I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
+ hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
+ }
+ else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
+ {
+ I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
+ hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
+ }
+ else
+ {
+ /* Do nothing */
+ }
+
+ /* Clear Configuration Register 2 */
+ I2C_RESET_CR2(hi2c);
+
+ /* Reset handle parameters */
+ hi2c->XferISR = NULL;
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+
+ if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET)
+ {
+ /* Clear NACK Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+ /* Set acknowledge error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+ }
+
+ /* Fetch Last receive data if any */
+ if ((hi2c->State == HAL_I2C_STATE_ABORT) && (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET))
+ {
+ /* Read data from RXDR */
+ tmpreg = (uint8_t)hi2c->Instance->RXDR;
+ UNUSED(tmpreg);
+ }
+
+ /* Flush TX register */
+ I2C_Flush_TXDR(hi2c);
+
+ /* Store current volatile hi2c->ErrorCode, misra rule */
+ tmperror = hi2c->ErrorCode;
+
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ if ((hi2c->State == HAL_I2C_STATE_ABORT) || (tmperror != HAL_I2C_ERROR_NONE))
+ {
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ I2C_ITError(hi2c, hi2c->ErrorCode);
+ }
+ /* hi2c->State == HAL_I2C_STATE_BUSY_TX */
+ else if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
+ {
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->PreviousState = I2C_STATE_NONE;
+
+ if (hi2c->Mode == HAL_I2C_MODE_MEM)
+ {
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ hi2c->MemTxCpltCallback(hi2c);
+#else
+ HAL_I2C_MemTxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+ }
+ else
+ {
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ hi2c->MasterTxCpltCallback(hi2c);
+#else
+ HAL_I2C_MasterTxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+ }
+ }
+ /* hi2c->State == HAL_I2C_STATE_BUSY_RX */
+ else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
+ {
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->PreviousState = I2C_STATE_NONE;
+
+ if (hi2c->Mode == HAL_I2C_MODE_MEM)
+ {
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ hi2c->MemRxCpltCallback(hi2c);
+#else
+ HAL_I2C_MemRxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+ }
+ else
+ {
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ hi2c->MasterRxCpltCallback(hi2c);
+#else
+ HAL_I2C_MasterRxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+ }
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+}
+
+/**
+ * @brief I2C Slave complete process.
+ * @param hi2c I2C handle.
+ * @param ITFlags Interrupt flags to handle.
+ * @retval None
+ */
+static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
+{
+ uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1);
+ uint32_t tmpITFlags = ITFlags;
+ HAL_I2C_StateTypeDef tmpstate = hi2c->State;
+
+ /* Clear STOP Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+ /* Disable Interrupts and Store Previous state */
+ if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN))
+ {
+ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
+ hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
+ }
+ else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
+ {
+ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
+ hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
+ }
+ else
+ {
+ /* Do nothing */
+ }
+
+ /* Disable Address Acknowledge */
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+ /* Clear Configuration Register 2 */
+ I2C_RESET_CR2(hi2c);
+
+ /* Flush TX register */
+ I2C_Flush_TXDR(hi2c);
+
+ /* If a DMA is ongoing, Update handle size context */
+ if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET)
+ {
+ /* Disable DMA Request */
+ hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+
+ if (hi2c->hdmatx != NULL)
+ {
+ hi2c->XferCount = (uint16_t)I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx);
+ }
+ }
+ else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET)
+ {
+ /* Disable DMA Request */
+ hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+
+ if (hi2c->hdmarx != NULL)
+ {
+ hi2c->XferCount = (uint16_t)I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx);
+ }
+ }
+ else
+ {
+ /* Do nothing */
+ }
+
+ /* Store Last receive data if any */
+ if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET)
+ {
+ /* Remove RXNE flag on temporary variable as read done */
+ tmpITFlags &= ~I2C_FLAG_RXNE;
+
+ /* Read data from RXDR */
+ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
+
+ if ((hi2c->XferSize > 0U))
+ {
+ hi2c->XferSize--;
+ hi2c->XferCount--;
+ }
+ }
+
+ /* All data are not transferred, so set error code accordingly */
+ if (hi2c->XferCount != 0U)
+ {
+ /* Set ErrorCode corresponding to a Non-Acknowledge */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+ }
+
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+ hi2c->XferISR = NULL;
+
+ if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
+ {
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ I2C_ITError(hi2c, hi2c->ErrorCode);
+
+ /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
+ if (hi2c->State == HAL_I2C_STATE_LISTEN)
+ {
+ /* Call I2C Listen complete process */
+ I2C_ITListenCplt(hi2c, tmpITFlags);
+ }
+ }
+ else if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
+ {
+ /* Call the Sequential Complete callback, to inform upper layer of the end of Transfer */
+ I2C_ITSlaveSeqCplt(hi2c);
+
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->PreviousState = I2C_STATE_NONE;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ hi2c->ListenCpltCallback(hi2c);
+#else
+ HAL_I2C_ListenCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+ }
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
+ {
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->PreviousState = I2C_STATE_NONE;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ hi2c->SlaveRxCpltCallback(hi2c);
+#else
+ HAL_I2C_SlaveRxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+ }
+ else
+ {
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->PreviousState = I2C_STATE_NONE;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ hi2c->SlaveTxCpltCallback(hi2c);
+#else
+ HAL_I2C_SlaveTxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+ }
+}
+
+/**
+ * @brief I2C Listen complete process.
+ * @param hi2c I2C handle.
+ * @param ITFlags Interrupt flags to handle.
+ * @retval None
+ */
+static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
+{
+ /* Reset handle parameters */
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ hi2c->PreviousState = I2C_STATE_NONE;
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+ hi2c->XferISR = NULL;
+
+ /* Store Last receive data if any */
+ if (I2C_CHECK_FLAG(ITFlags, I2C_FLAG_RXNE) != RESET)
+ {
+ /* Read data from RXDR */
+ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
+
+ if ((hi2c->XferSize > 0U))
+ {
+ hi2c->XferSize--;
+ hi2c->XferCount--;
+
+ /* Set ErrorCode corresponding to a Non-Acknowledge */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+ }
+ }
+
+ /* Disable all Interrupts*/
+ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);
+
+ /* Clear NACK Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ hi2c->ListenCpltCallback(hi2c);
+#else
+ HAL_I2C_ListenCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief I2C interrupts error process.
+ * @param hi2c I2C handle.
+ * @param ErrorCode Error code to handle.
+ * @retval None
+ */
+static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
+{
+ HAL_I2C_StateTypeDef tmpstate = hi2c->State;
+ uint32_t tmppreviousstate;
+
+ /* Reset handle parameters */
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ hi2c->XferCount = 0U;
+
+ /* Set new error code */
+ hi2c->ErrorCode |= ErrorCode;
+
+ /* Disable Interrupts */
+ if ((tmpstate == HAL_I2C_STATE_LISTEN) ||
+ (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN) ||
+ (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
+ {
+ /* Disable all interrupts, except interrupts related to LISTEN state */
+ I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_TX_IT);
+
+ /* keep HAL_I2C_STATE_LISTEN if set */
+ hi2c->State = HAL_I2C_STATE_LISTEN;
+ hi2c->XferISR = I2C_Slave_ISR_IT;
+ }
+ else
+ {
+ /* Disable all interrupts */
+ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);
+
+ /* If state is an abort treatment on going, don't change state */
+ /* This change will be do later */
+ if (hi2c->State != HAL_I2C_STATE_ABORT)
+ {
+ /* Set HAL_I2C_STATE_READY */
+ hi2c->State = HAL_I2C_STATE_READY;
+ }
+ hi2c->XferISR = NULL;
+ }
+
+ /* Abort DMA TX transfer if any */
+ tmppreviousstate = hi2c->PreviousState;
+ if ((hi2c->hdmatx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_TX) || \
+ (tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX)))
+ {
+ if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
+ {
+ hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+ }
+
+ if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY)
+ {
+ /* Set the I2C DMA Abort callback :
+ will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+ hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Abort DMA TX */
+ if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
+ {
+ /* Call Directly XferAbortCallback function in case of error */
+ hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
+ }
+ }
+ else
+ {
+ I2C_TreatErrorCallback(hi2c);
+ }
+ }
+ /* Abort DMA RX transfer if any */
+ else if ((hi2c->hdmarx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_RX) || \
+ (tmppreviousstate == I2C_STATE_SLAVE_BUSY_RX)))
+ {
+ if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
+ {
+ hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+ }
+
+ if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY)
+ {
+ /* Set the I2C DMA Abort callback :
+ will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+ hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Abort DMA RX */
+ if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
+ {
+ /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */
+ hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
+ }
+ }
+ else
+ {
+ I2C_TreatErrorCallback(hi2c);
+ }
+ }
+ else
+ {
+ I2C_TreatErrorCallback(hi2c);
+ }
+}
+
+/**
+ * @brief I2C Error callback treatment.
+ * @param hi2c I2C handle.
+ * @retval None
+ */
+static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c)
+{
+ if (hi2c->State == HAL_I2C_STATE_ABORT)
+ {
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->PreviousState = I2C_STATE_NONE;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ hi2c->AbortCpltCallback(hi2c);
+#else
+ HAL_I2C_AbortCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+ }
+ else
+ {
+ hi2c->PreviousState = I2C_STATE_NONE;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ hi2c->ErrorCallback(hi2c);
+#else
+ HAL_I2C_ErrorCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+ }
+}
+
+/**
+ * @brief I2C Tx data register flush process.
+ * @param hi2c I2C handle.
+ * @retval None
+ */
+static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c)
+{
+ /* If a pending TXIS flag is set */
+ /* Write a dummy data in TXDR to clear it */
+ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET)
+ {
+ hi2c->Instance->TXDR = 0x00U;
+ }
+
+ /* Flush TX register if not empty */
+ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
+ {
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE);
+ }
+}
+
+/**
+ * @brief DMA I2C master transmit process complete callback.
+ * @param hdma DMA handle
+ * @retval None
+ */
+static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma)
+{
+ /* Derogation MISRAC2012-Rule-11.5 */
+ I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
+
+ /* Disable DMA Request */
+ hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+
+ /* If last transfer, enable STOP interrupt */
+ if (hi2c->XferCount == 0U)
+ {
+ /* Enable STOP interrupt */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
+ }
+ /* else prepare a new DMA transfer and enable TCReload interrupt */
+ else
+ {
+ /* Update Buffer pointer */
+ hi2c->pBuffPtr += hi2c->XferSize;
+
+ /* Set the XferSize to transfer */
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ }
+ else
+ {
+ hi2c->XferSize = hi2c->XferCount;
+ }
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR,
+ hi2c->XferSize) != HAL_OK)
+ {
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
+ }
+ else
+ {
+ /* Enable TC interrupts */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);
+ }
+ }
+}
+
+/**
+ * @brief DMA I2C slave transmit process complete callback.
+ * @param hdma DMA handle
+ * @retval None
+ */
+static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma)
+{
+ /* Derogation MISRAC2012-Rule-11.5 */
+ I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
+ uint32_t tmpoptions = hi2c->XferOptions;
+
+ if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME))
+ {
+ /* Disable DMA Request */
+ hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+
+ /* Last Byte is Transmitted */
+ /* Call I2C Slave Sequential complete process */
+ I2C_ITSlaveSeqCplt(hi2c);
+ }
+ else
+ {
+ /* No specific action, Master fully manage the generation of STOP condition */
+ /* Mean that this generation can arrive at any time, at the end or during DMA process */
+ /* So STOP condition should be manage through Interrupt treatment */
+ }
+}
+
+/**
+ * @brief DMA I2C master receive process complete callback.
+ * @param hdma DMA handle
+ * @retval None
+ */
+static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+ /* Derogation MISRAC2012-Rule-11.5 */
+ I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
+
+ /* Disable DMA Request */
+ hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+
+ /* If last transfer, enable STOP interrupt */
+ if (hi2c->XferCount == 0U)
+ {
+ /* Enable STOP interrupt */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
+ }
+ /* else prepare a new DMA transfer and enable TCReload interrupt */
+ else
+ {
+ /* Update Buffer pointer */
+ hi2c->pBuffPtr += hi2c->XferSize;
+
+ /* Set the XferSize to transfer */
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ }
+ else
+ {
+ hi2c->XferSize = hi2c->XferCount;
+ }
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr,
+ hi2c->XferSize) != HAL_OK)
+ {
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
+ }
+ else
+ {
+ /* Enable TC interrupts */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);
+ }
+ }
+}
+
+/**
+ * @brief DMA I2C slave receive process complete callback.
+ * @param hdma DMA handle
+ * @retval None
+ */
+static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+ /* Derogation MISRAC2012-Rule-11.5 */
+ I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
+ uint32_t tmpoptions = hi2c->XferOptions;
+
+ if ((I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx) == 0U) && \
+ (tmpoptions != I2C_NO_OPTION_FRAME))
+ {
+ /* Disable DMA Request */
+ hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+
+ /* Call I2C Slave Sequential complete process */
+ I2C_ITSlaveSeqCplt(hi2c);
+ }
+ else
+ {
+ /* No specific action, Master fully manage the generation of STOP condition */
+ /* Mean that this generation can arrive at any time, at the end or during DMA process */
+ /* So STOP condition should be manage through Interrupt treatment */
+ }
+}
+
+/**
+ * @brief DMA I2C communication error callback.
+ * @param hdma DMA handle
+ * @retval None
+ */
+static void I2C_DMAError(DMA_HandleTypeDef *hdma)
+{
+ /* Derogation MISRAC2012-Rule-11.5 */
+ I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
+
+ /* Disable Acknowledge */
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
+}
+
+/**
+ * @brief DMA I2C communication abort callback
+ * (To be called at end of DMA Abort procedure).
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void I2C_DMAAbort(DMA_HandleTypeDef *hdma)
+{
+ /* Derogation MISRAC2012-Rule-11.5 */
+ I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
+
+ /* Reset AbortCpltCallback */
+ if (hi2c->hdmatx != NULL)
+ {
+ hi2c->hdmatx->XferAbortCallback = NULL;
+ }
+ if (hi2c->hdmarx != NULL)
+ {
+ hi2c->hdmarx->XferAbortCallback = NULL;
+ }
+
+ I2C_TreatErrorCallback(hi2c);
+}
+
+/**
+ * @brief This function handles I2C Communication Timeout. It waits
+ * until a flag is no longer in the specified status.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param Flag Specifies the I2C flag to check.
+ * @param Status The actual Flag status (SET or RESET).
+ * @param Timeout Timeout duration
+ * @param Tickstart Tick start value
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status,
+ uint32_t Timeout, uint32_t Tickstart)
+{
+ while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
+ {
+ /* Check for the Timeout */
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_ERROR;
+ }
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief This function handles I2C Communication Timeout for specific usage of TXIS flag.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param Timeout Timeout duration
+ * @param Tickstart Tick start value
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
+ uint32_t Tickstart)
+{
+ while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)
+ {
+ /* Check if an error is detected */
+ if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check for the Timeout */
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief This function handles I2C Communication Timeout for specific usage of STOP flag.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param Timeout Timeout duration
+ * @param Tickstart Tick start value
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
+ uint32_t Tickstart)
+{
+ while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
+ {
+ /* Check if an error is detected */
+ if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check for the Timeout */
+ if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief This function handles I2C Communication Timeout for specific usage of RXNE flag.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param Timeout Timeout duration
+ * @param Tickstart Tick start value
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
+ uint32_t Tickstart)
+{
+ while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)
+ {
+ /* Check if an error is detected */
+ if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check if a STOPF is detected */
+ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
+ {
+ /* Check if an RXNE is pending */
+ /* Store Last receive data if any */
+ if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) && (hi2c->XferSize > 0U))
+ {
+ /* Return HAL_OK */
+ /* The Reading of data from RXDR will be done in caller function */
+ return HAL_OK;
+ }
+ else
+ {
+ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
+ {
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+ hi2c->ErrorCode = HAL_I2C_ERROR_AF;
+ }
+ else
+ {
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ }
+
+ /* Clear STOP Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+ /* Clear Configuration Register 2 */
+ I2C_RESET_CR2(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
+ }
+
+ /* Check for the Timeout */
+ if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief This function handles errors detection during an I2C Communication.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param Timeout Timeout duration
+ * @param Tickstart Tick start value
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t itflag = hi2c->Instance->ISR;
+ uint32_t error_code = 0;
+ uint32_t tickstart = Tickstart;
+ uint32_t tmp1;
+ HAL_I2C_ModeTypeDef tmp2;
+
+ if (HAL_IS_BIT_SET(itflag, I2C_FLAG_AF))
+ {
+ /* Clear NACKF Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+ /* Wait until STOP Flag is set or timeout occurred */
+ /* AutoEnd should be initiate after AF */
+ while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (status == HAL_OK))
+ {
+ /* Check for the Timeout */
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+ {
+ tmp1 = (uint32_t)(hi2c->Instance->CR2 & I2C_CR2_STOP);
+ tmp2 = hi2c->Mode;
+
+ /* In case of I2C still busy, try to regenerate a STOP manually */
+ if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET) && \
+ (tmp1 != I2C_CR2_STOP) && \
+ (tmp2 != HAL_I2C_MODE_SLAVE))
+ {
+ /* Generate Stop */
+ hi2c->Instance->CR2 |= I2C_CR2_STOP;
+
+ /* Update Tick with new reference */
+ tickstart = HAL_GetTick();
+ }
+
+ while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
+ {
+ /* Check for the Timeout */
+ if ((HAL_GetTick() - tickstart) > I2C_TIMEOUT_STOPF)
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ status = HAL_ERROR;
+ }
+ }
+ }
+ }
+ }
+
+ /* In case STOP Flag is detected, clear it */
+ if (status == HAL_OK)
+ {
+ /* Clear STOP Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+ }
+
+ error_code |= HAL_I2C_ERROR_AF;
+
+ status = HAL_ERROR;
+ }
+
+ /* Refresh Content of Status register */
+ itflag = hi2c->Instance->ISR;
+
+ /* Then verify if an additional errors occurs */
+ /* Check if a Bus error occurred */
+ if (HAL_IS_BIT_SET(itflag, I2C_FLAG_BERR))
+ {
+ error_code |= HAL_I2C_ERROR_BERR;
+
+ /* Clear BERR flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
+
+ status = HAL_ERROR;
+ }
+
+ /* Check if an Over-Run/Under-Run error occurred */
+ if (HAL_IS_BIT_SET(itflag, I2C_FLAG_OVR))
+ {
+ error_code |= HAL_I2C_ERROR_OVR;
+
+ /* Clear OVR flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
+
+ status = HAL_ERROR;
+ }
+
+ /* Check if an Arbitration Loss error occurred */
+ if (HAL_IS_BIT_SET(itflag, I2C_FLAG_ARLO))
+ {
+ error_code |= HAL_I2C_ERROR_ARLO;
+
+ /* Clear ARLO flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
+
+ status = HAL_ERROR;
+ }
+
+ if (status != HAL_OK)
+ {
+ /* Flush TX register */
+ I2C_Flush_TXDR(hi2c);
+
+ /* Clear Configuration Register 2 */
+ I2C_RESET_CR2(hi2c);
+
+ hi2c->ErrorCode |= error_code;
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ }
+
+ return status;
+}
+
+/**
+ * @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
+ * @param hi2c I2C handle.
+ * @param DevAddress Specifies the slave address to be programmed.
+ * @param Size Specifies the number of bytes to be programmed.
+ * This parameter must be a value between 0 and 255.
+ * @param Mode New state of the I2C START condition generation.
+ * This parameter can be one of the following values:
+ * @arg @ref I2C_RELOAD_MODE Enable Reload mode .
+ * @arg @ref I2C_AUTOEND_MODE Enable Automatic end mode.
+ * @arg @ref I2C_SOFTEND_MODE Enable Software end mode.
+ * @param Request New state of the I2C START condition generation.
+ * This parameter can be one of the following values:
+ * @arg @ref I2C_NO_STARTSTOP Don't Generate stop and start condition.
+ * @arg @ref I2C_GENERATE_STOP Generate stop condition (Size should be set to 0).
+ * @arg @ref I2C_GENERATE_START_READ Generate Restart for read request.
+ * @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request.
+ * @retval None
+ */
+static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode,
+ uint32_t Request)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
+ assert_param(IS_TRANSFER_MODE(Mode));
+ assert_param(IS_TRANSFER_REQUEST(Request));
+
+ /* Declaration of tmp to prevent undefined behavior of volatile usage */
+ uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \
+ (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \
+ (uint32_t)Mode | (uint32_t)Request) & (~0x80000000U));
+
+ /* update CR2 register */
+ MODIFY_REG(hi2c->Instance->CR2, \
+ ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | \
+ (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | \
+ I2C_CR2_START | I2C_CR2_STOP)), tmp);
+}
+
+/**
+ * @brief Manage the enabling of Interrupts.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition.
+ * @retval None
+ */
+static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
+{
+ uint32_t tmpisr = 0U;
+
+ if ((hi2c->XferISR == I2C_Master_ISR_DMA) || \
+ (hi2c->XferISR == I2C_Slave_ISR_DMA))
+ {
+ if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
+ {
+ /* Enable ERR, STOP, NACK and ADDR interrupts */
+ tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
+ }
+
+ if (InterruptRequest == I2C_XFER_ERROR_IT)
+ {
+ /* Enable ERR and NACK interrupts */
+ tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
+ }
+
+ if (InterruptRequest == I2C_XFER_CPLT_IT)
+ {
+ /* Enable STOP interrupts */
+ tmpisr |= (I2C_IT_STOPI | I2C_IT_TCI);
+ }
+
+ if (InterruptRequest == I2C_XFER_RELOAD_IT)
+ {
+ /* Enable TC interrupts */
+ tmpisr |= I2C_IT_TCI;
+ }
+ }
+ else
+ {
+ if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
+ {
+ /* Enable ERR, STOP, NACK, and ADDR interrupts */
+ tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
+ }
+
+ if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
+ {
+ /* Enable ERR, TC, STOP, NACK and RXI interrupts */
+ tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI;
+ }
+
+ if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
+ {
+ /* Enable ERR, TC, STOP, NACK and TXI interrupts */
+ tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI;
+ }
+
+ if (InterruptRequest == I2C_XFER_CPLT_IT)
+ {
+ /* Enable STOP interrupts */
+ tmpisr |= I2C_IT_STOPI;
+ }
+ }
+
+ /* Enable interrupts only at the end */
+ /* to avoid the risk of I2C interrupt handle execution before */
+ /* all interrupts requested done */
+ __HAL_I2C_ENABLE_IT(hi2c, tmpisr);
+}
+
+/**
+ * @brief Manage the disabling of Interrupts.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition.
+ * @retval None
+ */
+static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
+{
+ uint32_t tmpisr = 0U;
+
+ if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
+ {
+ /* Disable TC and TXI interrupts */
+ tmpisr |= I2C_IT_TCI | I2C_IT_TXI;
+
+ if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN)
+ {
+ /* Disable NACK and STOP interrupts */
+ tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
+ }
+ }
+
+ if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
+ {
+ /* Disable TC and RXI interrupts */
+ tmpisr |= I2C_IT_TCI | I2C_IT_RXI;
+
+ if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN)
+ {
+ /* Disable NACK and STOP interrupts */
+ tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
+ }
+ }
+
+ if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
+ {
+ /* Disable ADDR, NACK and STOP interrupts */
+ tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
+ }
+
+ if (InterruptRequest == I2C_XFER_ERROR_IT)
+ {
+ /* Enable ERR and NACK interrupts */
+ tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
+ }
+
+ if (InterruptRequest == I2C_XFER_CPLT_IT)
+ {
+ /* Enable STOP interrupts */
+ tmpisr |= I2C_IT_STOPI;
+ }
+
+ if (InterruptRequest == I2C_XFER_RELOAD_IT)
+ {
+ /* Enable TC interrupts */
+ tmpisr |= I2C_IT_TCI;
+ }
+
+ /* Disable interrupts only at the end */
+ /* to avoid a breaking situation like at "t" time */
+ /* all disable interrupts request are not done */
+ __HAL_I2C_DISABLE_IT(hi2c, tmpisr);
+}
+
+/**
+ * @brief Convert I2Cx OTHER_xxx XferOptions to functional XferOptions.
+ * @param hi2c I2C handle.
+ * @retval None
+ */
+static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c)
+{
+ /* if user set XferOptions to I2C_OTHER_FRAME */
+ /* it request implicitly to generate a restart condition */
+ /* set XferOptions to I2C_FIRST_FRAME */
+ if (hi2c->XferOptions == I2C_OTHER_FRAME)
+ {
+ hi2c->XferOptions = I2C_FIRST_FRAME;
+ }
+ /* else if user set XferOptions to I2C_OTHER_AND_LAST_FRAME */
+ /* it request implicitly to generate a restart condition */
+ /* then generate a stop condition at the end of transfer */
+ /* set XferOptions to I2C_FIRST_AND_LAST_FRAME */
+ else if (hi2c->XferOptions == I2C_OTHER_AND_LAST_FRAME)
+ {
+ hi2c->XferOptions = I2C_FIRST_AND_LAST_FRAME;
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+}
+
+/**
+ * @}
+ */
+
+#endif /* HAL_I2C_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_i2c_ex.c b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_i2c_ex.c
new file mode 100644
index 0000000000..bc9cf4c824
--- /dev/null
+++ b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_i2c_ex.c
@@ -0,0 +1,356 @@
+/**
+ ******************************************************************************
+ * @file stm32c0xx_hal_i2c_ex.c
+ * @author MCD Application Team
+ * @brief I2C Extended HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of I2C Extended peripheral:
+ * + Filter Mode Functions
+ * + WakeUp Mode Functions
+ * + FastModePlus Functions
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2022 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### I2C peripheral Extended features #####
+ ==============================================================================
+
+ [..] Comparing to other previous devices, the I2C interface for STM32C0xx
+ devices contains the following additional features
+
+ (+) Possibility to disable or enable Analog Noise Filter
+ (+) Use of a configured Digital Noise Filter
+ (+) Disable or enable wakeup from Stop mode(s)
+ (+) Disable or enable Fast Mode Plus
+
+ ##### How to use this driver #####
+ ==============================================================================
+ [..] This driver provides functions to configure Noise Filter and Wake Up Feature
+ (#) Configure I2C Analog noise filter using the function HAL_I2CEx_ConfigAnalogFilter()
+ (#) Configure I2C Digital noise filter using the function HAL_I2CEx_ConfigDigitalFilter()
+ (#) Configure the enable or disable of I2C Wake Up Mode using the functions :
+ (++) HAL_I2CEx_EnableWakeUp()
+ (++) HAL_I2CEx_DisableWakeUp()
+ (#) Configure the enable or disable of fast mode plus driving capability using the functions :
+ (++) HAL_I2CEx_EnableFastModePlus()
+ (++) HAL_I2CEx_DisableFastModePlus()
+ @endverbatim
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32c0xx_hal.h"
+
+/** @addtogroup STM32C0xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup I2CEx I2CEx
+ * @brief I2C Extended HAL module driver
+ * @{
+ */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup I2CEx_Exported_Functions I2C Extended Exported Functions
+ * @{
+ */
+
+/** @defgroup I2CEx_Exported_Functions_Group1 Filter Mode Functions
+ * @brief Filter Mode Functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Filter Mode Functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Configure Noise Filters
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configure I2C Analog noise filter.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2Cx peripheral.
+ * @param AnalogFilter New state of the Analog filter.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
+ assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter));
+
+ if (hi2c->State == HAL_I2C_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_BUSY;
+
+ /* Disable the selected I2C peripheral */
+ __HAL_I2C_DISABLE(hi2c);
+
+ /* Reset I2Cx ANOFF bit */
+ hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF);
+
+ /* Set analog filter bit*/
+ hi2c->Instance->CR1 |= AnalogFilter;
+
+ __HAL_I2C_ENABLE(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Configure I2C Digital noise filter.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2Cx peripheral.
+ * @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
+{
+ uint32_t tmpreg;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
+ assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter));
+
+ if (hi2c->State == HAL_I2C_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_BUSY;
+
+ /* Disable the selected I2C peripheral */
+ __HAL_I2C_DISABLE(hi2c);
+
+ /* Get the old register value */
+ tmpreg = hi2c->Instance->CR1;
+
+ /* Reset I2Cx DNF bits [11:8] */
+ tmpreg &= ~(I2C_CR1_DNF);
+
+ /* Set I2Cx DNF coefficient */
+ tmpreg |= DigitalFilter << 8U;
+
+ /* Store the new register value */
+ hi2c->Instance->CR1 = tmpreg;
+
+ __HAL_I2C_ENABLE(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+/**
+ * @}
+ */
+
+/** @defgroup I2CEx_Exported_Functions_Group2 WakeUp Mode Functions
+ * @brief WakeUp Mode Functions
+ *
+@verbatim
+ ===============================================================================
+ ##### WakeUp Mode Functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Configure Wake Up Feature
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enable I2C wakeup from Stop mode(s).
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2Cx peripheral.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance));
+
+ if (hi2c->State == HAL_I2C_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_BUSY;
+
+ /* Disable the selected I2C peripheral */
+ __HAL_I2C_DISABLE(hi2c);
+
+ /* Enable wakeup from stop mode */
+ hi2c->Instance->CR1 |= I2C_CR1_WUPEN;
+
+ __HAL_I2C_ENABLE(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Disable I2C wakeup from Stop mode(s).
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2Cx peripheral.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance));
+
+ if (hi2c->State == HAL_I2C_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_BUSY;
+
+ /* Disable the selected I2C peripheral */
+ __HAL_I2C_DISABLE(hi2c);
+
+ /* Enable wakeup from stop mode */
+ hi2c->Instance->CR1 &= ~(I2C_CR1_WUPEN);
+
+ __HAL_I2C_ENABLE(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+/**
+ * @}
+ */
+
+/** @defgroup I2CEx_Exported_Functions_Group3 Fast Mode Plus Functions
+ * @brief Fast Mode Plus Functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Fast Mode Plus Functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Configure Fast Mode Plus
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enable the I2C fast mode plus driving capability.
+ * @param ConfigFastModePlus Selects the pin.
+ * This parameter can be one of the @ref I2CEx_FastModePlus values
+ * @note For I2C1, fast mode plus driving capability can be enabled on all selected
+ * I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently
+ * on each one of the following pins PB6, PB7, PB8 and PB9.
+ * @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability
+ * can be enabled only by using I2C_FASTMODEPLUS_I2C1 parameter.
+ * @retval None
+ */
+void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus)
+{
+ /* Check the parameter */
+ assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus));
+
+ /* Enable SYSCFG clock */
+ __HAL_RCC_SYSCFG_CLK_ENABLE();
+
+ /* Enable fast mode plus driving capability for selected pin */
+ SET_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus);
+}
+
+/**
+ * @brief Disable the I2C fast mode plus driving capability.
+ * @param ConfigFastModePlus Selects the pin.
+ * This parameter can be one of the @ref I2CEx_FastModePlus values
+ * @note For I2C1, fast mode plus driving capability can be disabled on all selected
+ * I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently
+ * on each one of the following pins PB6, PB7, PB8 and PB9.
+ * @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability
+ * can be disabled only by using I2C_FASTMODEPLUS_I2C1 parameter.
+ * @retval None
+ */
+void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus)
+{
+ /* Check the parameter */
+ assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus));
+
+ /* Enable SYSCFG clock */
+ __HAL_RCC_SYSCFG_CLK_ENABLE();
+
+ /* Disable fast mode plus driving capability for selected pin */
+ CLEAR_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus);
+}
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+
+#endif /* HAL_I2C_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_i2s.c b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_i2s.c
new file mode 100644
index 0000000000..69515eea16
--- /dev/null
+++ b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_i2s.c
@@ -0,0 +1,1857 @@
+/**
+ ******************************************************************************
+ * @file stm32c0xx_hal_i2s.c
+ * @author MCD Application Team
+ * @brief I2S HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Integrated Interchip Sound (I2S) peripheral:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral State and Errors functions
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2022 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ===============================================================================
+ ##### How to use this driver #####
+ ===============================================================================
+ [..]
+ The I2S HAL driver can be used as follow:
+
+ (#) Declare a I2S_HandleTypeDef handle structure.
+ (#) Initialize the I2S low level resources by implement the HAL_I2S_MspInit() API:
+ (##) Enable the SPIx interface clock.
+ (##) I2S pins configuration:
+ (+++) Enable the clock for the I2S GPIOs.
+ (+++) Configure these I2S pins as alternate function pull-up.
+ (##) NVIC configuration if you need to use interrupt process (HAL_I2S_Transmit_IT()
+ and HAL_I2S_Receive_IT() APIs).
+ (+++) Configure the I2Sx interrupt priority.
+ (+++) Enable the NVIC I2S IRQ handle.
+ (##) DMA Configuration if you need to use DMA process (HAL_I2S_Transmit_DMA()
+ and HAL_I2S_Receive_DMA() APIs:
+ (+++) Declare a DMA handle structure for the Tx/Rx Stream/Channel.
+ (+++) Enable the DMAx interface clock.
+ (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
+ (+++) Configure the DMA Tx/Rx Stream/Channel.
+ (+++) Associate the initialized DMA handle to the I2S DMA Tx/Rx handle.
+ (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the
+ DMA Tx/Rx Stream/Channel.
+
+ (#) Program the Mode, Standard, Data Format, MCLK Output, Audio frequency and Polarity
+ using HAL_I2S_Init() function.
+
+ -@- The specific I2S interrupts (Transmission complete interrupt,
+ RXNE interrupt and Error Interrupts) will be managed using the macros
+ __HAL_I2S_ENABLE_IT() and __HAL_I2S_DISABLE_IT() inside the transmit and receive process.
+ -@- Make sure that either:
+ (+@) SYSCLK is selected as I2S1 clock or
+ (+@) HSIKER clock is selected or
+ (+@) External clock source is configured after setting correctly
+ the define constant EXTERNAL_I2S1_CLOCK_VALUE in the stm32c0xx_hal_conf.h file.
+
+ (#) Three mode of operations are available within this driver :
+
+ *** Polling mode IO operation ***
+ =================================
+ [..]
+ (+) Send an amount of data in blocking mode using HAL_I2S_Transmit()
+ (+) Receive an amount of data in blocking mode using HAL_I2S_Receive()
+
+ *** Interrupt mode IO operation ***
+ ===================================
+ [..]
+ (+) Send an amount of data in non blocking mode using HAL_I2S_Transmit_IT()
+ (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
+ (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2S_TxCpltCallback
+ (+) Receive an amount of data in non blocking mode using HAL_I2S_Receive_IT()
+ (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
+ (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2S_RxCpltCallback
+ (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_I2S_ErrorCallback
+
+ *** DMA mode IO operation ***
+ ==============================
+ [..]
+ (+) Send an amount of data in non blocking mode (DMA) using HAL_I2S_Transmit_DMA()
+ (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
+ (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2S_TxCpltCallback
+ (+) Receive an amount of data in non blocking mode (DMA) using HAL_I2S_Receive_DMA()
+ (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
+ (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2S_RxCpltCallback
+ (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_I2S_ErrorCallback
+ (+) Pause the DMA Transfer using HAL_I2S_DMAPause()
+ (+) Resume the DMA Transfer using HAL_I2S_DMAResume()
+ (+) Stop the DMA Transfer using HAL_I2S_DMAStop()
+ In Slave mode, if HAL_I2S_DMAStop is used to stop the communication, an error
+ HAL_I2S_ERROR_BUSY_LINE_RX is raised as the master continue to transmit data.
+ In this case __HAL_I2S_FLUSH_RX_DR macro must be used to flush the remaining data
+ inside DR register and avoid using DeInit/Init process for the next transfer.
+
+ *** I2S HAL driver macros list ***
+ ===================================
+ [..]
+ Below the list of most used macros in I2S HAL driver.
+
+ (+) __HAL_I2S_ENABLE: Enable the specified SPI peripheral (in I2S mode)
+ (+) __HAL_I2S_DISABLE: Disable the specified SPI peripheral (in I2S mode)
+ (+) __HAL_I2S_ENABLE_IT : Enable the specified I2S interrupts
+ (+) __HAL_I2S_DISABLE_IT : Disable the specified I2S interrupts
+ (+) __HAL_I2S_GET_FLAG: Check whether the specified I2S flag is set or not
+ (+) __HAL_I2S_FLUSH_RX_DR: Read DR Register to Flush RX Data
+
+ [..]
+ (@) You can refer to the I2S HAL driver header file for more useful macros
+
+ *** I2S HAL driver macros list ***
+ ===================================
+ [..]
+ Callback registration:
+
+ (#) The compilation flag USE_HAL_I2S_REGISTER_CALLBACKS when set to 1U
+ allows the user to configure dynamically the driver callbacks.
+ Use Functions HAL_I2S_RegisterCallback() to register an interrupt callback.
+
+ Function HAL_I2S_RegisterCallback() allows to register following callbacks:
+ (++) TxCpltCallback : I2S Tx Completed callback
+ (++) RxCpltCallback : I2S Rx Completed callback
+ (++) TxHalfCpltCallback : I2S Tx Half Completed callback
+ (++) RxHalfCpltCallback : I2S Rx Half Completed callback
+ (++) ErrorCallback : I2S Error callback
+ (++) MspInitCallback : I2S Msp Init callback
+ (++) MspDeInitCallback : I2S Msp DeInit callback
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+
+ (#) Use function HAL_I2S_UnRegisterCallback to reset a callback to the default
+ weak function.
+ HAL_I2S_UnRegisterCallback takes as parameters the HAL peripheral handle,
+ and the Callback ID.
+ This function allows to reset following callbacks:
+ (++) TxCpltCallback : I2S Tx Completed callback
+ (++) RxCpltCallback : I2S Rx Completed callback
+ (++) TxHalfCpltCallback : I2S Tx Half Completed callback
+ (++) RxHalfCpltCallback : I2S Rx Half Completed callback
+ (++) ErrorCallback : I2S Error callback
+ (++) MspInitCallback : I2S Msp Init callback
+ (++) MspDeInitCallback : I2S Msp DeInit callback
+
+ [..]
+ By default, after the HAL_I2S_Init() and when the state is HAL_I2S_STATE_RESET
+ all callbacks are set to the corresponding weak functions:
+ examples HAL_I2S_MasterTxCpltCallback(), HAL_I2S_MasterRxCpltCallback().
+ Exception done for MspInit and MspDeInit functions that are
+ reset to the legacy weak functions in the HAL_I2S_Init()/ HAL_I2S_DeInit() only when
+ these callbacks are null (not registered beforehand).
+ If MspInit or MspDeInit are not null, the HAL_I2S_Init()/ HAL_I2S_DeInit()
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
+
+ [..]
+ Callbacks can be registered/unregistered in HAL_I2S_STATE_READY state only.
+ Exception done MspInit/MspDeInit functions that can be registered/unregistered
+ in HAL_I2S_STATE_READY or HAL_I2S_STATE_RESET state,
+ thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+ Then, the user first registers the MspInit/MspDeInit user callbacks
+ using HAL_I2S_RegisterCallback() before calling HAL_I2S_DeInit()
+ or HAL_I2S_Init() function.
+
+ [..]
+ When the compilation define USE_HAL_I2S_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registering feature is not available
+ and weak (surcharged) callbacks are used.
+
+ @endverbatim
+
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32c0xx_hal.h"
+
+#ifdef HAL_I2S_MODULE_ENABLED
+
+#if defined(SPI_I2S_SUPPORT)
+/** @addtogroup STM32C0xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup I2S I2S
+ * @brief I2S HAL module driver
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#define I2S_TIMEOUT_FLAG 100U /*!< Timeout 100 ms */
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup I2S_Private_Functions I2S Private Functions
+ * @{
+ */
+static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma);
+static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
+static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma);
+static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
+static void I2S_DMAError(DMA_HandleTypeDef *hdma);
+static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s);
+static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s);
+static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, FlagStatus State,
+ uint32_t Timeout);
+/**
+ * @}
+ */
+
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup I2S_Exported_Functions I2S Exported Functions
+ * @{
+ */
+
+/** @defgroup I2S_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..] This subsection provides a set of functions allowing to initialize and
+ de-initialize the I2Sx peripheral in simplex mode:
+
+ (+) User must Implement HAL_I2S_MspInit() function in which he configures
+ all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
+
+ (+) Call the function HAL_I2S_Init() to configure the selected device with
+ the selected configuration:
+ (++) Mode
+ (++) Standard
+ (++) Data Format
+ (++) MCLK Output
+ (++) Audio frequency
+ (++) Polarity
+
+ (+) Call the function HAL_I2S_DeInit() to restore the default configuration
+ of the selected I2Sx peripheral.
+ @endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the I2S according to the specified parameters
+ * in the I2S_InitTypeDef and create the associated handle.
+ * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
+{
+ uint32_t i2sdiv;
+ uint32_t i2sodd;
+ uint32_t packetlength;
+ uint32_t tmp;
+ uint32_t i2sclk;
+
+ /* Check the I2S handle allocation */
+ if (hi2s == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the I2S parameters */
+ assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance));
+ assert_param(IS_I2S_MODE(hi2s->Init.Mode));
+ assert_param(IS_I2S_STANDARD(hi2s->Init.Standard));
+ assert_param(IS_I2S_DATA_FORMAT(hi2s->Init.DataFormat));
+ assert_param(IS_I2S_MCLK_OUTPUT(hi2s->Init.MCLKOutput));
+ assert_param(IS_I2S_AUDIO_FREQ(hi2s->Init.AudioFreq));
+ assert_param(IS_I2S_CPOL(hi2s->Init.CPOL));
+
+ if (hi2s->State == HAL_I2S_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hi2s->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
+ /* Init the I2S Callback settings */
+ hi2s->TxCpltCallback = HAL_I2S_TxCpltCallback; /* Legacy weak TxCpltCallback */
+ hi2s->RxCpltCallback = HAL_I2S_RxCpltCallback; /* Legacy weak RxCpltCallback */
+ hi2s->TxHalfCpltCallback = HAL_I2S_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
+ hi2s->RxHalfCpltCallback = HAL_I2S_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
+ hi2s->ErrorCallback = HAL_I2S_ErrorCallback; /* Legacy weak ErrorCallback */
+
+ if (hi2s->MspInitCallback == NULL)
+ {
+ hi2s->MspInitCallback = HAL_I2S_MspInit; /* Legacy weak MspInit */
+ }
+
+ /* Init the low level hardware : GPIO, CLOCK, NVIC... */
+ hi2s->MspInitCallback(hi2s);
+#else
+ /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
+ HAL_I2S_MspInit(hi2s);
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
+ }
+
+ hi2s->State = HAL_I2S_STATE_BUSY;
+
+ /*----------------------- SPIx I2SCFGR & I2SPR Configuration ----------------*/
+ /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
+ CLEAR_BIT(hi2s->Instance->I2SCFGR, (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CKPOL | \
+ SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \
+ SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD));
+ hi2s->Instance->I2SPR = 0x0002U;
+
+ /*----------------------- I2SPR: I2SDIV and ODD Calculation -----------------*/
+ /* If the requested audio frequency is not the default, compute the prescaler */
+ if (hi2s->Init.AudioFreq != I2S_AUDIOFREQ_DEFAULT)
+ {
+ /* Check the frame length (For the Prescaler computing) ********************/
+ if (hi2s->Init.DataFormat == I2S_DATAFORMAT_16B)
+ {
+ /* Packet length is 16 bits */
+ packetlength = 16U;
+ }
+ else
+ {
+ /* Packet length is 32 bits */
+ packetlength = 32U;
+ }
+
+ /* I2S standard */
+ if (hi2s->Init.Standard <= I2S_STANDARD_LSB)
+ {
+ /* In I2S standard packet length is multiplied by 2 */
+ packetlength = packetlength * 2U;
+ }
+
+ /* Get the source clock value: based on System Clock value */
+ i2sclk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_I2S1);
+
+ /* Compute the Real divider depending on the MCLK output state, with a floating point */
+ if (hi2s->Init.MCLKOutput == I2S_MCLKOUTPUT_ENABLE)
+ {
+ /* MCLK output is enabled */
+ if (hi2s->Init.DataFormat != I2S_DATAFORMAT_16B)
+ {
+ tmp = (uint32_t)(((((i2sclk / (packetlength * 4U)) * 10U) / hi2s->Init.AudioFreq)) + 5U);
+ }
+ else
+ {
+ tmp = (uint32_t)(((((i2sclk / (packetlength * 8U)) * 10U) / hi2s->Init.AudioFreq)) + 5U);
+ }
+ }
+ else
+ {
+ /* MCLK output is disabled */
+ tmp = (uint32_t)(((((i2sclk / packetlength) * 10U) / hi2s->Init.AudioFreq)) + 5U);
+ }
+
+ /* Remove the flatting point */
+ tmp = tmp / 10U;
+
+ /* Check the parity of the divider */
+ i2sodd = (uint32_t)(tmp & (uint32_t)1U);
+
+ /* Compute the i2sdiv prescaler */
+ i2sdiv = (uint32_t)((tmp - i2sodd) / 2U);
+
+ /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
+ i2sodd = (uint32_t)(i2sodd << 8U);
+ }
+ else
+ {
+ /* Set the default values */
+ i2sdiv = 2U;
+ i2sodd = 0U;
+ }
+
+ /* Test if the divider is 1 or 0 or greater than 0xFF */
+ if ((i2sdiv < 2U) || (i2sdiv > 0xFFU))
+ {
+ /* Set the error code and execute error callback*/
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_PRESCALER);
+ return HAL_ERROR;
+ }
+
+ /*----------------------- SPIx I2SCFGR & I2SPR Configuration ----------------*/
+
+ /* Write to SPIx I2SPR register the computed value */
+ hi2s->Instance->I2SPR = (uint32_t)((uint32_t)i2sdiv | (uint32_t)(i2sodd | (uint32_t)hi2s->Init.MCLKOutput));
+
+ /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
+ /* And configure the I2S with the I2S_InitStruct values */
+ MODIFY_REG(hi2s->Instance->I2SCFGR, (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | \
+ SPI_I2SCFGR_CKPOL | SPI_I2SCFGR_I2SSTD | \
+ SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \
+ SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD), \
+ (SPI_I2SCFGR_I2SMOD | hi2s->Init.Mode | \
+ hi2s->Init.Standard | hi2s->Init.DataFormat | \
+ hi2s->Init.CPOL));
+
+#if defined(SPI_I2SCFGR_ASTRTEN)
+ if ((hi2s->Init.Standard == I2S_STANDARD_PCM_SHORT) || ((hi2s->Init.Standard == I2S_STANDARD_PCM_LONG)))
+ {
+ /* Write to SPIx I2SCFGR */
+ SET_BIT(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_ASTRTEN);
+ }
+#endif /* SPI_I2SCFGR_ASTRTEN */
+
+ hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+ hi2s->State = HAL_I2S_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the I2S peripheral
+ * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s)
+{
+ /* Check the I2S handle allocation */
+ if (hi2s == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance));
+
+ hi2s->State = HAL_I2S_STATE_BUSY;
+
+ /* Disable the I2S Peripheral Clock */
+ __HAL_I2S_DISABLE(hi2s);
+
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
+ if (hi2s->MspDeInitCallback == NULL)
+ {
+ hi2s->MspDeInitCallback = HAL_I2S_MspDeInit; /* Legacy weak MspDeInit */
+ }
+
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
+ hi2s->MspDeInitCallback(hi2s);
+#else
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
+ HAL_I2S_MspDeInit(hi2s);
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
+
+ hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+ hi2s->State = HAL_I2S_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hi2s);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief I2S MSP Init
+ * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval None
+ */
+__weak void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2s);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_I2S_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief I2S MSP DeInit
+ * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval None
+ */
+__weak void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2s);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_I2S_MspDeInit could be implemented in the user file
+ */
+}
+
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
+/**
+ * @brief Register a User I2S Callback
+ * To be used instead of the weak predefined callback
+ * @param hi2s Pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for the specified I2S.
+ * @param CallbackID ID of the callback to be registered
+ * @param pCallback pointer to the Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID,
+ pI2S_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hi2s->ErrorCode |= HAL_I2S_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+ /* Process locked */
+ __HAL_LOCK(hi2s);
+
+ if (HAL_I2S_STATE_READY == hi2s->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_I2S_TX_COMPLETE_CB_ID :
+ hi2s->TxCpltCallback = pCallback;
+ break;
+
+ case HAL_I2S_RX_COMPLETE_CB_ID :
+ hi2s->RxCpltCallback = pCallback;
+ break;
+
+ case HAL_I2S_TX_HALF_COMPLETE_CB_ID :
+ hi2s->TxHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_I2S_RX_HALF_COMPLETE_CB_ID :
+ hi2s->RxHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_I2S_ERROR_CB_ID :
+ hi2s->ErrorCallback = pCallback;
+ break;
+
+ case HAL_I2S_MSPINIT_CB_ID :
+ hi2s->MspInitCallback = pCallback;
+ break;
+
+ case HAL_I2S_MSPDEINIT_CB_ID :
+ hi2s->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_I2S_STATE_RESET == hi2s->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_I2S_MSPINIT_CB_ID :
+ hi2s->MspInitCallback = pCallback;
+ break;
+
+ case HAL_I2S_MSPDEINIT_CB_ID :
+ hi2s->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hi2s);
+ return status;
+}
+
+/**
+ * @brief Unregister an I2S Callback
+ * I2S callback is redirected to the weak predefined callback
+ * @param hi2s Pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for the specified I2S.
+ * @param CallbackID ID of the callback to be unregistered
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hi2s);
+
+ if (HAL_I2S_STATE_READY == hi2s->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_I2S_TX_COMPLETE_CB_ID :
+ hi2s->TxCpltCallback = HAL_I2S_TxCpltCallback; /* Legacy weak TxCpltCallback */
+ break;
+
+ case HAL_I2S_RX_COMPLETE_CB_ID :
+ hi2s->RxCpltCallback = HAL_I2S_RxCpltCallback; /* Legacy weak RxCpltCallback */
+ break;
+
+ case HAL_I2S_TX_HALF_COMPLETE_CB_ID :
+ hi2s->TxHalfCpltCallback = HAL_I2S_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
+ break;
+
+ case HAL_I2S_RX_HALF_COMPLETE_CB_ID :
+ hi2s->RxHalfCpltCallback = HAL_I2S_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
+ break;
+
+ case HAL_I2S_ERROR_CB_ID :
+ hi2s->ErrorCallback = HAL_I2S_ErrorCallback; /* Legacy weak ErrorCallback */
+ break;
+
+ case HAL_I2S_MSPINIT_CB_ID :
+ hi2s->MspInitCallback = HAL_I2S_MspInit; /* Legacy weak MspInit */
+ break;
+
+ case HAL_I2S_MSPDEINIT_CB_ID :
+ hi2s->MspDeInitCallback = HAL_I2S_MspDeInit; /* Legacy weak MspDeInit */
+ break;
+
+ default :
+ /* Update the error code */
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_I2S_STATE_RESET == hi2s->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_I2S_MSPINIT_CB_ID :
+ hi2s->MspInitCallback = HAL_I2S_MspInit; /* Legacy weak MspInit */
+ break;
+
+ case HAL_I2S_MSPDEINIT_CB_ID :
+ hi2s->MspDeInitCallback = HAL_I2S_MspDeInit; /* Legacy weak MspDeInit */
+ break;
+
+ default :
+ /* Update the error code */
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hi2s);
+ return status;
+}
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
+/**
+ * @}
+ */
+
+/** @defgroup I2S_Exported_Functions_Group2 IO operation functions
+ * @brief Data transfers functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the I2S data
+ transfers.
+
+ (#) There are two modes of transfer:
+ (++) Blocking mode : The communication is performed in the polling mode.
+ The status of all data processing is returned by the same function
+ after finishing transfer.
+ (++) No-Blocking mode : The communication is performed using Interrupts
+ or DMA. These functions return the status of the transfer startup.
+ The end of the data processing will be indicated through the
+ dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when
+ using DMA mode.
+
+ (#) Blocking mode functions are :
+ (++) HAL_I2S_Transmit()
+ (++) HAL_I2S_Receive()
+
+ (#) No-Blocking mode functions with Interrupt are :
+ (++) HAL_I2S_Transmit_IT()
+ (++) HAL_I2S_Receive_IT()
+
+ (#) No-Blocking mode functions with DMA are :
+ (++) HAL_I2S_Transmit_DMA()
+ (++) HAL_I2S_Receive_DMA()
+
+ (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
+ (++) HAL_I2S_TxCpltCallback()
+ (++) HAL_I2S_RxCpltCallback()
+ (++) HAL_I2S_ErrorCallback()
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Transmit an amount of data in blocking mode
+ * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @param pData a 16-bit pointer to data buffer.
+ * @param Size number of data sample to be sent:
+ * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
+ * configuration phase, the Size parameter means the number of 16-bit data length
+ * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
+ * the Size parameter means the number of 24-bit or 32-bit data length.
+ * @param Timeout Timeout duration
+ * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
+ * between Master and Slave(example: audio streaming).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ uint32_t tmpreg_cfgr;
+
+ if ((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
+ if (hi2s->State != HAL_I2S_STATE_READY)
+ {
+ __HAL_UNLOCK(hi2s);
+ return HAL_BUSY;
+ }
+
+ /* Set state and reset error code */
+ hi2s->State = HAL_I2S_STATE_BUSY_TX;
+ hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+ hi2s->pTxBuffPtr = pData;
+
+ tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
+
+ if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B))
+ {
+ hi2s->TxXferSize = (Size << 1U);
+ hi2s->TxXferCount = (Size << 1U);
+ }
+ else
+ {
+ hi2s->TxXferSize = Size;
+ hi2s->TxXferCount = Size;
+ }
+
+ tmpreg_cfgr = hi2s->Instance->I2SCFGR;
+
+ /* Check if the I2S is already enabled */
+ if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
+ {
+ /* Enable I2S peripheral */
+ __HAL_I2S_ENABLE(hi2s);
+ }
+
+ /* Wait until TXE flag is set */
+ if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, SET, Timeout) != HAL_OK)
+ {
+ /* Set the error code */
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
+ hi2s->State = HAL_I2S_STATE_READY;
+ __HAL_UNLOCK(hi2s);
+ return HAL_ERROR;
+ }
+
+ while (hi2s->TxXferCount > 0U)
+ {
+ hi2s->Instance->DR = (*hi2s->pTxBuffPtr);
+ hi2s->pTxBuffPtr++;
+ hi2s->TxXferCount--;
+
+ /* Wait until TXE flag is set */
+ if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, SET, Timeout) != HAL_OK)
+ {
+ /* Set the error code */
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
+ hi2s->State = HAL_I2S_STATE_READY;
+ __HAL_UNLOCK(hi2s);
+ return HAL_ERROR;
+ }
+
+ /* Check if an underrun occurs */
+ if (__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR) == SET)
+ {
+ /* Clear underrun flag */
+ __HAL_I2S_CLEAR_UDRFLAG(hi2s);
+
+ /* Set the error code */
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR);
+ }
+ }
+
+ /* Check if Slave mode is selected */
+ if (((tmpreg_cfgr & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX)
+ || ((tmpreg_cfgr & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_RX))
+ {
+ /* Wait until Busy flag is reset */
+ if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_BSY, RESET, Timeout) != HAL_OK)
+ {
+ /* Set the error code */
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
+ hi2s->State = HAL_I2S_STATE_READY;
+ __HAL_UNLOCK(hi2s);
+ return HAL_ERROR;
+ }
+ }
+
+ hi2s->State = HAL_I2S_STATE_READY;
+ __HAL_UNLOCK(hi2s);
+ return HAL_OK;
+}
+
+/**
+ * @brief Receive an amount of data in blocking mode
+ * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @param pData a 16-bit pointer to data buffer.
+ * @param Size number of data sample to be sent:
+ * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
+ * configuration phase, the Size parameter means the number of 16-bit data length
+ * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
+ * the Size parameter means the number of 24-bit or 32-bit data length.
+ * @param Timeout Timeout duration
+ * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
+ * between Master and Slave(example: audio streaming).
+ * @note In I2S Master Receiver mode, just after enabling the peripheral the clock will be generate
+ * in continuous way and as the I2S is not disabled at the end of the I2S transaction.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ uint32_t tmpreg_cfgr;
+
+ if ((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
+ if (hi2s->State != HAL_I2S_STATE_READY)
+ {
+ __HAL_UNLOCK(hi2s);
+ return HAL_BUSY;
+ }
+
+ /* Set state and reset error code */
+ hi2s->State = HAL_I2S_STATE_BUSY_RX;
+ hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+ hi2s->pRxBuffPtr = pData;
+
+ tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
+
+ if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B))
+ {
+ hi2s->RxXferSize = (Size << 1U);
+ hi2s->RxXferCount = (Size << 1U);
+ }
+ else
+ {
+ hi2s->RxXferSize = Size;
+ hi2s->RxXferCount = Size;
+ }
+
+ /* Check if the I2S is already enabled */
+ if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
+ {
+ /* Enable I2S peripheral */
+ __HAL_I2S_ENABLE(hi2s);
+ }
+
+ /* Check if Master Receiver mode is selected */
+ if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
+ {
+ /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read
+ access to the SPI_SR register. */
+ __HAL_I2S_CLEAR_OVRFLAG(hi2s);
+ }
+
+ /* Receive data */
+ while (hi2s->RxXferCount > 0U)
+ {
+ /* Wait until RXNE flag is set */
+ if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, SET, Timeout) != HAL_OK)
+ {
+ /* Set the error code */
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
+ hi2s->State = HAL_I2S_STATE_READY;
+ __HAL_UNLOCK(hi2s);
+ return HAL_ERROR;
+ }
+
+ (*hi2s->pRxBuffPtr) = (uint16_t)hi2s->Instance->DR;
+ hi2s->pRxBuffPtr++;
+ hi2s->RxXferCount--;
+
+ /* Check if an overrun occurs */
+ if (__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR) == SET)
+ {
+ /* Clear overrun flag */
+ __HAL_I2S_CLEAR_OVRFLAG(hi2s);
+
+ /* Set the error code */
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR);
+ }
+ }
+
+ hi2s->State = HAL_I2S_STATE_READY;
+ __HAL_UNLOCK(hi2s);
+ return HAL_OK;
+}
+
+/**
+ * @brief Transmit an amount of data in non-blocking mode with Interrupt
+ * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @param pData a 16-bit pointer to data buffer.
+ * @param Size number of data sample to be sent:
+ * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
+ * configuration phase, the Size parameter means the number of 16-bit data length
+ * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
+ * the Size parameter means the number of 24-bit or 32-bit data length.
+ * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
+ * between Master and Slave(example: audio streaming).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
+{
+ uint32_t tmpreg_cfgr;
+
+ if ((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
+ if (hi2s->State != HAL_I2S_STATE_READY)
+ {
+ __HAL_UNLOCK(hi2s);
+ return HAL_BUSY;
+ }
+
+ /* Set state and reset error code */
+ hi2s->State = HAL_I2S_STATE_BUSY_TX;
+ hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+ hi2s->pTxBuffPtr = pData;
+
+ tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
+
+ if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B))
+ {
+ hi2s->TxXferSize = (Size << 1U);
+ hi2s->TxXferCount = (Size << 1U);
+ }
+ else
+ {
+ hi2s->TxXferSize = Size;
+ hi2s->TxXferCount = Size;
+ }
+
+ /* Enable TXE and ERR interrupt */
+ __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
+
+ /* Check if the I2S is already enabled */
+ if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
+ {
+ /* Enable I2S peripheral */
+ __HAL_I2S_ENABLE(hi2s);
+ }
+
+ __HAL_UNLOCK(hi2s);
+ return HAL_OK;
+}
+
+/**
+ * @brief Receive an amount of data in non-blocking mode with Interrupt
+ * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @param pData a 16-bit pointer to the Receive data buffer.
+ * @param Size number of data sample to be sent:
+ * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
+ * configuration phase, the Size parameter means the number of 16-bit data length
+ * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
+ * the Size parameter means the number of 24-bit or 32-bit data length.
+ * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
+ * between Master and Slave(example: audio streaming).
+ * @note It is recommended to use DMA for the I2S receiver to avoid de-synchronization
+ * between Master and Slave otherwise the I2S interrupt should be optimized.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
+{
+ uint32_t tmpreg_cfgr;
+
+ if ((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
+ if (hi2s->State != HAL_I2S_STATE_READY)
+ {
+ __HAL_UNLOCK(hi2s);
+ return HAL_BUSY;
+ }
+
+ /* Set state and reset error code */
+ hi2s->State = HAL_I2S_STATE_BUSY_RX;
+ hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+ hi2s->pRxBuffPtr = pData;
+
+ tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
+
+ if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B))
+ {
+ hi2s->RxXferSize = (Size << 1U);
+ hi2s->RxXferCount = (Size << 1U);
+ }
+ else
+ {
+ hi2s->RxXferSize = Size;
+ hi2s->RxXferCount = Size;
+ }
+
+ /* Enable RXNE and ERR interrupt */
+ __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
+
+ /* Check if the I2S is already enabled */
+ if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
+ {
+ /* Enable I2S peripheral */
+ __HAL_I2S_ENABLE(hi2s);
+ }
+
+ __HAL_UNLOCK(hi2s);
+ return HAL_OK;
+}
+
+/**
+ * @brief Transmit an amount of data in non-blocking mode with DMA
+ * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @param pData a 16-bit pointer to the Transmit data buffer.
+ * @param Size number of data sample to be sent:
+ * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
+ * configuration phase, the Size parameter means the number of 16-bit data length
+ * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
+ * the Size parameter means the number of 24-bit or 32-bit data length.
+ * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
+ * between Master and Slave(example: audio streaming).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
+{
+ uint32_t tmpreg_cfgr;
+
+ if ((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
+ if (hi2s->State != HAL_I2S_STATE_READY)
+ {
+ __HAL_UNLOCK(hi2s);
+ return HAL_BUSY;
+ }
+
+ /* Set state and reset error code */
+ hi2s->State = HAL_I2S_STATE_BUSY_TX;
+ hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+ hi2s->pTxBuffPtr = pData;
+
+ tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
+
+ if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B))
+ {
+ hi2s->TxXferSize = (Size << 1U);
+ hi2s->TxXferCount = (Size << 1U);
+ }
+ else
+ {
+ hi2s->TxXferSize = Size;
+ hi2s->TxXferCount = Size;
+ }
+
+ /* Set the I2S Tx DMA Half transfer complete callback */
+ hi2s->hdmatx->XferHalfCpltCallback = I2S_DMATxHalfCplt;
+
+ /* Set the I2S Tx DMA transfer complete callback */
+ hi2s->hdmatx->XferCpltCallback = I2S_DMATxCplt;
+
+ /* Set the DMA error callback */
+ hi2s->hdmatx->XferErrorCallback = I2S_DMAError;
+
+ /* Enable the Tx DMA Stream/Channel */
+ if (HAL_OK != HAL_DMA_Start_IT(hi2s->hdmatx,
+ (uint32_t)hi2s->pTxBuffPtr,
+ (uint32_t)&hi2s->Instance->DR,
+ hi2s->TxXferSize))
+ {
+ /* Update SPI error code */
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
+ hi2s->State = HAL_I2S_STATE_READY;
+
+ __HAL_UNLOCK(hi2s);
+ return HAL_ERROR;
+ }
+
+ /* Check if the I2S is already enabled */
+ if (HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
+ {
+ /* Enable I2S peripheral */
+ __HAL_I2S_ENABLE(hi2s);
+ }
+
+ /* Check if the I2S Tx request is already enabled */
+ if (HAL_IS_BIT_CLR(hi2s->Instance->CR2, SPI_CR2_TXDMAEN))
+ {
+ /* Enable Tx DMA Request */
+ SET_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
+ }
+
+ __HAL_UNLOCK(hi2s);
+ return HAL_OK;
+}
+
+/**
+ * @brief Receive an amount of data in non-blocking mode with DMA
+ * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @param pData a 16-bit pointer to the Receive data buffer.
+ * @param Size number of data sample to be sent:
+ * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
+ * configuration phase, the Size parameter means the number of 16-bit data length
+ * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
+ * the Size parameter means the number of 24-bit or 32-bit data length.
+ * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
+ * between Master and Slave(example: audio streaming).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
+{
+ uint32_t tmpreg_cfgr;
+
+ if ((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
+ if (hi2s->State != HAL_I2S_STATE_READY)
+ {
+ __HAL_UNLOCK(hi2s);
+ return HAL_BUSY;
+ }
+
+ /* Set state and reset error code */
+ hi2s->State = HAL_I2S_STATE_BUSY_RX;
+ hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+ hi2s->pRxBuffPtr = pData;
+
+ tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
+
+ if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B))
+ {
+ hi2s->RxXferSize = (Size << 1U);
+ hi2s->RxXferCount = (Size << 1U);
+ }
+ else
+ {
+ hi2s->RxXferSize = Size;
+ hi2s->RxXferCount = Size;
+ }
+
+ /* Set the I2S Rx DMA Half transfer complete callback */
+ hi2s->hdmarx->XferHalfCpltCallback = I2S_DMARxHalfCplt;
+
+ /* Set the I2S Rx DMA transfer complete callback */
+ hi2s->hdmarx->XferCpltCallback = I2S_DMARxCplt;
+
+ /* Set the DMA error callback */
+ hi2s->hdmarx->XferErrorCallback = I2S_DMAError;
+
+ /* Check if Master Receiver mode is selected */
+ if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
+ {
+ /* Clear the Overrun Flag by a read operation to the SPI_DR register followed by a read
+ access to the SPI_SR register. */
+ __HAL_I2S_CLEAR_OVRFLAG(hi2s);
+ }
+
+ /* Enable the Rx DMA Stream/Channel */
+ if (HAL_OK != HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, (uint32_t)hi2s->pRxBuffPtr,
+ hi2s->RxXferSize))
+ {
+ /* Update SPI error code */
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
+ hi2s->State = HAL_I2S_STATE_READY;
+
+ __HAL_UNLOCK(hi2s);
+ return HAL_ERROR;
+ }
+
+ /* Check if the I2S is already enabled */
+ if (HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
+ {
+ /* Enable I2S peripheral */
+ __HAL_I2S_ENABLE(hi2s);
+ }
+
+ /* Check if the I2S Rx request is already enabled */
+ if (HAL_IS_BIT_CLR(hi2s->Instance->CR2, SPI_CR2_RXDMAEN))
+ {
+ /* Enable Rx DMA Request */
+ SET_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
+ }
+
+ __HAL_UNLOCK(hi2s);
+ return HAL_OK;
+}
+
+/**
+ * @brief Pauses the audio DMA Stream/Channel playing from the Media.
+ * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s)
+{
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
+ if (hi2s->State == HAL_I2S_STATE_BUSY_TX)
+ {
+ /* Disable the I2S DMA Tx request */
+ CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
+ }
+ else if (hi2s->State == HAL_I2S_STATE_BUSY_RX)
+ {
+ /* Disable the I2S DMA Rx request */
+ CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
+ }
+ else
+ {
+ /* nothing to do */
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Resumes the audio DMA Stream/Channel playing from the Media.
+ * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s)
+{
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
+ if (hi2s->State == HAL_I2S_STATE_BUSY_TX)
+ {
+ /* Enable the I2S DMA Tx request */
+ SET_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
+ }
+ else if (hi2s->State == HAL_I2S_STATE_BUSY_RX)
+ {
+ /* Enable the I2S DMA Rx request */
+ SET_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
+ }
+ else
+ {
+ /* nothing to do */
+ }
+
+ /* If the I2S peripheral is still not enabled, enable it */
+ if (HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
+ {
+ /* Enable I2S peripheral */
+ __HAL_I2S_ENABLE(hi2s);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the audio DMA Stream/Channel playing from the Media.
+ * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s)
+{
+ HAL_StatusTypeDef errorcode = HAL_OK;
+ /* The Lock is not implemented on this API to allow the user application
+ to call the HAL SPI API under callbacks HAL_I2S_TxCpltCallback() or HAL_I2S_RxCpltCallback()
+ when calling HAL_DMA_Abort() API the DMA TX or RX Transfer complete interrupt is generated
+ and the correspond call back is executed HAL_I2S_TxCpltCallback() or HAL_I2S_RxCpltCallback()
+ */
+
+ if ((hi2s->Init.Mode == I2S_MODE_MASTER_TX) || (hi2s->Init.Mode == I2S_MODE_SLAVE_TX))
+ {
+ /* Abort the I2S DMA tx Stream/Channel */
+ if (hi2s->hdmatx != NULL)
+ {
+ /* Disable the I2S DMA tx Stream/Channel */
+ if (HAL_OK != HAL_DMA_Abort(hi2s->hdmatx))
+ {
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
+ errorcode = HAL_ERROR;
+ }
+ }
+
+ /* Wait until TXE flag is set */
+ if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, SET, I2S_TIMEOUT_FLAG) != HAL_OK)
+ {
+ /* Set the error code */
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
+ hi2s->State = HAL_I2S_STATE_READY;
+ errorcode = HAL_ERROR;
+ }
+
+ /* Wait until BSY flag is Reset */
+ if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_BSY, RESET, I2S_TIMEOUT_FLAG) != HAL_OK)
+ {
+ /* Set the error code */
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
+ hi2s->State = HAL_I2S_STATE_READY;
+ errorcode = HAL_ERROR;
+ }
+
+ /* Disable I2S peripheral */
+ __HAL_I2S_DISABLE(hi2s);
+
+ /* Clear UDR flag */
+ __HAL_I2S_CLEAR_UDRFLAG(hi2s);
+
+ /* Disable the I2S Tx DMA requests */
+ CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
+
+ }
+
+ else if ((hi2s->Init.Mode == I2S_MODE_MASTER_RX) || (hi2s->Init.Mode == I2S_MODE_SLAVE_RX))
+ {
+ /* Abort the I2S DMA rx Stream/Channel */
+ if (hi2s->hdmarx != NULL)
+ {
+ /* Disable the I2S DMA rx Stream/Channel */
+ if (HAL_OK != HAL_DMA_Abort(hi2s->hdmarx))
+ {
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
+ errorcode = HAL_ERROR;
+ }
+ }
+
+ /* Disable I2S peripheral */
+ __HAL_I2S_DISABLE(hi2s);
+
+ /* Clear OVR flag */
+ __HAL_I2S_CLEAR_OVRFLAG(hi2s);
+
+ /* Disable the I2S Rx DMA request */
+ CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
+
+ if (hi2s->Init.Mode == I2S_MODE_SLAVE_RX)
+ {
+ /* Set the error code */
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_BUSY_LINE_RX);
+
+ /* Set the I2S State ready */
+ hi2s->State = HAL_I2S_STATE_READY;
+ errorcode = HAL_ERROR;
+ }
+ else
+ {
+ /* Read DR to Flush RX Data */
+ READ_REG((hi2s->Instance)->DR);
+ }
+ }
+
+ hi2s->State = HAL_I2S_STATE_READY;
+
+ return errorcode;
+}
+
+/**
+ * @brief This function handles I2S interrupt request.
+ * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval None
+ */
+void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s)
+{
+ uint32_t itsource = hi2s->Instance->CR2;
+ uint32_t itflag = hi2s->Instance->SR;
+
+ /* I2S in mode Receiver ------------------------------------------------*/
+ if ((I2S_CHECK_FLAG(itflag, I2S_FLAG_OVR) == RESET) &&
+ (I2S_CHECK_FLAG(itflag, I2S_FLAG_RXNE) != RESET) && (I2S_CHECK_IT_SOURCE(itsource, I2S_IT_RXNE) != RESET))
+ {
+ I2S_Receive_IT(hi2s);
+ return;
+ }
+
+ /* I2S in mode Tramitter -----------------------------------------------*/
+ if ((I2S_CHECK_FLAG(itflag, I2S_FLAG_TXE) != RESET) && (I2S_CHECK_IT_SOURCE(itsource, I2S_IT_TXE) != RESET))
+ {
+ I2S_Transmit_IT(hi2s);
+ return;
+ }
+
+ /* I2S interrupt error -------------------------------------------------*/
+ if (I2S_CHECK_IT_SOURCE(itsource, I2S_IT_ERR) != RESET)
+ {
+ /* I2S Overrun error interrupt occurred ---------------------------------*/
+ if (I2S_CHECK_FLAG(itflag, I2S_FLAG_OVR) != RESET)
+ {
+ /* Disable RXNE and ERR interrupt */
+ __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
+
+ /* Set the error code and execute error callback*/
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR);
+ }
+
+ /* I2S Underrun error interrupt occurred --------------------------------*/
+ if (I2S_CHECK_FLAG(itflag, I2S_FLAG_UDR) != RESET)
+ {
+ /* Disable TXE and ERR interrupt */
+ __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
+
+ /* Set the error code and execute error callback*/
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR);
+ }
+
+ /* Set the I2S State ready */
+ hi2s->State = HAL_I2S_STATE_READY;
+
+ /* Call user error callback */
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
+ hi2s->ErrorCallback(hi2s);
+#else
+ HAL_I2S_ErrorCallback(hi2s);
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
+ }
+}
+
+/**
+ * @brief Tx Transfer Half completed callbacks
+ * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval None
+ */
+__weak void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2s);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_I2S_TxHalfCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Tx Transfer completed callbacks
+ * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval None
+ */
+__weak void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2s);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_I2S_TxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Rx Transfer half completed callbacks
+ * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval None
+ */
+__weak void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2s);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_I2S_RxHalfCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Rx Transfer completed callbacks
+ * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval None
+ */
+__weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2s);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_I2S_RxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief I2S error callbacks
+ * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval None
+ */
+__weak void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2s);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_I2S_ErrorCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup I2S_Exported_Functions_Group3 Peripheral State and Errors functions
+ * @brief Peripheral State functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral State and Errors functions #####
+ ===============================================================================
+ [..]
+ This subsection permits to get in run-time the status of the peripheral
+ and the data flow.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the I2S state
+ * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval HAL state
+ */
+HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s)
+{
+ return hi2s->State;
+}
+
+/**
+ * @brief Return the I2S error code
+ * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval I2S Error Code
+ */
+uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s)
+{
+ return hi2s->ErrorCode;
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup I2S_Private_Functions I2S Private Functions
+ * @{
+ */
+/**
+ * @brief DMA I2S transmit process complete callback
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma)
+{
+ I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
+
+ /* if DMA is configured in DMA_NORMAL Mode */
+ if (hdma->Init.Mode == DMA_NORMAL)
+ {
+ /* Disable Tx DMA Request */
+ CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
+
+ hi2s->TxXferCount = 0U;
+ hi2s->State = HAL_I2S_STATE_READY;
+ }
+ /* Call user Tx complete callback */
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
+ hi2s->TxCpltCallback(hi2s);
+#else
+ HAL_I2S_TxCpltCallback(hi2s);
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief DMA I2S transmit process half complete callback
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+ I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
+
+ /* Call user Tx half complete callback */
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
+ hi2s->TxHalfCpltCallback(hi2s);
+#else
+ HAL_I2S_TxHalfCpltCallback(hi2s);
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief DMA I2S receive process complete callback
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma)
+{
+ I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
+
+ /* if DMA is configured in DMA_NORMAL Mode */
+ if (hdma->Init.Mode == DMA_NORMAL)
+ {
+ /* Disable Rx DMA Request */
+ CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
+ hi2s->RxXferCount = 0U;
+ hi2s->State = HAL_I2S_STATE_READY;
+ }
+ /* Call user Rx complete callback */
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
+ hi2s->RxCpltCallback(hi2s);
+#else
+ HAL_I2S_RxCpltCallback(hi2s);
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief DMA I2S receive process half complete callback
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+ I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
+
+ /* Call user Rx half complete callback */
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
+ hi2s->RxHalfCpltCallback(hi2s);
+#else
+ HAL_I2S_RxHalfCpltCallback(hi2s);
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief DMA I2S communication error callback
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void I2S_DMAError(DMA_HandleTypeDef *hdma)
+{
+ I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
+
+ /* Disable Rx and Tx DMA Request */
+ CLEAR_BIT(hi2s->Instance->CR2, (SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN));
+ hi2s->TxXferCount = 0U;
+ hi2s->RxXferCount = 0U;
+
+ hi2s->State = HAL_I2S_STATE_READY;
+
+ /* Set the error code and execute error callback*/
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
+ /* Call user error callback */
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
+ hi2s->ErrorCallback(hi2s);
+#else
+ HAL_I2S_ErrorCallback(hi2s);
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief Transmit an amount of data in non-blocking mode with Interrupt
+ * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval None
+ */
+static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s)
+{
+ /* Transmit data */
+ hi2s->Instance->DR = (*hi2s->pTxBuffPtr);
+ hi2s->pTxBuffPtr++;
+ hi2s->TxXferCount--;
+
+ if (hi2s->TxXferCount == 0U)
+ {
+ /* Disable TXE and ERR interrupt */
+ __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
+
+ hi2s->State = HAL_I2S_STATE_READY;
+ /* Call user Tx complete callback */
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
+ hi2s->TxCpltCallback(hi2s);
+#else
+ HAL_I2S_TxCpltCallback(hi2s);
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
+ }
+}
+
+/**
+ * @brief Receive an amount of data in non-blocking mode with Interrupt
+ * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval None
+ */
+static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s)
+{
+ /* Receive data */
+ (*hi2s->pRxBuffPtr) = (uint16_t)hi2s->Instance->DR;
+ hi2s->pRxBuffPtr++;
+ hi2s->RxXferCount--;
+
+ if (hi2s->RxXferCount == 0U)
+ {
+ /* Disable RXNE and ERR interrupt */
+ __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
+
+ hi2s->State = HAL_I2S_STATE_READY;
+ /* Call user Rx complete callback */
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
+ hi2s->RxCpltCallback(hi2s);
+#else
+ HAL_I2S_RxCpltCallback(hi2s);
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
+ }
+}
+
+/**
+ * @brief This function handles I2S Communication Timeout.
+ * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @param Flag Flag checked
+ * @param State Value of the flag expected
+ * @param Timeout Duration of the timeout
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, FlagStatus State,
+ uint32_t Timeout)
+{
+ uint32_t tickstart;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait until flag is set to status*/
+ while (((__HAL_I2S_GET_FLAG(hi2s, Flag)) ? SET : RESET) != State)
+ {
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U))
+ {
+ /* Set the I2S State ready */
+ hi2s->State = HAL_I2S_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* SPI_I2S_SUPPORT */
+
+#endif /* HAL_I2S_MODULE_ENABLED */
diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_irda.c b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_irda.c
new file mode 100644
index 0000000000..9297299dd9
--- /dev/null
+++ b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_irda.c
@@ -0,0 +1,3010 @@
+/**
+ ******************************************************************************
+ * @file stm32c0xx_hal_irda.c
+ * @author MCD Application Team
+ * @brief IRDA HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the IrDA (Infrared Data Association) Peripheral
+ * (IRDA)
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral State and Errors functions
+ * + Peripheral Control functions
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2022 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ The IRDA HAL driver can be used as follows:
+
+ (#) Declare a IRDA_HandleTypeDef handle structure (eg. IRDA_HandleTypeDef hirda).
+ (#) Initialize the IRDA low level resources by implementing the HAL_IRDA_MspInit() API
+ in setting the associated USART or UART in IRDA mode:
+ (++) Enable the USARTx/UARTx interface clock.
+ (++) USARTx/UARTx pins configuration:
+ (+++) Enable the clock for the USARTx/UARTx GPIOs.
+ (+++) Configure these USARTx/UARTx pins (TX as alternate function pull-up, RX as alternate function Input).
+ (++) NVIC configuration if you need to use interrupt process (HAL_IRDA_Transmit_IT()
+ and HAL_IRDA_Receive_IT() APIs):
+ (+++) Configure the USARTx/UARTx interrupt priority.
+ (+++) Enable the NVIC USARTx/UARTx IRQ handle.
+ (+++) The specific IRDA interrupts (Transmission complete interrupt,
+ RXNE interrupt and Error Interrupts) will be managed using the macros
+ __HAL_IRDA_ENABLE_IT() and __HAL_IRDA_DISABLE_IT() inside the transmit and receive process.
+
+ (++) DMA Configuration if you need to use DMA process (HAL_IRDA_Transmit_DMA()
+ and HAL_IRDA_Receive_DMA() APIs):
+ (+++) Declare a DMA handle structure for the Tx/Rx channel.
+ (+++) Enable the DMAx interface clock.
+ (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
+ (+++) Configure the DMA Tx/Rx channel.
+ (+++) Associate the initialized DMA handle to the IRDA DMA Tx/Rx handle.
+ (+++) Configure the priority and enable the NVIC for the transfer
+ complete interrupt on the DMA Tx/Rx channel.
+
+ (#) Program the Baud Rate, Word Length and Parity and Mode(Receiver/Transmitter),
+ the normal or low power mode and the clock prescaler in the hirda handle Init structure.
+
+ (#) Initialize the IRDA registers by calling the HAL_IRDA_Init() API:
+ (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
+ by calling the customized HAL_IRDA_MspInit() API.
+
+ -@@- The specific IRDA interrupts (Transmission complete interrupt,
+ RXNE interrupt and Error Interrupts) will be managed using the macros
+ __HAL_IRDA_ENABLE_IT() and __HAL_IRDA_DISABLE_IT() inside the transmit and receive process.
+
+ (#) Three operation modes are available within this driver :
+
+ *** Polling mode IO operation ***
+ =================================
+ [..]
+ (+) Send an amount of data in blocking mode using HAL_IRDA_Transmit()
+ (+) Receive an amount of data in blocking mode using HAL_IRDA_Receive()
+
+ *** Interrupt mode IO operation ***
+ ===================================
+ [..]
+ (+) Send an amount of data in non-blocking mode using HAL_IRDA_Transmit_IT()
+ (+) At transmission end of transfer HAL_IRDA_TxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_IRDA_TxCpltCallback()
+ (+) Receive an amount of data in non-blocking mode using HAL_IRDA_Receive_IT()
+ (+) At reception end of transfer HAL_IRDA_RxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_IRDA_RxCpltCallback()
+ (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_IRDA_ErrorCallback()
+
+ *** DMA mode IO operation ***
+ ==============================
+ [..]
+ (+) Send an amount of data in non-blocking mode (DMA) using HAL_IRDA_Transmit_DMA()
+ (+) At transmission half of transfer HAL_IRDA_TxHalfCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_IRDA_TxHalfCpltCallback()
+ (+) At transmission end of transfer HAL_IRDA_TxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_IRDA_TxCpltCallback()
+ (+) Receive an amount of data in non-blocking mode (DMA) using HAL_IRDA_Receive_DMA()
+ (+) At reception half of transfer HAL_IRDA_RxHalfCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_IRDA_RxHalfCpltCallback()
+ (+) At reception end of transfer HAL_IRDA_RxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_IRDA_RxCpltCallback()
+ (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_IRDA_ErrorCallback()
+
+ *** IRDA HAL driver macros list ***
+ ====================================
+ [..]
+ Below the list of most used macros in IRDA HAL driver.
+
+ (+) __HAL_IRDA_ENABLE: Enable the IRDA peripheral
+ (+) __HAL_IRDA_DISABLE: Disable the IRDA peripheral
+ (+) __HAL_IRDA_GET_FLAG : Check whether the specified IRDA flag is set or not
+ (+) __HAL_IRDA_CLEAR_FLAG : Clear the specified IRDA pending flag
+ (+) __HAL_IRDA_ENABLE_IT: Enable the specified IRDA interrupt
+ (+) __HAL_IRDA_DISABLE_IT: Disable the specified IRDA interrupt
+ (+) __HAL_IRDA_GET_IT_SOURCE: Check whether or not the specified IRDA interrupt is enabled
+
+ [..]
+ (@) You can refer to the IRDA HAL driver header file for more useful macros
+
+ ##### Callback registration #####
+ ==================================
+
+ [..]
+ The compilation define USE_HAL_IRDA_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+
+ [..]
+ Use Function HAL_IRDA_RegisterCallback() to register a user callback.
+ Function HAL_IRDA_RegisterCallback() allows to register following callbacks:
+ (+) TxHalfCpltCallback : Tx Half Complete Callback.
+ (+) TxCpltCallback : Tx Complete Callback.
+ (+) RxHalfCpltCallback : Rx Half Complete Callback.
+ (+) RxCpltCallback : Rx Complete Callback.
+ (+) ErrorCallback : Error Callback.
+ (+) AbortCpltCallback : Abort Complete Callback.
+ (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
+ (+) AbortReceiveCpltCallback : Abort Receive Complete Callback.
+ (+) MspInitCallback : IRDA MspInit.
+ (+) MspDeInitCallback : IRDA MspDeInit.
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+ [..]
+ Use function HAL_IRDA_UnRegisterCallback() to reset a callback to the default
+ weak (surcharged) function.
+ HAL_IRDA_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+ and the Callback ID.
+ This function allows to reset following callbacks:
+ (+) TxHalfCpltCallback : Tx Half Complete Callback.
+ (+) TxCpltCallback : Tx Complete Callback.
+ (+) RxHalfCpltCallback : Rx Half Complete Callback.
+ (+) RxCpltCallback : Rx Complete Callback.
+ (+) ErrorCallback : Error Callback.
+ (+) AbortCpltCallback : Abort Complete Callback.
+ (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
+ (+) AbortReceiveCpltCallback : Abort Receive Complete Callback.
+ (+) MspInitCallback : IRDA MspInit.
+ (+) MspDeInitCallback : IRDA MspDeInit.
+
+ [..]
+ By default, after the HAL_IRDA_Init() and when the state is HAL_IRDA_STATE_RESET
+ all callbacks are set to the corresponding weak (surcharged) functions:
+ examples HAL_IRDA_TxCpltCallback(), HAL_IRDA_RxHalfCpltCallback().
+ Exception done for MspInit and MspDeInit functions that are respectively
+ reset to the legacy weak (surcharged) functions in the HAL_IRDA_Init()
+ and HAL_IRDA_DeInit() only when these callbacks are null (not registered beforehand).
+ If not, MspInit or MspDeInit are not null, the HAL_IRDA_Init() and HAL_IRDA_DeInit()
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
+
+ [..]
+ Callbacks can be registered/unregistered in HAL_IRDA_STATE_READY state only.
+ Exception done MspInit/MspDeInit that can be registered/unregistered
+ in HAL_IRDA_STATE_READY or HAL_IRDA_STATE_RESET state, thus registered (user)
+ MspInit/DeInit callbacks can be used during the Init/DeInit.
+ In that case first register the MspInit/MspDeInit user callbacks
+ using HAL_IRDA_RegisterCallback() before calling HAL_IRDA_DeInit()
+ or HAL_IRDA_Init() function.
+
+ [..]
+ When The compilation define USE_HAL_IRDA_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registration feature is not available
+ and weak (surcharged) callbacks are used.
+
+ @endverbatim
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32c0xx_hal.h"
+
+/** @addtogroup STM32C0xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup IRDA IRDA
+ * @brief HAL IRDA module driver
+ * @{
+ */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup IRDA_Private_Constants IRDA Private Constants
+ * @{
+ */
+#define IRDA_TEACK_REACK_TIMEOUT 1000U /*!< IRDA TX or RX enable acknowledge time-out value */
+
+#define IRDA_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE \
+ | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE)) /*!< UART or USART CR1 fields of parameters set by IRDA_SetConfig API */
+
+#define USART_BRR_MIN 0x10U /*!< USART BRR minimum authorized value */
+
+#define USART_BRR_MAX 0x0000FFFFU /*!< USART BRR maximum authorized value */
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup IRDA_Private_Macros IRDA Private Macros
+ * @{
+ */
+/** @brief BRR division operation to set BRR register in 16-bit oversampling mode.
+ * @param __PCLK__ IRDA clock source.
+ * @param __BAUD__ Baud rate set by the user.
+ * @param __PRESCALER__ IRDA clock prescaler value.
+ * @retval Division result
+ */
+#define IRDA_DIV_SAMPLING16(__PCLK__, __BAUD__, __PRESCALER__) ((((__PCLK__)/IRDAPrescTable[(__PRESCALER__)])\
+ + ((__BAUD__)/2U)) / (__BAUD__))
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup IRDA_Private_Functions
+ * @{
+ */
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+void IRDA_InitCallbacksToDefault(IRDA_HandleTypeDef *hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
+static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda);
+static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda);
+static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status,
+ uint32_t Tickstart, uint32_t Timeout);
+static void IRDA_EndTxTransfer(IRDA_HandleTypeDef *hirda);
+static void IRDA_EndRxTransfer(IRDA_HandleTypeDef *hirda);
+static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma);
+static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma);
+static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
+static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma);
+static void IRDA_DMAError(DMA_HandleTypeDef *hdma);
+static void IRDA_DMAAbortOnError(DMA_HandleTypeDef *hdma);
+static void IRDA_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
+static void IRDA_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
+static void IRDA_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
+static void IRDA_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
+static void IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda);
+static void IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda);
+static void IRDA_Receive_IT(IRDA_HandleTypeDef *hirda);
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup IRDA_Exported_Functions IRDA Exported Functions
+ * @{
+ */
+
+/** @defgroup IRDA_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Initialization and Configuration functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to initialize the USARTx
+ in asynchronous IRDA mode.
+ (+) For the asynchronous mode only these parameters can be configured:
+ (++) Baud Rate
+ (++) Word Length
+ (++) Parity: If the parity is enabled, then the MSB bit of the data written
+ in the data register is transmitted but is changed by the parity bit.
+ (++) Power mode
+ (++) Prescaler setting
+ (++) Receiver/transmitter modes
+
+ [..]
+ The HAL_IRDA_Init() API follows the USART asynchronous configuration procedures
+ (details for the procedures are available in reference manual).
+
+@endverbatim
+
+ Depending on the frame length defined by the M1 and M0 bits (7-bit,
+ 8-bit or 9-bit), the possible IRDA frame formats are listed in the
+ following table.
+
+ Table 1. IRDA frame format.
+ +-----------------------------------------------------------------------+
+ | M1 bit | M0 bit | PCE bit | IRDA frame |
+ |---------|---------|-----------|---------------------------------------|
+ | 0 | 0 | 0 | | SB | 8 bit data | STB | |
+ |---------|---------|-----------|---------------------------------------|
+ | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | |
+ |---------|---------|-----------|---------------------------------------|
+ | 0 | 1 | 0 | | SB | 9 bit data | STB | |
+ |---------|---------|-----------|---------------------------------------|
+ | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | |
+ |---------|---------|-----------|---------------------------------------|
+ | 1 | 0 | 0 | | SB | 7 bit data | STB | |
+ |---------|---------|-----------|---------------------------------------|
+ | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | |
+ +-----------------------------------------------------------------------+
+
+ * @{
+ */
+
+/**
+ * @brief Initialize the IRDA mode according to the specified
+ * parameters in the IRDA_InitTypeDef and initialize the associated handle.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda)
+{
+ /* Check the IRDA handle allocation */
+ if (hirda == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the USART/UART associated to the IRDA handle */
+ assert_param(IS_IRDA_INSTANCE(hirda->Instance));
+
+ if (hirda->gState == HAL_IRDA_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hirda->Lock = HAL_UNLOCKED;
+
+#if USE_HAL_IRDA_REGISTER_CALLBACKS == 1
+ IRDA_InitCallbacksToDefault(hirda);
+
+ if (hirda->MspInitCallback == NULL)
+ {
+ hirda->MspInitCallback = HAL_IRDA_MspInit;
+ }
+
+ /* Init the low level hardware */
+ hirda->MspInitCallback(hirda);
+#else
+ /* Init the low level hardware : GPIO, CLOCK */
+ HAL_IRDA_MspInit(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
+ }
+
+ hirda->gState = HAL_IRDA_STATE_BUSY;
+
+ /* Disable the Peripheral to update the configuration registers */
+ __HAL_IRDA_DISABLE(hirda);
+
+ /* Set the IRDA Communication parameters */
+ if (IRDA_SetConfig(hirda) == HAL_ERROR)
+ {
+ return HAL_ERROR;
+ }
+
+ /* In IRDA mode, the following bits must be kept cleared:
+ - LINEN, STOP and CLKEN bits in the USART_CR2 register,
+ - SCEN and HDSEL bits in the USART_CR3 register.*/
+ CLEAR_BIT(hirda->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP));
+ CLEAR_BIT(hirda->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL));
+
+ /* set the UART/USART in IRDA mode */
+ hirda->Instance->CR3 |= USART_CR3_IREN;
+
+ /* Enable the Peripheral */
+ __HAL_IRDA_ENABLE(hirda);
+
+ /* TEACK and/or REACK to check before moving hirda->gState and hirda->RxState to Ready */
+ return (IRDA_CheckIdleState(hirda));
+}
+
+/**
+ * @brief DeInitialize the IRDA peripheral.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda)
+{
+ /* Check the IRDA handle allocation */
+ if (hirda == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the USART/UART associated to the IRDA handle */
+ assert_param(IS_IRDA_INSTANCE(hirda->Instance));
+
+ hirda->gState = HAL_IRDA_STATE_BUSY;
+
+ /* DeInit the low level hardware */
+#if USE_HAL_IRDA_REGISTER_CALLBACKS == 1
+ if (hirda->MspDeInitCallback == NULL)
+ {
+ hirda->MspDeInitCallback = HAL_IRDA_MspDeInit;
+ }
+ /* DeInit the low level hardware */
+ hirda->MspDeInitCallback(hirda);
+#else
+ HAL_IRDA_MspDeInit(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
+ /* Disable the Peripheral */
+ __HAL_IRDA_DISABLE(hirda);
+
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+ hirda->gState = HAL_IRDA_STATE_RESET;
+ hirda->RxState = HAL_IRDA_STATE_RESET;
+
+ /* Process Unlock */
+ __HAL_UNLOCK(hirda);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initialize the IRDA MSP.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval None
+ */
+__weak void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hirda);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_IRDA_MspInit can be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitialize the IRDA MSP.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval None
+ */
+__weak void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hirda);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_IRDA_MspDeInit can be implemented in the user file
+ */
+}
+
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a User IRDA Callback
+ * To be used instead of the weak predefined callback
+ * @param hirda irda handle
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_IRDA_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
+ * @arg @ref HAL_IRDA_TX_COMPLETE_CB_ID Tx Complete Callback ID
+ * @arg @ref HAL_IRDA_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
+ * @arg @ref HAL_IRDA_RX_COMPLETE_CB_ID Rx Complete Callback ID
+ * @arg @ref HAL_IRDA_ERROR_CB_ID Error Callback ID
+ * @arg @ref HAL_IRDA_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
+ * @arg @ref HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
+ * @arg @ref HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
+ * @arg @ref HAL_IRDA_MSPINIT_CB_ID MspInit Callback ID
+ * @arg @ref HAL_IRDA_MSPDEINIT_CB_ID MspDeInit Callback ID
+ * @param pCallback pointer to the Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IRDA_RegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID,
+ pIRDA_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+ /* Process locked */
+ __HAL_LOCK(hirda);
+
+ if (hirda->gState == HAL_IRDA_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+ case HAL_IRDA_TX_HALFCOMPLETE_CB_ID :
+ hirda->TxHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_IRDA_TX_COMPLETE_CB_ID :
+ hirda->TxCpltCallback = pCallback;
+ break;
+
+ case HAL_IRDA_RX_HALFCOMPLETE_CB_ID :
+ hirda->RxHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_IRDA_RX_COMPLETE_CB_ID :
+ hirda->RxCpltCallback = pCallback;
+ break;
+
+ case HAL_IRDA_ERROR_CB_ID :
+ hirda->ErrorCallback = pCallback;
+ break;
+
+ case HAL_IRDA_ABORT_COMPLETE_CB_ID :
+ hirda->AbortCpltCallback = pCallback;
+ break;
+
+ case HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID :
+ hirda->AbortTransmitCpltCallback = pCallback;
+ break;
+
+ case HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID :
+ hirda->AbortReceiveCpltCallback = pCallback;
+ break;
+
+ case HAL_IRDA_MSPINIT_CB_ID :
+ hirda->MspInitCallback = pCallback;
+ break;
+
+ case HAL_IRDA_MSPDEINIT_CB_ID :
+ hirda->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (hirda->gState == HAL_IRDA_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_IRDA_MSPINIT_CB_ID :
+ hirda->MspInitCallback = pCallback;
+ break;
+
+ case HAL_IRDA_MSPDEINIT_CB_ID :
+ hirda->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hirda);
+
+ return status;
+}
+
+/**
+ * @brief Unregister an IRDA callback
+ * IRDA callback is redirected to the weak predefined callback
+ * @param hirda irda handle
+ * @param CallbackID ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_IRDA_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
+ * @arg @ref HAL_IRDA_TX_COMPLETE_CB_ID Tx Complete Callback ID
+ * @arg @ref HAL_IRDA_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
+ * @arg @ref HAL_IRDA_RX_COMPLETE_CB_ID Rx Complete Callback ID
+ * @arg @ref HAL_IRDA_ERROR_CB_ID Error Callback ID
+ * @arg @ref HAL_IRDA_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
+ * @arg @ref HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
+ * @arg @ref HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
+ * @arg @ref HAL_IRDA_MSPINIT_CB_ID MspInit Callback ID
+ * @arg @ref HAL_IRDA_MSPDEINIT_CB_ID MspDeInit Callback ID
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hirda);
+
+ if (HAL_IRDA_STATE_READY == hirda->gState)
+ {
+ switch (CallbackID)
+ {
+ case HAL_IRDA_TX_HALFCOMPLETE_CB_ID :
+ hirda->TxHalfCpltCallback = HAL_IRDA_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
+ break;
+
+ case HAL_IRDA_TX_COMPLETE_CB_ID :
+ hirda->TxCpltCallback = HAL_IRDA_TxCpltCallback; /* Legacy weak TxCpltCallback */
+ break;
+
+ case HAL_IRDA_RX_HALFCOMPLETE_CB_ID :
+ hirda->RxHalfCpltCallback = HAL_IRDA_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
+ break;
+
+ case HAL_IRDA_RX_COMPLETE_CB_ID :
+ hirda->RxCpltCallback = HAL_IRDA_RxCpltCallback; /* Legacy weak RxCpltCallback */
+ break;
+
+ case HAL_IRDA_ERROR_CB_ID :
+ hirda->ErrorCallback = HAL_IRDA_ErrorCallback; /* Legacy weak ErrorCallback */
+ break;
+
+ case HAL_IRDA_ABORT_COMPLETE_CB_ID :
+ hirda->AbortCpltCallback = HAL_IRDA_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
+ break;
+
+ case HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID :
+ hirda->AbortTransmitCpltCallback = HAL_IRDA_AbortTransmitCpltCallback; /* Legacy weak
+ AbortTransmitCpltCallback */
+ break;
+
+ case HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID :
+ hirda->AbortReceiveCpltCallback = HAL_IRDA_AbortReceiveCpltCallback; /* Legacy weak
+ AbortReceiveCpltCallback */
+ break;
+
+ case HAL_IRDA_MSPINIT_CB_ID :
+ hirda->MspInitCallback = HAL_IRDA_MspInit; /* Legacy weak MspInitCallback */
+ break;
+
+ case HAL_IRDA_MSPDEINIT_CB_ID :
+ hirda->MspDeInitCallback = HAL_IRDA_MspDeInit; /* Legacy weak MspDeInitCallback */
+ break;
+
+ default :
+ /* Update the error code */
+ hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_IRDA_STATE_RESET == hirda->gState)
+ {
+ switch (CallbackID)
+ {
+ case HAL_IRDA_MSPINIT_CB_ID :
+ hirda->MspInitCallback = HAL_IRDA_MspInit;
+ break;
+
+ case HAL_IRDA_MSPDEINIT_CB_ID :
+ hirda->MspDeInitCallback = HAL_IRDA_MspDeInit;
+ break;
+
+ default :
+ /* Update the error code */
+ hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hirda);
+
+ return status;
+}
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+/** @defgroup IRDA_Exported_Functions_Group2 IO operation functions
+ * @brief IRDA Transmit and Receive functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the IRDA data transfers.
+
+ [..]
+ IrDA is a half duplex communication protocol. If the Transmitter is busy, any data
+ on the IrDA receive line will be ignored by the IrDA decoder and if the Receiver
+ is busy, data on the TX from the USART to IrDA will not be encoded by IrDA.
+ While receiving data, transmission should be avoided as the data to be transmitted
+ could be corrupted.
+
+ [..]
+ (#) There are two modes of transfer:
+ (++) Blocking mode: the communication is performed in polling mode.
+ The HAL status of all data processing is returned by the same function
+ after finishing transfer.
+ (++) Non-Blocking mode: the communication is performed using Interrupts
+ or DMA, these API's return the HAL status.
+ The end of the data processing will be indicated through the
+ dedicated IRDA IRQ when using Interrupt mode or the DMA IRQ when
+ using DMA mode.
+ The HAL_IRDA_TxCpltCallback(), HAL_IRDA_RxCpltCallback() user callbacks
+ will be executed respectively at the end of the Transmit or Receive process
+ The HAL_IRDA_ErrorCallback() user callback will be executed when a communication error is detected
+
+ (#) Blocking mode APIs are :
+ (++) HAL_IRDA_Transmit()
+ (++) HAL_IRDA_Receive()
+
+ (#) Non Blocking mode APIs with Interrupt are :
+ (++) HAL_IRDA_Transmit_IT()
+ (++) HAL_IRDA_Receive_IT()
+ (++) HAL_IRDA_IRQHandler()
+
+ (#) Non Blocking mode functions with DMA are :
+ (++) HAL_IRDA_Transmit_DMA()
+ (++) HAL_IRDA_Receive_DMA()
+ (++) HAL_IRDA_DMAPause()
+ (++) HAL_IRDA_DMAResume()
+ (++) HAL_IRDA_DMAStop()
+
+ (#) A set of Transfer Complete Callbacks are provided in Non Blocking mode:
+ (++) HAL_IRDA_TxHalfCpltCallback()
+ (++) HAL_IRDA_TxCpltCallback()
+ (++) HAL_IRDA_RxHalfCpltCallback()
+ (++) HAL_IRDA_RxCpltCallback()
+ (++) HAL_IRDA_ErrorCallback()
+
+ (#) Non-Blocking mode transfers could be aborted using Abort API's :
+ (++) HAL_IRDA_Abort()
+ (++) HAL_IRDA_AbortTransmit()
+ (++) HAL_IRDA_AbortReceive()
+ (++) HAL_IRDA_Abort_IT()
+ (++) HAL_IRDA_AbortTransmit_IT()
+ (++) HAL_IRDA_AbortReceive_IT()
+
+ (#) For Abort services based on interrupts (HAL_IRDA_Abortxxx_IT), a set of Abort Complete Callbacks are provided:
+ (++) HAL_IRDA_AbortCpltCallback()
+ (++) HAL_IRDA_AbortTransmitCpltCallback()
+ (++) HAL_IRDA_AbortReceiveCpltCallback()
+
+ (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
+ Errors are handled as follows :
+ (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
+ to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error
+ in Interrupt mode reception .
+ Received character is then retrieved and stored in Rx buffer, Error code is set to allow user
+ to identify error type, and HAL_IRDA_ErrorCallback() user callback is executed.
+ Transfer is kept ongoing on IRDA side.
+ If user wants to abort it, Abort services should be called by user.
+ (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
+ This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
+ Error code is set to allow user to identify error type, and
+ HAL_IRDA_ErrorCallback() user callback is executed.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Send an amount of data in blocking mode.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the sent data is handled as a set of u16. In this case, Size must reflect the number
+ * of u16 available through pData.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @param pData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be sent.
+ * @param Timeout Specify timeout value.
+ * @retval HAL status
+ */
+/**
+ * @note When IRDA parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits)
+ * (as sent data will be handled using u16 pointer cast). Depending on compilation chain,
+ * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData.
+ */
+HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ const uint8_t *pdata8bits;
+ const uint16_t *pdata16bits;
+ uint32_t tickstart;
+
+ /* Check that a Tx process is not already ongoing */
+ if (hirda->gState == HAL_IRDA_STATE_READY)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter
+ should be aligned on a u16 frontier, as data to be filled into TDR will be
+ handled through a u16 cast. */
+ if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
+ {
+ if ((((uint32_t)pData) & 1U) != 0U)
+ {
+ return HAL_ERROR;
+ }
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hirda);
+
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+ hirda->gState = HAL_IRDA_STATE_BUSY_TX;
+
+ /* Init tickstart for timeout management */
+ tickstart = HAL_GetTick();
+
+ hirda->TxXferSize = Size;
+ hirda->TxXferCount = Size;
+
+ /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */
+ if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
+ {
+ pdata8bits = NULL;
+ pdata16bits = (const uint16_t *) pData; /* Derogation R.11.3 */
+ }
+ else
+ {
+ pdata8bits = pData;
+ pdata16bits = NULL;
+ }
+
+ while (hirda->TxXferCount > 0U)
+ {
+ hirda->TxXferCount--;
+
+ if (IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ if (pdata8bits == NULL)
+ {
+ hirda->Instance->TDR = (uint16_t)(*pdata16bits & 0x01FFU);
+ pdata16bits++;
+ }
+ else
+ {
+ hirda->Instance->TDR = (uint8_t)(*pdata8bits & 0xFFU);
+ pdata8bits++;
+ }
+ }
+
+ if (IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* At end of Tx process, restore hirda->gState to Ready */
+ hirda->gState = HAL_IRDA_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hirda);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in blocking mode.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the received data is handled as a set of u16. In this case, Size must reflect the number
+ * of u16 available through pData.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @param pData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be received.
+ * @param Timeout Specify timeout value.
+ * @retval HAL status
+ */
+/**
+ * @note When IRDA parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits)
+ * (as received data will be handled using u16 pointer cast). Depending on compilation chain,
+ * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData.
+ */
+HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ uint8_t *pdata8bits;
+ uint16_t *pdata16bits;
+ uint16_t uhMask;
+ uint32_t tickstart;
+
+ /* Check that a Rx process is not already ongoing */
+ if (hirda->RxState == HAL_IRDA_STATE_READY)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter
+ should be aligned on a u16 frontier, as data to be received from RDR will be
+ handled through a u16 cast. */
+ if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
+ {
+ if ((((uint32_t)pData) & 1U) != 0U)
+ {
+ return HAL_ERROR;
+ }
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hirda);
+
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+ hirda->RxState = HAL_IRDA_STATE_BUSY_RX;
+
+ /* Init tickstart for timeout management */
+ tickstart = HAL_GetTick();
+
+ hirda->RxXferSize = Size;
+ hirda->RxXferCount = Size;
+
+ /* Computation of the mask to apply to RDR register
+ of the UART associated to the IRDA */
+ IRDA_MASK_COMPUTATION(hirda);
+ uhMask = hirda->Mask;
+
+ /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */
+ if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
+ {
+ pdata8bits = NULL;
+ pdata16bits = (uint16_t *) pData; /* Derogation R.11.3 */
+ }
+ else
+ {
+ pdata8bits = pData;
+ pdata16bits = NULL;
+ }
+
+ /* Check data remaining to be received */
+ while (hirda->RxXferCount > 0U)
+ {
+ hirda->RxXferCount--;
+
+ if (IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ if (pdata8bits == NULL)
+ {
+ *pdata16bits = (uint16_t)(hirda->Instance->RDR & uhMask);
+ pdata16bits++;
+ }
+ else
+ {
+ *pdata8bits = (uint8_t)(hirda->Instance->RDR & (uint8_t)uhMask);
+ pdata8bits++;
+ }
+ }
+
+ /* At end of Rx process, restore hirda->RxState to Ready */
+ hirda->RxState = HAL_IRDA_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hirda);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Send an amount of data in interrupt mode.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the sent data is handled as a set of u16. In this case, Size must reflect the number
+ * of u16 available through pData.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @param pData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be sent.
+ * @retval HAL status
+ */
+/**
+ * @note When IRDA parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits)
+ * (as sent data will be handled using u16 pointer cast). Depending on compilation chain,
+ * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData.
+ */
+HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size)
+{
+ /* Check that a Tx process is not already ongoing */
+ if (hirda->gState == HAL_IRDA_STATE_READY)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter
+ should be aligned on a u16 frontier, as data to be filled into TDR will be
+ handled through a u16 cast. */
+ if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
+ {
+ if ((((uint32_t)pData) & 1U) != 0U)
+ {
+ return HAL_ERROR;
+ }
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hirda);
+
+ hirda->pTxBuffPtr = pData;
+ hirda->TxXferSize = Size;
+ hirda->TxXferCount = Size;
+
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+ hirda->gState = HAL_IRDA_STATE_BUSY_TX;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hirda);
+
+ /* Enable the IRDA Transmit Data Register Empty Interrupt */
+ SET_BIT(hirda->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in interrupt mode.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the received data is handled as a set of u16. In this case, Size must reflect the number
+ * of u16 available through pData.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @param pData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be received.
+ * @retval HAL status
+ */
+/**
+ * @note When IRDA parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits)
+ * (as received data will be handled using u16 pointer cast). Depending on compilation chain,
+ * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData.
+ */
+HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
+{
+ /* Check that a Rx process is not already ongoing */
+ if (hirda->RxState == HAL_IRDA_STATE_READY)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter
+ should be aligned on a u16 frontier, as data to be received from RDR will be
+ handled through a u16 cast. */
+ if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
+ {
+ if ((((uint32_t)pData) & 1U) != 0U)
+ {
+ return HAL_ERROR;
+ }
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hirda);
+
+ hirda->pRxBuffPtr = pData;
+ hirda->RxXferSize = Size;
+ hirda->RxXferCount = Size;
+
+ /* Computation of the mask to apply to the RDR register
+ of the UART associated to the IRDA */
+ IRDA_MASK_COMPUTATION(hirda);
+
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+ hirda->RxState = HAL_IRDA_STATE_BUSY_RX;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hirda);
+
+ if (hirda->Init.Parity != IRDA_PARITY_NONE)
+ {
+ /* Enable the IRDA Parity Error and Data Register not empty Interrupts */
+ SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE);
+ }
+ else
+ {
+ /* Enable the IRDA Data Register not empty Interrupts */
+ SET_BIT(hirda->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
+ }
+
+ /* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
+ SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Send an amount of data in DMA mode.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the sent data is handled as a set of u16. In this case, Size must reflect the number
+ * of u16 available through pData.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @param pData pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be sent.
+ * @retval HAL status
+ */
+/**
+ * @note When IRDA parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits)
+ * (as sent data will be handled by DMA from halfword frontier). Depending on compilation chain,
+ * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData.
+ */
+HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size)
+{
+ /* Check that a Tx process is not already ongoing */
+ if (hirda->gState == HAL_IRDA_STATE_READY)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter
+ should be aligned on a u16 frontier, as data copy into TDR will be
+ handled by DMA from a u16 frontier. */
+ if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
+ {
+ if ((((uint32_t)pData) & 1U) != 0U)
+ {
+ return HAL_ERROR;
+ }
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hirda);
+
+ hirda->pTxBuffPtr = pData;
+ hirda->TxXferSize = Size;
+ hirda->TxXferCount = Size;
+
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+ hirda->gState = HAL_IRDA_STATE_BUSY_TX;
+
+ /* Set the IRDA DMA transfer complete callback */
+ hirda->hdmatx->XferCpltCallback = IRDA_DMATransmitCplt;
+
+ /* Set the IRDA DMA half transfer complete callback */
+ hirda->hdmatx->XferHalfCpltCallback = IRDA_DMATransmitHalfCplt;
+
+ /* Set the DMA error callback */
+ hirda->hdmatx->XferErrorCallback = IRDA_DMAError;
+
+ /* Set the DMA abort callback */
+ hirda->hdmatx->XferAbortCallback = NULL;
+
+ /* Enable the IRDA transmit DMA channel */
+ if (HAL_DMA_Start_IT(hirda->hdmatx, (uint32_t)hirda->pTxBuffPtr, (uint32_t)&hirda->Instance->TDR, Size) == HAL_OK)
+ {
+ /* Clear the TC flag in the ICR register */
+ __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_TCF);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hirda);
+
+ /* Enable the DMA transfer for transmit request by setting the DMAT bit
+ in the USART CR3 register */
+ SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
+
+ return HAL_OK;
+ }
+ else
+ {
+ /* Set error code to DMA */
+ hirda->ErrorCode = HAL_IRDA_ERROR_DMA;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hirda);
+
+ /* Restore hirda->gState to ready */
+ hirda->gState = HAL_IRDA_STATE_READY;
+
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in DMA mode.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the received data is handled as a set of u16. In this case, Size must reflect the number
+ * of u16 available through pData.
+ * @note When the IRDA parity is enabled (PCE = 1), the received data contains
+ * the parity bit (MSB position).
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @param pData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be received.
+ * @retval HAL status
+ */
+/**
+ * @note When IRDA parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits)
+ * (as received data will be handled by DMA from halfword frontier). Depending on compilation chain,
+ * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData.
+ */
+HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
+{
+ /* Check that a Rx process is not already ongoing */
+ if (hirda->RxState == HAL_IRDA_STATE_READY)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter
+ should be aligned on a u16 frontier, as data copy from RDR will be
+ handled by DMA from a u16 frontier. */
+ if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
+ {
+ if ((((uint32_t)pData) & 1U) != 0U)
+ {
+ return HAL_ERROR;
+ }
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hirda);
+
+ hirda->pRxBuffPtr = pData;
+ hirda->RxXferSize = Size;
+
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+ hirda->RxState = HAL_IRDA_STATE_BUSY_RX;
+
+ /* Set the IRDA DMA transfer complete callback */
+ hirda->hdmarx->XferCpltCallback = IRDA_DMAReceiveCplt;
+
+ /* Set the IRDA DMA half transfer complete callback */
+ hirda->hdmarx->XferHalfCpltCallback = IRDA_DMAReceiveHalfCplt;
+
+ /* Set the DMA error callback */
+ hirda->hdmarx->XferErrorCallback = IRDA_DMAError;
+
+ /* Set the DMA abort callback */
+ hirda->hdmarx->XferAbortCallback = NULL;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(hirda->hdmarx, (uint32_t)&hirda->Instance->RDR, (uint32_t)hirda->pRxBuffPtr, Size) == HAL_OK)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hirda);
+
+ if (hirda->Init.Parity != IRDA_PARITY_NONE)
+ {
+ /* Enable the UART Parity Error Interrupt */
+ SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
+ }
+
+ /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
+ SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+ /* Enable the DMA transfer for the receiver request by setting the DMAR bit
+ in the USART CR3 register */
+ SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+
+ return HAL_OK;
+ }
+ else
+ {
+ /* Set error code to DMA */
+ hirda->ErrorCode = HAL_IRDA_ERROR_DMA;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hirda);
+
+ /* Restore hirda->RxState to ready */
+ hirda->RxState = HAL_IRDA_STATE_READY;
+
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+
+/**
+ * @brief Pause the DMA Transfer.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda)
+{
+ /* Process Locked */
+ __HAL_LOCK(hirda);
+
+ if (hirda->gState == HAL_IRDA_STATE_BUSY_TX)
+ {
+ if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
+ {
+ /* Disable the IRDA DMA Tx request */
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
+ }
+ }
+ if (hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
+ {
+ if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
+ {
+ /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+ /* Disable the IRDA DMA Rx request */
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+ }
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hirda);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Resume the DMA Transfer.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda)
+{
+ /* Process Locked */
+ __HAL_LOCK(hirda);
+
+ if (hirda->gState == HAL_IRDA_STATE_BUSY_TX)
+ {
+ /* Enable the IRDA DMA Tx request */
+ SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
+ }
+ if (hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
+ {
+ /* Clear the Overrun flag before resuming the Rx transfer*/
+ __HAL_IRDA_CLEAR_OREFLAG(hirda);
+
+ /* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */
+ if (hirda->Init.Parity != IRDA_PARITY_NONE)
+ {
+ SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
+ }
+ SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+ /* Enable the IRDA DMA Rx request */
+ SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hirda);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Stop the DMA Transfer.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda)
+{
+ /* The Lock is not implemented on this API to allow the user application
+ to call the HAL IRDA API under callbacks HAL_IRDA_TxCpltCallback() / HAL_IRDA_RxCpltCallback() /
+ HAL_IRDA_TxHalfCpltCallback / HAL_IRDA_RxHalfCpltCallback:
+ indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete
+ interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of
+ the stream and the corresponding call back is executed. */
+
+ /* Stop IRDA DMA Tx request if ongoing */
+ if (hirda->gState == HAL_IRDA_STATE_BUSY_TX)
+ {
+ if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
+ {
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the IRDA DMA Tx channel */
+ if (hirda->hdmatx != NULL)
+ {
+ if (HAL_DMA_Abort(hirda->hdmatx) != HAL_OK)
+ {
+ if (HAL_DMA_GetError(hirda->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
+ {
+ /* Set error code to DMA */
+ hirda->ErrorCode = HAL_IRDA_ERROR_DMA;
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ IRDA_EndTxTransfer(hirda);
+ }
+ }
+
+ /* Stop IRDA DMA Rx request if ongoing */
+ if (hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
+ {
+ if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the IRDA DMA Rx channel */
+ if (hirda->hdmarx != NULL)
+ {
+ if (HAL_DMA_Abort(hirda->hdmarx) != HAL_OK)
+ {
+ if (HAL_DMA_GetError(hirda->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
+ {
+ /* Set error code to DMA */
+ hirda->ErrorCode = HAL_IRDA_ERROR_DMA;
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ IRDA_EndRxTransfer(hirda);
+ }
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing transfers (blocking mode).
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable IRDA Interrupts (Tx and Rx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda)
+{
+ /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | \
+ USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+ /* Disable the IRDA DMA Tx request if enabled */
+ if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
+ {
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the IRDA DMA Tx channel : use blocking DMA Abort API (no callback) */
+ if (hirda->hdmatx != NULL)
+ {
+ /* Set the IRDA DMA Abort callback to Null.
+ No call back execution at end of DMA abort procedure */
+ hirda->hdmatx->XferAbortCallback = NULL;
+
+ if (HAL_DMA_Abort(hirda->hdmatx) != HAL_OK)
+ {
+ if (HAL_DMA_GetError(hirda->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
+ {
+ /* Set error code to DMA */
+ hirda->ErrorCode = HAL_IRDA_ERROR_DMA;
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+
+ /* Disable the IRDA DMA Rx request if enabled */
+ if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the IRDA DMA Rx channel : use blocking DMA Abort API (no callback) */
+ if (hirda->hdmarx != NULL)
+ {
+ /* Set the IRDA DMA Abort callback to Null.
+ No call back execution at end of DMA abort procedure */
+ hirda->hdmarx->XferAbortCallback = NULL;
+
+ if (HAL_DMA_Abort(hirda->hdmarx) != HAL_OK)
+ {
+ if (HAL_DMA_GetError(hirda->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
+ {
+ /* Set error code to DMA */
+ hirda->ErrorCode = HAL_IRDA_ERROR_DMA;
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+
+ /* Reset Tx and Rx transfer counters */
+ hirda->TxXferCount = 0U;
+ hirda->RxXferCount = 0U;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
+
+ /* Restore hirda->gState and hirda->RxState to Ready */
+ hirda->gState = HAL_IRDA_STATE_READY;
+ hirda->RxState = HAL_IRDA_STATE_READY;
+
+ /* Reset Handle ErrorCode to No Error */
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing Transmit transfer (blocking mode).
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable IRDA Interrupts (Tx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda)
+{
+ /* Disable TXEIE and TCIE interrupts */
+ CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
+
+ /* Disable the IRDA DMA Tx request if enabled */
+ if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
+ {
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the IRDA DMA Tx channel : use blocking DMA Abort API (no callback) */
+ if (hirda->hdmatx != NULL)
+ {
+ /* Set the IRDA DMA Abort callback to Null.
+ No call back execution at end of DMA abort procedure */
+ hirda->hdmatx->XferAbortCallback = NULL;
+
+ if (HAL_DMA_Abort(hirda->hdmatx) != HAL_OK)
+ {
+ if (HAL_DMA_GetError(hirda->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
+ {
+ /* Set error code to DMA */
+ hirda->ErrorCode = HAL_IRDA_ERROR_DMA;
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+
+ /* Reset Tx transfer counter */
+ hirda->TxXferCount = 0U;
+
+ /* Restore hirda->gState to Ready */
+ hirda->gState = HAL_IRDA_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing Receive transfer (blocking mode).
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable IRDA Interrupts (Rx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IRDA_AbortReceive(IRDA_HandleTypeDef *hirda)
+{
+ /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+ /* Disable the IRDA DMA Rx request if enabled */
+ if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the IRDA DMA Rx channel : use blocking DMA Abort API (no callback) */
+ if (hirda->hdmarx != NULL)
+ {
+ /* Set the IRDA DMA Abort callback to Null.
+ No call back execution at end of DMA abort procedure */
+ hirda->hdmarx->XferAbortCallback = NULL;
+
+ if (HAL_DMA_Abort(hirda->hdmarx) != HAL_OK)
+ {
+ if (HAL_DMA_GetError(hirda->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
+ {
+ /* Set error code to DMA */
+ hirda->ErrorCode = HAL_IRDA_ERROR_DMA;
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+
+ /* Reset Rx transfer counter */
+ hirda->RxXferCount = 0U;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
+
+ /* Restore hirda->RxState to Ready */
+ hirda->RxState = HAL_IRDA_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing transfers (Interrupt mode).
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable IRDA Interrupts (Tx and Rx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * - At abort completion, call user abort complete callback
+ * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
+ * considered as completed only when user abort complete callback is executed (not when exiting function).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda)
+{
+ uint32_t abortcplt = 1U;
+
+ /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | \
+ USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+ /* If DMA Tx and/or DMA Rx Handles are associated to IRDA Handle, DMA Abort complete callbacks should be initialised
+ before any call to DMA Abort functions */
+ /* DMA Tx Handle is valid */
+ if (hirda->hdmatx != NULL)
+ {
+ /* Set DMA Abort Complete callback if IRDA DMA Tx request if enabled.
+ Otherwise, set it to NULL */
+ if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
+ {
+ hirda->hdmatx->XferAbortCallback = IRDA_DMATxAbortCallback;
+ }
+ else
+ {
+ hirda->hdmatx->XferAbortCallback = NULL;
+ }
+ }
+ /* DMA Rx Handle is valid */
+ if (hirda->hdmarx != NULL)
+ {
+ /* Set DMA Abort Complete callback if IRDA DMA Rx request if enabled.
+ Otherwise, set it to NULL */
+ if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
+ {
+ hirda->hdmarx->XferAbortCallback = IRDA_DMARxAbortCallback;
+ }
+ else
+ {
+ hirda->hdmarx->XferAbortCallback = NULL;
+ }
+ }
+
+ /* Disable the IRDA DMA Tx request if enabled */
+ if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
+ {
+ /* Disable DMA Tx at UART level */
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the IRDA DMA Tx channel : use non blocking DMA Abort API (callback) */
+ if (hirda->hdmatx != NULL)
+ {
+ /* IRDA Tx DMA Abort callback has already been initialised :
+ will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
+
+ /* Abort DMA TX */
+ if (HAL_DMA_Abort_IT(hirda->hdmatx) != HAL_OK)
+ {
+ hirda->hdmatx->XferAbortCallback = NULL;
+ }
+ else
+ {
+ abortcplt = 0U;
+ }
+ }
+ }
+
+ /* Disable the IRDA DMA Rx request if enabled */
+ if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the IRDA DMA Rx channel : use non blocking DMA Abort API (callback) */
+ if (hirda->hdmarx != NULL)
+ {
+ /* IRDA Rx DMA Abort callback has already been initialised :
+ will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
+
+ /* Abort DMA RX */
+ if (HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK)
+ {
+ hirda->hdmarx->XferAbortCallback = NULL;
+ abortcplt = 1U;
+ }
+ else
+ {
+ abortcplt = 0U;
+ }
+ }
+ }
+
+ /* if no DMA abort complete callback execution is required => call user Abort Complete callback */
+ if (abortcplt == 1U)
+ {
+ /* Reset Tx and Rx transfer counters */
+ hirda->TxXferCount = 0U;
+ hirda->RxXferCount = 0U;
+
+ /* Reset errorCode */
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
+
+ /* Restore hirda->gState and hirda->RxState to Ready */
+ hirda->gState = HAL_IRDA_STATE_READY;
+ hirda->RxState = HAL_IRDA_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort complete callback */
+ hirda->AbortCpltCallback(hirda);
+#else
+ /* Call legacy weak Abort complete callback */
+ HAL_IRDA_AbortCpltCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing Transmit transfer (Interrupt mode).
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable IRDA Interrupts (Tx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * - At abort completion, call user abort complete callback
+ * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
+ * considered as completed only when user abort complete callback is executed (not when exiting function).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda)
+{
+ /* Disable TXEIE and TCIE interrupts */
+ CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
+
+ /* Disable the IRDA DMA Tx request if enabled */
+ if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
+ {
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the IRDA DMA Tx channel : use non blocking DMA Abort API (callback) */
+ if (hirda->hdmatx != NULL)
+ {
+ /* Set the IRDA DMA Abort callback :
+ will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
+ hirda->hdmatx->XferAbortCallback = IRDA_DMATxOnlyAbortCallback;
+
+ /* Abort DMA TX */
+ if (HAL_DMA_Abort_IT(hirda->hdmatx) != HAL_OK)
+ {
+ /* Call Directly hirda->hdmatx->XferAbortCallback function in case of error */
+ hirda->hdmatx->XferAbortCallback(hirda->hdmatx);
+ }
+ }
+ else
+ {
+ /* Reset Tx transfer counter */
+ hirda->TxXferCount = 0U;
+
+ /* Restore hirda->gState to Ready */
+ hirda->gState = HAL_IRDA_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Transmit Complete Callback */
+ hirda->AbortTransmitCpltCallback(hirda);
+#else
+ /* Call legacy weak Abort Transmit Complete Callback */
+ HAL_IRDA_AbortTransmitCpltCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
+ }
+ }
+ else
+ {
+ /* Reset Tx transfer counter */
+ hirda->TxXferCount = 0U;
+
+ /* Restore hirda->gState to Ready */
+ hirda->gState = HAL_IRDA_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Transmit Complete Callback */
+ hirda->AbortTransmitCpltCallback(hirda);
+#else
+ /* Call legacy weak Abort Transmit Complete Callback */
+ HAL_IRDA_AbortTransmitCpltCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing Receive transfer (Interrupt mode).
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable IRDA Interrupts (Rx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * - At abort completion, call user abort complete callback
+ * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
+ * considered as completed only when user abort complete callback is executed (not when exiting function).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda)
+{
+ /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+ /* Disable the IRDA DMA Rx request if enabled */
+ if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the IRDA DMA Rx channel : use non blocking DMA Abort API (callback) */
+ if (hirda->hdmarx != NULL)
+ {
+ /* Set the IRDA DMA Abort callback :
+ will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
+ hirda->hdmarx->XferAbortCallback = IRDA_DMARxOnlyAbortCallback;
+
+ /* Abort DMA RX */
+ if (HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK)
+ {
+ /* Call Directly hirda->hdmarx->XferAbortCallback function in case of error */
+ hirda->hdmarx->XferAbortCallback(hirda->hdmarx);
+ }
+ }
+ else
+ {
+ /* Reset Rx transfer counter */
+ hirda->RxXferCount = 0U;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
+
+ /* Restore hirda->RxState to Ready */
+ hirda->RxState = HAL_IRDA_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Receive Complete Callback */
+ hirda->AbortReceiveCpltCallback(hirda);
+#else
+ /* Call legacy weak Abort Receive Complete Callback */
+ HAL_IRDA_AbortReceiveCpltCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
+ }
+ }
+ else
+ {
+ /* Reset Rx transfer counter */
+ hirda->RxXferCount = 0U;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
+
+ /* Restore hirda->RxState to Ready */
+ hirda->RxState = HAL_IRDA_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Receive Complete Callback */
+ hirda->AbortReceiveCpltCallback(hirda);
+#else
+ /* Call legacy weak Abort Receive Complete Callback */
+ HAL_IRDA_AbortReceiveCpltCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle IRDA interrupt request.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval None
+ */
+void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda)
+{
+ uint32_t isrflags = READ_REG(hirda->Instance->ISR);
+ uint32_t cr1its = READ_REG(hirda->Instance->CR1);
+ uint32_t cr3its;
+ uint32_t errorflags;
+ uint32_t errorcode;
+
+ /* If no error occurs */
+ errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE));
+ if (errorflags == 0U)
+ {
+ /* IRDA in mode Receiver ---------------------------------------------------*/
+ if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) && ((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U))
+ {
+ IRDA_Receive_IT(hirda);
+ return;
+ }
+ }
+
+ /* If some errors occur */
+ cr3its = READ_REG(hirda->Instance->CR3);
+ if ((errorflags != 0U)
+ && (((cr3its & USART_CR3_EIE) != 0U)
+ || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)) != 0U)))
+ {
+ /* IRDA parity error interrupt occurred -------------------------------------*/
+ if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
+ {
+ __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_PEF);
+
+ hirda->ErrorCode |= HAL_IRDA_ERROR_PE;
+ }
+
+ /* IRDA frame error interrupt occurred --------------------------------------*/
+ if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
+ {
+ __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_FEF);
+
+ hirda->ErrorCode |= HAL_IRDA_ERROR_FE;
+ }
+
+ /* IRDA noise error interrupt occurred --------------------------------------*/
+ if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
+ {
+ __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_NEF);
+
+ hirda->ErrorCode |= HAL_IRDA_ERROR_NE;
+ }
+
+ /* IRDA Over-Run interrupt occurred -----------------------------------------*/
+ if (((isrflags & USART_ISR_ORE) != 0U) &&
+ (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) || ((cr3its & USART_CR3_EIE) != 0U)))
+ {
+ __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_OREF);
+
+ hirda->ErrorCode |= HAL_IRDA_ERROR_ORE;
+ }
+
+ /* Call IRDA Error Call back function if need be --------------------------*/
+ if (hirda->ErrorCode != HAL_IRDA_ERROR_NONE)
+ {
+ /* IRDA in mode Receiver ---------------------------------------------------*/
+ if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) && ((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U))
+ {
+ IRDA_Receive_IT(hirda);
+ }
+
+ /* If Overrun error occurs, or if any error occurs in DMA mode reception,
+ consider error as blocking */
+ errorcode = hirda->ErrorCode;
+ if ((HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)) ||
+ ((errorcode & HAL_IRDA_ERROR_ORE) != 0U))
+ {
+ /* Blocking error : transfer is aborted
+ Set the IRDA state ready to be able to start again the process,
+ Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
+ IRDA_EndRxTransfer(hirda);
+
+ /* Disable the IRDA DMA Rx request if enabled */
+ if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the IRDA DMA Rx channel */
+ if (hirda->hdmarx != NULL)
+ {
+ /* Set the IRDA DMA Abort callback :
+ will lead to call HAL_IRDA_ErrorCallback() at end of DMA abort procedure */
+ hirda->hdmarx->XferAbortCallback = IRDA_DMAAbortOnError;
+
+ /* Abort DMA RX */
+ if (HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK)
+ {
+ /* Call Directly hirda->hdmarx->XferAbortCallback function in case of error */
+ hirda->hdmarx->XferAbortCallback(hirda->hdmarx);
+ }
+ }
+ else
+ {
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+ /* Call registered user error callback */
+ hirda->ErrorCallback(hirda);
+#else
+ /* Call legacy weak user error callback */
+ HAL_IRDA_ErrorCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
+ }
+ }
+ else
+ {
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+ /* Call registered user error callback */
+ hirda->ErrorCallback(hirda);
+#else
+ /* Call legacy weak user error callback */
+ HAL_IRDA_ErrorCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
+ }
+ }
+ else
+ {
+ /* Non Blocking error : transfer could go on.
+ Error is notified to user through user error callback */
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+ /* Call registered user error callback */
+ hirda->ErrorCallback(hirda);
+#else
+ /* Call legacy weak user error callback */
+ HAL_IRDA_ErrorCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+ }
+ }
+ return;
+
+ } /* End if some error occurs */
+
+ /* IRDA in mode Transmitter ------------------------------------------------*/
+ if (((isrflags & USART_ISR_TXE_TXFNF) != 0U) && ((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U))
+ {
+ IRDA_Transmit_IT(hirda);
+ return;
+ }
+
+ /* IRDA in mode Transmitter (transmission end) -----------------------------*/
+ if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U))
+ {
+ IRDA_EndTransmit_IT(hirda);
+ return;
+ }
+
+}
+
+/**
+ * @brief Tx Transfer completed callback.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval None
+ */
+__weak void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hirda);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_IRDA_TxCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief Tx Half Transfer completed callback.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
+ * @retval None
+ */
+__weak void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hirda);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_IRDA_TxHalfCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief Rx Transfer completed callback.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval None
+ */
+__weak void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hirda);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_IRDA_RxCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief Rx Half Transfer complete callback.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval None
+ */
+__weak void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hirda);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_IRDA_RxHalfCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief IRDA error callback.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval None
+ */
+__weak void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hirda);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_IRDA_ErrorCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief IRDA Abort Complete callback.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval None
+ */
+__weak void HAL_IRDA_AbortCpltCallback(IRDA_HandleTypeDef *hirda)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hirda);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_IRDA_AbortCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief IRDA Abort Complete callback.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval None
+ */
+__weak void HAL_IRDA_AbortTransmitCpltCallback(IRDA_HandleTypeDef *hirda)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hirda);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_IRDA_AbortTransmitCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief IRDA Abort Receive Complete callback.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval None
+ */
+__weak void HAL_IRDA_AbortReceiveCpltCallback(IRDA_HandleTypeDef *hirda)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hirda);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_IRDA_AbortReceiveCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup IRDA_Exported_Functions_Group4 Peripheral State and Error functions
+ * @brief IRDA State and Errors functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral State and Error functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to return the State of IrDA
+ communication process and also return Peripheral Errors occurred during communication process
+ (+) HAL_IRDA_GetState() API can be helpful to check in run-time the state
+ of the IRDA peripheral handle.
+ (+) HAL_IRDA_GetError() checks in run-time errors that could occur during
+ communication.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the IRDA handle state.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval HAL state
+ */
+HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda)
+{
+ /* Return IRDA handle state */
+ uint32_t temp1;
+ uint32_t temp2;
+ temp1 = (uint32_t)hirda->gState;
+ temp2 = (uint32_t)hirda->RxState;
+
+ return (HAL_IRDA_StateTypeDef)(temp1 | temp2);
+}
+
+/**
+ * @brief Return the IRDA handle error code.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval IRDA Error Code
+ */
+uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda)
+{
+ return hirda->ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup IRDA_Private_Functions IRDA Private Functions
+ * @{
+ */
+
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Initialize the callbacks to their default values.
+ * @param hirda IRDA handle.
+ * @retval none
+ */
+void IRDA_InitCallbacksToDefault(IRDA_HandleTypeDef *hirda)
+{
+ /* Init the IRDA Callback settings */
+ hirda->TxHalfCpltCallback = HAL_IRDA_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
+ hirda->TxCpltCallback = HAL_IRDA_TxCpltCallback; /* Legacy weak TxCpltCallback */
+ hirda->RxHalfCpltCallback = HAL_IRDA_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
+ hirda->RxCpltCallback = HAL_IRDA_RxCpltCallback; /* Legacy weak RxCpltCallback */
+ hirda->ErrorCallback = HAL_IRDA_ErrorCallback; /* Legacy weak ErrorCallback */
+ hirda->AbortCpltCallback = HAL_IRDA_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
+ hirda->AbortTransmitCpltCallback = HAL_IRDA_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */
+ hirda->AbortReceiveCpltCallback = HAL_IRDA_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */
+
+}
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
+
+/**
+ * @brief Configure the IRDA peripheral.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda)
+{
+ uint32_t tmpreg;
+ IRDA_ClockSourceTypeDef clocksource;
+ HAL_StatusTypeDef ret = HAL_OK;
+ static const uint16_t IRDAPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U};
+ uint32_t pclk;
+
+ /* Check the communication parameters */
+ assert_param(IS_IRDA_BAUDRATE(hirda->Init.BaudRate));
+ assert_param(IS_IRDA_WORD_LENGTH(hirda->Init.WordLength));
+ assert_param(IS_IRDA_PARITY(hirda->Init.Parity));
+ assert_param(IS_IRDA_TX_RX_MODE(hirda->Init.Mode));
+ assert_param(IS_IRDA_PRESCALER(hirda->Init.Prescaler));
+ assert_param(IS_IRDA_POWERMODE(hirda->Init.PowerMode));
+ assert_param(IS_IRDA_CLOCKPRESCALER(hirda->Init.ClockPrescaler));
+
+ /*-------------------------- USART CR1 Configuration -----------------------*/
+ /* Configure the IRDA Word Length, Parity and transfer Mode:
+ Set the M bits according to hirda->Init.WordLength value
+ Set PCE and PS bits according to hirda->Init.Parity value
+ Set TE and RE bits according to hirda->Init.Mode value */
+ tmpreg = (uint32_t)hirda->Init.WordLength | hirda->Init.Parity | hirda->Init.Mode ;
+
+ MODIFY_REG(hirda->Instance->CR1, IRDA_CR1_FIELDS, tmpreg);
+
+ /*-------------------------- USART CR3 Configuration -----------------------*/
+ MODIFY_REG(hirda->Instance->CR3, USART_CR3_IRLP, hirda->Init.PowerMode);
+
+ /*--------------------- USART clock PRESC Configuration ----------------*/
+ /* Configure
+ * - IRDA Clock Prescaler: set PRESCALER according to hirda->Init.ClockPrescaler value */
+ MODIFY_REG(hirda->Instance->PRESC, USART_PRESC_PRESCALER, hirda->Init.ClockPrescaler);
+
+ /*-------------------------- USART GTPR Configuration ----------------------*/
+ MODIFY_REG(hirda->Instance->GTPR, (uint16_t)USART_GTPR_PSC, (uint16_t)hirda->Init.Prescaler);
+
+ /*-------------------------- USART BRR Configuration -----------------------*/
+ IRDA_GETCLOCKSOURCE(hirda, clocksource);
+ tmpreg = 0U;
+ switch (clocksource)
+ {
+ case IRDA_CLOCKSOURCE_PCLK1:
+ pclk = HAL_RCC_GetPCLK1Freq();
+ tmpreg = (uint32_t)(IRDA_DIV_SAMPLING16(pclk, hirda->Init.BaudRate, hirda->Init.ClockPrescaler));
+ break;
+ case IRDA_CLOCKSOURCE_HSI:
+ pclk = (HSI_VALUE / ((__HAL_RCC_GET_HSIKER_DIVIDER() >> RCC_CR_HSIKERDIV_Pos) + 1U));
+ tmpreg = (uint32_t)(IRDA_DIV_SAMPLING16(pclk, hirda->Init.BaudRate, hirda->Init.ClockPrescaler));
+ break;
+ case IRDA_CLOCKSOURCE_SYSCLK:
+ pclk = HAL_RCC_GetSysClockFreq();
+ tmpreg = (uint32_t)(IRDA_DIV_SAMPLING16(pclk, hirda->Init.BaudRate, hirda->Init.ClockPrescaler));
+ break;
+ case IRDA_CLOCKSOURCE_LSE:
+ tmpreg = (uint32_t)(IRDA_DIV_SAMPLING16((uint32_t)LSE_VALUE, hirda->Init.BaudRate, hirda->Init.ClockPrescaler));
+ break;
+ default:
+ ret = HAL_ERROR;
+ break;
+ }
+
+ /* USARTDIV must be greater than or equal to 0d16 */
+ if ((tmpreg >= USART_BRR_MIN) && (tmpreg <= USART_BRR_MAX))
+ {
+ hirda->Instance->BRR = (uint16_t)tmpreg;
+ }
+ else
+ {
+ ret = HAL_ERROR;
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Check the IRDA Idle State.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda)
+{
+ uint32_t tickstart;
+
+ /* Initialize the IRDA ErrorCode */
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+
+ /* Init tickstart for timeout management */
+ tickstart = HAL_GetTick();
+
+ /* Check if the Transmitter is enabled */
+ if ((hirda->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
+ {
+ /* Wait until TEACK flag is set */
+ if (IRDA_WaitOnFlagUntilTimeout(hirda, USART_ISR_TEACK, RESET, tickstart, IRDA_TEACK_REACK_TIMEOUT) != HAL_OK)
+ {
+ /* Timeout occurred */
+ return HAL_TIMEOUT;
+ }
+ }
+ /* Check if the Receiver is enabled */
+ if ((hirda->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
+ {
+ /* Wait until REACK flag is set */
+ if (IRDA_WaitOnFlagUntilTimeout(hirda, USART_ISR_REACK, RESET, tickstart, IRDA_TEACK_REACK_TIMEOUT) != HAL_OK)
+ {
+ /* Timeout occurred */
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Initialize the IRDA state*/
+ hirda->gState = HAL_IRDA_STATE_READY;
+ hirda->RxState = HAL_IRDA_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hirda);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle IRDA Communication Timeout. It waits
+ * until a flag is no longer in the specified status.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @param Flag Specifies the IRDA flag to check.
+ * @param Status The actual Flag status (SET or RESET)
+ * @param Tickstart Tick start value
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status,
+ uint32_t Tickstart, uint32_t Timeout)
+{
+ /* Wait until flag is set */
+ while ((__HAL_IRDA_GET_FLAG(hirda, Flag) ? SET : RESET) == Status)
+ {
+ /* Check for the Timeout */
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
+ {
+ /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error)
+ interrupts for the interrupt process */
+ CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE));
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+ hirda->gState = HAL_IRDA_STATE_READY;
+ hirda->RxState = HAL_IRDA_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hirda);
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ return HAL_OK;
+}
+
+
+/**
+ * @brief End ongoing Tx transfer on IRDA peripheral (following error detection or Transmit completion).
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval None
+ */
+static void IRDA_EndTxTransfer(IRDA_HandleTypeDef *hirda)
+{
+ /* Disable TXEIE and TCIE interrupts */
+ CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
+
+ /* At end of Tx process, restore hirda->gState to Ready */
+ hirda->gState = HAL_IRDA_STATE_READY;
+}
+
+
+/**
+ * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval None
+ */
+static void IRDA_EndRxTransfer(IRDA_HandleTypeDef *hirda)
+{
+ /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+ /* At end of Rx process, restore hirda->RxState to Ready */
+ hirda->RxState = HAL_IRDA_STATE_READY;
+}
+
+
+/**
+ * @brief DMA IRDA transmit process complete callback.
+ * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma)
+{
+ IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent);
+
+ /* DMA Normal mode */
+ if (HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC))
+ {
+ hirda->TxXferCount = 0U;
+
+ /* Disable the DMA transfer for transmit request by resetting the DMAT bit
+ in the IRDA CR3 register */
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
+
+ /* Enable the IRDA Transmit Complete Interrupt */
+ SET_BIT(hirda->Instance->CR1, USART_CR1_TCIE);
+ }
+ /* DMA Circular mode */
+ else
+ {
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+ /* Call registered Tx complete callback */
+ hirda->TxCpltCallback(hirda);
+#else
+ /* Call legacy weak Tx complete callback */
+ HAL_IRDA_TxCpltCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
+ }
+
+}
+
+/**
+ * @brief DMA IRDA transmit process half complete callback.
+ * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma)
+{
+ IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent);
+
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+ /* Call registered Tx Half complete callback */
+ hirda->TxHalfCpltCallback(hirda);
+#else
+ /* Call legacy weak Tx complete callback */
+ HAL_IRDA_TxHalfCpltCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
+}
+
+/**
+ * @brief DMA IRDA receive process complete callback.
+ * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+ IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent);
+
+ /* DMA Normal mode */
+ if (HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC))
+ {
+ hirda->RxXferCount = 0U;
+
+ /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+ /* Disable the DMA transfer for the receiver request by resetting the DMAR bit
+ in the IRDA CR3 register */
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+
+ /* At end of Rx process, restore hirda->RxState to Ready */
+ hirda->RxState = HAL_IRDA_STATE_READY;
+ }
+
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+ /* Call registered Rx complete callback */
+ hirda->RxCpltCallback(hirda);
+#else
+ /* Call legacy weak Rx complete callback */
+ HAL_IRDA_RxCpltCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief DMA IRDA receive process half complete callback.
+ * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma)
+{
+ IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent);
+
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+ /*Call registered Rx Half complete callback*/
+ hirda->RxHalfCpltCallback(hirda);
+#else
+ /* Call legacy weak Rx Half complete callback */
+ HAL_IRDA_RxHalfCpltCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
+}
+
+/**
+ * @brief DMA IRDA communication error callback.
+ * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void IRDA_DMAError(DMA_HandleTypeDef *hdma)
+{
+ IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent);
+
+ /* Stop IRDA DMA Tx request if ongoing */
+ if (hirda->gState == HAL_IRDA_STATE_BUSY_TX)
+ {
+ if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
+ {
+ hirda->TxXferCount = 0U;
+ IRDA_EndTxTransfer(hirda);
+ }
+ }
+
+ /* Stop IRDA DMA Rx request if ongoing */
+ if (hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
+ {
+ if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
+ {
+ hirda->RxXferCount = 0U;
+ IRDA_EndRxTransfer(hirda);
+ }
+ }
+
+ hirda->ErrorCode |= HAL_IRDA_ERROR_DMA;
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+ /* Call registered user error callback */
+ hirda->ErrorCallback(hirda);
+#else
+ /* Call legacy weak user error callback */
+ HAL_IRDA_ErrorCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
+}
+
+/**
+ * @brief DMA IRDA communication abort callback, when initiated by HAL services on Error
+ * (To be called at end of DMA Abort procedure following error occurrence).
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void IRDA_DMAAbortOnError(DMA_HandleTypeDef *hdma)
+{
+ IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent);
+ hirda->RxXferCount = 0U;
+ hirda->TxXferCount = 0U;
+
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+ /* Call registered user error callback */
+ hirda->ErrorCallback(hirda);
+#else
+ /* Call legacy weak user error callback */
+ HAL_IRDA_ErrorCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
+}
+
+/**
+ * @brief DMA IRDA Tx communication abort callback, when initiated by user
+ * (To be called at end of DMA Tx Abort procedure following user abort request).
+ * @note When this callback is executed, User Abort complete call back is called only if no
+ * Abort still ongoing for Rx DMA Handle.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void IRDA_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent);
+
+ hirda->hdmatx->XferAbortCallback = NULL;
+
+ /* Check if an Abort process is still ongoing */
+ if (hirda->hdmarx != NULL)
+ {
+ if (hirda->hdmarx->XferAbortCallback != NULL)
+ {
+ return;
+ }
+ }
+
+ /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
+ hirda->TxXferCount = 0U;
+ hirda->RxXferCount = 0U;
+
+ /* Reset errorCode */
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
+
+ /* Restore hirda->gState and hirda->RxState to Ready */
+ hirda->gState = HAL_IRDA_STATE_READY;
+ hirda->RxState = HAL_IRDA_STATE_READY;
+
+ /* Call user Abort complete callback */
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort complete callback */
+ hirda->AbortCpltCallback(hirda);
+#else
+ /* Call legacy weak Abort complete callback */
+ HAL_IRDA_AbortCpltCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
+}
+
+
+/**
+ * @brief DMA IRDA Rx communication abort callback, when initiated by user
+ * (To be called at end of DMA Rx Abort procedure following user abort request).
+ * @note When this callback is executed, User Abort complete call back is called only if no
+ * Abort still ongoing for Tx DMA Handle.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void IRDA_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent);
+
+ hirda->hdmarx->XferAbortCallback = NULL;
+
+ /* Check if an Abort process is still ongoing */
+ if (hirda->hdmatx != NULL)
+ {
+ if (hirda->hdmatx->XferAbortCallback != NULL)
+ {
+ return;
+ }
+ }
+
+ /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
+ hirda->TxXferCount = 0U;
+ hirda->RxXferCount = 0U;
+
+ /* Reset errorCode */
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
+
+ /* Restore hirda->gState and hirda->RxState to Ready */
+ hirda->gState = HAL_IRDA_STATE_READY;
+ hirda->RxState = HAL_IRDA_STATE_READY;
+
+ /* Call user Abort complete callback */
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort complete callback */
+ hirda->AbortCpltCallback(hirda);
+#else
+ /* Call legacy weak Abort complete callback */
+ HAL_IRDA_AbortCpltCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
+}
+
+
+/**
+ * @brief DMA IRDA Tx communication abort callback, when initiated by user by a call to
+ * HAL_IRDA_AbortTransmit_IT API (Abort only Tx transfer)
+ * (This callback is executed at end of DMA Tx Abort procedure following user abort request,
+ * and leads to user Tx Abort Complete callback execution).
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void IRDA_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent);
+
+ hirda->TxXferCount = 0U;
+
+ /* Restore hirda->gState to Ready */
+ hirda->gState = HAL_IRDA_STATE_READY;
+
+ /* Call user Abort complete callback */
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Transmit Complete Callback */
+ hirda->AbortTransmitCpltCallback(hirda);
+#else
+ /* Call legacy weak Abort Transmit Complete Callback */
+ HAL_IRDA_AbortTransmitCpltCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
+}
+
+/**
+ * @brief DMA IRDA Rx communication abort callback, when initiated by user by a call to
+ * HAL_IRDA_AbortReceive_IT API (Abort only Rx transfer)
+ * (This callback is executed at end of DMA Rx Abort procedure following user abort request,
+ * and leads to user Rx Abort Complete callback execution).
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void IRDA_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ hirda->RxXferCount = 0U;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
+
+ /* Restore hirda->RxState to Ready */
+ hirda->RxState = HAL_IRDA_STATE_READY;
+
+ /* Call user Abort complete callback */
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Receive Complete Callback */
+ hirda->AbortReceiveCpltCallback(hirda);
+#else
+ /* Call legacy weak Abort Receive Complete Callback */
+ HAL_IRDA_AbortReceiveCpltCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
+}
+
+/**
+ * @brief Send an amount of data in interrupt mode.
+ * @note Function is called under interruption only, once
+ * interruptions have been enabled by HAL_IRDA_Transmit_IT().
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval None
+ */
+static void IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda)
+{
+ const uint16_t *tmp;
+
+ /* Check that a Tx process is ongoing */
+ if (hirda->gState == HAL_IRDA_STATE_BUSY_TX)
+ {
+ if (hirda->TxXferCount == 0U)
+ {
+ /* Disable the IRDA Transmit Data Register Empty Interrupt */
+ CLEAR_BIT(hirda->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
+
+ /* Enable the IRDA Transmit Complete Interrupt */
+ SET_BIT(hirda->Instance->CR1, USART_CR1_TCIE);
+ }
+ else
+ {
+ if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
+ {
+ tmp = (const uint16_t *) hirda->pTxBuffPtr; /* Derogation R.11.3 */
+ hirda->Instance->TDR = (uint16_t)(*tmp & 0x01FFU);
+ hirda->pTxBuffPtr += 2U;
+ }
+ else
+ {
+ hirda->Instance->TDR = (uint8_t)(*hirda->pTxBuffPtr & 0xFFU);
+ hirda->pTxBuffPtr++;
+ }
+ hirda->TxXferCount--;
+ }
+ }
+}
+
+/**
+ * @brief Wrap up transmission in non-blocking mode.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval None
+ */
+static void IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda)
+{
+ /* Disable the IRDA Transmit Complete Interrupt */
+ CLEAR_BIT(hirda->Instance->CR1, USART_CR1_TCIE);
+
+ /* Tx process is ended, restore hirda->gState to Ready */
+ hirda->gState = HAL_IRDA_STATE_READY;
+
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+ /* Call registered Tx complete callback */
+ hirda->TxCpltCallback(hirda);
+#else
+ /* Call legacy weak Tx complete callback */
+ HAL_IRDA_TxCpltCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
+}
+
+/**
+ * @brief Receive an amount of data in interrupt mode.
+ * @note Function is called under interruption only, once
+ * interruptions have been enabled by HAL_IRDA_Receive_IT()
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval None
+ */
+static void IRDA_Receive_IT(IRDA_HandleTypeDef *hirda)
+{
+ uint16_t *tmp;
+ uint16_t uhMask = hirda->Mask;
+ uint16_t uhdata;
+
+ /* Check that a Rx process is ongoing */
+ if (hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
+ {
+ uhdata = (uint16_t) READ_REG(hirda->Instance->RDR);
+ if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
+ {
+ tmp = (uint16_t *) hirda->pRxBuffPtr; /* Derogation R.11.3 */
+ *tmp = (uint16_t)(uhdata & uhMask);
+ hirda->pRxBuffPtr += 2U;
+ }
+ else
+ {
+ *hirda->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask);
+ hirda->pRxBuffPtr++;
+ }
+
+ hirda->RxXferCount--;
+ if (hirda->RxXferCount == 0U)
+ {
+ /* Disable the IRDA Parity Error Interrupt and RXNE interrupt */
+ CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
+
+ /* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+ /* Rx process is completed, restore hirda->RxState to Ready */
+ hirda->RxState = HAL_IRDA_STATE_READY;
+
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+ /* Call registered Rx complete callback */
+ hirda->RxCpltCallback(hirda);
+#else
+ /* Call legacy weak Rx complete callback */
+ HAL_IRDA_RxCpltCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
+ }
+ }
+ else
+ {
+ /* Clear RXNE interrupt flag */
+ __HAL_IRDA_SEND_REQ(hirda, IRDA_RXDATA_FLUSH_REQUEST);
+ }
+}
+
+/**
+ * @}
+ */
+
+#endif /* HAL_IRDA_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_iwdg.c b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_iwdg.c
new file mode 100644
index 0000000000..5d60ed8373
--- /dev/null
+++ b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_iwdg.c
@@ -0,0 +1,283 @@
+/**
+ ******************************************************************************
+ * @file stm32c0xx_hal_iwdg.c
+ * @author MCD Application Team
+ * @brief IWDG HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Independent Watchdog (IWDG) peripheral:
+ * + Initialization and Start functions
+ * + IO operation functions
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2022 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### IWDG Generic features #####
+ ==============================================================================
+ [..]
+ (+) The IWDG can be started by either software or hardware (configurable
+ through option byte).
+
+ (+) The IWDG is clocked by the Low-Speed Internal clock (LSI) and thus stays
+ active even if the main clock fails.
+
+ (+) Once the IWDG is started, the LSI is forced ON and both cannot be
+ disabled. The counter starts counting down from the reset value (0xFFF).
+ When it reaches the end of count value (0x000) a reset signal is
+ generated (IWDG reset).
+
+ (+) Whenever the key value 0x0000 AAAA is written in the IWDG_KR register,
+ the IWDG_RLR value is reloaded into the counter and the watchdog reset
+ is prevented.
+
+ (+) The IWDG is implemented in the VDD voltage domain that is still functional
+ in STOP and STANDBY mode (IWDG reset can wake up the CPU from STANDBY).
+ IWDGRST flag in RCC_CSR register can be used to inform when an IWDG
+ reset occurs.
+
+ (+) Debug mode: When the microcontroller enters debug mode (core halted),
+ the IWDG counter either continues to work normally or stops, depending
+ on DBG_IWDG_STOP configuration bit in DBG module, accessible through
+ __HAL_DBGMCU_FREEZE_IWDG() and __HAL_DBGMCU_UNFREEZE_IWDG() macros.
+
+ [..] Min-max timeout value @32KHz (LSI): ~125us / ~32.7s
+ The IWDG timeout may vary due to LSI clock frequency dispersion.
+ STM32C0xx devices provide the capability to measure the LSI clock
+ frequency (LSI clock is internally connected to TIM16 CH1 input capture).
+ The measured value can be used to have an IWDG timeout with an
+ acceptable accuracy.
+
+ [..] Default timeout value (necessary for IWDG_SR status register update):
+ Constant LSI_VALUE is defined based on the nominal LSI clock frequency.
+ This frequency being subject to variations as mentioned above, the
+ default timeout value (defined through constant HAL_IWDG_DEFAULT_TIMEOUT
+ below) may become too short or too long.
+ In such cases, this default timeout value can be tuned by redefining
+ the constant LSI_VALUE at user-application level (based, for instance,
+ on the measured LSI clock frequency as explained above).
+
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ (#) Use IWDG using HAL_IWDG_Init() function to :
+ (++) Enable instance by writing Start keyword in IWDG_KEY register. LSI
+ clock is forced ON and IWDG counter starts counting down.
+ (++) Enable write access to configuration registers:
+ IWDG_PR, IWDG_RLR and IWDG_WINR.
+ (++) Configure the IWDG prescaler and counter reload value. This reload
+ value will be loaded in the IWDG counter each time the watchdog is
+ reloaded, then the IWDG will start counting down from this value.
+ (++) Depending on window parameter:
+ (+++) If Window Init parameter is same as Window register value,
+ nothing more is done but reload counter value in order to exit
+ function with exact time base.
+ (+++) Else modify Window register. This will automatically reload
+ watchdog counter.
+ (++) Wait for status flags to be reset.
+
+ (#) Then the application program must refresh the IWDG counter at regular
+ intervals during normal operation to prevent an MCU reset, using
+ HAL_IWDG_Refresh() function.
+
+ *** IWDG HAL driver macros list ***
+ ====================================
+ [..]
+ Below the list of most used macros in IWDG HAL driver:
+ (+) __HAL_IWDG_START: Enable the IWDG peripheral
+ (+) __HAL_IWDG_RELOAD_COUNTER: Reloads IWDG counter with value defined in
+ the reload register
+
+ @endverbatim
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32c0xx_hal.h"
+
+/** @addtogroup STM32C0xx_HAL_Driver
+ * @{
+ */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+/** @addtogroup IWDG
+ * @brief IWDG HAL module driver.
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup IWDG_Private_Defines IWDG Private Defines
+ * @{
+ */
+/* Status register needs up to 5 LSI clock periods divided by the clock
+ prescaler to be updated. The number of LSI clock periods is upper-rounded to
+ 6 for the timeout value calculation.
+ The timeout value is calculated using the highest prescaler (256) and
+ the LSI_VALUE constant. The value of this constant can be changed by the user
+ to take into account possible LSI clock period variations.
+ The timeout value is multiplied by 1000 to be converted in milliseconds.
+ LSI startup time is also considered here by adding LSI_STARTUP_TIMEOUT
+ converted in milliseconds. */
+#define HAL_IWDG_DEFAULT_TIMEOUT (((6UL * 256UL * 1000UL) / LSI_VALUE) + ((LSI_STARTUP_TIME / 1000UL) + 1UL))
+#define IWDG_KERNEL_UPDATE_FLAGS (IWDG_SR_WVU | IWDG_SR_RVU | IWDG_SR_PVU)
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup IWDG_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup IWDG_Exported_Functions_Group1
+ * @brief Initialization and Start functions.
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and Start functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Initialize the IWDG according to the specified parameters in the
+ IWDG_InitTypeDef of associated handle.
+ (+) Manage Window option.
+ (+) Once initialization is performed in HAL_IWDG_Init function, Watchdog
+ is reloaded in order to exit function with correct time base.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initialize the IWDG according to the specified parameters in the
+ * IWDG_InitTypeDef and start watchdog. Before exiting function,
+ * watchdog is refreshed in order to have correct time base.
+ * @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains
+ * the configuration information for the specified IWDG module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
+{
+ uint32_t tickstart;
+
+ /* Check the IWDG handle allocation */
+ if (hiwdg == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_IWDG_ALL_INSTANCE(hiwdg->Instance));
+ assert_param(IS_IWDG_PRESCALER(hiwdg->Init.Prescaler));
+ assert_param(IS_IWDG_RELOAD(hiwdg->Init.Reload));
+ assert_param(IS_IWDG_WINDOW(hiwdg->Init.Window));
+
+ /* Enable IWDG. LSI is turned on automatically */
+ __HAL_IWDG_START(hiwdg);
+
+ /* Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers by writing
+ 0x5555 in KR */
+ IWDG_ENABLE_WRITE_ACCESS(hiwdg);
+
+ /* Write to IWDG registers the Prescaler & Reload values to work with */
+ hiwdg->Instance->PR = hiwdg->Init.Prescaler;
+ hiwdg->Instance->RLR = hiwdg->Init.Reload;
+
+ /* Check pending flag, if previous update not done, return timeout */
+ tickstart = HAL_GetTick();
+
+ /* Wait for register to be updated */
+ while ((hiwdg->Instance->SR & IWDG_KERNEL_UPDATE_FLAGS) != 0x00u)
+ {
+ if ((HAL_GetTick() - tickstart) > HAL_IWDG_DEFAULT_TIMEOUT)
+ {
+ if ((hiwdg->Instance->SR & IWDG_KERNEL_UPDATE_FLAGS) != 0x00u)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* If window parameter is different than current value, modify window
+ register */
+ if (hiwdg->Instance->WINR != hiwdg->Init.Window)
+ {
+ /* Write to IWDG WINR the IWDG_Window value to compare with. In any case,
+ even if window feature is disabled, Watchdog will be reloaded by writing
+ windows register */
+ hiwdg->Instance->WINR = hiwdg->Init.Window;
+ }
+ else
+ {
+ /* Reload IWDG counter with value defined in the reload register */
+ __HAL_IWDG_RELOAD_COUNTER(hiwdg);
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup IWDG_Exported_Functions_Group2
+ * @brief IO operation functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Refresh the IWDG.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Refresh the IWDG.
+ * @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains
+ * the configuration information for the specified IWDG module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg)
+{
+ /* Reload IWDG counter with value defined in the reload register */
+ __HAL_IWDG_RELOAD_COUNTER(hiwdg);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_IWDG_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_msp_template.c b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_msp_template.c
new file mode 100644
index 0000000000..43599b5046
--- /dev/null
+++ b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_msp_template.c
@@ -0,0 +1,107 @@
+/**
+ ******************************************************************************
+ * @file stm32c0xx_hal_msp_template.c
+ * @author MCD Application Team
+ * @brief HAL MSP module.
+ * This file template is located in the HAL folder and should be copied
+ * to the user folder.
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2022 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ===============================================================================
+ ##### How to use this driver #####
+ ===============================================================================
+ [..]
+
+ @endverbatim
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32c0xx_hal.h"
+
+/** @addtogroup STM32C0xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup HAL_MSP HAL MSP module driver
+ * @brief HAL MSP module.
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup HAL_MSP_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Initialize the Global MSP.
+ * @retval None
+ */
+void HAL_MspInit(void)
+{
+ /* NOTE : This function is generated automatically by STM32CubeMX and eventually
+ modified by the user
+ */
+}
+
+/**
+ * @brief DeInitialize the Global MSP.
+ * @retval None
+ */
+void HAL_MspDeInit(void)
+{
+ /* NOTE : This function is generated automatically by STM32CubeMX and eventually
+ modified by the user
+ */
+}
+
+/**
+ * @brief Initialize the PPP MSP.
+ * @retval None
+ */
+void HAL_PPP_MspInit(void)
+{
+ /* NOTE : This function is generated automatically by STM32CubeMX and eventually
+ modified by the user
+ */
+}
+
+/**
+ * @brief DeInitialize the PPP MSP.
+ * @retval None
+ */
+void HAL_PPP_MspDeInit(void)
+{
+ /* NOTE : This function is generated automatically by STM32CubeMX and eventually
+ modified by the user
+ */
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.c b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.c
new file mode 100644
index 0000000000..272c61a7d4
--- /dev/null
+++ b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.c
@@ -0,0 +1,433 @@
+/**
+ ******************************************************************************
+ * @file stm32c0xx_hal_pwr.c
+ * @author MCD Application Team
+ * @brief PWR HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Power Controller (PWR) peripheral:
+ * + Initialization/de-initialization functions
+ * + Peripheral Control functions
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2022 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32c0xx_hal.h"
+
+/** @addtogroup STM32C0xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup PWR
+ * @{
+ */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup PWR_Private_Defines PWR Private Defines
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup PWR_Exported_Functions PWR Exported Functions
+ * @{
+ */
+
+/** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and de-initialization functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..]
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Deinitialize the HAL PWR peripheral registers to their default reset
+ values.
+ * @retval None
+ */
+void HAL_PWR_DeInit(void)
+{
+ __HAL_RCC_PWR_FORCE_RESET();
+ __HAL_RCC_PWR_RELEASE_RESET();
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions
+ * @brief Low Power modes configuration functions
+ *
+@verbatim
+
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+
+ [..]
+
+ *** WakeUp pin configuration ***
+ ================================
+ [..]
+ (+) WakeUp pins are used to wakeup the system from Standby mode or
+ Shutdown mode. WakeUp pins polarity can be set to configure event
+ detection on high level (rising edge) or low level (falling edge).
+
+ *** Low Power mode configuration ***
+ =====================================
+ [..]
+ The devices feature 4 low-power modes:
+ (+) Sleep mode: Cortex-M0+ core stopped, peripherals kept running,
+ regulator is main mode.
+ (+) Stop 0 mode: all clocks are stopped except LSI and LSE, regulator is
+ main mode.
+ (+) Standby mode: all clocks are stopped except LSI and LSE, regulator is
+ disable.
+ (+) Shutdown mode: all clocks are stopped except LSE, regulator is
+ disable.
+
+
+ *** Sleep mode ***
+ =========================================
+ [..]
+ (+) Entry:
+ The Sleep is entered through HAL_PWR_EnterSLEEPMode() API specifying
+ the main regulator per default and if exit is interrupt or event
+ triggered.
+ (++) PWR_MAINREGULATOR_ON: Sleep mode (regulator in main mode).
+ (++) PWR_SLEEPENTRY_WFI: Core enters sleep mode with WFI instruction
+ (++) PWR_SLEEPENTRY_WFE: Core enters sleep mode with WFE instruction
+ (+) WFI Exit:
+ (++) Any interrupt enabled in nested vectored interrupt controller (NVIC)
+ (+) WFE Exit:
+ (++) Any wakeup event if cortex is configured with SEVONPEND = 0
+ (++) Interrupt even when disabled in NVIC if cortex is configured with
+ SEVONPEND = 1
+
+ *** Stop 0 mode ***
+ =============================
+ [..]
+ (+) Entry:
+ The Stop modes are entered through the following APIs:
+ (++) HAL_PWR_EnterSTOPMode() with following settings:
+ (+++) PWR_MAINREGULATOR_ON to enter STOP0 mode.
+ (+) Exit (interrupt or event-triggered, specified when entering STOP mode):
+ (++) PWR_STOPENTRY_WFI: enter Stop mode with WFI instruction
+ (++) PWR_STOPENTRY_WFE: enter Stop mode with WFE instruction
+ (+) WFI Exit:
+ (++) Any EXTI line (internal or external) configured in interrupt mode
+ with corresponding interrupt enable in NVIC
+ (+) WFE Exit:
+ (++) Any EXTI line (internal or external) configured in event mode if
+ cortex is configured with SEVONPEND = 0
+ (++) Any EXTI line configured in interrupt mode (even if the
+ corresponding EXTI Interrupt vector is disabled in the NVIC) if
+ cortex is configured with SEVONPEND = 0. The interrupt source can
+ be external interrupts or peripherals with wakeup capability.
+
+ *** Standby mode ***
+ ====================
+ [..]
+ (+) Entry:
+ (++) The Standby mode is entered through HAL_PWR_EnterSTANDBYMode() API, by
+ setting SLEEPDEEP in Cortex control register.
+ (+) Exit:
+ (++) WKUP pin edge detection, RTC event (alarm, timestamp),
+ LSE CSS detection, reset on NRST pin, IWDG reset & BOR reset.
+ [..] Exiting Standby generates a power reset: Cortex is reset and execute
+ Reset handler vector, all registers in the Vcore domain are set to
+ their reset value. Registers outside the VCORE domain (RTC, WKUP, IWDG,
+ and Standby/Shutdown modes control) are not impacted.
+
+ *** Shutdown mode ***
+ ======================
+ [..]
+ In Shutdown mode,
+ voltage regulator is disabled, all clocks are off except LSE, RRS bit is
+ cleared. SRAM and registers contents are lost except for backup domain
+ registers.
+ (+) Entry:
+ (++) The Shutdown mode is entered through HAL_PWREx_EnterSHUTDOWNMode() API,
+ by setting SLEEPDEEP in Cortex control register.
+ (+) Exit:
+ (++) WKUP pin edge detection, RTC event (alarm, timestamp),
+ LSE CSS detection, reset on NRST pin.
+ [..] Exiting Shutdown generates a brown out reset: Cortex is reset and execute
+ Reset handler vector, all registers are set to their reset value but ones
+ in backup domain.
+
+@endverbatim
+ * @{
+ */
+
+
+/**
+ * @brief Enable the WakeUp PINx functionality.
+ * @param WakeUpPinPolarity Specifies which Wake-Up pin to enable.
+ * This parameter can be one of the following legacy values which set
+ * the default polarity i.e. detection on high level (rising edge):
+ * @arg @ref PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN4,
+ * PWR_WAKEUP_PIN6
+ * or one of the following value where the user can explicitly specify
+ * the enabled pin and the chosen polarity:
+ * @arg @ref PWR_WAKEUP_PIN1_HIGH or PWR_WAKEUP_PIN1_LOW
+ * @arg @ref PWR_WAKEUP_PIN2_HIGH or PWR_WAKEUP_PIN2_LOW
+ * @arg @ref PWR_WAKEUP_PIN4_HIGH or PWR_WAKEUP_PIN4_LOW
+ * @arg @ref PWR_WAKEUP_PIN6_HIGH or PWR_WAKEUP_PIN6_LOW
+ * @note PWR_WAKEUP_PINx and PWR_WAKEUP_PINx_HIGH are equivalent.
+ * @retval None
+ */
+void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity)
+{
+ assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinPolarity));
+
+ /* Specifies the Wake-Up pin polarity for the event detection
+ (rising or falling edge) */
+ MODIFY_REG(PWR->CR4, (PWR_CR4_WP & WakeUpPinPolarity), (WakeUpPinPolarity >> PWR_WUP_POLARITY_SHIFT));
+
+ /* Enable wake-up pin */
+ SET_BIT(PWR->CR3, (PWR_CR3_EWUP & WakeUpPinPolarity));
+}
+
+
+/**
+ * @brief Disable the WakeUp PINx functionality.
+ * @param WakeUpPinx Specifies the Power Wake-Up pin to disable.
+ * This parameter can be one of the following values:
+ * @arg @ref PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN4,
+ * PWR_WAKEUP_PIN6
+ * @retval None
+ */
+void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
+{
+ assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
+
+ CLEAR_BIT(PWR->CR3, (PWR_CR3_EWUP & WakeUpPinx));
+}
+
+
+/**
+ * @brief Enter Sleep mode.
+ * @note In Sleep mode, all I/O pins keep the same state as
+ * in Run mode.
+ * @param Regulator Specifies the regulator state in Sleep mode.
+ * This parameter can be the following value:
+ * @arg @ref PWR_MAINREGULATOR_ON Sleep mode (regulator in main mode)
+ * @param SLEEPEntry Specifies if Sleep mode is entered with WFI or WFE
+ * instruction. This parameter can be one of the following values:
+ * @arg @ref PWR_SLEEPENTRY_WFI enter Sleep or Low-power Sleep
+ * mode with WFI instruction
+ * @arg @ref PWR_SLEEPENTRY_WFE enter Sleep or Low-power Sleep
+ * mode with WFE instruction
+ * @note When WFI entry is used, tick interrupt have to be disabled if not
+ * desired as the interrupt wake up source.
+ * @retval None
+ */
+void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
+{
+ /* Check the parameters */
+ assert_param(IS_PWR_REGULATOR(Regulator));
+ assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
+
+ /* Clear SLEEPDEEP bit of Cortex System Control Register */
+ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
+
+ /* Select SLEEP mode entry -------------------------------------------------*/
+ if (SLEEPEntry == PWR_SLEEPENTRY_WFI)
+ {
+ /* Request Wait For Interrupt */
+ __WFI();
+ }
+ else
+ {
+ /* Request Wait For Event */
+ __SEV();
+ __WFE();
+ __WFE();
+ }
+}
+
+
+/**
+ * @brief Enter Stop mode
+ * @note This API is named HAL_PWR_EnterSTOPMode to ensure compatibility with
+ * legacy code running on devices where only "Stop mode" is mentioned
+ * with main regulator ON.
+ * @note In Stop mode, all I/O pins keep the same state as in Run mode.
+ * @note All clocks in the VCORE domain are stopped; the HSI and the
+ * HSE oscillators are disabled. Some peripherals with the wakeup
+ * capability can switch on the HSI to receive a frame, and switch off
+ * the HSI after receiving the frame if it is not a wakeup frame.
+ * SRAM and register contents are preserved.
+ * @note When exiting Stop 0 mode by issuing an interrupt or a
+ * wakeup event, the HSI RC oscillator is selected as system clock
+ * @param Regulator Specifies the regulator state in Stop mode
+ * This parameter can be of the following value:
+ * @arg @ref PWR_MAINREGULATOR_ON Stop 0 mode (main regulator ON)
+ * @param STOPEntry Specifies Stop 0 mode is entered with WFI or
+ * WFE instruction. This parameter can be one of the following values:
+ * @arg @ref PWR_STOPENTRY_WFI Enter Stop 0 mode with WFI
+ * instruction.
+ * @arg @ref PWR_STOPENTRY_WFE Enter Stop 0 mode with WFE
+ * instruction.
+ * @retval None
+ */
+void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
+{
+ /* Check the parameters */
+ assert_param(IS_PWR_REGULATOR(Regulator));
+ assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
+
+ MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_LOWPOWERMODE_STOP0);
+
+ /* Set SLEEPDEEP bit of Cortex System Control Register */
+ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
+
+ /* Select Stop mode entry --------------------------------------------------*/
+ if (STOPEntry == PWR_STOPENTRY_WFI)
+ {
+ /* Request Wait For Interrupt */
+ __WFI();
+ }
+ else
+ {
+ /* Request Wait For Event */
+ __SEV();
+ __WFE();
+ __WFE();
+ }
+
+ /* Reset SLEEPDEEP bit of Cortex System Control Register */
+ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
+}
+
+
+/**
+ * @brief Enter Standby mode.
+ * @note In Standby mode,the HSI and the HSE oscillators are
+ * switched off. SRAM and register contents are lost except
+ * for registers in the Backup domain and Standby circuitry.
+ * @note The I/Os can be configured either with a pull-up or pull-down or can
+ * be kept in analog state.
+ * HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown()
+ * respectively enable Pull Up and PullDown state.
+ * HAL_PWREx_DisableGPIOPullUp() & HAL_PWREx_DisableGPIOPullDown()
+ * disable the same. These states are effective in Standby mode only if
+ * APC bit is set through HAL_PWREx_EnablePullUpPullDownConfig() API.
+ * @retval None
+ */
+void HAL_PWR_EnterSTANDBYMode(void)
+{
+ /* Set Stand-by mode */
+ MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_LOWPOWERMODE_STANDBY);
+
+ /* Set SLEEPDEEP bit of Cortex System Control Register */
+ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
+
+ /* This option is used to ensure that store operations are completed */
+#if defined ( __CC_ARM)
+ __force_stores();
+#endif /* __CC_ARM */
+
+ /* Request Wait For Interrupt */
+ __WFI();
+}
+
+
+/**
+ * @brief Enable Sleep-On-Exit Cortex feature
+ * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the
+ * processor enters SLEEP or DEEPSLEEP mode when an interruption
+ * handling is over returning to thread mode. Setting this bit is
+ * useful when the processor is expected to run only on interruptions
+ * handling.
+ * @retval None
+ */
+void HAL_PWR_EnableSleepOnExit(void)
+{
+ /* Set SLEEPONEXIT bit of Cortex System Control Register */
+ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
+}
+
+
+/**
+ * @brief Disable Sleep-On-Exit Cortex feature
+ * @note Clear SLEEPONEXIT bit of SCR register. When this bit is set, the
+ * processor enters SLEEP or DEEPSLEEP mode when an interruption
+ * handling is over.
+ * @retval None
+ */
+void HAL_PWR_DisableSleepOnExit(void)
+{
+ /* Clear SLEEPONEXIT bit of Cortex System Control Register */
+ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
+}
+
+
+/**
+ * @brief Enable Cortex Sev On Pending feature.
+ * @note Set SEVONPEND bit of SCR register. When this bit is set, enabled
+ * events and all interrupts, including disabled ones can wakeup
+ * processor from WFE.
+ * @retval None
+ */
+void HAL_PWR_EnableSEVOnPend(void)
+{
+ /* Set SEVONPEND bit of Cortex System Control Register */
+ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
+}
+
+
+/**
+ * @brief Disable Cortex Sev On Pending feature.
+ * @note Clear SEVONPEND bit of SCR register. When this bit is clear, only
+ * enable interrupts or events can wakeup processor from WFE
+ * @retval None
+ */
+void HAL_PWR_DisableSEVOnPend(void)
+{
+ /* Clear SEVONPEND bit of Cortex System Control Register */
+ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_PWR_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.c b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.c
new file mode 100644
index 0000000000..d46204db49
--- /dev/null
+++ b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.c
@@ -0,0 +1,492 @@
+/**
+ ******************************************************************************
+ * @file stm32c0xx_hal_pwr_ex.c
+ * @author MCD Application Team
+ * @brief Extended PWR HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Power Controller (PWR) peripheral:
+ * + Extended Initialization and de-initialization functions
+ * + Extended Peripheral Control functions
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2022 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32c0xx_hal.h"
+
+/** @addtogroup STM32C0xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup PWREx
+ * @{
+ */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup PWR_Extended_Private_Defines PWR Extended Private Defines
+ * @{
+ */
+
+/** @defgroup PWREx_Gpio_Pin_Number PWREx Gpio Pin Number
+ * @{
+ */
+#define PWR_GPIO_PIN_NB 16u /*!< Number of gpio pin in bank */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup PWREx_Exported_Functions PWR Extended Exported Functions
+ * @{
+ */
+
+/** @addtogroup PWREx_Exported_Functions_Group1 Extended Peripheral Control functions
+ * @brief Extended Peripheral Control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Extended Peripheral Initialization and de-initialization functions #####
+ ===============================================================================
+ [..]
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enable Internal Wake-up Line.
+ * @retval None
+ */
+void HAL_PWREx_EnableInternalWakeUpLine(void)
+{
+ SET_BIT(PWR->CR3, PWR_CR3_EIWUL);
+}
+
+
+/**
+ * @brief Disable Internal Wake-up Line.
+ * @retval None
+ */
+void HAL_PWREx_DisableInternalWakeUpLine(void)
+{
+ CLEAR_BIT(PWR->CR3, PWR_CR3_EIWUL);
+}
+
+
+/**
+ * @brief Enable GPIO pull-up state in Standby and Shutdown modes.
+ * @note Set the relevant PUy bit of PWR_PUCRx register to configure the I/O in
+ * pull-up state in Standby and Shutdown modes.
+ * @note This state is effective in Standby and Shutdown modes only if APC bit
+ * is set through HAL_PWREx_EnablePullUpPullDownConfig() API.
+ * @note The configuration is lost when exiting the Shutdown mode due to the
+ * power-on reset, maintained when exiting the Standby mode.
+ * @note To avoid any conflict at Standby and Shutdown modes exits, the corresponding
+ * PDy bit of PWR_PDCRx register is cleared unless it is reserved.
+ * @param GPIO Specify the IO port. This parameter can be PWR_GPIO_A, ..., PWR_GPIO_F
+ * to select the GPIO peripheral.
+ * @param GPIONumber Specify the I/O pins numbers.
+ * This parameter can be one of the following values:
+ * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for ports where less
+ * I/O pins are available) or the logical OR of several of them to set
+ * several bits for a given port in a single API call.
+ * @retval HAL Status
+ */
+HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ assert_param(IS_PWR_GPIO(GPIO));
+ assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber));
+
+ switch (GPIO)
+ {
+ case PWR_GPIO_A:
+ SET_BIT(PWR->PUCRA, GPIONumber);
+ CLEAR_BIT(PWR->PDCRA, GPIONumber);
+ break;
+
+ case PWR_GPIO_B:
+ SET_BIT(PWR->PUCRB, GPIONumber);
+ CLEAR_BIT(PWR->PDCRB, GPIONumber);
+ break;
+
+ case PWR_GPIO_C:
+ SET_BIT(PWR->PUCRC, GPIONumber);
+ CLEAR_BIT(PWR->PDCRC, GPIONumber);
+ break;
+#if defined (STM32C031xx)
+ case PWR_GPIO_D:
+ SET_BIT(PWR->PUCRD, GPIONumber);
+ CLEAR_BIT(PWR->PDCRD, GPIONumber);
+ break;
+#endif /* STM32C031xx */
+ case PWR_GPIO_F:
+ SET_BIT(PWR->PUCRF, GPIONumber);
+ CLEAR_BIT(PWR->PDCRF, GPIONumber);
+ break;
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ return status;
+}
+
+
+/**
+ * @brief Disable GPIO pull-up state in Standby mode and Shutdown modes.
+ * @note Reset the relevant PUy bit of PWR_PUCRx register used to configure the I/O
+ * in pull-up state in Standby and Shutdown modes.
+ * @param GPIO Specifies the IO port. This parameter can be PWR_GPIO_A, ..., PWR_GPIO_F
+ * to select the GPIO peripheral.
+ * @param GPIONumber Specify the I/O pins numbers.
+ * This parameter can be one of the following values:
+ * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for ports where less
+ * I/O pins are available) or the logical OR of several of them to reset
+ * several bits for a given port in a single API call.
+ * @retval HAL Status
+ */
+HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ assert_param(IS_PWR_GPIO(GPIO));
+ assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber));
+
+ switch (GPIO)
+ {
+ case PWR_GPIO_A:
+ CLEAR_BIT(PWR->PUCRA, GPIONumber);
+ break;
+
+ case PWR_GPIO_B:
+ CLEAR_BIT(PWR->PUCRB, GPIONumber);
+ break;
+
+ case PWR_GPIO_C:
+ CLEAR_BIT(PWR->PUCRC, GPIONumber);
+ break;
+#if defined (STM32C031xx)
+ case PWR_GPIO_D:
+ CLEAR_BIT(PWR->PUCRD, GPIONumber);
+ break;
+#endif /* STM32C031xx */
+ case PWR_GPIO_F:
+ CLEAR_BIT(PWR->PUCRF, GPIONumber);
+ break;
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ return status;
+}
+
+
+/**
+ * @brief Enable GPIO pull-down state in Standby and Shutdown modes.
+ * @note Set the relevant PDy bit of PWR_PDCRx register to configure the I/O in
+ * pull-down state in Standby and Shutdown modes.
+ * @note This state is effective in Standby and Shutdown modes only if APC bit
+ * is set through HAL_PWREx_EnablePullUpPullDownConfig() API.
+ * @note The configuration is lost when exiting the Shutdown mode due to the
+ * power-on reset, maintained when exiting the Standby mode.
+ * @note To avoid any conflict at Standby and Shutdown modes exits, the corresponding
+ * PUy bit of PWR_PUCRx register is cleared unless it is reserved.
+ * @param GPIO Specify the IO port. This parameter can be PWR_GPIO_A..PWR_GPIO_F
+ * to select the GPIO peripheral.
+ * @param GPIONumber Specify the I/O pins numbers.
+ * This parameter can be one of the following values:
+ * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for ports where less
+ * I/O pins are available) or the logical OR of several of them to set
+ * several bits for a given port in a single API call.
+ * @retval HAL Status
+ */
+HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ assert_param(IS_PWR_GPIO(GPIO));
+ assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber));
+
+ switch (GPIO)
+ {
+ case PWR_GPIO_A:
+ SET_BIT(PWR->PDCRA, GPIONumber);
+ CLEAR_BIT(PWR->PUCRA, GPIONumber);
+ break;
+
+ case PWR_GPIO_B:
+ SET_BIT(PWR->PDCRB, GPIONumber);
+ CLEAR_BIT(PWR->PUCRB, GPIONumber);
+ break;
+
+ case PWR_GPIO_C:
+ SET_BIT(PWR->PDCRC, GPIONumber);
+ CLEAR_BIT(PWR->PUCRC, GPIONumber);
+ break;
+#if defined (STM32C031xx)
+ case PWR_GPIO_D:
+ SET_BIT(PWR->PDCRD, GPIONumber);
+ CLEAR_BIT(PWR->PUCRD, GPIONumber);
+ break;
+#endif /* STM32C031xx */
+ case PWR_GPIO_F:
+ SET_BIT(PWR->PDCRF, GPIONumber);
+ CLEAR_BIT(PWR->PUCRF, GPIONumber);
+ break;
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ return status;
+}
+
+
+/**
+ * @brief Disable GPIO pull-down state in Standby and Shutdown modes.
+ * @note Reset the relevant PDy bit of PWR_PDCRx register used to configure the I/O
+ * in pull-down state in Standby and Shutdown modes.
+ * @param GPIO Specifies the IO port. This parameter can be PWR_GPIO_A..PWR_GPIO_F
+ * to select the GPIO peripheral.
+ * @param GPIONumber Specify the I/O pins numbers.
+ * This parameter can be one of the following values:
+ * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for ports where less
+ * I/O pins are available) or the logical OR of several of them to reset
+ * several bits for a given port in a single API call.
+ * @retval HAL Status
+ */
+HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ assert_param(IS_PWR_GPIO(GPIO));
+ assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber));
+
+ switch (GPIO)
+ {
+ case PWR_GPIO_A:
+ CLEAR_BIT(PWR->PDCRA, GPIONumber);
+ break;
+
+ case PWR_GPIO_B:
+ CLEAR_BIT(PWR->PDCRB, GPIONumber);
+ break;
+
+ case PWR_GPIO_C:
+ CLEAR_BIT(PWR->PDCRC, GPIONumber);
+ break;
+#if defined (STM32C031xx)
+ case PWR_GPIO_D:
+ CLEAR_BIT(PWR->PDCRD, GPIONumber);
+ break;
+#endif /* STM32C031xx */
+ case PWR_GPIO_F:
+ CLEAR_BIT(PWR->PDCRF, GPIONumber);
+ break;
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ return status;
+}
+
+
+/**
+ * @brief Enable pull-up and pull-down configuration.
+ * @note When APC bit is set, the I/O pull-up and pull-down configurations defined in
+ * PWR_PUCRx and PWR_PDCRx registers are applied in Standby and Shutdown modes.
+ * @note Pull-up set by PUy bit of PWR_PUCRx register is not activated if the corresponding
+ * PDy bit of PWR_PDCRx register is also set (pull-down configuration priority is higher).
+ * HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown() APIs ensure there
+ * is no conflict when setting PUy or PDy bit.
+ * @retval None
+ */
+void HAL_PWREx_EnablePullUpPullDownConfig(void)
+{
+ SET_BIT(PWR->CR3, PWR_CR3_APC);
+}
+
+/**
+ * @brief Disable pull-up and pull-down configuration.
+ * @note When APC bit is cleared, the I/O pull-up and pull-down configurations defined in
+ * PWR_PUCRx and PWR_PDCRx registers are not applied in Standby and Shutdown modes.
+ * @retval None
+ */
+void HAL_PWREx_DisablePullUpPullDownConfig(void)
+{
+ CLEAR_BIT(PWR->CR3, PWR_CR3_APC);
+}
+
+
+/**
+ * @brief Enable Flash Power Down.
+ * @note This API allows to enable flash power down capabilities in sleep and stop modes.
+ * @param PowerMode this can be a combination of following values:
+ * @arg @ref PWR_FLASHPD_SLEEP
+ * @arg @ref PWR_FLASHPD_STOP
+ * @retval None
+ */
+void HAL_PWREx_EnableFlashPowerDown(uint32_t PowerMode)
+{
+ assert_param(IS_PWR_FLASH_POWERDOWN(PowerMode));
+
+ PWR->CR1 |= PowerMode;
+}
+
+
+/**
+ * @brief Disable Flash Power Down.
+ * @note This API allows to disable flash power down capabilities in sleep and stop modes.
+ * @param PowerMode this can be a combination of following values:
+ * @arg @ref PWR_FLASHPD_SLEEP
+ * @arg @ref PWR_FLASHPD_STOP
+ * @retval None
+ */
+void HAL_PWREx_DisableFlashPowerDown(uint32_t PowerMode)
+{
+ assert_param(IS_PWR_FLASH_POWERDOWN(PowerMode));
+
+ PWR->CR1 &= ~PowerMode;
+}
+
+
+/**
+ * @brief Enter Shutdown mode.
+ * @note In Shutdown mode, the PLL, the HSI, the LSI and the HSE oscillators are switched
+ * off. The voltage regulator is disabled and Vcore domain is powered off.
+ * SRAM and registers contents are lost except for registers in the Backup domain.
+ * The BOR is not available.
+ * @note The I/Os can be configured either with a pull-up or pull-down or can
+ * be kept in analog state.
+ * HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown()
+ * respectively enable Pull Up and PullDown state.
+ * HAL_PWREx_DisableGPIOPullUp() & HAL_PWREx_DisableGPIOPullDown()
+ * disable the same. These states are effective in Standby mode only if
+ * APC bit is set through HAL_PWREx_EnablePullUpPullDownConfig() API.
+ * @retval None
+
+ * @retval None
+ */
+void HAL_PWREx_EnterSHUTDOWNMode(void)
+{
+ /* Set Shutdown mode */
+ MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_LOWPOWERMODE_SHUTDOWN);
+
+ /* Set SLEEPDEEP bit of Cortex System Control Register */
+ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
+
+ /* This option is used to ensure that store operations are completed */
+#if defined ( __CC_ARM)
+ __force_stores();
+#endif /* __CC_ARM */
+
+ /* Request Wait For Interrupt */
+ __WFI();
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup PWREx_Exported_Functions_Group2 Extended PWR Backup register functions
+ * @brief Extended PWR Backup register functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Extended PWR Backup register functions #####
+ ===============================================================================
+ [..]
+ This subsection provides functions allowing to
+ (+) Write a data in a specified PWR Backup data register
+ (+) Read a data in a specified PWR Backup data register
+@endverbatim
+ * @{
+ */
+
+
+/**
+ * @brief Write a data in a specified PWR Backup data register.
+ * @param BackupRegister PWR Backup data Register number.
+ * This parameter can be PWR_BKP_DRx where x can be from 0 to PWR_BACKUP_NB
+ * @param Data Data to be written in the specified Backup data register.
+ * @retval None
+ */
+void HAL_PWREx_BKUPWrite(uint32_t BackupRegister, uint16_t Data)
+{
+ uint32_t tmp;
+
+ /* Check the parameters */
+ assert_param(IS_PWR_BKP(BackupRegister));
+
+ tmp = (uint32_t) &(PWR->BKPREG1);
+ tmp += (BackupRegister * 4U);
+
+ /* Write the specified register */
+ *(__IO uint32_t *)tmp = (uint16_t)Data;
+}
+
+
+/**
+ * @brief Reads data from the specified PWR Backup data Register.
+ * @param BackupRegister PWR Backup data Register number.
+ * This parameter can be PWR_BKP_DRx where x can be from 0 to PWR_BACKUP_NB
+ * @retval Read value
+ */
+uint32_t HAL_PWREx_BKUPRead(uint32_t BackupRegister)
+{
+ uint32_t tmp;
+
+ /* Check the parameters */
+ assert_param(IS_PWR_BKP(BackupRegister));
+
+ tmp = (uint32_t) &(PWR->BKPREG1);
+ tmp += (BackupRegister * 4U);
+
+ /* Read the specified register */
+ return (*(__IO uint32_t *)tmp);
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_PWR_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c
new file mode 100644
index 0000000000..fda1d10cbd
--- /dev/null
+++ b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c
@@ -0,0 +1,1134 @@
+/**
+ ******************************************************************************
+ * @file stm32c0xx_hal_rcc.c
+ * @author MCD Application Team
+ * @brief RCC HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Reset and Clock Control (RCC) peripheral:
+ * + Initialization and de-initialization functions
+ * + Peripheral Control functions
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2022 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### RCC specific features #####
+ ==============================================================================
+ [..]
+ After reset the device is running from High Speed Internal oscillator
+ divided by 4 that is the default system clock with Flash 0 wait state.
+
+ (+) There is no prescaler on High speed (AHB) and Low speed (APB) busses:
+ all peripherals mapped on these busses are running at HSI speed.
+ (+) The clock for all peripherals is switched off, except the SRAM and FLASH.
+ (+) All GPIOs are in analog mode
+
+ [..]
+ Once the device started from reset, the user application has to:
+ (+) Configure the clock source to be used to drive the System clock
+ (if the application needs higher frequency/performance)
+ (+) Configure the System clock frequency and Flash settings
+ (+) Configure the AHB and APB busses prescalers
+ (+) Enable the clock for the peripheral(s) to be used
+ (+) Configure the clock source(s) for peripherals which clocks are not
+ derived from the System clock (RTC, ADC, USART, I2C, I2S)
+
+ @endverbatim
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32c0xx_hal.h"
+
+/** @addtogroup STM32C0xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup RCC RCC
+ * @brief RCC HAL module driver
+ * @{
+ */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup RCC_Private_Constants RCC Private Constants
+ * @{
+ */
+#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
+#define HSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */
+#define LSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */
+#define CLOCKSWITCH_TIMEOUT_VALUE (5000U) /* 5 s */
+
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/** @defgroup RCC_Private_Macros RCC Private Macros
+ * @{
+ */
+#define RCC_GET_MCO_GPIO_PIN(__RCC_MCOx__) ((__RCC_MCOx__) & GPIO_PIN_MASK)
+
+#define RCC_GET_MCO_GPIO_AF(__RCC_MCOx__) (((__RCC_MCOx__) & RCC_MCO_GPIOAF_MASK) >> RCC_MCO_GPIOAF_POS)
+
+#define RCC_GET_MCO_GPIO_INDEX(__RCC_MCOx__) (((__RCC_MCOx__) & RCC_MCO_GPIOPORT_MASK) >> RCC_MCO_GPIOPORT_POS)
+
+#define RCC_GET_MCO_GPIO_PORT(__RCC_MCOx__) (IOPORT_BASE + ((0x00000400UL) * RCC_GET_MCO_GPIO_INDEX((__RCC_MCOx__))))
+
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup RCC_Private_Variables RCC Private Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup RCC_Exported_Functions RCC Exported Functions
+ * @{
+ */
+
+/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+ @verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..]
+ This section provides functions allowing to configure the internal and external oscillators
+ (HSE, HSI, LSE, LSI, CSS and MCO) and the System busses clocks (SYSCLK, AHB, APB)
+
+ [..] Internal/external clock
+ (+) HSI (high-speed internal): 48 MHz factory-trimmed RC used directly as System clock source.
+
+ (+) LSI (low-speed internal): 32 KHz low consumption RC used as IWDG and/or RTC
+ clock source.
+
+ (+) HSE (high-speed external): 4 to 48 MHz crystal oscillator used directly or
+ through the PLL as System clock source. Can be used also optionally as RTC clock source.
+
+ (+) LSE (low-speed external): 32.768 KHz oscillator used optionally as RTC clock source.
+
+ (+) CSS (Clock security system): once enabled, if a HSE or LSE clock failure occurs,
+ the System clock is automatically switched respectively to HSI or LSI and an interrupt
+ is generated if enabled. The interrupt is linked to the Cortex-M0+ NMI (Non-Maskable Interrupt)
+ exception vector.
+
+ (+) MCOx (microcontroller clock output): used to output LSI, HSI, LSE, HSE and SYSCLK on different pins.
+
+ [..] System, AHB and APB busses clocks configuration
+ (+) Several clock sources can be used to drive the System clock (SYSCLK): HSI,
+ HSE, LSI and LSE.
+ The AHB clock (HCLK) is derived from System clock through configurable
+ prescaler and used to clock the CPU, memory and peripherals mapped
+ on AHB bus (DMA, GPIO...).and APB (PCLK1) clock is derived
+ from AHB clock through configurable prescalers and used to clock
+ the peripherals mapped on these busses. You can use
+ "@ref HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.
+
+ -@- All the peripheral clocks are derived from the System clock (SYSCLK) except:
+
+ (+@) RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock
+ divided by 2 to 31.
+ You have to use @ref __HAL_RCC_RTC_ENABLE() and @ref HAL_RCCEx_PeriphCLKConfig() function
+ to configure this clock.
+
+ (+@) ADC: the ADC clock can be derived either from system clock or HSI
+
+ (+@) USART: the USART clock can be derived either from APB clock or HSI or LSE
+ (+@) I2C: the I2C clock can be derived either from system clock or HSI
+
+ (+@) I2S: the I2S clock can be derived either from system clock or HSI or external clock source
+
+ (+) The maximum frequency of the SYSCLK, HCLK, PCLK is 48 MHz.
+
+ @endverbatim
+
+ (++) Table 1. HCLK clock frequency.
+ (++) +------------------------------------+
+ (++) | Latency | HCLK clock |
+ (++) | | frequency (MHz) |
+ (++) | |------------------|
+ (++) | | voltage range |
+ (++) | | VDD33 2V - 3.6V |
+ (++) | | VDD12 1V - 1.32V|
+ (++) |-----------------|------------------|
+ (++) |0WS(1 CPU cycles)| HCLK <= 24 |
+ (++) |-----------------|------------------|
+ (++) |1WS(2 CPU cycles)| HCLK <= 48 |
+ (++) +------------------------------------+
+ (++)
+ * @{
+ */
+
+/**
+ * @brief Reset the RCC clock configuration to the default reset state.
+ * @note The default reset state of the clock configuration is given below:
+ * - HSI ON and used as system clock source
+ * - HSE OFF
+ * - AHB and APB prescaler set to 1.
+ * - CSS, MCO1, MCO2 OFF
+ * - All interrupts disabled
+ * @note This function does not modify the configuration of the
+ * - Peripheral clocks
+ * - LSI, LSE and RTC clocks
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RCC_DeInit(void)
+{
+ uint32_t tickstart;
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Set HSION bit to the reset value */
+ SET_BIT(RCC->CR, RCC_CR_HSION);
+
+ /* Wait till HSI is ready */
+ while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
+ {
+ if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Set HSITRIM[6:0] bits to the reset value */
+ RCC->ICSCR = RCC_ICSCR_HSITRIM_6;
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Reset CFGR register (HSI is selected as system clock source) */
+ RCC->CFGR = 0x00000000u;
+
+ /* Wait till HSI is ready */
+ while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != 0U)
+ {
+ if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Clear CR register in 2 steps: first to clear HSEON in case bypass was enabled */
+ RCC->CR &= ~RCC_CR_HSEON;
+
+ /* Wait till HSEON is disabled */
+ while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U)
+ {
+ if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Then again to HSEBYP in case bypass was enabled */
+ RCC->CR &= ~RCC_CR_HSEBYP;
+
+ /* Disable all interrupts */
+ RCC->CIER = 0x00000000u;
+
+ /* Clear all flags */
+ RCC->CICR = 0xFFFFFFFFu;
+
+ /* Update the SystemCoreClock global variable */
+ SystemCoreClock = HSI_VALUE;
+
+ /* Adapt Systick interrupt period */
+ if (HAL_InitTick(uwTickPrio) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_OK;
+ }
+}
+
+/**
+ * @brief Initialize the RCC Oscillators according to the specified parameters in the
+ * @ref RCC_OscInitTypeDef.
+ * @param RCC_OscInitStruct pointer to a @ref RCC_OscInitTypeDef structure that
+ * contains the configuration information for the RCC Oscillators.
+ * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
+ * supported by this function. User should request a transition to HSE Off
+ * first and then to HSE On or HSE Bypass.
+ * @note Transition LSE Bypass to LSE On and LSE On to LSE Bypass are not
+ * supported by this function. User should request a transition to LSE Off
+ * first and then to LSE On or LSE Bypass.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
+{
+ uint32_t tickstart;
+ uint32_t temp_sysclksrc;
+
+ /* Check Null pointer */
+ if (RCC_OscInitStruct == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
+
+ /*------------------------------- HSE Configuration ------------------------*/
+ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
+
+ temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
+
+ /* When the HSE is used as system clock in these cases it is not allowed to be disabled */
+ if (temp_sysclksrc == RCC_CFGR_SWS_HSE)
+ {
+ if ((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
+ {
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ /* Set the new HSE configuration ---------------------------------------*/
+ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
+
+ /* Check the HSE State */
+ if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
+ {
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till HSE is ready */
+ while (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
+ {
+ if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ else
+ {
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till HSE is disabled */
+ while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U)
+ {
+ if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ }
+ /*----------------------------- HSI Configuration --------------------------*/
+ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
+ assert_param(IS_RCC_HSI_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
+ assert_param(IS_RCC_HSIDIV(RCC_OscInitStruct->HSIDiv));
+
+ /* Check if HSI48 is used as system clock */
+ temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
+
+ if (temp_sysclksrc == RCC_CFGR_SWS_HSI)
+ {
+ /* When HSI is used as system clock it can not be disabled */
+ if ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
+ {
+ return HAL_ERROR;
+ }
+ /* Otherwise, just the calibration is allowed */
+ else
+ {
+ /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
+ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
+
+ if (temp_sysclksrc == RCC_CFGR_SWS_HSI)
+ {
+ /* Adjust the HSI48 division factor */
+ __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIDiv);
+
+ /* Update the SystemCoreClock global variable with HSISYS value */
+ SystemCoreClock = (HSI_VALUE / (1UL << ((READ_BIT(RCC->CR, RCC_CR_HSIDIV)) >> RCC_CR_HSIDIV_Pos)));
+ }
+
+ /* Adapt Systick interrupt period */
+ if (HAL_InitTick(uwTickPrio) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ }
+ }
+ else
+ {
+ /* Check the HSI State */
+ if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
+ {
+ /* Configure the HSI48 division factor */
+ __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIDiv);
+
+ /* Enable the Internal High Speed oscillator (HSI48). */
+ __HAL_RCC_HSI_ENABLE();
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till HSI is ready */
+ while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
+ {
+ if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
+ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
+ }
+ else
+ {
+ /* Disable the Internal High Speed oscillator (HSI48). */
+ __HAL_RCC_HSI_DISABLE();
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till HSI is disabled */
+ while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U)
+ {
+ if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ }
+ /*------------------------------ LSI Configuration -------------------------*/
+ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
+
+ /* Check if LSI is used as system clock */
+ if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_LSI)
+ {
+ /* When LSI is used as system clock it will not be disabled */
+ if ((((RCC->CSR2) & RCC_CSR2_LSIRDY) != 0U) && (RCC_OscInitStruct->LSIState == RCC_LSI_OFF))
+ {
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ /* Check the LSI State */
+ if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
+ {
+ /* Enable the Internal Low Speed oscillator (LSI). */
+ __HAL_RCC_LSI_ENABLE();
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till LSI is ready */
+ while (READ_BIT(RCC->CSR2, RCC_CSR2_LSIRDY) == 0U)
+ {
+ if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ else
+ {
+ /* Disable the Internal Low Speed oscillator (LSI). */
+ __HAL_RCC_LSI_DISABLE();
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till LSI is disabled */
+ while (READ_BIT(RCC->CSR2, RCC_CSR2_LSIRDY) != 0U)
+ {
+ if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ }
+ /*------------------------------ LSE Configuration -------------------------*/
+ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
+ {
+ FlagStatus pwrclkchanged = RESET;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
+
+ /* When the LSE is used as system clock, it is not allowed disable it */
+ if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_LSE)
+ {
+ if ((((RCC->CSR1) & RCC_CSR1_LSERDY) != 0U) && (RCC_OscInitStruct->LSEState == RCC_LSE_OFF))
+ {
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ /* Update LSE configuration in RTC Domain control register */
+ /* Set the new LSE configuration -----------------------------------------*/
+ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
+
+ /* Check the LSE State */
+ if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
+ {
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till LSE is ready */
+ while (READ_BIT(RCC->CSR1, RCC_CSR1_LSERDY) == 0U)
+ {
+ if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ else
+ {
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till LSE is disabled */
+ while (READ_BIT(RCC->CSR1, RCC_CSR1_LSERDY) != 0U)
+ {
+ if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Restore clock configuration if changed */
+ if (pwrclkchanged == SET)
+ {
+ __HAL_RCC_PWR_CLK_DISABLE();
+ }
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief Initialize the CPU, AHB and APB busses clocks according to the specified
+ * parameters in the RCC_ClkInitStruct.
+ * @param RCC_ClkInitStruct pointer to a @ref RCC_ClkInitTypeDef structure that
+ * contains the configuration information for the RCC peripheral.
+ * @param FLatency FLASH Latency
+ * This parameter can be one of the following values:
+ * @arg FLASH_LATENCY_0 FLASH 0 Latency cycle
+ * @arg FLASH_LATENCY_1 FLASH 1 Latency cycle
+ *
+ * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
+ * and updated by @ref HAL_RCC_GetHCLKFreq() function called within this function
+ *
+ * @note The HSI is used by default as system clock source after
+ * startup from Reset, wake-up from STANDBY mode. After restart from Reset,
+ * the HSI frequency is set to 12 Mhz, as HSI divider is set to 4.
+ *
+ * @note The HSI can be selected as system clock source after
+ * from STOP modes or in case of failure of the HSE used directly or indirectly
+ * as system clock (if the Clock Security System CSS is enabled).
+ *
+ * @note The LSI can be selected as system clock source after
+ * in case of failure of the LSE used directly or indirectly
+ * as system clock (if the Clock Security System LSECSS is enabled).
+ *
+ * @note A switch from one clock source to another occurs only if the target
+ * clock source is ready (clock stable after startup delay).
+ * If a clock source which is not yet ready is selected, the switch will
+ * occur when the clock source is ready.
+ *
+ * @note You can use @ref HAL_RCC_GetClockConfig() function to know which clock is
+ * currently used as system clock source.
+ *
+ * @note Depending on the device voltage range, the software has to set correctly
+ * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
+ * (for more details refer to section above "Initialization/de-initialization functions")
+ * @retval None
+ */
+HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
+{
+ uint32_t tickstart;
+
+ /* Check Null pointer */
+ if (RCC_ClkInitStruct == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));
+ assert_param(IS_FLASH_LATENCY(FLatency));
+
+ /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
+ must be correctly programmed according to the frequency of the FLASH clock
+ (HCLK) and the supply voltage of the device. */
+
+ /* Increasing the number of wait states because of higher CPU frequency */
+ if (FLatency > __HAL_FLASH_GET_LATENCY())
+ {
+ /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
+ __HAL_FLASH_SET_LATENCY(FLatency);
+
+ /* Check that the new number of wait states is taken into account to access the Flash
+ memory by polling the FLASH_ACR register */
+ tickstart = HAL_GetTick();
+
+ while ((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
+ {
+ if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /*-------------------------- HCLK Configuration --------------------------*/
+ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
+ {
+ /* Set the highest APB divider in order to ensure that we do not go through
+ a non-spec phase whatever we decrease or increase HCLK. */
+ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
+ {
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_HCLK_DIV16);
+ }
+
+ /* Set the new HCLK clock divider */
+ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
+ }
+
+ /*------------------------- SYSCLK Configuration ---------------------------*/
+ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
+ {
+ assert_param(IS_RCC_SYSCLK(RCC_ClkInitStruct->SYSCLKDivider));
+ assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
+ MODIFY_REG(RCC->CR, RCC_CR_SYSDIV, RCC_ClkInitStruct->SYSCLKDivider);
+
+ /* HSE is selected as System Clock Source */
+ if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
+ {
+ /* Check the HSE ready flag */
+ if (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
+ {
+ return HAL_ERROR;
+ }
+ }
+ /* HSI is selected as System Clock Source */
+ else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI)
+ {
+ /* Check the HSI ready flag */
+ if (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
+ {
+ return HAL_ERROR;
+ }
+ }
+ /* LSI is selected as System Clock Source */
+ else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_LSI)
+ {
+ /* Check the LSI ready flag */
+ if (READ_BIT(RCC->CSR2, RCC_CSR2_LSIRDY) == 0U)
+ {
+ return HAL_ERROR;
+ }
+ }
+ /* LSE is selected as System Clock Source */
+ else
+ {
+ /* Check the LSE ready flag */
+ if (READ_BIT(RCC->CSR1, RCC_CSR1_LSERDY) == 0U)
+ {
+ return HAL_ERROR;
+ }
+ }
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
+ {
+ if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Decreasing the number of wait states because of lower CPU frequency */
+ if (FLatency < __HAL_FLASH_GET_LATENCY())
+ {
+ /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
+ __HAL_FLASH_SET_LATENCY(FLatency);
+
+ /* Check that the new number of wait states is taken into account to access the Flash
+ memory by polling the FLASH_ACR register */
+ tickstart = HAL_GetTick();
+
+ while ((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
+ {
+ if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /*-------------------------- PCLK1 Configuration ---------------------------*/
+ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
+ {
+ assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_ClkInitStruct->APB1CLKDivider);
+ }
+
+ /* Update the SystemCoreClock global variable */
+ SystemCoreClock = (HAL_RCC_GetSysClockFreq() >> ((AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]) & 0x1FU));
+
+ /* Configure the source of time base considering new system clocks settings*/
+ return HAL_InitTick(uwTickPrio);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions
+ * @brief RCC clocks control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to:
+
+ (+) output clock to MCO pin.
+ (+) Retrieve current clock frequencies.
+ (+) Enable the Clock Security System.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Select the clock source to output on MCOx pin.
+ * @note PA8 for MCO1 and PB2 for MCO2 should be configured in alternate function mode.
+ * @param RCC_MCOx specifies the output direction for the clock source.
+ * @arg @ref RCC_MCO1 Clock source to output on MCO1 pins.
+ * @arg @ref RCC_MCO2 Clock source to output on MCO2 pins.
+ * @param RCC_MCOSource specifies the clock source to output.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_MCO1SOURCE_NOCLOCK MCO1 output disabled, no clock on MCO1
+ * @arg @ref RCC_MCO1SOURCE_SYSCLK system clock selected as MCO1 source
+ * @arg @ref RCC_MCO1SOURCE_HSI HSI clock selected as MCO1 source
+ * @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO1 sourcee
+ * @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO1 source
+ * @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO1 source
+ * @arg @ref RCC_MCO2SOURCE_NOCLOCK MCO2 output disabled, no clock on MCO2
+ * @arg @ref RCC_MCO2SOURCE_SYSCLK system clock selected as MCO2 source
+ * @arg @ref RCC_MCO2SOURCE_HSI HSI clock selected as MCO2 source
+ * @arg @ref RCC_MCO2SOURCE_HSE HSE clock selected as MCO2 sourcee
+ * @arg @ref RCC_MCO2SOURCE_LSI LSI clock selected as MCO2 source
+ * @arg @ref RCC_MCO2SOURCE_LSE LSE clock selected as MCO2 source
+ * @param RCC_MCODiv specifies the MCO prescaler.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_MCODIV_1 no division applied to MCO clock
+ * @arg @ref RCC_MCODIV_2 division by 2 applied to MCO clock
+ * @arg @ref RCC_MCODIV_4 division by 4 applied to MCO clock
+ * @arg @ref RCC_MCODIV_8 division by 8 applied to MCO clock
+ * @arg @ref RCC_MCODIV_16 division by 16 applied to MCO clock
+ * @arg @ref RCC_MCODIV_32 division by 32 applied to MCO clock
+ * @arg @ref RCC_MCODIV_64 division by 64 applied to MCO clock
+ * @arg @ref RCC_MCODIV_128 division by 128 applied to MCO clock
+ * @retval None
+ */
+void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
+{
+ GPIO_InitTypeDef gpio_initstruct;
+ uint32_t mcoindex;
+ uint32_t mco_gpio_index;
+ GPIO_TypeDef *mco_gpio_port;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_MCO(RCC_MCOx));
+
+ /* Common GPIO init parameters */
+ gpio_initstruct.Mode = GPIO_MODE_AF_PP;
+ gpio_initstruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+ gpio_initstruct.Pull = GPIO_NOPULL;
+
+ /* Get MCOx selection */
+ mcoindex = RCC_MCOx & RCC_MCO_INDEX_MASK;
+
+ /* Get MCOx GPIO Port */
+ mco_gpio_port = (GPIO_TypeDef *) RCC_GET_MCO_GPIO_PORT(RCC_MCOx);
+
+ /* MCOx Clock Enable */
+ mco_gpio_index = RCC_GET_MCO_GPIO_INDEX(RCC_MCOx);
+ SET_BIT(RCC->IOPENR, (1UL << mco_gpio_index));
+
+ /* Configure the MCOx pin in alternate function mode */
+ gpio_initstruct.Pin = RCC_GET_MCO_GPIO_PIN(RCC_MCOx);
+ gpio_initstruct.Alternate = RCC_GET_MCO_GPIO_AF(RCC_MCOx);
+ HAL_GPIO_Init(mco_gpio_port, &gpio_initstruct);
+
+ if (mcoindex == RCC_MCO1_INDEX)
+ {
+ assert_param(IS_RCC_MCODIV(RCC_MCODiv));
+ assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));
+ /* Mask MCOSEL[] and MCOPRE[] bits then set MCO clock source and prescaler */
+ LL_RCC_ConfigMCO(RCC_MCOSource, RCC_MCODiv);
+ }
+ else if (mcoindex == RCC_MCO2_INDEX)
+ {
+ assert_param(IS_RCC_MCO2DIV(RCC_MCODiv));
+ assert_param(IS_RCC_MCO2SOURCE(RCC_MCOSource));
+ /* Mask MCOSEL[] and MCOPRE[] bits then set MCO clock source and prescaler */
+ LL_RCC_ConfigMCO2(RCC_MCOSource, RCC_MCODiv);
+ }
+ else
+ {}
+}
+
+/**
+ * @brief Return the SYSCLK frequency.
+ *
+ * @note The system frequency computed by this function is not the real
+ * frequency in the chip. It is calculated based on the predefined
+ * constant and the selected clock source:
+ * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE/HSIDIV(*)
+ * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
+ * @note If SYSCLK source is LSI, function returns values based on LSI_VALUE(***)
+ * @note If SYSCLK source is LSE, function returns values based on LSE_VALUE(****)
+ * @note (*) HSI_VALUE is a constant defined in stm32c0xx_hal_conf.h file (default value
+ * 48 MHz) but the real value may vary depending on the variations
+ * in voltage and temperature.
+ * @note (**) HSE_VALUE is a constant defined in stm32c0xx_hal_conf.h file (default value
+ * 48 MHz), user has to ensure that HSE_VALUE is same as the real
+ * frequency of the crystal used. Otherwise, this function may
+ * have wrong result.
+ * @note (***) LSE_VALUE is a constant defined in stm32c0xx_hal_conf.h file (default value
+ * 32768 Hz).
+ * @note (****) LSI_VALUE is a constant defined in stm32c0xx_hal_conf.h file (default value
+ * 32000 Hz).
+ *
+ * @note The result of this function could be not correct when using fractional
+ * value for HSE crystal.
+ *
+ * @note This function can be used by the user application to compute the
+ * baudrate for the communication peripherals or configure other parameters.
+ *
+ * @note Each time SYSCLK changes, this function must be called to update the
+ * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
+ *
+ *
+ * @retval SYSCLK frequency
+ */
+uint32_t HAL_RCC_GetSysClockFreq(void)
+{
+ uint32_t hsidiv;
+ uint32_t sysclockfreq;
+
+ if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI)
+ {
+ /* HSISYS can be derived for HSI48 */
+ hsidiv = (1UL << ((READ_BIT(RCC->CR, RCC_CR_HSIDIV)) >> RCC_CR_HSIDIV_Pos));
+
+ /* HSI used as system clock source */
+ sysclockfreq = (HSI_VALUE / hsidiv);
+ }
+ else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE)
+ {
+ /* HSE used as system clock source */
+ sysclockfreq = HSE_VALUE;
+ }
+ else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_LSE)
+ {
+ /* LSE used as system clock source */
+ sysclockfreq = LSE_VALUE;
+ }
+ else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_LSI)
+ {
+ /* LSI used as system clock source */
+ sysclockfreq = LSI_VALUE;
+ }
+ else
+ {
+ sysclockfreq = 0U;
+ }
+
+ return sysclockfreq;
+}
+
+/**
+ * @brief Return the HCLK frequency.
+ * @note Each time HCLK changes, this function must be called to update the
+ * right HCLK value. Otherwise, any configuration based on this function will be incorrect.
+ *
+ * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency.
+ * @retval HCLK frequency in Hz
+ */
+uint32_t HAL_RCC_GetHCLKFreq(void)
+{
+ return SystemCoreClock;
+}
+
+/**
+ * @brief Return the PCLK1 frequency.
+ * @note Each time PCLK1 changes, this function must be called to update the
+ * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
+ * @retval PCLK1 frequency in Hz
+ */
+uint32_t HAL_RCC_GetPCLK1Freq(void)
+{
+ /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
+ return (HAL_RCC_GetHCLKFreq() >> ((APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE) >> RCC_CFGR_PPRE_Pos]) & 0x1FU));
+}
+
+/**
+ * @brief Configure the RCC_OscInitStruct according to the internal
+ * RCC configuration registers.
+ * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that
+ * will be configured.
+ * @retval None
+ */
+void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
+{
+ /* Check the parameters */
+ assert_param(RCC_OscInitStruct != (void *)NULL);
+
+ /* Set all possible values for the Oscillator type parameter ---------------*/
+ RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | \
+ RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI;
+
+ /* Get the HSE configuration -----------------------------------------------*/
+ if ((RCC->CR & RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
+ {
+ RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
+ }
+ else if ((RCC->CR & RCC_CR_HSEON) == RCC_CR_HSEON)
+ {
+ RCC_OscInitStruct->HSEState = RCC_HSE_ON;
+ }
+ else
+ {
+ RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
+ }
+
+ /* Get the HSI configuration -----------------------------------------------*/
+ if ((RCC->CR & RCC_CR_HSION) == RCC_CR_HSION)
+ {
+ RCC_OscInitStruct->HSIState = RCC_HSI_ON;
+ }
+ else
+ {
+ RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
+ }
+
+ RCC_OscInitStruct->HSICalibrationValue = ((RCC->ICSCR & RCC_ICSCR_HSITRIM) >> RCC_ICSCR_HSITRIM_Pos);
+ RCC_OscInitStruct->HSIDiv = ((RCC->CR & RCC_CR_HSIDIV) >> RCC_CR_HSIDIV_Pos);
+
+ /* Get the LSE configuration -----------------------------------------------*/
+ if ((RCC->CSR1 & RCC_CSR1_LSEBYP) == RCC_CSR1_LSEBYP)
+ {
+ RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
+ }
+ else if ((RCC->CSR1 & RCC_CSR1_LSEON) == RCC_CSR1_LSEON)
+ {
+ RCC_OscInitStruct->LSEState = RCC_LSE_ON;
+ }
+ else
+ {
+ RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
+ }
+
+ /* Get the LSI configuration -----------------------------------------------*/
+ if ((RCC->CSR2 & RCC_CSR2_LSION) == RCC_CSR2_LSION)
+ {
+ RCC_OscInitStruct->LSIState = RCC_LSI_ON;
+ }
+ else
+ {
+ RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
+ }
+
+}
+
+/**
+ * @brief Configure the RCC_ClkInitStruct according to the internal
+ * RCC configuration registers.
+ * @param RCC_ClkInitStruct Pointer to a @ref RCC_ClkInitTypeDef structure that
+ * will be configured.
+ * @param pFLatency Pointer on the Flash Latency.
+ * @retval None
+ */
+void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
+{
+ /* Check the parameters */
+ assert_param(RCC_ClkInitStruct != (void *)NULL);
+ assert_param(pFLatency != (void *)NULL);
+
+ /* Set all possible values for the Clock type parameter --------------------*/
+ RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1;
+
+ /* Get the SYSCLK configuration --------------------------------------------*/
+ RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
+
+ /* Get the HCLK configuration ----------------------------------------------*/
+ RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE);
+
+ /* Get the APB1 configuration ----------------------------------------------*/
+ RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE);
+
+
+ /* Get the Flash Wait State (Latency) configuration ------------------------*/
+ *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
+}
+
+/**
+ * @brief Enable the Clock Security System.
+ * @note If a failure is detected on the HSE oscillator clock, this oscillator
+ * is automatically disabled and an interrupt is generated to inform the
+ * software about the failure (Clock Security System Interrupt, CSSI),
+ * allowing the MCU to perform rescue operations. The CSSI is linked to
+ * the Cortex-M0+ NMI (Non-Maskable Interrupt) exception vector.
+ * @note The Clock Security System can only be cleared by reset.
+ * @retval None
+ */
+void HAL_RCC_EnableCSS(void)
+{
+ SET_BIT(RCC->CR, RCC_CR_CSSON) ;
+}
+
+/**
+ * @brief Enable the LSE Clock Security System.
+ * @note If a failure is detected on the LSE oscillator clock, this oscillator
+ * is automatically disabled and an interrupt is generated to inform the
+ * software about the failure (Clock Security System Interrupt, CSSI),
+ * allowing the MCU to perform rescue operations. The CSSI is linked to
+ * the Cortex-M0+ NMI (Non-Maskable Interrupt) exception vector.
+ * @note The LSE Clock Security System Detection bit (LSECSSD in CSR1) can only be
+ * cleared by a backup domain reset.
+ * @retval None
+ */
+void HAL_RCC_EnableLSECSS(void)
+{
+ SET_BIT(RCC->CSR1, RCC_CSR1_LSECSSON) ;
+}
+
+/**
+ * @brief Disable the LSE Clock Security System.
+ * @note After LSE failure detection, the software must disable LSECSSON
+ * @note The Clock Security System can only be cleared by reset otherwise.
+ * @retval None
+ */
+void HAL_RCC_DisableLSECSS(void)
+{
+ CLEAR_BIT(RCC->CSR1, RCC_CSR1_LSECSSON) ;
+}
+
+/**
+ * @brief Handle the RCC Clock Security System interrupt request.
+ * @note This API should be called under the NMI_Handler().
+ * @retval None
+ */
+void HAL_RCC_NMI_IRQHandler(void)
+{
+ uint32_t itflag = RCC->CIFR;
+
+ /* Clear interrupt flags related to CSS */
+ RCC->CICR = (itflag & (RCC_CIFR_CSSF | RCC_CIFR_LSECSSF));
+
+ /* Check RCC CSSF interrupt flag */
+ if ((itflag & RCC_CIFR_CSSF) != 0x00u)
+ {
+ /* RCC Clock Security System interrupt user callback */
+ HAL_RCC_CSSCallback();
+ }
+
+ /* Check RCC LSECSSF interrupt flag */
+ if ((itflag & RCC_CIFR_LSECSSF) != 0x00u)
+ {
+ /* RCC Clock Security System interrupt user callback */
+ HAL_RCC_LSECSSCallback();
+ }
+}
+
+/**
+ * @brief Handle the RCC HSE Clock Security System interrupt callback.
+ * @retval none
+ */
+__weak void HAL_RCC_CSSCallback(void)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the @ref HAL_RCC_CSSCallback should be implemented in the user file
+ */
+}
+
+/**
+ * @brief RCC LSE Clock Security System interrupt callback.
+ * @retval none
+ */
+__weak void HAL_RCC_LSECSSCallback(void)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_RCC_LSECSSCallback should be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_RCC_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.c b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.c
new file mode 100644
index 0000000000..4e81dd8503
--- /dev/null
+++ b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.c
@@ -0,0 +1,486 @@
+/**
+ ******************************************************************************
+ * @file stm32c0xx_hal_rcc_ex.c
+ * @author MCD Application Team
+ * @brief Extended RCC HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities RCC extended peripheral:
+ * + Extended Peripheral Control functions
+ * + Extended Clock management functions
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2022 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32c0xx_hal.h"
+
+/** @addtogroup STM32C0xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup RCCEx RCCEx
+ * @brief RCC Extended HAL module driver
+ * @{
+ */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private defines -----------------------------------------------------------*/
+/** @defgroup RCCEx_Private_Constants RCCEx Private Constants
+ * @{
+ */
+#define LSCO_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
+#define LSCO_GPIO_PORT GPIOA
+#define LSCO_PIN GPIO_PIN_2
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions
+ * @{
+ */
+
+/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions
+ * @brief Extended Peripheral Control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Extended Peripheral Control functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control the RCC Clocks
+ frequencies.
+ [..]
+ (@) Important note: Care must be taken when @ref HAL_RCCEx_PeriphCLKConfig() is used to
+ select the RTC clock source; as consequence RTC registers and RCC_CSR1 register are
+ set to their reset values.
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Initialize the RCC extended peripherals clocks according to the specified
+ * parameters in the @ref RCC_PeriphCLKInitTypeDef.
+ * @param PeriphClkInit pointer to a @ref RCC_PeriphCLKInitTypeDef structure that
+ * contains a field PeriphClockSelection which can be a combination of the following values:
+ * @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock
+ * @arg @ref RCC_PERIPHCLK_ADC ADC peripheral clock
+ * @arg @ref RCC_PERIPHCLK_I2C1 I2C1 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_I2S1 I2S1 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_USART1 USART1 peripheral clock
+ * @note Care must be taken when @ref HAL_RCCEx_PeriphCLKConfig() is used to select
+ * the RTC clock source: in this case the access to RTC domain is enabled.
+ *
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
+{
+ uint32_t tmpregister;
+ uint32_t tickstart;
+ HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */
+ HAL_StatusTypeDef status = HAL_OK; /* Final status */
+
+ /* Check the parameters */
+ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
+
+ /*-------------------------- RTC clock source configuration ----------------------*/
+ if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
+ {
+ FlagStatus pwrclkchanged = RESET;
+
+ /* Check for RTC Parameters used to output RTCCLK */
+ assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
+
+ /* Enable Power Clock */
+ if (__HAL_RCC_PWR_IS_CLK_DISABLED())
+ {
+ __HAL_RCC_PWR_CLK_ENABLE();
+ pwrclkchanged = SET;
+ }
+
+
+ /* Reset the RTC domain only if the RTC Clock source selection is modified from default */
+ tmpregister = READ_BIT(RCC->CSR1, RCC_CSR1_RTCSEL);
+
+ /* Reset the RTC domain only if the RTC Clock source selection is modified */
+ if ((tmpregister != RCC_RTCCLKSOURCE_NONE) && (tmpregister != PeriphClkInit->RTCClockSelection))
+ {
+ /* Store the content of CSR1 register before the reset of RTC Domain */
+ tmpregister = READ_BIT(RCC->CSR1, ~(RCC_CSR1_RTCSEL));
+ /* RTC Clock selection can be changed only if the RTC Domain is reset */
+ __HAL_RCC_BACKUPRESET_FORCE();
+ __HAL_RCC_BACKUPRESET_RELEASE();
+ /* Restore the Content of CSR1 register */
+ RCC->CSR1 = tmpregister;
+ }
+
+ /* Wait for LSE reactivation if LSE was enable prior to RTC Domain reset */
+ if (HAL_IS_BIT_SET(tmpregister, RCC_CSR1_LSEON))
+ {
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till LSE is ready */
+ while (READ_BIT(RCC->CSR1, RCC_CSR1_LSERDY) == 0U)
+ {
+ if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
+ {
+ ret = HAL_TIMEOUT;
+ break;
+ }
+ }
+ }
+
+ if (ret == HAL_OK)
+ {
+ /* Apply new RTC clock source selection */
+ __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
+ }
+ else
+ {
+ /* set overall return value */
+ status = ret;
+ }
+
+ /* Restore clock configuration if changed */
+ if (pwrclkchanged == SET)
+ {
+ __HAL_RCC_PWR_CLK_DISABLE();
+ }
+ }
+
+ /*-------------------------- USART1 clock source configuration -------------------*/
+ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
+
+ /* Configure the USART1 clock source */
+ __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
+ }
+
+ /*-------------------------- I2C1 clock source configuration ---------------------*/
+ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
+
+ /* Configure the I2C1 clock source */
+ __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
+ }
+
+ /*-------------------------- ADC clock source configuration ----------------------*/
+ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_ADCCLKSOURCE(PeriphClkInit->AdcClockSelection));
+
+ /* Configure the ADC interface clock source */
+ __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection);
+
+ }
+
+ /*-------------------------- I2S1 clock source configuration ---------------------*/
+ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_I2S1CLKSOURCE(PeriphClkInit->I2s1ClockSelection));
+
+ /* Configure the I2S1 clock source */
+ __HAL_RCC_I2S1_CONFIG(PeriphClkInit->I2s1ClockSelection);
+ }
+ /*------------------------------------ HSI Kernel clock source configuration --------------------------------------*/
+ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_HSIKER) == RCC_PERIPHCLK_HSIKER)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_HSIKERDIV(PeriphClkInit->HSIKerClockDivider));
+
+ /* Configure the HSI Kernel clock source Divider */
+ __HAL_RCC_HSIKER_CONFIG(PeriphClkInit->HSIKerClockDivider);
+ }
+ return status;
+}
+
+/**
+ * @brief Get the RCC_ClkInitStruct according to the internal RCC configuration registers.
+ * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
+ * returns the configuration information for the Extended Peripherals
+ * clocks: I2C1, I2S1, USART1, RTC, ADC,
+ * @retval None
+ */
+void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
+{
+ /* Set all possible values for the extended clock type parameter------------*/
+ PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2S1 | \
+ RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_HSIKER ;
+
+
+ /* Get the USART1 clock source ---------------------------------------------*/
+ PeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE();
+
+ /* Get the I2C1 clock source -----------------------------------------------*/
+ PeriphClkInit->I2c1ClockSelection = __HAL_RCC_GET_I2C1_SOURCE();
+
+ /* Get the RTC clock source ------------------------------------------------*/
+ PeriphClkInit->RTCClockSelection = __HAL_RCC_GET_RTC_SOURCE();
+
+ /* Get the ADC clock source -----------------------------------------------*/
+ PeriphClkInit->AdcClockSelection = __HAL_RCC_GET_ADC_SOURCE();
+
+ /* Get the I2S1 clock source -----------------------------------------------*/
+ PeriphClkInit->I2s1ClockSelection = __HAL_RCC_GET_I2S1_SOURCE();
+
+ /* Get the HSI Kernel clock divider -----------------------------------------------*/
+ PeriphClkInit->HSIKerClockDivider = __HAL_RCC_GET_HSIKER_DIVIDER();
+}
+
+/**
+ * @brief Return the peripheral clock frequency for peripherals
+ * @note Return 0 if peripheral clock identifier not managed by this API
+ * @param PeriphClk Peripheral clock identifier
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock
+ * @arg @ref RCC_PERIPHCLK_ADC ADC peripheral clock
+ * @arg @ref RCC_PERIPHCLK_I2C1 I2C1 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_I2S1 I2S1 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_USART1 USART1 peripheral clock
+ * @retval Frequency in Hz
+ */
+uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
+{
+ uint32_t frequency = 0U;
+ uint32_t srcclk;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_PERIPHCLOCK(PeriphClk));
+
+ if (PeriphClk == RCC_PERIPHCLK_RTC)
+ {
+ /* Get the current RTC source */
+ srcclk = __HAL_RCC_GET_RTC_SOURCE();
+
+ /* Check if LSE is ready and if RTC clock selection is LSE */
+ if ((HAL_IS_BIT_SET(RCC->CSR1, RCC_CSR1_LSERDY)) && (srcclk == RCC_RTCCLKSOURCE_LSE))
+ {
+ frequency = LSE_VALUE;
+ }
+ /* Check if LSI is ready and if RTC clock selection is LSI */
+ else if ((HAL_IS_BIT_SET(RCC->CSR2, RCC_CSR2_LSIRDY)) && (srcclk == RCC_RTCCLKSOURCE_LSI))
+ {
+ frequency = LSI_VALUE;
+ }
+ /* Check if HSE is ready and if RTC clock selection is HSI_DIV32*/
+ else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (srcclk == RCC_RTCCLKSOURCE_HSE_DIV32))
+ {
+ frequency = HSE_VALUE / 32U;
+ }
+ /* Clock not enabled for RTC*/
+ else
+ {
+ /* Nothing to do as frequency already initialized to 0U */
+ }
+ }
+ else
+ {
+ /* Other external peripheral clock source than RTC */
+
+ switch (PeriphClk)
+ {
+
+ case RCC_PERIPHCLK_USART1:
+ /* Get the current USART1 source */
+ srcclk = __HAL_RCC_GET_USART1_SOURCE();
+
+ if (srcclk == RCC_USART1CLKSOURCE_PCLK1) /* PCLK1 */
+ {
+ frequency = HAL_RCC_GetPCLK1Freq();
+ }
+ else if (srcclk == RCC_USART1CLKSOURCE_SYSCLK) /* SYSCLK */
+ {
+ frequency = HAL_RCC_GetSysClockFreq();
+ }
+ else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_USART1CLKSOURCE_HSIKER))
+ {
+ frequency = (HSI_VALUE / ((__HAL_RCC_GET_HSIKER_DIVIDER() >> RCC_CR_HSIKERDIV_Pos) + 1U));
+ }
+ else if ((HAL_IS_BIT_SET(RCC->CSR1, RCC_CSR1_LSERDY)) && (srcclk == RCC_USART1CLKSOURCE_LSE))
+ {
+ frequency = LSE_VALUE;
+ }
+ /* Clock not enabled for USART1 */
+ else
+ {
+ /* Nothing to do as frequency already initialized to 0U */
+ }
+ break;
+
+ case RCC_PERIPHCLK_ADC:
+
+ srcclk = __HAL_RCC_GET_ADC_SOURCE();
+
+ if (srcclk == RCC_ADCCLKSOURCE_SYSCLK)
+ {
+ frequency = HAL_RCC_GetSysClockFreq();
+ }
+ else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_ADCCLKSOURCE_HSIKER))
+ {
+ frequency = (HSI_VALUE / ((__HAL_RCC_GET_HSIKER_DIVIDER() >> RCC_CR_HSIKERDIV_Pos) + 1U));
+ }
+ /* Clock not enabled for ADC */
+ else
+ {
+ /* Nothing to do as frequency already initialized to 0U */
+ }
+ break;
+
+ case RCC_PERIPHCLK_I2C1:
+ /* Get the current I2C1 source */
+ srcclk = __HAL_RCC_GET_I2C1_SOURCE();
+
+ if (srcclk == RCC_I2C1CLKSOURCE_PCLK1)
+ {
+ frequency = HAL_RCC_GetPCLK1Freq();
+ }
+ else if (srcclk == RCC_I2C1CLKSOURCE_SYSCLK)
+ {
+ frequency = HAL_RCC_GetSysClockFreq();
+ }
+ else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2C1CLKSOURCE_HSIKER))
+ {
+ frequency = (HSI_VALUE / ((__HAL_RCC_GET_HSIKER_DIVIDER() >> RCC_CR_HSIKERDIV_Pos) + 1U));
+ }
+ /* Clock not enabled for I2C1 */
+ else
+ {
+ /* Nothing to do as frequency already initialized to 0U */
+ }
+ break;
+
+ case RCC_PERIPHCLK_I2S1:
+ /* Get the current I2S1 source */
+ srcclk = __HAL_RCC_GET_I2S1_SOURCE();
+
+ if (srcclk == RCC_I2S1CLKSOURCE_SYSCLK)
+ {
+ frequency = HAL_RCC_GetSysClockFreq();
+ }
+ else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2S1CLKSOURCE_HSIKER))
+ {
+ frequency = (HSI_VALUE / ((__HAL_RCC_GET_HSIKER_DIVIDER() >> RCC_CR_HSIKERDIV_Pos) + 1U));
+ }
+ else if (srcclk == RCC_I2S1CLKSOURCE_EXT)
+ {
+ /* External clock used.*/
+ frequency = EXTERNAL_I2S1_CLOCK_VALUE;
+ }
+ /* Clock not enabled for I2S1 */
+ else
+ {
+ /* Nothing to do as frequency already initialized to 0U */
+ }
+ break;
+
+ default:
+ break;
+ }
+ }
+
+ return (frequency);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_Exported_Functions_Group2 Extended Clock management functions
+ * @brief Extended Clock management functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Extended clock management functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control the
+ activation or deactivation of LSE CSS, Low speed clock output and
+ clock after wake-up from STOP mode.
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Select the Low Speed clock source to output on LSCO pin (PA2).
+ * @param LSCOSource specifies the Low Speed clock source to output.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_LSCOSOURCE_LSI LSI clock selected as LSCO source
+ * @arg @ref RCC_LSCOSOURCE_LSE LSE clock selected as LSCO source
+ * @retval None
+ */
+void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource)
+{
+ GPIO_InitTypeDef GPIO_InitStruct;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_LSCOSOURCE(LSCOSource));
+
+ /* LSCO Pin Clock Enable */
+ LSCO_CLK_ENABLE();
+
+ /* configure the LSCO pin in analog mode */
+ GPIO_InitStruct.Pin = LSCO_PIN;
+ GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ HAL_GPIO_Init(LSCO_GPIO_PORT, &GPIO_InitStruct);
+
+ MODIFY_REG(RCC->CSR1, RCC_CSR1_LSCOSEL | RCC_CSR1_LSCOEN, LSCOSource | RCC_CSR1_LSCOEN);
+
+}
+
+/**
+ * @brief Disable the Low Speed clock output.
+ * @retval None
+ */
+void HAL_RCCEx_DisableLSCO(void)
+{
+
+ CLEAR_BIT(RCC->CSR1, RCC_CSR1_LSCOEN);
+
+}
+
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_RCC_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rtc.c b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rtc.c
new file mode 100644
index 0000000000..00e6c07f3e
--- /dev/null
+++ b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rtc.c
@@ -0,0 +1,1527 @@
+/**
+ ******************************************************************************
+ * @file stm32c0xx_hal_rtc.c
+ * @author MCD Application Team
+ * @brief RTC HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Real-Time Clock (RTC) peripheral:
+ * + Initialization/de-initialization functions
+ * + Calendar (Time and Date) configuration
+ * + Alarms (Alarm A) configuration
+ * + TimeStamp configuration
+ * + Interrupts and flags management
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2022 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ===============================================================================
+ ##### How to use RTC Driver #####
+ ===============================================================================
+ [..]
+
+ (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour
+ format using the HAL_RTC_Init() function.
+
+ *** Time and Date configuration ***
+ ===================================
+ [..]
+ (+) To configure the RTC Calendar (Time and Date) use the HAL_RTC_SetTime()
+ and HAL_RTC_SetDate() functions.
+ (+) To read the RTC Calendar, use the HAL_RTC_GetTime() and HAL_RTC_GetDate() functions.
+
+ *** Alarm configuration ***
+ ===========================
+ [..]
+ (+) To configure the RTC Alarm use the HAL_RTC_SetAlarm() function.
+ You can also configure the RTC Alarm with interrupt mode using the
+ HAL_RTC_SetAlarm_IT() function.
+ (+) To read the RTC Alarm, use the HAL_RTC_GetAlarm() function.
+
+ ##### RTC and low power modes #####
+ ==================================================================
+ [..] The MCU can be woken up from a low power mode by an RTC alternate
+ function.
+ [..] The RTC alternate functions are the RTC alarms (Alarm A) and RTC time stamp event detection.
+ These RTC alternate functions can wake up the system from the Stop and
+ Standby low power modes.
+ [..] The system can also wake up from low power modes without depending
+ on an external interrupt (Auto-wakeup mode), by using the RTC alarm events.
+ [..] The RTC provides a programmable time base for waking up from the
+ Stop or Standby mode at regular intervals.
+ Wakeup from STOP and STANDBY modes is possible only when the RTC clock source
+ is LSE or LSI.
+
+ *** Callback registration ***
+ =============================================
+
+ [..]
+ The compilation define USE_RTC_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+ Use Function @ref HAL_RTC_RegisterCallback() to register an interrupt callback.
+
+ [..]
+ Function @ref HAL_RTC_RegisterCallback() allows to register following callbacks:
+ (+) AlarmAEventCallback : RTC Alarm A Event callback.
+ (+) : RTC TimeStamp Event callback.
+ (+) MspInitCallback : RTC MspInit.
+ (+) MspDeInitCaTimeStampEventCallbackllback : RTC MspDeInit.
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+ Use function @ref HAL_RTC_UnRegisterCallback() to reset a callback to the default
+ weak function.
+ @ref HAL_RTC_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+ and the Callback ID.
+ This function allows to reset following callbacks:
+ (+) AlarmAEventCallback : RTC Alarm A Event callback.
+ (+) TimeStampEventCallback : RTC TimeStamp Event callback.
+ (+) MspInitCallback : RTC MspInit callback.
+ (+) MspDeInitCallback : RTC MspDeInit callback.
+
+ [..]
+ By default, after the @ref HAL_RTC_Init() and when the state is HAL_RTC_STATE_RESET,
+ all callbacks are set to the corresponding weak functions :
+ examples @ref AlarmAEventCallback(), @ref TimeStampEventCallback().
+ Exception done for MspInit and MspDeInit callbacks that are reset to the legacy weak function
+ in the @ref HAL_RTC_Init()/@ref HAL_RTC_DeInit() only when these callbacks are null
+ (not registered beforehand).
+ If not, MspInit or MspDeInit are not null, @ref HAL_RTC_Init()/@ref HAL_RTC_DeInit()
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
+
+ [..]
+ Callbacks can be registered/unregistered in HAL_RTC_STATE_READY state only.
+ Exception done MspInit/MspDeInit that can be registered/unregistered
+ in HAL_RTC_STATE_READY or HAL_RTC_STATE_RESET state,
+ thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+ In that case first register the MspInit/MspDeInit user callbacks
+ using @ref HAL_RTC_RegisterCallback() before calling @ref HAL_RTC_DeInit()
+ or @ref HAL_RTC_Init() function.
+
+ [..]
+ When The compilation define USE_HAL_RTC_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registration feature is not available and all callbacks
+ are set to the corresponding weak functions.
+
+ @endverbatim
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32c0xx_hal.h"
+
+/** @addtogroup STM32C0xx_HAL_Driver
+ * @{
+ */
+
+
+/** @addtogroup RTC
+ * @brief RTC HAL module driver
+ * @{
+ */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup RTC_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup RTC_Exported_Functions_Group1
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to initialize and configure the
+ RTC Prescaler (Synchronous and Asynchronous), RTC Hour format, disable
+ RTC registers Write protection, enter and exit the RTC initialization mode,
+ RTC registers synchronization check and reference clock detection enable.
+ (#) The RTC Prescaler is programmed to generate the RTC 1Hz time base.
+ It is split into 2 programmable prescalers to minimize power consumption.
+ (++) A 7-bit asynchronous prescaler and a 15-bit synchronous prescaler.
+ (++) When both prescalers are used, it is recommended to configure the
+ asynchronous prescaler to a high value to minimize power consumption.
+ (#) All RTC registers are Write protected. Writing to the RTC registers
+ is enabled by writing a key into the Write Protection register, RTC_WPR.
+ (#) To configure the RTC Calendar, user application should enter
+ initialization mode. In this mode, the calendar counter is stopped
+ and its value can be updated. When the initialization sequence is
+ complete, the calendar restarts counting after 4 RTCCLK cycles.
+ (#) To read the calendar through the shadow registers after Calendar
+ initialization, calendar update or after wakeup from low power modes
+ the software must first clear the RSF flag. The software must then
+ wait until it is set again before reading the calendar, which means
+ that the calendar registers have been correctly copied into the
+ RTC_TR and RTC_DR shadow registers.The HAL_RTC_WaitForSynchro() function
+ implements the above software sequence (RSF clear and RSF check).
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initialize the RTC peripheral
+ * @param hrtc RTC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc)
+{
+ HAL_StatusTypeDef status = HAL_ERROR;
+
+ /* Check the RTC peripheral state */
+ if (hrtc != NULL)
+ {
+ /* Check the parameters */
+ assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance));
+ assert_param(IS_RTC_HOUR_FORMAT(hrtc->Init.HourFormat));
+ assert_param(IS_RTC_ASYNCH_PREDIV(hrtc->Init.AsynchPrediv));
+ assert_param(IS_RTC_SYNCH_PREDIV(hrtc->Init.SynchPrediv));
+ assert_param(IS_RTC_OUTPUT(hrtc->Init.OutPut));
+ assert_param(IS_RTC_OUTPUT_REMAP(hrtc->Init.OutPutRemap));
+ assert_param(IS_RTC_OUTPUT_POL(hrtc->Init.OutPutPolarity));
+ assert_param(IS_RTC_OUTPUT_TYPE(hrtc->Init.OutPutType));
+ assert_param(IS_RTC_OUTPUT_PULLUP(hrtc->Init.OutPutPullUp));
+
+ if (hrtc->State == HAL_RTC_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hrtc->Lock = HAL_UNLOCKED;
+
+
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+ hrtc->AlarmAEventCallback = HAL_RTC_AlarmAEventCallback; /* Legacy weak AlarmAEventCallback */
+ hrtc->TimeStampEventCallback = HAL_RTCEx_TimeStampEventCallback; /* Legacy weak TimeStampEventCallback */
+
+ if (hrtc->MspInitCallback == NULL)
+ {
+ hrtc->MspInitCallback = HAL_RTC_MspInit;
+ }
+ /* Init the low level hardware */
+ hrtc->MspInitCallback(hrtc);
+
+ if (hrtc->MspDeInitCallback == NULL)
+ {
+ hrtc->MspDeInitCallback = HAL_RTC_MspDeInit;
+ }
+#else
+ /* Initialize RTC MSP */
+ HAL_RTC_MspInit(hrtc);
+#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */
+ }
+
+ /* Set RTC state */
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* Enter Initialization mode */
+ status = RTC_EnterInitMode(hrtc);
+ if (status == HAL_OK)
+ {
+ /* Clear RTC_CR FMT, OSEL and POL Bits */
+ hrtc->Instance->CR &= ~(RTC_CR_FMT | RTC_CR_POL | RTC_CR_OSEL);
+ /* Set RTC_CR register */
+ hrtc->Instance->CR |= (hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity);
+
+ /* Configure the RTC PRER */
+ hrtc->Instance->PRER = (hrtc->Init.SynchPrediv);
+ hrtc->Instance->PRER |= (hrtc->Init.AsynchPrediv << RTC_PRER_PREDIV_A_Pos);
+
+ /* Exit Initialization mode */
+ status = RTC_ExitInitMode(hrtc);
+ if (status == HAL_OK)
+ {
+ hrtc->Instance->CR &= ~(RTC_CR_TAMPALRM_PU | RTC_CR_TAMPALRM_TYPE | RTC_CR_OUT2EN);
+ hrtc->Instance->CR |= (hrtc->Init.OutPutPullUp | hrtc->Init.OutPutType | hrtc->Init.OutPutRemap);
+ }
+ }
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ if (status == HAL_OK)
+ {
+ hrtc->State = HAL_RTC_STATE_READY;
+ }
+ }
+
+ return status;
+}
+
+/**
+ * @brief DeInitialize the RTC peripheral.
+ * @note This function does not reset the RTC Backup Data registers.
+ * @param hrtc RTC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc)
+{
+ HAL_StatusTypeDef status;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance));
+
+ /* Set RTC state */
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* Enter Initialization mode */
+ status = RTC_EnterInitMode(hrtc);
+ if (status == HAL_OK)
+ {
+ /* Reset TR, DR and CR registers */
+ hrtc->Instance->TR = 0x00000000U;
+ hrtc->Instance->DR = ((uint32_t)(RTC_DR_WDU_0 | RTC_DR_MU_0 | RTC_DR_DU_0));
+
+ /* Reset all RTC CR register bits */
+ hrtc->Instance->CR &= 0x00000000U;
+ hrtc->Instance->PRER = ((uint32_t)(RTC_PRER_PREDIV_A | 0x000000FFU));
+ hrtc->Instance->ALRMAR = 0x00000000U;
+ hrtc->Instance->SHIFTR = 0x00000000U;
+ hrtc->Instance->CALR = 0x00000000U;
+ hrtc->Instance->ALRMASSR = 0x00000000U;
+
+ /* Exit initialization mode */
+ status = RTC_ExitInitMode(hrtc);
+ }
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ if (status == HAL_OK)
+ {
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+ if (hrtc->MspDeInitCallback == NULL)
+ {
+ hrtc->MspDeInitCallback = HAL_RTC_MspDeInit;
+ }
+
+ /* DeInit the low level hardware: CLOCK, NVIC.*/
+ hrtc->MspDeInitCallback(hrtc);
+
+#else
+ /* De-Initialize RTC MSP */
+ HAL_RTC_MspDeInit(hrtc);
+#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */
+
+ hrtc->State = HAL_RTC_STATE_RESET;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hrtc);
+
+ return status;
+}
+
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a User RTC Callback
+ * To be used instead of the weak predefined callback
+ * @param hrtc RTC handle
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_RTC_ALARM_A_EVENT_CB_ID Alarm A Event Callback ID
+ * @arg @ref HAL_RTC_TIMESTAMP_EVENT_CB_ID TimeStamp Event Callback ID
+ * @arg @ref HAL_RTC_MSPINIT_CB_ID Msp Init callback ID
+ * @arg @ref HAL_RTC_MSPDEINIT_CB_ID Msp DeInit callback ID
+ * @param pCallback pointer to the Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTC_RegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID,
+ pRTC_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hrtc);
+
+ if (HAL_RTC_STATE_READY == hrtc->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_RTC_ALARM_A_EVENT_CB_ID :
+ hrtc->AlarmAEventCallback = pCallback;
+ break;
+
+ case HAL_RTC_TIMESTAMP_EVENT_CB_ID :
+ hrtc->TimeStampEventCallback = pCallback;
+ break;
+
+ case HAL_RTC_MSPINIT_CB_ID :
+ hrtc->MspInitCallback = pCallback;
+ break;
+
+ case HAL_RTC_MSPDEINIT_CB_ID :
+ hrtc->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_RTC_STATE_RESET == hrtc->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_RTC_MSPINIT_CB_ID :
+ hrtc->MspInitCallback = pCallback;
+ break;
+
+ case HAL_RTC_MSPDEINIT_CB_ID :
+ hrtc->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hrtc);
+
+ return status;
+}
+
+/**
+ * @brief Unregister an RTC Callback
+ * RTC callback is redirected to the weak predefined callback
+ * @param hrtc RTC handle
+ * @param CallbackID ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_RTC_ALARM_A_EVENT_CB_ID Alarm A Event Callback ID
+ * @arg @ref HAL_RTC_TIMESTAMP_EVENT_CB_ID TimeStamp Event Callback ID
+ * @arg @ref HAL_RTC_MSPINIT_CB_ID Msp Init callback ID
+ * @arg @ref HAL_RTC_MSPDEINIT_CB_ID Msp DeInit callback ID
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTC_UnRegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hrtc);
+
+ if (HAL_RTC_STATE_READY == hrtc->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_RTC_ALARM_A_EVENT_CB_ID :
+ hrtc->AlarmAEventCallback = HAL_RTC_AlarmAEventCallback; /* Legacy weak AlarmAEventCallback */
+ break;
+
+ case HAL_RTC_TIMESTAMP_EVENT_CB_ID :
+ hrtc->TimeStampEventCallback = HAL_RTCEx_TimeStampEventCallback; /* Legacy weak TimeStampEventCallback */
+ break;
+
+ case HAL_RTC_MSPINIT_CB_ID :
+ hrtc->MspInitCallback = HAL_RTC_MspInit;
+ break;
+
+ case HAL_RTC_MSPDEINIT_CB_ID :
+ hrtc->MspDeInitCallback = HAL_RTC_MspDeInit;
+ break;
+
+ default :
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_RTC_STATE_RESET == hrtc->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_RTC_MSPINIT_CB_ID :
+ hrtc->MspInitCallback = HAL_RTC_MspInit;
+ break;
+
+ case HAL_RTC_MSPDEINIT_CB_ID :
+ hrtc->MspDeInitCallback = HAL_RTC_MspDeInit;
+ break;
+
+ default :
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hrtc);
+
+ return status;
+}
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
+
+/**
+ * @brief Initialize the RTC MSP.
+ * @param hrtc RTC handle
+ * @retval None
+ */
+__weak void HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hrtc);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_RTC_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitialize the RTC MSP.
+ * @param hrtc RTC handle
+ * @retval None
+ */
+__weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hrtc);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_RTC_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Exported_Functions_Group2
+ * @brief RTC Time and Date functions
+ *
+@verbatim
+ ===============================================================================
+ ##### RTC Time and Date functions #####
+ ===============================================================================
+
+ [..] This section provides functions allowing to configure Time and Date features
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Set RTC current time.
+ * @param hrtc RTC handle
+ * @param sTime Pointer to Time structure
+ * @param Format Specifies the format of the entered parameters.
+ * This parameter can be one of the following values:
+ * @arg RTC_FORMAT_BIN: Binary data format
+ * @arg RTC_FORMAT_BCD: BCD data format
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
+{
+ uint32_t tmpreg;
+ HAL_StatusTypeDef status;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_FORMAT(Format));
+ assert_param(IS_RTC_DAYLIGHT_SAVING(sTime->DayLightSaving));
+ assert_param(IS_RTC_STORE_OPERATION(sTime->StoreOperation));
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* Enter Initialization mode */
+ status = RTC_EnterInitMode(hrtc);
+ if (status == HAL_OK)
+ {
+ if (Format == RTC_FORMAT_BIN)
+ {
+ if ((hrtc->Instance->CR & RTC_CR_FMT) != 0U)
+ {
+ assert_param(IS_RTC_HOUR12(sTime->Hours));
+ assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat));
+ }
+ else
+ {
+ sTime->TimeFormat = 0x00U;
+ assert_param(IS_RTC_HOUR24(sTime->Hours));
+ }
+ assert_param(IS_RTC_MINUTES(sTime->Minutes));
+ assert_param(IS_RTC_SECONDS(sTime->Seconds));
+
+ tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(sTime->Hours) << RTC_TR_HU_Pos) | \
+ ((uint32_t)RTC_ByteToBcd2(sTime->Minutes) << RTC_TR_MNU_Pos) | \
+ ((uint32_t)RTC_ByteToBcd2(sTime->Seconds) << RTC_TR_SU_Pos) | \
+ (((uint32_t)sTime->TimeFormat) << RTC_TR_PM_Pos));
+ }
+ else
+ {
+ if ((hrtc->Instance->CR & RTC_CR_FMT) != 0U)
+ {
+ assert_param(IS_RTC_HOUR12(RTC_Bcd2ToByte(sTime->Hours)));
+ assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat));
+ }
+ else
+ {
+ sTime->TimeFormat = 0x00U;
+ assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sTime->Hours)));
+ }
+ assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sTime->Minutes)));
+ assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sTime->Seconds)));
+ tmpreg = (((uint32_t)(sTime->Hours) << RTC_TR_HU_Pos) | \
+ ((uint32_t)(sTime->Minutes) << RTC_TR_MNU_Pos) | \
+ ((uint32_t)(sTime->Seconds) << RTC_TR_SU_Pos) | \
+ ((uint32_t)(sTime->TimeFormat) << RTC_TR_PM_Pos));
+ }
+
+ /* Set the RTC_TR register */
+ hrtc->Instance->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK);
+
+ /* Clear the bits to be configured */
+ hrtc->Instance->CR &= ((uint32_t)~RTC_CR_BKP);
+
+ /* Configure the RTC_CR register */
+ hrtc->Instance->CR |= (uint32_t)(sTime->DayLightSaving | sTime->StoreOperation);
+
+ /* Exit Initialization mode */
+ status = RTC_ExitInitMode(hrtc);
+ }
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ if (status == HAL_OK)
+ {
+ hrtc->State = HAL_RTC_STATE_READY;
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return status;
+}
+
+/**
+ * @brief Get RTC current time.
+ * @note You can use SubSeconds and SecondFraction (sTime structure fields returned) to convert SubSeconds
+ * value in second fraction ratio with time unit following generic formula:
+ * Second fraction ratio * time_unit= [(SecondFraction-SubSeconds)/(SecondFraction+1)] * time_unit
+ * This conversion can be performed only if no shift operation is pending (ie. SHFP=0) when PREDIV_S >= SS
+ * @note You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values
+ * in the higher-order calendar shadow registers to ensure consistency between the time and date values.
+ * Reading RTC current time locks the values in calendar shadow registers until Current date is read
+ * to ensure consistency between the time and date values.
+ * @param hrtc RTC handle
+ * @param sTime Pointer to Time structure with Hours, Minutes and Seconds fields returned
+ * with input format (BIN or BCD), also SubSeconds field returning the
+ * RTC_SSR register content and SecondFraction field the Synchronous pre-scaler
+ * factor to be used for second fraction ratio computation.
+ * @param Format Specifies the format of the entered parameters.
+ * This parameter can be one of the following values:
+ * @arg RTC_FORMAT_BIN: Binary data format
+ * @arg RTC_FORMAT_BCD: BCD data format
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
+{
+ uint32_t tmpreg;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_FORMAT(Format));
+
+ /* Get subseconds structure field from the corresponding register*/
+ sTime->SubSeconds = (uint32_t)(hrtc->Instance->SSR);
+
+ /* Get SecondFraction structure field from the corresponding register field*/
+ sTime->SecondFraction = (uint32_t)(hrtc->Instance->PRER & RTC_PRER_PREDIV_S);
+
+ /* Get the TR register */
+ tmpreg = (uint32_t)(hrtc->Instance->TR & RTC_TR_RESERVED_MASK);
+
+ /* Fill the structure fields with the read parameters */
+ sTime->Hours = (uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> RTC_TR_HU_Pos);
+ sTime->Minutes = (uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >> RTC_TR_MNU_Pos);
+ sTime->Seconds = (uint8_t)((tmpreg & (RTC_TR_ST | RTC_TR_SU)) >> RTC_TR_SU_Pos);
+ sTime->TimeFormat = (uint8_t)((tmpreg & (RTC_TR_PM)) >> RTC_TR_PM_Pos);
+
+ /* Check the input parameters format */
+ if (Format == RTC_FORMAT_BIN)
+ {
+ /* Convert the time structure parameters to Binary format */
+ sTime->Hours = (uint8_t)RTC_Bcd2ToByte(sTime->Hours);
+ sTime->Minutes = (uint8_t)RTC_Bcd2ToByte(sTime->Minutes);
+ sTime->Seconds = (uint8_t)RTC_Bcd2ToByte(sTime->Seconds);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Set RTC current date.
+ * @param hrtc RTC handle
+ * @param sDate Pointer to date structure
+ * @param Format specifies the format of the entered parameters.
+ * This parameter can be one of the following values:
+ * @arg RTC_FORMAT_BIN: Binary data format
+ * @arg RTC_FORMAT_BCD: BCD data format
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
+{
+ uint32_t datetmpreg;
+ HAL_StatusTypeDef status;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_FORMAT(Format));
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ if ((Format == RTC_FORMAT_BIN) && ((sDate->Month & 0x10U) == 0x10U))
+ {
+ sDate->Month = (uint8_t)((sDate->Month & (uint8_t)~(0x10U)) + (uint8_t)0x0AU);
+ }
+
+ assert_param(IS_RTC_WEEKDAY(sDate->WeekDay));
+
+ if (Format == RTC_FORMAT_BIN)
+ {
+ assert_param(IS_RTC_YEAR(sDate->Year));
+ assert_param(IS_RTC_MONTH(sDate->Month));
+ assert_param(IS_RTC_DATE(sDate->Date));
+
+ datetmpreg = (((uint32_t)RTC_ByteToBcd2(sDate->Year) << RTC_DR_YU_Pos) | \
+ ((uint32_t)RTC_ByteToBcd2(sDate->Month) << RTC_DR_MU_Pos) | \
+ ((uint32_t)RTC_ByteToBcd2(sDate->Date) << RTC_DR_DU_Pos) | \
+ ((uint32_t)sDate->WeekDay << RTC_DR_WDU_Pos));
+ }
+ else
+ {
+ assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(sDate->Year)));
+ assert_param(IS_RTC_MONTH(RTC_Bcd2ToByte(sDate->Month)));
+ assert_param(IS_RTC_DATE(RTC_Bcd2ToByte(sDate->Date)));
+
+ datetmpreg = ((((uint32_t)sDate->Year) << RTC_DR_YU_Pos) | \
+ (((uint32_t)sDate->Month) << RTC_DR_MU_Pos) | \
+ (((uint32_t)sDate->Date) << RTC_DR_DU_Pos) | \
+ (((uint32_t)sDate->WeekDay) << RTC_DR_WDU_Pos));
+ }
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* Enter Initialization mode */
+ status = RTC_EnterInitMode(hrtc);
+ if (status == HAL_OK)
+ {
+ /* Set the RTC_DR register */
+ hrtc->Instance->DR = (uint32_t)(datetmpreg & RTC_DR_RESERVED_MASK);
+
+ /* Exit Initialization mode */
+ status = RTC_ExitInitMode(hrtc);
+ }
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ if (status == HAL_OK)
+ {
+ hrtc->State = HAL_RTC_STATE_READY;
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return status;
+}
+
+/**
+ * @brief Get RTC current date.
+ * @note You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values
+ * in the higher-order calendar shadow registers to ensure consistency between the time and date values.
+ * Reading RTC current time locks the values in calendar shadow registers until Current date is read.
+ * @param hrtc RTC handle
+ * @param sDate Pointer to Date structure
+ * @param Format Specifies the format of the entered parameters.
+ * This parameter can be one of the following values:
+ * @arg RTC_FORMAT_BIN: Binary data format
+ * @arg RTC_FORMAT_BCD: BCD data format
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
+{
+ uint32_t datetmpreg;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_FORMAT(Format));
+
+ /* Get the DR register */
+ datetmpreg = (uint32_t)(hrtc->Instance->DR & RTC_DR_RESERVED_MASK);
+
+ /* Fill the structure fields with the read parameters */
+ sDate->Year = (uint8_t)((datetmpreg & (RTC_DR_YT | RTC_DR_YU)) >> RTC_DR_YU_Pos);
+ sDate->Month = (uint8_t)((datetmpreg & (RTC_DR_MT | RTC_DR_MU)) >> RTC_DR_MU_Pos);
+ sDate->Date = (uint8_t)((datetmpreg & (RTC_DR_DT | RTC_DR_DU)) >> RTC_DR_DU_Pos);
+ sDate->WeekDay = (uint8_t)((datetmpreg & (RTC_DR_WDU)) >> RTC_DR_WDU_Pos);
+
+ /* Check the input parameters format */
+ if (Format == RTC_FORMAT_BIN)
+ {
+ /* Convert the date structure parameters to Binary format */
+ sDate->Year = (uint8_t)RTC_Bcd2ToByte(sDate->Year);
+ sDate->Month = (uint8_t)RTC_Bcd2ToByte(sDate->Month);
+ sDate->Date = (uint8_t)RTC_Bcd2ToByte(sDate->Date);
+ }
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Exported_Functions_Group3
+ * @brief RTC Alarm functions
+ *
+@verbatim
+ ===============================================================================
+ ##### RTC Alarm functions #####
+ ===============================================================================
+
+ [..] This section provides functions allowing to configure Alarm feature
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Set the specified RTC Alarm.
+ * @param hrtc RTC handle
+ * @param sAlarm Pointer to Alarm structure
+ * @param Format Specifies the format of the entered parameters.
+ * This parameter can be one of the following values:
+ * @arg RTC_FORMAT_BIN: Binary data format
+ * @arg RTC_FORMAT_BCD: BCD data format
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
+{
+ uint32_t tickstart;
+ uint32_t tmpreg;
+ uint32_t subsecondtmpreg;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_FORMAT(Format));
+ assert_param(IS_RTC_ALARM(sAlarm->Alarm));
+ assert_param(IS_RTC_ALARM_MASK(sAlarm->AlarmMask));
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel));
+ assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds));
+ assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask));
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ if (Format == RTC_FORMAT_BIN)
+ {
+ if ((hrtc->Instance->CR & RTC_CR_FMT) != 0U)
+ {
+ assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours));
+ assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
+ }
+ else
+ {
+ sAlarm->AlarmTime.TimeFormat = 0x00U;
+ assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours));
+ }
+ assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes));
+ assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds));
+
+ if (sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
+ {
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(sAlarm->AlarmDateWeekDay));
+ }
+ else
+ {
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay));
+ }
+
+ tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \
+ ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << RTC_ALRMAR_MNU_Pos) | \
+ ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds) << RTC_ALRMAR_SU_Pos) | \
+ ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_ALRMAR_PM_Pos) | \
+ ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << RTC_ALRMAR_DU_Pos) | \
+ ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
+ ((uint32_t)sAlarm->AlarmMask));
+ }
+ else
+ {
+ if ((hrtc->Instance->CR & RTC_CR_FMT) != 0U)
+ {
+ assert_param(IS_RTC_HOUR12(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
+ assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
+ }
+ else
+ {
+ sAlarm->AlarmTime.TimeFormat = 0x00U;
+ assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
+ }
+
+ assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes)));
+ assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds)));
+
+ if (sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
+ {
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay)));
+ }
+ else
+ {
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay)));
+ }
+
+ tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \
+ ((uint32_t)(sAlarm->AlarmTime.Minutes) << RTC_ALRMAR_MNU_Pos) | \
+ ((uint32_t)(sAlarm->AlarmTime.Seconds) << RTC_ALRMAR_SU_Pos) | \
+ ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_ALRMAR_PM_Pos) | \
+ ((uint32_t)(sAlarm->AlarmDateWeekDay) << RTC_ALRMAR_DU_Pos) | \
+ ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
+ ((uint32_t)sAlarm->AlarmMask));
+ }
+
+ /* Configure the Alarm A Sub Second registers */
+ subsecondtmpreg = (uint32_t)((uint32_t)(sAlarm->AlarmTime.SubSeconds) | (uint32_t)(sAlarm->AlarmSubSecondMask));
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* Configure the Alarm register */
+ if (sAlarm->Alarm == RTC_ALARM_A)
+ {
+ /* Disable the Alarm A interrupt */
+ __HAL_RTC_ALARMA_DISABLE(hrtc);
+
+ /* In case of interrupt mode is used, the interrupt source must disabled */
+ __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA);
+
+ tickstart = HAL_GetTick();
+ /* Wait till RTC ALRAWF flag is set and if Time out is reached exit */
+ while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == 0U)
+ {
+ if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_TIMEOUT;
+ }
+ }
+
+ hrtc->Instance->ALRMAR = (uint32_t)tmpreg;
+ /* Configure the Alarm A Sub Second register */
+ hrtc->Instance->ALRMASSR = subsecondtmpreg;
+ /* Configure the Alarm state: Enable Alarm */
+ __HAL_RTC_ALARMA_ENABLE(hrtc);
+ }
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Set the specified RTC Alarm with Interrupt.
+ * @note The Alarm register can only be written when the corresponding Alarm
+ * is disabled (Use the HAL_RTC_DeactivateAlarm()).
+ * @note The HAL_RTC_SetTime() must be called before enabling the Alarm feature.
+ * @param hrtc RTC handle
+ * @param sAlarm Pointer to Alarm structure
+ * @param Format Specifies the format of the entered parameters.
+ * This parameter can be one of the following values:
+ * @arg RTC_FORMAT_BIN: Binary data format
+ * @arg RTC_FORMAT_BCD: BCD data format
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
+{
+ uint32_t tickstart;
+ uint32_t tmpreg;
+ uint32_t subsecondtmpreg;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_FORMAT(Format));
+ assert_param(IS_RTC_ALARM(sAlarm->Alarm));
+ assert_param(IS_RTC_ALARM_MASK(sAlarm->AlarmMask));
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel));
+ assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds));
+ assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask));
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ if (Format == RTC_FORMAT_BIN)
+ {
+ if ((hrtc->Instance->CR & RTC_CR_FMT) != 0U)
+ {
+ assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours));
+ assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
+ }
+ else
+ {
+ sAlarm->AlarmTime.TimeFormat = 0x00U;
+ assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours));
+ }
+ assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes));
+ assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds));
+
+ if (sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
+ {
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(sAlarm->AlarmDateWeekDay));
+ }
+ else
+ {
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay));
+ }
+ tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \
+ ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << RTC_ALRMAR_MNU_Pos) | \
+ ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds) << RTC_ALRMAR_SU_Pos) | \
+ ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_ALRMAR_PM_Pos) | \
+ ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << RTC_ALRMAR_DU_Pos) | \
+ ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
+ ((uint32_t)sAlarm->AlarmMask));
+ }
+ else
+ {
+ if ((hrtc->Instance->CR & RTC_CR_FMT) != 0U)
+ {
+ assert_param(IS_RTC_HOUR12(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
+ assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
+ }
+ else
+ {
+ sAlarm->AlarmTime.TimeFormat = 0x00U;
+ assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
+ }
+
+ assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes)));
+ assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds)));
+
+ if (sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
+ {
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay)));
+ }
+ else
+ {
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay)));
+ }
+ tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \
+ ((uint32_t)(sAlarm->AlarmTime.Minutes) << RTC_ALRMAR_MNU_Pos) | \
+ ((uint32_t)(sAlarm->AlarmTime.Seconds) << RTC_ALRMAR_SU_Pos) | \
+ ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_ALRMAR_PM_Pos) | \
+ ((uint32_t)(sAlarm->AlarmDateWeekDay) << RTC_ALRMAR_DU_Pos) | \
+ ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
+ ((uint32_t)sAlarm->AlarmMask));
+ }
+ /* Configure the Alarm A or Alarm B Sub Second registers */
+ subsecondtmpreg = (uint32_t)((uint32_t)(sAlarm->AlarmTime.SubSeconds) | (uint32_t)(sAlarm->AlarmSubSecondMask));
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* Configure the Alarm register */
+ if (sAlarm->Alarm == RTC_ALARM_A)
+ {
+ /* Disable the Alarm A interrupt */
+ __HAL_RTC_ALARMA_DISABLE(hrtc);
+
+ /* Clear flag alarm A */
+ __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);
+
+ tickstart = HAL_GetTick();
+ /* Wait till RTC ALRAWF flag is set and if Time out is reached exit */
+ while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == 0U)
+ {
+ if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_TIMEOUT;
+ }
+ }
+
+ hrtc->Instance->ALRMAR = (uint32_t)tmpreg;
+ /* Configure the Alarm A Sub Second register */
+ hrtc->Instance->ALRMASSR = subsecondtmpreg;
+ /* Configure the Alarm state: Enable Alarm */
+ __HAL_RTC_ALARMA_ENABLE(hrtc);
+ /* Configure the Alarm interrupt */
+ __HAL_RTC_ALARM_ENABLE_IT(hrtc, RTC_IT_ALRA);
+ }
+
+ /* RTC Alarm Interrupt Configuration: EXTI configuration */
+ __HAL_RTC_ALARM_EXTI_ENABLE_IT();
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Deactivate the specified RTC Alarm.
+ * @param hrtc RTC handle
+ * @param Alarm Specifies the Alarm.
+ * This parameter can be one of the following values:
+ * @arg RTC_ALARM_A: AlarmA
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm)
+{
+ uint32_t tickstart;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_ALARM(Alarm));
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ if (Alarm == RTC_ALARM_A)
+ {
+ /* AlarmA */
+ __HAL_RTC_ALARMA_DISABLE(hrtc);
+
+ /* In case of interrupt mode is used, the interrupt source must disabled */
+ __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA);
+
+ tickstart = HAL_GetTick();
+
+ /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */
+ while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == 0U)
+ {
+ if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Get the RTC Alarm value and masks.
+ * @param hrtc RTC handle
+ * @param sAlarm Pointer to Date structure
+ * @param Alarm Specifies the Alarm.
+ * This parameter can be one of the following values:
+ * @arg RTC_ALARM_A: AlarmA
+ * @param Format Specifies the format of the entered parameters.
+ * This parameter can be one of the following values:
+ * @arg RTC_FORMAT_BIN: Binary data format
+ * @arg RTC_FORMAT_BCD: BCD data format
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format)
+{
+ uint32_t tmpreg;
+ uint32_t subsecondtmpreg;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_FORMAT(Format));
+ assert_param(IS_RTC_ALARM(Alarm));
+
+ if (Alarm == RTC_ALARM_A)
+ {
+ /* AlarmA */
+ sAlarm->Alarm = RTC_ALARM_A;
+
+ tmpreg = (uint32_t)(hrtc->Instance->ALRMAR);
+ subsecondtmpreg = (uint32_t)((hrtc->Instance->ALRMASSR) & RTC_ALRMASSR_SS);
+
+ /* Fill the structure with the read parameters */
+ sAlarm->AlarmTime.Hours = (uint8_t)((tmpreg & (RTC_ALRMAR_HT | RTC_ALRMAR_HU)) >> RTC_ALRMAR_HU_Pos);
+ sAlarm->AlarmTime.Minutes = (uint8_t)((tmpreg & (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU)) >> RTC_ALRMAR_MNU_Pos);
+ sAlarm->AlarmTime.Seconds = (uint8_t)((tmpreg & (RTC_ALRMAR_ST | RTC_ALRMAR_SU)) >> RTC_ALRMAR_SU_Pos);
+ sAlarm->AlarmTime.TimeFormat = (uint8_t)((tmpreg & RTC_ALRMAR_PM) >> RTC_ALRMAR_PM_Pos);
+ sAlarm->AlarmTime.SubSeconds = (uint32_t) subsecondtmpreg;
+ sAlarm->AlarmDateWeekDay = (uint8_t)((tmpreg & (RTC_ALRMAR_DT | RTC_ALRMAR_DU)) >> RTC_ALRMAR_DU_Pos);
+ sAlarm->AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMAR_WDSEL);
+ sAlarm->AlarmMask = (uint32_t)(tmpreg & RTC_ALARMMASK_ALL);
+ }
+
+ if (Format == RTC_FORMAT_BIN)
+ {
+ sAlarm->AlarmTime.Hours = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours);
+ sAlarm->AlarmTime.Minutes = RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes);
+ sAlarm->AlarmTime.Seconds = RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds);
+ sAlarm->AlarmDateWeekDay = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle Alarm interrupt request.
+ * @param hrtc RTC handle
+ * @retval None
+ */
+void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc)
+{
+ /* Get the AlarmA interrupt source enable status */
+ if (__HAL_RTC_ALARM_GET_IT_SOURCE(hrtc, RTC_IT_ALRA) != 0U)
+ {
+ /* Get the pending status of the AlarmA Interrupt */
+ if (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) != 0U)
+ {
+ /* Clear the AlarmA interrupt pending bit */
+ __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);
+
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+ /* Call Compare Match registered Callback */
+ hrtc->AlarmAEventCallback(hrtc);
+#else
+ /* AlarmA callback */
+ HAL_RTC_AlarmAEventCallback(hrtc);
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
+ }
+ }
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+}
+
+/**
+ * @brief Alarm A callback.
+ * @param hrtc RTC handle
+ * @retval None
+ */
+__weak void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hrtc);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_RTC_AlarmAEventCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Handle AlarmA Polling request.
+ * @param hrtc RTC handle
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
+{
+
+ uint32_t tickstart = HAL_GetTick();
+
+ while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) == 0U)
+ {
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+ {
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Clear the Alarm interrupt pending bit */
+ __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Exported_Functions_Group4
+ * @brief Peripheral Control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..]
+ This subsection provides functions allowing to
+ (+) Wait for RTC Time and Date Synchronization
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Wait until the RTC Time and Date registers (RTC_TR and RTC_DR) are
+ * synchronized with RTC APB clock.
+ * @note The RTC Resynchronization mode is write protected, use the
+ * __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function.
+ * @note To read the calendar through the shadow registers after Calendar
+ * initialization, calendar update or after wakeup from low power modes
+ * the software must first clear the RSF flag.
+ * The software must then wait until it is set again before reading
+ * the calendar, which means that the calendar registers have been
+ * correctly copied into the RTC_TR and RTC_DR shadow registers.
+ * @param hrtc RTC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc)
+{
+ uint32_t tickstart;
+
+ /* Clear RSF flag */
+ hrtc->Instance->ICSR &= (uint32_t)RTC_RSF_MASK;
+
+ tickstart = HAL_GetTick();
+
+ /* Wait the registers to be synchronised */
+ while ((hrtc->Instance->ICSR & RTC_ICSR_RSF) == 0U)
+ {
+ if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Exported_Functions_Group5
+ * @brief Peripheral State functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral State functions #####
+ ===============================================================================
+ [..]
+ This subsection provides functions allowing to
+ (+) Get RTC state
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Return the RTC handle state.
+ * @param hrtc RTC handle
+ * @retval HAL state
+ */
+HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc)
+{
+ /* Return RTC handle state */
+ return hrtc->State;
+}
+
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Private_Functions
+ * @{
+ */
+/**
+ * @brief Enter the RTC Initialization mode.
+ * @note The RTC Initialization mode is write protected, use the
+ * __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function.
+ * @param hrtc RTC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef *hrtc)
+{
+ uint32_t tickstart;
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check if the Initialization mode is set */
+ if ((hrtc->Instance->ICSR & RTC_ICSR_INITF) == 0U)
+ {
+ /* Set the Initialization mode */
+ SET_BIT(hrtc->Instance->ICSR, RTC_ICSR_INIT);
+
+ tickstart = HAL_GetTick();
+ /* Wait till RTC is in INIT state and if Time out is reached exit */
+ while (((hrtc->Instance->ICSR & RTC_ICSR_INITF) == 0U) && (status != HAL_TIMEOUT))
+ {
+ if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
+ {
+ status = HAL_TIMEOUT;
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+ }
+ }
+ }
+
+ return status;
+}
+
+/**
+ * @brief Exit the RTC Initialization mode.
+ * @param hrtc RTC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef RTC_ExitInitMode(RTC_HandleTypeDef *hrtc)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Exit Initialization mode */
+ CLEAR_BIT(RTC->ICSR, RTC_ICSR_INIT);
+
+ /* If CR_BYPSHAD bit = 0, wait for synchro */
+ if (READ_BIT(RTC->CR, RTC_CR_BYPSHAD) == 0U)
+ {
+ if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
+ {
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+ status = HAL_TIMEOUT;
+ }
+ }
+ else
+ {
+ /* Clear BYPSHAD bit */
+ CLEAR_BIT(RTC->CR, RTC_CR_BYPSHAD);
+ if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
+ {
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+ status = HAL_TIMEOUT;
+ }
+ /* Restore BYPSHAD bit */
+ SET_BIT(RTC->CR, RTC_CR_BYPSHAD);
+ }
+
+ return status;
+}
+/**
+ * @brief Convert a 2 digit decimal to BCD format.
+ * @param Value Byte to be converted
+ * @retval Converted byte
+ */
+uint8_t RTC_ByteToBcd2(uint8_t Value)
+{
+ uint32_t bcdhigh = 0U;
+ uint8_t Param = Value;
+
+ while (Param >= 10U)
+ {
+ bcdhigh++;
+ Param -= 10U;
+ }
+
+ return ((uint8_t)(bcdhigh << 4U) | Param);
+}
+
+/**
+ * @brief Convert from 2 digit BCD to Binary.
+ * @param Value BCD value to be converted
+ * @retval Converted word
+ */
+uint8_t RTC_Bcd2ToByte(uint8_t Value)
+{
+ uint32_t tmp;
+ tmp = (((uint32_t)Value & 0xF0U) >> 4U) * 10U;
+ return (uint8_t)(tmp + ((uint32_t)Value & 0x0FU));
+}
+
+/**
+ * @}
+ */
+
+#endif /* HAL_RTC_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rtc_ex.c b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rtc_ex.c
new file mode 100644
index 0000000000..633191c0f8
--- /dev/null
+++ b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rtc_ex.c
@@ -0,0 +1,834 @@
+/**
+ ******************************************************************************
+ * @file stm32c0xx_hal_rtc_ex.c
+ * @author MCD Application Team
+ * @brief Extended RTC HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Real Time Clock (RTC) Extended peripheral:
+ * + RTC Time Stamp functions
+ * + Extended Control functions
+ * + Extended RTC features functions
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2022 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ (+) Enable the RTC domain access.
+ (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour
+ format using the HAL_RTC_Init() function.
+
+ *** Outputs configuration ***
+ =============================
+ [..] The RTC has 2 different outputs:
+ (+) RTC_ALARM: this output is used to manage the RTC Alarm A.
+ To output the selected RTC signal, use the HAL_RTC_Init() function.
+ (+) RTC_CALIB: this output is 512Hz signal or 1Hz.
+ To enable the RTC_CALIB, use the HAL_RTCEx_SetCalibrationOutPut() function.
+ (+) Two pins can be used as RTC_ALARM or RTC_CALIB (PC13, PB2) managed on
+ the RTC_OR register.
+ (+) When the RTC_CALIB or RTC_ALARM output is selected, the RTC_OUT pin is
+ automatically configured in output alternate function.
+
+ *** Smooth digital Calibration configuration ***
+ ================================================
+ [..]
+ (+) Configure the RTC Original Digital Calibration Value and the corresponding
+ calibration cycle period (32s,16s and 8s) using the HAL_RTCEx_SetSmoothCalib()
+ function.
+
+ *** TimeStamp configuration ***
+ ===============================
+ [..]
+ (+) Enable the RTC TimeStamp using the HAL_RTCEx_SetTimeStamp() function.
+ You can also configure the RTC TimeStamp with interrupt mode using the
+ HAL_RTCEx_SetTimeStamp_IT() function.
+ (+) To read the RTC TimeStamp Time and Date register, use the HAL_RTCEx_GetTimeStamp()
+ function.
+
+ @endverbatim
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32c0xx_hal.h"
+
+/** @addtogroup STM32C0xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup RTCEx
+ * @brief RTC Extended HAL module driver
+ * @{
+ */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup RTCEx_Exported_Functions
+ * @{
+ */
+
+
+/** @addtogroup RTCEx_Exported_Functions_Group1
+ * @brief RTC TimeStamp and Tamper functions
+ *
+@verbatim
+ ===============================================================================
+ ##### RTC TimeStamp and Tamper functions #####
+ ===============================================================================
+
+ [..] This section provides functions allowing to configure TimeStamp feature
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Set TimeStamp.
+ * @note This API must be called before enabling the TimeStamp feature.
+ * @param hrtc RTC handle
+ * @param TimeStampEdge Specifies the pin edge on which the TimeStamp is
+ * activated.
+ * This parameter can be one of the following values:
+ * @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the
+ * rising edge of the related pin.
+ * @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the
+ * falling edge of the related pin.
+ * @param RTC_TimeStampPin specifies the RTC TimeStamp Pin.
+ * This parameter can be one of the following values:
+ * @arg RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC TimeStamp Pin.
+ * The RTC TimeStamp Pin is per default PC13, but for reasons of
+ * compatibility, this parameter is required.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
+{
+ uint32_t tmpreg;
+
+ /* Check the parameters */
+ assert_param(IS_TIMESTAMP_EDGE(TimeStampEdge));
+ assert_param(IS_RTC_TIMESTAMP_PIN(RTC_TimeStampPin));
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Get the RTC_CR register and clear the bits to be configured */
+ tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));
+
+ tmpreg |= TimeStampEdge;
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* Configure the Time Stamp TSEDGE and Enable bits */
+ hrtc->Instance->CR = (uint32_t)tmpreg;
+
+ __HAL_RTC_TIMESTAMP_ENABLE(hrtc);
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Set TimeStamp with Interrupt.
+ * @note This API must be called before enabling the TimeStamp feature.
+ * @param hrtc RTC handle
+ * @param TimeStampEdge Specifies the pin edge on which the TimeStamp is
+ * activated.
+ * This parameter can be one of the following values:
+ * @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the
+ * rising edge of the related pin.
+ * @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the
+ * falling edge of the related pin.
+ * @param RTC_TimeStampPin Specifies the RTC TimeStamp Pin.
+ * This parameter can be one of the following values:
+ * @arg RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC TimeStamp Pin.
+ * The RTC TimeStamp Pin is per default PC13, but for reasons of
+ * compatibility, this parameter is required.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
+{
+ uint32_t tmpreg;
+
+ /* Check the parameters */
+ assert_param(IS_TIMESTAMP_EDGE(TimeStampEdge));
+ assert_param(IS_RTC_TIMESTAMP_PIN(RTC_TimeStampPin));
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Get the RTC_CR register and clear the bits to be configured */
+ tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));
+
+ tmpreg |= TimeStampEdge;
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* Configure the Time Stamp TSEDGE and Enable bits */
+ hrtc->Instance->CR = (uint32_t)tmpreg;
+
+ __HAL_RTC_TIMESTAMP_ENABLE(hrtc);
+
+ /* Enable IT timestamp */
+ __HAL_RTC_TIMESTAMP_ENABLE_IT(hrtc, RTC_IT_TS);
+
+ /* RTC timestamp Interrupt Configuration: EXTI configuration */
+ __HAL_RTC_TIMESTAMP_EXTI_ENABLE_IT();
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Deactivate TimeStamp.
+ * @param hrtc RTC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc)
+{
+ uint32_t tmpreg;
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* In case of interrupt mode is used, the interrupt source must disabled */
+ __HAL_RTC_TIMESTAMP_DISABLE_IT(hrtc, RTC_IT_TS);
+
+ /* Get the RTC_CR register and clear the bits to be configured */
+ tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));
+
+ /* Configure the Time Stamp TSEDGE and Enable bits */
+ hrtc->Instance->CR = (uint32_t)tmpreg;
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Get the RTC TimeStamp value.
+ * @param hrtc RTC handle
+ * @param sTimeStamp Pointer to Time structure
+ * @param sTimeStampDate Pointer to Date structure
+ * @param Format specifies the format of the entered parameters.
+ * This parameter can be one of the following values:
+ * @arg RTC_FORMAT_BIN: Binary data format
+ * @arg RTC_FORMAT_BCD: BCD data format
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTimeStamp,
+ RTC_DateTypeDef *sTimeStampDate, uint32_t Format)
+{
+ uint32_t tmptime, tmpdate;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_FORMAT(Format));
+
+ /* Get the TimeStamp time and date registers values */
+ tmptime = (uint32_t)(hrtc->Instance->TSTR & RTC_TR_RESERVED_MASK);
+ tmpdate = (uint32_t)(hrtc->Instance->TSDR & RTC_DR_RESERVED_MASK);
+
+ /* Fill the Time structure fields with the read parameters */
+ sTimeStamp->Hours = (uint8_t)((tmptime & (RTC_TR_HT | RTC_TR_HU)) >> RTC_TSTR_HU_Pos);
+ sTimeStamp->Minutes = (uint8_t)((tmptime & (RTC_TR_MNT | RTC_TR_MNU)) >> RTC_TSTR_MNU_Pos);
+ sTimeStamp->Seconds = (uint8_t)((tmptime & (RTC_TR_ST | RTC_TR_SU)) >> RTC_TSTR_SU_Pos);
+ sTimeStamp->TimeFormat = (uint8_t)((tmptime & (RTC_TR_PM)) >> RTC_TSTR_PM_Pos);
+ sTimeStamp->SubSeconds = (uint32_t) hrtc->Instance->TSSSR;
+
+ /* Fill the Date structure fields with the read parameters */
+ sTimeStampDate->Year = 0U;
+ sTimeStampDate->Month = (uint8_t)((tmpdate & (RTC_DR_MT | RTC_DR_MU)) >> RTC_TSDR_MU_Pos);
+ sTimeStampDate->Date = (uint8_t)(tmpdate & (RTC_DR_DT | RTC_DR_DU));
+ sTimeStampDate->WeekDay = (uint8_t)((tmpdate & (RTC_DR_WDU)) >> RTC_TSDR_WDU_Pos);
+
+ /* Check the input parameters format */
+ if (Format == RTC_FORMAT_BIN)
+ {
+ /* Convert the TimeStamp structure parameters to Binary format */
+ sTimeStamp->Hours = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Hours);
+ sTimeStamp->Minutes = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Minutes);
+ sTimeStamp->Seconds = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Seconds);
+
+ /* Convert the DateTimeStamp structure parameters to Binary format */
+ sTimeStampDate->Month = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->Month);
+ sTimeStampDate->Date = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->Date);
+ sTimeStampDate->WeekDay = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->WeekDay);
+ }
+
+ /* Clear the TIMESTAMP Flags */
+ __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSF);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief TimeStamp callback.
+ * @param hrtc RTC handle
+ * @retval None
+ */
+__weak void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hrtc);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_RTCEx_TimeStampEventCallback could be implemented in the user file
+ */
+}
+
+
+/**
+ * @brief Handle TimeStamp interrupt request.
+ * @param hrtc RTC handle
+ * @retval None
+ */
+void HAL_RTCEx_TimeStampIRQHandler(RTC_HandleTypeDef *hrtc)
+{
+ /* Get the TimeStamp interrupt source enable status */
+ if (READ_BIT(RTC->MISR, RTC_MISR_TSMF) != 0U)
+ {
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+ /* Call TimeStampEvent registered Callback */
+ hrtc->TimeStampEventCallback(hrtc);
+#else
+ /* TIMESTAMP callback */
+ HAL_RTCEx_TimeStampEventCallback(hrtc);
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
+
+ /* Clearing flags after the Callback because the content of RTC_TSTR and RTC_TSDR are cleared when TSF bit is reset.*/
+ WRITE_REG(RTC->SCR, RTC_SCR_CTSF);
+ }
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+}
+
+
+/**
+ * @brief Handle TimeStamp polling request.
+ * @param hrtc RTC handle
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
+{
+ uint32_t tickstart = HAL_GetTick();
+
+ while (__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSF) == 0U)
+ {
+ if (__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSOVF) != 0U)
+ {
+ /* Clear the TIMESTAMP OverRun Flag */
+ __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSOVF);
+
+ /* Change TIMESTAMP state */
+ hrtc->State = HAL_RTC_STATE_ERROR;
+
+ return HAL_ERROR;
+ }
+
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+ {
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup RTCEx_Exported_Functions_Group3
+ * @brief Extended Peripheral Control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Extended Peripheral Control functions #####
+ ===============================================================================
+ [..]
+ This subsection provides functions allowing to
+ (+) Set the Coarse calibration parameters.
+ (+) Deactivate the Coarse calibration parameters
+ (+) Set the Smooth calibration parameters.
+ (+) Configure the Synchronization Shift Control Settings.
+ (+) Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
+ (+) Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
+ (+) Enable the RTC reference clock detection.
+ (+) Disable the RTC reference clock detection.
+ (+) Enable the Bypass Shadow feature.
+ (+) Disable the Bypass Shadow feature.
+
+@endverbatim
+ * @{
+ */
+
+
+
+/**
+ * @brief Set the Smooth calibration parameters.
+ * @note To deactivate the smooth calibration, the field SmoothCalibPlusPulses
+ * must be equal to SMOOTHCALIB_PLUSPULSES_RESET and the field
+ * SmoothCalibMinusPulsesValue must be equal to 0.
+ * @param hrtc RTC handle
+ * @param SmoothCalibPeriod Select the Smooth Calibration Period.
+ * This parameter can be can be one of the following values :
+ * @arg RTC_SMOOTHCALIB_PERIOD_32SEC: The smooth calibration period is 32s.
+ * @arg RTC_SMOOTHCALIB_PERIOD_16SEC: The smooth calibration period is 16s.
+ * @arg RTC_SMOOTHCALIB_PERIOD_8SEC: The smooth calibration period is 8s.
+ * @param SmoothCalibPlusPulses Select to Set or reset the CALP bit.
+ * This parameter can be one of the following values:
+ * @arg RTC_SMOOTHCALIB_PLUSPULSES_SET: Add one RTCCLK pulse every 2*11 pulses.
+ * @arg RTC_SMOOTHCALIB_PLUSPULSES_RESET: No RTCCLK pulses are added.
+ * @param SmoothCalibMinusPulsesValue Select the value of CALM[8:0] bits.
+ * This parameter can be one any value from 0 to 0x000001FF.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod,
+ uint32_t SmoothCalibPlusPulses, uint32_t SmoothCalibMinusPulsesValue)
+{
+ uint32_t tickstart;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_SMOOTH_CALIB_PERIOD(SmoothCalibPeriod));
+ assert_param(IS_RTC_SMOOTH_CALIB_PLUS(SmoothCalibPlusPulses));
+ assert_param(IS_RTC_SMOOTH_CALIB_MINUS(SmoothCalibMinusPulsesValue));
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* check if a calibration is pending*/
+ if ((hrtc->Instance->ICSR & RTC_ICSR_RECALPF) != 0U)
+ {
+ tickstart = HAL_GetTick();
+
+ /* check if a calibration is pending*/
+ while ((hrtc->Instance->ICSR & RTC_ICSR_RECALPF) != 0U)
+ {
+ if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Configure the Smooth calibration settings */
+ hrtc->Instance->CALR = (uint32_t)((uint32_t)SmoothCalibPeriod | (uint32_t)SmoothCalibPlusPulses | (uint32_t)SmoothCalibMinusPulsesValue);
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configure the Synchronization Shift Control Settings.
+ * @note When REFCKON is set, firmware must not write to Shift control register.
+ * @param hrtc RTC handle
+ * @param ShiftAdd1S Select to add or not 1 second to the time calendar.
+ * This parameter can be one of the following values:
+ * @arg RTC_SHIFTADD1S_SET: Add one second to the clock calendar.
+ * @arg RTC_SHIFTADD1S_RESET: No effect.
+ * @param ShiftSubFS Select the number of Second Fractions to substitute.
+ * This parameter can be one any value from 0 to 0x7FFF.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef *hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS)
+{
+ uint32_t tickstart;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_SHIFT_ADD1S(ShiftAdd1S));
+ assert_param(IS_RTC_SHIFT_SUBFS(ShiftSubFS));
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ tickstart = HAL_GetTick();
+
+ /* Wait until the shift is completed*/
+ while ((hrtc->Instance->ICSR & RTC_ICSR_SHPF) != 0U)
+ {
+ if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Check if the reference clock detection is disabled */
+ if ((hrtc->Instance->CR & RTC_CR_REFCKON) == 0U)
+ {
+ /* Configure the Shift settings */
+ hrtc->Instance->SHIFTR = (uint32_t)(uint32_t)(ShiftSubFS) | (uint32_t)(ShiftAdd1S);
+
+ /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
+ if ((hrtc->Instance->CR & RTC_CR_BYPSHAD) == 0U)
+ {
+ if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_ERROR;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_ERROR;
+ }
+ }
+ }
+ else
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_ERROR;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_ERROR;
+ }
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
+ * @param hrtc RTC handle
+ * @param CalibOutput Select the Calibration output Selection .
+ * This parameter can be one of the following values:
+ * @arg RTC_CALIBOUTPUT_512HZ: A signal has a regular waveform at 512Hz.
+ * @arg RTC_CALIBOUTPUT_1HZ: A signal has a regular waveform at 1Hz.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef *hrtc, uint32_t CalibOutput)
+{
+ /* Check the parameters */
+ assert_param(IS_RTC_CALIB_OUTPUT(CalibOutput));
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* Clear flags before config */
+ hrtc->Instance->CR &= (uint32_t)~RTC_CR_COSEL;
+
+ /* Configure the RTC_CR register */
+ hrtc->Instance->CR |= (uint32_t)CalibOutput;
+
+ __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(hrtc);
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
+ * @param hrtc RTC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef *hrtc)
+{
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(hrtc);
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Enable the RTC reference clock detection.
+ * @param hrtc RTC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef *hrtc)
+{
+ HAL_StatusTypeDef status;
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* Enter Initialization mode */
+ status = RTC_EnterInitMode(hrtc);
+ if (status == HAL_OK)
+ {
+ /* Enable clockref detection */
+ __HAL_RTC_CLOCKREF_DETECTION_ENABLE(hrtc);
+
+ /* Exit Initialization mode */
+ status = RTC_ExitInitMode(hrtc);
+ }
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ if (status == HAL_OK)
+ {
+ hrtc->State = HAL_RTC_STATE_READY;
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return status;
+}
+
+/**
+ * @brief Disable the RTC reference clock detection.
+ * @param hrtc RTC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef *hrtc)
+{
+ HAL_StatusTypeDef status;
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* Enter Initialization mode */
+ status = RTC_EnterInitMode(hrtc);
+ if (status == HAL_OK)
+ {
+ /* Disable clockref detection */
+ __HAL_RTC_CLOCKREF_DETECTION_DISABLE(hrtc);
+
+ /* Exit Initialization mode */
+ status = RTC_ExitInitMode(hrtc);
+ }
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ if (status == HAL_OK)
+ {
+ hrtc->State = HAL_RTC_STATE_READY;
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return status;
+}
+
+/**
+ * @brief Enable the Bypass Shadow feature.
+ * @note When the Bypass Shadow is enabled the calendar value are taken
+ * directly from the Calendar counter.
+ * @param hrtc RTC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef *hrtc)
+{
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* Set the BYPSHAD bit */
+ hrtc->Instance->CR |= (uint8_t)RTC_CR_BYPSHAD;
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disable the Bypass Shadow feature.
+ * @note When the Bypass Shadow is enabled the calendar value are taken
+ * directly from the Calendar counter.
+ * @param hrtc RTC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef *hrtc)
+{
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* Reset the BYPSHAD bit */
+ hrtc->Instance->CR &= ((uint8_t)~RTC_CR_BYPSHAD);
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_RTC_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_smartcard.c b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_smartcard.c
new file mode 100644
index 0000000000..44c9f55a35
--- /dev/null
+++ b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_smartcard.c
@@ -0,0 +1,3182 @@
+/**
+ ******************************************************************************
+ * @file stm32c0xx_hal_smartcard.c
+ * @author MCD Application Team
+ * @brief SMARTCARD HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the SMARTCARD peripheral:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral Control functions
+ * + Peripheral State and Error functions
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2022 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ The SMARTCARD HAL driver can be used as follows:
+
+ (#) Declare a SMARTCARD_HandleTypeDef handle structure (eg. SMARTCARD_HandleTypeDef hsmartcard).
+ (#) Associate a USART to the SMARTCARD handle hsmartcard.
+ (#) Initialize the SMARTCARD low level resources by implementing the HAL_SMARTCARD_MspInit() API:
+ (++) Enable the USARTx interface clock.
+ (++) USART pins configuration:
+ (+++) Enable the clock for the USART GPIOs.
+ (+++) Configure the USART pins (TX as alternate function pull-up, RX as alternate function Input).
+ (++) NVIC configuration if you need to use interrupt process (HAL_SMARTCARD_Transmit_IT()
+ and HAL_SMARTCARD_Receive_IT() APIs):
+ (+++) Configure the USARTx interrupt priority.
+ (+++) Enable the NVIC USART IRQ handle.
+ (++) DMA Configuration if you need to use DMA process (HAL_SMARTCARD_Transmit_DMA()
+ and HAL_SMARTCARD_Receive_DMA() APIs):
+ (+++) Declare a DMA handle structure for the Tx/Rx channel.
+ (+++) Enable the DMAx interface clock.
+ (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
+ (+++) Configure the DMA Tx/Rx channel.
+ (+++) Associate the initialized DMA handle to the SMARTCARD DMA Tx/Rx handle.
+ (+++) Configure the priority and enable the NVIC for the transfer complete
+ interrupt on the DMA Tx/Rx channel.
+
+ (#) Program the Baud Rate, Parity, Mode(Receiver/Transmitter), clock enabling/disabling and accordingly,
+ the clock parameters (parity, phase, last bit), prescaler value, guard time and NACK on transmission
+ error enabling or disabling in the hsmartcard handle Init structure.
+
+ (#) If required, program SMARTCARD advanced features (TX/RX pins swap, TimeOut, auto-retry counter,...)
+ in the hsmartcard handle AdvancedInit structure.
+
+ (#) Initialize the SMARTCARD registers by calling the HAL_SMARTCARD_Init() API:
+ (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
+ by calling the customized HAL_SMARTCARD_MspInit() API.
+ [..]
+ (@) The specific SMARTCARD interrupts (Transmission complete interrupt,
+ RXNE interrupt and Error Interrupts) will be managed using the macros
+ __HAL_SMARTCARD_ENABLE_IT() and __HAL_SMARTCARD_DISABLE_IT() inside the transmit and receive process.
+
+ [..]
+ [..] Three operation modes are available within this driver :
+
+ *** Polling mode IO operation ***
+ =================================
+ [..]
+ (+) Send an amount of data in blocking mode using HAL_SMARTCARD_Transmit()
+ (+) Receive an amount of data in blocking mode using HAL_SMARTCARD_Receive()
+
+ *** Interrupt mode IO operation ***
+ ===================================
+ [..]
+ (+) Send an amount of data in non-blocking mode using HAL_SMARTCARD_Transmit_IT()
+ (+) At transmission end of transfer HAL_SMARTCARD_TxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_SMARTCARD_TxCpltCallback()
+ (+) Receive an amount of data in non-blocking mode using HAL_SMARTCARD_Receive_IT()
+ (+) At reception end of transfer HAL_SMARTCARD_RxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_SMARTCARD_RxCpltCallback()
+ (+) In case of transfer Error, HAL_SMARTCARD_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_SMARTCARD_ErrorCallback()
+
+ *** DMA mode IO operation ***
+ ==============================
+ [..]
+ (+) Send an amount of data in non-blocking mode (DMA) using HAL_SMARTCARD_Transmit_DMA()
+ (+) At transmission end of transfer HAL_SMARTCARD_TxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_SMARTCARD_TxCpltCallback()
+ (+) Receive an amount of data in non-blocking mode (DMA) using HAL_SMARTCARD_Receive_DMA()
+ (+) At reception end of transfer HAL_SMARTCARD_RxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_SMARTCARD_RxCpltCallback()
+ (+) In case of transfer Error, HAL_SMARTCARD_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_SMARTCARD_ErrorCallback()
+
+ *** SMARTCARD HAL driver macros list ***
+ ========================================
+ [..]
+ Below the list of most used macros in SMARTCARD HAL driver.
+
+ (+) __HAL_SMARTCARD_GET_FLAG : Check whether or not the specified SMARTCARD flag is set
+ (+) __HAL_SMARTCARD_CLEAR_FLAG : Clear the specified SMARTCARD pending flag
+ (+) __HAL_SMARTCARD_ENABLE_IT: Enable the specified SMARTCARD interrupt
+ (+) __HAL_SMARTCARD_DISABLE_IT: Disable the specified SMARTCARD interrupt
+ (+) __HAL_SMARTCARD_GET_IT_SOURCE: Check whether or not the specified SMARTCARD interrupt is enabled
+
+ [..]
+ (@) You can refer to the SMARTCARD HAL driver header file for more useful macros
+
+ ##### Callback registration #####
+ ==================================
+
+ [..]
+ The compilation define USE_HAL_SMARTCARD_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+
+ [..]
+ Use Function HAL_SMARTCARD_RegisterCallback() to register a user callback.
+ Function HAL_SMARTCARD_RegisterCallback() allows to register following callbacks:
+ (+) TxCpltCallback : Tx Complete Callback.
+ (+) RxCpltCallback : Rx Complete Callback.
+ (+) ErrorCallback : Error Callback.
+ (+) AbortCpltCallback : Abort Complete Callback.
+ (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
+ (+) AbortReceiveCpltCallback : Abort Receive Complete Callback.
+ (+) RxFifoFullCallback : Rx Fifo Full Callback.
+ (+) TxFifoEmptyCallback : Tx Fifo Empty Callback.
+ (+) MspInitCallback : SMARTCARD MspInit.
+ (+) MspDeInitCallback : SMARTCARD MspDeInit.
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+ [..]
+ Use function HAL_SMARTCARD_UnRegisterCallback() to reset a callback to the default
+ weak (surcharged) function.
+ HAL_SMARTCARD_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+ and the Callback ID.
+ This function allows to reset following callbacks:
+ (+) TxCpltCallback : Tx Complete Callback.
+ (+) RxCpltCallback : Rx Complete Callback.
+ (+) ErrorCallback : Error Callback.
+ (+) AbortCpltCallback : Abort Complete Callback.
+ (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
+ (+) AbortReceiveCpltCallback : Abort Receive Complete Callback.
+ (+) RxFifoFullCallback : Rx Fifo Full Callback.
+ (+) TxFifoEmptyCallback : Tx Fifo Empty Callback.
+ (+) MspInitCallback : SMARTCARD MspInit.
+ (+) MspDeInitCallback : SMARTCARD MspDeInit.
+
+ [..]
+ By default, after the HAL_SMARTCARD_Init() and when the state is HAL_SMARTCARD_STATE_RESET
+ all callbacks are set to the corresponding weak (surcharged) functions:
+ examples HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback().
+ Exception done for MspInit and MspDeInit functions that are respectively
+ reset to the legacy weak (surcharged) functions in the HAL_SMARTCARD_Init()
+ and HAL_SMARTCARD_DeInit() only when these callbacks are null (not registered beforehand).
+ If not, MspInit or MspDeInit are not null, the HAL_SMARTCARD_Init() and HAL_SMARTCARD_DeInit()
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
+
+ [..]
+ Callbacks can be registered/unregistered in HAL_SMARTCARD_STATE_READY state only.
+ Exception done MspInit/MspDeInit that can be registered/unregistered
+ in HAL_SMARTCARD_STATE_READY or HAL_SMARTCARD_STATE_RESET state, thus registered (user)
+ MspInit/DeInit callbacks can be used during the Init/DeInit.
+ In that case first register the MspInit/MspDeInit user callbacks
+ using HAL_SMARTCARD_RegisterCallback() before calling HAL_SMARTCARD_DeInit()
+ or HAL_SMARTCARD_Init() function.
+
+ [..]
+ When The compilation define USE_HAL_SMARTCARD_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registration feature is not available
+ and weak (surcharged) callbacks are used.
+
+
+ @endverbatim
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32c0xx_hal.h"
+
+/** @addtogroup STM32C0xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup SMARTCARD SMARTCARD
+ * @brief HAL SMARTCARD module driver
+ * @{
+ */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup SMARTCARD_Private_Constants SMARTCARD Private Constants
+ * @{
+ */
+#define SMARTCARD_TEACK_REACK_TIMEOUT 1000U /*!< SMARTCARD TX or RX enable acknowledge time-out value */
+
+#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | \
+ USART_CR1_RE | USART_CR1_OVER8| \
+ USART_CR1_FIFOEN)) /*!< USART CR1 fields of parameters set by SMARTCARD_SetConfig API */
+
+#define USART_CR2_CLK_FIELDS ((uint32_t)(USART_CR2_CLKEN | USART_CR2_CPOL | \
+ USART_CR2_CPHA | USART_CR2_LBCL)) /*!< SMARTCARD clock-related USART CR2 fields of parameters */
+
+#define USART_CR2_FIELDS ((uint32_t)(USART_CR2_RTOEN | USART_CR2_CLK_FIELDS | \
+ USART_CR2_STOP)) /*!< USART CR2 fields of parameters set by SMARTCARD_SetConfig API */
+
+#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_ONEBIT | USART_CR3_NACK | USART_CR3_SCARCNT | \
+ USART_CR3_TXFTCFG | USART_CR3_RXFTCFG )) /*!< USART CR3 fields of parameters set by SMARTCARD_SetConfig API */
+
+#define USART_BRR_MIN 0x10U /*!< USART BRR minimum authorized value */
+
+#define USART_BRR_MAX 0x0000FFFFU /*!< USART BRR maximum authorized value */
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup SMARTCARD_Private_Functions
+ * @{
+ */
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+void SMARTCARD_InitCallbacksToDefault(SMARTCARD_HandleTypeDef *hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
+static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard);
+static void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsmartcard);
+static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsmartcard);
+static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Flag,
+ FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
+static void SMARTCARD_EndTxTransfer(SMARTCARD_HandleTypeDef *hsmartcard);
+static void SMARTCARD_EndRxTransfer(SMARTCARD_HandleTypeDef *hsmartcard);
+static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma);
+static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
+static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma);
+static void SMARTCARD_DMAAbortOnError(DMA_HandleTypeDef *hdma);
+static void SMARTCARD_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
+static void SMARTCARD_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
+static void SMARTCARD_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
+static void SMARTCARD_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
+static void SMARTCARD_TxISR(SMARTCARD_HandleTypeDef *hsmartcard);
+static void SMARTCARD_TxISR_FIFOEN(SMARTCARD_HandleTypeDef *hsmartcard);
+static void SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard);
+static void SMARTCARD_RxISR(SMARTCARD_HandleTypeDef *hsmartcard);
+static void SMARTCARD_RxISR_FIFOEN(SMARTCARD_HandleTypeDef *hsmartcard);
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup SMARTCARD_Exported_Functions SMARTCARD Exported Functions
+ * @{
+ */
+
+/** @defgroup SMARTCARD_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Initialization and Configuration functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to initialize the USARTx
+ associated to the SmartCard.
+ (+) These parameters can be configured:
+ (++) Baud Rate
+ (++) Parity: parity should be enabled, frame Length is fixed to 8 bits plus parity
+ (++) Receiver/transmitter modes
+ (++) Synchronous mode (and if enabled, phase, polarity and last bit parameters)
+ (++) Prescaler value
+ (++) Guard bit time
+ (++) NACK enabling or disabling on transmission error
+
+ (+) The following advanced features can be configured as well:
+ (++) TX and/or RX pin level inversion
+ (++) data logical level inversion
+ (++) RX and TX pins swap
+ (++) RX overrun detection disabling
+ (++) DMA disabling on RX error
+ (++) MSB first on communication line
+ (++) Time out enabling (and if activated, timeout value)
+ (++) Block length
+ (++) Auto-retry counter
+ [..]
+ The HAL_SMARTCARD_Init() API follows the USART synchronous configuration procedures
+ (details for the procedures are available in reference manual).
+
+@endverbatim
+
+ The USART frame format is given in the following table:
+
+ Table 1. USART frame format.
+ +---------------------------------------------------------------+
+ | M1M0 bits | PCE bit | USART frame |
+ |-----------------------|---------------------------------------|
+ | 01 | 1 | | SB | 8 bit data | PB | STB | |
+ +---------------------------------------------------------------+
+
+
+ * @{
+ */
+
+/**
+ * @brief Initialize the SMARTCARD mode according to the specified
+ * parameters in the SMARTCARD_HandleTypeDef and initialize the associated handle.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Check the SMARTCARD handle allocation */
+ if (hsmartcard == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the USART associated to the SMARTCARD handle */
+ assert_param(IS_SMARTCARD_INSTANCE(hsmartcard->Instance));
+
+ if (hsmartcard->gState == HAL_SMARTCARD_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hsmartcard->Lock = HAL_UNLOCKED;
+
+#if USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1
+ SMARTCARD_InitCallbacksToDefault(hsmartcard);
+
+ if (hsmartcard->MspInitCallback == NULL)
+ {
+ hsmartcard->MspInitCallback = HAL_SMARTCARD_MspInit;
+ }
+
+ /* Init the low level hardware */
+ hsmartcard->MspInitCallback(hsmartcard);
+#else
+ /* Init the low level hardware : GPIO, CLOCK */
+ HAL_SMARTCARD_MspInit(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
+ }
+
+ hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
+
+ /* Disable the Peripheral to set smartcard mode */
+ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+
+ /* In SmartCard mode, the following bits must be kept cleared:
+ - LINEN in the USART_CR2 register,
+ - HDSEL and IREN bits in the USART_CR3 register.*/
+ CLEAR_BIT(hsmartcard->Instance->CR2, USART_CR2_LINEN);
+ CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN));
+
+ /* set the USART in SMARTCARD mode */
+ SET_BIT(hsmartcard->Instance->CR3, USART_CR3_SCEN);
+
+ /* Set the SMARTCARD Communication parameters */
+ if (SMARTCARD_SetConfig(hsmartcard) == HAL_ERROR)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Set the SMARTCARD transmission completion indication */
+ SMARTCARD_TRANSMISSION_COMPLETION_SETTING(hsmartcard);
+
+ if (hsmartcard->AdvancedInit.AdvFeatureInit != SMARTCARD_ADVFEATURE_NO_INIT)
+ {
+ SMARTCARD_AdvFeatureConfig(hsmartcard);
+ }
+
+ /* Enable the Peripheral */
+ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+
+ /* TEACK and/or REACK to check before moving hsmartcard->gState and hsmartcard->RxState to Ready */
+ return (SMARTCARD_CheckIdleState(hsmartcard));
+}
+
+/**
+ * @brief DeInitialize the SMARTCARD peripheral.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Check the SMARTCARD handle allocation */
+ if (hsmartcard == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the USART/UART associated to the SMARTCARD handle */
+ assert_param(IS_SMARTCARD_INSTANCE(hsmartcard->Instance));
+
+ hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
+
+ /* Disable the Peripheral */
+ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+
+ WRITE_REG(hsmartcard->Instance->CR1, 0x0U);
+ WRITE_REG(hsmartcard->Instance->CR2, 0x0U);
+ WRITE_REG(hsmartcard->Instance->CR3, 0x0U);
+ WRITE_REG(hsmartcard->Instance->RTOR, 0x0U);
+ WRITE_REG(hsmartcard->Instance->GTPR, 0x0U);
+
+ /* DeInit the low level hardware */
+#if USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1
+ if (hsmartcard->MspDeInitCallback == NULL)
+ {
+ hsmartcard->MspDeInitCallback = HAL_SMARTCARD_MspDeInit;
+ }
+ /* DeInit the low level hardware */
+ hsmartcard->MspDeInitCallback(hsmartcard);
+#else
+ HAL_SMARTCARD_MspDeInit(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
+
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+ hsmartcard->gState = HAL_SMARTCARD_STATE_RESET;
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_RESET;
+
+ /* Process Unlock */
+ __HAL_UNLOCK(hsmartcard);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initialize the SMARTCARD MSP.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval None
+ */
+__weak void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsmartcard);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMARTCARD_MspInit can be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitialize the SMARTCARD MSP.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval None
+ */
+__weak void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsmartcard);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMARTCARD_MspDeInit can be implemented in the user file
+ */
+}
+
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a User SMARTCARD Callback
+ * To be used instead of the weak predefined callback
+ * @param hsmartcard smartcard handle
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_SMARTCARD_TX_COMPLETE_CB_ID Tx Complete Callback ID
+ * @arg @ref HAL_SMARTCARD_RX_COMPLETE_CB_ID Rx Complete Callback ID
+ * @arg @ref HAL_SMARTCARD_ERROR_CB_ID Error Callback ID
+ * @arg @ref HAL_SMARTCARD_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
+ * @arg @ref HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
+ * @arg @ref HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
+ * @arg @ref HAL_SMARTCARD_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID
+ * @arg @ref HAL_SMARTCARD_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID
+ * @arg @ref HAL_SMARTCARD_MSPINIT_CB_ID MspInit Callback ID
+ * @arg @ref HAL_SMARTCARD_MSPDEINIT_CB_ID MspDeInit Callback ID
+ * @param pCallback pointer to the Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard,
+ HAL_SMARTCARD_CallbackIDTypeDef CallbackID,
+ pSMARTCARD_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+ /* Process locked */
+ __HAL_LOCK(hsmartcard);
+
+ if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+
+ case HAL_SMARTCARD_TX_COMPLETE_CB_ID :
+ hsmartcard->TxCpltCallback = pCallback;
+ break;
+
+ case HAL_SMARTCARD_RX_COMPLETE_CB_ID :
+ hsmartcard->RxCpltCallback = pCallback;
+ break;
+
+ case HAL_SMARTCARD_ERROR_CB_ID :
+ hsmartcard->ErrorCallback = pCallback;
+ break;
+
+ case HAL_SMARTCARD_ABORT_COMPLETE_CB_ID :
+ hsmartcard->AbortCpltCallback = pCallback;
+ break;
+
+ case HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID :
+ hsmartcard->AbortTransmitCpltCallback = pCallback;
+ break;
+
+ case HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID :
+ hsmartcard->AbortReceiveCpltCallback = pCallback;
+ break;
+
+ case HAL_SMARTCARD_RX_FIFO_FULL_CB_ID :
+ hsmartcard->RxFifoFullCallback = pCallback;
+ break;
+
+ case HAL_SMARTCARD_TX_FIFO_EMPTY_CB_ID :
+ hsmartcard->TxFifoEmptyCallback = pCallback;
+ break;
+
+ case HAL_SMARTCARD_MSPINIT_CB_ID :
+ hsmartcard->MspInitCallback = pCallback;
+ break;
+
+ case HAL_SMARTCARD_MSPDEINIT_CB_ID :
+ hsmartcard->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (hsmartcard->gState == HAL_SMARTCARD_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_SMARTCARD_MSPINIT_CB_ID :
+ hsmartcard->MspInitCallback = pCallback;
+ break;
+
+ case HAL_SMARTCARD_MSPDEINIT_CB_ID :
+ hsmartcard->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hsmartcard);
+
+ return status;
+}
+
+/**
+ * @brief Unregister an SMARTCARD callback
+ * SMARTCARD callback is redirected to the weak predefined callback
+ * @param hsmartcard smartcard handle
+ * @param CallbackID ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_SMARTCARD_TX_COMPLETE_CB_ID Tx Complete Callback ID
+ * @arg @ref HAL_SMARTCARD_RX_COMPLETE_CB_ID Rx Complete Callback ID
+ * @arg @ref HAL_SMARTCARD_ERROR_CB_ID Error Callback ID
+ * @arg @ref HAL_SMARTCARD_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
+ * @arg @ref HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
+ * @arg @ref HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
+ * @arg @ref HAL_SMARTCARD_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID
+ * @arg @ref HAL_SMARTCARD_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID
+ * @arg @ref HAL_SMARTCARD_MSPINIT_CB_ID MspInit Callback ID
+ * @arg @ref HAL_SMARTCARD_MSPDEINIT_CB_ID MspDeInit Callback ID
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard,
+ HAL_SMARTCARD_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hsmartcard);
+
+ if (HAL_SMARTCARD_STATE_READY == hsmartcard->gState)
+ {
+ switch (CallbackID)
+ {
+ case HAL_SMARTCARD_TX_COMPLETE_CB_ID :
+ hsmartcard->TxCpltCallback = HAL_SMARTCARD_TxCpltCallback; /* Legacy weak TxCpltCallback */
+ break;
+
+ case HAL_SMARTCARD_RX_COMPLETE_CB_ID :
+ hsmartcard->RxCpltCallback = HAL_SMARTCARD_RxCpltCallback; /* Legacy weak RxCpltCallback */
+ break;
+
+ case HAL_SMARTCARD_ERROR_CB_ID :
+ hsmartcard->ErrorCallback = HAL_SMARTCARD_ErrorCallback; /* Legacy weak ErrorCallback */
+ break;
+
+ case HAL_SMARTCARD_ABORT_COMPLETE_CB_ID :
+ hsmartcard->AbortCpltCallback = HAL_SMARTCARD_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
+ break;
+
+ case HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID :
+ hsmartcard->AbortTransmitCpltCallback = HAL_SMARTCARD_AbortTransmitCpltCallback; /* Legacy weak
+ AbortTransmitCpltCallback*/
+ break;
+
+ case HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID :
+ hsmartcard->AbortReceiveCpltCallback = HAL_SMARTCARD_AbortReceiveCpltCallback; /* Legacy weak
+ AbortReceiveCpltCallback */
+ break;
+
+ case HAL_SMARTCARD_RX_FIFO_FULL_CB_ID :
+ hsmartcard->RxFifoFullCallback = HAL_SMARTCARDEx_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */
+ break;
+
+ case HAL_SMARTCARD_TX_FIFO_EMPTY_CB_ID :
+ hsmartcard->TxFifoEmptyCallback = HAL_SMARTCARDEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */
+ break;
+
+ case HAL_SMARTCARD_MSPINIT_CB_ID :
+ hsmartcard->MspInitCallback = HAL_SMARTCARD_MspInit; /* Legacy weak MspInitCallback */
+ break;
+
+ case HAL_SMARTCARD_MSPDEINIT_CB_ID :
+ hsmartcard->MspDeInitCallback = HAL_SMARTCARD_MspDeInit; /* Legacy weak MspDeInitCallback */
+ break;
+
+ default :
+ /* Update the error code */
+ hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_SMARTCARD_STATE_RESET == hsmartcard->gState)
+ {
+ switch (CallbackID)
+ {
+ case HAL_SMARTCARD_MSPINIT_CB_ID :
+ hsmartcard->MspInitCallback = HAL_SMARTCARD_MspInit;
+ break;
+
+ case HAL_SMARTCARD_MSPDEINIT_CB_ID :
+ hsmartcard->MspDeInitCallback = HAL_SMARTCARD_MspDeInit;
+ break;
+
+ default :
+ /* Update the error code */
+ hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hsmartcard);
+
+ return status;
+}
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Exported_Functions_Group2 IO operation functions
+ * @brief SMARTCARD Transmit and Receive functions
+ *
+@verbatim
+ ==============================================================================
+ ##### IO operation functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the SMARTCARD data transfers.
+
+ [..]
+ Smartcard is a single wire half duplex communication protocol.
+ The Smartcard interface is designed to support asynchronous protocol Smartcards as
+ defined in the ISO 7816-3 standard. The USART should be configured as:
+ (+) 8 bits plus parity: where M=1 and PCE=1 in the USART_CR1 register
+ (+) 1.5 stop bits when transmitting and receiving: where STOP=11 in the USART_CR2 register.
+
+ [..]
+ (#) There are two modes of transfer:
+ (##) Blocking mode: The communication is performed in polling mode.
+ The HAL status of all data processing is returned by the same function
+ after finishing transfer.
+ (##) Non-Blocking mode: The communication is performed using Interrupts
+ or DMA, the relevant API's return the HAL status.
+ The end of the data processing will be indicated through the
+ dedicated SMARTCARD IRQ when using Interrupt mode or the DMA IRQ when
+ using DMA mode.
+ (##) The HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback() user callbacks
+ will be executed respectively at the end of the Transmit or Receive process
+ The HAL_SMARTCARD_ErrorCallback() user callback will be executed when a communication
+ error is detected.
+
+ (#) Blocking mode APIs are :
+ (##) HAL_SMARTCARD_Transmit()
+ (##) HAL_SMARTCARD_Receive()
+
+ (#) Non Blocking mode APIs with Interrupt are :
+ (##) HAL_SMARTCARD_Transmit_IT()
+ (##) HAL_SMARTCARD_Receive_IT()
+ (##) HAL_SMARTCARD_IRQHandler()
+
+ (#) Non Blocking mode functions with DMA are :
+ (##) HAL_SMARTCARD_Transmit_DMA()
+ (##) HAL_SMARTCARD_Receive_DMA()
+
+ (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
+ (##) HAL_SMARTCARD_TxCpltCallback()
+ (##) HAL_SMARTCARD_RxCpltCallback()
+ (##) HAL_SMARTCARD_ErrorCallback()
+
+ [..]
+ (#) Non-Blocking mode transfers could be aborted using Abort API's :
+ (##) HAL_SMARTCARD_Abort()
+ (##) HAL_SMARTCARD_AbortTransmit()
+ (##) HAL_SMARTCARD_AbortReceive()
+ (##) HAL_SMARTCARD_Abort_IT()
+ (##) HAL_SMARTCARD_AbortTransmit_IT()
+ (##) HAL_SMARTCARD_AbortReceive_IT()
+
+ (#) For Abort services based on interrupts (HAL_SMARTCARD_Abortxxx_IT),
+ a set of Abort Complete Callbacks are provided:
+ (##) HAL_SMARTCARD_AbortCpltCallback()
+ (##) HAL_SMARTCARD_AbortTransmitCpltCallback()
+ (##) HAL_SMARTCARD_AbortReceiveCpltCallback()
+
+ (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
+ Errors are handled as follows :
+ (##) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
+ to be evaluated by user : this concerns Frame Error,
+ Parity Error or Noise Error in Interrupt mode reception .
+ Received character is then retrieved and stored in Rx buffer,
+ Error code is set to allow user to identify error type,
+ and HAL_SMARTCARD_ErrorCallback() user callback is executed. Transfer is kept ongoing on SMARTCARD side.
+ If user wants to abort it, Abort services should be called by user.
+ (##) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
+ This concerns Frame Error in Interrupt mode transmission, Overrun Error in Interrupt
+ mode reception and all errors in DMA mode.
+ Error code is set to allow user to identify error type,
+ and HAL_SMARTCARD_ErrorCallback() user callback is executed.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Send an amount of data in blocking mode.
+ * @note When FIFO mode is enabled, writing a data in the TDR register adds one
+ * data to the TXFIFO. Write operations to the TDR register are performed
+ * when TXFNF flag is set. From hardware perspective, TXFNF flag and
+ * TXE are mapped on the same bit-field.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @param pData pointer to data buffer.
+ * @param Size amount of data to be sent.
+ * @param Timeout Timeout duration.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, const uint8_t *pData, uint16_t Size,
+ uint32_t Timeout)
+{
+ uint32_t tickstart;
+ const uint8_t *ptmpdata = pData;
+
+ /* Check that a Tx process is not already ongoing */
+ if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
+ {
+ if ((ptmpdata == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hsmartcard);
+
+ hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY_TX;
+
+ /* Init tickstart for timeout management */
+ tickstart = HAL_GetTick();
+
+ /* Disable the Peripheral first to update mode for TX master */
+ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+
+ /* In case of TX only mode, if NACK is enabled, the USART must be able to monitor
+ the bidirectional line to detect a NACK signal in case of parity error.
+ Therefore, the receiver block must be enabled as well (RE bit must be set). */
+ if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX)
+ && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
+ {
+ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
+ }
+ /* Enable Tx */
+ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TE);
+
+ /* Enable the Peripheral */
+ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+
+ /* Perform a TX/RX FIFO Flush */
+ __HAL_SMARTCARD_FLUSH_DRREGISTER(hsmartcard);
+
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+ hsmartcard->TxXferSize = Size;
+ hsmartcard->TxXferCount = Size;
+
+ while (hsmartcard->TxXferCount > 0U)
+ {
+ hsmartcard->TxXferCount--;
+ if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ hsmartcard->Instance->TDR = (uint8_t)(*ptmpdata & 0xFFU);
+ ptmpdata++;
+ }
+ if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_TRANSMISSION_COMPLETION_FLAG(hsmartcard), RESET,
+ tickstart, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Disable the Peripheral first to update mode */
+ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+ if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX)
+ && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
+ {
+ /* In case of TX only mode, if NACK is enabled, receiver block has been enabled
+ for Transmit phase. Disable this receiver block. */
+ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
+ }
+ if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX_RX)
+ || (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
+ {
+ /* Perform a TX FIFO Flush at end of Tx phase, as all sent bytes are appearing in Rx Data register */
+ __HAL_SMARTCARD_FLUSH_DRREGISTER(hsmartcard);
+ }
+ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+
+ /* At end of Tx process, restore hsmartcard->gState to Ready */
+ hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmartcard);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in blocking mode.
+ * @note When FIFO mode is enabled, the RXFNE flag is set as long as the RXFIFO
+ * is not empty. Read operations from the RDR register are performed when
+ * RXFNE flag is set. From hardware perspective, RXFNE flag and
+ * RXNE are mapped on the same bit-field.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @param pData pointer to data buffer.
+ * @param Size amount of data to be received.
+ * @param Timeout Timeout duration.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size,
+ uint32_t Timeout)
+{
+ uint32_t tickstart;
+ uint8_t *ptmpdata = pData;
+
+ /* Check that a Rx process is not already ongoing */
+ if (hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
+ {
+ if ((ptmpdata == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hsmartcard);
+
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_BUSY_RX;
+
+ /* Init tickstart for timeout management */
+ tickstart = HAL_GetTick();
+
+ hsmartcard->RxXferSize = Size;
+ hsmartcard->RxXferCount = Size;
+
+ /* Check the remain data to be received */
+ while (hsmartcard->RxXferCount > 0U)
+ {
+ hsmartcard->RxXferCount--;
+
+ if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ *ptmpdata = (uint8_t)(hsmartcard->Instance->RDR & (uint8_t)0x00FF);
+ ptmpdata++;
+ }
+
+ /* At end of Rx process, restore hsmartcard->RxState to Ready */
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmartcard);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Send an amount of data in interrupt mode.
+ * @note When FIFO mode is disabled, USART interrupt is generated whenever
+ * USART_TDR register is empty, i.e one interrupt per data to transmit.
+ * @note When FIFO mode is enabled, USART interrupt is generated whenever
+ * TXFIFO threshold reached. In that case the interrupt rate depends on
+ * TXFIFO threshold configuration.
+ * @note This function sets the hsmartcard->TxIsr function pointer according to
+ * the FIFO mode (data transmission processing depends on FIFO mode).
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @param pData pointer to data buffer.
+ * @param Size amount of data to be sent.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, const uint8_t *pData, uint16_t Size)
+{
+ /* Check that a Tx process is not already ongoing */
+ if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hsmartcard);
+
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+ hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY_TX;
+
+ hsmartcard->pTxBuffPtr = pData;
+ hsmartcard->TxXferSize = Size;
+ hsmartcard->TxXferCount = Size;
+ hsmartcard->TxISR = NULL;
+
+ /* Disable the Peripheral first to update mode for TX master */
+ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+
+ /* In case of TX only mode, if NACK is enabled, the USART must be able to monitor
+ the bidirectional line to detect a NACK signal in case of parity error.
+ Therefore, the receiver block must be enabled as well (RE bit must be set). */
+ if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX)
+ && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
+ {
+ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
+ }
+ /* Enable Tx */
+ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TE);
+
+ /* Enable the Peripheral */
+ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+
+ /* Perform a TX/RX FIFO Flush */
+ __HAL_SMARTCARD_FLUSH_DRREGISTER(hsmartcard);
+
+ /* Configure Tx interrupt processing */
+ if (hsmartcard->FifoMode == SMARTCARD_FIFOMODE_ENABLE)
+ {
+ /* Set the Tx ISR function pointer */
+ hsmartcard->TxISR = SMARTCARD_TxISR_FIFOEN;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmartcard);
+
+ /* Enable the SMARTCARD Error Interrupt: (Frame error) */
+ SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+
+ /* Enable the TX FIFO threshold interrupt */
+ SET_BIT(hsmartcard->Instance->CR3, USART_CR3_TXFTIE);
+ }
+ else
+ {
+ /* Set the Tx ISR function pointer */
+ hsmartcard->TxISR = SMARTCARD_TxISR;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmartcard);
+
+ /* Enable the SMARTCARD Error Interrupt: (Frame error) */
+ SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+
+ /* Enable the SMARTCARD Transmit Data Register Empty Interrupt */
+ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
+ }
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in interrupt mode.
+ * @note When FIFO mode is disabled, USART interrupt is generated whenever
+ * USART_RDR register can be read, i.e one interrupt per data to receive.
+ * @note When FIFO mode is enabled, USART interrupt is generated whenever
+ * RXFIFO threshold reached. In that case the interrupt rate depends on
+ * RXFIFO threshold configuration.
+ * @note This function sets the hsmartcard->RxIsr function pointer according to
+ * the FIFO mode (data reception processing depends on FIFO mode).
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @param pData pointer to data buffer.
+ * @param Size amount of data to be received.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
+{
+ /* Check that a Rx process is not already ongoing */
+ if (hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hsmartcard);
+
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_BUSY_RX;
+
+ hsmartcard->pRxBuffPtr = pData;
+ hsmartcard->RxXferSize = Size;
+ hsmartcard->RxXferCount = Size;
+
+ /* Configure Rx interrupt processing */
+ if ((hsmartcard->FifoMode == SMARTCARD_FIFOMODE_ENABLE) && (Size >= hsmartcard->NbRxDataToProcess))
+ {
+ /* Set the Rx ISR function pointer */
+ hsmartcard->RxISR = SMARTCARD_RxISR_FIFOEN;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmartcard);
+
+ /* Enable the SMARTCART Parity Error interrupt and RX FIFO Threshold interrupt */
+ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE);
+ SET_BIT(hsmartcard->Instance->CR3, USART_CR3_RXFTIE);
+ }
+ else
+ {
+ /* Set the Rx ISR function pointer */
+ hsmartcard->RxISR = SMARTCARD_RxISR;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmartcard);
+
+ /* Enable the SMARTCARD Parity Error and Data Register not empty Interrupts */
+ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE);
+ }
+
+ /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
+ SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Send an amount of data in DMA mode.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @param pData pointer to data buffer.
+ * @param Size amount of data to be sent.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard, const uint8_t *pData, uint16_t Size)
+{
+ /* Check that a Tx process is not already ongoing */
+ if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hsmartcard);
+
+ hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY_TX;
+
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+ hsmartcard->pTxBuffPtr = pData;
+ hsmartcard->TxXferSize = Size;
+ hsmartcard->TxXferCount = Size;
+
+ /* Disable the Peripheral first to update mode for TX master */
+ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+
+ /* In case of TX only mode, if NACK is enabled, the USART must be able to monitor
+ the bidirectional line to detect a NACK signal in case of parity error.
+ Therefore, the receiver block must be enabled as well (RE bit must be set). */
+ if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX)
+ && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
+ {
+ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
+ }
+ /* Enable Tx */
+ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TE);
+
+ /* Enable the Peripheral */
+ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+
+ /* Perform a TX/RX FIFO Flush */
+ __HAL_SMARTCARD_FLUSH_DRREGISTER(hsmartcard);
+
+ /* Set the SMARTCARD DMA transfer complete callback */
+ hsmartcard->hdmatx->XferCpltCallback = SMARTCARD_DMATransmitCplt;
+
+ /* Set the SMARTCARD error callback */
+ hsmartcard->hdmatx->XferErrorCallback = SMARTCARD_DMAError;
+
+ /* Set the DMA abort callback */
+ hsmartcard->hdmatx->XferAbortCallback = NULL;
+
+ /* Enable the SMARTCARD transmit DMA channel */
+ if (HAL_DMA_Start_IT(hsmartcard->hdmatx, (uint32_t)hsmartcard->pTxBuffPtr, (uint32_t)&hsmartcard->Instance->TDR,
+ Size) == HAL_OK)
+ {
+ /* Clear the TC flag in the ICR register */
+ CLEAR_BIT(hsmartcard->Instance->ICR, USART_ICR_TCCF);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmartcard);
+
+ /* Enable the UART Error Interrupt: (Frame error) */
+ SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+
+ /* Enable the DMA transfer for transmit request by setting the DMAT bit
+ in the SMARTCARD associated USART CR3 register */
+ SET_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
+
+ return HAL_OK;
+ }
+ else
+ {
+ /* Set error code to DMA */
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_DMA;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmartcard);
+
+ /* Restore hsmartcard->State to ready */
+ hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in DMA mode.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @param pData pointer to data buffer.
+ * @param Size amount of data to be received.
+ * @note The SMARTCARD-associated USART parity is enabled (PCE = 1),
+ * the received data contain the parity bit (MSB position).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
+{
+ /* Check that a Rx process is not already ongoing */
+ if (hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hsmartcard);
+
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_BUSY_RX;
+
+ hsmartcard->pRxBuffPtr = pData;
+ hsmartcard->RxXferSize = Size;
+
+ /* Set the SMARTCARD DMA transfer complete callback */
+ hsmartcard->hdmarx->XferCpltCallback = SMARTCARD_DMAReceiveCplt;
+
+ /* Set the SMARTCARD DMA error callback */
+ hsmartcard->hdmarx->XferErrorCallback = SMARTCARD_DMAError;
+
+ /* Set the DMA abort callback */
+ hsmartcard->hdmarx->XferAbortCallback = NULL;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(hsmartcard->hdmarx, (uint32_t)&hsmartcard->Instance->RDR, (uint32_t)hsmartcard->pRxBuffPtr,
+ Size) == HAL_OK)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmartcard);
+
+ /* Enable the SMARTCARD Parity Error Interrupt */
+ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE);
+
+ /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
+ SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+
+ /* Enable the DMA transfer for the receiver request by setting the DMAR bit
+ in the SMARTCARD associated USART CR3 register */
+ SET_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
+
+ return HAL_OK;
+ }
+ else
+ {
+ /* Set error code to DMA */
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_DMA;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmartcard);
+
+ /* Restore hsmartcard->State to ready */
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Abort ongoing transfers (blocking mode).
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable SMARTCARD Interrupts (Tx and Rx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE, RXFT, TXFT and
+ ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(hsmartcard->Instance->CR1,
+ (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE | USART_CR1_RTOIE |
+ USART_CR1_EOBIE));
+ CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE));
+
+ /* Disable the SMARTCARD DMA Tx request if enabled */
+ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
+ {
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the SMARTCARD DMA Tx channel : use blocking DMA Abort API (no callback) */
+ if (hsmartcard->hdmatx != NULL)
+ {
+ /* Set the SMARTCARD DMA Abort callback to Null.
+ No call back execution at end of DMA abort procedure */
+ hsmartcard->hdmatx->XferAbortCallback = NULL;
+
+ if (HAL_DMA_Abort(hsmartcard->hdmatx) != HAL_OK)
+ {
+ if (HAL_DMA_GetError(hsmartcard->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
+ {
+ /* Set error code to DMA */
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_DMA;
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+
+ /* Disable the SMARTCARD DMA Rx request if enabled */
+ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the SMARTCARD DMA Rx channel : use blocking DMA Abort API (no callback) */
+ if (hsmartcard->hdmarx != NULL)
+ {
+ /* Set the SMARTCARD DMA Abort callback to Null.
+ No call back execution at end of DMA abort procedure */
+ hsmartcard->hdmarx->XferAbortCallback = NULL;
+
+ if (HAL_DMA_Abort(hsmartcard->hdmarx) != HAL_OK)
+ {
+ if (HAL_DMA_GetError(hsmartcard->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
+ {
+ /* Set error code to DMA */
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_DMA;
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+
+ /* Reset Tx and Rx transfer counters */
+ hsmartcard->TxXferCount = 0U;
+ hsmartcard->RxXferCount = 0U;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
+ SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF |
+ SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
+
+ /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
+ hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+ /* Reset Handle ErrorCode to No Error */
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing Transmit transfer (blocking mode).
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable SMARTCARD Interrupts (Tx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Disable TCIE, TXEIE and TXFTIE interrupts */
+ CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_TXFTIE);
+
+ /* Check if a receive process is ongoing or not. If not disable ERR IT */
+ if (hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
+ {
+ /* Disable the SMARTCARD Error Interrupt: (Frame error) */
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+ }
+
+ /* Disable the SMARTCARD DMA Tx request if enabled */
+ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
+ {
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the SMARTCARD DMA Tx channel : use blocking DMA Abort API (no callback) */
+ if (hsmartcard->hdmatx != NULL)
+ {
+ /* Set the SMARTCARD DMA Abort callback to Null.
+ No call back execution at end of DMA abort procedure */
+ hsmartcard->hdmatx->XferAbortCallback = NULL;
+
+ if (HAL_DMA_Abort(hsmartcard->hdmatx) != HAL_OK)
+ {
+ if (HAL_DMA_GetError(hsmartcard->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
+ {
+ /* Set error code to DMA */
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_DMA;
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+
+ /* Reset Tx transfer counter */
+ hsmartcard->TxXferCount = 0U;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_FEF);
+
+ /* Restore hsmartcard->gState to Ready */
+ hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing Receive transfer (blocking mode).
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable SMARTCARD Interrupts (Rx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Disable RTOIE, EOBIE, RXNE, PE, RXFT, TXFT and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE |
+ USART_CR1_EOBIE));
+ CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
+
+ /* Check if a Transmit process is ongoing or not. If not disable ERR IT */
+ if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
+ {
+ /* Disable the SMARTCARD Error Interrupt: (Frame error) */
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+ }
+
+ /* Disable the SMARTCARD DMA Rx request if enabled */
+ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the SMARTCARD DMA Rx channel : use blocking DMA Abort API (no callback) */
+ if (hsmartcard->hdmarx != NULL)
+ {
+ /* Set the SMARTCARD DMA Abort callback to Null.
+ No call back execution at end of DMA abort procedure */
+ hsmartcard->hdmarx->XferAbortCallback = NULL;
+
+ if (HAL_DMA_Abort(hsmartcard->hdmarx) != HAL_OK)
+ {
+ if (HAL_DMA_GetError(hsmartcard->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
+ {
+ /* Set error code to DMA */
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_DMA;
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+
+ /* Reset Rx transfer counter */
+ hsmartcard->RxXferCount = 0U;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
+ SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF |
+ SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
+
+ /* Restore hsmartcard->RxState to Ready */
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing transfers (Interrupt mode).
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable SMARTCARD Interrupts (Tx and Rx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * - At abort completion, call user abort complete callback
+ * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
+ * considered as completed only when user abort complete callback is executed (not when exiting function).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ uint32_t abortcplt = 1U;
+
+ /* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE, RXFT, TXFT and
+ ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(hsmartcard->Instance->CR1,
+ (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE | USART_CR1_RTOIE |
+ USART_CR1_EOBIE));
+ CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE));
+
+ /* If DMA Tx and/or DMA Rx Handles are associated to SMARTCARD Handle,
+ DMA Abort complete callbacks should be initialised before any call
+ to DMA Abort functions */
+ /* DMA Tx Handle is valid */
+ if (hsmartcard->hdmatx != NULL)
+ {
+ /* Set DMA Abort Complete callback if SMARTCARD DMA Tx request if enabled.
+ Otherwise, set it to NULL */
+ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
+ {
+ hsmartcard->hdmatx->XferAbortCallback = SMARTCARD_DMATxAbortCallback;
+ }
+ else
+ {
+ hsmartcard->hdmatx->XferAbortCallback = NULL;
+ }
+ }
+ /* DMA Rx Handle is valid */
+ if (hsmartcard->hdmarx != NULL)
+ {
+ /* Set DMA Abort Complete callback if SMARTCARD DMA Rx request if enabled.
+ Otherwise, set it to NULL */
+ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
+ {
+ hsmartcard->hdmarx->XferAbortCallback = SMARTCARD_DMARxAbortCallback;
+ }
+ else
+ {
+ hsmartcard->hdmarx->XferAbortCallback = NULL;
+ }
+ }
+
+ /* Disable the SMARTCARD DMA Tx request if enabled */
+ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
+ {
+ /* Disable DMA Tx at UART level */
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the SMARTCARD DMA Tx channel : use non blocking DMA Abort API (callback) */
+ if (hsmartcard->hdmatx != NULL)
+ {
+ /* SMARTCARD Tx DMA Abort callback has already been initialised :
+ will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
+
+ /* Abort DMA TX */
+ if (HAL_DMA_Abort_IT(hsmartcard->hdmatx) != HAL_OK)
+ {
+ hsmartcard->hdmatx->XferAbortCallback = NULL;
+ }
+ else
+ {
+ abortcplt = 0U;
+ }
+ }
+ }
+
+ /* Disable the SMARTCARD DMA Rx request if enabled */
+ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the SMARTCARD DMA Rx channel : use non blocking DMA Abort API (callback) */
+ if (hsmartcard->hdmarx != NULL)
+ {
+ /* SMARTCARD Rx DMA Abort callback has already been initialised :
+ will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
+
+ /* Abort DMA RX */
+ if (HAL_DMA_Abort_IT(hsmartcard->hdmarx) != HAL_OK)
+ {
+ hsmartcard->hdmarx->XferAbortCallback = NULL;
+ abortcplt = 1U;
+ }
+ else
+ {
+ abortcplt = 0U;
+ }
+ }
+ }
+
+ /* if no DMA abort complete callback execution is required => call user Abort Complete callback */
+ if (abortcplt == 1U)
+ {
+ /* Reset Tx and Rx transfer counters */
+ hsmartcard->TxXferCount = 0U;
+ hsmartcard->RxXferCount = 0U;
+
+ /* Clear ISR function pointers */
+ hsmartcard->RxISR = NULL;
+ hsmartcard->TxISR = NULL;
+
+ /* Reset errorCode */
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
+ SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF |
+ SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
+
+ /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
+ hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort complete callback */
+ hsmartcard->AbortCpltCallback(hsmartcard);
+#else
+ /* Call legacy weak Abort complete callback */
+ HAL_SMARTCARD_AbortCpltCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing Transmit transfer (Interrupt mode).
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable SMARTCARD Interrupts (Tx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * - At abort completion, call user abort complete callback
+ * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
+ * considered as completed only when user abort complete callback is executed (not when exiting function).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Disable TCIE, TXEIE and TXFTIE interrupts */
+ CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_TXFTIE);
+
+ /* Check if a receive process is ongoing or not. If not disable ERR IT */
+ if (hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
+ {
+ /* Disable the SMARTCARD Error Interrupt: (Frame error) */
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+ }
+
+ /* Disable the SMARTCARD DMA Tx request if enabled */
+ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
+ {
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the SMARTCARD DMA Tx channel : use non blocking DMA Abort API (callback) */
+ if (hsmartcard->hdmatx != NULL)
+ {
+ /* Set the SMARTCARD DMA Abort callback :
+ will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
+ hsmartcard->hdmatx->XferAbortCallback = SMARTCARD_DMATxOnlyAbortCallback;
+
+ /* Abort DMA TX */
+ if (HAL_DMA_Abort_IT(hsmartcard->hdmatx) != HAL_OK)
+ {
+ /* Call Directly hsmartcard->hdmatx->XferAbortCallback function in case of error */
+ hsmartcard->hdmatx->XferAbortCallback(hsmartcard->hdmatx);
+ }
+ }
+ else
+ {
+ /* Reset Tx transfer counter */
+ hsmartcard->TxXferCount = 0U;
+
+ /* Clear TxISR function pointers */
+ hsmartcard->TxISR = NULL;
+
+ /* Restore hsmartcard->gState to Ready */
+ hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Transmit Complete Callback */
+ hsmartcard->AbortTransmitCpltCallback(hsmartcard);
+#else
+ /* Call legacy weak Abort Transmit Complete Callback */
+ HAL_SMARTCARD_AbortTransmitCpltCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
+ }
+ }
+ else
+ {
+ /* Reset Tx transfer counter */
+ hsmartcard->TxXferCount = 0U;
+
+ /* Clear TxISR function pointers */
+ hsmartcard->TxISR = NULL;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_FEF);
+
+ /* Restore hsmartcard->gState to Ready */
+ hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Transmit Complete Callback */
+ hsmartcard->AbortTransmitCpltCallback(hsmartcard);
+#else
+ /* Call legacy weak Abort Transmit Complete Callback */
+ HAL_SMARTCARD_AbortTransmitCpltCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing Receive transfer (Interrupt mode).
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable SMARTCARD Interrupts (Rx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * - At abort completion, call user abort complete callback
+ * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
+ * considered as completed only when user abort complete callback is executed (not when exiting function).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Disable RTOIE, EOBIE, RXNE, PE, RXFT and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE |
+ USART_CR1_EOBIE));
+ CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
+
+ /* Check if a Transmit process is ongoing or not. If not disable ERR IT */
+ if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
+ {
+ /* Disable the SMARTCARD Error Interrupt: (Frame error) */
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+ }
+
+ /* Disable the SMARTCARD DMA Rx request if enabled */
+ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the SMARTCARD DMA Rx channel : use non blocking DMA Abort API (callback) */
+ if (hsmartcard->hdmarx != NULL)
+ {
+ /* Set the SMARTCARD DMA Abort callback :
+ will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
+ hsmartcard->hdmarx->XferAbortCallback = SMARTCARD_DMARxOnlyAbortCallback;
+
+ /* Abort DMA RX */
+ if (HAL_DMA_Abort_IT(hsmartcard->hdmarx) != HAL_OK)
+ {
+ /* Call Directly hsmartcard->hdmarx->XferAbortCallback function in case of error */
+ hsmartcard->hdmarx->XferAbortCallback(hsmartcard->hdmarx);
+ }
+ }
+ else
+ {
+ /* Reset Rx transfer counter */
+ hsmartcard->RxXferCount = 0U;
+
+ /* Clear RxISR function pointer */
+ hsmartcard->RxISR = NULL;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
+ SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF |
+ SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
+
+ /* Restore hsmartcard->RxState to Ready */
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Receive Complete Callback */
+ hsmartcard->AbortReceiveCpltCallback(hsmartcard);
+#else
+ /* Call legacy weak Abort Receive Complete Callback */
+ HAL_SMARTCARD_AbortReceiveCpltCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
+ }
+ }
+ else
+ {
+ /* Reset Rx transfer counter */
+ hsmartcard->RxXferCount = 0U;
+
+ /* Clear RxISR function pointer */
+ hsmartcard->RxISR = NULL;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
+ SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF |
+ SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
+
+ /* Restore hsmartcard->RxState to Ready */
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Receive Complete Callback */
+ hsmartcard->AbortReceiveCpltCallback(hsmartcard);
+#else
+ /* Call legacy weak Abort Receive Complete Callback */
+ HAL_SMARTCARD_AbortReceiveCpltCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle SMARTCARD interrupt requests.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval None
+ */
+void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ uint32_t isrflags = READ_REG(hsmartcard->Instance->ISR);
+ uint32_t cr1its = READ_REG(hsmartcard->Instance->CR1);
+ uint32_t cr3its = READ_REG(hsmartcard->Instance->CR3);
+ uint32_t errorflags;
+ uint32_t errorcode;
+
+ /* If no error occurs */
+ errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF));
+ if (errorflags == 0U)
+ {
+ /* SMARTCARD in mode Receiver ---------------------------------------------------*/
+ if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U)
+ && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)
+ || ((cr3its & USART_CR3_RXFTIE) != 0U)))
+ {
+ if (hsmartcard->RxISR != NULL)
+ {
+ hsmartcard->RxISR(hsmartcard);
+ }
+ return;
+ }
+ }
+
+ /* If some errors occur */
+ if ((errorflags != 0U)
+ && ((((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U)
+ || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)) != 0U))))
+ {
+ /* SMARTCARD parity error interrupt occurred -------------------------------------*/
+ if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
+ {
+ __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_PEF);
+
+ hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_PE;
+ }
+
+ /* SMARTCARD frame error interrupt occurred --------------------------------------*/
+ if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
+ {
+ __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_FEF);
+
+ hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_FE;
+ }
+
+ /* SMARTCARD noise error interrupt occurred --------------------------------------*/
+ if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
+ {
+ __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_NEF);
+
+ hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_NE;
+ }
+
+ /* SMARTCARD Over-Run interrupt occurred -----------------------------------------*/
+ if (((isrflags & USART_ISR_ORE) != 0U)
+ && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)
+ || ((cr3its & USART_CR3_RXFTIE) != 0U)
+ || ((cr3its & USART_CR3_EIE) != 0U)))
+ {
+ __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_OREF);
+
+ hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_ORE;
+ }
+
+ /* SMARTCARD receiver timeout interrupt occurred -----------------------------------------*/
+ if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U))
+ {
+ __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_RTOF);
+
+ hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_RTO;
+ }
+
+ /* Call SMARTCARD Error Call back function if need be --------------------------*/
+ if (hsmartcard->ErrorCode != HAL_SMARTCARD_ERROR_NONE)
+ {
+ /* SMARTCARD in mode Receiver ---------------------------------------------------*/
+ if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U)
+ && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)
+ || ((cr3its & USART_CR3_RXFTIE) != 0U)))
+ {
+ if (hsmartcard->RxISR != NULL)
+ {
+ hsmartcard->RxISR(hsmartcard);
+ }
+ }
+
+ /* If Error is to be considered as blocking :
+ - Receiver Timeout error in Reception
+ - Overrun error in Reception
+ - any error occurs in DMA mode reception
+ */
+ errorcode = hsmartcard->ErrorCode;
+ if ((HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
+ || ((errorcode & (HAL_SMARTCARD_ERROR_RTO | HAL_SMARTCARD_ERROR_ORE)) != 0U))
+ {
+ /* Blocking error : transfer is aborted
+ Set the SMARTCARD state ready to be able to start again the process,
+ Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
+ SMARTCARD_EndRxTransfer(hsmartcard);
+
+ /* Disable the SMARTCARD DMA Rx request if enabled */
+ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the SMARTCARD DMA Rx channel */
+ if (hsmartcard->hdmarx != NULL)
+ {
+ /* Set the SMARTCARD DMA Abort callback :
+ will lead to call HAL_SMARTCARD_ErrorCallback() at end of DMA abort procedure */
+ hsmartcard->hdmarx->XferAbortCallback = SMARTCARD_DMAAbortOnError;
+
+ /* Abort DMA RX */
+ if (HAL_DMA_Abort_IT(hsmartcard->hdmarx) != HAL_OK)
+ {
+ /* Call Directly hsmartcard->hdmarx->XferAbortCallback function in case of error */
+ hsmartcard->hdmarx->XferAbortCallback(hsmartcard->hdmarx);
+ }
+ }
+ else
+ {
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered user error callback */
+ hsmartcard->ErrorCallback(hsmartcard);
+#else
+ /* Call legacy weak user error callback */
+ HAL_SMARTCARD_ErrorCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
+ }
+ }
+ else
+ {
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered user error callback */
+ hsmartcard->ErrorCallback(hsmartcard);
+#else
+ /* Call legacy weak user error callback */
+ HAL_SMARTCARD_ErrorCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
+ }
+ }
+ /* other error type to be considered as blocking :
+ - Frame error in Transmission
+ */
+ else if ((hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX)
+ && ((errorcode & HAL_SMARTCARD_ERROR_FE) != 0U))
+ {
+ /* Blocking error : transfer is aborted
+ Set the SMARTCARD state ready to be able to start again the process,
+ Disable Tx Interrupts, and disable Tx DMA request, if ongoing */
+ SMARTCARD_EndTxTransfer(hsmartcard);
+
+ /* Disable the SMARTCARD DMA Tx request if enabled */
+ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
+ {
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the SMARTCARD DMA Tx channel */
+ if (hsmartcard->hdmatx != NULL)
+ {
+ /* Set the SMARTCARD DMA Abort callback :
+ will lead to call HAL_SMARTCARD_ErrorCallback() at end of DMA abort procedure */
+ hsmartcard->hdmatx->XferAbortCallback = SMARTCARD_DMAAbortOnError;
+
+ /* Abort DMA TX */
+ if (HAL_DMA_Abort_IT(hsmartcard->hdmatx) != HAL_OK)
+ {
+ /* Call Directly hsmartcard->hdmatx->XferAbortCallback function in case of error */
+ hsmartcard->hdmatx->XferAbortCallback(hsmartcard->hdmatx);
+ }
+ }
+ else
+ {
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered user error callback */
+ hsmartcard->ErrorCallback(hsmartcard);
+#else
+ /* Call legacy weak user error callback */
+ HAL_SMARTCARD_ErrorCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
+ }
+ }
+ else
+ {
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered user error callback */
+ hsmartcard->ErrorCallback(hsmartcard);
+#else
+ /* Call legacy weak user error callback */
+ HAL_SMARTCARD_ErrorCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
+ }
+ }
+ else
+ {
+ /* Non Blocking error : transfer could go on.
+ Error is notified to user through user error callback */
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered user error callback */
+ hsmartcard->ErrorCallback(hsmartcard);
+#else
+ /* Call legacy weak user error callback */
+ HAL_SMARTCARD_ErrorCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+ }
+ }
+ return;
+
+ } /* End if some error occurs */
+
+ /* SMARTCARD in mode Receiver, end of block interruption ------------------------*/
+ if (((isrflags & USART_ISR_EOBF) != 0U) && ((cr1its & USART_CR1_EOBIE) != 0U))
+ {
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+ __HAL_UNLOCK(hsmartcard);
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered Rx complete callback */
+ hsmartcard->RxCpltCallback(hsmartcard);
+#else
+ /* Call legacy weak Rx complete callback */
+ HAL_SMARTCARD_RxCpltCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
+ /* Clear EOBF interrupt after HAL_SMARTCARD_RxCpltCallback() call for the End of Block information
+ to be available during HAL_SMARTCARD_RxCpltCallback() processing */
+ __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_EOBF);
+ return;
+ }
+
+ /* SMARTCARD in mode Transmitter ------------------------------------------------*/
+ if (((isrflags & USART_ISR_TXE_TXFNF) != 0U)
+ && (((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U)
+ || ((cr3its & USART_CR3_TXFTIE) != 0U)))
+ {
+ if (hsmartcard->TxISR != NULL)
+ {
+ hsmartcard->TxISR(hsmartcard);
+ }
+ return;
+ }
+
+ /* SMARTCARD in mode Transmitter (transmission end) ------------------------*/
+ if (__HAL_SMARTCARD_GET_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication) != RESET)
+ {
+ if (__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication) != RESET)
+ {
+ SMARTCARD_EndTransmit_IT(hsmartcard);
+ return;
+ }
+ }
+
+ /* SMARTCARD TX Fifo Empty occurred ----------------------------------------------*/
+ if (((isrflags & USART_ISR_TXFE) != 0U) && ((cr1its & USART_CR1_TXFEIE) != 0U))
+ {
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered Tx Fifo Empty Callback */
+ hsmartcard->TxFifoEmptyCallback(hsmartcard);
+#else
+ /* Call legacy weak Tx Fifo Empty Callback */
+ HAL_SMARTCARDEx_TxFifoEmptyCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
+ return;
+ }
+
+ /* SMARTCARD RX Fifo Full occurred ----------------------------------------------*/
+ if (((isrflags & USART_ISR_RXFF) != 0U) && ((cr1its & USART_CR1_RXFFIE) != 0U))
+ {
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered Rx Fifo Full Callback */
+ hsmartcard->RxFifoFullCallback(hsmartcard);
+#else
+ /* Call legacy weak Rx Fifo Full Callback */
+ HAL_SMARTCARDEx_RxFifoFullCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
+ return;
+ }
+}
+
+/**
+ * @brief Tx Transfer completed callback.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval None
+ */
+__weak void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsmartcard);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMARTCARD_TxCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief Rx Transfer completed callback.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval None
+ */
+__weak void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsmartcard);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMARTCARD_RxCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief SMARTCARD error callback.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval None
+ */
+__weak void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsmartcard);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMARTCARD_ErrorCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief SMARTCARD Abort Complete callback.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval None
+ */
+__weak void HAL_SMARTCARD_AbortCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsmartcard);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMARTCARD_AbortCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief SMARTCARD Abort Complete callback.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval None
+ */
+__weak void HAL_SMARTCARD_AbortTransmitCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsmartcard);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMARTCARD_AbortTransmitCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief SMARTCARD Abort Receive Complete callback.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval None
+ */
+__weak void HAL_SMARTCARD_AbortReceiveCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsmartcard);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMARTCARD_AbortReceiveCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Exported_Functions_Group4 Peripheral State and Errors functions
+ * @brief SMARTCARD State and Errors functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral State and Errors functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to return the State of SmartCard
+ handle and also return Peripheral Errors occurred during communication process
+ (+) HAL_SMARTCARD_GetState() API can be helpful to check in run-time the state
+ of the SMARTCARD peripheral.
+ (+) HAL_SMARTCARD_GetError() checks in run-time errors that could occur during
+ communication.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the SMARTCARD handle state.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval SMARTCARD handle state
+ */
+HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Return SMARTCARD handle state */
+ uint32_t temp1;
+ uint32_t temp2;
+ temp1 = (uint32_t)hsmartcard->gState;
+ temp2 = (uint32_t)hsmartcard->RxState;
+
+ return (HAL_SMARTCARD_StateTypeDef)(temp1 | temp2);
+}
+
+/**
+ * @brief Return the SMARTCARD handle error code.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval SMARTCARD handle Error Code
+ */
+uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ return hsmartcard->ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Private_Functions SMARTCARD Private Functions
+ * @{
+ */
+
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Initialize the callbacks to their default values.
+ * @param hsmartcard SMARTCARD handle.
+ * @retval none
+ */
+void SMARTCARD_InitCallbacksToDefault(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Init the SMARTCARD Callback settings */
+ hsmartcard->TxCpltCallback = HAL_SMARTCARD_TxCpltCallback; /* Legacy weak TxCpltCallback */
+ hsmartcard->RxCpltCallback = HAL_SMARTCARD_RxCpltCallback; /* Legacy weak RxCpltCallback */
+ hsmartcard->ErrorCallback = HAL_SMARTCARD_ErrorCallback; /* Legacy weak ErrorCallback */
+ hsmartcard->AbortCpltCallback = HAL_SMARTCARD_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
+ hsmartcard->AbortTransmitCpltCallback = HAL_SMARTCARD_AbortTransmitCpltCallback; /* Legacy weak
+ AbortTransmitCpltCallback */
+ hsmartcard->AbortReceiveCpltCallback = HAL_SMARTCARD_AbortReceiveCpltCallback; /* Legacy weak
+ AbortReceiveCpltCallback */
+ hsmartcard->RxFifoFullCallback = HAL_SMARTCARDEx_RxFifoFullCallback; /* Legacy weak
+ RxFifoFullCallback */
+ hsmartcard->TxFifoEmptyCallback = HAL_SMARTCARDEx_TxFifoEmptyCallback; /* Legacy weak
+ TxFifoEmptyCallback */
+
+}
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
+
+/**
+ * @brief Configure the SMARTCARD associated USART peripheral.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ uint32_t tmpreg;
+ SMARTCARD_ClockSourceTypeDef clocksource;
+ HAL_StatusTypeDef ret = HAL_OK;
+ static const uint16_t SMARTCARDPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U};
+ uint32_t pclk;
+
+ /* Check the parameters */
+ assert_param(IS_SMARTCARD_INSTANCE(hsmartcard->Instance));
+ assert_param(IS_SMARTCARD_BAUDRATE(hsmartcard->Init.BaudRate));
+ assert_param(IS_SMARTCARD_WORD_LENGTH(hsmartcard->Init.WordLength));
+ assert_param(IS_SMARTCARD_STOPBITS(hsmartcard->Init.StopBits));
+ assert_param(IS_SMARTCARD_PARITY(hsmartcard->Init.Parity));
+ assert_param(IS_SMARTCARD_MODE(hsmartcard->Init.Mode));
+ assert_param(IS_SMARTCARD_POLARITY(hsmartcard->Init.CLKPolarity));
+ assert_param(IS_SMARTCARD_PHASE(hsmartcard->Init.CLKPhase));
+ assert_param(IS_SMARTCARD_LASTBIT(hsmartcard->Init.CLKLastBit));
+ assert_param(IS_SMARTCARD_ONE_BIT_SAMPLE(hsmartcard->Init.OneBitSampling));
+ assert_param(IS_SMARTCARD_NACK(hsmartcard->Init.NACKEnable));
+ assert_param(IS_SMARTCARD_TIMEOUT(hsmartcard->Init.TimeOutEnable));
+ assert_param(IS_SMARTCARD_AUTORETRY_COUNT(hsmartcard->Init.AutoRetryCount));
+ assert_param(IS_SMARTCARD_CLOCKPRESCALER(hsmartcard->Init.ClockPrescaler));
+
+ /*-------------------------- USART CR1 Configuration -----------------------*/
+ /* In SmartCard mode, M and PCE are forced to 1 (8 bits + parity).
+ * Oversampling is forced to 16 (OVER8 = 0).
+ * Configure the Parity and Mode:
+ * set PS bit according to hsmartcard->Init.Parity value
+ * set TE and RE bits according to hsmartcard->Init.Mode value */
+ tmpreg = (((uint32_t)hsmartcard->Init.Parity) | ((uint32_t)hsmartcard->Init.Mode) |
+ ((uint32_t)hsmartcard->Init.WordLength));
+ MODIFY_REG(hsmartcard->Instance->CR1, USART_CR1_FIELDS, tmpreg);
+
+ /*-------------------------- USART CR2 Configuration -----------------------*/
+ tmpreg = hsmartcard->Init.StopBits;
+ /* Synchronous mode is activated by default */
+ tmpreg |= (uint32_t) USART_CR2_CLKEN | hsmartcard->Init.CLKPolarity;
+ tmpreg |= (uint32_t) hsmartcard->Init.CLKPhase | hsmartcard->Init.CLKLastBit;
+ tmpreg |= (uint32_t) hsmartcard->Init.TimeOutEnable;
+ MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_FIELDS, tmpreg);
+
+ /*-------------------------- USART CR3 Configuration -----------------------*/
+ /* Configure
+ * - one-bit sampling method versus three samples' majority rule
+ * according to hsmartcard->Init.OneBitSampling
+ * - NACK transmission in case of parity error according
+ * to hsmartcard->Init.NACKEnable
+ * - autoretry counter according to hsmartcard->Init.AutoRetryCount */
+
+ tmpreg = (uint32_t) hsmartcard->Init.OneBitSampling | hsmartcard->Init.NACKEnable;
+ tmpreg |= ((uint32_t)hsmartcard->Init.AutoRetryCount << USART_CR3_SCARCNT_Pos);
+ MODIFY_REG(hsmartcard->Instance->CR3, USART_CR3_FIELDS, tmpreg);
+
+ /*--------------------- SMARTCARD clock PRESC Configuration ----------------*/
+ /* Configure
+ * - SMARTCARD Clock Prescaler: set PRESCALER according to hsmartcard->Init.ClockPrescaler value */
+ MODIFY_REG(hsmartcard->Instance->PRESC, USART_PRESC_PRESCALER, hsmartcard->Init.ClockPrescaler);
+
+ /*-------------------------- USART GTPR Configuration ----------------------*/
+ tmpreg = (hsmartcard->Init.Prescaler | ((uint32_t)hsmartcard->Init.GuardTime << USART_GTPR_GT_Pos));
+ MODIFY_REG(hsmartcard->Instance->GTPR, (uint16_t)(USART_GTPR_GT | USART_GTPR_PSC), (uint16_t)tmpreg);
+
+ /*-------------------------- USART RTOR Configuration ----------------------*/
+ tmpreg = ((uint32_t)hsmartcard->Init.BlockLength << USART_RTOR_BLEN_Pos);
+ if (hsmartcard->Init.TimeOutEnable == SMARTCARD_TIMEOUT_ENABLE)
+ {
+ assert_param(IS_SMARTCARD_TIMEOUT_VALUE(hsmartcard->Init.TimeOutValue));
+ tmpreg |= (uint32_t) hsmartcard->Init.TimeOutValue;
+ }
+ MODIFY_REG(hsmartcard->Instance->RTOR, (USART_RTOR_RTO | USART_RTOR_BLEN), tmpreg);
+
+ /*-------------------------- USART BRR Configuration -----------------------*/
+ SMARTCARD_GETCLOCKSOURCE(hsmartcard, clocksource);
+ tmpreg = 0U;
+ switch (clocksource)
+ {
+ case SMARTCARD_CLOCKSOURCE_PCLK1:
+ pclk = HAL_RCC_GetPCLK1Freq();
+ tmpreg = (uint32_t)(((pclk / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) +
+ (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
+ break;
+ case SMARTCARD_CLOCKSOURCE_HSI:
+ pclk = (HSI_VALUE / ((__HAL_RCC_GET_HSIKER_DIVIDER() >> RCC_CR_HSIKERDIV_Pos) + 1U));
+ tmpreg = (uint32_t)(((pclk / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) +
+ (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
+ break;
+ case SMARTCARD_CLOCKSOURCE_SYSCLK:
+ pclk = HAL_RCC_GetSysClockFreq();
+ tmpreg = (uint32_t)(((pclk / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) +
+ (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
+ break;
+ case SMARTCARD_CLOCKSOURCE_LSE:
+ tmpreg = (uint32_t)(((uint16_t)(LSE_VALUE / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) +
+ (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
+ break;
+ default:
+ ret = HAL_ERROR;
+ break;
+ }
+
+ /* USARTDIV must be greater than or equal to 0d16 */
+ if ((tmpreg >= USART_BRR_MIN) && (tmpreg <= USART_BRR_MAX))
+ {
+ hsmartcard->Instance->BRR = (uint16_t)tmpreg;
+ }
+ else
+ {
+ ret = HAL_ERROR;
+ }
+
+ /* Initialize the number of data to process during RX/TX ISR execution */
+ hsmartcard->NbTxDataToProcess = 1U;
+ hsmartcard->NbRxDataToProcess = 1U;
+
+ /* Clear ISR function pointers */
+ hsmartcard->RxISR = NULL;
+ hsmartcard->TxISR = NULL;
+
+ return ret;
+}
+
+
+/**
+ * @brief Configure the SMARTCARD associated USART peripheral advanced features.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval None
+ */
+static void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Check whether the set of advanced features to configure is properly set */
+ assert_param(IS_SMARTCARD_ADVFEATURE_INIT(hsmartcard->AdvancedInit.AdvFeatureInit));
+
+ /* if required, configure TX pin active level inversion */
+ if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_TXINVERT_INIT))
+ {
+ assert_param(IS_SMARTCARD_ADVFEATURE_TXINV(hsmartcard->AdvancedInit.TxPinLevelInvert));
+ MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_TXINV, hsmartcard->AdvancedInit.TxPinLevelInvert);
+ }
+
+ /* if required, configure RX pin active level inversion */
+ if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_RXINVERT_INIT))
+ {
+ assert_param(IS_SMARTCARD_ADVFEATURE_RXINV(hsmartcard->AdvancedInit.RxPinLevelInvert));
+ MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_RXINV, hsmartcard->AdvancedInit.RxPinLevelInvert);
+ }
+
+ /* if required, configure data inversion */
+ if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_DATAINVERT_INIT))
+ {
+ assert_param(IS_SMARTCARD_ADVFEATURE_DATAINV(hsmartcard->AdvancedInit.DataInvert));
+ MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_DATAINV, hsmartcard->AdvancedInit.DataInvert);
+ }
+
+ /* if required, configure RX/TX pins swap */
+ if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_SWAP_INIT))
+ {
+ assert_param(IS_SMARTCARD_ADVFEATURE_SWAP(hsmartcard->AdvancedInit.Swap));
+ MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_SWAP, hsmartcard->AdvancedInit.Swap);
+ }
+
+ /* if required, configure RX overrun detection disabling */
+ if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT))
+ {
+ assert_param(IS_SMARTCARD_OVERRUN(hsmartcard->AdvancedInit.OverrunDisable));
+ MODIFY_REG(hsmartcard->Instance->CR3, USART_CR3_OVRDIS, hsmartcard->AdvancedInit.OverrunDisable);
+ }
+
+ /* if required, configure DMA disabling on reception error */
+ if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT))
+ {
+ assert_param(IS_SMARTCARD_ADVFEATURE_DMAONRXERROR(hsmartcard->AdvancedInit.DMADisableonRxError));
+ MODIFY_REG(hsmartcard->Instance->CR3, USART_CR3_DDRE, hsmartcard->AdvancedInit.DMADisableonRxError);
+ }
+
+ /* if required, configure MSB first on communication line */
+ if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_MSBFIRST_INIT))
+ {
+ assert_param(IS_SMARTCARD_ADVFEATURE_MSBFIRST(hsmartcard->AdvancedInit.MSBFirst));
+ MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_MSBFIRST, hsmartcard->AdvancedInit.MSBFirst);
+ }
+
+}
+
+/**
+ * @brief Check the SMARTCARD Idle State.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ uint32_t tickstart;
+
+ /* Initialize the SMARTCARD ErrorCode */
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+
+ /* Init tickstart for timeout management */
+ tickstart = HAL_GetTick();
+
+ /* Check if the Transmitter is enabled */
+ if ((hsmartcard->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
+ {
+ /* Wait until TEACK flag is set */
+ if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, USART_ISR_TEACK, RESET, tickstart,
+ SMARTCARD_TEACK_REACK_TIMEOUT) != HAL_OK)
+ {
+ /* Timeout occurred */
+ return HAL_TIMEOUT;
+ }
+ }
+ /* Check if the Receiver is enabled */
+ if ((hsmartcard->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
+ {
+ /* Wait until REACK flag is set */
+ if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, USART_ISR_REACK, RESET, tickstart,
+ SMARTCARD_TEACK_REACK_TIMEOUT) != HAL_OK)
+ {
+ /* Timeout occurred */
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Initialize the SMARTCARD states */
+ hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmartcard);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle SMARTCARD Communication Timeout. It waits
+ * until a flag is no longer in the specified status.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @param Flag Specifies the SMARTCARD flag to check.
+ * @param Status The actual Flag status (SET or RESET).
+ * @param Tickstart Tick start value
+ * @param Timeout Timeout duration.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Flag,
+ FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
+{
+ /* Wait until flag is set */
+ while ((__HAL_SMARTCARD_GET_FLAG(hsmartcard, Flag) ? SET : RESET) == Status)
+ {
+ /* Check for the Timeout */
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
+ {
+ /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error)
+ interrupts for the interrupt process */
+ CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE));
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+
+ hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmartcard);
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ return HAL_OK;
+}
+
+
+/**
+ * @brief End ongoing Tx transfer on SMARTCARD peripheral (following error detection or Transmit completion).
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval None
+ */
+static void SMARTCARD_EndTxTransfer(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Disable TXEIE, TCIE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+
+ /* At end of Tx process, restore hsmartcard->gState to Ready */
+ hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+}
+
+
+/**
+ * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval None
+ */
+static void SMARTCARD_EndRxTransfer(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+
+ /* At end of Rx process, restore hsmartcard->RxState to Ready */
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+}
+
+
+/**
+ * @brief DMA SMARTCARD transmit process complete callback.
+ * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma)
+{
+ SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent);
+ hsmartcard->TxXferCount = 0U;
+
+ /* Disable the DMA transfer for transmit request by resetting the DMAT bit
+ in the SMARTCARD associated USART CR3 register */
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
+
+ /* Enable the SMARTCARD Transmit Complete Interrupt */
+ __HAL_SMARTCARD_ENABLE_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication);
+}
+
+/**
+ * @brief DMA SMARTCARD receive process complete callback.
+ * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+ SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent);
+ hsmartcard->RxXferCount = 0U;
+
+ /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE);
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+
+ /* Disable the DMA transfer for the receiver request by resetting the DMAR bit
+ in the SMARTCARD associated USART CR3 register */
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
+
+ /* At end of Rx process, restore hsmartcard->RxState to Ready */
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered Rx complete callback */
+ hsmartcard->RxCpltCallback(hsmartcard);
+#else
+ /* Call legacy weak Rx complete callback */
+ HAL_SMARTCARD_RxCpltCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
+}
+
+/**
+ * @brief DMA SMARTCARD communication error callback.
+ * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma)
+{
+ SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent);
+
+ /* Stop SMARTCARD DMA Tx request if ongoing */
+ if (hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX)
+ {
+ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
+ {
+ hsmartcard->TxXferCount = 0U;
+ SMARTCARD_EndTxTransfer(hsmartcard);
+ }
+ }
+
+ /* Stop SMARTCARD DMA Rx request if ongoing */
+ if (hsmartcard->RxState == HAL_SMARTCARD_STATE_BUSY_RX)
+ {
+ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
+ {
+ hsmartcard->RxXferCount = 0U;
+ SMARTCARD_EndRxTransfer(hsmartcard);
+ }
+ }
+
+ hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_DMA;
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered user error callback */
+ hsmartcard->ErrorCallback(hsmartcard);
+#else
+ /* Call legacy weak user error callback */
+ HAL_SMARTCARD_ErrorCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
+}
+
+/**
+ * @brief DMA SMARTCARD communication abort callback, when initiated by HAL services on Error
+ * (To be called at end of DMA Abort procedure following error occurrence).
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void SMARTCARD_DMAAbortOnError(DMA_HandleTypeDef *hdma)
+{
+ SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent);
+ hsmartcard->RxXferCount = 0U;
+ hsmartcard->TxXferCount = 0U;
+
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered user error callback */
+ hsmartcard->ErrorCallback(hsmartcard);
+#else
+ /* Call legacy weak user error callback */
+ HAL_SMARTCARD_ErrorCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
+}
+
+/**
+ * @brief DMA SMARTCARD Tx communication abort callback, when initiated by user
+ * (To be called at end of DMA Tx Abort procedure following user abort request).
+ * @note When this callback is executed, User Abort complete call back is called only if no
+ * Abort still ongoing for Rx DMA Handle.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void SMARTCARD_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent);
+
+ hsmartcard->hdmatx->XferAbortCallback = NULL;
+
+ /* Check if an Abort process is still ongoing */
+ if (hsmartcard->hdmarx != NULL)
+ {
+ if (hsmartcard->hdmarx->XferAbortCallback != NULL)
+ {
+ return;
+ }
+ }
+
+ /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
+ hsmartcard->TxXferCount = 0U;
+ hsmartcard->RxXferCount = 0U;
+
+ /* Reset errorCode */
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
+ SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF |
+ SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
+
+ /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
+ hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort complete callback */
+ hsmartcard->AbortCpltCallback(hsmartcard);
+#else
+ /* Call legacy weak Abort complete callback */
+ HAL_SMARTCARD_AbortCpltCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
+}
+
+
+/**
+ * @brief DMA SMARTCARD Rx communication abort callback, when initiated by user
+ * (To be called at end of DMA Rx Abort procedure following user abort request).
+ * @note When this callback is executed, User Abort complete call back is called only if no
+ * Abort still ongoing for Tx DMA Handle.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void SMARTCARD_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent);
+
+ hsmartcard->hdmarx->XferAbortCallback = NULL;
+
+ /* Check if an Abort process is still ongoing */
+ if (hsmartcard->hdmatx != NULL)
+ {
+ if (hsmartcard->hdmatx->XferAbortCallback != NULL)
+ {
+ return;
+ }
+ }
+
+ /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
+ hsmartcard->TxXferCount = 0U;
+ hsmartcard->RxXferCount = 0U;
+
+ /* Reset errorCode */
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
+ SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF |
+ SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
+
+ /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
+ hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort complete callback */
+ hsmartcard->AbortCpltCallback(hsmartcard);
+#else
+ /* Call legacy weak Abort complete callback */
+ HAL_SMARTCARD_AbortCpltCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
+}
+
+
+/**
+ * @brief DMA SMARTCARD Tx communication abort callback, when initiated by user by a call to
+ * HAL_SMARTCARD_AbortTransmit_IT API (Abort only Tx transfer)
+ * (This callback is executed at end of DMA Tx Abort procedure following user abort request,
+ * and leads to user Tx Abort Complete callback execution).
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void SMARTCARD_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent);
+
+ hsmartcard->TxXferCount = 0U;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_FEF);
+
+ /* Restore hsmartcard->gState to Ready */
+ hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Transmit Complete Callback */
+ hsmartcard->AbortTransmitCpltCallback(hsmartcard);
+#else
+ /* Call legacy weak Abort Transmit Complete Callback */
+ HAL_SMARTCARD_AbortTransmitCpltCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
+}
+
+/**
+ * @brief DMA SMARTCARD Rx communication abort callback, when initiated by user by a call to
+ * HAL_SMARTCARD_AbortReceive_IT API (Abort only Rx transfer)
+ * (This callback is executed at end of DMA Rx Abort procedure following user abort request,
+ * and leads to user Rx Abort Complete callback execution).
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void SMARTCARD_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent);
+
+ hsmartcard->RxXferCount = 0U;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
+ SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF |
+ SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
+
+ /* Restore hsmartcard->RxState to Ready */
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Receive Complete Callback */
+ hsmartcard->AbortReceiveCpltCallback(hsmartcard);
+#else
+ /* Call legacy weak Abort Receive Complete Callback */
+ HAL_SMARTCARD_AbortReceiveCpltCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
+}
+
+/**
+ * @brief Send an amount of data in non-blocking mode.
+ * @note Function called under interruption only, once
+ * interruptions have been enabled by HAL_SMARTCARD_Transmit_IT()
+ * and when the FIFO mode is disabled.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval None
+ */
+static void SMARTCARD_TxISR(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Check that a Tx process is ongoing */
+ if (hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX)
+ {
+ if (hsmartcard->TxXferCount == 0U)
+ {
+ /* Disable the SMARTCARD Transmit Data Register Empty Interrupt */
+ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
+
+ /* Enable the SMARTCARD Transmit Complete Interrupt */
+ __HAL_SMARTCARD_ENABLE_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication);
+ }
+ else
+ {
+ hsmartcard->Instance->TDR = (uint8_t)(*hsmartcard->pTxBuffPtr & 0xFFU);
+ hsmartcard->pTxBuffPtr++;
+ hsmartcard->TxXferCount--;
+ }
+ }
+}
+
+/**
+ * @brief Send an amount of data in non-blocking mode.
+ * @note Function called under interruption only, once
+ * interruptions have been enabled by HAL_SMARTCARD_Transmit_IT()
+ * and when the FIFO mode is enabled.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval None
+ */
+static void SMARTCARD_TxISR_FIFOEN(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ uint16_t nb_tx_data;
+
+ /* Check that a Tx process is ongoing */
+ if (hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX)
+ {
+ for (nb_tx_data = hsmartcard->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--)
+ {
+ if (hsmartcard->TxXferCount == 0U)
+ {
+ /* Disable the SMARTCARD Transmit Data Register Empty Interrupt */
+ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
+
+ /* Enable the SMARTCARD Transmit Complete Interrupt */
+ __HAL_SMARTCARD_ENABLE_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication);
+ }
+ else if (READ_BIT(hsmartcard->Instance->ISR, USART_ISR_TXE_TXFNF) != 0U)
+ {
+ hsmartcard->Instance->TDR = (uint8_t)(*hsmartcard->pTxBuffPtr & 0xFFU);
+ hsmartcard->pTxBuffPtr++;
+ hsmartcard->TxXferCount--;
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+ }
+ }
+}
+
+/**
+ * @brief Wrap up transmission in non-blocking mode.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval None
+ */
+static void SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Disable the SMARTCARD Transmit Complete Interrupt */
+ __HAL_SMARTCARD_DISABLE_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication);
+
+ /* Check if a receive process is ongoing or not. If not disable ERR IT */
+ if (hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
+ {
+ /* Disable the SMARTCARD Error Interrupt: (Frame error) */
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+ }
+
+ /* Disable the Peripheral first to update mode */
+ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+ if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX)
+ && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
+ {
+ /* In case of TX only mode, if NACK is enabled, receiver block has been enabled
+ for Transmit phase. Disable this receiver block. */
+ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
+ }
+ if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX_RX)
+ || (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
+ {
+ /* Perform a TX FIFO Flush at end of Tx phase, as all sent bytes are appearing in Rx Data register */
+ __HAL_SMARTCARD_FLUSH_DRREGISTER(hsmartcard);
+ }
+ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+
+ /* Tx process is ended, restore hsmartcard->gState to Ready */
+ hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+
+ /* Clear TxISR function pointer */
+ hsmartcard->TxISR = NULL;
+
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered Tx complete callback */
+ hsmartcard->TxCpltCallback(hsmartcard);
+#else
+ /* Call legacy weak Tx complete callback */
+ HAL_SMARTCARD_TxCpltCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
+}
+
+/**
+ * @brief Receive an amount of data in non-blocking mode.
+ * @note Function called under interruption only, once
+ * interruptions have been enabled by HAL_SMARTCARD_Receive_IT()
+ * and when the FIFO mode is disabled.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval None
+ */
+static void SMARTCARD_RxISR(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Check that a Rx process is ongoing */
+ if (hsmartcard->RxState == HAL_SMARTCARD_STATE_BUSY_RX)
+ {
+ *hsmartcard->pRxBuffPtr = (uint8_t)(hsmartcard->Instance->RDR & (uint8_t)0xFF);
+ hsmartcard->pRxBuffPtr++;
+
+ hsmartcard->RxXferCount--;
+ if (hsmartcard->RxXferCount == 0U)
+ {
+ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
+
+ /* Check if a transmit process is ongoing or not. If not disable ERR IT */
+ if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
+ {
+ /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+ }
+
+ /* Disable the SMARTCARD Parity Error Interrupt */
+ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE);
+
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+ /* Clear RxISR function pointer */
+ hsmartcard->RxISR = NULL;
+
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered Rx complete callback */
+ hsmartcard->RxCpltCallback(hsmartcard);
+#else
+ /* Call legacy weak Rx complete callback */
+ HAL_SMARTCARD_RxCpltCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
+ }
+ }
+ else
+ {
+ /* Clear RXNE interrupt flag */
+ __HAL_SMARTCARD_SEND_REQ(hsmartcard, SMARTCARD_RXDATA_FLUSH_REQUEST);
+ }
+}
+
+/**
+ * @brief Receive an amount of data in non-blocking mode.
+ * @note Function called under interruption only, once
+ * interruptions have been enabled by HAL_SMARTCARD_Receive_IT()
+ * and when the FIFO mode is enabled.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval None
+ */
+static void SMARTCARD_RxISR_FIFOEN(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ uint16_t nb_rx_data;
+ uint16_t rxdatacount;
+
+ /* Check that a Rx process is ongoing */
+ if (hsmartcard->RxState == HAL_SMARTCARD_STATE_BUSY_RX)
+ {
+ for (nb_rx_data = hsmartcard->NbRxDataToProcess ; nb_rx_data > 0U ; nb_rx_data--)
+ {
+ *hsmartcard->pRxBuffPtr = (uint8_t)(hsmartcard->Instance->RDR & (uint8_t)0xFF);
+ hsmartcard->pRxBuffPtr++;
+
+ hsmartcard->RxXferCount--;
+ if (hsmartcard->RxXferCount == 0U)
+ {
+ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
+
+ /* Check if a transmit process is ongoing or not. If not disable ERR IT */
+ if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
+ {
+ /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+ }
+
+ /* Disable the SMARTCARD Parity Error Interrupt */
+ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE);
+
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+ /* Clear RxISR function pointer */
+ hsmartcard->RxISR = NULL;
+
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered Rx complete callback */
+ hsmartcard->RxCpltCallback(hsmartcard);
+#else
+ /* Call legacy weak Rx complete callback */
+ HAL_SMARTCARD_RxCpltCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
+ }
+ }
+
+ /* When remaining number of bytes to receive is less than the RX FIFO
+ threshold, next incoming frames are processed as if FIFO mode was
+ disabled (i.e. one interrupt per received frame).
+ */
+ rxdatacount = hsmartcard->RxXferCount;
+ if (((rxdatacount != 0U)) && (rxdatacount < hsmartcard->NbRxDataToProcess))
+ {
+ /* Disable the UART RXFT interrupt*/
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_RXFTIE);
+
+ /* Update the RxISR function pointer */
+ hsmartcard->RxISR = SMARTCARD_RxISR;
+
+ /* Enable the UART Data Register Not Empty interrupt */
+ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
+ }
+ }
+ else
+ {
+ /* Clear RXNE interrupt flag */
+ __HAL_SMARTCARD_SEND_REQ(hsmartcard, SMARTCARD_RXDATA_FLUSH_REQUEST);
+ }
+}
+
+/**
+ * @}
+ */
+
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_smartcard_ex.c b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_smartcard_ex.c
new file mode 100644
index 0000000000..6fe950f7fd
--- /dev/null
+++ b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_smartcard_ex.c
@@ -0,0 +1,494 @@
+/**
+ ******************************************************************************
+ * @file stm32c0xx_hal_smartcard_ex.c
+ * @author MCD Application Team
+ * @brief SMARTCARD HAL module driver.
+ * This file provides extended firmware functions to manage the following
+ * functionalities of the SmartCard.
+ * + Initialization and de-initialization functions
+ * + Peripheral Control functions
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2022 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ =============================================================================
+ ##### SMARTCARD peripheral extended features #####
+ =============================================================================
+ [..]
+ The Extended SMARTCARD HAL driver can be used as follows:
+
+ (#) After having configured the SMARTCARD basic features with HAL_SMARTCARD_Init(),
+ then program SMARTCARD advanced features if required (TX/RX pins swap, TimeOut,
+ auto-retry counter,...) in the hsmartcard AdvancedInit structure.
+
+ (#) FIFO mode enabling/disabling and RX/TX FIFO threshold programming.
+
+ -@- When SMARTCARD operates in FIFO mode, FIFO mode must be enabled prior
+ starting RX/TX transfers. Also RX/TX FIFO thresholds must be
+ configured prior starting RX/TX transfers.
+
+ @endverbatim
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32c0xx_hal.h"
+
+/** @addtogroup STM32C0xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup SMARTCARDEx SMARTCARDEx
+ * @brief SMARTCARD Extended HAL module driver
+ * @{
+ */
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup SMARTCARDEx_Private_Constants SMARTCARD Extended Private Constants
+ * @{
+ */
+/* UART RX FIFO depth */
+#define RX_FIFO_DEPTH 8U
+
+/* UART TX FIFO depth */
+#define TX_FIFO_DEPTH 8U
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static void SMARTCARDEx_SetNbDataToProcess(SMARTCARD_HandleTypeDef *hsmartcard);
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup SMARTCARDEx_Exported_Functions SMARTCARD Extended Exported Functions
+ * @{
+ */
+
+/** @defgroup SMARTCARDEx_Exported_Functions_Group1 Extended Peripheral Control functions
+ * @brief Extended control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to initialize the SMARTCARD.
+ (+) HAL_SMARTCARDEx_BlockLength_Config() API allows to configure the Block Length on the fly
+ (+) HAL_SMARTCARDEx_TimeOut_Config() API allows to configure the receiver timeout value on the fly
+ (+) HAL_SMARTCARDEx_EnableReceiverTimeOut() API enables the receiver timeout feature
+ (+) HAL_SMARTCARDEx_DisableReceiverTimeOut() API disables the receiver timeout feature
+
+@endverbatim
+ * @{
+ */
+
+/** @brief Update on the fly the SMARTCARD block length in RTOR register.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @param BlockLength SMARTCARD block length (8-bit long at most)
+ * @retval None
+ */
+void HAL_SMARTCARDEx_BlockLength_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t BlockLength)
+{
+ MODIFY_REG(hsmartcard->Instance->RTOR, USART_RTOR_BLEN, ((uint32_t)BlockLength << USART_RTOR_BLEN_Pos));
+}
+
+/** @brief Update on the fly the receiver timeout value in RTOR register.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @param TimeOutValue receiver timeout value in number of baud blocks. The timeout
+ * value must be less or equal to 0x0FFFFFFFF.
+ * @retval None
+ */
+void HAL_SMARTCARDEx_TimeOut_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t TimeOutValue)
+{
+ assert_param(IS_SMARTCARD_TIMEOUT_VALUE(hsmartcard->Init.TimeOutValue));
+ MODIFY_REG(hsmartcard->Instance->RTOR, USART_RTOR_RTO, TimeOutValue);
+}
+
+/** @brief Enable the SMARTCARD receiver timeout feature.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hsmartcard);
+
+ hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
+
+ /* Set the USART RTOEN bit */
+ SET_BIT(hsmartcard->Instance->CR2, USART_CR2_RTOEN);
+
+ hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmartcard);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/** @brief Disable the SMARTCARD receiver timeout feature.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hsmartcard);
+
+ hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
+
+ /* Clear the USART RTOEN bit */
+ CLEAR_BIT(hsmartcard->Instance->CR2, USART_CR2_RTOEN);
+
+ hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmartcard);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARDEx_Exported_Functions_Group2 Extended Peripheral IO operation functions
+ * @brief SMARTCARD Transmit and Receive functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of FIFO mode related callback functions.
+
+ (#) TX/RX Fifos Callbacks:
+ (++) HAL_SMARTCARDEx_RxFifoFullCallback()
+ (++) HAL_SMARTCARDEx_TxFifoEmptyCallback()
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief SMARTCARD RX Fifo full callback.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval None
+ */
+__weak void HAL_SMARTCARDEx_RxFifoFullCallback(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsmartcard);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMARTCARDEx_RxFifoFullCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief SMARTCARD TX Fifo empty callback.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval None
+ */
+__weak void HAL_SMARTCARDEx_TxFifoEmptyCallback(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsmartcard);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMARTCARDEx_TxFifoEmptyCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARDEx_Exported_Functions_Group3 Extended Peripheral FIFO Control functions
+ * @brief SMARTCARD control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral FIFO Control functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control the SMARTCARD
+ FIFO feature.
+ (+) HAL_SMARTCARDEx_EnableFifoMode() API enables the FIFO mode
+ (+) HAL_SMARTCARDEx_DisableFifoMode() API disables the FIFO mode
+ (+) HAL_SMARTCARDEx_SetTxFifoThreshold() API sets the TX FIFO threshold
+ (+) HAL_SMARTCARDEx_SetRxFifoThreshold() API sets the RX FIFO threshold
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enable the FIFO mode.
+ * @param hsmartcard SMARTCARD handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARDEx_EnableFifoMode(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ uint32_t tmpcr1;
+
+ /* Check parameters */
+ assert_param(IS_UART_FIFO_INSTANCE(hsmartcard->Instance));
+
+ /* Process Locked */
+ __HAL_LOCK(hsmartcard);
+
+ hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
+
+ /* Save actual SMARTCARD configuration */
+ tmpcr1 = READ_REG(hsmartcard->Instance->CR1);
+
+ /* Disable SMARTCARD */
+ __HAL_SMARTCARD_DISABLE(hsmartcard);
+
+ /* Enable FIFO mode */
+ SET_BIT(tmpcr1, USART_CR1_FIFOEN);
+ hsmartcard->FifoMode = SMARTCARD_FIFOMODE_ENABLE;
+
+ /* Restore SMARTCARD configuration */
+ WRITE_REG(hsmartcard->Instance->CR1, tmpcr1);
+
+ /* Determine the number of data to process during RX/TX ISR execution */
+ SMARTCARDEx_SetNbDataToProcess(hsmartcard);
+
+ hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmartcard);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disable the FIFO mode.
+ * @param hsmartcard SMARTCARD handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARDEx_DisableFifoMode(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ uint32_t tmpcr1;
+
+ /* Check parameters */
+ assert_param(IS_UART_FIFO_INSTANCE(hsmartcard->Instance));
+
+ /* Process Locked */
+ __HAL_LOCK(hsmartcard);
+
+ hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
+
+ /* Save actual SMARTCARD configuration */
+ tmpcr1 = READ_REG(hsmartcard->Instance->CR1);
+
+ /* Disable SMARTCARD */
+ __HAL_SMARTCARD_DISABLE(hsmartcard);
+
+ /* Enable FIFO mode */
+ CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN);
+ hsmartcard->FifoMode = SMARTCARD_FIFOMODE_DISABLE;
+
+ /* Restore SMARTCARD configuration */
+ WRITE_REG(hsmartcard->Instance->CR1, tmpcr1);
+
+ hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmartcard);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Set the TXFIFO threshold.
+ * @param hsmartcard SMARTCARD handle.
+ * @param Threshold TX FIFO threshold value
+ * This parameter can be one of the following values:
+ * @arg @ref SMARTCARD_TXFIFO_THRESHOLD_1_8
+ * @arg @ref SMARTCARD_TXFIFO_THRESHOLD_1_4
+ * @arg @ref SMARTCARD_TXFIFO_THRESHOLD_1_2
+ * @arg @ref SMARTCARD_TXFIFO_THRESHOLD_3_4
+ * @arg @ref SMARTCARD_TXFIFO_THRESHOLD_7_8
+ * @arg @ref SMARTCARD_TXFIFO_THRESHOLD_8_8
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARDEx_SetTxFifoThreshold(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Threshold)
+{
+ uint32_t tmpcr1;
+
+ /* Check parameters */
+ assert_param(IS_UART_FIFO_INSTANCE(hsmartcard->Instance));
+ assert_param(IS_SMARTCARD_TXFIFO_THRESHOLD(Threshold));
+
+ /* Process Locked */
+ __HAL_LOCK(hsmartcard);
+
+ hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
+
+ /* Save actual SMARTCARD configuration */
+ tmpcr1 = READ_REG(hsmartcard->Instance->CR1);
+
+ /* Disable SMARTCARD */
+ __HAL_SMARTCARD_DISABLE(hsmartcard);
+
+ /* Update TX threshold configuration */
+ MODIFY_REG(hsmartcard->Instance->CR3, USART_CR3_TXFTCFG, Threshold);
+
+ /* Determine the number of data to process during RX/TX ISR execution */
+ SMARTCARDEx_SetNbDataToProcess(hsmartcard);
+
+ /* Restore SMARTCARD configuration */
+ MODIFY_REG(hsmartcard->Instance->CR1, USART_CR1_UE, tmpcr1);
+
+ hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmartcard);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Set the RXFIFO threshold.
+ * @param hsmartcard SMARTCARD handle.
+ * @param Threshold RX FIFO threshold value
+ * This parameter can be one of the following values:
+ * @arg @ref SMARTCARD_RXFIFO_THRESHOLD_1_8
+ * @arg @ref SMARTCARD_RXFIFO_THRESHOLD_1_4
+ * @arg @ref SMARTCARD_RXFIFO_THRESHOLD_1_2
+ * @arg @ref SMARTCARD_RXFIFO_THRESHOLD_3_4
+ * @arg @ref SMARTCARD_RXFIFO_THRESHOLD_7_8
+ * @arg @ref SMARTCARD_RXFIFO_THRESHOLD_8_8
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARDEx_SetRxFifoThreshold(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Threshold)
+{
+ uint32_t tmpcr1;
+
+ /* Check parameters */
+ assert_param(IS_UART_FIFO_INSTANCE(hsmartcard->Instance));
+ assert_param(IS_SMARTCARD_RXFIFO_THRESHOLD(Threshold));
+
+ /* Process Locked */
+ __HAL_LOCK(hsmartcard);
+
+ hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
+
+ /* Save actual SMARTCARD configuration */
+ tmpcr1 = READ_REG(hsmartcard->Instance->CR1);
+
+ /* Disable SMARTCARD */
+ __HAL_SMARTCARD_DISABLE(hsmartcard);
+
+ /* Update RX threshold configuration */
+ MODIFY_REG(hsmartcard->Instance->CR3, USART_CR3_RXFTCFG, Threshold);
+
+ /* Determine the number of data to process during RX/TX ISR execution */
+ SMARTCARDEx_SetNbDataToProcess(hsmartcard);
+
+ /* Restore SMARTCARD configuration */
+ MODIFY_REG(hsmartcard->Instance->CR1, USART_CR1_UE, tmpcr1);
+
+ hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmartcard);
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARDEx_Private_Functions SMARTCARD Extended Private Functions
+ * @{
+ */
+
+/**
+ * @brief Calculate the number of data to process in RX/TX ISR.
+ * @note The RX FIFO depth and the TX FIFO depth is extracted from
+ * the USART configuration registers.
+ * @param hsmartcard SMARTCARD handle.
+ * @retval None
+ */
+static void SMARTCARDEx_SetNbDataToProcess(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ uint8_t rx_fifo_depth;
+ uint8_t tx_fifo_depth;
+ uint8_t rx_fifo_threshold;
+ uint8_t tx_fifo_threshold;
+ /* 2 0U/1U added for MISRAC2012-Rule-18.1_b and MISRAC2012-Rule-18.1_d */
+ static const uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U};
+ static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U};
+
+ if (hsmartcard->FifoMode == SMARTCARD_FIFOMODE_DISABLE)
+ {
+ hsmartcard->NbTxDataToProcess = 1U;
+ hsmartcard->NbRxDataToProcess = 1U;
+ }
+ else
+ {
+ rx_fifo_depth = RX_FIFO_DEPTH;
+ tx_fifo_depth = TX_FIFO_DEPTH;
+ rx_fifo_threshold = (uint8_t)(READ_BIT(hsmartcard->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);
+ tx_fifo_threshold = (uint8_t)(READ_BIT(hsmartcard->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);
+ hsmartcard->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / \
+ (uint16_t)denominator[tx_fifo_threshold];
+ hsmartcard->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / \
+ (uint16_t)denominator[rx_fifo_threshold];
+ }
+}
+
+/**
+ * @}
+ */
+
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_smbus.c b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_smbus.c
new file mode 100644
index 0000000000..f5cfd04fdf
--- /dev/null
+++ b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_smbus.c
@@ -0,0 +1,2779 @@
+/**
+ ******************************************************************************
+ * @file stm32c0xx_hal_smbus.c
+ * @author MCD Application Team
+ * @brief SMBUS HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the System Management Bus (SMBus) peripheral,
+ * based on I2C principles of operation :
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral State and Errors functions
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2022 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ The SMBUS HAL driver can be used as follows:
+
+ (#) Declare a SMBUS_HandleTypeDef handle structure, for example:
+ SMBUS_HandleTypeDef hsmbus;
+
+ (#)Initialize the SMBUS low level resources by implementing the HAL_SMBUS_MspInit() API:
+ (##) Enable the SMBUSx interface clock
+ (##) SMBUS pins configuration
+ (+++) Enable the clock for the SMBUS GPIOs
+ (+++) Configure SMBUS pins as alternate function open-drain
+ (##) NVIC configuration if you need to use interrupt process
+ (+++) Configure the SMBUSx interrupt priority
+ (+++) Enable the NVIC SMBUS IRQ Channel
+
+ (#) Configure the Communication Clock Timing, Bus Timeout, Own Address1, Master Addressing mode,
+ Dual Addressing mode, Own Address2, Own Address2 Mask, General call, Nostretch mode,
+ Peripheral mode and Packet Error Check mode in the hsmbus Init structure.
+
+ (#) Initialize the SMBUS registers by calling the HAL_SMBUS_Init() API:
+ (++) These API's configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
+ by calling the customized HAL_SMBUS_MspInit(&hsmbus) API.
+
+ (#) To check if target device is ready for communication, use the function HAL_SMBUS_IsDeviceReady()
+
+ (#) For SMBUS IO operations, only one mode of operations is available within this driver
+
+ *** Interrupt mode IO operation ***
+ ===================================
+ [..]
+ (+) Transmit in master/host SMBUS mode an amount of data in non-blocking mode
+ using HAL_SMBUS_Master_Transmit_IT()
+ (++) At transmission end of transfer HAL_SMBUS_MasterTxCpltCallback() is executed and users can
+ add their own code by customization of function pointer HAL_SMBUS_MasterTxCpltCallback()
+ (+) Receive in master/host SMBUS mode an amount of data in non-blocking mode
+ using HAL_SMBUS_Master_Receive_IT()
+ (++) At reception end of transfer HAL_SMBUS_MasterRxCpltCallback() is executed and users can
+ add their own code by customization of function pointer HAL_SMBUS_MasterRxCpltCallback()
+ (+) Abort a master/host SMBUS process communication with Interrupt using HAL_SMBUS_Master_Abort_IT()
+ (++) The associated previous transfer callback is called at the end of abort process
+ (++) mean HAL_SMBUS_MasterTxCpltCallback() in case of previous state was master transmit
+ (++) mean HAL_SMBUS_MasterRxCpltCallback() in case of previous state was master receive
+ (+) Enable/disable the Address listen mode in slave/device or host/slave SMBUS mode
+ using HAL_SMBUS_EnableListen_IT() HAL_SMBUS_DisableListen_IT()
+ (++) When address slave/device SMBUS match, HAL_SMBUS_AddrCallback() is executed and users can
+ add their own code to check the Address Match Code and the transmission direction
+ request by master/host (Write/Read).
+ (++) At Listen mode end HAL_SMBUS_ListenCpltCallback() is executed and users can
+ add their own code by customization of function pointer HAL_SMBUS_ListenCpltCallback()
+ (+) Transmit in slave/device SMBUS mode an amount of data in non-blocking mode
+ using HAL_SMBUS_Slave_Transmit_IT()
+ (++) At transmission end of transfer HAL_SMBUS_SlaveTxCpltCallback() is executed and users can
+ add their own code by customization of function pointer HAL_SMBUS_SlaveTxCpltCallback()
+ (+) Receive in slave/device SMBUS mode an amount of data in non-blocking mode
+ using HAL_SMBUS_Slave_Receive_IT()
+ (++) At reception end of transfer HAL_SMBUS_SlaveRxCpltCallback() is executed and users can
+ add their own code by customization of function pointer HAL_SMBUS_SlaveRxCpltCallback()
+ (+) Enable/Disable the SMBUS alert mode using
+ HAL_SMBUS_EnableAlert_IT() or HAL_SMBUS_DisableAlert_IT()
+ (++) When SMBUS Alert is generated HAL_SMBUS_ErrorCallback() is executed and users can
+ add their own code by customization of function pointer HAL_SMBUS_ErrorCallback()
+ to check the Alert Error Code using function HAL_SMBUS_GetError()
+ (+) Get HAL state machine or error values using HAL_SMBUS_GetState() or HAL_SMBUS_GetError()
+ (+) In case of transfer Error, HAL_SMBUS_ErrorCallback() function is executed and users can
+ add their own code by customization of function pointer HAL_SMBUS_ErrorCallback()
+ to check the Error Code using function HAL_SMBUS_GetError()
+
+ *** SMBUS HAL driver macros list ***
+ ==================================
+ [..]
+ Below the list of most used macros in SMBUS HAL driver.
+
+ (+) __HAL_SMBUS_ENABLE: Enable the SMBUS peripheral
+ (+) __HAL_SMBUS_DISABLE: Disable the SMBUS peripheral
+ (+) __HAL_SMBUS_GET_FLAG: Check whether the specified SMBUS flag is set or not
+ (+) __HAL_SMBUS_CLEAR_FLAG: Clear the specified SMBUS pending flag
+ (+) __HAL_SMBUS_ENABLE_IT: Enable the specified SMBUS interrupt
+ (+) __HAL_SMBUS_DISABLE_IT: Disable the specified SMBUS interrupt
+
+ *** Callback registration ***
+ =============================================
+ [..]
+ The compilation flag USE_HAL_SMBUS_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+ Use Functions HAL_SMBUS_RegisterCallback() or HAL_SMBUS_RegisterAddrCallback()
+ to register an interrupt callback.
+ [..]
+ Function HAL_SMBUS_RegisterCallback() allows to register following callbacks:
+ (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
+ (+) MasterRxCpltCallback : callback for Master reception end of transfer.
+ (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer.
+ (+) SlaveRxCpltCallback : callback for Slave reception end of transfer.
+ (+) ListenCpltCallback : callback for end of listen mode.
+ (+) ErrorCallback : callback for error detection.
+ (+) MspInitCallback : callback for Msp Init.
+ (+) MspDeInitCallback : callback for Msp DeInit.
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+ [..]
+ For specific callback AddrCallback use dedicated register callbacks : HAL_SMBUS_RegisterAddrCallback.
+ [..]
+ Use function HAL_SMBUS_UnRegisterCallback to reset a callback to the default
+ weak function.
+ HAL_SMBUS_UnRegisterCallback takes as parameters the HAL peripheral handle,
+ and the Callback ID.
+ This function allows to reset following callbacks:
+ (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
+ (+) MasterRxCpltCallback : callback for Master reception end of transfer.
+ (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer.
+ (+) SlaveRxCpltCallback : callback for Slave reception end of transfer.
+ (+) ListenCpltCallback : callback for end of listen mode.
+ (+) ErrorCallback : callback for error detection.
+ (+) MspInitCallback : callback for Msp Init.
+ (+) MspDeInitCallback : callback for Msp DeInit.
+ [..]
+ For callback AddrCallback use dedicated register callbacks : HAL_SMBUS_UnRegisterAddrCallback.
+ [..]
+ By default, after the HAL_SMBUS_Init() and when the state is HAL_I2C_STATE_RESET
+ all callbacks are set to the corresponding weak functions:
+ examples HAL_SMBUS_MasterTxCpltCallback(), HAL_SMBUS_MasterRxCpltCallback().
+ Exception done for MspInit and MspDeInit functions that are
+ reset to the legacy weak functions in the HAL_SMBUS_Init()/ HAL_SMBUS_DeInit() only when
+ these callbacks are null (not registered beforehand).
+ If MspInit or MspDeInit are not null, the HAL_SMBUS_Init()/ HAL_SMBUS_DeInit()
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
+ [..]
+ Callbacks can be registered/unregistered in HAL_I2C_STATE_READY state only.
+ Exception done MspInit/MspDeInit functions that can be registered/unregistered
+ in HAL_I2C_STATE_READY or HAL_I2C_STATE_RESET state,
+ thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+ Then, the user first registers the MspInit/MspDeInit user callbacks
+ using HAL_SMBUS_RegisterCallback() before calling HAL_SMBUS_DeInit()
+ or HAL_SMBUS_Init() function.
+ [..]
+ When the compilation flag USE_HAL_SMBUS_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registration feature is not available and all callbacks
+ are set to the corresponding weak functions.
+
+ [..]
+ (@) You can refer to the SMBUS HAL driver header file for more useful macros
+
+ @endverbatim
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32c0xx_hal.h"
+
+/** @addtogroup STM32C0xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup SMBUS SMBUS
+ * @brief SMBUS HAL module driver
+ * @{
+ */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup SMBUS_Private_Define SMBUS Private Constants
+ * @{
+ */
+#define TIMING_CLEAR_MASK (0xF0FFFFFFUL) /*!< SMBUS TIMING clear register Mask */
+#define HAL_TIMEOUT_ADDR (10000U) /*!< 10 s */
+#define HAL_TIMEOUT_BUSY (25U) /*!< 25 ms */
+#define HAL_TIMEOUT_DIR (25U) /*!< 25 ms */
+#define HAL_TIMEOUT_RXNE (25U) /*!< 25 ms */
+#define HAL_TIMEOUT_STOPF (25U) /*!< 25 ms */
+#define HAL_TIMEOUT_TC (25U) /*!< 25 ms */
+#define HAL_TIMEOUT_TCR (25U) /*!< 25 ms */
+#define HAL_TIMEOUT_TXIS (25U) /*!< 25 ms */
+#define MAX_NBYTE_SIZE 255U
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup SMBUS_Private_Functions SMBUS Private Functions
+ * @{
+ */
+/* Private functions to handle flags during polling transfer */
+static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag,
+ FlagStatus Status, uint32_t Timeout);
+
+/* Private functions for SMBUS transfer IRQ handler */
+static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags);
+static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags);
+static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus);
+
+/* Private functions to centralize the enable/disable of Interrupts */
+static void SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest);
+static void SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest);
+
+/* Private function to flush TXDR register */
+static void SMBUS_Flush_TXDR(SMBUS_HandleTypeDef *hsmbus);
+
+/* Private function to handle start, restart or stop a transfer */
+static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size,
+ uint32_t Mode, uint32_t Request);
+
+/* Private function to Convert Specific options */
+static void SMBUS_ConvertOtherXferOptions(SMBUS_HandleTypeDef *hsmbus);
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup SMBUS_Exported_Functions SMBUS Exported Functions
+ * @{
+ */
+
+/** @defgroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..] This subsection provides a set of functions allowing to initialize and
+ deinitialize the SMBUSx peripheral:
+
+ (+) User must Implement HAL_SMBUS_MspInit() function in which he configures
+ all related peripherals resources (CLOCK, GPIO, IT and NVIC ).
+
+ (+) Call the function HAL_SMBUS_Init() to configure the selected device with
+ the selected configuration:
+ (++) Clock Timing
+ (++) Bus Timeout
+ (++) Analog Filer mode
+ (++) Own Address 1
+ (++) Addressing mode (Master, Slave)
+ (++) Dual Addressing mode
+ (++) Own Address 2
+ (++) Own Address 2 Mask
+ (++) General call mode
+ (++) Nostretch mode
+ (++) Packet Error Check mode
+ (++) Peripheral mode
+
+
+ (+) Call the function HAL_SMBUS_DeInit() to restore the default configuration
+ of the selected SMBUSx peripheral.
+
+ (+) Enable/Disable Analog/Digital filters with HAL_SMBUS_ConfigAnalogFilter() and
+ HAL_SMBUS_ConfigDigitalFilter().
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initialize the SMBUS according to the specified parameters
+ * in the SMBUS_InitTypeDef and initialize the associated handle.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus)
+{
+ /* Check the SMBUS handle allocation */
+ if (hsmbus == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
+ assert_param(IS_SMBUS_ANALOG_FILTER(hsmbus->Init.AnalogFilter));
+ assert_param(IS_SMBUS_OWN_ADDRESS1(hsmbus->Init.OwnAddress1));
+ assert_param(IS_SMBUS_ADDRESSING_MODE(hsmbus->Init.AddressingMode));
+ assert_param(IS_SMBUS_DUAL_ADDRESS(hsmbus->Init.DualAddressMode));
+ assert_param(IS_SMBUS_OWN_ADDRESS2(hsmbus->Init.OwnAddress2));
+ assert_param(IS_SMBUS_OWN_ADDRESS2_MASK(hsmbus->Init.OwnAddress2Masks));
+ assert_param(IS_SMBUS_GENERAL_CALL(hsmbus->Init.GeneralCallMode));
+ assert_param(IS_SMBUS_NO_STRETCH(hsmbus->Init.NoStretchMode));
+ assert_param(IS_SMBUS_PEC(hsmbus->Init.PacketErrorCheckMode));
+ assert_param(IS_SMBUS_PERIPHERAL_MODE(hsmbus->Init.PeripheralMode));
+
+ if (hsmbus->State == HAL_SMBUS_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hsmbus->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+ hsmbus->MasterTxCpltCallback = HAL_SMBUS_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */
+ hsmbus->MasterRxCpltCallback = HAL_SMBUS_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */
+ hsmbus->SlaveTxCpltCallback = HAL_SMBUS_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */
+ hsmbus->SlaveRxCpltCallback = HAL_SMBUS_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */
+ hsmbus->ListenCpltCallback = HAL_SMBUS_ListenCpltCallback; /* Legacy weak ListenCpltCallback */
+ hsmbus->ErrorCallback = HAL_SMBUS_ErrorCallback; /* Legacy weak ErrorCallback */
+ hsmbus->AddrCallback = HAL_SMBUS_AddrCallback; /* Legacy weak AddrCallback */
+
+ if (hsmbus->MspInitCallback == NULL)
+ {
+ hsmbus->MspInitCallback = HAL_SMBUS_MspInit; /* Legacy weak MspInit */
+ }
+
+ /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
+ hsmbus->MspInitCallback(hsmbus);
+#else
+ /* Init the low level hardware : GPIO, CLOCK, NVIC */
+ HAL_SMBUS_MspInit(hsmbus);
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
+ }
+
+ hsmbus->State = HAL_SMBUS_STATE_BUSY;
+
+ /* Disable the selected SMBUS peripheral */
+ __HAL_SMBUS_DISABLE(hsmbus);
+
+ /*---------------------------- SMBUSx TIMINGR Configuration ------------------------*/
+ /* Configure SMBUSx: Frequency range */
+ hsmbus->Instance->TIMINGR = hsmbus->Init.Timing & TIMING_CLEAR_MASK;
+
+ /*---------------------------- SMBUSx TIMEOUTR Configuration ------------------------*/
+ /* Configure SMBUSx: Bus Timeout */
+ hsmbus->Instance->TIMEOUTR &= ~I2C_TIMEOUTR_TIMOUTEN;
+ hsmbus->Instance->TIMEOUTR &= ~I2C_TIMEOUTR_TEXTEN;
+ hsmbus->Instance->TIMEOUTR = hsmbus->Init.SMBusTimeout;
+
+ /*---------------------------- SMBUSx OAR1 Configuration -----------------------*/
+ /* Configure SMBUSx: Own Address1 and ack own address1 mode */
+ hsmbus->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
+
+ if (hsmbus->Init.OwnAddress1 != 0UL)
+ {
+ if (hsmbus->Init.AddressingMode == SMBUS_ADDRESSINGMODE_7BIT)
+ {
+ hsmbus->Instance->OAR1 = (I2C_OAR1_OA1EN | hsmbus->Init.OwnAddress1);
+ }
+ }
+
+ /*---------------------------- SMBUSx CR2 Configuration ------------------------*/
+ /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process) */
+ /* AUTOEND and NACK bit will be manage during Transfer process */
+ hsmbus->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
+
+ /*---------------------------- SMBUSx OAR2 Configuration -----------------------*/
+ /* Configure SMBUSx: Dual mode and Own Address2 */
+ hsmbus->Instance->OAR2 = (hsmbus->Init.DualAddressMode | hsmbus->Init.OwnAddress2 | \
+ (hsmbus->Init.OwnAddress2Masks << 8U));
+
+ /*---------------------------- SMBUSx CR1 Configuration ------------------------*/
+ /* Configure SMBUSx: Generalcall and NoStretch mode */
+ hsmbus->Instance->CR1 = (hsmbus->Init.GeneralCallMode | hsmbus->Init.NoStretchMode | \
+ hsmbus->Init.PacketErrorCheckMode | hsmbus->Init.PeripheralMode | \
+ hsmbus->Init.AnalogFilter);
+
+ /* Enable Slave Byte Control only in case of Packet Error Check is enabled
+ and SMBUS Peripheral is set in Slave mode */
+ if ((hsmbus->Init.PacketErrorCheckMode == SMBUS_PEC_ENABLE) && \
+ ((hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || \
+ (hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP)))
+ {
+ hsmbus->Instance->CR1 |= I2C_CR1_SBC;
+ }
+
+ /* Enable the selected SMBUS peripheral */
+ __HAL_SMBUS_ENABLE(hsmbus);
+
+ hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
+ hsmbus->PreviousState = HAL_SMBUS_STATE_READY;
+ hsmbus->State = HAL_SMBUS_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitialize the SMBUS peripheral.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus)
+{
+ /* Check the SMBUS handle allocation */
+ if (hsmbus == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
+
+ hsmbus->State = HAL_SMBUS_STATE_BUSY;
+
+ /* Disable the SMBUS Peripheral Clock */
+ __HAL_SMBUS_DISABLE(hsmbus);
+
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+ if (hsmbus->MspDeInitCallback == NULL)
+ {
+ hsmbus->MspDeInitCallback = HAL_SMBUS_MspDeInit; /* Legacy weak MspDeInit */
+ }
+
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+ hsmbus->MspDeInitCallback(hsmbus);
+#else
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+ HAL_SMBUS_MspDeInit(hsmbus);
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
+
+ hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
+ hsmbus->PreviousState = HAL_SMBUS_STATE_RESET;
+ hsmbus->State = HAL_SMBUS_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hsmbus);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initialize the SMBUS MSP.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @retval None
+ */
+__weak void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsmbus);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMBUS_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitialize the SMBUS MSP.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @retval None
+ */
+__weak void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsmbus);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMBUS_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Configure Analog noise filter.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @param AnalogFilter This parameter can be one of the following values:
+ * @arg @ref SMBUS_ANALOGFILTER_ENABLE
+ * @arg @ref SMBUS_ANALOGFILTER_DISABLE
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMBUS_ConfigAnalogFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t AnalogFilter)
+{
+ /* Check the parameters */
+ assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
+ assert_param(IS_SMBUS_ANALOG_FILTER(AnalogFilter));
+
+ if (hsmbus->State == HAL_SMBUS_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hsmbus);
+
+ hsmbus->State = HAL_SMBUS_STATE_BUSY;
+
+ /* Disable the selected SMBUS peripheral */
+ __HAL_SMBUS_DISABLE(hsmbus);
+
+ /* Reset ANOFF bit */
+ hsmbus->Instance->CR1 &= ~(I2C_CR1_ANFOFF);
+
+ /* Set analog filter bit*/
+ hsmbus->Instance->CR1 |= AnalogFilter;
+
+ __HAL_SMBUS_ENABLE(hsmbus);
+
+ hsmbus->State = HAL_SMBUS_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Configure Digital noise filter.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t DigitalFilter)
+{
+ uint32_t tmpreg;
+
+ /* Check the parameters */
+ assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
+ assert_param(IS_SMBUS_DIGITAL_FILTER(DigitalFilter));
+
+ if (hsmbus->State == HAL_SMBUS_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hsmbus);
+
+ hsmbus->State = HAL_SMBUS_STATE_BUSY;
+
+ /* Disable the selected SMBUS peripheral */
+ __HAL_SMBUS_DISABLE(hsmbus);
+
+ /* Get the old register value */
+ tmpreg = hsmbus->Instance->CR1;
+
+ /* Reset I2C DNF bits [11:8] */
+ tmpreg &= ~(I2C_CR1_DNF);
+
+ /* Set I2Cx DNF coefficient */
+ tmpreg |= DigitalFilter << I2C_CR1_DNF_Pos;
+
+ /* Store the new register value */
+ hsmbus->Instance->CR1 = tmpreg;
+
+ __HAL_SMBUS_ENABLE(hsmbus);
+
+ hsmbus->State = HAL_SMBUS_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a User SMBUS Callback
+ * To be used instead of the weak predefined callback
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
+ * @arg @ref HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
+ * @arg @ref HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
+ * @arg @ref HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
+ * @arg @ref HAL_SMBUS_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
+ * @arg @ref HAL_SMBUS_ERROR_CB_ID Error callback ID
+ * @arg @ref HAL_SMBUS_MSPINIT_CB_ID MspInit callback ID
+ * @arg @ref HAL_SMBUS_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @param pCallback pointer to the Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus,
+ HAL_SMBUS_CallbackIDTypeDef CallbackID,
+ pSMBUS_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hsmbus);
+
+ if (HAL_SMBUS_STATE_READY == hsmbus->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID :
+ hsmbus->MasterTxCpltCallback = pCallback;
+ break;
+
+ case HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID :
+ hsmbus->MasterRxCpltCallback = pCallback;
+ break;
+
+ case HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID :
+ hsmbus->SlaveTxCpltCallback = pCallback;
+ break;
+
+ case HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID :
+ hsmbus->SlaveRxCpltCallback = pCallback;
+ break;
+
+ case HAL_SMBUS_LISTEN_COMPLETE_CB_ID :
+ hsmbus->ListenCpltCallback = pCallback;
+ break;
+
+ case HAL_SMBUS_ERROR_CB_ID :
+ hsmbus->ErrorCallback = pCallback;
+ break;
+
+ case HAL_SMBUS_MSPINIT_CB_ID :
+ hsmbus->MspInitCallback = pCallback;
+ break;
+
+ case HAL_SMBUS_MSPDEINIT_CB_ID :
+ hsmbus->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_SMBUS_STATE_RESET == hsmbus->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_SMBUS_MSPINIT_CB_ID :
+ hsmbus->MspInitCallback = pCallback;
+ break;
+
+ case HAL_SMBUS_MSPDEINIT_CB_ID :
+ hsmbus->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hsmbus);
+ return status;
+}
+
+/**
+ * @brief Unregister an SMBUS Callback
+ * SMBUS callback is redirected to the weak predefined callback
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @param CallbackID ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
+ * @arg @ref HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
+ * @arg @ref HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
+ * @arg @ref HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
+ * @arg @ref HAL_SMBUS_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
+ * @arg @ref HAL_SMBUS_ERROR_CB_ID Error callback ID
+ * @arg @ref HAL_SMBUS_MSPINIT_CB_ID MspInit callback ID
+ * @arg @ref HAL_SMBUS_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMBUS_UnRegisterCallback(SMBUS_HandleTypeDef *hsmbus,
+ HAL_SMBUS_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hsmbus);
+
+ if (HAL_SMBUS_STATE_READY == hsmbus->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID :
+ hsmbus->MasterTxCpltCallback = HAL_SMBUS_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */
+ break;
+
+ case HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID :
+ hsmbus->MasterRxCpltCallback = HAL_SMBUS_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */
+ break;
+
+ case HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID :
+ hsmbus->SlaveTxCpltCallback = HAL_SMBUS_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */
+ break;
+
+ case HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID :
+ hsmbus->SlaveRxCpltCallback = HAL_SMBUS_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */
+ break;
+
+ case HAL_SMBUS_LISTEN_COMPLETE_CB_ID :
+ hsmbus->ListenCpltCallback = HAL_SMBUS_ListenCpltCallback; /* Legacy weak ListenCpltCallback */
+ break;
+
+ case HAL_SMBUS_ERROR_CB_ID :
+ hsmbus->ErrorCallback = HAL_SMBUS_ErrorCallback; /* Legacy weak ErrorCallback */
+ break;
+
+ case HAL_SMBUS_MSPINIT_CB_ID :
+ hsmbus->MspInitCallback = HAL_SMBUS_MspInit; /* Legacy weak MspInit */
+ break;
+
+ case HAL_SMBUS_MSPDEINIT_CB_ID :
+ hsmbus->MspDeInitCallback = HAL_SMBUS_MspDeInit; /* Legacy weak MspDeInit */
+ break;
+
+ default :
+ /* Update the error code */
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_SMBUS_STATE_RESET == hsmbus->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_SMBUS_MSPINIT_CB_ID :
+ hsmbus->MspInitCallback = HAL_SMBUS_MspInit; /* Legacy weak MspInit */
+ break;
+
+ case HAL_SMBUS_MSPDEINIT_CB_ID :
+ hsmbus->MspDeInitCallback = HAL_SMBUS_MspDeInit; /* Legacy weak MspDeInit */
+ break;
+
+ default :
+ /* Update the error code */
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hsmbus);
+ return status;
+}
+
+/**
+ * @brief Register the Slave Address Match SMBUS Callback
+ * To be used instead of the weak HAL_SMBUS_AddrCallback() predefined callback
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @param pCallback pointer to the Address Match Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMBUS_RegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus,
+ pSMBUS_AddrCallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+ /* Process locked */
+ __HAL_LOCK(hsmbus);
+
+ if (HAL_SMBUS_STATE_READY == hsmbus->State)
+ {
+ hsmbus->AddrCallback = pCallback;
+ }
+ else
+ {
+ /* Update the error code */
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hsmbus);
+ return status;
+}
+
+/**
+ * @brief UnRegister the Slave Address Match SMBUS Callback
+ * Info Ready SMBUS Callback is redirected to the weak HAL_SMBUS_AddrCallback() predefined callback
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMBUS_UnRegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hsmbus);
+
+ if (HAL_SMBUS_STATE_READY == hsmbus->State)
+ {
+ hsmbus->AddrCallback = HAL_SMBUS_AddrCallback; /* Legacy weak AddrCallback */
+ }
+ else
+ {
+ /* Update the error code */
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hsmbus);
+ return status;
+}
+
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+/** @defgroup SMBUS_Exported_Functions_Group2 Input and Output operation functions
+ * @brief Data transfers functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the SMBUS data
+ transfers.
+
+ (#) Blocking mode function to check if device is ready for usage is :
+ (++) HAL_SMBUS_IsDeviceReady()
+
+ (#) There is only one mode of transfer:
+ (++) Non-Blocking mode : The communication is performed using Interrupts.
+ These functions return the status of the transfer startup.
+ The end of the data processing will be indicated through the
+ dedicated SMBUS IRQ when using Interrupt mode.
+
+ (#) Non-Blocking mode functions with Interrupt are :
+ (++) HAL_SMBUS_Master_Transmit_IT()
+ (++) HAL_SMBUS_Master_Receive_IT()
+ (++) HAL_SMBUS_Slave_Transmit_IT()
+ (++) HAL_SMBUS_Slave_Receive_IT()
+ (++) HAL_SMBUS_EnableListen_IT() or alias HAL_SMBUS_EnableListen_IT()
+ (++) HAL_SMBUS_DisableListen_IT()
+ (++) HAL_SMBUS_EnableAlert_IT()
+ (++) HAL_SMBUS_DisableAlert_IT()
+
+ (#) A set of Transfer Complete Callbacks are provided in non-Blocking mode:
+ (++) HAL_SMBUS_MasterTxCpltCallback()
+ (++) HAL_SMBUS_MasterRxCpltCallback()
+ (++) HAL_SMBUS_SlaveTxCpltCallback()
+ (++) HAL_SMBUS_SlaveRxCpltCallback()
+ (++) HAL_SMBUS_AddrCallback()
+ (++) HAL_SMBUS_ListenCpltCallback()
+ (++) HAL_SMBUS_ErrorCallback()
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Transmit in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @param DevAddress Target device address: The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress,
+ uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+{
+ uint32_t tmp;
+
+ /* Check the parameters */
+ assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+ if (hsmbus->State == HAL_SMBUS_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hsmbus);
+
+ hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_TX;
+ hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
+ /* Prepare transfer parameters */
+ hsmbus->pBuffPtr = pData;
+ hsmbus->XferCount = Size;
+ hsmbus->XferOptions = XferOptions;
+
+ /* In case of Quick command, remove autoend mode */
+ /* Manage the stop generation by software */
+ if (hsmbus->pBuffPtr == NULL)
+ {
+ hsmbus->XferOptions &= ~SMBUS_AUTOEND_MODE;
+ }
+
+ if (Size > MAX_NBYTE_SIZE)
+ {
+ hsmbus->XferSize = MAX_NBYTE_SIZE;
+ }
+ else
+ {
+ hsmbus->XferSize = Size;
+ }
+
+ /* Send Slave Address */
+ /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
+ if ((hsmbus->XferSize < hsmbus->XferCount) && (hsmbus->XferSize == MAX_NBYTE_SIZE))
+ {
+ SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize,
+ SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE),
+ SMBUS_GENERATE_START_WRITE);
+ }
+ else
+ {
+ /* If transfer direction not change, do not generate Restart Condition */
+ /* Mean Previous state is same as current state */
+
+ /* Store current volatile XferOptions, misra rule */
+ tmp = hsmbus->XferOptions;
+
+ if ((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX) && \
+ (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(tmp) == 0))
+ {
+ SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions,
+ SMBUS_NO_STARTSTOP);
+ }
+ /* Else transfer direction change, so generate Restart with new transfer direction */
+ else
+ {
+ /* Convert OTHER_xxx XferOptions if any */
+ SMBUS_ConvertOtherXferOptions(hsmbus);
+
+ /* Handle Transfer */
+ SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize,
+ hsmbus->XferOptions,
+ SMBUS_GENERATE_START_WRITE);
+ }
+
+ /* If PEC mode is enable, size to transmit manage by SW part should be Size-1 byte, corresponding to PEC byte */
+ /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
+ if (SMBUS_GET_PEC_MODE(hsmbus) != 0UL)
+ {
+ hsmbus->XferSize--;
+ hsmbus->XferCount--;
+ }
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ /* Note : The SMBUS interrupts must be enabled after unlocking current process
+ to avoid the risk of SMBUS interrupt handle execution before current
+ process unlock */
+ SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_TX);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @param DevAddress Target device address: The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData,
+ uint16_t Size, uint32_t XferOptions)
+{
+ uint32_t tmp;
+
+ /* Check the parameters */
+ assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+ if (hsmbus->State == HAL_SMBUS_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hsmbus);
+
+ hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_RX;
+ hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hsmbus->pBuffPtr = pData;
+ hsmbus->XferCount = Size;
+ hsmbus->XferOptions = XferOptions;
+
+ /* In case of Quick command, remove autoend mode */
+ /* Manage the stop generation by software */
+ if (hsmbus->pBuffPtr == NULL)
+ {
+ hsmbus->XferOptions &= ~SMBUS_AUTOEND_MODE;
+ }
+
+ if (Size > MAX_NBYTE_SIZE)
+ {
+ hsmbus->XferSize = MAX_NBYTE_SIZE;
+ }
+ else
+ {
+ hsmbus->XferSize = Size;
+ }
+
+ /* Send Slave Address */
+ /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
+ if ((hsmbus->XferSize < hsmbus->XferCount) && (hsmbus->XferSize == MAX_NBYTE_SIZE))
+ {
+ SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize,
+ SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE),
+ SMBUS_GENERATE_START_READ);
+ }
+ else
+ {
+ /* If transfer direction not change, do not generate Restart Condition */
+ /* Mean Previous state is same as current state */
+
+ /* Store current volatile XferOptions, Misra rule */
+ tmp = hsmbus->XferOptions;
+
+ if ((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX) && \
+ (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(tmp) == 0))
+ {
+ SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions,
+ SMBUS_NO_STARTSTOP);
+ }
+ /* Else transfer direction change, so generate Restart with new transfer direction */
+ else
+ {
+ /* Convert OTHER_xxx XferOptions if any */
+ SMBUS_ConvertOtherXferOptions(hsmbus);
+
+ /* Handle Transfer */
+ SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize,
+ hsmbus->XferOptions,
+ SMBUS_GENERATE_START_READ);
+ }
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ /* Note : The SMBUS interrupts must be enabled after unlocking current process
+ to avoid the risk of SMBUS interrupt handle execution before current
+ process unlock */
+ SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_RX);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Abort a master/host SMBUS process communication with Interrupt.
+ * @note This abort can be called only if state is ready
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @param DevAddress Target device address: The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress)
+{
+ if (hsmbus->State == HAL_SMBUS_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hsmbus);
+
+ /* Keep the same state as previous */
+ /* to perform as well the call of the corresponding end of transfer callback */
+ if (hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX)
+ {
+ hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_TX;
+ }
+ else if (hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX)
+ {
+ hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_RX;
+ }
+ else
+ {
+ /* Wrong usage of abort function */
+ /* This function should be used only in case of abort monitored by master device */
+ return HAL_ERROR;
+ }
+ hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
+
+ /* Set NBYTES to 1 to generate a dummy read on SMBUS peripheral */
+ /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */
+ SMBUS_TransferConfig(hsmbus, DevAddress, 1, SMBUS_AUTOEND_MODE, SMBUS_NO_STARTSTOP);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ /* Note : The SMBUS interrupts must be enabled after unlocking current process
+ to avoid the risk of SMBUS interrupt handle execution before current
+ process unlock */
+ if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
+ {
+ SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_TX);
+ }
+ else if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
+ {
+ SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_RX);
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Transmit in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size,
+ uint32_t XferOptions)
+{
+ /* Check the parameters */
+ assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+ if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN)
+ {
+ if ((pData == NULL) || (Size == 0UL))
+ {
+ hsmbus->ErrorCode = HAL_SMBUS_ERROR_INVALID_PARAM;
+ return HAL_ERROR;
+ }
+
+ /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
+ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR | SMBUS_IT_TX);
+
+ /* Process Locked */
+ __HAL_LOCK(hsmbus);
+
+ hsmbus->State = (HAL_SMBUS_STATE_SLAVE_BUSY_TX | HAL_SMBUS_STATE_LISTEN);
+ hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
+
+ /* Set SBC bit to manage Acknowledge at each bit */
+ hsmbus->Instance->CR1 |= I2C_CR1_SBC;
+
+ /* Enable Address Acknowledge */
+ hsmbus->Instance->CR2 &= ~I2C_CR2_NACK;
+
+ /* Prepare transfer parameters */
+ hsmbus->pBuffPtr = pData;
+ hsmbus->XferCount = Size;
+ hsmbus->XferOptions = XferOptions;
+
+ /* Convert OTHER_xxx XferOptions if any */
+ SMBUS_ConvertOtherXferOptions(hsmbus);
+
+ if (Size > MAX_NBYTE_SIZE)
+ {
+ hsmbus->XferSize = MAX_NBYTE_SIZE;
+ }
+ else
+ {
+ hsmbus->XferSize = Size;
+ }
+
+ /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
+ if ((hsmbus->XferSize < hsmbus->XferCount) && (hsmbus->XferSize == MAX_NBYTE_SIZE))
+ {
+ SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize,
+ SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE),
+ SMBUS_NO_STARTSTOP);
+ }
+ else
+ {
+ /* Set NBYTE to transmit */
+ SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions,
+ SMBUS_NO_STARTSTOP);
+
+ /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */
+ /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
+ if (SMBUS_GET_PEC_MODE(hsmbus) != 0UL)
+ {
+ hsmbus->XferSize--;
+ hsmbus->XferCount--;
+ }
+ }
+
+ /* Clear ADDR flag after prepare the transfer parameters */
+ /* This action will generate an acknowledge to the HOST */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ADDR);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ /* Note : The SMBUS interrupts must be enabled after unlocking current process
+ to avoid the risk of SMBUS interrupt handle execution before current
+ process unlock */
+ /* REnable ADDR interrupt */
+ SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_TX | SMBUS_IT_ADDR);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size,
+ uint32_t XferOptions)
+{
+ /* Check the parameters */
+ assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+ if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN)
+ {
+ if ((pData == NULL) || (Size == 0UL))
+ {
+ hsmbus->ErrorCode = HAL_SMBUS_ERROR_INVALID_PARAM;
+ return HAL_ERROR;
+ }
+
+ /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
+ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR | SMBUS_IT_RX);
+
+ /* Process Locked */
+ __HAL_LOCK(hsmbus);
+
+ hsmbus->State = (HAL_SMBUS_STATE_SLAVE_BUSY_RX | HAL_SMBUS_STATE_LISTEN);
+ hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
+
+ /* Set SBC bit to manage Acknowledge at each bit */
+ hsmbus->Instance->CR1 |= I2C_CR1_SBC;
+
+ /* Enable Address Acknowledge */
+ hsmbus->Instance->CR2 &= ~I2C_CR2_NACK;
+
+ /* Prepare transfer parameters */
+ hsmbus->pBuffPtr = pData;
+ hsmbus->XferSize = Size;
+ hsmbus->XferCount = Size;
+ hsmbus->XferOptions = XferOptions;
+
+ /* Convert OTHER_xxx XferOptions if any */
+ SMBUS_ConvertOtherXferOptions(hsmbus);
+
+ /* Set NBYTE to receive */
+ /* If XferSize equal "1", or XferSize equal "2" with PEC requested (mean 1 data byte + 1 PEC byte */
+ /* no need to set RELOAD bit mode, a ACK will be automatically generated in that case */
+ /* else need to set RELOAD bit mode to generate an automatic ACK at each byte Received */
+ /* This RELOAD bit will be reset for last BYTE to be receive in SMBUS_Slave_ISR */
+ if (((SMBUS_GET_PEC_MODE(hsmbus) != 0UL) && (hsmbus->XferSize == 2U)) || (hsmbus->XferSize == 1U))
+ {
+ SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions,
+ SMBUS_NO_STARTSTOP);
+ }
+ else
+ {
+ SMBUS_TransferConfig(hsmbus, 0, 1, hsmbus->XferOptions | SMBUS_RELOAD_MODE, SMBUS_NO_STARTSTOP);
+ }
+
+ /* Clear ADDR flag after prepare the transfer parameters */
+ /* This action will generate an acknowledge to the HOST */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ADDR);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ /* Note : The SMBUS interrupts must be enabled after unlocking current process
+ to avoid the risk of SMBUS interrupt handle execution before current
+ process unlock */
+ /* REnable ADDR interrupt */
+ SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_RX | SMBUS_IT_ADDR);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Enable the Address listen mode with Interrupt.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT(SMBUS_HandleTypeDef *hsmbus)
+{
+ hsmbus->State = HAL_SMBUS_STATE_LISTEN;
+
+ /* Enable the Address Match interrupt */
+ SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_ADDR);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disable the Address listen mode with Interrupt.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus)
+{
+ /* Disable Address listen mode only if a transfer is not ongoing */
+ if (hsmbus->State == HAL_SMBUS_STATE_LISTEN)
+ {
+ hsmbus->State = HAL_SMBUS_STATE_READY;
+
+ /* Disable the Address Match interrupt */
+ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Enable the SMBUS alert mode with Interrupt.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUSx peripheral.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus)
+{
+ /* Enable SMBus alert */
+ hsmbus->Instance->CR1 |= I2C_CR1_ALERTEN;
+
+ /* Clear ALERT flag */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ALERT);
+
+ /* Enable Alert Interrupt */
+ SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_ALERT);
+
+ return HAL_OK;
+}
+/**
+ * @brief Disable the SMBUS alert mode with Interrupt.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUSx peripheral.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus)
+{
+ /* Enable SMBus alert */
+ hsmbus->Instance->CR1 &= ~I2C_CR1_ALERTEN;
+
+ /* Disable Alert Interrupt */
+ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ALERT);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Check if target device is ready for communication.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @param DevAddress Target device address: The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @param Trials Number of trials
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials,
+ uint32_t Timeout)
+{
+ uint32_t tickstart;
+
+ __IO uint32_t SMBUS_Trials = 0UL;
+
+ FlagStatus tmp1;
+ FlagStatus tmp2;
+
+ if (hsmbus->State == HAL_SMBUS_STATE_READY)
+ {
+ if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_BUSY) != RESET)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hsmbus);
+
+ hsmbus->State = HAL_SMBUS_STATE_BUSY;
+ hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
+
+ do
+ {
+ /* Generate Start */
+ hsmbus->Instance->CR2 = SMBUS_GENERATE_START(hsmbus->Init.AddressingMode, DevAddress);
+
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+ /* Wait until STOPF flag is set or a NACK flag is set*/
+ tickstart = HAL_GetTick();
+
+ tmp1 = __HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF);
+ tmp2 = __HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF);
+
+ while ((tmp1 == RESET) && (tmp2 == RESET))
+ {
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL))
+ {
+ /* Device is ready */
+ hsmbus->State = HAL_SMBUS_STATE_READY;
+
+ /* Update SMBUS error code */
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_HALTIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+ return HAL_ERROR;
+ }
+ }
+
+ tmp1 = __HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF);
+ tmp2 = __HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF);
+ }
+
+ /* Check if the NACKF flag has not been set */
+ if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) == RESET)
+ {
+ /* Wait until STOPF flag is reset */
+ if (SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Clear STOP Flag */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
+
+ /* Device is ready */
+ hsmbus->State = HAL_SMBUS_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ return HAL_OK;
+ }
+ else
+ {
+ /* Wait until STOPF flag is reset */
+ if (SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Clear NACK Flag */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF);
+
+ /* Clear STOP Flag, auto generated with autoend*/
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
+ }
+
+ /* Check if the maximum allowed number of trials has been reached */
+ if (SMBUS_Trials == Trials)
+ {
+ /* Generate Stop */
+ hsmbus->Instance->CR2 |= I2C_CR2_STOP;
+
+ /* Wait until STOPF flag is reset */
+ if (SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Clear STOP Flag */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
+ }
+
+ /* Increment Trials */
+ SMBUS_Trials++;
+ } while (SMBUS_Trials < Trials);
+
+ hsmbus->State = HAL_SMBUS_STATE_READY;
+
+ /* Update SMBUS error code */
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_HALTIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+/**
+ * @}
+ */
+
+/** @defgroup SMBUS_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
+ * @{
+ */
+
+/**
+ * @brief Handle SMBUS event interrupt request.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @retval None
+ */
+void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus)
+{
+ /* Use a local variable to store the current ISR flags */
+ /* This action will avoid a wrong treatment due to ISR flags change during interrupt handler */
+ uint32_t tmpisrvalue = READ_REG(hsmbus->Instance->ISR);
+ uint32_t tmpcr1value = READ_REG(hsmbus->Instance->CR1);
+
+ /* SMBUS in mode Transmitter ---------------------------------------------------*/
+ if ((SMBUS_CHECK_IT_SOURCE(tmpcr1value, (SMBUS_IT_TCI | SMBUS_IT_STOPI |
+ SMBUS_IT_NACKI | SMBUS_IT_TXI)) != RESET) &&
+ ((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TXIS) != RESET) ||
+ (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) ||
+ (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) ||
+ (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) ||
+ (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)))
+ {
+ /* Slave mode selected */
+ if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX)
+ {
+ (void)SMBUS_Slave_ISR(hsmbus, tmpisrvalue);
+ }
+ /* Master mode selected */
+ else if ((hsmbus->State & HAL_SMBUS_STATE_MASTER_BUSY_TX) == HAL_SMBUS_STATE_MASTER_BUSY_TX)
+ {
+ (void)SMBUS_Master_ISR(hsmbus, tmpisrvalue);
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+ }
+
+ /* SMBUS in mode Receiver ----------------------------------------------------*/
+ if ((SMBUS_CHECK_IT_SOURCE(tmpcr1value, (SMBUS_IT_TCI | SMBUS_IT_STOPI |
+ SMBUS_IT_NACKI | SMBUS_IT_RXI)) != RESET) &&
+ ((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_RXNE) != RESET) ||
+ (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) ||
+ (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) ||
+ (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) ||
+ (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)))
+ {
+ /* Slave mode selected */
+ if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX)
+ {
+ (void)SMBUS_Slave_ISR(hsmbus, tmpisrvalue);
+ }
+ /* Master mode selected */
+ else if ((hsmbus->State & HAL_SMBUS_STATE_MASTER_BUSY_RX) == HAL_SMBUS_STATE_MASTER_BUSY_RX)
+ {
+ (void)SMBUS_Master_ISR(hsmbus, tmpisrvalue);
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+ }
+
+ /* SMBUS in mode Listener Only --------------------------------------------------*/
+ if (((SMBUS_CHECK_IT_SOURCE(tmpcr1value, SMBUS_IT_ADDRI) != RESET) ||
+ (SMBUS_CHECK_IT_SOURCE(tmpcr1value, SMBUS_IT_STOPI) != RESET) ||
+ (SMBUS_CHECK_IT_SOURCE(tmpcr1value, SMBUS_IT_NACKI) != RESET)) &&
+ ((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_ADDR) != RESET) ||
+ (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) ||
+ (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)))
+ {
+ if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN)
+ {
+ (void)SMBUS_Slave_ISR(hsmbus, tmpisrvalue);
+ }
+ }
+}
+
+/**
+ * @brief Handle SMBUS error interrupt request.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @retval None
+ */
+void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus)
+{
+ SMBUS_ITErrorHandler(hsmbus);
+}
+
+/**
+ * @brief Master Tx Transfer completed callback.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @retval None
+ */
+__weak void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsmbus);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMBUS_MasterTxCpltCallback() could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Master Rx Transfer completed callback.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @retval None
+ */
+__weak void HAL_SMBUS_MasterRxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsmbus);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMBUS_MasterRxCpltCallback() could be implemented in the user file
+ */
+}
+
+/** @brief Slave Tx Transfer completed callback.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @retval None
+ */
+__weak void HAL_SMBUS_SlaveTxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsmbus);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMBUS_SlaveTxCpltCallback() could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Slave Rx Transfer completed callback.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @retval None
+ */
+__weak void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsmbus);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMBUS_SlaveRxCpltCallback() could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Slave Address Match callback.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @param TransferDirection Master request Transfer Direction (Write/Read)
+ * @param AddrMatchCode Address Match Code
+ * @retval None
+ */
+__weak void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection,
+ uint16_t AddrMatchCode)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsmbus);
+ UNUSED(TransferDirection);
+ UNUSED(AddrMatchCode);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMBUS_AddrCallback() could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Listen Complete callback.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @retval None
+ */
+__weak void HAL_SMBUS_ListenCpltCallback(SMBUS_HandleTypeDef *hsmbus)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsmbus);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMBUS_ListenCpltCallback() could be implemented in the user file
+ */
+}
+
+/**
+ * @brief SMBUS error callback.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @retval None
+ */
+__weak void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsmbus);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMBUS_ErrorCallback() could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions
+ * @brief Peripheral State and Errors functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral State and Errors functions #####
+ ===============================================================================
+ [..]
+ This subsection permits to get in run-time the status of the peripheral
+ and the data flow.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the SMBUS handle state.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @retval HAL state
+ */
+uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus)
+{
+ /* Return SMBUS handle state */
+ return hsmbus->State;
+}
+
+/**
+ * @brief Return the SMBUS error code.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @retval SMBUS Error Code
+ */
+uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus)
+{
+ return hsmbus->ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup SMBUS_Private_Functions SMBUS Private Functions
+ * @brief Data transfers Private functions
+ * @{
+ */
+
+/**
+ * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @param StatusFlags Value of Interrupt Flags.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags)
+{
+ uint16_t DevAddress;
+
+ /* Process Locked */
+ __HAL_LOCK(hsmbus);
+
+ if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_AF) != RESET)
+ {
+ /* Clear NACK Flag */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF);
+
+ /* Set corresponding Error Code */
+ /* No need to generate STOP, it is automatically done */
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ACKF;
+
+ /* Flush TX register */
+ SMBUS_Flush_TXDR(hsmbus);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ /* Call the Error callback to inform upper layer */
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+ hsmbus->ErrorCallback(hsmbus);
+#else
+ HAL_SMBUS_ErrorCallback(hsmbus);
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
+ }
+ else if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_STOPF) != RESET)
+ {
+ /* Check and treat errors if errors occurs during STOP process */
+ SMBUS_ITErrorHandler(hsmbus);
+
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
+ {
+ /* Disable Interrupt */
+ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX);
+
+ /* Clear STOP Flag */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
+
+ /* Clear Configuration Register 2 */
+ SMBUS_RESET_CR2(hsmbus);
+
+ /* Flush remaining data in Fifo register in case of error occurs before TXEmpty */
+ /* Disable the selected SMBUS peripheral */
+ __HAL_SMBUS_DISABLE(hsmbus);
+
+ hsmbus->PreviousState = HAL_SMBUS_STATE_READY;
+ hsmbus->State = HAL_SMBUS_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ /* Re-enable the selected SMBUS peripheral */
+ __HAL_SMBUS_ENABLE(hsmbus);
+
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+ hsmbus->MasterTxCpltCallback(hsmbus);
+#else
+ HAL_SMBUS_MasterTxCpltCallback(hsmbus);
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
+ }
+ else if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
+ {
+ /* Store Last receive data if any */
+ if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_RXNE) != RESET)
+ {
+ /* Read data from RXDR */
+ *hsmbus->pBuffPtr = (uint8_t)(hsmbus->Instance->RXDR);
+
+ /* Increment Buffer pointer */
+ hsmbus->pBuffPtr++;
+
+ if ((hsmbus->XferSize > 0U))
+ {
+ hsmbus->XferSize--;
+ hsmbus->XferCount--;
+ }
+ }
+
+ /* Disable Interrupt */
+ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX);
+
+ /* Clear STOP Flag */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
+
+ /* Clear Configuration Register 2 */
+ SMBUS_RESET_CR2(hsmbus);
+
+ hsmbus->PreviousState = HAL_SMBUS_STATE_READY;
+ hsmbus->State = HAL_SMBUS_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+ hsmbus->MasterRxCpltCallback(hsmbus);
+#else
+ HAL_SMBUS_MasterRxCpltCallback(hsmbus);
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+ }
+ else if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_RXNE) != RESET)
+ {
+ /* Read data from RXDR */
+ *hsmbus->pBuffPtr = (uint8_t)(hsmbus->Instance->RXDR);
+
+ /* Increment Buffer pointer */
+ hsmbus->pBuffPtr++;
+
+ /* Increment Size counter */
+ hsmbus->XferSize--;
+ hsmbus->XferCount--;
+ }
+ else if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_TXIS) != RESET)
+ {
+ /* Write data to TXDR */
+ hsmbus->Instance->TXDR = *hsmbus->pBuffPtr;
+
+ /* Increment Buffer pointer */
+ hsmbus->pBuffPtr++;
+
+ /* Increment Size counter */
+ hsmbus->XferSize--;
+ hsmbus->XferCount--;
+ }
+ else if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_TCR) != RESET)
+ {
+ if ((hsmbus->XferCount != 0U) && (hsmbus->XferSize == 0U))
+ {
+ DevAddress = (uint16_t)(hsmbus->Instance->CR2 & I2C_CR2_SADD);
+
+ if (hsmbus->XferCount > MAX_NBYTE_SIZE)
+ {
+ SMBUS_TransferConfig(hsmbus, DevAddress, MAX_NBYTE_SIZE,
+ (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)),
+ SMBUS_NO_STARTSTOP);
+ hsmbus->XferSize = MAX_NBYTE_SIZE;
+ }
+ else
+ {
+ hsmbus->XferSize = hsmbus->XferCount;
+ SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions,
+ SMBUS_NO_STARTSTOP);
+ /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */
+ /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
+ if (SMBUS_GET_PEC_MODE(hsmbus) != 0UL)
+ {
+ hsmbus->XferSize--;
+ hsmbus->XferCount--;
+ }
+ }
+ }
+ else if ((hsmbus->XferCount == 0U) && (hsmbus->XferSize == 0U))
+ {
+ /* Call TxCpltCallback() if no stop mode is set */
+ if (SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE)
+ {
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
+ {
+ /* Disable Interrupt */
+ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX);
+ hsmbus->PreviousState = hsmbus->State;
+ hsmbus->State = HAL_SMBUS_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+ hsmbus->MasterTxCpltCallback(hsmbus);
+#else
+ HAL_SMBUS_MasterTxCpltCallback(hsmbus);
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
+ }
+ else if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
+ {
+ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX);
+ hsmbus->PreviousState = hsmbus->State;
+ hsmbus->State = HAL_SMBUS_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+ hsmbus->MasterRxCpltCallback(hsmbus);
+#else
+ HAL_SMBUS_MasterRxCpltCallback(hsmbus);
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+ }
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+ }
+ else if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_TC) != RESET)
+ {
+ if (hsmbus->XferCount == 0U)
+ {
+ /* Specific use case for Quick command */
+ if (hsmbus->pBuffPtr == NULL)
+ {
+ /* Generate a Stop command */
+ hsmbus->Instance->CR2 |= I2C_CR2_STOP;
+ }
+ /* Call TxCpltCallback() if no stop mode is set */
+ else if (SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE)
+ {
+ /* No Generate Stop, to permit restart mode */
+ /* The stop will be done at the end of transfer, when SMBUS_AUTOEND_MODE enable */
+
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
+ {
+ /* Disable Interrupt */
+ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX);
+ hsmbus->PreviousState = hsmbus->State;
+ hsmbus->State = HAL_SMBUS_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+ hsmbus->MasterTxCpltCallback(hsmbus);
+#else
+ HAL_SMBUS_MasterTxCpltCallback(hsmbus);
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
+ }
+ else if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
+ {
+ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX);
+ hsmbus->PreviousState = hsmbus->State;
+ hsmbus->State = HAL_SMBUS_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+ hsmbus->MasterRxCpltCallback(hsmbus);
+#else
+ HAL_SMBUS_MasterRxCpltCallback(hsmbus);
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+ }
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ return HAL_OK;
+}
+/**
+ * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @param StatusFlags Value of Interrupt Flags.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags)
+{
+ uint8_t TransferDirection;
+ uint16_t SlaveAddrCode;
+
+ /* Process Locked */
+ __HAL_LOCK(hsmbus);
+
+ if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_AF) != RESET)
+ {
+ /* Check that SMBUS transfer finished */
+ /* if yes, normal usecase, a NACK is sent by the HOST when Transfer is finished */
+ /* Mean XferCount == 0*/
+ /* So clear Flag NACKF only */
+ if (hsmbus->XferCount == 0U)
+ {
+ /* Clear NACK Flag */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF);
+
+ /* Flush TX register */
+ SMBUS_Flush_TXDR(hsmbus);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+ }
+ else
+ {
+ /* if no, error usecase, a Non-Acknowledge of last Data is generated by the HOST*/
+ /* Clear NACK Flag */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF);
+
+ /* Set HAL State to "Idle" State, mean to LISTEN state */
+ /* So reset Slave Busy state */
+ hsmbus->PreviousState = hsmbus->State;
+ hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_TX);
+ hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_RX);
+
+ /* Disable RX/TX Interrupts, keep only ADDR Interrupt */
+ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX | SMBUS_IT_TX);
+
+ /* Set ErrorCode corresponding to a Non-Acknowledge */
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ACKF;
+
+ /* Flush TX register */
+ SMBUS_Flush_TXDR(hsmbus);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ /* Call the Error callback to inform upper layer */
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+ hsmbus->ErrorCallback(hsmbus);
+#else
+ HAL_SMBUS_ErrorCallback(hsmbus);
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
+ }
+ }
+ else if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_ADDR) != RESET)
+ {
+ TransferDirection = (uint8_t)(SMBUS_GET_DIR(hsmbus));
+ SlaveAddrCode = (uint16_t)(SMBUS_GET_ADDR_MATCH(hsmbus));
+
+ /* Disable ADDR interrupt to prevent multiple ADDRInterrupt*/
+ /* Other ADDRInterrupt will be treat in next Listen usecase */
+ __HAL_SMBUS_DISABLE_IT(hsmbus, SMBUS_IT_ADDRI);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ /* Call Slave Addr callback */
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+ hsmbus->AddrCallback(hsmbus, TransferDirection, SlaveAddrCode);
+#else
+ HAL_SMBUS_AddrCallback(hsmbus, TransferDirection, SlaveAddrCode);
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
+ }
+ else if ((SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_RXNE) != RESET) ||
+ (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_TCR) != RESET))
+ {
+ if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX)
+ {
+ /* Read data from RXDR */
+ *hsmbus->pBuffPtr = (uint8_t)(hsmbus->Instance->RXDR);
+
+ /* Increment Buffer pointer */
+ hsmbus->pBuffPtr++;
+
+ hsmbus->XferSize--;
+ hsmbus->XferCount--;
+
+ if (hsmbus->XferCount == 1U)
+ {
+ /* Receive last Byte, can be PEC byte in case of PEC BYTE enabled */
+ /* or only the last Byte of Transfer */
+ /* So reset the RELOAD bit mode */
+ hsmbus->XferOptions &= ~SMBUS_RELOAD_MODE;
+ SMBUS_TransferConfig(hsmbus, 0, 1, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
+ }
+ else if (hsmbus->XferCount == 0U)
+ {
+ /* Last Byte is received, disable Interrupt */
+ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX);
+
+ /* Remove HAL_SMBUS_STATE_SLAVE_BUSY_RX, keep only HAL_SMBUS_STATE_LISTEN */
+ hsmbus->PreviousState = hsmbus->State;
+ hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_RX);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+ hsmbus->SlaveRxCpltCallback(hsmbus);
+#else
+ HAL_SMBUS_SlaveRxCpltCallback(hsmbus);
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
+ }
+ else
+ {
+ /* Set Reload for next Bytes */
+ SMBUS_TransferConfig(hsmbus, 0, 1,
+ SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE),
+ SMBUS_NO_STARTSTOP);
+
+ /* Ack last Byte Read */
+ hsmbus->Instance->CR2 &= ~I2C_CR2_NACK;
+ }
+ }
+ else if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX)
+ {
+ if ((hsmbus->XferCount != 0U) && (hsmbus->XferSize == 0U))
+ {
+ if (hsmbus->XferCount > MAX_NBYTE_SIZE)
+ {
+ SMBUS_TransferConfig(hsmbus, 0, MAX_NBYTE_SIZE,
+ (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)),
+ SMBUS_NO_STARTSTOP);
+ hsmbus->XferSize = MAX_NBYTE_SIZE;
+ }
+ else
+ {
+ hsmbus->XferSize = hsmbus->XferCount;
+ SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions,
+ SMBUS_NO_STARTSTOP);
+ /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */
+ /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
+ if (SMBUS_GET_PEC_MODE(hsmbus) != 0UL)
+ {
+ hsmbus->XferSize--;
+ hsmbus->XferCount--;
+ }
+ }
+ }
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+ }
+ else if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_TXIS) != RESET)
+ {
+ /* Write data to TXDR only if XferCount not reach "0" */
+ /* A TXIS flag can be set, during STOP treatment */
+ /* Check if all Data have already been sent */
+ /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */
+ if (hsmbus->XferCount > 0U)
+ {
+ /* Write data to TXDR */
+ hsmbus->Instance->TXDR = *hsmbus->pBuffPtr;
+
+ /* Increment Buffer pointer */
+ hsmbus->pBuffPtr++;
+
+ hsmbus->XferCount--;
+ hsmbus->XferSize--;
+ }
+
+ if (hsmbus->XferCount == 0U)
+ {
+ /* Last Byte is Transmitted */
+ /* Remove HAL_SMBUS_STATE_SLAVE_BUSY_TX, keep only HAL_SMBUS_STATE_LISTEN */
+ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX);
+ hsmbus->PreviousState = hsmbus->State;
+ hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_TX);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+ hsmbus->SlaveTxCpltCallback(hsmbus);
+#else
+ HAL_SMBUS_SlaveTxCpltCallback(hsmbus);
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
+ }
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+
+ /* Check if STOPF is set */
+ if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_STOPF) != RESET)
+ {
+ if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN)
+ {
+ /* Store Last receive data if any */
+ if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET)
+ {
+ /* Read data from RXDR */
+ *hsmbus->pBuffPtr = (uint8_t)(hsmbus->Instance->RXDR);
+
+ /* Increment Buffer pointer */
+ hsmbus->pBuffPtr++;
+
+ if ((hsmbus->XferSize > 0U))
+ {
+ hsmbus->XferSize--;
+ hsmbus->XferCount--;
+ }
+ }
+
+ /* Disable RX and TX Interrupts */
+ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX | SMBUS_IT_TX);
+
+ /* Disable ADDR Interrupt */
+ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR);
+
+ /* Disable Address Acknowledge */
+ hsmbus->Instance->CR2 |= I2C_CR2_NACK;
+
+ /* Clear Configuration Register 2 */
+ SMBUS_RESET_CR2(hsmbus);
+
+ /* Clear STOP Flag */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
+
+ /* Clear ADDR flag */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ADDR);
+
+ hsmbus->XferOptions = 0;
+ hsmbus->PreviousState = hsmbus->State;
+ hsmbus->State = HAL_SMBUS_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+ hsmbus->ListenCpltCallback(hsmbus);
+#else
+ HAL_SMBUS_ListenCpltCallback(hsmbus);
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
+ }
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ return HAL_OK;
+}
+/**
+ * @brief Manage the enabling of Interrupts.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @param InterruptRequest Value of @ref SMBUS_Interrupt_configuration_definition.
+ * @retval HAL status
+ */
+static void SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest)
+{
+ uint32_t tmpisr = 0UL;
+
+ if ((InterruptRequest & SMBUS_IT_ALERT) == SMBUS_IT_ALERT)
+ {
+ /* Enable ERR interrupt */
+ tmpisr |= SMBUS_IT_ERRI;
+ }
+
+ if ((InterruptRequest & SMBUS_IT_ADDR) == SMBUS_IT_ADDR)
+ {
+ /* Enable ADDR, STOP interrupt */
+ tmpisr |= SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_ERRI;
+ }
+
+ if ((InterruptRequest & SMBUS_IT_TX) == SMBUS_IT_TX)
+ {
+ /* Enable ERR, TC, STOP, NACK, RXI interrupt */
+ tmpisr |= SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI;
+ }
+
+ if ((InterruptRequest & SMBUS_IT_RX) == SMBUS_IT_RX)
+ {
+ /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+ tmpisr |= SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_RXI;
+ }
+
+ /* Enable interrupts only at the end */
+ /* to avoid the risk of SMBUS interrupt handle execution before */
+ /* all interrupts requested done */
+ __HAL_SMBUS_ENABLE_IT(hsmbus, tmpisr);
+}
+/**
+ * @brief Manage the disabling of Interrupts.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @param InterruptRequest Value of @ref SMBUS_Interrupt_configuration_definition.
+ * @retval HAL status
+ */
+static void SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest)
+{
+ uint32_t tmpisr = 0UL;
+ uint32_t tmpstate = hsmbus->State;
+
+ if ((tmpstate == HAL_SMBUS_STATE_READY) && ((InterruptRequest & SMBUS_IT_ALERT) == SMBUS_IT_ALERT))
+ {
+ /* Disable ERR interrupt */
+ tmpisr |= SMBUS_IT_ERRI;
+ }
+
+ if ((InterruptRequest & SMBUS_IT_TX) == SMBUS_IT_TX)
+ {
+ /* Disable TC, STOP, NACK and TXI interrupt */
+ tmpisr |= SMBUS_IT_TCI | SMBUS_IT_TXI;
+
+ if ((SMBUS_GET_ALERT_ENABLED(hsmbus) == 0UL)
+ && ((tmpstate & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN))
+ {
+ /* Disable ERR interrupt */
+ tmpisr |= SMBUS_IT_ERRI;
+ }
+
+ if ((tmpstate & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN)
+ {
+ /* Disable STOP and NACK interrupt */
+ tmpisr |= SMBUS_IT_STOPI | SMBUS_IT_NACKI;
+ }
+ }
+
+ if ((InterruptRequest & SMBUS_IT_RX) == SMBUS_IT_RX)
+ {
+ /* Disable TC, STOP, NACK and RXI interrupt */
+ tmpisr |= SMBUS_IT_TCI | SMBUS_IT_RXI;
+
+ if ((SMBUS_GET_ALERT_ENABLED(hsmbus) == 0UL)
+ && ((tmpstate & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN))
+ {
+ /* Disable ERR interrupt */
+ tmpisr |= SMBUS_IT_ERRI;
+ }
+
+ if ((tmpstate & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN)
+ {
+ /* Disable STOP and NACK interrupt */
+ tmpisr |= SMBUS_IT_STOPI | SMBUS_IT_NACKI;
+ }
+ }
+
+ if ((InterruptRequest & SMBUS_IT_ADDR) == SMBUS_IT_ADDR)
+ {
+ /* Disable ADDR, STOP and NACK interrupt */
+ tmpisr |= SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI;
+
+ if (SMBUS_GET_ALERT_ENABLED(hsmbus) == 0UL)
+ {
+ /* Disable ERR interrupt */
+ tmpisr |= SMBUS_IT_ERRI;
+ }
+ }
+
+ /* Disable interrupts only at the end */
+ /* to avoid a breaking situation like at "t" time */
+ /* all disable interrupts request are not done */
+ __HAL_SMBUS_DISABLE_IT(hsmbus, tmpisr);
+}
+
+/**
+ * @brief SMBUS interrupts error handler.
+ * @param hsmbus SMBUS handle.
+ * @retval None
+ */
+static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus)
+{
+ uint32_t itflags = READ_REG(hsmbus->Instance->ISR);
+ uint32_t itsources = READ_REG(hsmbus->Instance->CR1);
+ uint32_t tmpstate;
+ uint32_t tmperror;
+
+ /* SMBUS Bus error interrupt occurred ------------------------------------*/
+ if (((itflags & SMBUS_FLAG_BERR) == SMBUS_FLAG_BERR) && \
+ ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI))
+ {
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BERR;
+
+ /* Clear BERR flag */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_BERR);
+ }
+
+ /* SMBUS Over-Run/Under-Run interrupt occurred ----------------------------------------*/
+ if (((itflags & SMBUS_FLAG_OVR) == SMBUS_FLAG_OVR) && \
+ ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI))
+ {
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_OVR;
+
+ /* Clear OVR flag */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_OVR);
+ }
+
+ /* SMBUS Arbitration Loss error interrupt occurred ------------------------------------*/
+ if (((itflags & SMBUS_FLAG_ARLO) == SMBUS_FLAG_ARLO) && \
+ ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI))
+ {
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ARLO;
+
+ /* Clear ARLO flag */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ARLO);
+ }
+
+ /* SMBUS Timeout error interrupt occurred ---------------------------------------------*/
+ if (((itflags & SMBUS_FLAG_TIMEOUT) == SMBUS_FLAG_TIMEOUT) && \
+ ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI))
+ {
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BUSTIMEOUT;
+
+ /* Clear TIMEOUT flag */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_TIMEOUT);
+ }
+
+ /* SMBUS Alert error interrupt occurred -----------------------------------------------*/
+ if (((itflags & SMBUS_FLAG_ALERT) == SMBUS_FLAG_ALERT) && \
+ ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI))
+ {
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ALERT;
+
+ /* Clear ALERT flag */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ALERT);
+ }
+
+ /* SMBUS Packet Error Check error interrupt occurred ----------------------------------*/
+ if (((itflags & SMBUS_FLAG_PECERR) == SMBUS_FLAG_PECERR) && \
+ ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI))
+ {
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_PECERR;
+
+ /* Clear PEC error flag */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_PECERR);
+ }
+
+ /* Flush TX register */
+ SMBUS_Flush_TXDR(hsmbus);
+
+ /* Store current volatile hsmbus->ErrorCode, misra rule */
+ tmperror = hsmbus->ErrorCode;
+
+ /* Call the Error Callback in case of Error detected */
+ if ((tmperror != HAL_SMBUS_ERROR_NONE) && (tmperror != HAL_SMBUS_ERROR_ACKF))
+ {
+ /* Do not Reset the HAL state in case of ALERT error */
+ if ((tmperror & HAL_SMBUS_ERROR_ALERT) != HAL_SMBUS_ERROR_ALERT)
+ {
+ /* Store current volatile hsmbus->State, misra rule */
+ tmpstate = hsmbus->State;
+
+ if (((tmpstate & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX)
+ || ((tmpstate & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX))
+ {
+ /* Reset only HAL_SMBUS_STATE_SLAVE_BUSY_XX */
+ /* keep HAL_SMBUS_STATE_LISTEN if set */
+ hsmbus->PreviousState = HAL_SMBUS_STATE_READY;
+ hsmbus->State = HAL_SMBUS_STATE_LISTEN;
+ }
+ }
+
+ /* Call the Error callback to inform upper layer */
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+ hsmbus->ErrorCallback(hsmbus);
+#else
+ HAL_SMBUS_ErrorCallback(hsmbus);
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
+ }
+}
+
+/**
+ * @brief Handle SMBUS Communication Timeout.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @param Flag Specifies the SMBUS flag to check.
+ * @param Status The new Flag status (SET or RESET).
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag,
+ FlagStatus Status, uint32_t Timeout)
+{
+ uint32_t tickstart = HAL_GetTick();
+
+ /* Wait until flag is set */
+ while ((FlagStatus)(__HAL_SMBUS_GET_FLAG(hsmbus, Flag)) == Status)
+ {
+ /* Check for the Timeout */
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL))
+ {
+ hsmbus->PreviousState = hsmbus->State;
+ hsmbus->State = HAL_SMBUS_STATE_READY;
+
+ /* Update SMBUS error code */
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_HALTIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ return HAL_ERROR;
+ }
+ }
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief SMBUS Tx data register flush process.
+ * @param hsmbus SMBUS handle.
+ * @retval None
+ */
+static void SMBUS_Flush_TXDR(SMBUS_HandleTypeDef *hsmbus)
+{
+ /* If a pending TXIS flag is set */
+ /* Write a dummy data in TXDR to clear it */
+ if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TXIS) != RESET)
+ {
+ hsmbus->Instance->TXDR = 0x00U;
+ }
+
+ /* Flush TX register if not empty */
+ if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TXE) == RESET)
+ {
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_TXE);
+ }
+}
+
+/**
+ * @brief Handle SMBUSx communication when starting transfer or during transfer (TC or TCR flag are set).
+ * @param hsmbus SMBUS handle.
+ * @param DevAddress specifies the slave address to be programmed.
+ * @param Size specifies the number of bytes to be programmed.
+ * This parameter must be a value between 0 and 255.
+ * @param Mode New state of the SMBUS START condition generation.
+ * This parameter can be one or a combination of the following values:
+ * @arg @ref SMBUS_RELOAD_MODE Enable Reload mode.
+ * @arg @ref SMBUS_AUTOEND_MODE Enable Automatic end mode.
+ * @arg @ref SMBUS_SOFTEND_MODE Enable Software end mode and Reload mode.
+ * @arg @ref SMBUS_SENDPEC_MODE Enable Packet Error Calculation mode.
+ * @param Request New state of the SMBUS START condition generation.
+ * This parameter can be one of the following values:
+ * @arg @ref SMBUS_NO_STARTSTOP Don't Generate stop and start condition.
+ * @arg @ref SMBUS_GENERATE_STOP Generate stop condition (Size should be set to 0).
+ * @arg @ref SMBUS_GENERATE_START_READ Generate Restart for read request.
+ * @arg @ref SMBUS_GENERATE_START_WRITE Generate Restart for write request.
+ * @retval None
+ */
+static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size,
+ uint32_t Mode, uint32_t Request)
+{
+ /* Check the parameters */
+ assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
+ assert_param(IS_SMBUS_TRANSFER_MODE(Mode));
+ assert_param(IS_SMBUS_TRANSFER_REQUEST(Request));
+
+ /* update CR2 register */
+ MODIFY_REG(hsmbus->Instance->CR2,
+ ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | \
+ (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31UL - I2C_CR2_RD_WRN_Pos))) | \
+ I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_PECBYTE)), \
+ (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \
+ (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \
+ (uint32_t)Mode | (uint32_t)Request));
+}
+
+/**
+ * @brief Convert SMBUSx OTHER_xxx XferOptions to functional XferOptions.
+ * @param hsmbus SMBUS handle.
+ * @retval None
+ */
+static void SMBUS_ConvertOtherXferOptions(SMBUS_HandleTypeDef *hsmbus)
+{
+ /* if user set XferOptions to SMBUS_OTHER_FRAME_NO_PEC */
+ /* it request implicitly to generate a restart condition */
+ /* set XferOptions to SMBUS_FIRST_FRAME */
+ if (hsmbus->XferOptions == SMBUS_OTHER_FRAME_NO_PEC)
+ {
+ hsmbus->XferOptions = SMBUS_FIRST_FRAME;
+ }
+ /* else if user set XferOptions to SMBUS_OTHER_FRAME_WITH_PEC */
+ /* it request implicitly to generate a restart condition */
+ /* set XferOptions to SMBUS_FIRST_FRAME | SMBUS_SENDPEC_MODE */
+ else if (hsmbus->XferOptions == SMBUS_OTHER_FRAME_WITH_PEC)
+ {
+ hsmbus->XferOptions = SMBUS_FIRST_FRAME | SMBUS_SENDPEC_MODE;
+ }
+ /* else if user set XferOptions to SMBUS_OTHER_AND_LAST_FRAME_NO_PEC */
+ /* it request implicitly to generate a restart condition */
+ /* then generate a stop condition at the end of transfer */
+ /* set XferOptions to SMBUS_FIRST_AND_LAST_FRAME_NO_PEC */
+ else if (hsmbus->XferOptions == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC)
+ {
+ hsmbus->XferOptions = SMBUS_FIRST_AND_LAST_FRAME_NO_PEC;
+ }
+ /* else if user set XferOptions to SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC */
+ /* it request implicitly to generate a restart condition */
+ /* then generate a stop condition at the end of transfer */
+ /* set XferOptions to SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC */
+ else if (hsmbus->XferOptions == SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC)
+ {
+ hsmbus->XferOptions = SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC;
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+}
+/**
+ * @}
+ */
+
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_smbus_ex.c b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_smbus_ex.c
new file mode 100644
index 0000000000..19662b2637
--- /dev/null
+++ b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_smbus_ex.c
@@ -0,0 +1,242 @@
+/**
+ ******************************************************************************
+ * @file stm32c0xx_hal_smbus_ex.c
+ * @author MCD Application Team
+ * @brief SMBUS Extended HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of SMBUS Extended peripheral:
+ * + Extended features functions
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2022 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### SMBUS peripheral Extended features #####
+ ==============================================================================
+
+ [..] Comparing to other previous devices, the SMBUS interface for STM32C0xx
+ devices contains the following additional features
+
+ (+) Disable or enable wakeup from Stop mode(s)
+ (+) Disable or enable Fast Mode Plus
+
+ ##### How to use this driver #####
+ ==============================================================================
+ (#) Configure the enable or disable of SMBUS Wake Up Mode using the functions :
+ (++) HAL_SMBUSEx_EnableWakeUp()
+ (++) HAL_SMBUSEx_DisableWakeUp()
+ (#) Configure the enable or disable of fast mode plus driving capability using the functions :
+ (++) HAL_SMBUSEx_EnableFastModePlus()
+ (++) HAL_SMBUSEx_DisableFastModePlus()
+ @endverbatim
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32c0xx_hal.h"
+
+/** @addtogroup STM32C0xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup SMBUSEx SMBUSEx
+ * @brief SMBUS Extended HAL module driver
+ * @{
+ */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup SMBUSEx_Exported_Functions SMBUS Extended Exported Functions
+ * @{
+ */
+
+/** @defgroup SMBUSEx_Exported_Functions_Group2 WakeUp Mode Functions
+ * @brief WakeUp Mode Functions
+ *
+@verbatim
+ ===============================================================================
+ ##### WakeUp Mode Functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Configure Wake Up Feature
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enable SMBUS wakeup from Stop mode(s).
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUSx peripheral.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMBUSEx_EnableWakeUp(SMBUS_HandleTypeDef *hsmbus)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hsmbus->Instance));
+
+ if (hsmbus->State == HAL_SMBUS_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hsmbus);
+
+ hsmbus->State = HAL_SMBUS_STATE_BUSY;
+
+ /* Disable the selected SMBUS peripheral */
+ __HAL_SMBUS_DISABLE(hsmbus);
+
+ /* Enable wakeup from stop mode */
+ hsmbus->Instance->CR1 |= I2C_CR1_WUPEN;
+
+ __HAL_SMBUS_ENABLE(hsmbus);
+
+ hsmbus->State = HAL_SMBUS_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Disable SMBUS wakeup from Stop mode(s).
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUSx peripheral.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMBUSEx_DisableWakeUp(SMBUS_HandleTypeDef *hsmbus)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hsmbus->Instance));
+
+ if (hsmbus->State == HAL_SMBUS_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hsmbus);
+
+ hsmbus->State = HAL_SMBUS_STATE_BUSY;
+
+ /* Disable the selected SMBUS peripheral */
+ __HAL_SMBUS_DISABLE(hsmbus);
+
+ /* Disable wakeup from stop mode */
+ hsmbus->Instance->CR1 &= ~(I2C_CR1_WUPEN);
+
+ __HAL_SMBUS_ENABLE(hsmbus);
+
+ hsmbus->State = HAL_SMBUS_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+/**
+ * @}
+ */
+
+/** @defgroup SMBUSEx_Exported_Functions_Group3 Fast Mode Plus Functions
+ * @brief Fast Mode Plus Functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Fast Mode Plus Functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Configure Fast Mode Plus
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enable the SMBUS fast mode plus driving capability.
+ * @param ConfigFastModePlus Selects the pin.
+ * This parameter can be one of the @ref SMBUSEx_FastModePlus values
+ * @note For I2C1, fast mode plus driving capability can be enabled on all selected
+ * I2C1 pins using SMBUS_FASTMODEPLUS_I2C1 parameter or independently
+ * on each one of the following pins PB6, PB7, PB8 and PB9.
+ * @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability
+ * can be enabled only by using SMBUS_FASTMODEPLUS_I2C1 parameter.
+ * @retval None
+ */
+void HAL_SMBUSEx_EnableFastModePlus(uint32_t ConfigFastModePlus)
+{
+ /* Check the parameter */
+ assert_param(IS_SMBUS_FASTMODEPLUS(ConfigFastModePlus));
+
+ /* Enable SYSCFG clock */
+ __HAL_RCC_SYSCFG_CLK_ENABLE();
+
+ /* Enable fast mode plus driving capability for selected pin */
+ SET_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus);
+}
+
+/**
+ * @brief Disable the SMBUS fast mode plus driving capability.
+ * @param ConfigFastModePlus Selects the pin.
+ * This parameter can be one of the @ref SMBUSEx_FastModePlus values
+ * @note For I2C1, fast mode plus driving capability can be disabled on all selected
+ * I2C1 pins using SMBUS_FASTMODEPLUS_I2C1 parameter or independently
+ * on each one of the following pins PB6, PB7, PB8 and PB9.
+ * @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability
+ * can be disabled only by using SMBUS_FASTMODEPLUS_I2C1 parameter.
+ * @retval None
+ */
+void HAL_SMBUSEx_DisableFastModePlus(uint32_t ConfigFastModePlus)
+{
+ /* Check the parameter */
+ assert_param(IS_SMBUS_FASTMODEPLUS(ConfigFastModePlus));
+
+ /* Enable SYSCFG clock */
+ __HAL_RCC_SYSCFG_CLK_ENABLE();
+
+ /* Disable fast mode plus driving capability for selected pin */
+ CLEAR_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus);
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_spi.c b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_spi.c
new file mode 100644
index 0000000000..e2446fd10c
--- /dev/null
+++ b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_spi.c
@@ -0,0 +1,4435 @@
+/**
+ ******************************************************************************
+ * @file stm32c0xx_hal_spi.c
+ * @author MCD Application Team
+ * @brief SPI HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Serial Peripheral Interface (SPI) peripheral:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral Control functions
+ * + Peripheral State functions
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2022 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ The SPI HAL driver can be used as follows:
+
+ (#) Declare a SPI_HandleTypeDef handle structure, for example:
+ SPI_HandleTypeDef hspi;
+
+ (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit() API:
+ (##) Enable the SPIx interface clock
+ (##) SPI pins configuration
+ (+++) Enable the clock for the SPI GPIOs
+ (+++) Configure these SPI pins as alternate function push-pull
+ (##) NVIC configuration if you need to use interrupt process
+ (+++) Configure the SPIx interrupt priority
+ (+++) Enable the NVIC SPI IRQ handle
+ (##) DMA Configuration if you need to use DMA process
+ (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive Stream/Channel
+ (+++) Enable the DMAx clock
+ (+++) Configure the DMA handle parameters
+ (+++) Configure the DMA Tx or Rx Stream/Channel
+ (+++) Associate the initialized hdma_tx(or _rx) handle to the hspi DMA Tx or Rx handle
+ (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream/Channel
+
+ (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS
+ management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
+
+ (#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
+ (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
+ by calling the customized HAL_SPI_MspInit() API.
+ [..]
+ Circular mode restriction:
+ (#) The DMA circular mode cannot be used when the SPI is configured in these modes:
+ (##) Master 2Lines RxOnly
+ (##) Master 1Line Rx
+ (#) The CRC feature is not managed when the DMA circular mode is enabled
+ (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs
+ the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks
+ [..]
+ Master Receive mode restriction:
+ (#) In Master unidirectional receive-only mode (MSTR =1, BIDIMODE=0, RXONLY=1) or
+ bidirectional receive mode (MSTR=1, BIDIMODE=1, BIDIOE=0), to ensure that the SPI
+ does not initiate a new transfer the following procedure has to be respected:
+ (##) HAL_SPI_DeInit()
+ (##) HAL_SPI_Init()
+ [..]
+ Callback registration:
+
+ (#) The compilation flag USE_HAL_SPI_REGISTER_CALLBACKS when set to 1U
+ allows the user to configure dynamically the driver callbacks.
+ Use Functions HAL_SPI_RegisterCallback() to register an interrupt callback.
+
+ Function HAL_SPI_RegisterCallback() allows to register following callbacks:
+ (++) TxCpltCallback : SPI Tx Completed callback
+ (++) RxCpltCallback : SPI Rx Completed callback
+ (++) TxRxCpltCallback : SPI TxRx Completed callback
+ (++) TxHalfCpltCallback : SPI Tx Half Completed callback
+ (++) RxHalfCpltCallback : SPI Rx Half Completed callback
+ (++) TxRxHalfCpltCallback : SPI TxRx Half Completed callback
+ (++) ErrorCallback : SPI Error callback
+ (++) AbortCpltCallback : SPI Abort callback
+ (++) MspInitCallback : SPI Msp Init callback
+ (++) MspDeInitCallback : SPI Msp DeInit callback
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+
+ (#) Use function HAL_SPI_UnRegisterCallback to reset a callback to the default
+ weak function.
+ HAL_SPI_UnRegisterCallback takes as parameters the HAL peripheral handle,
+ and the Callback ID.
+ This function allows to reset following callbacks:
+ (++) TxCpltCallback : SPI Tx Completed callback
+ (++) RxCpltCallback : SPI Rx Completed callback
+ (++) TxRxCpltCallback : SPI TxRx Completed callback
+ (++) TxHalfCpltCallback : SPI Tx Half Completed callback
+ (++) RxHalfCpltCallback : SPI Rx Half Completed callback
+ (++) TxRxHalfCpltCallback : SPI TxRx Half Completed callback
+ (++) ErrorCallback : SPI Error callback
+ (++) AbortCpltCallback : SPI Abort callback
+ (++) MspInitCallback : SPI Msp Init callback
+ (++) MspDeInitCallback : SPI Msp DeInit callback
+
+ [..]
+ By default, after the HAL_SPI_Init() and when the state is HAL_SPI_STATE_RESET
+ all callbacks are set to the corresponding weak functions:
+ examples HAL_SPI_MasterTxCpltCallback(), HAL_SPI_MasterRxCpltCallback().
+ Exception done for MspInit and MspDeInit functions that are
+ reset to the legacy weak functions in the HAL_SPI_Init()/ HAL_SPI_DeInit() only when
+ these callbacks are null (not registered beforehand).
+ If MspInit or MspDeInit are not null, the HAL_SPI_Init()/ HAL_SPI_DeInit()
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
+
+ [..]
+ Callbacks can be registered/unregistered in HAL_SPI_STATE_READY state only.
+ Exception done MspInit/MspDeInit functions that can be registered/unregistered
+ in HAL_SPI_STATE_READY or HAL_SPI_STATE_RESET state,
+ thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+ Then, the user first registers the MspInit/MspDeInit user callbacks
+ using HAL_SPI_RegisterCallback() before calling HAL_SPI_DeInit()
+ or HAL_SPI_Init() function.
+
+ [..]
+ When the compilation define USE_HAL_PPP_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registering feature is not available
+ and weak (surcharged) callbacks are used.
+
+ [..]
+ Using the HAL it is not possible to reach all supported SPI frequency with the different SPI Modes,
+ the following table resume the max SPI frequency reached with data size 8bits/16bits,
+ according to frequency of the APBx Peripheral Clock (fPCLK) used by the SPI instance.
+
+ @endverbatim
+
+ Additional table :
+
+ DataSize = SPI_DATASIZE_8BIT:
+ +----------------------------------------------------------------------------------------------+
+ | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line |
+ | Process | Transfer mode |---------------------|----------------------|----------------------|
+ | | | Master | Slave | Master | Slave | Master | Slave |
+ |==============================================================================================|
+ | T | Polling | Fpclk/4 | Fpclk/8 | NA | NA | NA | NA |
+ | X |----------------|----------|----------|-----------|----------|-----------|----------|
+ | / | Interrupt | Fpclk/4 | Fpclk/16 | NA | NA | NA | NA |
+ | R |----------------|----------|----------|-----------|----------|-----------|----------|
+ | X | DMA | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA |
+ |=========|================|==========|==========|===========|==========|===========|==========|
+ | | Polling | Fpclk/4 | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 |
+ | |----------------|----------|----------|-----------|----------|-----------|----------|
+ | R | Interrupt | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 | Fpclk/4 |
+ | X |----------------|----------|----------|-----------|----------|-----------|----------|
+ | | DMA | Fpclk/4 | Fpclk/2 | Fpclk/2 | Fpclk/16 | Fpclk/2 | Fpclk/16 |
+ |=========|================|==========|==========|===========|==========|===========|==========|
+ | | Polling | Fpclk/8 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/8 |
+ | |----------------|----------|----------|-----------|----------|-----------|----------|
+ | T | Interrupt | Fpclk/2 | Fpclk/4 | NA | NA | Fpclk/16 | Fpclk/8 |
+ | X |----------------|----------|----------|-----------|----------|-----------|----------|
+ | | DMA | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/16 |
+ +----------------------------------------------------------------------------------------------+
+
+ DataSize = SPI_DATASIZE_16BIT:
+ +----------------------------------------------------------------------------------------------+
+ | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line |
+ | Process | Transfer mode |---------------------|----------------------|----------------------|
+ | | | Master | Slave | Master | Slave | Master | Slave |
+ |==============================================================================================|
+ | T | Polling | Fpclk/4 | Fpclk/8 | NA | NA | NA | NA |
+ | X |----------------|----------|----------|-----------|----------|-----------|----------|
+ | / | Interrupt | Fpclk/4 | Fpclk/16 | NA | NA | NA | NA |
+ | R |----------------|----------|----------|-----------|----------|-----------|----------|
+ | X | DMA | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA |
+ |=========|================|==========|==========|===========|==========|===========|==========|
+ | | Polling | Fpclk/4 | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 |
+ | |----------------|----------|----------|-----------|----------|-----------|----------|
+ | R | Interrupt | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 | Fpclk/4 |
+ | X |----------------|----------|----------|-----------|----------|-----------|----------|
+ | | DMA | Fpclk/4 | Fpclk/2 | Fpclk/2 | Fpclk/16 | Fpclk/2 | Fpclk/16 |
+ |=========|================|==========|==========|===========|==========|===========|==========|
+ | | Polling | Fpclk/8 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/8 |
+ | |----------------|----------|----------|-----------|----------|-----------|----------|
+ | T | Interrupt | Fpclk/2 | Fpclk/4 | NA | NA | Fpclk/16 | Fpclk/8 |
+ | X |----------------|----------|----------|-----------|----------|-----------|----------|
+ | | DMA | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/16 |
+ +----------------------------------------------------------------------------------------------+
+ @note The max SPI frequency depend on SPI data size (4bits, 5bits,..., 8bits,...15bits, 16bits),
+ SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA).
+ @note
+ (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA()
+ (#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA()
+ (#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA()
+
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32c0xx_hal.h"
+
+/** @addtogroup STM32C0xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup SPI SPI
+ * @brief SPI HAL module driver
+ * @{
+ */
+#ifdef HAL_SPI_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private defines -----------------------------------------------------------*/
+/** @defgroup SPI_Private_Constants SPI Private Constants
+ * @{
+ */
+#define SPI_DEFAULT_TIMEOUT 100U
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup SPI_Private_Functions SPI Private Functions
+ * @{
+ */
+static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
+static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
+static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);
+static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma);
+static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma);
+static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma);
+static void SPI_DMAError(DMA_HandleTypeDef *hdma);
+static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma);
+static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
+static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
+static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State,
+ uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State,
+ uint32_t Timeout, uint32_t Tickstart);
+static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
+static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
+static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
+static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
+static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
+static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
+static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
+static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
+#if (USE_SPI_CRC != 0U)
+static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
+static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
+static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
+static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
+#endif /* USE_SPI_CRC */
+static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi);
+static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi);
+static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi);
+static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi);
+static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi);
+static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup SPI_Exported_Functions SPI Exported Functions
+ * @{
+ */
+
+/** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..] This subsection provides a set of functions allowing to initialize and
+ de-initialize the SPIx peripheral:
+
+ (+) User must implement HAL_SPI_MspInit() function in which he configures
+ all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
+
+ (+) Call the function HAL_SPI_Init() to configure the selected device with
+ the selected configuration:
+ (++) Mode
+ (++) Direction
+ (++) Data Size
+ (++) Clock Polarity and Phase
+ (++) NSS Management
+ (++) BaudRate Prescaler
+ (++) FirstBit
+ (++) TIMode
+ (++) CRC Calculation
+ (++) CRC Polynomial if CRC enabled
+ (++) CRC Length, used only with Data8 and Data16
+ (++) FIFO reception threshold
+
+ (+) Call the function HAL_SPI_DeInit() to restore the default configuration
+ of the selected SPIx peripheral.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initialize the SPI according to the specified parameters
+ * in the SPI_InitTypeDef and initialize the associated handle.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
+{
+ uint32_t frxth;
+
+ /* Check the SPI handle allocation */
+ if (hspi == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
+ assert_param(IS_SPI_MODE(hspi->Init.Mode));
+ assert_param(IS_SPI_DIRECTION(hspi->Init.Direction));
+ assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
+ assert_param(IS_SPI_NSS(hspi->Init.NSS));
+ assert_param(IS_SPI_NSSP(hspi->Init.NSSPMode));
+ assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
+ assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
+ assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
+ if (hspi->Init.TIMode == SPI_TIMODE_DISABLE)
+ {
+ assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
+ assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
+
+ if (hspi->Init.Mode == SPI_MODE_MASTER)
+ {
+ assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
+ }
+ else
+ {
+ /* Baudrate prescaler not use in Motoraola Slave mode. force to default value */
+ hspi->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
+ }
+ }
+ else
+ {
+ assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
+
+ /* Force polarity and phase to TI protocaol requirements */
+ hspi->Init.CLKPolarity = SPI_POLARITY_LOW;
+ hspi->Init.CLKPhase = SPI_PHASE_1EDGE;
+ }
+#if (USE_SPI_CRC != 0U)
+ assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
+ assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength));
+ }
+#else
+ hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
+#endif /* USE_SPI_CRC */
+
+ if (hspi->State == HAL_SPI_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hspi->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ /* Init the SPI Callback settings */
+ hspi->TxCpltCallback = HAL_SPI_TxCpltCallback; /* Legacy weak TxCpltCallback */
+ hspi->RxCpltCallback = HAL_SPI_RxCpltCallback; /* Legacy weak RxCpltCallback */
+ hspi->TxRxCpltCallback = HAL_SPI_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */
+ hspi->TxHalfCpltCallback = HAL_SPI_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
+ hspi->RxHalfCpltCallback = HAL_SPI_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
+ hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */
+ hspi->ErrorCallback = HAL_SPI_ErrorCallback; /* Legacy weak ErrorCallback */
+ hspi->AbortCpltCallback = HAL_SPI_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
+
+ if (hspi->MspInitCallback == NULL)
+ {
+ hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */
+ }
+
+ /* Init the low level hardware : GPIO, CLOCK, NVIC... */
+ hspi->MspInitCallback(hspi);
+#else
+ /* Init the low level hardware : GPIO, CLOCK, NVIC... */
+ HAL_SPI_MspInit(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+ }
+
+ hspi->State = HAL_SPI_STATE_BUSY;
+
+ /* Disable the selected SPI peripheral */
+ __HAL_SPI_DISABLE(hspi);
+
+ /* Align by default the rs fifo threshold on the data size */
+ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+ {
+ frxth = SPI_RXFIFO_THRESHOLD_HF;
+ }
+ else
+ {
+ frxth = SPI_RXFIFO_THRESHOLD_QF;
+ }
+
+ /* CRC calculation is valid only for 16Bit and 8 Bit */
+ if ((hspi->Init.DataSize != SPI_DATASIZE_16BIT) && (hspi->Init.DataSize != SPI_DATASIZE_8BIT))
+ {
+ /* CRC must be disabled */
+ hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
+ }
+
+ /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
+ /* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management,
+ Communication speed, First bit and CRC calculation state */
+ WRITE_REG(hspi->Instance->CR1, ((hspi->Init.Mode & (SPI_CR1_MSTR | SPI_CR1_SSI)) |
+ (hspi->Init.Direction & (SPI_CR1_RXONLY | SPI_CR1_BIDIMODE)) |
+ (hspi->Init.CLKPolarity & SPI_CR1_CPOL) |
+ (hspi->Init.CLKPhase & SPI_CR1_CPHA) |
+ (hspi->Init.NSS & SPI_CR1_SSM) |
+ (hspi->Init.BaudRatePrescaler & SPI_CR1_BR_Msk) |
+ (hspi->Init.FirstBit & SPI_CR1_LSBFIRST) |
+ (hspi->Init.CRCCalculation & SPI_CR1_CRCEN)));
+#if (USE_SPI_CRC != 0U)
+ /*---------------------------- SPIx CRCL Configuration -------------------*/
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ /* Align the CRC Length on the data size */
+ if (hspi->Init.CRCLength == SPI_CRC_LENGTH_DATASIZE)
+ {
+ /* CRC Length aligned on the data size : value set by default */
+ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+ {
+ hspi->Init.CRCLength = SPI_CRC_LENGTH_16BIT;
+ }
+ else
+ {
+ hspi->Init.CRCLength = SPI_CRC_LENGTH_8BIT;
+ }
+ }
+
+ /* Configure : CRC Length */
+ if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
+ {
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCL);
+ }
+ }
+#endif /* USE_SPI_CRC */
+
+ /* Configure : NSS management, TI Mode, NSS Pulse, Data size and Rx Fifo threshold */
+ WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) |
+ (hspi->Init.TIMode & SPI_CR2_FRF) |
+ (hspi->Init.NSSPMode & SPI_CR2_NSSP) |
+ (hspi->Init.DataSize & SPI_CR2_DS_Msk) |
+ (frxth & SPI_CR2_FRXTH)));
+
+#if (USE_SPI_CRC != 0U)
+ /*---------------------------- SPIx CRCPOLY Configuration ------------------*/
+ /* Configure : CRC Polynomial */
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ WRITE_REG(hspi->Instance->CRCPR, (hspi->Init.CRCPolynomial & SPI_CRCPR_CRCPOLY_Msk));
+ }
+#endif /* USE_SPI_CRC */
+
+#if defined(SPI_I2SCFGR_I2SMOD)
+ /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
+ CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
+#endif /* SPI_I2SCFGR_I2SMOD */
+
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ hspi->State = HAL_SPI_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief De-Initialize the SPI peripheral.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
+{
+ /* Check the SPI handle allocation */
+ if (hspi == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check SPI Instance parameter */
+ assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
+
+ hspi->State = HAL_SPI_STATE_BUSY;
+
+ /* Disable the SPI Peripheral Clock */
+ __HAL_SPI_DISABLE(hspi);
+
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ if (hspi->MspDeInitCallback == NULL)
+ {
+ hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */
+ }
+
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
+ hspi->MspDeInitCallback(hspi);
+#else
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
+ HAL_SPI_MspDeInit(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ hspi->State = HAL_SPI_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hspi);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initialize the SPI MSP.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+__weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hspi);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SPI_MspInit should be implemented in the user file
+ */
+}
+
+/**
+ * @brief De-Initialize the SPI MSP.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+__weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hspi);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SPI_MspDeInit should be implemented in the user file
+ */
+}
+
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+/**
+ * @brief Register a User SPI Callback
+ * To be used instead of the weak predefined callback
+ * @param hspi Pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for the specified SPI.
+ * @param CallbackID ID of the callback to be registered
+ * @param pCallback pointer to the Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID,
+ pSPI_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hspi->ErrorCode |= HAL_SPI_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+ /* Process locked */
+ __HAL_LOCK(hspi);
+
+ if (HAL_SPI_STATE_READY == hspi->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_SPI_TX_COMPLETE_CB_ID :
+ hspi->TxCpltCallback = pCallback;
+ break;
+
+ case HAL_SPI_RX_COMPLETE_CB_ID :
+ hspi->RxCpltCallback = pCallback;
+ break;
+
+ case HAL_SPI_TX_RX_COMPLETE_CB_ID :
+ hspi->TxRxCpltCallback = pCallback;
+ break;
+
+ case HAL_SPI_TX_HALF_COMPLETE_CB_ID :
+ hspi->TxHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_SPI_RX_HALF_COMPLETE_CB_ID :
+ hspi->RxHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID :
+ hspi->TxRxHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_SPI_ERROR_CB_ID :
+ hspi->ErrorCallback = pCallback;
+ break;
+
+ case HAL_SPI_ABORT_CB_ID :
+ hspi->AbortCpltCallback = pCallback;
+ break;
+
+ case HAL_SPI_MSPINIT_CB_ID :
+ hspi->MspInitCallback = pCallback;
+ break;
+
+ case HAL_SPI_MSPDEINIT_CB_ID :
+ hspi->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_SPI_STATE_RESET == hspi->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_SPI_MSPINIT_CB_ID :
+ hspi->MspInitCallback = pCallback;
+ break;
+
+ case HAL_SPI_MSPDEINIT_CB_ID :
+ hspi->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hspi);
+ return status;
+}
+
+/**
+ * @brief Unregister an SPI Callback
+ * SPI callback is redirected to the weak predefined callback
+ * @param hspi Pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for the specified SPI.
+ * @param CallbackID ID of the callback to be unregistered
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hspi);
+
+ if (HAL_SPI_STATE_READY == hspi->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_SPI_TX_COMPLETE_CB_ID :
+ hspi->TxCpltCallback = HAL_SPI_TxCpltCallback; /* Legacy weak TxCpltCallback */
+ break;
+
+ case HAL_SPI_RX_COMPLETE_CB_ID :
+ hspi->RxCpltCallback = HAL_SPI_RxCpltCallback; /* Legacy weak RxCpltCallback */
+ break;
+
+ case HAL_SPI_TX_RX_COMPLETE_CB_ID :
+ hspi->TxRxCpltCallback = HAL_SPI_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */
+ break;
+
+ case HAL_SPI_TX_HALF_COMPLETE_CB_ID :
+ hspi->TxHalfCpltCallback = HAL_SPI_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
+ break;
+
+ case HAL_SPI_RX_HALF_COMPLETE_CB_ID :
+ hspi->RxHalfCpltCallback = HAL_SPI_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
+ break;
+
+ case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID :
+ hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */
+ break;
+
+ case HAL_SPI_ERROR_CB_ID :
+ hspi->ErrorCallback = HAL_SPI_ErrorCallback; /* Legacy weak ErrorCallback */
+ break;
+
+ case HAL_SPI_ABORT_CB_ID :
+ hspi->AbortCpltCallback = HAL_SPI_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
+ break;
+
+ case HAL_SPI_MSPINIT_CB_ID :
+ hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */
+ break;
+
+ case HAL_SPI_MSPDEINIT_CB_ID :
+ hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */
+ break;
+
+ default :
+ /* Update the error code */
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_SPI_STATE_RESET == hspi->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_SPI_MSPINIT_CB_ID :
+ hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */
+ break;
+
+ case HAL_SPI_MSPDEINIT_CB_ID :
+ hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */
+ break;
+
+ default :
+ /* Update the error code */
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hspi);
+ return status;
+}
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Exported_Functions_Group2 IO operation functions
+ * @brief Data transfers functions
+ *
+@verbatim
+ ==============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the SPI
+ data transfers.
+
+ [..] The SPI supports master and slave mode :
+
+ (#) There are two modes of transfer:
+ (++) Blocking mode: The communication is performed in polling mode.
+ The HAL status of all data processing is returned by the same function
+ after finishing transfer.
+ (++) No-Blocking mode: The communication is performed using Interrupts
+ or DMA, These APIs return the HAL status.
+ The end of the data processing will be indicated through the
+ dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
+ using DMA mode.
+ The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
+ will be executed respectively at the end of the transmit or Receive process
+ The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
+
+ (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)
+ exist for 1Line (simplex) and 2Lines (full duplex) modes.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Transmit an amount of data in blocking mode.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param pData pointer to data buffer
+ * @param Size amount of data to be sent
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ uint32_t tickstart;
+ HAL_StatusTypeDef errorcode = HAL_OK;
+ uint16_t initial_TxXferCount;
+
+ /* Check Direction parameter */
+ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
+
+ /* Process Locked */
+ __HAL_LOCK(hspi);
+
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+ initial_TxXferCount = Size;
+
+ if (hspi->State != HAL_SPI_STATE_READY)
+ {
+ errorcode = HAL_BUSY;
+ goto error;
+ }
+
+ if ((pData == NULL) || (Size == 0U))
+ {
+ errorcode = HAL_ERROR;
+ goto error;
+ }
+
+ /* Set the transaction information */
+ hspi->State = HAL_SPI_STATE_BUSY_TX;
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ hspi->pTxBuffPtr = (uint8_t *)pData;
+ hspi->TxXferSize = Size;
+ hspi->TxXferCount = Size;
+
+ /*Init field not used in handle to zero */
+ hspi->pRxBuffPtr = (uint8_t *)NULL;
+ hspi->RxXferSize = 0U;
+ hspi->RxXferCount = 0U;
+ hspi->TxISR = NULL;
+ hspi->RxISR = NULL;
+
+ /* Configure communication direction : 1Line */
+ if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
+ {
+ /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
+ __HAL_SPI_DISABLE(hspi);
+ SPI_1LINE_TX(hspi);
+ }
+
+#if (USE_SPI_CRC != 0U)
+ /* Reset CRC Calculation */
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ SPI_RESET_CRC(hspi);
+ }
+#endif /* USE_SPI_CRC */
+
+ /* Check if the SPI is already enabled */
+ if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
+ {
+ /* Enable SPI peripheral */
+ __HAL_SPI_ENABLE(hspi);
+ }
+
+ /* Transmit data in 16 Bit mode */
+ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+ {
+ if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
+ {
+ hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr += sizeof(uint16_t);
+ hspi->TxXferCount--;
+ }
+ /* Transmit data in 16 Bit mode */
+ while (hspi->TxXferCount > 0U)
+ {
+ /* Wait until TXE flag is set to send data */
+ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
+ {
+ hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr += sizeof(uint16_t);
+ hspi->TxXferCount--;
+ }
+ else
+ {
+ /* Timeout management */
+ if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
+ {
+ errorcode = HAL_TIMEOUT;
+ goto error;
+ }
+ }
+ }
+ }
+ /* Transmit data in 8 Bit mode */
+ else
+ {
+ if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
+ {
+ if (hspi->TxXferCount > 1U)
+ {
+ /* write on the data register in packing mode */
+ hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr += sizeof(uint16_t);
+ hspi->TxXferCount -= 2U;
+ }
+ else
+ {
+ *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr ++;
+ hspi->TxXferCount--;
+ }
+ }
+ while (hspi->TxXferCount > 0U)
+ {
+ /* Wait until TXE flag is set to send data */
+ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
+ {
+ if (hspi->TxXferCount > 1U)
+ {
+ /* write on the data register in packing mode */
+ hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr += sizeof(uint16_t);
+ hspi->TxXferCount -= 2U;
+ }
+ else
+ {
+ *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr++;
+ hspi->TxXferCount--;
+ }
+ }
+ else
+ {
+ /* Timeout management */
+ if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
+ {
+ errorcode = HAL_TIMEOUT;
+ goto error;
+ }
+ }
+ }
+ }
+#if (USE_SPI_CRC != 0U)
+ /* Enable CRC Transmission */
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
+ }
+#endif /* USE_SPI_CRC */
+
+ /* Check the end of the transaction */
+ if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
+ {
+ hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
+ }
+
+ /* Clear overrun flag in 2 Lines communication mode because received is not read */
+ if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
+ {
+ __HAL_SPI_CLEAR_OVRFLAG(hspi);
+ }
+
+ if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+ {
+ errorcode = HAL_ERROR;
+ }
+
+error:
+ hspi->State = HAL_SPI_STATE_READY;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+}
+
+/**
+ * @brief Receive an amount of data in blocking mode.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param pData pointer to data buffer
+ * @param Size amount of data to be received
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+#if (USE_SPI_CRC != 0U)
+ __IO uint32_t tmpreg = 0U;
+ __IO uint8_t *ptmpreg8;
+ __IO uint8_t tmpreg8 = 0;
+#endif /* USE_SPI_CRC */
+ uint32_t tickstart;
+ HAL_StatusTypeDef errorcode = HAL_OK;
+
+ if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
+ {
+ hspi->State = HAL_SPI_STATE_BUSY_RX;
+ /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
+ return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout);
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hspi);
+
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+
+ if (hspi->State != HAL_SPI_STATE_READY)
+ {
+ errorcode = HAL_BUSY;
+ goto error;
+ }
+
+ if ((pData == NULL) || (Size == 0U))
+ {
+ errorcode = HAL_ERROR;
+ goto error;
+ }
+
+ /* Set the transaction information */
+ hspi->State = HAL_SPI_STATE_BUSY_RX;
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ hspi->pRxBuffPtr = (uint8_t *)pData;
+ hspi->RxXferSize = Size;
+ hspi->RxXferCount = Size;
+
+ /*Init field not used in handle to zero */
+ hspi->pTxBuffPtr = (uint8_t *)NULL;
+ hspi->TxXferSize = 0U;
+ hspi->TxXferCount = 0U;
+ hspi->RxISR = NULL;
+ hspi->TxISR = NULL;
+
+#if (USE_SPI_CRC != 0U)
+ /* Reset CRC Calculation */
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ SPI_RESET_CRC(hspi);
+ /* this is done to handle the CRCNEXT before the latest data */
+ hspi->RxXferCount--;
+ }
+#endif /* USE_SPI_CRC */
+
+ /* Set the Rx Fifo threshold */
+ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+ {
+ /* Set RX Fifo threshold according the reception data length: 16bit */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+ }
+ else
+ {
+ /* Set RX Fifo threshold according the reception data length: 8bit */
+ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+ }
+
+ /* Configure communication direction: 1Line */
+ if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
+ {
+ /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
+ __HAL_SPI_DISABLE(hspi);
+ SPI_1LINE_RX(hspi);
+ }
+
+ /* Check if the SPI is already enabled */
+ if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
+ {
+ /* Enable SPI peripheral */
+ __HAL_SPI_ENABLE(hspi);
+ }
+
+ /* Receive data in 8 Bit mode */
+ if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT)
+ {
+ /* Transfer loop */
+ while (hspi->RxXferCount > 0U)
+ {
+ /* Check the RXNE flag */
+ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
+ {
+ /* read the received data */
+ (* (uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR;
+ hspi->pRxBuffPtr += sizeof(uint8_t);
+ hspi->RxXferCount--;
+ }
+ else
+ {
+ /* Timeout management */
+ if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
+ {
+ errorcode = HAL_TIMEOUT;
+ goto error;
+ }
+ }
+ }
+ }
+ else
+ {
+ /* Transfer loop */
+ while (hspi->RxXferCount > 0U)
+ {
+ /* Check the RXNE flag */
+ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
+ {
+ *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
+ hspi->pRxBuffPtr += sizeof(uint16_t);
+ hspi->RxXferCount--;
+ }
+ else
+ {
+ /* Timeout management */
+ if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
+ {
+ errorcode = HAL_TIMEOUT;
+ goto error;
+ }
+ }
+ }
+ }
+
+#if (USE_SPI_CRC != 0U)
+ /* Handle the CRC Transmission */
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ /* freeze the CRC before the latest data */
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
+
+ /* Read the latest data */
+ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
+ {
+ /* the latest data has not been received */
+ errorcode = HAL_TIMEOUT;
+ goto error;
+ }
+
+ /* Receive last data in 16 Bit mode */
+ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+ {
+ *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
+ }
+ /* Receive last data in 8 Bit mode */
+ else
+ {
+ (*(uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR;
+ }
+
+ /* Wait the CRC data */
+ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
+ errorcode = HAL_TIMEOUT;
+ goto error;
+ }
+
+ /* Read CRC to Flush DR and RXNE flag */
+ if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
+ {
+ /* Read 16bit CRC */
+ tmpreg = READ_REG(hspi->Instance->DR);
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
+ }
+ else
+ {
+ /* Initialize the 8bit temporary pointer */
+ ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
+ /* Read 8bit CRC */
+ tmpreg8 = *ptmpreg8;
+ /* To avoid GCC warning */
+ UNUSED(tmpreg8);
+
+ if ((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
+ {
+ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
+ {
+ /* Error on the CRC reception */
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
+ errorcode = HAL_TIMEOUT;
+ goto error;
+ }
+ /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */
+ tmpreg8 = *ptmpreg8;
+ /* To avoid GCC warning */
+ UNUSED(tmpreg8);
+ }
+ }
+ }
+#endif /* USE_SPI_CRC */
+
+ /* Check the end of the transaction */
+ if (SPI_EndRxTransaction(hspi, Timeout, tickstart) != HAL_OK)
+ {
+ hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
+ }
+
+#if (USE_SPI_CRC != 0U)
+ /* Check if CRC error occurred */
+ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
+ __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
+ }
+#endif /* USE_SPI_CRC */
+
+ if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+ {
+ errorcode = HAL_ERROR;
+ }
+
+error :
+ hspi->State = HAL_SPI_STATE_READY;
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+}
+
+/**
+ * @brief Transmit and Receive an amount of data in blocking mode.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param pTxData pointer to transmission data buffer
+ * @param pRxData pointer to reception data buffer
+ * @param Size amount of data to be sent and received
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,
+ uint32_t Timeout)
+{
+ uint16_t initial_TxXferCount;
+ uint16_t initial_RxXferCount;
+ uint32_t tmp_mode;
+ HAL_SPI_StateTypeDef tmp_state;
+ uint32_t tickstart;
+#if (USE_SPI_CRC != 0U)
+ __IO uint32_t tmpreg = 0U;
+ uint32_t spi_cr1;
+ uint32_t spi_cr2;
+ __IO uint8_t *ptmpreg8;
+ __IO uint8_t tmpreg8 = 0;
+#endif /* USE_SPI_CRC */
+
+ /* Variable used to alternate Rx and Tx during transfer */
+ uint32_t txallowed = 1U;
+ HAL_StatusTypeDef errorcode = HAL_OK;
+
+ /* Check Direction parameter */
+ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
+
+ /* Process Locked */
+ __HAL_LOCK(hspi);
+
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+
+ /* Init temporary variables */
+ tmp_state = hspi->State;
+ tmp_mode = hspi->Init.Mode;
+ initial_TxXferCount = Size;
+ initial_RxXferCount = Size;
+#if (USE_SPI_CRC != 0U)
+ spi_cr1 = READ_REG(hspi->Instance->CR1);
+ spi_cr2 = READ_REG(hspi->Instance->CR2);
+#endif /* USE_SPI_CRC */
+
+ if (!((tmp_state == HAL_SPI_STATE_READY) || \
+ ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
+ {
+ errorcode = HAL_BUSY;
+ goto error;
+ }
+
+ if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
+ {
+ errorcode = HAL_ERROR;
+ goto error;
+ }
+
+ /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
+ if (hspi->State != HAL_SPI_STATE_BUSY_RX)
+ {
+ hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
+ }
+
+ /* Set the transaction information */
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ hspi->pRxBuffPtr = (uint8_t *)pRxData;
+ hspi->RxXferCount = Size;
+ hspi->RxXferSize = Size;
+ hspi->pTxBuffPtr = (uint8_t *)pTxData;
+ hspi->TxXferCount = Size;
+ hspi->TxXferSize = Size;
+
+ /*Init field not used in handle to zero */
+ hspi->RxISR = NULL;
+ hspi->TxISR = NULL;
+
+#if (USE_SPI_CRC != 0U)
+ /* Reset CRC Calculation */
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ SPI_RESET_CRC(hspi);
+ }
+#endif /* USE_SPI_CRC */
+
+ /* Set the Rx Fifo threshold */
+ if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (initial_RxXferCount > 1U))
+ {
+ /* Set fiforxthreshold according the reception data length: 16bit */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+ }
+ else
+ {
+ /* Set fiforxthreshold according the reception data length: 8bit */
+ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+ }
+
+ /* Check if the SPI is already enabled */
+ if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
+ {
+ /* Enable SPI peripheral */
+ __HAL_SPI_ENABLE(hspi);
+ }
+
+ /* Transmit and Receive data in 16 Bit mode */
+ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+ {
+ if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
+ {
+ hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr += sizeof(uint16_t);
+ hspi->TxXferCount--;
+ }
+ while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
+ {
+ /* Check TXE flag */
+ if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U))
+ {
+ hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr += sizeof(uint16_t);
+ hspi->TxXferCount--;
+ /* Next Data is a reception (Rx). Tx not allowed */
+ txallowed = 0U;
+
+#if (USE_SPI_CRC != 0U)
+ /* Enable CRC Transmission */
+ if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
+ {
+ /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */
+ if ((READ_BIT(spi_cr1, SPI_CR1_MSTR) == 0U) && (READ_BIT(spi_cr2, SPI_CR2_NSSP) == SPI_CR2_NSSP))
+ {
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM);
+ }
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
+ }
+#endif /* USE_SPI_CRC */
+ }
+
+ /* Check RXNE flag */
+ if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U))
+ {
+ *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
+ hspi->pRxBuffPtr += sizeof(uint16_t);
+ hspi->RxXferCount--;
+ /* Next Data is a Transmission (Tx). Tx is allowed */
+ txallowed = 1U;
+ }
+ if (((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY))
+ {
+ errorcode = HAL_TIMEOUT;
+ goto error;
+ }
+ }
+ }
+ /* Transmit and Receive data in 8 Bit mode */
+ else
+ {
+ if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
+ {
+ if (hspi->TxXferCount > 1U)
+ {
+ hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr += sizeof(uint16_t);
+ hspi->TxXferCount -= 2U;
+ }
+ else
+ {
+ *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr++;
+ hspi->TxXferCount--;
+ }
+ }
+ while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
+ {
+ /* Check TXE flag */
+ if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U))
+ {
+ if (hspi->TxXferCount > 1U)
+ {
+ hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr += sizeof(uint16_t);
+ hspi->TxXferCount -= 2U;
+ }
+ else
+ {
+ *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr++;
+ hspi->TxXferCount--;
+ }
+ /* Next Data is a reception (Rx). Tx not allowed */
+ txallowed = 0U;
+
+#if (USE_SPI_CRC != 0U)
+ /* Enable CRC Transmission */
+ if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
+ {
+ /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */
+ if ((READ_BIT(spi_cr1, SPI_CR1_MSTR) == 0U) && (READ_BIT(spi_cr2, SPI_CR2_NSSP) == SPI_CR2_NSSP))
+ {
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM);
+ }
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
+ }
+#endif /* USE_SPI_CRC */
+ }
+
+ /* Wait until RXNE flag is reset */
+ if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U))
+ {
+ if (hspi->RxXferCount > 1U)
+ {
+ *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
+ hspi->pRxBuffPtr += sizeof(uint16_t);
+ hspi->RxXferCount -= 2U;
+ if (hspi->RxXferCount <= 1U)
+ {
+ /* Set RX Fifo threshold before to switch on 8 bit data size */
+ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+ }
+ }
+ else
+ {
+ (*(uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR;
+ hspi->pRxBuffPtr++;
+ hspi->RxXferCount--;
+ }
+ /* Next Data is a Transmission (Tx). Tx is allowed */
+ txallowed = 1U;
+ }
+ if ((((HAL_GetTick() - tickstart) >= Timeout) && ((Timeout != HAL_MAX_DELAY))) || (Timeout == 0U))
+ {
+ errorcode = HAL_TIMEOUT;
+ goto error;
+ }
+ }
+ }
+
+#if (USE_SPI_CRC != 0U)
+ /* Read CRC from DR to close CRC calculation process */
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ /* Wait until TXE flag */
+ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
+ {
+ /* Error on the CRC reception */
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
+ errorcode = HAL_TIMEOUT;
+ goto error;
+ }
+ /* Read CRC */
+ if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
+ {
+ /* Read 16bit CRC */
+ tmpreg = READ_REG(hspi->Instance->DR);
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
+ }
+ else
+ {
+ /* Initialize the 8bit temporary pointer */
+ ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
+ /* Read 8bit CRC */
+ tmpreg8 = *ptmpreg8;
+ /* To avoid GCC warning */
+ UNUSED(tmpreg8);
+
+ if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
+ {
+ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
+ {
+ /* Error on the CRC reception */
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
+ errorcode = HAL_TIMEOUT;
+ goto error;
+ }
+ /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */
+ tmpreg8 = *ptmpreg8;
+ /* To avoid GCC warning */
+ UNUSED(tmpreg8);
+ }
+ }
+ }
+
+ /* Check if CRC error occurred */
+ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
+ /* Clear CRC Flag */
+ __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
+
+ errorcode = HAL_ERROR;
+ }
+#endif /* USE_SPI_CRC */
+
+ /* Check the end of the transaction */
+ if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
+ {
+ errorcode = HAL_ERROR;
+ hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
+ }
+
+error :
+ hspi->State = HAL_SPI_STATE_READY;
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+}
+
+/**
+ * @brief Transmit an amount of data in non-blocking mode with Interrupt.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param pData pointer to data buffer
+ * @param Size amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
+{
+ HAL_StatusTypeDef errorcode = HAL_OK;
+
+ /* Check Direction parameter */
+ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
+
+ /* Process Locked */
+ __HAL_LOCK(hspi);
+
+ if ((pData == NULL) || (Size == 0U))
+ {
+ errorcode = HAL_ERROR;
+ goto error;
+ }
+
+ if (hspi->State != HAL_SPI_STATE_READY)
+ {
+ errorcode = HAL_BUSY;
+ goto error;
+ }
+
+ /* Set the transaction information */
+ hspi->State = HAL_SPI_STATE_BUSY_TX;
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ hspi->pTxBuffPtr = (uint8_t *)pData;
+ hspi->TxXferSize = Size;
+ hspi->TxXferCount = Size;
+
+ /* Init field not used in handle to zero */
+ hspi->pRxBuffPtr = (uint8_t *)NULL;
+ hspi->RxXferSize = 0U;
+ hspi->RxXferCount = 0U;
+ hspi->RxISR = NULL;
+
+ /* Set the function for IT treatment */
+ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+ {
+ hspi->TxISR = SPI_TxISR_16BIT;
+ }
+ else
+ {
+ hspi->TxISR = SPI_TxISR_8BIT;
+ }
+
+ /* Configure communication direction : 1Line */
+ if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
+ {
+ /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
+ __HAL_SPI_DISABLE(hspi);
+ SPI_1LINE_TX(hspi);
+ }
+
+#if (USE_SPI_CRC != 0U)
+ /* Reset CRC Calculation */
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ SPI_RESET_CRC(hspi);
+ }
+#endif /* USE_SPI_CRC */
+
+ /* Enable TXE and ERR interrupt */
+ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
+
+
+ /* Check if the SPI is already enabled */
+ if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
+ {
+ /* Enable SPI peripheral */
+ __HAL_SPI_ENABLE(hspi);
+ }
+
+error :
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+}
+
+/**
+ * @brief Receive an amount of data in non-blocking mode with Interrupt.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param pData pointer to data buffer
+ * @param Size amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
+{
+ HAL_StatusTypeDef errorcode = HAL_OK;
+
+ if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
+ {
+ hspi->State = HAL_SPI_STATE_BUSY_RX;
+ /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
+ return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size);
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hspi);
+
+ if (hspi->State != HAL_SPI_STATE_READY)
+ {
+ errorcode = HAL_BUSY;
+ goto error;
+ }
+
+ if ((pData == NULL) || (Size == 0U))
+ {
+ errorcode = HAL_ERROR;
+ goto error;
+ }
+
+ /* Set the transaction information */
+ hspi->State = HAL_SPI_STATE_BUSY_RX;
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ hspi->pRxBuffPtr = (uint8_t *)pData;
+ hspi->RxXferSize = Size;
+ hspi->RxXferCount = Size;
+
+ /* Init field not used in handle to zero */
+ hspi->pTxBuffPtr = (uint8_t *)NULL;
+ hspi->TxXferSize = 0U;
+ hspi->TxXferCount = 0U;
+ hspi->TxISR = NULL;
+
+ /* Check the data size to adapt Rx threshold and the set the function for IT treatment */
+ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+ {
+ /* Set RX Fifo threshold according the reception data length: 16 bit */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+ hspi->RxISR = SPI_RxISR_16BIT;
+ }
+ else
+ {
+ /* Set RX Fifo threshold according the reception data length: 8 bit */
+ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+ hspi->RxISR = SPI_RxISR_8BIT;
+ }
+
+ /* Configure communication direction : 1Line */
+ if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
+ {
+ /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
+ __HAL_SPI_DISABLE(hspi);
+ SPI_1LINE_RX(hspi);
+ }
+
+#if (USE_SPI_CRC != 0U)
+ /* Reset CRC Calculation */
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ hspi->CRCSize = 1U;
+ if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
+ {
+ hspi->CRCSize = 2U;
+ }
+ SPI_RESET_CRC(hspi);
+ }
+ else
+ {
+ hspi->CRCSize = 0U;
+ }
+#endif /* USE_SPI_CRC */
+
+ /* Enable TXE and ERR interrupt */
+ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
+
+ /* Note : The SPI must be enabled after unlocking current process
+ to avoid the risk of SPI interrupt handle execution before current
+ process unlock */
+
+ /* Check if the SPI is already enabled */
+ if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
+ {
+ /* Enable SPI peripheral */
+ __HAL_SPI_ENABLE(hspi);
+ }
+
+error :
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+}
+
+/**
+ * @brief Transmit and Receive an amount of data in non-blocking mode with Interrupt.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param pTxData pointer to transmission data buffer
+ * @param pRxData pointer to reception data buffer
+ * @param Size amount of data to be sent and received
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
+{
+ uint32_t tmp_mode;
+ HAL_SPI_StateTypeDef tmp_state;
+ HAL_StatusTypeDef errorcode = HAL_OK;
+
+ /* Check Direction parameter */
+ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
+
+ /* Process locked */
+ __HAL_LOCK(hspi);
+
+ /* Init temporary variables */
+ tmp_state = hspi->State;
+ tmp_mode = hspi->Init.Mode;
+
+ if (!((tmp_state == HAL_SPI_STATE_READY) || \
+ ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
+ {
+ errorcode = HAL_BUSY;
+ goto error;
+ }
+
+ if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
+ {
+ errorcode = HAL_ERROR;
+ goto error;
+ }
+
+ /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
+ if (hspi->State != HAL_SPI_STATE_BUSY_RX)
+ {
+ hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
+ }
+
+ /* Set the transaction information */
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ hspi->pTxBuffPtr = (uint8_t *)pTxData;
+ hspi->TxXferSize = Size;
+ hspi->TxXferCount = Size;
+ hspi->pRxBuffPtr = (uint8_t *)pRxData;
+ hspi->RxXferSize = Size;
+ hspi->RxXferCount = Size;
+
+ /* Set the function for IT treatment */
+ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+ {
+ hspi->RxISR = SPI_2linesRxISR_16BIT;
+ hspi->TxISR = SPI_2linesTxISR_16BIT;
+ }
+ else
+ {
+ hspi->RxISR = SPI_2linesRxISR_8BIT;
+ hspi->TxISR = SPI_2linesTxISR_8BIT;
+ }
+
+#if (USE_SPI_CRC != 0U)
+ /* Reset CRC Calculation */
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ hspi->CRCSize = 1U;
+ if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
+ {
+ hspi->CRCSize = 2U;
+ }
+ SPI_RESET_CRC(hspi);
+ }
+ else
+ {
+ hspi->CRCSize = 0U;
+ }
+#endif /* USE_SPI_CRC */
+
+ /* Check if packing mode is enabled and if there is more than 2 data to receive */
+ if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (Size >= 2U))
+ {
+ /* Set RX Fifo threshold according the reception data length: 16 bit */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+ }
+ else
+ {
+ /* Set RX Fifo threshold according the reception data length: 8 bit */
+ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+ }
+
+ /* Enable TXE, RXNE and ERR interrupt */
+ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
+
+ /* Check if the SPI is already enabled */
+ if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
+ {
+ /* Enable SPI peripheral */
+ __HAL_SPI_ENABLE(hspi);
+ }
+
+error :
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+}
+
+/**
+ * @brief Transmit an amount of data in non-blocking mode with DMA.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param pData pointer to data buffer
+ * @param Size amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
+{
+ HAL_StatusTypeDef errorcode = HAL_OK;
+
+ /* Check tx dma handle */
+ assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
+
+ /* Check Direction parameter */
+ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
+
+ /* Process Locked */
+ __HAL_LOCK(hspi);
+
+ if (hspi->State != HAL_SPI_STATE_READY)
+ {
+ errorcode = HAL_BUSY;
+ goto error;
+ }
+
+ if ((pData == NULL) || (Size == 0U))
+ {
+ errorcode = HAL_ERROR;
+ goto error;
+ }
+
+ /* Set the transaction information */
+ hspi->State = HAL_SPI_STATE_BUSY_TX;
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ hspi->pTxBuffPtr = (uint8_t *)pData;
+ hspi->TxXferSize = Size;
+ hspi->TxXferCount = Size;
+
+ /* Init field not used in handle to zero */
+ hspi->pRxBuffPtr = (uint8_t *)NULL;
+ hspi->TxISR = NULL;
+ hspi->RxISR = NULL;
+ hspi->RxXferSize = 0U;
+ hspi->RxXferCount = 0U;
+
+ /* Configure communication direction : 1Line */
+ if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
+ {
+ /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
+ __HAL_SPI_DISABLE(hspi);
+ SPI_1LINE_TX(hspi);
+ }
+
+#if (USE_SPI_CRC != 0U)
+ /* Reset CRC Calculation */
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ SPI_RESET_CRC(hspi);
+ }
+#endif /* USE_SPI_CRC */
+
+ /* Set the SPI TxDMA Half transfer complete callback */
+ hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;
+
+ /* Set the SPI TxDMA transfer complete callback */
+ hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;
+
+ /* Set the DMA error callback */
+ hspi->hdmatx->XferErrorCallback = SPI_DMAError;
+
+ /* Set the DMA AbortCpltCallback */
+ hspi->hdmatx->XferAbortCallback = NULL;
+
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
+ /* Packing mode is enabled only if the DMA setting is HALWORD */
+ if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
+ {
+ /* Check the even/odd of the data size + crc if enabled */
+ if ((hspi->TxXferCount & 0x1U) == 0U)
+ {
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
+ hspi->TxXferCount = (hspi->TxXferCount >> 1U);
+ }
+ else
+ {
+ SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
+ hspi->TxXferCount = (hspi->TxXferCount >> 1U) + 1U;
+ }
+ }
+
+ /* Enable the Tx DMA Stream/Channel */
+ if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR,
+ hspi->TxXferCount))
+ {
+ /* Update SPI error code */
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
+ errorcode = HAL_ERROR;
+
+ hspi->State = HAL_SPI_STATE_READY;
+ goto error;
+ }
+
+ /* Check if the SPI is already enabled */
+ if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
+ {
+ /* Enable SPI peripheral */
+ __HAL_SPI_ENABLE(hspi);
+ }
+
+ /* Enable the SPI Error Interrupt Bit */
+ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
+
+ /* Enable Tx DMA Request */
+ SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
+
+error :
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+}
+
+/**
+ * @brief Receive an amount of data in non-blocking mode with DMA.
+ * @note In case of MASTER mode and SPI_DIRECTION_2LINES direction, hdmatx shall be defined.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param pData pointer to data buffer
+ * @note When the CRC feature is enabled the pData Length must be Size + 1.
+ * @param Size amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
+{
+ HAL_StatusTypeDef errorcode = HAL_OK;
+
+ /* Check rx dma handle */
+ assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));
+
+ if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
+ {
+ hspi->State = HAL_SPI_STATE_BUSY_RX;
+
+ /* Check tx dma handle */
+ assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
+
+ /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
+ return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size);
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hspi);
+
+ if (hspi->State != HAL_SPI_STATE_READY)
+ {
+ errorcode = HAL_BUSY;
+ goto error;
+ }
+
+ if ((pData == NULL) || (Size == 0U))
+ {
+ errorcode = HAL_ERROR;
+ goto error;
+ }
+
+ /* Set the transaction information */
+ hspi->State = HAL_SPI_STATE_BUSY_RX;
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ hspi->pRxBuffPtr = (uint8_t *)pData;
+ hspi->RxXferSize = Size;
+ hspi->RxXferCount = Size;
+
+ /*Init field not used in handle to zero */
+ hspi->RxISR = NULL;
+ hspi->TxISR = NULL;
+ hspi->TxXferSize = 0U;
+ hspi->TxXferCount = 0U;
+
+ /* Configure communication direction : 1Line */
+ if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
+ {
+ /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
+ __HAL_SPI_DISABLE(hspi);
+ SPI_1LINE_RX(hspi);
+ }
+
+#if (USE_SPI_CRC != 0U)
+ /* Reset CRC Calculation */
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ SPI_RESET_CRC(hspi);
+ }
+#endif /* USE_SPI_CRC */
+
+
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
+ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+ {
+ /* Set RX Fifo threshold according the reception data length: 16bit */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+ }
+ else
+ {
+ /* Set RX Fifo threshold according the reception data length: 8bit */
+ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+
+ if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
+ {
+ /* Set RX Fifo threshold according the reception data length: 16bit */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+
+ if ((hspi->RxXferCount & 0x1U) == 0x0U)
+ {
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
+ hspi->RxXferCount = hspi->RxXferCount >> 1U;
+ }
+ else
+ {
+ SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
+ hspi->RxXferCount = (hspi->RxXferCount >> 1U) + 1U;
+ }
+ }
+ }
+
+ /* Set the SPI RxDMA Half transfer complete callback */
+ hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
+
+ /* Set the SPI Rx DMA transfer complete callback */
+ hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
+
+ /* Set the DMA error callback */
+ hspi->hdmarx->XferErrorCallback = SPI_DMAError;
+
+ /* Set the DMA AbortCpltCallback */
+ hspi->hdmarx->XferAbortCallback = NULL;
+
+ /* Enable the Rx DMA Stream/Channel */
+ if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr,
+ hspi->RxXferCount))
+ {
+ /* Update SPI error code */
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
+ errorcode = HAL_ERROR;
+
+ hspi->State = HAL_SPI_STATE_READY;
+ goto error;
+ }
+
+ /* Check if the SPI is already enabled */
+ if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
+ {
+ /* Enable SPI peripheral */
+ __HAL_SPI_ENABLE(hspi);
+ }
+
+ /* Enable the SPI Error Interrupt Bit */
+ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
+
+ /* Enable Rx DMA Request */
+ SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
+
+error:
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+}
+
+/**
+ * @brief Transmit and Receive an amount of data in non-blocking mode with DMA.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param pTxData pointer to transmission data buffer
+ * @param pRxData pointer to reception data buffer
+ * @note When the CRC feature is enabled the pRxData Length must be Size + 1
+ * @param Size amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
+ uint16_t Size)
+{
+ uint32_t tmp_mode;
+ HAL_SPI_StateTypeDef tmp_state;
+ HAL_StatusTypeDef errorcode = HAL_OK;
+
+ /* Check rx & tx dma handles */
+ assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));
+ assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
+
+ /* Check Direction parameter */
+ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
+
+ /* Process locked */
+ __HAL_LOCK(hspi);
+
+ /* Init temporary variables */
+ tmp_state = hspi->State;
+ tmp_mode = hspi->Init.Mode;
+
+ if (!((tmp_state == HAL_SPI_STATE_READY) ||
+ ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
+ {
+ errorcode = HAL_BUSY;
+ goto error;
+ }
+
+ if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
+ {
+ errorcode = HAL_ERROR;
+ goto error;
+ }
+
+ /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
+ if (hspi->State != HAL_SPI_STATE_BUSY_RX)
+ {
+ hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
+ }
+
+ /* Set the transaction information */
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ hspi->pTxBuffPtr = (uint8_t *)pTxData;
+ hspi->TxXferSize = Size;
+ hspi->TxXferCount = Size;
+ hspi->pRxBuffPtr = (uint8_t *)pRxData;
+ hspi->RxXferSize = Size;
+ hspi->RxXferCount = Size;
+
+ /* Init field not used in handle to zero */
+ hspi->RxISR = NULL;
+ hspi->TxISR = NULL;
+
+#if (USE_SPI_CRC != 0U)
+ /* Reset CRC Calculation */
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ SPI_RESET_CRC(hspi);
+ }
+#endif /* USE_SPI_CRC */
+
+ /* Reset the threshold bit */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX | SPI_CR2_LDMARX);
+
+ /* The packing mode management is enabled by the DMA settings according the spi data size */
+ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+ {
+ /* Set fiforxthreshold according the reception data length: 16bit */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+ }
+ else
+ {
+ /* Set RX Fifo threshold according the reception data length: 8bit */
+ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+
+ if (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
+ {
+ if ((hspi->TxXferSize & 0x1U) == 0x0U)
+ {
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
+ hspi->TxXferCount = hspi->TxXferCount >> 1U;
+ }
+ else
+ {
+ SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
+ hspi->TxXferCount = (hspi->TxXferCount >> 1U) + 1U;
+ }
+ }
+
+ if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
+ {
+ /* Set RX Fifo threshold according the reception data length: 16bit */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+
+ if ((hspi->RxXferCount & 0x1U) == 0x0U)
+ {
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
+ hspi->RxXferCount = hspi->RxXferCount >> 1U;
+ }
+ else
+ {
+ SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
+ hspi->RxXferCount = (hspi->RxXferCount >> 1U) + 1U;
+ }
+ }
+ }
+
+ /* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */
+ if (hspi->State == HAL_SPI_STATE_BUSY_RX)
+ {
+ /* Set the SPI Rx DMA Half transfer complete callback */
+ hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
+ hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
+ }
+ else
+ {
+ /* Set the SPI Tx/Rx DMA Half transfer complete callback */
+ hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;
+ hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt;
+ }
+
+ /* Set the DMA error callback */
+ hspi->hdmarx->XferErrorCallback = SPI_DMAError;
+
+ /* Set the DMA AbortCpltCallback */
+ hspi->hdmarx->XferAbortCallback = NULL;
+
+ /* Enable the Rx DMA Stream/Channel */
+ if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr,
+ hspi->RxXferCount))
+ {
+ /* Update SPI error code */
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
+ errorcode = HAL_ERROR;
+
+ hspi->State = HAL_SPI_STATE_READY;
+ goto error;
+ }
+
+ /* Enable Rx DMA Request */
+ SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
+
+ /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing
+ is performed in DMA reception complete callback */
+ hspi->hdmatx->XferHalfCpltCallback = NULL;
+ hspi->hdmatx->XferCpltCallback = NULL;
+ hspi->hdmatx->XferErrorCallback = NULL;
+ hspi->hdmatx->XferAbortCallback = NULL;
+
+ /* Enable the Tx DMA Stream/Channel */
+ if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR,
+ hspi->TxXferCount))
+ {
+ /* Update SPI error code */
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
+ errorcode = HAL_ERROR;
+
+ hspi->State = HAL_SPI_STATE_READY;
+ goto error;
+ }
+
+ /* Check if the SPI is already enabled */
+ if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
+ {
+ /* Enable SPI peripheral */
+ __HAL_SPI_ENABLE(hspi);
+ }
+ /* Enable the SPI Error Interrupt Bit */
+ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
+
+ /* Enable Tx DMA Request */
+ SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
+
+error :
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+}
+
+/**
+ * @brief Abort ongoing transfer (blocking mode).
+ * @param hspi SPI handle.
+ * @note This procedure could be used for aborting any ongoing transfer (Tx and Rx),
+ * started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable SPI Interrupts (depending of transfer direction)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi)
+{
+ HAL_StatusTypeDef errorcode;
+ __IO uint32_t count;
+ __IO uint32_t resetcount;
+
+ /* Initialized local variable */
+ errorcode = HAL_OK;
+ resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
+ count = resetcount;
+
+ /* Clear ERRIE interrupt to avoid error interrupts generation during Abort procedure */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
+
+ /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
+ if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
+ {
+ hspi->TxISR = SPI_AbortTx_ISR;
+ /* Wait HAL_SPI_STATE_ABORT state */
+ do
+ {
+ if (count == 0U)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
+ break;
+ }
+ count--;
+ } while (hspi->State != HAL_SPI_STATE_ABORT);
+ /* Reset Timeout Counter */
+ count = resetcount;
+ }
+
+ if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
+ {
+ hspi->RxISR = SPI_AbortRx_ISR;
+ /* Wait HAL_SPI_STATE_ABORT state */
+ do
+ {
+ if (count == 0U)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
+ break;
+ }
+ count--;
+ } while (hspi->State != HAL_SPI_STATE_ABORT);
+ /* Reset Timeout Counter */
+ count = resetcount;
+ }
+
+ /* Disable the SPI DMA Tx request if enabled */
+ if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
+ {
+ /* Abort the SPI DMA Tx Stream/Channel : use blocking DMA Abort API (no callback) */
+ if (hspi->hdmatx != NULL)
+ {
+ /* Set the SPI DMA Abort callback :
+ will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */
+ hspi->hdmatx->XferAbortCallback = NULL;
+
+ /* Abort DMA Tx Handle linked to SPI Peripheral */
+ if (HAL_DMA_Abort(hspi->hdmatx) != HAL_OK)
+ {
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ }
+
+ /* Disable Tx DMA Request */
+ CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN));
+
+ if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
+ {
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ }
+
+ /* Disable SPI Peripheral */
+ __HAL_SPI_DISABLE(hspi);
+
+ /* Empty the FRLVL fifo */
+ if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
+ {
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ }
+ }
+ }
+
+ /* Disable the SPI DMA Rx request if enabled */
+ if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
+ {
+ /* Abort the SPI DMA Rx Stream/Channel : use blocking DMA Abort API (no callback) */
+ if (hspi->hdmarx != NULL)
+ {
+ /* Set the SPI DMA Abort callback :
+ will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */
+ hspi->hdmarx->XferAbortCallback = NULL;
+
+ /* Abort DMA Rx Handle linked to SPI Peripheral */
+ if (HAL_DMA_Abort(hspi->hdmarx) != HAL_OK)
+ {
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ }
+
+ /* Disable peripheral */
+ __HAL_SPI_DISABLE(hspi);
+
+ /* Control the BSY flag */
+ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
+ {
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ }
+
+ /* Empty the FRLVL fifo */
+ if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
+ {
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ }
+
+ /* Disable Rx DMA Request */
+ CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXDMAEN));
+ }
+ }
+ /* Reset Tx and Rx transfer counters */
+ hspi->RxXferCount = 0U;
+ hspi->TxXferCount = 0U;
+
+ /* Check error during Abort procedure */
+ if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)
+ {
+ /* return HAL_Error in case of error during Abort procedure */
+ errorcode = HAL_ERROR;
+ }
+ else
+ {
+ /* Reset errorCode */
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ }
+
+ /* Clear the Error flags in the SR register */
+ __HAL_SPI_CLEAR_OVRFLAG(hspi);
+ __HAL_SPI_CLEAR_FREFLAG(hspi);
+
+ /* Restore hspi->state to ready */
+ hspi->State = HAL_SPI_STATE_READY;
+
+ return errorcode;
+}
+
+/**
+ * @brief Abort ongoing transfer (Interrupt mode).
+ * @param hspi SPI handle.
+ * @note This procedure could be used for aborting any ongoing transfer (Tx and Rx),
+ * started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable SPI Interrupts (depending of transfer direction)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * - At abort completion, call user abort complete callback
+ * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
+ * considered as completed only when user abort complete callback is executed (not when exiting function).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi)
+{
+ HAL_StatusTypeDef errorcode;
+ uint32_t abortcplt ;
+ __IO uint32_t count;
+ __IO uint32_t resetcount;
+
+ /* Initialized local variable */
+ errorcode = HAL_OK;
+ abortcplt = 1U;
+ resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
+ count = resetcount;
+
+ /* Clear ERRIE interrupt to avoid error interrupts generation during Abort procedure */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
+
+ /* Change Rx and Tx Irq Handler to Disable TXEIE, RXNEIE and ERRIE interrupts */
+ if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
+ {
+ hspi->TxISR = SPI_AbortTx_ISR;
+ /* Wait HAL_SPI_STATE_ABORT state */
+ do
+ {
+ if (count == 0U)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
+ break;
+ }
+ count--;
+ } while (hspi->State != HAL_SPI_STATE_ABORT);
+ /* Reset Timeout Counter */
+ count = resetcount;
+ }
+
+ if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
+ {
+ hspi->RxISR = SPI_AbortRx_ISR;
+ /* Wait HAL_SPI_STATE_ABORT state */
+ do
+ {
+ if (count == 0U)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
+ break;
+ }
+ count--;
+ } while (hspi->State != HAL_SPI_STATE_ABORT);
+ /* Reset Timeout Counter */
+ count = resetcount;
+ }
+
+ /* If DMA Tx and/or DMA Rx Handles are associated to SPI Handle, DMA Abort complete callbacks should be initialised
+ before any call to DMA Abort functions */
+ /* DMA Tx Handle is valid */
+ if (hspi->hdmatx != NULL)
+ {
+ /* Set DMA Abort Complete callback if UART DMA Tx request if enabled.
+ Otherwise, set it to NULL */
+ if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
+ {
+ hspi->hdmatx->XferAbortCallback = SPI_DMATxAbortCallback;
+ }
+ else
+ {
+ hspi->hdmatx->XferAbortCallback = NULL;
+ }
+ }
+ /* DMA Rx Handle is valid */
+ if (hspi->hdmarx != NULL)
+ {
+ /* Set DMA Abort Complete callback if UART DMA Rx request if enabled.
+ Otherwise, set it to NULL */
+ if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
+ {
+ hspi->hdmarx->XferAbortCallback = SPI_DMARxAbortCallback;
+ }
+ else
+ {
+ hspi->hdmarx->XferAbortCallback = NULL;
+ }
+ }
+
+ /* Disable the SPI DMA Tx request if enabled */
+ if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
+ {
+ /* Abort the SPI DMA Tx Stream/Channel */
+ if (hspi->hdmatx != NULL)
+ {
+ /* Abort DMA Tx Handle linked to SPI Peripheral */
+ if (HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK)
+ {
+ hspi->hdmatx->XferAbortCallback = NULL;
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ }
+ else
+ {
+ abortcplt = 0U;
+ }
+ }
+ }
+ /* Disable the SPI DMA Rx request if enabled */
+ if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
+ {
+ /* Abort the SPI DMA Rx Stream/Channel */
+ if (hspi->hdmarx != NULL)
+ {
+ /* Abort DMA Rx Handle linked to SPI Peripheral */
+ if (HAL_DMA_Abort_IT(hspi->hdmarx) != HAL_OK)
+ {
+ hspi->hdmarx->XferAbortCallback = NULL;
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ }
+ else
+ {
+ abortcplt = 0U;
+ }
+ }
+ }
+
+ if (abortcplt == 1U)
+ {
+ /* Reset Tx and Rx transfer counters */
+ hspi->RxXferCount = 0U;
+ hspi->TxXferCount = 0U;
+
+ /* Check error during Abort procedure */
+ if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)
+ {
+ /* return HAL_Error in case of error during Abort procedure */
+ errorcode = HAL_ERROR;
+ }
+ else
+ {
+ /* Reset errorCode */
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ }
+
+ /* Clear the Error flags in the SR register */
+ __HAL_SPI_CLEAR_OVRFLAG(hspi);
+ __HAL_SPI_CLEAR_FREFLAG(hspi);
+
+ /* Restore hspi->State to Ready */
+ hspi->State = HAL_SPI_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->AbortCpltCallback(hspi);
+#else
+ HAL_SPI_AbortCpltCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+ }
+
+ return errorcode;
+}
+
+/**
+ * @brief Pause the DMA Transfer.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for the specified SPI module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi)
+{
+ /* Process Locked */
+ __HAL_LOCK(hspi);
+
+ /* Disable the SPI DMA Tx & Rx requests */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Resume the DMA Transfer.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for the specified SPI module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)
+{
+ /* Process Locked */
+ __HAL_LOCK(hspi);
+
+ /* Enable the SPI DMA Tx & Rx requests */
+ SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Stop the DMA Transfer.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for the specified SPI module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
+{
+ HAL_StatusTypeDef errorcode = HAL_OK;
+ /* The Lock is not implemented on this API to allow the user application
+ to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback():
+ when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
+ and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback()
+ */
+
+ /* Abort the SPI DMA tx Stream/Channel */
+ if (hspi->hdmatx != NULL)
+ {
+ if (HAL_OK != HAL_DMA_Abort(hspi->hdmatx))
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
+ errorcode = HAL_ERROR;
+ }
+ }
+ /* Abort the SPI DMA rx Stream/Channel */
+ if (hspi->hdmarx != NULL)
+ {
+ if (HAL_OK != HAL_DMA_Abort(hspi->hdmarx))
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
+ errorcode = HAL_ERROR;
+ }
+ }
+
+ /* Disable the SPI DMA Tx & Rx requests */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
+ hspi->State = HAL_SPI_STATE_READY;
+ return errorcode;
+}
+
+/**
+ * @brief Handle SPI interrupt request.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for the specified SPI module.
+ * @retval None
+ */
+void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
+{
+ uint32_t itsource = hspi->Instance->CR2;
+ uint32_t itflag = hspi->Instance->SR;
+
+ /* SPI in mode Receiver ----------------------------------------------------*/
+ if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) == RESET) &&
+ (SPI_CHECK_FLAG(itflag, SPI_FLAG_RXNE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_RXNE) != RESET))
+ {
+ hspi->RxISR(hspi);
+ return;
+ }
+
+ /* SPI in mode Transmitter -------------------------------------------------*/
+ if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_TXE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_TXE) != RESET))
+ {
+ hspi->TxISR(hspi);
+ return;
+ }
+
+ /* SPI in Error Treatment --------------------------------------------------*/
+ if (((SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET) || (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET)
+ || (SPI_CHECK_FLAG(itflag, SPI_FLAG_FRE) != RESET)) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_ERR) != RESET))
+ {
+ /* SPI Overrun error interrupt occurred ----------------------------------*/
+ if (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET)
+ {
+ if (hspi->State != HAL_SPI_STATE_BUSY_TX)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR);
+ __HAL_SPI_CLEAR_OVRFLAG(hspi);
+ }
+ else
+ {
+ __HAL_SPI_CLEAR_OVRFLAG(hspi);
+ return;
+ }
+ }
+
+ /* SPI Mode Fault error interrupt occurred -------------------------------*/
+ if (SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF);
+ __HAL_SPI_CLEAR_MODFFLAG(hspi);
+ }
+
+ /* SPI Frame error interrupt occurred ------------------------------------*/
+ if (SPI_CHECK_FLAG(itflag, SPI_FLAG_FRE) != RESET)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FRE);
+ __HAL_SPI_CLEAR_FREFLAG(hspi);
+ }
+
+ if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+ {
+ /* Disable all interrupts */
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR);
+
+ hspi->State = HAL_SPI_STATE_READY;
+ /* Disable the SPI DMA requests if enabled */
+ if ((HAL_IS_BIT_SET(itsource, SPI_CR2_TXDMAEN)) || (HAL_IS_BIT_SET(itsource, SPI_CR2_RXDMAEN)))
+ {
+ CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN));
+
+ /* Abort the SPI DMA Rx channel */
+ if (hspi->hdmarx != NULL)
+ {
+ /* Set the SPI DMA Abort callback :
+ will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
+ hspi->hdmarx->XferAbortCallback = SPI_DMAAbortOnError;
+ if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmarx))
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
+ }
+ }
+ /* Abort the SPI DMA Tx channel */
+ if (hspi->hdmatx != NULL)
+ {
+ /* Set the SPI DMA Abort callback :
+ will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
+ hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError;
+ if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmatx))
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
+ }
+ }
+ }
+ else
+ {
+ /* Call user error callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->ErrorCallback(hspi);
+#else
+ HAL_SPI_ErrorCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+ }
+ }
+ return;
+ }
+}
+
+/**
+ * @brief Tx Transfer completed callback.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+__weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hspi);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SPI_TxCpltCallback should be implemented in the user file
+ */
+}
+
+/**
+ * @brief Rx Transfer completed callback.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+__weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hspi);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SPI_RxCpltCallback should be implemented in the user file
+ */
+}
+
+/**
+ * @brief Tx and Rx Transfer completed callback.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+__weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hspi);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SPI_TxRxCpltCallback should be implemented in the user file
+ */
+}
+
+/**
+ * @brief Tx Half Transfer completed callback.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+__weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hspi);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SPI_TxHalfCpltCallback should be implemented in the user file
+ */
+}
+
+/**
+ * @brief Rx Half Transfer completed callback.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+__weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hspi);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file
+ */
+}
+
+/**
+ * @brief Tx and Rx Half Transfer callback.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+__weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hspi);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file
+ */
+}
+
+/**
+ * @brief SPI error callback.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+__weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hspi);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SPI_ErrorCallback should be implemented in the user file
+ */
+ /* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes
+ and user can use HAL_SPI_GetError() API to check the latest error occurred
+ */
+}
+
+/**
+ * @brief SPI Abort Complete callback.
+ * @param hspi SPI handle.
+ * @retval None
+ */
+__weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hspi);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SPI_AbortCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
+ * @brief SPI control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral State and Errors functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control the SPI.
+ (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral
+ (+) HAL_SPI_GetError() check in run-time Errors occurring during communication
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the SPI handle state.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval SPI state
+ */
+HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
+{
+ /* Return SPI handle state */
+ return hspi->State;
+}
+
+/**
+ * @brief Return the SPI error code.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval SPI error code in bitmap format
+ */
+uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
+{
+ /* Return SPI ErrorCode */
+ return hspi->ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_Private_Functions
+ * @brief Private functions
+ * @{
+ */
+
+/**
+ * @brief DMA SPI transmit process complete callback.
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
+{
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+ uint32_t tickstart;
+
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+
+ /* DMA Normal Mode */
+ if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
+ {
+ /* Disable ERR interrupt */
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
+
+ /* Disable Tx DMA Request */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
+
+ /* Check the end of the transaction */
+ if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
+ }
+
+ /* Clear overrun flag in 2 Lines communication mode because received data is not read */
+ if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
+ {
+ __HAL_SPI_CLEAR_OVRFLAG(hspi);
+ }
+
+ hspi->TxXferCount = 0U;
+ hspi->State = HAL_SPI_STATE_READY;
+
+ if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+ {
+ /* Call user error callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->ErrorCallback(hspi);
+#else
+ HAL_SPI_ErrorCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+ return;
+ }
+ }
+ /* Call user Tx complete callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->TxCpltCallback(hspi);
+#else
+ HAL_SPI_TxCpltCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief DMA SPI receive process complete callback.
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+ uint32_t tickstart;
+#if (USE_SPI_CRC != 0U)
+ __IO uint32_t tmpreg = 0U;
+ __IO uint8_t *ptmpreg8;
+ __IO uint8_t tmpreg8 = 0;
+#endif /* USE_SPI_CRC */
+
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+
+ /* DMA Normal Mode */
+ if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
+ {
+ /* Disable ERR interrupt */
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
+
+#if (USE_SPI_CRC != 0U)
+ /* CRC handling */
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ /* Wait until RXNE flag */
+ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
+ {
+ /* Error on the CRC reception */
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
+ }
+ /* Read CRC */
+ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+ {
+ /* Read 16bit CRC */
+ tmpreg = READ_REG(hspi->Instance->DR);
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
+ }
+ else
+ {
+ /* Initialize the 8bit temporary pointer */
+ ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
+ /* Read 8bit CRC */
+ tmpreg8 = *ptmpreg8;
+ /* To avoid GCC warning */
+ UNUSED(tmpreg8);
+
+ if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
+ {
+ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
+ {
+ /* Error on the CRC reception */
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
+ }
+ /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */
+ tmpreg8 = *ptmpreg8;
+ /* To avoid GCC warning */
+ UNUSED(tmpreg8);
+ }
+ }
+ }
+#endif /* USE_SPI_CRC */
+
+ /* Check if we are in Master RX 2 line mode */
+ if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
+ {
+ /* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
+ }
+ else
+ {
+ /* Normal case */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
+ }
+
+ /* Check the end of the transaction */
+ if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
+ {
+ hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
+ }
+
+ hspi->RxXferCount = 0U;
+ hspi->State = HAL_SPI_STATE_READY;
+
+#if (USE_SPI_CRC != 0U)
+ /* Check if CRC error occurred */
+ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
+ __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
+ }
+#endif /* USE_SPI_CRC */
+
+ if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+ {
+ /* Call user error callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->ErrorCallback(hspi);
+#else
+ HAL_SPI_ErrorCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+ return;
+ }
+ }
+ /* Call user Rx complete callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->RxCpltCallback(hspi);
+#else
+ HAL_SPI_RxCpltCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief DMA SPI transmit receive process complete callback.
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+ uint32_t tickstart;
+#if (USE_SPI_CRC != 0U)
+ __IO uint32_t tmpreg = 0U;
+ __IO uint8_t *ptmpreg8;
+ __IO uint8_t tmpreg8 = 0;
+#endif /* USE_SPI_CRC */
+
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+
+ /* DMA Normal Mode */
+ if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
+ {
+ /* Disable ERR interrupt */
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
+
+#if (USE_SPI_CRC != 0U)
+ /* CRC handling */
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ if ((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_8BIT))
+ {
+ if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_QUARTER_FULL, SPI_DEFAULT_TIMEOUT,
+ tickstart) != HAL_OK)
+ {
+ /* Error on the CRC reception */
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
+ }
+ /* Initialize the 8bit temporary pointer */
+ ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
+ /* Read 8bit CRC */
+ tmpreg8 = *ptmpreg8;
+ /* To avoid GCC warning */
+ UNUSED(tmpreg8);
+ }
+ else
+ {
+ if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
+ {
+ /* Error on the CRC reception */
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
+ }
+ /* Read CRC to Flush DR and RXNE flag */
+ tmpreg = READ_REG(hspi->Instance->DR);
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
+ }
+ }
+#endif /* USE_SPI_CRC */
+
+ /* Check the end of the transaction */
+ if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
+ }
+
+ /* Disable Rx/Tx DMA Request */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
+
+ hspi->TxXferCount = 0U;
+ hspi->RxXferCount = 0U;
+ hspi->State = HAL_SPI_STATE_READY;
+
+#if (USE_SPI_CRC != 0U)
+ /* Check if CRC error occurred */
+ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
+ __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
+ }
+#endif /* USE_SPI_CRC */
+
+ if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+ {
+ /* Call user error callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->ErrorCallback(hspi);
+#else
+ HAL_SPI_ErrorCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+ return;
+ }
+ }
+ /* Call user TxRx complete callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->TxRxCpltCallback(hspi);
+#else
+ HAL_SPI_TxRxCpltCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief DMA SPI half transmit process complete callback.
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)
+{
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+
+ /* Call user Tx half complete callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->TxHalfCpltCallback(hspi);
+#else
+ HAL_SPI_TxHalfCpltCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief DMA SPI half receive process complete callback
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+
+ /* Call user Rx half complete callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->RxHalfCpltCallback(hspi);
+#else
+ HAL_SPI_RxHalfCpltCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief DMA SPI half transmit receive process complete callback.
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+
+ /* Call user TxRx half complete callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->TxRxHalfCpltCallback(hspi);
+#else
+ HAL_SPI_TxRxHalfCpltCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief DMA SPI communication error callback.
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void SPI_DMAError(DMA_HandleTypeDef *hdma)
+{
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+
+ /* Stop the disable DMA transfer on SPI side */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
+
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
+ hspi->State = HAL_SPI_STATE_READY;
+ /* Call user error callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->ErrorCallback(hspi);
+#else
+ HAL_SPI_ErrorCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief DMA SPI communication abort callback, when initiated by HAL services on Error
+ * (To be called at end of DMA Abort procedure following error occurrence).
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma)
+{
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+ hspi->RxXferCount = 0U;
+ hspi->TxXferCount = 0U;
+
+ /* Call user error callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->ErrorCallback(hspi);
+#else
+ HAL_SPI_ErrorCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief DMA SPI Tx communication abort callback, when initiated by user
+ * (To be called at end of DMA Tx Abort procedure following user abort request).
+ * @note When this callback is executed, User Abort complete call back is called only if no
+ * Abort still ongoing for Rx DMA Handle.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+
+ hspi->hdmatx->XferAbortCallback = NULL;
+
+ /* Disable Tx DMA Request */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
+
+ if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
+ {
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ }
+
+ /* Disable SPI Peripheral */
+ __HAL_SPI_DISABLE(hspi);
+
+ /* Empty the FRLVL fifo */
+ if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
+ {
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ }
+
+ /* Check if an Abort process is still ongoing */
+ if (hspi->hdmarx != NULL)
+ {
+ if (hspi->hdmarx->XferAbortCallback != NULL)
+ {
+ return;
+ }
+ }
+
+ /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */
+ hspi->RxXferCount = 0U;
+ hspi->TxXferCount = 0U;
+
+ /* Check no error during Abort procedure */
+ if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT)
+ {
+ /* Reset errorCode */
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ }
+
+ /* Clear the Error flags in the SR register */
+ __HAL_SPI_CLEAR_OVRFLAG(hspi);
+ __HAL_SPI_CLEAR_FREFLAG(hspi);
+
+ /* Restore hspi->State to Ready */
+ hspi->State = HAL_SPI_STATE_READY;
+
+ /* Call user Abort complete callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->AbortCpltCallback(hspi);
+#else
+ HAL_SPI_AbortCpltCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief DMA SPI Rx communication abort callback, when initiated by user
+ * (To be called at end of DMA Rx Abort procedure following user abort request).
+ * @note When this callback is executed, User Abort complete call back is called only if no
+ * Abort still ongoing for Tx DMA Handle.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+
+ /* Disable SPI Peripheral */
+ __HAL_SPI_DISABLE(hspi);
+
+ hspi->hdmarx->XferAbortCallback = NULL;
+
+ /* Disable Rx DMA Request */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
+
+ /* Control the BSY flag */
+ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
+ {
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ }
+
+ /* Empty the FRLVL fifo */
+ if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
+ {
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ }
+
+ /* Check if an Abort process is still ongoing */
+ if (hspi->hdmatx != NULL)
+ {
+ if (hspi->hdmatx->XferAbortCallback != NULL)
+ {
+ return;
+ }
+ }
+
+ /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */
+ hspi->RxXferCount = 0U;
+ hspi->TxXferCount = 0U;
+
+ /* Check no error during Abort procedure */
+ if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT)
+ {
+ /* Reset errorCode */
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ }
+
+ /* Clear the Error flags in the SR register */
+ __HAL_SPI_CLEAR_OVRFLAG(hspi);
+ __HAL_SPI_CLEAR_FREFLAG(hspi);
+
+ /* Restore hspi->State to Ready */
+ hspi->State = HAL_SPI_STATE_READY;
+
+ /* Call user Abort complete callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->AbortCpltCallback(hspi);
+#else
+ HAL_SPI_AbortCpltCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
+{
+ /* Receive data in packing mode */
+ if (hspi->RxXferCount > 1U)
+ {
+ *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR);
+ hspi->pRxBuffPtr += sizeof(uint16_t);
+ hspi->RxXferCount -= 2U;
+ if (hspi->RxXferCount == 1U)
+ {
+ /* Set RX Fifo threshold according the reception data length: 8bit */
+ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+ }
+ }
+ /* Receive data in 8 Bit mode */
+ else
+ {
+ *hspi->pRxBuffPtr = *((__IO uint8_t *)&hspi->Instance->DR);
+ hspi->pRxBuffPtr++;
+ hspi->RxXferCount--;
+ }
+
+ /* Check end of the reception */
+ if (hspi->RxXferCount == 0U)
+ {
+#if (USE_SPI_CRC != 0U)
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+ hspi->RxISR = SPI_2linesRxISR_8BITCRC;
+ return;
+ }
+#endif /* USE_SPI_CRC */
+
+ /* Disable RXNE and ERR interrupt */
+ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
+
+ if (hspi->TxXferCount == 0U)
+ {
+ SPI_CloseRxTx_ISR(hspi);
+ }
+ }
+}
+
+#if (USE_SPI_CRC != 0U)
+/**
+ * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
+{
+ __IO uint8_t *ptmpreg8;
+ __IO uint8_t tmpreg8 = 0;
+
+ /* Initialize the 8bit temporary pointer */
+ ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
+ /* Read 8bit CRC to flush Data Register */
+ tmpreg8 = *ptmpreg8;
+ /* To avoid GCC warning */
+ UNUSED(tmpreg8);
+
+ hspi->CRCSize--;
+
+ /* Check end of the reception */
+ if (hspi->CRCSize == 0U)
+ {
+ /* Disable RXNE and ERR interrupt */
+ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
+
+ if (hspi->TxXferCount == 0U)
+ {
+ SPI_CloseRxTx_ISR(hspi);
+ }
+ }
+}
+#endif /* USE_SPI_CRC */
+
+/**
+ * @brief Tx 8-bit handler for Transmit and Receive in Interrupt mode.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
+{
+ /* Transmit data in packing Bit mode */
+ if (hspi->TxXferCount >= 2U)
+ {
+ hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr += sizeof(uint16_t);
+ hspi->TxXferCount -= 2U;
+ }
+ /* Transmit data in 8 Bit mode */
+ else
+ {
+ *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr++;
+ hspi->TxXferCount--;
+ }
+
+ /* Check the end of the transmission */
+ if (hspi->TxXferCount == 0U)
+ {
+#if (USE_SPI_CRC != 0U)
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ /* Set CRC Next Bit to send CRC */
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
+ /* Disable TXE interrupt */
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
+ return;
+ }
+#endif /* USE_SPI_CRC */
+
+ /* Disable TXE interrupt */
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
+
+ if (hspi->RxXferCount == 0U)
+ {
+ SPI_CloseRxTx_ISR(hspi);
+ }
+ }
+}
+
+/**
+ * @brief Rx 16-bit handler for Transmit and Receive in Interrupt mode.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
+{
+ /* Receive data in 16 Bit mode */
+ *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR);
+ hspi->pRxBuffPtr += sizeof(uint16_t);
+ hspi->RxXferCount--;
+
+ if (hspi->RxXferCount == 0U)
+ {
+#if (USE_SPI_CRC != 0U)
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ hspi->RxISR = SPI_2linesRxISR_16BITCRC;
+ return;
+ }
+#endif /* USE_SPI_CRC */
+
+ /* Disable RXNE interrupt */
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
+
+ if (hspi->TxXferCount == 0U)
+ {
+ SPI_CloseRxTx_ISR(hspi);
+ }
+ }
+}
+
+#if (USE_SPI_CRC != 0U)
+/**
+ * @brief Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
+{
+ __IO uint32_t tmpreg = 0U;
+
+ /* Read 16bit CRC to flush Data Register */
+ tmpreg = READ_REG(hspi->Instance->DR);
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
+
+ /* Disable RXNE interrupt */
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
+
+ SPI_CloseRxTx_ISR(hspi);
+}
+#endif /* USE_SPI_CRC */
+
+/**
+ * @brief Tx 16-bit handler for Transmit and Receive in Interrupt mode.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
+{
+ /* Transmit data in 16 Bit mode */
+ hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr += sizeof(uint16_t);
+ hspi->TxXferCount--;
+
+ /* Enable CRC Transmission */
+ if (hspi->TxXferCount == 0U)
+ {
+#if (USE_SPI_CRC != 0U)
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ /* Set CRC Next Bit to send CRC */
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
+ /* Disable TXE interrupt */
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
+ return;
+ }
+#endif /* USE_SPI_CRC */
+
+ /* Disable TXE interrupt */
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
+
+ if (hspi->RxXferCount == 0U)
+ {
+ SPI_CloseRxTx_ISR(hspi);
+ }
+ }
+}
+
+#if (USE_SPI_CRC != 0U)
+/**
+ * @brief Manage the CRC 8-bit receive in Interrupt context.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
+{
+ __IO uint8_t *ptmpreg8;
+ __IO uint8_t tmpreg8 = 0;
+
+ /* Initialize the 8bit temporary pointer */
+ ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
+ /* Read 8bit CRC to flush Data Register */
+ tmpreg8 = *ptmpreg8;
+ /* To avoid GCC warning */
+ UNUSED(tmpreg8);
+
+ hspi->CRCSize--;
+
+ if (hspi->CRCSize == 0U)
+ {
+ SPI_CloseRx_ISR(hspi);
+ }
+}
+#endif /* USE_SPI_CRC */
+
+/**
+ * @brief Manage the receive 8-bit in Interrupt context.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
+{
+ *hspi->pRxBuffPtr = (*(__IO uint8_t *)&hspi->Instance->DR);
+ hspi->pRxBuffPtr++;
+ hspi->RxXferCount--;
+
+#if (USE_SPI_CRC != 0U)
+ /* Enable CRC Transmission */
+ if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
+ {
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
+ }
+#endif /* USE_SPI_CRC */
+
+ if (hspi->RxXferCount == 0U)
+ {
+#if (USE_SPI_CRC != 0U)
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ hspi->RxISR = SPI_RxISR_8BITCRC;
+ return;
+ }
+#endif /* USE_SPI_CRC */
+ SPI_CloseRx_ISR(hspi);
+ }
+}
+
+#if (USE_SPI_CRC != 0U)
+/**
+ * @brief Manage the CRC 16-bit receive in Interrupt context.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
+{
+ __IO uint32_t tmpreg = 0U;
+
+ /* Read 16bit CRC to flush Data Register */
+ tmpreg = READ_REG(hspi->Instance->DR);
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
+
+ /* Disable RXNE and ERR interrupt */
+ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
+
+ SPI_CloseRx_ISR(hspi);
+}
+#endif /* USE_SPI_CRC */
+
+/**
+ * @brief Manage the 16-bit receive in Interrupt context.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
+{
+ *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR);
+ hspi->pRxBuffPtr += sizeof(uint16_t);
+ hspi->RxXferCount--;
+
+#if (USE_SPI_CRC != 0U)
+ /* Enable CRC Transmission */
+ if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
+ {
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
+ }
+#endif /* USE_SPI_CRC */
+
+ if (hspi->RxXferCount == 0U)
+ {
+#if (USE_SPI_CRC != 0U)
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ hspi->RxISR = SPI_RxISR_16BITCRC;
+ return;
+ }
+#endif /* USE_SPI_CRC */
+ SPI_CloseRx_ISR(hspi);
+ }
+}
+
+/**
+ * @brief Handle the data 8-bit transmit in Interrupt mode.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
+{
+ *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr++;
+ hspi->TxXferCount--;
+
+ if (hspi->TxXferCount == 0U)
+ {
+#if (USE_SPI_CRC != 0U)
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ /* Enable CRC Transmission */
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
+ }
+#endif /* USE_SPI_CRC */
+ SPI_CloseTx_ISR(hspi);
+ }
+}
+
+/**
+ * @brief Handle the data 16-bit transmit in Interrupt mode.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
+{
+ /* Transmit data in 16 Bit mode */
+ hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr += sizeof(uint16_t);
+ hspi->TxXferCount--;
+
+ if (hspi->TxXferCount == 0U)
+ {
+#if (USE_SPI_CRC != 0U)
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ /* Enable CRC Transmission */
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
+ }
+#endif /* USE_SPI_CRC */
+ SPI_CloseTx_ISR(hspi);
+ }
+}
+
+/**
+ * @brief Handle SPI Communication Timeout.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param Flag SPI flag to check
+ * @param State flag state to check
+ * @param Timeout Timeout duration
+ * @param Tickstart tick start value
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State,
+ uint32_t Timeout, uint32_t Tickstart)
+{
+ __IO uint32_t count;
+ uint32_t tmp_timeout;
+ uint32_t tmp_tickstart;
+
+ /* Adjust Timeout value in case of end of transfer */
+ tmp_timeout = Timeout - (HAL_GetTick() - Tickstart);
+ tmp_tickstart = HAL_GetTick();
+
+ /* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */
+ count = tmp_timeout * ((SystemCoreClock * 32U) >> 20U);
+
+ while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State)
+ {
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) || (tmp_timeout == 0U))
+ {
+ /* Disable the SPI and reset the CRC: the CRC value should be cleared
+ on both master and slave sides in order to resynchronize the master
+ and slave for their respective CRC calculation */
+
+ /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
+ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
+
+ if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
+ || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
+ {
+ /* Disable SPI peripheral */
+ __HAL_SPI_DISABLE(hspi);
+ }
+
+ /* Reset CRC Calculation */
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ SPI_RESET_CRC(hspi);
+ }
+
+ hspi->State = HAL_SPI_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+
+ return HAL_TIMEOUT;
+ }
+ /* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */
+ if (count == 0U)
+ {
+ tmp_timeout = 0U;
+ }
+ count--;
+ }
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle SPI FIFO Communication Timeout.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param Fifo Fifo to check
+ * @param State Fifo state to check
+ * @param Timeout Timeout duration
+ * @param Tickstart tick start value
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State,
+ uint32_t Timeout, uint32_t Tickstart)
+{
+ __IO uint32_t count;
+ uint32_t tmp_timeout;
+ uint32_t tmp_tickstart;
+ __IO uint8_t *ptmpreg8;
+ __IO uint8_t tmpreg8 = 0;
+
+ /* Adjust Timeout value in case of end of transfer */
+ tmp_timeout = Timeout - (HAL_GetTick() - Tickstart);
+ tmp_tickstart = HAL_GetTick();
+
+ /* Initialize the 8bit temporary pointer */
+ ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
+
+ /* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */
+ count = tmp_timeout * ((SystemCoreClock * 35U) >> 20U);
+
+ while ((hspi->Instance->SR & Fifo) != State)
+ {
+ if ((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY))
+ {
+ /* Flush Data Register by a blank read */
+ tmpreg8 = *ptmpreg8;
+ /* To avoid GCC warning */
+ UNUSED(tmpreg8);
+ }
+
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) || (tmp_timeout == 0U))
+ {
+ /* Disable the SPI and reset the CRC: the CRC value should be cleared
+ on both master and slave sides in order to resynchronize the master
+ and slave for their respective CRC calculation */
+
+ /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
+ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
+
+ if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
+ || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
+ {
+ /* Disable SPI peripheral */
+ __HAL_SPI_DISABLE(hspi);
+ }
+
+ /* Reset CRC Calculation */
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ SPI_RESET_CRC(hspi);
+ }
+
+ hspi->State = HAL_SPI_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+
+ return HAL_TIMEOUT;
+ }
+ /* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */
+ if (count == 0U)
+ {
+ tmp_timeout = 0U;
+ }
+ count--;
+ }
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle the check of the RX transaction complete.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param Timeout Timeout duration
+ * @param Tickstart tick start value
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
+{
+ if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
+ || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
+ {
+ /* Disable SPI peripheral */
+ __HAL_SPI_DISABLE(hspi);
+ }
+
+ /* Control the BSY flag */
+ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
+ return HAL_TIMEOUT;
+ }
+
+ if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
+ || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
+ {
+ /* Empty the FRLVL fifo */
+ if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
+ return HAL_TIMEOUT;
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle the check of the RXTX or TX transaction complete.
+ * @param hspi SPI handle
+ * @param Timeout Timeout duration
+ * @param Tickstart tick start value
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
+{
+ /* Control if the TX fifo is empty */
+ if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FTLVL, SPI_FTLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
+ return HAL_TIMEOUT;
+ }
+
+ /* Control the BSY flag */
+ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
+ return HAL_TIMEOUT;
+ }
+
+ /* Control if the RX fifo is empty */
+ if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
+ return HAL_TIMEOUT;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle the end of the RXTX transaction.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)
+{
+ uint32_t tickstart;
+
+ /* Init tickstart for timeout management */
+ tickstart = HAL_GetTick();
+
+ /* Disable ERR interrupt */
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
+
+ /* Check the end of the transaction */
+ if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
+ }
+
+#if (USE_SPI_CRC != 0U)
+ /* Check if CRC error occurred */
+ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
+ {
+ hspi->State = HAL_SPI_STATE_READY;
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
+ __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
+ /* Call user error callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->ErrorCallback(hspi);
+#else
+ HAL_SPI_ErrorCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+ }
+ else
+ {
+#endif /* USE_SPI_CRC */
+ if (hspi->ErrorCode == HAL_SPI_ERROR_NONE)
+ {
+ if (hspi->State == HAL_SPI_STATE_BUSY_RX)
+ {
+ hspi->State = HAL_SPI_STATE_READY;
+ /* Call user Rx complete callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->RxCpltCallback(hspi);
+#else
+ HAL_SPI_RxCpltCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+ }
+ else
+ {
+ hspi->State = HAL_SPI_STATE_READY;
+ /* Call user TxRx complete callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->TxRxCpltCallback(hspi);
+#else
+ HAL_SPI_TxRxCpltCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+ }
+ }
+ else
+ {
+ hspi->State = HAL_SPI_STATE_READY;
+ /* Call user error callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->ErrorCallback(hspi);
+#else
+ HAL_SPI_ErrorCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+ }
+#if (USE_SPI_CRC != 0U)
+ }
+#endif /* USE_SPI_CRC */
+}
+
+/**
+ * @brief Handle the end of the RX transaction.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi)
+{
+ /* Disable RXNE and ERR interrupt */
+ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
+
+ /* Check the end of the transaction */
+ if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
+ }
+ hspi->State = HAL_SPI_STATE_READY;
+
+#if (USE_SPI_CRC != 0U)
+ /* Check if CRC error occurred */
+ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
+ __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
+ /* Call user error callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->ErrorCallback(hspi);
+#else
+ HAL_SPI_ErrorCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+ }
+ else
+ {
+#endif /* USE_SPI_CRC */
+ if (hspi->ErrorCode == HAL_SPI_ERROR_NONE)
+ {
+ /* Call user Rx complete callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->RxCpltCallback(hspi);
+#else
+ HAL_SPI_RxCpltCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+ }
+ else
+ {
+ /* Call user error callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->ErrorCallback(hspi);
+#else
+ HAL_SPI_ErrorCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+ }
+#if (USE_SPI_CRC != 0U)
+ }
+#endif /* USE_SPI_CRC */
+}
+
+/**
+ * @brief Handle the end of the TX transaction.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi)
+{
+ uint32_t tickstart;
+
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+
+ /* Disable TXE and ERR interrupt */
+ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
+
+ /* Check the end of the transaction */
+ if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
+ }
+
+ /* Clear overrun flag in 2 Lines communication mode because received is not read */
+ if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
+ {
+ __HAL_SPI_CLEAR_OVRFLAG(hspi);
+ }
+
+ hspi->State = HAL_SPI_STATE_READY;
+ if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+ {
+ /* Call user error callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->ErrorCallback(hspi);
+#else
+ HAL_SPI_ErrorCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+ }
+ else
+ {
+ /* Call user Rx complete callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->TxCpltCallback(hspi);
+#else
+ HAL_SPI_TxCpltCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+ }
+}
+
+/**
+ * @brief Handle abort a Rx transaction.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi)
+{
+ __IO uint32_t count;
+
+ /* Disable SPI Peripheral */
+ __HAL_SPI_DISABLE(hspi);
+
+ count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
+
+ /* Disable RXNEIE interrupt */
+ CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXNEIE));
+
+ /* Check RXNEIE is disabled */
+ do
+ {
+ if (count == 0U)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
+ break;
+ }
+ count--;
+ } while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE));
+
+ /* Control the BSY flag */
+ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
+ {
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ }
+
+ /* Empty the FRLVL fifo */
+ if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
+ {
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ }
+
+ hspi->State = HAL_SPI_STATE_ABORT;
+}
+
+/**
+ * @brief Handle abort a Tx or Rx/Tx transaction.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi)
+{
+ __IO uint32_t count;
+
+ count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
+
+ /* Disable TXEIE interrupt */
+ CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE));
+
+ /* Check TXEIE is disabled */
+ do
+ {
+ if (count == 0U)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
+ break;
+ }
+ count--;
+ } while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE));
+
+ if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
+ {
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ }
+
+ /* Disable SPI Peripheral */
+ __HAL_SPI_DISABLE(hspi);
+
+ /* Empty the FRLVL fifo */
+ if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
+ {
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ }
+
+ /* Check case of Full-Duplex Mode and disable directly RXNEIE interrupt */
+ if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
+ {
+ /* Disable RXNEIE interrupt */
+ CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXNEIE));
+
+ /* Check RXNEIE is disabled */
+ do
+ {
+ if (count == 0U)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
+ break;
+ }
+ count--;
+ } while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE));
+
+ /* Control the BSY flag */
+ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
+ {
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ }
+
+ /* Empty the FRLVL fifo */
+ if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
+ {
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ }
+ }
+ hspi->State = HAL_SPI_STATE_ABORT;
+}
+
+/**
+ * @}
+ */
+
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_spi_ex.c b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_spi_ex.c
new file mode 100644
index 0000000000..9ced2ecef7
--- /dev/null
+++ b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_spi_ex.c
@@ -0,0 +1,112 @@
+/**
+ ******************************************************************************
+ * @file stm32c0xx_hal_spi_ex.c
+ * @author MCD Application Team
+ * @brief Extended SPI HAL module driver.
+ * This file provides firmware functions to manage the following
+ * SPI peripheral extended functionalities :
+ * + IO operation functions
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2022 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32c0xx_hal.h"
+
+/** @addtogroup STM32C0xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup SPIEx SPIEx
+ * @brief SPI Extended HAL module driver
+ * @{
+ */
+#ifdef HAL_SPI_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private defines -----------------------------------------------------------*/
+/** @defgroup SPIEx_Private_Constants SPIEx Private Constants
+ * @{
+ */
+#define SPI_FIFO_SIZE 4UL
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup SPIEx_Exported_Functions SPIEx Exported Functions
+ * @{
+ */
+
+/** @defgroup SPIEx_Exported_Functions_Group1 IO operation functions
+ * @brief Data transfers functions
+ *
+@verbatim
+ ==============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of extended functions to manage the SPI
+ data transfers.
+
+ (#) Rx data flush function:
+ (++) HAL_SPIEx_FlushRxFifo()
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Flush the RX fifo.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for the specified SPI module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(SPI_HandleTypeDef *hspi)
+{
+ __IO uint32_t tmpreg;
+ uint8_t count = 0U;
+ while ((hspi->Instance->SR & SPI_FLAG_FRLVL) != SPI_FRLVL_EMPTY)
+ {
+ count++;
+ tmpreg = hspi->Instance->DR;
+ UNUSED(tmpreg); /* To avoid GCC warning */
+ if (count == SPI_FIFO_SIZE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c
new file mode 100644
index 0000000000..f9292fde59
--- /dev/null
+++ b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c
@@ -0,0 +1,7895 @@
+/**
+ ******************************************************************************
+ * @file stm32c0xx_hal_tim.c
+ * @author MCD Application Team
+ * @brief TIM HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Timer (TIM) peripheral:
+ * + TIM Time Base Initialization
+ * + TIM Time Base Start
+ * + TIM Time Base Start Interruption
+ * + TIM Time Base Start DMA
+ * + TIM Output Compare/PWM Initialization
+ * + TIM Output Compare/PWM Channel Configuration
+ * + TIM Output Compare/PWM Start
+ * + TIM Output Compare/PWM Start Interruption
+ * + TIM Output Compare/PWM Start DMA
+ * + TIM Input Capture Initialization
+ * + TIM Input Capture Channel Configuration
+ * + TIM Input Capture Start
+ * + TIM Input Capture Start Interruption
+ * + TIM Input Capture Start DMA
+ * + TIM One Pulse Initialization
+ * + TIM One Pulse Channel Configuration
+ * + TIM One Pulse Start
+ * + TIM Encoder Interface Initialization
+ * + TIM Encoder Interface Start
+ * + TIM Encoder Interface Start Interruption
+ * + TIM Encoder Interface Start DMA
+ * + Commutation Event configuration with Interruption and DMA
+ * + TIM OCRef clear configuration
+ * + TIM External Clock configuration
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2022 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### TIMER Generic features #####
+ ==============================================================================
+ [..] The Timer features include:
+ (#) 16-bit up, down, up/down auto-reload counter.
+ (#) 16-bit programmable prescaler allowing dividing (also on the fly) the
+ counter clock frequency either by any factor between 1 and 65536.
+ (#) Up to 4 independent channels for:
+ (++) Input Capture
+ (++) Output Compare
+ (++) PWM generation (Edge and Center-aligned Mode)
+ (++) One-pulse mode output
+ (#) Synchronization circuit to control the timer with external signals and to interconnect
+ several timers together.
+ (#) Supports incremental encoder for positioning purposes
+
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ (#) Initialize the TIM low level resources by implementing the following functions
+ depending on the selected feature:
+ (++) Time Base : HAL_TIM_Base_MspInit()
+ (++) Input Capture : HAL_TIM_IC_MspInit()
+ (++) Output Compare : HAL_TIM_OC_MspInit()
+ (++) PWM generation : HAL_TIM_PWM_MspInit()
+ (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
+ (++) Encoder mode output : HAL_TIM_Encoder_MspInit()
+
+ (#) Initialize the TIM low level resources :
+ (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
+ (##) TIM pins configuration
+ (+++) Enable the clock for the TIM GPIOs using the following function:
+ __HAL_RCC_GPIOx_CLK_ENABLE();
+ (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
+
+ (#) The external Clock can be configured, if needed (the default clock is the
+ internal clock from the APBx), using the following function:
+ HAL_TIM_ConfigClockSource, the clock configuration should be done before
+ any start function.
+
+ (#) Configure the TIM in the desired functioning mode using one of the
+ Initialization function of this driver:
+ (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
+ (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
+ Output Compare signal.
+ (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
+ PWM signal.
+ (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
+ external signal.
+ (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
+ in One Pulse Mode.
+ (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
+
+ (#) Activate the TIM peripheral using one of the start functions depending from the feature used:
+ (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
+ (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
+ (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
+ (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
+ (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
+ (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
+
+ (#) The DMA Burst is managed with the two following functions:
+ HAL_TIM_DMABurst_WriteStart()
+ HAL_TIM_DMABurst_ReadStart()
+
+ *** Callback registration ***
+ =============================================
+
+ [..]
+ The compilation define USE_HAL_TIM_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+
+ [..]
+ Use Function HAL_TIM_RegisterCallback() to register a callback.
+ HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle,
+ the Callback ID and a pointer to the user callback function.
+
+ [..]
+ Use function HAL_TIM_UnRegisterCallback() to reset a callback to the default
+ weak function.
+ HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle,
+ and the Callback ID.
+
+ [..]
+ These functions allow to register/unregister following callbacks:
+ (+) Base_MspInitCallback : TIM Base Msp Init Callback.
+ (+) Base_MspDeInitCallback : TIM Base Msp DeInit Callback.
+ (+) IC_MspInitCallback : TIM IC Msp Init Callback.
+ (+) IC_MspDeInitCallback : TIM IC Msp DeInit Callback.
+ (+) OC_MspInitCallback : TIM OC Msp Init Callback.
+ (+) OC_MspDeInitCallback : TIM OC Msp DeInit Callback.
+ (+) PWM_MspInitCallback : TIM PWM Msp Init Callback.
+ (+) PWM_MspDeInitCallback : TIM PWM Msp DeInit Callback.
+ (+) OnePulse_MspInitCallback : TIM One Pulse Msp Init Callback.
+ (+) OnePulse_MspDeInitCallback : TIM One Pulse Msp DeInit Callback.
+ (+) Encoder_MspInitCallback : TIM Encoder Msp Init Callback.
+ (+) Encoder_MspDeInitCallback : TIM Encoder Msp DeInit Callback.
+ (+) HallSensor_MspInitCallback : TIM Hall Sensor Msp Init Callback.
+ (+) HallSensor_MspDeInitCallback : TIM Hall Sensor Msp DeInit Callback.
+ (+) PeriodElapsedCallback : TIM Period Elapsed Callback.
+ (+) PeriodElapsedHalfCpltCallback : TIM Period Elapsed half complete Callback.
+ (+) TriggerCallback : TIM Trigger Callback.
+ (+) TriggerHalfCpltCallback : TIM Trigger half complete Callback.
+ (+) IC_CaptureCallback : TIM Input Capture Callback.
+ (+) IC_CaptureHalfCpltCallback : TIM Input Capture half complete Callback.
+ (+) OC_DelayElapsedCallback : TIM Output Compare Delay Elapsed Callback.
+ (+) PWM_PulseFinishedCallback : TIM PWM Pulse Finished Callback.
+ (+) PWM_PulseFinishedHalfCpltCallback : TIM PWM Pulse Finished half complete Callback.
+ (+) ErrorCallback : TIM Error Callback.
+ (+) CommutationCallback : TIM Commutation Callback.
+ (+) CommutationHalfCpltCallback : TIM Commutation half complete Callback.
+ (+) BreakCallback : TIM Break Callback.
+ (+) Break2Callback : TIM Break2 Callback.
+
+ [..]
+By default, after the Init and when the state is HAL_TIM_STATE_RESET
+all interrupt callbacks are set to the corresponding weak functions:
+ examples HAL_TIM_TriggerCallback(), HAL_TIM_ErrorCallback().
+
+ [..]
+ Exception done for MspInit and MspDeInit functions that are reset to the legacy weak
+ functionalities in the Init / DeInit only when these callbacks are null
+ (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init / DeInit
+ keep and use the user MspInit / MspDeInit callbacks(registered beforehand)
+
+ [..]
+ Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state only.
+ Exception done MspInit / MspDeInit that can be registered / unregistered
+ in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state,
+ thus registered(user) MspInit / DeInit callbacks can be used during the Init / DeInit.
+ In that case first register the MspInit/MspDeInit user callbacks
+ using HAL_TIM_RegisterCallback() before calling DeInit or Init function.
+
+ [..]
+ When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registration feature is not available and all callbacks
+ are set to the corresponding weak functions.
+
+ @endverbatim
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32c0xx_hal.h"
+
+/** @addtogroup STM32C0xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup TIM TIM
+ * @brief TIM HAL module driver
+ * @{
+ */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @addtogroup TIM_Private_Constants
+ * @{
+ */
+#define TIMx_OR1_OCREF_CLR 0x00000001U
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup TIM_Private_Functions
+ * @{
+ */
+static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
+static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
+static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
+static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
+static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
+static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
+static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+ uint32_t TIM_ICFilter);
+static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
+static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+ uint32_t TIM_ICFilter);
+static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+ uint32_t TIM_ICFilter);
+static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource);
+static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
+static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma);
+static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
+static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
+static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma);
+static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
+ TIM_SlaveConfigTypeDef *sSlaveConfig);
+/**
+ * @}
+ */
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup TIM_Exported_Functions TIM Exported Functions
+ * @{
+ */
+
+/** @defgroup TIM_Exported_Functions_Group1 TIM Time Base functions
+ * @brief Time Base functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Time Base functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Initialize and configure the TIM base.
+ (+) De-initialize the TIM base.
+ (+) Start the Time Base.
+ (+) Stop the Time Base.
+ (+) Start the Time Base and enable interrupt.
+ (+) Stop the Time Base and disable interrupt.
+ (+) Start the Time Base and enable DMA transfer.
+ (+) Stop the Time Base and disable DMA transfer.
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Initializes the TIM Time base Unit according to the specified
+ * parameters in the TIM_HandleTypeDef and initialize the associated handle.
+ * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+ * requires a timer reset to avoid unexpected direction
+ * due to DIR bit readonly in center aligned mode.
+ * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
+ * @param htim TIM Base handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
+{
+ /* Check the TIM handle allocation */
+ if (htim == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+ assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+ assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+
+ if (htim->State == HAL_TIM_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ /* Reset interrupt callbacks to legacy weak callbacks */
+ TIM_ResetCallback(htim);
+
+ if (htim->Base_MspInitCallback == NULL)
+ {
+ htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;
+ }
+ /* Init the low level hardware : GPIO, CLOCK, NVIC */
+ htim->Base_MspInitCallback(htim);
+#else
+ /* Init the low level hardware : GPIO, CLOCK, NVIC */
+ HAL_TIM_Base_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ }
+
+ /* Set the TIM state */
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Set the Time Base configuration */
+ TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+ /* Initialize the DMA burst operation state */
+ htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+
+ /* Initialize the TIM channels state */
+ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+
+ /* Initialize the TIM state*/
+ htim->State = HAL_TIM_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the TIM Base peripheral
+ * @param htim TIM Base handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Disable the TIM Peripheral Clock */
+ __HAL_TIM_DISABLE(htim);
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ if (htim->Base_MspDeInitCallback == NULL)
+ {
+ htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;
+ }
+ /* DeInit the low level hardware */
+ htim->Base_MspDeInitCallback(htim);
+#else
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+ HAL_TIM_Base_MspDeInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+ /* Change the DMA burst operation state */
+ htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
+
+ /* Change the TIM channels state */
+ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+ TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+
+ /* Change TIM state */
+ htim->State = HAL_TIM_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the TIM Base MSP.
+ * @param htim TIM Base handle
+ * @retval None
+ */
+__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_Base_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes TIM Base MSP.
+ * @param htim TIM Base handle
+ * @retval None
+ */
+__weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_Base_MspDeInit could be implemented in the user file
+ */
+}
+
+
+/**
+ * @brief Starts the TIM Base generation.
+ * @param htim TIM Base handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
+{
+ uint32_t tmpsmcr;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+ /* Check the TIM state */
+ if (htim->State != HAL_TIM_STATE_READY)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Set the TIM state */
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Base generation.
+ * @param htim TIM Base handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Set the TIM state */
+ htim->State = HAL_TIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM Base generation in interrupt mode.
+ * @param htim TIM Base handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
+{
+ uint32_t tmpsmcr;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+ /* Check the TIM state */
+ if (htim->State != HAL_TIM_STATE_READY)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Set the TIM state */
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Enable the TIM Update interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
+
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Base generation in interrupt mode.
+ * @param htim TIM Base handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+ /* Disable the TIM Update interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Set the TIM state */
+ htim->State = HAL_TIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM Base generation in DMA mode.
+ * @param htim TIM Base handle
+ * @param pData The source Buffer address.
+ * @param Length The length of data to be transferred from memory to peripheral.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
+{
+ uint32_t tmpsmcr;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
+
+ /* Set the TIM state */
+ if (htim->State == HAL_TIM_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+ else if (htim->State == HAL_TIM_STATE_READY)
+ {
+ if ((pData == NULL) && (Length > 0U))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ htim->State = HAL_TIM_STATE_BUSY;
+ }
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+
+ /* Set the DMA Period elapsed callbacks */
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR,
+ Length) != HAL_OK)
+ {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+
+ /* Enable the TIM Update DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
+
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Base generation in DMA mode.
+ * @param htim TIM Base handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
+
+ /* Disable the TIM Update DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
+
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Set the TIM state */
+ htim->State = HAL_TIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Exported_Functions_Group2 TIM Output Compare functions
+ * @brief TIM Output Compare functions
+ *
+@verbatim
+ ==============================================================================
+ ##### TIM Output Compare functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Initialize and configure the TIM Output Compare.
+ (+) De-initialize the TIM Output Compare.
+ (+) Start the TIM Output Compare.
+ (+) Stop the TIM Output Compare.
+ (+) Start the TIM Output Compare and enable interrupt.
+ (+) Stop the TIM Output Compare and disable interrupt.
+ (+) Start the TIM Output Compare and enable DMA transfer.
+ (+) Stop the TIM Output Compare and disable DMA transfer.
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Initializes the TIM Output Compare according to the specified
+ * parameters in the TIM_HandleTypeDef and initializes the associated handle.
+ * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+ * requires a timer reset to avoid unexpected direction
+ * due to DIR bit readonly in center aligned mode.
+ * Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init()
+ * @param htim TIM Output Compare handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim)
+{
+ /* Check the TIM handle allocation */
+ if (htim == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+ assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+ assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+
+ if (htim->State == HAL_TIM_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ /* Reset interrupt callbacks to legacy weak callbacks */
+ TIM_ResetCallback(htim);
+
+ if (htim->OC_MspInitCallback == NULL)
+ {
+ htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;
+ }
+ /* Init the low level hardware : GPIO, CLOCK, NVIC */
+ htim->OC_MspInitCallback(htim);
+#else
+ /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+ HAL_TIM_OC_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ }
+
+ /* Set the TIM state */
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Init the base time for the Output Compare */
+ TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+ /* Initialize the DMA burst operation state */
+ htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+
+ /* Initialize the TIM channels state */
+ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+
+ /* Initialize the TIM state*/
+ htim->State = HAL_TIM_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the TIM peripheral
+ * @param htim TIM Output Compare handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Disable the TIM Peripheral Clock */
+ __HAL_TIM_DISABLE(htim);
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ if (htim->OC_MspDeInitCallback == NULL)
+ {
+ htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;
+ }
+ /* DeInit the low level hardware */
+ htim->OC_MspDeInitCallback(htim);
+#else
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
+ HAL_TIM_OC_MspDeInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+ /* Change the DMA burst operation state */
+ htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
+
+ /* Change the TIM channels state */
+ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+ TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+
+ /* Change TIM state */
+ htim->State = HAL_TIM_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the TIM Output Compare MSP.
+ * @param htim TIM Output Compare handle
+ * @retval None
+ */
+__weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_OC_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes TIM Output Compare MSP.
+ * @param htim TIM Output Compare handle
+ * @retval None
+ */
+__weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_OC_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Starts the TIM Output Compare signal generation.
+ * @param htim TIM Output Compare handle
+ * @param Channel TIM Channel to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @arg TIM_CHANNEL_5: TIM Channel 5 selected
+ * @arg TIM_CHANNEL_6: TIM Channel 6 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ uint32_t tmpsmcr;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ /* Check the TIM channel state */
+ if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Set the TIM channel state */
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
+ /* Enable the Output compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Enable the main output */
+ __HAL_TIM_MOE_ENABLE(htim);
+ }
+
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Output Compare signal generation.
+ * @param htim TIM Output Compare handle
+ * @param Channel TIM Channel to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @arg TIM_CHANNEL_5: TIM Channel 5 selected
+ * @arg TIM_CHANNEL_6: TIM Channel 6 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ /* Disable the Output compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Disable the Main Output */
+ __HAL_TIM_MOE_DISABLE(htim);
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Set the TIM channel state */
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM Output Compare signal generation in interrupt mode.
+ * @param htim TIM Output Compare handle
+ * @param Channel TIM Channel to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t tmpsmcr;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ /* Check the TIM channel state */
+ if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Set the TIM channel state */
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Enable the TIM Capture/Compare 1 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+ break;
+ }
+
+ case TIM_CHANNEL_2:
+ {
+ /* Enable the TIM Capture/Compare 2 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+ break;
+ }
+
+ case TIM_CHANNEL_3:
+ {
+ /* Enable the TIM Capture/Compare 3 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+ break;
+ }
+
+ case TIM_CHANNEL_4:
+ {
+ /* Enable the TIM Capture/Compare 4 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
+ break;
+ }
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ if (status == HAL_OK)
+ {
+ /* Enable the Output compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Enable the main output */
+ __HAL_TIM_MOE_ENABLE(htim);
+ }
+
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Stops the TIM Output Compare signal generation in interrupt mode.
+ * @param htim TIM Output Compare handle
+ * @param Channel TIM Channel to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Disable the TIM Capture/Compare 1 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+ break;
+ }
+
+ case TIM_CHANNEL_2:
+ {
+ /* Disable the TIM Capture/Compare 2 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+ break;
+ }
+
+ case TIM_CHANNEL_3:
+ {
+ /* Disable the TIM Capture/Compare 3 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+ break;
+ }
+
+ case TIM_CHANNEL_4:
+ {
+ /* Disable the TIM Capture/Compare 4 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
+ break;
+ }
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ if (status == HAL_OK)
+ {
+ /* Disable the Output compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Disable the Main Output */
+ __HAL_TIM_MOE_DISABLE(htim);
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Set the TIM channel state */
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Starts the TIM Output Compare signal generation in DMA mode.
+ * @param htim TIM Output Compare handle
+ * @param Channel TIM Channel to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @param pData The source Buffer address.
+ * @param Length The length of data to be transferred from memory to TIM peripheral
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t tmpsmcr;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ /* Set the TIM channel state */
+ if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+ else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
+ {
+ if ((pData == NULL) && (Length > 0U))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ }
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Set the DMA compare callbacks */
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
+ Length) != HAL_OK)
+ {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+
+ /* Enable the TIM Capture/Compare 1 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+ break;
+ }
+
+ case TIM_CHANNEL_2:
+ {
+ /* Set the DMA compare callbacks */
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
+ Length) != HAL_OK)
+ {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+
+ /* Enable the TIM Capture/Compare 2 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+ break;
+ }
+
+ case TIM_CHANNEL_3:
+ {
+ /* Set the DMA compare callbacks */
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
+ Length) != HAL_OK)
+ {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ /* Enable the TIM Capture/Compare 3 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+ break;
+ }
+
+ case TIM_CHANNEL_4:
+ {
+ /* Set the DMA compare callbacks */
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4,
+ Length) != HAL_OK)
+ {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ /* Enable the TIM Capture/Compare 4 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
+ break;
+ }
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ if (status == HAL_OK)
+ {
+ /* Enable the Output compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Enable the main output */
+ __HAL_TIM_MOE_ENABLE(htim);
+ }
+
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Stops the TIM Output Compare signal generation in DMA mode.
+ * @param htim TIM Output Compare handle
+ * @param Channel TIM Channel to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Disable the TIM Capture/Compare 1 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+ break;
+ }
+
+ case TIM_CHANNEL_2:
+ {
+ /* Disable the TIM Capture/Compare 2 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+ break;
+ }
+
+ case TIM_CHANNEL_3:
+ {
+ /* Disable the TIM Capture/Compare 3 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+ break;
+ }
+
+ case TIM_CHANNEL_4:
+ {
+ /* Disable the TIM Capture/Compare 4 interrupt */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+ break;
+ }
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ if (status == HAL_OK)
+ {
+ /* Disable the Output compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Disable the Main Output */
+ __HAL_TIM_MOE_DISABLE(htim);
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Set the TIM channel state */
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Exported_Functions_Group3 TIM PWM functions
+ * @brief TIM PWM functions
+ *
+@verbatim
+ ==============================================================================
+ ##### TIM PWM functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Initialize and configure the TIM PWM.
+ (+) De-initialize the TIM PWM.
+ (+) Start the TIM PWM.
+ (+) Stop the TIM PWM.
+ (+) Start the TIM PWM and enable interrupt.
+ (+) Stop the TIM PWM and disable interrupt.
+ (+) Start the TIM PWM and enable DMA transfer.
+ (+) Stop the TIM PWM and disable DMA transfer.
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Initializes the TIM PWM Time Base according to the specified
+ * parameters in the TIM_HandleTypeDef and initializes the associated handle.
+ * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+ * requires a timer reset to avoid unexpected direction
+ * due to DIR bit readonly in center aligned mode.
+ * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
+ * @param htim TIM PWM handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
+{
+ /* Check the TIM handle allocation */
+ if (htim == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+ assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+ assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+
+ if (htim->State == HAL_TIM_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ /* Reset interrupt callbacks to legacy weak callbacks */
+ TIM_ResetCallback(htim);
+
+ if (htim->PWM_MspInitCallback == NULL)
+ {
+ htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;
+ }
+ /* Init the low level hardware : GPIO, CLOCK, NVIC */
+ htim->PWM_MspInitCallback(htim);
+#else
+ /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+ HAL_TIM_PWM_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ }
+
+ /* Set the TIM state */
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Init the base time for the PWM */
+ TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+ /* Initialize the DMA burst operation state */
+ htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+
+ /* Initialize the TIM channels state */
+ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+
+ /* Initialize the TIM state*/
+ htim->State = HAL_TIM_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the TIM peripheral
+ * @param htim TIM PWM handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Disable the TIM Peripheral Clock */
+ __HAL_TIM_DISABLE(htim);
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ if (htim->PWM_MspDeInitCallback == NULL)
+ {
+ htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;
+ }
+ /* DeInit the low level hardware */
+ htim->PWM_MspDeInitCallback(htim);
+#else
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
+ HAL_TIM_PWM_MspDeInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+ /* Change the DMA burst operation state */
+ htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
+
+ /* Change the TIM channels state */
+ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+ TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+
+ /* Change TIM state */
+ htim->State = HAL_TIM_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the TIM PWM MSP.
+ * @param htim TIM PWM handle
+ * @retval None
+ */
+__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_PWM_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes TIM PWM MSP.
+ * @param htim TIM PWM handle
+ * @retval None
+ */
+__weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_PWM_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Starts the PWM signal generation.
+ * @param htim TIM handle
+ * @param Channel TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @arg TIM_CHANNEL_5: TIM Channel 5 selected
+ * @arg TIM_CHANNEL_6: TIM Channel 6 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ uint32_t tmpsmcr;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ /* Check the TIM channel state */
+ if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Set the TIM channel state */
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
+ /* Enable the Capture compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Enable the main output */
+ __HAL_TIM_MOE_ENABLE(htim);
+ }
+
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the PWM signal generation.
+ * @param htim TIM PWM handle
+ * @param Channel TIM Channels to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @arg TIM_CHANNEL_5: TIM Channel 5 selected
+ * @arg TIM_CHANNEL_6: TIM Channel 6 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ /* Disable the Capture compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Disable the Main Output */
+ __HAL_TIM_MOE_DISABLE(htim);
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Set the TIM channel state */
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the PWM signal generation in interrupt mode.
+ * @param htim TIM PWM handle
+ * @param Channel TIM Channel to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t tmpsmcr;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ /* Check the TIM channel state */
+ if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Set the TIM channel state */
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Enable the TIM Capture/Compare 1 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+ break;
+ }
+
+ case TIM_CHANNEL_2:
+ {
+ /* Enable the TIM Capture/Compare 2 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+ break;
+ }
+
+ case TIM_CHANNEL_3:
+ {
+ /* Enable the TIM Capture/Compare 3 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+ break;
+ }
+
+ case TIM_CHANNEL_4:
+ {
+ /* Enable the TIM Capture/Compare 4 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
+ break;
+ }
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ if (status == HAL_OK)
+ {
+ /* Enable the Capture compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Enable the main output */
+ __HAL_TIM_MOE_ENABLE(htim);
+ }
+
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Stops the PWM signal generation in interrupt mode.
+ * @param htim TIM PWM handle
+ * @param Channel TIM Channels to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Disable the TIM Capture/Compare 1 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+ break;
+ }
+
+ case TIM_CHANNEL_2:
+ {
+ /* Disable the TIM Capture/Compare 2 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+ break;
+ }
+
+ case TIM_CHANNEL_3:
+ {
+ /* Disable the TIM Capture/Compare 3 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+ break;
+ }
+
+ case TIM_CHANNEL_4:
+ {
+ /* Disable the TIM Capture/Compare 4 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
+ break;
+ }
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ if (status == HAL_OK)
+ {
+ /* Disable the Capture compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Disable the Main Output */
+ __HAL_TIM_MOE_DISABLE(htim);
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Set the TIM channel state */
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Starts the TIM PWM signal generation in DMA mode.
+ * @param htim TIM PWM handle
+ * @param Channel TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @param pData The source Buffer address.
+ * @param Length The length of data to be transferred from memory to TIM peripheral
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t tmpsmcr;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ /* Set the TIM channel state */
+ if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+ else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
+ {
+ if ((pData == NULL) && (Length > 0U))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ }
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Set the DMA compare callbacks */
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
+ Length) != HAL_OK)
+ {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+
+ /* Enable the TIM Capture/Compare 1 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+ break;
+ }
+
+ case TIM_CHANNEL_2:
+ {
+ /* Set the DMA compare callbacks */
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
+ Length) != HAL_OK)
+ {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ /* Enable the TIM Capture/Compare 2 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+ break;
+ }
+
+ case TIM_CHANNEL_3:
+ {
+ /* Set the DMA compare callbacks */
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
+ Length) != HAL_OK)
+ {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ /* Enable the TIM Output Capture/Compare 3 request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+ break;
+ }
+
+ case TIM_CHANNEL_4:
+ {
+ /* Set the DMA compare callbacks */
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4,
+ Length) != HAL_OK)
+ {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ /* Enable the TIM Capture/Compare 4 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
+ break;
+ }
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ if (status == HAL_OK)
+ {
+ /* Enable the Capture compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Enable the main output */
+ __HAL_TIM_MOE_ENABLE(htim);
+ }
+
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Stops the TIM PWM signal generation in DMA mode.
+ * @param htim TIM PWM handle
+ * @param Channel TIM Channels to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Disable the TIM Capture/Compare 1 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+ break;
+ }
+
+ case TIM_CHANNEL_2:
+ {
+ /* Disable the TIM Capture/Compare 2 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+ break;
+ }
+
+ case TIM_CHANNEL_3:
+ {
+ /* Disable the TIM Capture/Compare 3 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+ break;
+ }
+
+ case TIM_CHANNEL_4:
+ {
+ /* Disable the TIM Capture/Compare 4 interrupt */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+ break;
+ }
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ if (status == HAL_OK)
+ {
+ /* Disable the Capture compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Disable the Main Output */
+ __HAL_TIM_MOE_DISABLE(htim);
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Set the TIM channel state */
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Exported_Functions_Group4 TIM Input Capture functions
+ * @brief TIM Input Capture functions
+ *
+@verbatim
+ ==============================================================================
+ ##### TIM Input Capture functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Initialize and configure the TIM Input Capture.
+ (+) De-initialize the TIM Input Capture.
+ (+) Start the TIM Input Capture.
+ (+) Stop the TIM Input Capture.
+ (+) Start the TIM Input Capture and enable interrupt.
+ (+) Stop the TIM Input Capture and disable interrupt.
+ (+) Start the TIM Input Capture and enable DMA transfer.
+ (+) Stop the TIM Input Capture and disable DMA transfer.
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Initializes the TIM Input Capture Time base according to the specified
+ * parameters in the TIM_HandleTypeDef and initializes the associated handle.
+ * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+ * requires a timer reset to avoid unexpected direction
+ * due to DIR bit readonly in center aligned mode.
+ * Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init()
+ * @param htim TIM Input Capture handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
+{
+ /* Check the TIM handle allocation */
+ if (htim == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+ assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+ assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+
+ if (htim->State == HAL_TIM_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ /* Reset interrupt callbacks to legacy weak callbacks */
+ TIM_ResetCallback(htim);
+
+ if (htim->IC_MspInitCallback == NULL)
+ {
+ htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;
+ }
+ /* Init the low level hardware : GPIO, CLOCK, NVIC */
+ htim->IC_MspInitCallback(htim);
+#else
+ /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+ HAL_TIM_IC_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ }
+
+ /* Set the TIM state */
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Init the base time for the input capture */
+ TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+ /* Initialize the DMA burst operation state */
+ htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+
+ /* Initialize the TIM channels state */
+ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+
+ /* Initialize the TIM state*/
+ htim->State = HAL_TIM_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the TIM peripheral
+ * @param htim TIM Input Capture handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Disable the TIM Peripheral Clock */
+ __HAL_TIM_DISABLE(htim);
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ if (htim->IC_MspDeInitCallback == NULL)
+ {
+ htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;
+ }
+ /* DeInit the low level hardware */
+ htim->IC_MspDeInitCallback(htim);
+#else
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
+ HAL_TIM_IC_MspDeInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+ /* Change the DMA burst operation state */
+ htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
+
+ /* Change the TIM channels state */
+ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+ TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+
+ /* Change TIM state */
+ htim->State = HAL_TIM_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the TIM Input Capture MSP.
+ * @param htim TIM Input Capture handle
+ * @retval None
+ */
+__weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_IC_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes TIM Input Capture MSP.
+ * @param htim TIM handle
+ * @retval None
+ */
+__weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_IC_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Starts the TIM Input Capture measurement.
+ * @param htim TIM Input Capture handle
+ * @param Channel TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ uint32_t tmpsmcr;
+ HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ /* Check the TIM channel state */
+ if ((channel_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Set the TIM channel state */
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
+ /* Enable the Input Capture channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Input Capture measurement.
+ * @param htim TIM Input Capture handle
+ * @param Channel TIM Channels to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ /* Disable the Input Capture channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Set the TIM channel state */
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM Input Capture measurement in interrupt mode.
+ * @param htim TIM Input Capture handle
+ * @param Channel TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t tmpsmcr;
+
+ HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ /* Check the TIM channel state */
+ if ((channel_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Set the TIM channel state */
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Enable the TIM Capture/Compare 1 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+ break;
+ }
+
+ case TIM_CHANNEL_2:
+ {
+ /* Enable the TIM Capture/Compare 2 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+ break;
+ }
+
+ case TIM_CHANNEL_3:
+ {
+ /* Enable the TIM Capture/Compare 3 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+ break;
+ }
+
+ case TIM_CHANNEL_4:
+ {
+ /* Enable the TIM Capture/Compare 4 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
+ break;
+ }
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ if (status == HAL_OK)
+ {
+ /* Enable the Input Capture channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Stops the TIM Input Capture measurement in interrupt mode.
+ * @param htim TIM Input Capture handle
+ * @param Channel TIM Channels to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Disable the TIM Capture/Compare 1 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+ break;
+ }
+
+ case TIM_CHANNEL_2:
+ {
+ /* Disable the TIM Capture/Compare 2 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+ break;
+ }
+
+ case TIM_CHANNEL_3:
+ {
+ /* Disable the TIM Capture/Compare 3 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+ break;
+ }
+
+ case TIM_CHANNEL_4:
+ {
+ /* Disable the TIM Capture/Compare 4 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
+ break;
+ }
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ if (status == HAL_OK)
+ {
+ /* Disable the Input Capture channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Set the TIM channel state */
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Starts the TIM Input Capture measurement in DMA mode.
+ * @param htim TIM Input Capture handle
+ * @param Channel TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @param pData The destination Buffer address.
+ * @param Length The length of data to be transferred from TIM peripheral to memory.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t tmpsmcr;
+
+ HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+ assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
+
+ /* Set the TIM channel state */
+ if ((channel_state == HAL_TIM_CHANNEL_STATE_BUSY)
+ || (complementary_channel_state == HAL_TIM_CHANNEL_STATE_BUSY))
+ {
+ return HAL_BUSY;
+ }
+ else if ((channel_state == HAL_TIM_CHANNEL_STATE_READY)
+ && (complementary_channel_state == HAL_TIM_CHANNEL_STATE_READY))
+ {
+ if ((pData == NULL) && (Length > 0U))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ }
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+
+ /* Enable the Input Capture channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Set the DMA capture callbacks */
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData,
+ Length) != HAL_OK)
+ {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ /* Enable the TIM Capture/Compare 1 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+ break;
+ }
+
+ case TIM_CHANNEL_2:
+ {
+ /* Set the DMA capture callbacks */
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData,
+ Length) != HAL_OK)
+ {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ /* Enable the TIM Capture/Compare 2 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+ break;
+ }
+
+ case TIM_CHANNEL_3:
+ {
+ /* Set the DMA capture callbacks */
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData,
+ Length) != HAL_OK)
+ {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ /* Enable the TIM Capture/Compare 3 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+ break;
+ }
+
+ case TIM_CHANNEL_4:
+ {
+ /* Set the DMA capture callbacks */
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData,
+ Length) != HAL_OK)
+ {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ /* Enable the TIM Capture/Compare 4 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
+ break;
+ }
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Stops the TIM Input Capture measurement in DMA mode.
+ * @param htim TIM Input Capture handle
+ * @param Channel TIM Channels to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+ assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
+
+ /* Disable the Input Capture channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Disable the TIM Capture/Compare 1 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+ break;
+ }
+
+ case TIM_CHANNEL_2:
+ {
+ /* Disable the TIM Capture/Compare 2 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+ break;
+ }
+
+ case TIM_CHANNEL_3:
+ {
+ /* Disable the TIM Capture/Compare 3 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+ break;
+ }
+
+ case TIM_CHANNEL_4:
+ {
+ /* Disable the TIM Capture/Compare 4 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+ break;
+ }
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ if (status == HAL_OK)
+ {
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Set the TIM channel state */
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ }
+
+ /* Return function status */
+ return status;
+}
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Exported_Functions_Group5 TIM One Pulse functions
+ * @brief TIM One Pulse functions
+ *
+@verbatim
+ ==============================================================================
+ ##### TIM One Pulse functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Initialize and configure the TIM One Pulse.
+ (+) De-initialize the TIM One Pulse.
+ (+) Start the TIM One Pulse.
+ (+) Stop the TIM One Pulse.
+ (+) Start the TIM One Pulse and enable interrupt.
+ (+) Stop the TIM One Pulse and disable interrupt.
+ (+) Start the TIM One Pulse and enable DMA transfer.
+ (+) Stop the TIM One Pulse and disable DMA transfer.
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Initializes the TIM One Pulse Time Base according to the specified
+ * parameters in the TIM_HandleTypeDef and initializes the associated handle.
+ * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+ * requires a timer reset to avoid unexpected direction
+ * due to DIR bit readonly in center aligned mode.
+ * Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init()
+ * @note When the timer instance is initialized in One Pulse mode, timer
+ * channels 1 and channel 2 are reserved and cannot be used for other
+ * purpose.
+ * @param htim TIM One Pulse handle
+ * @param OnePulseMode Select the One pulse mode.
+ * This parameter can be one of the following values:
+ * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
+ * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
+{
+ /* Check the TIM handle allocation */
+ if (htim == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+ assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+ assert_param(IS_TIM_OPM_MODE(OnePulseMode));
+ assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+
+ if (htim->State == HAL_TIM_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ /* Reset interrupt callbacks to legacy weak callbacks */
+ TIM_ResetCallback(htim);
+
+ if (htim->OnePulse_MspInitCallback == NULL)
+ {
+ htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;
+ }
+ /* Init the low level hardware : GPIO, CLOCK, NVIC */
+ htim->OnePulse_MspInitCallback(htim);
+#else
+ /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+ HAL_TIM_OnePulse_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ }
+
+ /* Set the TIM state */
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Configure the Time base in the One Pulse Mode */
+ TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+ /* Reset the OPM Bit */
+ htim->Instance->CR1 &= ~TIM_CR1_OPM;
+
+ /* Configure the OPM Mode */
+ htim->Instance->CR1 |= OnePulseMode;
+
+ /* Initialize the DMA burst operation state */
+ htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+
+ /* Initialize the TIM channels state */
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+
+ /* Initialize the TIM state*/
+ htim->State = HAL_TIM_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the TIM One Pulse
+ * @param htim TIM One Pulse handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Disable the TIM Peripheral Clock */
+ __HAL_TIM_DISABLE(htim);
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ if (htim->OnePulse_MspDeInitCallback == NULL)
+ {
+ htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;
+ }
+ /* DeInit the low level hardware */
+ htim->OnePulse_MspDeInitCallback(htim);
+#else
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+ HAL_TIM_OnePulse_MspDeInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+ /* Change the DMA burst operation state */
+ htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
+
+ /* Set the TIM channel state */
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
+
+ /* Change TIM state */
+ htim->State = HAL_TIM_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the TIM One Pulse MSP.
+ * @param htim TIM One Pulse handle
+ * @retval None
+ */
+__weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_OnePulse_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes TIM One Pulse MSP.
+ * @param htim TIM One Pulse handle
+ * @retval None
+ */
+__weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Starts the TIM One Pulse signal generation.
+ * @note Though OutputChannel parameter is deprecated and ignored by the function
+ * it has been kept to avoid HAL_TIM API compatibility break.
+ * @note The pulse output channel is determined when calling
+ * @ref HAL_TIM_OnePulse_ConfigChannel().
+ * @param htim TIM One Pulse handle
+ * @param OutputChannel See note above
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+ HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
+
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(OutputChannel);
+
+ /* Check the TIM channels state */
+ if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Set the TIM channels state */
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+
+ /* Enable the Capture compare and the Input Capture channels
+ (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
+ if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
+ if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
+ whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
+
+ No need to enable the counter, it's enabled automatically by hardware
+ (the counter starts in response to a stimulus and generate a pulse */
+
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Enable the main output */
+ __HAL_TIM_MOE_ENABLE(htim);
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM One Pulse signal generation.
+ * @note Though OutputChannel parameter is deprecated and ignored by the function
+ * it has been kept to avoid HAL_TIM API compatibility break.
+ * @note The pulse output channel is determined when calling
+ * @ref HAL_TIM_OnePulse_ConfigChannel().
+ * @param htim TIM One Pulse handle
+ * @param OutputChannel See note above
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(OutputChannel);
+
+ /* Disable the Capture compare and the Input Capture channels
+ (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
+ if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
+ if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
+ whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
+
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Disable the Main Output */
+ __HAL_TIM_MOE_DISABLE(htim);
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Set the TIM channels state */
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM One Pulse signal generation in interrupt mode.
+ * @note Though OutputChannel parameter is deprecated and ignored by the function
+ * it has been kept to avoid HAL_TIM API compatibility break.
+ * @note The pulse output channel is determined when calling
+ * @ref HAL_TIM_OnePulse_ConfigChannel().
+ * @param htim TIM One Pulse handle
+ * @param OutputChannel See note above
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+ HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
+
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(OutputChannel);
+
+ /* Check the TIM channels state */
+ if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Set the TIM channels state */
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+
+ /* Enable the Capture compare and the Input Capture channels
+ (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
+ if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
+ if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
+ whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
+
+ No need to enable the counter, it's enabled automatically by hardware
+ (the counter starts in response to a stimulus and generate a pulse */
+
+ /* Enable the TIM Capture/Compare 1 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+
+ /* Enable the TIM Capture/Compare 2 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Enable the main output */
+ __HAL_TIM_MOE_ENABLE(htim);
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM One Pulse signal generation in interrupt mode.
+ * @note Though OutputChannel parameter is deprecated and ignored by the function
+ * it has been kept to avoid HAL_TIM API compatibility break.
+ * @note The pulse output channel is determined when calling
+ * @ref HAL_TIM_OnePulse_ConfigChannel().
+ * @param htim TIM One Pulse handle
+ * @param OutputChannel See note above
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(OutputChannel);
+
+ /* Disable the TIM Capture/Compare 1 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+
+ /* Disable the TIM Capture/Compare 2 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+
+ /* Disable the Capture compare and the Input Capture channels
+ (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
+ if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
+ if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
+ whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Disable the Main Output */
+ __HAL_TIM_MOE_DISABLE(htim);
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Set the TIM channels state */
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Exported_Functions_Group6 TIM Encoder functions
+ * @brief TIM Encoder functions
+ *
+@verbatim
+ ==============================================================================
+ ##### TIM Encoder functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Initialize and configure the TIM Encoder.
+ (+) De-initialize the TIM Encoder.
+ (+) Start the TIM Encoder.
+ (+) Stop the TIM Encoder.
+ (+) Start the TIM Encoder and enable interrupt.
+ (+) Stop the TIM Encoder and disable interrupt.
+ (+) Start the TIM Encoder and enable DMA transfer.
+ (+) Stop the TIM Encoder and disable DMA transfer.
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Initializes the TIM Encoder Interface and initialize the associated handle.
+ * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+ * requires a timer reset to avoid unexpected direction
+ * due to DIR bit readonly in center aligned mode.
+ * Ex: call @ref HAL_TIM_Encoder_DeInit() before HAL_TIM_Encoder_Init()
+ * @note Encoder mode and External clock mode 2 are not compatible and must not be selected together
+ * Ex: A call for @ref HAL_TIM_Encoder_Init will erase the settings of @ref HAL_TIM_ConfigClockSource
+ * using TIM_CLOCKSOURCE_ETRMODE2 and vice versa
+ * @note When the timer instance is initialized in Encoder mode, timer
+ * channels 1 and channel 2 are reserved and cannot be used for other
+ * purpose.
+ * @param htim TIM Encoder Interface handle
+ * @param sConfig TIM Encoder Interface configuration structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig)
+{
+ uint32_t tmpsmcr;
+ uint32_t tmpccmr1;
+ uint32_t tmpccer;
+
+ /* Check the TIM handle allocation */
+ if (htim == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+ assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+ assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+ assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
+ assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
+ assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
+ assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC1Polarity));
+ assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC2Polarity));
+ assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
+ assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
+ assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
+ assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
+
+ if (htim->State == HAL_TIM_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ /* Reset interrupt callbacks to legacy weak callbacks */
+ TIM_ResetCallback(htim);
+
+ if (htim->Encoder_MspInitCallback == NULL)
+ {
+ htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;
+ }
+ /* Init the low level hardware : GPIO, CLOCK, NVIC */
+ htim->Encoder_MspInitCallback(htim);
+#else
+ /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+ HAL_TIM_Encoder_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ }
+
+ /* Set the TIM state */
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Reset the SMS and ECE bits */
+ htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE);
+
+ /* Configure the Time base in the Encoder Mode */
+ TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+ /* Get the TIMx SMCR register value */
+ tmpsmcr = htim->Instance->SMCR;
+
+ /* Get the TIMx CCMR1 register value */
+ tmpccmr1 = htim->Instance->CCMR1;
+
+ /* Get the TIMx CCER register value */
+ tmpccer = htim->Instance->CCER;
+
+ /* Set the encoder Mode */
+ tmpsmcr |= sConfig->EncoderMode;
+
+ /* Select the Capture Compare 1 and the Capture Compare 2 as input */
+ tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
+ tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U));
+
+ /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
+ tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
+ tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
+ tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U);
+ tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);
+
+ /* Set the TI1 and the TI2 Polarities */
+ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
+ tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
+ tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U);
+
+ /* Write to TIMx SMCR */
+ htim->Instance->SMCR = tmpsmcr;
+
+ /* Write to TIMx CCMR1 */
+ htim->Instance->CCMR1 = tmpccmr1;
+
+ /* Write to TIMx CCER */
+ htim->Instance->CCER = tmpccer;
+
+ /* Initialize the DMA burst operation state */
+ htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+
+ /* Set the TIM channels state */
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+
+ /* Initialize the TIM state*/
+ htim->State = HAL_TIM_STATE_READY;
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief DeInitializes the TIM Encoder interface
+ * @param htim TIM Encoder Interface handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Disable the TIM Peripheral Clock */
+ __HAL_TIM_DISABLE(htim);
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ if (htim->Encoder_MspDeInitCallback == NULL)
+ {
+ htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;
+ }
+ /* DeInit the low level hardware */
+ htim->Encoder_MspDeInitCallback(htim);
+#else
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+ HAL_TIM_Encoder_MspDeInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+ /* Change the DMA burst operation state */
+ htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
+
+ /* Set the TIM channels state */
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
+
+ /* Change TIM state */
+ htim->State = HAL_TIM_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the TIM Encoder Interface MSP.
+ * @param htim TIM Encoder Interface handle
+ * @retval None
+ */
+__weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_Encoder_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes TIM Encoder Interface MSP.
+ * @param htim TIM Encoder Interface handle
+ * @retval None
+ */
+__weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Starts the TIM Encoder Interface.
+ * @param htim TIM Encoder Interface handle
+ * @param Channel TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
+
+ /* Check the parameters */
+ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+
+ /* Set the TIM channel(s) state */
+ if (Channel == TIM_CHANNEL_1)
+ {
+ if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ }
+ }
+ else if (Channel == TIM_CHANNEL_2)
+ {
+ if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ }
+ }
+ else
+ {
+ if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ }
+ }
+
+ /* Enable the encoder interface channels */
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+ break;
+ }
+
+ case TIM_CHANNEL_2:
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+ break;
+ }
+
+ default :
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+ break;
+ }
+ }
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Encoder Interface.
+ * @param htim TIM Encoder Interface handle
+ * @param Channel TIM Channels to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+
+ /* Disable the Input Capture channels 1 and 2
+ (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+ break;
+ }
+
+ case TIM_CHANNEL_2:
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+ break;
+ }
+
+ default :
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+ break;
+ }
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Set the TIM channel(s) state */
+ if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
+ {
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ }
+ else
+ {
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM Encoder Interface in interrupt mode.
+ * @param htim TIM Encoder Interface handle
+ * @param Channel TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
+
+ /* Check the parameters */
+ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+
+ /* Set the TIM channel(s) state */
+ if (Channel == TIM_CHANNEL_1)
+ {
+ if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ }
+ }
+ else if (Channel == TIM_CHANNEL_2)
+ {
+ if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ }
+ }
+ else
+ {
+ if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ }
+ }
+
+ /* Enable the encoder interface channels */
+ /* Enable the capture compare Interrupts 1 and/or 2 */
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+ break;
+ }
+
+ case TIM_CHANNEL_2:
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+ break;
+ }
+
+ default :
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+ break;
+ }
+ }
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Encoder Interface in interrupt mode.
+ * @param htim TIM Encoder Interface handle
+ * @param Channel TIM Channels to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+
+ /* Disable the Input Capture channels 1 and 2
+ (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
+ if (Channel == TIM_CHANNEL_1)
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+
+ /* Disable the capture compare Interrupts 1 */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+ }
+ else if (Channel == TIM_CHANNEL_2)
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+ /* Disable the capture compare Interrupts 2 */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+ }
+ else
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+ /* Disable the capture compare Interrupts 1 and 2 */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Set the TIM channel(s) state */
+ if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
+ {
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ }
+ else
+ {
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM Encoder Interface in DMA mode.
+ * @param htim TIM Encoder Interface handle
+ * @param Channel TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+ * @param pData1 The destination Buffer address for IC1.
+ * @param pData2 The destination Buffer address for IC2.
+ * @param Length The length of data to be transferred from TIM peripheral to memory.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,
+ uint32_t *pData2, uint16_t Length)
+{
+ HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
+
+ /* Check the parameters */
+ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+
+ /* Set the TIM channel(s) state */
+ if (Channel == TIM_CHANNEL_1)
+ {
+ if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
+ || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY))
+ {
+ return HAL_BUSY;
+ }
+ else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
+ && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY))
+ {
+ if ((pData1 == NULL) && (Length > 0U))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ }
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+ }
+ else if (Channel == TIM_CHANNEL_2)
+ {
+ if ((channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)
+ || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY))
+ {
+ return HAL_BUSY;
+ }
+ else if ((channel_2_state == HAL_TIM_CHANNEL_STATE_READY)
+ && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
+ {
+ if ((pData2 == NULL) && (Length > 0U))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ }
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
+ || (channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)
+ || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
+ || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY))
+ {
+ return HAL_BUSY;
+ }
+ else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
+ && (channel_2_state == HAL_TIM_CHANNEL_STATE_READY)
+ && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
+ && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
+ {
+ if ((((pData1 == NULL) || (pData2 == NULL))) && (Length > 0U))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ }
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+ }
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Set the DMA capture callbacks */
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1,
+ Length) != HAL_OK)
+ {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ /* Enable the TIM Input Capture DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+
+ /* Enable the Capture compare channel */
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ break;
+ }
+
+ case TIM_CHANNEL_2:
+ {
+ /* Set the DMA capture callbacks */
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2,
+ Length) != HAL_OK)
+ {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ /* Enable the TIM Input Capture DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+
+ /* Enable the Capture compare channel */
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ break;
+ }
+
+ default:
+ {
+ /* Set the DMA capture callbacks */
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1,
+ Length) != HAL_OK)
+ {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+
+ /* Set the DMA capture callbacks */
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2,
+ Length) != HAL_OK)
+ {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+
+ /* Enable the TIM Input Capture DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+ /* Enable the TIM Input Capture DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+
+ /* Enable the Capture compare channel */
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ break;
+ }
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Encoder Interface in DMA mode.
+ * @param htim TIM Encoder Interface handle
+ * @param Channel TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+
+ /* Disable the Input Capture channels 1 and 2
+ (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
+ if (Channel == TIM_CHANNEL_1)
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+
+ /* Disable the capture compare DMA Request 1 */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+ }
+ else if (Channel == TIM_CHANNEL_2)
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+ /* Disable the capture compare DMA Request 2 */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+ }
+ else
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+ /* Disable the capture compare DMA Request 1 and 2 */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Set the TIM channel(s) state */
+ if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
+ {
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ }
+ else
+ {
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
+ * @brief TIM IRQ handler management
+ *
+@verbatim
+ ==============================================================================
+ ##### IRQ handler management #####
+ ==============================================================================
+ [..]
+ This section provides Timer IRQ handler function.
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief This function handles TIM interrupts requests.
+ * @param htim TIM handle
+ * @retval None
+ */
+void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
+{
+ /* Capture compare 1 event */
+ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
+ {
+ if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET)
+ {
+ {
+ __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+
+ /* Input capture event */
+ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
+ {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->IC_CaptureCallback(htim);
+#else
+ HAL_TIM_IC_CaptureCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ }
+ /* Output compare event */
+ else
+ {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->OC_DelayElapsedCallback(htim);
+ htim->PWM_PulseFinishedCallback(htim);
+#else
+ HAL_TIM_OC_DelayElapsedCallback(htim);
+ HAL_TIM_PWM_PulseFinishedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ }
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+ }
+ }
+ }
+ /* Capture compare 2 event */
+ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
+ {
+ if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET)
+ {
+ __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+ /* Input capture event */
+ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
+ {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->IC_CaptureCallback(htim);
+#else
+ HAL_TIM_IC_CaptureCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ }
+ /* Output compare event */
+ else
+ {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->OC_DelayElapsedCallback(htim);
+ htim->PWM_PulseFinishedCallback(htim);
+#else
+ HAL_TIM_OC_DelayElapsedCallback(htim);
+ HAL_TIM_PWM_PulseFinishedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ }
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+ }
+ }
+ /* Capture compare 3 event */
+ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
+ {
+ if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET)
+ {
+ __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+ /* Input capture event */
+ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
+ {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->IC_CaptureCallback(htim);
+#else
+ HAL_TIM_IC_CaptureCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ }
+ /* Output compare event */
+ else
+ {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->OC_DelayElapsedCallback(htim);
+ htim->PWM_PulseFinishedCallback(htim);
+#else
+ HAL_TIM_OC_DelayElapsedCallback(htim);
+ HAL_TIM_PWM_PulseFinishedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ }
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+ }
+ }
+ /* Capture compare 4 event */
+ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
+ {
+ if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET)
+ {
+ __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+ /* Input capture event */
+ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
+ {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->IC_CaptureCallback(htim);
+#else
+ HAL_TIM_IC_CaptureCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ }
+ /* Output compare event */
+ else
+ {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->OC_DelayElapsedCallback(htim);
+ htim->PWM_PulseFinishedCallback(htim);
+#else
+ HAL_TIM_OC_DelayElapsedCallback(htim);
+ HAL_TIM_PWM_PulseFinishedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ }
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+ }
+ }
+ /* TIM Update event */
+ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
+ {
+ if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET)
+ {
+ __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->PeriodElapsedCallback(htim);
+#else
+ HAL_TIM_PeriodElapsedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ }
+ }
+ /* TIM Break input event */
+ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
+ {
+ if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
+ {
+ __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->BreakCallback(htim);
+#else
+ HAL_TIMEx_BreakCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ }
+ }
+ /* TIM Break2 input event */
+ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK2) != RESET)
+ {
+ if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
+ {
+ __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->Break2Callback(htim);
+#else
+ HAL_TIMEx_Break2Callback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ }
+ }
+ /* TIM Trigger detection event */
+ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
+ {
+ if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET)
+ {
+ __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->TriggerCallback(htim);
+#else
+ HAL_TIM_TriggerCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ }
+ }
+ /* TIM commutation event */
+ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
+ {
+ if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET)
+ {
+ __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->CommutationCallback(htim);
+#else
+ HAL_TIMEx_CommutCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ }
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions
+ * @brief TIM Peripheral Control functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral Control functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
+ (+) Configure External Clock source.
+ (+) Configure Complementary channels, break features and dead time.
+ (+) Configure Master and the Slave synchronization.
+ (+) Configure the DMA Burst Mode.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the TIM Output Compare Channels according to the specified
+ * parameters in the TIM_OC_InitTypeDef.
+ * @param htim TIM Output Compare handle
+ * @param sConfig TIM Output Compare configuration structure
+ * @param Channel TIM Channels to configure
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @arg TIM_CHANNEL_5: TIM Channel 5 selected
+ * @arg TIM_CHANNEL_6: TIM Channel 6 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim,
+ TIM_OC_InitTypeDef *sConfig,
+ uint32_t Channel)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CHANNELS(Channel));
+ assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
+ assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
+
+ /* Process Locked */
+ __HAL_LOCK(htim);
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+
+ /* Configure the TIM Channel 1 in Output Compare */
+ TIM_OC1_SetConfig(htim->Instance, sConfig);
+ break;
+ }
+
+ case TIM_CHANNEL_2:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+ /* Configure the TIM Channel 2 in Output Compare */
+ TIM_OC2_SetConfig(htim->Instance, sConfig);
+ break;
+ }
+
+ case TIM_CHANNEL_3:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+
+ /* Configure the TIM Channel 3 in Output Compare */
+ TIM_OC3_SetConfig(htim->Instance, sConfig);
+ break;
+ }
+
+ case TIM_CHANNEL_4:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+
+ /* Configure the TIM Channel 4 in Output Compare */
+ TIM_OC4_SetConfig(htim->Instance, sConfig);
+ break;
+ }
+
+ case TIM_CHANNEL_5:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
+
+ /* Configure the TIM Channel 5 in Output Compare */
+ TIM_OC5_SetConfig(htim->Instance, sConfig);
+ break;
+ }
+
+ case TIM_CHANNEL_6:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
+
+ /* Configure the TIM Channel 6 in Output Compare */
+ TIM_OC6_SetConfig(htim->Instance, sConfig);
+ break;
+ }
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ __HAL_UNLOCK(htim);
+
+ return status;
+}
+
+/**
+ * @brief Initializes the TIM Input Capture Channels according to the specified
+ * parameters in the TIM_IC_InitTypeDef.
+ * @param htim TIM IC handle
+ * @param sConfig TIM Input Capture configuration structure
+ * @param Channel TIM Channel to configure
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
+ assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
+ assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
+ assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
+
+ /* Process Locked */
+ __HAL_LOCK(htim);
+
+ if (Channel == TIM_CHANNEL_1)
+ {
+ /* TI1 Configuration */
+ TIM_TI1_SetConfig(htim->Instance,
+ sConfig->ICPolarity,
+ sConfig->ICSelection,
+ sConfig->ICFilter);
+
+ /* Reset the IC1PSC Bits */
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
+
+ /* Set the IC1PSC value */
+ htim->Instance->CCMR1 |= sConfig->ICPrescaler;
+ }
+ else if (Channel == TIM_CHANNEL_2)
+ {
+ /* TI2 Configuration */
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+ TIM_TI2_SetConfig(htim->Instance,
+ sConfig->ICPolarity,
+ sConfig->ICSelection,
+ sConfig->ICFilter);
+
+ /* Reset the IC2PSC Bits */
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
+
+ /* Set the IC2PSC value */
+ htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U);
+ }
+ else if (Channel == TIM_CHANNEL_3)
+ {
+ /* TI3 Configuration */
+ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+
+ TIM_TI3_SetConfig(htim->Instance,
+ sConfig->ICPolarity,
+ sConfig->ICSelection,
+ sConfig->ICFilter);
+
+ /* Reset the IC3PSC Bits */
+ htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
+
+ /* Set the IC3PSC value */
+ htim->Instance->CCMR2 |= sConfig->ICPrescaler;
+ }
+ else if (Channel == TIM_CHANNEL_4)
+ {
+ /* TI4 Configuration */
+ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+
+ TIM_TI4_SetConfig(htim->Instance,
+ sConfig->ICPolarity,
+ sConfig->ICSelection,
+ sConfig->ICFilter);
+
+ /* Reset the IC4PSC Bits */
+ htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
+
+ /* Set the IC4PSC value */
+ htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U);
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+
+ __HAL_UNLOCK(htim);
+
+ return status;
+}
+
+/**
+ * @brief Initializes the TIM PWM channels according to the specified
+ * parameters in the TIM_OC_InitTypeDef.
+ * @param htim TIM PWM handle
+ * @param sConfig TIM PWM configuration structure
+ * @param Channel TIM Channels to be configured
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @arg TIM_CHANNEL_5: TIM Channel 5 selected
+ * @arg TIM_CHANNEL_6: TIM Channel 6 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
+ TIM_OC_InitTypeDef *sConfig,
+ uint32_t Channel)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CHANNELS(Channel));
+ assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
+ assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
+ assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
+
+ /* Process Locked */
+ __HAL_LOCK(htim);
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+
+ /* Configure the Channel 1 in PWM mode */
+ TIM_OC1_SetConfig(htim->Instance, sConfig);
+
+ /* Set the Preload enable bit for channel1 */
+ htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
+
+ /* Configure the Output Fast mode */
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
+ htim->Instance->CCMR1 |= sConfig->OCFastMode;
+ break;
+ }
+
+ case TIM_CHANNEL_2:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+ /* Configure the Channel 2 in PWM mode */
+ TIM_OC2_SetConfig(htim->Instance, sConfig);
+
+ /* Set the Preload enable bit for channel2 */
+ htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
+
+ /* Configure the Output Fast mode */
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
+ htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
+ break;
+ }
+
+ case TIM_CHANNEL_3:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+
+ /* Configure the Channel 3 in PWM mode */
+ TIM_OC3_SetConfig(htim->Instance, sConfig);
+
+ /* Set the Preload enable bit for channel3 */
+ htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
+
+ /* Configure the Output Fast mode */
+ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
+ htim->Instance->CCMR2 |= sConfig->OCFastMode;
+ break;
+ }
+
+ case TIM_CHANNEL_4:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+
+ /* Configure the Channel 4 in PWM mode */
+ TIM_OC4_SetConfig(htim->Instance, sConfig);
+
+ /* Set the Preload enable bit for channel4 */
+ htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
+
+ /* Configure the Output Fast mode */
+ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
+ htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
+ break;
+ }
+
+ case TIM_CHANNEL_5:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
+
+ /* Configure the Channel 5 in PWM mode */
+ TIM_OC5_SetConfig(htim->Instance, sConfig);
+
+ /* Set the Preload enable bit for channel5*/
+ htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE;
+
+ /* Configure the Output Fast mode */
+ htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE;
+ htim->Instance->CCMR3 |= sConfig->OCFastMode;
+ break;
+ }
+
+ case TIM_CHANNEL_6:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
+
+ /* Configure the Channel 6 in PWM mode */
+ TIM_OC6_SetConfig(htim->Instance, sConfig);
+
+ /* Set the Preload enable bit for channel6 */
+ htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE;
+
+ /* Configure the Output Fast mode */
+ htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE;
+ htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U;
+ break;
+ }
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ __HAL_UNLOCK(htim);
+
+ return status;
+}
+
+/**
+ * @brief Initializes the TIM One Pulse Channels according to the specified
+ * parameters in the TIM_OnePulse_InitTypeDef.
+ * @param htim TIM One Pulse handle
+ * @param sConfig TIM One Pulse configuration structure
+ * @param OutputChannel TIM output channel to configure
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @param InputChannel TIM input Channel to configure
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @note To output a waveform with a minimum delay user can enable the fast
+ * mode by calling the @ref __HAL_TIM_ENABLE_OCxFAST macro. Then CCx
+ * output is forced in response to the edge detection on TIx input,
+ * without taking in account the comparison.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig,
+ uint32_t OutputChannel, uint32_t InputChannel)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ TIM_OC_InitTypeDef temp1;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
+ assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
+
+ if (OutputChannel != InputChannel)
+ {
+ /* Process Locked */
+ __HAL_LOCK(htim);
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Extract the Output compare configuration from sConfig structure */
+ temp1.OCMode = sConfig->OCMode;
+ temp1.Pulse = sConfig->Pulse;
+ temp1.OCPolarity = sConfig->OCPolarity;
+ temp1.OCNPolarity = sConfig->OCNPolarity;
+ temp1.OCIdleState = sConfig->OCIdleState;
+ temp1.OCNIdleState = sConfig->OCNIdleState;
+
+ switch (OutputChannel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+
+ TIM_OC1_SetConfig(htim->Instance, &temp1);
+ break;
+ }
+
+ case TIM_CHANNEL_2:
+ {
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+ TIM_OC2_SetConfig(htim->Instance, &temp1);
+ break;
+ }
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ if (status == HAL_OK)
+ {
+ switch (InputChannel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+
+ TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
+ sConfig->ICSelection, sConfig->ICFilter);
+
+ /* Reset the IC1PSC Bits */
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
+
+ /* Select the Trigger source */
+ htim->Instance->SMCR &= ~TIM_SMCR_TS;
+ htim->Instance->SMCR |= TIM_TS_TI1FP1;
+
+ /* Select the Slave Mode */
+ htim->Instance->SMCR &= ~TIM_SMCR_SMS;
+ htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
+ break;
+ }
+
+ case TIM_CHANNEL_2:
+ {
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+ TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
+ sConfig->ICSelection, sConfig->ICFilter);
+
+ /* Reset the IC2PSC Bits */
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
+
+ /* Select the Trigger source */
+ htim->Instance->SMCR &= ~TIM_SMCR_TS;
+ htim->Instance->SMCR |= TIM_TS_TI2FP2;
+
+ /* Select the Slave Mode */
+ htim->Instance->SMCR &= ~TIM_SMCR_SMS;
+ htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
+ break;
+ }
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+ }
+
+ htim->State = HAL_TIM_STATE_READY;
+
+ __HAL_UNLOCK(htim);
+
+ return status;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
+ * @param htim TIM handle
+ * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write
+ * This parameter can be one of the following values:
+ * @arg TIM_DMABASE_CR1
+ * @arg TIM_DMABASE_CR2
+ * @arg TIM_DMABASE_SMCR
+ * @arg TIM_DMABASE_DIER
+ * @arg TIM_DMABASE_SR
+ * @arg TIM_DMABASE_EGR
+ * @arg TIM_DMABASE_CCMR1
+ * @arg TIM_DMABASE_CCMR2
+ * @arg TIM_DMABASE_CCER
+ * @arg TIM_DMABASE_CNT
+ * @arg TIM_DMABASE_PSC
+ * @arg TIM_DMABASE_ARR
+ * @arg TIM_DMABASE_RCR
+ * @arg TIM_DMABASE_CCR1
+ * @arg TIM_DMABASE_CCR2
+ * @arg TIM_DMABASE_CCR3
+ * @arg TIM_DMABASE_CCR4
+ * @arg TIM_DMABASE_BDTR
+ * @arg TIM_DMABASE_OR1
+ * @arg TIM_DMABASE_CCMR3
+ * @arg TIM_DMABASE_CCR5
+ * @arg TIM_DMABASE_CCR6
+ * @arg TIM_DMABASE_AF1
+ * @arg TIM_DMABASE_AF2
+ * @arg TIM_DMABASE_TISEL
+ * @param BurstRequestSrc TIM DMA Request sources
+ * This parameter can be one of the following values:
+ * @arg TIM_DMA_UPDATE: TIM update Interrupt source
+ * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
+ * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
+ * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
+ * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
+ * @arg TIM_DMA_COM: TIM Commutation DMA source
+ * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
+ * @param BurstBuffer The Buffer address.
+ * @param BurstLength DMA Burst length. This parameter can be one value
+ * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
+ * @note This function should be used only when BurstLength is equal to DMA data transfer length.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+ uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
+{
+ HAL_StatusTypeDef status;
+
+ status = HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
+ ((BurstLength) >> 8U) + 1U);
+ return status;
+}
+
+/**
+ * @brief Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral
+ * @param htim TIM handle
+ * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write
+ * This parameter can be one of the following values:
+ * @arg TIM_DMABASE_CR1
+ * @arg TIM_DMABASE_CR2
+ * @arg TIM_DMABASE_SMCR
+ * @arg TIM_DMABASE_DIER
+ * @arg TIM_DMABASE_SR
+ * @arg TIM_DMABASE_EGR
+ * @arg TIM_DMABASE_CCMR1
+ * @arg TIM_DMABASE_CCMR2
+ * @arg TIM_DMABASE_CCER
+ * @arg TIM_DMABASE_CNT
+ * @arg TIM_DMABASE_PSC
+ * @arg TIM_DMABASE_ARR
+ * @arg TIM_DMABASE_RCR
+ * @arg TIM_DMABASE_CCR1
+ * @arg TIM_DMABASE_CCR2
+ * @arg TIM_DMABASE_CCR3
+ * @arg TIM_DMABASE_CCR4
+ * @arg TIM_DMABASE_BDTR
+ * @arg TIM_DMABASE_OR1
+ * @arg TIM_DMABASE_CCMR3
+ * @arg TIM_DMABASE_CCR5
+ * @arg TIM_DMABASE_CCR6
+ * @arg TIM_DMABASE_AF1
+ * @arg TIM_DMABASE_AF2
+ * @arg TIM_DMABASE_TISEL
+ * @param BurstRequestSrc TIM DMA Request sources
+ * This parameter can be one of the following values:
+ * @arg TIM_DMA_UPDATE: TIM update Interrupt source
+ * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
+ * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
+ * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
+ * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
+ * @arg TIM_DMA_COM: TIM Commutation DMA source
+ * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
+ * @param BurstBuffer The Buffer address.
+ * @param BurstLength DMA Burst length. This parameter can be one value
+ * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
+ * @param DataLength Data length. This parameter can be one value
+ * between 1 and 0xFFFF.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+ uint32_t BurstRequestSrc, uint32_t *BurstBuffer,
+ uint32_t BurstLength, uint32_t DataLength)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
+ assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
+ assert_param(IS_TIM_DMA_LENGTH(BurstLength));
+ assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
+
+ if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+ else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY)
+ {
+ if ((BurstBuffer == NULL) && (BurstLength > 0U))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY;
+ }
+ }
+ else
+ {
+ /* nothing to do */
+ }
+
+ switch (BurstRequestSrc)
+ {
+ case TIM_DMA_UPDATE:
+ {
+ /* Set the DMA Period elapsed callbacks */
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer,
+ (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+ {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ break;
+ }
+ case TIM_DMA_CC1:
+ {
+ /* Set the DMA compare callbacks */
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer,
+ (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+ {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ break;
+ }
+ case TIM_DMA_CC2:
+ {
+ /* Set the DMA compare callbacks */
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer,
+ (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+ {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ break;
+ }
+ case TIM_DMA_CC3:
+ {
+ /* Set the DMA compare callbacks */
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer,
+ (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+ {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ break;
+ }
+ case TIM_DMA_CC4:
+ {
+ /* Set the DMA compare callbacks */
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer,
+ (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+ {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ break;
+ }
+ case TIM_DMA_COM:
+ {
+ /* Set the DMA commutation callbacks */
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer,
+ (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+ {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ break;
+ }
+ case TIM_DMA_TRIGGER:
+ {
+ /* Set the DMA trigger callbacks */
+ htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
+ htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer,
+ (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+ {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ break;
+ }
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ if (status == HAL_OK)
+ {
+ /* Configure the DMA Burst Mode */
+ htim->Instance->DCR = (BurstBaseAddress | BurstLength);
+ /* Enable the TIM DMA Request */
+ __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Stops the TIM DMA Burst mode
+ * @param htim TIM handle
+ * @param BurstRequestSrc TIM DMA Request sources to disable
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
+
+ /* Abort the DMA transfer (at least disable the DMA channel) */
+ switch (BurstRequestSrc)
+ {
+ case TIM_DMA_UPDATE:
+ {
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
+ break;
+ }
+ case TIM_DMA_CC1:
+ {
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+ break;
+ }
+ case TIM_DMA_CC2:
+ {
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+ break;
+ }
+ case TIM_DMA_CC3:
+ {
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+ break;
+ }
+ case TIM_DMA_CC4:
+ {
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+ break;
+ }
+ case TIM_DMA_COM:
+ {
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
+ break;
+ }
+ case TIM_DMA_TRIGGER:
+ {
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
+ break;
+ }
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ if (status == HAL_OK)
+ {
+ /* Disable the TIM Update DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
+
+ /* Change the DMA burst operation state */
+ htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
+ * @param htim TIM handle
+ * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read
+ * This parameter can be one of the following values:
+ * @arg TIM_DMABASE_CR1
+ * @arg TIM_DMABASE_CR2
+ * @arg TIM_DMABASE_SMCR
+ * @arg TIM_DMABASE_DIER
+ * @arg TIM_DMABASE_SR
+ * @arg TIM_DMABASE_EGR
+ * @arg TIM_DMABASE_CCMR1
+ * @arg TIM_DMABASE_CCMR2
+ * @arg TIM_DMABASE_CCER
+ * @arg TIM_DMABASE_CNT
+ * @arg TIM_DMABASE_PSC
+ * @arg TIM_DMABASE_ARR
+ * @arg TIM_DMABASE_RCR
+ * @arg TIM_DMABASE_CCR1
+ * @arg TIM_DMABASE_CCR2
+ * @arg TIM_DMABASE_CCR3
+ * @arg TIM_DMABASE_CCR4
+ * @arg TIM_DMABASE_BDTR
+ * @arg TIM_DMABASE_OR1
+ * @arg TIM_DMABASE_CCMR3
+ * @arg TIM_DMABASE_CCR5
+ * @arg TIM_DMABASE_CCR6
+ * @arg TIM_DMABASE_AF1
+ * @arg TIM_DMABASE_AF2
+ * @arg TIM_DMABASE_TISEL
+ * @param BurstRequestSrc TIM DMA Request sources
+ * This parameter can be one of the following values:
+ * @arg TIM_DMA_UPDATE: TIM update Interrupt source
+ * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
+ * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
+ * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
+ * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
+ * @arg TIM_DMA_COM: TIM Commutation DMA source
+ * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
+ * @param BurstBuffer The Buffer address.
+ * @param BurstLength DMA Burst length. This parameter can be one value
+ * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
+ * @note This function should be used only when BurstLength is equal to DMA data transfer length.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+ uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
+{
+ HAL_StatusTypeDef status;
+
+ status = HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
+ ((BurstLength) >> 8U) + 1U);
+ return status;
+}
+
+/**
+ * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
+ * @param htim TIM handle
+ * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read
+ * This parameter can be one of the following values:
+ * @arg TIM_DMABASE_CR1
+ * @arg TIM_DMABASE_CR2
+ * @arg TIM_DMABASE_SMCR
+ * @arg TIM_DMABASE_DIER
+ * @arg TIM_DMABASE_SR
+ * @arg TIM_DMABASE_EGR
+ * @arg TIM_DMABASE_CCMR1
+ * @arg TIM_DMABASE_CCMR2
+ * @arg TIM_DMABASE_CCER
+ * @arg TIM_DMABASE_CNT
+ * @arg TIM_DMABASE_PSC
+ * @arg TIM_DMABASE_ARR
+ * @arg TIM_DMABASE_RCR
+ * @arg TIM_DMABASE_CCR1
+ * @arg TIM_DMABASE_CCR2
+ * @arg TIM_DMABASE_CCR3
+ * @arg TIM_DMABASE_CCR4
+ * @arg TIM_DMABASE_BDTR
+ * @arg TIM_DMABASE_OR1
+ * @arg TIM_DMABASE_CCMR3
+ * @arg TIM_DMABASE_CCR5
+ * @arg TIM_DMABASE_CCR6
+ * @arg TIM_DMABASE_AF1
+ * @arg TIM_DMABASE_AF2
+ * @arg TIM_DMABASE_TISEL
+ * @param BurstRequestSrc TIM DMA Request sources
+ * This parameter can be one of the following values:
+ * @arg TIM_DMA_UPDATE: TIM update Interrupt source
+ * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
+ * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
+ * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
+ * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
+ * @arg TIM_DMA_COM: TIM Commutation DMA source
+ * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
+ * @param BurstBuffer The Buffer address.
+ * @param BurstLength DMA Burst length. This parameter can be one value
+ * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
+ * @param DataLength Data length. This parameter can be one value
+ * between 1 and 0xFFFF.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+ uint32_t BurstRequestSrc, uint32_t *BurstBuffer,
+ uint32_t BurstLength, uint32_t DataLength)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
+ assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
+ assert_param(IS_TIM_DMA_LENGTH(BurstLength));
+ assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
+
+ if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+ else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY)
+ {
+ if ((BurstBuffer == NULL) && (BurstLength > 0U))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY;
+ }
+ }
+ else
+ {
+ /* nothing to do */
+ }
+ switch (BurstRequestSrc)
+ {
+ case TIM_DMA_UPDATE:
+ {
+ /* Set the DMA Period elapsed callbacks */
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+ DataLength) != HAL_OK)
+ {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ break;
+ }
+ case TIM_DMA_CC1:
+ {
+ /* Set the DMA capture callbacks */
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+ DataLength) != HAL_OK)
+ {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ break;
+ }
+ case TIM_DMA_CC2:
+ {
+ /* Set the DMA capture callbacks */
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+ DataLength) != HAL_OK)
+ {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ break;
+ }
+ case TIM_DMA_CC3:
+ {
+ /* Set the DMA capture callbacks */
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+ DataLength) != HAL_OK)
+ {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ break;
+ }
+ case TIM_DMA_CC4:
+ {
+ /* Set the DMA capture callbacks */
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+ DataLength) != HAL_OK)
+ {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ break;
+ }
+ case TIM_DMA_COM:
+ {
+ /* Set the DMA commutation callbacks */
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+ DataLength) != HAL_OK)
+ {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ break;
+ }
+ case TIM_DMA_TRIGGER:
+ {
+ /* Set the DMA trigger callbacks */
+ htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
+ htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+ DataLength) != HAL_OK)
+ {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ break;
+ }
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ if (status == HAL_OK)
+ {
+ /* Configure the DMA Burst Mode */
+ htim->Instance->DCR = (BurstBaseAddress | BurstLength);
+
+ /* Enable the TIM DMA Request */
+ __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Stop the DMA burst reading
+ * @param htim TIM handle
+ * @param BurstRequestSrc TIM DMA Request sources to disable.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
+
+ /* Abort the DMA transfer (at least disable the DMA channel) */
+ switch (BurstRequestSrc)
+ {
+ case TIM_DMA_UPDATE:
+ {
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
+ break;
+ }
+ case TIM_DMA_CC1:
+ {
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+ break;
+ }
+ case TIM_DMA_CC2:
+ {
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+ break;
+ }
+ case TIM_DMA_CC3:
+ {
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+ break;
+ }
+ case TIM_DMA_CC4:
+ {
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+ break;
+ }
+ case TIM_DMA_COM:
+ {
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
+ break;
+ }
+ case TIM_DMA_TRIGGER:
+ {
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
+ break;
+ }
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ if (status == HAL_OK)
+ {
+ /* Disable the TIM Update DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
+
+ /* Change the DMA burst operation state */
+ htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Generate a software event
+ * @param htim TIM handle
+ * @param EventSource specifies the event source.
+ * This parameter can be one of the following values:
+ * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
+ * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
+ * @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
+ * @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
+ * @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
+ * @arg TIM_EVENTSOURCE_COM: Timer COM event source
+ * @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
+ * @arg TIM_EVENTSOURCE_BREAK: Timer Break event source
+ * @arg TIM_EVENTSOURCE_BREAK2: Timer Break2 event source
+ * @note Basic timers can only generate an update event.
+ * @note TIM_EVENTSOURCE_COM is relevant only with advanced timer instances.
+ * @note TIM_EVENTSOURCE_BREAK and TIM_EVENTSOURCE_BREAK2 are relevant
+ * only for timer instances supporting break input(s).
+ * @retval HAL status
+ */
+
+HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_EVENT_SOURCE(EventSource));
+
+ /* Process Locked */
+ __HAL_LOCK(htim);
+
+ /* Change the TIM state */
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Set the event sources */
+ htim->Instance->EGR = EventSource;
+
+ /* Change the TIM state */
+ htim->State = HAL_TIM_STATE_READY;
+
+ __HAL_UNLOCK(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Configures the OCRef clear feature
+ * @param htim TIM handle
+ * @param sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that
+ * contains the OCREF clear feature and parameters for the TIM peripheral.
+ * @param Channel specifies the TIM Channel
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1
+ * @arg TIM_CHANNEL_2: TIM Channel 2
+ * @arg TIM_CHANNEL_3: TIM Channel 3
+ * @arg TIM_CHANNEL_4: TIM Channel 4
+ * @arg TIM_CHANNEL_5: TIM Channel 5
+ * @arg TIM_CHANNEL_6: TIM Channel 6
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,
+ TIM_ClearInputConfigTypeDef *sClearInputConfig,
+ uint32_t Channel)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
+
+ /* Process Locked */
+ __HAL_LOCK(htim);
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ switch (sClearInputConfig->ClearInputSource)
+ {
+ case TIM_CLEARINPUTSOURCE_NONE:
+ {
+ /* Clear the OCREF clear selection bit and the the ETR Bits */
+ CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_OCCS | TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP));
+
+ /* Clear TIMx_OR1_OCREF_CLR (reset value) */
+ CLEAR_BIT(htim->Instance->OR1, TIMx_OR1_OCREF_CLR);
+ break;
+ }
+
+ case TIM_CLEARINPUTSOURCE_ETR:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
+ assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
+ assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
+
+ /* When OCRef clear feature is used with ETR source, ETR prescaler must be off */
+ if (sClearInputConfig->ClearInputPrescaler != TIM_CLEARINPUTPRESCALER_DIV1)
+ {
+ htim->State = HAL_TIM_STATE_READY;
+ __HAL_UNLOCK(htim);
+ return HAL_ERROR;
+ }
+
+ TIM_ETR_SetConfig(htim->Instance,
+ sClearInputConfig->ClearInputPrescaler,
+ sClearInputConfig->ClearInputPolarity,
+ sClearInputConfig->ClearInputFilter);
+
+ /* Set the OCREF clear selection bit */
+ SET_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS);
+
+ /* Clear TIMx_OR1_OCREF_CLR (reset value) */
+ CLEAR_BIT(htim->Instance->OR1, TIMx_OR1_OCREF_CLR);
+ break;
+ }
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ if (status == HAL_OK)
+ {
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
+ {
+ /* Enable the OCREF clear feature for Channel 1 */
+ SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
+ }
+ else
+ {
+ /* Disable the OCREF clear feature for Channel 1 */
+ CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
+ }
+ break;
+ }
+ case TIM_CHANNEL_2:
+ {
+ if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
+ {
+ /* Enable the OCREF clear feature for Channel 2 */
+ SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
+ }
+ else
+ {
+ /* Disable the OCREF clear feature for Channel 2 */
+ CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
+ }
+ break;
+ }
+ case TIM_CHANNEL_3:
+ {
+ if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
+ {
+ /* Enable the OCREF clear feature for Channel 3 */
+ SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
+ }
+ else
+ {
+ /* Disable the OCREF clear feature for Channel 3 */
+ CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
+ }
+ break;
+ }
+ case TIM_CHANNEL_4:
+ {
+ if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
+ {
+ /* Enable the OCREF clear feature for Channel 4 */
+ SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
+ }
+ else
+ {
+ /* Disable the OCREF clear feature for Channel 4 */
+ CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
+ }
+ break;
+ }
+ case TIM_CHANNEL_5:
+ {
+ if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
+ {
+ /* Enable the OCREF clear feature for Channel 5 */
+ SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE);
+ }
+ else
+ {
+ /* Disable the OCREF clear feature for Channel 5 */
+ CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE);
+ }
+ break;
+ }
+ case TIM_CHANNEL_6:
+ {
+ if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
+ {
+ /* Enable the OCREF clear feature for Channel 6 */
+ SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE);
+ }
+ else
+ {
+ /* Disable the OCREF clear feature for Channel 6 */
+ CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE);
+ }
+ break;
+ }
+ default:
+ break;
+ }
+ }
+
+ htim->State = HAL_TIM_STATE_READY;
+
+ __HAL_UNLOCK(htim);
+
+ return status;
+}
+
+/**
+ * @brief Configures the clock source to be used
+ * @param htim TIM handle
+ * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
+ * contains the clock source information for the TIM peripheral.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t tmpsmcr;
+
+ /* Process Locked */
+ __HAL_LOCK(htim);
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
+
+ /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
+ tmpsmcr = htim->Instance->SMCR;
+ tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
+ tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
+ htim->Instance->SMCR = tmpsmcr;
+
+ switch (sClockSourceConfig->ClockSource)
+ {
+ case TIM_CLOCKSOURCE_INTERNAL:
+ {
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+ break;
+ }
+
+ case TIM_CLOCKSOURCE_ETRMODE1:
+ {
+ /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/
+ assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
+
+ /* Check ETR input conditioning related parameters */
+ assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
+ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+ assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
+ /* Configure the ETR Clock source */
+ TIM_ETR_SetConfig(htim->Instance,
+ sClockSourceConfig->ClockPrescaler,
+ sClockSourceConfig->ClockPolarity,
+ sClockSourceConfig->ClockFilter);
+
+ /* Select the External clock mode1 and the ETRF trigger */
+ tmpsmcr = htim->Instance->SMCR;
+ tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
+ /* Write to TIMx SMCR */
+ htim->Instance->SMCR = tmpsmcr;
+ break;
+ }
+
+ case TIM_CLOCKSOURCE_ETRMODE2:
+ {
+ /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/
+ assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance));
+
+ /* Check ETR input conditioning related parameters */
+ assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
+ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+ assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
+ /* Configure the ETR Clock source */
+ TIM_ETR_SetConfig(htim->Instance,
+ sClockSourceConfig->ClockPrescaler,
+ sClockSourceConfig->ClockPolarity,
+ sClockSourceConfig->ClockFilter);
+ /* Enable the External clock mode2 */
+ htim->Instance->SMCR |= TIM_SMCR_ECE;
+ break;
+ }
+
+ case TIM_CLOCKSOURCE_TI1:
+ {
+ /* Check whether or not the timer instance supports external clock mode 1 */
+ assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
+
+ /* Check TI1 input conditioning related parameters */
+ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+ assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
+ TIM_TI1_ConfigInputStage(htim->Instance,
+ sClockSourceConfig->ClockPolarity,
+ sClockSourceConfig->ClockFilter);
+ TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
+ break;
+ }
+
+ case TIM_CLOCKSOURCE_TI2:
+ {
+ /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/
+ assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
+
+ /* Check TI2 input conditioning related parameters */
+ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+ assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
+ TIM_TI2_ConfigInputStage(htim->Instance,
+ sClockSourceConfig->ClockPolarity,
+ sClockSourceConfig->ClockFilter);
+ TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
+ break;
+ }
+
+ case TIM_CLOCKSOURCE_TI1ED:
+ {
+ /* Check whether or not the timer instance supports external clock mode 1 */
+ assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
+
+ /* Check TI1 input conditioning related parameters */
+ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+ assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
+ TIM_TI1_ConfigInputStage(htim->Instance,
+ sClockSourceConfig->ClockPolarity,
+ sClockSourceConfig->ClockFilter);
+ TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
+ break;
+ }
+
+ case TIM_CLOCKSOURCE_ITR0:
+ case TIM_CLOCKSOURCE_ITR1:
+ case TIM_CLOCKSOURCE_ITR2:
+ case TIM_CLOCKSOURCE_ITR3:
+ {
+ /* Check whether or not the timer instance supports internal trigger input */
+ assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
+
+ TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
+ break;
+ }
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+ htim->State = HAL_TIM_STATE_READY;
+
+ __HAL_UNLOCK(htim);
+
+ return status;
+}
+
+/**
+ * @brief Selects the signal connected to the TI1 input: direct from CH1_input
+ * or a XOR combination between CH1_input, CH2_input & CH3_input
+ * @param htim TIM handle.
+ * @param TI1_Selection Indicate whether or not channel 1 is connected to the
+ * output of a XOR gate.
+ * This parameter can be one of the following values:
+ * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
+ * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
+ * pins are connected to the TI1 input (XOR combination)
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
+{
+ uint32_t tmpcr2;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
+
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = htim->Instance->CR2;
+
+ /* Reset the TI1 selection */
+ tmpcr2 &= ~TIM_CR2_TI1S;
+
+ /* Set the TI1 selection */
+ tmpcr2 |= TI1_Selection;
+
+ /* Write to TIMxCR2 */
+ htim->Instance->CR2 = tmpcr2;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configures the TIM in Slave mode
+ * @param htim TIM handle.
+ * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
+ * contains the selected trigger (internal trigger input, filtered
+ * timer input or external trigger input) and the Slave mode
+ * (Disable, Reset, Gated, Trigger, External clock mode 1).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
+ assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
+
+ __HAL_LOCK(htim);
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
+ {
+ htim->State = HAL_TIM_STATE_READY;
+ __HAL_UNLOCK(htim);
+ return HAL_ERROR;
+ }
+
+ /* Disable Trigger Interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
+
+ /* Disable Trigger DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
+
+ htim->State = HAL_TIM_STATE_READY;
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configures the TIM in Slave mode in interrupt mode
+ * @param htim TIM handle.
+ * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
+ * contains the selected trigger (internal trigger input, filtered
+ * timer input or external trigger input) and the Slave mode
+ * (Disable, Reset, Gated, Trigger, External clock mode 1).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim,
+ TIM_SlaveConfigTypeDef *sSlaveConfig)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
+ assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
+
+ __HAL_LOCK(htim);
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
+ {
+ htim->State = HAL_TIM_STATE_READY;
+ __HAL_UNLOCK(htim);
+ return HAL_ERROR;
+ }
+
+ /* Enable Trigger Interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
+
+ /* Disable Trigger DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
+
+ htim->State = HAL_TIM_STATE_READY;
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Read the captured value from Capture Compare unit
+ * @param htim TIM handle.
+ * @param Channel TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval Captured value
+ */
+uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ uint32_t tmpreg = 0U;
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+
+ /* Return the capture 1 value */
+ tmpreg = htim->Instance->CCR1;
+
+ break;
+ }
+ case TIM_CHANNEL_2:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+ /* Return the capture 2 value */
+ tmpreg = htim->Instance->CCR2;
+
+ break;
+ }
+
+ case TIM_CHANNEL_3:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+
+ /* Return the capture 3 value */
+ tmpreg = htim->Instance->CCR3;
+
+ break;
+ }
+
+ case TIM_CHANNEL_4:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+
+ /* Return the capture 4 value */
+ tmpreg = htim->Instance->CCR4;
+
+ break;
+ }
+
+ default:
+ break;
+ }
+
+ return tmpreg;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
+ * @brief TIM Callbacks functions
+ *
+@verbatim
+ ==============================================================================
+ ##### TIM Callbacks functions #####
+ ==============================================================================
+ [..]
+ This section provides TIM callback functions:
+ (+) TIM Period elapsed callback
+ (+) TIM Output Compare callback
+ (+) TIM Input capture callback
+ (+) TIM Trigger callback
+ (+) TIM Error callback
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Period elapsed callback in non-blocking mode
+ * @param htim TIM handle
+ * @retval None
+ */
+__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_PeriodElapsedCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Period elapsed half complete callback in non-blocking mode
+ * @param htim TIM handle
+ * @retval None
+ */
+__weak void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_PeriodElapsedHalfCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Output Compare callback in non-blocking mode
+ * @param htim TIM OC handle
+ * @retval None
+ */
+__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Input Capture callback in non-blocking mode
+ * @param htim TIM IC handle
+ * @retval None
+ */
+__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_IC_CaptureCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Input Capture half complete callback in non-blocking mode
+ * @param htim TIM IC handle
+ * @retval None
+ */
+__weak void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_IC_CaptureHalfCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief PWM Pulse finished callback in non-blocking mode
+ * @param htim TIM handle
+ * @retval None
+ */
+__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief PWM Pulse finished half complete callback in non-blocking mode
+ * @param htim TIM handle
+ * @retval None
+ */
+__weak void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_PWM_PulseFinishedHalfCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Hall Trigger detection callback in non-blocking mode
+ * @param htim TIM handle
+ * @retval None
+ */
+__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_TriggerCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Hall Trigger detection half complete callback in non-blocking mode
+ * @param htim TIM handle
+ * @retval None
+ */
+__weak void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_TriggerHalfCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Timer error callback in non-blocking mode
+ * @param htim TIM handle
+ * @retval None
+ */
+__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_ErrorCallback could be implemented in the user file
+ */
+}
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a User TIM callback to be used instead of the weak predefined callback
+ * @param htim tim handle
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
+ * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
+ * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
+ * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
+ * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
+ * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
+ * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
+ * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
+ * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
+ * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
+ * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
+ * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
+ * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID
+ * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID
+ * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
+ * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
+ * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
+ * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
+ * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
+ * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
+ * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
+ * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
+ * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
+ * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
+ * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
+ * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID
+ * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID
+ * @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID
+ * @param pCallback pointer to the callback function
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,
+ pTIM_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ return HAL_ERROR;
+ }
+ /* Process locked */
+ __HAL_LOCK(htim);
+
+ if (htim->State == HAL_TIM_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+ case HAL_TIM_BASE_MSPINIT_CB_ID :
+ htim->Base_MspInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_BASE_MSPDEINIT_CB_ID :
+ htim->Base_MspDeInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_IC_MSPINIT_CB_ID :
+ htim->IC_MspInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_IC_MSPDEINIT_CB_ID :
+ htim->IC_MspDeInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_OC_MSPINIT_CB_ID :
+ htim->OC_MspInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_OC_MSPDEINIT_CB_ID :
+ htim->OC_MspDeInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_PWM_MSPINIT_CB_ID :
+ htim->PWM_MspInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_PWM_MSPDEINIT_CB_ID :
+ htim->PWM_MspDeInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
+ htim->OnePulse_MspInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
+ htim->OnePulse_MspDeInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_ENCODER_MSPINIT_CB_ID :
+ htim->Encoder_MspInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
+ htim->Encoder_MspDeInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
+ htim->HallSensor_MspInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
+ htim->HallSensor_MspDeInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_PERIOD_ELAPSED_CB_ID :
+ htim->PeriodElapsedCallback = pCallback;
+ break;
+
+ case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
+ htim->PeriodElapsedHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_TIM_TRIGGER_CB_ID :
+ htim->TriggerCallback = pCallback;
+ break;
+
+ case HAL_TIM_TRIGGER_HALF_CB_ID :
+ htim->TriggerHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_TIM_IC_CAPTURE_CB_ID :
+ htim->IC_CaptureCallback = pCallback;
+ break;
+
+ case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
+ htim->IC_CaptureHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
+ htim->OC_DelayElapsedCallback = pCallback;
+ break;
+
+ case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
+ htim->PWM_PulseFinishedCallback = pCallback;
+ break;
+
+ case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
+ htim->PWM_PulseFinishedHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_TIM_ERROR_CB_ID :
+ htim->ErrorCallback = pCallback;
+ break;
+
+ case HAL_TIM_COMMUTATION_CB_ID :
+ htim->CommutationCallback = pCallback;
+ break;
+
+ case HAL_TIM_COMMUTATION_HALF_CB_ID :
+ htim->CommutationHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_TIM_BREAK_CB_ID :
+ htim->BreakCallback = pCallback;
+ break;
+
+ case HAL_TIM_BREAK2_CB_ID :
+ htim->Break2Callback = pCallback;
+ break;
+
+ default :
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (htim->State == HAL_TIM_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_TIM_BASE_MSPINIT_CB_ID :
+ htim->Base_MspInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_BASE_MSPDEINIT_CB_ID :
+ htim->Base_MspDeInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_IC_MSPINIT_CB_ID :
+ htim->IC_MspInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_IC_MSPDEINIT_CB_ID :
+ htim->IC_MspDeInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_OC_MSPINIT_CB_ID :
+ htim->OC_MspInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_OC_MSPDEINIT_CB_ID :
+ htim->OC_MspDeInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_PWM_MSPINIT_CB_ID :
+ htim->PWM_MspInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_PWM_MSPDEINIT_CB_ID :
+ htim->PWM_MspDeInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
+ htim->OnePulse_MspInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
+ htim->OnePulse_MspDeInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_ENCODER_MSPINIT_CB_ID :
+ htim->Encoder_MspInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
+ htim->Encoder_MspDeInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
+ htim->HallSensor_MspInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
+ htim->HallSensor_MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(htim);
+
+ return status;
+}
+
+/**
+ * @brief Unregister a TIM callback
+ * TIM callback is redirected to the weak predefined callback
+ * @param htim tim handle
+ * @param CallbackID ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
+ * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
+ * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
+ * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
+ * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
+ * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
+ * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
+ * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
+ * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
+ * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
+ * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
+ * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
+ * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID
+ * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID
+ * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
+ * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
+ * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
+ * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
+ * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
+ * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
+ * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
+ * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
+ * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
+ * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
+ * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
+ * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID
+ * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID
+ * @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(htim);
+
+ if (htim->State == HAL_TIM_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+ case HAL_TIM_BASE_MSPINIT_CB_ID :
+ /* Legacy weak Base MspInit Callback */
+ htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;
+ break;
+
+ case HAL_TIM_BASE_MSPDEINIT_CB_ID :
+ /* Legacy weak Base Msp DeInit Callback */
+ htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;
+ break;
+
+ case HAL_TIM_IC_MSPINIT_CB_ID :
+ /* Legacy weak IC Msp Init Callback */
+ htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;
+ break;
+
+ case HAL_TIM_IC_MSPDEINIT_CB_ID :
+ /* Legacy weak IC Msp DeInit Callback */
+ htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;
+ break;
+
+ case HAL_TIM_OC_MSPINIT_CB_ID :
+ /* Legacy weak OC Msp Init Callback */
+ htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;
+ break;
+
+ case HAL_TIM_OC_MSPDEINIT_CB_ID :
+ /* Legacy weak OC Msp DeInit Callback */
+ htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;
+ break;
+
+ case HAL_TIM_PWM_MSPINIT_CB_ID :
+ /* Legacy weak PWM Msp Init Callback */
+ htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;
+ break;
+
+ case HAL_TIM_PWM_MSPDEINIT_CB_ID :
+ /* Legacy weak PWM Msp DeInit Callback */
+ htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;
+ break;
+
+ case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
+ /* Legacy weak One Pulse Msp Init Callback */
+ htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;
+ break;
+
+ case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
+ /* Legacy weak One Pulse Msp DeInit Callback */
+ htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;
+ break;
+
+ case HAL_TIM_ENCODER_MSPINIT_CB_ID :
+ /* Legacy weak Encoder Msp Init Callback */
+ htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;
+ break;
+
+ case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
+ /* Legacy weak Encoder Msp DeInit Callback */
+ htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;
+ break;
+
+ case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
+ /* Legacy weak Hall Sensor Msp Init Callback */
+ htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit;
+ break;
+
+ case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
+ /* Legacy weak Hall Sensor Msp DeInit Callback */
+ htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit;
+ break;
+
+ case HAL_TIM_PERIOD_ELAPSED_CB_ID :
+ /* Legacy weak Period Elapsed Callback */
+ htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback;
+ break;
+
+ case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
+ /* Legacy weak Period Elapsed half complete Callback */
+ htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback;
+ break;
+
+ case HAL_TIM_TRIGGER_CB_ID :
+ /* Legacy weak Trigger Callback */
+ htim->TriggerCallback = HAL_TIM_TriggerCallback;
+ break;
+
+ case HAL_TIM_TRIGGER_HALF_CB_ID :
+ /* Legacy weak Trigger half complete Callback */
+ htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback;
+ break;
+
+ case HAL_TIM_IC_CAPTURE_CB_ID :
+ /* Legacy weak IC Capture Callback */
+ htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback;
+ break;
+
+ case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
+ /* Legacy weak IC Capture half complete Callback */
+ htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback;
+ break;
+
+ case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
+ /* Legacy weak OC Delay Elapsed Callback */
+ htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback;
+ break;
+
+ case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
+ /* Legacy weak PWM Pulse Finished Callback */
+ htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback;
+ break;
+
+ case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
+ /* Legacy weak PWM Pulse Finished half complete Callback */
+ htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback;
+ break;
+
+ case HAL_TIM_ERROR_CB_ID :
+ /* Legacy weak Error Callback */
+ htim->ErrorCallback = HAL_TIM_ErrorCallback;
+ break;
+
+ case HAL_TIM_COMMUTATION_CB_ID :
+ /* Legacy weak Commutation Callback */
+ htim->CommutationCallback = HAL_TIMEx_CommutCallback;
+ break;
+
+ case HAL_TIM_COMMUTATION_HALF_CB_ID :
+ /* Legacy weak Commutation half complete Callback */
+ htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback;
+ break;
+
+ case HAL_TIM_BREAK_CB_ID :
+ /* Legacy weak Break Callback */
+ htim->BreakCallback = HAL_TIMEx_BreakCallback;
+ break;
+
+ case HAL_TIM_BREAK2_CB_ID :
+ /* Legacy weak Break2 Callback */
+ htim->Break2Callback = HAL_TIMEx_Break2Callback;
+ break;
+
+ default :
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (htim->State == HAL_TIM_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_TIM_BASE_MSPINIT_CB_ID :
+ /* Legacy weak Base MspInit Callback */
+ htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;
+ break;
+
+ case HAL_TIM_BASE_MSPDEINIT_CB_ID :
+ /* Legacy weak Base Msp DeInit Callback */
+ htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;
+ break;
+
+ case HAL_TIM_IC_MSPINIT_CB_ID :
+ /* Legacy weak IC Msp Init Callback */
+ htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;
+ break;
+
+ case HAL_TIM_IC_MSPDEINIT_CB_ID :
+ /* Legacy weak IC Msp DeInit Callback */
+ htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;
+ break;
+
+ case HAL_TIM_OC_MSPINIT_CB_ID :
+ /* Legacy weak OC Msp Init Callback */
+ htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;
+ break;
+
+ case HAL_TIM_OC_MSPDEINIT_CB_ID :
+ /* Legacy weak OC Msp DeInit Callback */
+ htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;
+ break;
+
+ case HAL_TIM_PWM_MSPINIT_CB_ID :
+ /* Legacy weak PWM Msp Init Callback */
+ htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;
+ break;
+
+ case HAL_TIM_PWM_MSPDEINIT_CB_ID :
+ /* Legacy weak PWM Msp DeInit Callback */
+ htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;
+ break;
+
+ case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
+ /* Legacy weak One Pulse Msp Init Callback */
+ htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;
+ break;
+
+ case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
+ /* Legacy weak One Pulse Msp DeInit Callback */
+ htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;
+ break;
+
+ case HAL_TIM_ENCODER_MSPINIT_CB_ID :
+ /* Legacy weak Encoder Msp Init Callback */
+ htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;
+ break;
+
+ case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
+ /* Legacy weak Encoder Msp DeInit Callback */
+ htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;
+ break;
+
+ case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
+ /* Legacy weak Hall Sensor Msp Init Callback */
+ htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit;
+ break;
+
+ case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
+ /* Legacy weak Hall Sensor Msp DeInit Callback */
+ htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit;
+ break;
+
+ default :
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(htim);
+
+ return status;
+}
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions
+ * @brief TIM Peripheral State functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral State functions #####
+ ==============================================================================
+ [..]
+ This subsection permits to get in run-time the status of the peripheral
+ and the data flow.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the TIM Base handle state.
+ * @param htim TIM Base handle
+ * @retval HAL state
+ */
+HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
+{
+ return htim->State;
+}
+
+/**
+ * @brief Return the TIM OC handle state.
+ * @param htim TIM Output Compare handle
+ * @retval HAL state
+ */
+HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
+{
+ return htim->State;
+}
+
+/**
+ * @brief Return the TIM PWM handle state.
+ * @param htim TIM handle
+ * @retval HAL state
+ */
+HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
+{
+ return htim->State;
+}
+
+/**
+ * @brief Return the TIM Input Capture handle state.
+ * @param htim TIM IC handle
+ * @retval HAL state
+ */
+HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
+{
+ return htim->State;
+}
+
+/**
+ * @brief Return the TIM One Pulse Mode handle state.
+ * @param htim TIM OPM handle
+ * @retval HAL state
+ */
+HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
+{
+ return htim->State;
+}
+
+/**
+ * @brief Return the TIM Encoder Mode handle state.
+ * @param htim TIM Encoder Interface handle
+ * @retval HAL state
+ */
+HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
+{
+ return htim->State;
+}
+
+/**
+ * @brief Return the TIM Encoder Mode handle state.
+ * @param htim TIM handle
+ * @retval Active channel
+ */
+HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim)
+{
+ return htim->Channel;
+}
+
+/**
+ * @brief Return actual state of the TIM channel.
+ * @param htim TIM handle
+ * @param Channel TIM Channel
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1
+ * @arg TIM_CHANNEL_2: TIM Channel 2
+ * @arg TIM_CHANNEL_3: TIM Channel 3
+ * @arg TIM_CHANNEL_4: TIM Channel 4
+ * @arg TIM_CHANNEL_5: TIM Channel 5
+ * @arg TIM_CHANNEL_6: TIM Channel 6
+ * @retval TIM Channel state
+ */
+HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ HAL_TIM_ChannelStateTypeDef channel_state;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
+
+ return channel_state;
+}
+
+/**
+ * @brief Return actual state of a DMA burst operation.
+ * @param htim TIM handle
+ * @retval DMA burst state
+ */
+HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
+
+ return htim->DMABurstState;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Private_Functions TIM Private Functions
+ * @{
+ */
+
+/**
+ * @brief TIM DMA error callback
+ * @param hdma pointer to DMA handle.
+ * @retval None
+ */
+void TIM_DMAError(DMA_HandleTypeDef *hdma)
+{
+ TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ if (hdma == htim->hdma[TIM_DMA_ID_CC1])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
+ }
+ else
+ {
+ htim->State = HAL_TIM_STATE_READY;
+ }
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->ErrorCallback(htim);
+#else
+ HAL_TIM_ErrorCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+}
+
+/**
+ * @brief TIM DMA Delay Pulse complete callback.
+ * @param hdma pointer to DMA handle.
+ * @retval None
+ */
+static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
+{
+ TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ if (hdma == htim->hdma[TIM_DMA_ID_CC1])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+
+ if (hdma->Init.Mode == DMA_NORMAL)
+ {
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ }
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+
+ if (hdma->Init.Mode == DMA_NORMAL)
+ {
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ }
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+
+ if (hdma->Init.Mode == DMA_NORMAL)
+ {
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
+ }
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+
+ if (hdma->Init.Mode == DMA_NORMAL)
+ {
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
+ }
+ }
+ else
+ {
+ /* nothing to do */
+ }
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->PWM_PulseFinishedCallback(htim);
+#else
+ HAL_TIM_PWM_PulseFinishedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+}
+
+/**
+ * @brief TIM DMA Delay Pulse half complete callback.
+ * @param hdma pointer to DMA handle.
+ * @retval None
+ */
+void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma)
+{
+ TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ if (hdma == htim->hdma[TIM_DMA_ID_CC1])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+ }
+ else
+ {
+ /* nothing to do */
+ }
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->PWM_PulseFinishedHalfCpltCallback(htim);
+#else
+ HAL_TIM_PWM_PulseFinishedHalfCpltCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+}
+
+/**
+ * @brief TIM DMA Capture complete callback.
+ * @param hdma pointer to DMA handle.
+ * @retval None
+ */
+void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
+{
+ TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ if (hdma == htim->hdma[TIM_DMA_ID_CC1])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+
+ if (hdma->Init.Mode == DMA_NORMAL)
+ {
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ }
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+
+ if (hdma->Init.Mode == DMA_NORMAL)
+ {
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ }
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+
+ if (hdma->Init.Mode == DMA_NORMAL)
+ {
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
+ }
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+
+ if (hdma->Init.Mode == DMA_NORMAL)
+ {
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
+ }
+ }
+ else
+ {
+ /* nothing to do */
+ }
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->IC_CaptureCallback(htim);
+#else
+ HAL_TIM_IC_CaptureCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+}
+
+/**
+ * @brief TIM DMA Capture half complete callback.
+ * @param hdma pointer to DMA handle.
+ * @retval None
+ */
+void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma)
+{
+ TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ if (hdma == htim->hdma[TIM_DMA_ID_CC1])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+ }
+ else
+ {
+ /* nothing to do */
+ }
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->IC_CaptureHalfCpltCallback(htim);
+#else
+ HAL_TIM_IC_CaptureHalfCpltCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+}
+
+/**
+ * @brief TIM DMA Period Elapse complete callback.
+ * @param hdma pointer to DMA handle.
+ * @retval None
+ */
+static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
+{
+ TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ if (htim->hdma[TIM_DMA_ID_UPDATE]->Init.Mode == DMA_NORMAL)
+ {
+ htim->State = HAL_TIM_STATE_READY;
+ }
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->PeriodElapsedCallback(htim);
+#else
+ HAL_TIM_PeriodElapsedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief TIM DMA Period Elapse half complete callback.
+ * @param hdma pointer to DMA handle.
+ * @retval None
+ */
+static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma)
+{
+ TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->PeriodElapsedHalfCpltCallback(htim);
+#else
+ HAL_TIM_PeriodElapsedHalfCpltCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief TIM DMA Trigger callback.
+ * @param hdma pointer to DMA handle.
+ * @retval None
+ */
+static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
+{
+ TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ if (htim->hdma[TIM_DMA_ID_TRIGGER]->Init.Mode == DMA_NORMAL)
+ {
+ htim->State = HAL_TIM_STATE_READY;
+ }
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->TriggerCallback(htim);
+#else
+ HAL_TIM_TriggerCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief TIM DMA Trigger half complete callback.
+ * @param hdma pointer to DMA handle.
+ * @retval None
+ */
+static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma)
+{
+ TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->TriggerHalfCpltCallback(htim);
+#else
+ HAL_TIM_TriggerHalfCpltCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief Time Base configuration
+ * @param TIMx TIM peripheral
+ * @param Structure TIM Base configuration structure
+ * @retval None
+ */
+void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
+{
+ uint32_t tmpcr1;
+ tmpcr1 = TIMx->CR1;
+
+ /* Set TIM Time Base Unit parameters ---------------------------------------*/
+ if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
+ {
+ /* Select the Counter Mode */
+ tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
+ tmpcr1 |= Structure->CounterMode;
+ }
+
+ if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
+ {
+ /* Set the clock division */
+ tmpcr1 &= ~TIM_CR1_CKD;
+ tmpcr1 |= (uint32_t)Structure->ClockDivision;
+ }
+
+ /* Set the auto-reload preload */
+ MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
+
+ TIMx->CR1 = tmpcr1;
+
+ /* Set the Autoreload value */
+ TIMx->ARR = (uint32_t)Structure->Period ;
+
+ /* Set the Prescaler value */
+ TIMx->PSC = Structure->Prescaler;
+
+ if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
+ {
+ /* Set the Repetition Counter value */
+ TIMx->RCR = Structure->RepetitionCounter;
+ }
+
+ /* Generate an update event to reload the Prescaler
+ and the repetition counter (only for advanced timer) value immediately */
+ TIMx->EGR = TIM_EGR_UG;
+}
+
+/**
+ * @brief Timer Output Compare 1 configuration
+ * @param TIMx to select the TIM peripheral
+ * @param OC_Config The output configuration structure
+ * @retval None
+ */
+static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
+{
+ uint32_t tmpccmrx;
+ uint32_t tmpccer;
+ uint32_t tmpcr2;
+
+ /* Disable the Channel 1: Reset the CC1E Bit */
+ TIMx->CCER &= ~TIM_CCER_CC1E;
+
+ /* Get the TIMx CCER register value */
+ tmpccer = TIMx->CCER;
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = TIMx->CR2;
+
+ /* Get the TIMx CCMR1 register value */
+ tmpccmrx = TIMx->CCMR1;
+
+ /* Reset the Output Compare Mode Bits */
+ tmpccmrx &= ~TIM_CCMR1_OC1M;
+ tmpccmrx &= ~TIM_CCMR1_CC1S;
+ /* Select the Output Compare Mode */
+ tmpccmrx |= OC_Config->OCMode;
+
+ /* Reset the Output Polarity level */
+ tmpccer &= ~TIM_CCER_CC1P;
+ /* Set the Output Compare Polarity */
+ tmpccer |= OC_Config->OCPolarity;
+
+ if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
+ {
+ /* Check parameters */
+ assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
+
+ /* Reset the Output N Polarity level */
+ tmpccer &= ~TIM_CCER_CC1NP;
+ /* Set the Output N Polarity */
+ tmpccer |= OC_Config->OCNPolarity;
+ /* Reset the Output N State */
+ tmpccer &= ~TIM_CCER_CC1NE;
+ }
+
+ if (IS_TIM_BREAK_INSTANCE(TIMx))
+ {
+ /* Check parameters */
+ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
+ assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
+
+ /* Reset the Output Compare and Output Compare N IDLE State */
+ tmpcr2 &= ~TIM_CR2_OIS1;
+ tmpcr2 &= ~TIM_CR2_OIS1N;
+ /* Set the Output Idle state */
+ tmpcr2 |= OC_Config->OCIdleState;
+ /* Set the Output N Idle state */
+ tmpcr2 |= OC_Config->OCNIdleState;
+ }
+
+ /* Write to TIMx CR2 */
+ TIMx->CR2 = tmpcr2;
+
+ /* Write to TIMx CCMR1 */
+ TIMx->CCMR1 = tmpccmrx;
+
+ /* Set the Capture Compare Register value */
+ TIMx->CCR1 = OC_Config->Pulse;
+
+ /* Write to TIMx CCER */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Timer Output Compare 2 configuration
+ * @param TIMx to select the TIM peripheral
+ * @param OC_Config The output configuration structure
+ * @retval None
+ */
+void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
+{
+ uint32_t tmpccmrx;
+ uint32_t tmpccer;
+ uint32_t tmpcr2;
+
+ /* Disable the Channel 2: Reset the CC2E Bit */
+ TIMx->CCER &= ~TIM_CCER_CC2E;
+
+ /* Get the TIMx CCER register value */
+ tmpccer = TIMx->CCER;
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = TIMx->CR2;
+
+ /* Get the TIMx CCMR1 register value */
+ tmpccmrx = TIMx->CCMR1;
+
+ /* Reset the Output Compare mode and Capture/Compare selection Bits */
+ tmpccmrx &= ~TIM_CCMR1_OC2M;
+ tmpccmrx &= ~TIM_CCMR1_CC2S;
+
+ /* Select the Output Compare Mode */
+ tmpccmrx |= (OC_Config->OCMode << 8U);
+
+ /* Reset the Output Polarity level */
+ tmpccer &= ~TIM_CCER_CC2P;
+ /* Set the Output Compare Polarity */
+ tmpccer |= (OC_Config->OCPolarity << 4U);
+
+ if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
+ {
+ assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
+
+ /* Reset the Output N Polarity level */
+ tmpccer &= ~TIM_CCER_CC2NP;
+ /* Set the Output N Polarity */
+ tmpccer |= (OC_Config->OCNPolarity << 4U);
+ /* Reset the Output N State */
+ tmpccer &= ~TIM_CCER_CC2NE;
+
+ }
+
+ if (IS_TIM_BREAK_INSTANCE(TIMx))
+ {
+ /* Check parameters */
+ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
+ assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
+
+ /* Reset the Output Compare and Output Compare N IDLE State */
+ tmpcr2 &= ~TIM_CR2_OIS2;
+ tmpcr2 &= ~TIM_CR2_OIS2N;
+ /* Set the Output Idle state */
+ tmpcr2 |= (OC_Config->OCIdleState << 2U);
+ /* Set the Output N Idle state */
+ tmpcr2 |= (OC_Config->OCNIdleState << 2U);
+ }
+
+ /* Write to TIMx CR2 */
+ TIMx->CR2 = tmpcr2;
+
+ /* Write to TIMx CCMR1 */
+ TIMx->CCMR1 = tmpccmrx;
+
+ /* Set the Capture Compare Register value */
+ TIMx->CCR2 = OC_Config->Pulse;
+
+ /* Write to TIMx CCER */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Timer Output Compare 3 configuration
+ * @param TIMx to select the TIM peripheral
+ * @param OC_Config The output configuration structure
+ * @retval None
+ */
+static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
+{
+ uint32_t tmpccmrx;
+ uint32_t tmpccer;
+ uint32_t tmpcr2;
+
+ /* Disable the Channel 3: Reset the CC2E Bit */
+ TIMx->CCER &= ~TIM_CCER_CC3E;
+
+ /* Get the TIMx CCER register value */
+ tmpccer = TIMx->CCER;
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = TIMx->CR2;
+
+ /* Get the TIMx CCMR2 register value */
+ tmpccmrx = TIMx->CCMR2;
+
+ /* Reset the Output Compare mode and Capture/Compare selection Bits */
+ tmpccmrx &= ~TIM_CCMR2_OC3M;
+ tmpccmrx &= ~TIM_CCMR2_CC3S;
+ /* Select the Output Compare Mode */
+ tmpccmrx |= OC_Config->OCMode;
+
+ /* Reset the Output Polarity level */
+ tmpccer &= ~TIM_CCER_CC3P;
+ /* Set the Output Compare Polarity */
+ tmpccer |= (OC_Config->OCPolarity << 8U);
+
+ if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
+ {
+ assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
+
+ /* Reset the Output N Polarity level */
+ tmpccer &= ~TIM_CCER_CC3NP;
+ /* Set the Output N Polarity */
+ tmpccer |= (OC_Config->OCNPolarity << 8U);
+ /* Reset the Output N State */
+ tmpccer &= ~TIM_CCER_CC3NE;
+ }
+
+ if (IS_TIM_BREAK_INSTANCE(TIMx))
+ {
+ /* Check parameters */
+ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
+ assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
+
+ /* Reset the Output Compare and Output Compare N IDLE State */
+ tmpcr2 &= ~TIM_CR2_OIS3;
+ tmpcr2 &= ~TIM_CR2_OIS3N;
+ /* Set the Output Idle state */
+ tmpcr2 |= (OC_Config->OCIdleState << 4U);
+ /* Set the Output N Idle state */
+ tmpcr2 |= (OC_Config->OCNIdleState << 4U);
+ }
+
+ /* Write to TIMx CR2 */
+ TIMx->CR2 = tmpcr2;
+
+ /* Write to TIMx CCMR2 */
+ TIMx->CCMR2 = tmpccmrx;
+
+ /* Set the Capture Compare Register value */
+ TIMx->CCR3 = OC_Config->Pulse;
+
+ /* Write to TIMx CCER */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Timer Output Compare 4 configuration
+ * @param TIMx to select the TIM peripheral
+ * @param OC_Config The output configuration structure
+ * @retval None
+ */
+static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
+{
+ uint32_t tmpccmrx;
+ uint32_t tmpccer;
+ uint32_t tmpcr2;
+
+ /* Disable the Channel 4: Reset the CC4E Bit */
+ TIMx->CCER &= ~TIM_CCER_CC4E;
+
+ /* Get the TIMx CCER register value */
+ tmpccer = TIMx->CCER;
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = TIMx->CR2;
+
+ /* Get the TIMx CCMR2 register value */
+ tmpccmrx = TIMx->CCMR2;
+
+ /* Reset the Output Compare mode and Capture/Compare selection Bits */
+ tmpccmrx &= ~TIM_CCMR2_OC4M;
+ tmpccmrx &= ~TIM_CCMR2_CC4S;
+
+ /* Select the Output Compare Mode */
+ tmpccmrx |= (OC_Config->OCMode << 8U);
+
+ /* Reset the Output Polarity level */
+ tmpccer &= ~TIM_CCER_CC4P;
+ /* Set the Output Compare Polarity */
+ tmpccer |= (OC_Config->OCPolarity << 12U);
+
+ if (IS_TIM_BREAK_INSTANCE(TIMx))
+ {
+ /* Check parameters */
+ assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
+
+ /* Reset the Output Compare IDLE State */
+ tmpcr2 &= ~TIM_CR2_OIS4;
+
+ /* Set the Output Idle state */
+ tmpcr2 |= (OC_Config->OCIdleState << 6U);
+ }
+
+ /* Write to TIMx CR2 */
+ TIMx->CR2 = tmpcr2;
+
+ /* Write to TIMx CCMR2 */
+ TIMx->CCMR2 = tmpccmrx;
+
+ /* Set the Capture Compare Register value */
+ TIMx->CCR4 = OC_Config->Pulse;
+
+ /* Write to TIMx CCER */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Timer Output Compare 5 configuration
+ * @param TIMx to select the TIM peripheral
+ * @param OC_Config The output configuration structure
+ * @retval None
+ */
+static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
+ TIM_OC_InitTypeDef *OC_Config)
+{
+ uint32_t tmpccmrx;
+ uint32_t tmpccer;
+ uint32_t tmpcr2;
+
+ /* Disable the output: Reset the CCxE Bit */
+ TIMx->CCER &= ~TIM_CCER_CC5E;
+
+ /* Get the TIMx CCER register value */
+ tmpccer = TIMx->CCER;
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = TIMx->CR2;
+ /* Get the TIMx CCMR1 register value */
+ tmpccmrx = TIMx->CCMR3;
+
+ /* Reset the Output Compare Mode Bits */
+ tmpccmrx &= ~(TIM_CCMR3_OC5M);
+ /* Select the Output Compare Mode */
+ tmpccmrx |= OC_Config->OCMode;
+
+ /* Reset the Output Polarity level */
+ tmpccer &= ~TIM_CCER_CC5P;
+ /* Set the Output Compare Polarity */
+ tmpccer |= (OC_Config->OCPolarity << 16U);
+
+ if (IS_TIM_BREAK_INSTANCE(TIMx))
+ {
+ /* Reset the Output Compare IDLE State */
+ tmpcr2 &= ~TIM_CR2_OIS5;
+ /* Set the Output Idle state */
+ tmpcr2 |= (OC_Config->OCIdleState << 8U);
+ }
+ /* Write to TIMx CR2 */
+ TIMx->CR2 = tmpcr2;
+
+ /* Write to TIMx CCMR3 */
+ TIMx->CCMR3 = tmpccmrx;
+
+ /* Set the Capture Compare Register value */
+ TIMx->CCR5 = OC_Config->Pulse;
+
+ /* Write to TIMx CCER */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Timer Output Compare 6 configuration
+ * @param TIMx to select the TIM peripheral
+ * @param OC_Config The output configuration structure
+ * @retval None
+ */
+static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
+ TIM_OC_InitTypeDef *OC_Config)
+{
+ uint32_t tmpccmrx;
+ uint32_t tmpccer;
+ uint32_t tmpcr2;
+
+ /* Disable the output: Reset the CCxE Bit */
+ TIMx->CCER &= ~TIM_CCER_CC6E;
+
+ /* Get the TIMx CCER register value */
+ tmpccer = TIMx->CCER;
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = TIMx->CR2;
+ /* Get the TIMx CCMR1 register value */
+ tmpccmrx = TIMx->CCMR3;
+
+ /* Reset the Output Compare Mode Bits */
+ tmpccmrx &= ~(TIM_CCMR3_OC6M);
+ /* Select the Output Compare Mode */
+ tmpccmrx |= (OC_Config->OCMode << 8U);
+
+ /* Reset the Output Polarity level */
+ tmpccer &= (uint32_t)~TIM_CCER_CC6P;
+ /* Set the Output Compare Polarity */
+ tmpccer |= (OC_Config->OCPolarity << 20U);
+
+ if (IS_TIM_BREAK_INSTANCE(TIMx))
+ {
+ /* Reset the Output Compare IDLE State */
+ tmpcr2 &= ~TIM_CR2_OIS6;
+ /* Set the Output Idle state */
+ tmpcr2 |= (OC_Config->OCIdleState << 10U);
+ }
+
+ /* Write to TIMx CR2 */
+ TIMx->CR2 = tmpcr2;
+
+ /* Write to TIMx CCMR3 */
+ TIMx->CCMR3 = tmpccmrx;
+
+ /* Set the Capture Compare Register value */
+ TIMx->CCR6 = OC_Config->Pulse;
+
+ /* Write to TIMx CCER */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Slave Timer configuration function
+ * @param htim TIM handle
+ * @param sSlaveConfig Slave timer configuration
+ * @retval None
+ */
+static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
+ TIM_SlaveConfigTypeDef *sSlaveConfig)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t tmpsmcr;
+ uint32_t tmpccmr1;
+ uint32_t tmpccer;
+
+ /* Get the TIMx SMCR register value */
+ tmpsmcr = htim->Instance->SMCR;
+
+ /* Reset the Trigger Selection Bits */
+ tmpsmcr &= ~TIM_SMCR_TS;
+ /* Set the Input Trigger source */
+ tmpsmcr |= sSlaveConfig->InputTrigger;
+
+ /* Reset the slave mode Bits */
+ tmpsmcr &= ~TIM_SMCR_SMS;
+ /* Set the slave mode */
+ tmpsmcr |= sSlaveConfig->SlaveMode;
+
+ /* Write to TIMx SMCR */
+ htim->Instance->SMCR = tmpsmcr;
+
+ /* Configure the trigger prescaler, filter, and polarity */
+ switch (sSlaveConfig->InputTrigger)
+ {
+ case TIM_TS_ETRF:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
+ assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
+ assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
+ /* Configure the ETR Trigger source */
+ TIM_ETR_SetConfig(htim->Instance,
+ sSlaveConfig->TriggerPrescaler,
+ sSlaveConfig->TriggerPolarity,
+ sSlaveConfig->TriggerFilter);
+ break;
+ }
+
+ case TIM_TS_TI1F_ED:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
+
+ if (sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Disable the Channel 1: Reset the CC1E Bit */
+ tmpccer = htim->Instance->CCER;
+ htim->Instance->CCER &= ~TIM_CCER_CC1E;
+ tmpccmr1 = htim->Instance->CCMR1;
+
+ /* Set the filter */
+ tmpccmr1 &= ~TIM_CCMR1_IC1F;
+ tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U);
+
+ /* Write to TIMx CCMR1 and CCER registers */
+ htim->Instance->CCMR1 = tmpccmr1;
+ htim->Instance->CCER = tmpccer;
+ break;
+ }
+
+ case TIM_TS_TI1FP1:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
+ assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
+
+ /* Configure TI1 Filter and Polarity */
+ TIM_TI1_ConfigInputStage(htim->Instance,
+ sSlaveConfig->TriggerPolarity,
+ sSlaveConfig->TriggerFilter);
+ break;
+ }
+
+ case TIM_TS_TI2FP2:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
+ assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
+
+ /* Configure TI2 Filter and Polarity */
+ TIM_TI2_ConfigInputStage(htim->Instance,
+ sSlaveConfig->TriggerPolarity,
+ sSlaveConfig->TriggerFilter);
+ break;
+ }
+
+ case TIM_TS_ITR0:
+ case TIM_TS_ITR1:
+ case TIM_TS_ITR2:
+ case TIM_TS_ITR3:
+ {
+ /* Check the parameter */
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+ break;
+ }
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Configure the TI1 as Input.
+ * @param TIMx to select the TIM peripheral.
+ * @param TIM_ICPolarity The Input Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPOLARITY_RISING
+ * @arg TIM_ICPOLARITY_FALLING
+ * @arg TIM_ICPOLARITY_BOTHEDGE
+ * @param TIM_ICSelection specifies the input to be used.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1.
+ * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2.
+ * @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC.
+ * @param TIM_ICFilter Specifies the Input Capture Filter.
+ * This parameter must be a value between 0x00 and 0x0F.
+ * @retval None
+ * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
+ * (on channel2 path) is used as the input signal. Therefore CCMR1 must be
+ * protected against un-initialized filter and polarity values.
+ */
+void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+ uint32_t TIM_ICFilter)
+{
+ uint32_t tmpccmr1;
+ uint32_t tmpccer;
+
+ /* Disable the Channel 1: Reset the CC1E Bit */
+ TIMx->CCER &= ~TIM_CCER_CC1E;
+ tmpccmr1 = TIMx->CCMR1;
+ tmpccer = TIMx->CCER;
+
+ /* Select the Input */
+ if (IS_TIM_CC2_INSTANCE(TIMx) != RESET)
+ {
+ tmpccmr1 &= ~TIM_CCMR1_CC1S;
+ tmpccmr1 |= TIM_ICSelection;
+ }
+ else
+ {
+ tmpccmr1 |= TIM_CCMR1_CC1S_0;
+ }
+
+ /* Set the filter */
+ tmpccmr1 &= ~TIM_CCMR1_IC1F;
+ tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F);
+
+ /* Select the Polarity and set the CC1E Bit */
+ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
+ tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));
+
+ /* Write to TIMx CCMR1 and CCER registers */
+ TIMx->CCMR1 = tmpccmr1;
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Configure the Polarity and Filter for TI1.
+ * @param TIMx to select the TIM peripheral.
+ * @param TIM_ICPolarity The Input Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPOLARITY_RISING
+ * @arg TIM_ICPOLARITY_FALLING
+ * @arg TIM_ICPOLARITY_BOTHEDGE
+ * @param TIM_ICFilter Specifies the Input Capture Filter.
+ * This parameter must be a value between 0x00 and 0x0F.
+ * @retval None
+ */
+static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
+{
+ uint32_t tmpccmr1;
+ uint32_t tmpccer;
+
+ /* Disable the Channel 1: Reset the CC1E Bit */
+ tmpccer = TIMx->CCER;
+ TIMx->CCER &= ~TIM_CCER_CC1E;
+ tmpccmr1 = TIMx->CCMR1;
+
+ /* Set the filter */
+ tmpccmr1 &= ~TIM_CCMR1_IC1F;
+ tmpccmr1 |= (TIM_ICFilter << 4U);
+
+ /* Select the Polarity and set the CC1E Bit */
+ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
+ tmpccer |= TIM_ICPolarity;
+
+ /* Write to TIMx CCMR1 and CCER registers */
+ TIMx->CCMR1 = tmpccmr1;
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Configure the TI2 as Input.
+ * @param TIMx to select the TIM peripheral
+ * @param TIM_ICPolarity The Input Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPOLARITY_RISING
+ * @arg TIM_ICPOLARITY_FALLING
+ * @arg TIM_ICPOLARITY_BOTHEDGE
+ * @param TIM_ICSelection specifies the input to be used.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2.
+ * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1.
+ * @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC.
+ * @param TIM_ICFilter Specifies the Input Capture Filter.
+ * This parameter must be a value between 0x00 and 0x0F.
+ * @retval None
+ * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
+ * (on channel1 path) is used as the input signal. Therefore CCMR1 must be
+ * protected against un-initialized filter and polarity values.
+ */
+static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+ uint32_t TIM_ICFilter)
+{
+ uint32_t tmpccmr1;
+ uint32_t tmpccer;
+
+ /* Disable the Channel 2: Reset the CC2E Bit */
+ TIMx->CCER &= ~TIM_CCER_CC2E;
+ tmpccmr1 = TIMx->CCMR1;
+ tmpccer = TIMx->CCER;
+
+ /* Select the Input */
+ tmpccmr1 &= ~TIM_CCMR1_CC2S;
+ tmpccmr1 |= (TIM_ICSelection << 8U);
+
+ /* Set the filter */
+ tmpccmr1 &= ~TIM_CCMR1_IC2F;
+ tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F);
+
+ /* Select the Polarity and set the CC2E Bit */
+ tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
+ tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));
+
+ /* Write to TIMx CCMR1 and CCER registers */
+ TIMx->CCMR1 = tmpccmr1 ;
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Configure the Polarity and Filter for TI2.
+ * @param TIMx to select the TIM peripheral.
+ * @param TIM_ICPolarity The Input Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPOLARITY_RISING
+ * @arg TIM_ICPOLARITY_FALLING
+ * @arg TIM_ICPOLARITY_BOTHEDGE
+ * @param TIM_ICFilter Specifies the Input Capture Filter.
+ * This parameter must be a value between 0x00 and 0x0F.
+ * @retval None
+ */
+static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
+{
+ uint32_t tmpccmr1;
+ uint32_t tmpccer;
+
+ /* Disable the Channel 2: Reset the CC2E Bit */
+ TIMx->CCER &= ~TIM_CCER_CC2E;
+ tmpccmr1 = TIMx->CCMR1;
+ tmpccer = TIMx->CCER;
+
+ /* Set the filter */
+ tmpccmr1 &= ~TIM_CCMR1_IC2F;
+ tmpccmr1 |= (TIM_ICFilter << 12U);
+
+ /* Select the Polarity and set the CC2E Bit */
+ tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
+ tmpccer |= (TIM_ICPolarity << 4U);
+
+ /* Write to TIMx CCMR1 and CCER registers */
+ TIMx->CCMR1 = tmpccmr1 ;
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Configure the TI3 as Input.
+ * @param TIMx to select the TIM peripheral
+ * @param TIM_ICPolarity The Input Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPOLARITY_RISING
+ * @arg TIM_ICPOLARITY_FALLING
+ * @arg TIM_ICPOLARITY_BOTHEDGE
+ * @param TIM_ICSelection specifies the input to be used.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3.
+ * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4.
+ * @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC.
+ * @param TIM_ICFilter Specifies the Input Capture Filter.
+ * This parameter must be a value between 0x00 and 0x0F.
+ * @retval None
+ * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
+ * (on channel1 path) is used as the input signal. Therefore CCMR2 must be
+ * protected against un-initialized filter and polarity values.
+ */
+static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+ uint32_t TIM_ICFilter)
+{
+ uint32_t tmpccmr2;
+ uint32_t tmpccer;
+
+ /* Disable the Channel 3: Reset the CC3E Bit */
+ TIMx->CCER &= ~TIM_CCER_CC3E;
+ tmpccmr2 = TIMx->CCMR2;
+ tmpccer = TIMx->CCER;
+
+ /* Select the Input */
+ tmpccmr2 &= ~TIM_CCMR2_CC3S;
+ tmpccmr2 |= TIM_ICSelection;
+
+ /* Set the filter */
+ tmpccmr2 &= ~TIM_CCMR2_IC3F;
+ tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F);
+
+ /* Select the Polarity and set the CC3E Bit */
+ tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
+ tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));
+
+ /* Write to TIMx CCMR2 and CCER registers */
+ TIMx->CCMR2 = tmpccmr2;
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Configure the TI4 as Input.
+ * @param TIMx to select the TIM peripheral
+ * @param TIM_ICPolarity The Input Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPOLARITY_RISING
+ * @arg TIM_ICPOLARITY_FALLING
+ * @arg TIM_ICPOLARITY_BOTHEDGE
+ * @param TIM_ICSelection specifies the input to be used.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4.
+ * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3.
+ * @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC.
+ * @param TIM_ICFilter Specifies the Input Capture Filter.
+ * This parameter must be a value between 0x00 and 0x0F.
+ * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
+ * (on channel1 path) is used as the input signal. Therefore CCMR2 must be
+ * protected against un-initialized filter and polarity values.
+ * @retval None
+ */
+static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+ uint32_t TIM_ICFilter)
+{
+ uint32_t tmpccmr2;
+ uint32_t tmpccer;
+
+ /* Disable the Channel 4: Reset the CC4E Bit */
+ TIMx->CCER &= ~TIM_CCER_CC4E;
+ tmpccmr2 = TIMx->CCMR2;
+ tmpccer = TIMx->CCER;
+
+ /* Select the Input */
+ tmpccmr2 &= ~TIM_CCMR2_CC4S;
+ tmpccmr2 |= (TIM_ICSelection << 8U);
+
+ /* Set the filter */
+ tmpccmr2 &= ~TIM_CCMR2_IC4F;
+ tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F);
+
+ /* Select the Polarity and set the CC4E Bit */
+ tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
+ tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP));
+
+ /* Write to TIMx CCMR2 and CCER registers */
+ TIMx->CCMR2 = tmpccmr2;
+ TIMx->CCER = tmpccer ;
+}
+
+/**
+ * @brief Selects the Input Trigger source
+ * @param TIMx to select the TIM peripheral
+ * @param InputTriggerSource The Input Trigger source.
+ * This parameter can be one of the following values:
+ * @arg TIM_TS_ITR0: Internal Trigger 0
+ * @arg TIM_TS_ITR1: Internal Trigger 1
+ * @arg TIM_TS_ITR2: Internal Trigger 2
+ * @arg TIM_TS_ITR3: Internal Trigger 3
+ * @arg TIM_TS_TI1F_ED: TI1 Edge Detector
+ * @arg TIM_TS_TI1FP1: Filtered Timer Input 1
+ * @arg TIM_TS_TI2FP2: Filtered Timer Input 2
+ * @arg TIM_TS_ETRF: External Trigger input
+ * @retval None
+ */
+static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
+{
+ uint32_t tmpsmcr;
+
+ /* Get the TIMx SMCR register value */
+ tmpsmcr = TIMx->SMCR;
+ /* Reset the TS Bits */
+ tmpsmcr &= ~TIM_SMCR_TS;
+ /* Set the Input Trigger source and the slave mode*/
+ tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
+ /* Write to TIMx SMCR */
+ TIMx->SMCR = tmpsmcr;
+}
+/**
+ * @brief Configures the TIMx External Trigger (ETR).
+ * @param TIMx to select the TIM peripheral
+ * @param TIM_ExtTRGPrescaler The external Trigger Prescaler.
+ * This parameter can be one of the following values:
+ * @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF.
+ * @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2.
+ * @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4.
+ * @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8.
+ * @param TIM_ExtTRGPolarity The external Trigger Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active.
+ * @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active.
+ * @param ExtTRGFilter External Trigger Filter.
+ * This parameter must be a value between 0x00 and 0x0F
+ * @retval None
+ */
+void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
+ uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
+{
+ uint32_t tmpsmcr;
+
+ tmpsmcr = TIMx->SMCR;
+
+ /* Reset the ETR Bits */
+ tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
+
+ /* Set the Prescaler, the Filter value and the Polarity */
+ tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
+
+ /* Write to TIMx SMCR */
+ TIMx->SMCR = tmpsmcr;
+}
+
+/**
+ * @brief Enables or disables the TIM Capture Compare Channel x.
+ * @param TIMx to select the TIM peripheral
+ * @param Channel specifies the TIM Channel
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1
+ * @arg TIM_CHANNEL_2: TIM Channel 2
+ * @arg TIM_CHANNEL_3: TIM Channel 3
+ * @arg TIM_CHANNEL_4: TIM Channel 4
+ * @arg TIM_CHANNEL_5: TIM Channel 5 selected
+ * @arg TIM_CHANNEL_6: TIM Channel 6 selected
+ * @param ChannelState specifies the TIM Channel CCxE bit new state.
+ * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE.
+ * @retval None
+ */
+void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
+{
+ uint32_t tmp;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CC1_INSTANCE(TIMx));
+ assert_param(IS_TIM_CHANNELS(Channel));
+
+ tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
+
+ /* Reset the CCxE Bit */
+ TIMx->CCER &= ~tmp;
+
+ /* Set or reset the CCxE Bit */
+ TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
+}
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Reset interrupt callbacks to the legacy weak callbacks.
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @retval None
+ */
+void TIM_ResetCallback(TIM_HandleTypeDef *htim)
+{
+ /* Reset the TIM callback to the legacy weak callbacks */
+ htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback;
+ htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback;
+ htim->TriggerCallback = HAL_TIM_TriggerCallback;
+ htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback;
+ htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback;
+ htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback;
+ htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback;
+ htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback;
+ htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback;
+ htim->ErrorCallback = HAL_TIM_ErrorCallback;
+ htim->CommutationCallback = HAL_TIMEx_CommutCallback;
+ htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback;
+ htim->BreakCallback = HAL_TIMEx_BreakCallback;
+ htim->Break2Callback = HAL_TIMEx_Break2Callback;
+}
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_TIM_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c
new file mode 100644
index 0000000000..66c66115de
--- /dev/null
+++ b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c
@@ -0,0 +1,2764 @@
+/**
+ ******************************************************************************
+ * @file stm32c0xx_hal_tim_ex.c
+ * @author MCD Application Team
+ * @brief TIM HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Timer Extended peripheral:
+ * + Time Hall Sensor Interface Initialization
+ * + Time Hall Sensor Interface Start
+ * + Time Complementary signal break and dead time configuration
+ * + Time Master and Slave synchronization configuration
+ * + Time Output Compare/PWM Channel Configuration (for channels 5 and 6)
+ * + Time OCRef clear configuration
+ * + Timer remapping capabilities configuration
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2022 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### TIMER Extended features #####
+ ==============================================================================
+ [..]
+ The Timer Extended features include:
+ (#) Complementary outputs with programmable dead-time for :
+ (++) Output Compare
+ (++) PWM generation (Edge and Center-aligned Mode)
+ (++) One-pulse mode output
+ (#) Synchronization circuit to control the timer with external signals and to
+ interconnect several timers together.
+ (#) Break input to put the timer output signals in reset state or in a known state.
+ (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for
+ positioning purposes
+
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ (#) Initialize the TIM low level resources by implementing the following functions
+ depending on the selected feature:
+ (++) Hall Sensor output : HAL_TIMEx_HallSensor_MspInit()
+
+ (#) Initialize the TIM low level resources :
+ (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
+ (##) TIM pins configuration
+ (+++) Enable the clock for the TIM GPIOs using the following function:
+ __HAL_RCC_GPIOx_CLK_ENABLE();
+ (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
+
+ (#) The external Clock can be configured, if needed (the default clock is the
+ internal clock from the APBx), using the following function:
+ HAL_TIM_ConfigClockSource, the clock configuration should be done before
+ any start function.
+
+ (#) Configure the TIM in the desired functioning mode using one of the
+ initialization function of this driver:
+ (++) HAL_TIMEx_HallSensor_Init() and HAL_TIMEx_ConfigCommutEvent(): to use the
+ Timer Hall Sensor Interface and the commutation event with the corresponding
+ Interrupt and DMA request if needed (Note that One Timer is used to interface
+ with the Hall sensor Interface and another Timer should be used to use
+ the commutation event).
+
+ (#) Activate the TIM peripheral using one of the start functions:
+ (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(),
+ HAL_TIMEx_OCN_Start_IT()
+ (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(),
+ HAL_TIMEx_PWMN_Start_IT()
+ (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT()
+ (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(),
+ HAL_TIMEx_HallSensor_Start_IT().
+
+ @endverbatim
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32c0xx_hal.h"
+
+/** @addtogroup STM32C0xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup TIMEx TIMEx
+ * @brief TIM Extended HAL module driver
+ * @{
+ */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup TIMEx_Private_Constants TIM Extended Private Constants
+ * @{
+ */
+/* Timeout for break input rearm */
+#define TIM_BREAKINPUT_REARM_TIMEOUT 5UL /* 5 milliseconds */
+/**
+ * @}
+ */
+/* End of private constants --------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma);
+static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma);
+static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState);
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup TIMEx_Exported_Functions TIM Extended Exported Functions
+ * @{
+ */
+
+/** @defgroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
+ * @brief Timer Hall Sensor functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Timer Hall Sensor functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Initialize and configure TIM HAL Sensor.
+ (+) De-initialize TIM HAL Sensor.
+ (+) Start the Hall Sensor Interface.
+ (+) Stop the Hall Sensor Interface.
+ (+) Start the Hall Sensor Interface and enable interrupts.
+ (+) Stop the Hall Sensor Interface and disable interrupts.
+ (+) Start the Hall Sensor Interface and enable DMA transfers.
+ (+) Stop the Hall Sensor Interface and disable DMA transfers.
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Initializes the TIM Hall Sensor Interface and initialize the associated handle.
+ * @note When the timer instance is initialized in Hall Sensor Interface mode,
+ * timer channels 1 and channel 2 are reserved and cannot be used for
+ * other purpose.
+ * @param htim TIM Hall Sensor Interface handle
+ * @param sConfig TIM Hall Sensor configuration structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig)
+{
+ TIM_OC_InitTypeDef OC_Config;
+
+ /* Check the TIM handle allocation */
+ if (htim == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+ assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+ assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+ assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
+ assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
+ assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
+
+ if (htim->State == HAL_TIM_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ /* Reset interrupt callbacks to legacy week callbacks */
+ TIM_ResetCallback(htim);
+
+ if (htim->HallSensor_MspInitCallback == NULL)
+ {
+ htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit;
+ }
+ /* Init the low level hardware : GPIO, CLOCK, NVIC */
+ htim->HallSensor_MspInitCallback(htim);
+#else
+ /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+ HAL_TIMEx_HallSensor_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ }
+
+ /* Set the TIM state */
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Configure the Time base in the Encoder Mode */
+ TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+ /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the Hall sensor */
+ TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter);
+
+ /* Reset the IC1PSC Bits */
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
+ /* Set the IC1PSC value */
+ htim->Instance->CCMR1 |= sConfig->IC1Prescaler;
+
+ /* Enable the Hall sensor interface (XOR function of the three inputs) */
+ htim->Instance->CR2 |= TIM_CR2_TI1S;
+
+ /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */
+ htim->Instance->SMCR &= ~TIM_SMCR_TS;
+ htim->Instance->SMCR |= TIM_TS_TI1F_ED;
+
+ /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */
+ htim->Instance->SMCR &= ~TIM_SMCR_SMS;
+ htim->Instance->SMCR |= TIM_SLAVEMODE_RESET;
+
+ /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/
+ OC_Config.OCFastMode = TIM_OCFAST_DISABLE;
+ OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET;
+ OC_Config.OCMode = TIM_OCMODE_PWM2;
+ OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET;
+ OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH;
+ OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH;
+ OC_Config.Pulse = sConfig->Commutation_Delay;
+
+ TIM_OC2_SetConfig(htim->Instance, &OC_Config);
+
+ /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2
+ register to 101 */
+ htim->Instance->CR2 &= ~TIM_CR2_MMS;
+ htim->Instance->CR2 |= TIM_TRGO_OC2REF;
+
+ /* Initialize the DMA burst operation state */
+ htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+
+ /* Initialize the TIM channels state */
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+
+ /* Initialize the TIM state*/
+ htim->State = HAL_TIM_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the TIM Hall Sensor interface
+ * @param htim TIM Hall Sensor Interface handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Disable the TIM Peripheral Clock */
+ __HAL_TIM_DISABLE(htim);
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ if (htim->HallSensor_MspDeInitCallback == NULL)
+ {
+ htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit;
+ }
+ /* DeInit the low level hardware */
+ htim->HallSensor_MspDeInitCallback(htim);
+#else
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+ HAL_TIMEx_HallSensor_MspDeInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+ /* Change the DMA burst operation state */
+ htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
+
+ /* Change the TIM channels state */
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
+
+ /* Change TIM state */
+ htim->State = HAL_TIM_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the TIM Hall Sensor MSP.
+ * @param htim TIM Hall Sensor Interface handle
+ * @retval None
+ */
+__weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes TIM Hall Sensor MSP.
+ * @param htim TIM Hall Sensor Interface handle
+ * @retval None
+ */
+__weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Starts the TIM Hall Sensor Interface.
+ * @param htim TIM Hall Sensor Interface handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim)
+{
+ uint32_t tmpsmcr;
+ HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
+
+ /* Check the parameters */
+ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+
+ /* Check the TIM channels state */
+ if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Set the TIM channels state */
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+
+ /* Enable the Input Capture channel 1
+ (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
+ TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Hall sensor Interface.
+ * @param htim TIM Hall Sensor Interface handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+
+ /* Disable the Input Capture channels 1, 2 and 3
+ (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
+ TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Set the TIM channels state */
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM Hall Sensor Interface in interrupt mode.
+ * @param htim TIM Hall Sensor Interface handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)
+{
+ uint32_t tmpsmcr;
+ HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
+
+ /* Check the parameters */
+ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+
+ /* Check the TIM channels state */
+ if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Set the TIM channels state */
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+
+ /* Enable the capture compare Interrupts 1 event */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+
+ /* Enable the Input Capture channel 1
+ (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
+ TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Hall Sensor Interface in interrupt mode.
+ * @param htim TIM Hall Sensor Interface handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+
+ /* Disable the Input Capture channel 1
+ (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
+ TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+
+ /* Disable the capture compare Interrupts event */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Set the TIM channels state */
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM Hall Sensor Interface in DMA mode.
+ * @param htim TIM Hall Sensor Interface handle
+ * @param pData The destination Buffer address.
+ * @param Length The length of data to be transferred from TIM peripheral to memory.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
+{
+ uint32_t tmpsmcr;
+ HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
+
+ /* Check the parameters */
+ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+
+ /* Set the TIM channel state */
+ if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
+ || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY))
+ {
+ return HAL_BUSY;
+ }
+ else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
+ && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY))
+ {
+ if ((pData == NULL) && (Length > 0U))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ }
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+
+ /* Enable the Input Capture channel 1
+ (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
+ TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+
+ /* Set the DMA Input Capture 1 Callbacks */
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel for Capture 1*/
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK)
+ {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ /* Enable the capture compare 1 Interrupt */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Hall Sensor Interface in DMA mode.
+ * @param htim TIM Hall Sensor Interface handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+
+ /* Disable the Input Capture channel 1
+ (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
+ TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+
+
+ /* Disable the capture compare Interrupts 1 event */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Set the TIM channel state */
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
+ * @brief Timer Complementary Output Compare functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Timer Complementary Output Compare functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Start the Complementary Output Compare/PWM.
+ (+) Stop the Complementary Output Compare/PWM.
+ (+) Start the Complementary Output Compare/PWM and enable interrupts.
+ (+) Stop the Complementary Output Compare/PWM and disable interrupts.
+ (+) Start the Complementary Output Compare/PWM and enable DMA transfers.
+ (+) Stop the Complementary Output Compare/PWM and disable DMA transfers.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Starts the TIM Output Compare signal generation on the complementary
+ * output.
+ * @param htim TIM Output Compare handle
+ * @param Channel TIM Channel to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ uint32_t tmpsmcr;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+ /* Check the TIM complementary channel state */
+ if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Set the TIM complementary channel state */
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
+ /* Enable the Capture compare channel N */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+ /* Enable the Main Output */
+ __HAL_TIM_MOE_ENABLE(htim);
+
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Output Compare signal generation on the complementary
+ * output.
+ * @param htim TIM handle
+ * @param Channel TIM Channel to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+ /* Disable the Capture compare channel N */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+ /* Disable the Main Output */
+ __HAL_TIM_MOE_DISABLE(htim);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Set the TIM complementary channel state */
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM Output Compare signal generation in interrupt mode
+ * on the complementary output.
+ * @param htim TIM OC handle
+ * @param Channel TIM Channel to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t tmpsmcr;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+ /* Check the TIM complementary channel state */
+ if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Set the TIM complementary channel state */
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Enable the TIM Output Compare interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+ break;
+ }
+
+ case TIM_CHANNEL_2:
+ {
+ /* Enable the TIM Output Compare interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+ break;
+ }
+
+ case TIM_CHANNEL_3:
+ {
+ /* Enable the TIM Output Compare interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+ break;
+ }
+
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ if (status == HAL_OK)
+ {
+ /* Enable the TIM Break interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
+
+ /* Enable the Capture compare channel N */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+ /* Enable the Main Output */
+ __HAL_TIM_MOE_ENABLE(htim);
+
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Stops the TIM Output Compare signal generation in interrupt mode
+ * on the complementary output.
+ * @param htim TIM Output Compare handle
+ * @param Channel TIM Channel to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t tmpccer;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Disable the TIM Output Compare interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+ break;
+ }
+
+ case TIM_CHANNEL_2:
+ {
+ /* Disable the TIM Output Compare interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+ break;
+ }
+
+ case TIM_CHANNEL_3:
+ {
+ /* Disable the TIM Output Compare interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+ break;
+ }
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ if (status == HAL_OK)
+ {
+ /* Disable the Capture compare channel N */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+ /* Disable the TIM Break interrupt (only if no more channel is active) */
+ tmpccer = htim->Instance->CCER;
+ if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET)
+ {
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
+ }
+
+ /* Disable the Main Output */
+ __HAL_TIM_MOE_DISABLE(htim);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Set the TIM complementary channel state */
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Starts the TIM Output Compare signal generation in DMA mode
+ * on the complementary output.
+ * @param htim TIM Output Compare handle
+ * @param Channel TIM Channel to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @param pData The source Buffer address.
+ * @param Length The length of data to be transferred from memory to TIM peripheral
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t tmpsmcr;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+ /* Set the TIM complementary channel state */
+ if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+ else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
+ {
+ if ((pData == NULL) && (Length > 0U))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ }
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Set the DMA compare callbacks */
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt;
+ htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
+ Length) != HAL_OK)
+ {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ /* Enable the TIM Output Compare DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+ break;
+ }
+
+ case TIM_CHANNEL_2:
+ {
+ /* Set the DMA compare callbacks */
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt;
+ htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
+ Length) != HAL_OK)
+ {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ /* Enable the TIM Output Compare DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+ break;
+ }
+
+ case TIM_CHANNEL_3:
+ {
+ /* Set the DMA compare callbacks */
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt;
+ htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
+ Length) != HAL_OK)
+ {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ /* Enable the TIM Output Compare DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+ break;
+ }
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ if (status == HAL_OK)
+ {
+ /* Enable the Capture compare channel N */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+ /* Enable the Main Output */
+ __HAL_TIM_MOE_ENABLE(htim);
+
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Stops the TIM Output Compare signal generation in DMA mode
+ * on the complementary output.
+ * @param htim TIM Output Compare handle
+ * @param Channel TIM Channel to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Disable the TIM Output Compare DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+ break;
+ }
+
+ case TIM_CHANNEL_2:
+ {
+ /* Disable the TIM Output Compare DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+ break;
+ }
+
+ case TIM_CHANNEL_3:
+ {
+ /* Disable the TIM Output Compare DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+ break;
+ }
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ if (status == HAL_OK)
+ {
+ /* Disable the Capture compare channel N */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+ /* Disable the Main Output */
+ __HAL_TIM_MOE_DISABLE(htim);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Set the TIM complementary channel state */
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
+ * @brief Timer Complementary PWM functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Timer Complementary PWM functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Start the Complementary PWM.
+ (+) Stop the Complementary PWM.
+ (+) Start the Complementary PWM and enable interrupts.
+ (+) Stop the Complementary PWM and disable interrupts.
+ (+) Start the Complementary PWM and enable DMA transfers.
+ (+) Stop the Complementary PWM and disable DMA transfers.
+ (+) Start the Complementary Input Capture measurement.
+ (+) Stop the Complementary Input Capture.
+ (+) Start the Complementary Input Capture and enable interrupts.
+ (+) Stop the Complementary Input Capture and disable interrupts.
+ (+) Start the Complementary Input Capture and enable DMA transfers.
+ (+) Stop the Complementary Input Capture and disable DMA transfers.
+ (+) Start the Complementary One Pulse generation.
+ (+) Stop the Complementary One Pulse.
+ (+) Start the Complementary One Pulse and enable interrupts.
+ (+) Stop the Complementary One Pulse and disable interrupts.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Starts the PWM signal generation on the complementary output.
+ * @param htim TIM handle
+ * @param Channel TIM Channel to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ uint32_t tmpsmcr;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+ /* Check the TIM complementary channel state */
+ if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Set the TIM complementary channel state */
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
+ /* Enable the complementary PWM output */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+ /* Enable the Main Output */
+ __HAL_TIM_MOE_ENABLE(htim);
+
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the PWM signal generation on the complementary output.
+ * @param htim TIM handle
+ * @param Channel TIM Channel to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+ /* Disable the complementary PWM output */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+ /* Disable the Main Output */
+ __HAL_TIM_MOE_DISABLE(htim);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Set the TIM complementary channel state */
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the PWM signal generation in interrupt mode on the
+ * complementary output.
+ * @param htim TIM handle
+ * @param Channel TIM Channel to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t tmpsmcr;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+ /* Check the TIM complementary channel state */
+ if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Set the TIM complementary channel state */
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Enable the TIM Capture/Compare 1 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+ break;
+ }
+
+ case TIM_CHANNEL_2:
+ {
+ /* Enable the TIM Capture/Compare 2 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+ break;
+ }
+
+ case TIM_CHANNEL_3:
+ {
+ /* Enable the TIM Capture/Compare 3 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+ break;
+ }
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ if (status == HAL_OK)
+ {
+ /* Enable the TIM Break interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
+
+ /* Enable the complementary PWM output */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+ /* Enable the Main Output */
+ __HAL_TIM_MOE_ENABLE(htim);
+
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Stops the PWM signal generation in interrupt mode on the
+ * complementary output.
+ * @param htim TIM handle
+ * @param Channel TIM Channel to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t tmpccer;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Disable the TIM Capture/Compare 1 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+ break;
+ }
+
+ case TIM_CHANNEL_2:
+ {
+ /* Disable the TIM Capture/Compare 2 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+ break;
+ }
+
+ case TIM_CHANNEL_3:
+ {
+ /* Disable the TIM Capture/Compare 3 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+ break;
+ }
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ if (status == HAL_OK)
+ {
+ /* Disable the complementary PWM output */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+ /* Disable the TIM Break interrupt (only if no more channel is active) */
+ tmpccer = htim->Instance->CCER;
+ if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET)
+ {
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
+ }
+
+ /* Disable the Main Output */
+ __HAL_TIM_MOE_DISABLE(htim);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Set the TIM complementary channel state */
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Starts the TIM PWM signal generation in DMA mode on the
+ * complementary output
+ * @param htim TIM handle
+ * @param Channel TIM Channel to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @param pData The source Buffer address.
+ * @param Length The length of data to be transferred from memory to TIM peripheral
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t tmpsmcr;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+ /* Set the TIM complementary channel state */
+ if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+ else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
+ {
+ if ((pData == NULL) && (Length > 0U))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ }
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Set the DMA compare callbacks */
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt;
+ htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
+ Length) != HAL_OK)
+ {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ /* Enable the TIM Capture/Compare 1 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+ break;
+ }
+
+ case TIM_CHANNEL_2:
+ {
+ /* Set the DMA compare callbacks */
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt;
+ htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
+ Length) != HAL_OK)
+ {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ /* Enable the TIM Capture/Compare 2 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+ break;
+ }
+
+ case TIM_CHANNEL_3:
+ {
+ /* Set the DMA compare callbacks */
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt;
+ htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
+ Length) != HAL_OK)
+ {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ /* Enable the TIM Capture/Compare 3 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+ break;
+ }
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ if (status == HAL_OK)
+ {
+ /* Enable the complementary PWM output */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+ /* Enable the Main Output */
+ __HAL_TIM_MOE_ENABLE(htim);
+
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Stops the TIM PWM signal generation in DMA mode on the complementary
+ * output
+ * @param htim TIM handle
+ * @param Channel TIM Channel to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Disable the TIM Capture/Compare 1 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+ break;
+ }
+
+ case TIM_CHANNEL_2:
+ {
+ /* Disable the TIM Capture/Compare 2 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+ break;
+ }
+
+ case TIM_CHANNEL_3:
+ {
+ /* Disable the TIM Capture/Compare 3 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+ break;
+ }
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ if (status == HAL_OK)
+ {
+ /* Disable the complementary PWM output */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+ /* Disable the Main Output */
+ __HAL_TIM_MOE_DISABLE(htim);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Set the TIM complementary channel state */
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
+ * @brief Timer Complementary One Pulse functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Timer Complementary One Pulse functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Start the Complementary One Pulse generation.
+ (+) Stop the Complementary One Pulse.
+ (+) Start the Complementary One Pulse and enable interrupts.
+ (+) Stop the Complementary One Pulse and disable interrupts.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Starts the TIM One Pulse signal generation on the complementary
+ * output.
+ * @note OutputChannel must match the pulse output channel chosen when calling
+ * @ref HAL_TIM_OnePulse_ConfigChannel().
+ * @param htim TIM One Pulse handle
+ * @param OutputChannel pulse output channel to enable
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+ uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
+ HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
+
+ /* Check the TIM channels state */
+ if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Set the TIM channels state */
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+
+ /* Enable the complementary One Pulse output channel and the Input Capture channel */
+ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
+ TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE);
+
+ /* Enable the Main Output */
+ __HAL_TIM_MOE_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM One Pulse signal generation on the complementary
+ * output.
+ * @note OutputChannel must match the pulse output channel chosen when calling
+ * @ref HAL_TIM_OnePulse_ConfigChannel().
+ * @param htim TIM One Pulse handle
+ * @param OutputChannel pulse output channel to disable
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+ uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
+
+ /* Disable the complementary One Pulse output channel and the Input Capture channel */
+ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
+ TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE);
+
+ /* Disable the Main Output */
+ __HAL_TIM_MOE_DISABLE(htim);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Set the TIM channels state */
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM One Pulse signal generation in interrupt mode on the
+ * complementary channel.
+ * @note OutputChannel must match the pulse output channel chosen when calling
+ * @ref HAL_TIM_OnePulse_ConfigChannel().
+ * @param htim TIM One Pulse handle
+ * @param OutputChannel pulse output channel to enable
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+ uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
+ HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
+
+ /* Check the TIM channels state */
+ if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Set the TIM channels state */
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+
+ /* Enable the TIM Capture/Compare 1 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+
+ /* Enable the TIM Capture/Compare 2 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+
+ /* Enable the complementary One Pulse output channel and the Input Capture channel */
+ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
+ TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE);
+
+ /* Enable the Main Output */
+ __HAL_TIM_MOE_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM One Pulse signal generation in interrupt mode on the
+ * complementary channel.
+ * @note OutputChannel must match the pulse output channel chosen when calling
+ * @ref HAL_TIM_OnePulse_ConfigChannel().
+ * @param htim TIM One Pulse handle
+ * @param OutputChannel pulse output channel to disable
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+ uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
+
+ /* Disable the TIM Capture/Compare 1 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+
+ /* Disable the TIM Capture/Compare 2 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+
+ /* Disable the complementary One Pulse output channel and the Input Capture channel */
+ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
+ TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE);
+
+ /* Disable the Main Output */
+ __HAL_TIM_MOE_DISABLE(htim);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Set the TIM channels state */
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
+ * @brief Peripheral Control functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral Control functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Configure the commutation event in case of use of the Hall sensor interface.
+ (+) Configure Output channels for OC and PWM mode.
+
+ (+) Configure Complementary channels, break features and dead time.
+ (+) Configure Master synchronization.
+ (+) Configure timer remapping capabilities.
+ (+) Select timer input source.
+ (+) Enable or disable channel grouping.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configure the TIM commutation event sequence.
+ * @note This function is mandatory to use the commutation event in order to
+ * update the configuration at each commutation detection on the TRGI input of the Timer,
+ * the typical use of this feature is with the use of another Timer(interface Timer)
+ * configured in Hall sensor interface, this interface Timer will generate the
+ * commutation at its TRGO output (connected to Timer used in this function) each time
+ * the TI1 of the Interface Timer detect a commutation at its input TI1.
+ * @param htim TIM handle
+ * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
+ * This parameter can be one of the following values:
+ * @arg TIM_TS_ITR0: Internal trigger 0 selected
+ * @arg TIM_TS_ITR1: Internal trigger 1 selected
+ * @arg TIM_TS_ITR2: Internal trigger 2 selected
+ * @arg TIM_TS_ITR3: Internal trigger 3 selected
+ * @arg TIM_TS_NONE: No trigger is needed
+ * @param CommutationSource the Commutation Event source
+ * This parameter can be one of the following values:
+ * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
+ * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
+ uint32_t CommutationSource)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
+
+ __HAL_LOCK(htim);
+
+ if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
+ (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
+ {
+ /* Select the Input trigger */
+ htim->Instance->SMCR &= ~TIM_SMCR_TS;
+ htim->Instance->SMCR |= InputTrigger;
+ }
+
+ /* Select the Capture Compare preload feature */
+ htim->Instance->CR2 |= TIM_CR2_CCPC;
+ /* Select the Commutation event source */
+ htim->Instance->CR2 &= ~TIM_CR2_CCUS;
+ htim->Instance->CR2 |= CommutationSource;
+
+ /* Disable Commutation Interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM);
+
+ /* Disable Commutation DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM);
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configure the TIM commutation event sequence with interrupt.
+ * @note This function is mandatory to use the commutation event in order to
+ * update the configuration at each commutation detection on the TRGI input of the Timer,
+ * the typical use of this feature is with the use of another Timer(interface Timer)
+ * configured in Hall sensor interface, this interface Timer will generate the
+ * commutation at its TRGO output (connected to Timer used in this function) each time
+ * the TI1 of the Interface Timer detect a commutation at its input TI1.
+ * @param htim TIM handle
+ * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
+ * This parameter can be one of the following values:
+ * @arg TIM_TS_ITR0: Internal trigger 0 selected
+ * @arg TIM_TS_ITR1: Internal trigger 1 selected
+ * @arg TIM_TS_ITR2: Internal trigger 2 selected
+ * @arg TIM_TS_ITR3: Internal trigger 3 selected
+ * @arg TIM_TS_NONE: No trigger is needed
+ * @param CommutationSource the Commutation Event source
+ * This parameter can be one of the following values:
+ * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
+ * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
+ uint32_t CommutationSource)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
+
+ __HAL_LOCK(htim);
+
+ if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
+ (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
+ {
+ /* Select the Input trigger */
+ htim->Instance->SMCR &= ~TIM_SMCR_TS;
+ htim->Instance->SMCR |= InputTrigger;
+ }
+
+ /* Select the Capture Compare preload feature */
+ htim->Instance->CR2 |= TIM_CR2_CCPC;
+ /* Select the Commutation event source */
+ htim->Instance->CR2 &= ~TIM_CR2_CCUS;
+ htim->Instance->CR2 |= CommutationSource;
+
+ /* Disable Commutation DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM);
+
+ /* Enable the Commutation Interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM);
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configure the TIM commutation event sequence with DMA.
+ * @note This function is mandatory to use the commutation event in order to
+ * update the configuration at each commutation detection on the TRGI input of the Timer,
+ * the typical use of this feature is with the use of another Timer(interface Timer)
+ * configured in Hall sensor interface, this interface Timer will generate the
+ * commutation at its TRGO output (connected to Timer used in this function) each time
+ * the TI1 of the Interface Timer detect a commutation at its input TI1.
+ * @note The user should configure the DMA in his own software, in This function only the COMDE bit is set
+ * @param htim TIM handle
+ * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
+ * This parameter can be one of the following values:
+ * @arg TIM_TS_ITR0: Internal trigger 0 selected
+ * @arg TIM_TS_ITR1: Internal trigger 1 selected
+ * @arg TIM_TS_ITR2: Internal trigger 2 selected
+ * @arg TIM_TS_ITR3: Internal trigger 3 selected
+ * @arg TIM_TS_NONE: No trigger is needed
+ * @param CommutationSource the Commutation Event source
+ * This parameter can be one of the following values:
+ * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
+ * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
+ uint32_t CommutationSource)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
+
+ __HAL_LOCK(htim);
+
+ if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
+ (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
+ {
+ /* Select the Input trigger */
+ htim->Instance->SMCR &= ~TIM_SMCR_TS;
+ htim->Instance->SMCR |= InputTrigger;
+ }
+
+ /* Select the Capture Compare preload feature */
+ htim->Instance->CR2 |= TIM_CR2_CCPC;
+ /* Select the Commutation event source */
+ htim->Instance->CR2 &= ~TIM_CR2_CCUS;
+ htim->Instance->CR2 |= CommutationSource;
+
+ /* Enable the Commutation DMA Request */
+ /* Set the DMA Commutation Callback */
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt;
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError;
+
+ /* Disable Commutation Interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM);
+
+ /* Enable the Commutation DMA Request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM);
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configures the TIM in master mode.
+ * @param htim TIM handle.
+ * @param sMasterConfig pointer to a TIM_MasterConfigTypeDef structure that
+ * contains the selected trigger output (TRGO) and the Master/Slave
+ * mode.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
+ TIM_MasterConfigTypeDef *sMasterConfig)
+{
+ uint32_t tmpcr2;
+ uint32_t tmpsmcr;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
+ assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
+
+ /* Check input state */
+ __HAL_LOCK(htim);
+
+ /* Change the handler state */
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = htim->Instance->CR2;
+
+ /* Get the TIMx SMCR register value */
+ tmpsmcr = htim->Instance->SMCR;
+
+ /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */
+ if (IS_TIM_TRGO2_INSTANCE(htim->Instance))
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2));
+
+ /* Clear the MMS2 bits */
+ tmpcr2 &= ~TIM_CR2_MMS2;
+ /* Select the TRGO2 source*/
+ tmpcr2 |= sMasterConfig->MasterOutputTrigger2;
+ }
+
+ /* Reset the MMS Bits */
+ tmpcr2 &= ~TIM_CR2_MMS;
+ /* Select the TRGO source */
+ tmpcr2 |= sMasterConfig->MasterOutputTrigger;
+
+ /* Update TIMx CR2 */
+ htim->Instance->CR2 = tmpcr2;
+
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ /* Reset the MSM Bit */
+ tmpsmcr &= ~TIM_SMCR_MSM;
+ /* Set master mode */
+ tmpsmcr |= sMasterConfig->MasterSlaveMode;
+
+ /* Update TIMx SMCR */
+ htim->Instance->SMCR = tmpsmcr;
+ }
+
+ /* Change the htim state */
+ htim->State = HAL_TIM_STATE_READY;
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State
+ * and the AOE(automatic output enable).
+ * @param htim TIM handle
+ * @param sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that
+ * contains the BDTR Register configuration information for the TIM peripheral.
+ * @note Interrupts can be generated when an active level is detected on the
+ * break input, the break 2 input or the system break input. Break
+ * interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
+ TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
+{
+ /* Keep this variable initialized to 0 as it is used to configure BDTR register */
+ uint32_t tmpbdtr = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode));
+ assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode));
+ assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel));
+ assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime));
+ assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState));
+ assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
+ assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter));
+ assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
+
+ /* Check input state */
+ __HAL_LOCK(htim);
+
+ /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
+ the OSSI State, the dead time value and the Automatic Output Enable Bit */
+
+ /* Set the BDTR bits */
+ MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos));
+
+ if (IS_TIM_ADVANCED_INSTANCE(htim->Instance))
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_BREAK_AFMODE(sBreakDeadTimeConfig->BreakAFMode));
+
+ /* Set BREAK AF mode */
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, sBreakDeadTimeConfig->BreakAFMode);
+ }
+
+ if (IS_TIM_BKIN2_INSTANCE(htim->Instance))
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State));
+ assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity));
+ assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter));
+
+ /* Set the BREAK2 input related BDTR bits */
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << TIM_BDTR_BK2F_Pos));
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity);
+
+ if (IS_TIM_ADVANCED_INSTANCE(htim->Instance))
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_BREAK2_AFMODE(sBreakDeadTimeConfig->Break2AFMode));
+
+ /* Set BREAK2 AF mode */
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, sBreakDeadTimeConfig->Break2AFMode);
+ }
+ }
+
+ /* Set TIMx_BDTR */
+ htim->Instance->BDTR = tmpbdtr;
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configures the break input source.
+ * @param htim TIM handle.
+ * @param BreakInput Break input to configure
+ * This parameter can be one of the following values:
+ * @arg TIM_BREAKINPUT_BRK: Timer break input
+ * @arg TIM_BREAKINPUT_BRK2: Timer break 2 input
+ * @param sBreakInputConfig Break input source configuration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim,
+ uint32_t BreakInput,
+ TIMEx_BreakInputConfigTypeDef *sBreakInputConfig)
+
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t tmporx;
+ uint32_t bkin_enable_mask;
+ uint32_t bkin_polarity_mask;
+ uint32_t bkin_enable_bitpos;
+ uint32_t bkin_polarity_bitpos;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_BREAKINPUT(BreakInput));
+ assert_param(IS_TIM_BREAKINPUTSOURCE(sBreakInputConfig->Source));
+ assert_param(IS_TIM_BREAKINPUTSOURCE_STATE(sBreakInputConfig->Enable));
+ assert_param(IS_TIM_BREAKINPUTSOURCE_POLARITY(sBreakInputConfig->Polarity));
+
+ /* Check input state */
+ __HAL_LOCK(htim);
+
+ switch (sBreakInputConfig->Source)
+ {
+ case TIM_BREAKINPUTSOURCE_BKIN:
+ {
+ bkin_enable_mask = TIM1_AF1_BKINE;
+ bkin_enable_bitpos = TIM1_AF1_BKINE_Pos;
+ bkin_polarity_mask = TIM1_AF1_BKINP;
+ bkin_polarity_bitpos = TIM1_AF1_BKINP_Pos;
+ break;
+ }
+
+ default:
+ {
+ bkin_enable_mask = 0U;
+ bkin_polarity_mask = 0U;
+ bkin_enable_bitpos = 0U;
+ bkin_polarity_bitpos = 0U;
+ break;
+ }
+ }
+
+ switch (BreakInput)
+ {
+ case TIM_BREAKINPUT_BRK:
+ {
+ /* Get the TIMx_AF1 register value */
+ tmporx = htim->Instance->AF1;
+
+ /* Enable the break input */
+ tmporx &= ~bkin_enable_mask;
+ tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask;
+
+ /* Set the break input polarity */
+ tmporx &= ~bkin_polarity_mask;
+ tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask;
+
+ /* Set TIMx_AF1 */
+ htim->Instance->AF1 = tmporx;
+ break;
+ }
+ case TIM_BREAKINPUT_BRK2:
+ {
+ /* Get the TIMx_AF2 register value */
+ tmporx = htim->Instance->AF2;
+
+ /* Enable the break input */
+ tmporx &= ~bkin_enable_mask;
+ tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask;
+
+ /* Set the break input polarity */
+ tmporx &= ~bkin_polarity_mask;
+ tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask;
+
+ /* Set TIMx_AF2 */
+ htim->Instance->AF2 = tmporx;
+ break;
+ }
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ __HAL_UNLOCK(htim);
+
+ return status;
+}
+
+/**
+ * @brief Configures the TIMx Remapping input capabilities.
+ * @param htim TIM handle.
+ * @param Remap specifies the TIM remapping source.
+ *
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)
+{
+ /* Check parameters */
+ assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_REMAP(Remap));
+
+ __HAL_LOCK(htim);
+
+ MODIFY_REG(htim->Instance->AF1, TIM1_AF1_ETRSEL_Msk, Remap);
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Select the timer input source
+ * @param htim TIM handle.
+ * @param TISelection specifies the timer input source
+ * @param Channel specifies the TIM Channel
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TI1 input channel
+ * @arg TIM_CHANNEL_2: TI2 input channel
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_TISelection(TIM_HandleTypeDef *htim, uint32_t TISelection, uint32_t Channel)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check parameters */
+ assert_param(IS_TIM_TISEL_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_TISEL(TISelection));
+
+ __HAL_LOCK(htim);
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI1SEL, TISelection);
+ break;
+ case TIM_CHANNEL_2:
+ MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI2SEL, TISelection);
+ break;
+ case TIM_CHANNEL_3:
+ MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI3SEL, TISelection);
+ break;
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ __HAL_UNLOCK(htim);
+
+ return status;
+}
+
+/**
+ * @brief Group channel 5 and channel 1, 2 or 3
+ * @param htim TIM handle.
+ * @param Channels specifies the reference signal(s) the OC5REF is combined with.
+ * This parameter can be any combination of the following values:
+ * TIM_GROUPCH5_NONE: No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC
+ * TIM_GROUPCH5_OC1REFC: OC1REFC is the logical AND of OC1REFC and OC5REF
+ * TIM_GROUPCH5_OC2REFC: OC2REFC is the logical AND of OC2REFC and OC5REF
+ * TIM_GROUPCH5_OC3REFC: OC3REFC is the logical AND of OC3REFC and OC5REF
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels)
+{
+ /* Check parameters */
+ assert_param(IS_TIM_COMBINED3PHASEPWM_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_GROUPCH5(Channels));
+
+ /* Process Locked */
+ __HAL_LOCK(htim);
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Clear GC5Cx bit fields */
+ htim->Instance->CCR5 &= ~(TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1);
+
+ /* Set GC5Cx bit fields */
+ htim->Instance->CCR5 |= Channels;
+
+ /* Change the htim state */
+ htim->State = HAL_TIM_STATE_READY;
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disarm the designated break input (when it operates in bidirectional mode).
+ * @param htim TIM handle.
+ * @param BreakInput Break input to disarm
+ * This parameter can be one of the following values:
+ * @arg TIM_BREAKINPUT_BRK: Timer break input
+ * @arg TIM_BREAKINPUT_BRK2: Timer break 2 input
+ * @note The break input can be disarmed only when it is configured in
+ * bidirectional mode and when when MOE is reset.
+ * @note Purpose is to be able to have the input voltage back to high-state,
+ * whatever the time constant on the output .
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_DisarmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t tmpbdtr;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_ADVANCED_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_BREAKINPUT(BreakInput));
+
+ switch (BreakInput)
+ {
+ case TIM_BREAKINPUT_BRK:
+ {
+ /* Check initial conditions */
+ tmpbdtr = READ_REG(htim->Instance->BDTR);
+ if ((READ_BIT(tmpbdtr, TIM_BDTR_BKBID) == TIM_BDTR_BKBID) &&
+ (READ_BIT(tmpbdtr, TIM_BDTR_MOE) == 0U))
+ {
+ /* Break input BRK is disarmed */
+ SET_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM);
+ }
+ break;
+ }
+
+ case TIM_BREAKINPUT_BRK2:
+ {
+ /* Check initial conditions */
+ tmpbdtr = READ_REG(htim->Instance->BDTR);
+ if ((READ_BIT(tmpbdtr, TIM_BDTR_BK2BID) == TIM_BDTR_BK2BID) &&
+ (READ_BIT(tmpbdtr, TIM_BDTR_MOE) == 0U))
+ {
+ /* Break input BRK is disarmed */
+ SET_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM);
+ }
+ break;
+ }
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Arm the designated break input (when it operates in bidirectional mode).
+ * @param htim TIM handle.
+ * @param BreakInput Break input to arm
+ * This parameter can be one of the following values:
+ * @arg TIM_BREAKINPUT_BRK: Timer break input
+ * @arg TIM_BREAKINPUT_BRK2: Timer break 2 input
+ * @note Arming is possible at anytime, even if fault is present.
+ * @note Break input is automatically armed as soon as MOE bit is set.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t tickstart;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_ADVANCED_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_BREAKINPUT(BreakInput));
+
+ switch (BreakInput)
+ {
+ case TIM_BREAKINPUT_BRK:
+ {
+ /* Check initial conditions */
+ if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKBID) == TIM_BDTR_BKBID)
+ {
+ /* Break input BRK is re-armed automatically by hardware. Poll to check whether fault condition disappeared */
+ /* Init tickstart for timeout management */
+ tickstart = HAL_GetTick();
+ while (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM) != 0UL)
+ {
+ if ((HAL_GetTick() - tickstart) > TIM_BREAKINPUT_REARM_TIMEOUT)
+ {
+ /* New check to avoid false timeout detection in case of preemption */
+ if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM) != 0UL)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ break;
+ }
+
+ case TIM_BREAKINPUT_BRK2:
+ {
+ /* Check initial conditions */
+ if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2BID) == TIM_BDTR_BK2BID)
+ {
+ /* Break input BRK2 is re-armed automatically by hardware. Poll to check whether fault condition disappeared */
+ /* Init tickstart for timeout management */
+ tickstart = HAL_GetTick();
+ while (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM) != 0UL)
+ {
+ if ((HAL_GetTick() - tickstart) > TIM_BREAKINPUT_REARM_TIMEOUT)
+ {
+ /* New check to avoid false timeout detection in case of preemption */
+ if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM) != 0UL)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ break;
+ }
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ return status;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions
+ * @brief Extended Callbacks functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Extended Callbacks functions #####
+ ==============================================================================
+ [..]
+ This section provides Extended TIM callback functions:
+ (+) Timer Commutation callback
+ (+) Timer Break callback
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Hall commutation changed callback in non-blocking mode
+ * @param htim TIM handle
+ * @retval None
+ */
+__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIMEx_CommutCallback could be implemented in the user file
+ */
+}
+/**
+ * @brief Hall commutation changed half complete callback in non-blocking mode
+ * @param htim TIM handle
+ * @retval None
+ */
+__weak void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIMEx_CommutHalfCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Hall Break detection callback in non-blocking mode
+ * @param htim TIM handle
+ * @retval None
+ */
+__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIMEx_BreakCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Hall Break2 detection callback in non blocking mode
+ * @param htim: TIM handle
+ * @retval None
+ */
+__weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_TIMEx_Break2Callback could be implemented in the user file
+ */
+}
+/**
+ * @}
+ */
+
+/** @defgroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions
+ * @brief Extended Peripheral State functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Extended Peripheral State functions #####
+ ==============================================================================
+ [..]
+ This subsection permits to get in run-time the status of the peripheral
+ and the data flow.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the TIM Hall Sensor interface handle state.
+ * @param htim TIM Hall Sensor handle
+ * @retval HAL state
+ */
+HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim)
+{
+ return htim->State;
+}
+
+/**
+ * @brief Return actual state of the TIM complementary channel.
+ * @param htim TIM handle
+ * @param ChannelN TIM Complementary channel
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1
+ * @arg TIM_CHANNEL_2: TIM Channel 2
+ * @arg TIM_CHANNEL_3: TIM Channel 3
+ * @retval TIM Complementary channel state
+ */
+HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, uint32_t ChannelN)
+{
+ HAL_TIM_ChannelStateTypeDef channel_state;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, ChannelN));
+
+ channel_state = TIM_CHANNEL_N_STATE_GET(htim, ChannelN);
+
+ return channel_state;
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup TIMEx_Private_Functions TIM Extended Private Functions
+ * @{
+ */
+
+/**
+ * @brief TIM DMA Commutation callback.
+ * @param hdma pointer to DMA handle.
+ * @retval None
+ */
+void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma)
+{
+ TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ /* Change the htim state */
+ htim->State = HAL_TIM_STATE_READY;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->CommutationCallback(htim);
+#else
+ HAL_TIMEx_CommutCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief TIM DMA Commutation half complete callback.
+ * @param hdma pointer to DMA handle.
+ * @retval None
+ */
+void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma)
+{
+ TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ /* Change the htim state */
+ htim->State = HAL_TIM_STATE_READY;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->CommutationHalfCpltCallback(htim);
+#else
+ HAL_TIMEx_CommutHalfCpltCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+}
+
+
+/**
+ * @brief TIM DMA Delay Pulse complete callback (complementary channel).
+ * @param hdma pointer to DMA handle.
+ * @retval None
+ */
+static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma)
+{
+ TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ if (hdma == htim->hdma[TIM_DMA_ID_CC1])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+
+ if (hdma->Init.Mode == DMA_NORMAL)
+ {
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ }
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+
+ if (hdma->Init.Mode == DMA_NORMAL)
+ {
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ }
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+
+ if (hdma->Init.Mode == DMA_NORMAL)
+ {
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
+ }
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+
+ if (hdma->Init.Mode == DMA_NORMAL)
+ {
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
+ }
+ }
+ else
+ {
+ /* nothing to do */
+ }
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->PWM_PulseFinishedCallback(htim);
+#else
+ HAL_TIM_PWM_PulseFinishedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+}
+
+/**
+ * @brief TIM DMA error callback (complementary channel)
+ * @param hdma pointer to DMA handle.
+ * @retval None
+ */
+static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma)
+{
+ TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ if (hdma == htim->hdma[TIM_DMA_ID_CC1])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
+ }
+ else
+ {
+ /* nothing to do */
+ }
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->ErrorCallback(htim);
+#else
+ HAL_TIM_ErrorCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+}
+
+/**
+ * @brief Enables or disables the TIM Capture Compare Channel xN.
+ * @param TIMx to select the TIM peripheral
+ * @param Channel specifies the TIM Channel
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1
+ * @arg TIM_CHANNEL_2: TIM Channel 2
+ * @arg TIM_CHANNEL_3: TIM Channel 3
+ * @param ChannelNState specifies the TIM Channel CCxNE bit new state.
+ * This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable.
+ * @retval None
+ */
+static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState)
+{
+ uint32_t tmp;
+
+ tmp = TIM_CCER_CC1NE << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
+
+ /* Reset the CCxNE Bit */
+ TIMx->CCER &= ~tmp;
+
+ /* Set or reset the CCxNE Bit */
+ TIMx->CCER |= (uint32_t)(ChannelNState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
+}
+/**
+ * @}
+ */
+
+#endif /* HAL_TIM_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_timebase_rtc_alarm_template.c b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_timebase_rtc_alarm_template.c
new file mode 100644
index 0000000000..ee6888d684
--- /dev/null
+++ b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_timebase_rtc_alarm_template.c
@@ -0,0 +1,295 @@
+/**
+ ******************************************************************************
+ * @file stm32c0xx_hal_timebase_rtc_alarm_template.c
+ * @author MCD Application Team
+ * @brief HAL time base based on the hardware RTC_ALARM Template.
+ *
+ * This file overrides the native HAL time base functions (defined as weak)
+ * to use the RTC ALARM for time base generation:
+ * + Initializes the RTC peripheral to increment the seconds registers each 1ms
+ * + The alarm is configured to assert an interrupt when the RTC reaches 1ms
+ * + HAL_IncTick is called at each Alarm event
+ * + HSE (default), LSE or LSI can be selected as RTC clock source
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2022 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ This file must be copied to the application folder and modified as follows:
+ (#) Rename it to 'stm32c0xx_hal_timebase_rtc_alarm.c'
+ (#) Add this file and the RTC HAL drivers to your project and uncomment
+ HAL_RTC_MODULE_ENABLED define in stm32c0xx_hal_conf.h
+
+ [..]
+ (@) HAL RTC alarm driver can not be used with low power modes:
+ The wake up capability of the RTC may be intrusive in case of prior low power mode
+ configuration requiring different wake up sources.
+ Application/Example behavior is no more guaranteed
+ (@) The stm32c0xx_hal_timebase_tim use is recommended for the Applications/Examples
+ requiring low power modes
+
+ @endverbatim
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32c0xx_hal.h"
+/** @addtogroup STM32C0xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup HAL_TimeBase_RTC_Alarm_Template HAL TimeBase RTC Alarm Template
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/* Uncomment the line below to select the appropriate RTC Clock source for your application:
+ + RTC_CLOCK_SOURCE_HSE: can be selected for applications requiring timing precision.
+ + RTC_CLOCK_SOURCE_LSE: can be selected for applications with low constraint on timing
+ precision.
+ + RTC_CLOCK_SOURCE_LSI: can be selected for applications with low constraint on timing
+ precision.
+ */
+#define RTC_CLOCK_SOURCE_HSE
+/* #define RTC_CLOCK_SOURCE_LSE */
+/* #define RTC_CLOCK_SOURCE_LSI */
+
+#ifdef RTC_CLOCK_SOURCE_HSE
+#define RTC_ASYNCH_PREDIV 49U
+#define RTC_SYNCH_PREDIV 4U
+#else /* RTC_CLOCK_SOURCE_LSE || RTC_CLOCK_SOURCE_LSI */
+#define RTC_ASYNCH_PREDIV 0U
+#define RTC_SYNCH_PREDIV 31U
+#endif /* RTC_CLOCK_SOURCE_HSE */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+extern RTC_HandleTypeDef hRTC_Handle;
+RTC_HandleTypeDef hRTC_Handle;
+
+/* Private function prototypes -----------------------------------------------*/
+void RTC_IRQHandler(void);
+/* Private functions ---------------------------------------------------------*/
+
+/**
+ * @brief This function configures the RTC_ALARMA as a time base source.
+ * The time source is configured to have 1ms time base with a dedicated
+ * Tick interrupt priority.
+ * @note This function is called automatically at the beginning of program after
+ * reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig().
+ * @param TickPriority: Tick interrupt priority.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
+{
+ __IO uint32_t counter = 0U;
+
+ RCC_OscInitTypeDef RCC_OscInitStruct;
+ RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
+
+#ifdef RTC_CLOCK_SOURCE_LSE
+ /* ConfigureLSE as RTC clock source */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
+ RCC_OscInitStruct.LSEState = RCC_LSE_ON;
+ PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE;
+#elif defined (RTC_CLOCK_SOURCE_LSI)
+ /* ConfigureLSI as RTC clock source */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI;
+ RCC_OscInitStruct.LSIState = RCC_LSI_ON;
+ PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSI;
+#elif defined (RTC_CLOCK_SOURCE_HSE)
+ /* ConfigureHSE as RTC clock source */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+ RCC_OscInitStruct.HSEState = RCC_HSE_ON;
+ PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_HSE_DIV32;
+#else
+#error Please select the RTC Clock source
+#endif /* RTC_CLOCK_SOURCE_LSE */
+
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK)
+ {
+ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC;
+ if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) == HAL_OK)
+ {
+ /* Enable RTC Clock */
+ __HAL_RCC_RTC_ENABLE();
+ __HAL_RCC_RTCAPB_CLK_ENABLE();
+
+ /* The time base should be 1ms
+ Time base = ((RTC_ASYNCH_PREDIV + 1) * (RTC_SYNCH_PREDIV + 1)) / RTC_CLOCK
+ HSE as RTC clock
+ Time base = ((49 + 1) * (4 + 1)) / 250kHz
+ = 1ms
+ LSE as RTC clock
+ Time base = ((31 + 1) * (0 + 1)) / 32.768KHz
+ = ~1ms
+ LSI as RTC clock
+ Time base = ((31 + 1) * (0 + 1)) / 32KHz
+ = 1ms
+ */
+ hRTC_Handle.Instance = RTC;
+ hRTC_Handle.Init.HourFormat = RTC_HOURFORMAT_24;
+ hRTC_Handle.Init.AsynchPrediv = RTC_ASYNCH_PREDIV;
+ hRTC_Handle.Init.SynchPrediv = RTC_SYNCH_PREDIV;
+ hRTC_Handle.Init.OutPut = RTC_OUTPUT_DISABLE;
+ hRTC_Handle.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH;
+ hRTC_Handle.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN;
+ if (HAL_RTC_Init(&hRTC_Handle) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(&hRTC_Handle);
+
+ /* Disable the Alarm A interrupt */
+ __HAL_RTC_ALARMA_DISABLE(&hRTC_Handle);
+
+ /* Clear flag alarm A */
+ __HAL_RTC_ALARM_CLEAR_FLAG(&hRTC_Handle, RTC_FLAG_ALRAF);
+
+ counter = 0U;
+ /* Wait till RTC ALRAWF flag is set and if Time out is reached exit */
+ while (__HAL_RTC_ALARM_GET_FLAG(&hRTC_Handle, RTC_FLAG_ALRAWF) == 0U)
+ {
+ if (counter++ == (SystemCoreClock / 56U)) /* Timeout = ~ 1s */
+ {
+ return HAL_ERROR;
+ }
+ }
+
+ hRTC_Handle.Instance->ALRMAR = (uint32_t)0x01U;
+
+ /* Configure the Alarm state: Enable Alarm */
+ __HAL_RTC_ALARMA_ENABLE(&hRTC_Handle);
+ /* Configure the Alarm interrupt */
+ __HAL_RTC_ALARM_ENABLE_IT(&hRTC_Handle, RTC_IT_ALRA);
+
+ /* RTC Alarm Interrupt Configuration: EXTI configuration */
+ __HAL_RTC_ALARM_EXTI_ENABLE_IT();
+
+ /* Check if the Initialization mode is set */
+ if ((hRTC_Handle.Instance->ICSR & RTC_ICSR_INITF) == (uint32_t)RESET)
+ {
+ /* Set the Initialization mode */
+ hRTC_Handle.Instance->ICSR = (uint32_t)RTC_INIT_MASK;
+ counter = 0U;
+ while ((hRTC_Handle.Instance->ICSR & RTC_ICSR_INITF) == (uint32_t)RESET)
+ {
+ if (counter++ == (SystemCoreClock / 56U)) /* Timeout = ~ 1s */
+ {
+ return HAL_ERROR;
+ }
+ }
+ }
+ hRTC_Handle.Instance->DR = 0U;
+ hRTC_Handle.Instance->TR = 0U;
+
+ hRTC_Handle.Instance->ICSR &= (uint32_t)~RTC_ICSR_INIT;
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(&hRTC_Handle);
+
+ HAL_NVIC_SetPriority(RTC_IRQn, TickPriority, 0U);
+ HAL_NVIC_EnableIRQ(RTC_IRQn);
+ return HAL_OK;
+ }
+ }
+ return HAL_ERROR;
+}
+
+/**
+ * @brief Suspend Tick increment.
+ * @note Disable the tick increment by disabling RTC ALARM interrupt.
+ * @retval None
+ */
+void HAL_SuspendTick(void)
+{
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(&hRTC_Handle);
+ /* Disable RTC ALARM update Interrupt */
+ __HAL_RTC_ALARM_DISABLE_IT(&hRTC_Handle, RTC_IT_ALRA);
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(&hRTC_Handle);
+}
+
+/**
+ * @brief Resume Tick increment.
+ * @note Enable the tick increment by Enabling RTC ALARM interrupt.
+ * @retval None
+ */
+void HAL_ResumeTick(void)
+{
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(&hRTC_Handle);
+ /* Enable RTC ALARM Update interrupt */
+ __HAL_RTC_ALARM_ENABLE_IT(&hRTC_Handle, RTC_IT_ALRA);
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(&hRTC_Handle);
+}
+
+/**
+ * @brief ALARM A Event Callback in non blocking mode
+ * @note This function is called when RTC_ALARM interrupt took place, inside
+ * RTC_ALARM_IRQHandler(). It makes a direct call to HAL_IncTick() to increment
+ * a global variable "uwTick" used as application time base.
+ * @param hrtc : RTC handle
+ * @retval None
+ */
+void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc)
+{
+ __IO uint32_t counter = 0U;
+
+ HAL_IncTick();
+
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* Set the Initialization mode */
+ hrtc->Instance->ICSR = (uint32_t)RTC_INIT_MASK;
+
+ while ((hrtc->Instance->ICSR & RTC_ICSR_INITF) == (uint32_t)RESET)
+ {
+ if (counter++ == (SystemCoreClock / 56U)) /* Timeout = ~ 1s */
+ {
+ break;
+ }
+ }
+
+ hrtc->Instance->DR = 0U;
+ hrtc->Instance->TR = 0U;
+
+ hrtc->Instance->ICSR &= (uint32_t)~RTC_ICSR_INIT;
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+}
+
+/**
+ * @brief This function handles RTC ALARM interrupt request.
+ * @retval None
+ */
+void RTC_IRQHandler(void)
+{
+ HAL_RTC_AlarmIRQHandler(&hRTC_Handle);
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_timebase_tim_template.c b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_timebase_tim_template.c
new file mode 100644
index 0000000000..65a904da46
--- /dev/null
+++ b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_timebase_tim_template.c
@@ -0,0 +1,176 @@
+/**
+ ******************************************************************************
+ * @file stm32c0xx_hal_timebase_tim_template.c
+ * @author MCD Application Team
+ * @brief HAL time base based on the hardware TIM.
+ *
+ * This file overrides the native HAL time base functions (defined as weak)
+ * the TIM time base:
+ * + Initializes the TIM peripheral to generate a Period elapsed Event each 1ms
+ * + HAL_IncTick is called inside HAL_TIM_PeriodElapsedCallback ie each 1ms
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2022 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ This file must be copied to the application folder and modified as follows:
+ (#) Rename it to 'stm32c0xx_hal_timebase_tim.c'
+ (#) Add this file and the TIM HAL drivers to your project and uncomment
+ HAL_TIM_MODULE_ENABLED define in stm32c0xx_hal_conf.h
+
+ @endverbatim
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32c0xx_hal.h"
+
+/** @addtogroup STM32C0xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup HAL_TimeBase_TIM
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+extern TIM_HandleTypeDef TimHandle;
+TIM_HandleTypeDef TimHandle;
+/* Private function prototypes -----------------------------------------------*/
+void TIM3_IRQHandler(void);
+/* Private functions ---------------------------------------------------------*/
+
+/**
+ * @brief This function configures the TIM3 as a time base source.
+ * The time source is configured to have 1ms time base with a dedicated
+ * Tick interrupt priority.
+ * @note This function is called automatically at the beginning of program after
+ * reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig().
+ * @param TickPriority Tick interrupt priority.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
+{
+ RCC_ClkInitTypeDef clkconfig;
+ uint32_t uwTimclock, uwAPB1Prescaler;
+ uint32_t uwPrescalerValue;
+ uint32_t pFLatency;
+
+ /*Configure the TIM3 IRQ priority */
+ HAL_NVIC_SetPriority(TIM3_IRQn, TickPriority, 0U);
+
+ /* Enable the TIM3 global Interrupt */
+ HAL_NVIC_EnableIRQ(TIM3_IRQn);
+
+ /* Enable TIM3 clock */
+ __HAL_RCC_TIM3_CLK_ENABLE();
+
+ /* Get clock configuration */
+ HAL_RCC_GetClockConfig(&clkconfig, &pFLatency);
+
+ /* Get APB1 prescaler */
+ uwAPB1Prescaler = clkconfig.APB1CLKDivider;
+
+ /* Compute TIM3 clock */
+ if (uwAPB1Prescaler == RCC_HCLK_DIV1)
+ {
+ uwTimclock = HAL_RCC_GetPCLK1Freq();
+ }
+ else
+ {
+ uwTimclock = 2U * HAL_RCC_GetPCLK1Freq();
+ }
+
+ /* Compute the prescaler value to have TIM3 counter clock equal to 1MHz */
+ uwPrescalerValue = (uint32_t)((uwTimclock / 1000000U) - 1U);
+
+ /* Initialize TIM3 */
+ TimHandle.Instance = TIM3;
+
+ /* Initialize TIMx peripheral as follow:
+ + Period = [(TIM3CLK/1000) - 1]. to have a (1/1000) s time base.
+ + Prescaler = (uwTimclock/1000000 - 1) to have a 1MHz counter clock.
+ + ClockDivision = 0
+ + Counter direction = Up
+ */
+ TimHandle.Init.Period = (1000000U / 1000U) - 1U;
+ TimHandle.Init.Prescaler = uwPrescalerValue;
+ TimHandle.Init.ClockDivision = 0U;
+ TimHandle.Init.CounterMode = TIM_COUNTERMODE_UP;
+ TimHandle.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
+ if (HAL_TIM_Base_Init(&TimHandle) == HAL_OK)
+ {
+ /* Start the TIM time Base generation in interrupt mode */
+ return HAL_TIM_Base_Start_IT(&TimHandle);
+ }
+
+ /* Return function status */
+ return HAL_ERROR;
+}
+
+/**
+ * @brief Suspend Tick increment.
+ * @note Disable the tick increment by disabling TIM3 update interrupt.
+ * @retval None
+ */
+void HAL_SuspendTick(void)
+{
+ /* Disable TIM3 update interrupt */
+ __HAL_TIM_DISABLE_IT(&TimHandle, TIM_IT_UPDATE);
+}
+
+/**
+ * @brief Resume Tick increment.
+ * @note Enable the tick increment by enabling TIM3 update interrupt.
+ * @retval None
+ */
+void HAL_ResumeTick(void)
+{
+ /* Enable TIM3 update interrupt */
+ __HAL_TIM_ENABLE_IT(&TimHandle, TIM_IT_UPDATE);
+}
+
+/**
+ * @brief Period elapsed callback in non blocking mode
+ * @note This function is called when TIM3 interrupt took place, inside
+ * HAL_TIM_IRQHandler(). It makes a direct call to HAL_IncTick() to increment
+ * a global variable "uwTick" used as application time base.
+ * @param htim TIM handle
+ * @retval None
+ */
+void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
+{
+ HAL_IncTick();
+}
+
+/**
+ * @brief This function handles TIM interrupt request.
+ * @retval None
+ */
+void TIM3_IRQHandler(void)
+{
+ HAL_TIM_IRQHandler(&TimHandle);
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c
new file mode 100644
index 0000000000..11ff3be7ab
--- /dev/null
+++ b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c
@@ -0,0 +1,4612 @@
+/**
+ ******************************************************************************
+ * @file stm32c0xx_hal_uart.c
+ * @author MCD Application Team
+ * @brief UART HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART).
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral Control functions
+ *
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2022 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ===============================================================================
+ ##### How to use this driver #####
+ ===============================================================================
+ [..]
+ The UART HAL driver can be used as follows:
+
+ (#) Declare a UART_HandleTypeDef handle structure (eg. UART_HandleTypeDef huart).
+ (#) Initialize the UART low level resources by implementing the HAL_UART_MspInit() API:
+ (++) Enable the USARTx interface clock.
+ (++) UART pins configuration:
+ (+++) Enable the clock for the UART GPIOs.
+ (+++) Configure these UART pins as alternate function pull-up.
+ (++) NVIC configuration if you need to use interrupt process (HAL_UART_Transmit_IT()
+ and HAL_UART_Receive_IT() APIs):
+ (+++) Configure the USARTx interrupt priority.
+ (+++) Enable the NVIC USART IRQ handle.
+ (++) UART interrupts handling:
+ -@@- The specific UART interrupts (Transmission complete interrupt,
+ RXNE interrupt, RX/TX FIFOs related interrupts and Error Interrupts)
+ are managed using the macros __HAL_UART_ENABLE_IT() and __HAL_UART_DISABLE_IT()
+ inside the transmit and receive processes.
+ (++) DMA Configuration if you need to use DMA process (HAL_UART_Transmit_DMA()
+ and HAL_UART_Receive_DMA() APIs):
+ (+++) Declare a DMA handle structure for the Tx/Rx channel.
+ (+++) Enable the DMAx interface clock.
+ (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
+ (+++) Configure the DMA Tx/Rx channel.
+ (+++) Associate the initialized DMA handle to the UART DMA Tx/Rx handle.
+ (+++) Configure the priority and enable the NVIC for the transfer complete
+ interrupt on the DMA Tx/Rx channel.
+
+ (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Prescaler value , Hardware
+ flow control and Mode (Receiver/Transmitter) in the huart handle Init structure.
+
+ (#) If required, program UART advanced features (TX/RX pins swap, auto Baud rate detection,...)
+ in the huart handle AdvancedInit structure.
+
+ (#) For the UART asynchronous mode, initialize the UART registers by calling
+ the HAL_UART_Init() API.
+
+ (#) For the UART Half duplex mode, initialize the UART registers by calling
+ the HAL_HalfDuplex_Init() API.
+
+ (#) For the UART LIN (Local Interconnection Network) mode, initialize the UART registers
+ by calling the HAL_LIN_Init() API.
+
+ (#) For the UART Multiprocessor mode, initialize the UART registers
+ by calling the HAL_MultiProcessor_Init() API.
+
+ (#) For the UART RS485 Driver Enabled mode, initialize the UART registers
+ by calling the HAL_RS485Ex_Init() API.
+
+ [..]
+ (@) These API's (HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(),
+ also configure the low level Hardware GPIO, CLOCK, CORTEX...etc) by
+ calling the customized HAL_UART_MspInit() API.
+
+ ##### Callback registration #####
+ ==================================
+
+ [..]
+ The compilation define USE_HAL_UART_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+
+ [..]
+ Use Function HAL_UART_RegisterCallback() to register a user callback.
+ Function HAL_UART_RegisterCallback() allows to register following callbacks:
+ (+) TxHalfCpltCallback : Tx Half Complete Callback.
+ (+) TxCpltCallback : Tx Complete Callback.
+ (+) RxHalfCpltCallback : Rx Half Complete Callback.
+ (+) RxCpltCallback : Rx Complete Callback.
+ (+) ErrorCallback : Error Callback.
+ (+) AbortCpltCallback : Abort Complete Callback.
+ (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
+ (+) AbortReceiveCpltCallback : Abort Receive Complete Callback.
+ (+) WakeupCallback : Wakeup Callback.
+ (+) RxFifoFullCallback : Rx Fifo Full Callback.
+ (+) TxFifoEmptyCallback : Tx Fifo Empty Callback.
+ (+) MspInitCallback : UART MspInit.
+ (+) MspDeInitCallback : UART MspDeInit.
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+ [..]
+ Use function HAL_UART_UnRegisterCallback() to reset a callback to the default
+ weak (surcharged) function.
+ HAL_UART_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+ and the Callback ID.
+ This function allows to reset following callbacks:
+ (+) TxHalfCpltCallback : Tx Half Complete Callback.
+ (+) TxCpltCallback : Tx Complete Callback.
+ (+) RxHalfCpltCallback : Rx Half Complete Callback.
+ (+) RxCpltCallback : Rx Complete Callback.
+ (+) ErrorCallback : Error Callback.
+ (+) AbortCpltCallback : Abort Complete Callback.
+ (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
+ (+) AbortReceiveCpltCallback : Abort Receive Complete Callback.
+ (+) WakeupCallback : Wakeup Callback.
+ (+) RxFifoFullCallback : Rx Fifo Full Callback.
+ (+) TxFifoEmptyCallback : Tx Fifo Empty Callback.
+ (+) MspInitCallback : UART MspInit.
+ (+) MspDeInitCallback : UART MspDeInit.
+
+ [..]
+ For specific callback RxEventCallback, use dedicated registration/reset functions:
+ respectively HAL_UART_RegisterRxEventCallback() , HAL_UART_UnRegisterRxEventCallback().
+
+ [..]
+ By default, after the HAL_UART_Init() and when the state is HAL_UART_STATE_RESET
+ all callbacks are set to the corresponding weak (surcharged) functions:
+ examples HAL_UART_TxCpltCallback(), HAL_UART_RxHalfCpltCallback().
+ Exception done for MspInit and MspDeInit functions that are respectively
+ reset to the legacy weak (surcharged) functions in the HAL_UART_Init()
+ and HAL_UART_DeInit() only when these callbacks are null (not registered beforehand).
+ If not, MspInit or MspDeInit are not null, the HAL_UART_Init() and HAL_UART_DeInit()
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
+
+ [..]
+ Callbacks can be registered/unregistered in HAL_UART_STATE_READY state only.
+ Exception done MspInit/MspDeInit that can be registered/unregistered
+ in HAL_UART_STATE_READY or HAL_UART_STATE_RESET state, thus registered (user)
+ MspInit/DeInit callbacks can be used during the Init/DeInit.
+ In that case first register the MspInit/MspDeInit user callbacks
+ using HAL_UART_RegisterCallback() before calling HAL_UART_DeInit()
+ or HAL_UART_Init() function.
+
+ [..]
+ When The compilation define USE_HAL_UART_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registration feature is not available
+ and weak (surcharged) callbacks are used.
+
+
+ @endverbatim
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32c0xx_hal.h"
+
+/** @addtogroup STM32C0xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup UART UART
+ * @brief HAL UART module driver
+ * @{
+ */
+
+#ifdef HAL_UART_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup UART_Private_Constants UART Private Constants
+ * @{
+ */
+#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | \
+ USART_CR1_OVER8 | USART_CR1_FIFOEN)) /*!< UART or USART CR1 fields of parameters set by UART_SetConfig API */
+
+#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT | USART_CR3_TXFTCFG | \
+ USART_CR3_RXFTCFG)) /*!< UART or USART CR3 fields of parameters set by UART_SetConfig API */
+
+
+#define UART_BRR_MIN 0x10U /* UART BRR minimum authorized value */
+#define UART_BRR_MAX 0x0000FFFFU /* UART BRR maximum authorized value */
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup UART_Private_Functions
+ * @{
+ */
+static void UART_EndTxTransfer(UART_HandleTypeDef *huart);
+static void UART_EndRxTransfer(UART_HandleTypeDef *huart);
+static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma);
+static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
+static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
+static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
+static void UART_DMAError(DMA_HandleTypeDef *hdma);
+static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma);
+static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
+static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
+static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
+static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
+static void UART_TxISR_8BIT(UART_HandleTypeDef *huart);
+static void UART_TxISR_16BIT(UART_HandleTypeDef *huart);
+static void UART_TxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart);
+static void UART_TxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart);
+static void UART_EndTransmit_IT(UART_HandleTypeDef *huart);
+static void UART_RxISR_8BIT(UART_HandleTypeDef *huart);
+static void UART_RxISR_16BIT(UART_HandleTypeDef *huart);
+static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart);
+static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart);
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/** @addtogroup UART_Private_variables
+ * @{
+ */
+const uint16_t UARTPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U};
+/**
+ * @}
+ */
+
+/* Exported Constants --------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup UART_Exported_Functions UART Exported Functions
+ * @{
+ */
+
+/** @defgroup UART_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+===============================================================================
+ ##### Initialization and Configuration functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
+ in asynchronous mode.
+ (+) For the asynchronous mode the parameters below can be configured:
+ (++) Baud Rate
+ (++) Word Length
+ (++) Stop Bit
+ (++) Parity: If the parity is enabled, then the MSB bit of the data written
+ in the data register is transmitted but is changed by the parity bit.
+ (++) Hardware flow control
+ (++) Receiver/transmitter modes
+ (++) Over Sampling Method
+ (++) One-Bit Sampling Method
+ (+) For the asynchronous mode, the following advanced features can be configured as well:
+ (++) TX and/or RX pin level inversion
+ (++) data logical level inversion
+ (++) RX and TX pins swap
+ (++) RX overrun detection disabling
+ (++) DMA disabling on RX error
+ (++) MSB first on communication line
+ (++) auto Baud rate detection
+ [..]
+ The HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init()and HAL_MultiProcessor_Init()API
+ follow respectively the UART asynchronous, UART Half duplex, UART LIN mode
+ and UART multiprocessor mode configuration procedures (details for the procedures
+ are available in reference manual).
+
+@endverbatim
+
+ Depending on the frame length defined by the M1 and M0 bits (7-bit,
+ 8-bit or 9-bit), the possible UART formats are listed in the
+ following table.
+
+ Table 1. UART frame format.
+ +-----------------------------------------------------------------------+
+ | M1 bit | M0 bit | PCE bit | UART frame |
+ |---------|---------|-----------|---------------------------------------|
+ | 0 | 0 | 0 | | SB | 8 bit data | STB | |
+ |---------|---------|-----------|---------------------------------------|
+ | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | |
+ |---------|---------|-----------|---------------------------------------|
+ | 0 | 1 | 0 | | SB | 9 bit data | STB | |
+ |---------|---------|-----------|---------------------------------------|
+ | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | |
+ |---------|---------|-----------|---------------------------------------|
+ | 1 | 0 | 0 | | SB | 7 bit data | STB | |
+ |---------|---------|-----------|---------------------------------------|
+ | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | |
+ +-----------------------------------------------------------------------+
+
+ * @{
+ */
+
+/**
+ * @brief Initialize the UART mode according to the specified
+ * parameters in the UART_InitTypeDef and initialize the associated handle.
+ * @param huart UART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
+{
+ /* Check the UART handle allocation */
+ if (huart == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ if (huart->Init.HwFlowCtl != UART_HWCONTROL_NONE)
+ {
+ /* Check the parameters */
+ assert_param(IS_UART_HWFLOW_INSTANCE(huart->Instance));
+ }
+ else
+ {
+ /* Check the parameters */
+ assert_param(IS_UART_INSTANCE(huart->Instance));
+ }
+
+ if (huart->gState == HAL_UART_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ huart->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ UART_InitCallbacksToDefault(huart);
+
+ if (huart->MspInitCallback == NULL)
+ {
+ huart->MspInitCallback = HAL_UART_MspInit;
+ }
+
+ /* Init the low level hardware */
+ huart->MspInitCallback(huart);
+#else
+ /* Init the low level hardware : GPIO, CLOCK */
+ HAL_UART_MspInit(huart);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+ }
+
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ __HAL_UART_DISABLE(huart);
+
+ /* Set the UART Communication parameters */
+ if (UART_SetConfig(huart) == HAL_ERROR)
+ {
+ return HAL_ERROR;
+ }
+
+ if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
+ {
+ UART_AdvFeatureConfig(huart);
+ }
+
+ /* In asynchronous mode, the following bits must be kept cleared:
+ - LINEN and CLKEN bits in the USART_CR2 register,
+ - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/
+ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+ CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
+
+ __HAL_UART_ENABLE(huart);
+
+ /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
+ return (UART_CheckIdleState(huart));
+}
+
+/**
+ * @brief Initialize the half-duplex mode according to the specified
+ * parameters in the UART_InitTypeDef and creates the associated handle.
+ * @param huart UART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart)
+{
+ /* Check the UART handle allocation */
+ if (huart == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check UART instance */
+ assert_param(IS_UART_HALFDUPLEX_INSTANCE(huart->Instance));
+
+ if (huart->gState == HAL_UART_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ huart->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ UART_InitCallbacksToDefault(huart);
+
+ if (huart->MspInitCallback == NULL)
+ {
+ huart->MspInitCallback = HAL_UART_MspInit;
+ }
+
+ /* Init the low level hardware */
+ huart->MspInitCallback(huart);
+#else
+ /* Init the low level hardware : GPIO, CLOCK */
+ HAL_UART_MspInit(huart);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+ }
+
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ __HAL_UART_DISABLE(huart);
+
+ /* Set the UART Communication parameters */
+ if (UART_SetConfig(huart) == HAL_ERROR)
+ {
+ return HAL_ERROR;
+ }
+
+ if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
+ {
+ UART_AdvFeatureConfig(huart);
+ }
+
+ /* In half-duplex mode, the following bits must be kept cleared:
+ - LINEN and CLKEN bits in the USART_CR2 register,
+ - SCEN and IREN bits in the USART_CR3 register.*/
+ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+ CLEAR_BIT(huart->Instance->CR3, (USART_CR3_IREN | USART_CR3_SCEN));
+
+ /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */
+ SET_BIT(huart->Instance->CR3, USART_CR3_HDSEL);
+
+ __HAL_UART_ENABLE(huart);
+
+ /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
+ return (UART_CheckIdleState(huart));
+}
+
+
+/**
+ * @brief Initialize the LIN mode according to the specified
+ * parameters in the UART_InitTypeDef and creates the associated handle.
+ * @param huart UART handle.
+ * @param BreakDetectLength Specifies the LIN break detection length.
+ * This parameter can be one of the following values:
+ * @arg @ref UART_LINBREAKDETECTLENGTH_10B 10-bit break detection
+ * @arg @ref UART_LINBREAKDETECTLENGTH_11B 11-bit break detection
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength)
+{
+ /* Check the UART handle allocation */
+ if (huart == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the LIN UART instance */
+ assert_param(IS_UART_LIN_INSTANCE(huart->Instance));
+ /* Check the Break detection length parameter */
+ assert_param(IS_UART_LIN_BREAK_DETECT_LENGTH(BreakDetectLength));
+
+ /* LIN mode limited to 16-bit oversampling only */
+ if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
+ {
+ return HAL_ERROR;
+ }
+ /* LIN mode limited to 8-bit data length */
+ if (huart->Init.WordLength != UART_WORDLENGTH_8B)
+ {
+ return HAL_ERROR;
+ }
+
+ if (huart->gState == HAL_UART_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ huart->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ UART_InitCallbacksToDefault(huart);
+
+ if (huart->MspInitCallback == NULL)
+ {
+ huart->MspInitCallback = HAL_UART_MspInit;
+ }
+
+ /* Init the low level hardware */
+ huart->MspInitCallback(huart);
+#else
+ /* Init the low level hardware : GPIO, CLOCK */
+ HAL_UART_MspInit(huart);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+ }
+
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ __HAL_UART_DISABLE(huart);
+
+ /* Set the UART Communication parameters */
+ if (UART_SetConfig(huart) == HAL_ERROR)
+ {
+ return HAL_ERROR;
+ }
+
+ if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
+ {
+ UART_AdvFeatureConfig(huart);
+ }
+
+ /* In LIN mode, the following bits must be kept cleared:
+ - LINEN and CLKEN bits in the USART_CR2 register,
+ - SCEN and IREN bits in the USART_CR3 register.*/
+ CLEAR_BIT(huart->Instance->CR2, USART_CR2_CLKEN);
+ CLEAR_BIT(huart->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN | USART_CR3_SCEN));
+
+ /* Enable the LIN mode by setting the LINEN bit in the CR2 register */
+ SET_BIT(huart->Instance->CR2, USART_CR2_LINEN);
+
+ /* Set the USART LIN Break detection length. */
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_LBDL, BreakDetectLength);
+
+ __HAL_UART_ENABLE(huart);
+
+ /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
+ return (UART_CheckIdleState(huart));
+}
+
+
+/**
+ * @brief Initialize the multiprocessor mode according to the specified
+ * parameters in the UART_InitTypeDef and initialize the associated handle.
+ * @param huart UART handle.
+ * @param Address UART node address (4-, 6-, 7- or 8-bit long).
+ * @param WakeUpMethod Specifies the UART wakeup method.
+ * This parameter can be one of the following values:
+ * @arg @ref UART_WAKEUPMETHOD_IDLELINE WakeUp by an idle line detection
+ * @arg @ref UART_WAKEUPMETHOD_ADDRESSMARK WakeUp by an address mark
+ * @note If the user resorts to idle line detection wake up, the Address parameter
+ * is useless and ignored by the initialization function.
+ * @note If the user resorts to address mark wake up, the address length detection
+ * is configured by default to 4 bits only. For the UART to be able to
+ * manage 6-, 7- or 8-bit long addresses detection, the API
+ * HAL_MultiProcessorEx_AddressLength_Set() must be called after
+ * HAL_MultiProcessor_Init().
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod)
+{
+ /* Check the UART handle allocation */
+ if (huart == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the wake up method parameter */
+ assert_param(IS_UART_WAKEUPMETHOD(WakeUpMethod));
+
+ if (huart->gState == HAL_UART_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ huart->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ UART_InitCallbacksToDefault(huart);
+
+ if (huart->MspInitCallback == NULL)
+ {
+ huart->MspInitCallback = HAL_UART_MspInit;
+ }
+
+ /* Init the low level hardware */
+ huart->MspInitCallback(huart);
+#else
+ /* Init the low level hardware : GPIO, CLOCK */
+ HAL_UART_MspInit(huart);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+ }
+
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ __HAL_UART_DISABLE(huart);
+
+ /* Set the UART Communication parameters */
+ if (UART_SetConfig(huart) == HAL_ERROR)
+ {
+ return HAL_ERROR;
+ }
+
+ if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
+ {
+ UART_AdvFeatureConfig(huart);
+ }
+
+ /* In multiprocessor mode, the following bits must be kept cleared:
+ - LINEN and CLKEN bits in the USART_CR2 register,
+ - SCEN, HDSEL and IREN bits in the USART_CR3 register. */
+ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+ CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
+
+ if (WakeUpMethod == UART_WAKEUPMETHOD_ADDRESSMARK)
+ {
+ /* If address mark wake up method is chosen, set the USART address node */
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)Address << UART_CR2_ADDRESS_LSB_POS));
+ }
+
+ /* Set the wake up method by setting the WAKE bit in the CR1 register */
+ MODIFY_REG(huart->Instance->CR1, USART_CR1_WAKE, WakeUpMethod);
+
+ __HAL_UART_ENABLE(huart);
+
+ /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
+ return (UART_CheckIdleState(huart));
+}
+
+
+/**
+ * @brief DeInitialize the UART peripheral.
+ * @param huart UART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart)
+{
+ /* Check the UART handle allocation */
+ if (huart == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_UART_INSTANCE(huart->Instance));
+
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ __HAL_UART_DISABLE(huart);
+
+ huart->Instance->CR1 = 0x0U;
+ huart->Instance->CR2 = 0x0U;
+ huart->Instance->CR3 = 0x0U;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ if (huart->MspDeInitCallback == NULL)
+ {
+ huart->MspDeInitCallback = HAL_UART_MspDeInit;
+ }
+ /* DeInit the low level hardware */
+ huart->MspDeInitCallback(huart);
+#else
+ /* DeInit the low level hardware */
+ HAL_UART_MspDeInit(huart);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+ huart->gState = HAL_UART_STATE_RESET;
+ huart->RxState = HAL_UART_STATE_RESET;
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initialize the UART MSP.
+ * @param huart UART handle.
+ * @retval None
+ */
+__weak void HAL_UART_MspInit(UART_HandleTypeDef *huart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(huart);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_UART_MspInit can be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitialize the UART MSP.
+ * @param huart UART handle.
+ * @retval None
+ */
+__weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(huart);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_UART_MspDeInit can be implemented in the user file
+ */
+}
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a User UART Callback
+ * To be used instead of the weak predefined callback
+ * @param huart uart handle
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
+ * @arg @ref HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID
+ * @arg @ref HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
+ * @arg @ref HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID
+ * @arg @ref HAL_UART_ERROR_CB_ID Error Callback ID
+ * @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
+ * @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
+ * @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
+ * @arg @ref HAL_UART_WAKEUP_CB_ID Wakeup Callback ID
+ * @arg @ref HAL_UART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID
+ * @arg @ref HAL_UART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID
+ * @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID
+ * @arg @ref HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID
+ * @param pCallback pointer to the Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID,
+ pUART_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+
+ __HAL_LOCK(huart);
+
+ if (huart->gState == HAL_UART_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+ case HAL_UART_TX_HALFCOMPLETE_CB_ID :
+ huart->TxHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_UART_TX_COMPLETE_CB_ID :
+ huart->TxCpltCallback = pCallback;
+ break;
+
+ case HAL_UART_RX_HALFCOMPLETE_CB_ID :
+ huart->RxHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_UART_RX_COMPLETE_CB_ID :
+ huart->RxCpltCallback = pCallback;
+ break;
+
+ case HAL_UART_ERROR_CB_ID :
+ huart->ErrorCallback = pCallback;
+ break;
+
+ case HAL_UART_ABORT_COMPLETE_CB_ID :
+ huart->AbortCpltCallback = pCallback;
+ break;
+
+ case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID :
+ huart->AbortTransmitCpltCallback = pCallback;
+ break;
+
+ case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID :
+ huart->AbortReceiveCpltCallback = pCallback;
+ break;
+
+ case HAL_UART_WAKEUP_CB_ID :
+ huart->WakeupCallback = pCallback;
+ break;
+
+ case HAL_UART_RX_FIFO_FULL_CB_ID :
+ huart->RxFifoFullCallback = pCallback;
+ break;
+
+ case HAL_UART_TX_FIFO_EMPTY_CB_ID :
+ huart->TxFifoEmptyCallback = pCallback;
+ break;
+
+ case HAL_UART_MSPINIT_CB_ID :
+ huart->MspInitCallback = pCallback;
+ break;
+
+ case HAL_UART_MSPDEINIT_CB_ID :
+ huart->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (huart->gState == HAL_UART_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_UART_MSPINIT_CB_ID :
+ huart->MspInitCallback = pCallback;
+ break;
+
+ case HAL_UART_MSPDEINIT_CB_ID :
+ huart->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+ status = HAL_ERROR;
+ }
+
+ __HAL_UNLOCK(huart);
+
+ return status;
+}
+
+/**
+ * @brief Unregister an UART Callback
+ * UART callaback is redirected to the weak predefined callback
+ * @param huart uart handle
+ * @param CallbackID ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
+ * @arg @ref HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID
+ * @arg @ref HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
+ * @arg @ref HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID
+ * @arg @ref HAL_UART_ERROR_CB_ID Error Callback ID
+ * @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
+ * @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
+ * @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
+ * @arg @ref HAL_UART_WAKEUP_CB_ID Wakeup Callback ID
+ * @arg @ref HAL_UART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID
+ * @arg @ref HAL_UART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID
+ * @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID
+ * @arg @ref HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ __HAL_LOCK(huart);
+
+ if (HAL_UART_STATE_READY == huart->gState)
+ {
+ switch (CallbackID)
+ {
+ case HAL_UART_TX_HALFCOMPLETE_CB_ID :
+ huart->TxHalfCpltCallback = HAL_UART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
+ break;
+
+ case HAL_UART_TX_COMPLETE_CB_ID :
+ huart->TxCpltCallback = HAL_UART_TxCpltCallback; /* Legacy weak TxCpltCallback */
+ break;
+
+ case HAL_UART_RX_HALFCOMPLETE_CB_ID :
+ huart->RxHalfCpltCallback = HAL_UART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
+ break;
+
+ case HAL_UART_RX_COMPLETE_CB_ID :
+ huart->RxCpltCallback = HAL_UART_RxCpltCallback; /* Legacy weak RxCpltCallback */
+ break;
+
+ case HAL_UART_ERROR_CB_ID :
+ huart->ErrorCallback = HAL_UART_ErrorCallback; /* Legacy weak ErrorCallback */
+ break;
+
+ case HAL_UART_ABORT_COMPLETE_CB_ID :
+ huart->AbortCpltCallback = HAL_UART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
+ break;
+
+ case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID :
+ huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak
+ AbortTransmitCpltCallback */
+ break;
+
+ case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID :
+ huart->AbortReceiveCpltCallback = HAL_UART_AbortReceiveCpltCallback; /* Legacy weak
+ AbortReceiveCpltCallback */
+ break;
+
+ case HAL_UART_WAKEUP_CB_ID :
+ huart->WakeupCallback = HAL_UARTEx_WakeupCallback; /* Legacy weak WakeupCallback */
+ break;
+
+ case HAL_UART_RX_FIFO_FULL_CB_ID :
+ huart->RxFifoFullCallback = HAL_UARTEx_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */
+ break;
+
+ case HAL_UART_TX_FIFO_EMPTY_CB_ID :
+ huart->TxFifoEmptyCallback = HAL_UARTEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */
+ break;
+
+ case HAL_UART_MSPINIT_CB_ID :
+ huart->MspInitCallback = HAL_UART_MspInit; /* Legacy weak MspInitCallback */
+ break;
+
+ case HAL_UART_MSPDEINIT_CB_ID :
+ huart->MspDeInitCallback = HAL_UART_MspDeInit; /* Legacy weak MspDeInitCallback */
+ break;
+
+ default :
+ huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_UART_STATE_RESET == huart->gState)
+ {
+ switch (CallbackID)
+ {
+ case HAL_UART_MSPINIT_CB_ID :
+ huart->MspInitCallback = HAL_UART_MspInit;
+ break;
+
+ case HAL_UART_MSPDEINIT_CB_ID :
+ huart->MspDeInitCallback = HAL_UART_MspDeInit;
+ break;
+
+ default :
+ huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+ status = HAL_ERROR;
+ }
+
+ __HAL_UNLOCK(huart);
+
+ return status;
+}
+
+/**
+ * @brief Register a User UART Rx Event Callback
+ * To be used instead of the weak predefined callback
+ * @param huart Uart handle
+ * @param pCallback Pointer to the Rx Event Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pUART_RxEventCallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(huart);
+
+ if (huart->gState == HAL_UART_STATE_READY)
+ {
+ huart->RxEventCallback = pCallback;
+ }
+ else
+ {
+ huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(huart);
+
+ return status;
+}
+
+/**
+ * @brief UnRegister the UART Rx Event Callback
+ * UART Rx Event Callback is redirected to the weak HAL_UARTEx_RxEventCallback() predefined callback
+ * @param huart Uart handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(huart);
+
+ if (huart->gState == HAL_UART_STATE_READY)
+ {
+ huart->RxEventCallback = HAL_UARTEx_RxEventCallback; /* Legacy weak UART Rx Event Callback */
+ }
+ else
+ {
+ huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(huart);
+ return status;
+}
+
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+/** @defgroup UART_Exported_Functions_Group2 IO operation functions
+ * @brief UART Transmit/Receive functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ This subsection provides a set of functions allowing to manage the UART asynchronous
+ and Half duplex data transfers.
+
+ (#) There are two mode of transfer:
+ (+) Blocking mode: The communication is performed in polling mode.
+ The HAL status of all data processing is returned by the same function
+ after finishing transfer.
+ (+) Non-Blocking mode: The communication is performed using Interrupts
+ or DMA, These API's return the HAL status.
+ The end of the data processing will be indicated through the
+ dedicated UART IRQ when using Interrupt mode or the DMA IRQ when
+ using DMA mode.
+ The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks
+ will be executed respectively at the end of the transmit or Receive process
+ The HAL_UART_ErrorCallback()user callback will be executed when a communication error is detected
+
+ (#) Blocking mode API's are :
+ (+) HAL_UART_Transmit()
+ (+) HAL_UART_Receive()
+
+ (#) Non-Blocking mode API's with Interrupt are :
+ (+) HAL_UART_Transmit_IT()
+ (+) HAL_UART_Receive_IT()
+ (+) HAL_UART_IRQHandler()
+
+ (#) Non-Blocking mode API's with DMA are :
+ (+) HAL_UART_Transmit_DMA()
+ (+) HAL_UART_Receive_DMA()
+ (+) HAL_UART_DMAPause()
+ (+) HAL_UART_DMAResume()
+ (+) HAL_UART_DMAStop()
+
+ (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode:
+ (+) HAL_UART_TxHalfCpltCallback()
+ (+) HAL_UART_TxCpltCallback()
+ (+) HAL_UART_RxHalfCpltCallback()
+ (+) HAL_UART_RxCpltCallback()
+ (+) HAL_UART_ErrorCallback()
+
+ (#) Non-Blocking mode transfers could be aborted using Abort API's :
+ (+) HAL_UART_Abort()
+ (+) HAL_UART_AbortTransmit()
+ (+) HAL_UART_AbortReceive()
+ (+) HAL_UART_Abort_IT()
+ (+) HAL_UART_AbortTransmit_IT()
+ (+) HAL_UART_AbortReceive_IT()
+
+ (#) For Abort services based on interrupts (HAL_UART_Abortxxx_IT), a set of Abort Complete Callbacks are provided:
+ (+) HAL_UART_AbortCpltCallback()
+ (+) HAL_UART_AbortTransmitCpltCallback()
+ (+) HAL_UART_AbortReceiveCpltCallback()
+
+ (#) A Rx Event Reception Callback (Rx event notification) is available for Non_Blocking modes of enhanced
+ reception services:
+ (+) HAL_UARTEx_RxEventCallback()
+
+ (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
+ Errors are handled as follows :
+ (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
+ to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error
+ in Interrupt mode reception .
+ Received character is then retrieved and stored in Rx buffer, Error code is set to allow user
+ to identify error type, and HAL_UART_ErrorCallback() user callback is executed.
+ Transfer is kept ongoing on UART side.
+ If user wants to abort it, Abort services should be called by user.
+ (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
+ This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
+ Error code is set to allow user to identify error type, and HAL_UART_ErrorCallback()
+ user callback is executed.
+
+ -@- In the Half duplex communication, it is forbidden to run the transmit
+ and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX can't be useful.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Send an amount of data in blocking mode.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the sent data is handled as a set of u16. In this case, Size must indicate the number
+ * of u16 provided through pData.
+ * @note When FIFO mode is enabled, writing a data in the TDR register adds one
+ * data to the TXFIFO. Write operations to the TDR register are performed
+ * when TXFNF flag is set. From hardware perspective, TXFNF flag and
+ * TXE are mapped on the same bit-field.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits)
+ * (as sent data will be handled using u16 pointer cast). Depending on compilation chain,
+ * use of specific alignment compilation directives or pragmas might be required
+ * to ensure proper alignment for pData.
+ * @param huart UART handle.
+ * @param pData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be sent.
+ * @param Timeout Timeout duration.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ const uint8_t *pdata8bits;
+ const uint16_t *pdata16bits;
+ uint32_t tickstart;
+
+ /* Check that a Tx process is not already ongoing */
+ if (huart->gState == HAL_UART_STATE_READY)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter
+ should be aligned on a u16 frontier, as data to be filled into TDR will be
+ handled through a u16 cast. */
+ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+ {
+ if ((((uint32_t)pData) & 1U) != 0U)
+ {
+ return HAL_ERROR;
+ }
+ }
+
+ __HAL_LOCK(huart);
+
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+ huart->gState = HAL_UART_STATE_BUSY_TX;
+
+ /* Init tickstart for timeout management */
+ tickstart = HAL_GetTick();
+
+ huart->TxXferSize = Size;
+ huart->TxXferCount = Size;
+
+ /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */
+ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+ {
+ pdata8bits = NULL;
+ pdata16bits = (const uint16_t *) pData;
+ }
+ else
+ {
+ pdata8bits = pData;
+ pdata16bits = NULL;
+ }
+
+ __HAL_UNLOCK(huart);
+
+ while (huart->TxXferCount > 0U)
+ {
+ if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ if (pdata8bits == NULL)
+ {
+ huart->Instance->TDR = (uint16_t)(*pdata16bits & 0x01FFU);
+ pdata16bits++;
+ }
+ else
+ {
+ huart->Instance->TDR = (uint8_t)(*pdata8bits & 0xFFU);
+ pdata8bits++;
+ }
+ huart->TxXferCount--;
+ }
+
+ if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* At end of Tx process, restore huart->gState to Ready */
+ huart->gState = HAL_UART_STATE_READY;
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in blocking mode.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the received data is handled as a set of u16. In this case, Size must indicate the number
+ * of u16 available through pData.
+ * @note When FIFO mode is enabled, the RXFNE flag is set as long as the RXFIFO
+ * is not empty. Read operations from the RDR register are performed when
+ * RXFNE flag is set. From hardware perspective, RXFNE flag and
+ * RXNE are mapped on the same bit-field.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * address of user data buffer for storing data to be received, should be aligned on a half word frontier
+ * (16 bits) (as received data will be handled using u16 pointer cast). Depending on compilation chain,
+ * use of specific alignment compilation directives or pragmas might be required
+ * to ensure proper alignment for pData.
+ * @param huart UART handle.
+ * @param pData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be received.
+ * @param Timeout Timeout duration.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ uint8_t *pdata8bits;
+ uint16_t *pdata16bits;
+ uint16_t uhMask;
+ uint32_t tickstart;
+
+ /* Check that a Rx process is not already ongoing */
+ if (huart->RxState == HAL_UART_STATE_READY)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter
+ should be aligned on a u16 frontier, as data to be received from RDR will be
+ handled through a u16 cast. */
+ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+ {
+ if ((((uint32_t)pData) & 1U) != 0U)
+ {
+ return HAL_ERROR;
+ }
+ }
+
+ __HAL_LOCK(huart);
+
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+ huart->RxState = HAL_UART_STATE_BUSY_RX;
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+ /* Init tickstart for timeout management */
+ tickstart = HAL_GetTick();
+
+ huart->RxXferSize = Size;
+ huart->RxXferCount = Size;
+
+ /* Computation of UART mask to apply to RDR register */
+ UART_MASK_COMPUTATION(huart);
+ uhMask = huart->Mask;
+
+ /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */
+ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+ {
+ pdata8bits = NULL;
+ pdata16bits = (uint16_t *) pData;
+ }
+ else
+ {
+ pdata8bits = pData;
+ pdata16bits = NULL;
+ }
+
+ __HAL_UNLOCK(huart);
+
+ /* as long as data have to be received */
+ while (huart->RxXferCount > 0U)
+ {
+ if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ if (pdata8bits == NULL)
+ {
+ *pdata16bits = (uint16_t)(huart->Instance->RDR & uhMask);
+ pdata16bits++;
+ }
+ else
+ {
+ *pdata8bits = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask);
+ pdata8bits++;
+ }
+ huart->RxXferCount--;
+ }
+
+ /* At end of Rx process, restore huart->RxState to Ready */
+ huart->RxState = HAL_UART_STATE_READY;
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Send an amount of data in interrupt mode.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the sent data is handled as a set of u16. In this case, Size must indicate the number
+ * of u16 provided through pData.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits)
+ * (as sent data will be handled using u16 pointer cast). Depending on compilation chain,
+ * use of specific alignment compilation directives or pragmas might be required
+ * to ensure proper alignment for pData.
+ * @param huart UART handle.
+ * @param pData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be sent.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size)
+{
+ /* Check that a Tx process is not already ongoing */
+ if (huart->gState == HAL_UART_STATE_READY)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter
+ should be aligned on a u16 frontier, as data to be filled into TDR will be
+ handled through a u16 cast. */
+ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+ {
+ if ((((uint32_t)pData) & 1U) != 0U)
+ {
+ return HAL_ERROR;
+ }
+ }
+
+ __HAL_LOCK(huart);
+
+ huart->pTxBuffPtr = pData;
+ huart->TxXferSize = Size;
+ huart->TxXferCount = Size;
+ huart->TxISR = NULL;
+
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+ huart->gState = HAL_UART_STATE_BUSY_TX;
+
+ /* Configure Tx interrupt processing */
+ if (huart->FifoMode == UART_FIFOMODE_ENABLE)
+ {
+ /* Set the Tx ISR function pointer according to the data word length */
+ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+ {
+ huart->TxISR = UART_TxISR_16BIT_FIFOEN;
+ }
+ else
+ {
+ huart->TxISR = UART_TxISR_8BIT_FIFOEN;
+ }
+
+ __HAL_UNLOCK(huart);
+
+ /* Enable the TX FIFO threshold interrupt */
+ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
+ }
+ else
+ {
+ /* Set the Tx ISR function pointer according to the data word length */
+ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+ {
+ huart->TxISR = UART_TxISR_16BIT;
+ }
+ else
+ {
+ huart->TxISR = UART_TxISR_8BIT;
+ }
+
+ __HAL_UNLOCK(huart);
+
+ /* Enable the Transmit Data Register Empty interrupt */
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
+ }
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in interrupt mode.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the received data is handled as a set of u16. In this case, Size must indicate the number
+ * of u16 available through pData.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * address of user data buffer for storing data to be received, should be aligned on a half word frontier
+ * (16 bits) (as received data will be handled using u16 pointer cast). Depending on compilation chain,
+ * use of specific alignment compilation directives or pragmas might be required
+ * to ensure proper alignment for pData.
+ * @param huart UART handle.
+ * @param pData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be received.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+{
+ /* Check that a Rx process is not already ongoing */
+ if (huart->RxState == HAL_UART_STATE_READY)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter
+ should be aligned on a u16 frontier, as data to be received from RDR will be
+ handled through a u16 cast. */
+ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+ {
+ if ((((uint32_t)pData) & 1U) != 0U)
+ {
+ return HAL_ERROR;
+ }
+ }
+
+ __HAL_LOCK(huart);
+
+ /* Set Reception type to Standard reception */
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+ /* Check that USART RTOEN bit is set */
+ if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
+ {
+ /* Enable the UART Receiver Timeout Interrupt */
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
+ }
+
+ return (UART_Start_Receive_IT(huart, pData, Size));
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Send an amount of data in DMA mode.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the sent data is handled as a set of u16. In this case, Size must indicate the number
+ * of u16 provided through pData.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits)
+ * (as sent data will be handled by DMA from halfword frontier). Depending on compilation chain,
+ * use of specific alignment compilation directives or pragmas might be required
+ * to ensure proper alignment for pData.
+ * @param huart UART handle.
+ * @param pData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be sent.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size)
+{
+ /* Check that a Tx process is not already ongoing */
+ if (huart->gState == HAL_UART_STATE_READY)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter
+ should be aligned on a u16 frontier, as data copy into TDR will be
+ handled by DMA from a u16 frontier. */
+ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+ {
+ if ((((uint32_t)pData) & 1U) != 0U)
+ {
+ return HAL_ERROR;
+ }
+ }
+
+ __HAL_LOCK(huart);
+
+ huart->pTxBuffPtr = pData;
+ huart->TxXferSize = Size;
+ huart->TxXferCount = Size;
+
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+ huart->gState = HAL_UART_STATE_BUSY_TX;
+
+ if (huart->hdmatx != NULL)
+ {
+ /* Set the UART DMA transfer complete callback */
+ huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt;
+
+ /* Set the UART DMA Half transfer complete callback */
+ huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt;
+
+ /* Set the DMA error callback */
+ huart->hdmatx->XferErrorCallback = UART_DMAError;
+
+ /* Set the DMA abort callback */
+ huart->hdmatx->XferAbortCallback = NULL;
+
+ /* Enable the UART transmit DMA channel */
+ if (HAL_DMA_Start_IT(huart->hdmatx, (uint32_t)huart->pTxBuffPtr, (uint32_t)&huart->Instance->TDR, Size) != HAL_OK)
+ {
+ /* Set error code to DMA */
+ huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+ __HAL_UNLOCK(huart);
+
+ /* Restore huart->gState to ready */
+ huart->gState = HAL_UART_STATE_READY;
+
+ return HAL_ERROR;
+ }
+ }
+ /* Clear the TC flag in the ICR register */
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF);
+
+ __HAL_UNLOCK(huart);
+
+ /* Enable the DMA transfer for transmit request by setting the DMAT bit
+ in the UART CR3 register */
+ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in DMA mode.
+ * @note When the UART parity is enabled (PCE = 1), the received data contain
+ * the parity bit (MSB position).
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the received data is handled as a set of u16. In this case, Size must indicate the number
+ * of u16 available through pData.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * address of user data buffer for storing data to be received, should be aligned on a half word frontier
+ * (16 bits) (as received data will be handled by DMA from halfword frontier). Depending on compilation chain,
+ * use of specific alignment compilation directives or pragmas might be required
+ * to ensure proper alignment for pData.
+ * @param huart UART handle.
+ * @param pData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be received.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+{
+ /* Check that a Rx process is not already ongoing */
+ if (huart->RxState == HAL_UART_STATE_READY)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter
+ should be aligned on a u16 frontier, as data copy from RDR will be
+ handled by DMA from a u16 frontier. */
+ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+ {
+ if ((((uint32_t)pData) & 1U) != 0U)
+ {
+ return HAL_ERROR;
+ }
+ }
+
+ __HAL_LOCK(huart);
+
+ /* Set Reception type to Standard reception */
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+ /* Check that USART RTOEN bit is set */
+ if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
+ {
+ /* Enable the UART Receiver Timeout Interrupt */
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
+ }
+
+ return (UART_Start_Receive_DMA(huart, pData, Size));
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Pause the DMA Transfer.
+ * @param huart UART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart)
+{
+ const HAL_UART_StateTypeDef gstate = huart->gState;
+ const HAL_UART_StateTypeDef rxstate = huart->RxState;
+
+ __HAL_LOCK(huart);
+
+ if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) &&
+ (gstate == HAL_UART_STATE_BUSY_TX))
+ {
+ /* Disable the UART DMA Tx request */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+ }
+ if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) &&
+ (rxstate == HAL_UART_STATE_BUSY_RX))
+ {
+ /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+ /* Disable the UART DMA Rx request */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+ }
+
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Resume the DMA Transfer.
+ * @param huart UART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart)
+{
+ __HAL_LOCK(huart);
+
+ if (huart->gState == HAL_UART_STATE_BUSY_TX)
+ {
+ /* Enable the UART DMA Tx request */
+ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+ }
+ if (huart->RxState == HAL_UART_STATE_BUSY_RX)
+ {
+ /* Clear the Overrun flag before resuming the Rx transfer */
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
+
+ /* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */
+ if (huart->Init.Parity != UART_PARITY_NONE)
+ {
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+ }
+ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+ /* Enable the UART DMA Rx request */
+ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+ }
+
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Stop the DMA Transfer.
+ * @param huart UART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart)
+{
+ /* The Lock is not implemented on this API to allow the user application
+ to call the HAL UART API under callbacks HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback() /
+ HAL_UART_TxHalfCpltCallback / HAL_UART_RxHalfCpltCallback:
+ indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete
+ interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of
+ the stream and the corresponding call back is executed. */
+
+ const HAL_UART_StateTypeDef gstate = huart->gState;
+ const HAL_UART_StateTypeDef rxstate = huart->RxState;
+
+ /* Stop UART DMA Tx request if ongoing */
+ if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) &&
+ (gstate == HAL_UART_STATE_BUSY_TX))
+ {
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the UART DMA Tx channel */
+ if (huart->hdmatx != NULL)
+ {
+ if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK)
+ {
+ if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
+ {
+ /* Set error code to DMA */
+ huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ UART_EndTxTransfer(huart);
+ }
+
+ /* Stop UART DMA Rx request if ongoing */
+ if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) &&
+ (rxstate == HAL_UART_STATE_BUSY_RX))
+ {
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the UART DMA Rx channel */
+ if (huart->hdmarx != NULL)
+ {
+ if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK)
+ {
+ if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
+ {
+ /* Set error code to DMA */
+ huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ UART_EndRxTransfer(huart);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing transfers (blocking mode).
+ * @param huart UART handle.
+ * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable UART Interrupts (Tx and Rx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart)
+{
+ /* Disable TXE, TC, RXNE, PE, RXFT, TXFT and ERR (Frame error, noise error, overrun error) interrupts */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE |
+ USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE);
+
+ /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */
+ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+ {
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
+ }
+
+ /* Abort the UART DMA Tx channel if enabled */
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
+ {
+ /* Disable the UART DMA Tx request if enabled */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */
+ if (huart->hdmatx != NULL)
+ {
+ /* Set the UART DMA Abort callback to Null.
+ No call back execution at end of DMA abort procedure */
+ huart->hdmatx->XferAbortCallback = NULL;
+
+ if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK)
+ {
+ if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
+ {
+ /* Set error code to DMA */
+ huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+
+ /* Abort the UART DMA Rx channel if enabled */
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+ {
+ /* Disable the UART DMA Rx request if enabled */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */
+ if (huart->hdmarx != NULL)
+ {
+ /* Set the UART DMA Abort callback to Null.
+ No call back execution at end of DMA abort procedure */
+ huart->hdmarx->XferAbortCallback = NULL;
+
+ if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK)
+ {
+ if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
+ {
+ /* Set error code to DMA */
+ huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+
+ /* Reset Tx and Rx transfer counters */
+ huart->TxXferCount = 0U;
+ huart->RxXferCount = 0U;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+
+ /* Flush the whole TX FIFO (if needed) */
+ if (huart->FifoMode == UART_FIFOMODE_ENABLE)
+ {
+ __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST);
+ }
+
+ /* Discard the received data */
+ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+
+ /* Restore huart->gState and huart->RxState to Ready */
+ huart->gState = HAL_UART_STATE_READY;
+ huart->RxState = HAL_UART_STATE_READY;
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing Transmit transfer (blocking mode).
+ * @param huart UART handle.
+ * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable UART Interrupts (Tx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart)
+{
+ /* Disable TCIE, TXEIE and TXFTIE interrupts */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TCIE | USART_CR1_TXEIE_TXFNFIE));
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
+
+ /* Abort the UART DMA Tx channel if enabled */
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
+ {
+ /* Disable the UART DMA Tx request if enabled */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */
+ if (huart->hdmatx != NULL)
+ {
+ /* Set the UART DMA Abort callback to Null.
+ No call back execution at end of DMA abort procedure */
+ huart->hdmatx->XferAbortCallback = NULL;
+
+ if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK)
+ {
+ if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
+ {
+ /* Set error code to DMA */
+ huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+
+ /* Reset Tx transfer counter */
+ huart->TxXferCount = 0U;
+
+ /* Flush the whole TX FIFO (if needed) */
+ if (huart->FifoMode == UART_FIFOMODE_ENABLE)
+ {
+ __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST);
+ }
+
+ /* Restore huart->gState to Ready */
+ huart->gState = HAL_UART_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing Receive transfer (blocking mode).
+ * @param huart UART handle.
+ * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable UART Interrupts (Rx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart)
+{
+ /* Disable PEIE, EIE, RXNEIE and RXFTIE interrupts */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE));
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE);
+
+ /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */
+ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+ {
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
+ }
+
+ /* Abort the UART DMA Rx channel if enabled */
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+ {
+ /* Disable the UART DMA Rx request if enabled */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */
+ if (huart->hdmarx != NULL)
+ {
+ /* Set the UART DMA Abort callback to Null.
+ No call back execution at end of DMA abort procedure */
+ huart->hdmarx->XferAbortCallback = NULL;
+
+ if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK)
+ {
+ if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
+ {
+ /* Set error code to DMA */
+ huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+
+ /* Reset Rx transfer counter */
+ huart->RxXferCount = 0U;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+
+ /* Discard the received data */
+ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+
+ /* Restore huart->RxState to Ready */
+ huart->RxState = HAL_UART_STATE_READY;
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing transfers (Interrupt mode).
+ * @param huart UART handle.
+ * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable UART Interrupts (Tx and Rx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * - At abort completion, call user abort complete callback
+ * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
+ * considered as completed only when user abort complete callback is executed (not when exiting function).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart)
+{
+ uint32_t abortcplt = 1U;
+
+ /* Disable interrupts */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_TCIE | USART_CR1_RXNEIE_RXFNEIE |
+ USART_CR1_TXEIE_TXFNFIE));
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE));
+
+ /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */
+ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+ {
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
+ }
+
+ /* If DMA Tx and/or DMA Rx Handles are associated to UART Handle, DMA Abort complete callbacks should be initialised
+ before any call to DMA Abort functions */
+ /* DMA Tx Handle is valid */
+ if (huart->hdmatx != NULL)
+ {
+ /* Set DMA Abort Complete callback if UART DMA Tx request if enabled.
+ Otherwise, set it to NULL */
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
+ {
+ huart->hdmatx->XferAbortCallback = UART_DMATxAbortCallback;
+ }
+ else
+ {
+ huart->hdmatx->XferAbortCallback = NULL;
+ }
+ }
+ /* DMA Rx Handle is valid */
+ if (huart->hdmarx != NULL)
+ {
+ /* Set DMA Abort Complete callback if UART DMA Rx request if enabled.
+ Otherwise, set it to NULL */
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+ {
+ huart->hdmarx->XferAbortCallback = UART_DMARxAbortCallback;
+ }
+ else
+ {
+ huart->hdmarx->XferAbortCallback = NULL;
+ }
+ }
+
+ /* Abort the UART DMA Tx channel if enabled */
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
+ {
+ /* Disable DMA Tx at UART level */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */
+ if (huart->hdmatx != NULL)
+ {
+ /* UART Tx DMA Abort callback has already been initialised :
+ will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
+
+ /* Abort DMA TX */
+ if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK)
+ {
+ huart->hdmatx->XferAbortCallback = NULL;
+ }
+ else
+ {
+ abortcplt = 0U;
+ }
+ }
+ }
+
+ /* Abort the UART DMA Rx channel if enabled */
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+ {
+ /* Disable the UART DMA Rx request if enabled */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */
+ if (huart->hdmarx != NULL)
+ {
+ /* UART Rx DMA Abort callback has already been initialised :
+ will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
+
+ /* Abort DMA RX */
+ if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
+ {
+ huart->hdmarx->XferAbortCallback = NULL;
+ abortcplt = 1U;
+ }
+ else
+ {
+ abortcplt = 0U;
+ }
+ }
+ }
+
+ /* if no DMA abort complete callback execution is required => call user Abort Complete callback */
+ if (abortcplt == 1U)
+ {
+ /* Reset Tx and Rx transfer counters */
+ huart->TxXferCount = 0U;
+ huart->RxXferCount = 0U;
+
+ /* Clear ISR function pointers */
+ huart->RxISR = NULL;
+ huart->TxISR = NULL;
+
+ /* Reset errorCode */
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+
+ /* Flush the whole TX FIFO (if needed) */
+ if (huart->FifoMode == UART_FIFOMODE_ENABLE)
+ {
+ __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST);
+ }
+
+ /* Discard the received data */
+ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+
+ /* Restore huart->gState and huart->RxState to Ready */
+ huart->gState = HAL_UART_STATE_READY;
+ huart->RxState = HAL_UART_STATE_READY;
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort complete callback */
+ huart->AbortCpltCallback(huart);
+#else
+ /* Call legacy weak Abort complete callback */
+ HAL_UART_AbortCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing Transmit transfer (Interrupt mode).
+ * @param huart UART handle.
+ * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable UART Interrupts (Tx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * - At abort completion, call user abort complete callback
+ * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
+ * considered as completed only when user abort complete callback is executed (not when exiting function).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart)
+{
+ /* Disable interrupts */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TCIE | USART_CR1_TXEIE_TXFNFIE));
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
+
+ /* Abort the UART DMA Tx channel if enabled */
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
+ {
+ /* Disable the UART DMA Tx request if enabled */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */
+ if (huart->hdmatx != NULL)
+ {
+ /* Set the UART DMA Abort callback :
+ will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
+ huart->hdmatx->XferAbortCallback = UART_DMATxOnlyAbortCallback;
+
+ /* Abort DMA TX */
+ if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK)
+ {
+ /* Call Directly huart->hdmatx->XferAbortCallback function in case of error */
+ huart->hdmatx->XferAbortCallback(huart->hdmatx);
+ }
+ }
+ else
+ {
+ /* Reset Tx transfer counter */
+ huart->TxXferCount = 0U;
+
+ /* Clear TxISR function pointers */
+ huart->TxISR = NULL;
+
+ /* Restore huart->gState to Ready */
+ huart->gState = HAL_UART_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Transmit Complete Callback */
+ huart->AbortTransmitCpltCallback(huart);
+#else
+ /* Call legacy weak Abort Transmit Complete Callback */
+ HAL_UART_AbortTransmitCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ }
+ }
+ else
+ {
+ /* Reset Tx transfer counter */
+ huart->TxXferCount = 0U;
+
+ /* Clear TxISR function pointers */
+ huart->TxISR = NULL;
+
+ /* Flush the whole TX FIFO (if needed) */
+ if (huart->FifoMode == UART_FIFOMODE_ENABLE)
+ {
+ __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST);
+ }
+
+ /* Restore huart->gState to Ready */
+ huart->gState = HAL_UART_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Transmit Complete Callback */
+ huart->AbortTransmitCpltCallback(huart);
+#else
+ /* Call legacy weak Abort Transmit Complete Callback */
+ HAL_UART_AbortTransmitCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing Receive transfer (Interrupt mode).
+ * @param huart UART handle.
+ * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable UART Interrupts (Rx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * - At abort completion, call user abort complete callback
+ * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
+ * considered as completed only when user abort complete callback is executed (not when exiting function).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart)
+{
+ /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE));
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
+
+ /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */
+ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+ {
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
+ }
+
+ /* Abort the UART DMA Rx channel if enabled */
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+ {
+ /* Disable the UART DMA Rx request if enabled */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */
+ if (huart->hdmarx != NULL)
+ {
+ /* Set the UART DMA Abort callback :
+ will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
+ huart->hdmarx->XferAbortCallback = UART_DMARxOnlyAbortCallback;
+
+ /* Abort DMA RX */
+ if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
+ {
+ /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */
+ huart->hdmarx->XferAbortCallback(huart->hdmarx);
+ }
+ }
+ else
+ {
+ /* Reset Rx transfer counter */
+ huart->RxXferCount = 0U;
+
+ /* Clear RxISR function pointer */
+ huart->pRxBuffPtr = NULL;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+
+ /* Discard the received data */
+ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+
+ /* Restore huart->RxState to Ready */
+ huart->RxState = HAL_UART_STATE_READY;
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Receive Complete Callback */
+ huart->AbortReceiveCpltCallback(huart);
+#else
+ /* Call legacy weak Abort Receive Complete Callback */
+ HAL_UART_AbortReceiveCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ }
+ }
+ else
+ {
+ /* Reset Rx transfer counter */
+ huart->RxXferCount = 0U;
+
+ /* Clear RxISR function pointer */
+ huart->pRxBuffPtr = NULL;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+
+ /* Restore huart->RxState to Ready */
+ huart->RxState = HAL_UART_STATE_READY;
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Receive Complete Callback */
+ huart->AbortReceiveCpltCallback(huart);
+#else
+ /* Call legacy weak Abort Receive Complete Callback */
+ HAL_UART_AbortReceiveCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle UART interrupt request.
+ * @param huart UART handle.
+ * @retval None
+ */
+void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
+{
+ uint32_t isrflags = READ_REG(huart->Instance->ISR);
+ uint32_t cr1its = READ_REG(huart->Instance->CR1);
+ uint32_t cr3its = READ_REG(huart->Instance->CR3);
+
+ uint32_t errorflags;
+ uint32_t errorcode;
+
+ /* If no error occurs */
+ errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF));
+ if (errorflags == 0U)
+ {
+ /* UART in mode Receiver ---------------------------------------------------*/
+ if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U)
+ && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)
+ || ((cr3its & USART_CR3_RXFTIE) != 0U)))
+ {
+ if (huart->RxISR != NULL)
+ {
+ huart->RxISR(huart);
+ }
+ return;
+ }
+ }
+
+ /* If some errors occur */
+ if ((errorflags != 0U)
+ && ((((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U)
+ || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE)) != 0U))))
+ {
+ /* UART parity error interrupt occurred -------------------------------------*/
+ if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
+ {
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF);
+
+ huart->ErrorCode |= HAL_UART_ERROR_PE;
+ }
+
+ /* UART frame error interrupt occurred --------------------------------------*/
+ if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
+ {
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF);
+
+ huart->ErrorCode |= HAL_UART_ERROR_FE;
+ }
+
+ /* UART noise error interrupt occurred --------------------------------------*/
+ if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
+ {
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF);
+
+ huart->ErrorCode |= HAL_UART_ERROR_NE;
+ }
+
+ /* UART Over-Run interrupt occurred -----------------------------------------*/
+ if (((isrflags & USART_ISR_ORE) != 0U)
+ && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) ||
+ ((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U)))
+ {
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
+
+ huart->ErrorCode |= HAL_UART_ERROR_ORE;
+ }
+
+ /* UART Receiver Timeout interrupt occurred ---------------------------------*/
+ if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U))
+ {
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
+
+ huart->ErrorCode |= HAL_UART_ERROR_RTO;
+ }
+
+ /* Call UART Error Call back function if need be ----------------------------*/
+ if (huart->ErrorCode != HAL_UART_ERROR_NONE)
+ {
+ /* UART in mode Receiver --------------------------------------------------*/
+ if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U)
+ && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)
+ || ((cr3its & USART_CR3_RXFTIE) != 0U)))
+ {
+ if (huart->RxISR != NULL)
+ {
+ huart->RxISR(huart);
+ }
+ }
+
+ /* If Error is to be considered as blocking :
+ - Receiver Timeout error in Reception
+ - Overrun error in Reception
+ - any error occurs in DMA mode reception
+ */
+ errorcode = huart->ErrorCode;
+ if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) ||
+ ((errorcode & (HAL_UART_ERROR_RTO | HAL_UART_ERROR_ORE)) != 0U))
+ {
+ /* Blocking error : transfer is aborted
+ Set the UART state ready to be able to start again the process,
+ Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
+ UART_EndRxTransfer(huart);
+
+ /* Abort the UART DMA Rx channel if enabled */
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+ {
+ /* Disable the UART DMA Rx request if enabled */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the UART DMA Rx channel */
+ if (huart->hdmarx != NULL)
+ {
+ /* Set the UART DMA Abort callback :
+ will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */
+ huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError;
+
+ /* Abort DMA RX */
+ if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
+ {
+ /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */
+ huart->hdmarx->XferAbortCallback(huart->hdmarx);
+ }
+ }
+ else
+ {
+ /* Call user error callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered error callback*/
+ huart->ErrorCallback(huart);
+#else
+ /*Call legacy weak error callback*/
+ HAL_UART_ErrorCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+
+ }
+ }
+ else
+ {
+ /* Call user error callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered error callback*/
+ huart->ErrorCallback(huart);
+#else
+ /*Call legacy weak error callback*/
+ HAL_UART_ErrorCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ }
+ }
+ else
+ {
+ /* Non Blocking error : transfer could go on.
+ Error is notified to user through user error callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered error callback*/
+ huart->ErrorCallback(huart);
+#else
+ /*Call legacy weak error callback*/
+ HAL_UART_ErrorCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+ }
+ }
+ return;
+
+ } /* End if some error occurs */
+
+ /* Check current reception Mode :
+ If Reception till IDLE event has been selected : */
+ if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+ && ((isrflags & USART_ISR_IDLE) != 0U)
+ && ((cr1its & USART_ISR_IDLE) != 0U))
+ {
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
+
+ /* Check if DMA mode is enabled in UART */
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+ {
+ /* DMA mode enabled */
+ /* Check received length : If all expected data are received, do nothing,
+ (DMA cplt callback will be called).
+ Otherwise, if at least one data has already been received, IDLE event is to be notified to user */
+ uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx);
+ if ((nb_remaining_rx_data > 0U)
+ && (nb_remaining_rx_data < huart->RxXferSize))
+ {
+ /* Reception is not complete */
+ huart->RxXferCount = nb_remaining_rx_data;
+
+ /* In Normal mode, end DMA xfer and HAL UART Rx process*/
+ if (HAL_IS_BIT_CLR(huart->hdmarx->Instance->CCR, DMA_CCR_CIRC))
+ {
+ /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+ /* Disable the DMA transfer for the receiver request by resetting the DMAR bit
+ in the UART CR3 register */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+ /* At end of Rx process, restore huart->RxState to Ready */
+ huart->RxState = HAL_UART_STATE_READY;
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+
+ /* Last bytes received, so no need as the abort is immediate */
+ (void)HAL_DMA_Abort(huart->hdmarx);
+ }
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered Rx Event callback*/
+ huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
+#else
+ /*Call legacy weak Rx Event callback*/
+ HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+ }
+ return;
+ }
+ else
+ {
+ /* DMA mode not enabled */
+ /* Check received length : If all expected data are received, do nothing.
+ Otherwise, if at least one data has already been received, IDLE event is to be notified to user */
+ uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount;
+ if ((huart->RxXferCount > 0U)
+ && (nb_rx_data > 0U))
+ {
+ /* Disable the UART Parity Error Interrupt and RXNE interrupts */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
+
+ /* Disable the UART Error Interrupt:(Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
+
+ /* Rx process is completed, restore huart->RxState to Ready */
+ huart->RxState = HAL_UART_STATE_READY;
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+ /* Clear RxISR function pointer */
+ huart->RxISR = NULL;
+
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered Rx complete callback*/
+ huart->RxEventCallback(huart, nb_rx_data);
+#else
+ /*Call legacy weak Rx Event callback*/
+ HAL_UARTEx_RxEventCallback(huart, nb_rx_data);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+ }
+ return;
+ }
+ }
+
+ /* UART wakeup from Stop mode interrupt occurred ---------------------------*/
+ if (((isrflags & USART_ISR_WUF) != 0U) && ((cr3its & USART_CR3_WUFIE) != 0U))
+ {
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_WUF);
+
+ /* UART Rx state is not reset as a reception process might be ongoing.
+ If UART handle state fields need to be reset to READY, this could be done in Wakeup callback */
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /* Call registered Wakeup Callback */
+ huart->WakeupCallback(huart);
+#else
+ /* Call legacy weak Wakeup Callback */
+ HAL_UARTEx_WakeupCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ return;
+ }
+
+ /* UART in mode Transmitter ------------------------------------------------*/
+ if (((isrflags & USART_ISR_TXE_TXFNF) != 0U)
+ && (((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U)
+ || ((cr3its & USART_CR3_TXFTIE) != 0U)))
+ {
+ if (huart->TxISR != NULL)
+ {
+ huart->TxISR(huart);
+ }
+ return;
+ }
+
+ /* UART in mode Transmitter (transmission end) -----------------------------*/
+ if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U))
+ {
+ UART_EndTransmit_IT(huart);
+ return;
+ }
+
+ /* UART TX Fifo Empty occurred ----------------------------------------------*/
+ if (((isrflags & USART_ISR_TXFE) != 0U) && ((cr1its & USART_CR1_TXFEIE) != 0U))
+ {
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /* Call registered Tx Fifo Empty Callback */
+ huart->TxFifoEmptyCallback(huart);
+#else
+ /* Call legacy weak Tx Fifo Empty Callback */
+ HAL_UARTEx_TxFifoEmptyCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ return;
+ }
+
+ /* UART RX Fifo Full occurred ----------------------------------------------*/
+ if (((isrflags & USART_ISR_RXFF) != 0U) && ((cr1its & USART_CR1_RXFFIE) != 0U))
+ {
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /* Call registered Rx Fifo Full Callback */
+ huart->RxFifoFullCallback(huart);
+#else
+ /* Call legacy weak Rx Fifo Full Callback */
+ HAL_UARTEx_RxFifoFullCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ return;
+ }
+}
+
+/**
+ * @brief Tx Transfer completed callback.
+ * @param huart UART handle.
+ * @retval None
+ */
+__weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(huart);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_UART_TxCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief Tx Half Transfer completed callback.
+ * @param huart UART handle.
+ * @retval None
+ */
+__weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(huart);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_UART_TxHalfCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief Rx Transfer completed callback.
+ * @param huart UART handle.
+ * @retval None
+ */
+__weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(huart);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_UART_RxCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief Rx Half Transfer completed callback.
+ * @param huart UART handle.
+ * @retval None
+ */
+__weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(huart);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_UART_RxHalfCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief UART error callback.
+ * @param huart UART handle.
+ * @retval None
+ */
+__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(huart);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_UART_ErrorCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief UART Abort Complete callback.
+ * @param huart UART handle.
+ * @retval None
+ */
+__weak void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(huart);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_UART_AbortCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief UART Abort Complete callback.
+ * @param huart UART handle.
+ * @retval None
+ */
+__weak void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(huart);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_UART_AbortTransmitCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief UART Abort Receive Complete callback.
+ * @param huart UART handle.
+ * @retval None
+ */
+__weak void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(huart);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_UART_AbortReceiveCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief Reception Event Callback (Rx event notification called after use of advanced reception service).
+ * @param huart UART handle
+ * @param Size Number of data available in application reception buffer (indicates a position in
+ * reception buffer until which, data are available)
+ * @retval None
+ */
+__weak void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(huart);
+ UNUSED(Size);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_UARTEx_RxEventCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup UART_Exported_Functions_Group3 Peripheral Control functions
+ * @brief UART control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control the UART.
+ (+) HAL_UART_ReceiverTimeout_Config() API allows to configure the receiver timeout value on the fly
+ (+) HAL_UART_EnableReceiverTimeout() API enables the receiver timeout feature
+ (+) HAL_UART_DisableReceiverTimeout() API disables the receiver timeout feature
+ (+) HAL_MultiProcessor_EnableMuteMode() API enables mute mode
+ (+) HAL_MultiProcessor_DisableMuteMode() API disables mute mode
+ (+) HAL_MultiProcessor_EnterMuteMode() API enters mute mode
+ (+) UART_SetConfig() API configures the UART peripheral
+ (+) UART_AdvFeatureConfig() API optionally configures the UART advanced features
+ (+) UART_CheckIdleState() API ensures that TEACK and/or REACK are set after initialization
+ (+) HAL_HalfDuplex_EnableTransmitter() API disables receiver and enables transmitter
+ (+) HAL_HalfDuplex_EnableReceiver() API disables transmitter and enables receiver
+ (+) HAL_LIN_SendBreak() API transmits the break characters
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Update on the fly the receiver timeout value in RTOR register.
+ * @param huart Pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @param TimeoutValue receiver timeout value in number of baud blocks. The timeout
+ * value must be less or equal to 0x0FFFFFFFF.
+ * @retval None
+ */
+void HAL_UART_ReceiverTimeout_Config(UART_HandleTypeDef *huart, uint32_t TimeoutValue)
+{
+ assert_param(IS_UART_RECEIVER_TIMEOUT_VALUE(TimeoutValue));
+ MODIFY_REG(huart->Instance->RTOR, USART_RTOR_RTO, TimeoutValue);
+}
+
+/**
+ * @brief Enable the UART receiver timeout feature.
+ * @param huart Pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_EnableReceiverTimeout(UART_HandleTypeDef *huart)
+{
+ if (huart->gState == HAL_UART_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ /* Set the USART RTOEN bit */
+ SET_BIT(huart->Instance->CR2, USART_CR2_RTOEN);
+
+ huart->gState = HAL_UART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Disable the UART receiver timeout feature.
+ * @param huart Pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_DisableReceiverTimeout(UART_HandleTypeDef *huart)
+{
+ if (huart->gState == HAL_UART_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ /* Clear the USART RTOEN bit */
+ CLEAR_BIT(huart->Instance->CR2, USART_CR2_RTOEN);
+
+ huart->gState = HAL_UART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Enable UART in mute mode (does not mean UART enters mute mode;
+ * to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called).
+ * @param huart UART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart)
+{
+ __HAL_LOCK(huart);
+
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ /* Enable USART mute mode by setting the MME bit in the CR1 register */
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_MME);
+
+ huart->gState = HAL_UART_STATE_READY;
+
+ return (UART_CheckIdleState(huart));
+}
+
+/**
+ * @brief Disable UART mute mode (does not mean the UART actually exits mute mode
+ * as it may not have been in mute mode at this very moment).
+ * @param huart UART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart)
+{
+ __HAL_LOCK(huart);
+
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ /* Disable USART mute mode by clearing the MME bit in the CR1 register */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_MME);
+
+ huart->gState = HAL_UART_STATE_READY;
+
+ return (UART_CheckIdleState(huart));
+}
+
+/**
+ * @brief Enter UART mute mode (means UART actually enters mute mode).
+ * @note To exit from mute mode, HAL_MultiProcessor_DisableMuteMode() API must be called.
+ * @param huart UART handle.
+ * @retval None
+ */
+void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart)
+{
+ __HAL_UART_SEND_REQ(huart, UART_MUTE_MODE_REQUEST);
+}
+
+/**
+ * @brief Enable the UART transmitter and disable the UART receiver.
+ * @param huart UART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart)
+{
+ __HAL_LOCK(huart);
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ /* Clear TE and RE bits */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE));
+
+ /* Enable the USART's transmit interface by setting the TE bit in the USART CR1 register */
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TE);
+
+ huart->gState = HAL_UART_STATE_READY;
+
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Enable the UART receiver and disable the UART transmitter.
+ * @param huart UART handle.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart)
+{
+ __HAL_LOCK(huart);
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ /* Clear TE and RE bits */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE));
+
+ /* Enable the USART's receive interface by setting the RE bit in the USART CR1 register */
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RE);
+
+ huart->gState = HAL_UART_STATE_READY;
+
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Transmit break characters.
+ * @param huart UART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart)
+{
+ /* Check the parameters */
+ assert_param(IS_UART_LIN_INSTANCE(huart->Instance));
+
+ __HAL_LOCK(huart);
+
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ /* Send break characters */
+ __HAL_UART_SEND_REQ(huart, UART_SENDBREAK_REQUEST);
+
+ huart->gState = HAL_UART_STATE_READY;
+
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup UART_Exported_Functions_Group4 Peripheral State and Error functions
+ * @brief UART Peripheral State functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral State and Error functions #####
+ ==============================================================================
+ [..]
+ This subsection provides functions allowing to :
+ (+) Return the UART handle state.
+ (+) Return the UART handle error code
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the UART handle state.
+ * @param huart Pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART.
+ * @retval HAL state
+ */
+HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart)
+{
+ uint32_t temp1;
+ uint32_t temp2;
+ temp1 = huart->gState;
+ temp2 = huart->RxState;
+
+ return (HAL_UART_StateTypeDef)(temp1 | temp2);
+}
+
+/**
+ * @brief Return the UART handle error code.
+ * @param huart Pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART.
+ * @retval UART Error Code
+ */
+uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart)
+{
+ return huart->ErrorCode;
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup UART_Private_Functions UART Private Functions
+ * @{
+ */
+
+/**
+ * @brief Initialize the callbacks to their default values.
+ * @param huart UART handle.
+ * @retval none
+ */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart)
+{
+ /* Init the UART Callback settings */
+ huart->TxHalfCpltCallback = HAL_UART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
+ huart->TxCpltCallback = HAL_UART_TxCpltCallback; /* Legacy weak TxCpltCallback */
+ huart->RxHalfCpltCallback = HAL_UART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
+ huart->RxCpltCallback = HAL_UART_RxCpltCallback; /* Legacy weak RxCpltCallback */
+ huart->ErrorCallback = HAL_UART_ErrorCallback; /* Legacy weak ErrorCallback */
+ huart->AbortCpltCallback = HAL_UART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
+ huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */
+ huart->AbortReceiveCpltCallback = HAL_UART_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */
+ huart->WakeupCallback = HAL_UARTEx_WakeupCallback; /* Legacy weak WakeupCallback */
+ huart->RxFifoFullCallback = HAL_UARTEx_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */
+ huart->TxFifoEmptyCallback = HAL_UARTEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */
+ huart->RxEventCallback = HAL_UARTEx_RxEventCallback; /* Legacy weak RxEventCallback */
+
+}
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+
+/**
+ * @brief Configure the UART peripheral.
+ * @param huart UART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
+{
+ uint32_t tmpreg;
+ uint16_t brrtemp;
+ UART_ClockSourceTypeDef clocksource;
+ uint32_t usartdiv;
+ HAL_StatusTypeDef ret = HAL_OK;
+ uint32_t pclk;
+
+ /* Check the parameters */
+ assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate));
+ assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
+ assert_param(IS_UART_STOPBITS(huart->Init.StopBits));
+ assert_param(IS_UART_ONE_BIT_SAMPLE(huart->Init.OneBitSampling));
+
+ assert_param(IS_UART_PARITY(huart->Init.Parity));
+ assert_param(IS_UART_MODE(huart->Init.Mode));
+ assert_param(IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl));
+ assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
+ assert_param(IS_UART_PRESCALER(huart->Init.ClockPrescaler));
+
+ /*-------------------------- USART CR1 Configuration -----------------------*/
+ /* Clear M, PCE, PS, TE, RE and OVER8 bits and configure
+ * the UART Word Length, Parity, Mode and oversampling:
+ * set the M bits according to huart->Init.WordLength value
+ * set PCE and PS bits according to huart->Init.Parity value
+ * set TE and RE bits according to huart->Init.Mode value
+ * set OVER8 bit according to huart->Init.OverSampling value */
+ tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
+ MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
+
+ /*-------------------------- USART CR2 Configuration -----------------------*/
+ /* Configure the UART Stop Bits: Set STOP[13:12] bits according
+ * to huart->Init.StopBits value */
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
+
+ /*-------------------------- USART CR3 Configuration -----------------------*/
+ /* Configure
+ * - UART HardWare Flow Control: set CTSE and RTSE bits according
+ * to huart->Init.HwFlowCtl value
+ * - one-bit sampling method versus three samples' majority rule according
+ * to huart->Init.OneBitSampling (not applicable to LPUART) */
+ tmpreg = (uint32_t)huart->Init.HwFlowCtl;
+
+ tmpreg |= huart->Init.OneBitSampling;
+ MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg);
+
+ /*-------------------------- USART PRESC Configuration -----------------------*/
+ /* Configure
+ * - UART Clock Prescaler : set PRESCALER according to huart->Init.ClockPrescaler value */
+ MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER, huart->Init.ClockPrescaler);
+
+ /*-------------------------- USART BRR Configuration -----------------------*/
+ UART_GETCLOCKSOURCE(huart, clocksource);
+
+ if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
+ {
+ switch (clocksource)
+ {
+ case UART_CLOCKSOURCE_PCLK1:
+ pclk = HAL_RCC_GetPCLK1Freq();
+ break;
+ case UART_CLOCKSOURCE_HSI:
+ pclk = (HSI_VALUE / ((__HAL_RCC_GET_HSIKER_DIVIDER() >> RCC_CR_HSIKERDIV_Pos) + 1U));
+ break;
+ case UART_CLOCKSOURCE_SYSCLK:
+ pclk = HAL_RCC_GetSysClockFreq();
+ break;
+ case UART_CLOCKSOURCE_LSE:
+ pclk = (uint32_t) LSE_VALUE;
+ break;
+ default:
+ pclk = 0U;
+ ret = HAL_ERROR;
+ break;
+ }
+
+ /* USARTDIV must be greater than or equal to 0d16 */
+ if (pclk != 0U)
+ {
+ usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
+ if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
+ {
+ brrtemp = (uint16_t)(usartdiv & 0xFFF0U);
+ brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
+ huart->Instance->BRR = brrtemp;
+ }
+ else
+ {
+ ret = HAL_ERROR;
+ }
+ }
+ }
+ else
+ {
+ switch (clocksource)
+ {
+ case UART_CLOCKSOURCE_PCLK1:
+ pclk = HAL_RCC_GetPCLK1Freq();
+ break;
+ case UART_CLOCKSOURCE_HSI:
+ pclk = (HSI_VALUE / ((__HAL_RCC_GET_HSIKER_DIVIDER() >> RCC_CR_HSIKERDIV_Pos) + 1U));
+ break;
+ case UART_CLOCKSOURCE_SYSCLK:
+ pclk = HAL_RCC_GetSysClockFreq();
+ break;
+ case UART_CLOCKSOURCE_LSE:
+ pclk = (uint32_t) LSE_VALUE;
+ break;
+ default:
+ pclk = 0U;
+ ret = HAL_ERROR;
+ break;
+ }
+
+ if (pclk != 0U)
+ {
+ /* USARTDIV must be greater than or equal to 0d16 */
+ usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
+ if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
+ {
+ huart->Instance->BRR = (uint16_t)usartdiv;
+ }
+ else
+ {
+ ret = HAL_ERROR;
+ }
+ }
+ }
+
+ /* Initialize the number of data to process during RX/TX ISR execution */
+ huart->NbTxDataToProcess = 1;
+ huart->NbRxDataToProcess = 1;
+
+ /* Clear ISR function pointers */
+ huart->RxISR = NULL;
+ huart->TxISR = NULL;
+
+ return ret;
+}
+
+/**
+ * @brief Configure the UART peripheral advanced features.
+ * @param huart UART handle.
+ * @retval None
+ */
+void UART_AdvFeatureConfig(UART_HandleTypeDef *huart)
+{
+ /* Check whether the set of advanced features to configure is properly set */
+ assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit));
+
+ /* if required, configure TX pin active level inversion */
+ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))
+ {
+ assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert));
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert);
+ }
+
+ /* if required, configure RX pin active level inversion */
+ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT))
+ {
+ assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert));
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert);
+ }
+
+ /* if required, configure data inversion */
+ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT))
+ {
+ assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert));
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert);
+ }
+
+ /* if required, configure RX/TX pins swap */
+ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
+ {
+ assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
+ }
+
+ /* if required, configure RX overrun detection disabling */
+ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))
+ {
+ assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable));
+ MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable);
+ }
+
+ /* if required, configure DMA disabling on reception error */
+ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT))
+ {
+ assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError));
+ MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError);
+ }
+
+ /* if required, configure auto Baud rate detection scheme */
+ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT))
+ {
+ assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance));
+ assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable));
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable);
+ /* set auto Baudrate detection parameters if detection is enabled */
+ if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)
+ {
+ assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode));
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode);
+ }
+ }
+
+ /* if required, configure MSB first on communication line */
+ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT))
+ {
+ assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst));
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst);
+ }
+}
+
+/**
+ * @brief Check the UART Idle State.
+ * @param huart UART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)
+{
+ uint32_t tickstart;
+
+ /* Initialize the UART ErrorCode */
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+
+ /* Init tickstart for timeout management */
+ tickstart = HAL_GetTick();
+
+ /* Check if the Transmitter is enabled */
+ if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
+ {
+ /* Wait until TEACK flag is set */
+ if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
+ {
+ /* Timeout occurred */
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Check if the Receiver is enabled */
+ if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
+ {
+ /* Wait until REACK flag is set */
+ if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
+ {
+ /* Timeout occurred */
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Initialize the UART State */
+ huart->gState = HAL_UART_STATE_READY;
+ huart->RxState = HAL_UART_STATE_READY;
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief This function handles UART Communication Timeout. It waits
+ * until a flag is no longer in the specified status.
+ * @param huart UART handle.
+ * @param Flag Specifies the UART flag to check
+ * @param Status The actual Flag status (SET or RESET)
+ * @param Tickstart Tick start value
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,
+ uint32_t Tickstart, uint32_t Timeout)
+{
+ /* Wait until flag is set */
+ while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
+ {
+ /* Check for the Timeout */
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
+ {
+ /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error)
+ interrupts for the interrupt process */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE |
+ USART_CR1_TXEIE_TXFNFIE));
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+ huart->gState = HAL_UART_STATE_READY;
+ huart->RxState = HAL_UART_STATE_READY;
+
+ __HAL_UNLOCK(huart);
+
+ return HAL_TIMEOUT;
+ }
+
+ if (READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U)
+ {
+ if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET)
+ {
+ /* Clear Receiver Timeout flag*/
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
+
+ /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error)
+ interrupts for the interrupt process */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE |
+ USART_CR1_TXEIE_TXFNFIE));
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+ huart->gState = HAL_UART_STATE_READY;
+ huart->RxState = HAL_UART_STATE_READY;
+ huart->ErrorCode = HAL_UART_ERROR_RTO;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief Start Receive operation in interrupt mode.
+ * @note This function could be called by all HAL UART API providing reception in Interrupt mode.
+ * @note When calling this function, parameters validity is considered as already checked,
+ * i.e. Rx State, buffer address, ...
+ * UART Handle is assumed as Locked.
+ * @param huart UART handle.
+ * @param pData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be received.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+{
+ huart->pRxBuffPtr = pData;
+ huart->RxXferSize = Size;
+ huart->RxXferCount = Size;
+ huart->RxISR = NULL;
+
+ /* Computation of UART mask to apply to RDR register */
+ UART_MASK_COMPUTATION(huart);
+
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+ huart->RxState = HAL_UART_STATE_BUSY_RX;
+
+ /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
+ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+ /* Configure Rx interrupt processing */
+ if ((huart->FifoMode == UART_FIFOMODE_ENABLE) && (Size >= huart->NbRxDataToProcess))
+ {
+ /* Set the Rx ISR function pointer according to the data word length */
+ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+ {
+ huart->RxISR = UART_RxISR_16BIT_FIFOEN;
+ }
+ else
+ {
+ huart->RxISR = UART_RxISR_8BIT_FIFOEN;
+ }
+
+ __HAL_UNLOCK(huart);
+
+ /* Enable the UART Parity Error interrupt and RX FIFO Threshold interrupt */
+ if (huart->Init.Parity != UART_PARITY_NONE)
+ {
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+ }
+ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
+ }
+ else
+ {
+ /* Set the Rx ISR function pointer according to the data word length */
+ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+ {
+ huart->RxISR = UART_RxISR_16BIT;
+ }
+ else
+ {
+ huart->RxISR = UART_RxISR_8BIT;
+ }
+
+ __HAL_UNLOCK(huart);
+
+ /* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */
+ if (huart->Init.Parity != UART_PARITY_NONE)
+ {
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE);
+ }
+ else
+ {
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief Start Receive operation in DMA mode.
+ * @note This function could be called by all HAL UART API providing reception in DMA mode.
+ * @note When calling this function, parameters validity is considered as already checked,
+ * i.e. Rx State, buffer address, ...
+ * UART Handle is assumed as Locked.
+ * @param huart UART handle.
+ * @param pData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be received.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+{
+ huart->pRxBuffPtr = pData;
+ huart->RxXferSize = Size;
+
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+ huart->RxState = HAL_UART_STATE_BUSY_RX;
+
+ if (huart->hdmarx != NULL)
+ {
+ /* Set the UART DMA transfer complete callback */
+ huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt;
+
+ /* Set the UART DMA Half transfer complete callback */
+ huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt;
+
+ /* Set the DMA error callback */
+ huart->hdmarx->XferErrorCallback = UART_DMAError;
+
+ /* Set the DMA abort callback */
+ huart->hdmarx->XferAbortCallback = NULL;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->RDR, (uint32_t)huart->pRxBuffPtr, Size) != HAL_OK)
+ {
+ /* Set error code to DMA */
+ huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+ __HAL_UNLOCK(huart);
+
+ /* Restore huart->RxState to ready */
+ huart->RxState = HAL_UART_STATE_READY;
+
+ return HAL_ERROR;
+ }
+ }
+ __HAL_UNLOCK(huart);
+
+ /* Enable the UART Parity Error Interrupt */
+ if (huart->Init.Parity != UART_PARITY_NONE)
+ {
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+ }
+
+ /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
+ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+ /* Enable the DMA transfer for the receiver request by setting the DMAR bit
+ in the UART CR3 register */
+ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion).
+ * @param huart UART handle.
+ * @retval None
+ */
+static void UART_EndTxTransfer(UART_HandleTypeDef *huart)
+{
+ /* Disable TXEIE, TCIE, TXFT interrupts */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_TXFTIE));
+
+ /* At end of Tx process, restore huart->gState to Ready */
+ huart->gState = HAL_UART_STATE_READY;
+}
+
+
+/**
+ * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
+ * @param huart UART handle.
+ * @retval None
+ */
+static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
+{
+ /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
+
+ /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */
+ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+ {
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+ }
+
+ /* At end of Rx process, restore huart->RxState to Ready */
+ huart->RxState = HAL_UART_STATE_READY;
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+ /* Reset RxIsr function pointer */
+ huart->RxISR = NULL;
+}
+
+
+/**
+ * @brief DMA UART transmit process complete callback.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
+{
+ UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+
+ /* DMA Normal mode */
+ if (HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC))
+ {
+ huart->TxXferCount = 0U;
+
+ /* Disable the DMA transfer for transmit request by resetting the DMAT bit
+ in the UART CR3 register */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+ /* Enable the UART Transmit Complete Interrupt */
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
+ }
+ /* DMA Circular mode */
+ else
+ {
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered Tx complete callback*/
+ huart->TxCpltCallback(huart);
+#else
+ /*Call legacy weak Tx complete callback*/
+ HAL_UART_TxCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ }
+}
+
+/**
+ * @brief DMA UART transmit process half complete callback.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+ UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered Tx Half complete callback*/
+ huart->TxHalfCpltCallback(huart);
+#else
+ /*Call legacy weak Tx Half complete callback*/
+ HAL_UART_TxHalfCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief DMA UART receive process complete callback.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+ UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+
+ /* DMA Normal mode */
+ if (HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC))
+ {
+ huart->RxXferCount = 0U;
+
+ /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+ /* Disable the DMA transfer for the receiver request by resetting the DMAR bit
+ in the UART CR3 register */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+ /* At end of Rx process, restore huart->RxState to Ready */
+ huart->RxState = HAL_UART_STATE_READY;
+
+ /* If Reception till IDLE event has been selected, Disable IDLE Interrupt */
+ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+ {
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+ }
+ }
+
+ /* Check current reception Mode :
+ If Reception till IDLE event has been selected : use Rx Event callback */
+ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+ {
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered Rx Event callback*/
+ huart->RxEventCallback(huart, huart->RxXferSize);
+#else
+ /*Call legacy weak Rx Event callback*/
+ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ }
+ else
+ {
+ /* In other cases : use Rx Complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered Rx complete callback*/
+ huart->RxCpltCallback(huart);
+#else
+ /*Call legacy weak Rx complete callback*/
+ HAL_UART_RxCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ }
+}
+
+/**
+ * @brief DMA UART receive process half complete callback.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+ UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+
+ /* Check current reception Mode :
+ If Reception till IDLE event has been selected : use Rx Event callback */
+ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+ {
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered Rx Event callback*/
+ huart->RxEventCallback(huart, huart->RxXferSize / 2U);
+#else
+ /*Call legacy weak Rx Event callback*/
+ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize / 2U);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ }
+ else
+ {
+ /* In other cases : use Rx Half Complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered Rx Half complete callback*/
+ huart->RxHalfCpltCallback(huart);
+#else
+ /*Call legacy weak Rx Half complete callback*/
+ HAL_UART_RxHalfCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ }
+}
+
+/**
+ * @brief DMA UART communication error callback.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void UART_DMAError(DMA_HandleTypeDef *hdma)
+{
+ UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+
+ const HAL_UART_StateTypeDef gstate = huart->gState;
+ const HAL_UART_StateTypeDef rxstate = huart->RxState;
+
+ /* Stop UART DMA Tx request if ongoing */
+ if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) &&
+ (gstate == HAL_UART_STATE_BUSY_TX))
+ {
+ huart->TxXferCount = 0U;
+ UART_EndTxTransfer(huart);
+ }
+
+ /* Stop UART DMA Rx request if ongoing */
+ if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) &&
+ (rxstate == HAL_UART_STATE_BUSY_RX))
+ {
+ huart->RxXferCount = 0U;
+ UART_EndRxTransfer(huart);
+ }
+
+ huart->ErrorCode |= HAL_UART_ERROR_DMA;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered error callback*/
+ huart->ErrorCallback(huart);
+#else
+ /*Call legacy weak error callback*/
+ HAL_UART_ErrorCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief DMA UART communication abort callback, when initiated by HAL services on Error
+ * (To be called at end of DMA Abort procedure following error occurrence).
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
+{
+ UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+ huart->RxXferCount = 0U;
+ huart->TxXferCount = 0U;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered error callback*/
+ huart->ErrorCallback(huart);
+#else
+ /*Call legacy weak error callback*/
+ HAL_UART_ErrorCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief DMA UART Tx communication abort callback, when initiated by user
+ * (To be called at end of DMA Tx Abort procedure following user abort request).
+ * @note When this callback is executed, User Abort complete call back is called only if no
+ * Abort still ongoing for Rx DMA Handle.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+
+ huart->hdmatx->XferAbortCallback = NULL;
+
+ /* Check if an Abort process is still ongoing */
+ if (huart->hdmarx != NULL)
+ {
+ if (huart->hdmarx->XferAbortCallback != NULL)
+ {
+ return;
+ }
+ }
+
+ /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
+ huart->TxXferCount = 0U;
+ huart->RxXferCount = 0U;
+
+ /* Reset errorCode */
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+
+ /* Flush the whole TX FIFO (if needed) */
+ if (huart->FifoMode == UART_FIFOMODE_ENABLE)
+ {
+ __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST);
+ }
+
+ /* Restore huart->gState and huart->RxState to Ready */
+ huart->gState = HAL_UART_STATE_READY;
+ huart->RxState = HAL_UART_STATE_READY;
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+ /* Call user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort complete callback */
+ huart->AbortCpltCallback(huart);
+#else
+ /* Call legacy weak Abort complete callback */
+ HAL_UART_AbortCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+
+
+/**
+ * @brief DMA UART Rx communication abort callback, when initiated by user
+ * (To be called at end of DMA Rx Abort procedure following user abort request).
+ * @note When this callback is executed, User Abort complete call back is called only if no
+ * Abort still ongoing for Tx DMA Handle.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+
+ huart->hdmarx->XferAbortCallback = NULL;
+
+ /* Check if an Abort process is still ongoing */
+ if (huart->hdmatx != NULL)
+ {
+ if (huart->hdmatx->XferAbortCallback != NULL)
+ {
+ return;
+ }
+ }
+
+ /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
+ huart->TxXferCount = 0U;
+ huart->RxXferCount = 0U;
+
+ /* Reset errorCode */
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+
+ /* Discard the received data */
+ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+
+ /* Restore huart->gState and huart->RxState to Ready */
+ huart->gState = HAL_UART_STATE_READY;
+ huart->RxState = HAL_UART_STATE_READY;
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+ /* Call user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort complete callback */
+ huart->AbortCpltCallback(huart);
+#else
+ /* Call legacy weak Abort complete callback */
+ HAL_UART_AbortCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+
+
+/**
+ * @brief DMA UART Tx communication abort callback, when initiated by user by a call to
+ * HAL_UART_AbortTransmit_IT API (Abort only Tx transfer)
+ * (This callback is executed at end of DMA Tx Abort procedure following user abort request,
+ * and leads to user Tx Abort Complete callback execution).
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+
+ huart->TxXferCount = 0U;
+
+ /* Flush the whole TX FIFO (if needed) */
+ if (huart->FifoMode == UART_FIFOMODE_ENABLE)
+ {
+ __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST);
+ }
+
+ /* Restore huart->gState to Ready */
+ huart->gState = HAL_UART_STATE_READY;
+
+ /* Call user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Transmit Complete Callback */
+ huart->AbortTransmitCpltCallback(huart);
+#else
+ /* Call legacy weak Abort Transmit Complete Callback */
+ HAL_UART_AbortTransmitCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief DMA UART Rx communication abort callback, when initiated by user by a call to
+ * HAL_UART_AbortReceive_IT API (Abort only Rx transfer)
+ * (This callback is executed at end of DMA Rx Abort procedure following user abort request,
+ * and leads to user Rx Abort Complete callback execution).
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ huart->RxXferCount = 0U;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+
+ /* Discard the received data */
+ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+
+ /* Restore huart->RxState to Ready */
+ huart->RxState = HAL_UART_STATE_READY;
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+ /* Call user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Receive Complete Callback */
+ huart->AbortReceiveCpltCallback(huart);
+#else
+ /* Call legacy weak Abort Receive Complete Callback */
+ HAL_UART_AbortReceiveCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief TX interrupt handler for 7 or 8 bits data word length .
+ * @note Function is called under interruption only, once
+ * interruptions have been enabled by HAL_UART_Transmit_IT().
+ * @param huart UART handle.
+ * @retval None
+ */
+static void UART_TxISR_8BIT(UART_HandleTypeDef *huart)
+{
+ /* Check that a Tx process is ongoing */
+ if (huart->gState == HAL_UART_STATE_BUSY_TX)
+ {
+ if (huart->TxXferCount == 0U)
+ {
+ /* Disable the UART Transmit Data Register Empty Interrupt */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
+
+ /* Enable the UART Transmit Complete Interrupt */
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
+ }
+ else
+ {
+ huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF);
+ huart->pTxBuffPtr++;
+ huart->TxXferCount--;
+ }
+ }
+}
+
+/**
+ * @brief TX interrupt handler for 9 bits data word length.
+ * @note Function is called under interruption only, once
+ * interruptions have been enabled by HAL_UART_Transmit_IT().
+ * @param huart UART handle.
+ * @retval None
+ */
+static void UART_TxISR_16BIT(UART_HandleTypeDef *huart)
+{
+ const uint16_t *tmp;
+
+ /* Check that a Tx process is ongoing */
+ if (huart->gState == HAL_UART_STATE_BUSY_TX)
+ {
+ if (huart->TxXferCount == 0U)
+ {
+ /* Disable the UART Transmit Data Register Empty Interrupt */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
+
+ /* Enable the UART Transmit Complete Interrupt */
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
+ }
+ else
+ {
+ tmp = (const uint16_t *) huart->pTxBuffPtr;
+ huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL);
+ huart->pTxBuffPtr += 2U;
+ huart->TxXferCount--;
+ }
+ }
+}
+
+/**
+ * @brief TX interrupt handler for 7 or 8 bits data word length and FIFO mode is enabled.
+ * @note Function is called under interruption only, once
+ * interruptions have been enabled by HAL_UART_Transmit_IT().
+ * @param huart UART handle.
+ * @retval None
+ */
+static void UART_TxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart)
+{
+ uint16_t nb_tx_data;
+
+ /* Check that a Tx process is ongoing */
+ if (huart->gState == HAL_UART_STATE_BUSY_TX)
+ {
+ for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--)
+ {
+ if (huart->TxXferCount == 0U)
+ {
+ /* Disable the TX FIFO threshold interrupt */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
+
+ /* Enable the UART Transmit Complete Interrupt */
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
+
+ break; /* force exit loop */
+ }
+ else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != 0U)
+ {
+ huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF);
+ huart->pTxBuffPtr++;
+ huart->TxXferCount--;
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+ }
+ }
+}
+
+/**
+ * @brief TX interrupt handler for 9 bits data word length and FIFO mode is enabled.
+ * @note Function is called under interruption only, once
+ * interruptions have been enabled by HAL_UART_Transmit_IT().
+ * @param huart UART handle.
+ * @retval None
+ */
+static void UART_TxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart)
+{
+ const uint16_t *tmp;
+ uint16_t nb_tx_data;
+
+ /* Check that a Tx process is ongoing */
+ if (huart->gState == HAL_UART_STATE_BUSY_TX)
+ {
+ for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--)
+ {
+ if (huart->TxXferCount == 0U)
+ {
+ /* Disable the TX FIFO threshold interrupt */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
+
+ /* Enable the UART Transmit Complete Interrupt */
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
+
+ break; /* force exit loop */
+ }
+ else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != 0U)
+ {
+ tmp = (const uint16_t *) huart->pTxBuffPtr;
+ huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL);
+ huart->pTxBuffPtr += 2U;
+ huart->TxXferCount--;
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+ }
+ }
+}
+
+/**
+ * @brief Wrap up transmission in non-blocking mode.
+ * @param huart pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @retval None
+ */
+static void UART_EndTransmit_IT(UART_HandleTypeDef *huart)
+{
+ /* Disable the UART Transmit Complete Interrupt */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE);
+
+ /* Tx process is ended, restore huart->gState to Ready */
+ huart->gState = HAL_UART_STATE_READY;
+
+ /* Cleat TxISR function pointer */
+ huart->TxISR = NULL;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered Tx complete callback*/
+ huart->TxCpltCallback(huart);
+#else
+ /*Call legacy weak Tx complete callback*/
+ HAL_UART_TxCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief RX interrupt handler for 7 or 8 bits data word length .
+ * @param huart UART handle.
+ * @retval None
+ */
+static void UART_RxISR_8BIT(UART_HandleTypeDef *huart)
+{
+ uint16_t uhMask = huart->Mask;
+ uint16_t uhdata;
+
+ /* Check that a Rx process is ongoing */
+ if (huart->RxState == HAL_UART_STATE_BUSY_RX)
+ {
+ uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
+ *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask);
+ huart->pRxBuffPtr++;
+ huart->RxXferCount--;
+
+ if (huart->RxXferCount == 0U)
+ {
+ /* Disable the UART Parity Error Interrupt and RXNE interrupts */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
+
+ /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+ /* Rx process is completed, restore huart->RxState to Ready */
+ huart->RxState = HAL_UART_STATE_READY;
+
+ /* Clear RxISR function pointer */
+ huart->RxISR = NULL;
+
+ /* Check current reception Mode :
+ If Reception till IDLE event has been selected : */
+ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+ {
+ /* Set reception type to Standard */
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+ /* Disable IDLE interrupt */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+
+ if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET)
+ {
+ /* Clear IDLE Flag */
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
+ }
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered Rx Event callback*/
+ huart->RxEventCallback(huart, huart->RxXferSize);
+#else
+ /*Call legacy weak Rx Event callback*/
+ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+ }
+ else
+ {
+ /* Standard reception API called */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered Rx complete callback*/
+ huart->RxCpltCallback(huart);
+#else
+ /*Call legacy weak Rx complete callback*/
+ HAL_UART_RxCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ }
+ }
+ }
+ else
+ {
+ /* Clear RXNE interrupt flag */
+ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+ }
+}
+
+/**
+ * @brief RX interrupt handler for 9 bits data word length .
+ * @note Function is called under interruption only, once
+ * interruptions have been enabled by HAL_UART_Receive_IT()
+ * @param huart UART handle.
+ * @retval None
+ */
+static void UART_RxISR_16BIT(UART_HandleTypeDef *huart)
+{
+ uint16_t *tmp;
+ uint16_t uhMask = huart->Mask;
+ uint16_t uhdata;
+
+ /* Check that a Rx process is ongoing */
+ if (huart->RxState == HAL_UART_STATE_BUSY_RX)
+ {
+ uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
+ tmp = (uint16_t *) huart->pRxBuffPtr ;
+ *tmp = (uint16_t)(uhdata & uhMask);
+ huart->pRxBuffPtr += 2U;
+ huart->RxXferCount--;
+
+ if (huart->RxXferCount == 0U)
+ {
+ /* Disable the UART Parity Error Interrupt and RXNE interrupt*/
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
+
+ /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+ /* Rx process is completed, restore huart->RxState to Ready */
+ huart->RxState = HAL_UART_STATE_READY;
+
+ /* Clear RxISR function pointer */
+ huart->RxISR = NULL;
+
+ /* Check current reception Mode :
+ If Reception till IDLE event has been selected : */
+ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+ {
+ /* Set reception type to Standard */
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+ /* Disable IDLE interrupt */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+
+ if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET)
+ {
+ /* Clear IDLE Flag */
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
+ }
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered Rx Event callback*/
+ huart->RxEventCallback(huart, huart->RxXferSize);
+#else
+ /*Call legacy weak Rx Event callback*/
+ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+ }
+ else
+ {
+ /* Standard reception API called */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered Rx complete callback*/
+ huart->RxCpltCallback(huart);
+#else
+ /*Call legacy weak Rx complete callback*/
+ HAL_UART_RxCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ }
+ }
+ }
+ else
+ {
+ /* Clear RXNE interrupt flag */
+ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+ }
+}
+
+/**
+ * @brief RX interrupt handler for 7 or 8 bits data word length and FIFO mode is enabled.
+ * @note Function is called under interruption only, once
+ * interruptions have been enabled by HAL_UART_Receive_IT()
+ * @param huart UART handle.
+ * @retval None
+ */
+static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart)
+{
+ uint16_t uhMask = huart->Mask;
+ uint16_t uhdata;
+ uint16_t nb_rx_data;
+ uint16_t rxdatacount;
+ uint32_t isrflags = READ_REG(huart->Instance->ISR);
+ uint32_t cr1its = READ_REG(huart->Instance->CR1);
+ uint32_t cr3its = READ_REG(huart->Instance->CR3);
+
+ /* Check that a Rx process is ongoing */
+ if (huart->RxState == HAL_UART_STATE_BUSY_RX)
+ {
+ nb_rx_data = huart->NbRxDataToProcess;
+ while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U))
+ {
+ uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
+ *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask);
+ huart->pRxBuffPtr++;
+ huart->RxXferCount--;
+ isrflags = READ_REG(huart->Instance->ISR);
+
+ /* If some non blocking errors occurred */
+ if ((isrflags & (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE)) != 0U)
+ {
+ /* UART parity error interrupt occurred -------------------------------------*/
+ if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
+ {
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF);
+
+ huart->ErrorCode |= HAL_UART_ERROR_PE;
+ }
+
+ /* UART frame error interrupt occurred --------------------------------------*/
+ if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
+ {
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF);
+
+ huart->ErrorCode |= HAL_UART_ERROR_FE;
+ }
+
+ /* UART noise error interrupt occurred --------------------------------------*/
+ if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
+ {
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF);
+
+ huart->ErrorCode |= HAL_UART_ERROR_NE;
+ }
+
+ /* Call UART Error Call back function if need be ----------------------------*/
+ if (huart->ErrorCode != HAL_UART_ERROR_NONE)
+ {
+ /* Non Blocking error : transfer could go on.
+ Error is notified to user through user error callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered error callback*/
+ huart->ErrorCallback(huart);
+#else
+ /*Call legacy weak error callback*/
+ HAL_UART_ErrorCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+ }
+ }
+
+ if (huart->RxXferCount == 0U)
+ {
+ /* Disable the UART Parity Error Interrupt and RXFT interrupt*/
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+
+ /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error)
+ and RX FIFO Threshold interrupt */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
+
+ /* Rx process is completed, restore huart->RxState to Ready */
+ huart->RxState = HAL_UART_STATE_READY;
+
+ /* Clear RxISR function pointer */
+ huart->RxISR = NULL;
+
+ /* Check current reception Mode :
+ If Reception till IDLE event has been selected : */
+ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+ {
+ /* Set reception type to Standard */
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+ /* Disable IDLE interrupt */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+
+ if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET)
+ {
+ /* Clear IDLE Flag */
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
+ }
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered Rx Event callback*/
+ huart->RxEventCallback(huart, huart->RxXferSize);
+#else
+ /*Call legacy weak Rx Event callback*/
+ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+ }
+ else
+ {
+ /* Standard reception API called */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered Rx complete callback*/
+ huart->RxCpltCallback(huart);
+#else
+ /*Call legacy weak Rx complete callback*/
+ HAL_UART_RxCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ }
+ }
+ }
+
+ /* When remaining number of bytes to receive is less than the RX FIFO
+ threshold, next incoming frames are processed as if FIFO mode was
+ disabled (i.e. one interrupt per received frame).
+ */
+ rxdatacount = huart->RxXferCount;
+ if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess))
+ {
+ /* Disable the UART RXFT interrupt*/
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
+
+ /* Update the RxISR function pointer */
+ huart->RxISR = UART_RxISR_8BIT;
+
+ /* Enable the UART Data Register Not Empty interrupt */
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
+ }
+ }
+ else
+ {
+ /* Clear RXNE interrupt flag */
+ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+ }
+}
+
+/**
+ * @brief RX interrupt handler for 9 bits data word length and FIFO mode is enabled.
+ * @note Function is called under interruption only, once
+ * interruptions have been enabled by HAL_UART_Receive_IT()
+ * @param huart UART handle.
+ * @retval None
+ */
+static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart)
+{
+ uint16_t *tmp;
+ uint16_t uhMask = huart->Mask;
+ uint16_t uhdata;
+ uint16_t nb_rx_data;
+ uint16_t rxdatacount;
+ uint32_t isrflags = READ_REG(huart->Instance->ISR);
+ uint32_t cr1its = READ_REG(huart->Instance->CR1);
+ uint32_t cr3its = READ_REG(huart->Instance->CR3);
+
+ /* Check that a Rx process is ongoing */
+ if (huart->RxState == HAL_UART_STATE_BUSY_RX)
+ {
+ nb_rx_data = huart->NbRxDataToProcess;
+ while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U))
+ {
+ uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
+ tmp = (uint16_t *) huart->pRxBuffPtr ;
+ *tmp = (uint16_t)(uhdata & uhMask);
+ huart->pRxBuffPtr += 2U;
+ huart->RxXferCount--;
+ isrflags = READ_REG(huart->Instance->ISR);
+
+ /* If some non blocking errors occurred */
+ if ((isrflags & (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE)) != 0U)
+ {
+ /* UART parity error interrupt occurred -------------------------------------*/
+ if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
+ {
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF);
+
+ huart->ErrorCode |= HAL_UART_ERROR_PE;
+ }
+
+ /* UART frame error interrupt occurred --------------------------------------*/
+ if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
+ {
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF);
+
+ huart->ErrorCode |= HAL_UART_ERROR_FE;
+ }
+
+ /* UART noise error interrupt occurred --------------------------------------*/
+ if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
+ {
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF);
+
+ huart->ErrorCode |= HAL_UART_ERROR_NE;
+ }
+
+ /* Call UART Error Call back function if need be ----------------------------*/
+ if (huart->ErrorCode != HAL_UART_ERROR_NONE)
+ {
+ /* Non Blocking error : transfer could go on.
+ Error is notified to user through user error callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered error callback*/
+ huart->ErrorCallback(huart);
+#else
+ /*Call legacy weak error callback*/
+ HAL_UART_ErrorCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+ }
+ }
+
+ if (huart->RxXferCount == 0U)
+ {
+ /* Disable the UART Parity Error Interrupt and RXFT interrupt*/
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+
+ /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error)
+ and RX FIFO Threshold interrupt */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
+
+ /* Rx process is completed, restore huart->RxState to Ready */
+ huart->RxState = HAL_UART_STATE_READY;
+
+ /* Clear RxISR function pointer */
+ huart->RxISR = NULL;
+
+ /* Check current reception Mode :
+ If Reception till IDLE event has been selected : */
+ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+ {
+ /* Set reception type to Standard */
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+ /* Disable IDLE interrupt */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+
+ if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET)
+ {
+ /* Clear IDLE Flag */
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
+ }
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered Rx Event callback*/
+ huart->RxEventCallback(huart, huart->RxXferSize);
+#else
+ /*Call legacy weak Rx Event callback*/
+ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+ }
+ else
+ {
+ /* Standard reception API called */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered Rx complete callback*/
+ huart->RxCpltCallback(huart);
+#else
+ /*Call legacy weak Rx complete callback*/
+ HAL_UART_RxCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ }
+ }
+ }
+
+ /* When remaining number of bytes to receive is less than the RX FIFO
+ threshold, next incoming frames are processed as if FIFO mode was
+ disabled (i.e. one interrupt per received frame).
+ */
+ rxdatacount = huart->RxXferCount;
+ if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess))
+ {
+ /* Disable the UART RXFT interrupt*/
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
+
+ /* Update the RxISR function pointer */
+ huart->RxISR = UART_RxISR_16BIT;
+
+ /* Enable the UART Data Register Not Empty interrupt */
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
+ }
+ }
+ else
+ {
+ /* Clear RXNE interrupt flag */
+ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+ }
+}
+
+/**
+ * @}
+ */
+
+#endif /* HAL_UART_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c
new file mode 100644
index 0000000000..c1c7c9317e
--- /dev/null
+++ b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c
@@ -0,0 +1,1065 @@
+/**
+ ******************************************************************************
+ * @file stm32c0xx_hal_uart_ex.c
+ * @author MCD Application Team
+ * @brief Extended UART HAL module driver.
+ * This file provides firmware functions to manage the following extended
+ * functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART).
+ * + Initialization and de-initialization functions
+ * + Peripheral Control functions
+ *
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2022 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### UART peripheral extended features #####
+ ==============================================================================
+
+ (#) Declare a UART_HandleTypeDef handle structure.
+
+ (#) For the UART RS485 Driver Enable mode, initialize the UART registers
+ by calling the HAL_RS485Ex_Init() API.
+
+ (#) FIFO mode enabling/disabling and RX/TX FIFO threshold programming.
+
+ -@- When UART operates in FIFO mode, FIFO mode must be enabled prior
+ starting RX/TX transfers. Also RX/TX FIFO thresholds must be
+ configured prior starting RX/TX transfers.
+
+ @endverbatim
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32c0xx_hal.h"
+
+/** @addtogroup STM32C0xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup UARTEx UARTEx
+ * @brief UART Extended HAL module driver
+ * @{
+ */
+
+#ifdef HAL_UART_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup UARTEX_Private_Constants UARTEx Private Constants
+ * @{
+ */
+/* UART RX FIFO depth */
+#define RX_FIFO_DEPTH 8U
+
+/* UART TX FIFO depth */
+#define TX_FIFO_DEPTH 8U
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup UARTEx_Private_Functions UARTEx Private Functions
+ * @{
+ */
+static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection);
+static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart);
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup UARTEx_Exported_Functions UARTEx Exported Functions
+ * @{
+ */
+
+/** @defgroup UARTEx_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Extended Initialization and Configuration Functions
+ *
+@verbatim
+===============================================================================
+ ##### Initialization and Configuration functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
+ in asynchronous mode.
+ (+) For the asynchronous mode the parameters below can be configured:
+ (++) Baud Rate
+ (++) Word Length
+ (++) Stop Bit
+ (++) Parity: If the parity is enabled, then the MSB bit of the data written
+ in the data register is transmitted but is changed by the parity bit.
+ (++) Hardware flow control
+ (++) Receiver/transmitter modes
+ (++) Over Sampling Method
+ (++) One-Bit Sampling Method
+ (+) For the asynchronous mode, the following advanced features can be configured as well:
+ (++) TX and/or RX pin level inversion
+ (++) data logical level inversion
+ (++) RX and TX pins swap
+ (++) RX overrun detection disabling
+ (++) DMA disabling on RX error
+ (++) MSB first on communication line
+ (++) auto Baud rate detection
+ [..]
+ The HAL_RS485Ex_Init() API follows the UART RS485 mode configuration
+ procedures (details for the procedures are available in reference manual).
+
+@endverbatim
+
+ Depending on the frame length defined by the M1 and M0 bits (7-bit,
+ 8-bit or 9-bit), the possible UART formats are listed in the
+ following table.
+
+ Table 1. UART frame format.
+ +-----------------------------------------------------------------------+
+ | M1 bit | M0 bit | PCE bit | UART frame |
+ |---------|---------|-----------|---------------------------------------|
+ | 0 | 0 | 0 | | SB | 8 bit data | STB | |
+ |---------|---------|-----------|---------------------------------------|
+ | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | |
+ |---------|---------|-----------|---------------------------------------|
+ | 0 | 1 | 0 | | SB | 9 bit data | STB | |
+ |---------|---------|-----------|---------------------------------------|
+ | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | |
+ |---------|---------|-----------|---------------------------------------|
+ | 1 | 0 | 0 | | SB | 7 bit data | STB | |
+ |---------|---------|-----------|---------------------------------------|
+ | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | |
+ +-----------------------------------------------------------------------+
+
+ * @{
+ */
+
+/**
+ * @brief Initialize the RS485 Driver enable feature according to the specified
+ * parameters in the UART_InitTypeDef and creates the associated handle.
+ * @param huart UART handle.
+ * @param Polarity Select the driver enable polarity.
+ * This parameter can be one of the following values:
+ * @arg @ref UART_DE_POLARITY_HIGH DE signal is active high
+ * @arg @ref UART_DE_POLARITY_LOW DE signal is active low
+ * @param AssertionTime Driver Enable assertion time:
+ * 5-bit value defining the time between the activation of the DE (Driver Enable)
+ * signal and the beginning of the start bit. It is expressed in sample time
+ * units (1/8 or 1/16 bit time, depending on the oversampling rate)
+ * @param DeassertionTime Driver Enable deassertion time:
+ * 5-bit value defining the time between the end of the last stop bit, in a
+ * transmitted message, and the de-activation of the DE (Driver Enable) signal.
+ * It is expressed in sample time units (1/8 or 1/16 bit time, depending on the
+ * oversampling rate).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime,
+ uint32_t DeassertionTime)
+{
+ uint32_t temp;
+
+ /* Check the UART handle allocation */
+ if (huart == NULL)
+ {
+ return HAL_ERROR;
+ }
+ /* Check the Driver Enable UART instance */
+ assert_param(IS_UART_DRIVER_ENABLE_INSTANCE(huart->Instance));
+
+ /* Check the Driver Enable polarity */
+ assert_param(IS_UART_DE_POLARITY(Polarity));
+
+ /* Check the Driver Enable assertion time */
+ assert_param(IS_UART_ASSERTIONTIME(AssertionTime));
+
+ /* Check the Driver Enable deassertion time */
+ assert_param(IS_UART_DEASSERTIONTIME(DeassertionTime));
+
+ if (huart->gState == HAL_UART_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ huart->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ UART_InitCallbacksToDefault(huart);
+
+ if (huart->MspInitCallback == NULL)
+ {
+ huart->MspInitCallback = HAL_UART_MspInit;
+ }
+
+ /* Init the low level hardware */
+ huart->MspInitCallback(huart);
+#else
+ /* Init the low level hardware : GPIO, CLOCK, CORTEX */
+ HAL_UART_MspInit(huart);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+ }
+
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ /* Disable the Peripheral */
+ __HAL_UART_DISABLE(huart);
+
+ /* Set the UART Communication parameters */
+ if (UART_SetConfig(huart) == HAL_ERROR)
+ {
+ return HAL_ERROR;
+ }
+
+ if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
+ {
+ UART_AdvFeatureConfig(huart);
+ }
+
+ /* Enable the Driver Enable mode by setting the DEM bit in the CR3 register */
+ SET_BIT(huart->Instance->CR3, USART_CR3_DEM);
+
+ /* Set the Driver Enable polarity */
+ MODIFY_REG(huart->Instance->CR3, USART_CR3_DEP, Polarity);
+
+ /* Set the Driver Enable assertion and deassertion times */
+ temp = (AssertionTime << UART_CR1_DEAT_ADDRESS_LSB_POS);
+ temp |= (DeassertionTime << UART_CR1_DEDT_ADDRESS_LSB_POS);
+ MODIFY_REG(huart->Instance->CR1, (USART_CR1_DEDT | USART_CR1_DEAT), temp);
+
+ /* Enable the Peripheral */
+ __HAL_UART_ENABLE(huart);
+
+ /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
+ return (UART_CheckIdleState(huart));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup UARTEx_Exported_Functions_Group2 IO operation functions
+ * @brief Extended functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ This subsection provides a set of Wakeup and FIFO mode related callback functions.
+
+ (#) Wakeup from Stop mode Callback:
+ (+) HAL_UARTEx_WakeupCallback()
+
+ (#) TX/RX Fifos Callbacks:
+ (+) HAL_UARTEx_RxFifoFullCallback()
+ (+) HAL_UARTEx_TxFifoEmptyCallback()
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief UART wakeup from Stop mode callback.
+ * @param huart UART handle.
+ * @retval None
+ */
+__weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(huart);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_UARTEx_WakeupCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief UART RX Fifo full callback.
+ * @param huart UART handle.
+ * @retval None
+ */
+__weak void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(huart);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_UARTEx_RxFifoFullCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief UART TX Fifo empty callback.
+ * @param huart UART handle.
+ * @retval None
+ */
+__weak void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(huart);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_UARTEx_TxFifoEmptyCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup UARTEx_Exported_Functions_Group3 Peripheral Control functions
+ * @brief Extended Peripheral Control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..] This section provides the following functions:
+ (+) HAL_MultiProcessorEx_AddressLength_Set() API optionally sets the UART node address
+ detection length to more than 4 bits for multiprocessor address mark wake up.
+ (+) HAL_UARTEx_StopModeWakeUpSourceConfig() API defines the wake-up from stop mode
+ trigger: address match, Start Bit detection or RXNE bit status.
+ (+) HAL_UARTEx_EnableStopMode() API enables the UART to wake up the MCU from stop mode
+ (+) HAL_UARTEx_DisableStopMode() API disables the above functionality
+ (+) HAL_UARTEx_EnableFifoMode() API enables the FIFO mode
+ (+) HAL_UARTEx_DisableFifoMode() API disables the FIFO mode
+ (+) HAL_UARTEx_SetTxFifoThreshold() API sets the TX FIFO threshold
+ (+) HAL_UARTEx_SetRxFifoThreshold() API sets the RX FIFO threshold
+
+ [..] This subsection also provides a set of additional functions providing enhanced reception
+ services to user. (For example, these functions allow application to handle use cases
+ where number of data to be received is unknown).
+
+ (#) Compared to standard reception services which only consider number of received
+ data elements as reception completion criteria, these functions also consider additional events
+ as triggers for updating reception status to caller :
+ (+) Detection of inactivity period (RX line has not been active for a given period).
+ (++) RX inactivity detected by IDLE event, i.e. RX line has been in idle state (normally high state)
+ for 1 frame time, after last received byte.
+ (++) RX inactivity detected by RTO, i.e. line has been in idle state
+ for a programmable time, after last received byte.
+ (+) Detection that a specific character has been received.
+
+ (#) There are two mode of transfer:
+ (+) Blocking mode: The reception is performed in polling mode, until either expected number of data is received,
+ or till IDLE event occurs. Reception is handled only during function execution.
+ When function exits, no data reception could occur. HAL status and number of actually received data elements,
+ are returned by function after finishing transfer.
+ (+) Non-Blocking mode: The reception is performed using Interrupts or DMA.
+ These API's return the HAL status.
+ The end of the data processing will be indicated through the
+ dedicated UART IRQ when using Interrupt mode or the DMA IRQ when using DMA mode.
+ The HAL_UARTEx_RxEventCallback() user callback will be executed during Receive process
+ The HAL_UART_ErrorCallback()user callback will be executed when a reception error is detected.
+
+ (#) Blocking mode API:
+ (+) HAL_UARTEx_ReceiveToIdle()
+
+ (#) Non-Blocking mode API with Interrupt:
+ (+) HAL_UARTEx_ReceiveToIdle_IT()
+
+ (#) Non-Blocking mode API with DMA:
+ (+) HAL_UARTEx_ReceiveToIdle_DMA()
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief By default in multiprocessor mode, when the wake up method is set
+ * to address mark, the UART handles only 4-bit long addresses detection;
+ * this API allows to enable longer addresses detection (6-, 7- or 8-bit
+ * long).
+ * @note Addresses detection lengths are: 6-bit address detection in 7-bit data mode,
+ * 7-bit address detection in 8-bit data mode, 8-bit address detection in 9-bit data mode.
+ * @param huart UART handle.
+ * @param AddressLength This parameter can be one of the following values:
+ * @arg @ref UART_ADDRESS_DETECT_4B 4-bit long address
+ * @arg @ref UART_ADDRESS_DETECT_7B 6-, 7- or 8-bit long address
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength)
+{
+ /* Check the UART handle allocation */
+ if (huart == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the address length parameter */
+ assert_param(IS_UART_ADDRESSLENGTH_DETECT(AddressLength));
+
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ /* Disable the Peripheral */
+ __HAL_UART_DISABLE(huart);
+
+ /* Set the address length */
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, AddressLength);
+
+ /* Enable the Peripheral */
+ __HAL_UART_ENABLE(huart);
+
+ /* TEACK and/or REACK to check before moving huart->gState to Ready */
+ return (UART_CheckIdleState(huart));
+}
+
+/**
+ * @brief Set Wakeup from Stop mode interrupt flag selection.
+ * @note It is the application responsibility to enable the interrupt used as
+ * usart_wkup interrupt source before entering low-power mode.
+ * @param huart UART handle.
+ * @param WakeUpSelection Address match, Start Bit detection or RXNE/RXFNE bit status.
+ * This parameter can be one of the following values:
+ * @arg @ref UART_WAKEUP_ON_ADDRESS
+ * @arg @ref UART_WAKEUP_ON_STARTBIT
+ * @arg @ref UART_WAKEUP_ON_READDATA_NONEMPTY
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t tickstart;
+
+ /* check the wake-up from stop mode UART instance */
+ assert_param(IS_UART_WAKEUP_FROMSTOP_INSTANCE(huart->Instance));
+ /* check the wake-up selection parameter */
+ assert_param(IS_UART_WAKEUP_SELECTION(WakeUpSelection.WakeUpEvent));
+
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ /* Disable the Peripheral */
+ __HAL_UART_DISABLE(huart);
+
+ /* Set the wake-up selection scheme */
+ MODIFY_REG(huart->Instance->CR3, USART_CR3_WUS, WakeUpSelection.WakeUpEvent);
+
+ if (WakeUpSelection.WakeUpEvent == UART_WAKEUP_ON_ADDRESS)
+ {
+ UARTEx_Wakeup_AddressConfig(huart, WakeUpSelection);
+ }
+
+ /* Enable the Peripheral */
+ __HAL_UART_ENABLE(huart);
+
+ /* Init tickstart for timeout management */
+ tickstart = HAL_GetTick();
+
+ /* Wait until REACK flag is set */
+ if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
+ {
+ status = HAL_TIMEOUT;
+ }
+ else
+ {
+ /* Initialize the UART State */
+ huart->gState = HAL_UART_STATE_READY;
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return status;
+}
+
+/**
+ * @brief Enable UART Stop Mode.
+ * @note The UART is able to wake up the MCU from Stop 1 mode as long as UART clock is HSI or LSE.
+ * @param huart UART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart)
+{
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ /* Set UESM bit */
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_UESM);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disable UART Stop Mode.
+ * @param huart UART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart)
+{
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ /* Clear UESM bit */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_UESM);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Enable the FIFO mode.
+ * @param huart UART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UARTEx_EnableFifoMode(UART_HandleTypeDef *huart)
+{
+ uint32_t tmpcr1;
+
+ /* Check parameters */
+ assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
+
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ /* Save actual UART configuration */
+ tmpcr1 = READ_REG(huart->Instance->CR1);
+
+ /* Disable UART */
+ __HAL_UART_DISABLE(huart);
+
+ /* Enable FIFO mode */
+ SET_BIT(tmpcr1, USART_CR1_FIFOEN);
+ huart->FifoMode = UART_FIFOMODE_ENABLE;
+
+ /* Restore UART configuration */
+ WRITE_REG(huart->Instance->CR1, tmpcr1);
+
+ /* Determine the number of data to process during RX/TX ISR execution */
+ UARTEx_SetNbDataToProcess(huart);
+
+ huart->gState = HAL_UART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disable the FIFO mode.
+ * @param huart UART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart)
+{
+ uint32_t tmpcr1;
+
+ /* Check parameters */
+ assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
+
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ /* Save actual UART configuration */
+ tmpcr1 = READ_REG(huart->Instance->CR1);
+
+ /* Disable UART */
+ __HAL_UART_DISABLE(huart);
+
+ /* Enable FIFO mode */
+ CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN);
+ huart->FifoMode = UART_FIFOMODE_DISABLE;
+
+ /* Restore UART configuration */
+ WRITE_REG(huart->Instance->CR1, tmpcr1);
+
+ huart->gState = HAL_UART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Set the TXFIFO threshold.
+ * @param huart UART handle.
+ * @param Threshold TX FIFO threshold value
+ * This parameter can be one of the following values:
+ * @arg @ref UART_TXFIFO_THRESHOLD_1_8
+ * @arg @ref UART_TXFIFO_THRESHOLD_1_4
+ * @arg @ref UART_TXFIFO_THRESHOLD_1_2
+ * @arg @ref UART_TXFIFO_THRESHOLD_3_4
+ * @arg @ref UART_TXFIFO_THRESHOLD_7_8
+ * @arg @ref UART_TXFIFO_THRESHOLD_8_8
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold)
+{
+ uint32_t tmpcr1;
+
+ /* Check parameters */
+ assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
+ assert_param(IS_UART_TXFIFO_THRESHOLD(Threshold));
+
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ /* Save actual UART configuration */
+ tmpcr1 = READ_REG(huart->Instance->CR1);
+
+ /* Disable UART */
+ __HAL_UART_DISABLE(huart);
+
+ /* Update TX threshold configuration */
+ MODIFY_REG(huart->Instance->CR3, USART_CR3_TXFTCFG, Threshold);
+
+ /* Determine the number of data to process during RX/TX ISR execution */
+ UARTEx_SetNbDataToProcess(huart);
+
+ /* Restore UART configuration */
+ WRITE_REG(huart->Instance->CR1, tmpcr1);
+
+ huart->gState = HAL_UART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Set the RXFIFO threshold.
+ * @param huart UART handle.
+ * @param Threshold RX FIFO threshold value
+ * This parameter can be one of the following values:
+ * @arg @ref UART_RXFIFO_THRESHOLD_1_8
+ * @arg @ref UART_RXFIFO_THRESHOLD_1_4
+ * @arg @ref UART_RXFIFO_THRESHOLD_1_2
+ * @arg @ref UART_RXFIFO_THRESHOLD_3_4
+ * @arg @ref UART_RXFIFO_THRESHOLD_7_8
+ * @arg @ref UART_RXFIFO_THRESHOLD_8_8
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold)
+{
+ uint32_t tmpcr1;
+
+ /* Check the parameters */
+ assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
+ assert_param(IS_UART_RXFIFO_THRESHOLD(Threshold));
+
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ /* Save actual UART configuration */
+ tmpcr1 = READ_REG(huart->Instance->CR1);
+
+ /* Disable UART */
+ __HAL_UART_DISABLE(huart);
+
+ /* Update RX threshold configuration */
+ MODIFY_REG(huart->Instance->CR3, USART_CR3_RXFTCFG, Threshold);
+
+ /* Determine the number of data to process during RX/TX ISR execution */
+ UARTEx_SetNbDataToProcess(huart);
+
+ /* Restore UART configuration */
+ WRITE_REG(huart->Instance->CR1, tmpcr1);
+
+ huart->gState = HAL_UART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Receive an amount of data in blocking mode till either the expected number of data
+ * is received or an IDLE event occurs.
+ * @note HAL_OK is returned if reception is completed (expected number of data has been received)
+ * or if reception is stopped after IDLE event (less than the expected number of data has been received)
+ * In this case, RxLen output parameter indicates number of data available in reception buffer.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the received data is handled as a set of uint16_t. In this case, Size must indicate the number
+ * of uint16_t available through pData.
+ * @note When FIFO mode is enabled, the RXFNE flag is set as long as the RXFIFO
+ * is not empty. Read operations from the RDR register are performed when
+ * RXFNE flag is set. From hardware perspective, RXFNE flag and
+ * RXNE are mapped on the same bit-field.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * address of user data buffer for storing data to be received, should be aligned on a half word frontier
+ * (16 bits) (as received data will be handled using uint16_t pointer cast). Depending on compilation chain,
+ * use of specific alignment compilation directives or pragmas might be required to ensure proper
+ * alignment for pData.
+ * @param huart UART handle.
+ * @param pData Pointer to data buffer (uint8_t or uint16_t data elements).
+ * @param Size Amount of data elements (uint8_t or uint16_t) to be received.
+ * @param RxLen Number of data elements finally received
+ * (could be lower than Size, in case reception ends on IDLE event)
+ * @param Timeout Timeout duration expressed in ms (covers the whole reception sequence).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen,
+ uint32_t Timeout)
+{
+ uint8_t *pdata8bits;
+ uint16_t *pdata16bits;
+ uint16_t uhMask;
+ uint32_t tickstart;
+
+ /* Check that a Rx process is not already ongoing */
+ if (huart->RxState == HAL_UART_STATE_READY)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter
+ should be aligned on a uint16_t frontier, as data to be received from RDR will be
+ handled through a uint16_t cast. */
+ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+ {
+ if ((((uint32_t)pData) & 1U) != 0U)
+ {
+ return HAL_ERROR;
+ }
+ }
+
+ __HAL_LOCK(huart);
+
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+ huart->RxState = HAL_UART_STATE_BUSY_RX;
+ huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;
+
+ /* Init tickstart for timeout management */
+ tickstart = HAL_GetTick();
+
+ huart->RxXferSize = Size;
+ huart->RxXferCount = Size;
+
+ /* Computation of UART mask to apply to RDR register */
+ UART_MASK_COMPUTATION(huart);
+ uhMask = huart->Mask;
+
+ /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */
+ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+ {
+ pdata8bits = NULL;
+ pdata16bits = (uint16_t *) pData;
+ }
+ else
+ {
+ pdata8bits = pData;
+ pdata16bits = NULL;
+ }
+
+ __HAL_UNLOCK(huart);
+
+ /* Initialize output number of received elements */
+ *RxLen = 0U;
+
+ /* as long as data have to be received */
+ while (huart->RxXferCount > 0U)
+ {
+ /* Check if IDLE flag is set */
+ if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE))
+ {
+ /* Clear IDLE flag in ISR */
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
+
+ /* If Set, but no data ever received, clear flag without exiting loop */
+ /* If Set, and data has already been received, this means Idle Event is valid : End reception */
+ if (*RxLen > 0U)
+ {
+ huart->RxState = HAL_UART_STATE_READY;
+
+ return HAL_OK;
+ }
+ }
+
+ /* Check if RXNE flag is set */
+ if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RXNE))
+ {
+ if (pdata8bits == NULL)
+ {
+ *pdata16bits = (uint16_t)(huart->Instance->RDR & uhMask);
+ pdata16bits++;
+ }
+ else
+ {
+ *pdata8bits = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask);
+ pdata8bits++;
+ }
+ /* Increment number of received elements */
+ *RxLen += 1U;
+ huart->RxXferCount--;
+ }
+
+ /* Check for the Timeout */
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+ {
+ huart->RxState = HAL_UART_STATE_READY;
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Set number of received elements in output parameter : RxLen */
+ *RxLen = huart->RxXferSize - huart->RxXferCount;
+ /* At end of Rx process, restore huart->RxState to Ready */
+ huart->RxState = HAL_UART_STATE_READY;
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in interrupt mode till either the expected number of data
+ * is received or an IDLE event occurs.
+ * @note Reception is initiated by this function call. Further progress of reception is achieved thanks
+ * to UART interrupts raised by RXNE and IDLE events. Callback is called at end of reception indicating
+ * number of received data elements.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the received data is handled as a set of uint16_t. In this case, Size must indicate the number
+ * of uint16_t available through pData.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * address of user data buffer for storing data to be received, should be aligned on a half word frontier
+ * (16 bits) (as received data will be handled using uint16_t pointer cast). Depending on compilation chain,
+ * use of specific alignment compilation directives or pragmas might be required
+ * to ensure proper alignment for pData.
+ * @param huart UART handle.
+ * @param pData Pointer to data buffer (uint8_t or uint16_t data elements).
+ * @param Size Amount of data elements (uint8_t or uint16_t) to be received.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+{
+ HAL_StatusTypeDef status;
+
+ /* Check that a Rx process is not already ongoing */
+ if (huart->RxState == HAL_UART_STATE_READY)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter
+ should be aligned on a uint16_t frontier, as data to be received from RDR will be
+ handled through a uint16_t cast. */
+ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+ {
+ if ((((uint32_t)pData) & 1U) != 0U)
+ {
+ return HAL_ERROR;
+ }
+ }
+
+ __HAL_LOCK(huart);
+
+ /* Set Reception type to reception till IDLE Event*/
+ huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;
+
+ status = UART_Start_Receive_IT(huart, pData, Size);
+
+ /* Check Rx process has been successfully started */
+ if (status == HAL_OK)
+ {
+ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+ {
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+ }
+ else
+ {
+ /* In case of errors already pending when reception is started,
+ Interrupts may have already been raised and lead to reception abortion.
+ (Overrun error for instance).
+ In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */
+ status = HAL_ERROR;
+ }
+ }
+
+ return status;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in DMA mode till either the expected number
+ * of data is received or an IDLE event occurs.
+ * @note Reception is initiated by this function call. Further progress of reception is achieved thanks
+ * to DMA services, transferring automatically received data elements in user reception buffer and
+ * calling registered callbacks at half/end of reception. UART IDLE events are also used to consider
+ * reception phase as ended. In all cases, callback execution will indicate number of received data elements.
+ * @note When the UART parity is enabled (PCE = 1), the received data contain
+ * the parity bit (MSB position).
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the received data is handled as a set of uint16_t. In this case, Size must indicate the number
+ * of uint16_t available through pData.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * address of user data buffer for storing data to be received, should be aligned on a half word frontier
+ * (16 bits) (as received data will be handled by DMA from halfword frontier). Depending on compilation chain,
+ * use of specific alignment compilation directives or pragmas might be required
+ * to ensure proper alignment for pData.
+ * @param huart UART handle.
+ * @param pData Pointer to data buffer (uint8_t or uint16_t data elements).
+ * @param Size Amount of data elements (uint8_t or uint16_t) to be received.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+{
+ HAL_StatusTypeDef status;
+
+ /* Check that a Rx process is not already ongoing */
+ if (huart->RxState == HAL_UART_STATE_READY)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter
+ should be aligned on a uint16_t frontier, as data copy from RDR will be
+ handled by DMA from a uint16_t frontier. */
+ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+ {
+ if ((((uint32_t)pData) & 1U) != 0U)
+ {
+ return HAL_ERROR;
+ }
+ }
+
+ __HAL_LOCK(huart);
+
+ /* Set Reception type to reception till IDLE Event*/
+ huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;
+
+ status = UART_Start_Receive_DMA(huart, pData, Size);
+
+ /* Check Rx process has been successfully started */
+ if (status == HAL_OK)
+ {
+ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+ {
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+ }
+ else
+ {
+ /* In case of errors already pending when reception is started,
+ Interrupts may have already been raised and lead to reception abortion.
+ (Overrun error for instance).
+ In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */
+ status = HAL_ERROR;
+ }
+ }
+
+ return status;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup UARTEx_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Initialize the UART wake-up from stop mode parameters when triggered by address detection.
+ * @param huart UART handle.
+ * @param WakeUpSelection UART wake up from stop mode parameters.
+ * @retval None
+ */
+static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)
+{
+ assert_param(IS_UART_ADDRESSLENGTH_DETECT(WakeUpSelection.AddressLength));
+
+ /* Set the USART address length */
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, WakeUpSelection.AddressLength);
+
+ /* Set the USART address node */
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)WakeUpSelection.Address << UART_CR2_ADDRESS_LSB_POS));
+}
+
+/**
+ * @brief Calculate the number of data to process in RX/TX ISR.
+ * @note The RX FIFO depth and the TX FIFO depth is extracted from
+ * the UART configuration registers.
+ * @param huart UART handle.
+ * @retval None
+ */
+static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart)
+{
+ uint8_t rx_fifo_depth;
+ uint8_t tx_fifo_depth;
+ uint8_t rx_fifo_threshold;
+ uint8_t tx_fifo_threshold;
+ static const uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U};
+ static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U};
+
+ if (huart->FifoMode == UART_FIFOMODE_DISABLE)
+ {
+ huart->NbTxDataToProcess = 1U;
+ huart->NbRxDataToProcess = 1U;
+ }
+ else
+ {
+ rx_fifo_depth = RX_FIFO_DEPTH;
+ tx_fifo_depth = TX_FIFO_DEPTH;
+ rx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);
+ tx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);
+ huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) /
+ (uint16_t)denominator[tx_fifo_threshold];
+ huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) /
+ (uint16_t)denominator[rx_fifo_threshold];
+ }
+}
+/**
+ * @}
+ */
+
+#endif /* HAL_UART_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_usart.c b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_usart.c
new file mode 100644
index 0000000000..8a99c14833
--- /dev/null
+++ b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_usart.c
@@ -0,0 +1,3844 @@
+/**
+ ******************************************************************************
+ * @file stm32c0xx_hal_usart.c
+ * @author MCD Application Team
+ * @brief USART HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Universal Synchronous/Asynchronous Receiver Transmitter
+ * Peripheral (USART).
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral Control functions
+ * + Peripheral State and Error functions
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2022 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ===============================================================================
+ ##### How to use this driver #####
+ ===============================================================================
+ [..]
+ The USART HAL driver can be used as follows:
+
+ (#) Declare a USART_HandleTypeDef handle structure (eg. USART_HandleTypeDef husart).
+ (#) Initialize the USART low level resources by implementing the HAL_USART_MspInit() API:
+ (++) Enable the USARTx interface clock.
+ (++) USART pins configuration:
+ (+++) Enable the clock for the USART GPIOs.
+ (+++) Configure these USART pins as alternate function pull-up.
+ (++) NVIC configuration if you need to use interrupt process (HAL_USART_Transmit_IT(),
+ HAL_USART_Receive_IT() and HAL_USART_TransmitReceive_IT() APIs):
+ (+++) Configure the USARTx interrupt priority.
+ (+++) Enable the NVIC USART IRQ handle.
+ (++) USART interrupts handling:
+ -@@- The specific USART interrupts (Transmission complete interrupt,
+ RXNE interrupt and Error Interrupts) will be managed using the macros
+ __HAL_USART_ENABLE_IT() and __HAL_USART_DISABLE_IT() inside the transmit and receive process.
+ (++) DMA Configuration if you need to use DMA process (HAL_USART_Transmit_DMA()
+ HAL_USART_Receive_DMA() and HAL_USART_TransmitReceive_DMA() APIs):
+ (+++) Declare a DMA handle structure for the Tx/Rx channel.
+ (+++) Enable the DMAx interface clock.
+ (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
+ (+++) Configure the DMA Tx/Rx channel.
+ (+++) Associate the initialized DMA handle to the USART DMA Tx/Rx handle.
+ (+++) Configure the priority and enable the NVIC for the transfer
+ complete interrupt on the DMA Tx/Rx channel.
+
+ (#) Program the Baud Rate, Word Length, Stop Bit, Parity, and Mode
+ (Receiver/Transmitter) in the husart handle Init structure.
+
+ (#) Initialize the USART registers by calling the HAL_USART_Init() API:
+ (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
+ by calling the customized HAL_USART_MspInit(&husart) API.
+
+ [..]
+ (@) To configure and enable/disable the USART to wake up the MCU from stop mode, resort to UART API's
+ HAL_UARTEx_StopModeWakeUpSourceConfig(), HAL_UARTEx_EnableStopMode() and
+ HAL_UARTEx_DisableStopMode() in casting the USART handle to UART type UART_HandleTypeDef.
+
+ ##### Callback registration #####
+ ==================================
+
+ [..]
+ The compilation define USE_HAL_USART_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+
+ [..]
+ Use Function HAL_USART_RegisterCallback() to register a user callback.
+ Function HAL_USART_RegisterCallback() allows to register following callbacks:
+ (+) TxHalfCpltCallback : Tx Half Complete Callback.
+ (+) TxCpltCallback : Tx Complete Callback.
+ (+) RxHalfCpltCallback : Rx Half Complete Callback.
+ (+) RxCpltCallback : Rx Complete Callback.
+ (+) TxRxCpltCallback : Tx Rx Complete Callback.
+ (+) ErrorCallback : Error Callback.
+ (+) AbortCpltCallback : Abort Complete Callback.
+ (+) RxFifoFullCallback : Rx Fifo Full Callback.
+ (+) TxFifoEmptyCallback : Tx Fifo Empty Callback.
+ (+) MspInitCallback : USART MspInit.
+ (+) MspDeInitCallback : USART MspDeInit.
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+ [..]
+ Use function HAL_USART_UnRegisterCallback() to reset a callback to the default
+ weak (surcharged) function.
+ HAL_USART_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+ and the Callback ID.
+ This function allows to reset following callbacks:
+ (+) TxHalfCpltCallback : Tx Half Complete Callback.
+ (+) TxCpltCallback : Tx Complete Callback.
+ (+) RxHalfCpltCallback : Rx Half Complete Callback.
+ (+) RxCpltCallback : Rx Complete Callback.
+ (+) TxRxCpltCallback : Tx Rx Complete Callback.
+ (+) ErrorCallback : Error Callback.
+ (+) AbortCpltCallback : Abort Complete Callback.
+ (+) RxFifoFullCallback : Rx Fifo Full Callback.
+ (+) TxFifoEmptyCallback : Tx Fifo Empty Callback.
+ (+) MspInitCallback : USART MspInit.
+ (+) MspDeInitCallback : USART MspDeInit.
+
+ [..]
+ By default, after the HAL_USART_Init() and when the state is HAL_USART_STATE_RESET
+ all callbacks are set to the corresponding weak (surcharged) functions:
+ examples HAL_USART_TxCpltCallback(), HAL_USART_RxHalfCpltCallback().
+ Exception done for MspInit and MspDeInit functions that are respectively
+ reset to the legacy weak (surcharged) functions in the HAL_USART_Init()
+ and HAL_USART_DeInit() only when these callbacks are null (not registered beforehand).
+ If not, MspInit or MspDeInit are not null, the HAL_USART_Init() and HAL_USART_DeInit()
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
+
+ [..]
+ Callbacks can be registered/unregistered in HAL_USART_STATE_READY state only.
+ Exception done MspInit/MspDeInit that can be registered/unregistered
+ in HAL_USART_STATE_READY or HAL_USART_STATE_RESET state, thus registered (user)
+ MspInit/DeInit callbacks can be used during the Init/DeInit.
+ In that case first register the MspInit/MspDeInit user callbacks
+ using HAL_USART_RegisterCallback() before calling HAL_USART_DeInit()
+ or HAL_USART_Init() function.
+
+ [..]
+ When The compilation define USE_HAL_USART_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registration feature is not available
+ and weak (surcharged) callbacks are used.
+
+
+ @endverbatim
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32c0xx_hal.h"
+
+/** @addtogroup STM32C0xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup USART USART
+ * @brief HAL USART Synchronous module driver
+ * @{
+ */
+
+#ifdef HAL_USART_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup USART_Private_Constants USART Private Constants
+ * @{
+ */
+#define USART_DUMMY_DATA ((uint16_t) 0xFFFF) /*!< USART transmitted dummy data */
+#define USART_TEACK_REACK_TIMEOUT 1000U /*!< USART TX or RX enable acknowledge time-out value */
+#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \
+ USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8 | \
+ USART_CR1_FIFOEN )) /*!< USART CR1 fields of parameters set by USART_SetConfig API */
+
+#define USART_CR2_FIELDS ((uint32_t)(USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_CLKEN | \
+ USART_CR2_LBCL | USART_CR2_STOP | USART_CR2_SLVEN | \
+ USART_CR2_DIS_NSS)) /*!< USART CR2 fields of parameters set by USART_SetConfig API */
+
+#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_TXFTCFG | USART_CR3_RXFTCFG )) /*!< USART or USART CR3 fields of parameters set by USART_SetConfig API */
+
+#define USART_BRR_MIN 0x10U /* USART BRR minimum authorized value */
+#define USART_BRR_MAX 0xFFFFU /* USART BRR maximum authorized value */
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup USART_Private_Functions
+ * @{
+ */
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+void USART_InitCallbacksToDefault(USART_HandleTypeDef *husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+static void USART_EndTransfer(USART_HandleTypeDef *husart);
+static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma);
+static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
+static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
+static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
+static void USART_DMAError(DMA_HandleTypeDef *hdma);
+static void USART_DMAAbortOnError(DMA_HandleTypeDef *hdma);
+static void USART_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
+static void USART_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
+static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status,
+ uint32_t Tickstart, uint32_t Timeout);
+static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart);
+static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart);
+static void USART_TxISR_8BIT(USART_HandleTypeDef *husart);
+static void USART_TxISR_16BIT(USART_HandleTypeDef *husart);
+static void USART_TxISR_8BIT_FIFOEN(USART_HandleTypeDef *husart);
+static void USART_TxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart);
+static void USART_EndTransmit_IT(USART_HandleTypeDef *husart);
+static void USART_RxISR_8BIT(USART_HandleTypeDef *husart);
+static void USART_RxISR_16BIT(USART_HandleTypeDef *husart);
+static void USART_RxISR_8BIT_FIFOEN(USART_HandleTypeDef *husart);
+static void USART_RxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart);
+
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup USART_Exported_Functions USART Exported Functions
+ * @{
+ */
+
+/** @defgroup USART_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and Configuration functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to initialize the USART
+ in asynchronous and in synchronous modes.
+ (+) For the asynchronous mode only these parameters can be configured:
+ (++) Baud Rate
+ (++) Word Length
+ (++) Stop Bit
+ (++) Parity: If the parity is enabled, then the MSB bit of the data written
+ in the data register is transmitted but is changed by the parity bit.
+ (++) USART polarity
+ (++) USART phase
+ (++) USART LastBit
+ (++) Receiver/transmitter modes
+
+ [..]
+ The HAL_USART_Init() function follows the USART synchronous configuration
+ procedure (details for the procedure are available in reference manual).
+
+@endverbatim
+
+ Depending on the frame length defined by the M1 and M0 bits (7-bit,
+ 8-bit or 9-bit), the possible USART formats are listed in the
+ following table.
+
+ Table 1. USART frame format.
+ +-----------------------------------------------------------------------+
+ | M1 bit | M0 bit | PCE bit | USART frame |
+ |---------|---------|-----------|---------------------------------------|
+ | 0 | 0 | 0 | | SB | 8 bit data | STB | |
+ |---------|---------|-----------|---------------------------------------|
+ | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | |
+ |---------|---------|-----------|---------------------------------------|
+ | 0 | 1 | 0 | | SB | 9 bit data | STB | |
+ |---------|---------|-----------|---------------------------------------|
+ | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | |
+ |---------|---------|-----------|---------------------------------------|
+ | 1 | 0 | 0 | | SB | 7 bit data | STB | |
+ |---------|---------|-----------|---------------------------------------|
+ | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | |
+ +-----------------------------------------------------------------------+
+
+ * @{
+ */
+
+/**
+ * @brief Initialize the USART mode according to the specified
+ * parameters in the USART_InitTypeDef and initialize the associated handle.
+ * @param husart USART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart)
+{
+ /* Check the USART handle allocation */
+ if (husart == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_USART_INSTANCE(husart->Instance));
+
+ if (husart->State == HAL_USART_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ husart->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ USART_InitCallbacksToDefault(husart);
+
+ if (husart->MspInitCallback == NULL)
+ {
+ husart->MspInitCallback = HAL_USART_MspInit;
+ }
+
+ /* Init the low level hardware */
+ husart->MspInitCallback(husart);
+#else
+ /* Init the low level hardware : GPIO, CLOCK */
+ HAL_USART_MspInit(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+ }
+
+ husart->State = HAL_USART_STATE_BUSY;
+
+ /* Disable the Peripheral */
+ __HAL_USART_DISABLE(husart);
+
+ /* Set the Usart Communication parameters */
+ if (USART_SetConfig(husart) == HAL_ERROR)
+ {
+ return HAL_ERROR;
+ }
+
+ /* In Synchronous mode, the following bits must be kept cleared:
+ - LINEN bit in the USART_CR2 register
+ - HDSEL, SCEN and IREN bits in the USART_CR3 register.
+ */
+ husart->Instance->CR2 &= ~USART_CR2_LINEN;
+ husart->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN);
+
+ /* Enable the Peripheral */
+ __HAL_USART_ENABLE(husart);
+
+ /* TEACK and/or REACK to check before moving husart->State to Ready */
+ return (USART_CheckIdleState(husart));
+}
+
+/**
+ * @brief DeInitialize the USART peripheral.
+ * @param husart USART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart)
+{
+ /* Check the USART handle allocation */
+ if (husart == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_USART_INSTANCE(husart->Instance));
+
+ husart->State = HAL_USART_STATE_BUSY;
+
+ husart->Instance->CR1 = 0x0U;
+ husart->Instance->CR2 = 0x0U;
+ husart->Instance->CR3 = 0x0U;
+
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ if (husart->MspDeInitCallback == NULL)
+ {
+ husart->MspDeInitCallback = HAL_USART_MspDeInit;
+ }
+ /* DeInit the low level hardware */
+ husart->MspDeInitCallback(husart);
+#else
+ /* DeInit the low level hardware */
+ HAL_USART_MspDeInit(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+
+ husart->ErrorCode = HAL_USART_ERROR_NONE;
+ husart->State = HAL_USART_STATE_RESET;
+
+ /* Process Unlock */
+ __HAL_UNLOCK(husart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initialize the USART MSP.
+ * @param husart USART handle.
+ * @retval None
+ */
+__weak void HAL_USART_MspInit(USART_HandleTypeDef *husart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(husart);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_USART_MspInit can be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitialize the USART MSP.
+ * @param husart USART handle.
+ * @retval None
+ */
+__weak void HAL_USART_MspDeInit(USART_HandleTypeDef *husart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(husart);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_USART_MspDeInit can be implemented in the user file
+ */
+}
+
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a User USART Callback
+ * To be used instead of the weak predefined callback
+ * @param husart usart handle
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_USART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
+ * @arg @ref HAL_USART_TX_COMPLETE_CB_ID Tx Complete Callback ID
+ * @arg @ref HAL_USART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
+ * @arg @ref HAL_USART_RX_COMPLETE_CB_ID Rx Complete Callback ID
+ * @arg @ref HAL_USART_TX_RX_COMPLETE_CB_ID Rx Complete Callback ID
+ * @arg @ref HAL_USART_ERROR_CB_ID Error Callback ID
+ * @arg @ref HAL_USART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
+ * @arg @ref HAL_USART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID
+ * @arg @ref HAL_USART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID
+ * @arg @ref HAL_USART_MSPINIT_CB_ID MspInit Callback ID
+ * @arg @ref HAL_USART_MSPDEINIT_CB_ID MspDeInit Callback ID
+ * @param pCallback pointer to the Callback function
+ * @retval HAL status
++ */
+HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID,
+ pUSART_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+ /* Process locked */
+ __HAL_LOCK(husart);
+
+ if (husart->State == HAL_USART_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+ case HAL_USART_TX_HALFCOMPLETE_CB_ID :
+ husart->TxHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_USART_TX_COMPLETE_CB_ID :
+ husart->TxCpltCallback = pCallback;
+ break;
+
+ case HAL_USART_RX_HALFCOMPLETE_CB_ID :
+ husart->RxHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_USART_RX_COMPLETE_CB_ID :
+ husart->RxCpltCallback = pCallback;
+ break;
+
+ case HAL_USART_TX_RX_COMPLETE_CB_ID :
+ husart->TxRxCpltCallback = pCallback;
+ break;
+
+ case HAL_USART_ERROR_CB_ID :
+ husart->ErrorCallback = pCallback;
+ break;
+
+ case HAL_USART_ABORT_COMPLETE_CB_ID :
+ husart->AbortCpltCallback = pCallback;
+ break;
+
+ case HAL_USART_RX_FIFO_FULL_CB_ID :
+ husart->RxFifoFullCallback = pCallback;
+ break;
+
+ case HAL_USART_TX_FIFO_EMPTY_CB_ID :
+ husart->TxFifoEmptyCallback = pCallback;
+ break;
+
+ case HAL_USART_MSPINIT_CB_ID :
+ husart->MspInitCallback = pCallback;
+ break;
+
+ case HAL_USART_MSPDEINIT_CB_ID :
+ husart->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (husart->State == HAL_USART_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_USART_MSPINIT_CB_ID :
+ husart->MspInitCallback = pCallback;
+ break;
+
+ case HAL_USART_MSPDEINIT_CB_ID :
+ husart->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(husart);
+
+ return status;
+}
+
+/**
+ * @brief Unregister an USART Callback
+ * USART callaback is redirected to the weak predefined callback
+ * @param husart usart handle
+ * @param CallbackID ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_USART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
+ * @arg @ref HAL_USART_TX_COMPLETE_CB_ID Tx Complete Callback ID
+ * @arg @ref HAL_USART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
+ * @arg @ref HAL_USART_RX_COMPLETE_CB_ID Rx Complete Callback ID
+ * @arg @ref HAL_USART_TX_RX_COMPLETE_CB_ID Rx Complete Callback ID
+ * @arg @ref HAL_USART_ERROR_CB_ID Error Callback ID
+ * @arg @ref HAL_USART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
+ * @arg @ref HAL_USART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID
+ * @arg @ref HAL_USART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID
+ * @arg @ref HAL_USART_MSPINIT_CB_ID MspInit Callback ID
+ * @arg @ref HAL_USART_MSPDEINIT_CB_ID MspDeInit Callback ID
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(husart);
+
+ if (HAL_USART_STATE_READY == husart->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_USART_TX_HALFCOMPLETE_CB_ID :
+ husart->TxHalfCpltCallback = HAL_USART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
+ break;
+
+ case HAL_USART_TX_COMPLETE_CB_ID :
+ husart->TxCpltCallback = HAL_USART_TxCpltCallback; /* Legacy weak TxCpltCallback */
+ break;
+
+ case HAL_USART_RX_HALFCOMPLETE_CB_ID :
+ husart->RxHalfCpltCallback = HAL_USART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
+ break;
+
+ case HAL_USART_RX_COMPLETE_CB_ID :
+ husart->RxCpltCallback = HAL_USART_RxCpltCallback; /* Legacy weak RxCpltCallback */
+ break;
+
+ case HAL_USART_TX_RX_COMPLETE_CB_ID :
+ husart->TxRxCpltCallback = HAL_USART_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */
+ break;
+
+ case HAL_USART_ERROR_CB_ID :
+ husart->ErrorCallback = HAL_USART_ErrorCallback; /* Legacy weak ErrorCallback */
+ break;
+
+ case HAL_USART_ABORT_COMPLETE_CB_ID :
+ husart->AbortCpltCallback = HAL_USART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
+ break;
+
+ case HAL_USART_RX_FIFO_FULL_CB_ID :
+ husart->RxFifoFullCallback = HAL_USARTEx_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */
+ break;
+
+ case HAL_USART_TX_FIFO_EMPTY_CB_ID :
+ husart->TxFifoEmptyCallback = HAL_USARTEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */
+ break;
+
+ case HAL_USART_MSPINIT_CB_ID :
+ husart->MspInitCallback = HAL_USART_MspInit; /* Legacy weak MspInitCallback */
+ break;
+
+ case HAL_USART_MSPDEINIT_CB_ID :
+ husart->MspDeInitCallback = HAL_USART_MspDeInit; /* Legacy weak MspDeInitCallback */
+ break;
+
+ default :
+ /* Update the error code */
+ husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_USART_STATE_RESET == husart->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_USART_MSPINIT_CB_ID :
+ husart->MspInitCallback = HAL_USART_MspInit;
+ break;
+
+ case HAL_USART_MSPDEINIT_CB_ID :
+ husart->MspDeInitCallback = HAL_USART_MspDeInit;
+ break;
+
+ default :
+ /* Update the error code */
+ husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(husart);
+
+ return status;
+}
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_Exported_Functions_Group2 IO operation functions
+ * @brief USART Transmit and Receive functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..] This subsection provides a set of functions allowing to manage the USART synchronous
+ data transfers.
+
+ [..] The USART supports master mode only: it cannot receive or send data related to an input
+ clock (SCLK is always an output).
+
+ [..]
+
+ (#) There are two modes of transfer:
+ (++) Blocking mode: The communication is performed in polling mode.
+ The HAL status of all data processing is returned by the same function
+ after finishing transfer.
+ (++) No-Blocking mode: The communication is performed using Interrupts
+ or DMA, These API's return the HAL status.
+ The end of the data processing will be indicated through the
+ dedicated USART IRQ when using Interrupt mode or the DMA IRQ when
+ using DMA mode.
+ The HAL_USART_TxCpltCallback(), HAL_USART_RxCpltCallback() and HAL_USART_TxRxCpltCallback() user callbacks
+ will be executed respectively at the end of the transmit or Receive process
+ The HAL_USART_ErrorCallback()user callback will be executed when a communication error is detected
+
+ (#) Blocking mode API's are :
+ (++) HAL_USART_Transmit() in simplex mode
+ (++) HAL_USART_Receive() in full duplex receive only
+ (++) HAL_USART_TransmitReceive() in full duplex mode
+
+ (#) Non-Blocking mode API's with Interrupt are :
+ (++) HAL_USART_Transmit_IT() in simplex mode
+ (++) HAL_USART_Receive_IT() in full duplex receive only
+ (++) HAL_USART_TransmitReceive_IT() in full duplex mode
+ (++) HAL_USART_IRQHandler()
+
+ (#) No-Blocking mode API's with DMA are :
+ (++) HAL_USART_Transmit_DMA() in simplex mode
+ (++) HAL_USART_Receive_DMA() in full duplex receive only
+ (++) HAL_USART_TransmitReceive_DMA() in full duplex mode
+ (++) HAL_USART_DMAPause()
+ (++) HAL_USART_DMAResume()
+ (++) HAL_USART_DMAStop()
+
+ (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode:
+ (++) HAL_USART_TxCpltCallback()
+ (++) HAL_USART_RxCpltCallback()
+ (++) HAL_USART_TxHalfCpltCallback()
+ (++) HAL_USART_RxHalfCpltCallback()
+ (++) HAL_USART_ErrorCallback()
+ (++) HAL_USART_TxRxCpltCallback()
+
+ (#) Non-Blocking mode transfers could be aborted using Abort API's :
+ (++) HAL_USART_Abort()
+ (++) HAL_USART_Abort_IT()
+
+ (#) For Abort services based on interrupts (HAL_USART_Abort_IT), a Abort Complete Callbacks is provided:
+ (++) HAL_USART_AbortCpltCallback()
+
+ (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
+ Errors are handled as follows :
+ (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
+ to be evaluated by user : this concerns Frame Error,
+ Parity Error or Noise Error in Interrupt mode reception .
+ Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify
+ error type, and HAL_USART_ErrorCallback() user callback is executed.
+ Transfer is kept ongoing on USART side.
+ If user wants to abort it, Abort services should be called by user.
+ (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
+ This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
+ Error code is set to allow user to identify error type,
+ and HAL_USART_ErrorCallback() user callback is executed.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Simplex send an amount of data in blocking mode.
+ * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the sent data is handled as a set of u16. In this case, Size must indicate the number
+ * of u16 provided through pTxData.
+ * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits)
+ * (as sent data will be handled using u16 pointer cast). Depending on compilation chain,
+ * use of specific alignment compilation directives or pragmas might be required
+ * to ensure proper alignment for pTxData.
+ * @param husart USART handle.
+ * @param pTxData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be sent.
+ * @param Timeout Timeout duration.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size,
+ uint32_t Timeout)
+{
+ const uint8_t *ptxdata8bits;
+ const uint16_t *ptxdata16bits;
+ uint32_t tickstart;
+
+ if (husart->State == HAL_USART_STATE_READY)
+ {
+ if ((pTxData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* In case of 9bits/No Parity transfer, pTxData buffer provided as input parameter
+ should be aligned on a u16 frontier, as data to be filled into TDR will be
+ handled through a u16 cast. */
+ if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
+ {
+ if ((((uint32_t)pTxData) & 1U) != 0U)
+ {
+ return HAL_ERROR;
+ }
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(husart);
+
+ husart->ErrorCode = HAL_USART_ERROR_NONE;
+ husart->State = HAL_USART_STATE_BUSY_TX;
+
+ /* Init tickstart for timeout management */
+ tickstart = HAL_GetTick();
+
+ husart->TxXferSize = Size;
+ husart->TxXferCount = Size;
+
+ /* In case of 9bits/No Parity transfer, pTxData needs to be handled as a uint16_t pointer */
+ if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
+ {
+ ptxdata8bits = NULL;
+ ptxdata16bits = (const uint16_t *) pTxData;
+ }
+ else
+ {
+ ptxdata8bits = pTxData;
+ ptxdata16bits = NULL;
+ }
+
+ /* Check the remaining data to be sent */
+ while (husart->TxXferCount > 0U)
+ {
+ if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ if (ptxdata8bits == NULL)
+ {
+ husart->Instance->TDR = (uint16_t)(*ptxdata16bits & 0x01FFU);
+ ptxdata16bits++;
+ }
+ else
+ {
+ husart->Instance->TDR = (uint8_t)(*ptxdata8bits & 0xFFU);
+ ptxdata8bits++;
+ }
+
+ husart->TxXferCount--;
+ }
+
+ if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Clear Transmission Complete Flag */
+ __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_TCF);
+
+ /* Clear overrun flag and discard the received data */
+ __HAL_USART_CLEAR_OREFLAG(husart);
+ __HAL_USART_SEND_REQ(husart, USART_RXDATA_FLUSH_REQUEST);
+ __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST);
+
+ /* At end of Tx process, restore husart->State to Ready */
+ husart->State = HAL_USART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in blocking mode.
+ * @note To receive synchronous data, dummy data are simultaneously transmitted.
+ * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the received data is handled as a set of u16. In this case, Size must indicate the number
+ * of u16 available through pRxData.
+ * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits)
+ * (as received data will be handled using u16 pointer cast). Depending on compilation chain,
+ * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pRxData.
+ * @param husart USART handle.
+ * @param pRxData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be received.
+ * @param Timeout Timeout duration.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
+{
+ uint8_t *prxdata8bits;
+ uint16_t *prxdata16bits;
+ uint16_t uhMask;
+ uint32_t tickstart;
+
+ if (husart->State == HAL_USART_STATE_READY)
+ {
+ if ((pRxData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* In case of 9bits/No Parity transfer, pRxData buffer provided as input parameter
+ should be aligned on a u16 frontier, as data to be received from RDR will be
+ handled through a u16 cast. */
+ if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
+ {
+ if ((((uint32_t)pRxData) & 1U) != 0U)
+ {
+ return HAL_ERROR;
+ }
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(husart);
+
+ husart->ErrorCode = HAL_USART_ERROR_NONE;
+ husart->State = HAL_USART_STATE_BUSY_RX;
+
+ /* Init tickstart for timeout management */
+ tickstart = HAL_GetTick();
+
+ husart->RxXferSize = Size;
+ husart->RxXferCount = Size;
+
+ /* Computation of USART mask to apply to RDR register */
+ USART_MASK_COMPUTATION(husart);
+ uhMask = husart->Mask;
+
+ /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */
+ if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
+ {
+ prxdata8bits = NULL;
+ prxdata16bits = (uint16_t *) pRxData;
+ }
+ else
+ {
+ prxdata8bits = pRxData;
+ prxdata16bits = NULL;
+ }
+
+ /* as long as data have to be received */
+ while (husart->RxXferCount > 0U)
+ {
+ if (husart->SlaveMode == USART_SLAVEMODE_DISABLE)
+ {
+ /* Wait until TXE flag is set to send dummy byte in order to generate the
+ * clock for the slave to send data.
+ * Whatever the frame length (7, 8 or 9-bit long), the same dummy value
+ * can be written for all the cases. */
+ if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x0FF);
+ }
+
+ /* Wait for RXNE Flag */
+ if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ if (prxdata8bits == NULL)
+ {
+ *prxdata16bits = (uint16_t)(husart->Instance->RDR & uhMask);
+ prxdata16bits++;
+ }
+ else
+ {
+ *prxdata8bits = (uint8_t)(husart->Instance->RDR & (uint8_t)(uhMask & 0xFFU));
+ prxdata8bits++;
+ }
+
+ husart->RxXferCount--;
+
+ }
+
+ /* Clear SPI slave underrun flag and discard transmit data */
+ if (husart->SlaveMode == USART_SLAVEMODE_ENABLE)
+ {
+ __HAL_USART_CLEAR_UDRFLAG(husart);
+ __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST);
+ }
+
+ /* At end of Rx process, restore husart->State to Ready */
+ husart->State = HAL_USART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Full-Duplex Send and Receive an amount of data in blocking mode.
+ * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number
+ * of u16 available through pTxData and through pRxData.
+ * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * address of user data buffers containing data to be sent/received, should be aligned on a half word frontier (16 bits)
+ * (as sent/received data will be handled using u16 pointer cast). Depending on compilation chain,
+ * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pTxData and pRxData.
+ * @param husart USART handle.
+ * @param pTxData pointer to TX data buffer (u8 or u16 data elements).
+ * @param pRxData pointer to RX data buffer (u8 or u16 data elements).
+ * @param Size amount of data elements (u8 or u16) to be sent (same amount to be received).
+ * @param Timeout Timeout duration.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData,
+ uint16_t Size, uint32_t Timeout)
+{
+ uint8_t *prxdata8bits;
+ uint16_t *prxdata16bits;
+ const uint8_t *ptxdata8bits;
+ const uint16_t *ptxdata16bits;
+ uint16_t uhMask;
+ uint16_t rxdatacount;
+ uint32_t tickstart;
+
+ if (husart->State == HAL_USART_STATE_READY)
+ {
+ if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* In case of 9bits/No Parity transfer, pTxData and pRxData buffers provided as input parameter
+ should be aligned on a u16 frontier, as data to be filled into TDR/retrieved from RDR will be
+ handled through a u16 cast. */
+ if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
+ {
+ if (((((uint32_t)pTxData) & 1U) != 0U) || ((((uint32_t)pRxData) & 1U) != 0U))
+ {
+ return HAL_ERROR;
+ }
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(husart);
+
+ husart->ErrorCode = HAL_USART_ERROR_NONE;
+ husart->State = HAL_USART_STATE_BUSY_RX;
+
+ /* Init tickstart for timeout management */
+ tickstart = HAL_GetTick();
+
+ husart->RxXferSize = Size;
+ husart->TxXferSize = Size;
+ husart->TxXferCount = Size;
+ husart->RxXferCount = Size;
+
+ /* Computation of USART mask to apply to RDR register */
+ USART_MASK_COMPUTATION(husart);
+ uhMask = husart->Mask;
+
+ /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */
+ if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
+ {
+ prxdata8bits = NULL;
+ ptxdata8bits = NULL;
+ ptxdata16bits = (const uint16_t *) pTxData;
+ prxdata16bits = (uint16_t *) pRxData;
+ }
+ else
+ {
+ prxdata8bits = pRxData;
+ ptxdata8bits = pTxData;
+ ptxdata16bits = NULL;
+ prxdata16bits = NULL;
+ }
+
+ if ((husart->TxXferCount == 0x01U) || (husart->SlaveMode == USART_SLAVEMODE_ENABLE))
+ {
+ /* Wait until TXE flag is set to send data */
+ if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ if (ptxdata8bits == NULL)
+ {
+ husart->Instance->TDR = (uint16_t)(*ptxdata16bits & uhMask);
+ ptxdata16bits++;
+ }
+ else
+ {
+ husart->Instance->TDR = (uint8_t)(*ptxdata8bits & (uint8_t)(uhMask & 0xFFU));
+ ptxdata8bits++;
+ }
+
+ husart->TxXferCount--;
+ }
+
+ /* Check the remain data to be sent */
+ /* rxdatacount is a temporary variable for MISRAC2012-Rule-13.5 */
+ rxdatacount = husart->RxXferCount;
+ while ((husart->TxXferCount > 0U) || (rxdatacount > 0U))
+ {
+ if (husart->TxXferCount > 0U)
+ {
+ /* Wait until TXE flag is set to send data */
+ if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ if (ptxdata8bits == NULL)
+ {
+ husart->Instance->TDR = (uint16_t)(*ptxdata16bits & uhMask);
+ ptxdata16bits++;
+ }
+ else
+ {
+ husart->Instance->TDR = (uint8_t)(*ptxdata8bits & (uint8_t)(uhMask & 0xFFU));
+ ptxdata8bits++;
+ }
+
+ husart->TxXferCount--;
+ }
+
+ if (husart->RxXferCount > 0U)
+ {
+ /* Wait for RXNE Flag */
+ if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ if (prxdata8bits == NULL)
+ {
+ *prxdata16bits = (uint16_t)(husart->Instance->RDR & uhMask);
+ prxdata16bits++;
+ }
+ else
+ {
+ *prxdata8bits = (uint8_t)(husart->Instance->RDR & (uint8_t)(uhMask & 0xFFU));
+ prxdata8bits++;
+ }
+
+ husart->RxXferCount--;
+ }
+ rxdatacount = husart->RxXferCount;
+ }
+
+ /* At end of TxRx process, restore husart->State to Ready */
+ husart->State = HAL_USART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Send an amount of data in interrupt mode.
+ * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the sent data is handled as a set of u16. In this case, Size must indicate the number
+ * of u16 provided through pTxData.
+ * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits)
+ * (as sent data will be handled using u16 pointer cast). Depending on compilation chain,
+ * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pTxData.
+ * @param husart USART handle.
+ * @param pTxData pointer to data buffer (u8 or u16 data elements).
+ * @param Size amount of data elements (u8 or u16) to be sent.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size)
+{
+ if (husart->State == HAL_USART_STATE_READY)
+ {
+ if ((pTxData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* In case of 9bits/No Parity transfer, pTxData buffer provided as input parameter
+ should be aligned on a u16 frontier, as data to be filled into TDR will be
+ handled through a u16 cast. */
+ if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
+ {
+ if ((((uint32_t)pTxData) & 1U) != 0U)
+ {
+ return HAL_ERROR;
+ }
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(husart);
+
+ husart->pTxBuffPtr = pTxData;
+ husart->TxXferSize = Size;
+ husart->TxXferCount = Size;
+ husart->TxISR = NULL;
+
+ husart->ErrorCode = HAL_USART_ERROR_NONE;
+ husart->State = HAL_USART_STATE_BUSY_TX;
+
+ /* The USART Error Interrupts: (Frame error, noise error, overrun error)
+ are not managed by the USART Transmit Process to avoid the overrun interrupt
+ when the usart mode is configured for transmit and receive "USART_MODE_TX_RX"
+ to benefit for the frame error and noise interrupts the usart mode should be
+ configured only for transmit "USART_MODE_TX" */
+
+ /* Configure Tx interrupt processing */
+ if (husart->FifoMode == USART_FIFOMODE_ENABLE)
+ {
+ /* Set the Tx ISR function pointer according to the data word length */
+ if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
+ {
+ husart->TxISR = USART_TxISR_16BIT_FIFOEN;
+ }
+ else
+ {
+ husart->TxISR = USART_TxISR_8BIT_FIFOEN;
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ /* Enable the TX FIFO threshold interrupt */
+ __HAL_USART_ENABLE_IT(husart, USART_IT_TXFT);
+ }
+ else
+ {
+ /* Set the Tx ISR function pointer according to the data word length */
+ if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
+ {
+ husart->TxISR = USART_TxISR_16BIT;
+ }
+ else
+ {
+ husart->TxISR = USART_TxISR_8BIT;
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ /* Enable the USART Transmit Data Register Empty Interrupt */
+ __HAL_USART_ENABLE_IT(husart, USART_IT_TXE);
+ }
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in interrupt mode.
+ * @note To receive synchronous data, dummy data are simultaneously transmitted.
+ * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the received data is handled as a set of u16. In this case, Size must indicate the number
+ * of u16 available through pRxData.
+ * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits)
+ * (as received data will be handled using u16 pointer cast). Depending on compilation chain,
+ * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pRxData.
+ * @param husart USART handle.
+ * @param pRxData pointer to data buffer (u8 or u16 data elements).
+ * @param Size amount of data elements (u8 or u16) to be received.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
+{
+ uint16_t nb_dummy_data;
+
+ if (husart->State == HAL_USART_STATE_READY)
+ {
+ if ((pRxData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* In case of 9bits/No Parity transfer, pRxData buffer provided as input parameter
+ should be aligned on a u16 frontier, as data to be received from RDR will be
+ handled through a u16 cast. */
+ if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
+ {
+ if ((((uint32_t)pRxData) & 1U) != 0U)
+ {
+ return HAL_ERROR;
+ }
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(husart);
+
+ husart->pRxBuffPtr = pRxData;
+ husart->RxXferSize = Size;
+ husart->RxXferCount = Size;
+ husart->RxISR = NULL;
+
+ USART_MASK_COMPUTATION(husart);
+
+ husart->ErrorCode = HAL_USART_ERROR_NONE;
+ husart->State = HAL_USART_STATE_BUSY_RX;
+
+ /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
+ SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
+
+ /* Configure Rx interrupt processing */
+ if ((husart->FifoMode == USART_FIFOMODE_ENABLE) && (Size >= husart->NbRxDataToProcess))
+ {
+ /* Set the Rx ISR function pointer according to the data word length */
+ if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
+ {
+ husart->RxISR = USART_RxISR_16BIT_FIFOEN;
+ }
+ else
+ {
+ husart->RxISR = USART_RxISR_8BIT_FIFOEN;
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ /* Enable the USART Parity Error interrupt and RX FIFO Threshold interrupt */
+ if (husart->Init.Parity != USART_PARITY_NONE)
+ {
+ SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
+ }
+ SET_BIT(husart->Instance->CR3, USART_CR3_RXFTIE);
+ }
+ else
+ {
+ /* Set the Rx ISR function pointer according to the data word length */
+ if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
+ {
+ husart->RxISR = USART_RxISR_16BIT;
+ }
+ else
+ {
+ husart->RxISR = USART_RxISR_8BIT;
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ /* Enable the USART Parity Error and Data Register not empty Interrupts */
+ if (husart->Init.Parity != USART_PARITY_NONE)
+ {
+ SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE);
+ }
+ else
+ {
+ SET_BIT(husart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
+ }
+ }
+
+ if (husart->SlaveMode == USART_SLAVEMODE_DISABLE)
+ {
+ /* Send dummy data in order to generate the clock for the Slave to send the next data.
+ When FIFO mode is disabled only one data must be transferred.
+ When FIFO mode is enabled data must be transmitted until the RX FIFO reaches its threshold.
+ */
+ if ((husart->FifoMode == USART_FIFOMODE_ENABLE) && (Size >= husart->NbRxDataToProcess))
+ {
+ for (nb_dummy_data = husart->NbRxDataToProcess ; nb_dummy_data > 0U ; nb_dummy_data--)
+ {
+ husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF);
+ }
+ }
+ else
+ {
+ husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF);
+ }
+ }
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Full-Duplex Send and Receive an amount of data in interrupt mode.
+ * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number
+ * of u16 available through pTxData and through pRxData.
+ * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * address of user data buffers containing data to be sent/received, should be aligned on a half word frontier (16 bits)
+ * (as sent/received data will be handled using u16 pointer cast). Depending on compilation chain,
+ * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pTxData and pRxData.
+ * @param husart USART handle.
+ * @param pTxData pointer to TX data buffer (u8 or u16 data elements).
+ * @param pRxData pointer to RX data buffer (u8 or u16 data elements).
+ * @param Size amount of data elements (u8 or u16) to be sent (same amount to be received).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData,
+ uint16_t Size)
+{
+
+ if (husart->State == HAL_USART_STATE_READY)
+ {
+ if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* In case of 9bits/No Parity transfer, pTxData and pRxData buffers provided as input parameter
+ should be aligned on a u16 frontier, as data to be filled into TDR/retrieved from RDR will be
+ handled through a u16 cast. */
+ if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
+ {
+ if (((((uint32_t)pTxData) & 1U) != 0U) || ((((uint32_t)pRxData) & 1U) != 0U))
+ {
+ return HAL_ERROR;
+ }
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(husart);
+
+ husart->pRxBuffPtr = pRxData;
+ husart->RxXferSize = Size;
+ husart->RxXferCount = Size;
+ husart->pTxBuffPtr = pTxData;
+ husart->TxXferSize = Size;
+ husart->TxXferCount = Size;
+
+ /* Computation of USART mask to apply to RDR register */
+ USART_MASK_COMPUTATION(husart);
+
+ husart->ErrorCode = HAL_USART_ERROR_NONE;
+ husart->State = HAL_USART_STATE_BUSY_TX_RX;
+
+ /* Configure TxRx interrupt processing */
+ if ((husart->FifoMode == USART_FIFOMODE_ENABLE) && (Size >= husart->NbRxDataToProcess))
+ {
+ /* Set the Rx ISR function pointer according to the data word length */
+ if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
+ {
+ husart->TxISR = USART_TxISR_16BIT_FIFOEN;
+ husart->RxISR = USART_RxISR_16BIT_FIFOEN;
+ }
+ else
+ {
+ husart->TxISR = USART_TxISR_8BIT_FIFOEN;
+ husart->RxISR = USART_RxISR_8BIT_FIFOEN;
+ }
+
+ /* Process Locked */
+ __HAL_UNLOCK(husart);
+
+ /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
+ SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
+
+ if (husart->Init.Parity != USART_PARITY_NONE)
+ {
+ /* Enable the USART Parity Error interrupt */
+ SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
+ }
+
+ /* Enable the TX and RX FIFO Threshold interrupts */
+ SET_BIT(husart->Instance->CR3, (USART_CR3_TXFTIE | USART_CR3_RXFTIE));
+ }
+ else
+ {
+ if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
+ {
+ husart->TxISR = USART_TxISR_16BIT;
+ husart->RxISR = USART_RxISR_16BIT;
+ }
+ else
+ {
+ husart->TxISR = USART_TxISR_8BIT;
+ husart->RxISR = USART_RxISR_8BIT;
+ }
+
+ /* Process Locked */
+ __HAL_UNLOCK(husart);
+
+ /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
+ SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
+
+ /* Enable the USART Parity Error and USART Data Register not empty Interrupts */
+ if (husart->Init.Parity != USART_PARITY_NONE)
+ {
+ SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE);
+ }
+ else
+ {
+ SET_BIT(husart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
+ }
+
+ /* Enable the USART Transmit Data Register Empty Interrupt */
+ SET_BIT(husart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
+ }
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Send an amount of data in DMA mode.
+ * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the sent data is handled as a set of u16. In this case, Size must indicate the number
+ * of u16 provided through pTxData.
+ * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits)
+ * (as sent data will be handled by DMA from halfword frontier). Depending on compilation chain,
+ * use of specific alignment compilation directives or pragmas might be required
+ * to ensure proper alignment for pTxData.
+ * @param husart USART handle.
+ * @param pTxData pointer to data buffer (u8 or u16 data elements).
+ * @param Size amount of data elements (u8 or u16) to be sent.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ const uint32_t *tmp;
+
+ if (husart->State == HAL_USART_STATE_READY)
+ {
+ if ((pTxData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* In case of 9bits/No Parity transfer, pTxData buffer provided as input parameter
+ should be aligned on a u16 frontier, as data copy into TDR will be
+ handled by DMA from a u16 frontier. */
+ if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
+ {
+ if ((((uint32_t)pTxData) & 1U) != 0U)
+ {
+ return HAL_ERROR;
+ }
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(husart);
+
+ husart->pTxBuffPtr = pTxData;
+ husart->TxXferSize = Size;
+ husart->TxXferCount = Size;
+
+ husart->ErrorCode = HAL_USART_ERROR_NONE;
+ husart->State = HAL_USART_STATE_BUSY_TX;
+
+ if (husart->hdmatx != NULL)
+ {
+ /* Set the USART DMA transfer complete callback */
+ husart->hdmatx->XferCpltCallback = USART_DMATransmitCplt;
+
+ /* Set the USART DMA Half transfer complete callback */
+ husart->hdmatx->XferHalfCpltCallback = USART_DMATxHalfCplt;
+
+ /* Set the DMA error callback */
+ husart->hdmatx->XferErrorCallback = USART_DMAError;
+
+ /* Enable the USART transmit DMA channel */
+ tmp = (const uint32_t *)&pTxData;
+ status = HAL_DMA_Start_IT(husart->hdmatx, *(const uint32_t *)tmp, (uint32_t)&husart->Instance->TDR, Size);
+ }
+
+ if (status == HAL_OK)
+ {
+ /* Clear the TC flag in the ICR register */
+ __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_TCF);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ /* Enable the DMA transfer for transmit request by setting the DMAT bit
+ in the USART CR3 register */
+ SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+
+ return HAL_OK;
+ }
+ else
+ {
+ /* Set error code to DMA */
+ husart->ErrorCode = HAL_USART_ERROR_DMA;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ /* Restore husart->State to ready */
+ husart->State = HAL_USART_STATE_READY;
+
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in DMA mode.
+ * @note When the USART parity is enabled (PCE = 1), the received data contain
+ * the parity bit (MSB position).
+ * @note The USART DMA transmit channel must be configured in order to generate the clock for the slave.
+ * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the received data is handled as a set of u16. In this case, Size must indicate the number
+ * of u16 available through pRxData.
+ * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * address of user data buffer for storing data to be received, should be aligned on
+ * a half word frontier (16 bits) (as received data will be handled by DMA from halfword frontier).
+ * Depending on compilation chain, use of specific alignment compilation directives or pragmas
+ * might be required to ensure proper alignment for pRxData.
+ * @param husart USART handle.
+ * @param pRxData pointer to data buffer (u8 or u16 data elements).
+ * @param Size amount of data elements (u8 or u16) to be received.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t *tmp = (uint32_t *)&pRxData;
+
+ /* Check that a Rx process is not already ongoing */
+ if (husart->State == HAL_USART_STATE_READY)
+ {
+ if ((pRxData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* In case of 9bits/No Parity transfer, pRxData buffer provided as input parameter
+ should be aligned on a u16 frontier, as data copy from RDR will be
+ handled by DMA from a u16 frontier. */
+ if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
+ {
+ if ((((uint32_t)pRxData) & 1U) != 0U)
+ {
+ return HAL_ERROR;
+ }
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(husart);
+
+ husart->pRxBuffPtr = pRxData;
+ husart->RxXferSize = Size;
+ husart->pTxBuffPtr = pRxData;
+ husart->TxXferSize = Size;
+
+ husart->ErrorCode = HAL_USART_ERROR_NONE;
+ husart->State = HAL_USART_STATE_BUSY_RX;
+
+ if (husart->hdmarx != NULL)
+ {
+ /* Set the USART DMA Rx transfer complete callback */
+ husart->hdmarx->XferCpltCallback = USART_DMAReceiveCplt;
+
+ /* Set the USART DMA Half transfer complete callback */
+ husart->hdmarx->XferHalfCpltCallback = USART_DMARxHalfCplt;
+
+ /* Set the USART DMA Rx transfer error callback */
+ husart->hdmarx->XferErrorCallback = USART_DMAError;
+
+ /* Enable the USART receive DMA channel */
+ status = HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->RDR, *(uint32_t *)tmp, Size);
+ }
+
+ if ((status == HAL_OK) &&
+ (husart->SlaveMode == USART_SLAVEMODE_DISABLE))
+ {
+ /* Enable the USART transmit DMA channel: the transmit channel is used in order
+ to generate in the non-blocking mode the clock to the slave device,
+ this mode isn't a simplex receive mode but a full-duplex receive mode */
+
+ /* Set the USART DMA Tx Complete and Error callback to Null */
+ if (husart->hdmatx != NULL)
+ {
+ husart->hdmatx->XferErrorCallback = NULL;
+ husart->hdmatx->XferHalfCpltCallback = NULL;
+ husart->hdmatx->XferCpltCallback = NULL;
+ status = HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t *)tmp, (uint32_t)&husart->Instance->TDR, Size);
+ }
+ }
+
+ if (status == HAL_OK)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ if (husart->Init.Parity != USART_PARITY_NONE)
+ {
+ /* Enable the USART Parity Error Interrupt */
+ SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
+ }
+
+ /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
+ SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
+
+ /* Enable the DMA transfer for the receiver request by setting the DMAR bit
+ in the USART CR3 register */
+ SET_BIT(husart->Instance->CR3, USART_CR3_DMAR);
+
+ /* Enable the DMA transfer for transmit request by setting the DMAT bit
+ in the USART CR3 register */
+ SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+
+ return HAL_OK;
+ }
+ else
+ {
+ if (husart->hdmarx != NULL)
+ {
+ status = HAL_DMA_Abort(husart->hdmarx);
+ }
+
+ /* No need to check on error code */
+ UNUSED(status);
+
+ /* Set error code to DMA */
+ husart->ErrorCode = HAL_USART_ERROR_DMA;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ /* Restore husart->State to ready */
+ husart->State = HAL_USART_STATE_READY;
+
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Full-Duplex Transmit Receive an amount of data in non-blocking mode.
+ * @note When the USART parity is enabled (PCE = 1) the data received contain the parity bit.
+ * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number
+ * of u16 available through pTxData and through pRxData.
+ * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * address of user data buffers containing data to be sent/received, should be aligned on a half word frontier
+ * (16 bits) (as sent/received data will be handled by DMA from halfword frontier). Depending on compilation
+ * chain, use of specific alignment compilation directives or pragmas might be required
+ * to ensure proper alignment for pTxData and pRxData.
+ * @param husart USART handle.
+ * @param pTxData pointer to TX data buffer (u8 or u16 data elements).
+ * @param pRxData pointer to RX data buffer (u8 or u16 data elements).
+ * @param Size amount of data elements (u8 or u16) to be received/sent.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData,
+ uint16_t Size)
+{
+ HAL_StatusTypeDef status;
+ const uint32_t *tmp;
+
+ if (husart->State == HAL_USART_STATE_READY)
+ {
+ if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* In case of 9bits/No Parity transfer, pTxData and pRxData buffers provided as input parameter
+ should be aligned on a u16 frontier, as data copy to/from TDR/RDR will be
+ handled by DMA from a u16 frontier. */
+ if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
+ {
+ if (((((uint32_t)pTxData) & 1U) != 0U) || ((((uint32_t)pRxData) & 1U) != 0U))
+ {
+ return HAL_ERROR;
+ }
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(husart);
+
+ husart->pRxBuffPtr = pRxData;
+ husart->RxXferSize = Size;
+ husart->pTxBuffPtr = pTxData;
+ husart->TxXferSize = Size;
+
+ husart->ErrorCode = HAL_USART_ERROR_NONE;
+ husart->State = HAL_USART_STATE_BUSY_TX_RX;
+
+ if ((husart->hdmarx != NULL) && (husart->hdmatx != NULL))
+ {
+ /* Set the USART DMA Rx transfer complete callback */
+ husart->hdmarx->XferCpltCallback = USART_DMAReceiveCplt;
+
+ /* Set the USART DMA Half transfer complete callback */
+ husart->hdmarx->XferHalfCpltCallback = USART_DMARxHalfCplt;
+
+ /* Set the USART DMA Tx transfer complete callback */
+ husart->hdmatx->XferCpltCallback = USART_DMATransmitCplt;
+
+ /* Set the USART DMA Half transfer complete callback */
+ husart->hdmatx->XferHalfCpltCallback = USART_DMATxHalfCplt;
+
+ /* Set the USART DMA Tx transfer error callback */
+ husart->hdmatx->XferErrorCallback = USART_DMAError;
+
+ /* Set the USART DMA Rx transfer error callback */
+ husart->hdmarx->XferErrorCallback = USART_DMAError;
+
+ /* Enable the USART receive DMA channel */
+ tmp = (uint32_t *)&pRxData;
+ status = HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->RDR, *(const uint32_t *)tmp, Size);
+
+ /* Enable the USART transmit DMA channel */
+ if (status == HAL_OK)
+ {
+ tmp = (const uint32_t *)&pTxData;
+ status = HAL_DMA_Start_IT(husart->hdmatx, *(const uint32_t *)tmp, (uint32_t)&husart->Instance->TDR, Size);
+ }
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+
+ if (status == HAL_OK)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ if (husart->Init.Parity != USART_PARITY_NONE)
+ {
+ /* Enable the USART Parity Error Interrupt */
+ SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
+ }
+
+ /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
+ SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
+
+ /* Clear the TC flag in the ICR register */
+ __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_TCF);
+
+ /* Enable the DMA transfer for the receiver request by setting the DMAR bit
+ in the USART CR3 register */
+ SET_BIT(husart->Instance->CR3, USART_CR3_DMAR);
+
+ /* Enable the DMA transfer for transmit request by setting the DMAT bit
+ in the USART CR3 register */
+ SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+
+ return HAL_OK;
+ }
+ else
+ {
+ if (husart->hdmarx != NULL)
+ {
+ status = HAL_DMA_Abort(husart->hdmarx);
+ }
+
+ /* No need to check on error code */
+ UNUSED(status);
+
+ /* Set error code to DMA */
+ husart->ErrorCode = HAL_USART_ERROR_DMA;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ /* Restore husart->State to ready */
+ husart->State = HAL_USART_STATE_READY;
+
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Pause the DMA Transfer.
+ * @param husart USART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart)
+{
+ const HAL_USART_StateTypeDef state = husart->State;
+
+ /* Process Locked */
+ __HAL_LOCK(husart);
+
+ if ((HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT)) &&
+ (state == HAL_USART_STATE_BUSY_TX))
+ {
+ /* Disable the USART DMA Tx request */
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+ }
+ else if ((state == HAL_USART_STATE_BUSY_RX) ||
+ (state == HAL_USART_STATE_BUSY_TX_RX))
+ {
+ if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
+ {
+ /* Disable the USART DMA Tx request */
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+ }
+ if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
+ {
+ /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE);
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
+
+ /* Disable the USART DMA Rx request */
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
+ }
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Resume the DMA Transfer.
+ * @param husart USART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart)
+{
+ const HAL_USART_StateTypeDef state = husart->State;
+
+ /* Process Locked */
+ __HAL_LOCK(husart);
+
+ if (state == HAL_USART_STATE_BUSY_TX)
+ {
+ /* Enable the USART DMA Tx request */
+ SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+ }
+ else if ((state == HAL_USART_STATE_BUSY_RX) ||
+ (state == HAL_USART_STATE_BUSY_TX_RX))
+ {
+ /* Clear the Overrun flag before resuming the Rx transfer*/
+ __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF);
+
+ /* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */
+ if (husart->Init.Parity != USART_PARITY_NONE)
+ {
+ SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
+ }
+ SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
+
+ /* Enable the USART DMA Rx request before the DMA Tx request */
+ SET_BIT(husart->Instance->CR3, USART_CR3_DMAR);
+
+ /* Enable the USART DMA Tx request */
+ SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Stop the DMA Transfer.
+ * @param husart USART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart)
+{
+ /* The Lock is not implemented on this API to allow the user application
+ to call the HAL USART API under callbacks HAL_USART_TxCpltCallback() / HAL_USART_RxCpltCallback() /
+ HAL_USART_TxHalfCpltCallback / HAL_USART_RxHalfCpltCallback:
+ indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete
+ interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of
+ the stream and the corresponding call back is executed. */
+
+ /* Disable the USART Tx/Rx DMA requests */
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the USART DMA tx channel */
+ if (husart->hdmatx != NULL)
+ {
+ if (HAL_DMA_Abort(husart->hdmatx) != HAL_OK)
+ {
+ if (HAL_DMA_GetError(husart->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
+ {
+ /* Set error code to DMA */
+ husart->ErrorCode = HAL_USART_ERROR_DMA;
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ /* Abort the USART DMA rx channel */
+ if (husart->hdmarx != NULL)
+ {
+ if (HAL_DMA_Abort(husart->hdmarx) != HAL_OK)
+ {
+ if (HAL_DMA_GetError(husart->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
+ {
+ /* Set error code to DMA */
+ husart->ErrorCode = HAL_USART_ERROR_DMA;
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ USART_EndTransfer(husart);
+ husart->State = HAL_USART_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing transfers (blocking mode).
+ * @param husart USART handle.
+ * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable USART Interrupts (Tx and Rx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart)
+{
+ /* Disable TXEIE, TCIE, RXNE, RXFT, TXFT, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE |
+ USART_CR1_TCIE));
+ CLEAR_BIT(husart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE));
+
+ /* Abort the USART DMA Tx channel if enabled */
+ if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
+ {
+ /* Disable the USART DMA Tx request if enabled */
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the USART DMA Tx channel : use blocking DMA Abort API (no callback) */
+ if (husart->hdmatx != NULL)
+ {
+ /* Set the USART DMA Abort callback to Null.
+ No call back execution at end of DMA abort procedure */
+ husart->hdmatx->XferAbortCallback = NULL;
+
+ if (HAL_DMA_Abort(husart->hdmatx) != HAL_OK)
+ {
+ if (HAL_DMA_GetError(husart->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
+ {
+ /* Set error code to DMA */
+ husart->ErrorCode = HAL_USART_ERROR_DMA;
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+
+ /* Abort the USART DMA Rx channel if enabled */
+ if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
+ {
+ /* Disable the USART DMA Rx request if enabled */
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the USART DMA Rx channel : use blocking DMA Abort API (no callback) */
+ if (husart->hdmarx != NULL)
+ {
+ /* Set the USART DMA Abort callback to Null.
+ No call back execution at end of DMA abort procedure */
+ husart->hdmarx->XferAbortCallback = NULL;
+
+ if (HAL_DMA_Abort(husart->hdmarx) != HAL_OK)
+ {
+ if (HAL_DMA_GetError(husart->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
+ {
+ /* Set error code to DMA */
+ husart->ErrorCode = HAL_USART_ERROR_DMA;
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+
+ /* Reset Tx and Rx transfer counters */
+ husart->TxXferCount = 0U;
+ husart->RxXferCount = 0U;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF);
+
+ /* Flush the whole TX FIFO (if needed) */
+ if (husart->FifoMode == USART_FIFOMODE_ENABLE)
+ {
+ __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST);
+ }
+
+ /* Discard the received data */
+ __HAL_USART_SEND_REQ(husart, USART_RXDATA_FLUSH_REQUEST);
+
+ /* Restore husart->State to Ready */
+ husart->State = HAL_USART_STATE_READY;
+
+ /* Reset Handle ErrorCode to No Error */
+ husart->ErrorCode = HAL_USART_ERROR_NONE;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing transfers (Interrupt mode).
+ * @param husart USART handle.
+ * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable USART Interrupts (Tx and Rx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * - At abort completion, call user abort complete callback
+ * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
+ * considered as completed only when user abort complete callback is executed (not when exiting function).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart)
+{
+ uint32_t abortcplt = 1U;
+
+ /* Disable TXEIE, TCIE, RXNE, RXFT, TXFT, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE |
+ USART_CR1_TCIE));
+ CLEAR_BIT(husart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE));
+
+ /* If DMA Tx and/or DMA Rx Handles are associated to USART Handle, DMA Abort complete callbacks should be initialised
+ before any call to DMA Abort functions */
+ /* DMA Tx Handle is valid */
+ if (husart->hdmatx != NULL)
+ {
+ /* Set DMA Abort Complete callback if USART DMA Tx request if enabled.
+ Otherwise, set it to NULL */
+ if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
+ {
+ husart->hdmatx->XferAbortCallback = USART_DMATxAbortCallback;
+ }
+ else
+ {
+ husart->hdmatx->XferAbortCallback = NULL;
+ }
+ }
+ /* DMA Rx Handle is valid */
+ if (husart->hdmarx != NULL)
+ {
+ /* Set DMA Abort Complete callback if USART DMA Rx request if enabled.
+ Otherwise, set it to NULL */
+ if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
+ {
+ husart->hdmarx->XferAbortCallback = USART_DMARxAbortCallback;
+ }
+ else
+ {
+ husart->hdmarx->XferAbortCallback = NULL;
+ }
+ }
+
+ /* Abort the USART DMA Tx channel if enabled */
+ if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
+ {
+ /* Disable DMA Tx at USART level */
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the USART DMA Tx channel : use non blocking DMA Abort API (callback) */
+ if (husart->hdmatx != NULL)
+ {
+ /* USART Tx DMA Abort callback has already been initialised :
+ will lead to call HAL_USART_AbortCpltCallback() at end of DMA abort procedure */
+
+ /* Abort DMA TX */
+ if (HAL_DMA_Abort_IT(husart->hdmatx) != HAL_OK)
+ {
+ husart->hdmatx->XferAbortCallback = NULL;
+ }
+ else
+ {
+ abortcplt = 0U;
+ }
+ }
+ }
+
+ /* Abort the USART DMA Rx channel if enabled */
+ if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
+ {
+ /* Disable the USART DMA Rx request if enabled */
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the USART DMA Rx channel : use non blocking DMA Abort API (callback) */
+ if (husart->hdmarx != NULL)
+ {
+ /* USART Rx DMA Abort callback has already been initialised :
+ will lead to call HAL_USART_AbortCpltCallback() at end of DMA abort procedure */
+
+ /* Abort DMA RX */
+ if (HAL_DMA_Abort_IT(husart->hdmarx) != HAL_OK)
+ {
+ husart->hdmarx->XferAbortCallback = NULL;
+ abortcplt = 1U;
+ }
+ else
+ {
+ abortcplt = 0U;
+ }
+ }
+ }
+
+ /* if no DMA abort complete callback execution is required => call user Abort Complete callback */
+ if (abortcplt == 1U)
+ {
+ /* Reset Tx and Rx transfer counters */
+ husart->TxXferCount = 0U;
+ husart->RxXferCount = 0U;
+
+ /* Reset errorCode */
+ husart->ErrorCode = HAL_USART_ERROR_NONE;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF);
+
+ /* Flush the whole TX FIFO (if needed) */
+ if (husart->FifoMode == USART_FIFOMODE_ENABLE)
+ {
+ __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST);
+ }
+
+ /* Discard the received data */
+ __HAL_USART_SEND_REQ(husart, USART_RXDATA_FLUSH_REQUEST);
+
+ /* Restore husart->State to Ready */
+ husart->State = HAL_USART_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Complete Callback */
+ husart->AbortCpltCallback(husart);
+#else
+ /* Call legacy weak Abort Complete Callback */
+ HAL_USART_AbortCpltCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle USART interrupt request.
+ * @param husart USART handle.
+ * @retval None
+ */
+void HAL_USART_IRQHandler(USART_HandleTypeDef *husart)
+{
+ uint32_t isrflags = READ_REG(husart->Instance->ISR);
+ uint32_t cr1its = READ_REG(husart->Instance->CR1);
+ uint32_t cr3its = READ_REG(husart->Instance->CR3);
+
+ uint32_t errorflags;
+ uint32_t errorcode;
+
+ /* If no error occurs */
+ errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF |
+ USART_ISR_UDR));
+ if (errorflags == 0U)
+ {
+ /* USART in mode Receiver ---------------------------------------------------*/
+ if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U)
+ && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)
+ || ((cr3its & USART_CR3_RXFTIE) != 0U)))
+ {
+ if (husart->RxISR != NULL)
+ {
+ husart->RxISR(husart);
+ }
+ return;
+ }
+ }
+
+ /* If some errors occur */
+ if ((errorflags != 0U)
+ && (((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U)
+ || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)) != 0U)))
+ {
+ /* USART parity error interrupt occurred -------------------------------------*/
+ if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
+ {
+ __HAL_USART_CLEAR_IT(husart, USART_CLEAR_PEF);
+
+ husart->ErrorCode |= HAL_USART_ERROR_PE;
+ }
+
+ /* USART frame error interrupt occurred --------------------------------------*/
+ if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
+ {
+ __HAL_USART_CLEAR_IT(husart, USART_CLEAR_FEF);
+
+ husart->ErrorCode |= HAL_USART_ERROR_FE;
+ }
+
+ /* USART noise error interrupt occurred --------------------------------------*/
+ if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
+ {
+ __HAL_USART_CLEAR_IT(husart, USART_CLEAR_NEF);
+
+ husart->ErrorCode |= HAL_USART_ERROR_NE;
+ }
+
+ /* USART Over-Run interrupt occurred -----------------------------------------*/
+ if (((isrflags & USART_ISR_ORE) != 0U)
+ && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) ||
+ ((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U)))
+ {
+ __HAL_USART_CLEAR_IT(husart, USART_CLEAR_OREF);
+
+ husart->ErrorCode |= HAL_USART_ERROR_ORE;
+ }
+
+ /* USART Receiver Timeout interrupt occurred ---------------------------------*/
+ if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U))
+ {
+ __HAL_USART_CLEAR_IT(husart, USART_CLEAR_RTOF);
+
+ husart->ErrorCode |= HAL_USART_ERROR_RTO;
+ }
+
+ /* USART SPI slave underrun error interrupt occurred -------------------------*/
+ if (((isrflags & USART_ISR_UDR) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
+ {
+ /* Ignore SPI slave underrun errors when reception is going on */
+ if (husart->State == HAL_USART_STATE_BUSY_RX)
+ {
+ __HAL_USART_CLEAR_UDRFLAG(husart);
+ return;
+ }
+ else
+ {
+ __HAL_USART_CLEAR_UDRFLAG(husart);
+ husart->ErrorCode |= HAL_USART_ERROR_UDR;
+ }
+ }
+
+ /* Call USART Error Call back function if need be --------------------------*/
+ if (husart->ErrorCode != HAL_USART_ERROR_NONE)
+ {
+ /* USART in mode Receiver ---------------------------------------------------*/
+ if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U)
+ && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)
+ || ((cr3its & USART_CR3_RXFTIE) != 0U)))
+ {
+ if (husart->RxISR != NULL)
+ {
+ husart->RxISR(husart);
+ }
+ }
+
+ /* If Overrun error occurs, or if any error occurs in DMA mode reception,
+ consider error as blocking */
+ errorcode = husart->ErrorCode & HAL_USART_ERROR_ORE;
+ if ((HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)) ||
+ (errorcode != 0U))
+ {
+ /* Blocking error : transfer is aborted
+ Set the USART state ready to be able to start again the process,
+ Disable Interrupts, and disable DMA requests, if ongoing */
+ USART_EndTransfer(husart);
+
+ /* Abort the USART DMA Rx channel if enabled */
+ if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
+ {
+ /* Disable the USART DMA Rx request if enabled */
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR | USART_CR3_DMAR);
+
+ /* Abort the USART DMA Tx channel */
+ if (husart->hdmatx != NULL)
+ {
+ /* Set the USART Tx DMA Abort callback to NULL : no callback
+ executed at end of DMA abort procedure */
+ husart->hdmatx->XferAbortCallback = NULL;
+
+ /* Abort DMA TX */
+ (void)HAL_DMA_Abort_IT(husart->hdmatx);
+ }
+
+ /* Abort the USART DMA Rx channel */
+ if (husart->hdmarx != NULL)
+ {
+ /* Set the USART Rx DMA Abort callback :
+ will lead to call HAL_USART_ErrorCallback() at end of DMA abort procedure */
+ husart->hdmarx->XferAbortCallback = USART_DMAAbortOnError;
+
+ /* Abort DMA RX */
+ if (HAL_DMA_Abort_IT(husart->hdmarx) != HAL_OK)
+ {
+ /* Call Directly husart->hdmarx->XferAbortCallback function in case of error */
+ husart->hdmarx->XferAbortCallback(husart->hdmarx);
+ }
+ }
+ else
+ {
+ /* Call user error callback */
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ /* Call registered Error Callback */
+ husart->ErrorCallback(husart);
+#else
+ /* Call legacy weak Error Callback */
+ HAL_USART_ErrorCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+ }
+ }
+ else
+ {
+ /* Call user error callback */
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ /* Call registered Error Callback */
+ husart->ErrorCallback(husart);
+#else
+ /* Call legacy weak Error Callback */
+ HAL_USART_ErrorCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+ }
+ }
+ else
+ {
+ /* Non Blocking error : transfer could go on.
+ Error is notified to user through user error callback */
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ /* Call registered Error Callback */
+ husart->ErrorCallback(husart);
+#else
+ /* Call legacy weak Error Callback */
+ HAL_USART_ErrorCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+ husart->ErrorCode = HAL_USART_ERROR_NONE;
+ }
+ }
+ return;
+
+ } /* End if some error occurs */
+
+
+ /* USART in mode Transmitter ------------------------------------------------*/
+ if (((isrflags & USART_ISR_TXE_TXFNF) != 0U)
+ && (((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U)
+ || ((cr3its & USART_CR3_TXFTIE) != 0U)))
+ {
+ if (husart->TxISR != NULL)
+ {
+ husart->TxISR(husart);
+ }
+ return;
+ }
+
+ /* USART in mode Transmitter (transmission end) -----------------------------*/
+ if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U))
+ {
+ USART_EndTransmit_IT(husart);
+ return;
+ }
+
+ /* USART TX Fifo Empty occurred ----------------------------------------------*/
+ if (((isrflags & USART_ISR_TXFE) != 0U) && ((cr1its & USART_CR1_TXFEIE) != 0U))
+ {
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ /* Call registered Tx Fifo Empty Callback */
+ husart->TxFifoEmptyCallback(husart);
+#else
+ /* Call legacy weak Tx Fifo Empty Callback */
+ HAL_USARTEx_TxFifoEmptyCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+ return;
+ }
+
+ /* USART RX Fifo Full occurred ----------------------------------------------*/
+ if (((isrflags & USART_ISR_RXFF) != 0U) && ((cr1its & USART_CR1_RXFFIE) != 0U))
+ {
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ /* Call registered Rx Fifo Full Callback */
+ husart->RxFifoFullCallback(husart);
+#else
+ /* Call legacy weak Rx Fifo Full Callback */
+ HAL_USARTEx_RxFifoFullCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+ return;
+ }
+}
+
+/**
+ * @brief Tx Transfer completed callback.
+ * @param husart USART handle.
+ * @retval None
+ */
+__weak void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(husart);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_USART_TxCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief Tx Half Transfer completed callback.
+ * @param husart USART handle.
+ * @retval None
+ */
+__weak void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(husart);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_USART_TxHalfCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief Rx Transfer completed callback.
+ * @param husart USART handle.
+ * @retval None
+ */
+__weak void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(husart);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_USART_RxCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief Rx Half Transfer completed callback.
+ * @param husart USART handle.
+ * @retval None
+ */
+__weak void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(husart);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_USART_RxHalfCpltCallback can be implemented in the user file
+ */
+}
+
+/**
+ * @brief Tx/Rx Transfers completed callback for the non-blocking process.
+ * @param husart USART handle.
+ * @retval None
+ */
+__weak void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(husart);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_USART_TxRxCpltCallback can be implemented in the user file
+ */
+}
+
+/**
+ * @brief USART error callback.
+ * @param husart USART handle.
+ * @retval None
+ */
+__weak void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(husart);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_USART_ErrorCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief USART Abort Complete callback.
+ * @param husart USART handle.
+ * @retval None
+ */
+__weak void HAL_USART_AbortCpltCallback(USART_HandleTypeDef *husart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(husart);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_USART_AbortCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_Exported_Functions_Group4 Peripheral State and Error functions
+ * @brief USART Peripheral State and Error functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral State and Error functions #####
+ ==============================================================================
+ [..]
+ This subsection provides functions allowing to :
+ (+) Return the USART handle state
+ (+) Return the USART handle error code
+
+@endverbatim
+ * @{
+ */
+
+
+/**
+ * @brief Return the USART handle state.
+ * @param husart pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART.
+ * @retval USART handle state
+ */
+HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart)
+{
+ return husart->State;
+}
+
+/**
+ * @brief Return the USART error code.
+ * @param husart pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART.
+ * @retval USART handle Error Code
+ */
+uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart)
+{
+ return husart->ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_Private_Functions USART Private Functions
+ * @{
+ */
+
+/**
+ * @brief Initialize the callbacks to their default values.
+ * @param husart USART handle.
+ * @retval none
+ */
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+void USART_InitCallbacksToDefault(USART_HandleTypeDef *husart)
+{
+ /* Init the USART Callback settings */
+ husart->TxHalfCpltCallback = HAL_USART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
+ husart->TxCpltCallback = HAL_USART_TxCpltCallback; /* Legacy weak TxCpltCallback */
+ husart->RxHalfCpltCallback = HAL_USART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
+ husart->RxCpltCallback = HAL_USART_RxCpltCallback; /* Legacy weak RxCpltCallback */
+ husart->TxRxCpltCallback = HAL_USART_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */
+ husart->ErrorCallback = HAL_USART_ErrorCallback; /* Legacy weak ErrorCallback */
+ husart->AbortCpltCallback = HAL_USART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
+ husart->RxFifoFullCallback = HAL_USARTEx_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */
+ husart->TxFifoEmptyCallback = HAL_USARTEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */
+}
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+
+/**
+ * @brief End ongoing transfer on USART peripheral (following error detection or Transfer completion).
+ * @param husart USART handle.
+ * @retval None
+ */
+static void USART_EndTransfer(USART_HandleTypeDef *husart)
+{
+ /* Disable TXEIE, TCIE, RXNE, RXFT, TXFT, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE |
+ USART_CR1_TCIE));
+ CLEAR_BIT(husart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE));
+
+ /* At end of process, restore husart->State to Ready */
+ husart->State = HAL_USART_STATE_READY;
+}
+
+/**
+ * @brief DMA USART transmit process complete callback.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
+{
+ USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent);
+
+ /* DMA Normal mode */
+ if (HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC))
+ {
+ husart->TxXferCount = 0U;
+
+ if (husart->State == HAL_USART_STATE_BUSY_TX)
+ {
+ /* Disable the DMA transfer for transmit request by resetting the DMAT bit
+ in the USART CR3 register */
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+
+ /* Enable the USART Transmit Complete Interrupt */
+ __HAL_USART_ENABLE_IT(husart, USART_IT_TC);
+ }
+ }
+ /* DMA Circular mode */
+ else
+ {
+ if (husart->State == HAL_USART_STATE_BUSY_TX)
+ {
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ /* Call registered Tx Complete Callback */
+ husart->TxCpltCallback(husart);
+#else
+ /* Call legacy weak Tx Complete Callback */
+ HAL_USART_TxCpltCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+ }
+ }
+}
+
+/**
+ * @brief DMA USART transmit process half complete callback.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+ USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent);
+
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ /* Call registered Tx Half Complete Callback */
+ husart->TxHalfCpltCallback(husart);
+#else
+ /* Call legacy weak Tx Half Complete Callback */
+ HAL_USART_TxHalfCpltCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief DMA USART receive process complete callback.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+ USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent);
+
+ /* DMA Normal mode */
+ if (HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC))
+ {
+ husart->RxXferCount = 0U;
+
+ /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE);
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
+
+ /* Disable the DMA RX transfer for the receiver request by resetting the DMAR bit
+ in USART CR3 register */
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
+ /* similarly, disable the DMA TX transfer that was started to provide the
+ clock to the slave device */
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+
+ if (husart->State == HAL_USART_STATE_BUSY_RX)
+ {
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ /* Call registered Rx Complete Callback */
+ husart->RxCpltCallback(husart);
+#else
+ /* Call legacy weak Rx Complete Callback */
+ HAL_USART_RxCpltCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+ }
+ /* The USART state is HAL_USART_STATE_BUSY_TX_RX */
+ else
+ {
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ /* Call registered Tx Rx Complete Callback */
+ husart->TxRxCpltCallback(husart);
+#else
+ /* Call legacy weak Tx Rx Complete Callback */
+ HAL_USART_TxRxCpltCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+ }
+ husart->State = HAL_USART_STATE_READY;
+ }
+ /* DMA circular mode */
+ else
+ {
+ if (husart->State == HAL_USART_STATE_BUSY_RX)
+ {
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ /* Call registered Rx Complete Callback */
+ husart->RxCpltCallback(husart);
+#else
+ /* Call legacy weak Rx Complete Callback */
+ HAL_USART_RxCpltCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+ }
+ /* The USART state is HAL_USART_STATE_BUSY_TX_RX */
+ else
+ {
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ /* Call registered Tx Rx Complete Callback */
+ husart->TxRxCpltCallback(husart);
+#else
+ /* Call legacy weak Tx Rx Complete Callback */
+ HAL_USART_TxRxCpltCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+ }
+ }
+}
+
+/**
+ * @brief DMA USART receive process half complete callback.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+ USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent);
+
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ /* Call registered Rx Half Complete Callback */
+ husart->RxHalfCpltCallback(husart);
+#else
+ /* Call legacy weak Rx Half Complete Callback */
+ HAL_USART_RxHalfCpltCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief DMA USART communication error callback.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void USART_DMAError(DMA_HandleTypeDef *hdma)
+{
+ USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent);
+
+ husart->RxXferCount = 0U;
+ husart->TxXferCount = 0U;
+ USART_EndTransfer(husart);
+
+ husart->ErrorCode |= HAL_USART_ERROR_DMA;
+ husart->State = HAL_USART_STATE_READY;
+
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ /* Call registered Error Callback */
+ husart->ErrorCallback(husart);
+#else
+ /* Call legacy weak Error Callback */
+ HAL_USART_ErrorCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief DMA USART communication abort callback, when initiated by HAL services on Error
+ * (To be called at end of DMA Abort procedure following error occurrence).
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void USART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
+{
+ USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent);
+ husart->RxXferCount = 0U;
+ husart->TxXferCount = 0U;
+
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ /* Call registered Error Callback */
+ husart->ErrorCallback(husart);
+#else
+ /* Call legacy weak Error Callback */
+ HAL_USART_ErrorCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief DMA USART Tx communication abort callback, when initiated by user
+ * (To be called at end of DMA Tx Abort procedure following user abort request).
+ * @note When this callback is executed, User Abort complete call back is called only if no
+ * Abort still ongoing for Rx DMA Handle.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void USART_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent);
+
+ husart->hdmatx->XferAbortCallback = NULL;
+
+ /* Check if an Abort process is still ongoing */
+ if (husart->hdmarx != NULL)
+ {
+ if (husart->hdmarx->XferAbortCallback != NULL)
+ {
+ return;
+ }
+ }
+
+ /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
+ husart->TxXferCount = 0U;
+ husart->RxXferCount = 0U;
+
+ /* Reset errorCode */
+ husart->ErrorCode = HAL_USART_ERROR_NONE;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF);
+
+ /* Restore husart->State to Ready */
+ husart->State = HAL_USART_STATE_READY;
+
+ /* Call user Abort complete callback */
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Complete Callback */
+ husart->AbortCpltCallback(husart);
+#else
+ /* Call legacy weak Abort Complete Callback */
+ HAL_USART_AbortCpltCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+
+}
+
+
+/**
+ * @brief DMA USART Rx communication abort callback, when initiated by user
+ * (To be called at end of DMA Rx Abort procedure following user abort request).
+ * @note When this callback is executed, User Abort complete call back is called only if no
+ * Abort still ongoing for Tx DMA Handle.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void USART_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent);
+
+ husart->hdmarx->XferAbortCallback = NULL;
+
+ /* Check if an Abort process is still ongoing */
+ if (husart->hdmatx != NULL)
+ {
+ if (husart->hdmatx->XferAbortCallback != NULL)
+ {
+ return;
+ }
+ }
+
+ /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
+ husart->TxXferCount = 0U;
+ husart->RxXferCount = 0U;
+
+ /* Reset errorCode */
+ husart->ErrorCode = HAL_USART_ERROR_NONE;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF);
+
+ /* Restore husart->State to Ready */
+ husart->State = HAL_USART_STATE_READY;
+
+ /* Call user Abort complete callback */
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Complete Callback */
+ husart->AbortCpltCallback(husart);
+#else
+ /* Call legacy weak Abort Complete Callback */
+ HAL_USART_AbortCpltCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+}
+
+
+/**
+ * @brief Handle USART Communication Timeout. It waits
+ * until a flag is no longer in the specified status.
+ * @param husart USART handle.
+ * @param Flag Specifies the USART flag to check.
+ * @param Status the actual Flag status (SET or RESET).
+ * @param Tickstart Tick start value
+ * @param Timeout timeout duration.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status,
+ uint32_t Tickstart, uint32_t Timeout)
+{
+ /* Wait until flag is set */
+ while ((__HAL_USART_GET_FLAG(husart, Flag) ? SET : RESET) == Status)
+ {
+ /* Check for the Timeout */
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
+ {
+ husart->State = HAL_USART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief Configure the USART peripheral.
+ * @param husart USART handle.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart)
+{
+ uint32_t tmpreg;
+ USART_ClockSourceTypeDef clocksource;
+ HAL_StatusTypeDef ret = HAL_OK;
+ uint16_t brrtemp;
+ uint32_t usartdiv = 0x00000000;
+ uint32_t pclk;
+
+ /* Check the parameters */
+ assert_param(IS_USART_POLARITY(husart->Init.CLKPolarity));
+ assert_param(IS_USART_PHASE(husart->Init.CLKPhase));
+ assert_param(IS_USART_LASTBIT(husart->Init.CLKLastBit));
+ assert_param(IS_USART_BAUDRATE(husart->Init.BaudRate));
+ assert_param(IS_USART_WORD_LENGTH(husart->Init.WordLength));
+ assert_param(IS_USART_STOPBITS(husart->Init.StopBits));
+ assert_param(IS_USART_PARITY(husart->Init.Parity));
+ assert_param(IS_USART_MODE(husart->Init.Mode));
+ assert_param(IS_USART_PRESCALER(husart->Init.ClockPrescaler));
+
+ /*-------------------------- USART CR1 Configuration -----------------------*/
+ /* Clear M, PCE, PS, TE and RE bits and configure
+ * the USART Word Length, Parity and Mode:
+ * set the M bits according to husart->Init.WordLength value
+ * set PCE and PS bits according to husart->Init.Parity value
+ * set TE and RE bits according to husart->Init.Mode value
+ * force OVER8 to 1 to allow to reach the maximum speed (Fclock/8) */
+ tmpreg = (uint32_t)husart->Init.WordLength | husart->Init.Parity | husart->Init.Mode | USART_CR1_OVER8;
+ MODIFY_REG(husart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
+
+ /*---------------------------- USART CR2 Configuration ---------------------*/
+ /* Clear and configure the USART Clock, CPOL, CPHA, LBCL STOP and SLVEN bits:
+ * set CPOL bit according to husart->Init.CLKPolarity value
+ * set CPHA bit according to husart->Init.CLKPhase value
+ * set LBCL bit according to husart->Init.CLKLastBit value (used in SPI master mode only)
+ * set STOP[13:12] bits according to husart->Init.StopBits value */
+ tmpreg = (uint32_t)(USART_CLOCK_ENABLE);
+ tmpreg |= (uint32_t)husart->Init.CLKLastBit;
+ tmpreg |= ((uint32_t)husart->Init.CLKPolarity | (uint32_t)husart->Init.CLKPhase);
+ tmpreg |= (uint32_t)husart->Init.StopBits;
+ MODIFY_REG(husart->Instance->CR2, USART_CR2_FIELDS, tmpreg);
+
+ /*-------------------------- USART PRESC Configuration -----------------------*/
+ /* Configure
+ * - USART Clock Prescaler : set PRESCALER according to husart->Init.ClockPrescaler value */
+ MODIFY_REG(husart->Instance->PRESC, USART_PRESC_PRESCALER, husart->Init.ClockPrescaler);
+
+ /*-------------------------- USART BRR Configuration -----------------------*/
+ /* BRR is filled-up according to OVER8 bit setting which is forced to 1 */
+ USART_GETCLOCKSOURCE(husart, clocksource);
+
+ switch (clocksource)
+ {
+ case USART_CLOCKSOURCE_PCLK1:
+ pclk = HAL_RCC_GetPCLK1Freq();
+ usartdiv = (uint32_t)(USART_DIV_SAMPLING8(pclk, husart->Init.BaudRate, husart->Init.ClockPrescaler));
+ break;
+ case USART_CLOCKSOURCE_HSI:
+ pclk = (HSI_VALUE / ((__HAL_RCC_GET_HSIKER_DIVIDER() >> RCC_CR_HSIKERDIV_Pos) + 1U));
+ usartdiv = (uint32_t)(USART_DIV_SAMPLING8(pclk, husart->Init.BaudRate, husart->Init.ClockPrescaler));
+ break;
+ case USART_CLOCKSOURCE_SYSCLK:
+ pclk = HAL_RCC_GetSysClockFreq();
+ usartdiv = (uint32_t)(USART_DIV_SAMPLING8(pclk, husart->Init.BaudRate, husart->Init.ClockPrescaler));
+ break;
+ case USART_CLOCKSOURCE_LSE:
+ usartdiv = (uint32_t)(USART_DIV_SAMPLING8(LSE_VALUE, husart->Init.BaudRate, husart->Init.ClockPrescaler));
+ break;
+ default:
+ ret = HAL_ERROR;
+ break;
+ }
+
+ /* USARTDIV must be greater than or equal to 0d16 and smaller than or equal to ffff */
+ if ((usartdiv >= USART_BRR_MIN) && (usartdiv <= USART_BRR_MAX))
+ {
+ brrtemp = (uint16_t)(usartdiv & 0xFFF0U);
+ brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
+ husart->Instance->BRR = brrtemp;
+ }
+ else
+ {
+ ret = HAL_ERROR;
+ }
+
+ /* Initialize the number of data to process during RX/TX ISR execution */
+ husart->NbTxDataToProcess = 1U;
+ husart->NbRxDataToProcess = 1U;
+
+ /* Clear ISR function pointers */
+ husart->RxISR = NULL;
+ husart->TxISR = NULL;
+
+ return ret;
+}
+
+/**
+ * @brief Check the USART Idle State.
+ * @param husart USART handle.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart)
+{
+ uint32_t tickstart;
+
+ /* Initialize the USART ErrorCode */
+ husart->ErrorCode = HAL_USART_ERROR_NONE;
+
+ /* Init tickstart for timeout management */
+ tickstart = HAL_GetTick();
+
+ /* Check if the Transmitter is enabled */
+ if ((husart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
+ {
+ /* Wait until TEACK flag is set */
+ if (USART_WaitOnFlagUntilTimeout(husart, USART_ISR_TEACK, RESET, tickstart, USART_TEACK_REACK_TIMEOUT) != HAL_OK)
+ {
+ /* Timeout occurred */
+ return HAL_TIMEOUT;
+ }
+ }
+ /* Check if the Receiver is enabled */
+ if ((husart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
+ {
+ /* Wait until REACK flag is set */
+ if (USART_WaitOnFlagUntilTimeout(husart, USART_ISR_REACK, RESET, tickstart, USART_TEACK_REACK_TIMEOUT) != HAL_OK)
+ {
+ /* Timeout occurred */
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Initialize the USART state*/
+ husart->State = HAL_USART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Simplex send an amount of data in non-blocking mode.
+ * @note Function called under interruption only, once
+ * interruptions have been enabled by HAL_USART_Transmit_IT().
+ * @note The USART errors are not managed to avoid the overrun error.
+ * @note ISR function executed when FIFO mode is disabled and when the
+ * data word length is less than 9 bits long.
+ * @param husart USART handle.
+ * @retval None
+ */
+static void USART_TxISR_8BIT(USART_HandleTypeDef *husart)
+{
+ const HAL_USART_StateTypeDef state = husart->State;
+
+ /* Check that a Tx process is ongoing */
+ if ((state == HAL_USART_STATE_BUSY_TX) ||
+ (state == HAL_USART_STATE_BUSY_TX_RX))
+ {
+ if (husart->TxXferCount == 0U)
+ {
+ /* Disable the USART Transmit data register empty interrupt */
+ __HAL_USART_DISABLE_IT(husart, USART_IT_TXE);
+
+ /* Enable the USART Transmit Complete Interrupt */
+ __HAL_USART_ENABLE_IT(husart, USART_IT_TC);
+ }
+ else
+ {
+ husart->Instance->TDR = (uint8_t)(*husart->pTxBuffPtr & (uint8_t)0xFF);
+ husart->pTxBuffPtr++;
+ husart->TxXferCount--;
+ }
+ }
+}
+
+/**
+ * @brief Simplex send an amount of data in non-blocking mode.
+ * @note Function called under interruption only, once
+ * interruptions have been enabled by HAL_USART_Transmit_IT().
+ * @note The USART errors are not managed to avoid the overrun error.
+ * @note ISR function executed when FIFO mode is disabled and when the
+ * data word length is 9 bits long.
+ * @param husart USART handle.
+ * @retval None
+ */
+static void USART_TxISR_16BIT(USART_HandleTypeDef *husart)
+{
+ const HAL_USART_StateTypeDef state = husart->State;
+ const uint16_t *tmp;
+
+ if ((state == HAL_USART_STATE_BUSY_TX) ||
+ (state == HAL_USART_STATE_BUSY_TX_RX))
+ {
+ if (husart->TxXferCount == 0U)
+ {
+ /* Disable the USART Transmit data register empty interrupt */
+ __HAL_USART_DISABLE_IT(husart, USART_IT_TXE);
+
+ /* Enable the USART Transmit Complete Interrupt */
+ __HAL_USART_ENABLE_IT(husart, USART_IT_TC);
+ }
+ else
+ {
+ tmp = (const uint16_t *) husart->pTxBuffPtr;
+ husart->Instance->TDR = (uint16_t)(*tmp & 0x01FFU);
+ husart->pTxBuffPtr += 2U;
+ husart->TxXferCount--;
+ }
+ }
+}
+
+/**
+ * @brief Simplex send an amount of data in non-blocking mode.
+ * @note Function called under interruption only, once
+ * interruptions have been enabled by HAL_USART_Transmit_IT().
+ * @note The USART errors are not managed to avoid the overrun error.
+ * @note ISR function executed when FIFO mode is enabled and when the
+ * data word length is less than 9 bits long.
+ * @param husart USART handle.
+ * @retval None
+ */
+static void USART_TxISR_8BIT_FIFOEN(USART_HandleTypeDef *husart)
+{
+ const HAL_USART_StateTypeDef state = husart->State;
+ uint16_t nb_tx_data;
+
+ /* Check that a Tx process is ongoing */
+ if ((state == HAL_USART_STATE_BUSY_TX) ||
+ (state == HAL_USART_STATE_BUSY_TX_RX))
+ {
+ for (nb_tx_data = husart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--)
+ {
+ if (husart->TxXferCount == 0U)
+ {
+ /* Disable the TX FIFO threshold interrupt */
+ __HAL_USART_DISABLE_IT(husart, USART_IT_TXFT);
+
+ /* Enable the USART Transmit Complete Interrupt */
+ __HAL_USART_ENABLE_IT(husart, USART_IT_TC);
+
+ break; /* force exit loop */
+ }
+ else if (__HAL_USART_GET_FLAG(husart, USART_FLAG_TXFNF) == SET)
+ {
+ husart->Instance->TDR = (uint8_t)(*husart->pTxBuffPtr & (uint8_t)0xFF);
+ husart->pTxBuffPtr++;
+ husart->TxXferCount--;
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+ }
+ }
+}
+
+/**
+ * @brief Simplex send an amount of data in non-blocking mode.
+ * @note Function called under interruption only, once
+ * interruptions have been enabled by HAL_USART_Transmit_IT().
+ * @note The USART errors are not managed to avoid the overrun error.
+ * @note ISR function executed when FIFO mode is enabled and when the
+ * data word length is 9 bits long.
+ * @param husart USART handle.
+ * @retval None
+ */
+static void USART_TxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart)
+{
+ const HAL_USART_StateTypeDef state = husart->State;
+ const uint16_t *tmp;
+ uint16_t nb_tx_data;
+
+ /* Check that a Tx process is ongoing */
+ if ((state == HAL_USART_STATE_BUSY_TX) ||
+ (state == HAL_USART_STATE_BUSY_TX_RX))
+ {
+ for (nb_tx_data = husart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--)
+ {
+ if (husart->TxXferCount == 0U)
+ {
+ /* Disable the TX FIFO threshold interrupt */
+ __HAL_USART_DISABLE_IT(husart, USART_IT_TXFT);
+
+ /* Enable the USART Transmit Complete Interrupt */
+ __HAL_USART_ENABLE_IT(husart, USART_IT_TC);
+
+ break; /* force exit loop */
+ }
+ else if (__HAL_USART_GET_FLAG(husart, USART_FLAG_TXFNF) == SET)
+ {
+ tmp = (const uint16_t *) husart->pTxBuffPtr;
+ husart->Instance->TDR = (uint16_t)(*tmp & 0x01FFU);
+ husart->pTxBuffPtr += 2U;
+ husart->TxXferCount--;
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+ }
+ }
+}
+
+/**
+ * @brief Wraps up transmission in non-blocking mode.
+ * @param husart Pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
+ * @retval None
+ */
+static void USART_EndTransmit_IT(USART_HandleTypeDef *husart)
+{
+ /* Disable the USART Transmit Complete Interrupt */
+ __HAL_USART_DISABLE_IT(husart, USART_IT_TC);
+
+ /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
+ __HAL_USART_DISABLE_IT(husart, USART_IT_ERR);
+
+ /* Clear TxISR function pointer */
+ husart->TxISR = NULL;
+
+ if (husart->State == HAL_USART_STATE_BUSY_TX)
+ {
+ /* Clear overrun flag and discard the received data */
+ __HAL_USART_CLEAR_OREFLAG(husart);
+ __HAL_USART_SEND_REQ(husart, USART_RXDATA_FLUSH_REQUEST);
+
+ /* Tx process is completed, restore husart->State to Ready */
+ husart->State = HAL_USART_STATE_READY;
+
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ /* Call registered Tx Complete Callback */
+ husart->TxCpltCallback(husart);
+#else
+ /* Call legacy weak Tx Complete Callback */
+ HAL_USART_TxCpltCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+ }
+ else if (husart->RxXferCount == 0U)
+ {
+ /* TxRx process is completed, restore husart->State to Ready */
+ husart->State = HAL_USART_STATE_READY;
+
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ /* Call registered Tx Rx Complete Callback */
+ husart->TxRxCpltCallback(husart);
+#else
+ /* Call legacy weak Tx Rx Complete Callback */
+ HAL_USART_TxRxCpltCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+}
+
+
+/**
+ * @brief Simplex receive an amount of data in non-blocking mode.
+ * @note Function called under interruption only, once
+ * interruptions have been enabled by HAL_USART_Receive_IT().
+ * @note ISR function executed when FIFO mode is disabled and when the
+ * data word length is less than 9 bits long.
+ * @param husart USART handle
+ * @retval None
+ */
+static void USART_RxISR_8BIT(USART_HandleTypeDef *husart)
+{
+ const HAL_USART_StateTypeDef state = husart->State;
+ uint16_t txdatacount;
+ uint16_t uhMask = husart->Mask;
+ uint32_t txftie;
+
+ if ((state == HAL_USART_STATE_BUSY_RX) ||
+ (state == HAL_USART_STATE_BUSY_TX_RX))
+ {
+ *husart->pRxBuffPtr = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask);
+ husart->pRxBuffPtr++;
+ husart->RxXferCount--;
+
+ if (husart->RxXferCount == 0U)
+ {
+ /* Disable the USART Parity Error Interrupt and RXNE interrupt*/
+ CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
+
+ /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
+
+ /* Clear RxISR function pointer */
+ husart->RxISR = NULL;
+
+ /* txftie and txdatacount are temporary variables for MISRAC2012-Rule-13.5 */
+ txftie = READ_BIT(husart->Instance->CR3, USART_CR3_TXFTIE);
+ txdatacount = husart->TxXferCount;
+
+ if (state == HAL_USART_STATE_BUSY_RX)
+ {
+ /* Clear SPI slave underrun flag and discard transmit data */
+ if (husart->SlaveMode == USART_SLAVEMODE_ENABLE)
+ {
+ __HAL_USART_CLEAR_UDRFLAG(husart);
+ __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST);
+ }
+
+ /* Rx process is completed, restore husart->State to Ready */
+ husart->State = HAL_USART_STATE_READY;
+
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ /* Call registered Rx Complete Callback */
+ husart->RxCpltCallback(husart);
+#else
+ /* Call legacy weak Rx Complete Callback */
+ HAL_USART_RxCpltCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+ }
+ else if ((READ_BIT(husart->Instance->CR1, USART_CR1_TCIE) != USART_CR1_TCIE) &&
+ (txftie != USART_CR3_TXFTIE) &&
+ (txdatacount == 0U))
+ {
+ /* TxRx process is completed, restore husart->State to Ready */
+ husart->State = HAL_USART_STATE_READY;
+
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ /* Call registered Tx Rx Complete Callback */
+ husart->TxRxCpltCallback(husart);
+#else
+ /* Call legacy weak Tx Rx Complete Callback */
+ HAL_USART_TxRxCpltCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+ }
+ else if ((state == HAL_USART_STATE_BUSY_RX) &&
+ (husart->SlaveMode == USART_SLAVEMODE_DISABLE))
+ {
+ /* Send dummy byte in order to generate the clock for the Slave to Send the next data */
+ husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF);
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+ }
+}
+
+/**
+ * @brief Simplex receive an amount of data in non-blocking mode.
+ * @note Function called under interruption only, once
+ * interruptions have been enabled by HAL_USART_Receive_IT().
+ * @note ISR function executed when FIFO mode is disabled and when the
+ * data word length is 9 bits long.
+ * @param husart USART handle
+ * @retval None
+ */
+static void USART_RxISR_16BIT(USART_HandleTypeDef *husart)
+{
+ const HAL_USART_StateTypeDef state = husart->State;
+ uint16_t txdatacount;
+ uint16_t *tmp;
+ uint16_t uhMask = husart->Mask;
+ uint32_t txftie;
+
+ if ((state == HAL_USART_STATE_BUSY_RX) ||
+ (state == HAL_USART_STATE_BUSY_TX_RX))
+ {
+ tmp = (uint16_t *) husart->pRxBuffPtr;
+ *tmp = (uint16_t)(husart->Instance->RDR & uhMask);
+ husart->pRxBuffPtr += 2U;
+ husart->RxXferCount--;
+
+ if (husart->RxXferCount == 0U)
+ {
+ /* Disable the USART Parity Error Interrupt and RXNE interrupt*/
+ CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
+
+ /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
+
+ /* Clear RxISR function pointer */
+ husart->RxISR = NULL;
+
+ /* txftie and txdatacount are temporary variables for MISRAC2012-Rule-13.5 */
+ txftie = READ_BIT(husart->Instance->CR3, USART_CR3_TXFTIE);
+ txdatacount = husart->TxXferCount;
+
+ if (state == HAL_USART_STATE_BUSY_RX)
+ {
+ /* Clear SPI slave underrun flag and discard transmit data */
+ if (husart->SlaveMode == USART_SLAVEMODE_ENABLE)
+ {
+ __HAL_USART_CLEAR_UDRFLAG(husart);
+ __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST);
+ }
+
+ /* Rx process is completed, restore husart->State to Ready */
+ husart->State = HAL_USART_STATE_READY;
+
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ /* Call registered Rx Complete Callback */
+ husart->RxCpltCallback(husart);
+#else
+ /* Call legacy weak Rx Complete Callback */
+ HAL_USART_RxCpltCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+ }
+ else if ((READ_BIT(husart->Instance->CR1, USART_CR1_TCIE) != USART_CR1_TCIE) &&
+ (txftie != USART_CR3_TXFTIE) &&
+ (txdatacount == 0U))
+ {
+ /* TxRx process is completed, restore husart->State to Ready */
+ husart->State = HAL_USART_STATE_READY;
+
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ /* Call registered Tx Rx Complete Callback */
+ husart->TxRxCpltCallback(husart);
+#else
+ /* Call legacy weak Tx Rx Complete Callback */
+ HAL_USART_TxRxCpltCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+ }
+ else if ((state == HAL_USART_STATE_BUSY_RX) &&
+ (husart->SlaveMode == USART_SLAVEMODE_DISABLE))
+ {
+ /* Send dummy byte in order to generate the clock for the Slave to Send the next data */
+ husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF);
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+ }
+}
+
+/**
+ * @brief Simplex receive an amount of data in non-blocking mode.
+ * @note Function called under interruption only, once
+ * interruptions have been enabled by HAL_USART_Receive_IT().
+ * @note ISR function executed when FIFO mode is enabled and when the
+ * data word length is less than 9 bits long.
+ * @param husart USART handle
+ * @retval None
+ */
+static void USART_RxISR_8BIT_FIFOEN(USART_HandleTypeDef *husart)
+{
+ HAL_USART_StateTypeDef state = husart->State;
+ uint16_t txdatacount;
+ uint16_t rxdatacount;
+ uint16_t uhMask = husart->Mask;
+ uint16_t nb_rx_data;
+ uint32_t txftie;
+
+ /* Check that a Rx process is ongoing */
+ if ((state == HAL_USART_STATE_BUSY_RX) ||
+ (state == HAL_USART_STATE_BUSY_TX_RX))
+ {
+ for (nb_rx_data = husart->NbRxDataToProcess ; nb_rx_data > 0U ; nb_rx_data--)
+ {
+ if (__HAL_USART_GET_FLAG(husart, USART_FLAG_RXFNE) == SET)
+ {
+ *husart->pRxBuffPtr = (uint8_t)(husart->Instance->RDR & (uint8_t)(uhMask & 0xFFU));
+ husart->pRxBuffPtr++;
+ husart->RxXferCount--;
+
+ if (husart->RxXferCount == 0U)
+ {
+ /* Disable the USART Parity Error Interrupt */
+ CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE);
+
+ /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error)
+ and RX FIFO Threshold interrupt */
+ CLEAR_BIT(husart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
+
+ /* Clear RxISR function pointer */
+ husart->RxISR = NULL;
+
+ /* txftie and txdatacount are temporary variables for MISRAC2012-Rule-13.5 */
+ txftie = READ_BIT(husart->Instance->CR3, USART_CR3_TXFTIE);
+ txdatacount = husart->TxXferCount;
+
+ if (state == HAL_USART_STATE_BUSY_RX)
+ {
+ /* Clear SPI slave underrun flag and discard transmit data */
+ if (husart->SlaveMode == USART_SLAVEMODE_ENABLE)
+ {
+ __HAL_USART_CLEAR_UDRFLAG(husart);
+ __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST);
+ }
+
+ /* Rx process is completed, restore husart->State to Ready */
+ husart->State = HAL_USART_STATE_READY;
+ state = HAL_USART_STATE_READY;
+
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ /* Call registered Rx Complete Callback */
+ husart->RxCpltCallback(husart);
+#else
+ /* Call legacy weak Rx Complete Callback */
+ HAL_USART_RxCpltCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+ }
+ else if ((READ_BIT(husart->Instance->CR1, USART_CR1_TCIE) != USART_CR1_TCIE) &&
+ (txftie != USART_CR3_TXFTIE) &&
+ (txdatacount == 0U))
+ {
+ /* TxRx process is completed, restore husart->State to Ready */
+ husart->State = HAL_USART_STATE_READY;
+ state = HAL_USART_STATE_READY;
+
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ /* Call registered Tx Rx Complete Callback */
+ husart->TxRxCpltCallback(husart);
+#else
+ /* Call legacy weak Tx Rx Complete Callback */
+ HAL_USART_TxRxCpltCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+ }
+ else if ((state == HAL_USART_STATE_BUSY_RX) &&
+ (husart->SlaveMode == USART_SLAVEMODE_DISABLE))
+ {
+ /* Send dummy byte in order to generate the clock for the Slave to Send the next data */
+ husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF);
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+ }
+ }
+
+ /* When remaining number of bytes to receive is less than the RX FIFO
+ threshold, next incoming frames are processed as if FIFO mode was
+ disabled (i.e. one interrupt per received frame).
+ */
+ rxdatacount = husart->RxXferCount;
+ if (((rxdatacount != 0U)) && (rxdatacount < husart->NbRxDataToProcess))
+ {
+ /* Disable the USART RXFT interrupt*/
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_RXFTIE);
+
+ /* Update the RxISR function pointer */
+ husart->RxISR = USART_RxISR_8BIT;
+
+ /* Enable the USART Data Register Not Empty interrupt */
+ SET_BIT(husart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
+
+ if ((husart->TxXferCount == 0U) &&
+ (state == HAL_USART_STATE_BUSY_TX_RX) &&
+ (husart->SlaveMode == USART_SLAVEMODE_DISABLE))
+ {
+ /* Send dummy byte in order to generate the clock for the Slave to Send the next data */
+ husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF);
+ }
+ }
+ }
+ else
+ {
+ /* Clear RXNE interrupt flag */
+ __HAL_USART_SEND_REQ(husart, USART_RXDATA_FLUSH_REQUEST);
+ }
+}
+
+/**
+ * @brief Simplex receive an amount of data in non-blocking mode.
+ * @note Function called under interruption only, once
+ * interruptions have been enabled by HAL_USART_Receive_IT().
+ * @note ISR function executed when FIFO mode is enabled and when the
+ * data word length is 9 bits long.
+ * @param husart USART handle
+ * @retval None
+ */
+static void USART_RxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart)
+{
+ HAL_USART_StateTypeDef state = husart->State;
+ uint16_t txdatacount;
+ uint16_t rxdatacount;
+ uint16_t *tmp;
+ uint16_t uhMask = husart->Mask;
+ uint16_t nb_rx_data;
+ uint32_t txftie;
+
+ /* Check that a Tx process is ongoing */
+ if ((state == HAL_USART_STATE_BUSY_RX) ||
+ (state == HAL_USART_STATE_BUSY_TX_RX))
+ {
+ for (nb_rx_data = husart->NbRxDataToProcess ; nb_rx_data > 0U ; nb_rx_data--)
+ {
+ if (__HAL_USART_GET_FLAG(husart, USART_FLAG_RXFNE) == SET)
+ {
+ tmp = (uint16_t *) husart->pRxBuffPtr;
+ *tmp = (uint16_t)(husart->Instance->RDR & uhMask);
+ husart->pRxBuffPtr += 2U;
+ husart->RxXferCount--;
+
+ if (husart->RxXferCount == 0U)
+ {
+ /* Disable the USART Parity Error Interrupt */
+ CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE);
+
+ /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error)
+ and RX FIFO Threshold interrupt */
+ CLEAR_BIT(husart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
+
+ /* Clear RxISR function pointer */
+ husart->RxISR = NULL;
+
+ /* txftie and txdatacount are temporary variables for MISRAC2012-Rule-13.5 */
+ txftie = READ_BIT(husart->Instance->CR3, USART_CR3_TXFTIE);
+ txdatacount = husart->TxXferCount;
+
+ if (state == HAL_USART_STATE_BUSY_RX)
+ {
+ /* Clear SPI slave underrun flag and discard transmit data */
+ if (husart->SlaveMode == USART_SLAVEMODE_ENABLE)
+ {
+ __HAL_USART_CLEAR_UDRFLAG(husart);
+ __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST);
+ }
+
+ /* Rx process is completed, restore husart->State to Ready */
+ husart->State = HAL_USART_STATE_READY;
+ state = HAL_USART_STATE_READY;
+
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ /* Call registered Rx Complete Callback */
+ husart->RxCpltCallback(husart);
+#else
+ /* Call legacy weak Rx Complete Callback */
+ HAL_USART_RxCpltCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+ }
+ else if ((READ_BIT(husart->Instance->CR1, USART_CR1_TCIE) != USART_CR1_TCIE) &&
+ (txftie != USART_CR3_TXFTIE) &&
+ (txdatacount == 0U))
+ {
+ /* TxRx process is completed, restore husart->State to Ready */
+ husart->State = HAL_USART_STATE_READY;
+ state = HAL_USART_STATE_READY;
+
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ /* Call registered Tx Rx Complete Callback */
+ husart->TxRxCpltCallback(husart);
+#else
+ /* Call legacy weak Tx Rx Complete Callback */
+ HAL_USART_TxRxCpltCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+ }
+ else if ((state == HAL_USART_STATE_BUSY_RX) &&
+ (husart->SlaveMode == USART_SLAVEMODE_DISABLE))
+ {
+ /* Send dummy byte in order to generate the clock for the Slave to Send the next data */
+ husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF);
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+ }
+ }
+
+ /* When remaining number of bytes to receive is less than the RX FIFO
+ threshold, next incoming frames are processed as if FIFO mode was
+ disabled (i.e. one interrupt per received frame).
+ */
+ rxdatacount = husart->RxXferCount;
+ if (((rxdatacount != 0U)) && (rxdatacount < husart->NbRxDataToProcess))
+ {
+ /* Disable the USART RXFT interrupt*/
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_RXFTIE);
+
+ /* Update the RxISR function pointer */
+ husart->RxISR = USART_RxISR_16BIT;
+
+ /* Enable the USART Data Register Not Empty interrupt */
+ SET_BIT(husart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
+
+ if ((husart->TxXferCount == 0U) &&
+ (state == HAL_USART_STATE_BUSY_TX_RX) &&
+ (husart->SlaveMode == USART_SLAVEMODE_DISABLE))
+ {
+ /* Send dummy byte in order to generate the clock for the Slave to Send the next data */
+ husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF);
+ }
+ }
+ }
+ else
+ {
+ /* Clear RXNE interrupt flag */
+ __HAL_USART_SEND_REQ(husart, USART_RXDATA_FLUSH_REQUEST);
+ }
+}
+
+/**
+ * @}
+ */
+
+#endif /* HAL_USART_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_usart_ex.c b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_usart_ex.c
new file mode 100644
index 0000000000..87f2677cd8
--- /dev/null
+++ b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_usart_ex.c
@@ -0,0 +1,540 @@
+/**
+ ******************************************************************************
+ * @file stm32c0xx_hal_usart_ex.c
+ * @author MCD Application Team
+ * @brief Extended USART HAL module driver.
+ * This file provides firmware functions to manage the following extended
+ * functionalities of the Universal Synchronous Receiver Transmitter Peripheral (USART).
+ * + Peripheral Control functions
+ *
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2022 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### USART peripheral extended features #####
+ ==============================================================================
+
+ (#) FIFO mode enabling/disabling and RX/TX FIFO threshold programming.
+
+ -@- When USART operates in FIFO mode, FIFO mode must be enabled prior
+ starting RX/TX transfers. Also RX/TX FIFO thresholds must be
+ configured prior starting RX/TX transfers.
+
+ (#) Slave mode enabling/disabling and NSS pin configuration.
+
+ -@- When USART operates in Slave mode, Slave mode must be enabled prior
+ starting RX/TX transfers.
+
+ @endverbatim
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32c0xx_hal.h"
+
+/** @addtogroup STM32C0xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup USARTEx USARTEx
+ * @brief USART Extended HAL module driver
+ * @{
+ */
+
+#ifdef HAL_USART_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/** @defgroup USARTEx_Private_Constants USARTEx Private Constants
+ * @{
+ */
+/* USART RX FIFO depth */
+#define RX_FIFO_DEPTH 8U
+
+/* USART TX FIFO depth */
+#define TX_FIFO_DEPTH 8U
+/**
+ * @}
+ */
+
+/* Private define ------------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup USARTEx_Private_Functions USARTEx Private Functions
+ * @{
+ */
+static void USARTEx_SetNbDataToProcess(USART_HandleTypeDef *husart);
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup USARTEx_Exported_Functions USARTEx Exported Functions
+ * @{
+ */
+
+/** @defgroup USARTEx_Exported_Functions_Group1 IO operation functions
+ * @brief Extended USART Transmit/Receive functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ This subsection provides a set of FIFO mode related callback functions.
+
+ (#) TX/RX Fifos Callbacks:
+ (+) HAL_USARTEx_RxFifoFullCallback()
+ (+) HAL_USARTEx_TxFifoEmptyCallback()
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief USART RX Fifo full callback.
+ * @param husart USART handle.
+ * @retval None
+ */
+__weak void HAL_USARTEx_RxFifoFullCallback(USART_HandleTypeDef *husart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(husart);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_USARTEx_RxFifoFullCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief USART TX Fifo empty callback.
+ * @param husart USART handle.
+ * @retval None
+ */
+__weak void HAL_USARTEx_TxFifoEmptyCallback(USART_HandleTypeDef *husart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(husart);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_USARTEx_TxFifoEmptyCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup USARTEx_Exported_Functions_Group2 Peripheral Control functions
+ * @brief Extended Peripheral Control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..] This section provides the following functions:
+ (+) HAL_USARTEx_EnableSPISlaveMode() API enables the SPI slave mode
+ (+) HAL_USARTEx_DisableSPISlaveMode() API disables the SPI slave mode
+ (+) HAL_USARTEx_ConfigNSS API configures the Slave Select input pin (NSS)
+ (+) HAL_USARTEx_EnableFifoMode() API enables the FIFO mode
+ (+) HAL_USARTEx_DisableFifoMode() API disables the FIFO mode
+ (+) HAL_USARTEx_SetTxFifoThreshold() API sets the TX FIFO threshold
+ (+) HAL_USARTEx_SetRxFifoThreshold() API sets the RX FIFO threshold
+
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enable the SPI slave mode.
+ * @note When the USART operates in SPI slave mode, it handles data flow using
+ * the serial interface clock derived from the external SCLK signal
+ * provided by the external master SPI device.
+ * @note In SPI slave mode, the USART must be enabled before starting the master
+ * communications (or between frames while the clock is stable). Otherwise,
+ * if the USART slave is enabled while the master is in the middle of a
+ * frame, it will become desynchronized with the master.
+ * @note The data register of the slave needs to be ready before the first edge
+ * of the communication clock or before the end of the ongoing communication,
+ * otherwise the SPI slave will transmit zeros.
+ * @param husart USART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_USARTEx_EnableSlaveMode(USART_HandleTypeDef *husart)
+{
+ uint32_t tmpcr1;
+
+ /* Check parameters */
+ assert_param(IS_UART_SPI_SLAVE_INSTANCE(husart->Instance));
+
+ /* Process Locked */
+ __HAL_LOCK(husart);
+
+ husart->State = HAL_USART_STATE_BUSY;
+
+ /* Save actual USART configuration */
+ tmpcr1 = READ_REG(husart->Instance->CR1);
+
+ /* Disable USART */
+ __HAL_USART_DISABLE(husart);
+
+ /* In SPI slave mode mode, the following bits must be kept cleared:
+ - LINEN and CLKEN bit in the USART_CR2 register
+ - HDSEL, SCEN and IREN bits in the USART_CR3 register.*/
+ CLEAR_BIT(husart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+ CLEAR_BIT(husart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
+
+ /* Enable SPI slave mode */
+ SET_BIT(husart->Instance->CR2, USART_CR2_SLVEN);
+
+ /* Restore USART configuration */
+ WRITE_REG(husart->Instance->CR1, tmpcr1);
+
+ husart->SlaveMode = USART_SLAVEMODE_ENABLE;
+
+ husart->State = HAL_USART_STATE_READY;
+
+ /* Enable USART */
+ __HAL_USART_ENABLE(husart);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disable the SPI slave mode.
+ * @param husart USART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_USARTEx_DisableSlaveMode(USART_HandleTypeDef *husart)
+{
+ uint32_t tmpcr1;
+
+ /* Check parameters */
+ assert_param(IS_UART_SPI_SLAVE_INSTANCE(husart->Instance));
+
+ /* Process Locked */
+ __HAL_LOCK(husart);
+
+ husart->State = HAL_USART_STATE_BUSY;
+
+ /* Save actual USART configuration */
+ tmpcr1 = READ_REG(husart->Instance->CR1);
+
+ /* Disable USART */
+ __HAL_USART_DISABLE(husart);
+
+ /* Disable SPI slave mode */
+ CLEAR_BIT(husart->Instance->CR2, USART_CR2_SLVEN);
+
+ /* Restore USART configuration */
+ WRITE_REG(husart->Instance->CR1, tmpcr1);
+
+ husart->SlaveMode = USART_SLAVEMODE_DISABLE;
+
+ husart->State = HAL_USART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configure the Slave Select input pin (NSS).
+ * @note Software NSS management: SPI slave will always be selected and NSS
+ * input pin will be ignored.
+ * @note Hardware NSS management: the SPI slave selection depends on NSS
+ * input pin. The slave is selected when NSS is low and deselected when
+ * NSS is high.
+ * @param husart USART handle.
+ * @param NSSConfig NSS configuration.
+ * This parameter can be one of the following values:
+ * @arg @ref USART_NSS_HARD
+ * @arg @ref USART_NSS_SOFT
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_USARTEx_ConfigNSS(USART_HandleTypeDef *husart, uint32_t NSSConfig)
+{
+ uint32_t tmpcr1;
+
+ /* Check parameters */
+ assert_param(IS_UART_SPI_SLAVE_INSTANCE(husart->Instance));
+ assert_param(IS_USART_NSS(NSSConfig));
+
+ /* Process Locked */
+ __HAL_LOCK(husart);
+
+ husart->State = HAL_USART_STATE_BUSY;
+
+ /* Save actual USART configuration */
+ tmpcr1 = READ_REG(husart->Instance->CR1);
+
+ /* Disable USART */
+ __HAL_USART_DISABLE(husart);
+
+ /* Program DIS_NSS bit in the USART_CR2 register */
+ MODIFY_REG(husart->Instance->CR2, USART_CR2_DIS_NSS, NSSConfig);
+
+ /* Restore USART configuration */
+ WRITE_REG(husart->Instance->CR1, tmpcr1);
+
+ husart->State = HAL_USART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Enable the FIFO mode.
+ * @param husart USART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_USARTEx_EnableFifoMode(USART_HandleTypeDef *husart)
+{
+ uint32_t tmpcr1;
+
+ /* Check parameters */
+ assert_param(IS_UART_FIFO_INSTANCE(husart->Instance));
+
+ /* Process Locked */
+ __HAL_LOCK(husart);
+
+ husart->State = HAL_USART_STATE_BUSY;
+
+ /* Save actual USART configuration */
+ tmpcr1 = READ_REG(husart->Instance->CR1);
+
+ /* Disable USART */
+ __HAL_USART_DISABLE(husart);
+
+ /* Enable FIFO mode */
+ SET_BIT(tmpcr1, USART_CR1_FIFOEN);
+ husart->FifoMode = USART_FIFOMODE_ENABLE;
+
+ /* Restore USART configuration */
+ WRITE_REG(husart->Instance->CR1, tmpcr1);
+
+ /* Determine the number of data to process during RX/TX ISR execution */
+ USARTEx_SetNbDataToProcess(husart);
+
+ husart->State = HAL_USART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disable the FIFO mode.
+ * @param husart USART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_USARTEx_DisableFifoMode(USART_HandleTypeDef *husart)
+{
+ uint32_t tmpcr1;
+
+ /* Check parameters */
+ assert_param(IS_UART_FIFO_INSTANCE(husart->Instance));
+
+ /* Process Locked */
+ __HAL_LOCK(husart);
+
+ husart->State = HAL_USART_STATE_BUSY;
+
+ /* Save actual USART configuration */
+ tmpcr1 = READ_REG(husart->Instance->CR1);
+
+ /* Disable USART */
+ __HAL_USART_DISABLE(husart);
+
+ /* Enable FIFO mode */
+ CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN);
+ husart->FifoMode = USART_FIFOMODE_DISABLE;
+
+ /* Restore USART configuration */
+ WRITE_REG(husart->Instance->CR1, tmpcr1);
+
+ husart->State = HAL_USART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Set the TXFIFO threshold.
+ * @param husart USART handle.
+ * @param Threshold TX FIFO threshold value
+ * This parameter can be one of the following values:
+ * @arg @ref USART_TXFIFO_THRESHOLD_1_8
+ * @arg @ref USART_TXFIFO_THRESHOLD_1_4
+ * @arg @ref USART_TXFIFO_THRESHOLD_1_2
+ * @arg @ref USART_TXFIFO_THRESHOLD_3_4
+ * @arg @ref USART_TXFIFO_THRESHOLD_7_8
+ * @arg @ref USART_TXFIFO_THRESHOLD_8_8
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_USARTEx_SetTxFifoThreshold(USART_HandleTypeDef *husart, uint32_t Threshold)
+{
+ uint32_t tmpcr1;
+
+ /* Check parameters */
+ assert_param(IS_UART_FIFO_INSTANCE(husart->Instance));
+ assert_param(IS_USART_TXFIFO_THRESHOLD(Threshold));
+
+ /* Process Locked */
+ __HAL_LOCK(husart);
+
+ husart->State = HAL_USART_STATE_BUSY;
+
+ /* Save actual USART configuration */
+ tmpcr1 = READ_REG(husart->Instance->CR1);
+
+ /* Disable USART */
+ __HAL_USART_DISABLE(husart);
+
+ /* Update TX threshold configuration */
+ MODIFY_REG(husart->Instance->CR3, USART_CR3_TXFTCFG, Threshold);
+
+ /* Determine the number of data to process during RX/TX ISR execution */
+ USARTEx_SetNbDataToProcess(husart);
+
+ /* Restore USART configuration */
+ WRITE_REG(husart->Instance->CR1, tmpcr1);
+
+ husart->State = HAL_USART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Set the RXFIFO threshold.
+ * @param husart USART handle.
+ * @param Threshold RX FIFO threshold value
+ * This parameter can be one of the following values:
+ * @arg @ref USART_RXFIFO_THRESHOLD_1_8
+ * @arg @ref USART_RXFIFO_THRESHOLD_1_4
+ * @arg @ref USART_RXFIFO_THRESHOLD_1_2
+ * @arg @ref USART_RXFIFO_THRESHOLD_3_4
+ * @arg @ref USART_RXFIFO_THRESHOLD_7_8
+ * @arg @ref USART_RXFIFO_THRESHOLD_8_8
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_USARTEx_SetRxFifoThreshold(USART_HandleTypeDef *husart, uint32_t Threshold)
+{
+ uint32_t tmpcr1;
+
+ /* Check the parameters */
+ assert_param(IS_UART_FIFO_INSTANCE(husart->Instance));
+ assert_param(IS_USART_RXFIFO_THRESHOLD(Threshold));
+
+ /* Process Locked */
+ __HAL_LOCK(husart);
+
+ husart->State = HAL_USART_STATE_BUSY;
+
+ /* Save actual USART configuration */
+ tmpcr1 = READ_REG(husart->Instance->CR1);
+
+ /* Disable USART */
+ __HAL_USART_DISABLE(husart);
+
+ /* Update RX threshold configuration */
+ MODIFY_REG(husart->Instance->CR3, USART_CR3_RXFTCFG, Threshold);
+
+ /* Determine the number of data to process during RX/TX ISR execution */
+ USARTEx_SetNbDataToProcess(husart);
+
+ /* Restore USART configuration */
+ WRITE_REG(husart->Instance->CR1, tmpcr1);
+
+ husart->State = HAL_USART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup USARTEx_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Calculate the number of data to process in RX/TX ISR.
+ * @note The RX FIFO depth and the TX FIFO depth is extracted from
+ * the USART configuration registers.
+ * @param husart USART handle.
+ * @retval None
+ */
+static void USARTEx_SetNbDataToProcess(USART_HandleTypeDef *husart)
+{
+ uint8_t rx_fifo_depth;
+ uint8_t tx_fifo_depth;
+ uint8_t rx_fifo_threshold;
+ uint8_t tx_fifo_threshold;
+ /* 2 0U/1U added for MISRAC2012-Rule-18.1_b and MISRAC2012-Rule-18.1_d */
+ static const uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U};
+ static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U};
+
+ if (husart->FifoMode == USART_FIFOMODE_DISABLE)
+ {
+ husart->NbTxDataToProcess = 1U;
+ husart->NbRxDataToProcess = 1U;
+ }
+ else
+ {
+ rx_fifo_depth = RX_FIFO_DEPTH;
+ tx_fifo_depth = TX_FIFO_DEPTH;
+ rx_fifo_threshold = (uint8_t)((READ_BIT(husart->Instance->CR3,
+ USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos) & 0xFFU);
+ tx_fifo_threshold = (uint8_t)((READ_BIT(husart->Instance->CR3,
+ USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos) & 0xFFU);
+ husart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) /
+ (uint16_t)denominator[tx_fifo_threshold];
+ husart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) /
+ (uint16_t)denominator[rx_fifo_threshold];
+ }
+}
+/**
+ * @}
+ */
+
+#endif /* HAL_USART_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_wwdg.c b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_wwdg.c
new file mode 100644
index 0000000000..b8e53e08b4
--- /dev/null
+++ b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_wwdg.c
@@ -0,0 +1,420 @@
+/**
+ ******************************************************************************
+ * @file stm32c0xx_hal_wwdg.c
+ * @author MCD Application Team
+ * @brief WWDG HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Window Watchdog (WWDG) peripheral:
+ * + Initialization and Configuration functions
+ * + IO operation functions
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2022 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### WWDG Specific features #####
+ ==============================================================================
+ [..]
+ Once enabled the WWDG generates a system reset on expiry of a programmed
+ time period, unless the program refreshes the counter (T[6;0] downcounter)
+ before reaching 0x3F value (i.e. a reset is generated when the counter
+ value rolls down from 0x40 to 0x3F).
+
+ (+) An MCU reset is also generated if the counter value is refreshed
+ before the counter has reached the refresh window value. This
+ implies that the counter must be refreshed in a limited window.
+ (+) Once enabled the WWDG cannot be disabled except by a system reset.
+ (+) If required by application, an Early Wakeup Interrupt can be triggered
+ in order to be warned before WWDG expiration. The Early Wakeup Interrupt
+ (EWI) can be used if specific safety operations or data logging must
+ be performed before the actual reset is generated. When the downcounter
+ reaches 0x40, interrupt occurs. This mechanism requires WWDG interrupt
+ line to be enabled in NVIC. Once enabled, EWI interrupt cannot be
+ disabled except by a system reset.
+ (+) WWDGRST flag in RCC CSR register can be used to inform when a WWDG
+ reset occurs.
+ (+) The WWDG counter input clock is derived from the APB clock divided
+ by a programmable prescaler.
+ (+) WWDG clock (Hz) = PCLK1 / (4096 * Prescaler)
+ (+) WWDG timeout (mS) = 1000 * (T[5;0] + 1) / WWDG clock (Hz)
+ where T[5;0] are the lowest 6 bits of Counter.
+ (+) WWDG Counter refresh is allowed between the following limits :
+ (++) min time (mS) = 1000 * (Counter - Window) / WWDG clock
+ (++) max time (mS) = 1000 * (Counter - 0x40) / WWDG clock
+ (+) Typical values:
+ (++) Counter min (T[5;0] = 0x00) at 32MHz (PCLK1) with zero prescaler:
+ max timeout before reset: approximately 41.79us
+ (++) Counter max (T[5;0] = 0x3F) at 32MHz (PCLK1) with prescaler
+ dividing by 128:
+ max timeout before reset: approximately 342.38ms
+
+ ##### How to use this driver #####
+ ==============================================================================
+
+ *** Common driver usage ***
+ ===========================
+
+ [..]
+ (+) Enable WWDG APB1 clock using __HAL_RCC_WWDG_CLK_ENABLE().
+ (+) Configure the WWDG prescaler, refresh window value, counter value and early
+ interrupt status using HAL_WWDG_Init() function. This will automatically
+ enable WWDG and start its downcounter. Time reference can be taken from
+ function exit. Care must be taken to provide a counter value
+ greater than 0x40 to prevent generation of immediate reset.
+ (+) If the Early Wakeup Interrupt (EWI) feature is enabled, an interrupt is
+ generated when the counter reaches 0x40. When HAL_WWDG_IRQHandler is
+ triggered by the interrupt service routine, flag will be automatically
+ cleared and HAL_WWDG_WakeupCallback user callback will be executed. User
+ can add his own code by customization of callback HAL_WWDG_WakeupCallback.
+ (+) Then the application program must refresh the WWDG counter at regular
+ intervals during normal operation to prevent an MCU reset, using
+ HAL_WWDG_Refresh() function. This operation must occur only when
+ the counter is lower than the refresh window value already programmed.
+
+ *** Callback registration ***
+ =============================
+
+ [..]
+ The compilation define USE_HAL_WWDG_REGISTER_CALLBACKS when set to 1 allows
+ the user to configure dynamically the driver callbacks. Use Functions
+ HAL_WWDG_RegisterCallback() to register a user callback.
+
+ (+) Function HAL_WWDG_RegisterCallback() allows to register following
+ callbacks:
+ (++) EwiCallback : callback for Early WakeUp Interrupt.
+ (++) MspInitCallback : WWDG MspInit.
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+ (+) Use function HAL_WWDG_UnRegisterCallback() to reset a callback to
+ the default weak (surcharged) function. HAL_WWDG_UnRegisterCallback()
+ takes as parameters the HAL peripheral handle and the Callback ID.
+ This function allows to reset following callbacks:
+ (++) EwiCallback : callback for Early WakeUp Interrupt.
+ (++) MspInitCallback : WWDG MspInit.
+
+ [..]
+ When calling HAL_WWDG_Init function, callbacks are reset to the
+ corresponding legacy weak (surcharged) functions:
+ HAL_WWDG_EarlyWakeupCallback() and HAL_WWDG_MspInit() only if they have
+ not been registered before.
+
+ [..]
+ When compilation define USE_HAL_WWDG_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registering feature is not available
+ and weak (surcharged) callbacks are used.
+
+ *** WWDG HAL driver macros list ***
+ ===================================
+ [..]
+ Below the list of available macros in WWDG HAL driver.
+ (+) __HAL_WWDG_ENABLE: Enable the WWDG peripheral
+ (+) __HAL_WWDG_GET_FLAG: Get the selected WWDG's flag status
+ (+) __HAL_WWDG_CLEAR_FLAG: Clear the WWDG's pending flags
+ (+) __HAL_WWDG_ENABLE_IT: Enable the WWDG early wakeup interrupt
+
+ @endverbatim
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32c0xx_hal.h"
+
+/** @addtogroup STM32C0xx_HAL_Driver
+ * @{
+ */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+/** @defgroup WWDG WWDG
+ * @brief WWDG HAL module driver.
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup WWDG_Exported_Functions WWDG Exported Functions
+ * @{
+ */
+
+/** @defgroup WWDG_Exported_Functions_Group1 Initialization and Configuration functions
+ * @brief Initialization and Configuration functions.
+ *
+@verbatim
+ ==============================================================================
+ ##### Initialization and Configuration functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Initialize and start the WWDG according to the specified parameters
+ in the WWDG_InitTypeDef of associated handle.
+ (+) Initialize the WWDG MSP.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initialize the WWDG according to the specified.
+ * parameters in the WWDG_InitTypeDef of associated handle.
+ * @param hwwdg pointer to a WWDG_HandleTypeDef structure that contains
+ * the configuration information for the specified WWDG module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg)
+{
+ /* Check the WWDG handle allocation */
+ if (hwwdg == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_WWDG_ALL_INSTANCE(hwwdg->Instance));
+ assert_param(IS_WWDG_PRESCALER(hwwdg->Init.Prescaler));
+ assert_param(IS_WWDG_WINDOW(hwwdg->Init.Window));
+ assert_param(IS_WWDG_COUNTER(hwwdg->Init.Counter));
+ assert_param(IS_WWDG_EWI_MODE(hwwdg->Init.EWIMode));
+
+#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
+ /* Reset Callback pointers */
+ if (hwwdg->EwiCallback == NULL)
+ {
+ hwwdg->EwiCallback = HAL_WWDG_EarlyWakeupCallback;
+ }
+
+ if (hwwdg->MspInitCallback == NULL)
+ {
+ hwwdg->MspInitCallback = HAL_WWDG_MspInit;
+ }
+
+ /* Init the low level hardware */
+ hwwdg->MspInitCallback(hwwdg);
+#else
+ /* Init the low level hardware */
+ HAL_WWDG_MspInit(hwwdg);
+#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
+
+ /* Set WWDG Counter */
+ WRITE_REG(hwwdg->Instance->CR, (WWDG_CR_WDGA | hwwdg->Init.Counter));
+
+ /* Set WWDG Prescaler and Window */
+ WRITE_REG(hwwdg->Instance->CFR, (hwwdg->Init.EWIMode | hwwdg->Init.Prescaler | hwwdg->Init.Window));
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Initialize the WWDG MSP.
+ * @param hwwdg pointer to a WWDG_HandleTypeDef structure that contains
+ * the configuration information for the specified WWDG module.
+ * @note When rewriting this function in user file, mechanism may be added
+ * to avoid multiple initialize when HAL_WWDG_Init function is called
+ * again to change parameters.
+ * @retval None
+ */
+__weak void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hwwdg);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_WWDG_MspInit could be implemented in the user file
+ */
+}
+
+
+#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a User WWDG Callback
+ * To be used instead of the weak (surcharged) predefined callback
+ * @param hwwdg WWDG handle
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_WWDG_EWI_CB_ID Early WakeUp Interrupt Callback ID
+ * @arg @ref HAL_WWDG_MSPINIT_CB_ID MspInit callback ID
+ * @param pCallback pointer to the Callback function
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_WWDG_RegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID,
+ pWWDG_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ status = HAL_ERROR;
+ }
+ else
+ {
+ switch (CallbackID)
+ {
+ case HAL_WWDG_EWI_CB_ID:
+ hwwdg->EwiCallback = pCallback;
+ break;
+
+ case HAL_WWDG_MSPINIT_CB_ID:
+ hwwdg->MspInitCallback = pCallback;
+ break;
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+ }
+
+ return status;
+}
+
+
+/**
+ * @brief Unregister a WWDG Callback
+ * WWDG Callback is redirected to the weak (surcharged) predefined callback
+ * @param hwwdg WWDG handle
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_WWDG_EWI_CB_ID Early WakeUp Interrupt Callback ID
+ * @arg @ref HAL_WWDG_MSPINIT_CB_ID MspInit callback ID
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_WWDG_UnRegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ switch (CallbackID)
+ {
+ case HAL_WWDG_EWI_CB_ID:
+ hwwdg->EwiCallback = HAL_WWDG_EarlyWakeupCallback;
+ break;
+
+ case HAL_WWDG_MSPINIT_CB_ID:
+ hwwdg->MspInitCallback = HAL_WWDG_MspInit;
+ break;
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ return status;
+}
+#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+/** @defgroup WWDG_Exported_Functions_Group2 IO operation functions
+ * @brief IO operation functions
+ *
+@verbatim
+ ==============================================================================
+ ##### IO operation functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Refresh the WWDG.
+ (+) Handle WWDG interrupt request and associated function callback.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Refresh the WWDG.
+ * @param hwwdg pointer to a WWDG_HandleTypeDef structure that contains
+ * the configuration information for the specified WWDG module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg)
+{
+ /* Write to WWDG CR the WWDG Counter value to refresh with */
+ WRITE_REG(hwwdg->Instance->CR, (hwwdg->Init.Counter));
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle WWDG interrupt request.
+ * @note The Early Wakeup Interrupt (EWI) can be used if specific safety operations
+ * or data logging must be performed before the actual reset is generated.
+ * The EWI interrupt is enabled by calling HAL_WWDG_Init function with
+ * EWIMode set to WWDG_EWI_ENABLE.
+ * When the downcounter reaches the value 0x40, and EWI interrupt is
+ * generated and the corresponding Interrupt Service Routine (ISR) can
+ * be used to trigger specific actions (such as communications or data
+ * logging), before resetting the device.
+ * @param hwwdg pointer to a WWDG_HandleTypeDef structure that contains
+ * the configuration information for the specified WWDG module.
+ * @retval None
+ */
+void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg)
+{
+ /* Check if Early Wakeup Interrupt is enable */
+ if (__HAL_WWDG_GET_IT_SOURCE(hwwdg, WWDG_IT_EWI) != RESET)
+ {
+ /* Check if WWDG Early Wakeup Interrupt occurred */
+ if (__HAL_WWDG_GET_FLAG(hwwdg, WWDG_FLAG_EWIF) != RESET)
+ {
+ /* Clear the WWDG Early Wakeup flag */
+ __HAL_WWDG_CLEAR_FLAG(hwwdg, WWDG_FLAG_EWIF);
+
+#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
+ /* Early Wakeup registered callback */
+ hwwdg->EwiCallback(hwwdg);
+#else
+ /* Early Wakeup callback */
+ HAL_WWDG_EarlyWakeupCallback(hwwdg);
+#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
+ }
+ }
+}
+
+
+/**
+ * @brief WWDG Early Wakeup callback.
+ * @param hwwdg pointer to a WWDG_HandleTypeDef structure that contains
+ * the configuration information for the specified WWDG module.
+ * @retval None
+ */
+__weak void HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef *hwwdg)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hwwdg);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_WWDG_EarlyWakeupCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_WWDG_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_ll_adc.c b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_ll_adc.c
new file mode 100644
index 0000000000..ce6f280f6a
--- /dev/null
+++ b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_ll_adc.c
@@ -0,0 +1,751 @@
+/**
+ ******************************************************************************
+ * @file stm32c0xx_ll_adc.c
+ * @author MCD Application Team
+ * @brief ADC LL module driver
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2022 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32c0xx_ll_adc.h"
+#include "stm32c0xx_ll_bus.h"
+
+#ifdef USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif
+
+/** @addtogroup STM32C0xx_LL_Driver
+ * @{
+ */
+
+#if defined (ADC1)
+
+/** @addtogroup ADC_LL ADC
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @addtogroup ADC_LL_Private_Constants
+ * @{
+ */
+
+/* Definitions of ADC hardware constraints delays */
+/* Note: Only ADC peripheral HW delays are defined in ADC LL driver driver, */
+/* not timeout values: */
+/* Timeout values for ADC operations are dependent to device clock */
+/* configuration (system clock versus ADC clock), */
+/* and therefore must be defined in user application. */
+/* Refer to @ref ADC_LL_EC_HW_DELAYS for description of ADC timeout */
+/* values definition. */
+/* Note: ADC timeout values are defined here in CPU cycles to be independent */
+/* of device clock setting. */
+/* In user application, ADC timeout values should be defined with */
+/* temporal values, in function of device clock settings. */
+/* Highest ratio CPU clock frequency vs ADC clock frequency: */
+/* - ADC clock from synchronous clock with AHB prescaler 512, */
+/* APB prescaler 16, ADC prescaler 4. */
+/* - ADC clock from asynchronous clock (HSI) with prescaler 1, */
+/* with highest ratio CPU clock frequency vs HSI clock frequency: */
+/* CPU clock frequency max 48MHz, HSI frequency 16MHz: ratio 4. */
+/* Unit: CPU cycles. */
+#define ADC_CLOCK_RATIO_VS_CPU_HIGHEST (512UL * 16UL * 4UL)
+#define ADC_TIMEOUT_DISABLE_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL)
+#define ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL)
+/* Note: CCRDY handshake requires 1APB + 2 ADC + 3 APB cycles */
+/* after the channel configuration has been changed. */
+/* Driver timeout is approximated to 6 CPU cycles. */
+#define ADC_TIMEOUT_CCRDY_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 6UL)
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+
+/** @addtogroup ADC_LL_Private_Macros
+ * @{
+ */
+
+/* Check of parameters for configuration of ADC hierarchical scope: */
+/* common to several ADC instances. */
+#define IS_LL_ADC_COMMON_CLOCK(__CLOCK__) \
+ (((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV1) \
+ || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV2) \
+ || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV4) \
+ || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV6) \
+ || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV8) \
+ || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV10) \
+ || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV12) \
+ || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV16) \
+ || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV32) \
+ || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV64) \
+ || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV128) \
+ || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV256) \
+ )
+
+#define IS_LL_ADC_CLOCK_FREQ_MODE(__CLOCK_FREQ_MODE__) \
+ (((__CLOCK_FREQ_MODE__) == LL_ADC_CLOCK_FREQ_MODE_HIGH) \
+ || ((__CLOCK_FREQ_MODE__) == LL_ADC_CLOCK_FREQ_MODE_LOW) \
+ )
+
+/* Check of parameters for configuration of ADC hierarchical scope: */
+/* ADC instance. */
+#define IS_LL_ADC_CLOCK(__CLOCK__) \
+ (((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV4) \
+ || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV2) \
+ || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV1) \
+ || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC) \
+ )
+
+#define IS_LL_ADC_RESOLUTION(__RESOLUTION__) \
+ (((__RESOLUTION__) == LL_ADC_RESOLUTION_12B) \
+ || ((__RESOLUTION__) == LL_ADC_RESOLUTION_10B) \
+ || ((__RESOLUTION__) == LL_ADC_RESOLUTION_8B) \
+ || ((__RESOLUTION__) == LL_ADC_RESOLUTION_6B) \
+ )
+
+#define IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__) \
+ (((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT) \
+ || ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT) \
+ )
+
+#define IS_LL_ADC_LOW_POWER(__LOW_POWER__) \
+ (((__LOW_POWER__) == LL_ADC_LP_MODE_NONE) \
+ || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT) \
+ || ((__LOW_POWER__) == LL_ADC_LP_AUTOPOWEROFF) \
+ || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF) \
+ )
+
+/* Check of parameters for configuration of ADC hierarchical scope: */
+/* ADC group regular */
+#define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \
+ (((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH4 ) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \
+ )
+#define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__) \
+ (((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) \
+ || ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS) \
+ )
+
+#define IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__) \
+ (((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE) \
+ || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_LIMITED) \
+ || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED) \
+ )
+
+#define IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(__REG_OVR_DATA_BEHAVIOR__) \
+ (((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_PRESERVED) \
+ || ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_OVERWRITTEN) \
+ )
+
+#define IS_LL_ADC_REG_SEQ_MODE(__REG_SEQ_MODE__) \
+ (((__REG_SEQ_MODE__) == LL_ADC_REG_SEQ_FIXED) \
+ || ((__REG_SEQ_MODE__) == LL_ADC_REG_SEQ_CONFIGURABLE) \
+ )
+
+#define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__) \
+ (((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS) \
+ )
+
+#define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__) \
+ (((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \
+ || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK) \
+ )
+
+/**
+ * @}
+ */
+
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup ADC_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup ADC_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief De-initialize registers of all ADC instances belonging to
+ * the same ADC common instance to their default reset values.
+ * @note This function is performing a hard reset, using high level
+ * clock source RCC ADC reset.
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: ADC common registers are de-initialized
+ * - ERROR: not applicable
+ */
+ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
+
+ /* Force reset of ADC clock (core clock) */
+ LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_ADC);
+
+ /* Release reset of ADC clock (core clock) */
+ LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_ADC);
+
+ return SUCCESS;
+}
+
+/**
+ * @brief Initialize some features of ADC common parameters
+ * (all ADC instances belonging to the same ADC common instance)
+ * and multimode (for devices with several ADC instances available).
+ * @note The setting of ADC common parameters is conditioned to
+ * ADC instances state:
+ * All ADC instances belonging to the same ADC common instance
+ * must be disabled.
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: ADC common registers are initialized
+ * - ERROR: ADC common registers are not initialized
+ */
+ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
+{
+ ErrorStatus status = SUCCESS;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
+ assert_param(IS_LL_ADC_COMMON_CLOCK(ADC_CommonInitStruct->CommonClock));
+
+ /* Note: Hardware constraint (refer to description of functions */
+ /* "LL_ADC_SetCommonXXX()": */
+ /* On this STM32 series, setting of these features is conditioned to */
+ /* ADC state: */
+ /* All ADC instances of the ADC common group must be disabled. */
+ if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0UL)
+ {
+ /* Configuration of ADC hierarchical scope: */
+ /* - common to several ADC */
+ /* (all ADC instances belonging to the same ADC common instance) */
+ /* - Set ADC clock (conversion clock) */
+ LL_ADC_SetCommonClock(ADCxy_COMMON, ADC_CommonInitStruct->CommonClock);
+ }
+ else
+ {
+ /* Initialization error: One or several ADC instances belonging to */
+ /* the same ADC common instance are not disabled. */
+ status = ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Set each @ref LL_ADC_CommonInitTypeDef field to default value.
+ * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
+ * whose fields will be set to default values.
+ * @retval None
+ */
+void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
+{
+ /* Set ADC_CommonInitStruct fields to default values */
+ /* Set fields of ADC common */
+ /* (all ADC instances belonging to the same ADC common instance) */
+ ADC_CommonInitStruct->CommonClock = LL_ADC_CLOCK_ASYNC_DIV2;
+
+}
+
+/**
+ * @brief De-initialize registers of the selected ADC instance
+ * to their default reset values.
+ * @note To reset all ADC instances quickly (perform a hard reset),
+ * use function @ref LL_ADC_CommonDeInit().
+ * @note If this functions returns error status, it means that ADC instance
+ * is in an unknown state.
+ * In this case, perform a hard reset using high level
+ * clock source RCC ADC reset.
+ * Refer to function @ref LL_ADC_CommonDeInit().
+ * @param ADCx ADC instance
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: ADC registers are de-initialized
+ * - ERROR: ADC registers are not de-initialized
+ */
+ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
+{
+ ErrorStatus status = SUCCESS;
+
+ __IO uint32_t timeout_cpu_cycles = 0UL;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(ADCx));
+
+ /* Disable ADC instance if not already disabled. */
+ if (LL_ADC_IsEnabled(ADCx) == 1UL)
+ {
+ /* Set ADC group regular trigger source to SW start to ensure to not */
+ /* have an external trigger event occurring during the conversion stop */
+ /* ADC disable process. */
+ LL_ADC_REG_SetTriggerSource(ADCx, LL_ADC_REG_TRIG_SOFTWARE);
+
+ /* Stop potential ADC conversion on going on ADC group regular. */
+ if (LL_ADC_REG_IsConversionOngoing(ADCx) != 0UL)
+ {
+ if (LL_ADC_REG_IsStopConversionOngoing(ADCx) == 0UL)
+ {
+ LL_ADC_REG_StopConversion(ADCx);
+ }
+ }
+
+ /* Wait for ADC conversions are effectively stopped */
+ timeout_cpu_cycles = ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES;
+ while (LL_ADC_REG_IsStopConversionOngoing(ADCx) == 1UL)
+ {
+ timeout_cpu_cycles--;
+ if (timeout_cpu_cycles == 0UL)
+ {
+ /* Time-out error */
+ status = ERROR;
+ break;
+ }
+ }
+
+ /* Disable the ADC instance */
+ LL_ADC_Disable(ADCx);
+
+ /* Wait for ADC instance is effectively disabled */
+ timeout_cpu_cycles = ADC_TIMEOUT_DISABLE_CPU_CYCLES;
+ while (LL_ADC_IsDisableOngoing(ADCx) == 1UL)
+ {
+ timeout_cpu_cycles--;
+ if (timeout_cpu_cycles == 0UL)
+ {
+ /* Time-out error */
+ status = ERROR;
+ break;
+ }
+ }
+ }
+
+ /* Check whether ADC state is compliant with expected state */
+ if (READ_BIT(ADCx->CR,
+ (ADC_CR_ADSTP | ADC_CR_ADSTART
+ | ADC_CR_ADDIS | ADC_CR_ADEN)
+ )
+ == 0UL)
+ {
+ /* ========== Reset ADC registers ========== */
+ /* Reset register IER */
+ CLEAR_BIT(ADCx->IER,
+ (LL_ADC_IT_ADRDY
+ | LL_ADC_IT_EOC
+ | LL_ADC_IT_EOS
+ | LL_ADC_IT_OVR
+ | LL_ADC_IT_EOSMP
+ | LL_ADC_IT_AWD1
+ | LL_ADC_IT_AWD2
+ | LL_ADC_IT_AWD3
+ | LL_ADC_IT_EOCAL
+ | LL_ADC_IT_CCRDY
+ )
+ );
+
+ /* Reset register ISR */
+ SET_BIT(ADCx->ISR,
+ (LL_ADC_FLAG_ADRDY
+ | LL_ADC_FLAG_EOC
+ | LL_ADC_FLAG_EOS
+ | LL_ADC_FLAG_OVR
+ | LL_ADC_FLAG_EOSMP
+ | LL_ADC_FLAG_AWD1
+ | LL_ADC_FLAG_AWD2
+ | LL_ADC_FLAG_AWD3
+ | LL_ADC_FLAG_EOCAL
+ | LL_ADC_FLAG_CCRDY
+ )
+ );
+
+ /* Reset register CR */
+ /* Bits ADC_CR_ADCAL, ADC_CR_ADSTP, ADC_CR_ADSTART are in access mode */
+ /* "read-set": no direct reset applicable. */
+ CLEAR_BIT(ADCx->CR, ADC_CR_ADVREGEN);
+
+ /* Reset register CFGR1 */
+ CLEAR_BIT(ADCx->CFGR1,
+ (ADC_CFGR1_AWD1CH | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL | ADC_CFGR1_DISCEN
+ | ADC_CFGR1_AUTOFF | ADC_CFGR1_WAIT | ADC_CFGR1_CONT | ADC_CFGR1_OVRMOD
+ | ADC_CFGR1_EXTEN | ADC_CFGR1_EXTSEL | ADC_CFGR1_ALIGN | ADC_CFGR1_RES
+ | ADC_CFGR1_SCANDIR | ADC_CFGR1_DMACFG | ADC_CFGR1_DMAEN)
+ );
+
+ /* Reset register CFGR2 */
+ /* Note: Update of ADC clock mode is conditioned to ADC state disabled: */
+ /* already done above. */
+ CLEAR_BIT(ADCx->CFGR2,
+ (ADC_CFGR2_CKMODE
+ | ADC_CFGR2_TOVS | ADC_CFGR2_OVSS | ADC_CFGR2_OVSR
+ | ADC_CFGR2_OVSE)
+ );
+
+ /* Reset register SMPR */
+ CLEAR_BIT(ADCx->SMPR, ADC_SMPR_SMP1 | ADC_SMPR_SMP2 | ADC_SMPR_SMPSEL);
+
+ /* Reset register TR1 */
+ MODIFY_REG(ADCx->TR1, ADC_TR1_HT1 | ADC_TR1_LT1, ADC_TR1_HT1);
+
+ /* Reset register TR2 */
+ MODIFY_REG(ADCx->TR2, ADC_TR2_HT2 | ADC_TR2_LT2, ADC_TR2_HT2);
+
+ /* Reset register TR3 */
+ MODIFY_REG(ADCx->TR3, ADC_TR3_HT3 | ADC_TR3_LT3, ADC_TR3_HT3);
+
+ /* Reset register CHSELR */
+ CLEAR_BIT(ADCx->CHSELR,
+ (ADC_CHSELR_CHSEL18 | ADC_CHSELR_CHSEL17 | ADC_CHSELR_CHSEL16
+ | ADC_CHSELR_CHSEL15 | ADC_CHSELR_CHSEL14 | ADC_CHSELR_CHSEL13 | ADC_CHSELR_CHSEL12
+ | ADC_CHSELR_CHSEL11 | ADC_CHSELR_CHSEL10 | ADC_CHSELR_CHSEL9 | ADC_CHSELR_CHSEL8
+ | ADC_CHSELR_CHSEL7 | ADC_CHSELR_CHSEL6 | ADC_CHSELR_CHSEL5 | ADC_CHSELR_CHSEL4
+ | ADC_CHSELR_CHSEL3 | ADC_CHSELR_CHSEL2 | ADC_CHSELR_CHSEL1 | ADC_CHSELR_CHSEL0)
+ );
+
+ /* Wait for ADC channel configuration ready */
+ timeout_cpu_cycles = ADC_TIMEOUT_CCRDY_CPU_CYCLES;
+ while (LL_ADC_IsActiveFlag_CCRDY(ADCx) == 0UL)
+ {
+ timeout_cpu_cycles--;
+ if (timeout_cpu_cycles == 0UL)
+ {
+ /* Time-out error */
+ status = ERROR;
+ break;
+ }
+ }
+
+ /* Clear flag ADC channel configuration ready */
+ LL_ADC_ClearFlag_CCRDY(ADCx);
+
+ /* Reset register DR */
+ /* bits in access mode read only, no direct reset applicable */
+
+ /* Reset register CALFACT */
+ CLEAR_BIT(ADCx->CALFACT, ADC_CALFACT_CALFACT);
+
+ }
+ else
+ {
+ /* ADC instance is in an unknown state */
+ /* Need to performing a hard reset of ADC instance, using high level */
+ /* clock source RCC ADC reset. */
+ /* Caution: On this STM32 series, if several ADC instances are available */
+ /* on the selected device, RCC ADC reset will reset */
+ /* all ADC instances belonging to the common ADC instance. */
+ status = ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Initialize some features of ADC instance.
+ * @note These parameters have an impact on ADC scope: ADC instance.
+ * Refer to corresponding unitary functions into
+ * @ref ADC_LL_EF_Configuration_ADC_Instance .
+ * @note The setting of these parameters by function @ref LL_ADC_Init()
+ * is conditioned to ADC state:
+ * ADC instance must be disabled.
+ * This condition is applied to all ADC features, for efficiency
+ * and compatibility over all STM32 families. However, the different
+ * features can be set under different ADC state conditions
+ * (setting possible with ADC enabled without conversion on going,
+ * ADC enabled with conversion on going, ...)
+ * Each feature can be updated afterwards with a unitary function
+ * and potentially with ADC in a different state than disabled,
+ * refer to description of each function for setting
+ * conditioned to ADC state.
+ * @note After using this function, some other features must be configured
+ * using LL unitary functions.
+ * The minimum configuration remaining to be done is:
+ * - Set ADC group regular sequencer:
+ * Depending on the sequencer mode (refer to
+ * function @ref LL_ADC_REG_SetSequencerConfigurable() ):
+ * - map channel on the selected sequencer rank.
+ * Refer to function @ref LL_ADC_REG_SetSequencerRanks();
+ * - map channel on rank corresponding to channel number.
+ * Refer to function @ref LL_ADC_REG_SetSequencerChannels();
+ * - Set ADC channel sampling time
+ * Refer to function LL_ADC_SetSamplingTimeCommonChannels();
+ * Refer to function LL_ADC_SetChannelSamplingTime();
+ * @param ADCx ADC instance
+ * @param ADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: ADC registers are initialized
+ * - ERROR: ADC registers are not initialized
+ */
+ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct)
+{
+ ErrorStatus status = SUCCESS;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(ADCx));
+
+ assert_param(IS_LL_ADC_CLOCK(ADC_InitStruct->Clock));
+ assert_param(IS_LL_ADC_RESOLUTION(ADC_InitStruct->Resolution));
+ assert_param(IS_LL_ADC_DATA_ALIGN(ADC_InitStruct->DataAlignment));
+ assert_param(IS_LL_ADC_LOW_POWER(ADC_InitStruct->LowPowerMode));
+
+ /* Note: Hardware constraint (refer to description of this function): */
+ /* ADC instance must be disabled. */
+ if (LL_ADC_IsEnabled(ADCx) == 0UL)
+ {
+ /* Configuration of ADC hierarchical scope: */
+ /* - ADC instance */
+ /* - Set ADC data resolution */
+ /* - Set ADC conversion data alignment */
+ /* - Set ADC low power mode */
+ MODIFY_REG(ADCx->CFGR1,
+ ADC_CFGR1_RES
+ | ADC_CFGR1_ALIGN
+ | ADC_CFGR1_WAIT
+ | ADC_CFGR1_AUTOFF
+ ,
+ ADC_InitStruct->Resolution
+ | ADC_InitStruct->DataAlignment
+ | ADC_InitStruct->LowPowerMode
+ );
+
+ MODIFY_REG(ADCx->CFGR2,
+ ADC_CFGR2_CKMODE
+ ,
+ ADC_InitStruct->Clock
+ );
+ }
+ else
+ {
+ /* Initialization error: ADC instance is not disabled. */
+ status = ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Set each @ref LL_ADC_InitTypeDef field to default value.
+ * @param ADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure
+ * whose fields will be set to default values.
+ * @retval None
+ */
+void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct)
+{
+ /* Set ADC_InitStruct fields to default values */
+ /* Set fields of ADC instance */
+ ADC_InitStruct->Clock = LL_ADC_CLOCK_SYNC_PCLK_DIV2;
+ ADC_InitStruct->Resolution = LL_ADC_RESOLUTION_12B;
+ ADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT;
+ ADC_InitStruct->LowPowerMode = LL_ADC_LP_MODE_NONE;
+
+}
+
+/**
+ * @brief Initialize some features of ADC group regular.
+ * @note These parameters have an impact on ADC scope: ADC group regular.
+ * Refer to corresponding unitary functions into
+ * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
+ * (functions with prefix "REG").
+ * @note The setting of these parameters by function @ref LL_ADC_Init()
+ * is conditioned to ADC state:
+ * ADC instance must be disabled.
+ * This condition is applied to all ADC features, for efficiency
+ * and compatibility over all STM32 families. However, the different
+ * features can be set under different ADC state conditions
+ * (setting possible with ADC enabled without conversion on going,
+ * ADC enabled with conversion on going, ...)
+ * Each feature can be updated afterwards with a unitary function
+ * and potentially with ADC in a different state than disabled,
+ * refer to description of each function for setting
+ * conditioned to ADC state.
+ * @note Before using this function, ADC group regular sequencer
+ * must be configured: refer to function
+ * @ref LL_ADC_REG_SetSequencerConfigurable().
+ * @note After using this function, other features must be configured
+ * using LL unitary functions.
+ * The minimum configuration remaining to be done is:
+ * - Set ADC group regular sequencer:
+ * Depending on the sequencer mode (refer to
+ * function @ref LL_ADC_REG_SetSequencerConfigurable() ):
+ * - map channel on the selected sequencer rank.
+ * Refer to function @ref LL_ADC_REG_SetSequencerRanks();
+ * - map channel on rank corresponding to channel number.
+ * Refer to function @ref LL_ADC_REG_SetSequencerChannels();
+ * - Set ADC channel sampling time
+ * Refer to function LL_ADC_SetSamplingTimeCommonChannels();
+ * Refer to function LL_ADC_SetChannelSamplingTime();
+ * @param ADCx ADC instance
+ * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: ADC registers are initialized
+ * - ERROR: ADC registers are not initialized
+ */
+ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
+{
+ ErrorStatus status = SUCCESS;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(ADCx));
+ assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADC_REG_InitStruct->TriggerSource));
+ assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode));
+ assert_param(IS_LL_ADC_REG_DMA_TRANSFER(ADC_REG_InitStruct->DMATransfer));
+ assert_param(IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(ADC_REG_InitStruct->Overrun));
+
+ if (LL_ADC_REG_GetSequencerConfigurable(ADCx) != LL_ADC_REG_SEQ_FIXED)
+ {
+ assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(ADC_REG_InitStruct->SequencerLength));
+ }
+
+ if ((LL_ADC_REG_GetSequencerConfigurable(ADCx) == LL_ADC_REG_SEQ_FIXED)
+ || (ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
+ )
+ {
+ assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont));
+
+ /* ADC group regular continuous mode and discontinuous mode */
+ /* can not be enabled simultenaeously */
+ assert_param((ADC_REG_InitStruct->ContinuousMode == LL_ADC_REG_CONV_SINGLE)
+ || (ADC_REG_InitStruct->SequencerDiscont == LL_ADC_REG_SEQ_DISCONT_DISABLE));
+ }
+
+ /* Note: Hardware constraint (refer to description of this function): */
+ /* ADC instance must be disabled. */
+ if (LL_ADC_IsEnabled(ADCx) == 0UL)
+ {
+ /* Configuration of ADC hierarchical scope: */
+ /* - ADC group regular */
+ /* - Set ADC group regular trigger source */
+ /* - Set ADC group regular sequencer length */
+ /* - Set ADC group regular sequencer discontinuous mode */
+ /* - Set ADC group regular continuous mode */
+ /* - Set ADC group regular conversion data transfer: no transfer or */
+ /* transfer by DMA, and DMA requests mode */
+ /* - Set ADC group regular overrun behavior */
+ /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by */
+ /* setting of trigger source to SW start. */
+ if ((LL_ADC_REG_GetSequencerConfigurable(ADCx) == LL_ADC_REG_SEQ_FIXED)
+ || (ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
+ )
+ {
+ /* Case of sequencer mode fixed
+ or sequencer length >= 2 ranks with sequencer mode fully configurable:
+ discontinuous mode configured */
+ MODIFY_REG(ADCx->CFGR1,
+ ADC_CFGR1_EXTSEL
+ | ADC_CFGR1_EXTEN
+ | ADC_CFGR1_DISCEN
+ | ADC_CFGR1_CONT
+ | ADC_CFGR1_DMAEN
+ | ADC_CFGR1_DMACFG
+ | ADC_CFGR1_OVRMOD
+ ,
+ ADC_REG_InitStruct->TriggerSource
+ | ADC_REG_InitStruct->SequencerDiscont
+ | ADC_REG_InitStruct->ContinuousMode
+ | ADC_REG_InitStruct->DMATransfer
+ | ADC_REG_InitStruct->Overrun
+ );
+ }
+ else
+ {
+ /* Case of sequencer mode fully configurable
+ and sequencer length 1 rank (sequencer disabled):
+ discontinuous mode discarded (fixed to disable) */
+ MODIFY_REG(ADCx->CFGR1,
+ ADC_CFGR1_EXTSEL
+ | ADC_CFGR1_EXTEN
+ | ADC_CFGR1_DISCEN
+ | ADC_CFGR1_CONT
+ | ADC_CFGR1_DMAEN
+ | ADC_CFGR1_DMACFG
+ | ADC_CFGR1_OVRMOD
+ ,
+ ADC_REG_InitStruct->TriggerSource
+ | LL_ADC_REG_SEQ_DISCONT_DISABLE
+ | ADC_REG_InitStruct->ContinuousMode
+ | ADC_REG_InitStruct->DMATransfer
+ | ADC_REG_InitStruct->Overrun
+ );
+ }
+
+ /* Set ADC group regular sequencer length */
+ if (LL_ADC_REG_GetSequencerConfigurable(ADCx) != LL_ADC_REG_SEQ_FIXED)
+ {
+ LL_ADC_REG_SetSequencerLength(ADCx, ADC_REG_InitStruct->SequencerLength);
+ }
+ }
+ else
+ {
+ /* Initialization error: ADC instance is not disabled. */
+ status = ERROR;
+ }
+ return status;
+}
+
+/**
+ * @brief Set each @ref LL_ADC_REG_InitTypeDef field to default value.
+ * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
+ * whose fields will be set to default values.
+ * @retval None
+ */
+void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
+{
+ /* Set ADC_REG_InitStruct fields to default values */
+ /* Set fields of ADC group regular */
+ /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by */
+ /* setting of trigger source to SW start. */
+ ADC_REG_InitStruct->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE;
+ ADC_REG_InitStruct->SequencerLength = LL_ADC_REG_SEQ_SCAN_DISABLE;
+ ADC_REG_InitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE;
+ ADC_REG_InitStruct->ContinuousMode = LL_ADC_REG_CONV_SINGLE;
+ ADC_REG_InitStruct->DMATransfer = LL_ADC_REG_DMA_TRANSFER_NONE;
+ ADC_REG_InitStruct->Overrun = LL_ADC_REG_OVR_DATA_OVERWRITTEN;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* ADC1 */
+
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_ll_crc.c b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_ll_crc.c
new file mode 100644
index 0000000000..3f07530cf2
--- /dev/null
+++ b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_ll_crc.c
@@ -0,0 +1,103 @@
+/**
+ ******************************************************************************
+ * @file stm32c0xx_ll_crc.c
+ * @author MCD Application Team
+ * @brief CRC LL module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2022 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32c0xx_ll_crc.h"
+#include "stm32c0xx_ll_bus.h"
+
+#ifdef USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+/** @addtogroup STM32C0xx_LL_Driver
+ * @{
+ */
+
+#if defined (CRC)
+
+/** @addtogroup CRC_LL
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup CRC_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup CRC_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief De-initialize CRC registers (Registers restored to their default values).
+ * @param CRCx CRC Instance
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: CRC registers are de-initialized
+ * - ERROR: CRC registers are not de-initialized
+ */
+ErrorStatus LL_CRC_DeInit(CRC_TypeDef *CRCx)
+{
+ ErrorStatus status = SUCCESS;
+
+ /* Check the parameters */
+ assert_param(IS_CRC_ALL_INSTANCE(CRCx));
+
+ if (CRCx == CRC)
+ {
+ /* Force CRC reset */
+ LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_CRC);
+
+ /* Release CRC reset */
+ LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_CRC);
+ }
+ else
+ {
+ status = ERROR;
+ }
+
+ return (status);
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined (CRC) */
+
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_ll_dma.c b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_ll_dma.c
new file mode 100644
index 0000000000..3f0cf6f241
--- /dev/null
+++ b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_ll_dma.c
@@ -0,0 +1,296 @@
+/**
+ ******************************************************************************
+ * @file stm32c0xx_ll_dma.c
+ * @author MCD Application Team
+ * @brief DMA LL module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2022 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32c0xx_ll_dma.h"
+#include "stm32c0xx_ll_bus.h"
+#ifdef USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+/** @addtogroup STM32C0xx_LL_Driver
+ * @{
+ */
+
+#if defined (DMA1)
+
+/** @defgroup DMA_LL DMA
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup DMA_LL_Private_Macros
+ * @{
+ */
+#define IS_LL_DMA_DIRECTION(__VALUE__) (((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) || \
+ ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) || \
+ ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY))
+
+#define IS_LL_DMA_MODE(__VALUE__) (((__VALUE__) == LL_DMA_MODE_NORMAL) || \
+ ((__VALUE__) == LL_DMA_MODE_CIRCULAR))
+
+#define IS_LL_DMA_PERIPHINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_PERIPH_INCREMENT) || \
+ ((__VALUE__) == LL_DMA_PERIPH_NOINCREMENT))
+
+#define IS_LL_DMA_MEMORYINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_MEMORY_INCREMENT) || \
+ ((__VALUE__) == LL_DMA_MEMORY_NOINCREMENT))
+
+#define IS_LL_DMA_PERIPHDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_PDATAALIGN_BYTE) || \
+ ((__VALUE__) == LL_DMA_PDATAALIGN_HALFWORD) || \
+ ((__VALUE__) == LL_DMA_PDATAALIGN_WORD))
+
+#define IS_LL_DMA_MEMORYDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_MDATAALIGN_BYTE) || \
+ ((__VALUE__) == LL_DMA_MDATAALIGN_HALFWORD) || \
+ ((__VALUE__) == LL_DMA_MDATAALIGN_WORD))
+
+#define IS_LL_DMA_NBDATA(__VALUE__) ((__VALUE__) <= 0x0000FFFFU)
+
+
+#define IS_LL_DMA_PERIPHREQUEST(__VALUE__) ((__VALUE__) <= LL_DMAMUX_REQ_USART2_TX)
+
+#define IS_LL_DMA_PRIORITY(__VALUE__) (((__VALUE__) == LL_DMA_PRIORITY_LOW) || \
+ ((__VALUE__) == LL_DMA_PRIORITY_MEDIUM) || \
+ ((__VALUE__) == LL_DMA_PRIORITY_HIGH) || \
+ ((__VALUE__) == LL_DMA_PRIORITY_VERYHIGH))
+
+#define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \
+ (((CHANNEL) == LL_DMA_CHANNEL_1) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_2) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_3))))
+
+/**
+ * @}
+ */
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup DMA_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup DMA_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief De-initialize the DMA registers to their default reset values.
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_ALL
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: DMA registers are de-initialized
+ * - ERROR: DMA registers are not de-initialized
+ */
+ErrorStatus LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ ErrorStatus status = SUCCESS;
+
+ /* Check the DMA Instance DMAx and Channel parameters*/
+ assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel) || (Channel == LL_DMA_CHANNEL_ALL));
+
+ if (Channel == LL_DMA_CHANNEL_ALL)
+ {
+ if (DMAx == DMA1)
+ {
+ /* Force reset of DMA clock */
+ LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA1);
+
+ /* Release reset of DMA clock */
+ LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA1);
+ }
+ else
+ {
+ status = ERROR;
+ }
+ }
+ else
+ {
+ DMA_Channel_TypeDef *tmp;
+
+ tmp = (DMA_Channel_TypeDef *)(__LL_DMA_GET_CHANNEL_INSTANCE(DMAx, Channel));
+
+ /* Disable the selected DMAx_Channely */
+ CLEAR_BIT(tmp->CCR, DMA_CCR_EN);
+
+ /* Reset DMAx_Channely control register */
+ WRITE_REG(tmp->CCR, 0U);
+
+ /* Reset DMAx_Channely remaining bytes register */
+ WRITE_REG(tmp->CNDTR, 0U);
+
+ /* Reset DMAx_Channely peripheral address register */
+ WRITE_REG(tmp->CPAR, 0U);
+
+ /* Reset DMAx_Channely memory address register */
+ WRITE_REG(tmp->CMAR, 0U);
+
+ /* Reset Request register field for DMAx Channel */
+ LL_DMA_SetPeriphRequest(DMAx, Channel, LL_DMAMUX_REQ_MEM2MEM);
+
+ if (Channel == LL_DMA_CHANNEL_1)
+ {
+ /* Reset interrupt pending bits for DMAx Channel1 */
+ LL_DMA_ClearFlag_GI1(DMAx);
+ }
+ else if (Channel == LL_DMA_CHANNEL_2)
+ {
+ /* Reset interrupt pending bits for DMAx Channel2 */
+ LL_DMA_ClearFlag_GI2(DMAx);
+ }
+ else if (Channel == LL_DMA_CHANNEL_3)
+ {
+ /* Reset interrupt pending bits for DMAx Channel3 */
+ LL_DMA_ClearFlag_GI3(DMAx);
+ }
+ else
+ {
+ status = ERROR;
+ }
+ }
+
+ return status;
+}
+
+/**
+ * @brief Initialize the DMA registers according to the specified parameters in DMA_InitStruct.
+ * @note To convert DMAx_Channely Instance to DMAx Instance and Channely, use helper macros :
+ * @arg @ref __LL_DMA_GET_INSTANCE
+ * @arg @ref __LL_DMA_GET_CHANNEL
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @param DMA_InitStruct pointer to a @ref LL_DMA_InitTypeDef structure.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: DMA registers are initialized
+ * - ERROR: Not applicable
+ */
+ErrorStatus LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct)
+{
+ /* Check the DMA Instance DMAx and Channel parameters*/
+ assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel));
+
+ /* Check the DMA parameters from DMA_InitStruct */
+ assert_param(IS_LL_DMA_DIRECTION(DMA_InitStruct->Direction));
+ assert_param(IS_LL_DMA_MODE(DMA_InitStruct->Mode));
+ assert_param(IS_LL_DMA_PERIPHINCMODE(DMA_InitStruct->PeriphOrM2MSrcIncMode));
+ assert_param(IS_LL_DMA_MEMORYINCMODE(DMA_InitStruct->MemoryOrM2MDstIncMode));
+ assert_param(IS_LL_DMA_PERIPHDATASIZE(DMA_InitStruct->PeriphOrM2MSrcDataSize));
+ assert_param(IS_LL_DMA_MEMORYDATASIZE(DMA_InitStruct->MemoryOrM2MDstDataSize));
+ assert_param(IS_LL_DMA_NBDATA(DMA_InitStruct->NbData));
+ assert_param(IS_LL_DMA_PERIPHREQUEST(DMA_InitStruct->PeriphRequest));
+ assert_param(IS_LL_DMA_PRIORITY(DMA_InitStruct->Priority));
+
+ /*---------------------------- DMAx CCR Configuration ------------------------
+ * Configure DMAx_Channely: data transfer direction, data transfer mode,
+ * peripheral and memory increment mode,
+ * data size alignment and priority level with parameters :
+ * - Direction: DMA_CCR_DIR and DMA_CCR_MEM2MEM bits
+ * - Mode: DMA_CCR_CIRC bit
+ * - PeriphOrM2MSrcIncMode: DMA_CCR_PINC bit
+ * - MemoryOrM2MDstIncMode: DMA_CCR_MINC bit
+ * - PeriphOrM2MSrcDataSize: DMA_CCR_PSIZE[1:0] bits
+ * - MemoryOrM2MDstDataSize: DMA_CCR_MSIZE[1:0] bits
+ * - Priority: DMA_CCR_PL[1:0] bits
+ */
+ LL_DMA_ConfigTransfer(DMAx, Channel, DMA_InitStruct->Direction | \
+ DMA_InitStruct->Mode | \
+ DMA_InitStruct->PeriphOrM2MSrcIncMode | \
+ DMA_InitStruct->MemoryOrM2MDstIncMode | \
+ DMA_InitStruct->PeriphOrM2MSrcDataSize | \
+ DMA_InitStruct->MemoryOrM2MDstDataSize | \
+ DMA_InitStruct->Priority);
+
+ /*-------------------------- DMAx CMAR Configuration -------------------------
+ * Configure the memory or destination base address with parameter :
+ * - MemoryOrM2MDstAddress: DMA_CMAR_MA[31:0] bits
+ */
+ LL_DMA_SetMemoryAddress(DMAx, Channel, DMA_InitStruct->MemoryOrM2MDstAddress);
+
+ /*-------------------------- DMAx CPAR Configuration -------------------------
+ * Configure the peripheral or source base address with parameter :
+ * - PeriphOrM2MSrcAddress: DMA_CPAR_PA[31:0] bits
+ */
+ LL_DMA_SetPeriphAddress(DMAx, Channel, DMA_InitStruct->PeriphOrM2MSrcAddress);
+
+ /*--------------------------- DMAx CNDTR Configuration -----------------------
+ * Configure the peripheral base address with parameter :
+ * - NbData: DMA_CNDTR_NDT[15:0] bits
+ */
+ LL_DMA_SetDataLength(DMAx, Channel, DMA_InitStruct->NbData);
+
+ /*--------------------------- DMAMUXx CCR Configuration ----------------------
+ * Configure the DMA request for DMA Channels on DMAMUX Channel x with parameter :
+ * - PeriphRequest: DMA_CxCR[7:0] bits
+ */
+ LL_DMA_SetPeriphRequest(DMAx, Channel, DMA_InitStruct->PeriphRequest);
+
+ return SUCCESS;
+}
+
+/**
+ * @brief Set each @ref LL_DMA_InitTypeDef field to default value.
+ * @param DMA_InitStruct Pointer to a @ref LL_DMA_InitTypeDef structure.
+ * @retval None
+ */
+void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct)
+{
+ /* Set DMA_InitStruct fields to default values */
+ DMA_InitStruct->PeriphOrM2MSrcAddress = 0x00000000U;
+ DMA_InitStruct->MemoryOrM2MDstAddress = 0x00000000U;
+ DMA_InitStruct->Direction = LL_DMA_DIRECTION_PERIPH_TO_MEMORY;
+ DMA_InitStruct->Mode = LL_DMA_MODE_NORMAL;
+ DMA_InitStruct->PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT;
+ DMA_InitStruct->MemoryOrM2MDstIncMode = LL_DMA_MEMORY_NOINCREMENT;
+ DMA_InitStruct->PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE;
+ DMA_InitStruct->MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE;
+ DMA_InitStruct->NbData = 0x00000000U;
+ DMA_InitStruct->PeriphRequest = LL_DMAMUX_REQ_MEM2MEM;
+ DMA_InitStruct->Priority = LL_DMA_PRIORITY_LOW;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* DMA1 */
+
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_ll_exti.c b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_ll_exti.c
new file mode 100644
index 0000000000..50af5587c6
--- /dev/null
+++ b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_ll_exti.c
@@ -0,0 +1,212 @@
+/**
+ ******************************************************************************
+ * @file stm32c0xx_ll_exti.c
+ * @author MCD Application Team
+ * @brief EXTI LL module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2022 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32c0xx_ll_exti.h"
+#ifdef USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+/** @addtogroup STM32C0xx_LL_Driver
+ * @{
+ */
+
+#if defined (EXTI)
+
+/** @defgroup EXTI_LL EXTI
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup EXTI_LL_Private_Macros
+ * @{
+ */
+
+#define IS_LL_EXTI_LINE_0_31(__VALUE__) (((__VALUE__) & ~LL_EXTI_LINE_ALL_0_31) == 0x00000000U)
+
+#define IS_LL_EXTI_MODE(__VALUE__) (((__VALUE__) == LL_EXTI_MODE_IT) \
+ || ((__VALUE__) == LL_EXTI_MODE_EVENT) \
+ || ((__VALUE__) == LL_EXTI_MODE_IT_EVENT))
+
+
+#define IS_LL_EXTI_TRIGGER(__VALUE__) (((__VALUE__) == LL_EXTI_TRIGGER_NONE) \
+ || ((__VALUE__) == LL_EXTI_TRIGGER_RISING) \
+ || ((__VALUE__) == LL_EXTI_TRIGGER_FALLING) \
+ || ((__VALUE__) == LL_EXTI_TRIGGER_RISING_FALLING))
+
+/**
+ * @}
+ */
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup EXTI_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup EXTI_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief De-initialize the EXTI registers to their default reset values.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: EXTI registers are de-initialized
+ * - ERROR: not applicable
+ */
+ErrorStatus LL_EXTI_DeInit(void)
+{
+ /* Interrupt mask register set to default reset values */
+ LL_EXTI_WriteReg(IMR1, 0xFFF80000U);
+ /* Event mask register set to default reset values */
+ LL_EXTI_WriteReg(EMR1, 0x00000000U);
+ /* Rising Trigger selection register set to default reset values */
+ LL_EXTI_WriteReg(RTSR1, 0x00000000U);
+ /* Falling Trigger selection register set to default reset values */
+ LL_EXTI_WriteReg(FTSR1, 0x00000000U);
+ /* Software interrupt event register set to default reset values */
+ LL_EXTI_WriteReg(SWIER1, 0x00000000U);
+ /* Pending register set to default reset values */
+ LL_EXTI_WriteReg(RPR1, 0x0007FFFFU);
+ LL_EXTI_WriteReg(FPR1, 0x0007FFFFU);
+ return SUCCESS;
+}
+
+/**
+ * @brief Initialize the EXTI registers according to the specified parameters in EXTI_InitStruct.
+ * @param EXTI_InitStruct pointer to a @ref LL_EXTI_InitTypeDef structure.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: EXTI registers are initialized
+ * - ERROR: not applicable
+ */
+ErrorStatus LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct)
+{
+ ErrorStatus status = SUCCESS;
+ /* Check the parameters */
+ assert_param(IS_LL_EXTI_LINE_0_31(EXTI_InitStruct->Line_0_31));
+ assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->LineCommand));
+ assert_param(IS_LL_EXTI_MODE(EXTI_InitStruct->Mode));
+
+ /* ENABLE LineCommand */
+ if (EXTI_InitStruct->LineCommand != DISABLE)
+ {
+ assert_param(IS_LL_EXTI_TRIGGER(EXTI_InitStruct->Trigger));
+
+ /* Configure EXTI Lines in range from 0 to 31 */
+ if (EXTI_InitStruct->Line_0_31 != LL_EXTI_LINE_NONE)
+ {
+ switch (EXTI_InitStruct->Mode)
+ {
+ case LL_EXTI_MODE_IT:
+ /* First Disable Event on provided Lines */
+ LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31);
+ /* Then Enable IT on provided Lines */
+ LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31);
+ break;
+ case LL_EXTI_MODE_EVENT:
+ /* First Disable IT on provided Lines */
+ LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31);
+ /* Then Enable Event on provided Lines */
+ LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31);
+ break;
+ case LL_EXTI_MODE_IT_EVENT:
+ /* Directly Enable IT & Event on provided Lines */
+ LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31);
+ LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31);
+ break;
+ default:
+ status = ERROR;
+ break;
+ }
+ if (EXTI_InitStruct->Trigger != LL_EXTI_TRIGGER_NONE)
+ {
+ switch (EXTI_InitStruct->Trigger)
+ {
+ case LL_EXTI_TRIGGER_RISING:
+ /* First Disable Falling Trigger on provided Lines */
+ LL_EXTI_DisableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
+ /* Then Enable Rising Trigger on provided Lines */
+ LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
+ break;
+ case LL_EXTI_TRIGGER_FALLING:
+ /* First Disable Rising Trigger on provided Lines */
+ LL_EXTI_DisableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
+ /* Then Enable Falling Trigger on provided Lines */
+ LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
+ break;
+ case LL_EXTI_TRIGGER_RISING_FALLING:
+ LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
+ LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
+ break;
+ default:
+ status = ERROR;
+ break;
+ }
+ }
+ }
+
+ }
+ /* DISABLE LineCommand */
+ else
+ {
+ /* De-configure EXTI Lines in range from 0 to 31 */
+ LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31);
+ LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31);
+ }
+ return status;
+}
+/**
+ * @brief Set each @ref LL_EXTI_InitTypeDef field to default value.
+ * @param EXTI_InitStruct Pointer to a @ref LL_EXTI_InitTypeDef structure.
+ * @retval None
+ */
+void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct)
+{
+ EXTI_InitStruct->Line_0_31 = LL_EXTI_LINE_NONE;
+
+ EXTI_InitStruct->LineCommand = DISABLE;
+ EXTI_InitStruct->Mode = LL_EXTI_MODE_IT;
+ EXTI_InitStruct->Trigger = LL_EXTI_TRIGGER_FALLING;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined (EXTI) */
+
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_ll_gpio.c b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_ll_gpio.c
new file mode 100644
index 0000000000..acd124ae16
--- /dev/null
+++ b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_ll_gpio.c
@@ -0,0 +1,260 @@
+/**
+ ******************************************************************************
+ * @file stm32c0xx_ll_gpio.c
+ * @author MCD Application Team
+ * @brief GPIO LL module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2022 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32c0xx_ll_gpio.h"
+#include "stm32c0xx_ll_bus.h"
+#ifdef USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+/** @addtogroup STM32C0xx_LL_Driver
+ * @{
+ */
+
+#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOF)
+
+/** @addtogroup GPIO_LL
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup GPIO_LL_Private_Macros
+ * @{
+ */
+#define IS_LL_GPIO_PIN(__VALUE__) (((0x00u) < (__VALUE__)) && ((__VALUE__) <= (LL_GPIO_PIN_ALL)))
+
+#define IS_LL_GPIO_MODE(__VALUE__) (((__VALUE__) == LL_GPIO_MODE_INPUT) ||\
+ ((__VALUE__) == LL_GPIO_MODE_OUTPUT) ||\
+ ((__VALUE__) == LL_GPIO_MODE_ALTERNATE) ||\
+ ((__VALUE__) == LL_GPIO_MODE_ANALOG))
+
+#define IS_LL_GPIO_OUTPUT_TYPE(__VALUE__) (((__VALUE__) == LL_GPIO_OUTPUT_PUSHPULL) ||\
+ ((__VALUE__) == LL_GPIO_OUTPUT_OPENDRAIN))
+
+#define IS_LL_GPIO_SPEED(__VALUE__) (((__VALUE__) == LL_GPIO_SPEED_FREQ_LOW) ||\
+ ((__VALUE__) == LL_GPIO_SPEED_FREQ_MEDIUM) ||\
+ ((__VALUE__) == LL_GPIO_SPEED_FREQ_HIGH) ||\
+ ((__VALUE__) == LL_GPIO_SPEED_FREQ_VERY_HIGH))
+
+#define IS_LL_GPIO_PULL(__VALUE__) (((__VALUE__) == LL_GPIO_PULL_NO) ||\
+ ((__VALUE__) == LL_GPIO_PULL_UP) ||\
+ ((__VALUE__) == LL_GPIO_PULL_DOWN))
+
+#define IS_LL_GPIO_ALTERNATE(__VALUE__) (((__VALUE__) == LL_GPIO_AF_0 ) ||\
+ ((__VALUE__) == LL_GPIO_AF_1 ) ||\
+ ((__VALUE__) == LL_GPIO_AF_2 ) ||\
+ ((__VALUE__) == LL_GPIO_AF_3 ) ||\
+ ((__VALUE__) == LL_GPIO_AF_4 ) ||\
+ ((__VALUE__) == LL_GPIO_AF_5 ) ||\
+ ((__VALUE__) == LL_GPIO_AF_6 ) ||\
+ ((__VALUE__) == LL_GPIO_AF_7 ) ||\
+ ((__VALUE__) == LL_GPIO_AF_8 ) ||\
+ ((__VALUE__) == LL_GPIO_AF_9 ) ||\
+ ((__VALUE__) == LL_GPIO_AF_10 ) ||\
+ ((__VALUE__) == LL_GPIO_AF_11 ) ||\
+ ((__VALUE__) == LL_GPIO_AF_12 ) ||\
+ ((__VALUE__) == LL_GPIO_AF_13 ) ||\
+ ((__VALUE__) == LL_GPIO_AF_14 ) ||\
+ ((__VALUE__) == LL_GPIO_AF_15 ))
+/**
+ * @}
+ */
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup GPIO_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup GPIO_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief De-initialize GPIO registers (Registers restored to their default values).
+ * @param GPIOx GPIO Port
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: GPIO registers are de-initialized
+ * - ERROR: Wrong GPIO Port
+ */
+ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx)
+{
+ ErrorStatus status = SUCCESS;
+
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+
+ /* Force and Release reset on clock of GPIOx Port */
+ if (GPIOx == GPIOA)
+ {
+ LL_IOP_GRP1_ForceReset(LL_IOP_GRP1_PERIPH_GPIOA);
+ LL_IOP_GRP1_ReleaseReset(LL_IOP_GRP1_PERIPH_GPIOA);
+ }
+ else if (GPIOx == GPIOB)
+ {
+ LL_IOP_GRP1_ForceReset(LL_IOP_GRP1_PERIPH_GPIOB);
+ LL_IOP_GRP1_ReleaseReset(LL_IOP_GRP1_PERIPH_GPIOB);
+ }
+ else if (GPIOx == GPIOC)
+ {
+ LL_IOP_GRP1_ForceReset(LL_IOP_GRP1_PERIPH_GPIOC);
+ LL_IOP_GRP1_ReleaseReset(LL_IOP_GRP1_PERIPH_GPIOC);
+ }
+#if defined(GPIOD)
+ else if (GPIOx == GPIOD)
+ {
+ LL_IOP_GRP1_ForceReset(LL_IOP_GRP1_PERIPH_GPIOD);
+ LL_IOP_GRP1_ReleaseReset(LL_IOP_GRP1_PERIPH_GPIOD);
+ }
+#endif /* GPIOD */
+ else if (GPIOx == GPIOF)
+ {
+ LL_IOP_GRP1_ForceReset(LL_IOP_GRP1_PERIPH_GPIOF);
+ LL_IOP_GRP1_ReleaseReset(LL_IOP_GRP1_PERIPH_GPIOF);
+ }
+ else
+ {
+ status = ERROR;
+ }
+
+ return (status);
+}
+
+/**
+ * @brief Initialize GPIO registers according to the specified parameters in GPIO_InitStruct.
+ * @param GPIOx GPIO Port
+ * @param GPIO_InitStruct pointer to a @ref LL_GPIO_InitTypeDef structure
+ * that contains the configuration information for the specified GPIO peripheral.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: GPIO registers are initialized according to GPIO_InitStruct content
+ * - ERROR: Not applicable
+ */
+ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct)
+{
+ uint32_t pinpos;
+ uint32_t currentpin;
+
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+ assert_param(IS_LL_GPIO_PIN(GPIO_InitStruct->Pin));
+ assert_param(IS_LL_GPIO_MODE(GPIO_InitStruct->Mode));
+ assert_param(IS_LL_GPIO_PULL(GPIO_InitStruct->Pull));
+
+ /* ------------------------- Configure the port pins ---------------- */
+ /* Initialize pinpos on first pin set */
+ pinpos = POSITION_VAL(GPIO_InitStruct->Pin);
+
+ /* Configure the port pins */
+ while (((GPIO_InitStruct->Pin) >> pinpos) != 0U)
+ {
+ /* Get current io position */
+ currentpin = (GPIO_InitStruct->Pin) & (1UL << pinpos);
+
+ if (currentpin != 0U)
+ {
+ /* Pin Mode configuration */
+ LL_GPIO_SetPinMode(GPIOx, currentpin, GPIO_InitStruct->Mode);
+
+ if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE))
+ {
+ /* Check Speed mode parameters */
+ assert_param(IS_LL_GPIO_SPEED(GPIO_InitStruct->Speed));
+
+ /* Speed mode configuration */
+ LL_GPIO_SetPinSpeed(GPIOx, currentpin, GPIO_InitStruct->Speed);
+ }
+
+ /* Pull-up Pull down resistor configuration*/
+ LL_GPIO_SetPinPull(GPIOx, currentpin, GPIO_InitStruct->Pull);
+
+ if (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE)
+ {
+ /* Check Alternate parameter */
+ assert_param(IS_LL_GPIO_ALTERNATE(GPIO_InitStruct->Alternate));
+
+ /* Speed mode configuration */
+ if (POSITION_VAL(currentpin) < 8U)
+ {
+ LL_GPIO_SetAFPin_0_7(GPIOx, currentpin, GPIO_InitStruct->Alternate);
+ }
+ else
+ {
+ LL_GPIO_SetAFPin_8_15(GPIOx, currentpin, GPIO_InitStruct->Alternate);
+ }
+ }
+ }
+ pinpos++;
+ }
+
+ if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE))
+ {
+ /* Check Output mode parameters */
+ assert_param(IS_LL_GPIO_OUTPUT_TYPE(GPIO_InitStruct->OutputType));
+
+ /* Output mode configuration*/
+ LL_GPIO_SetPinOutputType(GPIOx, GPIO_InitStruct->Pin, GPIO_InitStruct->OutputType);
+
+ }
+ return (SUCCESS);
+}
+
+/**
+ * @brief Set each @ref LL_GPIO_InitTypeDef field to default value.
+ * @param GPIO_InitStruct: pointer to a @ref LL_GPIO_InitTypeDef structure
+ * whose fields will be set to default values.
+ * @retval None
+ */
+
+void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct)
+{
+ /* Reset GPIO init structure parameters values */
+ GPIO_InitStruct->Pin = LL_GPIO_PIN_ALL;
+ GPIO_InitStruct->Mode = LL_GPIO_MODE_ANALOG;
+ GPIO_InitStruct->Speed = LL_GPIO_SPEED_FREQ_LOW;
+ GPIO_InitStruct->OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+ GPIO_InitStruct->Pull = LL_GPIO_PULL_NO;
+ GPIO_InitStruct->Alternate = LL_GPIO_AF_0;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOF) */
+
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_ll_i2c.c b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_ll_i2c.c
new file mode 100644
index 0000000000..60dccd778b
--- /dev/null
+++ b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_ll_i2c.c
@@ -0,0 +1,215 @@
+/**
+ ******************************************************************************
+ * @file stm32c0xx_ll_i2c.c
+ * @author MCD Application Team
+ * @brief I2C LL module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2022 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32c0xx_ll_i2c.h"
+#include "stm32c0xx_ll_bus.h"
+#ifdef USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+/** @addtogroup STM32C0xx_LL_Driver
+ * @{
+ */
+
+#if defined (I2C1)
+
+/** @defgroup I2C_LL I2C
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup I2C_LL_Private_Macros
+ * @{
+ */
+
+#define IS_LL_I2C_PERIPHERAL_MODE(__VALUE__) (((__VALUE__) == LL_I2C_MODE_I2C) || \
+ ((__VALUE__) == LL_I2C_MODE_SMBUS_HOST) || \
+ ((__VALUE__) == LL_I2C_MODE_SMBUS_DEVICE) || \
+ ((__VALUE__) == LL_I2C_MODE_SMBUS_DEVICE_ARP))
+
+#define IS_LL_I2C_ANALOG_FILTER(__VALUE__) (((__VALUE__) == LL_I2C_ANALOGFILTER_ENABLE) || \
+ ((__VALUE__) == LL_I2C_ANALOGFILTER_DISABLE))
+
+#define IS_LL_I2C_DIGITAL_FILTER(__VALUE__) ((__VALUE__) <= 0x0000000FU)
+
+#define IS_LL_I2C_OWN_ADDRESS1(__VALUE__) ((__VALUE__) <= 0x000003FFU)
+
+#define IS_LL_I2C_TYPE_ACKNOWLEDGE(__VALUE__) (((__VALUE__) == LL_I2C_ACK) || \
+ ((__VALUE__) == LL_I2C_NACK))
+
+#define IS_LL_I2C_OWN_ADDRSIZE(__VALUE__) (((__VALUE__) == LL_I2C_OWNADDRESS1_7BIT) || \
+ ((__VALUE__) == LL_I2C_OWNADDRESS1_10BIT))
+/**
+ * @}
+ */
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup I2C_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup I2C_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief De-initialize the I2C registers to their default reset values.
+ * @param I2Cx I2C Instance.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: I2C registers are de-initialized
+ * - ERROR: I2C registers are not de-initialized
+ */
+ErrorStatus LL_I2C_DeInit(I2C_TypeDef *I2Cx)
+{
+ ErrorStatus status = SUCCESS;
+
+ /* Check the I2C Instance I2Cx */
+ assert_param(IS_I2C_ALL_INSTANCE(I2Cx));
+
+ if (I2Cx == I2C1)
+ {
+ /* Force reset of I2C clock */
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C1);
+
+ /* Release reset of I2C clock */
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C1);
+ }
+ else
+ {
+ status = ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Initialize the I2C registers according to the specified parameters in I2C_InitStruct.
+ * @param I2Cx I2C Instance.
+ * @param I2C_InitStruct pointer to a @ref LL_I2C_InitTypeDef structure.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: I2C registers are initialized
+ * - ERROR: Not applicable
+ */
+ErrorStatus LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct)
+{
+ /* Check the I2C Instance I2Cx */
+ assert_param(IS_I2C_ALL_INSTANCE(I2Cx));
+
+ /* Check the I2C parameters from I2C_InitStruct */
+ assert_param(IS_LL_I2C_PERIPHERAL_MODE(I2C_InitStruct->PeripheralMode));
+ assert_param(IS_LL_I2C_ANALOG_FILTER(I2C_InitStruct->AnalogFilter));
+ assert_param(IS_LL_I2C_DIGITAL_FILTER(I2C_InitStruct->DigitalFilter));
+ assert_param(IS_LL_I2C_OWN_ADDRESS1(I2C_InitStruct->OwnAddress1));
+ assert_param(IS_LL_I2C_TYPE_ACKNOWLEDGE(I2C_InitStruct->TypeAcknowledge));
+ assert_param(IS_LL_I2C_OWN_ADDRSIZE(I2C_InitStruct->OwnAddrSize));
+
+ /* Disable the selected I2Cx Peripheral */
+ LL_I2C_Disable(I2Cx);
+
+ /*---------------------------- I2Cx CR1 Configuration ------------------------
+ * Configure the analog and digital noise filters with parameters :
+ * - AnalogFilter: I2C_CR1_ANFOFF bit
+ * - DigitalFilter: I2C_CR1_DNF[3:0] bits
+ */
+ LL_I2C_ConfigFilters(I2Cx, I2C_InitStruct->AnalogFilter, I2C_InitStruct->DigitalFilter);
+
+ /*---------------------------- I2Cx TIMINGR Configuration --------------------
+ * Configure the SDA setup, hold time and the SCL high, low period with parameter :
+ * - Timing: I2C_TIMINGR_PRESC[3:0], I2C_TIMINGR_SCLDEL[3:0], I2C_TIMINGR_SDADEL[3:0],
+ * I2C_TIMINGR_SCLH[7:0] and I2C_TIMINGR_SCLL[7:0] bits
+ */
+ LL_I2C_SetTiming(I2Cx, I2C_InitStruct->Timing);
+
+ /* Enable the selected I2Cx Peripheral */
+ LL_I2C_Enable(I2Cx);
+
+ /*---------------------------- I2Cx OAR1 Configuration -----------------------
+ * Disable, Configure and Enable I2Cx device own address 1 with parameters :
+ * - OwnAddress1: I2C_OAR1_OA1[9:0] bits
+ * - OwnAddrSize: I2C_OAR1_OA1MODE bit
+ */
+ LL_I2C_DisableOwnAddress1(I2Cx);
+ LL_I2C_SetOwnAddress1(I2Cx, I2C_InitStruct->OwnAddress1, I2C_InitStruct->OwnAddrSize);
+
+ /* OwnAdress1 == 0 is reserved for General Call address */
+ if (I2C_InitStruct->OwnAddress1 != 0U)
+ {
+ LL_I2C_EnableOwnAddress1(I2Cx);
+ }
+
+ /*---------------------------- I2Cx MODE Configuration -----------------------
+ * Configure I2Cx peripheral mode with parameter :
+ * - PeripheralMode: I2C_CR1_SMBDEN and I2C_CR1_SMBHEN bits
+ */
+ LL_I2C_SetMode(I2Cx, I2C_InitStruct->PeripheralMode);
+
+ /*---------------------------- I2Cx CR2 Configuration ------------------------
+ * Configure the ACKnowledge or Non ACKnowledge condition
+ * after the address receive match code or next received byte with parameter :
+ * - TypeAcknowledge: I2C_CR2_NACK bit
+ */
+ LL_I2C_AcknowledgeNextData(I2Cx, I2C_InitStruct->TypeAcknowledge);
+
+ return SUCCESS;
+}
+
+/**
+ * @brief Set each @ref LL_I2C_InitTypeDef field to default value.
+ * @param I2C_InitStruct Pointer to a @ref LL_I2C_InitTypeDef structure.
+ * @retval None
+ */
+void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct)
+{
+ /* Set I2C_InitStruct fields to default values */
+ I2C_InitStruct->PeripheralMode = LL_I2C_MODE_I2C;
+ I2C_InitStruct->Timing = 0U;
+ I2C_InitStruct->AnalogFilter = LL_I2C_ANALOGFILTER_ENABLE;
+ I2C_InitStruct->DigitalFilter = 0U;
+ I2C_InitStruct->OwnAddress1 = 0U;
+ I2C_InitStruct->TypeAcknowledge = LL_I2C_NACK;
+ I2C_InitStruct->OwnAddrSize = LL_I2C_OWNADDRESS1_7BIT;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* I2C1 */
+
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_ll_pwr.c b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_ll_pwr.c
new file mode 100644
index 0000000000..a78a541d05
--- /dev/null
+++ b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_ll_pwr.c
@@ -0,0 +1,82 @@
+/**
+ ******************************************************************************
+ * @file stm32c0xx_ll_pwr.c
+ * @author MCD Application Team
+ * @brief PWR LL module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2022 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32c0xx_ll_pwr.h"
+#include "stm32c0xx_ll_bus.h"
+
+/** @addtogroup STM32C0xx_LL_Driver
+ * @{
+ */
+
+#if defined(PWR)
+
+/** @defgroup PWR_LL PWR
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup PWR_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup PWR_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief De-initialize the PWR registers to their default reset values.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: PWR registers are de-initialized
+ * - ERROR: not applicable
+ */
+ErrorStatus LL_PWR_DeInit(void)
+{
+ /* Force reset of PWR clock */
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_PWR);
+
+ /* Release reset of PWR clock */
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_PWR);
+
+ return SUCCESS;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* defined(PWR) */
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_ll_rcc.c b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_ll_rcc.c
new file mode 100644
index 0000000000..c1ef0f7ca6
--- /dev/null
+++ b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_ll_rcc.c
@@ -0,0 +1,438 @@
+/**
+ ******************************************************************************
+ * @file stm32c0xx_ll_rcc.c
+ * @author MCD Application Team
+ * @brief RCC LL module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2022 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32c0xx_ll_rcc.h"
+#ifdef USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif
+/** @addtogroup STM32C0xx_LL_Driver
+ * @{
+ */
+
+#if defined(RCC)
+
+/** @addtogroup RCC_LL
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup RCC_LL_Private_Macros
+ * @{
+ */
+
+#define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_USART1_CLKSOURCE)
+#define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_I2C1_CLKSOURCE)
+#define IS_LL_RCC_ADC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_ADC_CLKSOURCE))
+#define IS_LL_RCC_I2S_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2S1_CLKSOURCE))
+
+/**
+ * @}
+ */
+
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup RCC_LL_Private_Functions RCC Private functions
+ * @{
+ */
+uint32_t RCC_GetSystemClockFreq(void);
+uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency);
+uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency);
+uint32_t RCC_PLL_GetFreqDomain_SYS(void);
+uint32_t RCC_PLL_GetFreqDomain_ADC(void);
+uint32_t RCC_PLL_GetFreqDomain_I2S1(void);
+/**
+ * @}
+ */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup RCC_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup RCC_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief Reset the RCC clock configuration to the default reset state.
+ * @note The default reset state of the clock configuration is given below:
+ * - HSI ON and used as system clock source
+ * - HSE OFF
+ * - AHB and APB1 prescaler set to 1.
+ * - CSS, MCO OFF
+ * - All interrupts disabled
+ * @note This function does not modify the configuration of the
+ * - Peripheral clocks
+ * - LSI, LSE and RTC clocks
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: RCC registers are de-initialized
+ * - ERROR: not applicable
+ */
+ErrorStatus LL_RCC_DeInit(void)
+{
+ /* Set HSION bit and wait for HSI READY bit */
+ LL_RCC_HSI_Enable();
+ while (LL_RCC_HSI_IsReady() != 1U)
+ {}
+
+ /* Set HSITRIM bits to reset value*/
+ LL_RCC_HSI_SetCalibTrimming(0x40U);
+
+ /* Reset CFGR register */
+ LL_RCC_WriteReg(CFGR, 0x00000000U);
+
+ /* Reset whole CR register but HSI in 2 steps in case HSEBYP is set */
+ LL_RCC_WriteReg(CR, RCC_CR_HSION);
+ while (LL_RCC_HSE_IsReady() != 0U)
+ {}
+ LL_RCC_WriteReg(CR, RCC_CR_HSION);
+
+ /* Disable all interrupts */
+ LL_RCC_WriteReg(CIER, 0x00000000U);
+
+ /* Clear all interrupts flags */
+ LL_RCC_WriteReg(CICR, 0xFFFFFFFFU);
+
+ return SUCCESS;
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup RCC_LL_EF_Get_Freq
+ * @brief Return the frequencies of different on chip clocks; System, AHB and APB1 buses clocks
+ * and different peripheral clocks available on the device.
+ * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE divided by HSI division factor(**)
+ * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(***)
+ * @note (**) HSI_VALUE is a constant defined in this file (default value
+ * 48 MHz) but the real value may vary depending on the variations
+ * in voltage and temperature.
+ * @note (***) HSE_VALUE is a constant defined in this file (default value
+ * 48 MHz), user has to ensure that HSE_VALUE is same as the real
+ * frequency of the crystal used. Otherwise, this function may
+ * have wrong result.
+ * @note The result of this function could be incorrect when using fractional
+ * value for HSE crystal.
+ * @note This function can be used by the user application to compute the
+ * baud-rate for the communication peripherals or configure other parameters.
+ * @{
+ */
+
+/**
+ * @brief Return the frequencies of different on chip clocks; System, AHB and APB1 buses clocks
+ * @note Each time SYSCLK, HCLK and/or PCLK1 clock changes, this function
+ * must be called to update structure fields. Otherwise, any
+ * configuration based on this function will be incorrect.
+ * @param RCC_Clocks pointer to a @ref LL_RCC_ClocksTypeDef structure which will hold the clocks frequencies
+ * @retval None
+ */
+void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks)
+{
+ /* Get SYSCLK frequency */
+ RCC_Clocks->SYSCLK_Frequency = RCC_GetSystemClockFreq();
+
+ /* HCLK clock frequency */
+ RCC_Clocks->HCLK_Frequency = RCC_GetHCLKClockFreq(RCC_Clocks->SYSCLK_Frequency);
+
+ /* PCLK1 clock frequency */
+ RCC_Clocks->PCLK1_Frequency = RCC_GetPCLK1ClockFreq(RCC_Clocks->HCLK_Frequency);
+}
+
+/**
+ * @brief Return USARTx clock frequency
+ * @param USARTxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_USART1_CLKSOURCE
+ * @retval USART clock frequency (in Hz)
+ * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
+ */
+uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource)
+{
+ uint32_t usart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+ /* Check parameter */
+ assert_param(IS_LL_RCC_USART_CLKSOURCE(USARTxSource));
+
+ if (USARTxSource == LL_RCC_USART1_CLKSOURCE)
+ {
+ /* USART1CLK clock frequency */
+ switch (LL_RCC_GetUSARTClockSource(USARTxSource))
+ {
+ case LL_RCC_USART1_CLKSOURCE_SYSCLK: /* USART1 Clock is System Clock */
+ usart_frequency = RCC_GetSystemClockFreq();
+ break;
+
+ case LL_RCC_USART1_CLKSOURCE_HSIKER: /* USART1 Clock is HSI Kernel */
+ if (LL_RCC_HSI_IsReady() == 1U)
+ {
+ usart_frequency = (HSI_VALUE / ((LL_RCC_HSIKER_GetDivider() >> RCC_CR_HSIKERDIV_Pos) + 1U));
+ }
+ break;
+
+ case LL_RCC_USART1_CLKSOURCE_LSE: /* USART1 Clock is LSE Osc. */
+ if (LL_RCC_LSE_IsReady() == 1U)
+ {
+ usart_frequency = LSE_VALUE;
+ }
+ break;
+
+ case LL_RCC_USART1_CLKSOURCE_PCLK1: /* USART1 Clock is PCLK1 */
+ default:
+ usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
+ break;
+ }
+ }
+ else
+ {
+ }
+ return usart_frequency;
+}
+
+/**
+ * @brief Return I2Cx clock frequency
+ * @param I2CxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_I2C1_CLKSOURCE
+ * @retval I2C clock frequency (in Hz)
+ * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that HSI oscillator is not ready
+ */
+uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource)
+{
+ uint32_t i2c_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+ /* Check parameter */
+ assert_param(IS_LL_RCC_I2C_CLKSOURCE(I2CxSource));
+
+ if (I2CxSource == LL_RCC_I2C1_CLKSOURCE)
+ {
+ /* I2C1 CLK clock frequency */
+ switch (LL_RCC_GetI2CClockSource(I2CxSource))
+ {
+ case LL_RCC_I2C1_CLKSOURCE_SYSCLK: /* I2C1 Clock is System Clock */
+ i2c_frequency = RCC_GetSystemClockFreq();
+ break;
+
+ case LL_RCC_I2C1_CLKSOURCE_HSIKER: /* I2C1 Clock is HSI Kernel */
+ if (LL_RCC_HSI_IsReady() == 1U)
+ {
+ i2c_frequency = (HSI_VALUE / ((LL_RCC_HSIKER_GetDivider() >> RCC_CR_HSIKERDIV_Pos) + 1U));
+ }
+ break;
+
+ case LL_RCC_I2C1_CLKSOURCE_PCLK1: /* I2C1 Clock is PCLK1 */
+ default:
+ i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
+ break;
+ }
+ }
+ else
+ {
+ }
+
+ return i2c_frequency;
+}
+
+/**
+ * @brief Return I2Sx clock frequency
+ * @param I2SxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_I2S1_CLKSOURCE
+ * @retval I2S clock frequency (in Hz)
+ * @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
+ */
+uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource)
+{
+ uint32_t i2s_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+ /* Check parameter */
+ assert_param(IS_LL_RCC_I2S_CLKSOURCE(I2SxSource));
+
+ if (I2SxSource == LL_RCC_I2S1_CLKSOURCE)
+ {
+ /* I2S1 CLK clock frequency */
+ switch (LL_RCC_GetI2SClockSource(I2SxSource))
+ {
+ case LL_RCC_I2S1_CLKSOURCE_HSIKER: /* I2S1 Clock is HSI Kernel */
+ i2s_frequency = (HSI_VALUE / ((LL_RCC_HSIKER_GetDivider() >> RCC_CR_HSIKERDIV_Pos) + 1U));
+ break;
+
+ case LL_RCC_I2S1_CLKSOURCE_PIN: /* I2S1 Clock is External clock */
+ i2s_frequency = EXTERNAL_CLOCK_VALUE;
+ break;
+
+ case LL_RCC_I2S1_CLKSOURCE_SYSCLK: /* I2S1 Clock is System Clock */
+ default:
+ i2s_frequency = RCC_GetSystemClockFreq();
+ break;
+ }
+ }
+
+ return i2s_frequency;
+}
+
+/**
+ * @brief Return ADCx clock frequency
+ * @param ADCxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_ADC_CLKSOURCE
+ * @retval ADC clock frequency (in Hz)
+ * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI) is not ready
+ * - @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected
+ */
+uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource)
+{
+ uint32_t adc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+ /* Check parameter */
+ assert_param(IS_LL_RCC_ADC_CLKSOURCE(ADCxSource));
+
+ /* ADCCLK clock frequency */
+ switch (LL_RCC_GetADCClockSource(ADCxSource))
+ {
+ case LL_RCC_ADC_CLKSOURCE_SYSCLK: /* SYSCLK clock used as ADC clock source */
+ adc_frequency = RCC_GetSystemClockFreq();
+ break;
+ case LL_RCC_ADC_CLKSOURCE_HSIKER : /* HSI clock Kernel used as ADC clock source */
+ adc_frequency = (HSI_VALUE / ((LL_RCC_HSIKER_GetDivider() >> RCC_CR_HSIKERDIV_Pos) + 1U));
+ break;
+ default:
+ adc_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
+ break;
+ }
+
+ return adc_frequency;
+}
+
+/**
+ * @brief Return RTC clock frequency
+ * @retval RTC clock frequency (in Hz)
+ * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillators (LSI, LSE or HSE) are not ready
+ * - @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected
+ */
+uint32_t LL_RCC_GetRTCClockFreq(void)
+{
+ uint32_t rtc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+ /* RTCCLK clock frequency */
+ switch (LL_RCC_GetRTCClockSource())
+ {
+ case LL_RCC_RTC_CLKSOURCE_LSE: /* LSE clock used as RTC clock source */
+ if (LL_RCC_LSE_IsReady() == 1U)
+ {
+ rtc_frequency = LSE_VALUE;
+ }
+ break;
+
+ case LL_RCC_RTC_CLKSOURCE_LSI: /* LSI clock used as RTC clock source */
+ if (LL_RCC_LSI_IsReady() == 1U)
+ {
+ rtc_frequency = LSI_VALUE;
+ }
+ break;
+
+ case LL_RCC_RTC_CLKSOURCE_HSE_DIV32: /* HSE clock used as ADC clock source */
+ rtc_frequency = HSE_VALUE / 32U;
+ break;
+
+ case LL_RCC_RTC_CLKSOURCE_NONE: /* No clock used as RTC clock source */
+ default:
+ rtc_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
+ break;
+ }
+
+ return rtc_frequency;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup RCC_LL_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Return SYSTEM clock frequency
+ * @retval SYSTEM clock frequency (in Hz)
+ */
+uint32_t RCC_GetSystemClockFreq(void)
+{
+ uint32_t frequency;
+ uint32_t hsidiv;
+
+ /* Get SYSCLK source -------------------------------------------------------*/
+ switch (LL_RCC_GetSysClkSource())
+ {
+ case LL_RCC_SYS_CLKSOURCE_STATUS_HSE: /* HSE used as system clock source */
+ frequency = HSE_VALUE;
+ break;
+ case LL_RCC_SYS_CLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
+ default:
+ hsidiv = (1UL << ((READ_BIT(RCC->CR, RCC_CR_HSIDIV)) >> RCC_CR_HSIDIV_Pos));
+ frequency = (HSI_VALUE / hsidiv);
+ break;
+ }
+
+ return frequency;
+}
+
+/**
+ * @brief Return HCLK clock frequency
+ * @param SYSCLK_Frequency SYSCLK clock frequency
+ * @retval HCLK clock frequency (in Hz)
+ */
+uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)
+{
+ /* HCLK clock frequency */
+ return __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler());
+}
+
+/**
+ * @brief Return PCLK1 clock frequency
+ * @param HCLK_Frequency HCLK clock frequency
+ * @retval PCLK1 clock frequency (in Hz)
+ */
+uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)
+{
+ /* PCLK1 clock frequency */
+ return __LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler());
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined(RCC) */
+
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_ll_rtc.c b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_ll_rtc.c
new file mode 100644
index 0000000000..571ad0283e
--- /dev/null
+++ b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_ll_rtc.c
@@ -0,0 +1,706 @@
+/**
+ ******************************************************************************
+ * @file stm32c0xx_ll_rtc.c
+ * @author MCD Application Team
+ * @brief RTC LL module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2022 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32c0xx_ll_rtc.h"
+#include "stm32c0xx_ll_cortex.h"
+#ifdef USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif
+
+/** @addtogroup STM32C0xx_LL_Driver
+ * @{
+ */
+
+#if defined(RTC)
+
+/** @addtogroup RTC_LL
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @addtogroup RTC_LL_Private_Constants
+ * @{
+ */
+/* Default values used for prescaler */
+#define RTC_ASYNCH_PRESC_DEFAULT 0x0000007FU
+#define RTC_SYNCH_PRESC_DEFAULT 0x000000FFU
+
+/* Values used for timeout */
+#define RTC_INITMODE_TIMEOUT 1000U /* 1s when tick set to 1ms */
+#define RTC_SYNCHRO_TIMEOUT 1000U /* 1s when tick set to 1ms */
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup RTC_LL_Private_Macros
+ * @{
+ */
+
+#define IS_LL_RTC_HOURFORMAT(__VALUE__) (((__VALUE__) == LL_RTC_HOURFORMAT_24HOUR) \
+ || ((__VALUE__) == LL_RTC_HOURFORMAT_AMPM))
+
+#define IS_LL_RTC_ASYNCH_PREDIV(__VALUE__) ((__VALUE__) <= 0x7FU)
+
+#define IS_LL_RTC_SYNCH_PREDIV(__VALUE__) ((__VALUE__) <= 0x7FFFU)
+
+#define IS_LL_RTC_FORMAT(__VALUE__) (((__VALUE__) == LL_RTC_FORMAT_BIN) \
+ || ((__VALUE__) == LL_RTC_FORMAT_BCD))
+
+#define IS_LL_RTC_TIME_FORMAT(__VALUE__) (((__VALUE__) == LL_RTC_TIME_FORMAT_AM_OR_24) \
+ || ((__VALUE__) == LL_RTC_TIME_FORMAT_PM))
+
+#define IS_LL_RTC_HOUR12(__HOUR__) (((__HOUR__) > 0U) && ((__HOUR__) <= 12U))
+#define IS_LL_RTC_HOUR24(__HOUR__) ((__HOUR__) <= 23U)
+#define IS_LL_RTC_MINUTES(__MINUTES__) ((__MINUTES__) <= 59U)
+#define IS_LL_RTC_SECONDS(__SECONDS__) ((__SECONDS__) <= 59U)
+
+#define IS_LL_RTC_WEEKDAY(__VALUE__) (((__VALUE__) == LL_RTC_WEEKDAY_MONDAY) \
+ || ((__VALUE__) == LL_RTC_WEEKDAY_TUESDAY) \
+ || ((__VALUE__) == LL_RTC_WEEKDAY_WEDNESDAY) \
+ || ((__VALUE__) == LL_RTC_WEEKDAY_THURSDAY) \
+ || ((__VALUE__) == LL_RTC_WEEKDAY_FRIDAY) \
+ || ((__VALUE__) == LL_RTC_WEEKDAY_SATURDAY) \
+ || ((__VALUE__) == LL_RTC_WEEKDAY_SUNDAY))
+
+#define IS_LL_RTC_DAY(__DAY__) (((__DAY__) >= 1U) && ((__DAY__) <= 31U))
+
+#define IS_LL_RTC_MONTH(__VALUE__) (((__VALUE__) == LL_RTC_MONTH_JANUARY) \
+ || ((__VALUE__) == LL_RTC_MONTH_FEBRUARY) \
+ || ((__VALUE__) == LL_RTC_MONTH_MARCH) \
+ || ((__VALUE__) == LL_RTC_MONTH_APRIL) \
+ || ((__VALUE__) == LL_RTC_MONTH_MAY) \
+ || ((__VALUE__) == LL_RTC_MONTH_JUNE) \
+ || ((__VALUE__) == LL_RTC_MONTH_JULY) \
+ || ((__VALUE__) == LL_RTC_MONTH_AUGUST) \
+ || ((__VALUE__) == LL_RTC_MONTH_SEPTEMBER) \
+ || ((__VALUE__) == LL_RTC_MONTH_OCTOBER) \
+ || ((__VALUE__) == LL_RTC_MONTH_NOVEMBER) \
+ || ((__VALUE__) == LL_RTC_MONTH_DECEMBER))
+
+#define IS_LL_RTC_YEAR(__YEAR__) ((__YEAR__) <= 99U)
+
+#define IS_LL_RTC_ALMA_MASK(__VALUE__) (((__VALUE__) == LL_RTC_ALMA_MASK_NONE) \
+ || ((__VALUE__) == LL_RTC_ALMA_MASK_DATEWEEKDAY) \
+ || ((__VALUE__) == LL_RTC_ALMA_MASK_HOURS) \
+ || ((__VALUE__) == LL_RTC_ALMA_MASK_MINUTES) \
+ || ((__VALUE__) == LL_RTC_ALMA_MASK_SECONDS) \
+ || ((__VALUE__) == LL_RTC_ALMA_MASK_ALL))
+
+#define IS_LL_RTC_ALMA_DATE_WEEKDAY_SEL(__SEL__) (((__SEL__) == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE) || \
+ ((__SEL__) == LL_RTC_ALMA_DATEWEEKDAYSEL_WEEKDAY))
+
+/**
+ * @}
+ */
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup RTC_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup RTC_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief De-Initializes the RTC registers to their default reset values.
+ * @note This function does not reset the RTC Clock source and RTC Backup Data
+ * registers.
+ * @param RTCx RTC Instance
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: RTC registers are de-initialized
+ * - ERROR: RTC registers are not de-initialized
+ */
+ErrorStatus LL_RTC_DeInit(RTC_TypeDef *RTCx)
+{
+ ErrorStatus status = ERROR;
+
+ /* Check the parameter */
+ assert_param(IS_RTC_ALL_INSTANCE(RTCx));
+
+ /* Disable the write protection for RTC registers */
+ LL_RTC_DisableWriteProtection(RTCx);
+
+ /* Set Initialization mode */
+ if (LL_RTC_EnterInitMode(RTCx) != ERROR)
+ {
+ /* Reset TR, DR and CR registers */
+ WRITE_REG(RTCx->TR, 0x00000000U);
+ WRITE_REG(RTCx->DR, (RTC_DR_WDU_0 | RTC_DR_MU_0 | RTC_DR_DU_0));
+ WRITE_REG(RTCx->PRER, (RTC_PRER_PREDIV_A | RTC_SYNCH_PRESC_DEFAULT));
+ WRITE_REG(RTCx->ALRMAR, 0x00000000U);
+ WRITE_REG(RTCx->SHIFTR, 0x00000000U);
+ WRITE_REG(RTCx->CALR, 0x00000000U);
+ WRITE_REG(RTCx->ALRMASSR, 0x00000000U);
+ /* Exit Initialization mode */
+ LL_RTC_DisableInitMode(RTCx);
+
+ /* Wait till the RTC RSF flag is set */
+ status = LL_RTC_WaitForSynchro(RTCx);
+ }
+
+ /* Enable the write protection for RTC registers */
+ LL_RTC_EnableWriteProtection(RTCx);
+
+ return status;
+}
+
+/**
+ * @brief Initializes the RTC registers according to the specified parameters
+ * in RTC_InitStruct.
+ * @param RTCx RTC Instance
+ * @param RTC_InitStruct pointer to a @ref LL_RTC_InitTypeDef structure that contains
+ * the configuration information for the RTC peripheral.
+ * @note The RTC Prescaler register is write protected and can be written in
+ * initialization mode only.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: RTC registers are initialized
+ * - ERROR: RTC registers are not initialized
+ */
+ErrorStatus LL_RTC_Init(RTC_TypeDef *RTCx, LL_RTC_InitTypeDef *RTC_InitStruct)
+{
+ ErrorStatus status = ERROR;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_ALL_INSTANCE(RTCx));
+ assert_param(IS_LL_RTC_HOURFORMAT(RTC_InitStruct->HourFormat));
+ assert_param(IS_LL_RTC_ASYNCH_PREDIV(RTC_InitStruct->AsynchPrescaler));
+ assert_param(IS_LL_RTC_SYNCH_PREDIV(RTC_InitStruct->SynchPrescaler));
+
+ /* Disable the write protection for RTC registers */
+ LL_RTC_DisableWriteProtection(RTCx);
+
+ /* Set Initialization mode */
+ if (LL_RTC_EnterInitMode(RTCx) != ERROR)
+ {
+ /* Set Hour Format */
+ LL_RTC_SetHourFormat(RTCx, RTC_InitStruct->HourFormat);
+
+ /* Configure Synchronous and Asynchronous prescaler factor */
+ LL_RTC_SetSynchPrescaler(RTCx, RTC_InitStruct->SynchPrescaler);
+ LL_RTC_SetAsynchPrescaler(RTCx, RTC_InitStruct->AsynchPrescaler);
+
+ /* Exit Initialization mode */
+ LL_RTC_DisableInitMode(RTCx);
+
+ status = SUCCESS;
+ }
+ /* Enable the write protection for RTC registers */
+ LL_RTC_EnableWriteProtection(RTCx);
+
+ return status;
+}
+
+/**
+ * @brief Set each @ref LL_RTC_InitTypeDef field to default value.
+ * @param RTC_InitStruct pointer to a @ref LL_RTC_InitTypeDef structure which will be initialized.
+ * @retval None
+ */
+void LL_RTC_StructInit(LL_RTC_InitTypeDef *RTC_InitStruct)
+{
+ /* Set RTC_InitStruct fields to default values */
+ RTC_InitStruct->HourFormat = LL_RTC_HOURFORMAT_24HOUR;
+ RTC_InitStruct->AsynchPrescaler = RTC_ASYNCH_PRESC_DEFAULT;
+ RTC_InitStruct->SynchPrescaler = RTC_SYNCH_PRESC_DEFAULT;
+}
+
+/**
+ * @brief Set the RTC current time.
+ * @param RTCx RTC Instance
+ * @param RTC_Format This parameter can be one of the following values:
+ * @arg @ref LL_RTC_FORMAT_BIN
+ * @arg @ref LL_RTC_FORMAT_BCD
+ * @param RTC_TimeStruct pointer to a RTC_TimeTypeDef structure that contains
+ * the time configuration information for the RTC.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: RTC Time register is configured
+ * - ERROR: RTC Time register is not configured
+ */
+ErrorStatus LL_RTC_TIME_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_TimeTypeDef *RTC_TimeStruct)
+{
+ ErrorStatus status = ERROR;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_ALL_INSTANCE(RTCx));
+ assert_param(IS_LL_RTC_FORMAT(RTC_Format));
+
+ if (RTC_Format == LL_RTC_FORMAT_BIN)
+ {
+ if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR)
+ {
+ assert_param(IS_LL_RTC_HOUR12(RTC_TimeStruct->Hours));
+ assert_param(IS_LL_RTC_TIME_FORMAT(RTC_TimeStruct->TimeFormat));
+ }
+ else
+ {
+ RTC_TimeStruct->TimeFormat = 0x00U;
+ assert_param(IS_LL_RTC_HOUR24(RTC_TimeStruct->Hours));
+ }
+ assert_param(IS_LL_RTC_MINUTES(RTC_TimeStruct->Minutes));
+ assert_param(IS_LL_RTC_SECONDS(RTC_TimeStruct->Seconds));
+ }
+ else
+ {
+ if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR)
+ {
+ assert_param(IS_LL_RTC_HOUR12(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Hours)));
+ assert_param(IS_LL_RTC_TIME_FORMAT(RTC_TimeStruct->TimeFormat));
+ }
+ else
+ {
+ RTC_TimeStruct->TimeFormat = 0x00U;
+ assert_param(IS_LL_RTC_HOUR24(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Hours)));
+ }
+ assert_param(IS_LL_RTC_MINUTES(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Minutes)));
+ assert_param(IS_LL_RTC_SECONDS(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Seconds)));
+ }
+
+ /* Disable the write protection for RTC registers */
+ LL_RTC_DisableWriteProtection(RTCx);
+
+ /* Set Initialization mode */
+ if (LL_RTC_EnterInitMode(RTCx) != ERROR)
+ {
+ /* Check the input parameters format */
+ if (RTC_Format != LL_RTC_FORMAT_BIN)
+ {
+ LL_RTC_TIME_Config(RTCx, RTC_TimeStruct->TimeFormat, RTC_TimeStruct->Hours,
+ RTC_TimeStruct->Minutes, RTC_TimeStruct->Seconds);
+ }
+ else
+ {
+ LL_RTC_TIME_Config(RTCx, RTC_TimeStruct->TimeFormat, __LL_RTC_CONVERT_BIN2BCD(RTC_TimeStruct->Hours),
+ __LL_RTC_CONVERT_BIN2BCD(RTC_TimeStruct->Minutes),
+ __LL_RTC_CONVERT_BIN2BCD(RTC_TimeStruct->Seconds));
+ }
+
+ /* Exit Initialization mode */
+ LL_RTC_DisableInitMode(RTC);
+
+ /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
+ if (LL_RTC_IsShadowRegBypassEnabled(RTCx) == 0U)
+ {
+ status = LL_RTC_WaitForSynchro(RTCx);
+ }
+ else
+ {
+ status = SUCCESS;
+ }
+ }
+ /* Enable the write protection for RTC registers */
+ LL_RTC_EnableWriteProtection(RTCx);
+
+ return status;
+}
+
+/**
+ * @brief Set each @ref LL_RTC_TimeTypeDef field to default value (Time = 00h:00min:00sec).
+ * @param RTC_TimeStruct pointer to a @ref LL_RTC_TimeTypeDef structure which will be initialized.
+ * @retval None
+ */
+void LL_RTC_TIME_StructInit(LL_RTC_TimeTypeDef *RTC_TimeStruct)
+{
+ /* Time = 00h:00min:00sec */
+ RTC_TimeStruct->TimeFormat = LL_RTC_TIME_FORMAT_AM_OR_24;
+ RTC_TimeStruct->Hours = 0U;
+ RTC_TimeStruct->Minutes = 0U;
+ RTC_TimeStruct->Seconds = 0U;
+}
+
+/**
+ * @brief Set the RTC current date.
+ * @param RTCx RTC Instance
+ * @param RTC_Format This parameter can be one of the following values:
+ * @arg @ref LL_RTC_FORMAT_BIN
+ * @arg @ref LL_RTC_FORMAT_BCD
+ * @param RTC_DateStruct pointer to a RTC_DateTypeDef structure that contains
+ * the date configuration information for the RTC.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: RTC Day register is configured
+ * - ERROR: RTC Day register is not configured
+ */
+ErrorStatus LL_RTC_DATE_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_DateTypeDef *RTC_DateStruct)
+{
+ ErrorStatus status = ERROR;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_ALL_INSTANCE(RTCx));
+ assert_param(IS_LL_RTC_FORMAT(RTC_Format));
+
+ if ((RTC_Format == LL_RTC_FORMAT_BIN) && ((RTC_DateStruct->Month & 0x10U) == 0x10U))
+ {
+ RTC_DateStruct->Month = (RTC_DateStruct->Month & (uint8_t)~(0x10U)) + 0x0AU;
+ }
+ if (RTC_Format == LL_RTC_FORMAT_BIN)
+ {
+ assert_param(IS_LL_RTC_YEAR(RTC_DateStruct->Year));
+ assert_param(IS_LL_RTC_MONTH(RTC_DateStruct->Month));
+ assert_param(IS_LL_RTC_DAY(RTC_DateStruct->Day));
+ }
+ else
+ {
+ assert_param(IS_LL_RTC_YEAR(__LL_RTC_CONVERT_BCD2BIN(RTC_DateStruct->Year)));
+ assert_param(IS_LL_RTC_MONTH(__LL_RTC_CONVERT_BCD2BIN(RTC_DateStruct->Month)));
+ assert_param(IS_LL_RTC_DAY(__LL_RTC_CONVERT_BCD2BIN(RTC_DateStruct->Day)));
+ }
+ assert_param(IS_LL_RTC_WEEKDAY(RTC_DateStruct->WeekDay));
+
+ /* Disable the write protection for RTC registers */
+ LL_RTC_DisableWriteProtection(RTCx);
+
+ /* Set Initialization mode */
+ if (LL_RTC_EnterInitMode(RTCx) != ERROR)
+ {
+ /* Check the input parameters format */
+ if (RTC_Format != LL_RTC_FORMAT_BIN)
+ {
+ LL_RTC_DATE_Config(RTCx, RTC_DateStruct->WeekDay, RTC_DateStruct->Day, RTC_DateStruct->Month, RTC_DateStruct->Year);
+ }
+ else
+ {
+ LL_RTC_DATE_Config(RTCx, RTC_DateStruct->WeekDay, __LL_RTC_CONVERT_BIN2BCD(RTC_DateStruct->Day),
+ __LL_RTC_CONVERT_BIN2BCD(RTC_DateStruct->Month), __LL_RTC_CONVERT_BIN2BCD(RTC_DateStruct->Year));
+ }
+
+ /* Exit Initialization mode */
+ LL_RTC_DisableInitMode(RTC);
+
+ /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
+ if (LL_RTC_IsShadowRegBypassEnabled(RTCx) == 0U)
+ {
+ status = LL_RTC_WaitForSynchro(RTCx);
+ }
+ else
+ {
+ status = SUCCESS;
+ }
+ }
+ /* Enable the write protection for RTC registers */
+ LL_RTC_EnableWriteProtection(RTCx);
+
+ return status;
+}
+
+/**
+ * @brief Set each @ref LL_RTC_DateTypeDef field to default value (date = Monday, January 01 xx00)
+ * @param RTC_DateStruct pointer to a @ref LL_RTC_DateTypeDef structure which will be initialized.
+ * @retval None
+ */
+void LL_RTC_DATE_StructInit(LL_RTC_DateTypeDef *RTC_DateStruct)
+{
+ /* Monday, January 01 xx00 */
+ RTC_DateStruct->WeekDay = LL_RTC_WEEKDAY_MONDAY;
+ RTC_DateStruct->Day = 1U;
+ RTC_DateStruct->Month = LL_RTC_MONTH_JANUARY;
+ RTC_DateStruct->Year = 0U;
+}
+
+/**
+ * @brief Set the RTC Alarm A.
+ * @note The Alarm register can only be written when the corresponding Alarm
+ * is disabled (Use @ref LL_RTC_ALMA_Disable function).
+ * @param RTCx RTC Instance
+ * @param RTC_Format This parameter can be one of the following values:
+ * @arg @ref LL_RTC_FORMAT_BIN
+ * @arg @ref LL_RTC_FORMAT_BCD
+ * @param RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure that
+ * contains the alarm configuration parameters.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: ALARMA registers are configured
+ * - ERROR: ALARMA registers are not configured
+ */
+ErrorStatus LL_RTC_ALMA_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
+{
+ /* Check the parameters */
+ assert_param(IS_RTC_ALL_INSTANCE(RTCx));
+ assert_param(IS_LL_RTC_FORMAT(RTC_Format));
+ assert_param(IS_LL_RTC_ALMA_MASK(RTC_AlarmStruct->AlarmMask));
+ assert_param(IS_LL_RTC_ALMA_DATE_WEEKDAY_SEL(RTC_AlarmStruct->AlarmDateWeekDaySel));
+
+ if (RTC_Format == LL_RTC_FORMAT_BIN)
+ {
+ if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR)
+ {
+ assert_param(IS_LL_RTC_HOUR12(RTC_AlarmStruct->AlarmTime.Hours));
+ assert_param(IS_LL_RTC_TIME_FORMAT(RTC_AlarmStruct->AlarmTime.TimeFormat));
+ }
+ else
+ {
+ RTC_AlarmStruct->AlarmTime.TimeFormat = 0x00U;
+ assert_param(IS_LL_RTC_HOUR24(RTC_AlarmStruct->AlarmTime.Hours));
+ }
+ assert_param(IS_LL_RTC_MINUTES(RTC_AlarmStruct->AlarmTime.Minutes));
+ assert_param(IS_LL_RTC_SECONDS(RTC_AlarmStruct->AlarmTime.Seconds));
+
+ if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE)
+ {
+ assert_param(IS_LL_RTC_DAY(RTC_AlarmStruct->AlarmDateWeekDay));
+ }
+ else
+ {
+ assert_param(IS_LL_RTC_WEEKDAY(RTC_AlarmStruct->AlarmDateWeekDay));
+ }
+ }
+ else
+ {
+ if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR)
+ {
+ assert_param(IS_LL_RTC_HOUR12(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours)));
+ assert_param(IS_LL_RTC_TIME_FORMAT(RTC_AlarmStruct->AlarmTime.TimeFormat));
+ }
+ else
+ {
+ RTC_AlarmStruct->AlarmTime.TimeFormat = 0x00U;
+ assert_param(IS_LL_RTC_HOUR24(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours)));
+ }
+
+ assert_param(IS_LL_RTC_MINUTES(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Minutes)));
+ assert_param(IS_LL_RTC_SECONDS(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Seconds)));
+
+ if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE)
+ {
+ assert_param(IS_LL_RTC_DAY(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmDateWeekDay)));
+ }
+ else
+ {
+ assert_param(IS_LL_RTC_WEEKDAY(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmDateWeekDay)));
+ }
+ }
+
+ /* Disable the write protection for RTC registers */
+ LL_RTC_DisableWriteProtection(RTCx);
+
+ /* Select weekday selection */
+ if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE)
+ {
+ /* Set the date for ALARM */
+ LL_RTC_ALMA_DisableWeekday(RTCx);
+ if (RTC_Format != LL_RTC_FORMAT_BIN)
+ {
+ LL_RTC_ALMA_SetDay(RTCx, RTC_AlarmStruct->AlarmDateWeekDay);
+ }
+ else
+ {
+ LL_RTC_ALMA_SetDay(RTCx, __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmDateWeekDay));
+ }
+ }
+ else
+ {
+ /* Set the week day for ALARM */
+ LL_RTC_ALMA_EnableWeekday(RTCx);
+ LL_RTC_ALMA_SetWeekDay(RTCx, RTC_AlarmStruct->AlarmDateWeekDay);
+ }
+
+ /* Configure the Alarm register */
+ if (RTC_Format != LL_RTC_FORMAT_BIN)
+ {
+ LL_RTC_ALMA_ConfigTime(RTCx, RTC_AlarmStruct->AlarmTime.TimeFormat, RTC_AlarmStruct->AlarmTime.Hours,
+ RTC_AlarmStruct->AlarmTime.Minutes, RTC_AlarmStruct->AlarmTime.Seconds);
+ }
+ else
+ {
+ LL_RTC_ALMA_ConfigTime(RTCx, RTC_AlarmStruct->AlarmTime.TimeFormat,
+ __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Hours),
+ __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Minutes),
+ __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Seconds));
+ }
+ /* Set ALARM mask */
+ LL_RTC_ALMA_SetMask(RTCx, RTC_AlarmStruct->AlarmMask);
+
+ /* Enable the write protection for RTC registers */
+ LL_RTC_EnableWriteProtection(RTCx);
+
+ return SUCCESS;
+}
+
+/**
+ * @brief Set each @ref LL_RTC_AlarmTypeDef of ALARMA field to default value (Time = 00h:00mn:00sec /
+ * Day = 1st day of the month/Mask = all fields are masked).
+ * @param RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure which will be initialized.
+ * @retval None
+ */
+void LL_RTC_ALMA_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
+{
+ /* Alarm Time Settings : Time = 00h:00mn:00sec */
+ RTC_AlarmStruct->AlarmTime.TimeFormat = LL_RTC_ALMA_TIME_FORMAT_AM;
+ RTC_AlarmStruct->AlarmTime.Hours = 0U;
+ RTC_AlarmStruct->AlarmTime.Minutes = 0U;
+ RTC_AlarmStruct->AlarmTime.Seconds = 0U;
+
+ /* Alarm Day Settings : Day = 1st day of the month */
+ RTC_AlarmStruct->AlarmDateWeekDaySel = LL_RTC_ALMA_DATEWEEKDAYSEL_DATE;
+ RTC_AlarmStruct->AlarmDateWeekDay = 1U;
+
+ /* Alarm Masks Settings : Mask = all fields are not masked */
+ RTC_AlarmStruct->AlarmMask = LL_RTC_ALMA_MASK_NONE;
+}
+
+/**
+ * @brief Enters the RTC Initialization mode.
+ * @note The RTC Initialization mode is write protected, use the
+ * @ref LL_RTC_DisableWriteProtection before calling this function.
+ * @param RTCx RTC Instance
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: RTC is in Init mode
+ * - ERROR: RTC is not in Init mode
+ */
+ErrorStatus LL_RTC_EnterInitMode(RTC_TypeDef *RTCx)
+{
+ __IO uint32_t timeout = RTC_INITMODE_TIMEOUT;
+ ErrorStatus status = SUCCESS;
+ uint32_t tmp;
+
+ /* Check the parameter */
+ assert_param(IS_RTC_ALL_INSTANCE(RTCx));
+
+ /* Check if the Initialization mode is set */
+ if (LL_RTC_IsActiveFlag_INIT(RTCx) == 0U)
+ {
+ /* Set the Initialization mode */
+ LL_RTC_EnableInitMode(RTCx);
+
+ /* Wait till RTC is in INIT state and if Time out is reached exit */
+ tmp = LL_RTC_IsActiveFlag_INIT(RTCx);
+ while ((timeout != 0U) && (tmp != 1U))
+ {
+ if (LL_SYSTICK_IsActiveCounterFlag() == 1U)
+ {
+ timeout --;
+ }
+ tmp = LL_RTC_IsActiveFlag_INIT(RTCx);
+ if (timeout == 0U)
+ {
+ status = ERROR;
+ }
+ }
+ }
+ return status;
+}
+
+/**
+ * @brief Exit the RTC Initialization mode.
+ * @note When the initialization sequence is complete, the calendar restarts
+ * counting after 4 RTCCLK cycles.
+ * @note The RTC Initialization mode is write protected, use the
+ * @ref LL_RTC_DisableWriteProtection before calling this function.
+ * @param RTCx RTC Instance
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: RTC exited from in Init mode
+ * - ERROR: Not applicable
+ */
+ErrorStatus LL_RTC_ExitInitMode(RTC_TypeDef *RTCx)
+{
+ /* Check the parameter */
+ assert_param(IS_RTC_ALL_INSTANCE(RTCx));
+
+ /* Disable initialization mode */
+ LL_RTC_DisableInitMode(RTCx);
+
+ return SUCCESS;
+}
+
+/**
+ * @brief Waits until the RTC Time and Day registers (RTC_TR and RTC_DR) are
+ * synchronized with RTC APB clock.
+ * @note The RTC Resynchronization mode is write protected, use the
+ * @ref LL_RTC_DisableWriteProtection before calling this function.
+ * @note To read the calendar through the shadow registers after Calendar
+ * initialization, calendar update or after wakeup from low power modes
+ * the software must first clear the RSF flag.
+ * The software must then wait until it is set again before reading
+ * the calendar, which means that the calendar registers have been
+ * correctly copied into the RTC_TR and RTC_DR shadow registers.
+ * @param RTCx RTC Instance
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: RTC registers are synchronised
+ * - ERROR: RTC registers are not synchronised
+ */
+ErrorStatus LL_RTC_WaitForSynchro(RTC_TypeDef *RTCx)
+{
+ __IO uint32_t timeout = RTC_SYNCHRO_TIMEOUT;
+ ErrorStatus status = SUCCESS;
+ uint32_t tmp;
+
+ /* Check the parameter */
+ assert_param(IS_RTC_ALL_INSTANCE(RTCx));
+
+ /* Clear RSF flag */
+ LL_RTC_ClearFlag_RS(RTCx);
+
+ /* Wait the registers to be synchronised */
+ tmp = LL_RTC_IsActiveFlag_RS(RTCx);
+ while ((timeout != 0U) && (tmp != 0U))
+ {
+ if (LL_SYSTICK_IsActiveCounterFlag() == 1U)
+ {
+ timeout--;
+ }
+ tmp = LL_RTC_IsActiveFlag_RS(RTCx);
+ if (timeout == 0U)
+ {
+ status = ERROR;
+ }
+ }
+
+ if (status != ERROR)
+ {
+ timeout = RTC_SYNCHRO_TIMEOUT;
+ tmp = LL_RTC_IsActiveFlag_RS(RTCx);
+ while ((timeout != 0U) && (tmp != 1U))
+ {
+ if (LL_SYSTICK_IsActiveCounterFlag() == 1U)
+ {
+ timeout--;
+ }
+ tmp = LL_RTC_IsActiveFlag_RS(RTCx);
+ if (timeout == 0U)
+ {
+ status = ERROR;
+ }
+ }
+ }
+
+ return (status);
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined(RTC) */
+
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_ll_spi.c b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_ll_spi.c
new file mode 100644
index 0000000000..b3b6e1cb69
--- /dev/null
+++ b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_ll_spi.c
@@ -0,0 +1,522 @@
+/**
+ ******************************************************************************
+ * @file stm32c0xx_ll_spi.c
+ * @author MCD Application Team
+ * @brief SPI LL module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2022 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32c0xx_ll_spi.h"
+#include "stm32c0xx_ll_bus.h"
+#include "stm32c0xx_ll_rcc.h"
+
+#ifdef USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+/** @addtogroup STM32C0xx_LL_Driver
+ * @{
+ */
+
+#if defined (SPI1)
+
+/** @addtogroup SPI_LL
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup SPI_LL_Private_Constants SPI Private Constants
+ * @{
+ */
+/* SPI registers Masks */
+#define SPI_CR1_CLEAR_MASK (SPI_CR1_CPHA | SPI_CR1_CPOL | SPI_CR1_MSTR | \
+ SPI_CR1_BR | SPI_CR1_LSBFIRST | SPI_CR1_SSI | \
+ SPI_CR1_SSM | SPI_CR1_RXONLY | SPI_CR1_CRCL | \
+ SPI_CR1_CRCNEXT | SPI_CR1_CRCEN | SPI_CR1_BIDIOE | \
+ SPI_CR1_BIDIMODE)
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup SPI_LL_Private_Macros SPI Private Macros
+ * @{
+ */
+#define IS_LL_SPI_TRANSFER_DIRECTION(__VALUE__) (((__VALUE__) == LL_SPI_FULL_DUPLEX) \
+ || ((__VALUE__) == LL_SPI_SIMPLEX_RX) \
+ || ((__VALUE__) == LL_SPI_HALF_DUPLEX_RX) \
+ || ((__VALUE__) == LL_SPI_HALF_DUPLEX_TX))
+
+#define IS_LL_SPI_MODE(__VALUE__) (((__VALUE__) == LL_SPI_MODE_MASTER) \
+ || ((__VALUE__) == LL_SPI_MODE_SLAVE))
+
+#define IS_LL_SPI_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_SPI_DATAWIDTH_4BIT) \
+ || ((__VALUE__) == LL_SPI_DATAWIDTH_5BIT) \
+ || ((__VALUE__) == LL_SPI_DATAWIDTH_6BIT) \
+ || ((__VALUE__) == LL_SPI_DATAWIDTH_7BIT) \
+ || ((__VALUE__) == LL_SPI_DATAWIDTH_8BIT) \
+ || ((__VALUE__) == LL_SPI_DATAWIDTH_9BIT) \
+ || ((__VALUE__) == LL_SPI_DATAWIDTH_10BIT) \
+ || ((__VALUE__) == LL_SPI_DATAWIDTH_11BIT) \
+ || ((__VALUE__) == LL_SPI_DATAWIDTH_12BIT) \
+ || ((__VALUE__) == LL_SPI_DATAWIDTH_13BIT) \
+ || ((__VALUE__) == LL_SPI_DATAWIDTH_14BIT) \
+ || ((__VALUE__) == LL_SPI_DATAWIDTH_15BIT) \
+ || ((__VALUE__) == LL_SPI_DATAWIDTH_16BIT))
+
+#define IS_LL_SPI_POLARITY(__VALUE__) (((__VALUE__) == LL_SPI_POLARITY_LOW) \
+ || ((__VALUE__) == LL_SPI_POLARITY_HIGH))
+
+#define IS_LL_SPI_PHASE(__VALUE__) (((__VALUE__) == LL_SPI_PHASE_1EDGE) \
+ || ((__VALUE__) == LL_SPI_PHASE_2EDGE))
+
+#define IS_LL_SPI_NSS(__VALUE__) (((__VALUE__) == LL_SPI_NSS_SOFT) \
+ || ((__VALUE__) == LL_SPI_NSS_HARD_INPUT) \
+ || ((__VALUE__) == LL_SPI_NSS_HARD_OUTPUT))
+
+#define IS_LL_SPI_BAUDRATE(__VALUE__) (((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV2) \
+ || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV4) \
+ || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV8) \
+ || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV16) \
+ || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV32) \
+ || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV64) \
+ || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV128) \
+ || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV256))
+
+#define IS_LL_SPI_BITORDER(__VALUE__) (((__VALUE__) == LL_SPI_LSB_FIRST) \
+ || ((__VALUE__) == LL_SPI_MSB_FIRST))
+
+#define IS_LL_SPI_CRCCALCULATION(__VALUE__) (((__VALUE__) == LL_SPI_CRCCALCULATION_ENABLE) \
+ || ((__VALUE__) == LL_SPI_CRCCALCULATION_DISABLE))
+
+#define IS_LL_SPI_CRC_POLYNOMIAL(__VALUE__) ((__VALUE__) >= 0x1U)
+
+/**
+ * @}
+ */
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SPI_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup SPI_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief De-initialize the SPI registers to their default reset values.
+ * @param SPIx SPI Instance
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: SPI registers are de-initialized
+ * - ERROR: SPI registers are not de-initialized
+ */
+ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx)
+{
+ ErrorStatus status = ERROR;
+
+ /* Check the parameters */
+ assert_param(IS_SPI_ALL_INSTANCE(SPIx));
+
+#if defined(SPI1)
+ if (SPIx == SPI1)
+ {
+ /* Force reset of SPI clock */
+ LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI1);
+
+ /* Release reset of SPI clock */
+ LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI1);
+
+ status = SUCCESS;
+ }
+#endif /* SPI1 */
+
+ return status;
+}
+
+/**
+ * @brief Initialize the SPI registers according to the specified parameters in SPI_InitStruct.
+ * @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
+ * SPI peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
+ * @param SPIx SPI Instance
+ * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
+ * @retval An ErrorStatus enumeration value. (Return always SUCCESS)
+ */
+ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct)
+{
+ ErrorStatus status = ERROR;
+
+ /* Check the SPI Instance SPIx*/
+ assert_param(IS_SPI_ALL_INSTANCE(SPIx));
+
+ /* Check the SPI parameters from SPI_InitStruct*/
+ assert_param(IS_LL_SPI_TRANSFER_DIRECTION(SPI_InitStruct->TransferDirection));
+ assert_param(IS_LL_SPI_MODE(SPI_InitStruct->Mode));
+ assert_param(IS_LL_SPI_DATAWIDTH(SPI_InitStruct->DataWidth));
+ assert_param(IS_LL_SPI_POLARITY(SPI_InitStruct->ClockPolarity));
+ assert_param(IS_LL_SPI_PHASE(SPI_InitStruct->ClockPhase));
+ assert_param(IS_LL_SPI_NSS(SPI_InitStruct->NSS));
+ assert_param(IS_LL_SPI_BAUDRATE(SPI_InitStruct->BaudRate));
+ assert_param(IS_LL_SPI_BITORDER(SPI_InitStruct->BitOrder));
+ assert_param(IS_LL_SPI_CRCCALCULATION(SPI_InitStruct->CRCCalculation));
+
+ if (LL_SPI_IsEnabled(SPIx) == 0x00000000U)
+ {
+ /*---------------------------- SPIx CR1 Configuration ------------------------
+ * Configure SPIx CR1 with parameters:
+ * - TransferDirection: SPI_CR1_BIDIMODE, SPI_CR1_BIDIOE and SPI_CR1_RXONLY bits
+ * - Master/Slave Mode: SPI_CR1_MSTR bit
+ * - ClockPolarity: SPI_CR1_CPOL bit
+ * - ClockPhase: SPI_CR1_CPHA bit
+ * - NSS management: SPI_CR1_SSM bit
+ * - BaudRate prescaler: SPI_CR1_BR[2:0] bits
+ * - BitOrder: SPI_CR1_LSBFIRST bit
+ * - CRCCalculation: SPI_CR1_CRCEN bit
+ */
+ MODIFY_REG(SPIx->CR1,
+ SPI_CR1_CLEAR_MASK,
+ SPI_InitStruct->TransferDirection | SPI_InitStruct->Mode |
+ SPI_InitStruct->ClockPolarity | SPI_InitStruct->ClockPhase |
+ SPI_InitStruct->NSS | SPI_InitStruct->BaudRate |
+ SPI_InitStruct->BitOrder | SPI_InitStruct->CRCCalculation);
+
+ /*---------------------------- SPIx CR2 Configuration ------------------------
+ * Configure SPIx CR2 with parameters:
+ * - DataWidth: DS[3:0] bits
+ * - NSS management: SSOE bit
+ */
+ MODIFY_REG(SPIx->CR2,
+ SPI_CR2_DS | SPI_CR2_SSOE,
+ SPI_InitStruct->DataWidth | (SPI_InitStruct->NSS >> 16U));
+
+ /* Set Rx FIFO to Quarter (1 Byte) in case of 8 Bits mode. No DataPacking by default */
+ if (SPI_InitStruct->DataWidth < LL_SPI_DATAWIDTH_9BIT)
+ {
+ LL_SPI_SetRxFIFOThreshold(SPIx, LL_SPI_RX_FIFO_TH_QUARTER);
+ }
+
+ /*---------------------------- SPIx CRCPR Configuration ----------------------
+ * Configure SPIx CRCPR with parameters:
+ * - CRCPoly: CRCPOLY[15:0] bits
+ */
+ if (SPI_InitStruct->CRCCalculation == LL_SPI_CRCCALCULATION_ENABLE)
+ {
+ assert_param(IS_LL_SPI_CRC_POLYNOMIAL(SPI_InitStruct->CRCPoly));
+ LL_SPI_SetCRCPolynomial(SPIx, SPI_InitStruct->CRCPoly);
+ }
+ status = SUCCESS;
+ }
+
+#if defined (SPI_I2S_SUPPORT)
+ /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */
+ CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD);
+#endif /* SPI_I2S_SUPPORT */
+ return status;
+}
+
+/**
+ * @brief Set each @ref LL_SPI_InitTypeDef field to default value.
+ * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
+ * whose fields will be set to default values.
+ * @retval None
+ */
+void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct)
+{
+ /* Set SPI_InitStruct fields to default values */
+ SPI_InitStruct->TransferDirection = LL_SPI_FULL_DUPLEX;
+ SPI_InitStruct->Mode = LL_SPI_MODE_SLAVE;
+ SPI_InitStruct->DataWidth = LL_SPI_DATAWIDTH_8BIT;
+ SPI_InitStruct->ClockPolarity = LL_SPI_POLARITY_LOW;
+ SPI_InitStruct->ClockPhase = LL_SPI_PHASE_1EDGE;
+ SPI_InitStruct->NSS = LL_SPI_NSS_HARD_INPUT;
+ SPI_InitStruct->BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV2;
+ SPI_InitStruct->BitOrder = LL_SPI_MSB_FIRST;
+ SPI_InitStruct->CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE;
+ SPI_InitStruct->CRCPoly = 7U;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#if defined(SPI_I2S_SUPPORT)
+/** @addtogroup I2S_LL
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup I2S_LL_Private_Constants I2S Private Constants
+ * @{
+ */
+/* I2S registers Masks */
+#define I2S_I2SCFGR_CLEAR_MASK (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | \
+ SPI_I2SCFGR_CKPOL | SPI_I2SCFGR_I2SSTD | \
+ SPI_I2SCFGR_I2SCFG | SPI_I2SCFGR_I2SMOD )
+
+#define I2S_I2SPR_CLEAR_MASK 0x0002U
+/**
+ * @}
+ */
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup I2S_LL_Private_Macros I2S Private Macros
+ * @{
+ */
+
+#define IS_LL_I2S_DATAFORMAT(__VALUE__) (((__VALUE__) == LL_I2S_DATAFORMAT_16B) \
+ || ((__VALUE__) == LL_I2S_DATAFORMAT_16B_EXTENDED) \
+ || ((__VALUE__) == LL_I2S_DATAFORMAT_24B) \
+ || ((__VALUE__) == LL_I2S_DATAFORMAT_32B))
+
+#define IS_LL_I2S_CPOL(__VALUE__) (((__VALUE__) == LL_I2S_POLARITY_LOW) \
+ || ((__VALUE__) == LL_I2S_POLARITY_HIGH))
+
+#define IS_LL_I2S_STANDARD(__VALUE__) (((__VALUE__) == LL_I2S_STANDARD_PHILIPS) \
+ || ((__VALUE__) == LL_I2S_STANDARD_MSB) \
+ || ((__VALUE__) == LL_I2S_STANDARD_LSB) \
+ || ((__VALUE__) == LL_I2S_STANDARD_PCM_SHORT) \
+ || ((__VALUE__) == LL_I2S_STANDARD_PCM_LONG))
+
+#define IS_LL_I2S_MODE(__VALUE__) (((__VALUE__) == LL_I2S_MODE_SLAVE_TX) \
+ || ((__VALUE__) == LL_I2S_MODE_SLAVE_RX) \
+ || ((__VALUE__) == LL_I2S_MODE_MASTER_TX) \
+ || ((__VALUE__) == LL_I2S_MODE_MASTER_RX))
+
+#define IS_LL_I2S_MCLK_OUTPUT(__VALUE__) (((__VALUE__) == LL_I2S_MCLK_OUTPUT_ENABLE) \
+ || ((__VALUE__) == LL_I2S_MCLK_OUTPUT_DISABLE))
+
+#define IS_LL_I2S_AUDIO_FREQ(__VALUE__) ((((__VALUE__) >= LL_I2S_AUDIOFREQ_8K) \
+ && ((__VALUE__) <= LL_I2S_AUDIOFREQ_192K)) \
+ || ((__VALUE__) == LL_I2S_AUDIOFREQ_DEFAULT))
+
+#define IS_LL_I2S_PRESCALER_LINEAR(__VALUE__) ((__VALUE__) >= 0x2U)
+
+#define IS_LL_I2S_PRESCALER_PARITY(__VALUE__) (((__VALUE__) == LL_I2S_PRESCALER_PARITY_EVEN) \
+ || ((__VALUE__) == LL_I2S_PRESCALER_PARITY_ODD))
+/**
+ * @}
+ */
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup I2S_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup I2S_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief De-initialize the SPI/I2S registers to their default reset values.
+ * @param SPIx SPI Instance
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: SPI registers are de-initialized
+ * - ERROR: SPI registers are not de-initialized
+ */
+ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx)
+{
+ return LL_SPI_DeInit(SPIx);
+}
+
+/**
+ * @brief Initializes the SPI/I2S registers according to the specified parameters in I2S_InitStruct.
+ * @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
+ * SPI peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
+ * @param SPIx SPI Instance
+ * @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: SPI registers are Initialized
+ * - ERROR: SPI registers are not Initialized
+ */
+ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct)
+{
+ uint32_t i2sdiv = 2U;
+ uint32_t i2sodd = 0U;
+ uint32_t packetlength = 1U;
+ uint32_t tmp;
+ LL_RCC_ClocksTypeDef rcc_clocks;
+ uint32_t sourceclock;
+ ErrorStatus status = ERROR;
+
+ /* Check the I2S parameters */
+ assert_param(IS_I2S_ALL_INSTANCE(SPIx));
+ assert_param(IS_LL_I2S_MODE(I2S_InitStruct->Mode));
+ assert_param(IS_LL_I2S_STANDARD(I2S_InitStruct->Standard));
+ assert_param(IS_LL_I2S_DATAFORMAT(I2S_InitStruct->DataFormat));
+ assert_param(IS_LL_I2S_MCLK_OUTPUT(I2S_InitStruct->MCLKOutput));
+ assert_param(IS_LL_I2S_AUDIO_FREQ(I2S_InitStruct->AudioFreq));
+ assert_param(IS_LL_I2S_CPOL(I2S_InitStruct->ClockPolarity));
+
+ if (LL_I2S_IsEnabled(SPIx) == 0x00000000U)
+ {
+ /*---------------------------- SPIx I2SCFGR Configuration --------------------
+ * Configure SPIx I2SCFGR with parameters:
+ * - Mode: SPI_I2SCFGR_I2SCFG[1:0] bit
+ * - Standard: SPI_I2SCFGR_I2SSTD[1:0] and SPI_I2SCFGR_PCMSYNC bits
+ * - DataFormat: SPI_I2SCFGR_CHLEN and SPI_I2SCFGR_DATLEN bits
+ * - ClockPolarity: SPI_I2SCFGR_CKPOL bit
+ */
+
+ /* Write to SPIx I2SCFGR */
+ MODIFY_REG(SPIx->I2SCFGR,
+ I2S_I2SCFGR_CLEAR_MASK,
+ I2S_InitStruct->Mode | I2S_InitStruct->Standard |
+ I2S_InitStruct->DataFormat | I2S_InitStruct->ClockPolarity |
+ SPI_I2SCFGR_I2SMOD);
+
+ /*---------------------------- SPIx I2SPR Configuration ----------------------
+ * Configure SPIx I2SPR with parameters:
+ * - MCLKOutput: SPI_I2SPR_MCKOE bit
+ * - AudioFreq: SPI_I2SPR_I2SDIV[7:0] and SPI_I2SPR_ODD bits
+ */
+
+ /* If the requested audio frequency is not the default, compute the prescaler (i2sodd, i2sdiv)
+ * else, default values are used: i2sodd = 0U, i2sdiv = 2U.
+ */
+ if (I2S_InitStruct->AudioFreq != LL_I2S_AUDIOFREQ_DEFAULT)
+ {
+ /* Check the frame length (For the Prescaler computing)
+ * Default value: LL_I2S_DATAFORMAT_16B (packetlength = 1U).
+ */
+ if (I2S_InitStruct->DataFormat != LL_I2S_DATAFORMAT_16B)
+ {
+ /* Packet length is 32 bits */
+ packetlength = 2U;
+ }
+
+ /* I2S Clock source is System clock: Get System Clock frequency */
+ LL_RCC_GetSystemClocksFreq(&rcc_clocks);
+
+ /* Get the source clock value: based on System Clock value */
+ sourceclock = rcc_clocks.SYSCLK_Frequency;
+
+ /* Compute the Real divider depending on the MCLK output state with a floating point */
+ if (I2S_InitStruct->MCLKOutput == LL_I2S_MCLK_OUTPUT_ENABLE)
+ {
+ /* MCLK output is enabled */
+ tmp = (((((sourceclock / 256U) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
+ }
+ else
+ {
+ /* MCLK output is disabled */
+ tmp = (((((sourceclock / (32U * packetlength)) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
+ }
+
+ /* Remove the floating point */
+ tmp = tmp / 10U;
+
+ /* Check the parity of the divider */
+ i2sodd = (tmp & (uint16_t)0x0001U);
+
+ /* Compute the i2sdiv prescaler */
+ i2sdiv = ((tmp - i2sodd) / 2U);
+
+ /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
+ i2sodd = (i2sodd << 8U);
+ }
+
+ /* Test if the divider is 1 or 0 or greater than 0xFF */
+ if ((i2sdiv < 2U) || (i2sdiv > 0xFFU))
+ {
+ /* Set the default values */
+ i2sdiv = 2U;
+ i2sodd = 0U;
+ }
+
+ /* Write to SPIx I2SPR register the computed value */
+ WRITE_REG(SPIx->I2SPR, i2sdiv | i2sodd | I2S_InitStruct->MCLKOutput);
+
+ status = SUCCESS;
+ }
+ return status;
+}
+
+/**
+ * @brief Set each @ref LL_I2S_InitTypeDef field to default value.
+ * @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
+ * whose fields will be set to default values.
+ * @retval None
+ */
+void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct)
+{
+ /*--------------- Reset I2S init structure parameters values -----------------*/
+ I2S_InitStruct->Mode = LL_I2S_MODE_SLAVE_TX;
+ I2S_InitStruct->Standard = LL_I2S_STANDARD_PHILIPS;
+ I2S_InitStruct->DataFormat = LL_I2S_DATAFORMAT_16B;
+ I2S_InitStruct->MCLKOutput = LL_I2S_MCLK_OUTPUT_DISABLE;
+ I2S_InitStruct->AudioFreq = LL_I2S_AUDIOFREQ_DEFAULT;
+ I2S_InitStruct->ClockPolarity = LL_I2S_POLARITY_LOW;
+}
+
+/**
+ * @brief Set linear and parity prescaler.
+ * @note To calculate value of PrescalerLinear(I2SDIV[7:0] bits) and PrescalerParity(ODD bit)\n
+ * Check Audio frequency table and formulas inside Reference Manual (SPI/I2S).
+ * @param SPIx SPI Instance
+ * @param PrescalerLinear value Min_Data=0x02 and Max_Data=0xFF.
+ * @param PrescalerParity This parameter can be one of the following values:
+ * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
+ * @arg @ref LL_I2S_PRESCALER_PARITY_ODD
+ * @retval None
+ */
+void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity)
+{
+ /* Check the I2S parameters */
+ assert_param(IS_I2S_ALL_INSTANCE(SPIx));
+ assert_param(IS_LL_I2S_PRESCALER_LINEAR(PrescalerLinear));
+ assert_param(IS_LL_I2S_PRESCALER_PARITY(PrescalerParity));
+
+ /* Write to SPIx I2SPR */
+ MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV | SPI_I2SPR_ODD, PrescalerLinear | (PrescalerParity << 8U));
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* SPI_I2S_SUPPORT */
+
+#endif /* defined (SPI1) */
+
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_ll_tim.c b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_ll_tim.c
new file mode 100644
index 0000000000..9ab836064c
--- /dev/null
+++ b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_ll_tim.c
@@ -0,0 +1,1335 @@
+/**
+ ******************************************************************************
+ * @file stm32c0xx_ll_tim.c
+ * @author MCD Application Team
+ * @brief TIM LL module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2022 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32c0xx_ll_tim.h"
+#include "stm32c0xx_ll_bus.h"
+
+#ifdef USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+/** @addtogroup STM32C0xx_LL_Driver
+ * @{
+ */
+
+#if defined (TIM1) || defined (TIM3) || defined (TIM14) || defined (TIM16) || defined (TIM17)
+
+/** @addtogroup TIM_LL
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup TIM_LL_Private_Macros
+ * @{
+ */
+#define IS_LL_TIM_COUNTERMODE(__VALUE__) (((__VALUE__) == LL_TIM_COUNTERMODE_UP) \
+ || ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \
+ || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \
+ || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \
+ || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN))
+
+#define IS_LL_TIM_CLOCKDIVISION(__VALUE__) (((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \
+ || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \
+ || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4))
+
+#define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \
+ || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \
+ || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \
+ || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \
+ || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \
+ || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \
+ || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \
+ || ((__VALUE__) == LL_TIM_OCMODE_PWM2) \
+ || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM1) \
+ || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM2) \
+ || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM1) \
+ || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM2) \
+ || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM1) \
+ || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM2))
+
+#define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \
+ || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE))
+
+#define IS_LL_TIM_OCPOLARITY(__VALUE__) (((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \
+ || ((__VALUE__) == LL_TIM_OCPOLARITY_LOW))
+
+#define IS_LL_TIM_OCIDLESTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCIDLESTATE_LOW) \
+ || ((__VALUE__) == LL_TIM_OCIDLESTATE_HIGH))
+
+#define IS_LL_TIM_ACTIVEINPUT(__VALUE__) (((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \
+ || ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \
+ || ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC))
+
+#define IS_LL_TIM_ICPSC(__VALUE__) (((__VALUE__) == LL_TIM_ICPSC_DIV1) \
+ || ((__VALUE__) == LL_TIM_ICPSC_DIV2) \
+ || ((__VALUE__) == LL_TIM_ICPSC_DIV4) \
+ || ((__VALUE__) == LL_TIM_ICPSC_DIV8))
+
+#define IS_LL_TIM_IC_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8))
+
+#define IS_LL_TIM_IC_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
+ || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING) \
+ || ((__VALUE__) == LL_TIM_IC_POLARITY_BOTHEDGE))
+
+#define IS_LL_TIM_ENCODERMODE(__VALUE__) (((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \
+ || ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \
+ || ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12))
+
+#define IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
+ || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING))
+
+#define IS_LL_TIM_OSSR_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSR_DISABLE) \
+ || ((__VALUE__) == LL_TIM_OSSR_ENABLE))
+
+#define IS_LL_TIM_OSSI_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSI_DISABLE) \
+ || ((__VALUE__) == LL_TIM_OSSI_ENABLE))
+
+#define IS_LL_TIM_LOCK_LEVEL(__VALUE__) (((__VALUE__) == LL_TIM_LOCKLEVEL_OFF) \
+ || ((__VALUE__) == LL_TIM_LOCKLEVEL_1) \
+ || ((__VALUE__) == LL_TIM_LOCKLEVEL_2) \
+ || ((__VALUE__) == LL_TIM_LOCKLEVEL_3))
+
+#define IS_LL_TIM_BREAK_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_DISABLE) \
+ || ((__VALUE__) == LL_TIM_BREAK_ENABLE))
+
+#define IS_LL_TIM_BREAK_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_POLARITY_LOW) \
+ || ((__VALUE__) == LL_TIM_BREAK_POLARITY_HIGH))
+
+#define IS_LL_TIM_BREAK_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1) \
+ || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N2) \
+ || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N4) \
+ || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N8) \
+ || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N6) \
+ || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N8) \
+ || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N6) \
+ || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N8) \
+ || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N6) \
+ || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N8) \
+ || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N5) \
+ || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N6) \
+ || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N8) \
+ || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N5) \
+ || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N6) \
+ || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N8))
+
+#define IS_LL_TIM_BREAK_AFMODE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_AFMODE_INPUT) \
+ || ((__VALUE__) == LL_TIM_BREAK_AFMODE_BIDIRECTIONAL))
+
+#define IS_LL_TIM_BREAK2_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_DISABLE) \
+ || ((__VALUE__) == LL_TIM_BREAK2_ENABLE))
+
+#define IS_LL_TIM_BREAK2_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_POLARITY_LOW) \
+ || ((__VALUE__) == LL_TIM_BREAK2_POLARITY_HIGH))
+
+#define IS_LL_TIM_BREAK2_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N2) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N4) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N8) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N6) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N8) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N6) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N8) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N6) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N8) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N5) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N6) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N8) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N5) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N6) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N8))
+
+#define IS_LL_TIM_BREAK2_AFMODE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_AFMODE_INPUT) \
+ || ((__VALUE__) == LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL))
+
+#define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__) (((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) \
+ || ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE))
+/**
+ * @}
+ */
+
+
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup TIM_LL_Private_Functions TIM Private Functions
+ * @{
+ */
+static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
+static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
+static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
+static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
+static ErrorStatus OC5Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
+static ErrorStatus OC6Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
+static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
+static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
+static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
+static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup TIM_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup TIM_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief Set TIMx registers to their reset values.
+ * @param TIMx Timer instance
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: TIMx registers are de-initialized
+ * - ERROR: invalid TIMx instance
+ */
+ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx)
+{
+ ErrorStatus result = SUCCESS;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(TIMx));
+
+ if (TIMx == TIM1)
+ {
+ LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM1);
+ LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM1);
+ }
+#if defined(TIM3)
+ else if (TIMx == TIM3)
+ {
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM3);
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM3);
+ }
+#endif /* TIM3 */
+
+ else if (TIMx == TIM14)
+ {
+ LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM14);
+ LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM14);
+ }
+
+ else if (TIMx == TIM16)
+ {
+ LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM16);
+ LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM16);
+ }
+#if defined(TIM17)
+ else if (TIMx == TIM17)
+ {
+ LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM17);
+ LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM17);
+ }
+#endif /* TIM17 */
+ else
+ {
+ result = ERROR;
+ }
+
+ return result;
+}
+
+/**
+ * @brief Set the fields of the time base unit configuration data structure
+ * to their default values.
+ * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (time base unit configuration data structure)
+ * @retval None
+ */
+void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct)
+{
+ /* Set the default configuration */
+ TIM_InitStruct->Prescaler = (uint16_t)0x0000;
+ TIM_InitStruct->CounterMode = LL_TIM_COUNTERMODE_UP;
+ TIM_InitStruct->Autoreload = 0xFFFFFFFFU;
+ TIM_InitStruct->ClockDivision = LL_TIM_CLOCKDIVISION_DIV1;
+ TIM_InitStruct->RepetitionCounter = 0x00000000U;
+}
+
+/**
+ * @brief Configure the TIMx time base unit.
+ * @param TIMx Timer Instance
+ * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure
+ * (TIMx time base unit configuration data structure)
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: TIMx registers are de-initialized
+ * - ERROR: not applicable
+ */
+ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct)
+{
+ uint32_t tmpcr1;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(TIMx));
+ assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode));
+ assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision));
+
+ tmpcr1 = LL_TIM_ReadReg(TIMx, CR1);
+
+ if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
+ {
+ /* Select the Counter Mode */
+ MODIFY_REG(tmpcr1, (TIM_CR1_DIR | TIM_CR1_CMS), TIM_InitStruct->CounterMode);
+ }
+
+ if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
+ {
+ /* Set the clock division */
+ MODIFY_REG(tmpcr1, TIM_CR1_CKD, TIM_InitStruct->ClockDivision);
+ }
+
+ /* Write to TIMx CR1 */
+ LL_TIM_WriteReg(TIMx, CR1, tmpcr1);
+
+ /* Set the Autoreload value */
+ LL_TIM_SetAutoReload(TIMx, TIM_InitStruct->Autoreload);
+
+ /* Set the Prescaler value */
+ LL_TIM_SetPrescaler(TIMx, TIM_InitStruct->Prescaler);
+
+ if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
+ {
+ /* Set the Repetition Counter value */
+ LL_TIM_SetRepetitionCounter(TIMx, TIM_InitStruct->RepetitionCounter);
+ }
+
+ /* Generate an update event to reload the Prescaler
+ and the repetition counter value (if applicable) immediately */
+ LL_TIM_GenerateEvent_UPDATE(TIMx);
+
+ return SUCCESS;
+}
+
+/**
+ * @brief Set the fields of the TIMx output channel configuration data
+ * structure to their default values.
+ * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure
+ * (the output channel configuration data structure)
+ * @retval None
+ */
+void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
+{
+ /* Set the default configuration */
+ TIM_OC_InitStruct->OCMode = LL_TIM_OCMODE_FROZEN;
+ TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE;
+ TIM_OC_InitStruct->OCNState = LL_TIM_OCSTATE_DISABLE;
+ TIM_OC_InitStruct->CompareValue = 0x00000000U;
+ TIM_OC_InitStruct->OCPolarity = LL_TIM_OCPOLARITY_HIGH;
+ TIM_OC_InitStruct->OCNPolarity = LL_TIM_OCPOLARITY_HIGH;
+ TIM_OC_InitStruct->OCIdleState = LL_TIM_OCIDLESTATE_LOW;
+ TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW;
+}
+
+/**
+ * @brief Configure the TIMx output channel.
+ * @param TIMx Timer Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @arg @ref LL_TIM_CHANNEL_CH5
+ * @arg @ref LL_TIM_CHANNEL_CH6
+ * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration
+ * data structure)
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: TIMx output channel is initialized
+ * - ERROR: TIMx output channel is not initialized
+ */
+ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
+{
+ ErrorStatus result = ERROR;
+
+ switch (Channel)
+ {
+ case LL_TIM_CHANNEL_CH1:
+ result = OC1Config(TIMx, TIM_OC_InitStruct);
+ break;
+ case LL_TIM_CHANNEL_CH2:
+ result = OC2Config(TIMx, TIM_OC_InitStruct);
+ break;
+ case LL_TIM_CHANNEL_CH3:
+ result = OC3Config(TIMx, TIM_OC_InitStruct);
+ break;
+ case LL_TIM_CHANNEL_CH4:
+ result = OC4Config(TIMx, TIM_OC_InitStruct);
+ break;
+ case LL_TIM_CHANNEL_CH5:
+ result = OC5Config(TIMx, TIM_OC_InitStruct);
+ break;
+ case LL_TIM_CHANNEL_CH6:
+ result = OC6Config(TIMx, TIM_OC_InitStruct);
+ break;
+ default:
+ break;
+ }
+
+ return result;
+}
+
+/**
+ * @brief Set the fields of the TIMx input channel configuration data
+ * structure to their default values.
+ * @param TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration
+ * data structure)
+ * @retval None
+ */
+void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
+{
+ /* Set the default configuration */
+ TIM_ICInitStruct->ICPolarity = LL_TIM_IC_POLARITY_RISING;
+ TIM_ICInitStruct->ICActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
+ TIM_ICInitStruct->ICPrescaler = LL_TIM_ICPSC_DIV1;
+ TIM_ICInitStruct->ICFilter = LL_TIM_IC_FILTER_FDIV1;
+}
+
+/**
+ * @brief Configure the TIMx input channel.
+ * @param TIMx Timer Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @param TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data
+ * structure)
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: TIMx output channel is initialized
+ * - ERROR: TIMx output channel is not initialized
+ */
+ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct)
+{
+ ErrorStatus result = ERROR;
+
+ switch (Channel)
+ {
+ case LL_TIM_CHANNEL_CH1:
+ result = IC1Config(TIMx, TIM_IC_InitStruct);
+ break;
+ case LL_TIM_CHANNEL_CH2:
+ result = IC2Config(TIMx, TIM_IC_InitStruct);
+ break;
+ case LL_TIM_CHANNEL_CH3:
+ result = IC3Config(TIMx, TIM_IC_InitStruct);
+ break;
+ case LL_TIM_CHANNEL_CH4:
+ result = IC4Config(TIMx, TIM_IC_InitStruct);
+ break;
+ default:
+ break;
+ }
+
+ return result;
+}
+
+/**
+ * @brief Fills each TIM_EncoderInitStruct field with its default value
+ * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface
+ * configuration data structure)
+ * @retval None
+ */
+void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
+{
+ /* Set the default configuration */
+ TIM_EncoderInitStruct->EncoderMode = LL_TIM_ENCODERMODE_X2_TI1;
+ TIM_EncoderInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING;
+ TIM_EncoderInitStruct->IC1ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
+ TIM_EncoderInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1;
+ TIM_EncoderInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1;
+ TIM_EncoderInitStruct->IC2Polarity = LL_TIM_IC_POLARITY_RISING;
+ TIM_EncoderInitStruct->IC2ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
+ TIM_EncoderInitStruct->IC2Prescaler = LL_TIM_ICPSC_DIV1;
+ TIM_EncoderInitStruct->IC2Filter = LL_TIM_IC_FILTER_FDIV1;
+}
+
+/**
+ * @brief Configure the encoder interface of the timer instance.
+ * @param TIMx Timer Instance
+ * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface
+ * configuration data structure)
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: TIMx registers are de-initialized
+ * - ERROR: not applicable
+ */
+ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
+{
+ uint32_t tmpccmr1;
+ uint32_t tmpccer;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx));
+ assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode));
+ assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity));
+ assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput));
+ assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler));
+ assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC1Filter));
+ assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC2Polarity));
+ assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC2ActiveInput));
+ assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC2Prescaler));
+ assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC2Filter));
+
+ /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
+ TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
+
+ /* Get the TIMx CCMR1 register value */
+ tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
+
+ /* Get the TIMx CCER register value */
+ tmpccer = LL_TIM_ReadReg(TIMx, CCER);
+
+ /* Configure TI1 */
+ tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC);
+ tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1ActiveInput >> 16U);
+ tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Filter >> 16U);
+ tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Prescaler >> 16U);
+
+ /* Configure TI2 */
+ tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC);
+ tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2ActiveInput >> 8U);
+ tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Filter >> 8U);
+ tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Prescaler >> 8U);
+
+ /* Set TI1 and TI2 polarity and enable TI1 and TI2 */
+ tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
+ tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity);
+ tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U);
+ tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
+
+ /* Set encoder mode */
+ LL_TIM_SetEncoderMode(TIMx, TIM_EncoderInitStruct->EncoderMode);
+
+ /* Write to TIMx CCMR1 */
+ LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
+
+ /* Write to TIMx CCER */
+ LL_TIM_WriteReg(TIMx, CCER, tmpccer);
+
+ return SUCCESS;
+}
+
+/**
+ * @brief Set the fields of the TIMx Hall sensor interface configuration data
+ * structure to their default values.
+ * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (HALL sensor interface
+ * configuration data structure)
+ * @retval None
+ */
+void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
+{
+ /* Set the default configuration */
+ TIM_HallSensorInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING;
+ TIM_HallSensorInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1;
+ TIM_HallSensorInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1;
+ TIM_HallSensorInitStruct->CommutationDelay = 0U;
+}
+
+/**
+ * @brief Configure the Hall sensor interface of the timer instance.
+ * @note TIMx CH1, CH2 and CH3 inputs connected through a XOR
+ * to the TI1 input channel
+ * @note TIMx slave mode controller is configured in reset mode.
+ Selected internal trigger is TI1F_ED.
+ * @note Channel 1 is configured as input, IC1 is mapped on TRC.
+ * @note Captured value stored in TIMx_CCR1 correspond to the time elapsed
+ * between 2 changes on the inputs. It gives information about motor speed.
+ * @note Channel 2 is configured in output PWM 2 mode.
+ * @note Compare value stored in TIMx_CCR2 corresponds to the commutation delay.
+ * @note OC2REF is selected as trigger output on TRGO.
+ * @note LL_TIM_IC_POLARITY_BOTHEDGE must not be used for TI1 when it is used
+ * when TIMx operates in Hall sensor interface mode.
+ * @param TIMx Timer Instance
+ * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor
+ * interface configuration data structure)
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: TIMx registers are de-initialized
+ * - ERROR: not applicable
+ */
+ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
+{
+ uint32_t tmpcr2;
+ uint32_t tmpccmr1;
+ uint32_t tmpccer;
+ uint32_t tmpsmcr;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(TIMx));
+ assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_HallSensorInitStruct->IC1Polarity));
+ assert_param(IS_LL_TIM_ICPSC(TIM_HallSensorInitStruct->IC1Prescaler));
+ assert_param(IS_LL_TIM_IC_FILTER(TIM_HallSensorInitStruct->IC1Filter));
+
+ /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
+ TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
+
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
+
+ /* Get the TIMx CCMR1 register value */
+ tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
+
+ /* Get the TIMx CCER register value */
+ tmpccer = LL_TIM_ReadReg(TIMx, CCER);
+
+ /* Get the TIMx SMCR register value */
+ tmpsmcr = LL_TIM_ReadReg(TIMx, SMCR);
+
+ /* Connect TIMx_CH1, CH2 and CH3 pins to the TI1 input */
+ tmpcr2 |= TIM_CR2_TI1S;
+
+ /* OC2REF signal is used as trigger output (TRGO) */
+ tmpcr2 |= LL_TIM_TRGO_OC2REF;
+
+ /* Configure the slave mode controller */
+ tmpsmcr &= (uint32_t)~(TIM_SMCR_TS | TIM_SMCR_SMS);
+ tmpsmcr |= LL_TIM_TS_TI1F_ED;
+ tmpsmcr |= LL_TIM_SLAVEMODE_RESET;
+
+ /* Configure input channel 1 */
+ tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC);
+ tmpccmr1 |= (uint32_t)(LL_TIM_ACTIVEINPUT_TRC >> 16U);
+ tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Filter >> 16U);
+ tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Prescaler >> 16U);
+
+ /* Configure input channel 2 */
+ tmpccmr1 &= (uint32_t)~(TIM_CCMR1_OC2M | TIM_CCMR1_OC2FE | TIM_CCMR1_OC2PE | TIM_CCMR1_OC2CE);
+ tmpccmr1 |= (uint32_t)(LL_TIM_OCMODE_PWM2 << 8U);
+
+ /* Set Channel 1 polarity and enable Channel 1 and Channel2 */
+ tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
+ tmpccer |= (uint32_t)(TIM_HallSensorInitStruct->IC1Polarity);
+ tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
+
+ /* Write to TIMx CR2 */
+ LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
+
+ /* Write to TIMx SMCR */
+ LL_TIM_WriteReg(TIMx, SMCR, tmpsmcr);
+
+ /* Write to TIMx CCMR1 */
+ LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
+
+ /* Write to TIMx CCER */
+ LL_TIM_WriteReg(TIMx, CCER, tmpccer);
+
+ /* Write to TIMx CCR2 */
+ LL_TIM_OC_SetCompareCH2(TIMx, TIM_HallSensorInitStruct->CommutationDelay);
+
+ return SUCCESS;
+}
+
+/**
+ * @brief Set the fields of the Break and Dead Time configuration data structure
+ * to their default values.
+ * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration
+ * data structure)
+ * @retval None
+ */
+void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
+{
+ /* Set the default configuration */
+ TIM_BDTRInitStruct->OSSRState = LL_TIM_OSSR_DISABLE;
+ TIM_BDTRInitStruct->OSSIState = LL_TIM_OSSI_DISABLE;
+ TIM_BDTRInitStruct->LockLevel = LL_TIM_LOCKLEVEL_OFF;
+ TIM_BDTRInitStruct->DeadTime = (uint8_t)0x00;
+ TIM_BDTRInitStruct->BreakState = LL_TIM_BREAK_DISABLE;
+ TIM_BDTRInitStruct->BreakPolarity = LL_TIM_BREAK_POLARITY_LOW;
+ TIM_BDTRInitStruct->BreakFilter = LL_TIM_BREAK_FILTER_FDIV1;
+ TIM_BDTRInitStruct->BreakAFMode = LL_TIM_BREAK_AFMODE_INPUT;
+ TIM_BDTRInitStruct->Break2State = LL_TIM_BREAK2_DISABLE;
+ TIM_BDTRInitStruct->Break2Polarity = LL_TIM_BREAK2_POLARITY_LOW;
+ TIM_BDTRInitStruct->Break2Filter = LL_TIM_BREAK2_FILTER_FDIV1;
+ TIM_BDTRInitStruct->Break2AFMode = LL_TIM_BREAK2_AFMODE_INPUT;
+ TIM_BDTRInitStruct->AutomaticOutput = LL_TIM_AUTOMATICOUTPUT_DISABLE;
+}
+
+/**
+ * @brief Configure the Break and Dead Time feature of the timer instance.
+ * @note As the bits BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR
+ * and DTG[7:0] can be write-locked depending on the LOCK configuration, it
+ * can be necessary to configure all of them during the first write access to
+ * the TIMx_BDTR register.
+ * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides a break input.
+ * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides a second break input.
+ * @param TIMx Timer Instance
+ * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration
+ * data structure)
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: Break and Dead Time is initialized
+ * - ERROR: not applicable
+ */
+ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
+{
+ uint32_t tmpbdtr = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_BREAK_INSTANCE(TIMx));
+ assert_param(IS_LL_TIM_OSSR_STATE(TIM_BDTRInitStruct->OSSRState));
+ assert_param(IS_LL_TIM_OSSI_STATE(TIM_BDTRInitStruct->OSSIState));
+ assert_param(IS_LL_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->LockLevel));
+ assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState));
+ assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity));
+ assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput));
+
+ /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
+ the OSSI State, the dead time value and the Automatic Output Enable Bit */
+
+ /* Set the BDTR bits */
+ MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, TIM_BDTRInitStruct->DeadTime);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, TIM_BDTRInitStruct->LockLevel);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, TIM_BDTRInitStruct->OSSIState);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, TIM_BDTRInitStruct->AutomaticOutput);
+ if (IS_TIM_ADVANCED_INSTANCE(TIMx))
+ {
+ assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter));
+ assert_param(IS_LL_TIM_BREAK_AFMODE(TIM_BDTRInitStruct->BreakAFMode));
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, TIM_BDTRInitStruct->BreakAFMode);
+ }
+
+ if (IS_TIM_BKIN2_INSTANCE(TIMx))
+ {
+ assert_param(IS_LL_TIM_BREAK2_STATE(TIM_BDTRInitStruct->Break2State));
+ assert_param(IS_LL_TIM_BREAK2_POLARITY(TIM_BDTRInitStruct->Break2Polarity));
+ assert_param(IS_LL_TIM_BREAK2_FILTER(TIM_BDTRInitStruct->Break2Filter));
+ assert_param(IS_LL_TIM_BREAK2_AFMODE(TIM_BDTRInitStruct->Break2AFMode));
+
+ /* Set the BREAK2 input related BDTR bit-fields */
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (TIM_BDTRInitStruct->Break2Filter));
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, TIM_BDTRInitStruct->Break2State);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, TIM_BDTRInitStruct->Break2Polarity);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, TIM_BDTRInitStruct->Break2AFMode);
+ }
+
+ /* Set TIMx_BDTR */
+ LL_TIM_WriteReg(TIMx, BDTR, tmpbdtr);
+
+ return SUCCESS;
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_LL_Private_Functions TIM Private Functions
+ * @brief Private functions
+ * @{
+ */
+/**
+ * @brief Configure the TIMx output channel 1.
+ * @param TIMx Timer Instance
+ * @param TIM_OCInitStruct pointer to the the TIMx output channel 1 configuration data structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: TIMx registers are de-initialized
+ * - ERROR: not applicable
+ */
+static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
+{
+ uint32_t tmpccmr1;
+ uint32_t tmpccer;
+ uint32_t tmpcr2;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CC1_INSTANCE(TIMx));
+ assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
+ assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
+ assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
+ assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
+ assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
+
+ /* Disable the Channel 1: Reset the CC1E Bit */
+ CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E);
+
+ /* Get the TIMx CCER register value */
+ tmpccer = LL_TIM_ReadReg(TIMx, CCER);
+
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
+
+ /* Get the TIMx CCMR1 register value */
+ tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
+
+ /* Reset Capture/Compare selection Bits */
+ CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC1S);
+
+ /* Set the Output Compare Mode */
+ MODIFY_REG(tmpccmr1, TIM_CCMR1_OC1M, TIM_OCInitStruct->OCMode);
+
+ /* Set the Output Compare Polarity */
+ MODIFY_REG(tmpccer, TIM_CCER_CC1P, TIM_OCInitStruct->OCPolarity);
+
+ /* Set the Output State */
+ MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState);
+
+ if (IS_TIM_BREAK_INSTANCE(TIMx))
+ {
+ assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
+ assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
+
+ /* Set the complementary output Polarity */
+ MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U);
+
+ /* Set the complementary output State */
+ MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U);
+
+ /* Set the Output Idle state */
+ MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState);
+
+ /* Set the complementary output Idle state */
+ MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U);
+ }
+
+ /* Write to TIMx CR2 */
+ LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
+
+ /* Write to TIMx CCMR1 */
+ LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
+
+ /* Set the Capture Compare Register value */
+ LL_TIM_OC_SetCompareCH1(TIMx, TIM_OCInitStruct->CompareValue);
+
+ /* Write to TIMx CCER */
+ LL_TIM_WriteReg(TIMx, CCER, tmpccer);
+
+ return SUCCESS;
+}
+
+/**
+ * @brief Configure the TIMx output channel 2.
+ * @param TIMx Timer Instance
+ * @param TIM_OCInitStruct pointer to the the TIMx output channel 2 configuration data structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: TIMx registers are de-initialized
+ * - ERROR: not applicable
+ */
+static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
+{
+ uint32_t tmpccmr1;
+ uint32_t tmpccer;
+ uint32_t tmpcr2;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CC2_INSTANCE(TIMx));
+ assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
+ assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
+ assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
+ assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
+ assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
+
+ /* Disable the Channel 2: Reset the CC2E Bit */
+ CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E);
+
+ /* Get the TIMx CCER register value */
+ tmpccer = LL_TIM_ReadReg(TIMx, CCER);
+
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
+
+ /* Get the TIMx CCMR1 register value */
+ tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
+
+ /* Reset Capture/Compare selection Bits */
+ CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC2S);
+
+ /* Select the Output Compare Mode */
+ MODIFY_REG(tmpccmr1, TIM_CCMR1_OC2M, TIM_OCInitStruct->OCMode << 8U);
+
+ /* Set the Output Compare Polarity */
+ MODIFY_REG(tmpccer, TIM_CCER_CC2P, TIM_OCInitStruct->OCPolarity << 4U);
+
+ /* Set the Output State */
+ MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U);
+
+ if (IS_TIM_BREAK_INSTANCE(TIMx))
+ {
+ assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
+ assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
+
+ /* Set the complementary output Polarity */
+ MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U);
+
+ /* Set the complementary output State */
+ MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U);
+
+ /* Set the Output Idle state */
+ MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U);
+
+ /* Set the complementary output Idle state */
+ MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U);
+ }
+
+ /* Write to TIMx CR2 */
+ LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
+
+ /* Write to TIMx CCMR1 */
+ LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
+
+ /* Set the Capture Compare Register value */
+ LL_TIM_OC_SetCompareCH2(TIMx, TIM_OCInitStruct->CompareValue);
+
+ /* Write to TIMx CCER */
+ LL_TIM_WriteReg(TIMx, CCER, tmpccer);
+
+ return SUCCESS;
+}
+
+/**
+ * @brief Configure the TIMx output channel 3.
+ * @param TIMx Timer Instance
+ * @param TIM_OCInitStruct pointer to the the TIMx output channel 3 configuration data structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: TIMx registers are de-initialized
+ * - ERROR: not applicable
+ */
+static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
+{
+ uint32_t tmpccmr2;
+ uint32_t tmpccer;
+ uint32_t tmpcr2;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CC3_INSTANCE(TIMx));
+ assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
+ assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
+ assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
+ assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
+ assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
+
+ /* Disable the Channel 3: Reset the CC3E Bit */
+ CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E);
+
+ /* Get the TIMx CCER register value */
+ tmpccer = LL_TIM_ReadReg(TIMx, CCER);
+
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
+
+ /* Get the TIMx CCMR2 register value */
+ tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
+
+ /* Reset Capture/Compare selection Bits */
+ CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S);
+
+ /* Select the Output Compare Mode */
+ MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode);
+
+ /* Set the Output Compare Polarity */
+ MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U);
+
+ /* Set the Output State */
+ MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U);
+
+ if (IS_TIM_BREAK_INSTANCE(TIMx))
+ {
+ assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
+ assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
+
+ /* Set the complementary output Polarity */
+ MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U);
+
+ /* Set the complementary output State */
+ MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U);
+
+ /* Set the Output Idle state */
+ MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U);
+
+ /* Set the complementary output Idle state */
+ MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U);
+ }
+
+ /* Write to TIMx CR2 */
+ LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
+
+ /* Write to TIMx CCMR2 */
+ LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
+
+ /* Set the Capture Compare Register value */
+ LL_TIM_OC_SetCompareCH3(TIMx, TIM_OCInitStruct->CompareValue);
+
+ /* Write to TIMx CCER */
+ LL_TIM_WriteReg(TIMx, CCER, tmpccer);
+
+ return SUCCESS;
+}
+
+/**
+ * @brief Configure the TIMx output channel 4.
+ * @param TIMx Timer Instance
+ * @param TIM_OCInitStruct pointer to the the TIMx output channel 4 configuration data structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: TIMx registers are de-initialized
+ * - ERROR: not applicable
+ */
+static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
+{
+ uint32_t tmpccmr2;
+ uint32_t tmpccer;
+ uint32_t tmpcr2;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CC4_INSTANCE(TIMx));
+ assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
+ assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
+ assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
+ assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
+ assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
+
+ /* Disable the Channel 4: Reset the CC4E Bit */
+ CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E);
+
+ /* Get the TIMx CCER register value */
+ tmpccer = LL_TIM_ReadReg(TIMx, CCER);
+
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
+
+ /* Get the TIMx CCMR2 register value */
+ tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
+
+ /* Reset Capture/Compare selection Bits */
+ CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S);
+
+ /* Select the Output Compare Mode */
+ MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U);
+
+ /* Set the Output Compare Polarity */
+ MODIFY_REG(tmpccer, TIM_CCER_CC4P, TIM_OCInitStruct->OCPolarity << 12U);
+
+ /* Set the Output State */
+ MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U);
+
+ if (IS_TIM_BREAK_INSTANCE(TIMx))
+ {
+ assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
+ assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
+
+ /* Set the Output Idle state */
+ MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U);
+ }
+
+ /* Write to TIMx CR2 */
+ LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
+
+ /* Write to TIMx CCMR2 */
+ LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
+
+ /* Set the Capture Compare Register value */
+ LL_TIM_OC_SetCompareCH4(TIMx, TIM_OCInitStruct->CompareValue);
+
+ /* Write to TIMx CCER */
+ LL_TIM_WriteReg(TIMx, CCER, tmpccer);
+
+ return SUCCESS;
+}
+
+/**
+ * @brief Configure the TIMx output channel 5.
+ * @param TIMx Timer Instance
+ * @param TIM_OCInitStruct pointer to the the TIMx output channel 5 configuration data structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: TIMx registers are de-initialized
+ * - ERROR: not applicable
+ */
+static ErrorStatus OC5Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
+{
+ uint32_t tmpccmr3;
+ uint32_t tmpccer;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CC5_INSTANCE(TIMx));
+ assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
+ assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
+ assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
+ assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
+ assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
+
+ /* Disable the Channel 5: Reset the CC5E Bit */
+ CLEAR_BIT(TIMx->CCER, TIM_CCER_CC5E);
+
+ /* Get the TIMx CCER register value */
+ tmpccer = LL_TIM_ReadReg(TIMx, CCER);
+
+ /* Get the TIMx CCMR3 register value */
+ tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3);
+
+ /* Select the Output Compare Mode */
+ MODIFY_REG(tmpccmr3, TIM_CCMR3_OC5M, TIM_OCInitStruct->OCMode);
+
+ /* Set the Output Compare Polarity */
+ MODIFY_REG(tmpccer, TIM_CCER_CC5P, TIM_OCInitStruct->OCPolarity << 16U);
+
+ /* Set the Output State */
+ MODIFY_REG(tmpccer, TIM_CCER_CC5E, TIM_OCInitStruct->OCState << 16U);
+
+ if (IS_TIM_BREAK_INSTANCE(TIMx))
+ {
+ assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
+ assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
+
+ /* Set the Output Idle state */
+ MODIFY_REG(TIMx->CR2, TIM_CR2_OIS5, TIM_OCInitStruct->OCIdleState << 8U);
+
+ }
+
+ /* Write to TIMx CCMR3 */
+ LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3);
+
+ /* Set the Capture Compare Register value */
+ LL_TIM_OC_SetCompareCH5(TIMx, TIM_OCInitStruct->CompareValue);
+
+ /* Write to TIMx CCER */
+ LL_TIM_WriteReg(TIMx, CCER, tmpccer);
+
+ return SUCCESS;
+}
+
+/**
+ * @brief Configure the TIMx output channel 6.
+ * @param TIMx Timer Instance
+ * @param TIM_OCInitStruct pointer to the the TIMx output channel 6 configuration data structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: TIMx registers are de-initialized
+ * - ERROR: not applicable
+ */
+static ErrorStatus OC6Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
+{
+ uint32_t tmpccmr3;
+ uint32_t tmpccer;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CC6_INSTANCE(TIMx));
+ assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
+ assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
+ assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
+ assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
+ assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
+
+ /* Disable the Channel 5: Reset the CC6E Bit */
+ CLEAR_BIT(TIMx->CCER, TIM_CCER_CC6E);
+
+ /* Get the TIMx CCER register value */
+ tmpccer = LL_TIM_ReadReg(TIMx, CCER);
+
+ /* Get the TIMx CCMR3 register value */
+ tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3);
+
+ /* Select the Output Compare Mode */
+ MODIFY_REG(tmpccmr3, TIM_CCMR3_OC6M, TIM_OCInitStruct->OCMode << 8U);
+
+ /* Set the Output Compare Polarity */
+ MODIFY_REG(tmpccer, TIM_CCER_CC6P, TIM_OCInitStruct->OCPolarity << 20U);
+
+ /* Set the Output State */
+ MODIFY_REG(tmpccer, TIM_CCER_CC6E, TIM_OCInitStruct->OCState << 20U);
+
+ if (IS_TIM_BREAK_INSTANCE(TIMx))
+ {
+ assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
+ assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
+
+ /* Set the Output Idle state */
+ MODIFY_REG(TIMx->CR2, TIM_CR2_OIS6, TIM_OCInitStruct->OCIdleState << 10U);
+ }
+
+ /* Write to TIMx CCMR3 */
+ LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3);
+
+ /* Set the Capture Compare Register value */
+ LL_TIM_OC_SetCompareCH6(TIMx, TIM_OCInitStruct->CompareValue);
+
+ /* Write to TIMx CCER */
+ LL_TIM_WriteReg(TIMx, CCER, tmpccer);
+
+ return SUCCESS;
+}
+
+/**
+ * @brief Configure the TIMx input channel 1.
+ * @param TIMx Timer Instance
+ * @param TIM_ICInitStruct pointer to the the TIMx input channel 1 configuration data structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: TIMx registers are de-initialized
+ * - ERROR: not applicable
+ */
+static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CC1_INSTANCE(TIMx));
+ assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
+ assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
+ assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
+ assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
+
+ /* Disable the Channel 1: Reset the CC1E Bit */
+ TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E;
+
+ /* Select the Input and set the filter and the prescaler value */
+ MODIFY_REG(TIMx->CCMR1,
+ (TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC),
+ (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
+
+ /* Select the Polarity and set the CC1E Bit */
+ MODIFY_REG(TIMx->CCER,
+ (TIM_CCER_CC1P | TIM_CCER_CC1NP),
+ (TIM_ICInitStruct->ICPolarity | TIM_CCER_CC1E));
+
+ return SUCCESS;
+}
+
+/**
+ * @brief Configure the TIMx input channel 2.
+ * @param TIMx Timer Instance
+ * @param TIM_ICInitStruct pointer to the the TIMx input channel 2 configuration data structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: TIMx registers are de-initialized
+ * - ERROR: not applicable
+ */
+static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CC2_INSTANCE(TIMx));
+ assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
+ assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
+ assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
+ assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
+
+ /* Disable the Channel 2: Reset the CC2E Bit */
+ TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E;
+
+ /* Select the Input and set the filter and the prescaler value */
+ MODIFY_REG(TIMx->CCMR1,
+ (TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC),
+ (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
+
+ /* Select the Polarity and set the CC2E Bit */
+ MODIFY_REG(TIMx->CCER,
+ (TIM_CCER_CC2P | TIM_CCER_CC2NP),
+ ((TIM_ICInitStruct->ICPolarity << 4U) | TIM_CCER_CC2E));
+
+ return SUCCESS;
+}
+
+/**
+ * @brief Configure the TIMx input channel 3.
+ * @param TIMx Timer Instance
+ * @param TIM_ICInitStruct pointer to the the TIMx input channel 3 configuration data structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: TIMx registers are de-initialized
+ * - ERROR: not applicable
+ */
+static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CC3_INSTANCE(TIMx));
+ assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
+ assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
+ assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
+ assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
+
+ /* Disable the Channel 3: Reset the CC3E Bit */
+ TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E;
+
+ /* Select the Input and set the filter and the prescaler value */
+ MODIFY_REG(TIMx->CCMR2,
+ (TIM_CCMR2_CC3S | TIM_CCMR2_IC3F | TIM_CCMR2_IC3PSC),
+ (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
+
+ /* Select the Polarity and set the CC3E Bit */
+ MODIFY_REG(TIMx->CCER,
+ (TIM_CCER_CC3P | TIM_CCER_CC3NP),
+ ((TIM_ICInitStruct->ICPolarity << 8U) | TIM_CCER_CC3E));
+
+ return SUCCESS;
+}
+
+/**
+ * @brief Configure the TIMx input channel 4.
+ * @param TIMx Timer Instance
+ * @param TIM_ICInitStruct pointer to the the TIMx input channel 4 configuration data structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: TIMx registers are de-initialized
+ * - ERROR: not applicable
+ */
+static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CC4_INSTANCE(TIMx));
+ assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
+ assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
+ assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
+ assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
+
+ /* Disable the Channel 4: Reset the CC4E Bit */
+ TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E;
+
+ /* Select the Input and set the filter and the prescaler value */
+ MODIFY_REG(TIMx->CCMR2,
+ (TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC),
+ (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
+
+ /* Select the Polarity and set the CC2E Bit */
+ MODIFY_REG(TIMx->CCER,
+ (TIM_CCER_CC4P | TIM_CCER_CC4NP),
+ ((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E));
+
+ return SUCCESS;
+}
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* TIM1 || TIM3 || TIM14 || TIM15 || TIM16 || TIM17 */
+
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_ll_usart.c b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_ll_usart.c
new file mode 100644
index 0000000000..c8af242c86
--- /dev/null
+++ b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_ll_usart.c
@@ -0,0 +1,380 @@
+/**
+ ******************************************************************************
+ * @file stm32c0xx_ll_usart.c
+ * @author MCD Application Team
+ * @brief USART LL module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2022 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32c0xx_ll_usart.h"
+#include "stm32c0xx_ll_rcc.h"
+#include "stm32c0xx_ll_bus.h"
+#ifdef USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+/** @addtogroup STM32C0xx_LL_Driver
+ * @{
+ */
+
+#if defined (USART1) || defined (USART2)
+
+/** @addtogroup USART_LL
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup USART_LL_Private_Macros
+ * @{
+ */
+
+#define IS_LL_USART_PRESCALER(__VALUE__) (((__VALUE__) == LL_USART_PRESCALER_DIV1) \
+ || ((__VALUE__) == LL_USART_PRESCALER_DIV2) \
+ || ((__VALUE__) == LL_USART_PRESCALER_DIV4) \
+ || ((__VALUE__) == LL_USART_PRESCALER_DIV6) \
+ || ((__VALUE__) == LL_USART_PRESCALER_DIV8) \
+ || ((__VALUE__) == LL_USART_PRESCALER_DIV10) \
+ || ((__VALUE__) == LL_USART_PRESCALER_DIV12) \
+ || ((__VALUE__) == LL_USART_PRESCALER_DIV16) \
+ || ((__VALUE__) == LL_USART_PRESCALER_DIV32) \
+ || ((__VALUE__) == LL_USART_PRESCALER_DIV64) \
+ || ((__VALUE__) == LL_USART_PRESCALER_DIV128) \
+ || ((__VALUE__) == LL_USART_PRESCALER_DIV256))
+
+/* __BAUDRATE__ The maximum Baud Rate is derived from the maximum clock available
+ * divided by the smallest oversampling used on the USART (i.e. 8) */
+#define IS_LL_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 8000000U)
+
+/* __VALUE__ In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. */
+#define IS_LL_USART_BRR_MIN(__VALUE__) ((__VALUE__) >= 16U)
+
+#define IS_LL_USART_DIRECTION(__VALUE__) (((__VALUE__) == LL_USART_DIRECTION_NONE) \
+ || ((__VALUE__) == LL_USART_DIRECTION_RX) \
+ || ((__VALUE__) == LL_USART_DIRECTION_TX) \
+ || ((__VALUE__) == LL_USART_DIRECTION_TX_RX))
+
+#define IS_LL_USART_PARITY(__VALUE__) (((__VALUE__) == LL_USART_PARITY_NONE) \
+ || ((__VALUE__) == LL_USART_PARITY_EVEN) \
+ || ((__VALUE__) == LL_USART_PARITY_ODD))
+
+#define IS_LL_USART_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_USART_DATAWIDTH_7B) \
+ || ((__VALUE__) == LL_USART_DATAWIDTH_8B) \
+ || ((__VALUE__) == LL_USART_DATAWIDTH_9B))
+
+#define IS_LL_USART_OVERSAMPLING(__VALUE__) (((__VALUE__) == LL_USART_OVERSAMPLING_16) \
+ || ((__VALUE__) == LL_USART_OVERSAMPLING_8))
+
+#define IS_LL_USART_LASTBITCLKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_LASTCLKPULSE_NO_OUTPUT) \
+ || ((__VALUE__) == LL_USART_LASTCLKPULSE_OUTPUT))
+
+#define IS_LL_USART_CLOCKPHASE(__VALUE__) (((__VALUE__) == LL_USART_PHASE_1EDGE) \
+ || ((__VALUE__) == LL_USART_PHASE_2EDGE))
+
+#define IS_LL_USART_CLOCKPOLARITY(__VALUE__) (((__VALUE__) == LL_USART_POLARITY_LOW) \
+ || ((__VALUE__) == LL_USART_POLARITY_HIGH))
+
+#define IS_LL_USART_CLOCKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_CLOCK_DISABLE) \
+ || ((__VALUE__) == LL_USART_CLOCK_ENABLE))
+
+#define IS_LL_USART_STOPBITS(__VALUE__) (((__VALUE__) == LL_USART_STOPBITS_0_5) \
+ || ((__VALUE__) == LL_USART_STOPBITS_1) \
+ || ((__VALUE__) == LL_USART_STOPBITS_1_5) \
+ || ((__VALUE__) == LL_USART_STOPBITS_2))
+
+#define IS_LL_USART_HWCONTROL(__VALUE__) (((__VALUE__) == LL_USART_HWCONTROL_NONE) \
+ || ((__VALUE__) == LL_USART_HWCONTROL_RTS) \
+ || ((__VALUE__) == LL_USART_HWCONTROL_CTS) \
+ || ((__VALUE__) == LL_USART_HWCONTROL_RTS_CTS))
+
+/**
+ * @}
+ */
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup USART_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup USART_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief De-initialize USART registers (Registers restored to their default values).
+ * @param USARTx USART Instance
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: USART registers are de-initialized
+ * - ERROR: USART registers are not de-initialized
+ */
+ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx)
+{
+ ErrorStatus status = SUCCESS;
+
+ /* Check the parameters */
+ assert_param(IS_UART_INSTANCE(USARTx));
+
+ if (USARTx == USART1)
+ {
+ /* Force reset of USART clock */
+ LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART1);
+
+ /* Release reset of USART clock */
+ LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART1);
+ }
+ else if (USARTx == USART2)
+ {
+ /* Force reset of USART clock */
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART2);
+
+ /* Release reset of USART clock */
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART2);
+ }
+ else
+ {
+ status = ERROR;
+ }
+
+ return (status);
+}
+
+/**
+ * @brief Initialize USART registers according to the specified
+ * parameters in USART_InitStruct.
+ * @note As some bits in USART configuration registers can only be written when
+ * the USART is disabled (USART_CR1_UE bit =0), USART Peripheral should be in disabled state prior calling
+ * this function. Otherwise, ERROR result will be returned.
+ * @note Baud rate value stored in USART_InitStruct BaudRate field, should be valid (different from 0).
+ * @param USARTx USART Instance
+ * @param USART_InitStruct pointer to a LL_USART_InitTypeDef structure
+ * that contains the configuration information for the specified USART peripheral.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: USART registers are initialized according to USART_InitStruct content
+ * - ERROR: Problem occurred during USART Registers initialization
+ */
+ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct)
+{
+ ErrorStatus status = ERROR;
+ uint32_t periphclk = LL_RCC_PERIPH_FREQUENCY_NO;
+ LL_RCC_ClocksTypeDef RCC_Clocks;
+
+ /* Check the parameters */
+ assert_param(IS_UART_INSTANCE(USARTx));
+ assert_param(IS_LL_USART_PRESCALER(USART_InitStruct->PrescalerValue));
+ assert_param(IS_LL_USART_BAUDRATE(USART_InitStruct->BaudRate));
+ assert_param(IS_LL_USART_DATAWIDTH(USART_InitStruct->DataWidth));
+ assert_param(IS_LL_USART_STOPBITS(USART_InitStruct->StopBits));
+ assert_param(IS_LL_USART_PARITY(USART_InitStruct->Parity));
+ assert_param(IS_LL_USART_DIRECTION(USART_InitStruct->TransferDirection));
+ assert_param(IS_LL_USART_HWCONTROL(USART_InitStruct->HardwareFlowControl));
+ assert_param(IS_LL_USART_OVERSAMPLING(USART_InitStruct->OverSampling));
+
+ /* USART needs to be in disabled state, in order to be able to configure some bits in
+ CRx registers */
+ if (LL_USART_IsEnabled(USARTx) == 0U)
+ {
+ /*---------------------------- USART CR1 Configuration ---------------------
+ * Configure USARTx CR1 (USART Word Length, Parity, Mode and Oversampling bits) with parameters:
+ * - DataWidth: USART_CR1_M bits according to USART_InitStruct->DataWidth value
+ * - Parity: USART_CR1_PCE, USART_CR1_PS bits according to USART_InitStruct->Parity value
+ * - TransferDirection: USART_CR1_TE, USART_CR1_RE bits according to USART_InitStruct->TransferDirection value
+ * - Oversampling: USART_CR1_OVER8 bit according to USART_InitStruct->OverSampling value.
+ */
+ MODIFY_REG(USARTx->CR1,
+ (USART_CR1_M | USART_CR1_PCE | USART_CR1_PS |
+ USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8),
+ (USART_InitStruct->DataWidth | USART_InitStruct->Parity |
+ USART_InitStruct->TransferDirection | USART_InitStruct->OverSampling));
+
+ /*---------------------------- USART CR2 Configuration ---------------------
+ * Configure USARTx CR2 (Stop bits) with parameters:
+ * - Stop Bits: USART_CR2_STOP bits according to USART_InitStruct->StopBits value.
+ * - CLKEN, CPOL, CPHA and LBCL bits are to be configured using LL_USART_ClockInit().
+ */
+ LL_USART_SetStopBitsLength(USARTx, USART_InitStruct->StopBits);
+
+ /*---------------------------- USART CR3 Configuration ---------------------
+ * Configure USARTx CR3 (Hardware Flow Control) with parameters:
+ * - HardwareFlowControl: USART_CR3_RTSE, USART_CR3_CTSE bits according to
+ * USART_InitStruct->HardwareFlowControl value.
+ */
+ LL_USART_SetHWFlowCtrl(USARTx, USART_InitStruct->HardwareFlowControl);
+
+ /*---------------------------- USART BRR Configuration ---------------------
+ * Retrieve Clock frequency used for USART Peripheral
+ */
+ if (USARTx == USART1)
+ {
+ periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART1_CLKSOURCE);
+ }
+ else if (USARTx == USART2)
+ {
+ /* USART2 clock is PCLK */
+ LL_RCC_GetSystemClocksFreq(&RCC_Clocks);
+ periphclk = RCC_Clocks.PCLK1_Frequency;
+ }
+ else
+ {
+ /* Nothing to do, as error code is already assigned to ERROR value */
+ }
+
+ /* Configure the USART Baud Rate :
+ - prescaler value is required
+ - valid baud rate value (different from 0) is required
+ - Peripheral clock as returned by RCC service, should be valid (different from 0).
+ */
+ if ((periphclk != LL_RCC_PERIPH_FREQUENCY_NO)
+ && (USART_InitStruct->BaudRate != 0U))
+ {
+ status = SUCCESS;
+ LL_USART_SetBaudRate(USARTx,
+ periphclk,
+ USART_InitStruct->PrescalerValue,
+ USART_InitStruct->OverSampling,
+ USART_InitStruct->BaudRate);
+
+ /* Check BRR is greater than or equal to 16d */
+ assert_param(IS_LL_USART_BRR_MIN(USARTx->BRR));
+ }
+
+ /*---------------------------- USART PRESC Configuration -----------------------
+ * Configure USARTx PRESC (Prescaler) with parameters:
+ * - PrescalerValue: USART_PRESC_PRESCALER bits according to USART_InitStruct->PrescalerValue value.
+ */
+ LL_USART_SetPrescaler(USARTx, USART_InitStruct->PrescalerValue);
+ }
+ /* Endif (=> USART not in Disabled state => return ERROR) */
+
+ return (status);
+}
+
+/**
+ * @brief Set each @ref LL_USART_InitTypeDef field to default value.
+ * @param USART_InitStruct pointer to a @ref LL_USART_InitTypeDef structure
+ * whose fields will be set to default values.
+ * @retval None
+ */
+
+void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct)
+{
+ /* Set USART_InitStruct fields to default values */
+ USART_InitStruct->PrescalerValue = LL_USART_PRESCALER_DIV1;
+ USART_InitStruct->BaudRate = 9600U;
+ USART_InitStruct->DataWidth = LL_USART_DATAWIDTH_8B;
+ USART_InitStruct->StopBits = LL_USART_STOPBITS_1;
+ USART_InitStruct->Parity = LL_USART_PARITY_NONE ;
+ USART_InitStruct->TransferDirection = LL_USART_DIRECTION_TX_RX;
+ USART_InitStruct->HardwareFlowControl = LL_USART_HWCONTROL_NONE;
+ USART_InitStruct->OverSampling = LL_USART_OVERSAMPLING_16;
+}
+
+/**
+ * @brief Initialize USART Clock related settings according to the
+ * specified parameters in the USART_ClockInitStruct.
+ * @note As some bits in USART configuration registers can only be written when
+ * the USART is disabled (USART_CR1_UE bit =0), USART Peripheral should be in disabled state prior calling
+ * this function. Otherwise, ERROR result will be returned.
+ * @param USARTx USART Instance
+ * @param USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure
+ * that contains the Clock configuration information for the specified USART peripheral.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: USART registers related to Clock settings are initialized according
+ * to USART_ClockInitStruct content
+ * - ERROR: Problem occurred during USART Registers initialization
+ */
+ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
+{
+ ErrorStatus status = SUCCESS;
+
+ /* Check USART Instance and Clock signal output parameters */
+ assert_param(IS_UART_INSTANCE(USARTx));
+ assert_param(IS_LL_USART_CLOCKOUTPUT(USART_ClockInitStruct->ClockOutput));
+
+ /* USART needs to be in disabled state, in order to be able to configure some bits in
+ CRx registers */
+ if (LL_USART_IsEnabled(USARTx) == 0U)
+ {
+ /* Ensure USART instance is USART capable */
+ assert_param(IS_USART_INSTANCE(USARTx));
+
+ /* Check clock related parameters */
+ assert_param(IS_LL_USART_CLOCKPOLARITY(USART_ClockInitStruct->ClockPolarity));
+ assert_param(IS_LL_USART_CLOCKPHASE(USART_ClockInitStruct->ClockPhase));
+ assert_param(IS_LL_USART_LASTBITCLKOUTPUT(USART_ClockInitStruct->LastBitClockPulse));
+
+ /*---------------------------- USART CR2 Configuration -----------------------
+ * Configure USARTx CR2 (Clock signal related bits) with parameters:
+ * - Clock Output: USART_CR2_CLKEN bit according to USART_ClockInitStruct->ClockOutput value
+ * - Clock Polarity: USART_CR2_CPOL bit according to USART_ClockInitStruct->ClockPolarity value
+ * - Clock Phase: USART_CR2_CPHA bit according to USART_ClockInitStruct->ClockPhase value
+ * - Last Bit Clock Pulse Output: USART_CR2_LBCL bit according to USART_ClockInitStruct->LastBitClockPulse value.
+ */
+ MODIFY_REG(USARTx->CR2,
+ USART_CR2_CLKEN | USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL,
+ USART_ClockInitStruct->ClockOutput | USART_ClockInitStruct->ClockPolarity |
+ USART_ClockInitStruct->ClockPhase | USART_ClockInitStruct->LastBitClockPulse);
+ }
+ /* Else (USART not in Disabled state => return ERROR */
+ else
+ {
+ status = ERROR;
+ }
+
+ return (status);
+}
+
+/**
+ * @brief Set each field of a @ref LL_USART_ClockInitTypeDef type structure to default value.
+ * @param USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure
+ * whose fields will be set to default values.
+ * @retval None
+ */
+void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
+{
+ /* Set LL_USART_ClockInitStruct fields with default values */
+ USART_ClockInitStruct->ClockOutput = LL_USART_CLOCK_DISABLE;
+ USART_ClockInitStruct->ClockPolarity = LL_USART_POLARITY_LOW; /* Not relevant when ClockOutput =
+ LL_USART_CLOCK_DISABLE */
+ USART_ClockInitStruct->ClockPhase = LL_USART_PHASE_1EDGE; /* Not relevant when ClockOutput =
+ LL_USART_CLOCK_DISABLE */
+ USART_ClockInitStruct->LastBitClockPulse = LL_USART_LASTCLKPULSE_NO_OUTPUT; /* Not relevant when ClockOutput =
+ LL_USART_CLOCK_DISABLE */
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* USART1 || USART2 */
+
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_ll_utils.c b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_ll_utils.c
new file mode 100644
index 0000000000..e7afe82c10
--- /dev/null
+++ b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_ll_utils.c
@@ -0,0 +1,275 @@
+/**
+ ******************************************************************************
+ * @file stm32c0xx_ll_utils.c
+ * @author MCD Application Team
+ * @brief UTILS LL module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2022 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+/* Includes ------------------------------------------------------------------*/
+#include "stm32c0xx_ll_utils.h"
+#include "stm32c0xx_ll_rcc.h"
+#include "stm32c0xx_ll_system.h"
+#include "stm32c0xx_ll_pwr.h"
+#ifdef USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+/** @addtogroup STM32C0xx_LL_Driver
+ * @{
+ */
+
+/** @addtogroup UTILS_LL
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @addtogroup UTILS_LL_Private_Constants
+ * @{
+ */
+#define UTILS_MAX_FREQUENCY 48000000U /*!< Maximum frequency for system clock, in Hz */
+
+/* Defines used for HSE range */
+#define UTILS_HSE_FREQUENCY_MIN 4000000U /*!< Frequency min for HSE frequency, in Hz */
+#define UTILS_HSE_FREQUENCY_MAX 48000000U /*!< Frequency max for HSE frequency, in Hz */
+
+/* Defines used for FLASH latency according to HCLK Frequency */
+#define UTILS_SCALE1_LATENCY1_FREQ 24000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */
+#define UTILS_SCALE1_LATENCY2_FREQ 48000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 1 */
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup UTILS_LL_Private_Macros
+ * @{
+ */
+#define IS_LL_UTILS_SYSCLK_DIV(__VALUE__) (((__VALUE__) == LL_RCC_SYSCLK_DIV_1) \
+ || ((__VALUE__) == LL_RCC_SYSCLK_DIV_2) \
+ || ((__VALUE__) == LL_RCC_SYSCLK_DIV_4) \
+ || ((__VALUE__) == LL_RCC_SYSCLK_DIV_8) \
+ || ((__VALUE__) == LL_RCC_SYSCLK_DIV_16) \
+ || ((__VALUE__) == LL_RCC_SYSCLK_DIV_64) \
+ || ((__VALUE__) == LL_RCC_SYSCLK_DIV_128) \
+ || ((__VALUE__) == LL_RCC_SYSCLK_DIV_256) \
+ || ((__VALUE__) == LL_RCC_SYSCLK_DIV_512))
+
+#define IS_LL_UTILS_APB1_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB1_DIV_1) \
+ || ((__VALUE__) == LL_RCC_APB1_DIV_2) \
+ || ((__VALUE__) == LL_RCC_APB1_DIV_4) \
+ || ((__VALUE__) == LL_RCC_APB1_DIV_8) \
+ || ((__VALUE__) == LL_RCC_APB1_DIV_16))
+
+#define IS_LL_UTILS_HSI_DIV(__VALUE__) (((__VALUE__) == LL_RCC_HSI_DIV_1) \
+ || ((__VALUE__) == LL_RCC_HSI_DIV_2) \
+ || ((__VALUE__) == LL_RCC_HSI_DIV_4) \
+ || ((__VALUE__) == LL_RCC_HSI_DIV_8) \
+ || ((__VALUE__) == LL_RCC_HSI_DIV_16) \
+ || ((__VALUE__) == LL_RCC_HSI_DIV_32) \
+ || ((__VALUE__) == LL_RCC_HSI_DIV_64) \
+ || ((__VALUE__) == LL_RCC_HSI_DIV_128))
+
+#define IS_LL_UTILS_HSIKER_DIV(__VALUE__) (((__VALUE__) == LL_RCC_HSIKER_DIV_1) \
+ || ((__VALUE__) == LL_RCC_HSIKER_DIV_2) \
+ || ((__VALUE__) == LL_RCC_HSIKER_DIV_3) \
+ || ((__VALUE__) == LL_RCC_HSIKER_DIV_4) \
+ || ((__VALUE__) == LL_RCC_HSIKER_DIV_5) \
+ || ((__VALUE__) == LL_RCC_HSIKER_DIV_6) \
+ || ((__VALUE__) == LL_RCC_HSIKER_DIV_7) \
+ || ((__VALUE__) == LL_RCC_HSIKER_DIV_8))
+
+#define IS_LL_UTILS_HSE_BYPASS(__STATE__) (((__STATE__) == LL_UTILS_HSEBYPASS_ON) \
+ || ((__STATE__) == LL_UTILS_HSEBYPASS_OFF))
+
+#define IS_LL_UTILS_HSE_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) >= UTILS_HSE_FREQUENCY_MIN)\
+ && ((__FREQUENCY__) <= UTILS_HSE_FREQUENCY_MAX))
+/**
+ * @}
+ */
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup UTILS_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup UTILS_LL_EF_DELAY
+ * @{
+ */
+
+/**
+ * @brief This function configures the Cortex-M SysTick source to have 1ms time base.
+ * @note When a RTOS is used, it is recommended to avoid changing the Systick
+ * configuration by calling this function, for a delay use rather osDelay RTOS service.
+ * @param HCLKFrequency HCLK frequency in Hz
+ * @note HCLK frequency can be calculated thanks to RCC helper macro or function @ref LL_RCC_GetSystemClocksFreq
+ * @retval None
+ */
+void LL_Init1msTick(uint32_t HCLKFrequency)
+{
+ /* Use frequency provided in argument */
+ LL_InitTick(HCLKFrequency, 1000U);
+}
+
+/**
+ * @brief This function provides accurate delay (in milliseconds) based
+ * on SysTick counter flag
+ * @note When a RTOS is used, it is recommended to avoid using blocking delay
+ * and use rather osDelay service.
+ * @note To respect 1ms timebase, user should call @ref LL_Init1msTick function which
+ * will configure Systick to 1ms
+ * @param Delay specifies the delay time length, in milliseconds.
+ * @retval None
+ */
+void LL_mDelay(uint32_t Delay)
+{
+ __IO uint32_t tmp = SysTick->CTRL; /* Clear the COUNTFLAG first */
+ uint32_t tmpDelay; /* MISRAC2012-Rule-17.8 */
+ /* Add this code to indicate that local variable is not used */
+ ((void)tmp);
+ tmpDelay = Delay;
+ /* Add a period to guaranty minimum wait */
+ if (tmpDelay < LL_MAX_DELAY)
+ {
+ tmpDelay ++;
+ }
+
+ while (tmpDelay != 0U)
+ {
+ if ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) != 0U)
+ {
+ tmpDelay --;
+ }
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup UTILS_EF_SYSTEM
+ * @brief System Configuration functions
+ *
+ @verbatim
+ ===============================================================================
+ ##### System Configuration functions #####
+ ===============================================================================
+ [..]
+ System, AHB and APB buses clocks configuration
+
+ (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 is 48000000 Hz.
+ @endverbatim
+ @internal
+ Depending on the device voltage range, the maximum frequency should be
+ adapted accordingly:
+
+ (++) Table 1. HCLK clock frequency.
+ (++) +------------------------------------+
+ (++) | Latency | HCLK clock |
+ (++) | | frequency (MHz) |
+ (++) | | |
+ (++) | |-------------------
+ (++) | | voltage range 1 |
+ (++) | | 1.08V - 1.32V |
+ (++) |-----------------|------------------|
+ (++) |0WS(1 CPU cycles)| HCLK <= 24 |
+ (++) |-----------------|------------------|
+ (++) |1WS(2 CPU cycles)| HCLK <= 48 |
+ (++) +------------------------------------+
+
+ @endinternal
+ * @{
+ */
+
+/**
+ * @brief This function sets directly SystemCoreClock CMSIS variable.
+ * @note Variable can be calculated also through SystemCoreClockUpdate function.
+ * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
+ * @retval None
+ */
+void LL_SetSystemCoreClock(uint32_t HCLKFrequency)
+{
+ /* HCLK clock frequency */
+ SystemCoreClock = HCLKFrequency;
+}
+
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup UTILS_LL_Private_Functions
+ * @{
+ */
+/**
+ * @brief Update number of Flash wait states in line with new frequency and current
+ voltage range.
+ * @param HCLK_Frequency HCLK frequency
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: Latency has been modified
+ * - ERROR: Latency cannot be modified
+ */
+ErrorStatus UTILS_SetFlashLatency(uint32_t HCLK_Frequency)
+{
+ ErrorStatus status = SUCCESS;
+
+ uint32_t latency = LL_FLASH_LATENCY_0; /* default value 0WS */
+
+ /* Frequency cannot be equal to 0 */
+ if (HCLK_Frequency == 0U)
+ {
+ status = ERROR;
+ }
+ else
+ {
+ if (HCLK_Frequency > UTILS_SCALE1_LATENCY1_FREQ)
+ {
+ /* 24 < HCLK <= 48 => 1WS (2 CPU cycles) */
+ latency = LL_FLASH_LATENCY_1;
+ }
+ else
+ {
+ /* else HCLK_Frequency < 24MHz default LL_FLASH_LATENCY_0 0WS */
+ }
+
+ LL_FLASH_SetLatency(latency);
+
+ /* Check that the new number of wait states is taken into account to access the Flash
+ memory by reading the FLASH_ACR register */
+ if (LL_FLASH_GetLatency() != latency)
+ {
+ status = ERROR;
+ }
+ }
+ return status;
+}
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/system/Drivers/STM32C0xx_HAL_Driver/_htmresc/Add button.svg b/system/Drivers/STM32C0xx_HAL_Driver/_htmresc/Add button.svg
new file mode 100644
index 0000000000..c211545dad
--- /dev/null
+++ b/system/Drivers/STM32C0xx_HAL_Driver/_htmresc/Add button.svg
@@ -0,0 +1,2 @@
+
+
diff --git a/system/Drivers/STM32C0xx_HAL_Driver/_htmresc/Update.svg b/system/Drivers/STM32C0xx_HAL_Driver/_htmresc/Update.svg
new file mode 100644
index 0000000000..f88381f1e6
--- /dev/null
+++ b/system/Drivers/STM32C0xx_HAL_Driver/_htmresc/Update.svg
@@ -0,0 +1,2 @@
+
+
diff --git a/system/Drivers/STM32C0xx_HAL_Driver/_htmresc/favicon.png b/system/Drivers/STM32C0xx_HAL_Driver/_htmresc/favicon.png
new file mode 100644
index 0000000000..06713eec49
Binary files /dev/null and b/system/Drivers/STM32C0xx_HAL_Driver/_htmresc/favicon.png differ
diff --git a/system/Drivers/STM32C0xx_HAL_Driver/_htmresc/mini-st.css b/system/Drivers/STM32C0xx_HAL_Driver/_htmresc/mini-st.css
new file mode 100644
index 0000000000..3caf11c32e
--- /dev/null
+++ b/system/Drivers/STM32C0xx_HAL_Driver/_htmresc/mini-st.css
@@ -0,0 +1,1700 @@
+@charset "UTF-8";
+/*
+ Flavor name: Default (mini-default)
+ Author: Angelos Chalaris (chalarangelo@gmail.com)
+ Maintainers: Angelos Chalaris
+ mini.css version: v3.0.0-alpha.3
+*/
+/*
+ Browsers resets and base typography.
+*/
+/* Core module CSS variable definitions */
+:root {
+ --fore-color: #111;
+ --secondary-fore-color: #444;
+ --back-color: #f8f8f8;
+ --secondary-back-color: #f0f0f0;
+ --blockquote-color: #f57c00;
+ --pre-color: #1565c0;
+ --border-color: #aaa;
+ --secondary-border-color: #ddd;
+ --heading-ratio: 1.19;
+ --universal-margin: 0.5rem;
+ --universal-padding: 0.125rem;
+ --universal-border-radius: 0.125rem;
+ --a-link-color: #0277bd;
+ --a-visited-color: #01579b; }
+
+html {
+ font-size: 14px; }
+
+a, b, del, em, i, ins, q, span, strong, u {
+ font-size: 1em; }
+
+html, * {
+ font-family: -apple-system, BlinkMacSystemFont, "Segoe UI", Roboto, Ubuntu, "Helvetica Neue", Helvetica, sans-serif;
+ line-height: 1.4;
+ -webkit-text-size-adjust: 100%; }
+
+* {
+ font-size: 1rem; }
+
+body {
+ margin: 0;
+ color: var(--fore-color);
+ background: var(--back-color); }
+
+details {
+ display: block; }
+
+summary {
+ display: list-item; }
+
+abbr[title] {
+ border-bottom: none;
+ text-decoration: underline dotted; }
+
+input {
+ overflow: visible; }
+
+img {
+ max-width: 100%;
+ height: auto; }
+
+h1, h2, h3, h4, h5, h6 {
+ line-height: 1.2;
+ margin: calc(1.5 * var(--universal-margin)) var(--universal-margin);
+ font-weight: 500; }
+ h1 small, h2 small, h3 small, h4 small, h5 small, h6 small {
+ color: var(--secondary-fore-color);
+ display: block;
+ margin-top: -0.25rem; }
+
+h1 {
+ font-size: calc(1rem * var(--heading-ratio) * var(--heading-ratio) * var(--heading-ratio)); }
+
+h2 {
+ font-size: calc(1rem * var(--heading-ratio) * var(--heading-ratio); );
+ background: var(--mark-back-color);
+ font-weight: 600;
+ padding: 0.1em 0.5em 0.2em 0.5em;
+ color: var(--mark-fore-color); }
+
+h3 {
+ font-size: calc(1rem * var(--heading-ratio));
+ padding-left: calc(2 * var(--universal-margin));
+ /* background: var(--border-color); */
+ }
+
+h4 {
+ font-size: 1rem;);
+ padding-left: calc(4 * var(--universal-margin)); }
+
+h5 {
+ font-size: 1rem; }
+
+h6 {
+ font-size: calc(1rem / var(--heading-ratio)); }
+
+p {
+ margin: var(--universal-margin); }
+
+ol, ul {
+ margin: var(--universal-margin);
+ padding-left: calc(6 * var(--universal-margin)); }
+
+b, strong {
+ font-weight: 700; }
+
+hr {
+ box-sizing: content-box;
+ border: 0;
+ line-height: 1.25em;
+ margin: var(--universal-margin);
+ height: 0.0625rem;
+ background: linear-gradient(to right, transparent, var(--border-color) 20%, var(--border-color) 80%, transparent); }
+
+blockquote {
+ display: block;
+ position: relative;
+ font-style: italic;
+ color: var(--secondary-fore-color);
+ margin: var(--universal-margin);
+ padding: calc(3 * var(--universal-padding));
+ border: 0.0625rem solid var(--secondary-border-color);
+ border-left: 0.375rem solid var(--blockquote-color);
+ border-radius: 0 var(--universal-border-radius) var(--universal-border-radius) 0; }
+ blockquote:before {
+ position: absolute;
+ top: calc(0rem - var(--universal-padding));
+ left: 0;
+ font-family: sans-serif;
+ font-size: 3rem;
+ font-weight: 700;
+ content: "\201c";
+ color: var(--blockquote-color); }
+ blockquote[cite]:after {
+ font-style: normal;
+ font-size: 0.75em;
+ font-weight: 700;
+ content: "\a— " attr(cite);
+ white-space: pre; }
+
+code, kbd, pre, samp {
+ font-family: Menlo, Consolas, monospace;
+ font-size: 0.85em; }
+
+code {
+ background: var(--secondary-back-color);
+ border-radius: var(--universal-border-radius);
+ padding: calc(var(--universal-padding) / 4) calc(var(--universal-padding) / 2); }
+
+kbd {
+ background: var(--fore-color);
+ color: var(--back-color);
+ border-radius: var(--universal-border-radius);
+ padding: calc(var(--universal-padding) / 4) calc(var(--universal-padding) / 2); }
+
+pre {
+ overflow: auto;
+ background: var(--secondary-back-color);
+ padding: calc(1.5 * var(--universal-padding));
+ margin: var(--universal-margin);
+ border: 0.0625rem solid var(--secondary-border-color);
+ border-left: 0.25rem solid var(--pre-color);
+ border-radius: 0 var(--universal-border-radius) var(--universal-border-radius) 0; }
+
+sup, sub, code, kbd {
+ line-height: 0;
+ position: relative;
+ vertical-align: baseline; }
+
+small, sup, sub, figcaption {
+ font-size: 0.75em; }
+
+sup {
+ top: -0.5em; }
+
+sub {
+ bottom: -0.25em; }
+
+figure {
+ margin: var(--universal-margin); }
+
+figcaption {
+ color: var(--secondary-fore-color); }
+
+a {
+ text-decoration: none; }
+ a:link {
+ color: var(--a-link-color); }
+ a:visited {
+ color: var(--a-visited-color); }
+ a:hover, a:focus {
+ text-decoration: underline; }
+
+/*
+ Definitions for the grid system, cards and containers.
+*/
+.container {
+ margin: 0 auto;
+ padding: 0 calc(1.5 * var(--universal-padding)); }
+
+.row {
+ box-sizing: border-box;
+ display: flex;
+ flex: 0 1 auto;
+ flex-flow: row wrap; }
+
+.col-sm,
+[class^='col-sm-'],
+[class^='col-sm-offset-'],
+.row[class*='cols-sm-'] > * {
+ box-sizing: border-box;
+ flex: 0 0 auto;
+ padding: 0 calc(var(--universal-padding) / 2); }
+
+.col-sm,
+.row.cols-sm > * {
+ max-width: 100%;
+ flex-grow: 1;
+ flex-basis: 0; }
+
+.col-sm-1,
+.row.cols-sm-1 > * {
+ max-width: 8.3333333333%;
+ flex-basis: 8.3333333333%; }
+
+.col-sm-offset-0 {
+ margin-left: 0; }
+
+.col-sm-2,
+.row.cols-sm-2 > * {
+ max-width: 16.6666666667%;
+ flex-basis: 16.6666666667%; }
+
+.col-sm-offset-1 {
+ margin-left: 8.3333333333%; }
+
+.col-sm-3,
+.row.cols-sm-3 > * {
+ max-width: 25%;
+ flex-basis: 25%; }
+
+.col-sm-offset-2 {
+ margin-left: 16.6666666667%; }
+
+.col-sm-4,
+.row.cols-sm-4 > * {
+ max-width: 33.3333333333%;
+ flex-basis: 33.3333333333%; }
+
+.col-sm-offset-3 {
+ margin-left: 25%; }
+
+.col-sm-5,
+.row.cols-sm-5 > * {
+ max-width: 41.6666666667%;
+ flex-basis: 41.6666666667%; }
+
+.col-sm-offset-4 {
+ margin-left: 33.3333333333%; }
+
+.col-sm-6,
+.row.cols-sm-6 > * {
+ max-width: 50%;
+ flex-basis: 50%; }
+
+.col-sm-offset-5 {
+ margin-left: 41.6666666667%; }
+
+.col-sm-7,
+.row.cols-sm-7 > * {
+ max-width: 58.3333333333%;
+ flex-basis: 58.3333333333%; }
+
+.col-sm-offset-6 {
+ margin-left: 50%; }
+
+.col-sm-8,
+.row.cols-sm-8 > * {
+ max-width: 66.6666666667%;
+ flex-basis: 66.6666666667%; }
+
+.col-sm-offset-7 {
+ margin-left: 58.3333333333%; }
+
+.col-sm-9,
+.row.cols-sm-9 > * {
+ max-width: 75%;
+ flex-basis: 75%; }
+
+.col-sm-offset-8 {
+ margin-left: 66.6666666667%; }
+
+.col-sm-10,
+.row.cols-sm-10 > * {
+ max-width: 83.3333333333%;
+ flex-basis: 83.3333333333%; }
+
+.col-sm-offset-9 {
+ margin-left: 75%; }
+
+.col-sm-11,
+.row.cols-sm-11 > * {
+ max-width: 91.6666666667%;
+ flex-basis: 91.6666666667%; }
+
+.col-sm-offset-10 {
+ margin-left: 83.3333333333%; }
+
+.col-sm-12,
+.row.cols-sm-12 > * {
+ max-width: 100%;
+ flex-basis: 100%; }
+
+.col-sm-offset-11 {
+ margin-left: 91.6666666667%; }
+
+.col-sm-normal {
+ order: initial; }
+
+.col-sm-first {
+ order: -999; }
+
+.col-sm-last {
+ order: 999; }
+
+@media screen and (min-width: 500px) {
+ .col-md,
+ [class^='col-md-'],
+ [class^='col-md-offset-'],
+ .row[class*='cols-md-'] > * {
+ box-sizing: border-box;
+ flex: 0 0 auto;
+ padding: 0 calc(var(--universal-padding) / 2); }
+
+ .col-md,
+ .row.cols-md > * {
+ max-width: 100%;
+ flex-grow: 1;
+ flex-basis: 0; }
+
+ .col-md-1,
+ .row.cols-md-1 > * {
+ max-width: 8.3333333333%;
+ flex-basis: 8.3333333333%; }
+
+ .col-md-offset-0 {
+ margin-left: 0; }
+
+ .col-md-2,
+ .row.cols-md-2 > * {
+ max-width: 16.6666666667%;
+ flex-basis: 16.6666666667%; }
+
+ .col-md-offset-1 {
+ margin-left: 8.3333333333%; }
+
+ .col-md-3,
+ .row.cols-md-3 > * {
+ max-width: 25%;
+ flex-basis: 25%; }
+
+ .col-md-offset-2 {
+ margin-left: 16.6666666667%; }
+
+ .col-md-4,
+ .row.cols-md-4 > * {
+ max-width: 33.3333333333%;
+ flex-basis: 33.3333333333%; }
+
+ .col-md-offset-3 {
+ margin-left: 25%; }
+
+ .col-md-5,
+ .row.cols-md-5 > * {
+ max-width: 41.6666666667%;
+ flex-basis: 41.6666666667%; }
+
+ .col-md-offset-4 {
+ margin-left: 33.3333333333%; }
+
+ .col-md-6,
+ .row.cols-md-6 > * {
+ max-width: 50%;
+ flex-basis: 50%; }
+
+ .col-md-offset-5 {
+ margin-left: 41.6666666667%; }
+
+ .col-md-7,
+ .row.cols-md-7 > * {
+ max-width: 58.3333333333%;
+ flex-basis: 58.3333333333%; }
+
+ .col-md-offset-6 {
+ margin-left: 50%; }
+
+ .col-md-8,
+ .row.cols-md-8 > * {
+ max-width: 66.6666666667%;
+ flex-basis: 66.6666666667%; }
+
+ .col-md-offset-7 {
+ margin-left: 58.3333333333%; }
+
+ .col-md-9,
+ .row.cols-md-9 > * {
+ max-width: 75%;
+ flex-basis: 75%; }
+
+ .col-md-offset-8 {
+ margin-left: 66.6666666667%; }
+
+ .col-md-10,
+ .row.cols-md-10 > * {
+ max-width: 83.3333333333%;
+ flex-basis: 83.3333333333%; }
+
+ .col-md-offset-9 {
+ margin-left: 75%; }
+
+ .col-md-11,
+ .row.cols-md-11 > * {
+ max-width: 91.6666666667%;
+ flex-basis: 91.6666666667%; }
+
+ .col-md-offset-10 {
+ margin-left: 83.3333333333%; }
+
+ .col-md-12,
+ .row.cols-md-12 > * {
+ max-width: 100%;
+ flex-basis: 100%; }
+
+ .col-md-offset-11 {
+ margin-left: 91.6666666667%; }
+
+ .col-md-normal {
+ order: initial; }
+
+ .col-md-first {
+ order: -999; }
+
+ .col-md-last {
+ order: 999; } }
+@media screen and (min-width: 1280px) {
+ .col-lg,
+ [class^='col-lg-'],
+ [class^='col-lg-offset-'],
+ .row[class*='cols-lg-'] > * {
+ box-sizing: border-box;
+ flex: 0 0 auto;
+ padding: 0 calc(var(--universal-padding) / 2); }
+
+ .col-lg,
+ .row.cols-lg > * {
+ max-width: 100%;
+ flex-grow: 1;
+ flex-basis: 0; }
+
+ .col-lg-1,
+ .row.cols-lg-1 > * {
+ max-width: 8.3333333333%;
+ flex-basis: 8.3333333333%; }
+
+ .col-lg-offset-0 {
+ margin-left: 0; }
+
+ .col-lg-2,
+ .row.cols-lg-2 > * {
+ max-width: 16.6666666667%;
+ flex-basis: 16.6666666667%; }
+
+ .col-lg-offset-1 {
+ margin-left: 8.3333333333%; }
+
+ .col-lg-3,
+ .row.cols-lg-3 > * {
+ max-width: 25%;
+ flex-basis: 25%; }
+
+ .col-lg-offset-2 {
+ margin-left: 16.6666666667%; }
+
+ .col-lg-4,
+ .row.cols-lg-4 > * {
+ max-width: 33.3333333333%;
+ flex-basis: 33.3333333333%; }
+
+ .col-lg-offset-3 {
+ margin-left: 25%; }
+
+ .col-lg-5,
+ .row.cols-lg-5 > * {
+ max-width: 41.6666666667%;
+ flex-basis: 41.6666666667%; }
+
+ .col-lg-offset-4 {
+ margin-left: 33.3333333333%; }
+
+ .col-lg-6,
+ .row.cols-lg-6 > * {
+ max-width: 50%;
+ flex-basis: 50%; }
+
+ .col-lg-offset-5 {
+ margin-left: 41.6666666667%; }
+
+ .col-lg-7,
+ .row.cols-lg-7 > * {
+ max-width: 58.3333333333%;
+ flex-basis: 58.3333333333%; }
+
+ .col-lg-offset-6 {
+ margin-left: 50%; }
+
+ .col-lg-8,
+ .row.cols-lg-8 > * {
+ max-width: 66.6666666667%;
+ flex-basis: 66.6666666667%; }
+
+ .col-lg-offset-7 {
+ margin-left: 58.3333333333%; }
+
+ .col-lg-9,
+ .row.cols-lg-9 > * {
+ max-width: 75%;
+ flex-basis: 75%; }
+
+ .col-lg-offset-8 {
+ margin-left: 66.6666666667%; }
+
+ .col-lg-10,
+ .row.cols-lg-10 > * {
+ max-width: 83.3333333333%;
+ flex-basis: 83.3333333333%; }
+
+ .col-lg-offset-9 {
+ margin-left: 75%; }
+
+ .col-lg-11,
+ .row.cols-lg-11 > * {
+ max-width: 91.6666666667%;
+ flex-basis: 91.6666666667%; }
+
+ .col-lg-offset-10 {
+ margin-left: 83.3333333333%; }
+
+ .col-lg-12,
+ .row.cols-lg-12 > * {
+ max-width: 100%;
+ flex-basis: 100%; }
+
+ .col-lg-offset-11 {
+ margin-left: 91.6666666667%; }
+
+ .col-lg-normal {
+ order: initial; }
+
+ .col-lg-first {
+ order: -999; }
+
+ .col-lg-last {
+ order: 999; } }
+/* Card component CSS variable definitions */
+:root {
+ --card-back-color: #f8f8f8;
+ --card-fore-color: #111;
+ --card-border-color: #ddd; }
+
+.card {
+ display: flex;
+ flex-direction: column;
+ justify-content: space-between;
+ align-self: center;
+ position: relative;
+ width: 100%;
+ background: var(--card-back-color);
+ color: var(--card-fore-color);
+ border: 0.0625rem solid var(--card-border-color);
+ border-radius: var(--universal-border-radius);
+ margin: var(--universal-margin);
+ overflow: hidden; }
+ @media screen and (min-width: 320px) {
+ .card {
+ max-width: 320px; } }
+ .card > .sectione {
+ background: var(--card-back-color);
+ color: var(--card-fore-color);
+ box-sizing: border-box;
+ margin: 0;
+ border: 0;
+ border-radius: 0;
+ border-bottom: 0.0625rem solid var(--card-border-color);
+ padding: var(--universal-padding);
+ width: 100%; }
+ .card > .sectione.media {
+ height: 200px;
+ padding: 0;
+ -o-object-fit: cover;
+ object-fit: cover; }
+ .card > .sectione:last-child {
+ border-bottom: 0; }
+
+/*
+ Custom elements for card elements.
+*/
+@media screen and (min-width: 240px) {
+ .card.small {
+ max-width: 240px; } }
+@media screen and (min-width: 480px) {
+ .card.large {
+ max-width: 480px; } }
+.card.fluid {
+ max-width: 100%;
+ width: auto; }
+
+.card.warning {
+/* --card-back-color: #ffca28; */
+ --card-back-color: #e5b8b7;
+ --card-border-color: #e8b825; }
+
+.card.error {
+ --card-back-color: #b71c1c;
+ --card-fore-color: #f8f8f8;
+ --card-border-color: #a71a1a; }
+
+.card > .sectione.dark {
+ --card-back-color: #e0e0e0; }
+
+.card > .sectione.double-padded {
+ padding: calc(1.5 * var(--universal-padding)); }
+
+/*
+ Definitions for forms and input elements.
+*/
+/* Input_control module CSS variable definitions */
+:root {
+ --form-back-color: #f0f0f0;
+ --form-fore-color: #111;
+ --form-border-color: #ddd;
+ --input-back-color: #f8f8f8;
+ --input-fore-color: #111;
+ --input-border-color: #ddd;
+ --input-focus-color: #0288d1;
+ --input-invalid-color: #d32f2f;
+ --button-back-color: #e2e2e2;
+ --button-hover-back-color: #dcdcdc;
+ --button-fore-color: #212121;
+ --button-border-color: transparent;
+ --button-hover-border-color: transparent;
+ --button-group-border-color: rgba(124, 124, 124, 0.54); }
+
+form {
+ background: var(--form-back-color);
+ color: var(--form-fore-color);
+ border: 0.0625rem solid var(--form-border-color);
+ border-radius: var(--universal-border-radius);
+ margin: var(--universal-margin);
+ padding: calc(2 * var(--universal-padding)) var(--universal-padding); }
+
+fieldset {
+ border: 0.0625rem solid var(--form-border-color);
+ border-radius: var(--universal-border-radius);
+ margin: calc(var(--universal-margin) / 4);
+ padding: var(--universal-padding); }
+
+legend {
+ box-sizing: border-box;
+ display: table;
+ max-width: 100%;
+ white-space: normal;
+ font-weight: 700;
+ padding: calc(var(--universal-padding) / 2); }
+
+label {
+ padding: calc(var(--universal-padding) / 2) var(--universal-padding); }
+
+.input-group {
+ display: inline-block; }
+ .input-group.fluid {
+ display: flex;
+ align-items: center;
+ justify-content: center; }
+ .input-group.fluid > input {
+ max-width: 100%;
+ flex-grow: 1;
+ flex-basis: 0px; }
+ @media screen and (max-width: 499px) {
+ .input-group.fluid {
+ align-items: stretch;
+ flex-direction: column; } }
+ .input-group.vertical {
+ display: flex;
+ align-items: stretch;
+ flex-direction: column; }
+ .input-group.vertical > input {
+ max-width: 100%;
+ flex-grow: 1;
+ flex-basis: 0px; }
+
+[type="number"]::-webkit-inner-spin-button, [type="number"]::-webkit-outer-spin-button {
+ height: auto; }
+
+[type="search"] {
+ -webkit-appearance: textfield;
+ outline-offset: -2px; }
+
+[type="search"]::-webkit-search-cancel-button,
+[type="search"]::-webkit-search-decoration {
+ -webkit-appearance: none; }
+
+input:not([type]), [type="text"], [type="email"], [type="number"], [type="search"],
+[type="password"], [type="url"], [type="tel"], [type="checkbox"], [type="radio"], textarea, select {
+ box-sizing: border-box;
+ background: var(--input-back-color);
+ color: var(--input-fore-color);
+ border: 0.0625rem solid var(--input-border-color);
+ border-radius: var(--universal-border-radius);
+ margin: calc(var(--universal-margin) / 2);
+ padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); }
+
+input:not([type="button"]):not([type="submit"]):not([type="reset"]):hover, input:not([type="button"]):not([type="submit"]):not([type="reset"]):focus, textarea:hover, textarea:focus, select:hover, select:focus {
+ border-color: var(--input-focus-color);
+ box-shadow: none; }
+input:not([type="button"]):not([type="submit"]):not([type="reset"]):invalid, input:not([type="button"]):not([type="submit"]):not([type="reset"]):focus:invalid, textarea:invalid, textarea:focus:invalid, select:invalid, select:focus:invalid {
+ border-color: var(--input-invalid-color);
+ box-shadow: none; }
+input:not([type="button"]):not([type="submit"]):not([type="reset"])[readonly], textarea[readonly], select[readonly] {
+ background: var(--secondary-back-color); }
+
+select {
+ max-width: 100%; }
+
+option {
+ overflow: hidden;
+ text-overflow: ellipsis; }
+
+[type="checkbox"], [type="radio"] {
+ -webkit-appearance: none;
+ -moz-appearance: none;
+ appearance: none;
+ position: relative;
+ height: calc(1rem + var(--universal-padding) / 2);
+ width: calc(1rem + var(--universal-padding) / 2);
+ vertical-align: text-bottom;
+ padding: 0;
+ flex-basis: calc(1rem + var(--universal-padding) / 2) !important;
+ flex-grow: 0 !important; }
+ [type="checkbox"]:checked:before, [type="radio"]:checked:before {
+ position: absolute; }
+
+[type="checkbox"]:checked:before {
+ content: '\2713';
+ font-family: sans-serif;
+ font-size: calc(1rem + var(--universal-padding) / 2);
+ top: calc(0rem - var(--universal-padding));
+ left: calc(var(--universal-padding) / 4); }
+
+[type="radio"] {
+ border-radius: 100%; }
+ [type="radio"]:checked:before {
+ border-radius: 100%;
+ content: '';
+ top: calc(0.0625rem + var(--universal-padding) / 2);
+ left: calc(0.0625rem + var(--universal-padding) / 2);
+ background: var(--input-fore-color);
+ width: 0.5rem;
+ height: 0.5rem; }
+
+:placeholder-shown {
+ color: var(--input-fore-color); }
+
+::-ms-placeholder {
+ color: var(--input-fore-color);
+ opacity: 0.54; }
+
+button::-moz-focus-inner, [type="button"]::-moz-focus-inner, [type="reset"]::-moz-focus-inner, [type="submit"]::-moz-focus-inner {
+ border-style: none;
+ padding: 0; }
+
+button, html [type="button"], [type="reset"], [type="submit"] {
+ -webkit-appearance: button; }
+
+button {
+ overflow: visible;
+ text-transform: none; }
+
+button, [type="button"], [type="submit"], [type="reset"],
+a.button, label.button, .button,
+a[role="button"], label[role="button"], [role="button"] {
+ display: inline-block;
+ background: var(--button-back-color);
+ color: var(--button-fore-color);
+ border: 0.0625rem solid var(--button-border-color);
+ border-radius: var(--universal-border-radius);
+ padding: var(--universal-padding) calc(1.5 * var(--universal-padding));
+ margin: var(--universal-margin);
+ text-decoration: none;
+ cursor: pointer;
+ transition: background 0.3s; }
+ button:hover, button:focus, [type="button"]:hover, [type="button"]:focus, [type="submit"]:hover, [type="submit"]:focus, [type="reset"]:hover, [type="reset"]:focus,
+ a.button:hover,
+ a.button:focus, label.button:hover, label.button:focus, .button:hover, .button:focus,
+ a[role="button"]:hover,
+ a[role="button"]:focus, label[role="button"]:hover, label[role="button"]:focus, [role="button"]:hover, [role="button"]:focus {
+ background: var(--button-hover-back-color);
+ border-color: var(--button-hover-border-color); }
+
+input:disabled, input[disabled], textarea:disabled, textarea[disabled], select:disabled, select[disabled], button:disabled, button[disabled], .button:disabled, .button[disabled], [role="button"]:disabled, [role="button"][disabled] {
+ cursor: not-allowed;
+ opacity: 0.75; }
+
+.button-group {
+ display: flex;
+ border: 0.0625rem solid var(--button-group-border-color);
+ border-radius: var(--universal-border-radius);
+ margin: var(--universal-margin); }
+ .button-group > button, .button-group [type="button"], .button-group > [type="submit"], .button-group > [type="reset"], .button-group > .button, .button-group > [role="button"] {
+ margin: 0;
+ max-width: 100%;
+ flex: 1 1 auto;
+ text-align: center;
+ border: 0;
+ border-radius: 0;
+ box-shadow: none; }
+ .button-group > :not(:first-child) {
+ border-left: 0.0625rem solid var(--button-group-border-color); }
+ @media screen and (max-width: 499px) {
+ .button-group {
+ flex-direction: column; }
+ .button-group > :not(:first-child) {
+ border: 0;
+ border-top: 0.0625rem solid var(--button-group-border-color); } }
+
+/*
+ Custom elements for forms and input elements.
+*/
+button.primary, [type="button"].primary, [type="submit"].primary, [type="reset"].primary, .button.primary, [role="button"].primary {
+ --button-back-color: #1976d2;
+ --button-fore-color: #f8f8f8; }
+ button.primary:hover, button.primary:focus, [type="button"].primary:hover, [type="button"].primary:focus, [type="submit"].primary:hover, [type="submit"].primary:focus, [type="reset"].primary:hover, [type="reset"].primary:focus, .button.primary:hover, .button.primary:focus, [role="button"].primary:hover, [role="button"].primary:focus {
+ --button-hover-back-color: #1565c0; }
+
+button.secondary, [type="button"].secondary, [type="submit"].secondary, [type="reset"].secondary, .button.secondary, [role="button"].secondary {
+ --button-back-color: #d32f2f;
+ --button-fore-color: #f8f8f8; }
+ button.secondary:hover, button.secondary:focus, [type="button"].secondary:hover, [type="button"].secondary:focus, [type="submit"].secondary:hover, [type="submit"].secondary:focus, [type="reset"].secondary:hover, [type="reset"].secondary:focus, .button.secondary:hover, .button.secondary:focus, [role="button"].secondary:hover, [role="button"].secondary:focus {
+ --button-hover-back-color: #c62828; }
+
+button.tertiary, [type="button"].tertiary, [type="submit"].tertiary, [type="reset"].tertiary, .button.tertiary, [role="button"].tertiary {
+ --button-back-color: #308732;
+ --button-fore-color: #f8f8f8; }
+ button.tertiary:hover, button.tertiary:focus, [type="button"].tertiary:hover, [type="button"].tertiary:focus, [type="submit"].tertiary:hover, [type="submit"].tertiary:focus, [type="reset"].tertiary:hover, [type="reset"].tertiary:focus, .button.tertiary:hover, .button.tertiary:focus, [role="button"].tertiary:hover, [role="button"].tertiary:focus {
+ --button-hover-back-color: #277529; }
+
+button.inverse, [type="button"].inverse, [type="submit"].inverse, [type="reset"].inverse, .button.inverse, [role="button"].inverse {
+ --button-back-color: #212121;
+ --button-fore-color: #f8f8f8; }
+ button.inverse:hover, button.inverse:focus, [type="button"].inverse:hover, [type="button"].inverse:focus, [type="submit"].inverse:hover, [type="submit"].inverse:focus, [type="reset"].inverse:hover, [type="reset"].inverse:focus, .button.inverse:hover, .button.inverse:focus, [role="button"].inverse:hover, [role="button"].inverse:focus {
+ --button-hover-back-color: #111; }
+
+button.small, [type="button"].small, [type="submit"].small, [type="reset"].small, .button.small, [role="button"].small {
+ padding: calc(0.5 * var(--universal-padding)) calc(0.75 * var(--universal-padding));
+ margin: var(--universal-margin); }
+
+button.large, [type="button"].large, [type="submit"].large, [type="reset"].large, .button.large, [role="button"].large {
+ padding: calc(1.5 * var(--universal-padding)) calc(2 * var(--universal-padding));
+ margin: var(--universal-margin); }
+
+/*
+ Definitions for navigation elements.
+*/
+/* Navigation module CSS variable definitions */
+:root {
+ --header-back-color: #f8f8f8;
+ --header-hover-back-color: #f0f0f0;
+ --header-fore-color: #444;
+ --header-border-color: #ddd;
+ --nav-back-color: #f8f8f8;
+ --nav-hover-back-color: #f0f0f0;
+ --nav-fore-color: #444;
+ --nav-border-color: #ddd;
+ --nav-link-color: #0277bd;
+ --footer-fore-color: #444;
+ --footer-back-color: #f8f8f8;
+ --footer-border-color: #ddd;
+ --footer-link-color: #0277bd;
+ --drawer-back-color: #f8f8f8;
+ --drawer-hover-back-color: #f0f0f0;
+ --drawer-border-color: #ddd;
+ --drawer-close-color: #444; }
+
+header {
+ height: 3.1875rem;
+ background: var(--header-back-color);
+ color: var(--header-fore-color);
+ border-bottom: 0.0625rem solid var(--header-border-color);
+ padding: calc(var(--universal-padding) / 4) 0;
+ white-space: nowrap;
+ overflow-x: auto;
+ overflow-y: hidden; }
+ header.row {
+ box-sizing: content-box; }
+ header .logo {
+ color: var(--header-fore-color);
+ font-size: 1.75rem;
+ padding: var(--universal-padding) calc(2 * var(--universal-padding));
+ text-decoration: none; }
+ header button, header [type="button"], header .button, header [role="button"] {
+ box-sizing: border-box;
+ position: relative;
+ top: calc(0rem - var(--universal-padding) / 4);
+ height: calc(3.1875rem + var(--universal-padding) / 2);
+ background: var(--header-back-color);
+ line-height: calc(3.1875rem - var(--universal-padding) * 1.5);
+ text-align: center;
+ color: var(--header-fore-color);
+ border: 0;
+ border-radius: 0;
+ margin: 0;
+ text-transform: uppercase; }
+ header button:hover, header button:focus, header [type="button"]:hover, header [type="button"]:focus, header .button:hover, header .button:focus, header [role="button"]:hover, header [role="button"]:focus {
+ background: var(--header-hover-back-color); }
+
+nav {
+ background: var(--nav-back-color);
+ color: var(--nav-fore-color);
+ border: 0.0625rem solid var(--nav-border-color);
+ border-radius: var(--universal-border-radius);
+ margin: var(--universal-margin); }
+ nav * {
+ padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); }
+ nav a, nav a:visited {
+ display: block;
+ color: var(--nav-link-color);
+ border-radius: var(--universal-border-radius);
+ transition: background 0.3s; }
+ nav a:hover, nav a:focus, nav a:visited:hover, nav a:visited:focus {
+ text-decoration: none;
+ background: var(--nav-hover-back-color); }
+ nav .sublink-1 {
+ position: relative;
+ margin-left: calc(2 * var(--universal-padding)); }
+ nav .sublink-1:before {
+ position: absolute;
+ left: calc(var(--universal-padding) - 1 * var(--universal-padding));
+ top: -0.0625rem;
+ content: '';
+ height: 100%;
+ border: 0.0625rem solid var(--nav-border-color);
+ border-left: 0; }
+ nav .sublink-2 {
+ position: relative;
+ margin-left: calc(4 * var(--universal-padding)); }
+ nav .sublink-2:before {
+ position: absolute;
+ left: calc(var(--universal-padding) - 3 * var(--universal-padding));
+ top: -0.0625rem;
+ content: '';
+ height: 100%;
+ border: 0.0625rem solid var(--nav-border-color);
+ border-left: 0; }
+
+footer {
+ background: var(--footer-back-color);
+ color: var(--footer-fore-color);
+ border-top: 0.0625rem solid var(--footer-border-color);
+ padding: calc(2 * var(--universal-padding)) var(--universal-padding);
+ font-size: 0.875rem; }
+ footer a, footer a:visited {
+ color: var(--footer-link-color); }
+
+header.sticky {
+ position: -webkit-sticky;
+ position: sticky;
+ z-index: 1101;
+ top: 0; }
+
+footer.sticky {
+ position: -webkit-sticky;
+ position: sticky;
+ z-index: 1101;
+ bottom: 0; }
+
+.drawer-toggle:before {
+ display: inline-block;
+ position: relative;
+ vertical-align: bottom;
+ content: '\00a0\2261\00a0';
+ font-family: sans-serif;
+ font-size: 1.5em; }
+@media screen and (min-width: 500px) {
+ .drawer-toggle:not(.persistent) {
+ display: none; } }
+
+[type="checkbox"].drawer {
+ height: 1px;
+ width: 1px;
+ margin: -1px;
+ overflow: hidden;
+ position: absolute;
+ clip: rect(0 0 0 0);
+ -webkit-clip-path: inset(100%);
+ clip-path: inset(100%); }
+ [type="checkbox"].drawer + * {
+ display: block;
+ box-sizing: border-box;
+ position: fixed;
+ top: 0;
+ width: 320px;
+ height: 100vh;
+ overflow-y: auto;
+ background: var(--drawer-back-color);
+ border: 0.0625rem solid var(--drawer-border-color);
+ border-radius: 0;
+ margin: 0;
+ z-index: 1110;
+ right: -320px;
+ transition: right 0.3s; }
+ [type="checkbox"].drawer + * .drawer-close {
+ position: absolute;
+ top: var(--universal-margin);
+ right: var(--universal-margin);
+ z-index: 1111;
+ width: 2rem;
+ height: 2rem;
+ border-radius: var(--universal-border-radius);
+ padding: var(--universal-padding);
+ margin: 0;
+ cursor: pointer;
+ transition: background 0.3s; }
+ [type="checkbox"].drawer + * .drawer-close:before {
+ display: block;
+ content: '\00D7';
+ color: var(--drawer-close-color);
+ position: relative;
+ font-family: sans-serif;
+ font-size: 2rem;
+ line-height: 1;
+ text-align: center; }
+ [type="checkbox"].drawer + * .drawer-close:hover, [type="checkbox"].drawer + * .drawer-close:focus {
+ background: var(--drawer-hover-back-color); }
+ @media screen and (max-width: 320px) {
+ [type="checkbox"].drawer + * {
+ width: 100%; } }
+ [type="checkbox"].drawer:checked + * {
+ right: 0; }
+ @media screen and (min-width: 500px) {
+ [type="checkbox"].drawer:not(.persistent) + * {
+ position: static;
+ height: 100%;
+ z-index: 1100; }
+ [type="checkbox"].drawer:not(.persistent) + * .drawer-close {
+ display: none; } }
+
+/*
+ Definitions for the responsive table component.
+*/
+/* Table module CSS variable definitions. */
+:root {
+ --table-border-color: #aaa;
+ --table-border-separator-color: #666;
+ --table-head-back-color: #e6e6e6;
+ --table-head-fore-color: #111;
+ --table-body-back-color: #f8f8f8;
+ --table-body-fore-color: #111;
+ --table-body-alt-back-color: #eee; }
+
+table {
+ border-collapse: separate;
+ border-spacing: 0;
+ : margin: calc(1.5 * var(--universal-margin)) var(--universal-margin);
+ display: flex;
+ flex: 0 1 auto;
+ flex-flow: row wrap;
+ padding: var(--universal-padding);
+ padding-top: 0;
+ margin: calc(1.5 * var(--universal-margin)) var(--universal-margin); }
+ table caption {
+ font-size: 1.25 * rem;
+ margin: calc(2 * var(--universal-margin)) 0;
+ max-width: 100%;
+ flex: 0 0 100%;
+ text-align: left;}
+ table thead, table tbody {
+ display: flex;
+ flex-flow: row wrap;
+ border: 0.0625rem solid var(--table-border-color); }
+ table thead {
+ z-index: 999;
+ border-radius: var(--universal-border-radius) var(--universal-border-radius) 0 0;
+ border-bottom: 0.0625rem solid var(--table-border-separator-color); }
+ table tbody {
+ border-top: 0;
+ margin-top: calc(0 - var(--universal-margin));
+ border-radius: 0 0 var(--universal-border-radius) var(--universal-border-radius); }
+ table tr {
+ display: flex;
+ padding: 0; }
+ table th, table td {
+ padding: calc(0.5 * var(--universal-padding));
+ font-size: 0.9rem; }
+ table th {
+ text-align: left;
+ background: var(--table-head-back-color);
+ color: var(--table-head-fore-color); }
+ table td {
+ background: var(--table-body-back-color);
+ color: var(--table-body-fore-color);
+ border-top: 0.0625rem solid var(--table-border-color); }
+
+table:not(.horizontal) {
+ overflow: auto;
+ max-height: 850px; }
+ table:not(.horizontal) thead, table:not(.horizontal) tbody {
+ max-width: 100%;
+ flex: 0 0 100%; }
+ table:not(.horizontal) tr {
+ flex-flow: row wrap;
+ flex: 0 0 100%; }
+ table:not(.horizontal) th, table:not(.horizontal) td {
+ flex: 1 0 0%;
+ overflow: hidden;
+ text-overflow: ellipsis; }
+ table:not(.horizontal) thead {
+ position: sticky;
+ top: 0; }
+ table:not(.horizontal) tbody tr:first-child td {
+ border-top: 0; }
+
+table.horizontal {
+ border: 0; }
+ table.horizontal thead, table.horizontal tbody {
+ border: 0;
+ flex-flow: row nowrap; }
+ table.horizontal tbody {
+ overflow: auto;
+ justify-content: space-between;
+ flex: 1 0 0;
+ margin-left: calc( 4 * var(--universal-margin));
+ padding-bottom: calc(var(--universal-padding) / 4); }
+ table.horizontal tr {
+ flex-direction: column;
+ flex: 1 0 auto; }
+ table.horizontal th, table.horizontal td {
+ width: 100%;
+ border: 0;
+ border-bottom: 0.0625rem solid var(--table-border-color); }
+ table.horizontal th:not(:first-child), table.horizontal td:not(:first-child) {
+ border-top: 0; }
+ table.horizontal th {
+ text-align: right;
+ border-left: 0.0625rem solid var(--table-border-color);
+ border-right: 0.0625rem solid var(--table-border-separator-color); }
+ table.horizontal thead tr:first-child {
+ padding-left: 0; }
+ table.horizontal th:first-child, table.horizontal td:first-child {
+ border-top: 0.0625rem solid var(--table-border-color); }
+ table.horizontal tbody tr:last-child td {
+ border-right: 0.0625rem solid var(--table-border-color); }
+ table.horizontal tbody tr:last-child td:first-child {
+ border-top-right-radius: 0.25rem; }
+ table.horizontal tbody tr:last-child td:last-child {
+ border-bottom-right-radius: 0.25rem; }
+ table.horizontal thead tr:first-child th:first-child {
+ border-top-left-radius: 0.25rem; }
+ table.horizontal thead tr:first-child th:last-child {
+ border-bottom-left-radius: 0.25rem; }
+
+@media screen and (max-width: 499px) {
+ table, table.horizontal {
+ border-collapse: collapse;
+ border: 0;
+ width: 100%;
+ display: table; }
+ table thead, table th, table.horizontal thead, table.horizontal th {
+ border: 0;
+ height: 1px;
+ width: 1px;
+ margin: -1px;
+ overflow: hidden;
+ padding: 0;
+ position: absolute;
+ clip: rect(0 0 0 0);
+ -webkit-clip-path: inset(100%);
+ clip-path: inset(100%); }
+ table tbody, table.horizontal tbody {
+ border: 0;
+ display: table-row-group; }
+ table tr, table.horizontal tr {
+ display: block;
+ border: 0.0625rem solid var(--table-border-color);
+ border-radius: var(--universal-border-radius);
+ background: #fafafa;
+ padding: var(--universal-padding);
+ margin: var(--universal-margin);
+ margin-bottom: calc(2 * var(--universal-margin)); }
+ table th, table td, table.horizontal th, table.horizontal td {
+ width: auto; }
+ table td, table.horizontal td {
+ display: block;
+ border: 0;
+ text-align: right; }
+ table td:before, table.horizontal td:before {
+ content: attr(data-label);
+ float: left;
+ font-weight: 600; }
+ table th:first-child, table td:first-child, table.horizontal th:first-child, table.horizontal td:first-child {
+ border-top: 0; }
+ table tbody tr:last-child td, table.horizontal tbody tr:last-child td {
+ border-right: 0; } }
+:root {
+ --table-body-alt-back-color: #eee; }
+
+table tr:nth-of-type(2n) > td {
+ background: var(--table-body-alt-back-color); }
+
+@media screen and (max-width: 500px) {
+ table tr:nth-of-type(2n) {
+ background: var(--table-body-alt-back-color); } }
+:root {
+ --table-body-hover-back-color: #90caf9; }
+
+table.hoverable tr:hover, table.hoverable tr:hover > td, table.hoverable tr:focus, table.hoverable tr:focus > td {
+ background: var(--table-body-hover-back-color); }
+
+@media screen and (max-width: 500px) {
+ table.hoverable tr:hover, table.hoverable tr:hover > td, table.hoverable tr:focus, table.hoverable tr:focus > td {
+ background: var(--table-body-hover-back-color); } }
+/*
+ Definitions for contextual background elements, toasts and tooltips.
+*/
+/* Contextual module CSS variable definitions */
+:root {
+ --mark-back-color: #0277bd;
+ --mark-fore-color: #fafafa; }
+
+mark {
+ background: var(--mark-back-color);
+ color: var(--mark-fore-color);
+ font-size: 0.95em;
+ line-height: 1em;
+ border-radius: var(--universal-border-radius);
+ padding: calc(var(--universal-padding) / 4) calc(var(--universal-padding) / 2); }
+ mark.inline-block {
+ display: inline-block;
+ font-size: 1em;
+ line-height: 1.5;
+ padding: calc(var(--universal-padding) / 2) var(--universal-padding); }
+
+:root {
+ --toast-back-color: #424242;
+ --toast-fore-color: #fafafa; }
+
+.toast {
+ position: fixed;
+ bottom: calc(var(--universal-margin) * 3);
+ left: 50%;
+ transform: translate(-50%, -50%);
+ z-index: 1111;
+ color: var(--toast-fore-color);
+ background: var(--toast-back-color);
+ border-radius: calc(var(--universal-border-radius) * 16);
+ padding: var(--universal-padding) calc(var(--universal-padding) * 3); }
+
+:root {
+ --tooltip-back-color: #212121;
+ --tooltip-fore-color: #fafafa; }
+
+.tooltip {
+ position: relative;
+ display: inline-block; }
+ .tooltip:before, .tooltip:after {
+ position: absolute;
+ opacity: 0;
+ clip: rect(0 0 0 0);
+ -webkit-clip-path: inset(100%);
+ clip-path: inset(100%);
+ transition: all 0.3s;
+ z-index: 1010;
+ left: 50%; }
+ .tooltip:not(.bottom):before, .tooltip:not(.bottom):after {
+ bottom: 75%; }
+ .tooltip.bottom:before, .tooltip.bottom:after {
+ top: 75%; }
+ .tooltip:hover:before, .tooltip:hover:after, .tooltip:focus:before, .tooltip:focus:after {
+ opacity: 1;
+ clip: auto;
+ -webkit-clip-path: inset(0%);
+ clip-path: inset(0%); }
+ .tooltip:before {
+ content: '';
+ background: transparent;
+ border: var(--universal-margin) solid transparent;
+ left: calc(50% - var(--universal-margin)); }
+ .tooltip:not(.bottom):before {
+ border-top-color: #212121; }
+ .tooltip.bottom:before {
+ border-bottom-color: #212121; }
+ .tooltip:after {
+ content: attr(aria-label);
+ color: var(--tooltip-fore-color);
+ background: var(--tooltip-back-color);
+ border-radius: var(--universal-border-radius);
+ padding: var(--universal-padding);
+ white-space: nowrap;
+ transform: translateX(-50%); }
+ .tooltip:not(.bottom):after {
+ margin-bottom: calc(2 * var(--universal-margin)); }
+ .tooltip.bottom:after {
+ margin-top: calc(2 * var(--universal-margin)); }
+
+:root {
+ --modal-overlay-color: rgba(0, 0, 0, 0.45);
+ --modal-close-color: #444;
+ --modal-close-hover-color: #f0f0f0; }
+
+[type="checkbox"].modal {
+ height: 1px;
+ width: 1px;
+ margin: -1px;
+ overflow: hidden;
+ position: absolute;
+ clip: rect(0 0 0 0);
+ -webkit-clip-path: inset(100%);
+ clip-path: inset(100%); }
+ [type="checkbox"].modal + div {
+ position: fixed;
+ top: 0;
+ left: 0;
+ display: none;
+ width: 100vw;
+ height: 100vh;
+ background: var(--modal-overlay-color); }
+ [type="checkbox"].modal + div .card {
+ margin: 0 auto;
+ max-height: 50vh;
+ overflow: auto; }
+ [type="checkbox"].modal + div .card .modal-close {
+ position: absolute;
+ top: 0;
+ right: 0;
+ width: 1.75rem;
+ height: 1.75rem;
+ border-radius: var(--universal-border-radius);
+ padding: var(--universal-padding);
+ margin: 0;
+ cursor: pointer;
+ transition: background 0.3s; }
+ [type="checkbox"].modal + div .card .modal-close:before {
+ display: block;
+ content: '\00D7';
+ color: var(--modal-close-color);
+ position: relative;
+ font-family: sans-serif;
+ font-size: 1.75rem;
+ line-height: 1;
+ text-align: center; }
+ [type="checkbox"].modal + div .card .modal-close:hover, [type="checkbox"].modal + div .card .modal-close:focus {
+ background: var(--modal-close-hover-color); }
+ [type="checkbox"].modal:checked + div {
+ display: flex;
+ flex: 0 1 auto;
+ z-index: 1200; }
+ [type="checkbox"].modal:checked + div .card .modal-close {
+ z-index: 1211; }
+
+:root {
+ --collapse-label-back-color: #e8e8e8;
+ --collapse-label-fore-color: #212121;
+ --collapse-label-hover-back-color: #f0f0f0;
+ --collapse-selected-label-back-color: #ececec;
+ --collapse-border-color: #ddd;
+ --collapse-content-back-color: #fafafa;
+ --collapse-selected-label-border-color: #0277bd; }
+
+.collapse {
+ width: calc(100% - 2 * var(--universal-margin));
+ opacity: 1;
+ display: flex;
+ flex-direction: column;
+ margin: var(--universal-margin);
+ border-radius: var(--universal-border-radius); }
+ .collapse > [type="radio"], .collapse > [type="checkbox"] {
+ height: 1px;
+ width: 1px;
+ margin: -1px;
+ overflow: hidden;
+ position: absolute;
+ clip: rect(0 0 0 0);
+ -webkit-clip-path: inset(100%);
+ clip-path: inset(100%); }
+ .collapse > label {
+ flex-grow: 1;
+ display: inline-block;
+ height: 1.5rem;
+ cursor: pointer;
+ transition: background 0.3s;
+ color: var(--collapse-label-fore-color);
+ background: var(--collapse-label-back-color);
+ border: 0.0625rem solid var(--collapse-border-color);
+ padding: calc(1.5 * var(--universal-padding)); }
+ .collapse > label:hover, .collapse > label:focus {
+ background: var(--collapse-label-hover-back-color); }
+ .collapse > label + div {
+ flex-basis: auto;
+ height: 1px;
+ width: 1px;
+ margin: -1px;
+ overflow: hidden;
+ position: absolute;
+ clip: rect(0 0 0 0);
+ -webkit-clip-path: inset(100%);
+ clip-path: inset(100%);
+ transition: max-height 0.3s;
+ max-height: 1px; }
+ .collapse > :checked + label {
+ background: var(--collapse-selected-label-back-color);
+ border-bottom-color: var(--collapse-selected-label-border-color); }
+ .collapse > :checked + label + div {
+ box-sizing: border-box;
+ position: relative;
+ width: 100%;
+ height: auto;
+ overflow: auto;
+ margin: 0;
+ background: var(--collapse-content-back-color);
+ border: 0.0625rem solid var(--collapse-border-color);
+ border-top: 0;
+ padding: var(--universal-padding);
+ clip: auto;
+ -webkit-clip-path: inset(0%);
+ clip-path: inset(0%);
+ max-height: 850px; }
+ .collapse > label:not(:first-of-type) {
+ border-top: 0; }
+ .collapse > label:first-of-type {
+ border-radius: var(--universal-border-radius) var(--universal-border-radius) 0 0; }
+ .collapse > label:last-of-type:not(:first-of-type) {
+ border-radius: 0 0 var(--universal-border-radius) var(--universal-border-radius); }
+ .collapse > label:last-of-type:first-of-type {
+ border-radius: var(--universal-border-radius); }
+ .collapse > :checked:last-of-type:not(:first-of-type) + label {
+ border-radius: 0; }
+ .collapse > :checked:last-of-type + label + div {
+ border-radius: 0 0 var(--universal-border-radius) var(--universal-border-radius); }
+
+/*
+ Custom elements for contextual background elements, toasts and tooltips.
+*/
+mark.secondary {
+ --mark-back-color: #d32f2f; }
+
+mark.tertiary {
+ --mark-back-color: #308732; }
+
+mark.tag {
+ padding: calc(var(--universal-padding)/2) var(--universal-padding);
+ border-radius: 1em; }
+
+/*
+ Definitions for progress elements and spinners.
+*/
+/* Progess module CSS variable definitions */
+:root {
+ --progress-back-color: #ddd;
+ --progress-fore-color: #555; }
+
+progress {
+ display: block;
+ vertical-align: baseline;
+ -webkit-appearance: none;
+ -moz-appearance: none;
+ appearance: none;
+ height: 0.75rem;
+ width: calc(100% - 2 * var(--universal-margin));
+ margin: var(--universal-margin);
+ border: 0;
+ border-radius: calc(2 * var(--universal-border-radius));
+ background: var(--progress-back-color);
+ color: var(--progress-fore-color); }
+ progress::-webkit-progress-value {
+ background: var(--progress-fore-color);
+ border-top-left-radius: calc(2 * var(--universal-border-radius));
+ border-bottom-left-radius: calc(2 * var(--universal-border-radius)); }
+ progress::-webkit-progress-bar {
+ background: var(--progress-back-color); }
+ progress::-moz-progress-bar {
+ background: var(--progress-fore-color);
+ border-top-left-radius: calc(2 * var(--universal-border-radius));
+ border-bottom-left-radius: calc(2 * var(--universal-border-radius)); }
+ progress[value="1000"]::-webkit-progress-value {
+ border-radius: calc(2 * var(--universal-border-radius)); }
+ progress[value="1000"]::-moz-progress-bar {
+ border-radius: calc(2 * var(--universal-border-radius)); }
+ progress.inline {
+ display: inline-block;
+ vertical-align: middle;
+ width: 60%; }
+
+:root {
+ --spinner-back-color: #ddd;
+ --spinner-fore-color: #555; }
+
+@keyframes spinner-donut-anim {
+ 0% {
+ transform: rotate(0deg); }
+ 100% {
+ transform: rotate(360deg); } }
+.spinner {
+ display: inline-block;
+ margin: var(--universal-margin);
+ border: 0.25rem solid var(--spinner-back-color);
+ border-left: 0.25rem solid var(--spinner-fore-color);
+ border-radius: 50%;
+ width: 1.25rem;
+ height: 1.25rem;
+ animation: spinner-donut-anim 1.2s linear infinite; }
+
+/*
+ Custom elements for progress bars and spinners.
+*/
+progress.primary {
+ --progress-fore-color: #1976d2; }
+
+progress.secondary {
+ --progress-fore-color: #d32f2f; }
+
+progress.tertiary {
+ --progress-fore-color: #308732; }
+
+.spinner.primary {
+ --spinner-fore-color: #1976d2; }
+
+.spinner.secondary {
+ --spinner-fore-color: #d32f2f; }
+
+.spinner.tertiary {
+ --spinner-fore-color: #308732; }
+
+/*
+ Definitions for icons - powered by Feather (https://feathericons.com/).
+*/
+span[class^='icon-'] {
+ display: inline-block;
+ height: 1em;
+ width: 1em;
+ vertical-align: -0.125em;
+ background-size: contain;
+ margin: 0 calc(var(--universal-margin) / 4); }
+ span[class^='icon-'].secondary {
+ -webkit-filter: invert(25%);
+ filter: invert(25%); }
+ span[class^='icon-'].inverse {
+ -webkit-filter: invert(100%);
+ filter: invert(100%); }
+
+span.icon-alert {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='8' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='16' x2='12' y2='16'%3E%3C/line%3E%3C/svg%3E"); }
+span.icon-bookmark {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M19 21l-7-5-7 5V5a2 2 0 0 1 2-2h10a2 2 0 0 1 2 2z'%3E%3C/path%3E%3C/svg%3E"); }
+span.icon-calendar {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='4' width='18' height='18' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='16' y1='2' x2='16' y2='6'%3E%3C/line%3E%3Cline x1='8' y1='2' x2='8' y2='6'%3E%3C/line%3E%3Cline x1='3' y1='10' x2='21' y2='10'%3E%3C/line%3E%3C/svg%3E"); }
+span.icon-credit {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='1' y='4' width='22' height='16' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='1' y1='10' x2='23' y2='10'%3E%3C/line%3E%3C/svg%3E"); }
+span.icon-edit {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M20 14.66V20a2 2 0 0 1-2 2H4a2 2 0 0 1-2-2V6a2 2 0 0 1 2-2h5.34'%3E%3C/path%3E%3Cpolygon points='18 2 22 6 12 16 8 16 8 12 18 2'%3E%3C/polygon%3E%3C/svg%3E"); }
+span.icon-link {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M18 13v6a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2V8a2 2 0 0 1 2-2h6'%3E%3C/path%3E%3Cpolyline points='15 3 21 3 21 9'%3E%3C/polyline%3E%3Cline x1='10' y1='14' x2='21' y2='3'%3E%3C/line%3E%3C/svg%3E"); }
+span.icon-help {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M9.09 9a3 3 0 0 1 5.83 1c0 2-3 3-3 3'%3E%3C/path%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='17' x2='12' y2='17'%3E%3C/line%3E%3C/svg%3E"); }
+span.icon-home {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M3 9l9-7 9 7v11a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2z'%3E%3C/path%3E%3Cpolyline points='9 22 9 12 15 12 15 22'%3E%3C/polyline%3E%3C/svg%3E"); }
+span.icon-info {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='16' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='8' x2='12' y2='8'%3E%3C/line%3E%3C/svg%3E"); }
+span.icon-lock {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='11' width='18' height='11' rx='2' ry='2'%3E%3C/rect%3E%3Cpath d='M7 11V7a5 5 0 0 1 10 0v4'%3E%3C/path%3E%3C/svg%3E"); }
+span.icon-mail {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M4 4h16c1.1 0 2 .9 2 2v12c0 1.1-.9 2-2 2H4c-1.1 0-2-.9-2-2V6c0-1.1.9-2 2-2z'%3E%3C/path%3E%3Cpolyline points='22,6 12,13 2,6'%3E%3C/polyline%3E%3C/svg%3E"); }
+span.icon-location {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M21 10c0 7-9 13-9 13s-9-6-9-13a9 9 0 0 1 18 0z'%3E%3C/path%3E%3Ccircle cx='12' cy='10' r='3'%3E%3C/circle%3E%3C/svg%3E"); }
+span.icon-phone {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M22 16.92v3a2 2 0 0 1-2.18 2 19.79 19.79 0 0 1-8.63-3.07 19.5 19.5 0 0 1-6-6 19.79 19.79 0 0 1-3.07-8.67A2 2 0 0 1 4.11 2h3a2 2 0 0 1 2 1.72 12.84 12.84 0 0 0 .7 2.81 2 2 0 0 1-.45 2.11L8.09 9.91a16 16 0 0 0 6 6l1.27-1.27a2 2 0 0 1 2.11-.45 12.84 12.84 0 0 0 2.81.7A2 2 0 0 1 22 16.92z'%3E%3C/path%3E%3C/svg%3E"); }
+span.icon-rss {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M4 11a9 9 0 0 1 9 9'%3E%3C/path%3E%3Cpath d='M4 4a16 16 0 0 1 16 16'%3E%3C/path%3E%3Ccircle cx='5' cy='19' r='1'%3E%3C/circle%3E%3C/svg%3E"); }
+span.icon-search {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='11' cy='11' r='8'%3E%3C/circle%3E%3Cline x1='21' y1='21' x2='16.65' y2='16.65'%3E%3C/line%3E%3C/svg%3E"); }
+span.icon-settings {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='3'%3E%3C/circle%3E%3Cpath d='M19.4 15a1.65 1.65 0 0 0 .33 1.82l.06.06a2 2 0 0 1 0 2.83 2 2 0 0 1-2.83 0l-.06-.06a1.65 1.65 0 0 0-1.82-.33 1.65 1.65 0 0 0-1 1.51V21a2 2 0 0 1-2 2 2 2 0 0 1-2-2v-.09A1.65 1.65 0 0 0 9 19.4a1.65 1.65 0 0 0-1.82.33l-.06.06a2 2 0 0 1-2.83 0 2 2 0 0 1 0-2.83l.06-.06a1.65 1.65 0 0 0 .33-1.82 1.65 1.65 0 0 0-1.51-1H3a2 2 0 0 1-2-2 2 2 0 0 1 2-2h.09A1.65 1.65 0 0 0 4.6 9a1.65 1.65 0 0 0-.33-1.82l-.06-.06a2 2 0 0 1 0-2.83 2 2 0 0 1 2.83 0l.06.06a1.65 1.65 0 0 0 1.82.33H9a1.65 1.65 0 0 0 1-1.51V3a2 2 0 0 1 2-2 2 2 0 0 1 2 2v.09a1.65 1.65 0 0 0 1 1.51 1.65 1.65 0 0 0 1.82-.33l.06-.06a2 2 0 0 1 2.83 0 2 2 0 0 1 0 2.83l-.06.06a1.65 1.65 0 0 0-.33 1.82V9a1.65 1.65 0 0 0 1.51 1H21a2 2 0 0 1 2 2 2 2 0 0 1-2 2h-.09a1.65 1.65 0 0 0-1.51 1z'%3E%3C/path%3E%3C/svg%3E"); }
+span.icon-share {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='18' cy='5' r='3'%3E%3C/circle%3E%3Ccircle cx='6' cy='12' r='3'%3E%3C/circle%3E%3Ccircle cx='18' cy='19' r='3'%3E%3C/circle%3E%3Cline x1='8.59' y1='13.51' x2='15.42' y2='17.49'%3E%3C/line%3E%3Cline x1='15.41' y1='6.51' x2='8.59' y2='10.49'%3E%3C/line%3E%3C/svg%3E"); }
+span.icon-cart {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='9' cy='21' r='1'%3E%3C/circle%3E%3Ccircle cx='20' cy='21' r='1'%3E%3C/circle%3E%3Cpath d='M1 1h4l2.68 13.39a2 2 0 0 0 2 1.61h9.72a2 2 0 0 0 2-1.61L23 6H6'%3E%3C/path%3E%3C/svg%3E"); }
+span.icon-upload {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M21 15v4a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2v-4'%3E%3C/path%3E%3Cpolyline points='17 8 12 3 7 8'%3E%3C/polyline%3E%3Cline x1='12' y1='3' x2='12' y2='15'%3E%3C/line%3E%3C/svg%3E"); }
+span.icon-user {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M20 21v-2a4 4 0 0 0-4-4H8a4 4 0 0 0-4 4v2'%3E%3C/path%3E%3Ccircle cx='12' cy='7' r='4'%3E%3C/circle%3E%3C/svg%3E"); }
+
+/*
+ Definitions for utilities and helper classes.
+*/
+/* Utility module CSS variable definitions */
+:root {
+ --generic-border-color: rgba(0, 0, 0, 0.3);
+ --generic-box-shadow: 0 0.25rem 0.25rem 0 rgba(0, 0, 0, 0.125), 0 0.125rem 0.125rem -0.125rem rgba(0, 0, 0, 0.25); }
+
+.hidden {
+ display: none !important; }
+
+.visually-hidden {
+ position: absolute !important;
+ width: 1px !important;
+ height: 1px !important;
+ margin: -1px !important;
+ border: 0 !important;
+ padding: 0 !important;
+ clip: rect(0 0 0 0) !important;
+ -webkit-clip-path: inset(100%) !important;
+ clip-path: inset(100%) !important;
+ overflow: hidden !important; }
+
+.bordered {
+ border: 0.0625rem solid var(--generic-border-color) !important; }
+
+.rounded {
+ border-radius: var(--universal-border-radius) !important; }
+
+.circular {
+ border-radius: 50% !important; }
+
+.shadowed {
+ box-shadow: var(--generic-box-shadow) !important; }
+
+.responsive-margin {
+ margin: calc(var(--universal-margin) / 4) !important; }
+ @media screen and (min-width: 500px) {
+ .responsive-margin {
+ margin: calc(var(--universal-margin) / 2) !important; } }
+ @media screen and (min-width: 1280px) {
+ .responsive-margin {
+ margin: var(--universal-margin) !important; } }
+
+.responsive-padding {
+ padding: calc(var(--universal-padding) / 4) !important; }
+ @media screen and (min-width: 500px) {
+ .responsive-padding {
+ padding: calc(var(--universal-padding) / 2) !important; } }
+ @media screen and (min-width: 1280px) {
+ .responsive-padding {
+ padding: var(--universal-padding) !important; } }
+
+@media screen and (max-width: 499px) {
+ .hidden-sm {
+ display: none !important; } }
+@media screen and (min-width: 500px) and (max-width: 1279px) {
+ .hidden-md {
+ display: none !important; } }
+@media screen and (min-width: 1280px) {
+ .hidden-lg {
+ display: none !important; } }
+@media screen and (max-width: 499px) {
+ .visually-hidden-sm {
+ position: absolute !important;
+ width: 1px !important;
+ height: 1px !important;
+ margin: -1px !important;
+ border: 0 !important;
+ padding: 0 !important;
+ clip: rect(0 0 0 0) !important;
+ -webkit-clip-path: inset(100%) !important;
+ clip-path: inset(100%) !important;
+ overflow: hidden !important; } }
+@media screen and (min-width: 500px) and (max-width: 1279px) {
+ .visually-hidden-md {
+ position: absolute !important;
+ width: 1px !important;
+ height: 1px !important;
+ margin: -1px !important;
+ border: 0 !important;
+ padding: 0 !important;
+ clip: rect(0 0 0 0) !important;
+ -webkit-clip-path: inset(100%) !important;
+ clip-path: inset(100%) !important;
+ overflow: hidden !important; } }
+@media screen and (min-width: 1280px) {
+ .visually-hidden-lg {
+ position: absolute !important;
+ width: 1px !important;
+ height: 1px !important;
+ margin: -1px !important;
+ border: 0 !important;
+ padding: 0 !important;
+ clip: rect(0 0 0 0) !important;
+ -webkit-clip-path: inset(100%) !important;
+ clip-path: inset(100%) !important;
+ overflow: hidden !important; } }
+
+/*# sourceMappingURL=mini-default.css.map */
diff --git a/system/Drivers/STM32C0xx_HAL_Driver/_htmresc/mini-st_2020.css b/system/Drivers/STM32C0xx_HAL_Driver/_htmresc/mini-st_2020.css
new file mode 100644
index 0000000000..db8b406aa4
--- /dev/null
+++ b/system/Drivers/STM32C0xx_HAL_Driver/_htmresc/mini-st_2020.css
@@ -0,0 +1,1711 @@
+@charset "UTF-8";
+/*
+ Flavor name: Custom (mini-custom)
+ Generated online - https://minicss.org/flavors
+ mini.css version: v3.0.1
+*/
+/*
+ Browsers resets and base typography.
+*/
+/* Core module CSS variable definitions */
+:root {
+ --fore-color: #03234b;
+ --secondary-fore-color: #03234b;
+ --back-color: #ffffff;
+ --secondary-back-color: #ffffff;
+ --blockquote-color: #e6007e;
+ --pre-color: #e6007e;
+ --border-color: #3cb4e6;
+ --secondary-border-color: #3cb4e6;
+ --heading-ratio: 1.2;
+ --universal-margin: 0.5rem;
+ --universal-padding: 0.25rem;
+ --universal-border-radius: 0.075rem;
+ --background-margin: 1.5%;
+ --a-link-color: #3cb4e6;
+ --a-visited-color: #8c0078; }
+
+html {
+ font-size: 13.5px; }
+
+a, b, del, em, i, ins, q, span, strong, u {
+ font-size: 1em; }
+
+html, * {
+ font-family: -apple-system, BlinkMacSystemFont, Helvetica, arial, sans-serif;
+ line-height: 1.25;
+ -webkit-text-size-adjust: 100%; }
+
+* {
+ font-size: 1rem; }
+
+body {
+ margin: 0;
+ color: var(--fore-color);
+ @background: var(--back-color);
+ background: var(--back-color) linear-gradient(#ffd200, #ffd200) repeat-y left top;
+ background-size: var(--background-margin);
+ }
+
+details {
+ display: block; }
+
+summary {
+ display: list-item; }
+
+abbr[title] {
+ border-bottom: none;
+ text-decoration: underline dotted; }
+
+input {
+ overflow: visible; }
+
+img {
+ max-width: 100%;
+ height: auto; }
+
+h1, h2, h3, h4, h5, h6 {
+ line-height: 1.25;
+ margin: calc(1.5 * var(--universal-margin)) var(--universal-margin);
+ font-weight: 400; }
+ h1 small, h2 small, h3 small, h4 small, h5 small, h6 small {
+ color: var(--secondary-fore-color);
+ display: block;
+ margin-top: -0.25rem; }
+
+h1 {
+ font-size: calc(1rem * var(--heading-ratio) * var(--heading-ratio) * var(--heading-ratio)); }
+
+h2 {
+ font-size: calc(1rem * var(--heading-ratio) * var(--heading-ratio) );
+ border-style: none none solid none ;
+ border-width: thin;
+ border-color: var(--border-color); }
+h3 {
+ font-size: calc(1rem * var(--heading-ratio) ); }
+
+h4 {
+ font-size: calc(1rem * var(--heading-ratio)); }
+
+h5 {
+ font-size: 1rem; }
+
+h6 {
+ font-size: calc(1rem / var(--heading-ratio)); }
+
+p {
+ margin: var(--universal-margin); }
+
+ol, ul {
+ margin: var(--universal-margin);
+ padding-left: calc(3 * var(--universal-margin)); }
+
+b, strong {
+ font-weight: 700; }
+
+hr {
+ box-sizing: content-box;
+ border: 0;
+ line-height: 1.25em;
+ margin: var(--universal-margin);
+ height: 0.0714285714rem;
+ background: linear-gradient(to right, transparent, var(--border-color) 20%, var(--border-color) 80%, transparent); }
+
+blockquote {
+ display: block;
+ position: relative;
+ font-style: italic;
+ color: var(--secondary-fore-color);
+ margin: var(--universal-margin);
+ padding: calc(3 * var(--universal-padding));
+ border: 0.0714285714rem solid var(--secondary-border-color);
+ border-left: 0.3rem solid var(--blockquote-color);
+ border-radius: 0 var(--universal-border-radius) var(--universal-border-radius) 0; }
+ blockquote:before {
+ position: absolute;
+ top: calc(0rem - var(--universal-padding));
+ left: 0;
+ font-family: sans-serif;
+ font-size: 2rem;
+ font-weight: 800;
+ content: "\201c";
+ color: var(--blockquote-color); }
+ blockquote[cite]:after {
+ font-style: normal;
+ font-size: 0.75em;
+ font-weight: 700;
+ content: "\a— " attr(cite);
+ white-space: pre; }
+
+code, kbd, pre, samp {
+ font-family: Menlo, Consolas, monospace;
+ font-size: 0.85em; }
+
+code {
+ background: var(--secondary-back-color);
+ border-radius: var(--universal-border-radius);
+ padding: calc(var(--universal-padding) / 4) calc(var(--universal-padding) / 2); }
+
+kbd {
+ background: var(--fore-color);
+ color: var(--back-color);
+ border-radius: var(--universal-border-radius);
+ padding: calc(var(--universal-padding) / 4) calc(var(--universal-padding) / 2); }
+
+pre {
+ overflow: auto;
+ background: var(--secondary-back-color);
+ padding: calc(1.5 * var(--universal-padding));
+ margin: var(--universal-margin);
+ border: 0.0714285714rem solid var(--secondary-border-color);
+ border-left: 0.2857142857rem solid var(--pre-color);
+ border-radius: 0 var(--universal-border-radius) var(--universal-border-radius) 0; }
+
+sup, sub, code, kbd {
+ line-height: 0;
+ position: relative;
+ vertical-align: baseline; }
+
+small, sup, sub, figcaption {
+ font-size: 0.75em; }
+
+sup {
+ top: -0.5em; }
+
+sub {
+ bottom: -0.25em; }
+
+figure {
+ margin: var(--universal-margin); }
+
+figcaption {
+ color: var(--secondary-fore-color); }
+
+a {
+ text-decoration: none; }
+ a:link {
+ color: var(--a-link-color); }
+ a:visited {
+ color: var(--a-visited-color); }
+ a:hover, a:focus {
+ text-decoration: underline; }
+
+/*
+ Definitions for the grid system, cards and containers.
+*/
+.container {
+ margin: 0 auto;
+ padding: 0 calc(1.5 * var(--universal-padding)); }
+
+.row {
+ box-sizing: border-box;
+ display: flex;
+ flex: 0 1 auto;
+ flex-flow: row wrap;
+ margin: 0 0 0 var(--background-margin); }
+
+.col-sm,
+[class^='col-sm-'],
+[class^='col-sm-offset-'],
+.row[class*='cols-sm-'] > * {
+ box-sizing: border-box;
+ flex: 0 0 auto;
+ padding: 0 calc(var(--universal-padding) / 2); }
+
+.col-sm,
+.row.cols-sm > * {
+ max-width: 100%;
+ flex-grow: 1;
+ flex-basis: 0; }
+
+.col-sm-1,
+.row.cols-sm-1 > * {
+ max-width: 8.3333333333%;
+ flex-basis: 8.3333333333%; }
+
+.col-sm-offset-0 {
+ margin-left: 0; }
+
+.col-sm-2,
+.row.cols-sm-2 > * {
+ max-width: 16.6666666667%;
+ flex-basis: 16.6666666667%; }
+
+.col-sm-offset-1 {
+ margin-left: 8.3333333333%; }
+
+.col-sm-3,
+.row.cols-sm-3 > * {
+ max-width: 25%;
+ flex-basis: 25%; }
+
+.col-sm-offset-2 {
+ margin-left: 16.6666666667%; }
+
+.col-sm-4,
+.row.cols-sm-4 > * {
+ max-width: 33.3333333333%;
+ flex-basis: 33.3333333333%; }
+
+.col-sm-offset-3 {
+ margin-left: 25%; }
+
+.col-sm-5,
+.row.cols-sm-5 > * {
+ max-width: 41.6666666667%;
+ flex-basis: 41.6666666667%; }
+
+.col-sm-offset-4 {
+ margin-left: 33.3333333333%; }
+
+.col-sm-6,
+.row.cols-sm-6 > * {
+ max-width: 50%;
+ flex-basis: 50%; }
+
+.col-sm-offset-5 {
+ margin-left: 41.6666666667%; }
+
+.col-sm-7,
+.row.cols-sm-7 > * {
+ max-width: 58.3333333333%;
+ flex-basis: 58.3333333333%; }
+
+.col-sm-offset-6 {
+ margin-left: 50%; }
+
+.col-sm-8,
+.row.cols-sm-8 > * {
+ max-width: 66.6666666667%;
+ flex-basis: 66.6666666667%; }
+
+.col-sm-offset-7 {
+ margin-left: 58.3333333333%; }
+
+.col-sm-9,
+.row.cols-sm-9 > * {
+ max-width: 75%;
+ flex-basis: 75%; }
+
+.col-sm-offset-8 {
+ margin-left: 66.6666666667%; }
+
+.col-sm-10,
+.row.cols-sm-10 > * {
+ max-width: 83.3333333333%;
+ flex-basis: 83.3333333333%; }
+
+.col-sm-offset-9 {
+ margin-left: 75%; }
+
+.col-sm-11,
+.row.cols-sm-11 > * {
+ max-width: 91.6666666667%;
+ flex-basis: 91.6666666667%; }
+
+.col-sm-offset-10 {
+ margin-left: 83.3333333333%; }
+
+.col-sm-12,
+.row.cols-sm-12 > * {
+ max-width: 100%;
+ flex-basis: 100%; }
+
+.col-sm-offset-11 {
+ margin-left: 91.6666666667%; }
+
+.col-sm-normal {
+ order: initial; }
+
+.col-sm-first {
+ order: -999; }
+
+.col-sm-last {
+ order: 999; }
+
+@media screen and (min-width: 500px) {
+ .col-md,
+ [class^='col-md-'],
+ [class^='col-md-offset-'],
+ .row[class*='cols-md-'] > * {
+ box-sizing: border-box;
+ flex: 0 0 auto;
+ padding: 0 calc(var(--universal-padding) / 2); }
+
+ .col-md,
+ .row.cols-md > * {
+ max-width: 100%;
+ flex-grow: 1;
+ flex-basis: 0; }
+
+ .col-md-1,
+ .row.cols-md-1 > * {
+ max-width: 8.3333333333%;
+ flex-basis: 8.3333333333%; }
+
+ .col-md-offset-0 {
+ margin-left: 0; }
+
+ .col-md-2,
+ .row.cols-md-2 > * {
+ max-width: 16.6666666667%;
+ flex-basis: 16.6666666667%; }
+
+ .col-md-offset-1 {
+ margin-left: 8.3333333333%; }
+
+ .col-md-3,
+ .row.cols-md-3 > * {
+ max-width: 25%;
+ flex-basis: 25%; }
+
+ .col-md-offset-2 {
+ margin-left: 16.6666666667%; }
+
+ .col-md-4,
+ .row.cols-md-4 > * {
+ max-width: 33.3333333333%;
+ flex-basis: 33.3333333333%; }
+
+ .col-md-offset-3 {
+ margin-left: 25%; }
+
+ .col-md-5,
+ .row.cols-md-5 > * {
+ max-width: 41.6666666667%;
+ flex-basis: 41.6666666667%; }
+
+ .col-md-offset-4 {
+ margin-left: 33.3333333333%; }
+
+ .col-md-6,
+ .row.cols-md-6 > * {
+ max-width: 50%;
+ flex-basis: 50%; }
+
+ .col-md-offset-5 {
+ margin-left: 41.6666666667%; }
+
+ .col-md-7,
+ .row.cols-md-7 > * {
+ max-width: 58.3333333333%;
+ flex-basis: 58.3333333333%; }
+
+ .col-md-offset-6 {
+ margin-left: 50%; }
+
+ .col-md-8,
+ .row.cols-md-8 > * {
+ max-width: 66.6666666667%;
+ flex-basis: 66.6666666667%; }
+
+ .col-md-offset-7 {
+ margin-left: 58.3333333333%; }
+
+ .col-md-9,
+ .row.cols-md-9 > * {
+ max-width: 75%;
+ flex-basis: 75%; }
+
+ .col-md-offset-8 {
+ margin-left: 66.6666666667%; }
+
+ .col-md-10,
+ .row.cols-md-10 > * {
+ max-width: 83.3333333333%;
+ flex-basis: 83.3333333333%; }
+
+ .col-md-offset-9 {
+ margin-left: 75%; }
+
+ .col-md-11,
+ .row.cols-md-11 > * {
+ max-width: 91.6666666667%;
+ flex-basis: 91.6666666667%; }
+
+ .col-md-offset-10 {
+ margin-left: 83.3333333333%; }
+
+ .col-md-12,
+ .row.cols-md-12 > * {
+ max-width: 100%;
+ flex-basis: 100%; }
+
+ .col-md-offset-11 {
+ margin-left: 91.6666666667%; }
+
+ .col-md-normal {
+ order: initial; }
+
+ .col-md-first {
+ order: -999; }
+
+ .col-md-last {
+ order: 999; } }
+@media screen and (min-width: 1280px) {
+ .col-lg,
+ [class^='col-lg-'],
+ [class^='col-lg-offset-'],
+ .row[class*='cols-lg-'] > * {
+ box-sizing: border-box;
+ flex: 0 0 auto;
+ padding: 0 calc(var(--universal-padding) / 2); }
+
+ .col-lg,
+ .row.cols-lg > * {
+ max-width: 100%;
+ flex-grow: 1;
+ flex-basis: 0; }
+
+ .col-lg-1,
+ .row.cols-lg-1 > * {
+ max-width: 8.3333333333%;
+ flex-basis: 8.3333333333%; }
+
+ .col-lg-offset-0 {
+ margin-left: 0; }
+
+ .col-lg-2,
+ .row.cols-lg-2 > * {
+ max-width: 16.6666666667%;
+ flex-basis: 16.6666666667%; }
+
+ .col-lg-offset-1 {
+ margin-left: 8.3333333333%; }
+
+ .col-lg-3,
+ .row.cols-lg-3 > * {
+ max-width: 25%;
+ flex-basis: 25%; }
+
+ .col-lg-offset-2 {
+ margin-left: 16.6666666667%; }
+
+ .col-lg-4,
+ .row.cols-lg-4 > * {
+ max-width: 33.3333333333%;
+ flex-basis: 33.3333333333%; }
+
+ .col-lg-offset-3 {
+ margin-left: 25%; }
+
+ .col-lg-5,
+ .row.cols-lg-5 > * {
+ max-width: 41.6666666667%;
+ flex-basis: 41.6666666667%; }
+
+ .col-lg-offset-4 {
+ margin-left: 33.3333333333%; }
+
+ .col-lg-6,
+ .row.cols-lg-6 > * {
+ max-width: 50%;
+ flex-basis: 50%; }
+
+ .col-lg-offset-5 {
+ margin-left: 41.6666666667%; }
+
+ .col-lg-7,
+ .row.cols-lg-7 > * {
+ max-width: 58.3333333333%;
+ flex-basis: 58.3333333333%; }
+
+ .col-lg-offset-6 {
+ margin-left: 50%; }
+
+ .col-lg-8,
+ .row.cols-lg-8 > * {
+ max-width: 66.6666666667%;
+ flex-basis: 66.6666666667%; }
+
+ .col-lg-offset-7 {
+ margin-left: 58.3333333333%; }
+
+ .col-lg-9,
+ .row.cols-lg-9 > * {
+ max-width: 75%;
+ flex-basis: 75%; }
+
+ .col-lg-offset-8 {
+ margin-left: 66.6666666667%; }
+
+ .col-lg-10,
+ .row.cols-lg-10 > * {
+ max-width: 83.3333333333%;
+ flex-basis: 83.3333333333%; }
+
+ .col-lg-offset-9 {
+ margin-left: 75%; }
+
+ .col-lg-11,
+ .row.cols-lg-11 > * {
+ max-width: 91.6666666667%;
+ flex-basis: 91.6666666667%; }
+
+ .col-lg-offset-10 {
+ margin-left: 83.3333333333%; }
+
+ .col-lg-12,
+ .row.cols-lg-12 > * {
+ max-width: 100%;
+ flex-basis: 100%; }
+
+ .col-lg-offset-11 {
+ margin-left: 91.6666666667%; }
+
+ .col-lg-normal {
+ order: initial; }
+
+ .col-lg-first {
+ order: -999; }
+
+ .col-lg-last {
+ order: 999; } }
+/* Card component CSS variable definitions */
+:root {
+ --card-back-color: #3cb4e6;
+ --card-fore-color: #03234b;
+ --card-border-color: #03234b; }
+
+.card {
+ display: flex;
+ flex-direction: column;
+ justify-content: space-between;
+ align-self: center;
+ position: relative;
+ width: 100%;
+ background: var(--card-back-color);
+ color: var(--card-fore-color);
+ border: 0.0714285714rem solid var(--card-border-color);
+ border-radius: var(--universal-border-radius);
+ margin: var(--universal-margin);
+ overflow: hidden; }
+ @media screen and (min-width: 320px) {
+ .card {
+ max-width: 320px; } }
+ .card > .sectione {
+ background: var(--card-back-color);
+ color: var(--card-fore-color);
+ box-sizing: border-box;
+ margin: 0;
+ border: 0;
+ border-radius: 0;
+ border-bottom: 0.0714285714rem solid var(--card-border-color);
+ padding: var(--universal-padding);
+ width: 100%; }
+ .card > .sectione.media {
+ height: 200px;
+ padding: 0;
+ -o-object-fit: cover;
+ object-fit: cover; }
+ .card > .sectione:last-child {
+ border-bottom: 0; }
+
+/*
+ Custom elements for card elements.
+*/
+@media screen and (min-width: 240px) {
+ .card.small {
+ max-width: 240px; } }
+@media screen and (min-width: 480px) {
+ .card.large {
+ max-width: 480px; } }
+.card.fluid {
+ max-width: 100%;
+ width: auto; }
+
+.card.warning {
+ --card-back-color: #e5b8b7;
+ --card-fore-color: #3b234b;
+ --card-border-color: #8c0078; }
+
+.card.error {
+ --card-back-color: #464650;
+ --card-fore-color: #ffffff;
+ --card-border-color: #8c0078; }
+
+.card > .sectione.dark {
+ --card-back-color: #3b234b;
+ --card-fore-color: #ffffff; }
+
+.card > .sectione.double-padded {
+ padding: calc(1.5 * var(--universal-padding)); }
+
+/*
+ Definitions for forms and input elements.
+*/
+/* Input_control module CSS variable definitions */
+:root {
+ --form-back-color: #ffe97f;
+ --form-fore-color: #03234b;
+ --form-border-color: #3cb4e6;
+ --input-back-color: #ffffff;
+ --input-fore-color: #03234b;
+ --input-border-color: #3cb4e6;
+ --input-focus-color: #0288d1;
+ --input-invalid-color: #d32f2f;
+ --button-back-color: #e2e2e2;
+ --button-hover-back-color: #dcdcdc;
+ --button-fore-color: #212121;
+ --button-border-color: transparent;
+ --button-hover-border-color: transparent;
+ --button-group-border-color: rgba(124, 124, 124, 0.54); }
+
+form {
+ background: var(--form-back-color);
+ color: var(--form-fore-color);
+ border: 0.0714285714rem solid var(--form-border-color);
+ border-radius: var(--universal-border-radius);
+ margin: var(--universal-margin);
+ padding: calc(2 * var(--universal-padding)) var(--universal-padding); }
+
+fieldset {
+ border: 0.0714285714rem solid var(--form-border-color);
+ border-radius: var(--universal-border-radius);
+ margin: calc(var(--universal-margin) / 4);
+ padding: var(--universal-padding); }
+
+legend {
+ box-sizing: border-box;
+ display: table;
+ max-width: 100%;
+ white-space: normal;
+ font-weight: 500;
+ padding: calc(var(--universal-padding) / 2); }
+
+label {
+ padding: calc(var(--universal-padding) / 2) var(--universal-padding); }
+
+.input-group {
+ display: inline-block; }
+ .input-group.fluid {
+ display: flex;
+ align-items: center;
+ justify-content: center; }
+ .input-group.fluid > input {
+ max-width: 100%;
+ flex-grow: 1;
+ flex-basis: 0px; }
+ @media screen and (max-width: 499px) {
+ .input-group.fluid {
+ align-items: stretch;
+ flex-direction: column; } }
+ .input-group.vertical {
+ display: flex;
+ align-items: stretch;
+ flex-direction: column; }
+ .input-group.vertical > input {
+ max-width: 100%;
+ flex-grow: 1;
+ flex-basis: 0px; }
+
+[type="number"]::-webkit-inner-spin-button, [type="number"]::-webkit-outer-spin-button {
+ height: auto; }
+
+[type="search"] {
+ -webkit-appearance: textfield;
+ outline-offset: -2px; }
+
+[type="search"]::-webkit-search-cancel-button,
+[type="search"]::-webkit-search-decoration {
+ -webkit-appearance: none; }
+
+input:not([type]), [type="text"], [type="email"], [type="number"], [type="search"],
+[type="password"], [type="url"], [type="tel"], [type="checkbox"], [type="radio"], textarea, select {
+ box-sizing: border-box;
+ background: var(--input-back-color);
+ color: var(--input-fore-color);
+ border: 0.0714285714rem solid var(--input-border-color);
+ border-radius: var(--universal-border-radius);
+ margin: calc(var(--universal-margin) / 2);
+ padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); }
+
+input:not([type="button"]):not([type="submit"]):not([type="reset"]):hover, input:not([type="button"]):not([type="submit"]):not([type="reset"]):focus, textarea:hover, textarea:focus, select:hover, select:focus {
+ border-color: var(--input-focus-color);
+ box-shadow: none; }
+input:not([type="button"]):not([type="submit"]):not([type="reset"]):invalid, input:not([type="button"]):not([type="submit"]):not([type="reset"]):focus:invalid, textarea:invalid, textarea:focus:invalid, select:invalid, select:focus:invalid {
+ border-color: var(--input-invalid-color);
+ box-shadow: none; }
+input:not([type="button"]):not([type="submit"]):not([type="reset"])[readonly], textarea[readonly], select[readonly] {
+ background: var(--secondary-back-color); }
+
+select {
+ max-width: 100%; }
+
+option {
+ overflow: hidden;
+ text-overflow: ellipsis; }
+
+[type="checkbox"], [type="radio"] {
+ -webkit-appearance: none;
+ -moz-appearance: none;
+ appearance: none;
+ position: relative;
+ height: calc(1rem + var(--universal-padding) / 2);
+ width: calc(1rem + var(--universal-padding) / 2);
+ vertical-align: text-bottom;
+ padding: 0;
+ flex-basis: calc(1rem + var(--universal-padding) / 2) !important;
+ flex-grow: 0 !important; }
+ [type="checkbox"]:checked:before, [type="radio"]:checked:before {
+ position: absolute; }
+
+[type="checkbox"]:checked:before {
+ content: '\2713';
+ font-family: sans-serif;
+ font-size: calc(1rem + var(--universal-padding) / 2);
+ top: calc(0rem - var(--universal-padding));
+ left: calc(var(--universal-padding) / 4); }
+
+[type="radio"] {
+ border-radius: 100%; }
+ [type="radio"]:checked:before {
+ border-radius: 100%;
+ content: '';
+ top: calc(0.0714285714rem + var(--universal-padding) / 2);
+ left: calc(0.0714285714rem + var(--universal-padding) / 2);
+ background: var(--input-fore-color);
+ width: 0.5rem;
+ height: 0.5rem; }
+
+:placeholder-shown {
+ color: var(--input-fore-color); }
+
+::-ms-placeholder {
+ color: var(--input-fore-color);
+ opacity: 0.54; }
+
+button::-moz-focus-inner, [type="button"]::-moz-focus-inner, [type="reset"]::-moz-focus-inner, [type="submit"]::-moz-focus-inner {
+ border-style: none;
+ padding: 0; }
+
+button, html [type="button"], [type="reset"], [type="submit"] {
+ -webkit-appearance: button; }
+
+button {
+ overflow: visible;
+ text-transform: none; }
+
+button, [type="button"], [type="submit"], [type="reset"],
+a.button, label.button, .button,
+a[role="button"], label[role="button"], [role="button"] {
+ display: inline-block;
+ background: var(--button-back-color);
+ color: var(--button-fore-color);
+ border: 0.0714285714rem solid var(--button-border-color);
+ border-radius: var(--universal-border-radius);
+ padding: var(--universal-padding) calc(1.5 * var(--universal-padding));
+ margin: var(--universal-margin);
+ text-decoration: none;
+ cursor: pointer;
+ transition: background 0.3s; }
+ button:hover, button:focus, [type="button"]:hover, [type="button"]:focus, [type="submit"]:hover, [type="submit"]:focus, [type="reset"]:hover, [type="reset"]:focus,
+ a.button:hover,
+ a.button:focus, label.button:hover, label.button:focus, .button:hover, .button:focus,
+ a[role="button"]:hover,
+ a[role="button"]:focus, label[role="button"]:hover, label[role="button"]:focus, [role="button"]:hover, [role="button"]:focus {
+ background: var(--button-hover-back-color);
+ border-color: var(--button-hover-border-color); }
+
+input:disabled, input[disabled], textarea:disabled, textarea[disabled], select:disabled, select[disabled], button:disabled, button[disabled], .button:disabled, .button[disabled], [role="button"]:disabled, [role="button"][disabled] {
+ cursor: not-allowed;
+ opacity: 0.75; }
+
+.button-group {
+ display: flex;
+ border: 0.0714285714rem solid var(--button-group-border-color);
+ border-radius: var(--universal-border-radius);
+ margin: var(--universal-margin); }
+ .button-group > button, .button-group [type="button"], .button-group > [type="submit"], .button-group > [type="reset"], .button-group > .button, .button-group > [role="button"] {
+ margin: 0;
+ max-width: 100%;
+ flex: 1 1 auto;
+ text-align: center;
+ border: 0;
+ border-radius: 0;
+ box-shadow: none; }
+ .button-group > :not(:first-child) {
+ border-left: 0.0714285714rem solid var(--button-group-border-color); }
+ @media screen and (max-width: 499px) {
+ .button-group {
+ flex-direction: column; }
+ .button-group > :not(:first-child) {
+ border: 0;
+ border-top: 0.0714285714rem solid var(--button-group-border-color); } }
+
+/*
+ Custom elements for forms and input elements.
+*/
+button.primary, [type="button"].primary, [type="submit"].primary, [type="reset"].primary, .button.primary, [role="button"].primary {
+ --button-back-color: #1976d2;
+ --button-fore-color: #f8f8f8; }
+ button.primary:hover, button.primary:focus, [type="button"].primary:hover, [type="button"].primary:focus, [type="submit"].primary:hover, [type="submit"].primary:focus, [type="reset"].primary:hover, [type="reset"].primary:focus, .button.primary:hover, .button.primary:focus, [role="button"].primary:hover, [role="button"].primary:focus {
+ --button-hover-back-color: #1565c0; }
+
+button.secondary, [type="button"].secondary, [type="submit"].secondary, [type="reset"].secondary, .button.secondary, [role="button"].secondary {
+ --button-back-color: #d32f2f;
+ --button-fore-color: #f8f8f8; }
+ button.secondary:hover, button.secondary:focus, [type="button"].secondary:hover, [type="button"].secondary:focus, [type="submit"].secondary:hover, [type="submit"].secondary:focus, [type="reset"].secondary:hover, [type="reset"].secondary:focus, .button.secondary:hover, .button.secondary:focus, [role="button"].secondary:hover, [role="button"].secondary:focus {
+ --button-hover-back-color: #c62828; }
+
+button.tertiary, [type="button"].tertiary, [type="submit"].tertiary, [type="reset"].tertiary, .button.tertiary, [role="button"].tertiary {
+ --button-back-color: #308732;
+ --button-fore-color: #f8f8f8; }
+ button.tertiary:hover, button.tertiary:focus, [type="button"].tertiary:hover, [type="button"].tertiary:focus, [type="submit"].tertiary:hover, [type="submit"].tertiary:focus, [type="reset"].tertiary:hover, [type="reset"].tertiary:focus, .button.tertiary:hover, .button.tertiary:focus, [role="button"].tertiary:hover, [role="button"].tertiary:focus {
+ --button-hover-back-color: #277529; }
+
+button.inverse, [type="button"].inverse, [type="submit"].inverse, [type="reset"].inverse, .button.inverse, [role="button"].inverse {
+ --button-back-color: #212121;
+ --button-fore-color: #f8f8f8; }
+ button.inverse:hover, button.inverse:focus, [type="button"].inverse:hover, [type="button"].inverse:focus, [type="submit"].inverse:hover, [type="submit"].inverse:focus, [type="reset"].inverse:hover, [type="reset"].inverse:focus, .button.inverse:hover, .button.inverse:focus, [role="button"].inverse:hover, [role="button"].inverse:focus {
+ --button-hover-back-color: #111; }
+
+button.small, [type="button"].small, [type="submit"].small, [type="reset"].small, .button.small, [role="button"].small {
+ padding: calc(0.5 * var(--universal-padding)) calc(0.75 * var(--universal-padding));
+ margin: var(--universal-margin); }
+
+button.large, [type="button"].large, [type="submit"].large, [type="reset"].large, .button.large, [role="button"].large {
+ padding: calc(1.5 * var(--universal-padding)) calc(2 * var(--universal-padding));
+ margin: var(--universal-margin); }
+
+/*
+ Definitions for navigation elements.
+*/
+/* Navigation module CSS variable definitions */
+:root {
+ --header-back-color: #03234b;
+ --header-hover-back-color: #ffd200;
+ --header-fore-color: #ffffff;
+ --header-border-color: #3cb4e6;
+ --nav-back-color: #ffffff;
+ --nav-hover-back-color: #ffe97f;
+ --nav-fore-color: #e6007e;
+ --nav-border-color: #3cb4e6;
+ --nav-link-color: #3cb4e6;
+ --footer-fore-color: #ffffff;
+ --footer-back-color: #03234b;
+ --footer-border-color: #3cb4e6;
+ --footer-link-color: #3cb4e6;
+ --drawer-back-color: #ffffff;
+ --drawer-hover-back-color: #ffe97f;
+ --drawer-border-color: #3cb4e6;
+ --drawer-close-color: #e6007e; }
+
+header {
+ height: 2.75rem;
+ background: var(--header-back-color);
+ color: var(--header-fore-color);
+ border-bottom: 0.0714285714rem solid var(--header-border-color);
+ padding: calc(var(--universal-padding) / 4) 0;
+ white-space: nowrap;
+ overflow-x: auto;
+ overflow-y: hidden; }
+ header.row {
+ box-sizing: content-box; }
+ header .logo {
+ color: var(--header-fore-color);
+ font-size: 1.75rem;
+ padding: var(--universal-padding) calc(2 * var(--universal-padding));
+ text-decoration: none; }
+ header button, header [type="button"], header .button, header [role="button"] {
+ box-sizing: border-box;
+ position: relative;
+ top: calc(0rem - var(--universal-padding) / 4);
+ height: calc(3.1875rem + var(--universal-padding) / 2);
+ background: var(--header-back-color);
+ line-height: calc(3.1875rem - var(--universal-padding) * 1.5);
+ text-align: center;
+ color: var(--header-fore-color);
+ border: 0;
+ border-radius: 0;
+ margin: 0;
+ text-transform: uppercase; }
+ header button:hover, header button:focus, header [type="button"]:hover, header [type="button"]:focus, header .button:hover, header .button:focus, header [role="button"]:hover, header [role="button"]:focus {
+ background: var(--header-hover-back-color); }
+
+nav {
+ background: var(--nav-back-color);
+ color: var(--nav-fore-color);
+ border: 0.0714285714rem solid var(--nav-border-color);
+ border-radius: var(--universal-border-radius);
+ margin: var(--universal-margin); }
+ nav * {
+ padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); }
+ nav a, nav a:visited {
+ display: block;
+ color: var(--nav-link-color);
+ border-radius: var(--universal-border-radius);
+ transition: background 0.3s; }
+ nav a:hover, nav a:focus, nav a:visited:hover, nav a:visited:focus {
+ text-decoration: none;
+ background: var(--nav-hover-back-color); }
+ nav .sublink-1 {
+ position: relative;
+ margin-left: calc(2 * var(--universal-padding)); }
+ nav .sublink-1:before {
+ position: absolute;
+ left: calc(var(--universal-padding) - 1 * var(--universal-padding));
+ top: -0.0714285714rem;
+ content: '';
+ height: 100%;
+ border: 0.0714285714rem solid var(--nav-border-color);
+ border-left: 0; }
+ nav .sublink-2 {
+ position: relative;
+ margin-left: calc(4 * var(--universal-padding)); }
+ nav .sublink-2:before {
+ position: absolute;
+ left: calc(var(--universal-padding) - 3 * var(--universal-padding));
+ top: -0.0714285714rem;
+ content: '';
+ height: 100%;
+ border: 0.0714285714rem solid var(--nav-border-color);
+ border-left: 0; }
+
+footer {
+ background: var(--footer-back-color);
+ color: var(--footer-fore-color);
+ border-top: 0.0714285714rem solid var(--footer-border-color);
+ padding: calc(2 * var(--universal-padding)) var(--universal-padding);
+ font-size: 0.875rem; }
+ footer a, footer a:visited {
+ color: var(--footer-link-color); }
+
+header.sticky {
+ position: -webkit-sticky;
+ position: sticky;
+ z-index: 1101;
+ top: 0; }
+
+footer.sticky {
+ position: -webkit-sticky;
+ position: sticky;
+ z-index: 1101;
+ bottom: 0; }
+
+.drawer-toggle:before {
+ display: inline-block;
+ position: relative;
+ vertical-align: bottom;
+ content: '\00a0\2261\00a0';
+ font-family: sans-serif;
+ font-size: 1.5em; }
+@media screen and (min-width: 500px) {
+ .drawer-toggle:not(.persistent) {
+ display: none; } }
+
+[type="checkbox"].drawer {
+ height: 1px;
+ width: 1px;
+ margin: -1px;
+ overflow: hidden;
+ position: absolute;
+ clip: rect(0 0 0 0);
+ -webkit-clip-path: inset(100%);
+ clip-path: inset(100%); }
+ [type="checkbox"].drawer + * {
+ display: block;
+ box-sizing: border-box;
+ position: fixed;
+ top: 0;
+ width: 320px;
+ height: 100vh;
+ overflow-y: auto;
+ background: var(--drawer-back-color);
+ border: 0.0714285714rem solid var(--drawer-border-color);
+ border-radius: 0;
+ margin: 0;
+ z-index: 1110;
+ right: -320px;
+ transition: right 0.3s; }
+ [type="checkbox"].drawer + * .drawer-close {
+ position: absolute;
+ top: var(--universal-margin);
+ right: var(--universal-margin);
+ z-index: 1111;
+ width: 2rem;
+ height: 2rem;
+ border-radius: var(--universal-border-radius);
+ padding: var(--universal-padding);
+ margin: 0;
+ cursor: pointer;
+ transition: background 0.3s; }
+ [type="checkbox"].drawer + * .drawer-close:before {
+ display: block;
+ content: '\00D7';
+ color: var(--drawer-close-color);
+ position: relative;
+ font-family: sans-serif;
+ font-size: 2rem;
+ line-height: 1;
+ text-align: center; }
+ [type="checkbox"].drawer + * .drawer-close:hover, [type="checkbox"].drawer + * .drawer-close:focus {
+ background: var(--drawer-hover-back-color); }
+ @media screen and (max-width: 320px) {
+ [type="checkbox"].drawer + * {
+ width: 100%; } }
+ [type="checkbox"].drawer:checked + * {
+ right: 0; }
+ @media screen and (min-width: 500px) {
+ [type="checkbox"].drawer:not(.persistent) + * {
+ position: static;
+ height: 100%;
+ z-index: 1100; }
+ [type="checkbox"].drawer:not(.persistent) + * .drawer-close {
+ display: none; } }
+
+/*
+ Definitions for the responsive table component.
+*/
+/* Table module CSS variable definitions. */
+:root {
+ --table-border-color: #03234b;
+ --table-border-separator-color: #03234b;
+ --table-head-back-color: #03234b;
+ --table-head-fore-color: #ffffff;
+ --table-body-back-color: #ffffff;
+ --table-body-fore-color: #03234b;
+ --table-body-alt-back-color: #f4f4f4; }
+
+table {
+ border-collapse: separate;
+ border-spacing: 0;
+ margin: 0;
+ display: flex;
+ flex: 0 1 auto;
+ flex-flow: row wrap;
+ padding: var(--universal-padding);
+ padding-top: 0; }
+ table caption {
+ font-size: 1rem;
+ margin: calc(2 * var(--universal-margin)) 0;
+ max-width: 100%;
+ flex: 0 0 100%; }
+ table thead, table tbody {
+ display: flex;
+ flex-flow: row wrap;
+ border: 0.0714285714rem solid var(--table-border-color); }
+ table thead {
+ z-index: 999;
+ border-radius: var(--universal-border-radius) var(--universal-border-radius) 0 0;
+ border-bottom: 0.0714285714rem solid var(--table-border-separator-color); }
+ table tbody {
+ border-top: 0;
+ margin-top: calc(0 - var(--universal-margin));
+ border-radius: 0 0 var(--universal-border-radius) var(--universal-border-radius); }
+ table tr {
+ display: flex;
+ padding: 0; }
+ table th, table td {
+ padding: calc(0.5 * var(--universal-padding));
+ font-size: 0.9rem; }
+ table th {
+ text-align: left;
+ background: var(--table-head-back-color);
+ color: var(--table-head-fore-color); }
+ table td {
+ background: var(--table-body-back-color);
+ color: var(--table-body-fore-color);
+ border-top: 0.0714285714rem solid var(--table-border-color); }
+
+table:not(.horizontal) {
+ overflow: auto;
+ max-height: 100%; }
+ table:not(.horizontal) thead, table:not(.horizontal) tbody {
+ max-width: 100%;
+ flex: 0 0 100%; }
+ table:not(.horizontal) tr {
+ flex-flow: row wrap;
+ flex: 0 0 100%; }
+ table:not(.horizontal) th, table:not(.horizontal) td {
+ flex: 1 0 0%;
+ overflow: hidden;
+ text-overflow: ellipsis; }
+ table:not(.horizontal) thead {
+ position: sticky;
+ top: 0; }
+ table:not(.horizontal) tbody tr:first-child td {
+ border-top: 0; }
+
+table.horizontal {
+ border: 0; }
+ table.horizontal thead, table.horizontal tbody {
+ border: 0;
+ flex: .2 0 0;
+ flex-flow: row nowrap; }
+ table.horizontal tbody {
+ overflow: auto;
+ justify-content: space-between;
+ flex: .8 0 0;
+ margin-left: 0;
+ padding-bottom: calc(var(--universal-padding) / 4); }
+ table.horizontal tr {
+ flex-direction: column;
+ flex: 1 0 auto; }
+ table.horizontal th, table.horizontal td {
+ width: auto;
+ border: 0;
+ border-bottom: 0.0714285714rem solid var(--table-border-color); }
+ table.horizontal th:not(:first-child), table.horizontal td:not(:first-child) {
+ border-top: 0; }
+ table.horizontal th {
+ text-align: right;
+ border-left: 0.0714285714rem solid var(--table-border-color);
+ border-right: 0.0714285714rem solid var(--table-border-separator-color); }
+ table.horizontal thead tr:first-child {
+ padding-left: 0; }
+ table.horizontal th:first-child, table.horizontal td:first-child {
+ border-top: 0.0714285714rem solid var(--table-border-color); }
+ table.horizontal tbody tr:last-child td {
+ border-right: 0.0714285714rem solid var(--table-border-color); }
+ table.horizontal tbody tr:last-child td:first-child {
+ border-top-right-radius: 0.25rem; }
+ table.horizontal tbody tr:last-child td:last-child {
+ border-bottom-right-radius: 0.25rem; }
+ table.horizontal thead tr:first-child th:first-child {
+ border-top-left-radius: 0.25rem; }
+ table.horizontal thead tr:first-child th:last-child {
+ border-bottom-left-radius: 0.25rem; }
+
+@media screen and (max-width: 499px) {
+ table, table.horizontal {
+ border-collapse: collapse;
+ border: 0;
+ width: 100%;
+ display: table; }
+ table thead, table th, table.horizontal thead, table.horizontal th {
+ border: 0;
+ height: 1px;
+ width: 1px;
+ margin: -1px;
+ overflow: hidden;
+ padding: 0;
+ position: absolute;
+ clip: rect(0 0 0 0);
+ -webkit-clip-path: inset(100%);
+ clip-path: inset(100%); }
+ table tbody, table.horizontal tbody {
+ border: 0;
+ display: table-row-group; }
+ table tr, table.horizontal tr {
+ display: block;
+ border: 0.0714285714rem solid var(--table-border-color);
+ border-radius: var(--universal-border-radius);
+ background: #ffffff;
+ padding: var(--universal-padding);
+ margin: var(--universal-margin);
+ margin-bottom: calc(1 * var(--universal-margin)); }
+ table th, table td, table.horizontal th, table.horizontal td {
+ width: auto; }
+ table td, table.horizontal td {
+ display: block;
+ border: 0;
+ text-align: right; }
+ table td:before, table.horizontal td:before {
+ content: attr(data-label);
+ float: left;
+ font-weight: 600; }
+ table th:first-child, table td:first-child, table.horizontal th:first-child, table.horizontal td:first-child {
+ border-top: 0; }
+ table tbody tr:last-child td, table.horizontal tbody tr:last-child td {
+ border-right: 0; } }
+table tr:nth-of-type(2n) > td {
+ background: var(--table-body-alt-back-color); }
+
+@media screen and (max-width: 500px) {
+ table tr:nth-of-type(2n) {
+ background: var(--table-body-alt-back-color); } }
+:root {
+ --table-body-hover-back-color: #90caf9; }
+
+table.hoverable tr:hover, table.hoverable tr:hover > td, table.hoverable tr:focus, table.hoverable tr:focus > td {
+ background: var(--table-body-hover-back-color); }
+
+@media screen and (max-width: 500px) {
+ table.hoverable tr:hover, table.hoverable tr:hover > td, table.hoverable tr:focus, table.hoverable tr:focus > td {
+ background: var(--table-body-hover-back-color); } }
+/*
+ Definitions for contextual background elements, toasts and tooltips.
+*/
+/* Contextual module CSS variable definitions */
+:root {
+ --mark-back-color: #3cb4e6;
+ --mark-fore-color: #ffffff; }
+
+mark {
+ background: var(--mark-back-color);
+ color: var(--mark-fore-color);
+ font-size: 0.95em;
+ line-height: 1em;
+ border-radius: var(--universal-border-radius);
+ padding: calc(var(--universal-padding) / 4) var(--universal-padding); }
+ mark.inline-block {
+ display: inline-block;
+ font-size: 1em;
+ line-height: 1.4;
+ padding: calc(var(--universal-padding) / 2) var(--universal-padding); }
+
+:root {
+ --toast-back-color: #424242;
+ --toast-fore-color: #fafafa; }
+
+.toast {
+ position: fixed;
+ bottom: calc(var(--universal-margin) * 3);
+ left: 50%;
+ transform: translate(-50%, -50%);
+ z-index: 1111;
+ color: var(--toast-fore-color);
+ background: var(--toast-back-color);
+ border-radius: calc(var(--universal-border-radius) * 16);
+ padding: var(--universal-padding) calc(var(--universal-padding) * 3); }
+
+:root {
+ --tooltip-back-color: #212121;
+ --tooltip-fore-color: #fafafa; }
+
+.tooltip {
+ position: relative;
+ display: inline-block; }
+ .tooltip:before, .tooltip:after {
+ position: absolute;
+ opacity: 0;
+ clip: rect(0 0 0 0);
+ -webkit-clip-path: inset(100%);
+ clip-path: inset(100%);
+ transition: all 0.3s;
+ z-index: 1010;
+ left: 50%; }
+ .tooltip:not(.bottom):before, .tooltip:not(.bottom):after {
+ bottom: 75%; }
+ .tooltip.bottom:before, .tooltip.bottom:after {
+ top: 75%; }
+ .tooltip:hover:before, .tooltip:hover:after, .tooltip:focus:before, .tooltip:focus:after {
+ opacity: 1;
+ clip: auto;
+ -webkit-clip-path: inset(0%);
+ clip-path: inset(0%); }
+ .tooltip:before {
+ content: '';
+ background: transparent;
+ border: var(--universal-margin) solid transparent;
+ left: calc(50% - var(--universal-margin)); }
+ .tooltip:not(.bottom):before {
+ border-top-color: #212121; }
+ .tooltip.bottom:before {
+ border-bottom-color: #212121; }
+ .tooltip:after {
+ content: attr(aria-label);
+ color: var(--tooltip-fore-color);
+ background: var(--tooltip-back-color);
+ border-radius: var(--universal-border-radius);
+ padding: var(--universal-padding);
+ white-space: nowrap;
+ transform: translateX(-50%); }
+ .tooltip:not(.bottom):after {
+ margin-bottom: calc(2 * var(--universal-margin)); }
+ .tooltip.bottom:after {
+ margin-top: calc(2 * var(--universal-margin)); }
+
+:root {
+ --modal-overlay-color: rgba(0, 0, 0, 0.45);
+ --modal-close-color: #e6007e;
+ --modal-close-hover-color: #ffe97f; }
+
+[type="checkbox"].modal {
+ height: 1px;
+ width: 1px;
+ margin: -1px;
+ overflow: hidden;
+ position: absolute;
+ clip: rect(0 0 0 0);
+ -webkit-clip-path: inset(100%);
+ clip-path: inset(100%); }
+ [type="checkbox"].modal + div {
+ position: fixed;
+ top: 0;
+ left: 0;
+ display: none;
+ width: 100vw;
+ height: 100vh;
+ background: var(--modal-overlay-color); }
+ [type="checkbox"].modal + div .card {
+ margin: 0 auto;
+ max-height: 50vh;
+ overflow: auto; }
+ [type="checkbox"].modal + div .card .modal-close {
+ position: absolute;
+ top: 0;
+ right: 0;
+ width: 1.75rem;
+ height: 1.75rem;
+ border-radius: var(--universal-border-radius);
+ padding: var(--universal-padding);
+ margin: 0;
+ cursor: pointer;
+ transition: background 0.3s; }
+ [type="checkbox"].modal + div .card .modal-close:before {
+ display: block;
+ content: '\00D7';
+ color: var(--modal-close-color);
+ position: relative;
+ font-family: sans-serif;
+ font-size: 1.75rem;
+ line-height: 1;
+ text-align: center; }
+ [type="checkbox"].modal + div .card .modal-close:hover, [type="checkbox"].modal + div .card .modal-close:focus {
+ background: var(--modal-close-hover-color); }
+ [type="checkbox"].modal:checked + div {
+ display: flex;
+ flex: 0 1 auto;
+ z-index: 1200; }
+ [type="checkbox"].modal:checked + div .card .modal-close {
+ z-index: 1211; }
+
+:root {
+ --collapse-label-back-color: #03234b;
+ --collapse-label-fore-color: #ffffff;
+ --collapse-label-hover-back-color: #3cb4e6;
+ --collapse-selected-label-back-color: #3cb4e6;
+ --collapse-border-color: var(--collapse-label-back-color);
+ --collapse-selected-border-color: #ceecf8;
+ --collapse-content-back-color: #ffffff;
+ --collapse-selected-label-border-color: #3cb4e6; }
+
+.collapse {
+ width: calc(100% - 2 * var(--universal-margin));
+ opacity: 1;
+ display: flex;
+ flex-direction: column;
+ margin: var(--universal-margin);
+ border-radius: var(--universal-border-radius); }
+ .collapse > [type="radio"], .collapse > [type="checkbox"] {
+ height: 1px;
+ width: 1px;
+ margin: -1px;
+ overflow: hidden;
+ position: absolute;
+ clip: rect(0 0 0 0);
+ -webkit-clip-path: inset(100%);
+ clip-path: inset(100%); }
+ .collapse > label {
+ flex-grow: 1;
+ display: inline-block;
+ height: 1.25rem;
+ cursor: pointer;
+ transition: background 0.2s;
+ color: var(--collapse-label-fore-color);
+ background: var(--collapse-label-back-color);
+ border: 0.0714285714rem solid var(--collapse-selected-border-color);
+ padding: calc(1.25 * var(--universal-padding)); }
+ .collapse > label:hover, .collapse > label:focus {
+ background: var(--collapse-label-hover-back-color); }
+ .collapse > label + div {
+ flex-basis: auto;
+ height: 1px;
+ width: 1px;
+ margin: -1px;
+ overflow: hidden;
+ position: absolute;
+ clip: rect(0 0 0 0);
+ -webkit-clip-path: inset(100%);
+ clip-path: inset(100%);
+ transition: max-height 0.3s;
+ max-height: 1px; }
+ .collapse > :checked + label {
+ background: var(--collapse-selected-label-back-color);
+ border-color: var(--collapse-selected-label-border-color); }
+ .collapse > :checked + label + div {
+ box-sizing: border-box;
+ position: relative;
+ width: 100%;
+ height: auto;
+ overflow: auto;
+ margin: 0;
+ background: var(--collapse-content-back-color);
+ border: 0.0714285714rem solid var(--collapse-selected-border-color);
+ border-top: 0;
+ padding: var(--universal-padding);
+ clip: auto;
+ -webkit-clip-path: inset(0%);
+ clip-path: inset(0%);
+ max-height: 100%; }
+ .collapse > label:not(:first-of-type) {
+ border-top: 0; }
+ .collapse > label:first-of-type {
+ border-radius: var(--universal-border-radius) var(--universal-border-radius) 0 0; }
+ .collapse > label:last-of-type:not(:first-of-type) {
+ border-radius: 0 0 var(--universal-border-radius) var(--universal-border-radius); }
+ .collapse > label:last-of-type:first-of-type {
+ border-radius: var(--universal-border-radius); }
+ .collapse > :checked:last-of-type:not(:first-of-type) + label {
+ border-radius: 0; }
+ .collapse > :checked:last-of-type + label + div {
+ border-radius: 0 0 var(--universal-border-radius) var(--universal-border-radius); }
+
+/*
+ Custom elements for contextual background elements, toasts and tooltips.
+*/
+mark.tertiary {
+ --mark-back-color: #3cb4e6; }
+
+mark.tag {
+ padding: calc(var(--universal-padding)/2) var(--universal-padding);
+ border-radius: 1em; }
+
+/*
+ Definitions for progress elements and spinners.
+*/
+/* Progress module CSS variable definitions */
+:root {
+ --progress-back-color: #3cb4e6;
+ --progress-fore-color: #555; }
+
+progress {
+ display: block;
+ vertical-align: baseline;
+ -webkit-appearance: none;
+ -moz-appearance: none;
+ appearance: none;
+ height: 0.75rem;
+ width: calc(100% - 2 * var(--universal-margin));
+ margin: var(--universal-margin);
+ border: 0;
+ border-radius: calc(2 * var(--universal-border-radius));
+ background: var(--progress-back-color);
+ color: var(--progress-fore-color); }
+ progress::-webkit-progress-value {
+ background: var(--progress-fore-color);
+ border-top-left-radius: calc(2 * var(--universal-border-radius));
+ border-bottom-left-radius: calc(2 * var(--universal-border-radius)); }
+ progress::-webkit-progress-bar {
+ background: var(--progress-back-color); }
+ progress::-moz-progress-bar {
+ background: var(--progress-fore-color);
+ border-top-left-radius: calc(2 * var(--universal-border-radius));
+ border-bottom-left-radius: calc(2 * var(--universal-border-radius)); }
+ progress[value="1000"]::-webkit-progress-value {
+ border-radius: calc(2 * var(--universal-border-radius)); }
+ progress[value="1000"]::-moz-progress-bar {
+ border-radius: calc(2 * var(--universal-border-radius)); }
+ progress.inline {
+ display: inline-block;
+ vertical-align: middle;
+ width: 60%; }
+
+:root {
+ --spinner-back-color: #ddd;
+ --spinner-fore-color: #555; }
+
+@keyframes spinner-donut-anim {
+ 0% {
+ transform: rotate(0deg); }
+ 100% {
+ transform: rotate(360deg); } }
+.spinner {
+ display: inline-block;
+ margin: var(--universal-margin);
+ border: 0.25rem solid var(--spinner-back-color);
+ border-left: 0.25rem solid var(--spinner-fore-color);
+ border-radius: 50%;
+ width: 1.25rem;
+ height: 1.25rem;
+ animation: spinner-donut-anim 1.2s linear infinite; }
+
+/*
+ Custom elements for progress bars and spinners.
+*/
+progress.primary {
+ --progress-fore-color: #1976d2; }
+
+progress.secondary {
+ --progress-fore-color: #d32f2f; }
+
+progress.tertiary {
+ --progress-fore-color: #308732; }
+
+.spinner.primary {
+ --spinner-fore-color: #1976d2; }
+
+.spinner.secondary {
+ --spinner-fore-color: #d32f2f; }
+
+.spinner.tertiary {
+ --spinner-fore-color: #308732; }
+
+/*
+ Definitions for icons - powered by Feather (https://feathericons.com/).
+*/
+span[class^='icon-'] {
+ display: inline-block;
+ height: 1em;
+ width: 1em;
+ vertical-align: -0.125em;
+ background-size: contain;
+ margin: 0 calc(var(--universal-margin) / 4); }
+ span[class^='icon-'].secondary {
+ -webkit-filter: invert(25%);
+ filter: invert(25%); }
+ span[class^='icon-'].inverse {
+ -webkit-filter: invert(100%);
+ filter: invert(100%); }
+
+span.icon-alert {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='8' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='16' x2='12' y2='16'%3E%3C/line%3E%3C/svg%3E"); }
+span.icon-bookmark {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M19 21l-7-5-7 5V5a2 2 0 0 1 2-2h10a2 2 0 0 1 2 2z'%3E%3C/path%3E%3C/svg%3E"); }
+span.icon-calendar {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='4' width='18' height='18' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='16' y1='2' x2='16' y2='6'%3E%3C/line%3E%3Cline x1='8' y1='2' x2='8' y2='6'%3E%3C/line%3E%3Cline x1='3' y1='10' x2='21' y2='10'%3E%3C/line%3E%3C/svg%3E"); }
+span.icon-credit {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='1' y='4' width='22' height='16' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='1' y1='10' x2='23' y2='10'%3E%3C/line%3E%3C/svg%3E"); }
+span.icon-edit {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M20 14.66V20a2 2 0 0 1-2 2H4a2 2 0 0 1-2-2V6a2 2 0 0 1 2-2h5.34'%3E%3C/path%3E%3Cpolygon points='18 2 22 6 12 16 8 16 8 12 18 2'%3E%3C/polygon%3E%3C/svg%3E"); }
+span.icon-link {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M18 13v6a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2V8a2 2 0 0 1 2-2h6'%3E%3C/path%3E%3Cpolyline points='15 3 21 3 21 9'%3E%3C/polyline%3E%3Cline x1='10' y1='14' x2='21' y2='3'%3E%3C/line%3E%3C/svg%3E"); }
+span.icon-help {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M9.09 9a3 3 0 0 1 5.83 1c0 2-3 3-3 3'%3E%3C/path%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='17' x2='12' y2='17'%3E%3C/line%3E%3C/svg%3E"); }
+span.icon-home {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M3 9l9-7 9 7v11a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2z'%3E%3C/path%3E%3Cpolyline points='9 22 9 12 15 12 15 22'%3E%3C/polyline%3E%3C/svg%3E"); }
+span.icon-info {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='16' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='8' x2='12' y2='8'%3E%3C/line%3E%3C/svg%3E"); }
+span.icon-lock {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='11' width='18' height='11' rx='2' ry='2'%3E%3C/rect%3E%3Cpath d='M7 11V7a5 5 0 0 1 10 0v4'%3E%3C/path%3E%3C/svg%3E"); }
+span.icon-mail {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M4 4h16c1.1 0 2 .9 2 2v12c0 1.1-.9 2-2 2H4c-1.1 0-2-.9-2-2V6c0-1.1.9-2 2-2z'%3E%3C/path%3E%3Cpolyline points='22,6 12,13 2,6'%3E%3C/polyline%3E%3C/svg%3E"); }
+span.icon-location {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M21 10c0 7-9 13-9 13s-9-6-9-13a9 9 0 0 1 18 0z'%3E%3C/path%3E%3Ccircle cx='12' cy='10' r='3'%3E%3C/circle%3E%3C/svg%3E"); }
+span.icon-phone {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M22 16.92v3a2 2 0 0 1-2.18 2 19.79 19.79 0 0 1-8.63-3.07 19.5 19.5 0 0 1-6-6 19.79 19.79 0 0 1-3.07-8.67A2 2 0 0 1 4.11 2h3a2 2 0 0 1 2 1.72 12.84 12.84 0 0 0 .7 2.81 2 2 0 0 1-.45 2.11L8.09 9.91a16 16 0 0 0 6 6l1.27-1.27a2 2 0 0 1 2.11-.45 12.84 12.84 0 0 0 2.81.7A2 2 0 0 1 22 16.92z'%3E%3C/path%3E%3C/svg%3E"); }
+span.icon-rss {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M4 11a9 9 0 0 1 9 9'%3E%3C/path%3E%3Cpath d='M4 4a16 16 0 0 1 16 16'%3E%3C/path%3E%3Ccircle cx='5' cy='19' r='1'%3E%3C/circle%3E%3C/svg%3E"); }
+span.icon-search {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='11' cy='11' r='8'%3E%3C/circle%3E%3Cline x1='21' y1='21' x2='16.65' y2='16.65'%3E%3C/line%3E%3C/svg%3E"); }
+span.icon-settings {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='3'%3E%3C/circle%3E%3Cpath d='M19.4 15a1.65 1.65 0 0 0 .33 1.82l.06.06a2 2 0 0 1 0 2.83 2 2 0 0 1-2.83 0l-.06-.06a1.65 1.65 0 0 0-1.82-.33 1.65 1.65 0 0 0-1 1.51V21a2 2 0 0 1-2 2 2 2 0 0 1-2-2v-.09A1.65 1.65 0 0 0 9 19.4a1.65 1.65 0 0 0-1.82.33l-.06.06a2 2 0 0 1-2.83 0 2 2 0 0 1 0-2.83l.06-.06a1.65 1.65 0 0 0 .33-1.82 1.65 1.65 0 0 0-1.51-1H3a2 2 0 0 1-2-2 2 2 0 0 1 2-2h.09A1.65 1.65 0 0 0 4.6 9a1.65 1.65 0 0 0-.33-1.82l-.06-.06a2 2 0 0 1 0-2.83 2 2 0 0 1 2.83 0l.06.06a1.65 1.65 0 0 0 1.82.33H9a1.65 1.65 0 0 0 1-1.51V3a2 2 0 0 1 2-2 2 2 0 0 1 2 2v.09a1.65 1.65 0 0 0 1 1.51 1.65 1.65 0 0 0 1.82-.33l.06-.06a2 2 0 0 1 2.83 0 2 2 0 0 1 0 2.83l-.06.06a1.65 1.65 0 0 0-.33 1.82V9a1.65 1.65 0 0 0 1.51 1H21a2 2 0 0 1 2 2 2 2 0 0 1-2 2h-.09a1.65 1.65 0 0 0-1.51 1z'%3E%3C/path%3E%3C/svg%3E"); }
+span.icon-share {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='18' cy='5' r='3'%3E%3C/circle%3E%3Ccircle cx='6' cy='12' r='3'%3E%3C/circle%3E%3Ccircle cx='18' cy='19' r='3'%3E%3C/circle%3E%3Cline x1='8.59' y1='13.51' x2='15.42' y2='17.49'%3E%3C/line%3E%3Cline x1='15.41' y1='6.51' x2='8.59' y2='10.49'%3E%3C/line%3E%3C/svg%3E"); }
+span.icon-cart {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='9' cy='21' r='1'%3E%3C/circle%3E%3Ccircle cx='20' cy='21' r='1'%3E%3C/circle%3E%3Cpath d='M1 1h4l2.68 13.39a2 2 0 0 0 2 1.61h9.72a2 2 0 0 0 2-1.61L23 6H6'%3E%3C/path%3E%3C/svg%3E"); }
+span.icon-upload {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M21 15v4a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2v-4'%3E%3C/path%3E%3Cpolyline points='17 8 12 3 7 8'%3E%3C/polyline%3E%3Cline x1='12' y1='3' x2='12' y2='15'%3E%3C/line%3E%3C/svg%3E"); }
+span.icon-user {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M20 21v-2a4 4 0 0 0-4-4H8a4 4 0 0 0-4 4v2'%3E%3C/path%3E%3Ccircle cx='12' cy='7' r='4'%3E%3C/circle%3E%3C/svg%3E"); }
+
+/*
+ Definitions for STMicroelectronics icons (https://brandportal.st.com/document/26).
+*/
+span.icon-st-update {
+ background-image: url("Update.svg"); }
+span.icon-st-add {
+ background-image: url("Add button.svg"); }
+
+/*
+ Definitions for utilities and helper classes.
+*/
+/* Utility module CSS variable definitions */
+:root {
+ --generic-border-color: rgba(0, 0, 0, 0.3);
+ --generic-box-shadow: 0 0.2857142857rem 0.2857142857rem 0 rgba(0, 0, 0, 0.125), 0 0.1428571429rem 0.1428571429rem -0.1428571429rem rgba(0, 0, 0, 0.125); }
+
+.hidden {
+ display: none !important; }
+
+.visually-hidden {
+ position: absolute !important;
+ width: 1px !important;
+ height: 1px !important;
+ margin: -1px !important;
+ border: 0 !important;
+ padding: 0 !important;
+ clip: rect(0 0 0 0) !important;
+ -webkit-clip-path: inset(100%) !important;
+ clip-path: inset(100%) !important;
+ overflow: hidden !important; }
+
+.bordered {
+ border: 0.0714285714rem solid var(--generic-border-color) !important; }
+
+.rounded {
+ border-radius: var(--universal-border-radius) !important; }
+
+.circular {
+ border-radius: 50% !important; }
+
+.shadowed {
+ box-shadow: var(--generic-box-shadow) !important; }
+
+.responsive-margin {
+ margin: calc(var(--universal-margin) / 4) !important; }
+ @media screen and (min-width: 500px) {
+ .responsive-margin {
+ margin: calc(var(--universal-margin) / 2) !important; } }
+ @media screen and (min-width: 1280px) {
+ .responsive-margin {
+ margin: var(--universal-margin) !important; } }
+
+.responsive-padding {
+ padding: calc(var(--universal-padding) / 4) !important; }
+ @media screen and (min-width: 500px) {
+ .responsive-padding {
+ padding: calc(var(--universal-padding) / 2) !important; } }
+ @media screen and (min-width: 1280px) {
+ .responsive-padding {
+ padding: var(--universal-padding) !important; } }
+
+@media screen and (max-width: 499px) {
+ .hidden-sm {
+ display: none !important; } }
+@media screen and (min-width: 500px) and (max-width: 1279px) {
+ .hidden-md {
+ display: none !important; } }
+@media screen and (min-width: 1280px) {
+ .hidden-lg {
+ display: none !important; } }
+@media screen and (max-width: 499px) {
+ .visually-hidden-sm {
+ position: absolute !important;
+ width: 1px !important;
+ height: 1px !important;
+ margin: -1px !important;
+ border: 0 !important;
+ padding: 0 !important;
+ clip: rect(0 0 0 0) !important;
+ -webkit-clip-path: inset(100%) !important;
+ clip-path: inset(100%) !important;
+ overflow: hidden !important; } }
+@media screen and (min-width: 500px) and (max-width: 1279px) {
+ .visually-hidden-md {
+ position: absolute !important;
+ width: 1px !important;
+ height: 1px !important;
+ margin: -1px !important;
+ border: 0 !important;
+ padding: 0 !important;
+ clip: rect(0 0 0 0) !important;
+ -webkit-clip-path: inset(100%) !important;
+ clip-path: inset(100%) !important;
+ overflow: hidden !important; } }
+@media screen and (min-width: 1280px) {
+ .visually-hidden-lg {
+ position: absolute !important;
+ width: 1px !important;
+ height: 1px !important;
+ margin: -1px !important;
+ border: 0 !important;
+ padding: 0 !important;
+ clip: rect(0 0 0 0) !important;
+ -webkit-clip-path: inset(100%) !important;
+ clip-path: inset(100%) !important;
+ overflow: hidden !important; } }
+
+/*# sourceMappingURL=mini-custom.css.map */
+
+img[alt="ST logo"] { display: block; margin: auto; width: 75%; max-width: 250px; min-width: 71px; }
+img[alt="Cube logo"] { float: right; width: 30%; max-width: 10rem; min-width: 8rem; padding-right: 1rem;}
+
+.figure {
+ display: block;
+ margin-left: auto;
+ margin-right: auto;
+ text-align: center;
+}
\ No newline at end of file
diff --git a/system/Drivers/STM32C0xx_HAL_Driver/_htmresc/st_logo.png b/system/Drivers/STM32C0xx_HAL_Driver/_htmresc/st_logo.png
new file mode 100644
index 0000000000..8b80057fd3
Binary files /dev/null and b/system/Drivers/STM32C0xx_HAL_Driver/_htmresc/st_logo.png differ
diff --git a/system/Drivers/STM32C0xx_HAL_Driver/_htmresc/st_logo_2020.png b/system/Drivers/STM32C0xx_HAL_Driver/_htmresc/st_logo_2020.png
new file mode 100644
index 0000000000..d6cebb5ac7
Binary files /dev/null and b/system/Drivers/STM32C0xx_HAL_Driver/_htmresc/st_logo_2020.png differ
diff --git a/system/Drivers/STM32YYxx_HAL_Driver_version.md b/system/Drivers/STM32YYxx_HAL_Driver_version.md
index 9ab5eefd9f..421001a5fd 100644
--- a/system/Drivers/STM32YYxx_HAL_Driver_version.md
+++ b/system/Drivers/STM32YYxx_HAL_Driver_version.md
@@ -1,5 +1,6 @@
# STM32YYxx HAL Drivers version:
+ * STM32C0: 1.0.1
* STM32F0: 1.7.6
* STM32F1: 1.1.8
* STM32F2: 1.2.7
diff --git a/system/STM32C0xx/stm32c0xx_hal_conf.h b/system/STM32C0xx/stm32c0xx_hal_conf.h
new file mode 100644
index 0000000000..a12f05dc45
--- /dev/null
+++ b/system/STM32C0xx/stm32c0xx_hal_conf.h
@@ -0,0 +1,16 @@
+#ifndef __STM32C0xx_HAL_CONF_H
+#define __STM32C0xx_HAL_CONF_H
+
+#include "variant.h"
+
+/* STM32C0xx specific HAL configuration options. */
+#if __has_include("hal_conf_custom.h")
+#include "hal_conf_custom.h"
+#else
+#if __has_include("hal_conf_extra.h")
+#include "hal_conf_extra.h"
+#endif
+#include "stm32c0xx_hal_conf_default.h"
+#endif
+
+#endif /* __STM32C0xx_HAL_CONF_H */
\ No newline at end of file
diff --git a/system/STM32C0xx/stm32c0xx_hal_conf_default.h b/system/STM32C0xx/stm32c0xx_hal_conf_default.h
new file mode 100644
index 0000000000..2730a106bc
--- /dev/null
+++ b/system/STM32C0xx/stm32c0xx_hal_conf_default.h
@@ -0,0 +1,286 @@
+/**
+ ******************************************************************************
+ * @file stm32c0xx_hal_conf_default.h
+ * @brief HAL default configuration template file.
+ * This file should be copied to the application folder and renamed
+ * to stm32c0xx_hal_conf.h.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2022 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32C0xx_HAL_CONF_DEFAULT_H
+#define STM32C0xx_HAL_CONF_DEFAULT_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+ * @brief Include the default list of modules to be used in the HAL driver
+ * and manage module deactivation
+ */
+#include "stm32yyxx_hal_conf.h"
+#if 0
+/**
+ * @brief This is the list of modules to be used in the HAL driver
+ */
+#define HAL_MODULE_ENABLED
+#define HAL_ADC_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_CRC_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_I2C_MODULE_ENABLED
+#define HAL_I2S_MODULE_ENABLED
+#define HAL_IRDA_MODULE_ENABLED
+#define HAL_IWDG_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+#define HAL_RTC_MODULE_ENABLED
+#define HAL_SMARTCARD_MODULE_ENABLED
+#define HAL_SMBUS_MODULE_ENABLED
+#define HAL_SPI_MODULE_ENABLED
+#define HAL_TIM_MODULE_ENABLED
+#define HAL_UART_MODULE_ENABLED
+#define HAL_USART_MODULE_ENABLED
+#define HAL_WWDG_MODULE_ENABLED
+#endif
+
+/* ########################## Register Callbacks selection ############################## */
+/**
+ * @brief Set below the peripheral configuration to "1U" to add the support
+ * of HAL callback registration/unregistration feature for the HAL
+ * driver(s). This allows user application to provide specific callback
+ * functions thanks to HAL_PPP_RegisterCallback() rather than overwriting
+ * the default weak callback functions (see each stm32c0xx_hal_ppp.h file
+ * for possible callback identifiers defined in HAL_PPP_CallbackIDTypeDef
+ * for each PPP peripheral).
+ */
+#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */
+#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */
+#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */
+#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */
+#define USE_HAL_IWDG_REGISTER_CALLBACKS 0U /* IWDG register callback disabled */
+#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */
+#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */
+#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */
+#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */
+#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */
+#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */
+#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */
+#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+ * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+ * This value is used by the RCC HAL module to compute the system frequency
+ * (when HSE is used as system clock source, directly or through the PLL).
+ */
+#if !defined (HSE_VALUE)
+#define HSE_VALUE (48000000U) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined (HSE_STARTUP_TIMEOUT)
+#define HSE_STARTUP_TIMEOUT (100UL) /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+ * @brief Internal High Speed oscillator (HSI) value.
+ * This value is used by the RCC HAL module to compute the system frequency
+ * (when HSI is used as system clock source, directly or through the PLL).
+ */
+#if !defined (HSI_VALUE)
+#define HSI_VALUE (48000000U) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+ * @brief Internal Low Speed oscillator (LSI) value.
+ */
+#if !defined (LSI_VALUE)
+#define LSI_VALUE (32000UL) /*!< LSI Typical Value in Hz*/
+#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
+The real value may vary depending on the variations
+in voltage and temperature.*/
+#if !defined (LSI_STARTUP_TIME)
+#define LSI_STARTUP_TIME 130UL /*!< Time out for LSI start up, in ms */
+#endif /* LSI_STARTUP_TIME */
+/**
+ * @brief External Low Speed oscillator (LSE) value.
+ * This value is used by the UART, RTC HAL module to compute the system frequency
+ */
+#if !defined (LSE_VALUE)
+#define LSE_VALUE (32768UL) /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+#if !defined (LSE_STARTUP_TIMEOUT)
+#define LSE_STARTUP_TIMEOUT (5000UL) /*!< Time out for LSE start up, in ms */
+#endif /* LSE_STARTUP_TIMEOUT */
+
+/**
+ * @brief External clock source for I2S1 peripheral
+ * This value is used by the RCC HAL module to compute the I2S1 clock source
+ * frequency.
+ */
+#if !defined (EXTERNAL_I2S1_CLOCK_VALUE)
+#define EXTERNAL_I2S1_CLOCK_VALUE (48000UL) /*!< Value of the I2S1 External clock source in Hz*/
+#endif /* EXTERNAL_I2S1_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+ === you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+ * @brief This is the HAL system configuration section
+ */
+#if !defined (VDD_VALUE)
+#define VDD_VALUE (3300UL) /*!< Value of VDD in mv */
+#endif
+#if !defined (TICK_INT_PRIORITY)
+#define TICK_INT_PRIORITY ((1UL<<__NVIC_PRIO_BITS) - 1UL) /*!< tick interrupt priority */
+#endif
+#if !defined (USE_RTOS)
+#define USE_RTOS 0U
+#endif
+#if !defined (PREFETCH_ENABLE)
+#define PREFETCH_ENABLE 1U
+#endif
+#if !defined (INSTRUCTION_CACHE_ENABLE)
+#define INSTRUCTION_CACHE_ENABLE 1U
+#endif
+
+
+/* ########################## Assert Selection ############################## */
+/**
+ * @brief Uncomment the line below to expanse the "assert_param" macro in the
+ * HAL drivers code
+ */
+/* #define USE_FULL_ASSERT 1U */
+
+/* Includes ------------------------------------------------------------------*/
+/**
+ * @brief Include modules header file
+ */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+#include "stm32c0xx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+#include "stm32c0xx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+#include "stm32c0xx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+#include "stm32c0xx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+#include "stm32c0xx_hal_adc.h"
+#include "stm32c0xx_hal_adc_ex.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+#include "stm32c0xx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+#include "stm32c0xx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+#include "stm32c0xx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+#include "stm32c0xx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+#include "stm32c0xx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+#include "stm32c0xx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+#include "stm32c0xx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+#include "stm32c0xx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+#include "stm32c0xx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+#include "stm32c0xx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+#include "stm32c0xx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+#include "stm32c0xx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+#include "stm32c0xx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+#include "stm32c0xx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+#include "stm32c0xx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+#include "stm32c0xx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef USE_FULL_ASSERT
+/**
+ * @brief The assert_param macro is used for functions parameters check.
+ * @param expr If expr is false, it calls assert_failed function
+ * which reports the name of the source file and the source
+ * line number of the call that failed.
+ * If expr is true, it returns no value.
+ * @retval None
+ */
+#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+void assert_failed(uint8_t *file, uint32_t line);
+#else
+#define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32C0xx_HAL_CONF_DEFAULT_H */
diff --git a/system/STM32C0xx/system_stm32c0xx.c b/system/STM32C0xx/system_stm32c0xx.c
new file mode 100644
index 0000000000..194f60d018
--- /dev/null
+++ b/system/STM32C0xx/system_stm32c0xx.c
@@ -0,0 +1,214 @@
+/**
+ ******************************************************************************
+ * @file system_stm32c0xx.c
+ * @author MCD Application Team
+ * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Source File
+ *
+ * This file provides two functions and one global variable to be called from
+ * user application:
+ * - SystemInit(): This function is called at startup just after reset and
+ * before branch to main program. This call is made inside
+ * the "startup_stm32c0xx.s" file.
+ *
+ * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+ * by the user application to setup the SysTick
+ * timer or configure other parameters.
+ *
+ * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+ * be called whenever the core clock is changed
+ * during program execution.
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2022 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32c0xx_system
+ * @{
+ */
+
+/** @addtogroup STM32C0xx_System_Private_Includes
+ * @{
+ */
+
+#include "stm32c0xx.h"
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32C0xx_System_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32C0xx_System_Private_Defines
+ * @{
+ */
+
+/************************* Miscellaneous Configuration ************************/
+/*!< Uncomment the following line if you need to relocate your vector Table in
+ Internal SRAM. */
+//#define VECT_TAB_SRAM
+#ifndef VECT_TAB_OFFSET
+#define VECT_TAB_OFFSET 0x0U /*!< Vector Table base offset field.
+ This value must be a multiple of 0x100. */
+#endif
+/******************************************************************************/
+/**
+ * @}
+ */
+
+/** @addtogroup STM32C0xx_System_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32C0xx_System_Private_Variables
+ * @{
+ */
+ /* The SystemCoreClock variable is updated in three ways:
+ 1) by calling CMSIS function SystemCoreClockUpdate()
+ 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+ 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+ Note: If you use this function to configure the system clock; then there
+ is no need to call the 2 first functions listed above, since SystemCoreClock
+ variable is updated automatically.
+ */
+ uint32_t SystemCoreClock = 48000000UL;
+
+ const uint32_t AHBPrescTable[16UL] = {0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL, 6UL, 7UL, 8UL, 9UL};
+ const uint32_t APBPrescTable[8UL] = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32C0xx_System_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32C0xx_System_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Setup the microcontroller system.
+ * @param None
+ * @retval None
+ */
+void SystemInit(void)
+{
+
+ /* Configure the Vector Table location add offset address ------------------*/
+#ifdef VECT_TAB_SRAM
+ SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+ SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+#endif
+}
+
+/**
+ * @brief Update SystemCoreClock variable according to Clock Register Values.
+ * The SystemCoreClock variable contains the core clock (HCLK), it can
+ * be used by the user application to setup the SysTick timer or configure
+ * other parameters.
+ *
+ * @note Each time the core clock (HCLK) changes, this function must be called
+ * to update SystemCoreClock variable value. Otherwise, any configuration
+ * based on this variable will be incorrect.
+ *
+ * @note - The system frequency computed by this function is not the real
+ * frequency in the chip. It is calculated based on the predefined
+ * constant and the selected clock source:
+ *
+ * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**) / HSI division factor
+ *
+ * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+ *
+ * - If SYSCLK source is LSI, SystemCoreClock will contain the LSI_VALUE
+ *
+ * - If SYSCLK source is LSE, SystemCoreClock will contain the LSE_VALUE
+ *
+ * (**) HSI_VALUE is a constant defined in stm32c0xx_hal_conf.h file (default value
+ * 48 MHz) but the real value may vary depending on the variations
+ * in voltage and temperature.
+ *
+ * (***) HSE_VALUE is a constant defined in stm32c0xx_hal_conf.h file (default value
+ * 48 MHz), user has to ensure that HSE_VALUE is same as the real
+ * frequency of the crystal used. Otherwise, this function may
+ * have wrong result.
+ *
+ * - The result of this function could be not correct when using fractional
+ * value for HSE crystal.
+ *
+ * @param None
+ * @retval None
+ */
+void SystemCoreClockUpdate(void)
+{
+ uint32_t tmp;
+ uint32_t hsidiv;
+
+ /* Get SYSCLK source -------------------------------------------------------*/
+ switch (RCC->CFGR & RCC_CFGR_SWS)
+ {
+ case RCC_CFGR_SWS_0: /* HSE used as system clock */
+ SystemCoreClock = HSE_VALUE;
+ break;
+
+ case (RCC_CFGR_SWS_1 | RCC_CFGR_SWS_0): /* LSI used as system clock */
+ SystemCoreClock = LSI_VALUE;
+ break;
+
+ case RCC_CFGR_SWS_2: /* LSE used as system clock */
+ SystemCoreClock = LSE_VALUE;
+ break;
+
+ case 0x00000000U: /* HSI used as system clock */
+ default: /* HSI used as system clock */
+ hsidiv = (1UL << ((READ_BIT(RCC->CR, RCC_CR_HSIDIV))>> RCC_CR_HSIDIV_Pos));
+ SystemCoreClock = (HSI_VALUE/hsidiv);
+ break;
+ }
+ /* Compute HCLK clock frequency --------------------------------------------*/
+ /* Get HCLK prescaler */
+ tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
+ /* HCLK clock frequency */
+ SystemCoreClock >>= tmp;
+}
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/variants/STM32C0xx/C011D6Y_C011F(4-6)(P-U)_C031F(4-6)P/PeripheralPins.c b/variants/STM32C0xx/C011D6Y_C011F(4-6)(P-U)_C031F(4-6)P/PeripheralPins.c
new file mode 100644
index 0000000000..34db234d9d
--- /dev/null
+++ b/variants/STM32C0xx/C011D6Y_C011F(4-6)(P-U)_C031F(4-6)P/PeripheralPins.c
@@ -0,0 +1,228 @@
+/*
+ *******************************************************************************
+ * Copyright (c) 2020, STMicroelectronics
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+/*
+ * Automatically generated from STM32C011D6Yx.xml, STM32C011F(4-6)Px.xml
+ * STM32C011F(4-6)Ux.xml, STM32C031F(4-6)Px.xml
+ * CubeMX DB release 6.0.70
+ */
+#if !defined(CUSTOM_PERIPHERAL_PINS)
+#include "Arduino.h"
+#include "PeripheralPins.h"
+
+/* =====
+ * Notes:
+ * - The pins mentioned Px_y_ALTz are alternative possibilities which use other
+ * HW peripheral instances. You can use them the same way as any other "normal"
+ * pin (i.e. analogWrite(PA7_ALT1, 128);).
+ *
+ * - Commented lines are alternative possibilities which are not used per default.
+ * If you change them, you will have to know what you do
+ * =====
+ */
+
+//*** ADC ***
+
+#ifdef HAL_ADC_MODULE_ENABLED
+WEAK const PinMap PinMap_ADC[] = {
+ {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_IN0
+ {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1
+ {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2
+ {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3
+ {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4
+ {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5
+ {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6
+ {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7
+ {PA_8, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8
+ {PA_11, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11
+ {PA_12, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12
+ {PA_13, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13
+ {PA_14, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14
+ {NC, NP, 0}
+};
+#endif
+
+//*** No DAC ***
+
+//*** I2C ***
+
+#ifdef HAL_I2C_MODULE_ENABLED
+WEAK const PinMap PinMap_I2C_SDA[] = {
+ {PA_10_R, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C1)},
+ {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C1)},
+ {PC_14, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF14_I2C1)},
+ {NC, NP, 0}
+};
+#endif
+
+#ifdef HAL_I2C_MODULE_ENABLED
+WEAK const PinMap PinMap_I2C_SCL[] = {
+ {PA_9_R, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C1)},
+ {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C1)},
+ {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF14_I2C1)},
+ {NC, NP, 0}
+};
+#endif
+
+//*** TIM ***
+
+#ifdef HAL_TIM_MODULE_ENABLED
+WEAK const PinMap PinMap_TIM[] = {
+ {PA_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM1, 1, 0)}, // TIM1_CH1
+ {PA_0_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM16, 1, 0)}, // TIM16_CH1
+ {PA_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM1, 2, 0)}, // TIM1_CH2
+ {PA_1_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM17, 1, 0)}, // TIM17_CH1
+ {PA_2, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM1, 3, 0)}, // TIM1_CH3
+ {PA_2_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM16, 1, 1)}, // TIM16_CH1N
+ {PA_3, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 1, 1)}, // TIM1_CH1N
+ {PA_3_ALT1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM1, 4, 0)}, // TIM1_CH4
+ {PA_4, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 2, 1)}, // TIM1_CH2N
+ {PA_4_ALT1, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM14, 1, 0)}, // TIM14_CH1
+ {PA_4_ALT2, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM17, 1, 1)}, // TIM17_CH1N
+ {PA_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM1, 1, 0)}, // TIM1_CH1
+ {PA_5_ALT1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 3, 1)}, // TIM1_CH3N
+ {PA_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 1, 0)}, // TIM3_CH1
+ {PA_6_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM16, 1, 0)}, // TIM16_CH1
+ {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 1, 1)}, // TIM1_CH1N
+ {PA_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 2, 0)}, // TIM3_CH2
+ {PA_7_ALT2, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM14, 1, 0)}, // TIM14_CH1
+ {PA_7_ALT3, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM17, 1, 0)}, // TIM17_CH1
+ {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 1, 0)}, // TIM1_CH1
+ {PA_8_ALT1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM1, 2, 1)}, // TIM1_CH2N
+ {PA_8_ALT2, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM1, 3, 1)}, // TIM1_CH3N
+ {PA_8_ALT3, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_TIM3, 3, 0)}, // TIM3_CH3
+ {PA_8_ALT4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_TIM3, 4, 0)}, // TIM3_CH4
+ {PA_8_ALT5, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF13_TIM14, 1, 0)}, // TIM14_CH1
+ {PA_9_R, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 2, 0)}, // TIM1_CH2
+ {PA_10_R, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 3, 0)}, // TIM1_CH3
+ {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 4, 0)}, // TIM1_CH4
+ {PA_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM1, 1, 0)}, // TIM1_CH1
+ {PB_6, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_TIM1, 2, 0)}, // TIM1_CH2
+ {PB_6_ALT1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3
+ {PB_6_ALT2, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_TIM3, 1, 0)}, // TIM3_CH1
+ {PB_6_ALT3, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF13_TIM3, 2, 0)}, // TIM3_CH2
+ {PB_6_ALT4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM3, 3, 0)}, // TIM3_CH3
+ {PB_6_ALT5, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM16, 1, 1)}, // TIM16_CH1N
+ {PB_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4
+ {PB_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_TIM3, 1, 0)}, // TIM3_CH1
+ {PB_7_ALT2, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM3, 4, 0)}, // TIM3_CH4
+ {PB_7_ALT3, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM16, 1, 0)}, // TIM16_CH1
+ {PB_7_ALT4, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM17, 1, 1)}, // TIM17_CH1N
+ {PC_14, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_TIM3, 2, 0)}, // TIM3_CH2
+ {PC_14_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM17, 1, 0)}, // TIM17_CH1
+ {PC_15, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM3, 3, 0)}, // TIM3_CH3
+ {PF_2, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4
+ {NC, NP, 0}
+};
+#endif
+
+//*** UART ***
+
+#ifdef HAL_UART_MODULE_ENABLED
+WEAK const PinMap PinMap_UART_TX[] = {
+ {PA_0, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)},
+ {PA_2, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)},
+ {PA_4, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)},
+ {PA_8, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)},
+ {PA_9_R, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)},
+ {PA_14, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)},
+ {PB_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)},
+ {PC_14, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)},
+ {NC, NP, 0}
+};
+#endif
+
+#ifdef HAL_UART_MODULE_ENABLED
+WEAK const PinMap PinMap_UART_RX[] = {
+ {PA_1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)},
+ {PA_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)},
+ {PA_5, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)},
+ {PA_8, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_USART1)},
+ {PA_10_R, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)},
+ {PA_13, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)},
+ {PA_14, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_USART2)},
+ {PB_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)},
+ {NC, NP, 0}
+};
+#endif
+
+#ifdef HAL_UART_MODULE_ENABLED
+WEAK const PinMap PinMap_UART_RTS[] = {
+ {PA_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)},
+ {PA_12, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)},
+ {PA_14, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_USART1)},
+ {PB_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)},
+ {PC_14, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_USART2)},
+ {NC, NP, 0}
+};
+#endif
+
+#ifdef HAL_UART_MODULE_ENABLED
+WEAK const PinMap PinMap_UART_CTS[] = {
+ {PA_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)},
+ {PA_11, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)},
+ {PB_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_USART1)},
+ {PB_7, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_USART2)},
+ {NC, NP, 0}
+};
+#endif
+
+//*** SPI ***
+
+#ifdef HAL_SPI_MODULE_ENABLED
+WEAK const PinMap PinMap_SPI_MOSI[] = {
+ {PA_2, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
+ {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
+ {PA_12, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
+ {PB_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI1)},
+ {NC, NP, 0}
+};
+#endif
+
+#ifdef HAL_SPI_MODULE_ENABLED
+WEAK const PinMap PinMap_SPI_MISO[] = {
+ {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
+ {PA_11, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
+ {PB_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_SPI1)},
+ {NC, NP, 0}
+};
+#endif
+
+#ifdef HAL_SPI_MODULE_ENABLED
+WEAK const PinMap PinMap_SPI_SCLK[] = {
+ {PA_1, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
+ {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
+ {PB_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SPI1)},
+ {NC, NP, 0}
+};
+#endif
+
+#ifdef HAL_SPI_MODULE_ENABLED
+WEAK const PinMap PinMap_SPI_SSEL[] = {
+ {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
+ {PA_8, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI1)},
+ {PA_14, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI1)},
+ {NC, NP, 0}
+};
+#endif
+
+//*** No CAN ***
+
+//*** No ETHERNET ***
+
+//*** No QUADSPI ***
+
+//*** No USB ***
+
+//*** No SD ***
+
+#endif /* !CUSTOM_PERIPHERAL_PINS */
diff --git a/variants/STM32C0xx/C011D6Y_C011F(4-6)(P-U)_C031F(4-6)P/PinNamesVar.h b/variants/STM32C0xx/C011D6Y_C011F(4-6)(P-U)_C031F(4-6)P/PinNamesVar.h
new file mode 100644
index 0000000000..279477859b
--- /dev/null
+++ b/variants/STM32C0xx/C011D6Y_C011F(4-6)(P-U)_C031F(4-6)P/PinNamesVar.h
@@ -0,0 +1,59 @@
+/* Remap pin name */
+PA_9_R = PA_9 | PREMAP,
+PA_10_R = PA_10 | PREMAP,
+
+/* Alternate pin name */
+PA_0_ALT1 = PA_0 | ALT1,
+PA_1_ALT1 = PA_1 | ALT1,
+PA_2_ALT1 = PA_2 | ALT1,
+PA_3_ALT1 = PA_3 | ALT1,
+PA_4_ALT1 = PA_4 | ALT1,
+PA_4_ALT2 = PA_4 | ALT2,
+PA_5_ALT1 = PA_5 | ALT1,
+PA_6_ALT1 = PA_6 | ALT1,
+PA_7_ALT1 = PA_7 | ALT1,
+PA_7_ALT2 = PA_7 | ALT2,
+PA_7_ALT3 = PA_7 | ALT3,
+PA_8_ALT1 = PA_8 | ALT1,
+PA_8_ALT2 = PA_8 | ALT2,
+PA_8_ALT3 = PA_8 | ALT3,
+PA_8_ALT4 = PA_8 | ALT4,
+PA_8_ALT5 = PA_8 | ALT5,
+PB_6_ALT1 = PB_6 | ALT1,
+PB_6_ALT2 = PB_6 | ALT2,
+PB_6_ALT3 = PB_6 | ALT3,
+PB_6_ALT4 = PB_6 | ALT4,
+PB_6_ALT5 = PB_6 | ALT5,
+PB_7_ALT1 = PB_7 | ALT1,
+PB_7_ALT2 = PB_7 | ALT2,
+PB_7_ALT3 = PB_7 | ALT3,
+PB_7_ALT4 = PB_7 | ALT4,
+PC_14_ALT1 = PC_14 | ALT1,
+
+/* SYS_WKUP */
+#ifdef PWR_WAKEUP_PIN1
+ SYS_WKUP1 = PA_0,
+#endif
+#ifdef PWR_WAKEUP_PIN2
+ SYS_WKUP2 = PA_4,
+#endif
+#ifdef PWR_WAKEUP_PIN3
+ SYS_WKUP3 = PB_6,
+#endif
+#ifdef PWR_WAKEUP_PIN4
+ SYS_WKUP4 = PA_2,
+#endif
+#ifdef PWR_WAKEUP_PIN5
+ SYS_WKUP5 = NC,
+#endif
+#ifdef PWR_WAKEUP_PIN6
+ SYS_WKUP6 = NC,
+#endif
+#ifdef PWR_WAKEUP_PIN7
+ SYS_WKUP7 = NC,
+#endif
+#ifdef PWR_WAKEUP_PIN8
+ SYS_WKUP8 = NC,
+#endif
+
+/* No USB */
diff --git a/variants/STM32C0xx/C011D6Y_C011F(4-6)(P-U)_C031F(4-6)P/boards_entry.txt b/variants/STM32C0xx/C011D6Y_C011F(4-6)(P-U)_C031F(4-6)P/boards_entry.txt
new file mode 100644
index 0000000000..b22cab3ba3
--- /dev/null
+++ b/variants/STM32C0xx/C011D6Y_C011F(4-6)(P-U)_C031F(4-6)P/boards_entry.txt
@@ -0,0 +1,61 @@
+# This file help to add generic board entry.
+# upload.maximum_size and product_line have to be verified
+# and changed if needed.
+# See: https://github.com/stm32duino/wiki/wiki/Add-a-new-variant-%28board%29
+
+# Generic C011D6Yx
+GenC0.menu.pnum.GENERIC_C011D6YX=Generic C011D6Yx
+GenC0.menu.pnum.GENERIC_C011D6YX.upload.maximum_size=32768
+GenC0.menu.pnum.GENERIC_C011D6YX.upload.maximum_data_size=6144
+GenC0.menu.pnum.GENERIC_C011D6YX.build.board=GENERIC_C011D6YX
+GenC0.menu.pnum.GENERIC_C011D6YX.build.product_line=STM32C011xx
+GenC0.menu.pnum.GENERIC_C011D6YX.build.variant=STM32C0xx/C011D6Y_C011F(4-6)(P-U)_C031F(4-6)P
+
+# Generic C011F4Px
+GenC0.menu.pnum.GENERIC_C011F4PX=Generic C011F4Px
+GenC0.menu.pnum.GENERIC_C011F4PX.upload.maximum_size=16384
+GenC0.menu.pnum.GENERIC_C011F4PX.upload.maximum_data_size=6144
+GenC0.menu.pnum.GENERIC_C011F4PX.build.board=GENERIC_C011F4PX
+GenC0.menu.pnum.GENERIC_C011F4PX.build.product_line=STM32C011xx
+GenC0.menu.pnum.GENERIC_C011F4PX.build.variant=STM32C0xx/C011D6Y_C011F(4-6)(P-U)_C031F(4-6)P
+
+# Generic C011F6Px
+GenC0.menu.pnum.GENERIC_C011F6PX=Generic C011F6Px
+GenC0.menu.pnum.GENERIC_C011F6PX.upload.maximum_size=32768
+GenC0.menu.pnum.GENERIC_C011F6PX.upload.maximum_data_size=6144
+GenC0.menu.pnum.GENERIC_C011F6PX.build.board=GENERIC_C011F6PX
+GenC0.menu.pnum.GENERIC_C011F6PX.build.product_line=STM32C011xx
+GenC0.menu.pnum.GENERIC_C011F6PX.build.variant=STM32C0xx/C011D6Y_C011F(4-6)(P-U)_C031F(4-6)P
+
+# Generic C011F4Ux
+GenC0.menu.pnum.GENERIC_C011F4UX=Generic C011F4Ux
+GenC0.menu.pnum.GENERIC_C011F4UX.upload.maximum_size=16384
+GenC0.menu.pnum.GENERIC_C011F4UX.upload.maximum_data_size=6144
+GenC0.menu.pnum.GENERIC_C011F4UX.build.board=GENERIC_C011F4UX
+GenC0.menu.pnum.GENERIC_C011F4UX.build.product_line=STM32C011xx
+GenC0.menu.pnum.GENERIC_C011F4UX.build.variant=STM32C0xx/C011D6Y_C011F(4-6)(P-U)_C031F(4-6)P
+
+# Generic C011F6Ux
+GenC0.menu.pnum.GENERIC_C011F6UX=Generic C011F6Ux
+GenC0.menu.pnum.GENERIC_C011F6UX.upload.maximum_size=32768
+GenC0.menu.pnum.GENERIC_C011F6UX.upload.maximum_data_size=6144
+GenC0.menu.pnum.GENERIC_C011F6UX.build.board=GENERIC_C011F6UX
+GenC0.menu.pnum.GENERIC_C011F6UX.build.product_line=STM32C011xx
+GenC0.menu.pnum.GENERIC_C011F6UX.build.variant=STM32C0xx/C011D6Y_C011F(4-6)(P-U)_C031F(4-6)P
+
+# Generic C031F4Px
+GenC0.menu.pnum.GENERIC_C031F4PX=Generic C031F4Px
+GenC0.menu.pnum.GENERIC_C031F4PX.upload.maximum_size=16384
+GenC0.menu.pnum.GENERIC_C031F4PX.upload.maximum_data_size=12288
+GenC0.menu.pnum.GENERIC_C031F4PX.build.board=GENERIC_C031F4PX
+GenC0.menu.pnum.GENERIC_C031F4PX.build.product_line=STM32C031xx
+GenC0.menu.pnum.GENERIC_C031F4PX.build.variant=STM32C0xx/C011D6Y_C011F(4-6)(P-U)_C031F(4-6)P
+
+# Generic C031F6Px
+GenC0.menu.pnum.GENERIC_C031F6PX=Generic C031F6Px
+GenC0.menu.pnum.GENERIC_C031F6PX.upload.maximum_size=32768
+GenC0.menu.pnum.GENERIC_C031F6PX.upload.maximum_data_size=12288
+GenC0.menu.pnum.GENERIC_C031F6PX.build.board=GENERIC_C031F6PX
+GenC0.menu.pnum.GENERIC_C031F6PX.build.product_line=STM32C031xx
+GenC0.menu.pnum.GENERIC_C031F6PX.build.variant=STM32C0xx/C011D6Y_C011F(4-6)(P-U)_C031F(4-6)P
+
diff --git a/variants/STM32C0xx/C011D6Y_C011F(4-6)(P-U)_C031F(4-6)P/generic_clock.c b/variants/STM32C0xx/C011D6Y_C011F(4-6)(P-U)_C031F(4-6)P/generic_clock.c
new file mode 100644
index 0000000000..93cb896aa0
--- /dev/null
+++ b/variants/STM32C0xx/C011D6Y_C011F(4-6)(P-U)_C031F(4-6)P/generic_clock.c
@@ -0,0 +1,30 @@
+/*
+ *******************************************************************************
+ * Copyright (c) 2020, STMicroelectronics
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+#if defined(ARDUINO_GENERIC_C011D6YX) || defined(ARDUINO_GENERIC_C011F4PX) ||\
+ defined(ARDUINO_GENERIC_C011F4UX) || defined(ARDUINO_GENERIC_C011F6PX) ||\
+ defined(ARDUINO_GENERIC_C011F6UX) || defined(ARDUINO_GENERIC_C031F4PX) ||\
+ defined(ARDUINO_GENERIC_C031F6PX)
+#include "pins_arduino.h"
+
+/**
+ * @brief System Clock Configuration
+ * @param None
+ * @retval None
+ */
+WEAK void SystemClock_Config(void)
+{
+ /* SystemClock_Config can be generated by STM32CubeMX */
+#warning "SystemClock_Config() is empty. Default clock at reset is used."
+}
+
+#endif /* ARDUINO_GENERIC_* */
diff --git a/variants/STM32C0xx/C011D6Y_C011F(4-6)(P-U)_C031F(4-6)P/variant_generic.cpp b/variants/STM32C0xx/C011D6Y_C011F(4-6)(P-U)_C031F(4-6)P/variant_generic.cpp
new file mode 100644
index 0000000000..b876310983
--- /dev/null
+++ b/variants/STM32C0xx/C011D6Y_C011F(4-6)(P-U)_C031F(4-6)P/variant_generic.cpp
@@ -0,0 +1,60 @@
+/*
+ *******************************************************************************
+ * Copyright (c) 2020, STMicroelectronics
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+#if defined(ARDUINO_GENERIC_C011D6YX) || defined(ARDUINO_GENERIC_C011F4PX) ||\
+ defined(ARDUINO_GENERIC_C011F4UX) || defined(ARDUINO_GENERIC_C011F6PX) ||\
+ defined(ARDUINO_GENERIC_C011F6UX) || defined(ARDUINO_GENERIC_C031F4PX) ||\
+ defined(ARDUINO_GENERIC_C031F6PX)
+#include "pins_arduino.h"
+
+// Digital PinName array
+const PinName digitalPin[] = {
+ PA_0, // D0/A0
+ PA_1, // D1/A1
+ PA_2, // D2/A2
+ PA_3, // D3/A3
+ PA_4, // D4/A4
+ PA_5, // D5/A5
+ PA_6, // D6/A6
+ PA_7, // D7/A7
+ PA_8, // D8/A8
+ PA_11, // D9/A9
+ PA_12, // D10/A10
+ PA_13, // D11/A11
+ PA_14, // D12/A12
+ PB_6, // D13
+ PB_7, // D14
+ PC_14, // D15
+ PC_15, // D16
+ PF_2, // D17
+ PA_9_R, // D18
+ PA_10_R // D19
+};
+
+// Analog (Ax) pin number array
+const uint32_t analogInputPin[] = {
+ 0, // A0, PA0
+ 1, // A1, PA1
+ 2, // A2, PA2
+ 3, // A3, PA3
+ 4, // A4, PA4
+ 5, // A5, PA5
+ 6, // A6, PA6
+ 7, // A7, PA7
+ 8, // A8, PA8
+ 9, // A9, PA11
+ 10, // A10, PA12
+ 11, // A11, PA13
+ 12 // A12, PA14
+};
+
+#endif /* ARDUINO_GENERIC_* */
diff --git a/variants/STM32C0xx/C011D6Y_C011F(4-6)(P-U)_C031F(4-6)P/variant_generic.h b/variants/STM32C0xx/C011D6Y_C011F(4-6)(P-U)_C031F(4-6)P/variant_generic.h
new file mode 100644
index 0000000000..19778f9b5b
--- /dev/null
+++ b/variants/STM32C0xx/C011D6Y_C011F(4-6)(P-U)_C031F(4-6)P/variant_generic.h
@@ -0,0 +1,161 @@
+/*
+ *******************************************************************************
+ * Copyright (c) 2020, STMicroelectronics
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+#pragma once
+
+/*----------------------------------------------------------------------------
+ * STM32 pins number
+ *----------------------------------------------------------------------------*/
+#define PA0 PIN_A0
+#define PA1 PIN_A1
+#define PA2 PIN_A2
+#define PA3 PIN_A3
+#define PA4 PIN_A4
+#define PA5 PIN_A5
+#define PA6 PIN_A6
+#define PA7 PIN_A7
+#define PA8 PIN_A8
+#define PA11 PIN_A9
+#define PA12 PIN_A10
+#define PA13 PIN_A11
+#define PA14 PIN_A12
+#define PB6 13
+#define PB7 14
+#define PC14 15
+#define PC15 16
+#define PF2 17
+#define PA9_R 18
+#define PA10_R 19
+
+// Alternate pins number
+#define PA0_ALT1 (PA0 | ALT1)
+#define PA1_ALT1 (PA1 | ALT1)
+#define PA2_ALT1 (PA2 | ALT1)
+#define PA3_ALT1 (PA3 | ALT1)
+#define PA4_ALT1 (PA4 | ALT1)
+#define PA4_ALT2 (PA4 | ALT2)
+#define PA5_ALT1 (PA5 | ALT1)
+#define PA6_ALT1 (PA6 | ALT1)
+#define PA7_ALT1 (PA7 | ALT1)
+#define PA7_ALT2 (PA7 | ALT2)
+#define PA7_ALT3 (PA7 | ALT3)
+#define PA8_ALT1 (PA8 | ALT1)
+#define PA8_ALT2 (PA8 | ALT2)
+#define PA8_ALT3 (PA8 | ALT3)
+#define PA8_ALT4 (PA8 | ALT4)
+#define PA8_ALT5 (PA8 | ALT5)
+#define PB6_ALT1 (PB6 | ALT1)
+#define PB6_ALT2 (PB6 | ALT2)
+#define PB6_ALT3 (PB6 | ALT3)
+#define PB6_ALT4 (PB6 | ALT4)
+#define PB6_ALT5 (PB6 | ALT5)
+#define PB7_ALT1 (PB7 | ALT1)
+#define PB7_ALT2 (PB7 | ALT2)
+#define PB7_ALT3 (PB7 | ALT3)
+#define PB7_ALT4 (PB7 | ALT4)
+#define PC14_ALT1 (PC14 | ALT1)
+
+#define NUM_DIGITAL_PINS 20
+#define NUM_REMAP_PINS 2
+#define NUM_ANALOG_INPUTS 13
+
+// On-board LED pin number
+#ifndef LED_BUILTIN
+ #define LED_BUILTIN PNUM_NOT_DEFINED
+#endif
+
+// On-board user button
+#ifndef USER_BTN
+ #define USER_BTN PNUM_NOT_DEFINED
+#endif
+
+// SPI definitions
+#ifndef PIN_SPI_SS
+ #define PIN_SPI_SS PA4
+#endif
+#ifndef PIN_SPI_SS1
+ #define PIN_SPI_SS1 PA8
+#endif
+#ifndef PIN_SPI_SS2
+ #define PIN_SPI_SS2 PA14
+#endif
+#ifndef PIN_SPI_SS3
+ #define PIN_SPI_SS3 PNUM_NOT_DEFINED
+#endif
+#ifndef PIN_SPI_MOSI
+ #define PIN_SPI_MOSI PA2
+#endif
+#ifndef PIN_SPI_MISO
+ #define PIN_SPI_MISO PA6
+#endif
+#ifndef PIN_SPI_SCK
+ #define PIN_SPI_SCK PA1
+#endif
+
+// I2C definitions
+#ifndef PIN_WIRE_SDA
+ #define PIN_WIRE_SDA PA10_R
+#endif
+#ifndef PIN_WIRE_SCL
+ #define PIN_WIRE_SCL PA9_R
+#endif
+
+// Timer Definitions
+// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin
+#ifndef TIMER_TONE
+ #define TIMER_TONE TIM14
+#endif
+#ifndef TIMER_SERVO
+ #define TIMER_SERVO TIM16
+#endif
+
+// UART Definitions
+#ifndef SERIAL_UART_INSTANCE
+ #define SERIAL_UART_INSTANCE 1
+#endif
+
+// Default pin used for generic 'Serial' instance
+// Mandatory for Firmata
+#ifndef PIN_SERIAL_RX
+ #define PIN_SERIAL_RX PA1
+#endif
+#ifndef PIN_SERIAL_TX
+ #define PIN_SERIAL_TX PA0
+#endif
+
+/*----------------------------------------------------------------------------
+ * Arduino objects - C++ only
+ *----------------------------------------------------------------------------*/
+
+#ifdef __cplusplus
+ // These serial port names are intended to allow libraries and architecture-neutral
+ // sketches to automatically default to the correct port name for a particular type
+ // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN,
+ // the first hardware serial port whose RX/TX pins are not dedicated to another use.
+ //
+ // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor
+ //
+ // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial
+ //
+ // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library
+ //
+ // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins.
+ //
+ // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX
+ // pins are NOT connected to anything by default.
+ #ifndef SERIAL_PORT_MONITOR
+ #define SERIAL_PORT_MONITOR Serial
+ #endif
+ #ifndef SERIAL_PORT_HARDWARE
+ #define SERIAL_PORT_HARDWARE Serial
+ #endif
+#endif
diff --git a/variants/STM32C0xx/C011J(4-6)M/PeripheralPins.c b/variants/STM32C0xx/C011J(4-6)M/PeripheralPins.c
new file mode 100644
index 0000000000..f2e67f0580
--- /dev/null
+++ b/variants/STM32C0xx/C011J(4-6)M/PeripheralPins.c
@@ -0,0 +1,202 @@
+/*
+ *******************************************************************************
+ * Copyright (c) 2020, STMicroelectronics
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+/*
+ * Automatically generated from STM32C011J(4-6)Mx.xml
+ * CubeMX DB release 6.0.70
+ */
+#if !defined(CUSTOM_PERIPHERAL_PINS)
+#include "Arduino.h"
+#include "PeripheralPins.h"
+
+/* =====
+ * Notes:
+ * - The pins mentioned Px_y_ALTz are alternative possibilities which use other
+ * HW peripheral instances. You can use them the same way as any other "normal"
+ * pin (i.e. analogWrite(PA7_ALT1, 128);).
+ *
+ * - Commented lines are alternative possibilities which are not used per default.
+ * If you change them, you will have to know what you do
+ * =====
+ */
+
+//*** ADC ***
+
+#ifdef HAL_ADC_MODULE_ENABLED
+WEAK const PinMap PinMap_ADC[] = {
+ {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_IN0
+ {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1
+ {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2
+ {PA_8, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8
+ {PA_11, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11
+ {PA_12, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12
+ {PA_13, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13
+ {PA_14, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14
+ {NC, NP, 0}
+};
+#endif
+
+//*** No DAC ***
+
+//*** I2C ***
+
+#ifdef HAL_I2C_MODULE_ENABLED
+WEAK const PinMap PinMap_I2C_SDA[] = {
+ {PA_10_R, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C1)},
+ {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C1)},
+ {PC_14, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF14_I2C1)},
+ {NC, NP, 0}
+};
+#endif
+
+#ifdef HAL_I2C_MODULE_ENABLED
+WEAK const PinMap PinMap_I2C_SCL[] = {
+ {PA_9_R, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C1)},
+ {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C1)},
+ {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF14_I2C1)},
+ {NC, NP, 0}
+};
+#endif
+
+//*** TIM ***
+
+#ifdef HAL_TIM_MODULE_ENABLED
+WEAK const PinMap PinMap_TIM[] = {
+ {PA_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM1, 1, 0)}, // TIM1_CH1
+ {PA_0_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM16, 1, 0)}, // TIM16_CH1
+ {PA_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM1, 2, 0)}, // TIM1_CH2
+ {PA_1_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM17, 1, 0)}, // TIM17_CH1
+ {PA_2, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM1, 3, 0)}, // TIM1_CH3
+ {PA_2_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM16, 1, 1)}, // TIM16_CH1N
+ {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 1, 0)}, // TIM1_CH1
+ {PA_8_ALT1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM1, 2, 1)}, // TIM1_CH2N
+ {PA_8_ALT2, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM1, 3, 1)}, // TIM1_CH3N
+ {PA_8_ALT3, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_TIM3, 3, 0)}, // TIM3_CH3
+ {PA_8_ALT4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_TIM3, 4, 0)}, // TIM3_CH4
+ {PA_8_ALT5, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF13_TIM14, 1, 0)}, // TIM14_CH1
+ {PA_9_R, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 2, 0)}, // TIM1_CH2
+ {PA_10_R, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 3, 0)}, // TIM1_CH3
+ {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 4, 0)}, // TIM1_CH4
+ {PA_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM1, 1, 0)}, // TIM1_CH1
+ {PB_6, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_TIM1, 2, 0)}, // TIM1_CH2
+ {PB_6_ALT1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3
+ {PB_6_ALT2, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_TIM3, 1, 0)}, // TIM3_CH1
+ {PB_6_ALT3, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF13_TIM3, 2, 0)}, // TIM3_CH2
+ {PB_6_ALT4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM3, 3, 0)}, // TIM3_CH3
+ {PB_6_ALT5, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM16, 1, 1)}, // TIM16_CH1N
+ {PB_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4
+ {PB_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_TIM3, 1, 0)}, // TIM3_CH1
+ {PB_7_ALT2, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM3, 4, 0)}, // TIM3_CH4
+ {PB_7_ALT3, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM16, 1, 0)}, // TIM16_CH1
+ {PB_7_ALT4, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM17, 1, 1)}, // TIM17_CH1N
+ {PC_14, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_TIM3, 2, 0)}, // TIM3_CH2
+ {PC_14_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM17, 1, 0)}, // TIM17_CH1
+ {PC_15, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM3, 3, 0)}, // TIM3_CH3
+ {PF_2, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4
+ {NC, NP, 0}
+};
+#endif
+
+//*** UART ***
+
+#ifdef HAL_UART_MODULE_ENABLED
+WEAK const PinMap PinMap_UART_TX[] = {
+ {PA_0, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)},
+ {PA_2, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)},
+ {PA_8, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)},
+ {PA_9_R, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)},
+ {PA_14, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)},
+ {PB_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)},
+ {PC_14, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)},
+ {NC, NP, 0}
+};
+#endif
+
+#ifdef HAL_UART_MODULE_ENABLED
+WEAK const PinMap PinMap_UART_RX[] = {
+ {PA_1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)},
+ {PA_8, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_USART1)},
+ {PA_10_R, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)},
+ {PA_13, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)},
+ {PA_14, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_USART2)},
+ {PB_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)},
+ {NC, NP, 0}
+};
+#endif
+
+#ifdef HAL_UART_MODULE_ENABLED
+WEAK const PinMap PinMap_UART_RTS[] = {
+ {PA_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)},
+ {PA_12, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)},
+ {PA_14, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_USART1)},
+ {PB_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)},
+ {PC_14, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_USART2)},
+ {NC, NP, 0}
+};
+#endif
+
+#ifdef HAL_UART_MODULE_ENABLED
+WEAK const PinMap PinMap_UART_CTS[] = {
+ {PA_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)},
+ {PA_11, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)},
+ {PB_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_USART1)},
+ {PB_7, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_USART2)},
+ {NC, NP, 0}
+};
+#endif
+
+//*** SPI ***
+
+#ifdef HAL_SPI_MODULE_ENABLED
+WEAK const PinMap PinMap_SPI_MOSI[] = {
+ {PA_2, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
+ {PA_12, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
+ {PB_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI1)},
+ {NC, NP, 0}
+};
+#endif
+
+#ifdef HAL_SPI_MODULE_ENABLED
+WEAK const PinMap PinMap_SPI_MISO[] = {
+ {PA_11, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
+ {PB_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_SPI1)},
+ {NC, NP, 0}
+};
+#endif
+
+#ifdef HAL_SPI_MODULE_ENABLED
+WEAK const PinMap PinMap_SPI_SCLK[] = {
+ {PA_1, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
+ {PB_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SPI1)},
+ {NC, NP, 0}
+};
+#endif
+
+#ifdef HAL_SPI_MODULE_ENABLED
+WEAK const PinMap PinMap_SPI_SSEL[] = {
+ {PA_8, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI1)},
+ {PA_14, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI1)},
+ {NC, NP, 0}
+};
+#endif
+
+//*** No CAN ***
+
+//*** No ETHERNET ***
+
+//*** No QUADSPI ***
+
+//*** No USB ***
+
+//*** No SD ***
+
+#endif /* !CUSTOM_PERIPHERAL_PINS */
diff --git a/variants/STM32C0xx/C011J(4-6)M/PinNamesVar.h b/variants/STM32C0xx/C011J(4-6)M/PinNamesVar.h
new file mode 100644
index 0000000000..1bc0a76082
--- /dev/null
+++ b/variants/STM32C0xx/C011J(4-6)M/PinNamesVar.h
@@ -0,0 +1,51 @@
+/* Remap pin name */
+PA_9_R = PA_9 | PREMAP,
+PA_10_R = PA_10 | PREMAP,
+
+/* Alternate pin name */
+PA_0_ALT1 = PA_0 | ALT1,
+PA_1_ALT1 = PA_1 | ALT1,
+PA_2_ALT1 = PA_2 | ALT1,
+PA_8_ALT1 = PA_8 | ALT1,
+PA_8_ALT2 = PA_8 | ALT2,
+PA_8_ALT3 = PA_8 | ALT3,
+PA_8_ALT4 = PA_8 | ALT4,
+PA_8_ALT5 = PA_8 | ALT5,
+PB_6_ALT1 = PB_6 | ALT1,
+PB_6_ALT2 = PB_6 | ALT2,
+PB_6_ALT3 = PB_6 | ALT3,
+PB_6_ALT4 = PB_6 | ALT4,
+PB_6_ALT5 = PB_6 | ALT5,
+PB_7_ALT1 = PB_7 | ALT1,
+PB_7_ALT2 = PB_7 | ALT2,
+PB_7_ALT3 = PB_7 | ALT3,
+PB_7_ALT4 = PB_7 | ALT4,
+PC_14_ALT1 = PC_14 | ALT1,
+
+/* SYS_WKUP */
+#ifdef PWR_WAKEUP_PIN1
+ SYS_WKUP1 = PA_0,
+#endif
+#ifdef PWR_WAKEUP_PIN2
+ SYS_WKUP2 = NC,
+#endif
+#ifdef PWR_WAKEUP_PIN3
+ SYS_WKUP3 = PB_6,
+#endif
+#ifdef PWR_WAKEUP_PIN4
+ SYS_WKUP4 = PA_2,
+#endif
+#ifdef PWR_WAKEUP_PIN5
+ SYS_WKUP5 = NC,
+#endif
+#ifdef PWR_WAKEUP_PIN6
+ SYS_WKUP6 = NC,
+#endif
+#ifdef PWR_WAKEUP_PIN7
+ SYS_WKUP7 = NC,
+#endif
+#ifdef PWR_WAKEUP_PIN8
+ SYS_WKUP8 = NC,
+#endif
+
+/* No USB */
diff --git a/variants/STM32C0xx/C011J(4-6)M/boards_entry.txt b/variants/STM32C0xx/C011J(4-6)M/boards_entry.txt
new file mode 100644
index 0000000000..b0bef3c69a
--- /dev/null
+++ b/variants/STM32C0xx/C011J(4-6)M/boards_entry.txt
@@ -0,0 +1,21 @@
+# This file help to add generic board entry.
+# upload.maximum_size and product_line have to be verified
+# and changed if needed.
+# See: https://github.com/stm32duino/wiki/wiki/Add-a-new-variant-%28board%29
+
+# Generic C011J4Mx
+GenC0.menu.pnum.GENERIC_C011J4MX=Generic C011J4Mx
+GenC0.menu.pnum.GENERIC_C011J4MX.upload.maximum_size=16384
+GenC0.menu.pnum.GENERIC_C011J4MX.upload.maximum_data_size=6144
+GenC0.menu.pnum.GENERIC_C011J4MX.build.board=GENERIC_C011J4MX
+GenC0.menu.pnum.GENERIC_C011J4MX.build.product_line=STM32C011xx
+GenC0.menu.pnum.GENERIC_C011J4MX.build.variant=STM32C0xx/C011J(4-6)M
+
+# Generic C011J6Mx
+GenC0.menu.pnum.GENERIC_C011J6MX=Generic C011J6Mx
+GenC0.menu.pnum.GENERIC_C011J6MX.upload.maximum_size=32768
+GenC0.menu.pnum.GENERIC_C011J6MX.upload.maximum_data_size=6144
+GenC0.menu.pnum.GENERIC_C011J6MX.build.board=GENERIC_C011J6MX
+GenC0.menu.pnum.GENERIC_C011J6MX.build.product_line=STM32C011xx
+GenC0.menu.pnum.GENERIC_C011J6MX.build.variant=STM32C0xx/C011J(4-6)M
+
diff --git a/variants/STM32C0xx/C011J(4-6)M/generic_clock.c b/variants/STM32C0xx/C011J(4-6)M/generic_clock.c
new file mode 100644
index 0000000000..b8c94ff32c
--- /dev/null
+++ b/variants/STM32C0xx/C011J(4-6)M/generic_clock.c
@@ -0,0 +1,27 @@
+/*
+ *******************************************************************************
+ * Copyright (c) 2020, STMicroelectronics
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+#if defined(ARDUINO_GENERIC_C011J4MX) || defined(ARDUINO_GENERIC_C011J6MX)
+#include "pins_arduino.h"
+
+/**
+ * @brief System Clock Configuration
+ * @param None
+ * @retval None
+ */
+WEAK void SystemClock_Config(void)
+{
+ /* SystemClock_Config can be generated by STM32CubeMX */
+#warning "SystemClock_Config() is empty. Default clock at reset is used."
+}
+
+#endif /* ARDUINO_GENERIC_* */
diff --git a/variants/STM32C0xx/C011J(4-6)M/variant_generic.cpp b/variants/STM32C0xx/C011J(4-6)M/variant_generic.cpp
new file mode 100644
index 0000000000..145be0ff92
--- /dev/null
+++ b/variants/STM32C0xx/C011J(4-6)M/variant_generic.cpp
@@ -0,0 +1,47 @@
+/*
+ *******************************************************************************
+ * Copyright (c) 2020, STMicroelectronics
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+#if defined(ARDUINO_GENERIC_C011J4MX) || defined(ARDUINO_GENERIC_C011J6MX)
+#include "pins_arduino.h"
+
+// Digital PinName array
+const PinName digitalPin[] = {
+ PA_0, // D0/A0
+ PA_1, // D1/A1
+ PA_2, // D2/A2
+ PA_8, // D3/A3
+ PA_11, // D4/A4
+ PA_12, // D5/A5
+ PA_13, // D6/A6
+ PA_14, // D7/A7
+ PB_6, // D8
+ PB_7, // D9
+ PC_14, // D10
+ PC_15, // D11
+ PF_2, // D12
+ PA_9_R, // D13
+ PA_10_R // D14
+};
+
+// Analog (Ax) pin number array
+const uint32_t analogInputPin[] = {
+ 0, // A0, PA0
+ 1, // A1, PA1
+ 2, // A2, PA2
+ 3, // A3, PA8
+ 4, // A4, PA11
+ 5, // A5, PA12
+ 6, // A6, PA13
+ 7 // A7, PA14
+};
+
+#endif /* ARDUINO_GENERIC_* */
diff --git a/variants/STM32C0xx/C011J(4-6)M/variant_generic.h b/variants/STM32C0xx/C011J(4-6)M/variant_generic.h
new file mode 100644
index 0000000000..d07da3866b
--- /dev/null
+++ b/variants/STM32C0xx/C011J(4-6)M/variant_generic.h
@@ -0,0 +1,148 @@
+/*
+ *******************************************************************************
+ * Copyright (c) 2020, STMicroelectronics
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+#pragma once
+
+/*----------------------------------------------------------------------------
+ * STM32 pins number
+ *----------------------------------------------------------------------------*/
+#define PA0 PIN_A0
+#define PA1 PIN_A1
+#define PA2 PIN_A2
+#define PA8 PIN_A3
+#define PA11 PIN_A4
+#define PA12 PIN_A5
+#define PA13 PIN_A6
+#define PA14 PIN_A7
+#define PB6 8
+#define PB7 9
+#define PC14 10
+#define PC15 11
+#define PF2 12
+#define PA9_R 13
+#define PA10_R 14
+
+// Alternate pins number
+#define PA0_ALT1 (PA0 | ALT1)
+#define PA1_ALT1 (PA1 | ALT1)
+#define PA2_ALT1 (PA2 | ALT1)
+#define PA8_ALT1 (PA8 | ALT1)
+#define PA8_ALT2 (PA8 | ALT2)
+#define PA8_ALT3 (PA8 | ALT3)
+#define PA8_ALT4 (PA8 | ALT4)
+#define PA8_ALT5 (PA8 | ALT5)
+#define PB6_ALT1 (PB6 | ALT1)
+#define PB6_ALT2 (PB6 | ALT2)
+#define PB6_ALT3 (PB6 | ALT3)
+#define PB6_ALT4 (PB6 | ALT4)
+#define PB6_ALT5 (PB6 | ALT5)
+#define PB7_ALT1 (PB7 | ALT1)
+#define PB7_ALT2 (PB7 | ALT2)
+#define PB7_ALT3 (PB7 | ALT3)
+#define PB7_ALT4 (PB7 | ALT4)
+#define PC14_ALT1 (PC14 | ALT1)
+
+#define NUM_DIGITAL_PINS 15
+#define NUM_REMAP_PINS 2
+#define NUM_ANALOG_INPUTS 8
+
+// On-board LED pin number
+#ifndef LED_BUILTIN
+ #define LED_BUILTIN PNUM_NOT_DEFINED
+#endif
+
+// On-board user button
+#ifndef USER_BTN
+ #define USER_BTN PNUM_NOT_DEFINED
+#endif
+
+// SPI definitions
+#ifndef PIN_SPI_SS
+ #define PIN_SPI_SS PA8
+#endif
+#ifndef PIN_SPI_SS1
+ #define PIN_SPI_SS1 PA14
+#endif
+#ifndef PIN_SPI_SS2
+ #define PIN_SPI_SS2 PNUM_NOT_DEFINED
+#endif
+#ifndef PIN_SPI_SS3
+ #define PIN_SPI_SS3 PNUM_NOT_DEFINED
+#endif
+#ifndef PIN_SPI_MOSI
+ #define PIN_SPI_MOSI PA2
+#endif
+#ifndef PIN_SPI_MISO
+ #define PIN_SPI_MISO PA11
+#endif
+#ifndef PIN_SPI_SCK
+ #define PIN_SPI_SCK PA1
+#endif
+
+// I2C definitions
+#ifndef PIN_WIRE_SDA
+ #define PIN_WIRE_SDA PA10_R
+#endif
+#ifndef PIN_WIRE_SCL
+ #define PIN_WIRE_SCL PA9_R
+#endif
+
+// Timer Definitions
+// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin
+#ifndef TIMER_TONE
+ #define TIMER_TONE TIM14
+#endif
+#ifndef TIMER_SERVO
+ #define TIMER_SERVO TIM16
+#endif
+
+// UART Definitions
+#ifndef SERIAL_UART_INSTANCE
+ #define SERIAL_UART_INSTANCE 1
+#endif
+
+// Default pin used for generic 'Serial' instance
+// Mandatory for Firmata
+#ifndef PIN_SERIAL_RX
+ #define PIN_SERIAL_RX PA1
+#endif
+#ifndef PIN_SERIAL_TX
+ #define PIN_SERIAL_TX PA0
+#endif
+
+/*----------------------------------------------------------------------------
+ * Arduino objects - C++ only
+ *----------------------------------------------------------------------------*/
+
+#ifdef __cplusplus
+ // These serial port names are intended to allow libraries and architecture-neutral
+ // sketches to automatically default to the correct port name for a particular type
+ // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN,
+ // the first hardware serial port whose RX/TX pins are not dedicated to another use.
+ //
+ // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor
+ //
+ // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial
+ //
+ // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library
+ //
+ // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins.
+ //
+ // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX
+ // pins are NOT connected to anything by default.
+ #ifndef SERIAL_PORT_MONITOR
+ #define SERIAL_PORT_MONITOR Serial
+ #endif
+ #ifndef SERIAL_PORT_HARDWARE
+ #define SERIAL_PORT_HARDWARE Serial
+ #endif
+#endif
diff --git a/variants/STM32C0xx/C031C(4-6)(T-U)/PeripheralPins.c b/variants/STM32C0xx/C031C(4-6)(T-U)/PeripheralPins.c
new file mode 100644
index 0000000000..5c2cd13428
--- /dev/null
+++ b/variants/STM32C0xx/C031C(4-6)(T-U)/PeripheralPins.c
@@ -0,0 +1,280 @@
+/*
+ *******************************************************************************
+ * Copyright (c) 2020, STMicroelectronics
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+/*
+ * Automatically generated from STM32C031C(4-6)Tx.xml, STM32C031C(4-6)Ux.xml
+ * CubeMX DB release 6.0.70
+ */
+#if !defined(CUSTOM_PERIPHERAL_PINS)
+#include "Arduino.h"
+#include "PeripheralPins.h"
+
+/* =====
+ * Notes:
+ * - The pins mentioned Px_y_ALTz are alternative possibilities which use other
+ * HW peripheral instances. You can use them the same way as any other "normal"
+ * pin (i.e. analogWrite(PA7_ALT1, 128);).
+ *
+ * - Commented lines are alternative possibilities which are not used per default.
+ * If you change them, you will have to know what you do
+ * =====
+ */
+
+//*** ADC ***
+
+#ifdef HAL_ADC_MODULE_ENABLED
+WEAK const PinMap PinMap_ADC[] = {
+ {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_IN0
+ {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1
+ {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2
+ {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3
+ {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4
+ {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5
+ {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6
+ {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7
+ {PA_8, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8
+ {PA_11, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11
+ {PA_12, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12
+ {PA_13, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13
+ {PA_14, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14
+ {PB_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC1_IN17
+ {PB_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_IN18
+ {PB_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC1_IN19
+ {PB_10, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 20, 0)}, // ADC1_IN20
+ {PB_11, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 21, 0)}, // ADC1_IN21
+ {PB_12, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 22, 0)}, // ADC1_IN22
+ {NC, NP, 0}
+};
+#endif
+
+//*** No DAC ***
+
+//*** I2C ***
+
+#ifdef HAL_I2C_MODULE_ENABLED
+WEAK const PinMap PinMap_I2C_SDA[] = {
+ {PA_10, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C1)},
+ {PA_10_R, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C1)},
+ {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C1)},
+ {PB_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C1)},
+ {PC_14, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF14_I2C1)},
+ {NC, NP, 0}
+};
+#endif
+
+#ifdef HAL_I2C_MODULE_ENABLED
+WEAK const PinMap PinMap_I2C_SCL[] = {
+ {PA_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C1)},
+ {PA_9_R, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C1)},
+ {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C1)},
+ {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF14_I2C1)},
+ {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C1)},
+ {NC, NP, 0}
+};
+#endif
+
+//*** TIM ***
+
+#ifdef HAL_TIM_MODULE_ENABLED
+WEAK const PinMap PinMap_TIM[] = {
+ {PA_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM1, 1, 0)}, // TIM1_CH1
+ {PA_0_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM16, 1, 0)}, // TIM16_CH1
+ {PA_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM1, 2, 0)}, // TIM1_CH2
+ {PA_1_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM17, 1, 0)}, // TIM17_CH1
+ {PA_2, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM1, 3, 0)}, // TIM1_CH3
+ {PA_2_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM16, 1, 1)}, // TIM16_CH1N
+ {PA_3, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 1, 1)}, // TIM1_CH1N
+ {PA_3_ALT1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM1, 4, 0)}, // TIM1_CH4
+ {PA_4, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 2, 1)}, // TIM1_CH2N
+ {PA_4_ALT1, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM14, 1, 0)}, // TIM14_CH1
+ {PA_4_ALT2, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM17, 1, 1)}, // TIM17_CH1N
+ {PA_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM1, 1, 0)}, // TIM1_CH1
+ {PA_5_ALT1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 3, 1)}, // TIM1_CH3N
+ {PA_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 1, 0)}, // TIM3_CH1
+ {PA_6_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM16, 1, 0)}, // TIM16_CH1
+ {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 1, 1)}, // TIM1_CH1N
+ {PA_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 2, 0)}, // TIM3_CH2
+ {PA_7_ALT2, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM14, 1, 0)}, // TIM14_CH1
+ {PA_7_ALT3, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM17, 1, 0)}, // TIM17_CH1
+ {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 1, 0)}, // TIM1_CH1
+ {PA_8_ALT1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM1, 2, 1)}, // TIM1_CH2N
+ {PA_8_ALT2, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM1, 3, 1)}, // TIM1_CH3N
+ {PA_8_ALT3, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_TIM3, 3, 0)}, // TIM3_CH3
+ {PA_8_ALT4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_TIM3, 4, 0)}, // TIM3_CH4
+ {PA_8_ALT5, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF13_TIM14, 1, 0)}, // TIM14_CH1
+ {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 2, 0)}, // TIM1_CH2
+ {PA_9_R, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 2, 0)}, // TIM1_CH2
+ {PA_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 3, 0)}, // TIM1_CH3
+ {PA_10_R, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 3, 0)}, // TIM1_CH3
+ {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 4, 0)}, // TIM1_CH4
+ {PA_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM1, 1, 0)}, // TIM1_CH1
+ {PA_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 1, 0)}, // TIM1_CH1
+ {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 2, 1)}, // TIM1_CH2N
+ {PB_0_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 3, 0)}, // TIM3_CH3
+ {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM1, 2, 1)}, // TIM1_CH2N
+ {PB_1_ALT1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 3, 1)}, // TIM1_CH3N
+ {PB_1_ALT2, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 4, 0)}, // TIM3_CH4
+ {PB_1_ALT3, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_TIM14, 1, 0)}, // TIM14_CH1
+ {PB_3, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2
+ {PB_3_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM3, 2, 0)}, // TIM3_CH2
+ {PB_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 1, 0)}, // TIM3_CH1
+ {PB_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 2, 0)}, // TIM3_CH2
+ {PB_5_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM3, 3, 0)}, // TIM3_CH3
+ {PB_6, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_TIM1, 2, 0)}, // TIM1_CH2
+ {PB_6_ALT1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3
+ {PB_6_ALT2, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_TIM3, 1, 0)}, // TIM3_CH1
+ {PB_6_ALT3, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF13_TIM3, 2, 0)}, // TIM3_CH2
+ {PB_6_ALT4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM3, 3, 0)}, // TIM3_CH3
+ {PB_6_ALT5, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM16, 1, 1)}, // TIM16_CH1N
+ {PB_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4
+ {PB_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_TIM3, 1, 0)}, // TIM3_CH1
+ {PB_7_ALT2, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM3, 4, 0)}, // TIM3_CH4
+ {PB_7_ALT3, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM16, 1, 0)}, // TIM16_CH1
+ {PB_7_ALT4, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM17, 1, 1)}, // TIM17_CH1N
+ {PB_8, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM3, 1, 0)}, // TIM3_CH1
+ {PB_8_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM16, 1, 0)}, // TIM16_CH1
+ {PB_9, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM3, 2, 0)}, // TIM3_CH2
+ {PB_9_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM17, 1, 0)}, // TIM17_CH1
+ {PB_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 1, 1)}, // TIM1_CH1N
+ {PB_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 2, 1)}, // TIM1_CH2N
+ {PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 3, 1)}, // TIM1_CH3N
+ {PC_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 1, 0)}, // TIM3_CH1
+ {PC_7, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 2, 0)}, // TIM3_CH2
+ {PC_14, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_TIM3, 2, 0)}, // TIM3_CH2
+ {PC_14_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM17, 1, 0)}, // TIM17_CH1
+ {PC_15, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM3, 3, 0)}, // TIM3_CH3
+ {PD_0, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM16, 1, 0)}, // TIM16_CH1
+ {PD_1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM17, 1, 0)}, // TIM17_CH1
+ {PD_2, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 1, 1)}, // TIM1_CH1N
+ {PD_3, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 2, 1)}, // TIM1_CH2N
+ {PF_0, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM14, 1, 0)}, // TIM14_CH1
+ {PF_2, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4
+ {NC, NP, 0}
+};
+#endif
+
+//*** UART ***
+
+#ifdef HAL_UART_MODULE_ENABLED
+WEAK const PinMap PinMap_UART_TX[] = {
+ {PA_0, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)},
+ {PA_2, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)},
+ {PA_4, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)},
+ {PA_8, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)},
+ {PA_9, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)},
+ {PA_9_R, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)},
+ {PA_14, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)},
+ {PB_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)},
+ {PC_14, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)},
+ {NC, NP, 0}
+};
+#endif
+
+#ifdef HAL_UART_MODULE_ENABLED
+WEAK const PinMap PinMap_UART_RX[] = {
+ {PA_1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)},
+ {PA_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)},
+ {PA_5, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)},
+ {PA_8, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_USART1)},
+ {PA_10, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)},
+ {PA_10_R, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)},
+ {PA_13, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)},
+ {PA_14, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_USART2)},
+ {PA_15, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)},
+ {PB_2, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)},
+ {PB_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)},
+ {NC, NP, 0}
+};
+#endif
+
+#ifdef HAL_UART_MODULE_ENABLED
+WEAK const PinMap PinMap_UART_RTS[] = {
+ {PA_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)},
+ {PA_12, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)},
+ {PA_14, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_USART1)},
+ {PA_15, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)},
+ {PB_3, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)},
+ {PB_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)},
+ {PB_9, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)},
+ {PC_14, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_USART2)},
+ {NC, NP, 0}
+};
+#endif
+
+#ifdef HAL_UART_MODULE_ENABLED
+WEAK const PinMap PinMap_UART_CTS[] = {
+ {PA_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)},
+ {PA_11, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)},
+ {PB_4, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)},
+ {PB_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_USART1)},
+ {PB_7, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_USART2)},
+ {PB_8, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)},
+ {PD_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART2)},
+ {NC, NP, 0}
+};
+#endif
+
+//*** SPI ***
+
+#ifdef HAL_SPI_MODULE_ENABLED
+WEAK const PinMap PinMap_SPI_MOSI[] = {
+ {PA_2, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
+ {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
+ {PA_12, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
+ {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
+ {PB_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI1)},
+ {NC, NP, 0}
+};
+#endif
+
+#ifdef HAL_SPI_MODULE_ENABLED
+WEAK const PinMap PinMap_SPI_MISO[] = {
+ {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
+ {PA_11, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
+ {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
+ {PB_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_SPI1)},
+ {NC, NP, 0}
+};
+#endif
+
+#ifdef HAL_SPI_MODULE_ENABLED
+WEAK const PinMap PinMap_SPI_SCLK[] = {
+ {PA_1, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
+ {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
+ {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
+ {PB_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SPI1)},
+ {NC, NP, 0}
+};
+#endif
+
+#ifdef HAL_SPI_MODULE_ENABLED
+WEAK const PinMap PinMap_SPI_SSEL[] = {
+ {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
+ {PA_8, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI1)},
+ {PA_14, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI1)},
+ {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
+ {PB_0, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
+ {NC, NP, 0}
+};
+#endif
+
+//*** No CAN ***
+
+//*** No ETHERNET ***
+
+//*** No QUADSPI ***
+
+//*** No USB ***
+
+//*** No SD ***
+
+#endif /* !CUSTOM_PERIPHERAL_PINS */
diff --git a/variants/STM32C0xx/C031C(4-6)(T-U)/PinNamesVar.h b/variants/STM32C0xx/C031C(4-6)(T-U)/PinNamesVar.h
new file mode 100644
index 0000000000..c0e6b7b4dd
--- /dev/null
+++ b/variants/STM32C0xx/C031C(4-6)(T-U)/PinNamesVar.h
@@ -0,0 +1,67 @@
+/* Remap pin name */
+PA_9_R = PA_9 | PREMAP,
+PA_10_R = PA_10 | PREMAP,
+
+/* Alternate pin name */
+PA_0_ALT1 = PA_0 | ALT1,
+PA_1_ALT1 = PA_1 | ALT1,
+PA_2_ALT1 = PA_2 | ALT1,
+PA_3_ALT1 = PA_3 | ALT1,
+PA_4_ALT1 = PA_4 | ALT1,
+PA_4_ALT2 = PA_4 | ALT2,
+PA_5_ALT1 = PA_5 | ALT1,
+PA_6_ALT1 = PA_6 | ALT1,
+PA_7_ALT1 = PA_7 | ALT1,
+PA_7_ALT2 = PA_7 | ALT2,
+PA_7_ALT3 = PA_7 | ALT3,
+PA_8_ALT1 = PA_8 | ALT1,
+PA_8_ALT2 = PA_8 | ALT2,
+PA_8_ALT3 = PA_8 | ALT3,
+PA_8_ALT4 = PA_8 | ALT4,
+PA_8_ALT5 = PA_8 | ALT5,
+PB_0_ALT1 = PB_0 | ALT1,
+PB_1_ALT1 = PB_1 | ALT1,
+PB_1_ALT2 = PB_1 | ALT2,
+PB_1_ALT3 = PB_1 | ALT3,
+PB_3_ALT1 = PB_3 | ALT1,
+PB_5_ALT1 = PB_5 | ALT1,
+PB_6_ALT1 = PB_6 | ALT1,
+PB_6_ALT2 = PB_6 | ALT2,
+PB_6_ALT3 = PB_6 | ALT3,
+PB_6_ALT4 = PB_6 | ALT4,
+PB_6_ALT5 = PB_6 | ALT5,
+PB_7_ALT1 = PB_7 | ALT1,
+PB_7_ALT2 = PB_7 | ALT2,
+PB_7_ALT3 = PB_7 | ALT3,
+PB_7_ALT4 = PB_7 | ALT4,
+PB_8_ALT1 = PB_8 | ALT1,
+PB_9_ALT1 = PB_9 | ALT1,
+PC_14_ALT1 = PC_14 | ALT1,
+
+/* SYS_WKUP */
+#ifdef PWR_WAKEUP_PIN1
+ SYS_WKUP1 = PA_0,
+#endif
+#ifdef PWR_WAKEUP_PIN2
+ SYS_WKUP2 = PC_13,
+#endif
+#ifdef PWR_WAKEUP_PIN3
+ SYS_WKUP3 = PB_6,
+#endif
+#ifdef PWR_WAKEUP_PIN4
+ SYS_WKUP4 = PA_2,
+#endif
+#ifdef PWR_WAKEUP_PIN5
+ SYS_WKUP5 = NC,
+#endif
+#ifdef PWR_WAKEUP_PIN6
+ SYS_WKUP6 = PB_5,
+#endif
+#ifdef PWR_WAKEUP_PIN7
+ SYS_WKUP7 = NC,
+#endif
+#ifdef PWR_WAKEUP_PIN8
+ SYS_WKUP8 = NC,
+#endif
+
+/* No USB */
diff --git a/variants/STM32C0xx/C031C(4-6)(T-U)/boards_entry.txt b/variants/STM32C0xx/C031C(4-6)(T-U)/boards_entry.txt
new file mode 100644
index 0000000000..c6bf809359
--- /dev/null
+++ b/variants/STM32C0xx/C031C(4-6)(T-U)/boards_entry.txt
@@ -0,0 +1,37 @@
+# This file help to add generic board entry.
+# upload.maximum_size and product_line have to be verified
+# and changed if needed.
+# See: https://github.com/stm32duino/wiki/wiki/Add-a-new-variant-%28board%29
+
+# Generic C031C4Tx
+GenC0.menu.pnum.GENERIC_C031C4TX=Generic C031C4Tx
+GenC0.menu.pnum.GENERIC_C031C4TX.upload.maximum_size=16384
+GenC0.menu.pnum.GENERIC_C031C4TX.upload.maximum_data_size=12288
+GenC0.menu.pnum.GENERIC_C031C4TX.build.board=GENERIC_C031C4TX
+GenC0.menu.pnum.GENERIC_C031C4TX.build.product_line=STM32C031xx
+GenC0.menu.pnum.GENERIC_C031C4TX.build.variant=STM32C0xx/C031C(4-6)(T-U)
+
+# Generic C031C6Tx
+GenC0.menu.pnum.GENERIC_C031C6TX=Generic C031C6Tx
+GenC0.menu.pnum.GENERIC_C031C6TX.upload.maximum_size=32768
+GenC0.menu.pnum.GENERIC_C031C6TX.upload.maximum_data_size=12288
+GenC0.menu.pnum.GENERIC_C031C6TX.build.board=GENERIC_C031C6TX
+GenC0.menu.pnum.GENERIC_C031C6TX.build.product_line=STM32C031xx
+GenC0.menu.pnum.GENERIC_C031C6TX.build.variant=STM32C0xx/C031C(4-6)(T-U)
+
+# Generic C031C4Ux
+GenC0.menu.pnum.GENERIC_C031C4UX=Generic C031C4Ux
+GenC0.menu.pnum.GENERIC_C031C4UX.upload.maximum_size=16384
+GenC0.menu.pnum.GENERIC_C031C4UX.upload.maximum_data_size=12288
+GenC0.menu.pnum.GENERIC_C031C4UX.build.board=GENERIC_C031C4UX
+GenC0.menu.pnum.GENERIC_C031C4UX.build.product_line=STM32C031xx
+GenC0.menu.pnum.GENERIC_C031C4UX.build.variant=STM32C0xx/C031C(4-6)(T-U)
+
+# Generic C031C6Ux
+GenC0.menu.pnum.GENERIC_C031C6UX=Generic C031C6Ux
+GenC0.menu.pnum.GENERIC_C031C6UX.upload.maximum_size=32768
+GenC0.menu.pnum.GENERIC_C031C6UX.upload.maximum_data_size=12288
+GenC0.menu.pnum.GENERIC_C031C6UX.build.board=GENERIC_C031C6UX
+GenC0.menu.pnum.GENERIC_C031C6UX.build.product_line=STM32C031xx
+GenC0.menu.pnum.GENERIC_C031C6UX.build.variant=STM32C0xx/C031C(4-6)(T-U)
+
diff --git a/variants/STM32C0xx/C031C(4-6)(T-U)/generic_clock.c b/variants/STM32C0xx/C031C(4-6)(T-U)/generic_clock.c
new file mode 100644
index 0000000000..7432f3b741
--- /dev/null
+++ b/variants/STM32C0xx/C031C(4-6)(T-U)/generic_clock.c
@@ -0,0 +1,53 @@
+/*
+ *******************************************************************************
+ * Copyright (c) 2020, STMicroelectronics
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+#if defined(ARDUINO_GENERIC_C031C4TX) || defined(ARDUINO_GENERIC_C031C4UX) ||\
+ defined(ARDUINO_GENERIC_C031C6TX) || defined(ARDUINO_GENERIC_C031C6UX)
+#include "pins_arduino.h"
+#include "stm32yyxx_ll_utils.h"
+
+/**
+ * @brief System Clock Configuration
+ * @param None
+ * @retval None
+ */
+WEAK void SystemClock_Config(void)
+{
+ LL_FLASH_SetLatency(LL_FLASH_LATENCY_1);
+
+ /* HSI configuration and activation */
+ LL_RCC_HSI_Enable();
+ while (LL_RCC_HSI_IsReady() != 1) {
+ }
+
+ LL_RCC_HSI_SetCalibTrimming(64);
+ LL_RCC_SetHSIDiv(LL_RCC_HSI_DIV_1);
+ /* Set AHB prescaler*/
+ LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1);
+
+ /* Sysclk activation on the HSI */
+ LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_HSI);
+ while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSI) {
+ }
+
+ /* Set APB1 prescaler*/
+ LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_1);
+ /* Update CMSIS variable (which can be updated also through SystemCoreClockUpdate function) */
+ LL_SetSystemCoreClock(48000000);
+
+ /* Update the time base */
+ if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) {
+ Error_Handler();
+ }
+}
+
+#endif /* ARDUINO_GENERIC_* */
diff --git a/variants/STM32C0xx/C031C(4-6)(T-U)/ldscript.ld b/variants/STM32C0xx/C031C(4-6)(T-U)/ldscript.ld
new file mode 100644
index 0000000000..fb176f70ab
--- /dev/null
+++ b/variants/STM32C0xx/C031C(4-6)(T-U)/ldscript.ld
@@ -0,0 +1,177 @@
+/**
+ ******************************************************************************
+ * @file LinkerScript.ld
+ * @author Auto-generated by STM32CubeIDE
+ * Abstract : Linker script for STM32C031CxTx Device from stm32c0 series
+ * 32Kbytes FLASH
+ * 12Kbytes RAM
+ *
+ * Set heap size, stack size and stack location according
+ * to application requirements.
+ *
+ * Set memory bank area and size if external memory is used
+ ******************************************************************************
+ * @attention
+ *
+ *
+
+![ST logo]()
+
+
+Release Notes +for STM32CubeC0 HAL and LL drivers
+Copyright © 2022 STMicroelectronics
+
Purpose
+The STM32Cube HAL and LL, an STM32 abstraction layer embedded +software, ensure maximized portability across STM32 portfolio.
+The portable APIs layer provides a generic, multi instanced and +simple set of APIs to interact with the upper layer (application, +libraries and stacks). It is composed of native and extended APIs set. +It is directly built around a generic architecture and allows the +build-upon layers, like the middleware layer, to implement its functions +without knowing in-depth the used STM32 device. This improves the +library code reusability and guarantees an easy portability on other +devices and STM32 families.
+The Low Layer (LL) drivers are part of the STM32Cube firmware HAL +that provides a basic set of optimized and one-shot services. The Low +layer drivers, contrary to the HAL ones are not fully portable across +the STM32 families; the availability of some functions depends on the +physical availability of the relative features on the product. The Low +Layer (LL) drivers are designed to offer the following features:
+-
+
- New set of inline functions for direct and atomic register +access +
- One-shot operations that can be used by the HAL drivers or from +application level +
- Full independence from HAL and standalone usage (without HAL +drivers) +
- Full features coverage of all the supported peripherals +
Update History
+
+
+
+
+
+
+Main Changes
+-
+
Patch Release of STM32CubeC0 Firmware Package
+Update ADC HAL driver with proper internal sensor calibration implementation:
+-
+
- Helper macro “__LL_ADC_CALC_TEMPERATURE()” is not available and +macro “__LL_ADC_CALC_TEMPERATURE_TYP_PARAMS()” must be used. +
+Update RCC LL driver by adding missing AHB Prescaler.
+
Known Limitations
+N/A
+
+
+
+
+
+
+Main Changes
+First official release of HAL and LL drivers for STM32C031xx / +STM32C011xx devices
+Known Limitations
+N/A
+