diff --git a/variants/STM32H5xx/H503RBT/CMakeLists.txt b/variants/STM32H5xx/H503RBT/CMakeLists.txt index 2a4d55b6b1..455bd2130d 100644 --- a/variants/STM32H5xx/H503RBT/CMakeLists.txt +++ b/variants/STM32H5xx/H503RBT/CMakeLists.txt @@ -22,10 +22,10 @@ add_library(variant_bin STATIC EXCLUDE_FROM_ALL generic_clock.c PeripheralPins.c variant_generic.cpp + variant_NUCLEO_H503RB.cpp ) target_link_libraries(variant_bin PUBLIC variant_usage) target_link_libraries(variant INTERFACE variant_bin -) - +) \ No newline at end of file diff --git a/variants/STM32H5xx/H503RBT/generic_clock.c b/variants/STM32H5xx/H503RBT/generic_clock.c index f30dcfb8df..75fca0da3c 100644 --- a/variants/STM32H5xx/H503RBT/generic_clock.c +++ b/variants/STM32H5xx/H503RBT/generic_clock.c @@ -10,18 +10,86 @@ * ******************************************************************************* */ + #if defined(ARDUINO_GENERIC_H503RBTX) #include "pins_arduino.h" /** - * @brief System Clock Configuration - * @param None - * @retval None - */ +* @note [How to generate PLL clock] +* +* HSI 64 MHz ... internal clock +* HSI48 48 MHz ... internal clock for USB/RNG with recovery +* LSI 32.768 kHz ... internal clock +* CSI 4 MHz ... internal clock for low power +* +* +* SOURCE / PLLM * PLLN +* +* +* PLL ... MULTIPLEXER / PLLP +* +* - Default CPU clock: 4(CSI) / 2(PLLM) * 250(PLLN) / 2(PLLP) ... 250 MHz +* - PLL3 supports only H562/H563/H573. +*/ + WEAK void SystemClock_Config(void) { - /* SystemClock_Config can be generated by STM32CubeMX */ -#warning "SystemClock_Config() is empty. Default clock at reset is used." + RCC_OscInitTypeDef RCC_OscInitStruct = {}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {}; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {}; + + /* Configure the main internal regulator output voltage */ + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0); + + while (!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {} + + /* Initializes the RCC Oscillators according to the specified parameters in the RCC_OscInitTypeDef structure */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_CSI; + RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.HSIDiv = RCC_HSI_DIV1; + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + RCC_OscInitStruct.LSIState = RCC_LSI_ON; + RCC_OscInitStruct.CSIState = RCC_CSI_ON; + RCC_OscInitStruct.CSICalibrationValue = RCC_CSICALIBRATION_DEFAULT; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLL1_SOURCE_CSI; + RCC_OscInitStruct.PLL.PLLM = 2; + RCC_OscInitStruct.PLL.PLLN = 250; + RCC_OscInitStruct.PLL.PLLP = 2; + RCC_OscInitStruct.PLL.PLLQ = 2; + RCC_OscInitStruct.PLL.PLLR = 2; + RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1_VCIRANGE_1; + RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1_VCORANGE_WIDE; + RCC_OscInitStruct.PLL.PLLFRACN = 0; + + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + Error_Handler(); + } + + /* Initializes the CPU, AHB and APB buses clocks */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_PCLK3; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + RCC_ClkInitStruct.APB3CLKDivider = RCC_HCLK_DIV1; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) { + Error_Handler(); + } + + /* Initializes the peripherals clock */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_USB; + PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; + PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_HSI; + PeriphClkInitStruct.Sdmmc1ClockSelection = RCC_SDMMC1CLKSOURCE_PLL1Q; + PeriphClkInitStruct.AdcDacClockSelection = RCC_ADCDACCLKSOURCE_HCLK; + PeriphClkInitStruct.OspiClockSelection = RCC_OSPICLKSOURCE_HCLK; + + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { + Error_Handler(); + } } -#endif /* ARDUINO_GENERIC_* */ +#endif /* ARDUINO_GENERIC_H503RBTX */ \ No newline at end of file diff --git a/variants/STM32H5xx/H503RBT/ldscript.ld b/variants/STM32H5xx/H503RBT/ldscript.ld new file mode 100644 index 0000000000..3f85cdba2e --- /dev/null +++ b/variants/STM32H5xx/H503RBT/ldscript.ld @@ -0,0 +1,175 @@ +/* +****************************************************************************** +** +** @file : LinkerScript.ld +** +** @author : Auto-generated by STM32CubeIDE +** +** @brief : Linker script for STM32H503RBTx Device from STM32H5 series +** 128Kbytes FLASH +** 32Kbytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +****************************************************************************** +** @attention +** +** Copyright (c) 2021 STMicroelectronics. +** All rights reserved. +** +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. +** +****************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Memories definition */ +MEMORY { + RAM (rwx) : ORIGIN = 0x20000000, LENGTH = LD_MAX_DATA_SIZE + FLASH ( rx) : ORIGIN = 0x08000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET +} + +/* Sections */ +SECTIONS { + /* The startup code into "FLASH" Rom type memory */ + .isr_vector : { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > FLASH + + /* The program code and other data into "FLASH" Rom type memory */ + .text : { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP(*(.init)) + KEEP(*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } > FLASH + + /* Constant data into "FLASH" Rom type memory */ + .rodata : { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } > FLASH + + .ARM.extab : { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } > FLASH + + .ARM : { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } > FLASH + + .preinit_array : { + . = ALIGN(4); + PROVIDE_HIDDEN(__preinit_array_start = .); + KEEP(*(.preinit_array*)) + PROVIDE_HIDDEN(__preinit_array_end = .); + . = ALIGN(4); + } > FLASH + + .init_array : { + . = ALIGN(4); + PROVIDE_HIDDEN(__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array*)) + PROVIDE_HIDDEN(__init_array_end = .); + . = ALIGN(4); + } > FLASH + + .fini_array : { + . = ALIGN(4); + PROVIDE_HIDDEN(__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array*)) + PROVIDE_HIDDEN(__fini_array_end = .); + . = ALIGN(4); + } > FLASH + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } > RAM AT > FLASH + + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } > RAM + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : { + . = ALIGN(8); + PROVIDE(end = .); + PROVIDE(_end = .); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } > RAM + + /* Remove information from the compiler libraries */ + /DISCARD/ : { + libc.a (*) + libm.a (*) + libgcc.a (*) + } + + .ARM.attributes 0 : { + *(.ARM.attributes) + } +} \ No newline at end of file diff --git a/variants/STM32H5xx/H503RBT/variant_NUCLEO_H503RB.cpp b/variants/STM32H5xx/H503RBT/variant_NUCLEO_H503RB.cpp new file mode 100644 index 0000000000..fb0560800f --- /dev/null +++ b/variants/STM32H5xx/H503RBT/variant_NUCLEO_H503RB.cpp @@ -0,0 +1,178 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +#if defined(ARDUINO_NUCLEO_H503RB) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_15 // D0 + PA_14 // D1 + PA_10 // D2 + PB_3 // D3 + PB_5 // D4 + PB_4 // D5 + PB_10 // D6 + PA_8 // D7 + PC_7 // D8 + PC_6 // D9 + PC_9 // D10 + PA_7 // D11 + PA_6 // D12 + PA_5 // D13 + PB_7 // D14 + PB_6 // D15/A0 + PA_0 // D16/A1 + PA_1 // D17/A2 + PA_2 // D18/A3 + PB_0 // D19/A4 + PC_1 // D20/A5 + PC_0 // D21 + PA_3 // D22 + PA_4 // D23 + PA_9 // D24 + PA_13 // D25 + PC_2 // D26 + PC_3 // D27 + PC_5 // D28 + PC_8 // D29 + PC_10 // D30 + PC_11 // D31 + PC_12 // D32 + PC_13 // D33 + PC_14 // D34 + PC_15 // D35 + PD_2 // D36 + PH_0 // D37 + PH_1 // D38 + PA_12 // D39/A6 + PA_11 // D40/A7 + PB_12 // D41/A8 + PB_2 // D42/A9 + PB_1 // D43/A10 + PB_15 // D44/A11 + PB_14 // D45/A12 + PB_13 // D46/A13 + PC_4 // D47/A14 + PB_8 // D48/A15 +}; + +// Analog (Ax) pin number array +const uint32_t analogInputPin[] = { + 15, // A0, PA0 + 16, // A1, PA1 + 17, // A2, PA2 + 18, // A3, PB0 + 19, // A4, PC1 + 20, // A5, PC0 + 39, // A6, PA12 + 40, // A7, PA11 + 41, // A8, PB12 + 42, // A9, PB2 + 43, // A10, PB1 + 44, // A11, PB15 + 45, // A12, PB14 + 46, // A13, PB13 + 47, // A14, PC4 + 48 // A15, PB8 +}; + +#ifdef __cplusplus +extern "C" { +#endif + +/** +* @note [How to generate PLL clock] +* +* HSE 8 MHz ... STLINK MCO output +* HSE 24 MHz ... on-board X3 (default) +* HSE 4~50 MHz ... prepare your own external clock +* LSE 32.768 kHz ... on-board X2 +* HSI 64 MHz ... internal clock +* HSI48 48 MHz ... internal clock for USB/RNG with recovery +* LSI 32.768 kHz ... internal clock +* CSI 4 MHz ... internal clock for low power +* +* +* SOURCE / PLLM * PLLN +* +* +* PLL ... MULTIPLEXER / PLLP +* +* - Default CPU clock: 24(HSE) / 12(PLLM) * 250(PLLN) / 2(PLLP) ... 250 MHz +* - PLL3 supports only H562/H563/H573. +*/ + +WEAK void SystemClock_Config(void) +{ + RCC_OscInitTypeDef RCC_OscInitStruct = {}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {}; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {}; + + /* Configure the main internal regulator output voltage */ + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0); + + while (!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {} + + /* Initializes the RCC Oscillators according to the specified parameters in the RCC_OscInitTypeDef structure */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_LSE; + RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS_DIGITAL; + RCC_OscInitStruct.LSEState = RCC_LSE_ON; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.HSIDiv = RCC_HSI_DIV1; + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLL1_SOURCE_HSE; + RCC_OscInitStruct.PLL.PLLM = 12; + RCC_OscInitStruct.PLL.PLLN = 250; + RCC_OscInitStruct.PLL.PLLP = 2; + RCC_OscInitStruct.PLL.PLLQ = 2; + RCC_OscInitStruct.PLL.PLLR = 2; + RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1_VCIRANGE_1; + RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1_VCORANGE_WIDE; + RCC_OscInitStruct.PLL.PLLFRACN = 0; + + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + Error_Handler(); + } + + /* Initializes the CPU, AHB and APB buses clocks */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_PCLK3; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + RCC_ClkInitStruct.APB3CLKDivider = RCC_HCLK_DIV1; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) { + Error_Handler(); + } + + /* Initializes the peripherals clock */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_USB; + PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; + PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_HSI; + PeriphClkInitStruct.Sdmmc1ClockSelection = RCC_SDMMC1CLKSOURCE_PLL1Q; + PeriphClkInitStruct.AdcDacClockSelection = RCC_ADCDACCLKSOURCE_HCLK; + PeriphClkInitStruct.OspiClockSelection = RCC_OSPICLKSOURCE_HCLK; + + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { + Error_Handler(); + } +} + +#ifdef __cplusplus +} +#endif + +#endif /* ARDUINO_NUCLEO_H503RB */ \ No newline at end of file diff --git a/variants/STM32H5xx/H503RBT/variant_NUCLEO_H503RB.h b/variants/STM32H5xx/H503RBT/variant_NUCLEO_H503RB.h new file mode 100644 index 0000000000..7f8c4913fa --- /dev/null +++ b/variants/STM32H5xx/H503RBT/variant_NUCLEO_H503RB.h @@ -0,0 +1,180 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA15 0 +#define PA14 1 +#define PA10 2 +#define PB3 3 +#define PB5 4 +#define PB4 5 +#define PB10 6 +#define PA8 7 +#define PC7 8 +#define PC6 9 +#define PC9 10 +#define PA7 11 +#define PA6 12 +#define PA5 13 +#define PB7 14 +#define PB6 15 +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA2 PIN_A2 +#define PB0 PIN_A3 +#define PC1 PIN_A4 +#define PC0 PIN_A5 +#define PA3 22 +#define PA4 23 +#define PA9 24 +#define PA13 25 +#define PC2 26 +#define PC3 27 +#define PC5 28 +#define PC8 29 +#define PC10 30 +#define PC11 31 +#define PC12 32 +#define PC13 33 +#define PC14 34 +#define PC15 35 +#define PD2 36 +#define PH0 37 +#define PH1 38 +#define PA12 PIN_A6 +#define PA11 PIN_A7 +#define PB12 PIN_A8 +#define PB2 PIN_A9 +#define PB1 PIN_A10 +#define PB15 PIN_A11 +#define PB14 PIN_A12 +#define PB13 PIN_A13 +#define PC4 PIN_A14 +#define PB8 PIN_A15 + +// Alternate pins number +#define PA0_ALT1 (PA0 | ALT1) +#define PA0_ALT2 (PA0 | ALT2) +#define PA1_ALT1 (PA1 | ALT1) +#define PA2_ALT1 (PA2 | ALT1) +#define PA3_ALT1 (PA3 | ALT1) +#define PA4_ALT1 (PA4 | ALT1) +#define PA5_ALT1 (PA5 | ALT1) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA8_ALT1 (PA8 | ALT1) +#define PA8_ALT2 (PA8 | ALT2) +#define PA9_ALT1 (PA9 | ALT1) +#define PA10_ALT1 (PA10 | ALT1) +#define PA11_ALT1 (PA11 | ALT1) +#define PA12_ALT1 (PA12 | ALT1) +#define PA13_ALT1 (PA13 | ALT1) +#define PA14_ALT1 (PA14 | ALT1) +#define PA14_ALT2 (PA14 | ALT2) +#define PA15_ALT1 (PA15 | ALT1) +#define PB0_ALT1 (PB0 | ALT1) +#define PB1_ALT1 (PB1 | ALT1) +#define PB1_ALT2 (PB1 | ALT2) +#define PB2_ALT1 (PB2 | ALT1) +#define PB3_ALT1 (PB3 | ALT1) +#define PB4_ALT1 (PB4 | ALT1) +#define PB4_ALT2 (PB4 | ALT2) +#define PB5_ALT1 (PB5 | ALT1) +#define PB6_ALT1 (PB6 | ALT1) +#define PB6_ALT2 (PB6 | ALT2) +#define PB7_ALT1 (PB7 | ALT1) +#define PB13_ALT1 (PB13 | ALT1) +#define PB14_ALT1 (PB14 | ALT1) +#define PB15_ALT1 (PB15 | ALT1) +#define PB15_ALT2 (PB15 | ALT2) +#define PC1_ALT1 (PC1 | ALT1) +#define PC2_ALT1 (PC2 | ALT1) +#define PC3_ALT1 (PC3 | ALT1) +#define PC6_ALT1 (PC6 | ALT1) +#define PC7_ALT1 (PC7 | ALT1) +#define PC8_ALT1 (PC8 | ALT1) +#define PC9_ALT1 (PC9 | ALT1) +#define PC12_ALT1 (PC12 | ALT1) + +#define NUM_DIGITAL_PINS 49 +#define NUM_ANALOG_INPUTS 16 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PA5 +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PC13 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM6 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM7 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 3 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA3 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA4 +#endif + +// Extra HAL modules +#if !defined(HAL_DAC_MODULE_DISABLED) + #define HAL_DAC_MODULE_ENABLED +#endif + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif \ No newline at end of file