From 7fd3d747f827143e658010d678d6dbf9b5ab6bcb Mon Sep 17 00:00:00 2001 From: stnolting Date: Fri, 17 Sep 2021 18:17:50 +0200 Subject: [PATCH 1/9] [sw/lib] now using struct-based low-level HW access instead of single "define" pointers --- sw/lib/include/neorv32.h | 743 ++++++++++++++++----------------------- 1 file changed, 301 insertions(+), 442 deletions(-) diff --git a/sw/lib/include/neorv32.h b/sw/lib/include/neorv32.h index 015b4923a..6015c2d36 100644 --- a/sw/lib/include/neorv32.h +++ b/sw/lib/include/neorv32.h @@ -490,7 +490,28 @@ enum NEORV32_CLOCK_PRSC_enum { /**********************************************************************//** - * @name Helper macros for easy memory-mapped register access + * @name Address space sections + **************************************************************************/ +/**@{*/ +/** instruction memory base address (r/w/x) */ +// -> configured via ispace_base_c constant in neorv32_package.vhd and available to SW via SYSCONFIG entry +/** data memory base address (r/w/x) */ +// -> configured via dspace_base_c constant in neorv32_package.vhd and available to SW via SYSCONFIG entry +/** bootloader memory base address (r/-/x) */ +#define BOOTLOADER_BASE_ADDRESS (0xFFFF0000UL) +/** peripheral/IO devices memory base address (r/w/x) */ +#define IO_BASE_ADDRESS (0xFFFFFE00UL) +/**@}*/ + + +// ############################################################################################################################ +// Peripheral/IO Devices - IO Address Space +// ############################################################################################################################ + + +/// @cond LEGACY_SYMBOLS +/**********************************************************************//** + * @name Helper macros for easy memory-mapped register access (DEPRECATED!) **************************************************************************/ /**@{*/ /** memory-mapped byte (8-bit) read/write register */ @@ -510,101 +531,20 @@ enum NEORV32_CLOCK_PRSC_enum { /** memory-mapped double-word (64-bit) read-only register */ #define IO_ROM64 (const volatile uint64_t*) /**@}*/ - - -/**********************************************************************//** - * @name Address space sections - **************************************************************************/ -/**@{*/ -/** instruction memory base address (r/w/x) */ -// -> configured via ispace_base_c constant in neorv32_package.vhd and available to SW via SYSCONFIG entry -/** data memory base address (r/w/x) */ -// -> configured via dspace_base_c constant in neorv32_package.vhd and available to SW via SYSCONFIG entry -/** bootloader memory base address (r/-/x) */ -#define BOOTLOADER_BASE_ADDRESS (0xFFFF0000UL) -/** peripheral/IO devices memory base address (r/w/x) */ -#define IO_BASE_ADDRESS (0xFFFFFE00UL) -/**@}*/ - - -// ############################################################################################################################ -// Peripheral/IO Devices - IO Address Space -// ############################################################################################################################ +/// @endcond /**********************************************************************//** * @name IO Device: Custom Functions Subsystem (CFS) **************************************************************************/ /**@{*/ -/** CFS base address */ -#define CFS_BASE (0xFFFFFE00UL) // /**< CFS base address */ -/** CFS address space size in bytes */ -#define CFS_SIZE (64*4) // /**< CFS address space size in bytes */ - -/** custom CFS register 0 */ -#define CFS_REG_0 (*(IO_REG32 (CFS_BASE + 0))) // /**< (r)/(w): CFS register 0, user-defined */ -/** custom CFS register 1 */ -#define CFS_REG_1 (*(IO_REG32 (CFS_BASE + 4))) // /**< (r)/(w): CFS register 1, user-defined */ -/** custom CFS register 2 */ -#define CFS_REG_2 (*(IO_REG32 (CFS_BASE + 8))) // /**< (r)/(w): CFS register 2, user-defined */ -/** custom CFS register 3 */ -#define CFS_REG_3 (*(IO_REG32 (CFS_BASE + 12))) // /**< (r)/(w): CFS register 3, user-defined */ -/** custom CFS register 4 */ -#define CFS_REG_4 (*(IO_REG32 (CFS_BASE + 16))) // /**< (r)/(w): CFS register 4, user-defined */ -/** custom CFS register 5 */ -#define CFS_REG_5 (*(IO_REG32 (CFS_BASE + 20))) // /**< (r)/(w): CFS register 5, user-defined */ -/** custom CFS register 6 */ -#define CFS_REG_6 (*(IO_REG32 (CFS_BASE + 24))) // /**< (r)/(w): CFS register 6, user-defined */ -/** custom CFS register 7 */ -#define CFS_REG_7 (*(IO_REG32 (CFS_BASE + 28))) // /**< (r)/(w): CFS register 7, user-defined */ -/** custom CFS register 8 */ -#define CFS_REG_8 (*(IO_REG32 (CFS_BASE + 32))) // /**< (r)/(w): CFS register 8, user-defined */ -/** custom CFS register 9 */ -#define CFS_REG_9 (*(IO_REG32 (CFS_BASE + 36))) // /**< (r)/(w): CFS register 9, user-defined */ -/** custom CFS register 10 */ -#define CFS_REG_10 (*(IO_REG32 (CFS_BASE + 40))) // /**< (r)/(w): CFS register 10, user-defined */ -/** custom CFS register 11 */ -#define CFS_REG_11 (*(IO_REG32 (CFS_BASE + 44))) // /**< (r)/(w): CFS register 11, user-defined */ -/** custom CFS register 12 */ -#define CFS_REG_12 (*(IO_REG32 (CFS_BASE + 48))) // /**< (r)/(w): CFS register 12, user-defined */ -/** custom CFS register 13 */ -#define CFS_REG_13 (*(IO_REG32 (CFS_BASE + 52))) // /**< (r)/(w): CFS register 13, user-defined */ -/** custom CFS register 14 */ -#define CFS_REG_14 (*(IO_REG32 (CFS_BASE + 56))) // /**< (r)/(w): CFS register 14, user-defined */ -/** custom CFS register 15 */ -#define CFS_REG_15 (*(IO_REG32 (CFS_BASE + 60))) // /**< (r)/(w): CFS register 15, user-defined */ -/** custom CFS register 16 */ -#define CFS_REG_16 (*(IO_REG32 (CFS_BASE + 64))) // /**< (r)/(w): CFS register 16, user-defined */ -/** custom CFS register 17 */ -#define CFS_REG_17 (*(IO_REG32 (CFS_BASE + 68))) // /**< (r)/(w): CFS register 17, user-defined */ -/** custom CFS register 18 */ -#define CFS_REG_18 (*(IO_REG32 (CFS_BASE + 72))) // /**< (r)/(w): CFS register 18, user-defined */ -/** custom CFS register 19 */ -#define CFS_REG_19 (*(IO_REG32 (CFS_BASE + 76))) // /**< (r)/(w): CFS register 19, user-defined */ -/** custom CFS register 20 */ -#define CFS_REG_20 (*(IO_REG32 (CFS_BASE + 80))) // /**< (r)/(w): CFS register 20, user-defined */ -/** custom CFS register 21 */ -#define CFS_REG_21 (*(IO_REG32 (CFS_BASE + 84))) // /**< (r)/(w): CFS register 21, user-defined */ -/** custom CFS register 22 */ -#define CFS_REG_22 (*(IO_REG32 (CFS_BASE + 88))) // /**< (r)/(w): CFS register 22, user-defined */ -/** custom CFS register 23 */ -#define CFS_REG_23 (*(IO_REG32 (CFS_BASE + 92))) // /**< (r)/(w): CFS register 23, user-defined */ -/** custom CFS register 24 */ -#define CFS_REG_24 (*(IO_REG32 (CFS_BASE + 96))) // /**< (r)/(w): CFS register 24, user-defined */ -/** custom CFS register 25 */ -#define CFS_REG_25 (*(IO_REG32 (CFS_BASE + 100))) // /**< (r)/(w): CFS register 25, user-defined */ -/** custom CFS register 26 */ -#define CFS_REG_26 (*(IO_REG32 (CFS_BASE + 104))) // /**< (r)/(w): CFS register 26, user-defined */ -/** custom CFS register 27 */ -#define CFS_REG_27 (*(IO_REG32 (CFS_BASE + 108))) // /**< (r)/(w): CFS register 27, user-defined */ -/** custom CFS register 28 */ -#define CFS_REG_28 (*(IO_REG32 (CFS_BASE + 112))) // /**< (r)/(w): CFS register 28, user-defined */ -/** custom CFS register 29 */ -#define CFS_REG_29 (*(IO_REG32 (CFS_BASE + 116))) // /**< (r)/(w): CFS register 29, user-defined */ -/** custom CFS register 30 */ -#define CFS_REG_30 (*(IO_REG32 (CFS_BASE + 120))) // /**< (r)/(w): CFS register 30, user-defined */ -/** custom CFS register 31 */ -#define CFS_REG_31 (*(IO_REG32 (CFS_BASE + 124))) // /**< (r)/(w): CFS register 31, user-defined */ +/** CFS module prototype */ +typedef struct __attribute__((packed,aligned(4))) { + uint32_t REG[32]; /**< offset 0..124: CFS register 0..31, user-defined */ +} neorv32_cfs_t; + +/** CFS module hardware access (#neorv32_cfs_t) */ +#define NEORV32_CFS (*((volatile neorv32_cfs_t*) (0xFFFFFE00UL))) /**@}*/ @@ -612,50 +552,21 @@ enum NEORV32_CLOCK_PRSC_enum { * @name IO Device: Pulse Width Modulation Controller (PWM) **************************************************************************/ /**@{*/ -/** PWM base address */ -#define PWM_BASE (0xFFFFFE80UL) // /**< PWM base address */ -/** PWM address space size in bytes */ -#define PWM_SIZE (16*4) // /**< PWM address space size in bytes */ - -/** PWM control register (r/w) */ -#define PWM_CT (*(IO_REG32 (PWM_BASE + 0))) // r/w: control register -/** PWM duty cycle register 0 (r/w) */ -#define PWM_DUTY0 (*(IO_REG32 (PWM_BASE + 4))) // r/w: duty cycle channel 3:0 -/** PWM duty cycle register 1 (r/w) */ -#define PWM_DUTY1 (*(IO_REG32 (PWM_BASE + 8))) // r/w: duty cycle channel 7:4 -/** PWM duty cycle register 2 (r/w) */ -#define PWM_DUTY2 (*(IO_REG32 (PWM_BASE + 12))) // r/w: duty cycle channel 11:8 -/** PWM duty cycle register 3 (r/w) */ -#define PWM_DUTY3 (*(IO_REG32 (PWM_BASE + 16))) // r/w: duty cycle channel 15:12 -/** PWM duty cycle register 4 (r/w) */ -#define PWM_DUTY4 (*(IO_REG32 (PWM_BASE + 20))) // r/w: duty cycle channel 19:16 -/** PWM duty cycle register 5 (r/w) */ -#define PWM_DUTY5 (*(IO_REG32 (PWM_BASE + 24))) // r/w: duty cycle channel 23:20 -/** PWM duty cycle register 6 (r/w) */ -#define PWM_DUTY6 (*(IO_REG32 (PWM_BASE + 28))) // r/w: duty cycle channel 27:24 -/** PWM duty cycle register 7 (r/w) */ -#define PWM_DUTY7 (*(IO_REG32 (PWM_BASE + 32))) // r/w: duty cycle channel 31:28 -/** PWM duty cycle register 8 (r/w) */ -#define PWM_DUTY8 (*(IO_REG32 (PWM_BASE + 36))) // r/w: duty cycle channel 35:32 -/** PWM duty cycle register 9 (r/w) */ -#define PWM_DUTY9 (*(IO_REG32 (PWM_BASE + 40))) // r/w: duty cycle channel 39:36 -/** PWM duty cycle register 10 (r/w) */ -#define PWM_DUTY10 (*(IO_REG32 (PWM_BASE + 44))) // r/w: duty cycle channel 43:40 -/** PWM duty cycle register 11 (r/w) */ -#define PWM_DUTY11 (*(IO_REG32 (PWM_BASE + 48))) // r/w: duty cycle channel 47:44 -/** PWM duty cycle register 12 (r/w) */ -#define PWM_DUTY12 (*(IO_REG32 (PWM_BASE + 52))) // r/w: duty cycle channel 51:48 -/** PWM duty cycle register 13 (r/w) */ -#define PWM_DUTY13 (*(IO_REG32 (PWM_BASE + 56))) // r/w: duty cycle channel 55:52 -/** PWM duty cycle register 14 (r/w) */ -#define PWM_DUTY14 (*(IO_REG32 (PWM_BASE + 60))) // r/w: duty cycle channel 59:56 +/** PWM module prototype */ +typedef struct __attribute__((packed,aligned(4))) { + uint32_t CTRL; /**< offset 0: control register (#NEORV32_PWM_CTRL_enum) */ + uint32_t DUTY[15]; /**< offset 4..60: duty cycle register 0..14 */ +} neorv32_pwm_t; + +/** PWM module hardware access (#neorv32_pwm_t) */ +#define NEORV32_PWM (*((volatile neorv32_pwm_t*) (0xFFFFFE80UL))) /** PWM control register bits */ -enum NEORV32_PWM_CT_enum { - PWM_CT_EN = 0, /**< PWM control register(0) (r/w): PWM controller enable */ - PWM_CT_PRSC0 = 1, /**< PWM control register(1) (r/w): Clock prescaler select bit 0 */ - PWM_CT_PRSC1 = 2, /**< PWM control register(2) (r/w): Clock prescaler select bit 1 */ - PWM_CT_PRSC2 = 3 /**< PWM control register(3) (r/w): Clock prescaler select bit 2 */ +enum NEORV32_PWM_CTRL_enum { + PWM_CTRL_EN = 0, /**< PWM control register(0) (r/w): PWM controller enable */ + PWM_CTRL_PRSC0 = 1, /**< PWM control register(1) (r/w): Clock prescaler select bit 0 */ + PWM_CTRL_PRSC1 = 2, /**< PWM control register(2) (r/w): Clock prescaler select bit 1 */ + PWM_CTRL_PRSC2 = 3 /**< PWM control register(3) (r/w): Clock prescaler select bit 2 */ }; /**@}*/ @@ -664,55 +575,41 @@ enum NEORV32_PWM_CT_enum { * @name IO Device: Stream link interface (SLINK) **************************************************************************/ /**@{*/ -/** SLINK base address */ -#define SLINK_BASE (0xFFFFFEC0UL) // /**< SLINK base address */ -/** SLINK address space size in bytes */ -#define SLINK_SIZE (16*4) // /**< SLINK address space size in bytes */ - -/** SLINK control register (r/w) */ -#define SLINK_CT (*(IO_REG32 (SLINK_BASE + 0))) // r/w: control register -/** SLINK status register (r/-) */ -#define SLINK_STATUS (*(IO_ROM32 (SLINK_BASE + 16))) // r/-: status register -/** stream link 0 (r/w) */ -#define SLINK_CH0 (*(IO_REG32 (SLINK_BASE + 32 + 0))) // r/w: link 0 -/** stream link 1 (r/w) */ -#define SLINK_CH1 (*(IO_REG32 (SLINK_BASE + 32 + 4))) // r/w: link 1 -/** stream link 2 (r/w) */ -#define SLINK_CH2 (*(IO_REG32 (SLINK_BASE + 32 + 8))) // r/w: link 2 -/** stream link 3 (r/w) */ -#define SLINK_CH3 (*(IO_REG32 (SLINK_BASE + 32 + 12))) // r/w: link 3 -/** stream link 4 (r/w) */ -#define SLINK_CH4 (*(IO_REG32 (SLINK_BASE + 32 + 16))) // r/w: link 4 -/** stream link 5 (r/w) */ -#define SLINK_CH5 (*(IO_REG32 (SLINK_BASE + 32 + 20))) // r/w: link 5 -/** stream link 6 (r/w) */ -#define SLINK_CH6 (*(IO_REG32 (SLINK_BASE + 32 + 24))) // r/w: link 6 -/** stream link 7 (r/w) */ -#define SLINK_CH7 (*(IO_REG32 (SLINK_BASE + 32 + 28))) // r/w: link 7 +/** SLINK module prototype */ +typedef struct __attribute__((packed,aligned(4))) { + uint32_t CTRL; /**< offset 0: control register (#NEORV32_SLINK_CTRL_enum) */ + const uint32_t reserved[3]; /**< offset 4..12: reserved */ + uint32_t STATUS; /**< offset 16: status register (#NEORV32_SLINK_STATUS_enum) */ + const uint32_t reserved2[3]; /**< offset 20..28: reserved */ + uint32_t DATA[8]; /**< offset 32..60: stream link data channel 0..7 */ +} neorv32_slink_t; + +/** SLINK module hardware access (#neorv32_slink_t) */ +#define NEORV32_SLINK (*((volatile neorv32_slink_t*) (0xFFFFFEC0UL))) /** SLINK control register bits */ -enum NEORV32_SLINK_CT_enum { - SLINK_CT_RX_NUM0 = 0, /**< SLINK control register(0) (r/-): number of implemented RX links bit 0 */ - SLINK_CT_RX_NUM1 = 1, /**< SLINK control register(1) (r/-): number of implemented RX links bit 1 */ - SLINK_CT_RX_NUM2 = 2, /**< SLINK control register(2) (r/-): number of implemented RX links bit 2 */ - SLINK_CT_RX_NUM3 = 3, /**< SLINK control register(3) (r/-): number of implemented RX links bit 3 */ - - SLINK_CT_TX_NUM0 = 4, /**< SLINK control register(4) (r/-): number of implemented TX links bit 0 */ - SLINK_CT_TX_NUM1 = 5, /**< SLINK control register(5) (r/-): number of implemented TX links bit 1 */ - SLINK_CT_TX_NUM2 = 6, /**< SLINK control register(6) (r/-): number of implemented TX links bit 2 */ - SLINK_CT_TX_NUM3 = 7, /**< SLINK control register(7) (r/-): number of implemented TX links bit 3 */ - - SLINK_CT_RX_FIFO_S0 = 8, /**< SLINK control register( 8) (r/-): log2(RX FIFO size) bit 0 */ - SLINK_CT_RX_FIFO_S1 = 9, /**< SLINK control register( 9) (r/-): log2(RX FIFO size) bit 1 */ - SLINK_CT_RX_FIFO_S2 = 10, /**< SLINK control register(10) (r/-): log2(RX FIFO size) bit 2 */ - SLINK_CT_RX_FIFO_S3 = 11, /**< SLINK control register(11) (r/-): log2(RX FIFO size) bit 3 */ - - SLINK_CT_TX_FIFO_S0 = 12, /**< SLINK control register(12) (r/-): log2(TX FIFO size) bit 0 */ - SLINK_CT_TX_FIFO_S1 = 13, /**< SLINK control register(13) (r/-): log2(TX FIFO size) bit 1 */ - SLINK_CT_TX_FIFO_S2 = 14, /**< SLINK control register(14) (r/-): log2(TX FIFO size) bit 2 */ - SLINK_CT_TX_FIFO_S3 = 15, /**< SLINK control register(15) (r/-): log2(TX FIFO size) bit 3 */ - - SLINK_CT_EN = 31, /**< SLINK control register(0) (r/w): SLINK controller enable */ +enum NEORV32_SLINK_CTRL_enum { + SLINK_CTRL_RX_NUM0 = 0, /**< SLINK control register(0) (r/-): number of implemented RX links bit 0 */ + SLINK_CTRL_RX_NUM1 = 1, /**< SLINK control register(1) (r/-): number of implemented RX links bit 1 */ + SLINK_CTRL_RX_NUM2 = 2, /**< SLINK control register(2) (r/-): number of implemented RX links bit 2 */ + SLINK_CTRL_RX_NUM3 = 3, /**< SLINK control register(3) (r/-): number of implemented RX links bit 3 */ + + SLINK_CTRL_TX_NUM0 = 4, /**< SLINK control register(4) (r/-): number of implemented TX links bit 0 */ + SLINK_CTRL_TX_NUM1 = 5, /**< SLINK control register(5) (r/-): number of implemented TX links bit 1 */ + SLINK_CTRL_TX_NUM2 = 6, /**< SLINK control register(6) (r/-): number of implemented TX links bit 2 */ + SLINK_CTRL_TX_NUM3 = 7, /**< SLINK control register(7) (r/-): number of implemented TX links bit 3 */ + + SLINK_CTRL_RX_FIFO_S0 = 8, /**< SLINK control register( 8) (r/-): log2(RX FIFO size) bit 0 */ + SLINK_CTRL_RX_FIFO_S1 = 9, /**< SLINK control register( 9) (r/-): log2(RX FIFO size) bit 1 */ + SLINK_CTRL_RX_FIFO_S2 = 10, /**< SLINK control register(10) (r/-): log2(RX FIFO size) bit 2 */ + SLINK_CTRL_RX_FIFO_S3 = 11, /**< SLINK control register(11) (r/-): log2(RX FIFO size) bit 3 */ + + SLINK_CTRL_TX_FIFO_S0 = 12, /**< SLINK control register(12) (r/-): log2(TX FIFO size) bit 0 */ + SLINK_CTRL_TX_FIFO_S1 = 13, /**< SLINK control register(13) (r/-): log2(TX FIFO size) bit 1 */ + SLINK_CTRL_TX_FIFO_S2 = 14, /**< SLINK control register(14) (r/-): log2(TX FIFO size) bit 2 */ + SLINK_CTRL_TX_FIFO_S3 = 15, /**< SLINK control register(15) (r/-): log2(TX FIFO size) bit 3 */ + + SLINK_CTRL_EN = 31, /**< SLINK control register(0) (r/w): SLINK controller enable */ }; /** SLINK status register bits */ @@ -760,19 +657,16 @@ enum NEORV32_SLINK_STATUS_enum { * @name IO Device: External Interrupt Controller (XIRQ) **************************************************************************/ /**@{*/ -/** XIRQ base address */ -#define XIRQ_BASE (0xFFFFFF80UL) // /**< XIRQ base address */ -/** XIRQ address space size in bytes */ -#define XIRQ_SIZE (4*4) // /**< XIRQ address space size in bytes */ - -/** XIRQ IRQ input enable register (r/w) */ -#define XIRQ_IER (*(IO_REG32 (XIRQ_BASE + 0))) -/** XIRQ pending IRQ register /ack/clear (r/w) */ -#define XIRQ_IPR (*(IO_REG32 (XIRQ_BASE + 4))) -/** EXTIRW (time compare register) low word (r/w) */ -#define XIRQ_SCR (*(IO_REG32 (XIRQ_BASE + 8))) -// reserved -//#define XIRQ_reserved (*(IO_REG32 (XIRQ_BASE + 12))) +/** XIRQ module prototype */ +typedef struct __attribute__((packed,aligned(4))) { + uint32_t IER; /**< offset 0: IRQ input enable register */ + uint32_t IPR; /**< offset 4: pending IRQ register /ack/clear */ + uint32_t SCR; /**< offset 8: interrupt source register */ + const uint32_t reserved; /**< offset 12: reserved */ +} neorv32_xirq_t; + +/** XIRQ module hardware access (#neorv32_xirq_t) */ +#define NEORV32_XIRQ (*((volatile neorv32_xirq_t*) (0xFFFFFF80UL))) /**@}*/ @@ -780,24 +674,16 @@ enum NEORV32_SLINK_STATUS_enum { * @name IO Device: Machine System Timer (MTIME) **************************************************************************/ /**@{*/ -/** MTIME base address */ -#define MTIME_BASE (0xFFFFFF90UL) // /**< MTIME base address */ -/** MTIME address space size in bytes */ -#define MTIME_SIZE (4*4) // /**< MTIME address space size in bytes */ - -/** MTIME (time register) low word (r/w) */ -#define MTIME_LO (*(IO_REG32 (MTIME_BASE + 0))) -/** MTIME (time register) high word (r/w) */ -#define MTIME_HI (*(IO_REG32 (MTIME_BASE + 4))) -/** MTIMECMP (time compare register) low word (r/w) */ -#define MTIMECMP_LO (*(IO_REG32 (MTIME_BASE + 8))) -/** MTIMECMP (time register) high word (r/w) */ -#define MTIMECMP_HI (*(IO_REG32 (MTIME_BASE + 12))) - -/** MTIME (time register) 64-bit access (r/w) */ -#define MTIME (*(IO_REG64 (&MTIME_LO))) -/** MTIMECMP (time compare register) low word (r/w) */ -#define MTIMECMP (*(IO_REG64 (&MTIMECMP_LO))) +/** MTIME module prototype */ +typedef struct __attribute__((packed,aligned(4))) { + uint32_t TIME_LO; /**< offset 0: time register low word */ + uint32_t TIME_HI; /**< offset 4: time register high word */ + uint32_t TIMECMP_LO; /**< offset 8: compare register low word */ + uint32_t TIMECMP_HI; /**< offset 12: compare register high word */ +} neorv32_mtime_t; + +/** MTIME module hardware access (#neorv32_mtime_t) */ +#define NEORV32_MTIME (*((volatile neorv32_mtime_t*) (0xFFFFFF90UL))) /**@}*/ @@ -805,54 +691,51 @@ enum NEORV32_SLINK_STATUS_enum { * @name IO Device: Primary/Secondary Universal Asynchronous Receiver and Transmitter (UART0 / UART1) **************************************************************************/ /**@{*/ -/** UART0 base address */ -#define UART0_BASE (0xFFFFFFA0UL) // /**< UART0 base address */ -/** UART0 address space size in bytes */ -#define UART0_SIZE (2*4) // /**< UART0 address space size in bytes */ +/** UART0 module prototype */ +typedef struct __attribute__((packed,aligned(4))) { + uint32_t CTRL; /**< offset 0: control register (#NEORV32_UART_CTRL_enum) */ + uint32_t DATA; /**< offset 4: data register (#NEORV32_UART_DATA_enum) */ +} neorv32_uart0_t; -/** UART0 control register (r/w) */ -#define UART0_CT (*(IO_REG32 (UART0_BASE + 0))) -/** UART0 receive/transmit data register (r/w) */ -#define UART0_DATA (*(IO_REG32 (UART0_BASE + 4))) +/** UART0 module hardware access (#neorv32_uart0_t) */ +#define NEORV32_UART0 (*((volatile neorv32_uart0_t*) (0xFFFFFFA0UL))) +/** UART1 module prototype */ +typedef struct __attribute__((packed,aligned(4))) { + uint32_t CTRL; /**< offset 0: control register (#NEORV32_UART_CTRL_enum) */ + uint32_t DATA; /**< offset 4: data register (#NEORV32_UART_DATA_enum) */ +} neorv32_uart1_t; -/** UART1 base address */ -#define UART1_BASE (0xFFFFFFD0UL) // /**< UART1 base address */ -/** UART1 address space size in bytes */ -#define UART1_SIZE (2*4) // /**< UART1 address space size in bytes */ - -/** UART1 control register (r/w) */ -#define UART1_CT (*(IO_REG32 (UART1_BASE + 0))) -/** UART1 receive/transmit data register (r/w) */ -#define UART1_DATA (*(IO_REG32 (UART1_BASE + 4))) +/** UART1 module hardware access (#neorv32_uart1_t) */ +#define NEORV32_UART1 (*((volatile neorv32_uart1_t*) (0xFFFFFFD0UL))) /** UART0/UART1 control register bits */ -enum NEORV32_UART_CT_enum { - UART_CT_BAUD00 = 0, /**< UART control register(0) (r/w): BAUD rate config value lsb (12-bit, bit 0) */ - UART_CT_BAUD01 = 1, /**< UART control register(1) (r/w): BAUD rate config value (12-bit, bit 1) */ - UART_CT_BAUD02 = 2, /**< UART control register(2) (r/w): BAUD rate config value (12-bit, bit 2) */ - UART_CT_BAUD03 = 3, /**< UART control register(3) (r/w): BAUD rate config value (12-bit, bit 3) */ - UART_CT_BAUD04 = 4, /**< UART control register(4) (r/w): BAUD rate config value (12-bit, bit 4) */ - UART_CT_BAUD05 = 5, /**< UART control register(5) (r/w): BAUD rate config value (12-bit, bit 4) */ - UART_CT_BAUD06 = 6, /**< UART control register(6) (r/w): BAUD rate config value (12-bit, bit 5) */ - UART_CT_BAUD07 = 7, /**< UART control register(7) (r/w): BAUD rate config value (12-bit, bit 6) */ - UART_CT_BAUD08 = 8, /**< UART control register(8) (r/w): BAUD rate config value (12-bit, bit 7) */ - UART_CT_BAUD09 = 9, /**< UART control register(9) (r/w): BAUD rate config value (12-bit, bit 8) */ - UART_CT_BAUD10 = 10, /**< UART control register(10) (r/w): BAUD rate config value (12-bit, bit 9) */ - UART_CT_BAUD11 = 11, /**< UART control register(11) (r/w): BAUD rate config value msb (12-bit, bit 0) */ - UART_CT_SIM_MODE = 12, /**< UART control register(12) (r/w): Simulation output override enable, for use in simulation only */ - - UART_CT_RTS_EN = 20, /**< UART control register(20) (r/w): Enable hardware flow control: Assert RTS output if UART.RX is ready to receive */ - UART_CT_CTS_EN = 21, /**< UART control register(21) (r/w): Enable hardware flow control: UART.TX starts sending only if CTS input is asserted */ - UART_CT_PMODE0 = 22, /**< UART control register(22) (r/w): Parity configuration (0=even; 1=odd) */ - UART_CT_PMODE1 = 23, /**< UART control register(23) (r/w): Parity bit enabled when set */ - UART_CT_PRSC0 = 24, /**< UART control register(24) (r/w): BAUD rate clock prescaler select bit 0 */ - UART_CT_PRSC1 = 25, /**< UART control register(25) (r/w): BAUD rate clock prescaler select bit 1 */ - UART_CT_PRSC2 = 26, /**< UART control register(26) (r/w): BAUD rate clock prescaler select bit 2 */ - UART_CT_CTS = 27, /**< UART control register(27) (r/-): current state of CTS input */ - UART_CT_EN = 28, /**< UART control register(28) (r/w): UART global enable */ - - UART_CT_TX_BUSY = 31 /**< UART control register(31) (r/-): Transmitter is busy when set */ +enum NEORV32_UART_CTRL_enum { + UART_CTRL_BAUD00 = 0, /**< UART control register(0) (r/w): BAUD rate config value lsb (12-bit, bit 0) */ + UART_CTRL_BAUD01 = 1, /**< UART control register(1) (r/w): BAUD rate config value (12-bit, bit 1) */ + UART_CTRL_BAUD02 = 2, /**< UART control register(2) (r/w): BAUD rate config value (12-bit, bit 2) */ + UART_CTRL_BAUD03 = 3, /**< UART control register(3) (r/w): BAUD rate config value (12-bit, bit 3) */ + UART_CTRL_BAUD04 = 4, /**< UART control register(4) (r/w): BAUD rate config value (12-bit, bit 4) */ + UART_CTRL_BAUD05 = 5, /**< UART control register(5) (r/w): BAUD rate config value (12-bit, bit 4) */ + UART_CTRL_BAUD06 = 6, /**< UART control register(6) (r/w): BAUD rate config value (12-bit, bit 5) */ + UART_CTRL_BAUD07 = 7, /**< UART control register(7) (r/w): BAUD rate config value (12-bit, bit 6) */ + UART_CTRL_BAUD08 = 8, /**< UART control register(8) (r/w): BAUD rate config value (12-bit, bit 7) */ + UART_CTRL_BAUD09 = 9, /**< UART control register(9) (r/w): BAUD rate config value (12-bit, bit 8) */ + UART_CTRL_BAUD10 = 10, /**< UART control register(10) (r/w): BAUD rate config value (12-bit, bit 9) */ + UART_CTRL_BAUD11 = 11, /**< UART control register(11) (r/w): BAUD rate config value msb (12-bit, bit 0) */ + UART_CTRL_SIM_MODE = 12, /**< UART control register(12) (r/w): Simulation output override enable, for use in simulation only */ + + UART_CTRL_RTS_EN = 20, /**< UART control register(20) (r/w): Enable hardware flow control: Assert RTS output if UART.RX is ready to receive */ + UART_CTRL_CTS_EN = 21, /**< UART control register(21) (r/w): Enable hardware flow control: UART.TX starts sending only if CTS input is asserted */ + UART_CTRL_PMODE0 = 22, /**< UART control register(22) (r/w): Parity configuration (0=even; 1=odd) */ + UART_CTRL_PMODE1 = 23, /**< UART control register(23) (r/w): Parity bit enabled when set */ + UART_CTRL_PRSC0 = 24, /**< UART control register(24) (r/w): BAUD rate clock prescaler select bit 0 */ + UART_CTRL_PRSC1 = 25, /**< UART control register(25) (r/w): BAUD rate clock prescaler select bit 1 */ + UART_CTRL_PRSC2 = 26, /**< UART control register(26) (r/w): BAUD rate clock prescaler select bit 2 */ + UART_CTRL_CTS = 27, /**< UART control register(27) (r/-): current state of CTS input */ + UART_CTRL_EN = 28, /**< UART control register(28) (r/w): UART global enable */ + + UART_CTRL_TX_BUSY = 31 /**< UART control register(31) (r/-): Transmitter is busy when set */ }; /** UART0/UART1 parity configuration */ @@ -887,35 +770,34 @@ enum NEORV32_UART_DATA_enum { * @name IO Device: Serial Peripheral Interface Controller (SPI) **************************************************************************/ /**@{*/ -/** SPI base address */ -#define SPI_BASE (0xFFFFFFA8UL) // /**< SPI base address */ -/** SPI address space size in bytes */ -#define SPI_SIZE (2*4) // /**< SPI address space size in bytes */ +/** SPI module prototype */ +typedef struct __attribute__((packed,aligned(4))) { + uint32_t CTRL; /**< offset 0: control register (#NEORV32_SPI_CTRL_enum) */ + uint32_t DATA; /**< offset 4: data register */ +} neorv32_spi_t; -/** SPI control register (r/w) */ -#define SPI_CT (*(IO_REG32 (SPI_BASE + 0))) -/** SPI receive/transmit data register (r/w) */ -#define SPI_DATA (*(IO_REG32 (SPI_BASE + 4))) +/** SPI module hardware access (#neorv32_spi_t) */ +#define NEORV32_SPI (*((volatile neorv32_spi_t*) (0xFFFFFFA8UL))) /** SPI control register bits */ -enum NEORV32_SPI_CT_enum { - SPI_CT_CS0 = 0, /**< UART control register(0) (r/w): Direct chip select line 0 (output is low when set) */ - SPI_CT_CS1 = 1, /**< UART control register(1) (r/w): Direct chip select line 1 (output is low when set) */ - SPI_CT_CS2 = 2, /**< UART control register(2) (r/w): Direct chip select line 2 (output is low when set) */ - SPI_CT_CS3 = 3, /**< UART control register(3) (r/w): Direct chip select line 3 (output is low when set) */ - SPI_CT_CS4 = 4, /**< UART control register(4) (r/w): Direct chip select line 4 (output is low when set) */ - SPI_CT_CS5 = 5, /**< UART control register(5) (r/w): Direct chip select line 5 (output is low when set) */ - SPI_CT_CS6 = 6, /**< UART control register(6) (r/w): Direct chip select line 6 (output is low when set) */ - SPI_CT_CS7 = 7, /**< UART control register(7) (r/w): Direct chip select line 7 (output is low when set) */ - SPI_CT_EN = 8, /**< UART control register(8) (r/w): SPI unit enable */ - SPI_CT_CPHA = 9, /**< UART control register(9) (r/w): Clock polarity (idle polarity) */ - SPI_CT_PRSC0 = 10, /**< UART control register(10) (r/w): Clock prescaler select bit 0 */ - SPI_CT_PRSC1 = 11, /**< UART control register(11) (r/w): Clock prescaler select bit 1 */ - SPI_CT_PRSC2 = 12, /**< UART control register(12) (r/w): Clock prescaler select bit 2 */ - SPI_CT_SIZE0 = 13, /**< UART control register(13) (r/w): Transfer data size lsb (00: 8-bit, 01: 16-bit, 10: 24-bit, 11: 32-bit) */ - SPI_CT_SIZE1 = 14, /**< UART control register(14) (r/w): Transfer data size msb (00: 8-bit, 01: 16-bit, 10: 24-bit, 11: 32-bit) */ - - SPI_CT_BUSY = 31 /**< UART control register(31) (r/-): SPI busy flag */ +enum NEORV32_SPI_CTRL_enum { + SPI_CTRL_CS0 = 0, /**< UART control register(0) (r/w): Direct chip select line 0 (output is low when set) */ + SPI_CTRL_CS1 = 1, /**< UART control register(1) (r/w): Direct chip select line 1 (output is low when set) */ + SPI_CTRL_CS2 = 2, /**< UART control register(2) (r/w): Direct chip select line 2 (output is low when set) */ + SPI_CTRL_CS3 = 3, /**< UART control register(3) (r/w): Direct chip select line 3 (output is low when set) */ + SPI_CTRL_CS4 = 4, /**< UART control register(4) (r/w): Direct chip select line 4 (output is low when set) */ + SPI_CTRL_CS5 = 5, /**< UART control register(5) (r/w): Direct chip select line 5 (output is low when set) */ + SPI_CTRL_CS6 = 6, /**< UART control register(6) (r/w): Direct chip select line 6 (output is low when set) */ + SPI_CTRL_CS7 = 7, /**< UART control register(7) (r/w): Direct chip select line 7 (output is low when set) */ + SPI_CTRL_EN = 8, /**< UART control register(8) (r/w): SPI unit enable */ + SPI_CTRL_CPHA = 9, /**< UART control register(9) (r/w): Clock polarity (idle polarity) */ + SPI_CTRL_PRSC0 = 10, /**< UART control register(10) (r/w): Clock prescaler select bit 0 */ + SPI_CTRL_PRSC1 = 11, /**< UART control register(11) (r/w): Clock prescaler select bit 1 */ + SPI_CTRL_PRSC2 = 12, /**< UART control register(12) (r/w): Clock prescaler select bit 2 */ + SPI_CTRL_SIZE0 = 13, /**< UART control register(13) (r/w): Transfer data size lsb (00: 8-bit, 01: 16-bit, 10: 24-bit, 11: 32-bit) */ + SPI_CTRL_SIZE1 = 14, /**< UART control register(14) (r/w): Transfer data size msb (00: 8-bit, 01: 16-bit, 10: 24-bit, 11: 32-bit) */ + + SPI_CTRL_BUSY = 31 /**< UART control register(31) (r/-): SPI busy flag */ }; /**@}*/ @@ -924,29 +806,28 @@ enum NEORV32_SPI_CT_enum { * @name IO Device: Two-Wire Interface Controller (TWI) **************************************************************************/ /**@{*/ -/** TWI base address */ -#define TWI_BASE (0xFFFFFFB0UL) // /**< TWI base address */ -/** TWI address space size in bytes */ -#define TWI_SIZE (2*4) // /**< TWI address space size in bytes */ +/** TWI module prototype */ +typedef struct __attribute__((packed,aligned(4))) { + uint32_t CTRL; /**< offset 0: control register (#NEORV32_TWI_CTRL_enum) */ + uint32_t DATA; /**< offset 4: data register (#NEORV32_TWI_DATA_enum) */ +} neorv32_twi_t; -/** TWI control register (r/w) */ -#define TWI_CT (*(IO_REG32 (TWI_BASE + 0))) -/** TWI receive/transmit data register (r/w) */ -#define TWI_DATA (*(IO_REG32 (TWI_BASE + 4))) +/** TWI module hardware access (#neorv32_twi_t) */ +#define NEORV32_TWI (*((volatile neorv32_twi_t*) (0xFFFFFFB0UL))) /** TWI control register bits */ -enum NEORV32_TWI_CT_enum { - TWI_CT_EN = 0, /**< TWI control register(0) (r/w): TWI enable */ - TWI_CT_START = 1, /**< TWI control register(1) (-/w): Generate START condition, auto-clears */ - TWI_CT_STOP = 2, /**< TWI control register(2) (-/w): Generate STOP condition, auto-clears */ - TWI_CT_PRSC0 = 3, /**< TWI control register(3) (r/w): Clock prescaler select bit 0 */ - TWI_CT_PRSC1 = 4, /**< TWI control register(4) (r/w): Clock prescaler select bit 1 */ - TWI_CT_PRSC2 = 5, /**< TWI control register(5) (r/w): Clock prescaler select bit 2 */ - TWI_CT_MACK = 6, /**< TWI control register(6) (r/w): Generate controller ACK for each transmission */ - TWI_CT_CKSTEN = 7, /**< TWI control register(7) (r/w): Enable clock stretching (by peripheral) */ - - TWI_CT_ACK = 30, /**< TWI control register(30) (r/-): ACK received when set */ - TWI_CT_BUSY = 31 /**< TWI control register(31) (r/-): Transfer in progress, busy flag */ +enum NEORV32_TWI_CTRL_enum { + TWI_CTRL_EN = 0, /**< TWI control register(0) (r/w): TWI enable */ + TWI_CTRL_START = 1, /**< TWI control register(1) (-/w): Generate START condition, auto-clears */ + TWI_CTRL_STOP = 2, /**< TWI control register(2) (-/w): Generate STOP condition, auto-clears */ + TWI_CTRL_PRSC0 = 3, /**< TWI control register(3) (r/w): Clock prescaler select bit 0 */ + TWI_CTRL_PRSC1 = 4, /**< TWI control register(4) (r/w): Clock prescaler select bit 1 */ + TWI_CTRL_PRSC2 = 5, /**< TWI control register(5) (r/w): Clock prescaler select bit 2 */ + TWI_CTRL_MACK = 6, /**< TWI control register(6) (r/w): Generate controller ACK for each transmission */ + TWI_CTRL_CKSTEN = 7, /**< TWI control register(7) (r/w): Enable clock stretching (by peripheral) */ + + TWI_CTRL_ACK = 30, /**< TWI control register(30) (r/-): ACK received when set */ + TWI_CTRL_BUSY = 31 /**< TWI control register(31) (r/-): Transfer in progress, busy flag */ }; /** WTD receive/transmit data register bits */ @@ -961,21 +842,21 @@ enum NEORV32_TWI_DATA_enum { * @name IO Device: True Random Number Generator (TRNG) **************************************************************************/ /**@{*/ -/** TRNG base address */ -#define TRNG_BASE (0xFFFFFFB8UL) // /**< TRNG base address */ -/** TRNG address space size in bytes */ -#define TRNG_SIZE (1*4) // /**< TRNG address space size in bytes */ +/** TRNG module prototype */ +typedef struct __attribute__((packed,aligned(4))) { + uint32_t CTRL; /**< offset 0: control register (#NEORV32_TRNG_CTRL_enum) */ +} neorv32_trng_t; -/** TRNG control/data register (r/w) */ -#define TRNG_CT (*(IO_REG32 (TRNG_BASE + 0))) +/** TRNG module hardware access (#neorv32_trng_t) */ +#define NEORV32_TRNG (*((volatile neorv32_trng_t*) (0xFFFFFFB8UL))) /** TRNG control/data register bits */ -enum NEORV32_TRNG_CT_enum { - TRNG_CT_DATA_LSB = 0, /**< TRNG data/control register(0) (r/-): Random data byte LSB */ - TRNG_CT_DATA_MSB = 7, /**< TRNG data/control register(7) (r/-): Random data byte MSB */ +enum NEORV32_TRNG_CTRL_enum { + TRNG_CTRL_DATA_LSB = 0, /**< TRNG data/control register(0) (r/-): Random data byte LSB */ + TRNG_CTRL_DATA_MSB = 7, /**< TRNG data/control register(7) (r/-): Random data byte MSB */ - TRNG_CT_EN = 30, /**< TRNG data/control register(30) (r/w): TRNG enable */ - TRNG_CT_VALID = 31 /**< TRNG data/control register(31) (r/-): Random data output valid */ + TRNG_CTRL_EN = 30, /**< TRNG data/control register(30) (r/w): TRNG enable */ + TRNG_CTRL_VALID = 31 /**< TRNG data/control register(31) (r/-): Random data output valid */ }; /**@}*/ @@ -984,25 +865,25 @@ enum NEORV32_TRNG_CT_enum { * @name IO Device: Watchdog Timer (WDT) **************************************************************************/ /**@{*/ -/** WDT base address */ -#define WDT_BASE (0xFFFFFFBCUL) // /**< WDT base address */ -/** WDT address space size in bytes */ -#define WDT_SIZE (1*4) // /**< WDT address space size in bytes */ +/** WDT module prototype */ +typedef struct __attribute__((packed,aligned(4))) { + uint32_t CTRL; /**< offset 0: control register (#NEORV32_WDT_CTRL_enum) */ +} neorv32_wdt_t; -/** Watchdog control register (r/w) */ -#define WDT_CT (*(IO_REG32 (WDT_BASE + 0))) +/** WDT module hardware access (#neorv32_wdt_t) */ +#define NEORV32_WDT (*((volatile neorv32_wdt_t*) (0xFFFFFFBCUL))) /** WTD control register bits */ -enum NEORV32_WDT_CT_enum { - WDT_CT_EN = 0, /**< WDT control register(0) (r/w): Watchdog enable */ - WDT_CT_CLK_SEL0 = 1, /**< WDT control register(1) (r/w): Clock prescaler select bit 0 */ - WDT_CT_CLK_SEL1 = 2, /**< WDT control register(2) (r/w): Clock prescaler select bit 1 */ - WDT_CT_CLK_SEL2 = 3, /**< WDT control register(3) (r/w): Clock prescaler select bit 2 */ - WDT_CT_MODE = 4, /**< WDT control register(4) (r/w): Watchdog mode: 0=timeout causes interrupt, 1=timeout causes processor reset */ - WDT_CT_RCAUSE = 5, /**< WDT control register(5) (r/-): Cause of last system reset: 0=external reset, 1=watchdog */ - WDT_CT_RESET = 6, /**< WDT control register(6) (-/w): Reset WDT counter when set, auto-clears */ - WDT_CT_FORCE = 7, /**< WDT control register(7) (-/w): Force WDT action, auto-clears */ - WDT_CT_LOCK = 8 /**< WDT control register(8) (r/w): Lock write access to control register, clears on reset (HW or WDT) only */ +enum NEORV32_WDT_CTRL_enum { + WDT_CTRL_EN = 0, /**< WDT control register(0) (r/w): Watchdog enable */ + WDT_CTRL_CLK_SEL0 = 1, /**< WDT control register(1) (r/w): Clock prescaler select bit 0 */ + WDT_CTRL_CLK_SEL1 = 2, /**< WDT control register(2) (r/w): Clock prescaler select bit 1 */ + WDT_CTRL_CLK_SEL2 = 3, /**< WDT control register(3) (r/w): Clock prescaler select bit 2 */ + WDT_CTRL_MODE = 4, /**< WDT control register(4) (r/w): Watchdog mode: 0=timeout causes interrupt, 1=timeout causes processor reset */ + WDT_CTRL_RCAUSE = 5, /**< WDT control register(5) (r/-): Cause of last system reset: 0=external reset, 1=watchdog */ + WDT_CTRL_RESET = 6, /**< WDT control register(6) (-/w): Reset WDT counter when set, auto-clears */ + WDT_CTRL_FORCE = 7, /**< WDT control register(7) (-/w): Force WDT action, auto-clears */ + WDT_CTRL_LOCK = 8 /**< WDT control register(8) (r/w): Lock write access to control register, clears on reset (HW or WDT) only */ }; /**@}*/ @@ -1011,24 +892,16 @@ enum NEORV32_WDT_CT_enum { * @name IO Device: General Purpose Input/Output Port Unit (GPIO) **************************************************************************/ /**@{*/ -/** GPIO base address */ -#define GPIO_BASE (0xFFFFFFC0UL) // /**< GPIO base address */ -/** GPIO address space size in bytes */ -#define GPIO_SIZE (4*4) // /**< GPIO address space size in bytes */ - -/** GPIO parallel input port lower 32-bit (r/-) */ -#define GPIO_INPUT_LO (*(IO_ROM32 (GPIO_BASE + 0))) -/** GPIO parallel input port upper 32-bit (r/-) */ -#define GPIO_INPUT_HI (*(IO_ROM32 (GPIO_BASE + 4))) -/** GPIO parallel output port lower 32-bit (r/w) */ -#define GPIO_OUTPUT_LO (*(IO_REG32 (GPIO_BASE + 8))) -/** GPIO parallel output port upper 32-bit (r/w) */ -#define GPIO_OUTPUT_HI (*(IO_REG32 (GPIO_BASE + 12))) - -/** GPIO parallel input 64-bit access (r/-) */ -#define GPIO_INPUT (*(IO_ROM64 (&GPIO_INPUT_LO))) -/** GPIO parallel output 64-bit access (r/w) */ -#define GPIO_OUTPUT (*(IO_REG64 (&GPIO_OUTPUT_LO))) +/** GPIO module prototype */ +typedef struct __attribute__((packed,aligned(4))) { + const uint32_t INPUT_LO; /**< offset 0: parallel input port lower 32-bit */ + const uint32_t INPUT_HI; /**< offset 4: parallel input port upper 32-bit */ + uint32_t OUTPUT_LO; /**< offset 8: parallel output port lower 32-bit */ + uint32_t OUTPUT_HI; /**< offset 12: parallel output port upper 32-bit */ +} neorv32_gpio_t; + +/** GPIO module hardware access (#neorv32_gpio_t) */ +#define NEORV32_GPIO (*((volatile neorv32_gpio_t*) (0xFFFFFFC0UL))) /**@}*/ @@ -1036,88 +909,75 @@ enum NEORV32_WDT_CT_enum { * @name IO Device: Smart LED Hardware Interface (NEOLED) **************************************************************************/ /**@{*/ -/** NEOLED base address */ -#define NEOLED_BASE (0xFFFFFFD8UL) // /**< NEOLED base address */ -/** NEOLED address space size in bytes */ -#define NEOLED_SIZE (2*4) // /**< NEOLED address space size in bytes */ +/** NEOLED module prototype */ +typedef struct __attribute__((packed,aligned(4))) { + uint32_t CTRL; /**< offset 0: control register */ + uint32_t DATA; /**< offset 4: data register (#NEORV32_NEOLED_CTRL_enum) */ +} neorv32_neoled_t; -/** NEOLED control register (r/w) */ -#define NEOLED_CT (*(IO_REG32 (NEOLED_BASE + 0))) // r/w: control register -/** NEOLED TX data register (-/w) */ -#define NEOLED_DATA (*(IO_REG32 (NEOLED_BASE + 4))) // -/w: TX data register +/** NEOLED module hardware access (#neorv32_neoled_t) */ +#define NEORV32_NEOLED (*((volatile neorv32_neoled_t*) (0xFFFFFFD8UL))) /** NEOLED control register bits */ -enum NEORV32_NEOLED_CT_enum { - NEOLED_CT_EN = 0, /**< NEOLED control register(0) (r/w): NEOLED global enable */ - NEOLED_CT_MODE = 1, /**< NEOLED control register(1) (r/w): TX mode (0=24-bit, 1=32-bit) */ - NEOLED_CT_STROBE = 2, /**< NEOLED control register(2) (r/w): Strobe (0=send normal data, 1=send RESET command on data write) */ - NEOLED_CT_PRSC0 = 3, /**< NEOLED control register(3) (r/w): Clock prescaler select bit 0 (pulse-clock speed select) */ - NEOLED_CT_PRSC1 = 4, /**< NEOLED control register(4) (r/w): Clock prescaler select bit 1 (pulse-clock speed select) */ - NEOLED_CT_PRSC2 = 5, /**< NEOLED control register(5) (r/w): Clock prescaler select bit 2 (pulse-clock speed select) */ +enum NEORV32_NEOLED_CTRL_enum { + NEOLED_CTRL_EN = 0, /**< NEOLED control register(0) (r/w): NEOLED global enable */ + NEOLED_CTRL_MODE = 1, /**< NEOLED control register(1) (r/w): TX mode (0=24-bit, 1=32-bit) */ + NEOLED_CTRL_STROBE = 2, /**< NEOLED control register(2) (r/w): Strobe (0=send normal data, 1=send RESET command on data write) */ + NEOLED_CTRL_PRSC0 = 3, /**< NEOLED control register(3) (r/w): Clock prescaler select bit 0 (pulse-clock speed select) */ + NEOLED_CTRL_PRSC1 = 4, /**< NEOLED control register(4) (r/w): Clock prescaler select bit 1 (pulse-clock speed select) */ + NEOLED_CTRL_PRSC2 = 5, /**< NEOLED control register(5) (r/w): Clock prescaler select bit 2 (pulse-clock speed select) */ // - NEOLED_CT_BUFS_0 = 6, /**< NEOLED control register(6) (r/-): log2(tx buffer size) bit 0 */ - NEOLED_CT_BUFS_1 = 7, /**< NEOLED control register(7) (r/-): log2(tx buffer size) bit 1 */ - NEOLED_CT_BUFS_2 = 8, /**< NEOLED control register(8) (r/-): log2(tx buffer size) bit 2 */ - NEOLED_CT_BUFS_3 = 9, /**< NEOLED control register(9) (r/-): log2(tx buffer size) bit 3 */ + NEOLED_CTRL_BUFS_0 = 6, /**< NEOLED control register(6) (r/-): log2(tx buffer size) bit 0 */ + NEOLED_CTRL_BUFS_1 = 7, /**< NEOLED control register(7) (r/-): log2(tx buffer size) bit 1 */ + NEOLED_CTRL_BUFS_2 = 8, /**< NEOLED control register(8) (r/-): log2(tx buffer size) bit 2 */ + NEOLED_CTRL_BUFS_3 = 9, /**< NEOLED control register(9) (r/-): log2(tx buffer size) bit 3 */ // - NEOLED_CT_T_TOT_0 = 10, /**< NEOLED control register(10) (r/w): pulse-clock ticks per total period bit 0 */ - NEOLED_CT_T_TOT_1 = 11, /**< NEOLED control register(11) (r/w): pulse-clock ticks per total period bit 1 */ - NEOLED_CT_T_TOT_2 = 12, /**< NEOLED control register(12) (r/w): pulse-clock ticks per total period bit 2 */ - NEOLED_CT_T_TOT_3 = 13, /**< NEOLED control register(13) (r/w): pulse-clock ticks per total period bit 3 */ - NEOLED_CT_T_TOT_4 = 14, /**< NEOLED control register(14) (r/w): pulse-clock ticks per total period bit 4 */ + NEOLED_CTRL_T_TOT_0 = 10, /**< NEOLED control register(10) (r/w): pulse-clock ticks per total period bit 0 */ + NEOLED_CTRL_T_TOT_1 = 11, /**< NEOLED control register(11) (r/w): pulse-clock ticks per total period bit 1 */ + NEOLED_CTRL_T_TOT_2 = 12, /**< NEOLED control register(12) (r/w): pulse-clock ticks per total period bit 2 */ + NEOLED_CTRL_T_TOT_3 = 13, /**< NEOLED control register(13) (r/w): pulse-clock ticks per total period bit 3 */ + NEOLED_CTRL_T_TOT_4 = 14, /**< NEOLED control register(14) (r/w): pulse-clock ticks per total period bit 4 */ // - NEOLED_CT_T_ZERO_H_0 = 15, /**< NEOLED control register(15) (r/w): pulse-clock ticks per ZERO high-time bit 0 */ - NEOLED_CT_T_ZERO_H_1 = 16, /**< NEOLED control register(16) (r/w): pulse-clock ticks per ZERO high-time bit 1 */ - NEOLED_CT_T_ZERO_H_2 = 17, /**< NEOLED control register(17) (r/w): pulse-clock ticks per ZERO high-time bit 2 */ - NEOLED_CT_T_ZERO_H_3 = 18, /**< NEOLED control register(18) (r/w): pulse-clock ticks per ZERO high-time bit 3 */ - NEOLED_CT_T_ZERO_H_4 = 19, /**< NEOLED control register(19) (r/w): pulse-clock ticks per ZERO high-time bit 4 */ + NEOLED_CTRL_T_ZERO_H_0 = 15, /**< NEOLED control register(15) (r/w): pulse-clock ticks per ZERO high-time bit 0 */ + NEOLED_CTRL_T_ZERO_H_1 = 16, /**< NEOLED control register(16) (r/w): pulse-clock ticks per ZERO high-time bit 1 */ + NEOLED_CTRL_T_ZERO_H_2 = 17, /**< NEOLED control register(17) (r/w): pulse-clock ticks per ZERO high-time bit 2 */ + NEOLED_CTRL_T_ZERO_H_3 = 18, /**< NEOLED control register(18) (r/w): pulse-clock ticks per ZERO high-time bit 3 */ + NEOLED_CTRL_T_ZERO_H_4 = 19, /**< NEOLED control register(19) (r/w): pulse-clock ticks per ZERO high-time bit 4 */ // - NEOLED_CT_T_ONE_H_0 = 20, /**< NEOLED control register(20) (r/w): pulse-clock ticks per ONE high-time bit 0 */ - NEOLED_CT_T_ONE_H_1 = 21, /**< NEOLED control register(21) (r/w): pulse-clock ticks per ONE high-time bit 1 */ - NEOLED_CT_T_ONE_H_2 = 22, /**< NEOLED control register(22) (r/w): pulse-clock ticks per ONE high-time bit 2 */ - NEOLED_CT_T_ONE_H_3 = 23, /**< NEOLED control register(23) (r/w): pulse-clock ticks per ONE high-time bit 3 */ - NEOLED_CT_T_ONE_H_4 = 24, /**< NEOLED control register(24) (r/w): pulse-clock ticks per ONE high-time bit 4 */ + NEOLED_CTRL_T_ONE_H_0 = 20, /**< NEOLED control register(20) (r/w): pulse-clock ticks per ONE high-time bit 0 */ + NEOLED_CTRL_T_ONE_H_1 = 21, /**< NEOLED control register(21) (r/w): pulse-clock ticks per ONE high-time bit 1 */ + NEOLED_CTRL_T_ONE_H_2 = 22, /**< NEOLED control register(22) (r/w): pulse-clock ticks per ONE high-time bit 2 */ + NEOLED_CTRL_T_ONE_H_3 = 23, /**< NEOLED control register(23) (r/w): pulse-clock ticks per ONE high-time bit 3 */ + NEOLED_CTRL_T_ONE_H_4 = 24, /**< NEOLED control register(24) (r/w): pulse-clock ticks per ONE high-time bit 4 */ // - NEOLED_CT_TX_EMPTY = 28, /**< NEOLED control register(28) (r/-): TX FIFO is empty */ - NEOLED_CT_TX_HALF = 29, /**< NEOLED control register(29) (r/-): TX FIFO is at least half-full */ - NEOLED_CT_TX_FULL = 30, /**< NEOLED control register(30) (r/-): TX FIFO is full */ - NEOLED_CT_TX_BUSY = 31 /**< NEOLED control register(31) (r/-): busy / buffer status flag (configured via #NEOLED_CT_BSCON) */ + NEOLED_CTRL_TX_EMPTY = 28, /**< NEOLED control register(28) (r/-): TX FIFO is empty */ + NEOLED_CTRL_TX_HALF = 29, /**< NEOLED control register(29) (r/-): TX FIFO is at least half-full */ + NEOLED_CTRL_TX_FULL = 30, /**< NEOLED control register(30) (r/-): TX FIFO is full */ + NEOLED_CTRL_TX_BUSY = 31 /**< NEOLED control register(31) (r/-): busy / buffer status flag (configured via #NEOLED_CT_BSCON) */ }; /**@}*/ /**********************************************************************//** - * @name IO Device: System Configuration Info Memory (SYSINFO) + * @name IO Device: System Configuration Information Memory (SYSINFO) **************************************************************************/ /**@{*/ -/** SYSINFO base address */ -#define SYSINFO_BASE (0xFFFFFFE0UL) // /**< SYSINFO base address */ -/** SYSINFO address space size in bytes */ -#define SYSINFO_SIZE (8*4) // /**< SYSINFO address space size in bytes */ - -/** SYSINFO(0): Clock speed */ -#define SYSINFO_CLK (*(IO_ROM32 (SYSINFO_BASE + 0))) -/** SYSINFO(1): CPU core features */ -#define SYSINFO_CPU (*(IO_ROM32 (SYSINFO_BASE + 4))) -/** SYSINFO(2): Processor/SoC features */ -#define SYSINFO_FEATURES (*(IO_ROM32 (SYSINFO_BASE + 8))) -/** SYSINFO(3): Cache configuration */ -#define SYSINFO_CACHE (*(IO_ROM32 (SYSINFO_BASE + 12))) -/** SYSINFO(4): Instruction memory address space base */ -#define SYSINFO_ISPACE_BASE (*(IO_ROM32 (SYSINFO_BASE + 16))) -/** SYSINFO(5): Data memory address space base */ -#define SYSINFO_DSPACE_BASE (*(IO_ROM32 (SYSINFO_BASE + 20))) -/** SYSINFO(6): Internal instruction memory (IMEM) size in bytes */ -#define SYSINFO_IMEM_SIZE (*(IO_ROM32 (SYSINFO_BASE + 24))) -/** SYSINFO(7): Internal data memory (DMEM) size in bytes */ -#define SYSINFO_DMEM_SIZE (*(IO_ROM32 (SYSINFO_BASE + 28))) -/**@}*/ - - - -/**********************************************************************//** - * SYSINFO_CPU (r/-): Implemented CPU sub-extensions/features - **************************************************************************/ +/** SYSINFO module prototype */ +typedef struct __attribute__((packed,aligned(4))) { + const uint32_t CLK; /**< offset 0: clock speed in Hz */ + const uint32_t CPU; /**< offset 4: CPU core features (#NEORV32_SYSINFO_CPU_enum) */ + const uint32_t SOC; /**< offset 8: SoC features (#NEORV32_SYSINFO_SOC_enum) */ + const uint32_t CACHE; /**< offset 12: cache configuration (#NEORV32_SYSINFO_CACHE_enum) */ + const uint32_t ISPACE_BASE; /**< offset 16: instruction memory address space base */ + const uint32_t DSPACE_BASE; /**< offset 20: data memory address space base */ + const uint32_t IMEM_SIZE; /**< offset 24: internal instruction memory (IMEM) size in bytes */ + const uint32_t DMEM_SIZE; /**< offset 28: internal data memory (DMEM) size in bytes */ +} neorv32_sysinfo_t; + +/** SYSINFO module hardware access (#neorv32_sysinfo_t) */ +#define NEORV32_SYSINFO (*((volatile neorv32_sysinfo_t*) (0xFFFFFFE0UL))) + +/** NEORV32_SYSINFO.CPU (r/-): Implemented CPU sub-extensions/features */ enum NEORV32_SYSINFO_CPU_enum { SYSINFO_CPU_ZICSR = 0, /**< SYSINFO_CPU (0): Zicsr extension (I sub-extension) available when set (r/-) */ SYSINFO_CPU_ZIFENCEI = 1, /**< SYSINFO_CPU (1): Zifencei extension (I sub-extension) available when set (r/-) */ @@ -1135,38 +995,34 @@ enum NEORV32_SYSINFO_CPU_enum { SYSINFO_CPU_FASTSHIFT = 31 /**< SYSINFO_CPU (31): fast shifts (via FAST_SHIFT_EN generic) available when set (r/-) */ }; -/**********************************************************************//** - * SYSINFO_FEATURES (r/-): Implemented processor devices/features - **************************************************************************/ -enum NEORV32_SYSINFO_FEATURES_enum { - SYSINFO_FEATURES_BOOTLOADER = 0, /**< SYSINFO_FEATURES (0) (r/-): Bootloader implemented when 1 (via INT_BOOTLOADER_EN generic) */ - SYSINFO_FEATURES_MEM_EXT = 1, /**< SYSINFO_FEATURES (1) (r/-): External bus interface implemented when 1 (via MEM_EXT_EN generic) */ - SYSINFO_FEATURES_MEM_INT_IMEM = 2, /**< SYSINFO_FEATURES (2) (r/-): Processor-internal instruction memory implemented when 1 (via MEM_INT_IMEM_EN generic) */ - SYSINFO_FEATURES_MEM_INT_DMEM = 3, /**< SYSINFO_FEATURES (3) (r/-): Processor-internal data memory implemented when 1 (via MEM_INT_DMEM_EN generic) */ - SYSINFO_FEATURES_MEM_EXT_ENDIAN = 4, /**< SYSINFO_FEATURES (4) (r/-): External bus interface uses BIG-endian byte-order when 1 (via MEM_EXT_BIG_ENDIAN generic) */ - SYSINFO_FEATURES_ICACHE = 5, /**< SYSINFO_FEATURES (5) (r/-): Processor-internal instruction cache implemented when 1 (via ICACHE_EN generic) */ - - SYSINFO_FEATURES_OCD = 14, /**< SYSINFO_FEATURES (14) (r/-): On-chip debugger implemented when 1 (via ON_CHIP_DEBUGGER_EN generic) */ - SYSINFO_FEATURES_HW_RESET = 15, /**< SYSINFO_FEATURES (15) (r/-): Dedicated hardware reset of core registers implemented when 1 (via package's dedicated_reset_c constant) */ - - SYSINFO_FEATURES_IO_GPIO = 16, /**< SYSINFO_FEATURES (16) (r/-): General purpose input/output port unit implemented when 1 (via IO_GPIO_EN generic) */ - SYSINFO_FEATURES_IO_MTIME = 17, /**< SYSINFO_FEATURES (17) (r/-): Machine system timer implemented when 1 (via IO_MTIME_EN generic) */ - SYSINFO_FEATURES_IO_UART0 = 18, /**< SYSINFO_FEATURES (18) (r/-): Primary universal asynchronous receiver/transmitter 0 implemented when 1 (via IO_UART0_EN generic) */ - SYSINFO_FEATURES_IO_SPI = 19, /**< SYSINFO_FEATURES (19) (r/-): Serial peripheral interface implemented when 1 (via IO_SPI_EN generic) */ - SYSINFO_FEATURES_IO_TWI = 20, /**< SYSINFO_FEATURES (20) (r/-): Two-wire interface implemented when 1 (via IO_TWI_EN generic) */ - SYSINFO_FEATURES_IO_PWM = 21, /**< SYSINFO_FEATURES (21) (r/-): Pulse-width modulation unit implemented when 1 (via IO_PWM_EN generic) */ - SYSINFO_FEATURES_IO_WDT = 22, /**< SYSINFO_FEATURES (22) (r/-): Watchdog timer implemented when 1 (via IO_WDT_EN generic) */ - SYSINFO_FEATURES_IO_CFS = 23, /**< SYSINFO_FEATURES (23) (r/-): Custom functions subsystem implemented when 1 (via IO_CFS_EN generic) */ - SYSINFO_FEATURES_IO_TRNG = 24, /**< SYSINFO_FEATURES (24) (r/-): True random number generator implemented when 1 (via IO_TRNG_EN generic) */ - SYSINFO_FEATURES_IO_SLINK = 25, /**< SYSINFO_FEATURES (25) (r/-): Stream link interface implemented when 1 (via SLINK_NUM_RX & SLINK_NUM_TX generics) */ - SYSINFO_FEATURES_IO_UART1 = 26, /**< SYSINFO_FEATURES (26) (r/-): Secondary universal asynchronous receiver/transmitter 1 implemented when 1 (via IO_UART1_EN generic) */ - SYSINFO_FEATURES_IO_NEOLED = 27, /**< SYSINFO_FEATURES (27) (r/-): NeoPixel-compatible smart LED interface implemented when 1 (via IO_NEOLED_EN generic) */ - SYSINFO_FEATURES_IO_XIRQ = 28 /**< SYSINFO_FEATURES (28) (r/-): External interrupt controller implemented when 1 (via XIRQ_NUM_IO generic) */ +/** NEORV32_SYSINFO.SOC (r/-): Implemented processor devices/features */ +enum NEORV32_SYSINFO_SOC_enum { + SYSINFO_SOC_BOOTLOADER = 0, /**< SYSINFO_FEATURES (0) (r/-): Bootloader implemented when 1 (via INT_BOOTLOADER_EN generic) */ + SYSINFO_SOC_MEM_EXT = 1, /**< SYSINFO_FEATURES (1) (r/-): External bus interface implemented when 1 (via MEM_EXT_EN generic) */ + SYSINFO_SOC_MEM_INT_IMEM = 2, /**< SYSINFO_FEATURES (2) (r/-): Processor-internal instruction memory implemented when 1 (via MEM_INT_IMEM_EN generic) */ + SYSINFO_SOC_MEM_INT_DMEM = 3, /**< SYSINFO_FEATURES (3) (r/-): Processor-internal data memory implemented when 1 (via MEM_INT_DMEM_EN generic) */ + SYSINFO_SOC_MEM_EXT_ENDIAN = 4, /**< SYSINFO_FEATURES (4) (r/-): External bus interface uses BIG-endian byte-order when 1 (via MEM_EXT_BIG_ENDIAN generic) */ + SYSINFO_SOC_ICACHE = 5, /**< SYSINFO_FEATURES (5) (r/-): Processor-internal instruction cache implemented when 1 (via ICACHE_EN generic) */ + + SYSINFO_SOC_OCD = 14, /**< SYSINFO_FEATURES (14) (r/-): On-chip debugger implemented when 1 (via ON_CHIP_DEBUGGER_EN generic) */ + SYSINFO_SOC_HW_RESET = 15, /**< SYSINFO_FEATURES (15) (r/-): Dedicated hardware reset of core registers implemented when 1 (via package's dedicated_reset_c constant) */ + + SYSINFO_SOC_IO_GPIO = 16, /**< SYSINFO_FEATURES (16) (r/-): General purpose input/output port unit implemented when 1 (via IO_GPIO_EN generic) */ + SYSINFO_SOC_IO_MTIME = 17, /**< SYSINFO_FEATURES (17) (r/-): Machine system timer implemented when 1 (via IO_MTIME_EN generic) */ + SYSINFO_SOC_IO_UART0 = 18, /**< SYSINFO_FEATURES (18) (r/-): Primary universal asynchronous receiver/transmitter 0 implemented when 1 (via IO_UART0_EN generic) */ + SYSINFO_SOC_IO_SPI = 19, /**< SYSINFO_FEATURES (19) (r/-): Serial peripheral interface implemented when 1 (via IO_SPI_EN generic) */ + SYSINFO_SOC_IO_TWI = 20, /**< SYSINFO_FEATURES (20) (r/-): Two-wire interface implemented when 1 (via IO_TWI_EN generic) */ + SYSINFO_SOC_IO_PWM = 21, /**< SYSINFO_FEATURES (21) (r/-): Pulse-width modulation unit implemented when 1 (via IO_PWM_EN generic) */ + SYSINFO_SOC_IO_WDT = 22, /**< SYSINFO_FEATURES (22) (r/-): Watchdog timer implemented when 1 (via IO_WDT_EN generic) */ + SYSINFO_SOC_IO_CFS = 23, /**< SYSINFO_FEATURES (23) (r/-): Custom functions subsystem implemented when 1 (via IO_CFS_EN generic) */ + SYSINFO_SOC_IO_TRNG = 24, /**< SYSINFO_FEATURES (24) (r/-): True random number generator implemented when 1 (via IO_TRNG_EN generic) */ + SYSINFO_SOC_IO_SLINK = 25, /**< SYSINFO_FEATURES (25) (r/-): Stream link interface implemented when 1 (via SLINK_NUM_RX & SLINK_NUM_TX generics) */ + SYSINFO_SOC_IO_UART1 = 26, /**< SYSINFO_FEATURES (26) (r/-): Secondary universal asynchronous receiver/transmitter 1 implemented when 1 (via IO_UART1_EN generic) */ + SYSINFO_SOC_IO_NEOLED = 27, /**< SYSINFO_FEATURES (27) (r/-): NeoPixel-compatible smart LED interface implemented when 1 (via IO_NEOLED_EN generic) */ + SYSINFO_SOC_IO_XIRQ = 28 /**< SYSINFO_FEATURES (28) (r/-): External interrupt controller implemented when 1 (via XIRQ_NUM_IO generic) */ }; -/**********************************************************************//** - * SYSINFO_CACHE (r/-): Cache configuration - **************************************************************************/ +/** NEORV32_SYSINFO.CACHE (r/-): Cache configuration */ enum NEORV32_SYSINFO_CACHE_enum { SYSINFO_CACHE_IC_BLOCK_SIZE_0 = 0, /**< SYSINFO_CACHE (0) (r/-): i-cache: log2(Block size in bytes), bit 0 (via ICACHE_BLOCK_SIZE generic) */ SYSINFO_CACHE_IC_BLOCK_SIZE_1 = 1, /**< SYSINFO_CACHE (1) (r/-): i-cache: log2(Block size in bytes), bit 1 (via ICACHE_BLOCK_SIZE generic) */ @@ -1188,11 +1044,15 @@ enum NEORV32_SYSINFO_FEATURES_enum { SYSINFO_CACHE_IC_REPLACEMENT_2 = 14, /**< SYSINFO_CACHE (14) (r/-): i-cache: replacement policy (0001 = LRU if associativity > 0) bit 2 */ SYSINFO_CACHE_IC_REPLACEMENT_3 = 15, /**< SYSINFO_CACHE (15) (r/-): i-cache: replacement policy (0001 = LRU if associativity > 0) bit 3 */ }; +/**@}*/ // ---------------------------------------------------------------------------- // Include all IO driver headers // ---------------------------------------------------------------------------- +// legacy compatibility layer +#include "neorv32_legacy.h" + // cpu core #include "neorv32_cpu.h" @@ -1216,7 +1076,6 @@ enum NEORV32_SYSINFO_FEATURES_enum { #include "neorv32_wdt.h" #include "neorv32_xirq.h" - #ifdef __cplusplus } #endif From d435b3e9ff3a006868b80a6f906dda649d594581 Mon Sep 17 00:00:00 2001 From: stnolting Date: Fri, 17 Sep 2021 18:28:58 +0200 Subject: [PATCH 2/9] [sw/lib] ported all low-level drivers --- sw/lib/include/neorv32_cpu.h | 2 +- sw/lib/include/neorv32_neoled.h | 2 +- sw/lib/include/neorv32_slink.h | 32 ++++++------- sw/lib/source/neorv32_cfs.c | 2 +- sw/lib/source/neorv32_cpu.c | 73 +++++++++++++++++------------ sw/lib/source/neorv32_gpio.c | 37 ++++++++++----- sw/lib/source/neorv32_mtime.c | 30 +++++++----- sw/lib/source/neorv32_neoled.c | 50 ++++++++++---------- sw/lib/source/neorv32_pwm.c | 38 ++++++--------- sw/lib/source/neorv32_rte.c | 66 +++++++++++++------------- sw/lib/source/neorv32_slink.c | 82 ++++++++++++++++----------------- sw/lib/source/neorv32_spi.c | 36 +++++++-------- sw/lib/source/neorv32_trng.c | 16 +++---- sw/lib/source/neorv32_twi.c | 46 +++++++++--------- sw/lib/source/neorv32_uart.c | 76 +++++++++++++++--------------- sw/lib/source/neorv32_wdt.c | 26 +++++------ sw/lib/source/neorv32_xirq.c | 22 ++++----- 17 files changed, 332 insertions(+), 304 deletions(-) diff --git a/sw/lib/include/neorv32_cpu.h b/sw/lib/include/neorv32_cpu.h index dbef0565e..8124d0b99 100644 --- a/sw/lib/include/neorv32_cpu.h +++ b/sw/lib/include/neorv32_cpu.h @@ -50,7 +50,7 @@ void neorv32_cpu_set_mcycle(uint64_t value); uint64_t neorv32_cpu_get_instret(void); void neorv32_cpu_set_minstret(uint64_t value); uint64_t neorv32_cpu_get_systime(void); -void neorv32_cpu_delay_ms(int16_t time_ms); +void neorv32_cpu_delay_ms(uint32_t time_ms); void __attribute__((naked)) neorv32_cpu_goto_user_mode(void); uint32_t neorv32_cpu_pmp_get_num_regions(void); uint32_t neorv32_cpu_pmp_get_granularity(void); diff --git a/sw/lib/include/neorv32_neoled.h b/sw/lib/include/neorv32_neoled.h index b28c88dfe..f0d7ff750 100644 --- a/sw/lib/include/neorv32_neoled.h +++ b/sw/lib/include/neorv32_neoled.h @@ -66,7 +66,7 @@ uint32_t neorv32_neoled_get_buffer_size(void); **************************************************************************/ inline void __attribute__ ((always_inline)) neorv32_neoled_write_nonblocking(uint32_t data) { - NEOLED_DATA = data; // send new LED data + NEORV32_NEOLED.DATA = data; // send new LED data } #endif // neorv32_neoled_h diff --git a/sw/lib/include/neorv32_slink.h b/sw/lib/include/neorv32_slink.h index 8ecd38324..d88fb9262 100644 --- a/sw/lib/include/neorv32_slink.h +++ b/sw/lib/include/neorv32_slink.h @@ -80,7 +80,7 @@ int neorv32_slink_rx7_nonblocking(uint32_t *rx_data); * @param[in] tx_data Data to send to link. **************************************************************************/ inline void __attribute__ ((always_inline)) neorv32_slink_tx0_blocking(uint32_t tx_data) { - SLINK_CH0 = tx_data; + NEORV32_SLINK.DATA[0] = tx_data; } @@ -92,7 +92,7 @@ inline void __attribute__ ((always_inline)) neorv32_slink_tx0_blocking(uint32_t * @param[in] tx_data Data to send to link. **************************************************************************/ inline void __attribute__ ((always_inline)) neorv32_slink_tx1_blocking(uint32_t tx_data) { - SLINK_CH1 = tx_data; + NEORV32_SLINK.DATA[1] = tx_data; } @@ -104,7 +104,7 @@ inline void __attribute__ ((always_inline)) neorv32_slink_tx1_blocking(uint32_t * @param[in] tx_data Data to send to link. **************************************************************************/ inline void __attribute__ ((always_inline)) neorv32_slink_tx2_blocking(uint32_t tx_data) { - SLINK_CH2 = tx_data; + NEORV32_SLINK.DATA[2] = tx_data; } @@ -116,7 +116,7 @@ inline void __attribute__ ((always_inline)) neorv32_slink_tx2_blocking(uint32_t * @param[in] tx_data Data to send to link. **************************************************************************/ inline void __attribute__ ((always_inline)) neorv32_slink_tx3_blocking(uint32_t tx_data) { - SLINK_CH3 = tx_data; + NEORV32_SLINK.DATA[3] = tx_data; } @@ -128,7 +128,7 @@ inline void __attribute__ ((always_inline)) neorv32_slink_tx3_blocking(uint32_t * @param[in] tx_data Data to send to link. **************************************************************************/ inline void __attribute__ ((always_inline)) neorv32_slink_tx4_blocking(uint32_t tx_data) { - SLINK_CH4 = tx_data; + NEORV32_SLINK.DATA[4] = tx_data; } @@ -140,7 +140,7 @@ inline void __attribute__ ((always_inline)) neorv32_slink_tx4_blocking(uint32_t * @param[in] tx_data Data to send to link. **************************************************************************/ inline void __attribute__ ((always_inline)) neorv32_slink_tx5_blocking(uint32_t tx_data) { - SLINK_CH5 = tx_data; + NEORV32_SLINK.DATA[5] = tx_data; } @@ -152,7 +152,7 @@ inline void __attribute__ ((always_inline)) neorv32_slink_tx5_blocking(uint32_t * @param[in] tx_data Data to send to link. **************************************************************************/ inline void __attribute__ ((always_inline)) neorv32_slink_tx6_blocking(uint32_t tx_data) { - SLINK_CH6 = tx_data; + NEORV32_SLINK.DATA[6] = tx_data; } @@ -164,7 +164,7 @@ inline void __attribute__ ((always_inline)) neorv32_slink_tx6_blocking(uint32_t * @param[in] tx_data Data to send to link. **************************************************************************/ inline void __attribute__ ((always_inline)) neorv32_slink_tx7_blocking(uint32_t tx_data) { - SLINK_CH7 = tx_data; + NEORV32_SLINK.DATA[7] = tx_data; } @@ -176,7 +176,7 @@ inline void __attribute__ ((always_inline)) neorv32_slink_tx7_blocking(uint32_t * @param[in,out] rx_data Pointer to return read data. **************************************************************************/ inline void __attribute__ ((always_inline)) neorv32_slink_rx0_blocking(uint32_t *rx_data) { - *rx_data = SLINK_CH0; + *rx_data = NEORV32_SLINK.DATA[0]; } @@ -188,7 +188,7 @@ inline void __attribute__ ((always_inline)) neorv32_slink_rx0_blocking(uint32_t * @param[in,out] rx_data Pointer to return read data. **************************************************************************/ inline void __attribute__ ((always_inline)) neorv32_slink_rx1_blocking(uint32_t *rx_data) { - *rx_data = SLINK_CH1; + *rx_data = NEORV32_SLINK.DATA[1]; } @@ -200,7 +200,7 @@ inline void __attribute__ ((always_inline)) neorv32_slink_rx1_blocking(uint32_t * @param[in,out] rx_data Pointer to return read data. **************************************************************************/ inline void __attribute__ ((always_inline)) neorv32_slink_rx2_blocking(uint32_t *rx_data) { - *rx_data = SLINK_CH2; + *rx_data = NEORV32_SLINK.DATA[2]; } @@ -212,7 +212,7 @@ inline void __attribute__ ((always_inline)) neorv32_slink_rx2_blocking(uint32_t * @param[in,out] rx_data Pointer to return read data. **************************************************************************/ inline void __attribute__ ((always_inline)) neorv32_slink_rx3_blocking(uint32_t *rx_data) { - *rx_data = SLINK_CH3; + *rx_data = NEORV32_SLINK.DATA[3]; } @@ -224,7 +224,7 @@ inline void __attribute__ ((always_inline)) neorv32_slink_rx3_blocking(uint32_t * @param[in,out] rx_data Pointer to return read data. **************************************************************************/ inline void __attribute__ ((always_inline)) neorv32_slink_rx4_blocking(uint32_t *rx_data) { - *rx_data = SLINK_CH4; + *rx_data = NEORV32_SLINK.DATA[4]; } @@ -236,7 +236,7 @@ inline void __attribute__ ((always_inline)) neorv32_slink_rx4_blocking(uint32_t * @param[in,out] rx_data Pointer to return read data. **************************************************************************/ inline void __attribute__ ((always_inline)) neorv32_slink_rx5_blocking(uint32_t *rx_data) { - *rx_data = SLINK_CH5; + *rx_data = NEORV32_SLINK.DATA[5]; } @@ -248,7 +248,7 @@ inline void __attribute__ ((always_inline)) neorv32_slink_rx5_blocking(uint32_t * @param[in,out] rx_data Pointer to return read data. **************************************************************************/ inline void __attribute__ ((always_inline)) neorv32_slink_rx6_blocking(uint32_t *rx_data) { - *rx_data = SLINK_CH6; + *rx_data = NEORV32_SLINK.DATA[6]; } @@ -260,7 +260,7 @@ inline void __attribute__ ((always_inline)) neorv32_slink_rx6_blocking(uint32_t * @param[in,out] rx_data Pointer to return read data. **************************************************************************/ inline void __attribute__ ((always_inline)) neorv32_slink_rx7_blocking(uint32_t *rx_data) { - *rx_data = SLINK_CH7; + *rx_data = NEORV32_SLINK.DATA[7]; } diff --git a/sw/lib/source/neorv32_cfs.c b/sw/lib/source/neorv32_cfs.c index 787649503..97fded1ef 100644 --- a/sw/lib/source/neorv32_cfs.c +++ b/sw/lib/source/neorv32_cfs.c @@ -55,7 +55,7 @@ **************************************************************************/ int neorv32_cfs_available(void) { - if (SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_IO_CFS)) { + if (NEORV32_SYSINFO.SOC & (1 << SYSINFO_SOC_IO_CFS)) { return 1; } else { diff --git a/sw/lib/source/neorv32_cpu.c b/sw/lib/source/neorv32_cpu.c index 7fdb9f367..eae4ab24f 100644 --- a/sw/lib/source/neorv32_cpu.c +++ b/sw/lib/source/neorv32_cpu.c @@ -151,7 +151,7 @@ uint64_t neorv32_cpu_get_cycle(void) { uint32_t uint32[sizeof(uint64_t)/2]; } cycles; - uint32_t tmp1, tmp2, tmp3; + register uint32_t tmp1, tmp2, tmp3; while(1) { tmp1 = neorv32_cpu_csr_read(CSR_CYCLEH); tmp2 = neorv32_cpu_csr_read(CSR_CYCLE); @@ -202,7 +202,7 @@ uint64_t neorv32_cpu_get_instret(void) { uint32_t uint32[sizeof(uint64_t)/2]; } cycles; - uint32_t tmp1, tmp2, tmp3; + register uint32_t tmp1, tmp2, tmp3; while(1) { tmp1 = neorv32_cpu_csr_read(CSR_INSTRETH); tmp2 = neorv32_cpu_csr_read(CSR_INSTRET); @@ -253,7 +253,7 @@ uint64_t neorv32_cpu_get_systime(void) { uint32_t uint32[sizeof(uint64_t)/2]; } cycles; - uint32_t tmp1, tmp2, tmp3; + register uint32_t tmp1, tmp2, tmp3; while(1) { tmp1 = neorv32_cpu_csr_read(CSR_TIMEH); tmp2 = neorv32_cpu_csr_read(CSR_TIME); @@ -271,36 +271,51 @@ uint64_t neorv32_cpu_get_systime(void) { /**********************************************************************//** - * Simple delay function using busy wait (simple loop). + * Delay function using busy wait. * - * @warning This function is not really precise (especially if there is no M extension available)! Use a timer-based approach (using cycle or time CSRs) for precise timings. + * @note This function uses the time CSRs (from int./ext. MTIME). A simple ASM loop + * is used as fall back if system timer is not advancing (no MTIME available). * - * @param[in] time_ms Time in ms to wait (max 32767ms). + * @warning Delay time might be less precise if M extensions is not available + * (especially if MTIME unit is not available). + * + * @param[in] time_ms Time in ms to wait (unsigned 32-bit). **************************************************************************/ -void neorv32_cpu_delay_ms(int16_t time_ms) { - - const uint32_t loop_cycles_c = 16; // clock cycles per iteration of the ASM loop +void neorv32_cpu_delay_ms(uint32_t time_ms) { - // check input - if (time_ms < 0) { - time_ms = -time_ms; - } - - uint32_t clock = SYSINFO_CLK; // clock ticks per second + uint32_t clock = NEORV32_SYSINFO.CLK; // clock ticks per second clock = clock / 1000; // clock ticks per ms uint64_t wait_cycles = ((uint64_t)clock) * ((uint64_t)time_ms); - uint32_t ticks = (uint32_t)(wait_cycles / loop_cycles_c); - - asm volatile (" .balign 4 \n" // make sure this is 32-bit aligned - " __neorv32_cpu_delay_ms_start: \n" - " beq %[cnt_r], zero, __neorv32_cpu_delay_ms_end \n" // 3 cycles (not taken) - " beq %[cnt_r], zero, __neorv32_cpu_delay_ms_end \n" // 3 cycles (never taken) - " addi %[cnt_w], %[cnt_r], -1 \n" // 2 cycles - " nop \n" // 2 cycles - " j __neorv32_cpu_delay_ms_start \n" // 6 cycles - " __neorv32_cpu_delay_ms_end: " - : [cnt_w] "=r" (ticks) : [cnt_r] "r" (ticks)); + + register uint64_t tmp = neorv32_cpu_get_systime(); + if (neorv32_cpu_get_systime() > tmp) { // system time advancing (MTIME available and running)? + + // use MTIME machine timer + tmp += wait_cycles; + while(1) { + if (neorv32_cpu_get_systime() >= tmp) { + break; + } + } + } + else { + // use ASM loop + // warning! not really precise (especially if M extensions is not available)! + + const uint32_t loop_cycles_c = 16; // clock cycles per iteration of the ASM loop + uint32_t iterations = (uint32_t)(wait_cycles / loop_cycles_c); + + asm volatile (" .balign 4 \n" // make sure this is 32-bit aligned + " __neorv32_cpu_delay_ms_start: \n" + " beq %[cnt_r], zero, __neorv32_cpu_delay_ms_end \n" // 3 cycles (not taken) + " beq %[cnt_r], zero, __neorv32_cpu_delay_ms_end \n" // 3 cycles (never taken) + " addi %[cnt_w], %[cnt_r], -1 \n" // 2 cycles + " nop \n" // 2 cycles + " j __neorv32_cpu_delay_ms_start \n" // 6 cycles + " __neorv32_cpu_delay_ms_end: " + : [cnt_w] "=r" (iterations) : [cnt_r] "r" (iterations)); + } } @@ -332,7 +347,7 @@ void __attribute__((naked)) neorv32_cpu_goto_user_mode(void) { uint32_t neorv32_cpu_pmp_get_num_regions(void) { // PMP implemented at all? - if ((SYSINFO_CPU & (1<> NEOLED_CT_BUFS_0; + uint32_t tmp = NEORV32_NEOLED.CTRL; + tmp = tmp >> NEOLED_CTRL_BUFS_0; tmp = tmp & 0xf; // isolate buffer size bits return (1 << tmp); // num entries = pow(2, buffer size flags) diff --git a/sw/lib/source/neorv32_pwm.c b/sw/lib/source/neorv32_pwm.c index 2b0f05f4b..aa843864c 100644 --- a/sw/lib/source/neorv32_pwm.c +++ b/sw/lib/source/neorv32_pwm.c @@ -52,7 +52,7 @@ **************************************************************************/ int neorv32_pwm_available(void) { - if (SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_IO_PWM)) { + if (NEORV32_SYSINFO.SOC & (1 << SYSINFO_SOC_IO_PWM)) { return 1; } else { @@ -62,21 +62,21 @@ int neorv32_pwm_available(void) { /**********************************************************************//** - * Enable and configure pulse width modulation controller. The PWM control register bits are listed in #NEORV32_PWM_CT_enum. + * Enable and configure pulse width modulation controller. The PWM control register bits are listed in #NEORV32_PWM_CTRL_enum. * * @param[in] prsc Clock prescaler select (0..7). See #NEORV32_CLOCK_PRSC_enum. **************************************************************************/ void neorv32_pwm_setup(uint8_t prsc) { - PWM_CT = 0; // reset + NEORV32_PWM.CTRL = 0; // reset uint32_t ct_enable = 1; - ct_enable = ct_enable << PWM_CT_EN; + ct_enable = ct_enable << PWM_CTRL_EN; uint32_t ct_prsc = (uint32_t)(prsc & 0x07); - ct_prsc = ct_prsc << PWM_CT_PRSC0; + ct_prsc = ct_prsc << PWM_CTRL_PRSC0; - PWM_CT = ct_enable | ct_prsc; + NEORV32_PWM.CTRL = ct_enable | ct_prsc; } @@ -85,7 +85,7 @@ void neorv32_pwm_setup(uint8_t prsc) { **************************************************************************/ void neorv32_pwm_disable(void) { - PWM_CT &= ~((uint32_t)(1 << PWM_CT_EN)); + NEORV32_PWM.CTRL &= ~((uint32_t)(1 << PWM_CTRL_EN)); } @@ -94,7 +94,7 @@ void neorv32_pwm_disable(void) { **************************************************************************/ void neorv32_pwm_enable(void) { - PWM_CT |= ((uint32_t)(1 << PWM_CT_EN)); + NEORV32_PWM.CTRL |= ((uint32_t)(1 << PWM_CTRL_EN)); } @@ -132,23 +132,19 @@ void neorv32_pwm_set(uint8_t channel, uint8_t duty) { return; // out-of-range } - // compute duty-cycle offset - uint32_t reg_offset = (uint32_t)(channel / 4); - uint8_t byte_offset = channel % 4; - // read-modify-write uint32_t duty_mask = 0xff; uint32_t duty_new = (uint32_t)duty; - duty_mask = duty_mask << (byte_offset * 8); - duty_new = duty_new << (byte_offset * 8); + duty_mask = duty_mask << ((channel % 4) * 8); + duty_new = duty_new << ((channel % 4) * 8); - uint32_t duty_cycle = (*(IO_REG32 (&PWM_DUTY0 + reg_offset))); + uint32_t duty_cycle = NEORV32_PWM.DUTY[channel/4]; duty_cycle &= ~duty_mask; // clear previous duty cycle duty_cycle |= duty_new; // set new duty cycle - (*(IO_REG32 (&PWM_DUTY0 + reg_offset))) = duty_cycle; + NEORV32_PWM.DUTY[channel/4] = duty_cycle; } @@ -164,13 +160,7 @@ uint8_t neorv32_pwm_get(uint8_t channel) { return 0; // out-of-range } - // compute duty-cycle offset - uint32_t reg_offset = (uint32_t)(channel / 4); - uint8_t byte_offset = channel % 4; - - // read - uint32_t tmp = (*(IO_REG32 (&PWM_DUTY0 + reg_offset))); - tmp = tmp >> ((byte_offset * 8)); + uint32_t reg_data = NEORV32_PWM.DUTY[channel/4] >> (((channel % 4) * 8)); - return (uint8_t)tmp; + return (uint8_t)reg_data; } diff --git a/sw/lib/source/neorv32_rte.c b/sw/lib/source/neorv32_rte.c index d39bf1313..69263788e 100644 --- a/sw/lib/source/neorv32_rte.c +++ b/sw/lib/source/neorv32_rte.c @@ -277,16 +277,16 @@ void neorv32_rte_print_hw_config(void) { // Processor - general stuff neorv32_uart0_printf("\n=== << General >> ===\n" - "Clock speed: %u Hz\n", SYSINFO_CLK); - neorv32_uart0_printf("Full HW reset: "); __neorv32_rte_print_true_false(SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_HW_RESET)); + "Clock speed: %u Hz\n", NEORV32_SYSINFO.CLK); + neorv32_uart0_printf("Full HW reset: "); __neorv32_rte_print_true_false(NEORV32_SYSINFO.SOC & (1 << SYSINFO_SOC_HW_RESET)); neorv32_uart0_printf("Boot Config.: Boot "); - if (SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_BOOTLOADER)) { + if (NEORV32_SYSINFO.SOC & (1 << SYSINFO_SOC_BOOTLOADER)) { neorv32_uart0_printf("via Bootloader\n"); } else { - neorv32_uart0_printf("from memory (@ 0x%x)\n", SYSINFO_ISPACE_BASE); + neorv32_uart0_printf("from memory (@ 0x%x)\n", NEORV32_SYSINFO.ISPACE_BASE); } - neorv32_uart0_printf("On-chip debug: "); __neorv32_rte_print_true_false(SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_OCD)); + neorv32_uart0_printf("On-chip debug: "); __neorv32_rte_print_true_false(NEORV32_SYSINFO.SOC & (1 << SYSINFO_SOC_OCD)); // CPU configuration @@ -330,7 +330,7 @@ void neorv32_rte_print_hw_config(void) { } // Z* CPU extensions - tmp = SYSINFO_CPU; + tmp = NEORV32_SYSINFO.CPU; if (tmp & (1<> ===\n"); - neorv32_uart0_printf("Instr. base address: 0x%x\n", SYSINFO_ISPACE_BASE); + neorv32_uart0_printf("Instr. base address: 0x%x\n", NEORV32_SYSINFO.ISPACE_BASE); // IMEM neorv32_uart0_printf("Internal IMEM: "); - if (SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_MEM_INT_IMEM)) { - neorv32_uart0_printf("yes, %u bytes\n", SYSINFO_IMEM_SIZE); + if (NEORV32_SYSINFO.SOC & (1 << SYSINFO_SOC_MEM_INT_IMEM)) { + neorv32_uart0_printf("yes, %u bytes\n", NEORV32_SYSINFO.IMEM_SIZE); } else { neorv32_uart0_printf("no\n"); } // DMEM - neorv32_uart0_printf("Data base address: 0x%x\n", SYSINFO_DSPACE_BASE); + neorv32_uart0_printf("Data base address: 0x%x\n", NEORV32_SYSINFO.DSPACE_BASE); neorv32_uart0_printf("Internal DMEM: "); - if (SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_MEM_INT_DMEM)) { neorv32_uart0_printf("yes, %u bytes\n", SYSINFO_DMEM_SIZE); } + if (NEORV32_SYSINFO.SOC & (1 << SYSINFO_SOC_MEM_INT_DMEM)) { neorv32_uart0_printf("yes, %u bytes\n", NEORV32_SYSINFO.DMEM_SIZE); } else { neorv32_uart0_printf("no\n"); } // i-cache neorv32_uart0_printf("Internal i-cache: "); - __neorv32_rte_print_true_false(SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_ICACHE)); - if (SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_ICACHE)) { + __neorv32_rte_print_true_false(NEORV32_SYSINFO.SOC & (1 << SYSINFO_SOC_ICACHE)); + if (NEORV32_SYSINFO.SOC & (1 << SYSINFO_SOC_ICACHE)) { neorv32_uart0_printf("- "); - uint32_t ic_block_size = (SYSINFO_CACHE >> SYSINFO_CACHE_IC_BLOCK_SIZE_0) & 0x0F; + uint32_t ic_block_size = (NEORV32_SYSINFO.CACHE >> SYSINFO_CACHE_IC_BLOCK_SIZE_0) & 0x0F; if (ic_block_size) { ic_block_size = 1 << ic_block_size; } @@ -412,7 +412,7 @@ void neorv32_rte_print_hw_config(void) { ic_block_size = 0; } - uint32_t ic_num_blocks = (SYSINFO_CACHE >> SYSINFO_CACHE_IC_NUM_BLOCKS_0) & 0x0F; + uint32_t ic_num_blocks = (NEORV32_SYSINFO.CACHE >> SYSINFO_CACHE_IC_NUM_BLOCKS_0) & 0x0F; if (ic_num_blocks) { ic_num_blocks = 1 << ic_num_blocks; } @@ -420,14 +420,14 @@ void neorv32_rte_print_hw_config(void) { ic_num_blocks = 0; } - uint32_t ic_associativity = (SYSINFO_CACHE >> SYSINFO_CACHE_IC_ASSOCIATIVITY_0) & 0x0F; + uint32_t ic_associativity = (NEORV32_SYSINFO.CACHE >> SYSINFO_CACHE_IC_ASSOCIATIVITY_0) & 0x0F; ic_associativity = 1 << ic_associativity; neorv32_uart0_printf("%u bytes: %u set(s), %u block(s) per set, %u bytes per block", ic_associativity*ic_num_blocks*ic_block_size, ic_associativity, ic_num_blocks, ic_block_size); if (ic_associativity == 1) { neorv32_uart0_printf(" (direct-mapped)\n"); } - else if (((SYSINFO_CACHE >> SYSINFO_CACHE_IC_REPLACEMENT_0) & 0x0F) == 1) { + else if (((NEORV32_SYSINFO.CACHE >> SYSINFO_CACHE_IC_REPLACEMENT_0) & 0x0F) == 1) { neorv32_uart0_printf(" (LRU replacement policy)\n"); } else { @@ -436,9 +436,9 @@ void neorv32_rte_print_hw_config(void) { } neorv32_uart0_printf("Ext. bus interface: "); - __neorv32_rte_print_true_false(SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_MEM_EXT)); + __neorv32_rte_print_true_false(NEORV32_SYSINFO.SOC & (1 << SYSINFO_SOC_MEM_EXT)); neorv32_uart0_printf("Ext. bus Endianness: "); - if (SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_MEM_EXT_ENDIAN)) { + if (NEORV32_SYSINFO.SOC & (1 << SYSINFO_SOC_MEM_EXT_ENDIAN)) { neorv32_uart0_printf("big\n"); } else { @@ -448,20 +448,20 @@ void neorv32_rte_print_hw_config(void) { // peripherals neorv32_uart0_printf("\n=== << Peripherals >> ===\n"); - tmp = SYSINFO_FEATURES; - neorv32_uart0_printf("GPIO - "); __neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_GPIO)); - neorv32_uart0_printf("MTIME - "); __neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_MTIME)); - neorv32_uart0_printf("UART0 - "); __neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_UART0)); - neorv32_uart0_printf("UART1 - "); __neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_UART1)); - neorv32_uart0_printf("SPI - "); __neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_SPI)); - neorv32_uart0_printf("TWI - "); __neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_TWI)); - neorv32_uart0_printf("PWM - "); __neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_PWM)); - neorv32_uart0_printf("WDT - "); __neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_WDT)); - neorv32_uart0_printf("TRNG - "); __neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_TRNG)); - neorv32_uart0_printf("CFS - "); __neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_CFS)); - neorv32_uart0_printf("SLINK - "); __neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_SLINK)); - neorv32_uart0_printf("NEOLED - "); __neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_NEOLED)); - neorv32_uart0_printf("XIRQ - "); __neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_XIRQ)); + tmp = NEORV32_SYSINFO.SOC; + neorv32_uart0_printf("GPIO - "); __neorv32_rte_print_true_false(tmp & (1 << SYSINFO_SOC_IO_GPIO)); + neorv32_uart0_printf("MTIME - "); __neorv32_rte_print_true_false(tmp & (1 << SYSINFO_SOC_IO_MTIME)); + neorv32_uart0_printf("UART0 - "); __neorv32_rte_print_true_false(tmp & (1 << SYSINFO_SOC_IO_UART0)); + neorv32_uart0_printf("UART1 - "); __neorv32_rte_print_true_false(tmp & (1 << SYSINFO_SOC_IO_UART1)); + neorv32_uart0_printf("SPI - "); __neorv32_rte_print_true_false(tmp & (1 << SYSINFO_SOC_IO_SPI)); + neorv32_uart0_printf("TWI - "); __neorv32_rte_print_true_false(tmp & (1 << SYSINFO_SOC_IO_TWI)); + neorv32_uart0_printf("PWM - "); __neorv32_rte_print_true_false(tmp & (1 << SYSINFO_SOC_IO_PWM)); + neorv32_uart0_printf("WDT - "); __neorv32_rte_print_true_false(tmp & (1 << SYSINFO_SOC_IO_WDT)); + neorv32_uart0_printf("TRNG - "); __neorv32_rte_print_true_false(tmp & (1 << SYSINFO_SOC_IO_TRNG)); + neorv32_uart0_printf("CFS - "); __neorv32_rte_print_true_false(tmp & (1 << SYSINFO_SOC_IO_CFS)); + neorv32_uart0_printf("SLINK - "); __neorv32_rte_print_true_false(tmp & (1 << SYSINFO_SOC_IO_SLINK)); + neorv32_uart0_printf("NEOLED - "); __neorv32_rte_print_true_false(tmp & (1 << SYSINFO_SOC_IO_NEOLED)); + neorv32_uart0_printf("XIRQ - "); __neorv32_rte_print_true_false(tmp & (1 << SYSINFO_SOC_IO_XIRQ)); } diff --git a/sw/lib/source/neorv32_slink.c b/sw/lib/source/neorv32_slink.c index fa175760d..76ef43bb3 100644 --- a/sw/lib/source/neorv32_slink.c +++ b/sw/lib/source/neorv32_slink.c @@ -50,7 +50,7 @@ **************************************************************************/ int neorv32_slink_available(void) { - if (SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_IO_SLINK)) { + if (NEORV32_SYSINFO.SOC & (1 << SYSINFO_SOC_IO_SLINK)) { return 1; } else { @@ -64,7 +64,7 @@ int neorv32_slink_available(void) { **************************************************************************/ void neorv32_slink_enable(void) { - SLINK_CT |= (uint32_t)(1 << SLINK_CT_EN); + NEORV32_SLINK.CTRL |= (uint32_t)(1 << SLINK_CTRL_EN); } @@ -75,7 +75,7 @@ void neorv32_slink_enable(void) { **************************************************************************/ void neorv32_slink_disable(void) { - SLINK_CT &= ~(uint32_t)(1 << SLINK_CT_EN); + NEORV32_SLINK.CTRL &= ~(uint32_t)(1 << SLINK_CTRL_EN); } @@ -87,7 +87,7 @@ void neorv32_slink_disable(void) { int neorv32_slink_get_rx_num(void) { if (neorv32_slink_available()) { - return (int)((SLINK_CT >> SLINK_CT_RX_NUM0) & 0xf); + return (int)((NEORV32_SLINK.CTRL >> SLINK_CTRL_RX_NUM0) & 0xf); } else { return 0; @@ -103,7 +103,7 @@ int neorv32_slink_get_rx_num(void) { int neorv32_slink_get_tx_num(void) { if (neorv32_slink_available()) { - return (int)((SLINK_CT >> SLINK_CT_TX_NUM0) & 0xf); + return (int)((NEORV32_SLINK.CTRL >> SLINK_CTRL_TX_NUM0) & 0xf); } else { return 0; @@ -119,7 +119,7 @@ int neorv32_slink_get_tx_num(void) { int neorv32_slink_get_rx_depth(void) { if (neorv32_slink_available()) { - uint32_t tmp = (SLINK_CT >> SLINK_CT_RX_FIFO_S0) & 0x0f; + uint32_t tmp = (NEORV32_SLINK.CTRL >> SLINK_CTRL_RX_FIFO_S0) & 0x0f; return (int)(1 << tmp); } else { @@ -136,7 +136,7 @@ int neorv32_slink_get_rx_depth(void) { int neorv32_slink_get_tx_depth(void) { if (neorv32_slink_available()) { - uint32_t tmp = (SLINK_CT >> SLINK_CT_TX_FIFO_S0) & 0x0f; + uint32_t tmp = (NEORV32_SLINK.CTRL >> SLINK_CTRL_TX_FIFO_S0) & 0x0f; return (int)(1 << tmp); } else { @@ -155,7 +155,7 @@ int neorv32_slink_check_rx_half_full(int link_id) { const uint32_t mask = 1 << SLINK_STATUS_RX0_HALF; - if (SLINK_STATUS & (mask << (link_id & 0x7))) { + if (NEORV32_SLINK.STATUS & (mask << (link_id & 0x7))) { return 1; } else { @@ -174,7 +174,7 @@ int neorv32_slink_check_tx_half_full(int link_id) { const uint32_t mask = 1 << SLINK_STATUS_TX0_HALF; - if (SLINK_STATUS & (mask << (link_id & 0x7))) { + if (NEORV32_SLINK.STATUS & (mask << (link_id & 0x7))) { return 1; } else { @@ -191,8 +191,8 @@ int neorv32_slink_check_tx_half_full(int link_id) { **************************************************************************/ int neorv32_slink_tx0_nonblocking(uint32_t tx_data) { - if (SLINK_STATUS & (1 << SLINK_STATUS_TX0_FREE)) { - SLINK_CH0 = tx_data; + if (NEORV32_SLINK.STATUS & (1 << SLINK_STATUS_TX0_FREE)) { + NEORV32_SLINK.DATA[0] = tx_data; return 0; } return 1; @@ -207,8 +207,8 @@ int neorv32_slink_tx0_nonblocking(uint32_t tx_data) { **************************************************************************/ int neorv32_slink_tx1_nonblocking(uint32_t tx_data) { - if (SLINK_STATUS & (1 << SLINK_STATUS_TX1_FREE)) { - SLINK_CH1 = tx_data; + if (NEORV32_SLINK.STATUS & (1 << SLINK_STATUS_TX1_FREE)) { + NEORV32_SLINK.DATA[1] = tx_data; return 0; } return 1; @@ -223,8 +223,8 @@ int neorv32_slink_tx1_nonblocking(uint32_t tx_data) { **************************************************************************/ int neorv32_slink_tx2_nonblocking(uint32_t tx_data) { - if (SLINK_STATUS & (1 << SLINK_STATUS_TX2_FREE)) { - SLINK_CH2 = tx_data; + if (NEORV32_SLINK.STATUS & (1 << SLINK_STATUS_TX2_FREE)) { + NEORV32_SLINK.DATA[2] = tx_data; return 0; } return 1; @@ -239,8 +239,8 @@ int neorv32_slink_tx2_nonblocking(uint32_t tx_data) { **************************************************************************/ int neorv32_slink_tx3_nonblocking(uint32_t tx_data) { - if (SLINK_STATUS & (1 << SLINK_STATUS_TX3_FREE)) { - SLINK_CH3 = tx_data; + if (NEORV32_SLINK.STATUS & (1 << SLINK_STATUS_TX3_FREE)) { + NEORV32_SLINK.DATA[3] = tx_data; return 0; } return 1; @@ -255,8 +255,8 @@ int neorv32_slink_tx3_nonblocking(uint32_t tx_data) { **************************************************************************/ int neorv32_slink_tx4_nonblocking(uint32_t tx_data) { - if (SLINK_STATUS & (1 << SLINK_STATUS_TX4_FREE)) { - SLINK_CH4 = tx_data; + if (NEORV32_SLINK.STATUS & (1 << SLINK_STATUS_TX4_FREE)) { + NEORV32_SLINK.DATA[4] = tx_data; return 0; } return 1; @@ -271,8 +271,8 @@ int neorv32_slink_tx4_nonblocking(uint32_t tx_data) { **************************************************************************/ int neorv32_slink_tx5_nonblocking(uint32_t tx_data) { - if (SLINK_STATUS & (1 << SLINK_STATUS_TX5_FREE)) { - SLINK_CH5 = tx_data; + if (NEORV32_SLINK.STATUS & (1 << SLINK_STATUS_TX5_FREE)) { + NEORV32_SLINK.DATA[5] = tx_data; return 0; } return 1; @@ -287,8 +287,8 @@ int neorv32_slink_tx5_nonblocking(uint32_t tx_data) { **************************************************************************/ int neorv32_slink_tx6_nonblocking(uint32_t tx_data) { - if (SLINK_STATUS & (1 << SLINK_STATUS_TX6_FREE)) { - SLINK_CH6 = tx_data; + if (NEORV32_SLINK.STATUS & (1 << SLINK_STATUS_TX6_FREE)) { + NEORV32_SLINK.DATA[6] = tx_data; return 0; } return 1; @@ -303,8 +303,8 @@ int neorv32_slink_tx6_nonblocking(uint32_t tx_data) { **************************************************************************/ int neorv32_slink_tx7_nonblocking(uint32_t tx_data) { - if (SLINK_STATUS & (1 << SLINK_STATUS_TX7_FREE)) { - SLINK_CH7 = tx_data; + if (NEORV32_SLINK.STATUS & (1 << SLINK_STATUS_TX7_FREE)) { + NEORV32_SLINK.DATA[7] = tx_data; return 0; } return 1; @@ -319,8 +319,8 @@ int neorv32_slink_tx7_nonblocking(uint32_t tx_data) { **************************************************************************/ int neorv32_slink_rx0_nonblocking(uint32_t *rx_data) { - if (SLINK_STATUS & (1 << SLINK_STATUS_RX0_AVAIL)) { - *rx_data = SLINK_CH0; + if (NEORV32_SLINK.STATUS & (1 << SLINK_STATUS_RX0_AVAIL)) { + *rx_data = NEORV32_SLINK.DATA[0]; return 0; } return 1; @@ -335,8 +335,8 @@ int neorv32_slink_rx0_nonblocking(uint32_t *rx_data) { **************************************************************************/ int neorv32_slink_rx1_nonblocking(uint32_t *rx_data) { - if (SLINK_STATUS & (1 << SLINK_STATUS_RX1_AVAIL)) { - *rx_data = SLINK_CH1; + if (NEORV32_SLINK.STATUS & (1 << SLINK_STATUS_RX1_AVAIL)) { + *rx_data = NEORV32_SLINK.DATA[1]; return 0; } return 1; @@ -351,8 +351,8 @@ int neorv32_slink_rx1_nonblocking(uint32_t *rx_data) { **************************************************************************/ int neorv32_slink_rx2_nonblocking(uint32_t *rx_data) { - if (SLINK_STATUS & (1 << SLINK_STATUS_RX2_AVAIL)) { - *rx_data = SLINK_CH2; + if (NEORV32_SLINK.STATUS & (1 << SLINK_STATUS_RX2_AVAIL)) { + *rx_data = NEORV32_SLINK.DATA[2]; return 0; } return 1; @@ -367,8 +367,8 @@ int neorv32_slink_rx2_nonblocking(uint32_t *rx_data) { **************************************************************************/ int neorv32_slink_rx3_nonblocking(uint32_t *rx_data) { - if (SLINK_STATUS & (1 << SLINK_STATUS_RX3_AVAIL)) { - *rx_data = SLINK_CH3; + if (NEORV32_SLINK.STATUS & (1 << SLINK_STATUS_RX3_AVAIL)) { + *rx_data = NEORV32_SLINK.DATA[3]; return 0; } return 1; @@ -383,8 +383,8 @@ int neorv32_slink_rx3_nonblocking(uint32_t *rx_data) { **************************************************************************/ int neorv32_slink_rx4_nonblocking(uint32_t *rx_data) { - if (SLINK_STATUS & (1 << SLINK_STATUS_RX4_AVAIL)) { - *rx_data = SLINK_CH4; + if (NEORV32_SLINK.STATUS & (1 << SLINK_STATUS_RX4_AVAIL)) { + *rx_data = NEORV32_SLINK.DATA[4]; return 0; } return 1; @@ -399,8 +399,8 @@ int neorv32_slink_rx4_nonblocking(uint32_t *rx_data) { **************************************************************************/ int neorv32_slink_rx5_nonblocking(uint32_t *rx_data) { - if (SLINK_STATUS & (1 << SLINK_STATUS_RX5_AVAIL)) { - *rx_data = SLINK_CH5; + if (NEORV32_SLINK.STATUS & (1 << SLINK_STATUS_RX5_AVAIL)) { + *rx_data = NEORV32_SLINK.DATA[5]; return 0; } return 1; @@ -415,8 +415,8 @@ int neorv32_slink_rx5_nonblocking(uint32_t *rx_data) { **************************************************************************/ int neorv32_slink_rx6_nonblocking(uint32_t *rx_data) { - if (SLINK_STATUS & (1 << SLINK_STATUS_RX6_AVAIL)) { - *rx_data = SLINK_CH6; + if (NEORV32_SLINK.STATUS & (1 << SLINK_STATUS_RX6_AVAIL)) { + *rx_data = NEORV32_SLINK.DATA[6]; return 0; } return 1; @@ -431,8 +431,8 @@ int neorv32_slink_rx6_nonblocking(uint32_t *rx_data) { **************************************************************************/ int neorv32_slink_rx7_nonblocking(uint32_t *rx_data) { - if (SLINK_STATUS & (1 << SLINK_STATUS_RX7_AVAIL)) { - *rx_data = SLINK_CH7; + if (NEORV32_SLINK.STATUS & (1 << SLINK_STATUS_RX7_AVAIL)) { + *rx_data = NEORV32_SLINK.DATA[7]; return 0; } return 1; diff --git a/sw/lib/source/neorv32_spi.c b/sw/lib/source/neorv32_spi.c index c13cd9930..12b25a30e 100644 --- a/sw/lib/source/neorv32_spi.c +++ b/sw/lib/source/neorv32_spi.c @@ -52,7 +52,7 @@ **************************************************************************/ int neorv32_spi_available(void) { - if (SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_IO_SPI)) { + if (NEORV32_SYSINFO.SOC & (1 << SYSINFO_SOC_IO_SPI)) { return 1; } else { @@ -62,7 +62,7 @@ int neorv32_spi_available(void) { /**********************************************************************//** - * Enable and configure SPI controller. The SPI control register bits are listed in #NEORV32_SPI_CT_enum. + * Enable and configure SPI controller. The SPI control register bits are listed in #NEORV32_SPI_CTRL_enum. * * @param[in] prsc Clock prescaler select (0..7). See #NEORV32_CLOCK_PRSC_enum. * @param[in] clk_polarity Idle clock polarity (0, 1). @@ -70,21 +70,21 @@ int neorv32_spi_available(void) { **************************************************************************/ void neorv32_spi_setup(uint8_t prsc, uint8_t clk_polarity, uint8_t data_size) { - SPI_CT = 0; // reset + NEORV32_SPI.CTRL = 0; // reset uint32_t ct_enable = 1; - ct_enable = ct_enable << SPI_CT_EN; + ct_enable = ct_enable << SPI_CTRL_EN; uint32_t ct_prsc = (uint32_t)(prsc & 0x07); - ct_prsc = ct_prsc << SPI_CT_PRSC0; + ct_prsc = ct_prsc << SPI_CTRL_PRSC0; uint32_t ct_polarity = (uint32_t)(clk_polarity & 0x01); - ct_polarity = ct_polarity << SPI_CT_CPHA; + ct_polarity = ct_polarity << SPI_CTRL_CPHA; uint32_t ct_size = (uint32_t)(data_size & 0x03); - ct_size = ct_size << SPI_CT_SIZE0; + ct_size = ct_size << SPI_CTRL_SIZE0; - SPI_CT = ct_enable | ct_prsc | ct_polarity | ct_size; + NEORV32_SPI.CTRL = ct_enable | ct_prsc | ct_polarity | ct_size; } @@ -93,7 +93,7 @@ void neorv32_spi_setup(uint8_t prsc, uint8_t clk_polarity, uint8_t data_size) { **************************************************************************/ void neorv32_spi_disable(void) { - SPI_CT &= ~((uint32_t)(1 << SPI_CT_EN)); + NEORV32_SPI.CTRL &= ~((uint32_t)(1 << SPI_CTRL_EN)); } @@ -102,7 +102,7 @@ void neorv32_spi_disable(void) { **************************************************************************/ void neorv32_spi_enable(void) { - SPI_CT |= ((uint32_t)(1 << SPI_CT_EN)); + NEORV32_SPI.CTRL |= ((uint32_t)(1 << SPI_CTRL_EN)); } @@ -116,8 +116,8 @@ void neorv32_spi_enable(void) { void neorv32_spi_cs_en(uint8_t cs) { uint32_t cs_mask = (uint32_t)(1 << (cs & 0x07)); - cs_mask = cs_mask << SPI_CT_CS0; - SPI_CT |= cs_mask; + cs_mask = cs_mask << SPI_CTRL_CS0; + NEORV32_SPI.CTRL |= cs_mask; } @@ -131,8 +131,8 @@ void neorv32_spi_cs_en(uint8_t cs) { void neorv32_spi_cs_dis(uint8_t cs) { uint32_t cs_mask = (uint32_t)(1 << (cs & 0x07)); - cs_mask = cs_mask << SPI_CT_CS0; - SPI_CT &= ~cs_mask; + cs_mask = cs_mask << SPI_CTRL_CS0; + NEORV32_SPI.CTRL &= ~cs_mask; } @@ -148,10 +148,10 @@ void neorv32_spi_cs_dis(uint8_t cs) { **************************************************************************/ uint32_t neorv32_spi_trans(uint32_t tx_data) { - SPI_DATA = tx_data; // trigger transfer - while((SPI_CT & (1<> TRNG_CT_DATA_LSB); + *data = (uint8_t)(ct_reg >> TRNG_CTRL_DATA_LSB); return 0; // valid data } diff --git a/sw/lib/source/neorv32_twi.c b/sw/lib/source/neorv32_twi.c index 2e4aee4f9..824e61b1a 100644 --- a/sw/lib/source/neorv32_twi.c +++ b/sw/lib/source/neorv32_twi.c @@ -52,7 +52,7 @@ **************************************************************************/ int neorv32_twi_available(void) { - if (SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_IO_TWI)) { + if (NEORV32_SYSINFO.SOC & (1 << SYSINFO_SOC_IO_TWI)) { return 1; } else { @@ -62,25 +62,25 @@ int neorv32_twi_available(void) { /**********************************************************************//** - * Enable and configure TWI controller. The TWI control register bits are listed in #NEORV32_TWI_CT_enum. + * Enable and configure TWI controller. The TWI control register bits are listed in #NEORV32_TWI_CTRL_enum. * * @param[in] prsc Clock prescaler select (0..7). See #NEORV32_CLOCK_PRSC_enum. * @param[in] ckst_en Enable clock-stretching by peripherals when 1. **************************************************************************/ void neorv32_twi_setup(uint8_t prsc, uint8_t ckst_en) { - TWI_CT = 0; // reset + NEORV32_TWI.CTRL = 0; // reset uint32_t ct_enable = 1; - ct_enable = ct_enable << TWI_CT_EN; + ct_enable = ct_enable << TWI_CTRL_EN; uint32_t ct_prsc = (uint32_t)(prsc & 0x07); - ct_prsc = ct_prsc << TWI_CT_PRSC0; + ct_prsc = ct_prsc << TWI_CTRL_PRSC0; uint32_t ct_cksten = (uint32_t)(ckst_en & 0x01); - ct_cksten = ct_cksten << TWI_CT_CKSTEN; + ct_cksten = ct_cksten << TWI_CTRL_CKSTEN; - TWI_CT = ct_enable | ct_prsc | ct_cksten; + NEORV32_TWI.CTRL = ct_enable | ct_prsc | ct_cksten; } @@ -89,7 +89,7 @@ void neorv32_twi_setup(uint8_t prsc, uint8_t ckst_en) { **************************************************************************/ void neorv32_twi_disable(void) { - TWI_CT &= ~((uint32_t)(1 << TWI_CT_EN)); + NEORV32_TWI.CTRL &= ~((uint32_t)(1 << TWI_CTRL_EN)); } @@ -98,7 +98,7 @@ void neorv32_twi_disable(void) { **************************************************************************/ void neorv32_twi_enable(void) { - TWI_CT |= (uint32_t)(1 << TWI_CT_EN); + NEORV32_TWI.CTRL |= (uint32_t)(1 << TWI_CTRL_EN); } @@ -107,7 +107,7 @@ void neorv32_twi_enable(void) { **************************************************************************/ void neorv32_twi_mack_enable(void) { - TWI_CT |= ((uint32_t)(1 << TWI_CT_MACK)); + NEORV32_TWI.CTRL |= ((uint32_t)(1 << TWI_CTRL_MACK)); } @@ -116,7 +116,7 @@ void neorv32_twi_mack_enable(void) { **************************************************************************/ void neorv32_twi_mack_disable(void) { - TWI_CT &= ~((uint32_t)(1 << TWI_CT_MACK)); + NEORV32_TWI.CTRL &= ~((uint32_t)(1 << TWI_CTRL_MACK)); } @@ -129,7 +129,7 @@ void neorv32_twi_mack_disable(void) { **************************************************************************/ int neorv32_twi_busy(void) { - if (TWI_CT & (1 << TWI_CT_BUSY)) { + if (NEORV32_TWI.CTRL & (1 << TWI_CTRL_BUSY)) { return 1; } return 0; @@ -148,11 +148,11 @@ int neorv32_twi_start_trans(uint8_t a) { neorv32_twi_generate_start(); // generate START condition - TWI_DATA = (uint32_t)a; // send address - while(TWI_CT & (1 << TWI_CT_BUSY)); // wait until idle again + NEORV32_TWI.DATA = (uint32_t)a; // send address + while(NEORV32_TWI.CTRL & (1 << TWI_CTRL_BUSY)); // wait until idle again // check for ACK/NACK - if (TWI_CT & (1 << TWI_CT_ACK)) + if (NEORV32_TWI.CTRL & (1 << TWI_CTRL_ACK)) return 0; // ACK received else return 1; // NACK received @@ -169,11 +169,11 @@ int neorv32_twi_start_trans(uint8_t a) { **************************************************************************/ int neorv32_twi_trans(uint8_t d) { - TWI_DATA = (uint32_t)d; // send data - while(TWI_CT & (1 << TWI_CT_BUSY)); // wait until idle again + NEORV32_TWI.DATA = (uint32_t)d; // send data + while(NEORV32_TWI.CTRL & (1 << TWI_CTRL_BUSY)); // wait until idle again // check for ACK/NACK - if (TWI_CT & (1 << TWI_CT_ACK)) + if (NEORV32_TWI.CTRL & (1 << TWI_CTRL_ACK)) return 0; // ACK received else return 1; // NACK received @@ -187,7 +187,7 @@ int neorv32_twi_trans(uint8_t d) { **************************************************************************/ uint8_t neorv32_twi_get_data(void) { - return (uint8_t)TWI_DATA; // get RX data from previous transmission + return (uint8_t)NEORV32_TWI.DATA; // get RX data from previous transmission } @@ -198,8 +198,8 @@ uint8_t neorv32_twi_get_data(void) { **************************************************************************/ void neorv32_twi_generate_stop(void) { - TWI_CT |= (uint32_t)(1 << TWI_CT_STOP); // generate STOP condition - while(TWI_CT & (1 << TWI_CT_BUSY)); // wait until idle again + NEORV32_TWI.CTRL |= (uint32_t)(1 << TWI_CTRL_STOP); // generate STOP condition + while(NEORV32_TWI.CTRL & (1 << TWI_CTRL_BUSY)); // wait until idle again } @@ -210,6 +210,6 @@ void neorv32_twi_generate_stop(void) { **************************************************************************/ void neorv32_twi_generate_start(void) { - TWI_CT |= (1 << TWI_CT_START); // generate START condition - while(TWI_CT & (1 << TWI_CT_BUSY)); // wait until idle again + NEORV32_TWI.CTRL |= (1 << TWI_CTRL_START); // generate START condition + while(NEORV32_TWI.CTRL & (1 << TWI_CTRL_BUSY)); // wait until idle again } diff --git a/sw/lib/source/neorv32_uart.c b/sw/lib/source/neorv32_uart.c index 190faedcb..a91c78bf0 100644 --- a/sw/lib/source/neorv32_uart.c +++ b/sw/lib/source/neorv32_uart.c @@ -226,7 +226,7 @@ int neorv32_uart_scan(char *buffer, int max_size, int echo) { return neorv32_uar **************************************************************************/ int neorv32_uart0_available(void) { - if (SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_IO_UART0)) { + if (NEORV32_SYSINFO.SOC & (1 << SYSINFO_SOC_IO_UART0)) { return 1; } else { @@ -249,9 +249,9 @@ int neorv32_uart0_available(void) { **************************************************************************/ void neorv32_uart0_setup(uint32_t baudrate, uint8_t parity, uint8_t flow_con) { - UART0_CT = 0; // reset + NEORV32_UART0.CTRL = 0; // reset - uint32_t clock = SYSINFO_CLK; + uint32_t clock = NEORV32_SYSINFO.CLK; uint16_t i = 0; // BAUD rate divisor uint8_t p = 0; // initial prsc = CLK/2 @@ -277,20 +277,20 @@ void neorv32_uart0_setup(uint32_t baudrate, uint8_t parity, uint8_t flow_con) { } uint32_t clk_prsc = (uint32_t)p; - clk_prsc = clk_prsc << UART_CT_PRSC0; + clk_prsc = clk_prsc << UART_CTRL_PRSC0; uint32_t baud_prsc = (uint32_t)i; baud_prsc = baud_prsc - 1; - baud_prsc = baud_prsc << UART_CT_BAUD00; + baud_prsc = baud_prsc << UART_CTRL_BAUD00; uint32_t uart_en = 1; - uart_en = uart_en << UART_CT_EN; + uart_en = uart_en << UART_CTRL_EN; uint32_t parity_config = (uint32_t)(parity & 3); - parity_config = parity_config << UART_CT_PMODE0; + parity_config = parity_config << UART_CTRL_PMODE0; uint32_t flow_control = (uint32_t)(flow_con & 3); - flow_control = flow_control << UART_CT_RTS_EN; + flow_control = flow_control << UART_CTRL_RTS_EN; /* Enable UART0 for SIM mode. */ /* USE THIS ONLY FOR SIMULATION! */ @@ -299,12 +299,12 @@ void neorv32_uart0_setup(uint32_t baudrate, uint8_t parity, uint8_t flow_con) { #endif #if defined UART0_SIM_MODE || defined UART_SIM_MODE #warning UART0_SIM_MODE (primary UART) enabled! Sending all UART0.TX data to text.io simulation output instead of real UART0 transmitter. Use this for simulations only! - uint32_t sim_mode = 1 << UART_CT_SIM_MODE; + uint32_t sim_mode = 1 << UART_CTRL_SIM_MODE; #else uint32_t sim_mode = 0; #endif - UART0_CT = clk_prsc | baud_prsc | uart_en | parity_config | sim_mode | flow_control; + NEORV32_UART0.CTRL = clk_prsc | baud_prsc | uart_en | parity_config | sim_mode | flow_control; } @@ -313,7 +313,7 @@ void neorv32_uart0_setup(uint32_t baudrate, uint8_t parity, uint8_t flow_con) { **************************************************************************/ void neorv32_uart0_disable(void) { - UART0_CT &= ~((uint32_t)(1 << UART_CT_EN)); + NEORV32_UART0.CTRL &= ~((uint32_t)(1 << UART_CTRL_EN)); } @@ -322,7 +322,7 @@ void neorv32_uart0_disable(void) { **************************************************************************/ void neorv32_uart0_enable(void) { - UART0_CT = ((uint32_t)(1 << UART_CT_EN)); + NEORV32_UART0.CTRL = ((uint32_t)(1 << UART_CTRL_EN)); } @@ -336,8 +336,8 @@ void neorv32_uart0_enable(void) { void neorv32_uart0_putc(char c) { // wait for previous transfer to finish - while ((UART0_CT & (1< Date: Fri, 17 Sep 2021 18:29:26 +0200 Subject: [PATCH 3/9] [sw/lib] added back-compatibility layer --- sw/lib/include/neorv32_legacy.h | 225 ++++++++++++++++++++++++++++++++ 1 file changed, 225 insertions(+) create mode 100644 sw/lib/include/neorv32_legacy.h diff --git a/sw/lib/include/neorv32_legacy.h b/sw/lib/include/neorv32_legacy.h new file mode 100644 index 000000000..168e8c834 --- /dev/null +++ b/sw/lib/include/neorv32_legacy.h @@ -0,0 +1,225 @@ +// ################################################################################################# +// # << NEORV32: neorv32_legacy.h - Legacy Compatibility Layer >> # +// # ********************************************************************************************* # +// # BSD 3-Clause License # +// # # +// # Copyright (c) 2021, Stephan Nolting. All rights reserved. # +// # # +// # Redistribution and use in source and binary forms, with or without modification, are # +// # permitted provided that the following conditions are met: # +// # # +// # 1. Redistributions of source code must retain the above copyright notice, this list of # +// # conditions and the following disclaimer. # +// # # +// # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +// # conditions and the following disclaimer in the documentation and/or other materials # +// # provided with the distribution. # +// # # +// # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +// # endorse or promote products derived from this software without specific prior written # +// # permission. # +// # # +// # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +// # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +// # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +// # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +// # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +// # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +// # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +// # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +// # OF THE POSSIBILITY OF SUCH DAMAGE. # +// # ********************************************************************************************* # +// # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +// ################################################################################################# + + +/**********************************************************************//** + * @file neorv32_legacy.h + * @author Stephan Nolting + * @brief Legacy compatibility layer. + * + * @warning Stuff from this file _should not_ be used for new designs as + * the compatibility layer _will not be updated_ for new/modifies hardware! + **************************************************************************/ + +#ifndef neorv32_legacy_h +#define neorv32_legacy_h + +/// @cond LEGACY_SYMBOLS + +/**********************************************************************//** + * @Custom Functions Subsystem (CFS) + **************************************************************************/ +#define CFS_REG_0 (NEORV32_CFS.REG[00]) +#define CFS_REG_1 (NEORV32_CFS.REG[01]) +#define CFS_REG_2 (NEORV32_CFS.REG[02]) +#define CFS_REG_3 (NEORV32_CFS.REG[03]) +#define CFS_REG_4 (NEORV32_CFS.REG[04]) +#define CFS_REG_5 (NEORV32_CFS.REG[05]) +#define CFS_REG_6 (NEORV32_CFS.REG[06]) +#define CFS_REG_7 (NEORV32_CFS.REG[07]) +#define CFS_REG_8 (NEORV32_CFS.REG[08]) +#define CFS_REG_9 (NEORV32_CFS.REG[09]) +#define CFS_REG_10 (NEORV32_CFS.REG[10]) +#define CFS_REG_11 (NEORV32_CFS.REG[11]) +#define CFS_REG_12 (NEORV32_CFS.REG[12]) +#define CFS_REG_13 (NEORV32_CFS.REG[13]) +#define CFS_REG_14 (NEORV32_CFS.REG[14]) +#define CFS_REG_15 (NEORV32_CFS.REG[15]) +#define CFS_REG_16 (NEORV32_CFS.REG[16]) +#define CFS_REG_17 (NEORV32_CFS.REG[17]) +#define CFS_REG_18 (NEORV32_CFS.REG[18]) +#define CFS_REG_19 (NEORV32_CFS.REG[19]) +#define CFS_REG_20 (NEORV32_CFS.REG[20]) +#define CFS_REG_21 (NEORV32_CFS.REG[21]) +#define CFS_REG_22 (NEORV32_CFS.REG[22]) +#define CFS_REG_23 (NEORV32_CFS.REG[23]) +#define CFS_REG_24 (NEORV32_CFS.REG[24]) +#define CFS_REG_25 (NEORV32_CFS.REG[25]) +#define CFS_REG_26 (NEORV32_CFS.REG[26]) +#define CFS_REG_27 (NEORV32_CFS.REG[27]) +#define CFS_REG_28 (NEORV32_CFS.REG[28]) +#define CFS_REG_29 (NEORV32_CFS.REG[29]) +#define CFS_REG_30 (NEORV32_CFS.REG[30]) +#define CFS_REG_31 (NEORV32_CFS.REG[31]) + +/**********************************************************************//** + * Pulse Width Modulation Controller (PWM) + **************************************************************************/ +#define PWM_CT (NEORV32_PWM.CTRL) +#define PWM_DUTY0 (NEORV32_PWM.DUTY[0]) +#define PWM_DUTY1 (NEORV32_PWM.DUTY[1]) +#define PWM_DUTY2 (NEORV32_PWM.DUTY[2]) +#define PWM_DUTY3 (NEORV32_PWM.DUTY[3]) +#define PWM_DUTY4 (NEORV32_PWM.DUTY[4]) +#define PWM_DUTY5 (NEORV32_PWM.DUTY[5]) +#define PWM_DUTY6 (NEORV32_PWM.DUTY[6]) +#define PWM_DUTY7 (NEORV32_PWM.DUTY[7]) +#define PWM_DUTY8 (NEORV32_PWM.DUTY[8]) +#define PWM_DUTY9 (NEORV32_PWM.DUTY[9]) +#define PWM_DUTY10 (NEORV32_PWM.DUTY[10]) +#define PWM_DUTY11 (NEORV32_PWM.DUTY[11]) +#define PWM_DUTY12 (NEORV32_PWM.DUTY[12]) +#define PWM_DUTY13 (NEORV32_PWM.DUTY[13]) +#define PWM_DUTY14 (NEORV32_PWM.DUTY[14]) + +/**********************************************************************//** + * Stream link interface (SLINK) + **************************************************************************/ +#define SLINK_CT (NEORV32_SLINK.CTRL) +#define SLINK_STATUS (NEORV32_SLINK.STATUS) +#define SLINK_CH0 (NEORV32_SLINK.DATA[0]) +#define SLINK_CH1 (NEORV32_SLINK.DATA[1]) +#define SLINK_CH2 (NEORV32_SLINK.DATA[2]) +#define SLINK_CH3 (NEORV32_SLINK.DATA[3]) +#define SLINK_CH4 (NEORV32_SLINK.DATA[4]) +#define SLINK_CH5 (NEORV32_SLINK.DATA[5]) +#define SLINK_CH6 (NEORV32_SLINK.DATA[6]) +#define SLINK_CH7 (NEORV32_SLINK.DATA[7]) + +/**********************************************************************//** + * External Interrupt Controller (XIRQ) + **************************************************************************/ +#define XIRQ_IER (NEORV32_XIRQ.IER) +#define XIRQ_IPR (NEORV32_XIRQ.IPR) +#define XIRQ_SCR (NEORV32_XIRQ.SCR) +/**@}*/ + +/**********************************************************************//** + * Machine System Timer (MTIME) + **************************************************************************/ +#define MTIME_LO (NEORV32_MTIME.TIME_LO) +#define MTIME_HI (NEORV32_MTIME.TIME_HI) +#define MTIMECMP_LO (NEORV32_MTIME.TIMECMP_LO) +#define MTIMECMP_HI (NEORV32_MTIME.TIMECMP_HI) +#define MTIME (*(IO_ROM64 (&NEORV32_MTIME.TIME_LO))) +#define MTIMECMP (*(IO_REG64 (&NEORV32_MTIME.TIMECMP_LO))) + +/**********************************************************************//** + * Primary/Secondary Universal Asynchronous Receiver and Transmitter (UART0 / UART1) + **************************************************************************/ +#define UART0_CT (NEORV32_UART0.CTRL) +#define UART0_DATA (NEORV32_UART0.DATA) +#define UART1_CT (NEORV32_UART1.CTRL) +#define UART1_DATA (NEORV32_UART1.DATA) + +/**********************************************************************//** + * Serial Peripheral Interface Controller (SPI) + **************************************************************************/ +#define SPI_CT (NEORV32_SPI.CTRL) +#define SPI_DATA (NEORV32_SPI.DATA) + +/**********************************************************************//** + * Two-Wire Interface Controller (TWI) + **************************************************************************/ +#define TWI_CT (NEORV32_TWI.CTRL) +#define TWI_DATA (NEORV32_TWI.DATA) + +/**********************************************************************//** + * True Random Number Generator (TRNG) + **************************************************************************/ +#define TRNG_CT (NEORV32_TRNG.CTRL) + +/**********************************************************************//** + * Watchdog Timer (WDT) + **************************************************************************/ +#define WDT_CT (NEORV32_WDT.CTRL) + +/**********************************************************************//** + * Device: General Purpose Input/Output Port Unit (GPIO) + **************************************************************************/ +#define GPIO_INPUT_LO (NEORV32_GPIO.INPUT_LO) +#define GPIO_INPUT_HI (NEORV32_GPIO.INPUT_HI) +#define GPIO_OUTPUT_LO (NEORV32_GPIO.OUTPUT_LO) +#define GPIO_OUTPUT_HI (NEORV32_GPIO.OUTPUT_HI) +#define GPIO_INPUT (*(IO_ROM64 (&NEORV32_GPIO.INPUT_LO))) +#define GPIO_OUTPUT (*(IO_REG64 (&NEORV32_GPIO.OUTPUT_LO))) + +/**********************************************************************//** + * Smart LED Hardware Interface (NEOLED) + **************************************************************************/ +#define NEOLED_CT (NEORV32_NEOLED.CTRL) +#define NEOLED_DATA (NEORV32_NEOLED.DATA) + +/**********************************************************************//** + * System Configuration Information Memory (SYSINFO) + **************************************************************************/ +#define SYSINFO_CLK (NEORV32_SYSINFO.CLK) +#define SYSINFO_CPU (NEORV32_SYSINFO.CPU) +#define SYSINFO_FEATURES (NEORV32_SYSINFO.SOC) +#define SYSINFO_CACHE (NEORV32_SYSINFO.CACHE) +#define SYSINFO_ISPACE_BASE (NEORV32_SYSINFO.ISPACE_BASE) +#define SYSINFO_DSPACE_BASE (NEORV32_SYSINFO.DSPACE_BASE) +#define SYSINFO_IMEM_SIZE (NEORV32_SYSINFO.IMEM_SIZE) +#define SYSINFO_DMEM_SIZE (NEORV32_SYSINFO.DMEM_SIZE) + +// SYSINFO_FEATURES bits (OBSOLETE!!! new version is #NEORV32_SOC_FEATURES_enum) +enum NEORV32_SYSINFO_FEATURES_enum { + SYSINFO_FEATURES_BOOTLOADER = 0, + SYSINFO_FEATURES_MEM_EXT = 1, + SYSINFO_FEATURES_MEM_INT_IMEM = 2, + SYSINFO_FEATURES_MEM_INT_DMEM = 3, + SYSINFO_FEATURES_MEM_EXT_ENDIAN = 4, + SYSINFO_FEATURES_ICACHE = 5, + + SYSINFO_FEATURES_OCD = 14, + SYSINFO_FEATURES_HW_RESET = 15, + + SYSINFO_FEATURES_IO_GPIO = 16, + SYSINFO_FEATURES_IO_MTIME = 17, + SYSINFO_FEATURES_IO_UART0 = 18, + SYSINFO_FEATURES_IO_SPI = 19, + SYSINFO_FEATURES_IO_TWI = 20, + SYSINFO_FEATURES_IO_PWM = 21, + SYSINFO_FEATURES_IO_WDT = 22, + SYSINFO_FEATURES_IO_CFS = 23, + SYSINFO_FEATURES_IO_TRNG = 24, + SYSINFO_FEATURES_IO_SLINK = 25, + SYSINFO_FEATURES_IO_UART1 = 26, + SYSINFO_FEATURES_IO_NEOLED = 27, + SYSINFO_FEATURES_IO_XIRQ = 28 +}; + +/// @endcond + +#endif // neorv32_legacy_h From 2cf4a59200885e3408307299822cf1e084f0b3a1 Mon Sep 17 00:00:00 2001 From: stnolting Date: Fri, 17 Sep 2021 18:29:57 +0200 Subject: [PATCH 4/9] [sw/example] converted example programs --- sw/example/bitmanip_test/main.c | 2 +- sw/example/coremark/core_portme.c | 4 +-- sw/example/demo_neopixel/main.c | 2 +- sw/example/demo_twi/main.c | 6 ++-- sw/example/dhrystone/dhry_1.c | 14 ++++---- sw/example/floating_point_test/main.c | 2 +- sw/example/processor_check/main.c | 52 +++++++++++++-------------- 7 files changed, 41 insertions(+), 41 deletions(-) diff --git a/sw/example/bitmanip_test/main.c b/sw/example/bitmanip_test/main.c index 4143997dd..5d030469f 100644 --- a/sw/example/bitmanip_test/main.c +++ b/sw/example/bitmanip_test/main.c @@ -97,7 +97,7 @@ int main() { neorv32_rte_check_isa(0); // silent = 0 -> show message if isa mismatch // check if Zbb extension is implemented at all - if ((SYSINFO_CPU & (1< extension not synthesized!\n"); return 1; } diff --git a/sw/example/coremark/core_portme.c b/sw/example/coremark/core_portme.c index 11d40cd26..80a58b9a3 100644 --- a/sw/example/coremark/core_portme.c +++ b/sw/example/coremark/core_portme.c @@ -125,7 +125,7 @@ secs_ret time_in_secs(CORE_TICKS ticks) { /* NEORV32-specific */ - secs_ret retval = (secs_ret)(((CORE_TICKS)ticks) / ((CORE_TICKS)SYSINFO_CLK)); + secs_ret retval = (secs_ret)(((CORE_TICKS)ticks) / ((CORE_TICKS)NEORV32_SYSINFO.CLK)); return retval; } @@ -183,7 +183,7 @@ portable_init(core_portable *p, int *argc, char *argv[]) neorv32_cpu_csr_write(CSR_MHPMCOUNTER13, 0); neorv32_cpu_csr_write(CSR_MHPMEVENT13, 1 << HPMCNT_EVENT_TRAP); neorv32_cpu_csr_write(CSR_MHPMCOUNTER14, 0); neorv32_cpu_csr_write(CSR_MHPMEVENT14, 1 << HPMCNT_EVENT_ILLEGAL); - neorv32_uart_printf("NEORV32: Processor running at %u Hz\n", (uint32_t)SYSINFO_CLK); + neorv32_uart_printf("NEORV32: Processor running at %u Hz\n", (uint32_t)NEORV32_SYSINFO.CLK); neorv32_uart_printf("NEORV32: Executing coremark (%u iterations). This may take some time...\n\n", (uint32_t)ITERATIONS); // clear cycle counter diff --git a/sw/example/demo_neopixel/main.c b/sw/example/demo_neopixel/main.c index db970c579..a9feda061 100644 --- a/sw/example/demo_neopixel/main.c +++ b/sw/example/demo_neopixel/main.c @@ -102,7 +102,7 @@ int main() { // check NEOLED configuration neorv32_uart0_printf("Checking NEOLED configuration:\n" " Hardware FIFO size: %u entries\n" - " Control register: 0x%x\n\n", neorv32_neoled_get_buffer_size(), NEOLED_CT); + " Control register: 0x%x\n\n", neorv32_neoled_get_buffer_size(), NEORV32_NEOLED.CTRL); // clear all LEDs diff --git a/sw/example/demo_twi/main.c b/sw/example/demo_twi/main.c index 707586793..cd7f70662 100644 --- a/sw/example/demo_twi/main.c +++ b/sw/example/demo_twi/main.c @@ -180,8 +180,8 @@ void set_speed(void) { uint8_t prsc = (uint8_t)hexstr_to_uint(terminal_buffer, strlen(terminal_buffer)); if ((prsc >= 0) && (prsc < 8)) { // valid? - TWI_CT = 0; // reset - TWI_CT = (1 << TWI_CT_EN) | (prsc << TWI_CT_PRSC0); + NEORV32_TWI.CTRL = 0; // reset + NEORV32_TWI.CTRL = (1 << TWI_CTRL_EN) | (prsc << TWI_CTRL_PRSC0); neorv32_uart_printf("\nDone.\n"); } else { @@ -202,7 +202,7 @@ void set_speed(void) { case 7: div = 4 * 4096; break; default: div = 0; break; } - uint32_t clock = SYSINFO_CLK / div; + uint32_t clock = NEORV32_SYSINFO.CLK / div; neorv32_uart_printf("New I2C clock: %u Hz\n", clock); } diff --git a/sw/example/dhrystone/dhry_1.c b/sw/example/dhrystone/dhry_1.c index 537e4bad0..01451f5a1 100644 --- a/sw/example/dhrystone/dhry_1.c +++ b/sw/example/dhrystone/dhry_1.c @@ -108,7 +108,7 @@ int main (void) // check available hardware extensions and compare with compiler flags neorv32_rte_check_isa(0); // silent = 0 -> show message if isa mismatch - neorv32_uart_printf("NEORV32: Processor running at %u Hz\n", (uint32_t)SYSINFO_CLK); + neorv32_uart_printf("NEORV32: Processor running at %u Hz\n", (uint32_t)NEORV32_SYSINFO.CLK); neorv32_uart_printf("NEORV32: Executing Dhrystone (%u iterations). This may take some time...\n\n", (uint32_t)DHRY_ITERS); // clear cycle counter @@ -343,26 +343,26 @@ int main (void) */ { /* ***** NEORV32-SPECIFIC ***** */ neorv32_uart_printf ("Microseconds for one run through Dhrystone: "); - neorv32_uart_printf ("%u \n", (uint32_t)(((User_Time/SYSINFO_CLK) * Mic_secs_Per_Second) / Number_Of_Runs)); + neorv32_uart_printf ("%u \n", (uint32_t)(((User_Time/NEORV32_SYSINFO.CLK) * Mic_secs_Per_Second) / Number_Of_Runs)); neorv32_uart_printf ("Dhrystones per Second: "); - neorv32_uart_printf ("%u \n", (uint32_t)(Number_Of_Runs / (User_Time/SYSINFO_CLK))); + neorv32_uart_printf ("%u \n", (uint32_t)(Number_Of_Runs / (User_Time/NEORV32_SYSINFO.CLK))); neorv32_uart_printf ("\n"); - uint32_t dhry_per_sec = (uint32_t)(Number_Of_Runs / (User_Time/SYSINFO_CLK)); + uint32_t dhry_per_sec = (uint32_t)(Number_Of_Runs / (User_Time/NEORV32_SYSINFO.CLK)); uint32_t vax_per_sec = dhry_per_sec / 1757; neorv32_uart_printf("NEORV32: << DETAILED RESULTS (integer parts only) >>\n"); neorv32_uart_printf("NEORV32: Total cycles: %u\n", (uint32_t)User_Time); -neorv32_uart_printf("NEORV32: Cycles per second: %u\n", (uint32_t)SYSINFO_CLK); +neorv32_uart_printf("NEORV32: Cycles per second: %u\n", (uint32_t)NEORV32_SYSINFO.CLK); neorv32_uart_printf("NEORV32: Total runs: %u\n", (uint32_t)Number_Of_Runs); neorv32_uart_printf("\n"); neorv32_uart_printf("NEORV32: DMIPS/s: %u\n", (uint32_t)dhry_per_sec); -neorv32_uart_printf("NEORV32: DMIPS/MHz: %u\n", (uint32_t)(dhry_per_sec / (SYSINFO_CLK / 1000000))); +neorv32_uart_printf("NEORV32: DMIPS/MHz: %u\n", (uint32_t)(dhry_per_sec / (NEORV32_SYSINFO.CLK / 1000000))); neorv32_uart_printf("\n"); neorv32_uart_printf("NEORV32: VAX DMIPS/s: %u\n", (uint32_t)vax_per_sec); -neorv32_uart_printf("NEORV32: VAX DMIPS/MHz: %u/%u\n", (uint32_t)vax_per_sec, (uint32_t)(SYSINFO_CLK / 1000000)); +neorv32_uart_printf("NEORV32: VAX DMIPS/MHz: %u/%u\n", (uint32_t)vax_per_sec, (uint32_t)(NEORV32_SYSINFO.CLK / 1000000)); } /* ***** /NEORV32-SPECIFIC ***** */ /* neorv32_uart_printf ("Microseconds for one run through Dhrystone: "); diff --git a/sw/example/floating_point_test/main.c b/sw/example/floating_point_test/main.c index 2608c1252..af7de3b0a 100644 --- a/sw/example/floating_point_test/main.c +++ b/sw/example/floating_point_test/main.c @@ -123,7 +123,7 @@ int main() { neorv32_rte_check_isa(0); // silent = 0 -> show message if isa mismatch // check if Zfinx extension is implemented at all - if ((SYSINFO_CPU & (1< extension not synthesized!\n"); return 1; } diff --git a/sw/example/processor_check/main.c b/sw/example/processor_check/main.c index 0866564ff..d9b2743f0 100644 --- a/sw/example/processor_check/main.c +++ b/sw/example/processor_check/main.c @@ -118,7 +118,7 @@ int main() { // init UARTs at default baud rate, no parity bits, no hw flow control neorv32_uart0_setup(BAUD_RATE, PARITY_NONE, FLOW_CONTROL_NONE); - UART1_CT = UART0_CT; // copy configuration to initialize UART1 + NEORV32_UART1.CTRL = NEORV32_UART0.CTRL; // copy configuration to initialize UART1 #ifdef SUPPRESS_OPTIONAL_UART_PRINT neorv32_uart0_disable(); // do not generate any UART0 output @@ -416,7 +416,7 @@ int main() { PRINT_STANDARD("[%i] MRET in U-mode: ", cnt_test); // skip if U-mode is not implemented - if (SYSINFO_CPU & (1< Date: Fri, 17 Sep 2021 18:30:10 +0200 Subject: [PATCH 5/9] [sw/bootloader] converted --- sw/bootloader/bootloader.c | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/sw/bootloader/bootloader.c b/sw/bootloader/bootloader.c index a827a9a2e..310e87c78 100644 --- a/sw/bootloader/bootloader.c +++ b/sw/bootloader/bootloader.c @@ -113,7 +113,7 @@ #define SPI_FLASH_SECTOR_SIZE 65536 // default = 64kB #endif -/** SPI flash clock pre-scaler; see #NEORV32_TWI_CT_enum */ +/** SPI flash clock pre-scaler; see #NEORV32_SPI_CTRL_enum */ #ifndef SPI_FLASH_CLK_PRSC #define SPI_FLASH_CLK_PRSC CLK_PRSC_8 #endif @@ -333,7 +333,7 @@ int main(void) { // Configure machine system timer interrupt for ~2Hz if (neorv32_mtime_available()) { - neorv32_mtime_set_timecmp(neorv32_mtime_get_time() + (SYSINFO_CLK/4)); + neorv32_mtime_set_timecmp(neorv32_mtime_get_time() + (NEORV32_SYSINFO.CLK/4)); // active timer IRQ neorv32_cpu_csr_write(CSR_MIE, 1 << CSR_MIE_MTIE); // activate MTIME IRQ source only! neorv32_cpu_eint(); // enable global interrupts @@ -347,21 +347,21 @@ int main(void) { "BLDV: "__DATE__"\nHWV: "); PRINT_XNUM(neorv32_cpu_csr_read(CSR_MIMPID)); PRINT_TEXT("\nCLK: "); - PRINT_XNUM(SYSINFO_CLK); + PRINT_XNUM(NEORV32_SYSINFO.CLK); PRINT_TEXT("\nMISA: "); PRINT_XNUM(neorv32_cpu_csr_read(CSR_MISA)); - PRINT_TEXT("\nZEXT: "); - PRINT_XNUM(SYSINFO_CPU); - PRINT_TEXT("\nPROC: "); - PRINT_XNUM(SYSINFO_FEATURES); + PRINT_TEXT("\nCPU : "); + PRINT_XNUM(NEORV32_SYSINFO.CPU); + PRINT_TEXT("\nSOC : "); + PRINT_XNUM(NEORV32_SYSINFO.SOC); PRINT_TEXT("\nIMEM: "); - PRINT_XNUM(SYSINFO_IMEM_SIZE); + PRINT_XNUM(NEORV32_SYSINFO.IMEM_SIZE); PRINT_TEXT(" bytes @"); - PRINT_XNUM(SYSINFO_ISPACE_BASE); + PRINT_XNUM(NEORV32_SYSINFO.ISPACE_BASE); PRINT_TEXT("\nDMEM: "); - PRINT_XNUM(SYSINFO_DMEM_SIZE); + PRINT_XNUM(NEORV32_SYSINFO.DMEM_SIZE); PRINT_TEXT(" bytes @"); - PRINT_XNUM(SYSINFO_DSPACE_BASE); + PRINT_XNUM(NEORV32_SYSINFO.DSPACE_BASE); // ------------------------------------------------ @@ -372,7 +372,7 @@ int main(void) { if (neorv32_mtime_available()) { PRINT_TEXT("\n\nAutoboot in "xstr(AUTO_BOOT_TIMEOUT)"s. Press key to abort.\n"); - uint64_t timeout_time = neorv32_mtime_get_time() + (uint64_t)(AUTO_BOOT_TIMEOUT * SYSINFO_CLK); + uint64_t timeout_time = neorv32_mtime_get_time() + (uint64_t)(AUTO_BOOT_TIMEOUT * NEORV32_SYSINFO.CLK); while(1){ @@ -477,7 +477,7 @@ void start_app(void) { while (neorv32_uart0_tx_busy()); // start app at instruction space base address - register uint32_t app_base = SYSINFO_ISPACE_BASE; + register uint32_t app_base = NEORV32_SYSINFO.ISPACE_BASE; asm volatile ("jalr zero, %0" : : "r" (app_base)); while (1); } @@ -503,7 +503,7 @@ void __attribute__((__interrupt__)) bootloader_trap_handler(void) { #endif // set time for next IRQ if (neorv32_mtime_available()) { - neorv32_mtime_set_timecmp(neorv32_mtime_get_time() + (SYSINFO_CLK/4)); + neorv32_mtime_set_timecmp(neorv32_mtime_get_time() + (NEORV32_SYSINFO.CLK/4)); } } @@ -570,7 +570,7 @@ void get_exe(int src) { uint32_t check = get_exe_word(src, addr + EXE_OFFSET_CHECKSUM); // complement sum checksum // transfer program data - uint32_t *pnt = (uint32_t*)SYSINFO_ISPACE_BASE; + uint32_t *pnt = (uint32_t*)NEORV32_SYSINFO.ISPACE_BASE; uint32_t checksum = 0; uint32_t d = 0, i = 0; addr = addr + EXE_OFFSET_DATA; @@ -646,7 +646,7 @@ void save_exe(void) { // store data from instruction memory and update checksum uint32_t checksum = 0; - uint32_t *pnt = (uint32_t*)SYSINFO_ISPACE_BASE; + uint32_t *pnt = (uint32_t*)NEORV32_SYSINFO.ISPACE_BASE; addr = addr + EXE_OFFSET_DATA; uint32_t i = 0; while (i < (size/4)) { // in words From ecafcd4d82ed13029a4ba3687332d95c881cd336 Mon Sep 17 00:00:00 2001 From: stnolting Date: Fri, 17 Sep 2021 18:42:10 +0200 Subject: [PATCH 6/9] [docs/datasheet] updated low-level registers --- docs/datasheet/cpu.adoc | 2 +- docs/datasheet/cpu_csr.adoc | 8 +-- docs/datasheet/soc.adoc | 29 ++++++-- docs/datasheet/soc_cfs.adoc | 18 ++--- docs/datasheet/soc_gpio.adoc | 10 +-- docs/datasheet/soc_mtime.adoc | 18 ++--- docs/datasheet/soc_neoled.adoc | 106 +++++++++++++-------------- docs/datasheet/soc_pwm.adoc | 42 +++++------ docs/datasheet/soc_slink.adoc | 72 +++++++++---------- docs/datasheet/soc_spi.adoc | 56 +++++++-------- docs/datasheet/soc_sysinfo.adoc | 60 ++++++++-------- docs/datasheet/soc_trng.adoc | 16 ++--- docs/datasheet/soc_twi.adoc | 42 +++++------ docs/datasheet/soc_uart.adoc | 118 +++++++++++++++---------------- docs/datasheet/soc_wdt.adoc | 36 +++++----- docs/datasheet/soc_wishbone.adoc | 3 +- docs/datasheet/soc_xirq.adoc | 26 +++---- docs/datasheet/software.adoc | 13 ++-- 18 files changed, 345 insertions(+), 330 deletions(-) diff --git a/docs/datasheet/cpu.adoc b/docs/datasheet/cpu.adoc index 49425a2fa..c3709a6b7 100644 --- a/docs/datasheet/cpu.adoc +++ b/docs/datasheet/cpu.adoc @@ -344,7 +344,7 @@ Volume II: Privileged Architecture_, which are available in the projects `docs/r [TIP] The CPU can discover available ISA extensions via the <<_misa>> CSR and the -_SYSINFO_CPU_ <<_system_configuration_information_memory_sysinfo, SYSINFO>> register +`CPU` <<_system_configuration_information_memory_sysinfo, SYSINFO>> register or by executing an instruction and checking for an _illegal instruction exception_. [NOTE] diff --git a/docs/datasheet/cpu_csr.adoc b/docs/datasheet/cpu_csr.adoc index 87199a76d..cd8995b4c 100644 --- a/docs/datasheet/cpu_csr.adoc +++ b/docs/datasheet/cpu_csr.adoc @@ -229,7 +229,7 @@ CSR is simply ignored and will NOT cause an illegal instruction exception. [TIP] Information regarding the implemented RISC-V `Z*` _sub-extensions_ (like `Zicsr` or `Zfinx`) can be found -in the _SYSINFO_CPU_ <<_system_configuration_information_memory_sysinfo, SYSINFO>> register. +in the `CPU` <<_system_configuration_information_memory_sysinfo, SYSINFO>> register. :sectnums!: @@ -508,16 +508,16 @@ configuration with <<_cpu_cnt_width>> less than 64 is not RISC-V compliant. [IMPORTANT] If _CPU_CNT_WIDTH_ is less than 64 (the default value) and greater than or equal 32, the according MSBs of `[m]cycleh` and `[m]instreth` are read-only and always read as zero. This configuration -will also set the _SYSINFO_CPU_ZXSCNT_ flag in the _SYSINFO_CPU_ <<_system_configuration_information_memory_sysinfo, SYSINFO>> register. + +will also set the _SYSINFO_CPU_ZXSCNT_ flag in the `CPU` <<_system_configuration_information_memory_sysinfo, SYSINFO>> register. + + If _CPU_CNT_WIDTH_ is less than 32 and greater than 0, the `[m]cycleh` and `[m]instreth` do not exist and any access will raise an illegal instruction exception. Furthermore, the according MSBs of `[m]cycle` and `[m]instret` are read-only and always read as zero. This configuration will also -set the _SYSINFO_CPU_ZXSCNT_ flag in the _SYSINFO_CPU_ <<_system_configuration_information_memory_sysinfo, SYSINFO>> register. + +set the _SYSINFO_CPU_ZXSCNT_ flag in the `CPU` <<_system_configuration_information_memory_sysinfo, SYSINFO>> register. + + If _CPU_CNT_WIDTH_ is 0, <<_cycleh>> and <<_instreth>> / <<_mcycleh>> and <<_minstreth>> do not exist and any access will raise an illegal instruction exception. This configuration will also set the -_SYSINFO_CPU_ZXNOCNT_ flag in the _SYSINFO_CPU_ <<_system_configuration_information_memory_sysinfo, SYSINFO>> register. +_SYSINFO_CPU_ZXNOCNT_ flag in the `CPU` <<_system_configuration_information_memory_sysinfo, SYSINFO>> register. :sectnums!: diff --git a/docs/datasheet/soc.adoc b/docs/datasheet/soc.adoc index 253380b76..94a1482f1 100644 --- a/docs/datasheet/soc.adoc +++ b/docs/datasheet/soc.adoc @@ -137,7 +137,7 @@ https://stnolting.github.io/neorv32/ug/#_application_specific_processor_configur [TIP] Privileged software can determine the actual CPU and processor configuration via the `misa` and the -i_SYSINFO_CPU_ <<_system_configuration_information_memory_sysinfo, SYSINFO>> register. +<<_system_configuration_information_memory_sysinfo, SYSINFO>> registers. [NOTE] If optional modules (like CPU extensions or peripheral devices) are *not enabled* the according circuitry @@ -432,7 +432,7 @@ See section <<_pmp_physical_memory_protection>> for more information. | **PMP_NUM_REGIONS** | _natural_ | 0 3+| Total number of implemented protections regions (0..64). If this generics is zero no physical memory protection logic will be implemented at all. Setting <<_pmp_num_regions>>_ > 0 will set the _SYSINFO_CPU_PMP_ flag -in the _SYSINFO_CPU_ <<_system_configuration_information_memory_sysinfo, SYSINFO>> register. +in the `CPU` <<_system_configuration_information_memory_sysinfo, SYSINFO>> register. |====== @@ -463,7 +463,7 @@ See section <<_hpm_hardware_performance_monitors>> for more information. | **HPM_NUM_CNTS** | _natural_ | 0 3+| Total number of implemented hardware performance monitor counters (0..29). If this generics is zero, no hardware performance monitor logic will be implemented at all. Setting <<_hpm_num_cnts>> > 0 will set the _SYSINFO_CPU_HPM_ flag -in the _SYSINFO_CPU_ <<_system_configuration_information_memory_sysinfo, SYSINFO>> register. +in the `CPU` <<_system_configuration_information_memory_sysinfo, SYSINFO>> register. |====== @@ -1312,6 +1312,11 @@ address _0xFFFFFE00_. A region of 512 bytes is reserved for this devices. Hence, accessed using a memory-mapped scheme. A special linker script as well as the NEORV32 core software library abstract the specific memory layout for the user. +[IMPORTANT] +The base address of each component/module has to be aligned to the +total size of the module's occupied address space! The occupied address space +has to be a power of two (minimum 4 bytes)! Address spaces must not overlap! + [IMPORTANT] When accessing an IO device that hast not been implemented (via the according _IO_x_EN_ generic), a load/store access fault exception is triggered. @@ -1335,11 +1340,21 @@ application start-up code `crt0.S`. **Nomenclature for the Peripheral / IO Devices Listing** Each peripheral device chapter features a register map showing accessible control and data registers of the -according device including the implemented control and status bits. You can directly interact with these -registers/bits via the provided _C-code defines_. These defines are set in the main processor core library -include file `sw/lib/include/neorv32.h`. The registers and/or register bits, which can be accessed -directly using plain C-code, are marked with a "[C]". +according device including the implemented control and status bits. C-language code can directly interact with these +registers via pre-defined `struct`. Each IO/peripheral module provides a unique `struct`. All accessible +interface registers of this module are defined as members of this `struct`. The pre-defined `struct` are defined int the +main processor core library include file `sw/lib/include/neorv32.h`. + +The naming scheme of these low-level hardware access structs is `NEORV32_.`. + +.Low-level hardware access example in C using the pre-defined `struct` +[source,c] +---- +// Read from SYSINFO "CLK" register +uint32_t temp = NEORV32_SYSINFO.CLK; +---- +The registers and/or register bits, which can be accessed directly using plain C-code, are marked with a "[C]". Not all registers or register bits can be arbitrarily read/written. The following read/write access types are available: diff --git a/docs/datasheet/soc_cfs.adoc b/docs/datasheet/soc_cfs.adoc index ea323fd54..123278698 100644 --- a/docs/datasheet/soc_cfs.adoc +++ b/docs/datasheet/soc_cfs.adoc @@ -24,7 +24,7 @@ The custom functions subsystem can be used to implement application-specific use custom hardware accelerators via the external memory interface, the CFS provide a convenient and low-latency extension and customization option. -The CFS provides up to 32x 32-bit memory-mapped registers (see register map table below). The actual +The CFS provides up to 32x 32-bit memory-mapped registers `REG` (see register map table below). The actual functionality of these register has to be defined by the hardware designer. [INFO] @@ -39,8 +39,8 @@ register map table below). Note that all interface registers provide 32-bit acce [source,c] ---- // C-code CFS usage example -CFS_REG_0 = (uint32_t)some_data_array(i); // write to CFS register 0 -uint32_t temp = CFS_REG_20; // read from CFS register 20 +NEORV32_CFS.REG[0] = (uint32_t)some_data_array(i); // write to CFS register 0 +uint32_t temp = NEORV32_CFS.REG[20]; // read from CFS register 20 ---- **CFS Interrupt** @@ -63,14 +63,14 @@ generic (default = 32-bit). The size of the output signal conduit `cfs_out_o` is _IO_CFS_OUT_SIZE_ configuration generic (default = 32-bit). If the custom function subsystem is not implemented (_IO_CFS_EN_ = false) the `cfs_out_o` signal is tied to all-zero. -.CFS register map +.CFS register map (`struct NEORV32_CFS`) [cols="^4,<5,^2,^3,<14"] [options="header",grid="all"] |======================= | Address | Name [C] | Bit(s) | R/W | Function -| `0xfffffe00` | _CFS_REG_0_ |`31:0` | (r)/(w) | custom CFS interface register 0 -| `0xfffffe04` | _CFS_REG_1_ |`31:0` | (r)/(w) | custom CFS interface register 1 -| ... | ... |`31:0` | (r)/(w) | ... -| `0xfffffe78` | _CFS_REG_30_ |`31:0` | (r)/(w) | custom CFS interface register 30 -| `0xfffffe7c` | _CFS_REG_31_ |`31:0` | (r)/(w) | custom CFS interface register 31 +| `0xfffffe00` | `NEORV32_CFS.REG[0]` |`31:0` | (r)/(w) | custom CFS interface register 0 +| `0xfffffe04` | `NEORV32_CFS.REG[1]` |`31:0` | (r)/(w) | custom CFS interface register 1 +| ... | ... |`31:0` | (r)/(w) | ... +| `0xfffffe78` | `NEORV32_CFS.REG[30]` |`31:0` | (r)/(w) | custom CFS interface register 30 +| `0xfffffe7c` | `NEORV32_CFS.REG[31]` |`31:0` | (r)/(w) | custom CFS interface register 31 |======================= diff --git a/docs/datasheet/soc_gpio.adoc b/docs/datasheet/soc_gpio.adoc index 8e4a7a574..6767b129e 100644 --- a/docs/datasheet/soc_gpio.adoc +++ b/docs/datasheet/soc_gpio.adoc @@ -27,13 +27,13 @@ The GPIO modules uses two memory-mapped registers (each 32-bit) each for accessi output signals. Since the CPU can only process 32-bit "at once" updating the entire output cannot be performed within a single clock cycle. -.GPIO unit register map +.GPIO unit register map (`struct NEORV32_GPIO`) [cols="<2,<2,^1,^1,<6"] [options="header",grid="rows"] |======================= | Address | Name [C] | Bit(s) | R/W | Function -| `0xffffffc0` | _GPIO_INPUT_LO_ | 31:0 | r/- | parallel input port pins 31:0 (write accesses are ignored) -| `0xffffffc4` | _GPIO_INPUT_HI_ | 31:0 | r/- | parallel input port pins 63:32 (write accesses are ignored) -| `0xffffffc8` | _GPIO_OUTPUT_LO_ | 31:0 | r/w | parallel output port pins 31:0 -| `0xffffffcc` | _GPIO_OUTPUT_HI_ | 31:0 | r/w | parallel output port pins 63:32 +| `0xffffffc0` | `NEORV32_GPIO.INPUT_LO` | 31:0 | r/- | parallel input port pins 31:0 (write accesses are ignored) +| `0xffffffc4` | `NEORV32_GPIO.INPUT_HI` | 31:0 | r/- | parallel input port pins 63:32 (write accesses are ignored) +| `0xffffffc8` | `NEORV32_GPIO.OUTPUT_LO` | 31:0 | r/w | parallel output port pins 31:0 +| `0xffffffcc` | `NEORV32_GPIO.OUTPUT_HI` | 31:0 | r/w | parallel output port pins 63:32 |======================= diff --git a/docs/datasheet/soc_mtime.adoc b/docs/datasheet/soc_mtime.adoc index 49a6e121f..af261fb10 100644 --- a/docs/datasheet/soc_mtime.adoc +++ b/docs/datasheet/soc_mtime.adoc @@ -25,26 +25,26 @@ use via the top's `mtime_o` signal. If the processor-internal **MTIME unit is NOT implemented**, the top's `mtime_i` input signal is used to update the `time[h]` CSRs and the `MTI` machine timer interrupt) CPU interrupt is directly connected to the top's `mtime_irq_i` input. -The 64-bit system time can be accessed via the `MTIME_LO` and `MTIME_HI` memory-mapped registers (read/write) and also via -the CPU's `time[h]` CSRs (read-only). A 64-bit time compare register – accessible via memory-mapped `MTIMECMP_LO` and `MTIMECMP_HI` +The 64-bit system time can be accessed via the `TIME_LO` and `TIME_HI` memory-mapped registers (read/write) and also via +the CPU's `time[h]` CSRs (read-only). A 64-bit time compare register – accessible via memory-mapped `TIMECMP_LO` and `TIMECMP_HI` registers – are used to configure an interrupt to the CPU. The interrupt is triggered -whenever `MTIME` (high & low part) >= `MTIMECMP` (high & low part) and is directly forwarded to the CPU's `MTI` interrupt. +whenever `TIME` (high & low part) >= `TIMECMP` (high & low part) and is directly forwarded to the CPU's `MTI` interrupt. [TIP] The interrupt request is a single-shot signal, so the CPU is triggered once if the system time is greater than or equal to the compare time. Hence, -another MTIME IRQ is only possible when updating `MTIMECMP`. +another MTIME IRQ is only possible when updating `TIMECMP`. The 64-bit counter and the 64-bit comparator are implemented as 2×32-bit counters and comparators with a registered carry to prevent a 64-bit carry chain and thus, to simplify timing closure. -.MTIME register map +.MTIME register map (`struct NEORV32_MTIME`) [cols="<3,<3,^1,^1,<6"] [options="header",grid="all"] |======================= | Address | Name [C] | Bits | R/W | Function -| `0xffffff90` | _MTIME_LO_ | 31:0 | r/w | machine system time, low word -| `0xffffff94` | _MTIME_HI_ | 31:0 | r/w | machine system time, high word -| `0xffffff98` | _MTIMECMP_LO_ | 31:0 | r/w | time compare, low word -| `0xffffff9c` | _MTIMECMP_HI_ | 31:0 | r/w | time compare, high word +| `0xffffff90` | `NEORV32_MTIME.TIME_LO` | 31:0 | r/w | machine system time, low word +| `0xffffff94` | `NEORV32_MTIME.TIME_HI` | 31:0 | r/w | machine system time, high word +| `0xffffff98` | `NEORV32_MTIME.TIMECMP_LO` | 31:0 | r/w | time compare, low word +| `0xffffff9c` | `NEORV32_MTIME.TIMECMP_HI` | 31:0 | r/w | time compare, high word |======================= diff --git a/docs/datasheet/soc_neoled.adoc b/docs/datasheet/soc_neoled.adoc index e8a6cb79f..a32f24e8f 100644 --- a/docs/datasheet/soc_neoled.adoc +++ b/docs/datasheet/soc_neoled.adoc @@ -32,11 +32,11 @@ and RGBW LEDs (32-bit color including a dedicated white LED chip) is possible. **Theory of Operation – NEOLED Module** -The NEOLED modules provides two accessible interface registers: the control register _NEOLED_CT_ and the -TX data register _NEOLED_DATA_. The NEOLED module is globally enabled via the control register's -_NEOLED_CT_EN_ bit. Clearing this bit will terminate any current operation, clear the TX buffer, reset the module +The NEOLED modules provides two accessible interface registers: the control register `CTRL` and the +TX data register `DATA`. The NEOLED module is globally enabled via the control register's +_NEOLED_CTRL_EN_ bit. Clearing this bit will terminate any current operation, clear the TX buffer, reset the module and set the `neoled_o` output to zero. The precise timing (implementing the **WS2812** protocol) and transmission -mode are fully programmable via the _NEOLED_CT_ register to provide maximum flexibility. +mode are fully programmable via the `CTRL` register to provide maximum flexibility. **RGB / RGBW Configuration** @@ -48,8 +48,8 @@ LEDs require a frame of 32-bit per module. The data transfer quantity of the NEOLED module can be configured via the _NEOLED_MODE_EN_ control register bit. If this bit is cleared, the NEOLED interface operates in 24-bit mode and will transmit bits `23:0` of -the data written to _NEOLED_DATA_ to the LEDs. If _NEOLED_MODE_EN_ is set, the NEOLED interface operates in 32-bit -mode and will transmit bits `31:0` of the data written to _NEOLED_DATA_ to the LEDs. +the data written to `DATA` to the LEDs. If _NEOLED_MODE_EN_ is set, the NEOLED interface operates in 32-bit +mode and will transmit bits `31:0` of the data written to `DATA` to the LEDs. The mode bit can be configured before writing each new data word in order to support an arbitrary setup of RGB and RGBW LEDs. @@ -80,19 +80,19 @@ image::neopixel.png[align=center] **Timing Configuration** -The basic carrier frequency (800kHz for the WS2812 LEDs) is configured via a 3-bit main clock prescaler (_NEOLED_CT_PRSCx_, see table below) -that scales the main processor clock f~main~ and a 5-bit cycle multiplier _NEOLED_CT_T_TOT_x_. +The basic carrier frequency (800kHz for the WS2812 LEDs) is configured via a 3-bit main clock prescaler (_NEOLED_CTRL_PRSCx_, see table below) +that scales the main processor clock f~main~ and a 5-bit cycle multiplier _NEOLED_CTRL_T_TOT_x_. .NEOLED prescaler configuration [cols="<4,^1,^1,^1,^1,^1,^1,^1,^1"] [options="header",grid="rows"] |======================= -| **`NEOLED_CT_PRSCx`** | `0b000` | `0b001` | `0b010` | `0b011` | `0b100` | `0b101` | `0b110` | `0b111` +| **`NEOLED_CTRL_PRSCx`** | `0b000` | `0b001` | `0b010` | `0b011` | `0b100` | `0b101` | `0b110` | `0b111` | Resulting `clock_prescaler` | 2 | 4 | 8 | 64 | 128 | 1024 | 2048 | 4096 |======================= The duty-cycles (or more precisely: the high- and low-times for sending either a '1' bit or a '0' bit) are -defined via the 5-bit _NEOLED_CT_T_ONE_H_x_ and _NEOLED_CT_T_ZERO_H_x_ values, respecively. These programmable +defined via the 5-bit _NEOLED_CTRL_T_ONE_H_x_ and _NEOLED_CTRL_T_ZERO_H_x_ values, respectively. These programmable timing constants allow to adapt the interface for a wide variety of smart LED protocol (for example WS2812 vs. WS2811). @@ -102,7 +102,7 @@ WS2811). Generate the base clock f~TX~ for the NEOLED TX engine: * processor clock f~main~ = 100 MHz -* _NEOLED_CT_PRSCx_ = `0b001` = f~main~ / 4 +* _NEOLED_CTRL_PRSCx_ = `0b001` = f~main~ / 4 _**f~TX~**_ = _f~main~[Hz]_ / `clock_prescaler` = 100MHz / 4 = 25MHz @@ -110,15 +110,15 @@ _**T~TX~**_ = 1 / _**f~TX~**_ = 40ns Generate carrier period (T~carrier~) and *high-times* (duty cycle) for sending `0` (T~0H~) and `1` (T~1H~) bits: -* _NEOLED_CT_T_TOT_ = `0b11110` (= decimal 30) -* _NEOLED_CT_T_ZERO_H_ = `0b01010` (= decimal 10) -* _NEOLED_CT_T_ONE_H_ = `0b10100` (= decimal 20) +* _NEOLED_CTRL_T_TOT_ = `0b11110` (= decimal 30) +* _NEOLED_CTRL_T_ZERO_H_ = `0b01010` (= decimal 10) +* _NEOLED_CTRL_T_ONE_H_ = `0b10100` (= decimal 20) -_**T~carrier~**_ = _**T~TX~**_ * _NEOLED_CT_T_TOT_ = 40ns * 30 = 1.4µs +_**T~carrier~**_ = _**T~TX~**_ * _NEOLED_CTRL_T_TOT_ = 40ns * 30 = 1.4µs -_**T~0H~**_ = _**T~TX~**_ * _NEOLED_CT_T_ZERO_H_ = 40ns * 10 = 0.4µs +_**T~0H~**_ = _**T~TX~**_ * _NEOLED_CTRL_T_ZERO_H_ = 40ns * 10 = 0.4µs -_**T~1H~**_ = _**T~TX~**_ * _NEOLED_CT_T_ONE_H_ = 40ns * 20 = 0.8µs +_**T~1H~**_ = _**T~TX~**_ * _NEOLED_CTRL_T_ONE_H_ = 40ns * 20 = 0.8µs [TIP] The NEOLED SW driver library (`neorv32_neoled.h`) provides a simplified configuration @@ -130,21 +130,21 @@ clock frequency. The interface features a TX data buffer (a FIFO) to allow more CPU-independent operation. The buffer depth is configured via the _IO_NEOLED_TX_FIFO_ top generic (default = 1 entry). -The FIFO size configuration can be read via the _NEOLED_CT_BUFS_x_ +The FIFO size configuration can be read via the _NEOLED_CTRL_BUFS_x_ control register bits, which result log2(_IO_NEOLED_TX_FIFO_). -When writing data to the _NEOLED_DATA_ register the data is automatically written to the TX buffer. Whenever +When writing data to the `DATA` register the data is automatically written to the TX buffer. Whenever data is available in the buffer the serial transmission engine will take it and transmit it to the LEDs. The data transfer size (_NEOLED_MODE_EN_) can be modified at every time since this control register bit is also buffered in the FIFO. This allows to arbitrarily mixing RGB and RGBW LEDs in the chain. -Software can check the FIFO fill level via the control register's _NEOLED_CT_TX_EMPTY_, _NEOLED_CT_TX_HALF_ -and _NEOLED_CT_TX_FULL_ flags. The _NEOLED_CT_TX_BUSY_ flags provides additional information if the the TX unit is +Software can check the FIFO fill level via the control register's _NEOLED_CTRL_TX_EMPTY_, _NEOLED_CTRL_TX_HALF_ +and _NEOLED_CTRL_TX_FULL_ flags. The _NEOLED_CTRL_TX_BUSY_ flags provides additional information if the the TX unit is still busy sending data. [WARNING] -Please note that the timing configurations (_NEOLED_CT_PRSCx_, _NEOLED_CT_T_TOT_x_, -_NEOLED_CT_T_ONE_H_x_ and _NEOLED_CT_T_ZERO_H_x_) are **NOT** stored to the buffer. Changing +Please note that the timing configurations (_NEOLED_CTRL_PRSCx_, _NEOLED_CTRL_T_TOT_x_, +_NEOLED_CTRL_T_ONE_H_x_ and _NEOLED_CTRL_T_ZERO_H_x_) are **NOT** stored to the buffer. Changing these value while the buffer is not empty or the TX engine is still busy will cause data corruption. @@ -155,11 +155,11 @@ registers when the data line is low for 50μs ("RESET" command, see table above) using busy-wait for at least 50μs. Obviously, this concept wastes a lot of processing power. To circumvent this, the NEOLED module provides an option to automatically issue an idle time for creating the RESET -command. If the _NEOLED_CT_STROBE_ control register bit is set, _all_ data written to the data FIFO (via _NEOLED_DATA_, +command. If the _NEOLED_CTRL_STROBE_ control register bit is set, _all_ data written to the data FIFO (via `DATA`, the actually written data is irrelevant) will trigger an idle phase (`neoled_o` = zero) of 127 periods (= _**T~carrier~**_). This idle time will cause the LEDs to strobe the color data into the PWM driver registers. -Since the _NEOLED_CT_STROBE_ flag is also buffered in the TX buffer, the RESET command is treated as just another +Since the _NEOLED_CTRL_STROBE_ flag is also buffered in the TX buffer, the RESET command is treated as just another data word being written to the TX buffer making busy wait concepts obsolete and allowing maximum refresh rates. @@ -167,42 +167,42 @@ data word being written to the TX buffer making busy wait concepts obsolete and The NEOLED modules features a single interrupt that is triggered whenever the TX FIFO's fill level falls below _half-full_ level. In this case software can write up to _IO_NEOLED_TX_FIFO_/2 new data -words to _NEOLED_DATA_ without checking the FIFO status flags. +words to `DATA` without checking the FIFO status flags. This highly relaxes time constraints for sending a continuous data stream to the LEDs (as an idle time beyond 50μs will trigger the LED's a RESET command). <<< -.NEOLED register map +.NEOLED register map (`struct NEORV32_NEOLED`) [cols="<4,<5,<9,^2,<9"] [options="header",grid="all"] |======================= | Address | Name [C] | Bit(s), Name [C] | R/W | Function -.25+<| `0xffffffd8` .25+<| _NEOLED_CT_ <|`0` _NEOLED_CT_EN_ ^| r/w <| NEOLED enable - <|`1` _NEOLED_CT_MODE_ ^| r/w <| data transfer size; `0`=24-bit; `1`=32-bit - <|`2` _NEOLED_CT_STROBE_ ^| r/w <| `0`=send normal color data; `1`=send RESET command on data write access - <|`3` _NEOLED_CT_PRSC0_ ^| r/w <| 3-bit clock prescaler, bit 0 - <|`4` _NEOLED_CT_PRSC1_ ^| r/w <| 3-bit clock prescaler, bit 1 - <|`5` _NEOLED_CT_PRSC2_ ^| r/w <| 3-bit clock prescaler, bit 2 - <|`6` _NEOLED_CT_BUFS0_ ^| r/- .4+<| 4-bit log2(_IO_NEOLED_TX_FIFO_) - <|`7` _NEOLED_CT_BUFS1_ ^| r/- - <|`8` _NEOLED_CT_BUFS2_ ^| r/- - <|`9` _NEOLED_CT_BUFS3_ ^| r/- - <|`10` _NEOLED_CT_T_TOT_0_ ^| r/w .5+<| 5-bit pulse clock ticks per total single-bit period (T~total~) - <|`11` _NEOLED_CT_T_TOT_1_ ^| r/w - <|`12` _NEOLED_CT_T_TOT_2_ ^| r/w - <|`13` _NEOLED_CT_T_TOT_3_ ^| r/w - <|`14` _NEOLED_CT_T_TOT_4_ ^| r/w - <|`20` _NEOLED_CT_ONE_H_0_ ^| r/w .5+<| 5-bit pulse clock ticks per high-time for sending a one-bit (T~H1~) - <|`21` _NEOLED_CT_ONE_H_1_ ^| r/w - <|`22` _NEOLED_CT_ONE_H_2_ ^| r/w - <|`23` _NEOLED_CT_ONE_H_3_ ^| r/w - <|`24` _NEOLED_CT_ONE_H_4_ ^| r/w - <|`30` _NEOLED_CT_TX_STATUS_ ^| r/- <| transmit engine busy when `1` - <|`31` _NEOLED_CT_TX_EMPTY_ ^| r/- <| TX FIFO is empty - <|`31` _NEOLED_CT_TX_HALF_ ^| r/- <| TX FIFO is _at least_ half full - <|`31` _NEOLED_CT_TX_FULL_ ^| r/- <| TX FIFO is full - <|`31` _NEOLED_CT_TX_BUSY_ ^| r/- <| TX serial engine is busy when set -| `0xffffffdc` | _NEOLED_DATA_ <|`31:0` / `23:0` ^| -/w <| TX data (32-/24-bit) +.25+<| `0xffffffd8` .25+<| `NEORV32_NEOLED.CTRL` <|`0` _NEOLED_CTRL_EN_ ^| r/w <| NEOLED enable + <|`1` _NEOLED_CTRL_MODE_ ^| r/w <| data transfer size; `0`=24-bit; `1`=32-bit + <|`2` _NEOLED_CTRL_STROBE_ ^| r/w <| `0`=send normal color data; `1`=send RESET command on data write access + <|`3` _NEOLED_CTRL_PRSC0_ ^| r/w <| 3-bit clock prescaler, bit 0 + <|`4` _NEOLED_CTRL_PRSC1_ ^| r/w <| 3-bit clock prescaler, bit 1 + <|`5` _NEOLED_CTRL_PRSC2_ ^| r/w <| 3-bit clock prescaler, bit 2 + <|`6` _NEOLED_CTRL_BUFS0_ ^| r/- .4+<| 4-bit log2(_IO_NEOLED_TX_FIFO_) + <|`7` _NEOLED_CTRL_BUFS1_ ^| r/- + <|`8` _NEOLED_CTRL_BUFS2_ ^| r/- + <|`9` _NEOLED_CTRL_BUFS3_ ^| r/- + <|`10` _NEOLED_CTRL_T_TOT_0_ ^| r/w .5+<| 5-bit pulse clock ticks per total single-bit period (T~total~) + <|`11` _NEOLED_CTRL_T_TOT_1_ ^| r/w + <|`12` _NEOLED_CTRL_T_TOT_2_ ^| r/w + <|`13` _NEOLED_CTRL_T_TOT_3_ ^| r/w + <|`14` _NEOLED_CTRL_T_TOT_4_ ^| r/w + <|`20` _NEOLED_CTRL_ONE_H_0_ ^| r/w .5+<| 5-bit pulse clock ticks per high-time for sending a one-bit (T~H1~) + <|`21` _NEOLED_CTRL_ONE_H_1_ ^| r/w + <|`22` _NEOLED_CTRL_ONE_H_2_ ^| r/w + <|`23` _NEOLED_CTRL_ONE_H_3_ ^| r/w + <|`24` _NEOLED_CTRL_ONE_H_4_ ^| r/w + <|`30` _NEOLED_CTRL_TX_STATUS_ ^| r/- <| transmit engine busy when `1` + <|`31` _NEOLED_CTRL_TX_EMPTY_ ^| r/- <| TX FIFO is empty + <|`31` _NEOLED_CTRL_TX_HALF_ ^| r/- <| TX FIFO is _at least_ half full + <|`31` _NEOLED_CTRL_TX_FULL_ ^| r/- <| TX FIFO is full + <|`31` _NEOLED_CTRL_TX_BUSY_ ^| r/- <| TX serial engine is busy when set +| `0xffffffdc` | `NEORV32_NEOLED.DATA` <|`31:0` / `23:0` ^| -/w <| TX data (32-/24-bit) |======================= diff --git a/docs/datasheet/soc_pwm.adoc b/docs/datasheet/soc_pwm.adoc index 06a8b0db5..824242d95 100644 --- a/docs/datasheet/soc_pwm.adoc +++ b/docs/datasheet/soc_pwm.adoc @@ -24,13 +24,13 @@ can be used to smooth the generated "analog" signals. **Theory of Operation** -The PWM controller is activated by setting the _PWM_CT_EN_ bit in the module's control register _PWM_CT_. When this +The PWM controller is activated by setting the _PWM_CTRL_EN_ bit in the module's control register `CTRL`. When this bit is cleared, the unit is reset and all PWM output channels are set to zero. The 8-bit duty cycle for each channel, which represents the channel's "intensity", is defined via an 8-bit value. The module -provides up to 15 duty cycle registers _PWM_DUTY0_ to _PWM_DUTY14_ (depending on the number of implemented channels). +provides up to 15 duty cycle registers `DUTY[0]` to `DUTY[14]` (depending on the number of implemented channels). Each register contains the duty cycle configuration for 4 consecutive channels. For example, the duty cycle of channel 0 -is defined via bits 7:0 in _PWM_DUTY0_. The duty cycle of channel 2 is defined via bits 15:0 in _PWM_DUTY0_. -Channel 4's duty cycle is defined via bits 7:0 in _PWM_DUTY1_ and so on. +is defined via bits 7:0 in `DUTY[0]`. The duty cycle of channel 2 is defined via bits 15:0 in `DUTY[0]`. +Channel 4's duty cycle is defined via bits 7:0 in `DUTY[1]` and so on. [NOTE] Regardless of the configuration of _IO_PWM_NUM_CH_ all module registers can be accessed without raising an exception. @@ -39,17 +39,17 @@ reading those values back. The duty-cycle of channels that were not implemented Based on the configured duty cycle the according intensity of the channel can be computed by the following formula: -_**Intensity~x~**_ = _PWM_DUTY_CHx_ / (2^8^) +_**Intensity~x~**_ = `DUTY[y](i*8+7 downto i*8)` / (2^8^) The base frequency of the generated PWM signals is defined by the PWM core clock. This clock is derived -from the main processor clock and divided by a prescaler via the 3-bit PWM_CT_PRSCx in the unit's control +from the main processor clock and divided by a prescaler via the 3-bit PWM_CTRL_PRSCx in the unit's control register. The following prescalers are available: .PWM prescaler configuration [cols="<4,^1,^1,^1,^1,^1,^1,^1,^1"] [options="header",grid="rows"] |======================= -| **`PWM_CT_PRSCx`** | `0b000` | `0b001` | `0b010` | `0b011` | `0b100` | `0b101` | `0b110` | `0b111` +| **`PWM_CTRL_PRSCx`** | `0b000` | `0b001` | `0b010` | `0b011` | `0b100` | `0b101` | `0b110` | `0b111` | Resulting `clock_prescaler` | 2 | 4 | 8 | 64 | 128 | 1024 | 2048 | 4096 |======================= @@ -58,22 +58,22 @@ The resulting PWM base frequency is defined by: _**f~PWM~**_ = _f~main~[Hz]_ / (2^8^ * `clock_prescaler`) <<< -.PWM register map +.PWM register map (`struct neorv32_pwm_t`) [cols="<4,<4,<6,^2,<8"] [options="header",grid="all"] |======================= | Address | Name [C] | Bit(s), Name [C] | R/W | Function -.4+<| `0xfffffe80` .4+<| _PWM_CT_ <|`0` _PWM_CT_EN_ ^| r/w | PWM enable - <|`1` _PWM_CT_PRSC0_ ^| r/w .3+<| 3-bit clock prescaler select - <|`2` _PWM_CT_PRSC1_ ^| r/w - <|`3` _PWM_CT_PRSC2_ ^| r/w -.4+<| `0xfffffe84` .4+<| _PWM_DUTY0_ <|`7:0` ^| r/w <| 8-bit duty cycle for channel 0 - <|`15:8` ^| r/w <| 8-bit duty cycle for channel 1 - <|`23:16` ^| r/w <| 8-bit duty cycle for channel 2 - <|`31:24` ^| r/w <| 8-bit duty cycle for channel 3 -| ... | ... | ... | r/w | ... -.4+<| `0xfffffebc` .4+<| _PWM_DUTY14_ <|`7:0` ^| r/w <| 8-bit duty cycle for channel 56 - <|`15:8` ^| r/w <| 8-bit duty cycle for channel 57 - <|`23:16` ^| r/w <| 8-bit duty cycle for channel 58 - <|`31:24` ^| r/w <| 8-bit duty cycle for channel 59 +.4+<| `0xfffffe80` .4+<| `NEORV32_PWM.CTRL` <|`0` _PWM_CTRL_EN_ ^| r/w | PWM enable + <|`1` _PWM_CTRL_PRSC0_ ^| r/w .3+<| 3-bit clock prescaler select + <|`2` _PWM_CTRL_PRSC1_ ^| r/w + <|`3` _PWM_CTRL_PRSC2_ ^| r/w +.4+<| `0xfffffe84` .4+<| `NEORV32_PWM.DUTY[0]` <|`7:0` ^| r/w <| 8-bit duty cycle for channel 0 + <|`15:8` ^| r/w <| 8-bit duty cycle for channel 1 + <|`23:16` ^| r/w <| 8-bit duty cycle for channel 2 + <|`31:24` ^| r/w <| 8-bit duty cycle for channel 3 +| ... | ... | ... | r/w | ... +.4+<| `0xfffffebc` .4+<| `NEORV32_PWM.DUTY[14]` <|`7:0` ^| r/w <| 8-bit duty cycle for channel 56 + <|`15:8` ^| r/w <| 8-bit duty cycle for channel 57 + <|`23:16` ^| r/w <| 8-bit duty cycle for channel 58 + <|`31:24` ^| r/w <| 8-bit duty cycle for channel 59 |======================= diff --git a/docs/datasheet/soc_slink.adoc b/docs/datasheet/soc_slink.adoc index 708d1ba39..697989c7f 100644 --- a/docs/datasheet/soc_slink.adoc +++ b/docs/datasheet/soc_slink.adoc @@ -46,20 +46,20 @@ tag signals. **Theory of Operation** -The SLINK provides eight data registers (_SLINK_CHx_) to access the links (read accesses will access the RX links, write -accesses will access the TX links), one control register (_SLINK_CT_) and one status register (_SLINK_STATUS_). +The SLINK provides eight data registers (`DATA[i]`) to access the links (read accesses will access the RX links, write +accesses will access the TX links), one control register (`CTRL`) and one status register (`STATUS`). -The SLINK is globally activated by setting the control register's enable bit _SLINK_CT_EN_. -The actual data links are accessed by reading or writing the according link data registers _SLINK_CH0_ -to _SLINK_CH7_. For example, writing the _SLINK_CH0_ will put the according data into the FIFO of TX link 0. -Accordingly, reading from _SLINK_CH0_ will return one data word from the FIFO of RX link 0. +The SLINK is globally activated by setting the control register's enable bit _SLINK_CTRL_EN_. +The actual data links are accessed by reading or writing the according link data registers `DATA[0]` +to `DATA[7]`. For example, writing the `DATA[0]` will put the according data into the FIFO of TX link 0. +Accordingly, reading from `DATA[0]` will return one data word from the FIFO of RX link 0. The configuration (done via the SLINK generics) can be checked by software by evaluating bit fields in the -control register. The _SLINK_CT_TX_FIFO_Sx_ and _SLINK_CT_RX_FIFO_Sx_ indicate the TX & RX FIFO sizes. -The _SLINK_CT_TX_NUMx_ and _SLINK_CT_RX_NUMx_ bits represent the absolute number of implemented TX and RX links. +control register. The _SLINK_CTRL_TX_FIFO_Sx_ and _SLINK_CTRL_RX_FIFO_Sx_ indicate the TX & RX FIFO sizes. +The _SLINK_CTRL_TX_NUMx_ and _SLINK_CTRL_RX_NUMx_ bits represent the absolute number of implemented TX and RX links. -The status register shows the FIFO status flags of each RX and TX link. The _SLINK_CT_RXx_AVAIL_ flags indicate -that there is _at least_ one data word in the according RX link's FIFO. The _SLINK_CT_TXx_FREE_ flags indicate +The status register shows the FIFO status flags of each RX and TX link. The _SLINK_CTRL_RXx_AVAIL_ flags indicate +that there is _at least_ one data word in the according RX link's FIFO. The _SLINK_CTRL_TXx_FREE_ flags indicate there is _at least_ one free entry in the according TX link's FIFO. The _SLINK_STATUS_RXx_HALF_ and _SLINK_STATUS_RXx_HALF_ flags show if a certain FIFO's fill level has exceeded half of its capacity. @@ -68,10 +68,10 @@ _SLINK_STATUS_RXx_HALF_ flags show if a certain FIFO's fill level has exceeded h When directly accessing the link data registers (without checking the according FIFO status flags) the access is as _blocking_. That means the CPU access will stall until the accessed link responds. For -example, when reading RX link 0 (via _SLINK_CH0_ register) the CPU will stall, if there is not data +example, when reading RX link 0 (via `DATA[0]` register) the CPU will stall, if there is not data available in the according FIFO yet. The CPU access will complete as soon as RX link 0 receives new data. -Vice versa, writing data to TX link 0 (via _SLINK_CH0_ register) will stall the CPU access until there is +Vice versa, writing data to TX link 0 (via `DATA[0]` register) will stall the CPU access until there is at least one free entry in the link's FIFO. [WARNING] @@ -84,10 +84,10 @@ from an _empty_ RX link. Hence, this concept should only be used when evaluating **Non-Blocking Link Access** -For a non-blocking link access concept, the FIFO status flags in _SLINK_STATUS_ need to be checked _before_ +For a non-blocking link access concept, the FIFO status flags in `STATUS` need to be checked _before_ reading/writing the actual link data register. For example, a non-blocking write access to a TX link 0 has to check _SLINK_STATUS_TX0_FREE_ first. If the bit is set, the FIFO of TX link 0 can take another data word -and the actual data can be written to _SLINK_CH0_. If the bit is cleared, the link's FIFO is full +and the actual data can be written to `DATA[0]`. If the bit is cleared, the link's FIFO is full and the status flag can be polled until it there is free space in the available. This concept will not raise any exception as there is no "direct" access to the link data registers. @@ -111,7 +111,7 @@ interrupt. No further interrupt can fire until the CPU acknowledges the last int However, further IRQ conditions are buffered and will trigger another interrupt after the current one has been acknowledged. Note that these interrupts can only fire if the SLINK module is actually enabled by setting the -_SLINK_CT_EN_ bit in the unit's control register. +_SLINK_CTRL_EN_ bit in the unit's control register. **Stream Link Interface & Protocol** @@ -133,29 +133,29 @@ image::stream_link_interface.png[width=560,align=center] [TIP] The SLINK handshake protocol is compatible with the https://developer.arm.com/documentation/ihi0051/a/Introduction/About-the-AXI4-Stream-protocol[AXI4-Stream] base protocol. -.SLINK register map +.SLINK register map (`struct NEORV32_SLINK`) [cols="^4,<5,^2,^2,<14"] [options="header",grid="all"] |======================= | Address | Name [C] | Bit(s) | R/W | Function -.6+<| `0xfffffec0` .6+<| _SLINK_CT_ <| `31` _SLINK_CT_EN_ ^| r/w | SLINK global enable - <| `30:16` _reserved_ ^| r/- <| reserved, read as zero - <| `15:12` _SLINK_CT_TX_FIFO_S3_ : _SLINK_CT_TX_FIFO_S0_ ^| r/- <| TX links FIFO depth, log2 of_SLINK_TX_FIFO_ generic - <| `11:8` _SLINK_CT_RX_FIFO_S3_ : _SLINK_CT_RX_FIFO_S0_ ^| r/- <| RX links FIFO depth, log2 of_SLINK_RX_FIFO_ generic - <| `7:4` _SLINK_CT_TX_NUM3_ : _SLINK_CT_TX_NUM0_ ^| r/- <| Number of implemented TX links - <| `3:0` _SLINK_CT_RX_NUM3_ : _SLINK_CT_RX_NUM0_ ^| r/- <| Number of implemented RX links -| `0xfffffec4` : `0xfffffeec` | _SLINK_CT_ |`31:0` | | _mirrored control register_ -.4+<| `0xfffffed0` .4+<| _SLINK_STATUS_ <| `31:24` _SLINK_STATUS_TX7_HALF_ : _SLINK_STATUS_TX0_HALF_ ^| r/- | TX link 7..0 FIFO fill level is > half-full - <| `23:16` _SLINK_STATUS_RX7_HALF_ : _SLINK_STATUS_RX0_HALF_ ^| r/- <| RX link 7..0 FIFO fill level is >= half-full - <| `15:8` _SLINK_CT_TX7_FREE_ : _SLINK_CT_TX0_FREE_ ^| r/- <| At least one free TX FIFO entry available for link 7..0 - <| `7:0` _SLINK_CT_RX7_AVAIL_ : _SLINK_CT_RX0_AVAIL_ ^| r/- <| At least one data word in RX FIFO available for link 7..0 -| `0xfffffed4` : `0xfffffedc` | _SLINK_STATUS_ |`31:0` | | _mirrored status register_ -| `0xfffffee0` | _SLINK_CH0_ | `31:0` | r/w | Link 0 RX/TX data -| `0xfffffee4` | _SLINK_CH1_ | `31:0` | r/w | Link 1 RX/TX data -| `0xfffffee8` | _SLINK_CH2_ | `31:0` | r/w | Link 2 RX/TX data -| `0xfffffeec` | _SLINK_CH3_ | `31:0` | r/w | Link 3 RX/TX data -| `0xfffffef0` | _SLINK_CH4_ | `31:0` | r/w | Link 4 RX/TX data -| `0xfffffef4` | _SLINK_CH5_ | `31:0` | r/w | Link 5 RX/TX data -| `0xfffffef8` | _SLINK_CH6_ | `31:0` | r/w | Link 6 RX/TX data -| `0xfffffefc` | _SLINK_CH7_ | `31:0` | r/w | Link 7 RX/TX data +.6+<| `0xfffffec0` .6+<| `NEORV32_SLINK.CTRL` <| `31` _SLINK_CTRL_EN_ ^| r/w | SLINK global enable + <| `30:16` _reserved_ ^| r/- <| reserved, read as zero + <| `15:12` _SLINK_CTRL_TX_FIFO_S3_ : _SLINK_CTRL_TX_FIFO_S0_ ^| r/- <| TX links FIFO depth, log2 of_SLINK_TX_FIFO_ generic + <| `11:8` _SLINK_CTRL_RX_FIFO_S3_ : _SLINK_CTRL_RX_FIFO_S0_ ^| r/- <| RX links FIFO depth, log2 of_SLINK_RX_FIFO_ generic + <| `7:4` _SLINK_CTRL_TX_NUM3_ : _SLINK_CTRL_TX_NUM0_ ^| r/- <| Number of implemented TX links + <| `3:0` _SLINK_CTRL_RX_NUM3_ : _SLINK_CTRL_RX_NUM0_ ^| r/- <| Number of implemented RX links +| `0xfffffec4` : `0xfffffeec` | - |`31:0` | | _reserved +.4+<| `0xfffffed0` .4+<| `NEORV32_SLINK.STATUS` <| `31:24` _SLINK_STATUS_TX7_HALF_ : _SLINK_STATUS_TX0_HALF_ ^| r/- | TX link 7..0 FIFO fill level is > half-full + <| `23:16` _SLINK_STATUS_RX7_HALF_ : _SLINK_STATUS_RX0_HALF_ ^| r/- <| RX link 7..0 FIFO fill level is >= half-full + <| `15:8` _SLINK_STATUS_TX7_FREE_ : _SLINK_STATUS_TX0_FREE_ ^| r/- <| At least one free TX FIFO entry available for link 7..0 + <| `7:0` _SLINK_STATUS_RX7_AVAIL_ : _SLINK_STATUS_RX0_AVAIL_ ^| r/- <| At least one data word in RX FIFO available for link 7..0 +| `0xfffffed4` : `0xfffffedc` | - |`31:0` | | _reserved_ +| `0xfffffee0` | `NEORV32_SLINK.DATA[0]` | `31:0` | r/w | Link 0 RX/TX data +| `0xfffffee4` | `NEORV32_SLINK.DATA[1]` | `31:0` | r/w | Link 1 RX/TX data +| `0xfffffee8` | `NEORV32_SLINK.DATA[2]` | `31:0` | r/w | Link 2 RX/TX data +| `0xfffffeec` | `NEORV32_SLINK.DATA[3]` | `31:0` | r/w | Link 3 RX/TX data +| `0xfffffef0` | `NEORV32_SLINK.DATA[4]` | `31:0` | r/w | Link 4 RX/TX data +| `0xfffffef4` | `NEORV32_SLINK.DATA[5]` | `31:0` | r/w | Link 5 RX/TX data +| `0xfffffef8` | `NEORV32_SLINK.DATA[6]` | `31:0` | r/w | Link 6 RX/TX data +| `0xfffffefc` | `NEORV32_SLINK.DATA[7]` | `31:0` | r/w | Link 7 RX/TX data |======================= diff --git a/docs/datasheet/soc_spi.adoc b/docs/datasheet/soc_spi.adoc index 8427bb432..118dff19e 100644 --- a/docs/datasheet/soc_spi.adoc +++ b/docs/datasheet/soc_spi.adoc @@ -22,54 +22,54 @@ SPI is a synchronous serial transmission interface. The NEORV32 SPI transceiver bit long transmissions. The unit provides 8 dedicated chip select signals via the top entity's `spi_csn_o` signal. -The SPI unit is enabled via the _SPI_CT_EN_ bit in the _SPI_CT_ control register. The idle clock polarity is configured via the _SPI_CT_CPHA_ +The SPI unit is enabled via the _SPI_CTRL_EN_ bit in the `CTRL` control register. The idle clock polarity is configured via the _SPI_CTRL_CPHA_ bit and can be low (`0`) or high (`1`) during idle. The data quantity to be transferred within a -single transmission is defined via the _SPI_CT_SIZEx bits_. The unit supports 8-bit (`00`), 16-bit (`01`), 24- +single transmission is defined via the _SPI_CTRL_SIZEx bits_. The unit supports 8-bit (`00`), 16-bit (`01`), 24- bit (`10`) and 32-bit (`11`) transfers. Whenever a transfer is completed, the "transmission done interrupt" is triggered. -A transmission is still in progress as long as the _SPI_CT_BUSY_ flag is set. +A transmission is still in progress as long as the _SPI_CTRL_BUSY_ flag is set. -The SPI controller features 8 dedicated chip-select lines. These lines are controlled via the control register's _SPI_CT_CSx_ bits. When -a specifc _SPI_CT_CSx_ bit is **set**, the according chip select line `spi_csn_o(x)` goes **low** (low-active chip select lines). +The SPI controller features 8 dedicated chip-select lines. These lines are controlled via the control register's _SPI_CTRL_CSx_ bits. When +a specifc _SPI_CTRL_CSx_ bit is **set**, the according chip select line `spi_csn_o(x)` goes **low** (low-active chip select lines). -The SPI clock frequency is defined via the 3-bit _SPI_CT_PRSCx_ clock prescaler. The following prescalers +The SPI clock frequency is defined via the 3-bit _SPI_CTRL_PRSCx_ clock prescaler. The following prescalers are available: .SPI prescaler configuration [cols="<4,^1,^1,^1,^1,^1,^1,^1,^1"] [options="header",grid="rows"] |======================= -| **`SPI_CT_PRSCx`** | `0b000` | `0b001` | `0b010` | `0b011` | `0b100` | `0b101` | `0b110` | `0b111` +| **`SPI_CTRL_PRSCx`** | `0b000` | `0b001` | `0b010` | `0b011` | `0b100` | `0b101` | `0b110` | `0b111` | Resulting `clock_prescaler` | 2 | 4 | 8 | 64 | 128 | 1024 | 2048 | 4096 |======================= -Based on the _SPI_CT_PRSCx_ configuration, the actual SPI clock frequency f~SPI~ is derived from the processor's main clock f~main~ and is determined by: +Based on the _SPI_CTRL_PRSCx_ configuration, the actual SPI clock frequency f~SPI~ is derived from the processor's main clock f~main~ and is determined by: _**f~SPI~**_ = _f~main~[Hz]_ / (2 * `clock_prescaler`) -A transmission is started when writing data to the _SPI_DATA_ register. The data must be LSB-aligned. So if +A transmission is started when writing data to the `DATA` register. The data must be LSB-aligned. So if the SPI transceiver is configured for less than 32-bit transfers data quantity, the transmit data must be placed -into the lowest 8/16/24 bit of _SPI_DATA_. Vice versa, the received data is also always LSB-aligned. +into the lowest 8/16/24 bit of `DATA`. Vice versa, the received data is also always LSB-aligned. -.SPI register map +.SPI register map (`struct NEORV32_SPI`) [cols="<2,<2,<4,^1,<7"] [options="header",grid="all"] |======================= | Address | Name [C] | Bit(s), Name [C] | R/W | Function -.16+<| `0xffffffa8` .16+<| _SPI_CT_ <|`0` _SPI_CT_CS0_ ^| r/w .8+<| Direct chip-select 0..7; setting `spi_csn_o(x)` low when set - <|`1` _SPI_CT_CS1_ ^| r/w - <|`2` _SPI_CT_CS2_ ^| r/w - <|`3` _SPI_CT_CS3_ ^| r/w - <|`4` _SPI_CT_CS4_ ^| r/w - <|`5` _SPI_CT_CS5_ ^| r/w - <|`6` _SPI_CT_CS6_ ^| r/w - <|`7` _SPI_CT_CS7_ ^| r/w - <|`8` _SPI_CT_EN_ ^| r/w <| SPI enable - <|`9` _SPI_CT_CPHA_ ^| r/w <| polarity of `spi_sck_o` when idle - <|`10` _SPI_CT_PRSC0_ ^| r/w .3+| 3-bit clock prescaler select - <|`11` _SPI_CT_PRSC1_ ^| r/w - <|`12` _SPI_CT_PRSC2_ ^| r/w - <|`14` _SPI_CT_SIZE0_ ^| r/w .2+<| transfer size (`00`=8-bit, `01`=16-bit, `10`=24-bit, `11`=32-bit) - <|`15` _SPI_CT_SIZE1_ ^| r/w - <|`31` _SPI_CT_BUSY_ ^| r/- <| transmission in progress when set -| `0xffffffac` | _SPI_DATA_ |`31:0` | r/w | receive/transmit data, LSB-aligned +.16+<| `0xffffffa8` .16+<| `NEORV32_SPI.CTRL` <|`0` _SPI_CTRL_CS0_ ^| r/w .8+<| Direct chip-select 0..7; setting `spi_csn_o(x)` low when set + <|`1` _SPI_CTRL_CS1_ ^| r/w + <|`2` _SPI_CTRL_CS2_ ^| r/w + <|`3` _SPI_CTRL_CS3_ ^| r/w + <|`4` _SPI_CTRL_CS4_ ^| r/w + <|`5` _SPI_CTRL_CS5_ ^| r/w + <|`6` _SPI_CTRL_CS6_ ^| r/w + <|`7` _SPI_CTRL_CS7_ ^| r/w + <|`8` _SPI_CTRL_EN_ ^| r/w <| SPI enable + <|`9` _SPI_CTRL_CPHA_ ^| r/w <| polarity of `spi_sck_o` when idle + <|`10` _SPI_CTRL_PRSC0_ ^| r/w .3+| 3-bit clock prescaler select + <|`11` _SPI_CTRL_PRSC1_ ^| r/w + <|`12` _SPI_CTRL_PRSC2_ ^| r/w + <|`14` _SPI_CTRL_SIZE0_ ^| r/w .2+<| transfer size (`00`=8-bit, `01`=16-bit, `10`=24-bit, `11`=32-bit) + <|`15` _SPI_CTRL_SIZE1_ ^| r/w + <|`31` _SPI_CTRL_BUSY_ ^| r/- <| transmission in progress when set +| `0xffffffac` | `NEORV32_SPI.DATA` |`31:0` | r/w | receive/transmit data, LSB-aligned |======================= diff --git a/docs/datasheet/soc_sysinfo.adoc b/docs/datasheet/soc_sysinfo.adoc index 27025320e..0d178792a 100644 --- a/docs/datasheet/soc_sysinfo.adoc +++ b/docs/datasheet/soc_sysinfo.adoc @@ -21,19 +21,19 @@ This device is always implemented – regardless of the actual hardware configur as the NEORV32 software runtime environment require information from this device (like memory layout and default clock speed) for correct operation. -.SYSINFO register map +.SYSINFO register map (`struct NEORV32_SYSINFO`) [cols="<2,<4,<7"] [options="header",grid="all"] |======================= | Address | Name [C] | Function -| `0xffffffe0` | _SYSINFO_CLK_ | clock speed in Hz (via top's <<_clock_frequency>> generic) -| `0xffffffe4` | _SYSINFO_CPU_ | specific CPU configuration (see <<_sysinfo_cpu_configuration>>) -| `0xffffffe8` | _SYSINFO_FEATURES_ | specific SoC configuration (see <<_sysinfo_soc_configuration>>) -| `0xffffffec` | _SYSINFO_CACHE_ | cache configuration information (see <<_sysinfo_cache_configuration>>) -| `0xfffffff0` | _SYSINFO_ISPACE_BASE_ | instruction address space base (via package's `ispace_base_c` constant) -| `0xfffffff4` | _SYSINFO_IMEM_SIZE_ | internal IMEM size in bytes (via top's <<_mem_int_imem_size>> generic) -| `0xfffffff8` | _SYSINFO_DSPACE_BASE_ | data address space base (via package's `sdspace_base_c` constant) -| `0xfffffffc` | _SYSINFO_DMEM_SIZE_ | internal DMEM size in bytes (via top's <<_mem_int_dmem_size>> generic) +| `0xffffffe0` | `NEORV32_SYSINFO.CLK` | clock speed in Hz (via top's <<_clock_frequency>> generic) +| `0xffffffe4` | `NEORV32_SYSINFO.CPU` | specific CPU configuration (see <<_sysinfo_cpu_configuration>>) +| `0xffffffe8` | `NEORV32_SYSINFO.SOC` | specific SoC configuration (see <<_sysinfo_soc_configuration>>) +| `0xffffffec` | `NEORV32_SYSINFO.CACHE` | cache configuration information (see <<_sysinfo_cache_configuration>>) +| `0xfffffff0` | `NEORV32_SYSINFO.ISPACE_BASE` | instruction address space base (via package's `ispace_base_c` constant) +| `0xfffffff4` | `NEORV32_SYSINFO.IMEM_SIZE` | internal IMEM size in bytes (via top's <<_mem_int_imem_size>> generic) +| `0xfffffff8` | `NEORV32_SYSINFO.DSPACE_BASE` | data address space base (via package's `sdspace_base_c` constant) +| `0xfffffffc` | `NEORV32_SYSINFO.DMEM_SIZE` | internal DMEM size in bytes (via top's <<_mem_int_dmem_size>> generic) |======================= @@ -61,31 +61,31 @@ and default clock speed) for correct operation. ===== SYSINFO - SoC Configuration -._SYSINFO_FEATURES_ bits +._SYSINFO_SOC_ bits [cols="^1,<10,<11"] [options="header",grid="all"] |======================= | Bit | Name [C] | Function -| `0` | _SYSINFO_FEATURES_BOOTLOADER_ | set if the processor-internal bootloader is implemented (via top's <<_int_bootloader_en>> generic) -| `1` | _SYSINFO_FEATURES_MEM_EXT_ | set if the external Wishbone bus interface is implemented (via top's <<_mem_ext_en>> generic) -| `2` | _SYSINFO_FEATURES_MEM_INT_IMEM_ | set if the processor-internal DMEM implemented (via top's <<_mem_int_dmem_en>> generic) -| `3` | _SYSINFO_FEATURES_MEM_INT_DMEM_ | set if the processor-internal IMEM is implemented (via top's <<_mem_int_imem_en>> generic) -| `4` | _SYSINFO_FEATURES_MEM_EXT_ENDIAN_ | set if external bus interface uses BIG-endian byte-order (via top's <<_mem_ext_big_endian>> generic) -| `5` | _SYSINFO_FEATURES_ICACHE_ | set if processor-internal instruction cache is implemented (via top's <<_icache_en>> generic) -| `14` | _SYSINFO_FEATURES_HW_RESET_ | set if on-chip debugger implemented (via top's <<_on_chip_debugger_en>> generic) -| `15` | _SYSINFO_FEATURES_HW_RST_ | set if a dedicated hardware reset of all core registers is implemented (via package's `dedicated_reset_c` constant) -| `16` | _SYSINFO_FEATURES_IO_GPIO_ | set if the GPIO is implemented (via top's <<_io_gpio_en>> generic) -| `17` | _SYSINFO_FEATURES_IO_MTIME_ | set if the MTIME is implemented (via top's <<_io_mtime_en>> generic) -| `18` | _SYSINFO_FEATURES_IO_UART0_ | set if the primary UART0 is implemented (via top's <<_io_uart0_en>> generic) -| `19` | _SYSINFO_FEATURES_IO_SPI_ | set if the SPI is implemented (via top's <<_io_spi_en>> generic) -| `20` | _SYSINFO_FEATURES_IO_TWI_ | set if the TWI is implemented (via top's <<_io_twi_en>> generic) -| `21` | _SYSINFO_FEATURES_IO_PWM_ | set if the PWM is implemented (via top's <<_io_pwm_en>> generic) -| `22` | _SYSINFO_FEATURES_IO_WDT_ | set if the WDT is implemented (via top's <<_io_wdt_en>> generic) -| `23` | _SYSINFO_FEATURES_IO_CFS_ | set if the custom functions subsystem is implemented (via top's <<_io_cfs_en>> generic) -| `24` | _SYSINFO_FEATURES_IO_TRNG_ | set if the TRNG is implemented (via top's _IO_TRNG_EN_ generic) -| `25` | _SYSINFO_FEATURES_IO_SLINK_ | set if the SLINK is implemented (via top's <<_slink_num_tx>> and/or <<_slink_num_rx>> generics) -| `26` | _SYSINFO_FEATURES_IO_UART1_ | set if the secondary UART1 is implemented (via top's <<_io_uart1_en>> generic) -| `27` | _SYSINFO_FEATURES_IO_NEOLED_ | set if the NEOLED is implemented (via top's <<_io_neoled_en>> generic) +| `0` | _SYSINFO_SOC_BOOTLOADER_ | set if the processor-internal bootloader is implemented (via top's <<_int_bootloader_en>> generic) +| `1` | _SYSINFO_SOC_MEM_EXT_ | set if the external Wishbone bus interface is implemented (via top's <<_mem_ext_en>> generic) +| `2` | _SYSINFO_SOC_MEM_INT_IMEM_ | set if the processor-internal DMEM implemented (via top's <<_mem_int_dmem_en>> generic) +| `3` | _SYSINFO_SOC_MEM_INT_DMEM_ | set if the processor-internal IMEM is implemented (via top's <<_mem_int_imem_en>> generic) +| `4` | _SYSINFO_SOC_MEM_EXT_ENDIAN_ | set if external bus interface uses BIG-endian byte-order (via top's <<_mem_ext_big_endian>> generic) +| `5` | _SYSINFO_SOC_ICACHE_ | set if processor-internal instruction cache is implemented (via top's <<_icache_en>> generic) +| `14` | _SYSINFO_SOC_HW_RESET_ | set if on-chip debugger implemented (via top's <<_on_chip_debugger_en>> generic) +| `15` | _SYSINFO_SOC_HW_RST_ | set if a dedicated hardware reset of all core registers is implemented (via package's `dedicated_reset_c` constant) +| `16` | _SYSINFO_SOC_IO_GPIO_ | set if the GPIO is implemented (via top's <<_io_gpio_en>> generic) +| `17` | _SYSINFO_SOC_IO_MTIME_ | set if the MTIME is implemented (via top's <<_io_mtime_en>> generic) +| `18` | _SYSINFO_SOC_IO_UART0_ | set if the primary UART0 is implemented (via top's <<_io_uart0_en>> generic) +| `19` | _SYSINFO_SOC_IO_SPI_ | set if the SPI is implemented (via top's <<_io_spi_en>> generic) +| `20` | _SYSINFO_SOC_IO_TWI_ | set if the TWI is implemented (via top's <<_io_twi_en>> generic) +| `21` | _SYSINFO_SOC_IO_PWM_ | set if the PWM is implemented (via top's <<_io_pwm_en>> generic) +| `22` | _SYSINFO_SOC_IO_WDT_ | set if the WDT is implemented (via top's <<_io_wdt_en>> generic) +| `23` | _SYSINFO_SOC_IO_CFS_ | set if the custom functions subsystem is implemented (via top's <<_io_cfs_en>> generic) +| `24` | _SYSINFO_SOC_IO_TRNG_ | set if the TRNG is implemented (via top's _IO_TRNG_EN_ generic) +| `25` | _SYSINFO_SOC_IO_SLINK_ | set if the SLINK is implemented (via top's <<_slink_num_tx>> and/or <<_slink_num_rx>> generics) +| `26` | _SYSINFO_SOC_IO_UART1_ | set if the secondary UART1 is implemented (via top's <<_io_uart1_en>> generic) +| `27` | _SYSINFO_SOC_IO_NEOLED_ | set if the NEOLED is implemented (via top's <<_io_neoled_en>> generic) |======================= diff --git a/docs/datasheet/soc_trng.adoc b/docs/datasheet/soc_trng.adoc index 6e5556356..c4babb62d 100644 --- a/docs/datasheet/soc_trng.adoc +++ b/docs/datasheet/soc_trng.adoc @@ -55,10 +55,10 @@ mask of the LFSR can be customized using `lfsr_taps_c`. **Using the TRNG** -The TRNG features a single register for status and data access. When the _TRNG_CT_EN_ control register bit is -set, the TRNG is enabled and starts operation. As soon as the _TRNG_CT_VALID_ bit is set, the currently -sampled 8-bit random data byte can be obtained from the lowest 8 bits of the TRNG_CT register -(_TRNG_CT_DATA_MSB_ : _TRNG_CT_DATA_LSB_). The _TRNG_CT_VALID_ bit is automatically cleared +The TRNG features a single register for status and data access. When the _TRNG_CTRL_EN_ control register (`CTRL`) +bit is set, the TRNG is enabled and starts operation. As soon as the _TRNG_CTRL_VALID_ bit is set, the currently +sampled 8-bit random data byte can be obtained from the lowest 8 bits of the `CTRL` register +(_TRNG_CTRL_DATA_MSB_ : _TRNG_CTRL_DATA_LSB_). The _TRNG_CTRL_VALID_ bit is automatically cleared when reading the control register. [IMPORTANT] @@ -73,12 +73,12 @@ However, generating larger histograms of the generated random number shows an eq average of the random numbers = 127). A simple evaluation test/demo program can be found in `sw/example/demo_trng`. -.TRNG register map +.TRNG register map (`struct NEORV32_TRNG`) [cols="<2,<2,<4,^1,<7"] [options="header",grid="all"] |======================= | Address | Name [C] | Bit(s), Name [C] | R/W | Function -.3+<| `0xffffffb8` .3+<| _TRNG_CT_ <|`7:0` _TRNG_CT_DATA_MSB_ : _TRNG_CT_DATA_MSB_ ^| r/- <| 8-bit random data output - <|`30` _TRNG_CT_EN_ ^| r/w <| TRNG enable - <|`31` _TRNG_CT_VALID_ ^| r/- <| random data output is valid when set +.3+<| `0xffffffb8` .3+<| `NEORV32_TRNG.CTRL` <|`7:0` _TRNG_CTRL_DATA_MSB_ : _TRNG_CTRL_DATA_MSB_ ^| r/- <| 8-bit random data output + <|`30` _TRNG_CTRL_EN_ ^| r/w <| TRNG enable + <|`31` _TRNG_CTRL_VALID_ ^| r/- <| random data output is valid when set |======================= diff --git a/docs/datasheet/soc_twi.adoc b/docs/datasheet/soc_twi.adoc index a3483f2bd..ce49ca383 100644 --- a/docs/datasheet/soc_twi.adoc +++ b/docs/datasheet/soc_twi.adoc @@ -25,19 +25,19 @@ The NEORV32 TWI implements a **TWI controller**. It features "clock stretching" register), so a slow peripheral can halt the transmission by pulling the SCL line low. Currently, **no multi-controller support** is available. Also, the NEORV32 TWI unit cannot operate in peripheral mode. -The TWI is enabled via the _TWI_CT_EN_ bit in the _TWI_CT_ control register. The user program can start / stop a +The TWI is enabled via the _TWI_CTRL_EN_ bit in the `CTRL` control register. The user program can start / stop a transmission by issuing a START or STOP condition. These conditions are generated by setting the -according bits (_TWI_CT_START_ or _TWI_CT_STOP_) in the control register. +according bits (_TWI_CTRL_START_ or _TWI_CTRL_STOP_) in the control register. -Data is send by writing a byte to the _TWI_DATA_ register. Received data can also be read from this +Data is send by writing a byte to the `DATA` register. Received data can also be read from this register. The TWI controller is busy (transmitting data or performing a START or STOP condition) as long as the -_TWI_CT_BUSY_ bit in the control register is set. +_TWI_CTRL_BUSY_ bit in the control register is set. -An accessed peripheral has to acknowledge each transferred byte. When the _TWI_CT_ACK_ bit is set after a +An accessed peripheral has to acknowledge each transferred byte. When the _TWI_CTRL_ACK_ bit is set after a completed transmission, the accessed peripheral has send an acknowledge. If it is cleared after a transmission, the peripheral has send a not-acknowledge (NACK). The NEORV32 TWI controller can also send an ACK by itself ("controller acknowledge _MACK_") after a transmission by pulling SDA low during the -ACK time slot. Set the _TWI_CT_MACK_ bit to activate this feature. If this bit is cleared, the ACK/NACK of the +ACK time slot. Set the _TWI_CTRL_MACK_ bit to activate this feature. If this bit is cleared, the ACK/NACK of the peripheral is sampled in this time slot instead (normal mode). In summary, the following independent TWI operations can be triggered by the application program: @@ -50,35 +50,35 @@ In summary, the following independent TWI operations can be triggered by the app The serial clock (SCL) and the serial data (SDA) lines can only be actively driven low by the controller. Hence, external pull-up resistors are required for these lines. -The TWI clock frequency is defined via the 3-bit _TWI_CT_PRSCx_ clock prescaler. The following prescalers +The TWI clock frequency is defined via the 3-bit _TWI_CTRL_PRSCx_ clock prescaler. The following prescalers are available: .TWI prescaler configuration [cols="<4,^1,^1,^1,^1,^1,^1,^1,^1"] [options="header",grid="rows"] |======================= -| **`TWI_CT_PRSCx`** | `0b000` | `0b001` | `0b010` | `0b011` | `0b100` | `0b101` | `0b110` | `0b111` +| **`TWI_CTRL_PRSCx`** | `0b000` | `0b001` | `0b010` | `0b011` | `0b100` | `0b101` | `0b110` | `0b111` | Resulting `clock_prescaler` | 2 | 4 | 8 | 64 | 128 | 1024 | 2048 | 4096 |======================= -Based on the _TWI_CT_PRSCx_ configuration, the actual TWI clock frequency f~SCL~ is derived from the processor main clock f~main~ and is determined by: +Based on the _TWI_CTRL_PRSCx_ configuration, the actual TWI clock frequency f~SCL~ is derived from the processor main clock f~main~ and is determined by: _**f~SCL~**_ = _f~main~[Hz]_ / (4 * `clock_prescaler`) -.TWI register map +.TWI register map (`struct NEORV32_TWI`) [cols="<2,<2,<4,^1,<7"] [options="header",grid="all"] |======================= | Address | Name [C] | Bit(s), Name [C] | R/W | Function -.10+<| `0xffffffb0` .10+<| _TWI_CT_ <|`0` _TWI_CT_EN_ ^| r/w <| TWI enable - <|`1` _TWI_CT_START_ ^| r/w <| generate START condition - <|`2` _TWI_CT_STOP_ ^| r/w <| generate STOP condition - <|`3` _TWI_CT_PRSC0_ ^| r/w .3+<| 3-bit clock prescaler select - <|`4` _TWI_CT_PRSC1_ ^| r/w - <|`5` _TWI_CT_PRSC2_ ^| r/w - <|`6` _TWI_CT_MACK_ ^| r/w <| generate controller ACK for each transmission ("MACK") - <|`7` _TWI_CT_CKSTEN_ ^| r/w <| allow clock-stretching by peripherals when set - <|`30` _TWI_CT_ACK_ ^| r/- <| ACK received when set - <|`31` _TWI_CT_BUSY_ ^| r/- <| transfer/START/STOP in progress when set -| `0xffffffb4` | _TWI_DATA_ |`7:0` _TWI_DATA_MSB_ : TWI_DATA_LSB_ | r/w | receive/transmit data +.10+<| `0xffffffb0` .10+<| `NEORV32_TWI.CTRL` <|`0` _TWI_CTRL_EN_ ^| r/w <| TWI enable + <|`1` _TWI_CTRL_START_ ^| r/w <| generate START condition + <|`2` _TWI_CTRL_STOP_ ^| r/w <| generate STOP condition + <|`3` _TWI_CTRL_PRSC0_ ^| r/w .3+<| 3-bit clock prescaler select + <|`4` _TWI_CTRL_PRSC1_ ^| r/w + <|`5` _TWI_CTRL_PRSC2_ ^| r/w + <|`6` _TWI_CTRL_MACK_ ^| r/w <| generate controller ACK for each transmission ("MACK") + <|`7` _TWI_CTRL_CKSTEN_ ^| r/w <| allow clock-stretching by peripherals when set + <|`30` _TWI_CTRL_ACK_ ^| r/- <| ACK received when set + <|`31` _TWI_CTRL_BUSY_ ^| r/- <| transfer/START/STOP in progress when set +| `0xffffffb4` | `NEORV32_TWI.DATA` |`7:0` _TWI_DATA_MSB_ : TWI_DATA_LSB_ | r/w | receive/transmit data |======================= diff --git a/docs/datasheet/soc_uart.adoc b/docs/datasheet/soc_uart.adoc index eae02dd6d..1c9d67603 100644 --- a/docs/datasheet/soc_uart.adoc +++ b/docs/datasheet/soc_uart.adoc @@ -31,22 +31,22 @@ computer/user and an application running on the processor platform. The NEORV32 standard configuration frame configuration: 8 data bits, an optional parity bit (even or odd) and 1 stop bit. The parity and the actual Baudrate are configurable by software. -The UART0 is enabled by setting the _UART_CT_EN_ bit in the UART control register _UART0_CT_. The actual -transmission Baudrate (like 19200) is configured via the 12-bit _UART_CT_BAUDxx_ baud prescaler (`baud_rate`) and the -3-bit _UART_CT_PRSCx_ clock prescaler. +The UART0 is enabled by setting the _UART_CTRL_EN_ bit in the UART control register `CTRL`. The actual +transmission Baudrate (like 19200) is configured via the 12-bit _UART_CTRL_BAUDxx_ baud prescaler (`baud_rate`) and the +3-bit _UART_CTRL_PRSCx_ clock prescaler. .UART prescaler configuration [cols="<4,^1,^1,^1,^1,^1,^1,^1,^1"] [options="header",grid="rows"] |======================= -| **`UART_CT_PRSCx`** | `0b000` | `0b001` | `0b010` | `0b011` | `0b100` | `0b101` | `0b110` | `0b111` +| **`UART_CTRL_PRSCx`** | `0b000` | `0b001` | `0b010` | `0b011` | `0b100` | `0b101` | `0b110` | `0b111` | Resulting `clock_prescaler` | 2 | 4 | 8 | 64 | 128 | 1024 | 2048 | 4096 |======================= _**Baudrate**_ = (_f~main~[Hz]_ / `clock_prescaler`) / (`baud_rate` + 1) -A new transmission is started by writing the data byte to be send to the lowest byte of the _UART0_DATA_ register. The -transfer is completed when the _UART_CT_TX_BUSY_ control register flag returns to zero. A new received byte +A new transmission is started by writing the data byte to be send to the lowest byte of the `DATA` register. The +transfer is completed when the _UART_CTRL_TX_BUSY_ control register flag returns to zero. A new received byte is available when the _UART_DATA_AVAIL_ flag of the UART0_DATA register is set. A "frame error" in a received byte (broken stop bit) is indicated via the _UART_DATA_FERR_ flag in the UART0_DATA register. @@ -55,23 +55,23 @@ is available when the _UART_DATA_AVAIL_ flag of the UART0_DATA register is set. The UART receive engine provides a simple data buffer with two entries. These two entries are transparent for the user. The transmitting device can send up to 2 chars to the UART without risking data loss. If another char is sent before at least one char has been read from the buffer data loss occurs. This situation can be -detected via the receiver overrun flag _UART_DATA_OVERR_ in the _UART0_DATA_ register. The flag is -automatically cleared after reading _UART0_DATA_. +detected via the receiver overrun flag _UART_DATA_OVERR_ in the `DATA` register. The flag is +automatically cleared after reading `DATA`. **Parity Modes** -The parity flag is added if the _UART_CT_PMODE1_ flag is set. When _UART_CT_PMODE0_ is zero the UART +The parity flag is added if the _UART_CTRL_PMODE1_ flag is set. When _UART_CTRL_PMODE0_ is zero the UART operates in "even parity" mode. If this flag is set, the UART operates in "odd parity" mode. Parity errors in received data are indicated via the _UART_DATA_PERR_ flag in the _UART_DATA_ registers. This flag is updated with each new received character. A frame error in the received data (i.e. stop bit is not set) is indicated via the -_UART_DATA_FERR_ flag in the _UART0_DATA_. This flag is also updated with each new received character +_UART_DATA_FERR_ flag in the `DATA`. This flag is also updated with each new received character **Hardware Flow Control – RTS/CTS** The UART supports hardware flow control using the standard CTS (clear to send) and/or RTS (ready to send / ready to receive "RTR") signals. Both hardware control flow mechanisms can be individually enabled. -If **RTS hardware flow control** is enabled by setting the _UART_CT_RTS_EN_ control register flag, the UART +If **RTS hardware flow control** is enabled by setting the _UART_CTRL_RTS_EN_ control register flag, the UART will pull the `uart0_rts_o` signal low if the UART's receiver is idle and no received data is waiting to get read by application software. As long as this signal is low the connected device can send new data. `uart0_rts_o` is always LOW if the UART is disabled. @@ -79,19 +79,19 @@ The RTS line is de-asserted (going high) as soon as the start bit of a new incom detected. The transmitting device continues sending the current char and can also send another char (due to the RX double-buffering), which is done by most terminal programs. Any additional data send when RTS is still asserted will override the RX input buffer causing data loss. This will set the _UART_DATA_OVERR_ flag in the -_UART0_DATA_ register. Any read access to this register clears the flag again. +`DATA` register. Any read access to this register clears the flag again. -If **CTS hardware flow control** is enabled by setting the _UART_CT_CTS_EN_ control register flag, the UART's +If **CTS hardware flow control** is enabled by setting the _UART_CTRL_CTS_EN_ control register flag, the UART's transmitter will not start sending a new char until the `uart0_cts_i` signal goes low. If a new data to be send is written to the UART data register while `uart0_cts_i` is not asserted (=low), the UART will wait for `uart0_cts_i` to become asserted (=high) before sending starts. During this time, the UART busy flag -_UART_CT_TX_BUSY_ remains set. +_UART_CTRL_TX_BUSY_ remains set. If `uart0_cts_i` is asserted, no new data transmission will be started by the UART. The state of the `uart0_cts_i` signals has no effect on a transmission being already in progress. Signal changes on `uart0_cts_i` during an active transmission are ignored. Application software can check -the current state of the `uart0_cts_o` input signal via the _UART_CT_CTS_ control register flag. +the current state of the `uart0_cts_o` input signal via the _UART_CTRL_CTS_ control register flag. [TIP] Please note that – just like the RXD and TXD signals – the RTS and CTS signals have to be **cross**-coupled @@ -108,18 +108,18 @@ state of the RX double-buffer. **Simulation Mode** -The default UART0 operation will transmit any data written to the _UART0_DATA_ register via the serial TX line at +The default UART0 operation will transmit any data written to the `DATA` register via the serial TX line at the defined baud rate. Even though the default testbench provides a simulated UART0 receiver, which outputs any received char to the simulator console, such a transmission takes a lot of time. To accelerate UART0 output during simulation (and also to dump large amounts of data for further processing like verification) the UART0 features a **simulation mode**. -The simulation mode is enabled by setting the _UART_CT_SIM_MODE_ bit in the UART0's control register -_UART0_CT_. Any other UART0 configuration bits are irrelevant, but the UART0 has to be enabled via the -_UART_CT_EN_ bit. When the simulation mode is enabled, any written char to _UART0_DATA_ (bits 7:0) is +The simulation mode is enabled by setting the _UART_CTRL_SIM_MODE_ bit in the UART0's control register +`CTRL`. Any other UART0 configuration bits are irrelevant, but the UART0 has to be enabled via the +_UART_CTRL_EN_ bit. When the simulation mode is enabled, any written char to `DATA` (bits 7:0) is directly output as ASCII char to the simulator console. Additionally, all text is also stored to a text file `neorv32.uart0.sim_mode.text.out` in the simulation home folder. Furthermore, the whole 32-bit word -written to _UART0_DATA_ is stored as plain 8-char hexadecimal value to a second text file +written to `DATA` is stored as plain 8-char hexadecimal value to a second text file `neorv32.uart0.sim_mode.data.out` also located in the simulation home folder. If the UART is configured for simulation mode there will be **NO physical UART0 transmissions via @@ -129,29 +129,29 @@ If the UART is configured for simulation mode there will be **NO physical UART0 More information regarding the simulation-mode of the UART0 can be found in the Uer Guide section https://stnolting.github.io/neorv32/ug/#_simulating_the_processor[Simulating the Processor]. -.UART0 register map +.UART0 register map (`struct NEORV32_UART0`) [cols="<6,<7,<10,^2,<18"] [options="header",grid="all"] |======================= | Address | Name [C] | Bit(s), Name [C] | R/W | Function -.12+<| `0xffffffa0` .12+<| _UART0_CT_ <|`11:0` _UART_CT_BAUDxx_ ^| r/w <| 12-bit BAUD value configuration value - <|`12` _UART_CT_SIM_MODE_ ^| r/w <| enable **simulation mode** - <|`20` _UART_CT_RTS_EN_ ^| r/w <| enable RTS hardware flow control - <|`21` _UART_CT_CTS_EN_ ^| r/w <| enable CTS hardware flow control - <|`22` _UART_CT_PMODE0_ ^| r/w .2+<| parity bit enable and configuration (`00`/`01`= no parity; `10`=even parity; `11`=odd parity) - <|`23` _UART_CT_PMODE1_ ^| r/w - <|`24` _UART_CT_PRSC0_ ^| r/w .3+<| 3-bit baudrate clock prescaler select - <|`25` _UART_CT_PRSC1_ ^| r/w - <|`26` _UART_CT_PRSC2_ ^| r/w - <|`27` _UART_CT_CTS_ ^| r/- <| current state of UART's CTS input signal - <|`28` _UART_CT_EN_ ^| r/w <| UART enable - <|`31` _UART_CT_TX_BUSY_ ^| r/- <| trasmitter busy flag -.6+<| `0xffffffa4` .6+<| _UART0_DATA_ <|`7:0` _UART_DATA_MSB_ : _UART_DATA_LSB_ ^| r/w <| receive/transmit data (8-bit) - <|`31:0` - ^| -/w <| **simulation data output** - <|`28` _UART_DATA_PERR_ ^| r/- <| RX parity error - <|`29` _UART_DATA_FERR_ ^| r/- <| RX data frame error (stop bit nt set) - <|`30` _UART_DATA_OVERR_ ^| r/- <| RX data overrun - <|`31` _UART_DATA_AVAIL_ ^| r/- <| RX data available when set +.12+<| `0xffffffa0` .12+<| `NEORV32_UART0.CTRL` <|`11:0` _UART_CT_BAUDxx_ ^| r/w <| 12-bit BAUD value configuration value + <|`12` _UART_CT_SIM_MODE_ ^| r/w <| enable **simulation mode** + <|`20` _UART_CT_RTS_EN_ ^| r/w <| enable RTS hardware flow control + <|`21` _UART_CT_CTS_EN_ ^| r/w <| enable CTS hardware flow control + <|`22` _UART_CT_PMODE0_ ^| r/w .2+<| parity bit enable and configuration (`00`/`01`= no parity; `10`=even parity; `11`=odd parity) + <|`23` _UART_CT_PMODE1_ ^| r/w + <|`24` _UART_CT_PRSC0_ ^| r/w .3+<| 3-bit baudrate clock prescaler select + <|`25` _UART_CT_PRSC1_ ^| r/w + <|`26` _UART_CT_PRSC2_ ^| r/w + <|`27` _UART_CT_CTS_ ^| r/- <| current state of UART's CTS input signal + <|`28` _UART_CT_EN_ ^| r/w <| UART enable + <|`31` _UART_CT_TX_BUSY_ ^| r/- <| trasmitter busy flag +.6+<| `0xffffffa4` .6+<| `NEORV32_UART0.DATA` <|`7:0` _UART_DATA_MSB_ : _UART_DATA_LSB_ ^| r/w <| receive/transmit data (8-bit) + <|`31:0` - ^| -/w <| **simulation data output** + <|`28` _UART_DATA_PERR_ ^| r/- <| RX parity error + <|`29` _UART_DATA_FERR_ ^| r/- <| RX data frame error (stop bit nt set) + <|`30` _UART_DATA_OVERR_ ^| r/- <| RX data overrun + <|`31` _UART_DATA_AVAIL_ ^| r/- <| RX data available when set |======================= @@ -180,7 +180,7 @@ section https://stnolting.github.io/neorv32/ug/#_simulating_the_processor[Simula The secondary UART (UART1) is functional identical to the primary UART (<<_primary_universal_asynchronous_receiver_and_transmitter_uart0>>). Obviously, UART1 has different addresses for -thw control register (_UART1_CT_) and the data register (_UART1_DATA_) – see the register map below. However, the +the control register (`CTRL`) and the data register (`DATA`) – see the register map below. However, the register bits/flags use the same bit positions and naming. Furthermore, the "RX done" and "TX done" interrupts are mapped to different CPU fast interrupt channels. @@ -191,27 +191,27 @@ output data is written to UART1-specific files: `neorv32.uart1.sim_mode.text.out plain ASCII text and `neorv32.uart1.sim_mode.data.out` is used to store full 32-bit hexadecimal encoded data words. -.UART1 register map +.UART1 register map (`struct NEORV32_UART1`) [cols="<6,<7,<10,^2,<18"] [options="header",grid="all"] |======================= | Address | Name [C] | Bit(s), Name [C] | R/W | Function -.12+<| `0xffffffd0` .12+<| _UART1_CT_ <|`11:0` _UART_CT_BAUDxx_ ^| r/w <| 12-bit BAUD value configuration value - <|`12` _UART_CT_SIM_MODE_ ^| r/w <| enable **simulation mode** - <|`20` _UART_CT_RTS_EN_ ^| r/w <| enable RTS hardware flow control - <|`21` _UART_CT_CTS_EN_ ^| r/w <| enable CTS hardware flow control - <|`22` _UART_CT_PMODE0_ ^| r/w .2+<| parity bit enable and configuration (`00`/`01`= no parity; `10`=even parity; `11`=odd parity) - <|`23` _UART_CT_PMODE1_ ^| r/w - <|`24` _UART_CT_PRSC0_ ^| r/w .3+<| 3-bit baudrate clock prescaler select - <|`25` _UART_CT_PRSC1_ ^| r/w - <|`26` _UART_CT_PRSC2_ ^| r/w - <|`27` _UART_CT_CTS_ ^| r/- <| current state of UART's CTS input signal - <|`28` _UART_CT_EN_ ^| r/w <| UART enable - <|`31` _UART_CT_TX_BUSY_ ^| r/- <| trasmitter busy flag -.6+<| `0xffffffd4` .6+<| _UART1_DATA_ <|`7:0` _UART_DATA_MSB_ : _UART_DATA_LSB_ ^| r/w <| receive/transmit data (8-bit) - <|`31:0` - ^| -/w <| **simulation data output** - <|`28` _UART_DATA_PERR_ ^| r/- <| RX parity error - <|`29` _UART_DATA_FERR_ ^| r/- <| RX data frame error (stop bit nt set) - <|`30` _UART_DATA_OVERR_ ^| r/- <| RX data overrun - <|`31` _UART_DATA_AVAIL_ ^| r/- <| RX data available when set +.12+<| `0xffffffd0` .12+<| `NEORV32_UART1.CTRL` <|`11:0` _UART_CT_BAUDxx_ ^| r/w <| 12-bit BAUD value configuration value + <|`12` _UART_CT_SIM_MODE_ ^| r/w <| enable **simulation mode** + <|`20` _UART_CT_RTS_EN_ ^| r/w <| enable RTS hardware flow control + <|`21` _UART_CT_CTS_EN_ ^| r/w <| enable CTS hardware flow control + <|`22` _UART_CT_PMODE0_ ^| r/w .2+<| parity bit enable and configuration (`00`/`01`= no parity; `10`=even parity; `11`=odd parity) + <|`23` _UART_CT_PMODE1_ ^| r/w + <|`24` _UART_CT_PRSC0_ ^| r/w .3+<| 3-bit baudrate clock prescaler select + <|`25` _UART_CT_PRSC1_ ^| r/w + <|`26` _UART_CT_PRSC2_ ^| r/w + <|`27` _UART_CT_CTS_ ^| r/- <| current state of UART's CTS input signal + <|`28` _UART_CT_EN_ ^| r/w <| UART enable + <|`31` _UART_CT_TX_BUSY_ ^| r/- <| trasmitter busy flag +.6+<| `0xffffffd4` .6+<| `NEORV32_UART1.DATA` <|`7:0` _UART_DATA_MSB_ : _UART_DATA_LSB_ ^| r/w <| receive/transmit data (8-bit) + <|`31:0` - ^| -/w <| **simulation data output** + <|`28` _UART_DATA_PERR_ ^| r/- <| RX parity error + <|`29` _UART_DATA_FERR_ ^| r/- <| RX data frame error (stop bit nt set) + <|`30` _UART_DATA_OVERR_ ^| r/- <| RX data overrun + <|`31` _UART_DATA_AVAIL_ ^| r/- <| RX data available when set |======================= diff --git a/docs/datasheet/soc_wdt.adoc b/docs/datasheet/soc_wdt.adoc index 18d0353cc..07358b463 100644 --- a/docs/datasheet/soc_wdt.adoc +++ b/docs/datasheet/soc_wdt.adoc @@ -19,14 +19,14 @@ The watchdog (WDT) provides a last resort for safety-critical applications. The wide counter that needs to be reset every now and then by the user program. If the counter overflows, either a system reset or an interrupt is generated (depending on the configured operation mode). -Configuration of the watchdog is done by a single control register _WDT_CT_. The watchdog is enabled by -setting the _WDT_CT_EN_ bit. The clock used to increment the internal counter is selected via the 3-bit -_WDT_CT_CLK_SELx_ prescaler: +Configuration of the watchdog is done by a single control register `CTRL`. The watchdog is enabled by +setting the _WDT_CTRL_EN_ bit. The clock used to increment the internal counter is selected via the 3-bit +_WDT_CTRL_CLK_SELx_ prescaler: [cols="^3,^3,>4"] [options="header",grid="rows"] |======================= -| **`WDT_CT_CLK_SELx`** | Main clock prescaler | Timeout period in clock cycles +| **`WDT_CTRL_CLK_SELx`** | Main clock prescaler | Timeout period in clock cycles | `0b000` | 2 | 2 097 152 | `0b001` | 4 | 4 194 304 | `0b010` | 8 | 8 388 608 @@ -39,31 +39,31 @@ _WDT_CT_CLK_SELx_ prescaler: Whenever the internal timer overflows the watchdog executes one of two possible actions: Either a hard processor reset is triggered or an interrupt is requested at CPU's fast interrupt channel #0. The -WDT_CT_MODE bit defines the action to be taken on an overflow: When cleared, the Watchdog will trigger an +WDT_CTRL_MODE bit defines the action to be taken on an overflow: When cleared, the Watchdog will trigger an IRQ, when set the WDT will cause a system reset. The configured actions can also be triggered manually at -any time by setting the _WDT_CT_FORCE_ bit. The watchdog is reset by setting the _WDT_CT_RESET_ bit. +any time by setting the _WDT_CTRL_FORCE_ bit. The watchdog is reset by setting the _WDT_CTRL_RESET_ bit. -The cause of the last action of the watchdog can be determined via the _WDT_CT_RCAUSE_ flag. If this flag is +The cause of the last action of the watchdog can be determined via the _WDT_CTRL_RCAUSE_ flag. If this flag is zero, the processor has been reset via the external reset signal. If this flag is set the last system reset was initiated by the watchdog. The Watchdog control register can be locked in order to protect the current configuration. The lock is -activated by setting bit _WDT_CT_LOCK_. In the locked state any write access to the configuration flags is +activated by setting bit _WDT_CTRL_LOCK_. In the locked state any write access to the configuration flags is ignored (see table below, "accessible if locked"). Read accesses to the control register are not effected. The lock can only be removed by a system reset (via external reset signal or via a watchdog reset action). -.WDT register map +.WDT register map (`struct NEORV32_WDT`) [cols="<2,<2,<4,^1,^2,<4"] [options="header",grid="all"] |======================= | Address | Name [C] | Bit(s), Name [C] | R/W | Writable if locked | Function -.9+<| `0xffffffbc` .9+<| _WDT_CT_ <|`0` _WDT_CT_EN_ ^| r/w ^| no <| watchdog enable - <|`1` _WDT_CT_CLK_SEL0_ ^| r/w ^| no .3+<| 3-bit clock prescaler select - <|`2` _WDT_CT_CLK_SEL1_ ^| r/w ^| no - <|`3` _WDT_CT_CLK_SEL2_ ^| r/w ^| no - <|`4` _WDT_CT_MODE_ ^| r/w ^| no <| overflow action: `1`=reset, `0`=IRQ - <|`5` _WDT_CT_RCAUSE_ ^| r/- ^| - <| cause of last system reset: `0`=caused by external reset signal, `1`=caused by watchdog - <|`6` _WDT_CT_RESET_ ^| -/w ^| yes <| watchdog reset when set, auto-clears - <|`7` _WDT_CT_FORCE_ ^| -/w ^| yes <| force configured watchdog action when set, auto-clears - <|`8` _WDT_CT_LOCK_ ^| r/w ^| no <| lock access to configuration when set, clears only on system reset (via external reset signal OR watchdog reset action = reset) +.9+<| `0xffffffbc` .9+<| `NEORV32_WDT.CTRL` <|`0` _WDT_CTRL_EN_ ^| r/w ^| no <| watchdog enable + <|`1` _WDT_CTRL_CLK_SEL0_ ^| r/w ^| no .3+<| 3-bit clock prescaler select + <|`2` _WDT_CTRL_CLK_SEL1_ ^| r/w ^| no + <|`3` _WDT_CTRL_CLK_SEL2_ ^| r/w ^| no + <|`4` _WDT_CTRL_MODE_ ^| r/w ^| no <| overflow action: `1`=reset, `0`=IRQ + <|`5` _WDT_CTRL_RCAUSE_ ^| r/- ^| - <| cause of last system reset: `0`=caused by external reset signal, `1`=caused by watchdog + <|`6` _WDT_CTRL_RESET_ ^| -/w ^| yes <| watchdog reset when set, auto-clears + <|`7` _WDT_CTRL_FORCE_ ^| -/w ^| yes <| force configured watchdog action when set, auto-clears + <|`8` _WDT_CTRL_LOCK_ ^| r/w ^| no <| lock access to configuration when set, clears only on system reset (via external reset signal OR watchdog reset action = reset) |======================= diff --git a/docs/datasheet/soc_wishbone.adoc b/docs/datasheet/soc_wishbone.adoc index 01f0ae0e0..3433add27 100644 --- a/docs/datasheet/soc_wishbone.adoc +++ b/docs/datasheet/soc_wishbone.adoc @@ -128,8 +128,7 @@ Endianness (of the external memory interface) can be configured via the _MEM_EXT By default, the external memory interface uses little-endian byte-order (like the rest of the processor / CPU). Application software can check the Endianness configuration of the external bus interface via the -_SYSINFO_FEATURES_MEM_EXT_ENDIAN_ flag in the processor's SYSINFO module (see section -<<_system_configuration_information_memory_sysinfo>> for more information). +SYSINFO module (see section <<_system_configuration_information_memory_sysinfo>> for more information). **AXI4-Lite Connectivity** diff --git a/docs/datasheet/soc_xirq.adoc b/docs/datasheet/soc_xirq.adoc index ae814f2dd..aa4e21021 100644 --- a/docs/datasheet/soc_xirq.adoc +++ b/docs/datasheet/soc_xirq.adoc @@ -21,23 +21,23 @@ single _CPU fast interrupt request_. **Theory of Operation** -The XIRQ provides up to 32 interrupt _channels_ (configured via the _XIRQ_NUM_CH_ generic). Each bit in `xirq_i` -represents one interrupt channel. An interrupt channel is enabled by setting the according bit in the -interrupt enable register _XIRQ_IER_. +The XIRQ provides up to 32 interrupt _channels_ (configured via the _XIRQ_NUM_CH_ generic). Each bit in the `xirq_i` +input signal vector represents one interrupt channel. An interrupt channel is enabled by setting the according bit in the +interrupt enable register `IER`. If the configured trigger (see below) of an enabled channel fires, the request is stored into an internal buffer. -This buffer is available via the interrupt pending register _XIRQ_IPR_. A `1` in this register indicates that the +This buffer is available via the interrupt pending register `IPR`. A `1` in this register indicates that the corresponding interrupt channel has fired but has not yet been serviced (so it is pending). Pending IRQs can be cleared by writing `1` to the according pending bit. As soon as there is a least one pending interrupt in the buffer, an interrupt request is send to the CPU. -The CPU can determine firing interrupt request either by checking the bits in the _XIRQ_IPR_ register, which show all -pending interrupt and does not prioritize, or by reading the interrupt source _XIRQ_SCR_ register. +The CPU can determine firing interrupt request either by checking the bits in the `IPR` register, which show all +pending interrupt, or by reading the interrupt source register `SCR`. This register provides a 5-bit wide ID (0..31) that shows the interrupt request with _highest priority_. Interrupt channel `xirq_i(0)` has highest priority and `xirq_i(_XIRQ_NUM_CH_-1)` has lowest priority. This priority assignment is fixed and cannot be altered by software. -The CPU can use the ID from _XIRQ_SCR_ to service IRQ according to their priority. To acknowledge the according -interrupt the CPU can write `1 << XIRQ_SCR` to _XIRQ_IPR_. +The CPU can use the ID from `SCR` to service IRQ according to their priority. To acknowledge the according +interrupt the CPU can write `1 << SCR` to `IPR`. **IRQ Trigger Configuration** @@ -57,13 +57,13 @@ XIRQ_TRIGGER_TYPE => x"00000001"; XIRQ_TRIGGER_POLARITY => x"ffffffff"; ---- -.XIRQ register map +.XIRQ register map (`struct NEORV32_XIRQ`) [cols="^4,<5,^2,^2,<14"] [options="header",grid="all"] |======================= | Address | Name [C] | Bit(s) | R/W | Function -| `0xffffff80` | _XIRQ_IER_ | `31:0` | r/w | Interrupt enable register (one bit per channel, LSB-aligned) -| `0xffffff84` | _XIRQ_IPR_ | `31:0` | r/w | Interrupt pending register (one bit per channel, LSB-aligned); writing 1 to a bit clears according interrupt; writing _any_ value acknowledges the _current_ CPU interrupt -| `0xffffff88` | _XIRQ_SCR_ | `4:0` | r/- | Channel id (0..31) of firing IRQ (prioritized!) -| `0xffffff8c` | - | `31:0` | r/- | _reserved_, read as zero +| `0xffffff80` | `NEORV32_XIRQ.IER` | `31:0` | r/w | Interrupt enable register (one bit per channel, LSB-aligned) +| `0xffffff84` | `NEORV32_XIRQ.IPR` | `31:0` | r/w | Interrupt pending register (one bit per channel, LSB-aligned); writing 1 to a bit clears according interrupt; writing _any_ value acknowledges the _current_ CPU interrupt +| `0xffffff88` | `NEORV32_XIRQ.SCR` | `4:0` | r/- | Channel id (0..31) of firing IRQ (prioritized!) +| `0xffffff8c` | - | `31:0` | r/- | _reserved_, read as zero |======================= diff --git a/docs/datasheet/software.adoc b/docs/datasheet/software.adoc index 1d3710fe1..9d9f7a82e 100644 --- a/docs/datasheet/software.adoc +++ b/docs/datasheet/software.adoc @@ -61,6 +61,7 @@ files are currently part of the NEORV32 core library: |======================= | C source file | C header file | Description | - | `neorv32.h` | main NEORV32 definitions and library file +| - | `neorv32_legacy.h` | legacy back-compatibility layer | `neorv32_cfs.c` | `neorv32_cfs.h` | HW driver (stub)footnote:[This driver file only represents a stub, since the real CFS drivers are defined by the actual CFS implementation.] functions for the custom functions subsystem | `neorv32_cpu.c` | `neorv32_cpu.h` | HW driver functions for the NEORV32 **CPU** | `neorv32_gpio.c` | `neorv32_gpio.h` | HW driver functions for the **GPIO** @@ -441,8 +442,8 @@ BLDV: Mar 23 2021 HWV: 0x01050208 CLK: 0x05F5E100 MISA: 0x40901105 -ZEXT: 0x00000023 -PROC: 0x0EFF0037 +CPU: 0x00000023 +SOC: 0x0EFF0037 IMEM: 0x00004000 bytes @ 0x00000000 DMEM: 0x00002000 bytes @ 0x80000000 @@ -458,8 +459,8 @@ This start-up screen also gives some brief information about the bootloader and | `HWV` | Processor hardware version (from the `mimpid` CSR) in BCD format (example: `0x01040606` = v1.4.6.6). | `CLK` | Processor clock speed in Hz (via the SYSINFO module, from the _CLOCK_FREQUENCY_ generic). | `MISA` | CPU extensions (from the `misa` CSR). -| `ZEXT` | CPU sub-extensions (via the _SYSINFO_CPU_ register in the SYSINFO module) -| `PROC` | Processor configuration (via the _SYSINFO_FEATURES_ register in the SYSINFO module / from the IO_* and MEM_* configuration generics). +| `CPU` | CPU sub-extensions (via the `CPU` register in the SYSINFO module) +| `SOC` | Processor configuration (via the `SOC` register in the SYSINFO module / from the IO_* and MEM_* configuration generics). | `IMEM` | IMEM memory base address and size in byte (from the _MEM_INT_IMEM_SIZE_ generic). | `DMEM` | DMEM memory base address and size in byte (from the _MEM_INT_DMEM_SIZE_ generic). |======================= @@ -476,8 +477,8 @@ HWV: 0x01050208 CLK: 0x05F5E100 USER: 0x10000DE0 MISA: 0x40901105 -ZEXT: 0x00000023 -PROC: 0x0EFF0037 +CPU: 0x00000023 +SOC: 0x0EFF0037 IMEM: 0x00004000 bytes @ 0x00000000 DMEM: 0x00002000 bytes @ 0x80000000 From 0ac508d3519cdd965a22c3980578aea3aab37931 Mon Sep 17 00:00:00 2001 From: stnolting Date: Fri, 17 Sep 2021 18:48:25 +0200 Subject: [PATCH 7/9] [rtl/core] updated pre-built images default app (blink_led) and bootloader --- rtl/core/neorv32_application_image.vhd | 1390 ++++++++++++------------ rtl/core/neorv32_bootloader_image.vhd | 745 +++++++------ 2 files changed, 1081 insertions(+), 1054 deletions(-) diff --git a/rtl/core/neorv32_application_image.vhd b/rtl/core/neorv32_application_image.vhd index 191659b1b..85bea29f4 100644 --- a/rtl/core/neorv32_application_image.vhd +++ b/rtl/core/neorv32_application_image.vhd @@ -1,6 +1,6 @@ -- The NEORV32 RISC-V Processor, https://github.com/stnolting/neorv32 -- Auto-generated memory init file (for APPLICATION) from source file --- Size: 3196 bytes +-- Size: 3324 bytes library ieee; use ieee.std_logic_1164.all; @@ -67,7 +67,7 @@ package neorv32_application_image is 00000053 => x"00158593", 00000054 => x"ff5ff06f", 00000055 => x"00001597", - 00000056 => x"ba058593", + 00000056 => x"c2058593", 00000057 => x"80000617", 00000058 => x"f1c60613", 00000059 => x"80000697", @@ -113,17 +113,17 @@ package neorv32_application_image is 00000099 => x"00000593", 00000100 => x"b0050513", 00000101 => x"00112623", - 00000102 => x"118000ef", - 00000103 => x"694000ef", + 00000102 => x"5b8000ef", + 00000103 => x"628000ef", 00000104 => x"00050c63", - 00000105 => x"644000ef", + 00000105 => x"4c4000ef", 00000106 => x"00001537", - 00000107 => x"9d850513", - 00000108 => x"170000ef", + 00000107 => x"a5850513", + 00000108 => x"610000ef", 00000109 => x"020000ef", 00000110 => x"00001537", - 00000111 => x"9b450513", - 00000112 => x"160000ef", + 00000111 => x"a3450513", + 00000112 => x"600000ef", 00000113 => x"00c12083", 00000114 => x"00100513", 00000115 => x"01010113", @@ -133,683 +133,715 @@ package neorv32_application_image is 00000119 => x"00000593", 00000120 => x"00112623", 00000121 => x"00812423", - 00000122 => x"658000ef", + 00000122 => x"5ec000ef", 00000123 => x"00000513", 00000124 => x"00150413", 00000125 => x"00000593", 00000126 => x"0ff57513", - 00000127 => x"644000ef", + 00000127 => x"5d8000ef", 00000128 => x"0c800513", - 00000129 => x"120000ef", + 00000129 => x"60c000ef", 00000130 => x"00040513", 00000131 => x"fe5ff06f", - 00000132 => x"fe802503", - 00000133 => x"01255513", - 00000134 => x"00157513", - 00000135 => x"00008067", - 00000136 => x"fa002023", - 00000137 => x"fe002703", - 00000138 => x"00151513", - 00000139 => x"00000793", - 00000140 => x"04a77463", - 00000141 => x"000016b7", - 00000142 => x"00000713", - 00000143 => x"ffe68693", - 00000144 => x"04f6e663", - 00000145 => x"00367613", - 00000146 => x"0035f593", - 00000147 => x"fff78793", - 00000148 => x"01461613", - 00000149 => x"00c7e7b3", - 00000150 => x"01659593", - 00000151 => x"01871713", - 00000152 => x"00b7e7b3", - 00000153 => x"00e7e7b3", - 00000154 => x"10000737", - 00000155 => x"00e7e7b3", - 00000156 => x"faf02023", - 00000157 => x"00008067", - 00000158 => x"00178793", - 00000159 => x"01079793", - 00000160 => x"40a70733", - 00000161 => x"0107d793", - 00000162 => x"fa9ff06f", - 00000163 => x"ffe70513", - 00000164 => x"0fd57513", - 00000165 => x"00051a63", - 00000166 => x"0037d793", - 00000167 => x"00170713", - 00000168 => x"0ff77713", - 00000169 => x"f9dff06f", - 00000170 => x"0017d793", - 00000171 => x"ff1ff06f", - 00000172 => x"f71ff06f", - 00000173 => x"fa002783", - 00000174 => x"fe07cee3", - 00000175 => x"faa02223", - 00000176 => x"00008067", - 00000177 => x"ff1ff06f", - 00000178 => x"ff010113", - 00000179 => x"00812423", - 00000180 => x"01212023", - 00000181 => x"00112623", - 00000182 => x"00912223", - 00000183 => x"00050413", - 00000184 => x"00a00913", - 00000185 => x"00044483", - 00000186 => x"00140413", - 00000187 => x"00049e63", - 00000188 => x"00c12083", - 00000189 => x"00812403", - 00000190 => x"00412483", - 00000191 => x"00012903", - 00000192 => x"01010113", - 00000193 => x"00008067", - 00000194 => x"01249663", - 00000195 => x"00d00513", - 00000196 => x"fa5ff0ef", - 00000197 => x"00048513", - 00000198 => x"f9dff0ef", - 00000199 => x"fc9ff06f", - 00000200 => x"fa9ff06f", - 00000201 => x"fe010113", - 00000202 => x"00112e23", - 00000203 => x"00050613", - 00000204 => x"00055863", - 00000205 => x"40a00633", - 00000206 => x"01061613", - 00000207 => x"41065613", - 00000208 => x"fe002503", - 00000209 => x"3e800593", - 00000210 => x"00c12623", - 00000211 => x"5bc000ef", - 00000212 => x"00c12603", - 00000213 => x"00000593", - 00000214 => x"41f65693", - 00000215 => x"514000ef", - 00000216 => x"01c59593", - 00000217 => x"00455513", - 00000218 => x"00a5e533", - 00000219 => x"00050a63", - 00000220 => x"00050863", - 00000221 => x"fff50513", - 00000222 => x"00000013", - 00000223 => x"ff1ff06f", - 00000224 => x"01c12083", - 00000225 => x"02010113", - 00000226 => x"00008067", - 00000227 => x"00000000", - 00000228 => x"fc010113", - 00000229 => x"02112e23", - 00000230 => x"02512c23", - 00000231 => x"02612a23", - 00000232 => x"02712823", - 00000233 => x"02a12623", - 00000234 => x"02b12423", - 00000235 => x"02c12223", - 00000236 => x"02d12023", - 00000237 => x"00e12e23", - 00000238 => x"00f12c23", - 00000239 => x"01012a23", - 00000240 => x"01112823", - 00000241 => x"01c12623", - 00000242 => x"01d12423", - 00000243 => x"01e12223", - 00000244 => x"01f12023", - 00000245 => x"34102773", - 00000246 => x"34071073", - 00000247 => x"342027f3", - 00000248 => x"0807c863", - 00000249 => x"00071683", - 00000250 => x"00300593", - 00000251 => x"0036f693", - 00000252 => x"00270613", - 00000253 => x"00b69463", - 00000254 => x"00470613", - 00000255 => x"34161073", - 00000256 => x"00b00713", - 00000257 => x"04f77a63", - 00000258 => x"60800793", - 00000259 => x"000780e7", - 00000260 => x"03c12083", - 00000261 => x"03812283", - 00000262 => x"03412303", - 00000263 => x"03012383", - 00000264 => x"02c12503", - 00000265 => x"02812583", - 00000266 => x"02412603", - 00000267 => x"02012683", - 00000268 => x"01c12703", - 00000269 => x"01812783", - 00000270 => x"01412803", - 00000271 => x"01012883", - 00000272 => x"00c12e03", - 00000273 => x"00812e83", - 00000274 => x"00412f03", - 00000275 => x"00012f83", - 00000276 => x"04010113", - 00000277 => x"30200073", - 00000278 => x"00001737", - 00000279 => x"00279793", - 00000280 => x"9f470713", - 00000281 => x"00e787b3", - 00000282 => x"0007a783", - 00000283 => x"00078067", - 00000284 => x"80000737", - 00000285 => x"00e787b3", - 00000286 => x"01f00713", - 00000287 => x"f8f766e3", - 00000288 => x"00001737", - 00000289 => x"00279793", - 00000290 => x"a2470713", - 00000291 => x"00e787b3", - 00000292 => x"0007a783", - 00000293 => x"00078067", - 00000294 => x"800007b7", - 00000295 => x"0007a783", - 00000296 => x"f6dff06f", - 00000297 => x"800007b7", - 00000298 => x"0047a783", - 00000299 => x"f61ff06f", - 00000300 => x"800007b7", - 00000301 => x"0087a783", - 00000302 => x"f55ff06f", - 00000303 => x"800007b7", - 00000304 => x"00c7a783", - 00000305 => x"f49ff06f", - 00000306 => x"8101a783", - 00000307 => x"f41ff06f", - 00000308 => x"8141a783", - 00000309 => x"f39ff06f", - 00000310 => x"8181a783", - 00000311 => x"f31ff06f", - 00000312 => x"81c1a783", - 00000313 => x"f29ff06f", - 00000314 => x"8201a783", - 00000315 => x"f21ff06f", - 00000316 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x"73736563", + 00000760 => x"75616620", + 00000761 => x"0000746c", + 00000762 => x"69766e45", + 00000763 => x"6d6e6f72", + 00000764 => x"20746e65", + 00000765 => x"6c6c6163", + 00000766 => x"6f726620", + 00000767 => x"2d55206d", + 00000768 => x"65646f6d", + 00000769 => x"00000000", + 00000770 => x"69766e45", + 00000771 => x"6d6e6f72", + 00000772 => x"20746e65", + 00000773 => x"6c6c6163", + 00000774 => x"6f726620", + 00000775 => x"2d4d206d", + 00000776 => x"65646f6d", + 00000777 => x"00000000", + 00000778 => x"6863614d", + 00000779 => x"20656e69", + 00000780 => x"74666f73", + 00000781 => x"65726177", + 00000782 => x"746e6920", + 00000783 => x"75727265", + 00000784 => x"00007470", + 00000785 => x"6863614d", + 00000786 => x"20656e69", + 00000787 => x"656d6974", + 00000788 => x"6e692072", + 00000789 => x"72726574", + 00000790 => x"00747075", + 00000791 => x"6863614d", + 00000792 => x"20656e69", + 00000793 => x"65747865", + 00000794 => x"6c616e72", + 00000795 => x"746e6920", + 00000796 => x"75727265", + 00000797 => x"00007470", + 00000798 => x"74736146", + 00000799 => x"746e6920", + 00000800 => x"75727265", + 00000801 => x"00207470", + 00000802 => x"6e6b6e55", + 00000803 => x"206e776f", + 00000804 => x"70617274", + 00000805 => x"75616320", + 00000806 => x"203a6573", + 00000807 => x"00000000", + 00000808 => x"50204020", + 00000809 => x"00003d43", + 00000810 => x"544d202c", + 00000811 => x"3d4c4156", + 00000812 => x"00000000", + 00000813 => x"522f3c20", + 00000814 => x"003e4554", + 00000815 => x"00000544", + 00000816 => x"00000594", + 00000817 => x"000005a0", + 00000818 => x"000005ac", + 00000819 => x"000005b8", + 00000820 => x"000005c4", + 00000821 => x"000005d0", + 00000822 => x"000005dc", + 00000823 => x"000005e8", + 00000824 => x"00000504", + 00000825 => x"00000504", + 00000826 => x"000005f4", + 00000827 => x"33323130", + 00000828 => x"37363534", + 00000829 => x"42413938", + 00000830 => x"46454443" ); end neorv32_application_image; diff --git a/rtl/core/neorv32_bootloader_image.vhd b/rtl/core/neorv32_bootloader_image.vhd index dafafaaff..65abaa608 100644 --- a/rtl/core/neorv32_bootloader_image.vhd +++ b/rtl/core/neorv32_bootloader_image.vhd @@ -1,6 +1,6 @@ -- The NEORV32 RISC-V Processor, https://github.com/stnolting/neorv32 -- Auto-generated memory init file (for BOOTLOADER) from source file --- Size: 4068 bytes +-- Size: 4048 bytes library ieee; use ieee.std_logic_1164.all; @@ -51,7 +51,7 @@ package neorv32_bootloader_image is 00000037 => x"00158593", 00000038 => x"ff5ff06f", 00000039 => x"00001597", - 00000040 => x"f4858593", + 00000040 => x"f3458593", 00000041 => x"80010617", 00000042 => x"f5c60613", 00000043 => x"80010697", @@ -110,18 +110,18 @@ package neorv32_bootloader_image is 00000096 => x"00000613", 00000097 => x"00000593", 00000098 => x"00200513", - 00000099 => x"399000ef", - 00000100 => x"421000ef", + 00000099 => x"381000ef", + 00000100 => x"409000ef", 00000101 => x"00048493", 00000102 => x"00050863", 00000103 => x"00100513", 00000104 => x"00000593", - 00000105 => x"44d000ef", + 00000105 => x"435000ef", 00000106 => x"00005537", 00000107 => x"00000613", 00000108 => x"00000593", 00000109 => x"b0050513", - 00000110 => x"23d000ef", + 00000110 => x"225000ef", 00000111 => x"1bd000ef", 00000112 => x"02050a63", 00000113 => x"1c5000ef", @@ -137,61 +137,61 @@ package neorv32_bootloader_image is 00000123 => x"00000013", 00000124 => x"00000013", 00000125 => x"ffff1537", - 00000126 => x"f1450513", - 00000127 => x"2c1000ef", + 00000126 => x"f0050513", + 00000127 => x"2a9000ef", 00000128 => x"f1302573", 00000129 => x"244000ef", 00000130 => x"ffff1537", - 00000131 => x"f4c50513", - 00000132 => x"2ad000ef", + 00000131 => x"f3850513", + 00000132 => x"295000ef", 00000133 => x"fe002503", 00000134 => x"230000ef", 00000135 => x"ffff1537", - 00000136 => x"f5450513", - 00000137 => x"299000ef", + 00000136 => x"f4050513", + 00000137 => x"281000ef", 00000138 => x"30102573", 00000139 => x"21c000ef", 00000140 => x"ffff1537", - 00000141 => x"f5c50513", - 00000142 => x"285000ef", + 00000141 => x"f4850513", + 00000142 => x"26d000ef", 00000143 => x"fe402503", 00000144 => x"ffff1437", 00000145 => x"204000ef", 00000146 => x"ffff1537", - 00000147 => x"f6450513", - 00000148 => x"26d000ef", + 00000147 => x"f5050513", + 00000148 => x"255000ef", 00000149 => x"fe802503", 00000150 => x"1f0000ef", 00000151 => x"ffff1537", - 00000152 => x"f6c50513", - 00000153 => x"259000ef", + 00000152 => x"f5850513", + 00000153 => x"241000ef", 00000154 => x"ff802503", 00000155 => x"1dc000ef", - 00000156 => x"f7440513", - 00000157 => x"249000ef", + 00000156 => x"f6040513", + 00000157 => x"231000ef", 00000158 => x"ff002503", 00000159 => x"1cc000ef", 00000160 => x"ffff1537", - 00000161 => x"f8050513", - 00000162 => x"235000ef", + 00000161 => x"f6c50513", + 00000162 => x"21d000ef", 00000163 => x"ffc02503", 00000164 => x"1b8000ef", - 00000165 => x"f7440513", - 00000166 => x"225000ef", + 00000165 => x"f6040513", + 00000166 => x"20d000ef", 00000167 => x"ff402503", 00000168 => x"1a8000ef", 00000169 => x"0d5000ef", 00000170 => x"06050663", 00000171 => x"ffff1537", - 00000172 => x"f8850513", - 00000173 => x"209000ef", + 00000172 => x"f7450513", + 00000173 => x"1f1000ef", 00000174 => x"0d1000ef", 00000175 => x"fe002403", 00000176 => x"00341413", 00000177 => x"00a40933", 00000178 => x"00893433", 00000179 => x"00b40433", - 00000180 => x"115000ef", + 00000180 => x"0fd000ef", 00000181 => x"02051663", 00000182 => x"0b1000ef", 00000183 => x"fe85eae3", @@ -200,14 +200,14 @@ package neorv32_bootloader_image is 00000186 => x"00100513", 00000187 => x"4d4000ef", 00000188 => x"ffff1537", - 00000189 => x"fb050513", - 00000190 => x"1c5000ef", + 00000189 => x"f9c50513", + 00000190 => x"1ad000ef", 00000191 => x"0cc000ef", - 00000192 => x"1b1000ef", + 00000192 => x"199000ef", 00000193 => x"fc050ae3", 00000194 => x"ffff1537", - 00000195 => x"fb450513", - 00000196 => x"1ad000ef", + 00000195 => x"fa050513", + 00000196 => x"195000ef", 00000197 => x"0a8000ef", 00000198 => x"ffff19b7", 00000199 => x"ffff1a37", @@ -217,13 +217,13 @@ package neorv32_bootloader_image is 00000203 => x"07300c13", 00000204 => x"ffff1937", 00000205 => x"ffff1cb7", - 00000206 => x"fc098513", - 00000207 => x"181000ef", - 00000208 => x"161000ef", + 00000206 => x"fac98513", + 00000207 => x"169000ef", + 00000208 => x"149000ef", 00000209 => x"00050413", - 00000210 => x"13d000ef", - 00000211 => x"fb0a0513", - 00000212 => x"16d000ef", + 00000210 => x"125000ef", + 00000211 => x"f9ca0513", + 00000212 => x"155000ef", 00000213 => x"01541863", 00000214 => x"ffff02b7", 00000215 => x"00028067", @@ -245,23 +245,23 @@ package neorv32_bootloader_image is 00000231 => x"00f41c63", 00000232 => x"0004a783", 00000233 => x"f4079ce3", - 00000234 => x"ebcc8513", - 00000235 => x"111000ef", + 00000234 => x"ea8c8513", + 00000235 => x"0f9000ef", 00000236 => x"f89ff06f", - 00000237 => x"fc890513", + 00000237 => x"fb490513", 00000238 => x"ff5ff06f", 00000239 => x"ffff1537", - 00000240 => x"dfc50513", - 00000241 => x"0f90006f", + 00000240 => x"de850513", + 00000241 => x"0e10006f", 00000242 => x"ff010113", 00000243 => x"00112623", 00000244 => x"30047073", 00000245 => x"00000013", 00000246 => x"00000013", 00000247 => x"ffff1537", - 00000248 => x"e6050513", - 00000249 => x"0d9000ef", - 00000250 => x"0ad000ef", + 00000248 => x"e4c50513", + 00000249 => x"0c1000ef", + 00000250 => x"095000ef", 00000251 => x"fe051ee3", 00000252 => x"ff002783", 00000253 => x"00078067", @@ -270,41 +270,41 @@ package neorv32_bootloader_image is 00000256 => x"00812423", 00000257 => x"00050413", 00000258 => x"ffff1537", - 00000259 => x"e7050513", + 00000259 => x"e5c50513", 00000260 => x"00112623", - 00000261 => x"0a9000ef", + 00000261 => x"091000ef", 00000262 => x"03040513", 00000263 => x"0ff57513", - 00000264 => x"065000ef", + 00000264 => x"04d000ef", 00000265 => x"30047073", 00000266 => x"00000013", 00000267 => x"00000013", - 00000268 => x"181000ef", + 00000268 => x"169000ef", 00000269 => x"00050863", 00000270 => x"00100513", 00000271 => x"00000593", - 00000272 => x"1b1000ef", + 00000272 => x"199000ef", 00000273 => x"0000006f", 00000274 => x"fe010113", 00000275 => x"01212823", 00000276 => x"00050913", 00000277 => x"ffff1537", 00000278 => x"00912a23", - 00000279 => x"e7c50513", + 00000279 => x"e6850513", 00000280 => x"ffff14b7", 00000281 => x"00812c23", 00000282 => x"01312623", 00000283 => x"00112e23", 00000284 => x"01c00413", - 00000285 => x"049000ef", - 00000286 => x"fd448493", + 00000285 => x"031000ef", + 00000286 => x"fc048493", 00000287 => x"ffc00993", 00000288 => x"008957b3", 00000289 => x"00f7f793", 00000290 => x"00f487b3", 00000291 => x"0007c503", 00000292 => x"ffc40413", - 00000293 => x"7f0000ef", + 00000293 => x"7d8000ef", 00000294 => x"ff3414e3", 00000295 => x"01c12083", 00000296 => x"01812403", @@ -336,10 +336,10 @@ package neorv32_bootloader_image is 00000322 => x"800007b7", 00000323 => x"00778793", 00000324 => x"08f49463", - 00000325 => x"09d000ef", + 00000325 => x"085000ef", 00000326 => x"00050663", 00000327 => x"00000513", - 00000328 => x"0a1000ef", + 00000328 => x"089000ef", 00000329 => x"654000ef", 00000330 => x"02050063", 00000331 => x"65c000ef", @@ -376,24 +376,24 @@ package neorv32_bootloader_image is 00000362 => x"00100513", 00000363 => x"e51ff0ef", 00000364 => x"34102473", - 00000365 => x"630000ef", + 00000365 => x"618000ef", 00000366 => x"04050263", 00000367 => x"ffff1537", - 00000368 => x"e8050513", - 00000369 => x"6f8000ef", + 00000368 => x"e6c50513", + 00000369 => x"6e0000ef", 00000370 => x"00048513", 00000371 => x"e7dff0ef", 00000372 => x"02000513", - 00000373 => x"6b0000ef", + 00000373 => x"698000ef", 00000374 => x"00040513", 00000375 => x"e6dff0ef", 00000376 => x"02000513", - 00000377 => x"6a0000ef", + 00000377 => x"688000ef", 00000378 => x"34302573", 00000379 => x"e5dff0ef", 00000380 => x"ffff1537", - 00000381 => x"e8850513", - 00000382 => x"6c4000ef", + 00000381 => x"e7450513", + 00000382 => x"6ac000ef", 00000383 => x"00440413", 00000384 => x"34141073", 00000385 => x"f45ff06f", @@ -401,14 +401,14 @@ package neorv32_bootloader_image is 00000387 => x"00000513", 00000388 => x"00112623", 00000389 => x"00812423", - 00000390 => x"740000ef", + 00000390 => x"728000ef", 00000391 => x"09e00513", - 00000392 => x"77c000ef", + 00000392 => x"764000ef", 00000393 => x"00000513", - 00000394 => x"774000ef", + 00000394 => x"75c000ef", 00000395 => x"00050413", 00000396 => x"00000513", - 00000397 => x"744000ef", + 00000397 => x"72c000ef", 00000398 => x"00c12083", 00000399 => x"0ff47513", 00000400 => x"00812403", @@ -418,15 +418,15 @@ package neorv32_bootloader_image is 00000404 => x"00112623", 00000405 => x"00812423", 00000406 => x"00000513", - 00000407 => x"6fc000ef", + 00000407 => x"6e4000ef", 00000408 => x"00500513", - 00000409 => x"738000ef", + 00000409 => x"720000ef", 00000410 => x"00000513", - 00000411 => x"730000ef", + 00000411 => x"718000ef", 00000412 => x"00050413", 00000413 => x"00147413", 00000414 => x"00000513", - 00000415 => x"6fc000ef", + 00000415 => x"6e4000ef", 00000416 => x"fc041ce3", 00000417 => x"00c12083", 00000418 => x"00812403", @@ -435,43 +435,43 @@ package neorv32_bootloader_image is 00000421 => x"ff010113", 00000422 => x"00000513", 00000423 => x"00112623", - 00000424 => x"6b8000ef", + 00000424 => x"6a0000ef", 00000425 => x"00600513", - 00000426 => x"6f4000ef", + 00000426 => x"6dc000ef", 00000427 => x"00c12083", 00000428 => x"00000513", 00000429 => x"01010113", - 00000430 => x"6c00006f", + 00000430 => x"6a80006f", 00000431 => x"ff010113", 00000432 => x"00812423", 00000433 => x"00050413", 00000434 => x"01055513", 00000435 => x"0ff57513", 00000436 => x"00112623", - 00000437 => x"6c8000ef", + 00000437 => x"6b0000ef", 00000438 => x"00845513", 00000439 => x"0ff57513", - 00000440 => x"6bc000ef", + 00000440 => x"6a4000ef", 00000441 => x"0ff47513", 00000442 => x"00812403", 00000443 => x"00c12083", 00000444 => x"01010113", - 00000445 => x"6a80006f", + 00000445 => x"6900006f", 00000446 => x"ff010113", 00000447 => x"00812423", 00000448 => x"00050413", 00000449 => x"00000513", 00000450 => x"00112623", - 00000451 => x"64c000ef", + 00000451 => x"634000ef", 00000452 => x"00300513", - 00000453 => x"688000ef", + 00000453 => x"670000ef", 00000454 => x"00040513", 00000455 => x"fa1ff0ef", 00000456 => x"00000513", - 00000457 => x"678000ef", + 00000457 => x"660000ef", 00000458 => x"00050413", 00000459 => x"00000513", - 00000460 => x"648000ef", + 00000460 => x"630000ef", 00000461 => x"00c12083", 00000462 => x"0ff47513", 00000463 => x"00812403", @@ -490,7 +490,7 @@ package neorv32_bootloader_image is 00000476 => x"00000413", 00000477 => x"00400a13", 00000478 => x"02091e63", - 00000479 => x"524000ef", + 00000479 => x"50c000ef", 00000480 => x"00a48023", 00000481 => x"00140413", 00000482 => x"00148493", @@ -525,8 +525,8 @@ package neorv32_bootloader_image is 00000511 => x"80418a13", 00000512 => x"02051863", 00000513 => x"ffff1537", - 00000514 => x"e8c50513", - 00000515 => x"4b0000ef", + 00000514 => x"e7850513", + 00000515 => x"498000ef", 00000516 => x"080005b7", 00000517 => x"00040513", 00000518 => x"f31ff0ef", @@ -536,9 +536,9 @@ package neorv32_bootloader_image is 00000522 => x"00000513", 00000523 => x"01c0006f", 00000524 => x"ffff1537", - 00000525 => x"eac50513", - 00000526 => x"484000ef", - 00000527 => x"4d8000ef", + 00000525 => x"e9850513", + 00000526 => x"46c000ef", + 00000527 => x"4c0000ef", 00000528 => x"00051663", 00000529 => x"00300513", 00000530 => x"bb5ff0ef", @@ -565,8 +565,8 @@ package neorv32_bootloader_image is 00000551 => x"00200513", 00000552 => x"fa0494e3", 00000553 => x"ffff1537", - 00000554 => x"eb850513", - 00000555 => x"410000ef", + 00000554 => x"ea450513", + 00000555 => x"3f8000ef", 00000556 => x"02c12083", 00000557 => x"02812403", 00000558 => x"800007b7", @@ -597,15 +597,15 @@ package neorv32_bootloader_image is 00000583 => x"00050493", 00000584 => x"d75ff0ef", 00000585 => x"00000513", - 00000586 => x"430000ef", + 00000586 => x"418000ef", 00000587 => x"00200513", - 00000588 => x"46c000ef", + 00000588 => x"454000ef", 00000589 => x"00048513", 00000590 => x"d85ff0ef", 00000591 => x"00040513", - 00000592 => x"45c000ef", + 00000592 => x"444000ef", 00000593 => x"00000513", - 00000594 => x"430000ef", + 00000594 => x"418000ef", 00000595 => x"00812403", 00000596 => x"00c12083", 00000597 => x"00412483", @@ -639,13 +639,13 @@ package neorv32_bootloader_image is 00000625 => x"00050413", 00000626 => x"ccdff0ef", 00000627 => x"00000513", - 00000628 => x"388000ef", + 00000628 => x"370000ef", 00000629 => x"0d800513", - 00000630 => x"3c4000ef", + 00000630 => x"3ac000ef", 00000631 => x"00040513", 00000632 => x"cddff0ef", 00000633 => x"00000513", - 00000634 => x"390000ef", + 00000634 => x"378000ef", 00000635 => x"00812403", 00000636 => x"00c12083", 00000637 => x"01010113", @@ -662,7 +662,7 @@ package neorv32_bootloader_image is 00000648 => x"01512223", 00000649 => x"02041863", 00000650 => x"ffff1537", - 00000651 => x"ebc50513", + 00000651 => x"ea850513", 00000652 => x"01812403", 00000653 => x"01c12083", 00000654 => x"01412483", @@ -671,23 +671,23 @@ package neorv32_bootloader_image is 00000657 => x"00812a03", 00000658 => x"00412a83", 00000659 => x"02010113", - 00000660 => x"26c0006f", + 00000660 => x"2540006f", 00000661 => x"ffff1537", - 00000662 => x"ed850513", - 00000663 => x"260000ef", + 00000662 => x"ec450513", + 00000663 => x"248000ef", 00000664 => x"00040513", 00000665 => x"9e5ff0ef", 00000666 => x"ffff1537", - 00000667 => x"ee050513", - 00000668 => x"24c000ef", + 00000667 => x"ecc50513", + 00000668 => x"234000ef", 00000669 => x"08000537", 00000670 => x"9d1ff0ef", 00000671 => x"ffff1537", - 00000672 => x"ef850513", - 00000673 => x"238000ef", - 00000674 => x"218000ef", + 00000672 => x"ee450513", + 00000673 => x"220000ef", + 00000674 => x"200000ef", 00000675 => x"00050493", - 00000676 => x"1f4000ef", + 00000676 => x"1dc000ef", 00000677 => x"07900793", 00000678 => x"0af49e63", 00000679 => x"b6dff0ef", @@ -695,9 +695,9 @@ package neorv32_bootloader_image is 00000681 => x"00300513", 00000682 => x"955ff0ef", 00000683 => x"ffff1537", - 00000684 => x"f0450513", + 00000684 => x"ef050513", 00000685 => x"01045493", - 00000686 => x"204000ef", + 00000686 => x"1ec000ef", 00000687 => x"00148493", 00000688 => x"08000937", 00000689 => x"fff00993", @@ -725,7 +725,7 @@ package neorv32_bootloader_image is 00000711 => x"412005b3", 00000712 => x"e41ff0ef", 00000713 => x"ffff1537", - 00000714 => x"eb850513", + 00000714 => x"ea450513", 00000715 => x"f05ff06f", 00000716 => x"00090513", 00000717 => x"e85ff0ef", @@ -760,274 +760,269 @@ package neorv32_bootloader_image is 00000746 => x"00412583", 00000747 => x"01010113", 00000748 => x"00008067", - 00000749 => x"ff010113", - 00000750 => x"00a12023", - 00000751 => x"00b12223", - 00000752 => x"f9800793", - 00000753 => x"fff00713", - 00000754 => x"00e7a023", - 00000755 => x"00412703", - 00000756 => x"f8e02e23", - 00000757 => x"00012703", - 00000758 => x"00e7a023", - 00000759 => x"01010113", - 00000760 => x"00008067", - 00000761 => x"fe802503", - 00000762 => x"01255513", - 00000763 => x"00157513", - 00000764 => x"00008067", - 00000765 => x"fa002023", - 00000766 => x"fe002703", - 00000767 => x"00151513", - 00000768 => x"00000793", - 00000769 => x"04a77463", - 00000770 => x"000016b7", - 00000771 => x"00000713", - 00000772 => x"ffe68693", - 00000773 => x"04f6e663", - 00000774 => x"00367613", - 00000775 => x"0035f593", - 00000776 => x"fff78793", - 00000777 => x"01461613", - 00000778 => x"00c7e7b3", - 00000779 => x"01659593", - 00000780 => x"01871713", - 00000781 => x"00b7e7b3", - 00000782 => x"00e7e7b3", - 00000783 => x"10000737", - 00000784 => x"00e7e7b3", - 00000785 => x"faf02023", - 00000786 => x"00008067", - 00000787 => x"00178793", - 00000788 => x"01079793", - 00000789 => x"40a70733", - 00000790 => x"0107d793", - 00000791 => x"fa9ff06f", - 00000792 => x"ffe70513", - 00000793 => x"0fd57513", - 00000794 => x"00051a63", - 00000795 => x"0037d793", - 00000796 => x"00170713", - 00000797 => x"0ff77713", - 00000798 => x"f9dff06f", - 00000799 => x"0017d793", - 00000800 => x"ff1ff06f", - 00000801 => x"fa002783", - 00000802 => x"fe07cee3", - 00000803 => x"faa02223", - 00000804 => x"00008067", - 00000805 => x"fa002503", - 00000806 => x"01f55513", - 00000807 => x"00008067", - 00000808 => x"fa402503", - 00000809 => x"fe055ee3", - 00000810 => x"0ff57513", - 00000811 => x"00008067", - 00000812 => x"fa402503", - 00000813 => x"01f55513", - 00000814 => x"00008067", - 00000815 => x"ff010113", - 00000816 => x"00812423", - 00000817 => x"01212023", - 00000818 => x"00112623", - 00000819 => x"00912223", - 00000820 => x"00050413", - 00000821 => x"00a00913", - 00000822 => x"00044483", - 00000823 => x"00140413", - 00000824 => x"00049e63", - 00000825 => x"00c12083", - 00000826 => x"00812403", - 00000827 => x"00412483", - 00000828 => x"00012903", - 00000829 => x"01010113", - 00000830 => x"00008067", - 00000831 => x"01249663", - 00000832 => x"00d00513", - 00000833 => x"f81ff0ef", - 00000834 => x"00048513", - 00000835 => x"f79ff0ef", - 00000836 => x"fc9ff06f", - 00000837 => x"fe802503", - 00000838 => x"01355513", - 00000839 => x"00157513", - 00000840 => x"00008067", - 00000841 => x"00757513", - 00000842 => x"00367613", - 00000843 => x"0015f593", - 00000844 => x"00a51513", - 00000845 => x"00d61613", - 00000846 => x"00c56533", - 00000847 => x"00959593", - 00000848 => x"fa800793", - 00000849 => x"00b56533", - 00000850 => x"0007a023", - 00000851 => x"10056513", - 00000852 => x"00a7a023", - 00000853 => x"00008067", - 00000854 => x"fa800713", - 00000855 => x"00072683", - 00000856 => x"00757793", - 00000857 => x"00100513", - 00000858 => x"00f51533", - 00000859 => x"00d56533", - 00000860 => x"00a72023", - 00000861 => x"00008067", - 00000862 => x"fa800713", - 00000863 => x"00072683", - 00000864 => x"00757513", - 00000865 => x"00100793", - 00000866 => x"00a797b3", - 00000867 => x"fff7c793", - 00000868 => x"00d7f7b3", - 00000869 => x"00f72023", - 00000870 => x"00008067", - 00000871 => x"faa02623", - 00000872 => x"fa802783", - 00000873 => x"fe07cee3", - 00000874 => x"fac02503", - 00000875 => x"00008067", - 00000876 => x"fe802503", - 00000877 => x"01055513", - 00000878 => x"00157513", - 00000879 => x"00008067", - 00000880 => x"00100793", - 00000881 => x"01f00713", - 00000882 => x"00a797b3", - 00000883 => x"00a74a63", - 00000884 => x"fc802703", - 00000885 => x"00f747b3", - 00000886 => x"fcf02423", - 00000887 => x"00008067", - 00000888 => x"fcc02703", - 00000889 => x"00f747b3", - 00000890 => x"fcf02623", - 00000891 => x"00008067", - 00000892 => x"fca02423", - 00000893 => x"fcb02623", - 00000894 => x"00008067", - 00000895 => x"69617641", - 00000896 => x"6c62616c", - 00000897 => x"4d432065", - 00000898 => x"0a3a7344", - 00000899 => x"203a6820", - 00000900 => x"706c6548", - 00000901 => x"3a72200a", - 00000902 => x"73655220", - 00000903 => x"74726174", - 00000904 => x"3a75200a", - 00000905 => x"6c705520", - 00000906 => x"0a64616f", - 00000907 => x"203a7320", - 00000908 => x"726f7453", - 00000909 => x"6f742065", + 00000749 => x"f9000793", + 00000750 => x"fff00713", + 00000751 => x"00e7a423", + 00000752 => x"00b7a623", + 00000753 => x"00a7a423", + 00000754 => x"00008067", + 00000755 => x"fe802503", + 00000756 => x"01255513", + 00000757 => x"00157513", + 00000758 => x"00008067", + 00000759 => x"fa002023", + 00000760 => x"fe002703", + 00000761 => x"00151513", + 00000762 => x"00000793", + 00000763 => x"04a77463", + 00000764 => x"000016b7", + 00000765 => x"00000713", + 00000766 => x"ffe68693", + 00000767 => x"04f6e663", + 00000768 => x"00367613", + 00000769 => x"0035f593", + 00000770 => x"fff78793", + 00000771 => x"01461613", + 00000772 => x"00c7e7b3", + 00000773 => x"01659593", + 00000774 => x"01871713", + 00000775 => x"00b7e7b3", + 00000776 => x"00e7e7b3", + 00000777 => x"10000737", + 00000778 => x"00e7e7b3", + 00000779 => x"faf02023", + 00000780 => x"00008067", + 00000781 => x"00178793", + 00000782 => x"01079793", + 00000783 => x"40a70733", + 00000784 => x"0107d793", + 00000785 => x"fa9ff06f", + 00000786 => x"ffe70513", + 00000787 => x"0fd57513", + 00000788 => x"00051a63", + 00000789 => x"0037d793", + 00000790 => x"00170713", + 00000791 => x"0ff77713", + 00000792 => x"f9dff06f", + 00000793 => x"0017d793", + 00000794 => x"ff1ff06f", + 00000795 => x"fa002783", + 00000796 => x"fe07cee3", + 00000797 => x"faa02223", + 00000798 => x"00008067", + 00000799 => x"fa002503", + 00000800 => x"01f55513", + 00000801 => x"00008067", + 00000802 => x"fa402503", + 00000803 => x"fe055ee3", + 00000804 => x"0ff57513", + 00000805 => x"00008067", + 00000806 => x"fa402503", + 00000807 => x"01f55513", + 00000808 => x"00008067", + 00000809 => x"ff010113", + 00000810 => x"00812423", + 00000811 => x"01212023", + 00000812 => x"00112623", + 00000813 => x"00912223", + 00000814 => x"00050413", + 00000815 => x"00a00913", + 00000816 => x"00044483", + 00000817 => x"00140413", + 00000818 => x"00049e63", + 00000819 => x"00c12083", + 00000820 => x"00812403", + 00000821 => x"00412483", + 00000822 => x"00012903", + 00000823 => x"01010113", + 00000824 => x"00008067", + 00000825 => x"01249663", + 00000826 => x"00d00513", + 00000827 => x"f81ff0ef", + 00000828 => x"00048513", + 00000829 => x"f79ff0ef", + 00000830 => x"fc9ff06f", + 00000831 => x"fe802503", + 00000832 => x"01355513", + 00000833 => x"00157513", + 00000834 => x"00008067", + 00000835 => x"00757513", + 00000836 => x"00367613", + 00000837 => x"0015f593", + 00000838 => x"00a51513", + 00000839 => x"00d61613", + 00000840 => x"00c56533", + 00000841 => x"00959593", + 00000842 => x"fa800793", + 00000843 => x"00b56533", + 00000844 => x"0007a023", + 00000845 => x"10056513", + 00000846 => x"00a7a023", + 00000847 => x"00008067", + 00000848 => x"fa800713", + 00000849 => x"00072683", + 00000850 => x"00757793", + 00000851 => x"00100513", + 00000852 => x"00f51533", + 00000853 => x"00d56533", + 00000854 => x"00a72023", + 00000855 => x"00008067", + 00000856 => x"fa800713", + 00000857 => x"00072683", + 00000858 => x"00757513", + 00000859 => x"00100793", + 00000860 => x"00a797b3", + 00000861 => x"fff7c793", + 00000862 => x"00d7f7b3", + 00000863 => x"00f72023", + 00000864 => x"00008067", + 00000865 => x"faa02623", + 00000866 => x"fa802783", + 00000867 => x"fe07cee3", + 00000868 => x"fac02503", + 00000869 => x"00008067", + 00000870 => x"fe802503", + 00000871 => x"01055513", + 00000872 => x"00157513", + 00000873 => x"00008067", + 00000874 => x"00100793", + 00000875 => x"01f00713", + 00000876 => x"00a797b3", + 00000877 => x"00a74a63", + 00000878 => x"fc802703", + 00000879 => x"00f747b3", + 00000880 => x"fcf02423", + 00000881 => x"00008067", + 00000882 => x"fcc02703", + 00000883 => x"00f747b3", + 00000884 => x"fcf02623", + 00000885 => x"00008067", + 00000886 => x"fc000793", + 00000887 => x"00a7a423", + 00000888 => x"00b7a623", + 00000889 => x"00008067", + 00000890 => x"69617641", + 00000891 => x"6c62616c", + 00000892 => x"4d432065", + 00000893 => x"0a3a7344", + 00000894 => x"203a6820", + 00000895 => x"706c6548", + 00000896 => x"3a72200a", + 00000897 => x"73655220", + 00000898 => x"74726174", + 00000899 => x"3a75200a", + 00000900 => x"6c705520", + 00000901 => x"0a64616f", + 00000902 => x"203a7320", + 00000903 => x"726f7453", + 00000904 => x"6f742065", + 00000905 => x"616c6620", + 00000906 => x"200a6873", + 00000907 => x"4c203a6c", + 00000908 => x"2064616f", + 00000909 => x"6d6f7266", 00000910 => x"616c6620", 00000911 => x"200a6873", - 00000912 => x"4c203a6c", - 00000913 => x"2064616f", - 00000914 => x"6d6f7266", - 00000915 => x"616c6620", - 00000916 => x"200a6873", - 00000917 => x"45203a65", - 00000918 => x"75636578", - 00000919 => x"00006574", - 00000920 => x"746f6f42", - 00000921 => x"2e676e69", - 00000922 => x"0a0a2e2e", - 00000923 => x"00000000", - 00000924 => x"52450a07", - 00000925 => x"5f524f52", - 00000926 => x"00000000", - 00000927 => x"00007830", - 00000928 => x"58455b0a", - 00000929 => x"00002043", - 00000930 => x"00000a5d", - 00000931 => x"69617741", - 00000932 => x"676e6974", - 00000933 => x"6f656e20", - 00000934 => x"32337672", - 00000935 => x"6578655f", - 00000936 => x"6e69622e", - 00000937 => x"202e2e2e", - 00000938 => x"00000000", - 00000939 => x"64616f4c", - 00000940 => x"2e676e69", - 00000941 => x"00202e2e", - 00000942 => x"00004b4f", - 00000943 => x"65206f4e", - 00000944 => x"75636578", - 00000945 => x"6c626174", - 00000946 => x"76612065", - 00000947 => x"616c6961", - 00000948 => x"2e656c62", - 00000949 => x"00000000", - 00000950 => x"74697257", - 00000951 => x"00002065", - 00000952 => x"74796220", - 00000953 => x"74207365", - 00000954 => x"5053206f", - 00000955 => x"6c662049", - 00000956 => x"20687361", - 00000957 => x"00002040", - 00000958 => x"7928203f", - 00000959 => x"20296e2f", - 00000960 => x"00000000", - 00000961 => x"616c460a", - 00000962 => x"6e696873", - 00000963 => x"2e2e2e67", - 00000964 => x"00000020", - 00000965 => x"3c0a0a0a", - 00000966 => x"454e203c", - 00000967 => x"3356524f", - 00000968 => x"6f422032", - 00000969 => x"6f6c746f", - 00000970 => x"72656461", - 00000971 => x"0a3e3e20", - 00000972 => x"444c420a", - 00000973 => x"41203a56", - 00000974 => x"31206775", - 00000975 => x"30322039", - 00000976 => x"480a3132", - 00000977 => x"203a5657", - 00000978 => x"00000020", - 00000979 => x"4b4c430a", - 00000980 => x"0020203a", - 00000981 => x"53494d0a", - 00000982 => x"00203a41", - 00000983 => x"58455a0a", - 00000984 => x"00203a54", - 00000985 => x"4f52500a", - 00000986 => x"00203a43", - 00000987 => x"454d490a", + 00000912 => x"45203a65", + 00000913 => x"75636578", + 00000914 => x"00006574", + 00000915 => x"746f6f42", + 00000916 => x"2e676e69", + 00000917 => x"0a0a2e2e", + 00000918 => x"00000000", + 00000919 => x"52450a07", + 00000920 => x"5f524f52", + 00000921 => x"00000000", + 00000922 => x"00007830", + 00000923 => x"58455b0a", + 00000924 => x"00002043", + 00000925 => x"00000a5d", + 00000926 => x"69617741", + 00000927 => x"676e6974", + 00000928 => x"6f656e20", + 00000929 => x"32337672", + 00000930 => x"6578655f", + 00000931 => x"6e69622e", + 00000932 => x"202e2e2e", + 00000933 => x"00000000", + 00000934 => x"64616f4c", + 00000935 => x"2e676e69", + 00000936 => x"00202e2e", + 00000937 => x"00004b4f", + 00000938 => x"65206f4e", + 00000939 => x"75636578", + 00000940 => x"6c626174", + 00000941 => x"76612065", + 00000942 => x"616c6961", + 00000943 => x"2e656c62", + 00000944 => x"00000000", + 00000945 => x"74697257", + 00000946 => x"00002065", + 00000947 => x"74796220", + 00000948 => x"74207365", + 00000949 => x"5053206f", + 00000950 => x"6c662049", + 00000951 => x"20687361", + 00000952 => x"00002040", + 00000953 => x"7928203f", + 00000954 => x"20296e2f", + 00000955 => x"00000000", + 00000956 => x"616c460a", + 00000957 => x"6e696873", + 00000958 => x"2e2e2e67", + 00000959 => x"00000020", + 00000960 => x"3c0a0a0a", + 00000961 => x"454e203c", + 00000962 => x"3356524f", + 00000963 => x"6f422032", + 00000964 => x"6f6c746f", + 00000965 => x"72656461", + 00000966 => x"0a3e3e20", + 00000967 => x"444c420a", + 00000968 => x"53203a56", + 00000969 => x"31207065", + 00000970 => x"30322037", + 00000971 => x"480a3132", + 00000972 => x"203a5657", + 00000973 => x"00000020", + 00000974 => x"4b4c430a", + 00000975 => x"0020203a", + 00000976 => x"53494d0a", + 00000977 => x"00203a41", + 00000978 => x"5550430a", + 00000979 => x"00203a20", + 00000980 => x"434f530a", + 00000981 => x"00203a20", + 00000982 => x"454d490a", + 00000983 => x"00203a4d", + 00000984 => x"74796220", + 00000985 => x"40207365", + 00000986 => x"00000000", + 00000987 => x"454d440a", 00000988 => x"00203a4d", - 00000989 => x"74796220", - 00000990 => x"40207365", - 00000991 => x"00000000", - 00000992 => x"454d440a", - 00000993 => x"00203a4d", - 00000994 => x"75410a0a", - 00000995 => x"6f626f74", - 00000996 => x"6920746f", - 00000997 => x"7338206e", - 00000998 => x"7250202e", - 00000999 => x"20737365", - 00001000 => x"2079656b", - 00001001 => x"61206f74", - 00001002 => x"74726f62", - 00001003 => x"00000a2e", - 00001004 => x"0000000a", - 00001005 => x"726f6241", - 00001006 => x"2e646574", - 00001007 => x"00000a0a", - 00001008 => x"444d430a", - 00001009 => x"00203e3a", - 00001010 => x"61766e49", - 00001011 => x"2064696c", - 00001012 => x"00444d43", - 00001013 => x"33323130", - 00001014 => x"37363534", - 00001015 => x"62613938", - 00001016 => x"66656463" + 00000989 => x"75410a0a", + 00000990 => x"6f626f74", + 00000991 => x"6920746f", + 00000992 => x"7338206e", + 00000993 => x"7250202e", + 00000994 => x"20737365", + 00000995 => x"2079656b", + 00000996 => x"61206f74", + 00000997 => x"74726f62", + 00000998 => x"00000a2e", + 00000999 => x"0000000a", + 00001000 => x"726f6241", + 00001001 => x"2e646574", + 00001002 => x"00000a0a", + 00001003 => x"444d430a", + 00001004 => x"00203e3a", + 00001005 => x"61766e49", + 00001006 => x"2064696c", + 00001007 => x"00444d43", + 00001008 => x"33323130", + 00001009 => x"37363534", + 00001010 => x"62613938", + 00001011 => x"66656463" ); end neorv32_bootloader_image; From d9ad214a125f3bf0c6ccdae54db0f58b43fac02d Mon Sep 17 00:00:00 2001 From: stnolting Date: Sat, 18 Sep 2021 22:50:23 +0200 Subject: [PATCH 8/9] [sw] added deprecated control register defines --- sw/lib/include/neorv32_legacy.h | 160 ++++++++++++++++++++++++++++++++ 1 file changed, 160 insertions(+) diff --git a/sw/lib/include/neorv32_legacy.h b/sw/lib/include/neorv32_legacy.h index 168e8c834..250c1e1e1 100644 --- a/sw/lib/include/neorv32_legacy.h +++ b/sw/lib/include/neorv32_legacy.h @@ -220,6 +220,166 @@ enum NEORV32_SYSINFO_FEATURES_enum { SYSINFO_FEATURES_IO_XIRQ = 28 }; +/** PWM control register bits */ +enum NEORV32_PWM_CT_enum { + PWM_CT_EN = 0, /**< PWM control register(0) (r/w): PWM controller enable */ + PWM_CT_PRSC0 = 1, /**< PWM control register(1) (r/w): Clock prescaler select bit 0 */ + PWM_CT_PRSC1 = 2, /**< PWM control register(2) (r/w): Clock prescaler select bit 1 */ + PWM_CT_PRSC2 = 3 /**< PWM control register(3) (r/w): Clock prescaler select bit 2 */ +}; + +/** SLINK control register bits */ +enum NEORV32_SLINK_CT_enum { + SLINK_CT_RX_NUM0 = 0, /**< SLINK control register(0) (r/-): number of implemented RX links bit 0 */ + SLINK_CT_RX_NUM1 = 1, /**< SLINK control register(1) (r/-): number of implemented RX links bit 1 */ + SLINK_CT_RX_NUM2 = 2, /**< SLINK control register(2) (r/-): number of implemented RX links bit 2 */ + SLINK_CT_RX_NUM3 = 3, /**< SLINK control register(3) (r/-): number of implemented RX links bit 3 */ + + SLINK_CT_TX_NUM0 = 4, /**< SLINK control register(4) (r/-): number of implemented TX links bit 0 */ + SLINK_CT_TX_NUM1 = 5, /**< SLINK control register(5) (r/-): number of implemented TX links bit 1 */ + SLINK_CT_TX_NUM2 = 6, /**< SLINK control register(6) (r/-): number of implemented TX links bit 2 */ + SLINK_CT_TX_NUM3 = 7, /**< SLINK control register(7) (r/-): number of implemented TX links bit 3 */ + + SLINK_CT_RX_FIFO_S0 = 8, /**< SLINK control register( 8) (r/-): log2(RX FIFO size) bit 0 */ + SLINK_CT_RX_FIFO_S1 = 9, /**< SLINK control register( 9) (r/-): log2(RX FIFO size) bit 1 */ + SLINK_CT_RX_FIFO_S2 = 10, /**< SLINK control register(10) (r/-): log2(RX FIFO size) bit 2 */ + SLINK_CT_RX_FIFO_S3 = 11, /**< SLINK control register(11) (r/-): log2(RX FIFO size) bit 3 */ + + SLINK_CT_TX_FIFO_S0 = 12, /**< SLINK control register(12) (r/-): log2(TX FIFO size) bit 0 */ + SLINK_CT_TX_FIFO_S1 = 13, /**< SLINK control register(13) (r/-): log2(TX FIFO size) bit 1 */ + SLINK_CT_TX_FIFO_S2 = 14, /**< SLINK control register(14) (r/-): log2(TX FIFO size) bit 2 */ + SLINK_CT_TX_FIFO_S3 = 15, /**< SLINK control register(15) (r/-): log2(TX FIFO size) bit 3 */ + + SLINK_CT_EN = 31, /**< SLINK control register(0) (r/w): SLINK controller enable */ +}; + +/** UART0/UART1 control register bits */ +enum NEORV32_UART_CT_enum { + UART_CT_BAUD00 = 0, /**< UART control register(0) (r/w): BAUD rate config value lsb (12-bit, bit 0) */ + UART_CT_BAUD01 = 1, /**< UART control register(1) (r/w): BAUD rate config value (12-bit, bit 1) */ + UART_CT_BAUD02 = 2, /**< UART control register(2) (r/w): BAUD rate config value (12-bit, bit 2) */ + UART_CT_BAUD03 = 3, /**< UART control register(3) (r/w): BAUD rate config value (12-bit, bit 3) */ + UART_CT_BAUD04 = 4, /**< UART control register(4) (r/w): BAUD rate config value (12-bit, bit 4) */ + UART_CT_BAUD05 = 5, /**< UART control register(5) (r/w): BAUD rate config value (12-bit, bit 4) */ + UART_CT_BAUD06 = 6, /**< UART control register(6) (r/w): BAUD rate config value (12-bit, bit 5) */ + UART_CT_BAUD07 = 7, /**< UART control register(7) (r/w): BAUD rate config value (12-bit, bit 6) */ + UART_CT_BAUD08 = 8, /**< UART control register(8) (r/w): BAUD rate config value (12-bit, bit 7) */ + UART_CT_BAUD09 = 9, /**< UART control register(9) (r/w): BAUD rate config value (12-bit, bit 8) */ + UART_CT_BAUD10 = 10, /**< UART control register(10) (r/w): BAUD rate config value (12-bit, bit 9) */ + UART_CT_BAUD11 = 11, /**< UART control register(11) (r/w): BAUD rate config value msb (12-bit, bit 0) */ + UART_CT_SIM_MODE = 12, /**< UART control register(12) (r/w): Simulation output override enable, for use in simulation only */ + + UART_CT_RTS_EN = 20, /**< UART control register(20) (r/w): Enable hardware flow control: Assert RTS output if UART.RX is ready to receive */ + UART_CT_CTS_EN = 21, /**< UART control register(21) (r/w): Enable hardware flow control: UART.TX starts sending only if CTS input is asserted */ + UART_CT_PMODE0 = 22, /**< UART control register(22) (r/w): Parity configuration (0=even; 1=odd) */ + UART_CT_PMODE1 = 23, /**< UART control register(23) (r/w): Parity bit enabled when set */ + UART_CT_PRSC0 = 24, /**< UART control register(24) (r/w): BAUD rate clock prescaler select bit 0 */ + UART_CT_PRSC1 = 25, /**< UART control register(25) (r/w): BAUD rate clock prescaler select bit 1 */ + UART_CT_PRSC2 = 26, /**< UART control register(26) (r/w): BAUD rate clock prescaler select bit 2 */ + UART_CT_CTS = 27, /**< UART control register(27) (r/-): current state of CTS input */ + UART_CT_EN = 28, /**< UART control register(28) (r/w): UART global enable */ + + UART_CT_TX_BUSY = 31 /**< UART control register(31) (r/-): Transmitter is busy when set */ +}; + +/** SPI control register bits */ +enum NEORV32_SPI_CT_enum { + SPI_CT_CS0 = 0, /**< UART control register(0) (r/w): Direct chip select line 0 (output is low when set) */ + SPI_CT_CS1 = 1, /**< UART control register(1) (r/w): Direct chip select line 1 (output is low when set) */ + SPI_CT_CS2 = 2, /**< UART control register(2) (r/w): Direct chip select line 2 (output is low when set) */ + SPI_CT_CS3 = 3, /**< UART control register(3) (r/w): Direct chip select line 3 (output is low when set) */ + SPI_CT_CS4 = 4, /**< UART control register(4) (r/w): Direct chip select line 4 (output is low when set) */ + SPI_CT_CS5 = 5, /**< UART control register(5) (r/w): Direct chip select line 5 (output is low when set) */ + SPI_CT_CS6 = 6, /**< UART control register(6) (r/w): Direct chip select line 6 (output is low when set) */ + SPI_CT_CS7 = 7, /**< UART control register(7) (r/w): Direct chip select line 7 (output is low when set) */ + SPI_CT_EN = 8, /**< UART control register(8) (r/w): SPI unit enable */ + SPI_CT_CPHA = 9, /**< UART control register(9) (r/w): Clock polarity (idle polarity) */ + SPI_CT_PRSC0 = 10, /**< UART control register(10) (r/w): Clock prescaler select bit 0 */ + SPI_CT_PRSC1 = 11, /**< UART control register(11) (r/w): Clock prescaler select bit 1 */ + SPI_CT_PRSC2 = 12, /**< UART control register(12) (r/w): Clock prescaler select bit 2 */ + SPI_CT_SIZE0 = 13, /**< UART control register(13) (r/w): Transfer data size lsb (00: 8-bit, 01: 16-bit, 10: 24-bit, 11: 32-bit) */ + SPI_CT_SIZE1 = 14, /**< UART control register(14) (r/w): Transfer data size msb (00: 8-bit, 01: 16-bit, 10: 24-bit, 11: 32-bit) */ + + SPI_CT_BUSY = 31 /**< UART control register(31) (r/-): SPI busy flag */ +}; + +/** TWI control register bits */ +enum NEORV32_TWI_CT_enum { + TWI_CT_EN = 0, /**< TWI control register(0) (r/w): TWI enable */ + TWI_CT_START = 1, /**< TWI control register(1) (-/w): Generate START condition, auto-clears */ + TWI_CT_STOP = 2, /**< TWI control register(2) (-/w): Generate STOP condition, auto-clears */ + TWI_CT_PRSC0 = 3, /**< TWI control register(3) (r/w): Clock prescaler select bit 0 */ + TWI_CT_PRSC1 = 4, /**< TWI control register(4) (r/w): Clock prescaler select bit 1 */ + TWI_CT_PRSC2 = 5, /**< TWI control register(5) (r/w): Clock prescaler select bit 2 */ + TWI_CT_MACK = 6, /**< TWI control register(6) (r/w): Generate controller ACK for each transmission */ + TWI_CT_CKSTEN = 7, /**< TWI control register(7) (r/w): Enable clock stretching (by peripheral) */ + + TWI_CT_ACK = 30, /**< TWI control register(30) (r/-): ACK received when set */ + TWI_CT_BUSY = 31 /**< TWI control register(31) (r/-): Transfer in progress, busy flag */ +}; + +/** TRNG control/data register bits */ +enum NEORV32_TRNG_CT_enum { + TRNG_CT_DATA_LSB = 0, /**< TRNG data/control register(0) (r/-): Random data byte LSB */ + TRNG_CT_DATA_MSB = 7, /**< TRNG data/control register(7) (r/-): Random data byte MSB */ + + TRNG_CT_EN = 30, /**< TRNG data/control register(30) (r/w): TRNG enable */ + TRNG_CT_VALID = 31 /**< TRNG data/control register(31) (r/-): Random data output valid */ +}; + +/** WTD control register bits */ +enum NEORV32_WDT_CT_enum { + WDT_CT_EN = 0, /**< WDT control register(0) (r/w): Watchdog enable */ + WDT_CT_CLK_SEL0 = 1, /**< WDT control register(1) (r/w): Clock prescaler select bit 0 */ + WDT_CT_CLK_SEL1 = 2, /**< WDT control register(2) (r/w): Clock prescaler select bit 1 */ + WDT_CT_CLK_SEL2 = 3, /**< WDT control register(3) (r/w): Clock prescaler select bit 2 */ + WDT_CT_MODE = 4, /**< WDT control register(4) (r/w): Watchdog mode: 0=timeout causes interrupt, 1=timeout causes processor reset */ + WDT_CT_RCAUSE = 5, /**< WDT control register(5) (r/-): Cause of last system reset: 0=external reset, 1=watchdog */ + WDT_CT_RESET = 6, /**< WDT control register(6) (-/w): Reset WDT counter when set, auto-clears */ + WDT_CT_FORCE = 7, /**< WDT control register(7) (-/w): Force WDT action, auto-clears */ + WDT_CT_LOCK = 8 /**< WDT control register(8) (r/w): Lock write access to control register, clears on reset (HW or WDT) only */ +}; + +/** NEOLED control register bits */ +enum NEORV32_NEOLED_CT_enum { + NEOLED_CT_EN = 0, /**< NEOLED control register(0) (r/w): NEOLED global enable */ + NEOLED_CT_MODE = 1, /**< NEOLED control register(1) (r/w): TX mode (0=24-bit, 1=32-bit) */ + NEOLED_CT_STROBE = 2, /**< NEOLED control register(2) (r/w): Strobe (0=send normal data, 1=send RESET command on data write) */ + NEOLED_CT_PRSC0 = 3, /**< NEOLED control register(3) (r/w): Clock prescaler select bit 0 (pulse-clock speed select) */ + NEOLED_CT_PRSC1 = 4, /**< NEOLED control register(4) (r/w): Clock prescaler select bit 1 (pulse-clock speed select) */ + NEOLED_CT_PRSC2 = 5, /**< NEOLED control register(5) (r/w): Clock prescaler select bit 2 (pulse-clock speed select) */ + // + NEOLED_CT_BUFS_0 = 6, /**< NEOLED control register(6) (r/-): log2(tx buffer size) bit 0 */ + NEOLED_CT_BUFS_1 = 7, /**< NEOLED control register(7) (r/-): log2(tx buffer size) bit 1 */ + NEOLED_CT_BUFS_2 = 8, /**< NEOLED control register(8) (r/-): log2(tx buffer size) bit 2 */ + NEOLED_CT_BUFS_3 = 9, /**< NEOLED control register(9) (r/-): log2(tx buffer size) bit 3 */ + // + NEOLED_CT_T_TOT_0 = 10, /**< NEOLED control register(10) (r/w): pulse-clock ticks per total period bit 0 */ + NEOLED_CT_T_TOT_1 = 11, /**< NEOLED control register(11) (r/w): pulse-clock ticks per total period bit 1 */ + NEOLED_CT_T_TOT_2 = 12, /**< NEOLED control register(12) (r/w): pulse-clock ticks per total period bit 2 */ + NEOLED_CT_T_TOT_3 = 13, /**< NEOLED control register(13) (r/w): pulse-clock ticks per total period bit 3 */ + NEOLED_CT_T_TOT_4 = 14, /**< NEOLED control register(14) (r/w): pulse-clock ticks per total period bit 4 */ + // + NEOLED_CT_T_ZERO_H_0 = 15, /**< NEOLED control register(15) (r/w): pulse-clock ticks per ZERO high-time bit 0 */ + NEOLED_CT_T_ZERO_H_1 = 16, /**< NEOLED control register(16) (r/w): pulse-clock ticks per ZERO high-time bit 1 */ + NEOLED_CT_T_ZERO_H_2 = 17, /**< NEOLED control register(17) (r/w): pulse-clock ticks per ZERO high-time bit 2 */ + NEOLED_CT_T_ZERO_H_3 = 18, /**< NEOLED control register(18) (r/w): pulse-clock ticks per ZERO high-time bit 3 */ + NEOLED_CT_T_ZERO_H_4 = 19, /**< NEOLED control register(19) (r/w): pulse-clock ticks per ZERO high-time bit 4 */ + // + NEOLED_CT_T_ONE_H_0 = 20, /**< NEOLED control register(20) (r/w): pulse-clock ticks per ONE high-time bit 0 */ + NEOLED_CT_T_ONE_H_1 = 21, /**< NEOLED control register(21) (r/w): pulse-clock ticks per ONE high-time bit 1 */ + NEOLED_CT_T_ONE_H_2 = 22, /**< NEOLED control register(22) (r/w): pulse-clock ticks per ONE high-time bit 2 */ + NEOLED_CT_T_ONE_H_3 = 23, /**< NEOLED control register(23) (r/w): pulse-clock ticks per ONE high-time bit 3 */ + NEOLED_CT_T_ONE_H_4 = 24, /**< NEOLED control register(24) (r/w): pulse-clock ticks per ONE high-time bit 4 */ + // + NEOLED_CT_TX_EMPTY = 28, /**< NEOLED control register(28) (r/-): TX FIFO is empty */ + NEOLED_CT_TX_HALF = 29, /**< NEOLED control register(29) (r/-): TX FIFO is at least half-full */ + NEOLED_CT_TX_FULL = 30, /**< NEOLED control register(30) (r/-): TX FIFO is full */ + NEOLED_CT_TX_BUSY = 31 /**< NEOLED control register(31) (r/-): busy / buffer status flag (configured via #NEOLED_CT_BSCON) */ +}; + + + /// @endcond #endif // neorv32_legacy_h From ad076386766cc320ecebb8551cf64bc11e5452f7 Mon Sep 17 00:00:00 2001 From: stnolting Date: Sat, 18 Sep 2021 23:07:28 +0200 Subject: [PATCH 9/9] updated version and changelog --- CHANGELOG.md | 1 + rtl/core/neorv32_package.vhd | 6 +++++- 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index 7d5d8e718..71ff1fc36 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -25,6 +25,7 @@ defined by the `hw_version_c` constant in the main VHDL package file [`rtl/core/ | Date (*dd.mm.yyyy*) | Version | Comment | |:----------:|:-------:|:--------| +| 18.09.2021 | 1.6.0.4 | :warning: :warning: **major change** modified low-level hardware access (memory-mapped registers) [PR #158](https://github.com/stnolting/neorv32/pull/158): now using `struct`-based access concept (IO module = `struct`, interface registers = members of struct) instead of `#define` single-pointers (inspired by https://blog.feabhas.com/2019/01/peripheral-register-access-using-c-structs-part-1/), format: `NEORV32_.`; renamed all control registers and bits from `*CT*` to `*CTRL*`; added `sw/lib/include/neorv32_legacy.h` compatibility layer (maps deprecated "defines" to according struct registers, provides old control register/bit names, _do not use for new designs!_) | | 16.09.2021 | 1.6.0.3 | :bug: fixed another missing IRQ signal connection (NMI) in `system_integration` wrappers | | 15.09.2021 | 1.6.0.2 | :warning: **split** processor-internal memory VHDL sources (IMEM and DMEM) into separated files ([#151](https://github.com/stnolting/neorv32/pull/151)): entity-only (`rtl/core/neorv32_*mem.entity.vhd`) and _default_ architecture-only (`rtl/core/mem/neorv32_*mem.default.vhd`); allows easy replacement by optimized platform-specific architectures | | 13.09.2021 | 1.6.0.1 | :bug: fixed missing IRQ signal assignments (MSW and XIRQ) in AXI4-lite top wrapper | diff --git a/rtl/core/neorv32_package.vhd b/rtl/core/neorv32_package.vhd index 9116cd144..6cb06e6c5 100644 --- a/rtl/core/neorv32_package.vhd +++ b/rtl/core/neorv32_package.vhd @@ -64,7 +64,7 @@ package neorv32_package is -- Architecture Constants (do not modify!) ------------------------------------------------ -- ------------------------------------------------------------------------------------------- constant data_width_c : natural := 32; -- native data path width - do not change! - constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01060003"; -- no touchy! + constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01060004"; -- no touchy! constant archid_c : natural := 19; -- official NEORV32 architecture ID - hands off! -- External Interface Types --------------------------------------------------------------- @@ -117,6 +117,10 @@ package neorv32_package is constant dmem_base_c : std_ulogic_vector(data_width_c-1 downto 0) := dspace_base_c; -- internal data memory base address --> internal data/instruction memory sizes are configured via top's generics + -- !!! IMPORTANT: The base address of each component/module has to be aligned to the !!! + -- !!! total size of the module's occupied address space. The occupied address space !!! + -- !!! has to be a power of two (minimum 4 bytes). Address spaces must not overlap. !!! + -- Internal Bootloader ROM -- -- Actual bootloader size is determined during runtime via the length of the bootloader initialization image constant boot_rom_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffff0000"; -- bootloader base address, fixed!