From c97018d4c716aea6965d8033f3eb57ddcdbeb2ba Mon Sep 17 00:00:00 2001 From: Simon Moll Date: Thu, 15 Oct 2020 10:37:21 +0200 Subject: [PATCH 1/2] [VE] Make SPU reg in vops match the vop elem type (was I64 before) Before, the scalar register operand always had to be in a I64 register. Yet, the VE backend defines F32,I32 subregisters. By using those (and making them match the element type of the vop) vector instruction selection patterns become simpler (no subreg insertions/reg copies required). --- .../include/clang/Basic/BuiltinsVEVL.gen.def | 36 ++++---- llvm/include/llvm/IR/IntrinsicsVEVL.gen.td | 24 +++--- llvm/lib/Target/VE/VEInstrIntrinsicVL.gen.td | 24 +++--- llvm/lib/Target/VE/VEInstrPatternsVec.td | 6 +- llvm/lib/Target/VE/VEInstrVec.td | 85 ++++++++++--------- llvm/lib/Target/VE/VEInstrVecVL.gen.td | 24 +++--- llvm/lib/Target/VE/veintrin.py | 2 +- .../CodeGen/VE/gen-velintrin-vslawsx_vvsl.ll | 6 +- .../VE/gen-velintrin-vslawsx_vvsl_imm.ll | 4 +- .../VE/gen-velintrin-vslawsx_vvsmvl.ll | 6 +- .../VE/gen-velintrin-vslawsx_vvsmvl_imm.ll | 4 +- .../CodeGen/VE/gen-velintrin-vslawzx_vvsl.ll | 6 +- .../VE/gen-velintrin-vslawzx_vvsl_imm.ll | 4 +- .../VE/gen-velintrin-vslawzx_vvsmvl.ll | 6 +- .../VE/gen-velintrin-vslawzx_vvsmvl_imm.ll | 4 +- .../CodeGen/VE/gen-velintrin-vsrawsx_vvsl.ll | 6 +- .../VE/gen-velintrin-vsrawsx_vvsl_imm.ll | 4 +- .../VE/gen-velintrin-vsrawsx_vvsmvl.ll | 6 +- .../VE/gen-velintrin-vsrawsx_vvsmvl_imm.ll | 4 +- .../CodeGen/VE/gen-velintrin-vsrawzx_vvsl.ll | 6 +- .../VE/gen-velintrin-vsrawzx_vvsl_imm.ll | 4 +- .../VE/gen-velintrin-vsrawzx_vvsmvl.ll | 6 +- .../VE/gen-velintrin-vsrawzx_vvsmvl_imm.ll | 4 +- 23 files changed, 142 insertions(+), 139 deletions(-) diff --git a/clang/include/clang/Basic/BuiltinsVEVL.gen.def b/clang/include/clang/Basic/BuiltinsVEVL.gen.def index b8c29effe3da..0755774452a3 100644 --- a/clang/include/clang/Basic/BuiltinsVEVL.gen.def +++ b/clang/include/clang/Basic/BuiltinsVEVL.gen.def @@ -441,16 +441,16 @@ BUILTIN(__builtin_ve_vl_pvsrl_vvvMvl, "V256dV256dV256dV512bV256dUi", "n") BUILTIN(__builtin_ve_vl_pvsrl_vvsMvl, "V256dV256dLUiV512bV256dUi", "n") BUILTIN(__builtin_ve_vl_vslawsx_vvvl, "V256dV256dV256dUi", "n") BUILTIN(__builtin_ve_vl_vslawsx_vvvvl, "V256dV256dV256dV256dUi", "n") -BUILTIN(__builtin_ve_vl_vslawsx_vvsl, "V256dV256dLUiUi", "n") -BUILTIN(__builtin_ve_vl_vslawsx_vvsvl, "V256dV256dLUiV256dUi", "n") +BUILTIN(__builtin_ve_vl_vslawsx_vvsl, "V256dV256diUi", "n") +BUILTIN(__builtin_ve_vl_vslawsx_vvsvl, "V256dV256diV256dUi", "n") BUILTIN(__builtin_ve_vl_vslawsx_vvvmvl, "V256dV256dV256dV256bV256dUi", "n") -BUILTIN(__builtin_ve_vl_vslawsx_vvsmvl, "V256dV256dLUiV256bV256dUi", "n") +BUILTIN(__builtin_ve_vl_vslawsx_vvsmvl, "V256dV256diV256bV256dUi", "n") BUILTIN(__builtin_ve_vl_vslawzx_vvvl, "V256dV256dV256dUi", "n") BUILTIN(__builtin_ve_vl_vslawzx_vvvvl, "V256dV256dV256dV256dUi", "n") -BUILTIN(__builtin_ve_vl_vslawzx_vvsl, "V256dV256dLUiUi", "n") -BUILTIN(__builtin_ve_vl_vslawzx_vvsvl, "V256dV256dLUiV256dUi", "n") +BUILTIN(__builtin_ve_vl_vslawzx_vvsl, "V256dV256diUi", "n") +BUILTIN(__builtin_ve_vl_vslawzx_vvsvl, "V256dV256diV256dUi", "n") BUILTIN(__builtin_ve_vl_vslawzx_vvvmvl, "V256dV256dV256dV256bV256dUi", "n") -BUILTIN(__builtin_ve_vl_vslawzx_vvsmvl, "V256dV256dLUiV256bV256dUi", "n") +BUILTIN(__builtin_ve_vl_vslawzx_vvsmvl, "V256dV256diV256bV256dUi", "n") BUILTIN(__builtin_ve_vl_pvsla_vvvl, "V256dV256dV256dUi", "n") BUILTIN(__builtin_ve_vl_pvsla_vvvvl, "V256dV256dV256dV256dUi", "n") BUILTIN(__builtin_ve_vl_pvsla_vvsl, "V256dV256dLUiUi", "n") @@ -459,22 +459,22 @@ BUILTIN(__builtin_ve_vl_pvsla_vvvMvl, "V256dV256dV256dV512bV256dUi", "n") BUILTIN(__builtin_ve_vl_pvsla_vvsMvl, "V256dV256dLUiV512bV256dUi", "n") BUILTIN(__builtin_ve_vl_vslal_vvvl, "V256dV256dV256dUi", "n") BUILTIN(__builtin_ve_vl_vslal_vvvvl, "V256dV256dV256dV256dUi", "n") -BUILTIN(__builtin_ve_vl_vslal_vvsl, "V256dV256dLUiUi", "n") -BUILTIN(__builtin_ve_vl_vslal_vvsvl, "V256dV256dLUiV256dUi", "n") +BUILTIN(__builtin_ve_vl_vslal_vvsl, "V256dV256dLiUi", "n") +BUILTIN(__builtin_ve_vl_vslal_vvsvl, "V256dV256dLiV256dUi", "n") BUILTIN(__builtin_ve_vl_vslal_vvvmvl, "V256dV256dV256dV256bV256dUi", "n") -BUILTIN(__builtin_ve_vl_vslal_vvsmvl, "V256dV256dLUiV256bV256dUi", "n") +BUILTIN(__builtin_ve_vl_vslal_vvsmvl, "V256dV256dLiV256bV256dUi", "n") BUILTIN(__builtin_ve_vl_vsrawsx_vvvl, "V256dV256dV256dUi", "n") BUILTIN(__builtin_ve_vl_vsrawsx_vvvvl, "V256dV256dV256dV256dUi", "n") -BUILTIN(__builtin_ve_vl_vsrawsx_vvsl, "V256dV256dLUiUi", "n") -BUILTIN(__builtin_ve_vl_vsrawsx_vvsvl, "V256dV256dLUiV256dUi", "n") +BUILTIN(__builtin_ve_vl_vsrawsx_vvsl, "V256dV256diUi", "n") +BUILTIN(__builtin_ve_vl_vsrawsx_vvsvl, "V256dV256diV256dUi", "n") BUILTIN(__builtin_ve_vl_vsrawsx_vvvmvl, "V256dV256dV256dV256bV256dUi", "n") -BUILTIN(__builtin_ve_vl_vsrawsx_vvsmvl, "V256dV256dLUiV256bV256dUi", "n") +BUILTIN(__builtin_ve_vl_vsrawsx_vvsmvl, "V256dV256diV256bV256dUi", "n") BUILTIN(__builtin_ve_vl_vsrawzx_vvvl, "V256dV256dV256dUi", "n") BUILTIN(__builtin_ve_vl_vsrawzx_vvvvl, "V256dV256dV256dV256dUi", "n") -BUILTIN(__builtin_ve_vl_vsrawzx_vvsl, "V256dV256dLUiUi", "n") -BUILTIN(__builtin_ve_vl_vsrawzx_vvsvl, "V256dV256dLUiV256dUi", "n") +BUILTIN(__builtin_ve_vl_vsrawzx_vvsl, "V256dV256diUi", "n") +BUILTIN(__builtin_ve_vl_vsrawzx_vvsvl, "V256dV256diV256dUi", "n") BUILTIN(__builtin_ve_vl_vsrawzx_vvvmvl, "V256dV256dV256dV256bV256dUi", "n") -BUILTIN(__builtin_ve_vl_vsrawzx_vvsmvl, "V256dV256dLUiV256bV256dUi", "n") +BUILTIN(__builtin_ve_vl_vsrawzx_vvsmvl, "V256dV256diV256bV256dUi", "n") BUILTIN(__builtin_ve_vl_pvsra_vvvl, "V256dV256dV256dUi", "n") BUILTIN(__builtin_ve_vl_pvsra_vvvvl, "V256dV256dV256dV256dUi", "n") BUILTIN(__builtin_ve_vl_pvsra_vvsl, "V256dV256dLUiUi", "n") @@ -483,10 +483,10 @@ BUILTIN(__builtin_ve_vl_pvsra_vvvMvl, "V256dV256dV256dV512bV256dUi", "n") BUILTIN(__builtin_ve_vl_pvsra_vvsMvl, "V256dV256dLUiV512bV256dUi", "n") BUILTIN(__builtin_ve_vl_vsral_vvvl, "V256dV256dV256dUi", "n") BUILTIN(__builtin_ve_vl_vsral_vvvvl, "V256dV256dV256dV256dUi", "n") -BUILTIN(__builtin_ve_vl_vsral_vvsl, "V256dV256dLUiUi", "n") -BUILTIN(__builtin_ve_vl_vsral_vvsvl, "V256dV256dLUiV256dUi", "n") +BUILTIN(__builtin_ve_vl_vsral_vvsl, "V256dV256dLiUi", "n") +BUILTIN(__builtin_ve_vl_vsral_vvsvl, "V256dV256dLiV256dUi", "n") BUILTIN(__builtin_ve_vl_vsral_vvvmvl, "V256dV256dV256dV256bV256dUi", "n") -BUILTIN(__builtin_ve_vl_vsral_vvsmvl, "V256dV256dLUiV256bV256dUi", "n") +BUILTIN(__builtin_ve_vl_vsral_vvsmvl, "V256dV256dLiV256bV256dUi", "n") BUILTIN(__builtin_ve_vl_vsfa_vvssl, "V256dV256dLUiLUiUi", "n") BUILTIN(__builtin_ve_vl_vsfa_vvssvl, "V256dV256dLUiLUiV256dUi", "n") BUILTIN(__builtin_ve_vl_vsfa_vvssmvl, "V256dV256dLUiLUiV256bV256dUi", "n") diff --git a/llvm/include/llvm/IR/IntrinsicsVEVL.gen.td b/llvm/include/llvm/IR/IntrinsicsVEVL.gen.td index 76f3fa7e792c..ba4a40c480a4 100644 --- a/llvm/include/llvm/IR/IntrinsicsVEVL.gen.td +++ b/llvm/include/llvm/IR/IntrinsicsVEVL.gen.td @@ -441,16 +441,16 @@ let TargetPrefix = "ve" in def int_ve_vl_pvsrl_vvvMvl : GCCBuiltin<"__builtin_ve let TargetPrefix = "ve" in def int_ve_vl_pvsrl_vvsMvl : GCCBuiltin<"__builtin_ve_vl_pvsrl_vvsMvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType, LLVMType, LLVMType], [IntrNoMem]>; let TargetPrefix = "ve" in def int_ve_vl_vslawsx_vvvl : GCCBuiltin<"__builtin_ve_vl_vslawsx_vvvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType], [IntrNoMem]>; let TargetPrefix = "ve" in def int_ve_vl_vslawsx_vvvvl : GCCBuiltin<"__builtin_ve_vl_vslawsx_vvvvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType, LLVMType], [IntrNoMem]>; -let TargetPrefix = "ve" in def int_ve_vl_vslawsx_vvsl : GCCBuiltin<"__builtin_ve_vl_vslawsx_vvsl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType], [IntrNoMem]>; -let TargetPrefix = "ve" in def int_ve_vl_vslawsx_vvsvl : GCCBuiltin<"__builtin_ve_vl_vslawsx_vvsvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_vslawsx_vvsl : GCCBuiltin<"__builtin_ve_vl_vslawsx_vvsl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_vslawsx_vvsvl : GCCBuiltin<"__builtin_ve_vl_vslawsx_vvsvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType, LLVMType], [IntrNoMem]>; let TargetPrefix = "ve" in def int_ve_vl_vslawsx_vvvmvl : GCCBuiltin<"__builtin_ve_vl_vslawsx_vvvmvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType, LLVMType, LLVMType], [IntrNoMem]>; -let TargetPrefix = "ve" in def int_ve_vl_vslawsx_vvsmvl : GCCBuiltin<"__builtin_ve_vl_vslawsx_vvsmvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_vslawsx_vvsmvl : GCCBuiltin<"__builtin_ve_vl_vslawsx_vvsmvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType, LLVMType, LLVMType], [IntrNoMem]>; let TargetPrefix = "ve" in def int_ve_vl_vslawzx_vvvl : GCCBuiltin<"__builtin_ve_vl_vslawzx_vvvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType], [IntrNoMem]>; let TargetPrefix = "ve" in def int_ve_vl_vslawzx_vvvvl : GCCBuiltin<"__builtin_ve_vl_vslawzx_vvvvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType, LLVMType], [IntrNoMem]>; -let TargetPrefix = "ve" in def int_ve_vl_vslawzx_vvsl : GCCBuiltin<"__builtin_ve_vl_vslawzx_vvsl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType], [IntrNoMem]>; -let TargetPrefix = "ve" in def int_ve_vl_vslawzx_vvsvl : GCCBuiltin<"__builtin_ve_vl_vslawzx_vvsvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_vslawzx_vvsl : GCCBuiltin<"__builtin_ve_vl_vslawzx_vvsl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_vslawzx_vvsvl : GCCBuiltin<"__builtin_ve_vl_vslawzx_vvsvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType, LLVMType], [IntrNoMem]>; let TargetPrefix = "ve" in def int_ve_vl_vslawzx_vvvmvl : GCCBuiltin<"__builtin_ve_vl_vslawzx_vvvmvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType, LLVMType, LLVMType], [IntrNoMem]>; -let TargetPrefix = "ve" in def int_ve_vl_vslawzx_vvsmvl : GCCBuiltin<"__builtin_ve_vl_vslawzx_vvsmvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_vslawzx_vvsmvl : GCCBuiltin<"__builtin_ve_vl_vslawzx_vvsmvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType, LLVMType, LLVMType], [IntrNoMem]>; let TargetPrefix = "ve" in def int_ve_vl_pvsla_vvvl : GCCBuiltin<"__builtin_ve_vl_pvsla_vvvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType], [IntrNoMem]>; let TargetPrefix = "ve" in def int_ve_vl_pvsla_vvvvl : GCCBuiltin<"__builtin_ve_vl_pvsla_vvvvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType, LLVMType], [IntrNoMem]>; let TargetPrefix = "ve" in def int_ve_vl_pvsla_vvsl : GCCBuiltin<"__builtin_ve_vl_pvsla_vvsl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType], [IntrNoMem]>; @@ -465,16 +465,16 @@ let TargetPrefix = "ve" in def int_ve_vl_vslal_vvvmvl : GCCBuiltin<"__builtin_ve let TargetPrefix = "ve" in def int_ve_vl_vslal_vvsmvl : GCCBuiltin<"__builtin_ve_vl_vslal_vvsmvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType, LLVMType, LLVMType], [IntrNoMem]>; let TargetPrefix = "ve" in def int_ve_vl_vsrawsx_vvvl : GCCBuiltin<"__builtin_ve_vl_vsrawsx_vvvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType], [IntrNoMem]>; let TargetPrefix = "ve" in def int_ve_vl_vsrawsx_vvvvl : GCCBuiltin<"__builtin_ve_vl_vsrawsx_vvvvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType, LLVMType], [IntrNoMem]>; -let TargetPrefix = "ve" in def int_ve_vl_vsrawsx_vvsl : GCCBuiltin<"__builtin_ve_vl_vsrawsx_vvsl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType], [IntrNoMem]>; -let TargetPrefix = "ve" in def int_ve_vl_vsrawsx_vvsvl : GCCBuiltin<"__builtin_ve_vl_vsrawsx_vvsvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_vsrawsx_vvsl : GCCBuiltin<"__builtin_ve_vl_vsrawsx_vvsl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_vsrawsx_vvsvl : GCCBuiltin<"__builtin_ve_vl_vsrawsx_vvsvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType, LLVMType], [IntrNoMem]>; let TargetPrefix = "ve" in def int_ve_vl_vsrawsx_vvvmvl : GCCBuiltin<"__builtin_ve_vl_vsrawsx_vvvmvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType, LLVMType, LLVMType], [IntrNoMem]>; -let TargetPrefix = "ve" in def int_ve_vl_vsrawsx_vvsmvl : GCCBuiltin<"__builtin_ve_vl_vsrawsx_vvsmvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_vsrawsx_vvsmvl : GCCBuiltin<"__builtin_ve_vl_vsrawsx_vvsmvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType, LLVMType, LLVMType], [IntrNoMem]>; let TargetPrefix = "ve" in def int_ve_vl_vsrawzx_vvvl : GCCBuiltin<"__builtin_ve_vl_vsrawzx_vvvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType], [IntrNoMem]>; let TargetPrefix = "ve" in def int_ve_vl_vsrawzx_vvvvl : GCCBuiltin<"__builtin_ve_vl_vsrawzx_vvvvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType, LLVMType], [IntrNoMem]>; -let TargetPrefix = "ve" in def int_ve_vl_vsrawzx_vvsl : GCCBuiltin<"__builtin_ve_vl_vsrawzx_vvsl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType], [IntrNoMem]>; -let TargetPrefix = "ve" in def int_ve_vl_vsrawzx_vvsvl : GCCBuiltin<"__builtin_ve_vl_vsrawzx_vvsvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_vsrawzx_vvsl : GCCBuiltin<"__builtin_ve_vl_vsrawzx_vvsl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_vsrawzx_vvsvl : GCCBuiltin<"__builtin_ve_vl_vsrawzx_vvsvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType, LLVMType], [IntrNoMem]>; let TargetPrefix = "ve" in def int_ve_vl_vsrawzx_vvvmvl : GCCBuiltin<"__builtin_ve_vl_vsrawzx_vvvmvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType, LLVMType, LLVMType], [IntrNoMem]>; -let TargetPrefix = "ve" in def int_ve_vl_vsrawzx_vvsmvl : GCCBuiltin<"__builtin_ve_vl_vsrawzx_vvsmvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType, LLVMType, LLVMType], [IntrNoMem]>; +let TargetPrefix = "ve" in def int_ve_vl_vsrawzx_vvsmvl : GCCBuiltin<"__builtin_ve_vl_vsrawzx_vvsmvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType, LLVMType, LLVMType], [IntrNoMem]>; let TargetPrefix = "ve" in def int_ve_vl_pvsra_vvvl : GCCBuiltin<"__builtin_ve_vl_pvsra_vvvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType], [IntrNoMem]>; let TargetPrefix = "ve" in def int_ve_vl_pvsra_vvvvl : GCCBuiltin<"__builtin_ve_vl_pvsra_vvvvl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType, LLVMType], [IntrNoMem]>; let TargetPrefix = "ve" in def int_ve_vl_pvsra_vvsl : GCCBuiltin<"__builtin_ve_vl_pvsra_vvsl">, Intrinsic<[LLVMType], [LLVMType, LLVMType, LLVMType], [IntrNoMem]>; diff --git a/llvm/lib/Target/VE/VEInstrIntrinsicVL.gen.td b/llvm/lib/Target/VE/VEInstrIntrinsicVL.gen.td index c6fa42906f5b..a591db46699c 100644 --- a/llvm/lib/Target/VE/VEInstrIntrinsicVL.gen.td +++ b/llvm/lib/Target/VE/VEInstrIntrinsicVL.gen.td @@ -645,21 +645,21 @@ def : Pat<(int_ve_vl_pvsrl_vvvMvl v256f64:$vz, v256f64:$vy, v512i1:$vm, v256f64: def : Pat<(int_ve_vl_pvsrl_vvsMvl v256f64:$vz, i64:$sy, v512i1:$vm, v256f64:$pt, i32:$vl), (PVSRLvrxl_v v256f64:$vz, i64:$sy, v512i1:$vm, i32:$vl, v256f64:$pt)>; def : Pat<(int_ve_vl_vslawsx_vvvl v256f64:$vz, v256f64:$vy, i32:$vl), (VSLAWSXvvl v256f64:$vz, v256f64:$vy, i32:$vl)>; def : Pat<(int_ve_vl_vslawsx_vvvvl v256f64:$vz, v256f64:$vy, v256f64:$pt, i32:$vl), (VSLAWSXvvl_v v256f64:$vz, v256f64:$vy, i32:$vl, v256f64:$pt)>; -def : Pat<(int_ve_vl_vslawsx_vvsl v256f64:$vz, i64:$sy, i32:$vl), (VSLAWSXvrl v256f64:$vz, i64:$sy, i32:$vl)>; -def : Pat<(int_ve_vl_vslawsx_vvsvl v256f64:$vz, i64:$sy, v256f64:$pt, i32:$vl), (VSLAWSXvrl_v v256f64:$vz, i64:$sy, i32:$vl, v256f64:$pt)>; +def : Pat<(int_ve_vl_vslawsx_vvsl v256f64:$vz, i32:$sy, i32:$vl), (VSLAWSXvrl v256f64:$vz, i32:$sy, i32:$vl)>; +def : Pat<(int_ve_vl_vslawsx_vvsvl v256f64:$vz, i32:$sy, v256f64:$pt, i32:$vl), (VSLAWSXvrl_v v256f64:$vz, i32:$sy, i32:$vl, v256f64:$pt)>; def : Pat<(int_ve_vl_vslawsx_vvsl v256f64:$vz, uimm6:$N, i32:$vl), (VSLAWSXvil v256f64:$vz, (ULO7 $N), i32:$vl)>; def : Pat<(int_ve_vl_vslawsx_vvsvl v256f64:$vz, uimm6:$N, v256f64:$pt, i32:$vl), (VSLAWSXvil_v v256f64:$vz, (ULO7 $N), i32:$vl, v256f64:$pt)>; def : Pat<(int_ve_vl_vslawsx_vvvmvl v256f64:$vz, v256f64:$vy, v256i1:$vm, v256f64:$pt, i32:$vl), (VSLAWSXvvxl_v v256f64:$vz, v256f64:$vy, v256i1:$vm, i32:$vl, v256f64:$pt)>; -def : Pat<(int_ve_vl_vslawsx_vvsmvl v256f64:$vz, i64:$sy, v256i1:$vm, v256f64:$pt, i32:$vl), (VSLAWSXvrxl_v v256f64:$vz, i64:$sy, v256i1:$vm, i32:$vl, v256f64:$pt)>; +def : Pat<(int_ve_vl_vslawsx_vvsmvl v256f64:$vz, i32:$sy, v256i1:$vm, v256f64:$pt, i32:$vl), (VSLAWSXvrxl_v v256f64:$vz, i32:$sy, v256i1:$vm, i32:$vl, v256f64:$pt)>; def : Pat<(int_ve_vl_vslawsx_vvsmvl v256f64:$vz, uimm6:$N, v256i1:$vm, v256f64:$pt, i32:$vl), (VSLAWSXvixl_v v256f64:$vz, (ULO7 $N), v256i1:$vm, i32:$vl, v256f64:$pt)>; def : Pat<(int_ve_vl_vslawzx_vvvl v256f64:$vz, v256f64:$vy, i32:$vl), (VSLAWZXvvl v256f64:$vz, v256f64:$vy, i32:$vl)>; def : Pat<(int_ve_vl_vslawzx_vvvvl v256f64:$vz, v256f64:$vy, v256f64:$pt, i32:$vl), (VSLAWZXvvl_v v256f64:$vz, v256f64:$vy, i32:$vl, v256f64:$pt)>; -def : Pat<(int_ve_vl_vslawzx_vvsl v256f64:$vz, i64:$sy, i32:$vl), (VSLAWZXvrl v256f64:$vz, i64:$sy, i32:$vl)>; -def : Pat<(int_ve_vl_vslawzx_vvsvl v256f64:$vz, i64:$sy, v256f64:$pt, i32:$vl), (VSLAWZXvrl_v v256f64:$vz, i64:$sy, i32:$vl, v256f64:$pt)>; +def : Pat<(int_ve_vl_vslawzx_vvsl v256f64:$vz, i32:$sy, i32:$vl), (VSLAWZXvrl v256f64:$vz, i32:$sy, i32:$vl)>; +def : Pat<(int_ve_vl_vslawzx_vvsvl v256f64:$vz, i32:$sy, v256f64:$pt, i32:$vl), (VSLAWZXvrl_v v256f64:$vz, i32:$sy, i32:$vl, v256f64:$pt)>; def : Pat<(int_ve_vl_vslawzx_vvsl v256f64:$vz, uimm6:$N, i32:$vl), (VSLAWZXvil v256f64:$vz, (ULO7 $N), i32:$vl)>; def : Pat<(int_ve_vl_vslawzx_vvsvl v256f64:$vz, uimm6:$N, v256f64:$pt, i32:$vl), (VSLAWZXvil_v v256f64:$vz, (ULO7 $N), i32:$vl, v256f64:$pt)>; def : Pat<(int_ve_vl_vslawzx_vvvmvl v256f64:$vz, v256f64:$vy, v256i1:$vm, v256f64:$pt, i32:$vl), (VSLAWZXvvxl_v v256f64:$vz, v256f64:$vy, v256i1:$vm, i32:$vl, v256f64:$pt)>; -def : Pat<(int_ve_vl_vslawzx_vvsmvl v256f64:$vz, i64:$sy, v256i1:$vm, v256f64:$pt, i32:$vl), (VSLAWZXvrxl_v v256f64:$vz, i64:$sy, v256i1:$vm, i32:$vl, v256f64:$pt)>; +def : Pat<(int_ve_vl_vslawzx_vvsmvl v256f64:$vz, i32:$sy, v256i1:$vm, v256f64:$pt, i32:$vl), (VSLAWZXvrxl_v v256f64:$vz, i32:$sy, v256i1:$vm, i32:$vl, v256f64:$pt)>; def : Pat<(int_ve_vl_vslawzx_vvsmvl v256f64:$vz, uimm6:$N, v256i1:$vm, v256f64:$pt, i32:$vl), (VSLAWZXvixl_v v256f64:$vz, (ULO7 $N), v256i1:$vm, i32:$vl, v256f64:$pt)>; def : Pat<(int_ve_vl_pvsla_vvvl v256f64:$vz, v256f64:$vy, i32:$vl), (PVSLAvvl v256f64:$vz, v256f64:$vy, i32:$vl)>; def : Pat<(int_ve_vl_pvsla_vvvvl v256f64:$vz, v256f64:$vy, v256f64:$pt, i32:$vl), (PVSLAvvl_v v256f64:$vz, v256f64:$vy, i32:$vl, v256f64:$pt)>; @@ -678,21 +678,21 @@ def : Pat<(int_ve_vl_vslal_vvsmvl v256f64:$vz, i64:$sy, v256i1:$vm, v256f64:$pt, def : Pat<(int_ve_vl_vslal_vvsmvl v256f64:$vz, uimm6:$N, v256i1:$vm, v256f64:$pt, i32:$vl), (VSLALvixl_v v256f64:$vz, (ULO7 $N), v256i1:$vm, i32:$vl, v256f64:$pt)>; def : Pat<(int_ve_vl_vsrawsx_vvvl v256f64:$vz, v256f64:$vy, i32:$vl), (VSRAWSXvvl v256f64:$vz, v256f64:$vy, i32:$vl)>; def : Pat<(int_ve_vl_vsrawsx_vvvvl v256f64:$vz, v256f64:$vy, v256f64:$pt, i32:$vl), (VSRAWSXvvl_v v256f64:$vz, v256f64:$vy, i32:$vl, v256f64:$pt)>; -def : Pat<(int_ve_vl_vsrawsx_vvsl v256f64:$vz, i64:$sy, i32:$vl), (VSRAWSXvrl v256f64:$vz, i64:$sy, i32:$vl)>; -def : Pat<(int_ve_vl_vsrawsx_vvsvl v256f64:$vz, i64:$sy, v256f64:$pt, i32:$vl), (VSRAWSXvrl_v v256f64:$vz, i64:$sy, i32:$vl, v256f64:$pt)>; +def : Pat<(int_ve_vl_vsrawsx_vvsl v256f64:$vz, i32:$sy, i32:$vl), (VSRAWSXvrl v256f64:$vz, i32:$sy, i32:$vl)>; +def : Pat<(int_ve_vl_vsrawsx_vvsvl v256f64:$vz, i32:$sy, v256f64:$pt, i32:$vl), (VSRAWSXvrl_v v256f64:$vz, i32:$sy, i32:$vl, v256f64:$pt)>; def : Pat<(int_ve_vl_vsrawsx_vvsl v256f64:$vz, uimm6:$N, i32:$vl), (VSRAWSXvil v256f64:$vz, (ULO7 $N), i32:$vl)>; def : Pat<(int_ve_vl_vsrawsx_vvsvl v256f64:$vz, uimm6:$N, v256f64:$pt, i32:$vl), (VSRAWSXvil_v v256f64:$vz, (ULO7 $N), i32:$vl, v256f64:$pt)>; def : Pat<(int_ve_vl_vsrawsx_vvvmvl v256f64:$vz, v256f64:$vy, v256i1:$vm, v256f64:$pt, i32:$vl), (VSRAWSXvvxl_v v256f64:$vz, v256f64:$vy, v256i1:$vm, i32:$vl, v256f64:$pt)>; -def : Pat<(int_ve_vl_vsrawsx_vvsmvl v256f64:$vz, i64:$sy, v256i1:$vm, v256f64:$pt, i32:$vl), (VSRAWSXvrxl_v v256f64:$vz, i64:$sy, v256i1:$vm, i32:$vl, v256f64:$pt)>; +def : Pat<(int_ve_vl_vsrawsx_vvsmvl v256f64:$vz, i32:$sy, v256i1:$vm, v256f64:$pt, i32:$vl), (VSRAWSXvrxl_v v256f64:$vz, i32:$sy, v256i1:$vm, i32:$vl, v256f64:$pt)>; def : Pat<(int_ve_vl_vsrawsx_vvsmvl v256f64:$vz, uimm6:$N, v256i1:$vm, v256f64:$pt, i32:$vl), (VSRAWSXvixl_v v256f64:$vz, (ULO7 $N), v256i1:$vm, i32:$vl, v256f64:$pt)>; def : Pat<(int_ve_vl_vsrawzx_vvvl v256f64:$vz, v256f64:$vy, i32:$vl), (VSRAWZXvvl v256f64:$vz, v256f64:$vy, i32:$vl)>; def : Pat<(int_ve_vl_vsrawzx_vvvvl v256f64:$vz, v256f64:$vy, v256f64:$pt, i32:$vl), (VSRAWZXvvl_v v256f64:$vz, v256f64:$vy, i32:$vl, v256f64:$pt)>; -def : Pat<(int_ve_vl_vsrawzx_vvsl v256f64:$vz, i64:$sy, i32:$vl), (VSRAWZXvrl v256f64:$vz, i64:$sy, i32:$vl)>; -def : Pat<(int_ve_vl_vsrawzx_vvsvl v256f64:$vz, i64:$sy, v256f64:$pt, i32:$vl), (VSRAWZXvrl_v v256f64:$vz, i64:$sy, i32:$vl, v256f64:$pt)>; +def : Pat<(int_ve_vl_vsrawzx_vvsl v256f64:$vz, i32:$sy, i32:$vl), (VSRAWZXvrl v256f64:$vz, i32:$sy, i32:$vl)>; +def : Pat<(int_ve_vl_vsrawzx_vvsvl v256f64:$vz, i32:$sy, v256f64:$pt, i32:$vl), (VSRAWZXvrl_v v256f64:$vz, i32:$sy, i32:$vl, v256f64:$pt)>; def : Pat<(int_ve_vl_vsrawzx_vvsl v256f64:$vz, uimm6:$N, i32:$vl), (VSRAWZXvil v256f64:$vz, (ULO7 $N), i32:$vl)>; def : Pat<(int_ve_vl_vsrawzx_vvsvl v256f64:$vz, uimm6:$N, v256f64:$pt, i32:$vl), (VSRAWZXvil_v v256f64:$vz, (ULO7 $N), i32:$vl, v256f64:$pt)>; def : Pat<(int_ve_vl_vsrawzx_vvvmvl v256f64:$vz, v256f64:$vy, v256i1:$vm, v256f64:$pt, i32:$vl), (VSRAWZXvvxl_v v256f64:$vz, v256f64:$vy, v256i1:$vm, i32:$vl, v256f64:$pt)>; -def : Pat<(int_ve_vl_vsrawzx_vvsmvl v256f64:$vz, i64:$sy, v256i1:$vm, v256f64:$pt, i32:$vl), (VSRAWZXvrxl_v v256f64:$vz, i64:$sy, v256i1:$vm, i32:$vl, v256f64:$pt)>; +def : Pat<(int_ve_vl_vsrawzx_vvsmvl v256f64:$vz, i32:$sy, v256i1:$vm, v256f64:$pt, i32:$vl), (VSRAWZXvrxl_v v256f64:$vz, i32:$sy, v256i1:$vm, i32:$vl, v256f64:$pt)>; def : Pat<(int_ve_vl_vsrawzx_vvsmvl v256f64:$vz, uimm6:$N, v256i1:$vm, v256f64:$pt, i32:$vl), (VSRAWZXvixl_v v256f64:$vz, (ULO7 $N), v256i1:$vm, i32:$vl, v256f64:$pt)>; def : Pat<(int_ve_vl_pvsra_vvvl v256f64:$vz, v256f64:$vy, i32:$vl), (PVSRAvvl v256f64:$vz, v256f64:$vy, i32:$vl)>; def : Pat<(int_ve_vl_pvsra_vvvvl v256f64:$vz, v256f64:$vy, v256f64:$pt, i32:$vl), (PVSRAvvl_v v256f64:$vz, v256f64:$vy, i32:$vl, v256f64:$pt)>; diff --git a/llvm/lib/Target/VE/VEInstrPatternsVec.td b/llvm/lib/Target/VE/VEInstrPatternsVec.td index 7a4c01ec0768..18e65a2ce3a7 100644 --- a/llvm/lib/Target/VE/VEInstrPatternsVec.td +++ b/llvm/lib/Target/VE/VEInstrPatternsVec.td @@ -722,15 +722,15 @@ multiclass shift_for_vector_length { (EXTRACT_SUBREG (LEAzii 0, 0, length), sub_i32))>; def : Pat<(shl vi32:$vx, (vi32 (vec_broadcast i32:$sy))), (PVSLALOvrl vi32:$vx, - (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $sy, sub_i32), + $sy, (EXTRACT_SUBREG (LEAzii 0, 0, length), sub_i32))>; def : Pat<(srl vi32:$vx, (vi32 (vec_broadcast i32:$sy))), (PVSRLLOvrl vi32:$vx, - (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $sy, sub_i32), + $sy, (EXTRACT_SUBREG (LEAzii 0, 0, length), sub_i32))>; def : Pat<(sra vi32:$vx, (vi32 (vec_broadcast i32:$sy))), (PVSRALOvrl vi32:$vx, - (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $sy, sub_i32), + $sy, (EXTRACT_SUBREG (LEAzii 0, 0, length), sub_i32))>; } diff --git a/llvm/lib/Target/VE/VEInstrVec.td b/llvm/lib/Target/VE/VEInstrVec.td index d762254b2f33..548a5af381f8 100644 --- a/llvm/lib/Target/VE/VEInstrVec.td +++ b/llvm/lib/Target/VE/VEInstrVec.td @@ -577,14 +577,14 @@ multiclass RVDIVmopc, RegisterClass VRC, // Generic RV multiclass with 2 arguments for logical operations. // e.g. VAND, VOR, VXOR, and etc. let VE_VLIndex = 3 in -multiclass RVLmopc, RegisterClass RC, +multiclass RVLmopc, RegisterClass ScaRC, RegisterClass RC, RegisterClass RCM1, RegisterClass RCM2> { let cy = 0, sy = 0, vy = ?, vz = ? in defm vv : RVmm; let cs = 1, vz = ? in defm rv : RVmm; + (ins ScaRC:$sy, RC:$vz)>; let cs = 1, cy = 0, vz = ? in defm mv : RVmm; @@ -592,14 +592,14 @@ multiclass RVLmopc, RegisterClass RC, // Generic RV multiclass with 2 arguments for shift operations. // e.g. VSLL, VSRL, VSLA, and etc. let VE_VLIndex = 3 in -multiclass RVSmopc, RegisterClass RC, +multiclass RVSmopc, RegisterClass ScaRC, RegisterClass RC, RegisterClass RCM1, RegisterClass RCM2> { let cy = 0, sy = 0, vy = ?, vz = ? in defm vv : RVmm; let cs = 1, vz = ? in defm vr : RVmm; + (ins RC:$vz, ScaRC:$sy)>; let cs = 1, cy = 0, vz = ? in defm vi : RVmm; @@ -703,7 +703,10 @@ multiclass RVSHFmopc, RegisterClass RC, let vx = ?, hasSideEffects = 0, Uses = [VL] in multiclass RVIbmopc, RegisterClass RC, dag dag_in, string disEnc = ""> { - let Constraints = "$vx = $base", DisableEncoding = disEnc#"$base" in + let DisableEncoding = disEnc in + def "" : RV; + let isCodeGenOnly = 1, Constraints = "$vx = $base", DisableEncoding = disEnc#"$base" in def _v : RV; } @@ -1012,28 +1015,28 @@ defm VMINSL : RVm<"vmins.l", 0x9a, V64, I64, VM_, VM>; //----------------------------------------------------------------------------- // Section 8.11.1 - VAND (Vector And) -let cx = 0, cx2 = 0 in defm VAND : RVLm<"vand", 0xc4, V64, VM_, VM>; -let cx = 0, cx2 = 1 in defm PVANDLO : RVLm<"pvand.lo", 0xc4, V64, VM_, VM>; -let cx = 1, cx2 = 0 in defm PVANDUP : RVLm<"pvand.up", 0xc4, V64, VM_, VM>; -let cx = 1, cx2 = 1 in defm PVAND : RVLm<"pvand", 0xc4, V64, VM512_, VM512>; +let cx = 0, cx2 = 0 in defm VAND : RVLm<"vand", 0xc4, I64, V64, VM_, VM>; +let cx = 0, cx2 = 1 in defm PVANDLO : RVLm<"pvand.lo", 0xc4, I32, V64, VM_, VM>; +let cx = 1, cx2 = 0 in defm PVANDUP : RVLm<"pvand.up", 0xc4, F32, V64, VM_, VM>; +let cx = 1, cx2 = 1 in defm PVAND : RVLm<"pvand", 0xc4, I64, V64, VM512_, VM512>; // Section 8.11.2 - VOR (Vector Or) -let cx = 0, cx2 = 0 in defm VOR : RVLm<"vor", 0xc5, V64, VM_, VM>; -let cx = 0, cx2 = 1 in defm PVORLO : RVLm<"pvor.lo", 0xc5, V64, VM_, VM>; -let cx = 1, cx2 = 0 in defm PVORUP : RVLm<"pvor.up", 0xc5, V64, VM_, VM>; -let cx = 1, cx2 = 1 in defm PVOR : RVLm<"pvor", 0xc5, V64, VM512_, VM512>; +let cx = 0, cx2 = 0 in defm VOR : RVLm<"vor", 0xc5, I64, V64, VM_, VM>; +let cx = 0, cx2 = 1 in defm PVORLO : RVLm<"pvor.lo", 0xc5, I32, V64, VM_, VM>; +let cx = 1, cx2 = 0 in defm PVORUP : RVLm<"pvor.up", 0xc5, F32, V64, VM_, VM>; +let cx = 1, cx2 = 1 in defm PVOR : RVLm<"pvor", 0xc5, I64, V64, VM512_, VM512>; // Section 8.11.3 - VXOR (Vector Exclusive Or) -let cx = 0, cx2 = 0 in defm VXOR : RVLm<"vxor", 0xc6, V64, VM_, VM>; -let cx = 0, cx2 = 1 in defm PVXORLO : RVLm<"pvxor.lo", 0xc6, V64, VM_, VM>; -let cx = 1, cx2 = 0 in defm PVXORUP : RVLm<"pvxor.up", 0xc6, V64, VM_, VM>; -let cx = 1, cx2 = 1 in defm PVXOR : RVLm<"pvxor", 0xc6, V64, VM512_, VM512>; +let cx = 0, cx2 = 0 in defm VXOR : RVLm<"vxor", 0xc6, I64, V64, VM_, VM>; +let cx = 0, cx2 = 1 in defm PVXORLO : RVLm<"pvxor.lo", 0xc6, I32, V64, VM_, VM>; +let cx = 1, cx2 = 0 in defm PVXORUP : RVLm<"pvxor.up", 0xc6, F32, V64, VM_, VM>; +let cx = 1, cx2 = 1 in defm PVXOR : RVLm<"pvxor", 0xc6, I64, V64, VM512_, VM512>; // Section 8.11.4 - VEQV (Vector Equivalence) -let cx = 0, cx2 = 0 in defm VEQV : RVLm<"veqv", 0xc7, V64, VM_, VM>; -let cx = 0, cx2 = 1 in defm PVEQVLO : RVLm<"pveqv.lo", 0xc7, V64, VM_, VM>; -let cx = 1, cx2 = 0 in defm PVEQVUP : RVLm<"pveqv.up", 0xc7, V64, VM_, VM>; -let cx = 1, cx2 = 1 in defm PVEQV : RVLm<"pveqv", 0xc7, V64, VM512_, VM512>; +let cx = 0, cx2 = 0 in defm VEQV : RVLm<"veqv", 0xc7, I64, V64, VM_, VM>; +let cx = 0, cx2 = 1 in defm PVEQVLO : RVLm<"pveqv.lo", 0xc7, I32, V64, VM_, VM>; +let cx = 1, cx2 = 0 in defm PVEQVUP : RVLm<"pveqv.up", 0xc7, F32, V64, VM_, VM>; +let cx = 1, cx2 = 1 in defm PVEQV : RVLm<"pveqv", 0xc7, I64, V64, VM512_, VM512>; // Section 8.11.5 - VLDZ (Vector Leading Zero Count) let cx = 0, cx2 = 0 in defm VLDZ : RV1m<"vldz", 0xe7, V64, VM_, VM>; @@ -1064,54 +1067,54 @@ let cx = 1, cx2 = 1 in defm PVSEQ : RV0m<"pvseq", 0x99, V64, VM512_, VM512>; //----------------------------------------------------------------------------- // Section 8.12.1 - VSLL (Vector Shift Left Logical) -let cx = 0, cx2 = 0 in defm VSLL : RVSm<"vsll", 0xe5, V64, VM_, VM>; -let cx = 0, cx2 = 1 in defm PVSLLLO : RVSm<"pvsll.lo", 0xe5, V64, VM_, VM>; -let cx = 1, cx2 = 0 in defm PVSLLUP : RVSm<"pvsll.up", 0xe5, V64, VM_, VM>; -let cx = 1, cx2 = 1 in defm PVSLL : RVSm<"pvsll", 0xe5, V64, VM512_, VM512>; +let cx = 0, cx2 = 0 in defm VSLL : RVSm<"vsll", 0xe5, I64, V64, VM_, VM>; +let cx = 0, cx2 = 1 in defm PVSLLLO : RVSm<"pvsll.lo", 0xe5, I32, V64, VM_, VM>; +let cx = 1, cx2 = 0 in defm PVSLLUP : RVSm<"pvsll.up", 0xe5, F32, V64, VM_, VM>; +let cx = 1, cx2 = 1 in defm PVSLL : RVSm<"pvsll", 0xe5, I64, V64, VM512_, VM512>; // Section 8.12.2 - VSLD (Vector Shift Left Double) defm VSLD : RVSDm<"vsld", 0xe4, V64, VM_, VM>; // Section 8.12.3 - VSRL (Vector Shift Right Logical) -let cx = 0, cx2 = 0 in defm VSRL : RVSm<"vsrl", 0xf5, V64, VM_, VM>; -let cx = 0, cx2 = 1 in defm PVSRLLO : RVSm<"pvsrl.lo", 0xf5, V64, VM_, VM>; -let cx = 1, cx2 = 0 in defm PVSRLUP : RVSm<"pvsrl.up", 0xf5, V64, VM_, VM>; -let cx = 1, cx2 = 1 in defm PVSRL : RVSm<"pvsrl", 0xf5, V64, VM512_, VM512>; +let cx = 0, cx2 = 0 in defm VSRL : RVSm<"vsrl", 0xf5, I64, V64, VM_, VM>; +let cx = 0, cx2 = 1 in defm PVSRLLO : RVSm<"pvsrl.lo", 0xf5, I32, V64, VM_, VM>; +let cx = 1, cx2 = 0 in defm PVSRLUP : RVSm<"pvsrl.up", 0xf5, F32, V64, VM_, VM>; +let cx = 1, cx2 = 1 in defm PVSRL : RVSm<"pvsrl", 0xf5, I64, V64, VM512_, VM512>; // Section 8.12.4 - VSRD (Vector Shift Right Double) defm VSRD : RVSDm<"vsrd", 0xf4, V64, VM_, VM>; // Section 8.12.5 - VSLA (Vector Shift Left Arithmetic) -let cx = 0, cx2 = 0 in defm VSLAWSX : RVSm<"vsla.w.sx", 0xe6, V64, VM_, VM>; +let cx = 0, cx2 = 0 in defm VSLAWSX : RVSm<"vsla.w.sx", 0xe6, I32, V64, VM_, VM>; let cx = 0, cx2 = 1 in { - defm PVSLALO : RVSm<"pvsla.lo", 0xe6, V64, VM_, VM>; - let isCodeGenOnly = 1 in defm VSLAWZX : RVSm<"vsla.w.zx", 0xe6, V64, VM_, VM>; + defm PVSLALO : RVSm<"pvsla.lo", 0xe6, I32, V64, VM_, VM>; + let isCodeGenOnly = 1 in defm VSLAWZX : RVSm<"vsla.w.zx", 0xe6, I32, V64, VM_, VM>; } -let cx = 1, cx2 = 0 in defm PVSLAUP : RVSm<"pvsla.up", 0xe6, V64, VM_, VM>; -let cx = 1, cx2 = 1 in defm PVSLA : RVSm<"pvsla", 0xe6, V64, VM512_, VM512>; +let cx = 1, cx2 = 0 in defm PVSLAUP : RVSm<"pvsla.up", 0xe6, F32, V64, VM_, VM>; +let cx = 1, cx2 = 1 in defm PVSLA : RVSm<"pvsla", 0xe6, I64, V64, VM512_, VM512>; def : MnemonicAlias<"pvsla.lo.sx", "vsla.w.sx">; def : MnemonicAlias<"vsla.w.zx", "pvsla.lo">; def : MnemonicAlias<"vsla.w", "pvsla.lo">; def : MnemonicAlias<"pvsla.lo.zx", "pvsla.lo">; // Section 8.12.6 - VSLAX (Vector Shift Left Arithmetic) -defm VSLAL : RVSm<"vsla.l", 0xd4, V64, VM_, VM>; +defm VSLAL : RVSm<"vsla.l", 0xd4, I64, V64, VM_, VM>; // Section 8.12.7 - VSRA (Vector Shift Right Arithmetic) -let cx = 0, cx2 = 0 in defm VSRAWSX : RVSm<"vsra.w.sx", 0xf6, V64, VM_, VM>; +let cx = 0, cx2 = 0 in defm VSRAWSX : RVSm<"vsra.w.sx", 0xf6, I32, V64, VM_, VM>; let cx = 0, cx2 = 1 in { - defm PVSRALO : RVSm<"pvsra.lo", 0xf6, V64, VM_, VM>; - let isCodeGenOnly = 1 in defm VSRAWZX : RVSm<"vsra.w.zx", 0xf6, V64, VM_, VM>; + defm PVSRALO : RVSm<"pvsra.lo", 0xf6, I32, V64, VM_, VM>; + let isCodeGenOnly = 1 in defm VSRAWZX : RVSm<"vsra.w.zx", 0xf6, I32, V64, VM_, VM>; } -let cx = 1, cx2 = 0 in defm PVSRAUP : RVSm<"pvsra.up", 0xf6, V64, VM_, VM>; -let cx = 1, cx2 = 1 in defm PVSRA : RVSm<"pvsra", 0xf6, V64, VM512_, VM512>; +let cx = 1, cx2 = 0 in defm PVSRAUP : RVSm<"pvsra.up", 0xf6, F32, V64, VM_, VM>; +let cx = 1, cx2 = 1 in defm PVSRA : RVSm<"pvsra", 0xf6, I64, V64, VM512_, VM512>; def : MnemonicAlias<"pvsra.lo.sx", "vsra.w.sx">; def : MnemonicAlias<"vsra.w.zx", "pvsra.lo">; def : MnemonicAlias<"vsra.w", "pvsra.lo">; def : MnemonicAlias<"pvsra.lo.zx", "pvsra.lo">; // Section 8.12.8 - VSRAX (Vector Shift Right Arithmetic) -defm VSRAL : RVSm<"vsra.l", 0xd5, V64, VM_, VM>; +defm VSRAL : RVSm<"vsra.l", 0xd5, I64, V64, VM_, VM>; // Section 8.12.9 - VSFA (Vector Shift Left and Add) defm VSFA : RVSAm<"vsfa", 0xd7, V64, VM_, VM>; diff --git a/llvm/lib/Target/VE/VEInstrVecVL.gen.td b/llvm/lib/Target/VE/VEInstrVecVL.gen.td index 5cdfb8f3bc49..04743d5190da 100644 --- a/llvm/lib/Target/VE/VEInstrVecVL.gen.td +++ b/llvm/lib/Target/VE/VEInstrVecVL.gen.td @@ -6164,7 +6164,7 @@ def veoldVSLAWSXvvl_v : RV<0xe6, (outs V64:$vx), (ins V64:$vz, V64:$vy, I32:$vl, } // inst=VSLA asm=vsla.w.sx intrisic=vslawsx_vvsl -def veoldVSLAWSXvrl : RV<0xe6, (outs V64:$vx), (ins V64:$vz, I64:$sy, I32:$vl), +def veoldVSLAWSXvrl : RV<0xe6, (outs V64:$vx), (ins V64:$vz, I32:$sy, I32:$vl), "vsla.w.sx $vx,$vz,$sy", [], NoItinerary> { let DecoderNamespace = "VEL"; @@ -6173,7 +6173,7 @@ def veoldVSLAWSXvrl : RV<0xe6, (outs V64:$vx), (ins V64:$vz, I64:$sy, I32:$vl), } // inst=VSLA asm=vsla.w.sx intrisic=vslawsx_vvsvl -def veoldVSLAWSXvrl_v : RV<0xe6, (outs V64:$vx), (ins V64:$vz, I64:$sy, I32:$vl, V64:$pt), +def veoldVSLAWSXvrl_v : RV<0xe6, (outs V64:$vx), (ins V64:$vz, I32:$sy, I32:$vl, V64:$pt), "vsla.w.sx $vx,$vz,$sy", [], NoItinerary> { let Constraints = "$vx = $pt"; @@ -6212,7 +6212,7 @@ def veoldVSLAWSXvvxl_v : RV<0xe6, (outs V64:$vx), (ins V64:$vz, V64:$vy, VM:$vm, } // inst=VSLA asm=vsla.w.sx intrisic=vslawsx_vvsmvl -def veoldVSLAWSXvrxl_v : RV<0xe6, (outs V64:$vx), (ins V64:$vz, I64:$sy, VM:$vm, I32:$vl, V64:$pt), +def veoldVSLAWSXvrxl_v : RV<0xe6, (outs V64:$vx), (ins V64:$vz, I32:$sy, VM:$vm, I32:$vl, V64:$pt), "vsla.w.sx $vx,$vz,$sy,$vm", [], NoItinerary> { let Constraints = "$vx = $pt"; @@ -6251,7 +6251,7 @@ def veoldVSLAWZXvvl_v : RV<0xe6, (outs V64:$vx), (ins V64:$vz, V64:$vy, I32:$vl, } // inst=VSLA asm=vsla.w.zx intrisic=vslawzx_vvsl -def veoldVSLAWZXvrl : RV<0xe6, (outs V64:$vx), (ins V64:$vz, I64:$sy, I32:$vl), +def veoldVSLAWZXvrl : RV<0xe6, (outs V64:$vx), (ins V64:$vz, I32:$sy, I32:$vl), "vsla.w.zx $vx,$vz,$sy", [], NoItinerary> { let DecoderNamespace = "VEL"; @@ -6260,7 +6260,7 @@ def veoldVSLAWZXvrl : RV<0xe6, (outs V64:$vx), (ins V64:$vz, I64:$sy, I32:$vl), } // inst=VSLA asm=vsla.w.zx intrisic=vslawzx_vvsvl -def veoldVSLAWZXvrl_v : RV<0xe6, (outs V64:$vx), (ins V64:$vz, I64:$sy, I32:$vl, V64:$pt), +def veoldVSLAWZXvrl_v : RV<0xe6, (outs V64:$vx), (ins V64:$vz, I32:$sy, I32:$vl, V64:$pt), "vsla.w.zx $vx,$vz,$sy", [], NoItinerary> { let Constraints = "$vx = $pt"; @@ -6299,7 +6299,7 @@ def veoldVSLAWZXvvxl_v : RV<0xe6, (outs V64:$vx), (ins V64:$vz, V64:$vy, VM:$vm, } // inst=VSLA asm=vsla.w.zx intrisic=vslawzx_vvsmvl -def veoldVSLAWZXvrxl_v : RV<0xe6, (outs V64:$vx), (ins V64:$vz, I64:$sy, VM:$vm, I32:$vl, V64:$pt), +def veoldVSLAWZXvrxl_v : RV<0xe6, (outs V64:$vx), (ins V64:$vz, I32:$sy, VM:$vm, I32:$vl, V64:$pt), "vsla.w.zx $vx,$vz,$sy,$vm", [], NoItinerary> { let Constraints = "$vx = $pt"; @@ -6483,7 +6483,7 @@ def veoldVSRAWSXvvl_v : RV<0xf6, (outs V64:$vx), (ins V64:$vz, V64:$vy, I32:$vl, } // inst=VSRA asm=vsra.w.sx intrisic=vsrawsx_vvsl -def veoldVSRAWSXvrl : RV<0xf6, (outs V64:$vx), (ins V64:$vz, I64:$sy, I32:$vl), +def veoldVSRAWSXvrl : RV<0xf6, (outs V64:$vx), (ins V64:$vz, I32:$sy, I32:$vl), "vsra.w.sx $vx,$vz,$sy", [], NoItinerary> { let DecoderNamespace = "VEL"; @@ -6492,7 +6492,7 @@ def veoldVSRAWSXvrl : RV<0xf6, (outs V64:$vx), (ins V64:$vz, I64:$sy, I32:$vl), } // inst=VSRA asm=vsra.w.sx intrisic=vsrawsx_vvsvl -def veoldVSRAWSXvrl_v : RV<0xf6, (outs V64:$vx), (ins V64:$vz, I64:$sy, I32:$vl, V64:$pt), +def veoldVSRAWSXvrl_v : RV<0xf6, (outs V64:$vx), (ins V64:$vz, I32:$sy, I32:$vl, V64:$pt), "vsra.w.sx $vx,$vz,$sy", [], NoItinerary> { let Constraints = "$vx = $pt"; @@ -6531,7 +6531,7 @@ def veoldVSRAWSXvvxl_v : RV<0xf6, (outs V64:$vx), (ins V64:$vz, V64:$vy, VM:$vm, } // inst=VSRA asm=vsra.w.sx intrisic=vsrawsx_vvsmvl -def veoldVSRAWSXvrxl_v : RV<0xf6, (outs V64:$vx), (ins V64:$vz, I64:$sy, VM:$vm, I32:$vl, V64:$pt), +def veoldVSRAWSXvrxl_v : RV<0xf6, (outs V64:$vx), (ins V64:$vz, I32:$sy, VM:$vm, I32:$vl, V64:$pt), "vsra.w.sx $vx,$vz,$sy,$vm", [], NoItinerary> { let Constraints = "$vx = $pt"; @@ -6570,7 +6570,7 @@ def veoldVSRAWZXvvl_v : RV<0xf6, (outs V64:$vx), (ins V64:$vz, V64:$vy, I32:$vl, } // inst=VSRA asm=vsra.w.zx intrisic=vsrawzx_vvsl -def veoldVSRAWZXvrl : RV<0xf6, (outs V64:$vx), (ins V64:$vz, I64:$sy, I32:$vl), +def veoldVSRAWZXvrl : RV<0xf6, (outs V64:$vx), (ins V64:$vz, I32:$sy, I32:$vl), "vsra.w.zx $vx,$vz,$sy", [], NoItinerary> { let DecoderNamespace = "VEL"; @@ -6579,7 +6579,7 @@ def veoldVSRAWZXvrl : RV<0xf6, (outs V64:$vx), (ins V64:$vz, I64:$sy, I32:$vl), } // inst=VSRA asm=vsra.w.zx intrisic=vsrawzx_vvsvl -def veoldVSRAWZXvrl_v : RV<0xf6, (outs V64:$vx), (ins V64:$vz, I64:$sy, I32:$vl, V64:$pt), +def veoldVSRAWZXvrl_v : RV<0xf6, (outs V64:$vx), (ins V64:$vz, I32:$sy, I32:$vl, V64:$pt), "vsra.w.zx $vx,$vz,$sy", [], NoItinerary> { let Constraints = "$vx = $pt"; @@ -6618,7 +6618,7 @@ def veoldVSRAWZXvvxl_v : RV<0xf6, (outs V64:$vx), (ins V64:$vz, V64:$vy, VM:$vm, } // inst=VSRA asm=vsra.w.zx intrisic=vsrawzx_vvsmvl -def veoldVSRAWZXvrxl_v : RV<0xf6, (outs V64:$vx), (ins V64:$vz, I64:$sy, VM:$vm, I32:$vl, V64:$pt), +def veoldVSRAWZXvrxl_v : RV<0xf6, (outs V64:$vx), (ins V64:$vz, I32:$sy, VM:$vm, I32:$vl, V64:$pt), "vsra.w.zx $vx,$vz,$sy,$vm", [], NoItinerary> { let Constraints = "$vx = $pt"; diff --git a/llvm/lib/Target/VE/veintrin.py b/llvm/lib/Target/VE/veintrin.py index d53e8d9c032b..86bf1119335b 100755 --- a/llvm/lib/Target/VE/veintrin.py +++ b/llvm/lib/Target/VE/veintrin.py @@ -1043,7 +1043,7 @@ def Logical(self, opc, name, instName, expr): def Shift(self, opc, name, instName, ty, expr): O_vvv = [VX(ty), VZ(ty), VY(T_u64)] - O_vvs = [VX(ty), VZ(ty), SY(T_u64)] + O_vvs = [VX(ty), VZ(ty), SY(ty)] O_vvN = [VX(ty), VZ(ty), ImmN(T_u64)] OL = [O_vvv, O_vvs, O_vvN] diff --git a/llvm/test/CodeGen/VE/gen-velintrin-vslawsx_vvsl.ll b/llvm/test/CodeGen/VE/gen-velintrin-vslawsx_vvsl.ll index e87a3964247e..223b17e51234 100644 --- a/llvm/test/CodeGen/VE/gen-velintrin-vslawsx_vvsl.ll +++ b/llvm/test/CodeGen/VE/gen-velintrin-vslawsx_vvsl.ll @@ -5,7 +5,7 @@ target datalayout = "e-m:e-i64:64-n32:64-S128-v64:64:64-v128:64:64-v256:64:64-v5 target triple = "ve-unknown-linux-gnu" ; Function Attrs: nounwind -define dso_local void @vslawsx_vvsl(i32* %0, i32* %1, i64 %2, i32 signext %3) local_unnamed_addr #0 { +define dso_local void @vslawsx_vvsl(i32* %0, i32* %1, i32 %2, i32 signext %3) local_unnamed_addr #0 { ; CHECK: vsla.w.sx %v0, %v0, %s2 %5 = icmp sgt i32 %3, 0 br i1 %5, label %7, label %6 @@ -22,7 +22,7 @@ define dso_local void @vslawsx_vvsl(i32* %0, i32* %1, i64 %2, i32 signext %3) lo %13 = select i1 %12, i32 %11, i32 256 %14 = bitcast i32* %9 to i8* %15 = tail call <256 x double> @llvm.ve.vl.vldlsx.vssl(i64 4, i8* %14, i32 %13) - %16 = tail call <256 x double> @llvm.ve.vl.vslawsx.vvsl(<256 x double> %15, i64 %2, i32 %13) + %16 = tail call <256 x double> @llvm.ve.vl.vslawsx.vvsl(<256 x double> %15, i32 %2, i32 %13) %17 = bitcast i32* %8 to i8* tail call void @llvm.ve.vl.vstl.vssl(<256 x double> %16, i64 4, i8* %17, i32 %13) %18 = getelementptr inbounds i32, i32* %8, i64 256 @@ -36,7 +36,7 @@ define dso_local void @vslawsx_vvsl(i32* %0, i32* %1, i64 %2, i32 signext %3) lo declare <256 x double> @llvm.ve.vl.vldlsx.vssl(i64, i8*, i32) #1 ; Function Attrs: nounwind readnone -declare <256 x double> @llvm.ve.vl.vslawsx.vvsl(<256 x double>, i64, i32) #2 +declare <256 x double> @llvm.ve.vl.vslawsx.vvsl(<256 x double>, i32, i32) #2 ; Function Attrs: nounwind writeonly declare void @llvm.ve.vl.vstl.vssl(<256 x double>, i64, i8*, i32) #3 diff --git a/llvm/test/CodeGen/VE/gen-velintrin-vslawsx_vvsl_imm.ll b/llvm/test/CodeGen/VE/gen-velintrin-vslawsx_vvsl_imm.ll index 8a9ab1231a24..92cba58c65f2 100644 --- a/llvm/test/CodeGen/VE/gen-velintrin-vslawsx_vvsl_imm.ll +++ b/llvm/test/CodeGen/VE/gen-velintrin-vslawsx_vvsl_imm.ll @@ -22,7 +22,7 @@ define dso_local void @vslawsx_vvsl_imm(i32* %0, i32* %1, i32 signext %2) local_ %12 = select i1 %11, i32 %10, i32 256 %13 = bitcast i32* %8 to i8* %14 = tail call <256 x double> @llvm.ve.vl.vldlsx.vssl(i64 4, i8* %13, i32 %12) - %15 = tail call <256 x double> @llvm.ve.vl.vslawsx.vvsl(<256 x double> %14, i64 3, i32 %12) + %15 = tail call <256 x double> @llvm.ve.vl.vslawsx.vvsl(<256 x double> %14, i32 3, i32 %12) %16 = bitcast i32* %7 to i8* tail call void @llvm.ve.vl.vstl.vssl(<256 x double> %15, i64 4, i8* %16, i32 %12) %17 = getelementptr inbounds i32, i32* %7, i64 256 @@ -36,7 +36,7 @@ define dso_local void @vslawsx_vvsl_imm(i32* %0, i32* %1, i32 signext %2) local_ declare <256 x double> @llvm.ve.vl.vldlsx.vssl(i64, i8*, i32) #1 ; Function Attrs: nounwind readnone -declare <256 x double> @llvm.ve.vl.vslawsx.vvsl(<256 x double>, i64, i32) #2 +declare <256 x double> @llvm.ve.vl.vslawsx.vvsl(<256 x double>, i32, i32) #2 ; Function Attrs: nounwind writeonly declare void @llvm.ve.vl.vstl.vssl(<256 x double>, i64, i8*, i32) #3 diff --git a/llvm/test/CodeGen/VE/gen-velintrin-vslawsx_vvsmvl.ll b/llvm/test/CodeGen/VE/gen-velintrin-vslawsx_vvsmvl.ll index f657e2e5a3cc..31b4cd303b7b 100644 --- a/llvm/test/CodeGen/VE/gen-velintrin-vslawsx_vvsmvl.ll +++ b/llvm/test/CodeGen/VE/gen-velintrin-vslawsx_vvsmvl.ll @@ -5,7 +5,7 @@ target datalayout = "e-m:e-i64:64-n32:64-S128-v64:64:64-v128:64:64-v256:64:64-v5 target triple = "ve-unknown-linux-gnu" ; Function Attrs: nounwind -define dso_local void @vslawsx_vvsmvl(i32* %0, i32* %1, i64 %2, i32* %3, i32* %4, i32 signext %5) local_unnamed_addr #0 { +define dso_local void @vslawsx_vvsmvl(i32* %0, i32* %1, i32 %2, i32* %3, i32* %4, i32 signext %5) local_unnamed_addr #0 { ; CHECK: vsla.w.sx %v2, %v0, %s2, %vm1 %7 = icmp sgt i32 %5, 0 br i1 %7, label %9, label %8 @@ -30,7 +30,7 @@ define dso_local void @vslawsx_vvsmvl(i32* %0, i32* %1, i64 %2, i32* %3, i32* %4 %23 = bitcast i32* %13 to i8* %24 = tail call <256 x double> @llvm.ve.vl.vldlsx.vssl(i64 4, i8* %23, i32 %17) %25 = bitcast i32* %10 to i8* - %26 = tail call <256 x double> @llvm.ve.vl.vslawsx.vvsmvl(<256 x double> %19, i64 %2, <256 x i1> %22, <256 x double> %24, i32 %17) + %26 = tail call <256 x double> @llvm.ve.vl.vslawsx.vvsmvl(<256 x double> %19, i32 %2, <256 x i1> %22, <256 x double> %24, i32 %17) tail call void @llvm.ve.vl.vstl.vssl(<256 x double> %26, i64 4, i8* %25, i32 %17) %27 = getelementptr inbounds i32, i32* %10, i64 256 %28 = getelementptr inbounds i32, i32* %11, i64 256 @@ -51,7 +51,7 @@ declare <256 x double> @llvm.ve.vl.vldlzx.vssl(i64, i8*, i32) #1 declare <256 x i1> @llvm.ve.vl.vfmkwgt.mvl(<256 x double>, i32) #2 ; Function Attrs: nounwind readnone -declare <256 x double> @llvm.ve.vl.vslawsx.vvsmvl(<256 x double>, i64, <256 x i1>, <256 x double>, i32) #2 +declare <256 x double> @llvm.ve.vl.vslawsx.vvsmvl(<256 x double>, i32, <256 x i1>, <256 x double>, i32) #2 ; Function Attrs: nounwind writeonly declare void @llvm.ve.vl.vstl.vssl(<256 x double>, i64, i8*, i32) #3 diff --git a/llvm/test/CodeGen/VE/gen-velintrin-vslawsx_vvsmvl_imm.ll b/llvm/test/CodeGen/VE/gen-velintrin-vslawsx_vvsmvl_imm.ll index 45e7366cd495..80fc9fe64a1f 100644 --- a/llvm/test/CodeGen/VE/gen-velintrin-vslawsx_vvsmvl_imm.ll +++ b/llvm/test/CodeGen/VE/gen-velintrin-vslawsx_vvsmvl_imm.ll @@ -30,7 +30,7 @@ define dso_local void @vslawsx_vvsmvl_imm(i32* %0, i32* %1, i32* %2, i32* %3, i3 %22 = bitcast i32* %12 to i8* %23 = tail call <256 x double> @llvm.ve.vl.vldlsx.vssl(i64 4, i8* %22, i32 %16) %24 = bitcast i32* %9 to i8* - %25 = tail call <256 x double> @llvm.ve.vl.vslawsx.vvsmvl(<256 x double> %18, i64 3, <256 x i1> %21, <256 x double> %23, i32 %16) + %25 = tail call <256 x double> @llvm.ve.vl.vslawsx.vvsmvl(<256 x double> %18, i32 3, <256 x i1> %21, <256 x double> %23, i32 %16) tail call void @llvm.ve.vl.vstl.vssl(<256 x double> %25, i64 4, i8* %24, i32 %16) %26 = getelementptr inbounds i32, i32* %9, i64 256 %27 = getelementptr inbounds i32, i32* %10, i64 256 @@ -51,7 +51,7 @@ declare <256 x double> @llvm.ve.vl.vldlzx.vssl(i64, i8*, i32) #1 declare <256 x i1> @llvm.ve.vl.vfmkwgt.mvl(<256 x double>, i32) #2 ; Function Attrs: nounwind readnone -declare <256 x double> @llvm.ve.vl.vslawsx.vvsmvl(<256 x double>, i64, <256 x i1>, <256 x double>, i32) #2 +declare <256 x double> @llvm.ve.vl.vslawsx.vvsmvl(<256 x double>, i32, <256 x i1>, <256 x double>, i32) #2 ; Function Attrs: nounwind writeonly declare void @llvm.ve.vl.vstl.vssl(<256 x double>, i64, i8*, i32) #3 diff --git a/llvm/test/CodeGen/VE/gen-velintrin-vslawzx_vvsl.ll b/llvm/test/CodeGen/VE/gen-velintrin-vslawzx_vvsl.ll index e6980a7020aa..a94820e42bdd 100644 --- a/llvm/test/CodeGen/VE/gen-velintrin-vslawzx_vvsl.ll +++ b/llvm/test/CodeGen/VE/gen-velintrin-vslawzx_vvsl.ll @@ -5,7 +5,7 @@ target datalayout = "e-m:e-i64:64-n32:64-S128-v64:64:64-v128:64:64-v256:64:64-v5 target triple = "ve-unknown-linux-gnu" ; Function Attrs: nounwind -define dso_local void @vslawzx_vvsl(i32* %0, i32* %1, i64 %2, i32 signext %3) local_unnamed_addr #0 { +define dso_local void @vslawzx_vvsl(i32* %0, i32* %1, i32 %2, i32 signext %3) local_unnamed_addr #0 { ; CHECK: vsla.w.zx %v0, %v0, %s2 %5 = icmp sgt i32 %3, 0 br i1 %5, label %7, label %6 @@ -22,7 +22,7 @@ define dso_local void @vslawzx_vvsl(i32* %0, i32* %1, i64 %2, i32 signext %3) lo %13 = select i1 %12, i32 %11, i32 256 %14 = bitcast i32* %9 to i8* %15 = tail call <256 x double> @llvm.ve.vl.vldlsx.vssl(i64 4, i8* %14, i32 %13) - %16 = tail call <256 x double> @llvm.ve.vl.vslawzx.vvsl(<256 x double> %15, i64 %2, i32 %13) + %16 = tail call <256 x double> @llvm.ve.vl.vslawzx.vvsl(<256 x double> %15, i32 %2, i32 %13) %17 = bitcast i32* %8 to i8* tail call void @llvm.ve.vl.vstl.vssl(<256 x double> %16, i64 4, i8* %17, i32 %13) %18 = getelementptr inbounds i32, i32* %8, i64 256 @@ -36,7 +36,7 @@ define dso_local void @vslawzx_vvsl(i32* %0, i32* %1, i64 %2, i32 signext %3) lo declare <256 x double> @llvm.ve.vl.vldlsx.vssl(i64, i8*, i32) #1 ; Function Attrs: nounwind readnone -declare <256 x double> @llvm.ve.vl.vslawzx.vvsl(<256 x double>, i64, i32) #2 +declare <256 x double> @llvm.ve.vl.vslawzx.vvsl(<256 x double>, i32, i32) #2 ; Function Attrs: nounwind writeonly declare void @llvm.ve.vl.vstl.vssl(<256 x double>, i64, i8*, i32) #3 diff --git a/llvm/test/CodeGen/VE/gen-velintrin-vslawzx_vvsl_imm.ll b/llvm/test/CodeGen/VE/gen-velintrin-vslawzx_vvsl_imm.ll index feeb509584a4..aa8dc280df4b 100644 --- a/llvm/test/CodeGen/VE/gen-velintrin-vslawzx_vvsl_imm.ll +++ b/llvm/test/CodeGen/VE/gen-velintrin-vslawzx_vvsl_imm.ll @@ -22,7 +22,7 @@ define dso_local void @vslawzx_vvsl_imm(i32* %0, i32* %1, i32 signext %2) local_ %12 = select i1 %11, i32 %10, i32 256 %13 = bitcast i32* %8 to i8* %14 = tail call <256 x double> @llvm.ve.vl.vldlsx.vssl(i64 4, i8* %13, i32 %12) - %15 = tail call <256 x double> @llvm.ve.vl.vslawzx.vvsl(<256 x double> %14, i64 3, i32 %12) + %15 = tail call <256 x double> @llvm.ve.vl.vslawzx.vvsl(<256 x double> %14, i32 3, i32 %12) %16 = bitcast i32* %7 to i8* tail call void @llvm.ve.vl.vstl.vssl(<256 x double> %15, i64 4, i8* %16, i32 %12) %17 = getelementptr inbounds i32, i32* %7, i64 256 @@ -36,7 +36,7 @@ define dso_local void @vslawzx_vvsl_imm(i32* %0, i32* %1, i32 signext %2) local_ declare <256 x double> @llvm.ve.vl.vldlsx.vssl(i64, i8*, i32) #1 ; Function Attrs: nounwind readnone -declare <256 x double> @llvm.ve.vl.vslawzx.vvsl(<256 x double>, i64, i32) #2 +declare <256 x double> @llvm.ve.vl.vslawzx.vvsl(<256 x double>, i32, i32) #2 ; Function Attrs: nounwind writeonly declare void @llvm.ve.vl.vstl.vssl(<256 x double>, i64, i8*, i32) #3 diff --git a/llvm/test/CodeGen/VE/gen-velintrin-vslawzx_vvsmvl.ll b/llvm/test/CodeGen/VE/gen-velintrin-vslawzx_vvsmvl.ll index 37711a291544..71d4254d9eb6 100644 --- a/llvm/test/CodeGen/VE/gen-velintrin-vslawzx_vvsmvl.ll +++ b/llvm/test/CodeGen/VE/gen-velintrin-vslawzx_vvsmvl.ll @@ -5,7 +5,7 @@ target datalayout = "e-m:e-i64:64-n32:64-S128-v64:64:64-v128:64:64-v256:64:64-v5 target triple = "ve-unknown-linux-gnu" ; Function Attrs: nounwind -define dso_local void @vslawzx_vvsmvl(i32* %0, i32* %1, i64 %2, i32* %3, i32* %4, i32 signext %5) local_unnamed_addr #0 { +define dso_local void @vslawzx_vvsmvl(i32* %0, i32* %1, i32 %2, i32* %3, i32* %4, i32 signext %5) local_unnamed_addr #0 { ; CHECK: vsla.w.zx %v2, %v0, %s2, %vm1 %7 = icmp sgt i32 %5, 0 br i1 %7, label %9, label %8 @@ -30,7 +30,7 @@ define dso_local void @vslawzx_vvsmvl(i32* %0, i32* %1, i64 %2, i32* %3, i32* %4 %23 = bitcast i32* %13 to i8* %24 = tail call <256 x double> @llvm.ve.vl.vldlsx.vssl(i64 4, i8* %23, i32 %17) %25 = bitcast i32* %10 to i8* - %26 = tail call <256 x double> @llvm.ve.vl.vslawzx.vvsmvl(<256 x double> %19, i64 %2, <256 x i1> %22, <256 x double> %24, i32 %17) + %26 = tail call <256 x double> @llvm.ve.vl.vslawzx.vvsmvl(<256 x double> %19, i32 %2, <256 x i1> %22, <256 x double> %24, i32 %17) tail call void @llvm.ve.vl.vstl.vssl(<256 x double> %26, i64 4, i8* %25, i32 %17) %27 = getelementptr inbounds i32, i32* %10, i64 256 %28 = getelementptr inbounds i32, i32* %11, i64 256 @@ -51,7 +51,7 @@ declare <256 x double> @llvm.ve.vl.vldlzx.vssl(i64, i8*, i32) #1 declare <256 x i1> @llvm.ve.vl.vfmkwgt.mvl(<256 x double>, i32) #2 ; Function Attrs: nounwind readnone -declare <256 x double> @llvm.ve.vl.vslawzx.vvsmvl(<256 x double>, i64, <256 x i1>, <256 x double>, i32) #2 +declare <256 x double> @llvm.ve.vl.vslawzx.vvsmvl(<256 x double>, i32, <256 x i1>, <256 x double>, i32) #2 ; Function Attrs: nounwind writeonly declare void @llvm.ve.vl.vstl.vssl(<256 x double>, i64, i8*, i32) #3 diff --git a/llvm/test/CodeGen/VE/gen-velintrin-vslawzx_vvsmvl_imm.ll b/llvm/test/CodeGen/VE/gen-velintrin-vslawzx_vvsmvl_imm.ll index c87cfc5f22e7..af6f2e0aeaef 100644 --- a/llvm/test/CodeGen/VE/gen-velintrin-vslawzx_vvsmvl_imm.ll +++ b/llvm/test/CodeGen/VE/gen-velintrin-vslawzx_vvsmvl_imm.ll @@ -30,7 +30,7 @@ define dso_local void @vslawzx_vvsmvl_imm(i32* %0, i32* %1, i32* %2, i32* %3, i3 %22 = bitcast i32* %12 to i8* %23 = tail call <256 x double> @llvm.ve.vl.vldlsx.vssl(i64 4, i8* %22, i32 %16) %24 = bitcast i32* %9 to i8* - %25 = tail call <256 x double> @llvm.ve.vl.vslawzx.vvsmvl(<256 x double> %18, i64 3, <256 x i1> %21, <256 x double> %23, i32 %16) + %25 = tail call <256 x double> @llvm.ve.vl.vslawzx.vvsmvl(<256 x double> %18, i32 3, <256 x i1> %21, <256 x double> %23, i32 %16) tail call void @llvm.ve.vl.vstl.vssl(<256 x double> %25, i64 4, i8* %24, i32 %16) %26 = getelementptr inbounds i32, i32* %9, i64 256 %27 = getelementptr inbounds i32, i32* %10, i64 256 @@ -51,7 +51,7 @@ declare <256 x double> @llvm.ve.vl.vldlzx.vssl(i64, i8*, i32) #1 declare <256 x i1> @llvm.ve.vl.vfmkwgt.mvl(<256 x double>, i32) #2 ; Function Attrs: nounwind readnone -declare <256 x double> @llvm.ve.vl.vslawzx.vvsmvl(<256 x double>, i64, <256 x i1>, <256 x double>, i32) #2 +declare <256 x double> @llvm.ve.vl.vslawzx.vvsmvl(<256 x double>, i32, <256 x i1>, <256 x double>, i32) #2 ; Function Attrs: nounwind writeonly declare void @llvm.ve.vl.vstl.vssl(<256 x double>, i64, i8*, i32) #3 diff --git a/llvm/test/CodeGen/VE/gen-velintrin-vsrawsx_vvsl.ll b/llvm/test/CodeGen/VE/gen-velintrin-vsrawsx_vvsl.ll index 88cc9d24a0e8..df25a40ebf12 100644 --- a/llvm/test/CodeGen/VE/gen-velintrin-vsrawsx_vvsl.ll +++ b/llvm/test/CodeGen/VE/gen-velintrin-vsrawsx_vvsl.ll @@ -5,7 +5,7 @@ target datalayout = "e-m:e-i64:64-n32:64-S128-v64:64:64-v128:64:64-v256:64:64-v5 target triple = "ve-unknown-linux-gnu" ; Function Attrs: nounwind -define dso_local void @vsrawsx_vvsl(i32* %0, i32* %1, i64 %2, i32 signext %3) local_unnamed_addr #0 { +define dso_local void @vsrawsx_vvsl(i32* %0, i32* %1, i32 %2, i32 signext %3) local_unnamed_addr #0 { ; CHECK: vsra.w.sx %v0, %v0, %s2 %5 = icmp sgt i32 %3, 0 br i1 %5, label %7, label %6 @@ -22,7 +22,7 @@ define dso_local void @vsrawsx_vvsl(i32* %0, i32* %1, i64 %2, i32 signext %3) lo %13 = select i1 %12, i32 %11, i32 256 %14 = bitcast i32* %9 to i8* %15 = tail call <256 x double> @llvm.ve.vl.vldlsx.vssl(i64 4, i8* %14, i32 %13) - %16 = tail call <256 x double> @llvm.ve.vl.vsrawsx.vvsl(<256 x double> %15, i64 %2, i32 %13) + %16 = tail call <256 x double> @llvm.ve.vl.vsrawsx.vvsl(<256 x double> %15, i32 %2, i32 %13) %17 = bitcast i32* %8 to i8* tail call void @llvm.ve.vl.vstl.vssl(<256 x double> %16, i64 4, i8* %17, i32 %13) %18 = getelementptr inbounds i32, i32* %8, i64 256 @@ -36,7 +36,7 @@ define dso_local void @vsrawsx_vvsl(i32* %0, i32* %1, i64 %2, i32 signext %3) lo declare <256 x double> @llvm.ve.vl.vldlsx.vssl(i64, i8*, i32) #1 ; Function Attrs: nounwind readnone -declare <256 x double> @llvm.ve.vl.vsrawsx.vvsl(<256 x double>, i64, i32) #2 +declare <256 x double> @llvm.ve.vl.vsrawsx.vvsl(<256 x double>, i32, i32) #2 ; Function Attrs: nounwind writeonly declare void @llvm.ve.vl.vstl.vssl(<256 x double>, i64, i8*, i32) #3 diff --git a/llvm/test/CodeGen/VE/gen-velintrin-vsrawsx_vvsl_imm.ll b/llvm/test/CodeGen/VE/gen-velintrin-vsrawsx_vvsl_imm.ll index 24d69bf4076d..ab6675e4cd3f 100644 --- a/llvm/test/CodeGen/VE/gen-velintrin-vsrawsx_vvsl_imm.ll +++ b/llvm/test/CodeGen/VE/gen-velintrin-vsrawsx_vvsl_imm.ll @@ -22,7 +22,7 @@ define dso_local void @vsrawsx_vvsl_imm(i32* %0, i32* %1, i32 signext %2) local_ %12 = select i1 %11, i32 %10, i32 256 %13 = bitcast i32* %8 to i8* %14 = tail call <256 x double> @llvm.ve.vl.vldlsx.vssl(i64 4, i8* %13, i32 %12) - %15 = tail call <256 x double> @llvm.ve.vl.vsrawsx.vvsl(<256 x double> %14, i64 3, i32 %12) + %15 = tail call <256 x double> @llvm.ve.vl.vsrawsx.vvsl(<256 x double> %14, i32 3, i32 %12) %16 = bitcast i32* %7 to i8* tail call void @llvm.ve.vl.vstl.vssl(<256 x double> %15, i64 4, i8* %16, i32 %12) %17 = getelementptr inbounds i32, i32* %7, i64 256 @@ -36,7 +36,7 @@ define dso_local void @vsrawsx_vvsl_imm(i32* %0, i32* %1, i32 signext %2) local_ declare <256 x double> @llvm.ve.vl.vldlsx.vssl(i64, i8*, i32) #1 ; Function Attrs: nounwind readnone -declare <256 x double> @llvm.ve.vl.vsrawsx.vvsl(<256 x double>, i64, i32) #2 +declare <256 x double> @llvm.ve.vl.vsrawsx.vvsl(<256 x double>, i32, i32) #2 ; Function Attrs: nounwind writeonly declare void @llvm.ve.vl.vstl.vssl(<256 x double>, i64, i8*, i32) #3 diff --git a/llvm/test/CodeGen/VE/gen-velintrin-vsrawsx_vvsmvl.ll b/llvm/test/CodeGen/VE/gen-velintrin-vsrawsx_vvsmvl.ll index 092e00863779..12ad4181af28 100644 --- a/llvm/test/CodeGen/VE/gen-velintrin-vsrawsx_vvsmvl.ll +++ b/llvm/test/CodeGen/VE/gen-velintrin-vsrawsx_vvsmvl.ll @@ -5,7 +5,7 @@ target datalayout = "e-m:e-i64:64-n32:64-S128-v64:64:64-v128:64:64-v256:64:64-v5 target triple = "ve-unknown-linux-gnu" ; Function Attrs: nounwind -define dso_local void @vsrawsx_vvsmvl(i32* %0, i32* %1, i64 %2, i32* %3, i32* %4, i32 signext %5) local_unnamed_addr #0 { +define dso_local void @vsrawsx_vvsmvl(i32* %0, i32* %1, i32 %2, i32* %3, i32* %4, i32 signext %5) local_unnamed_addr #0 { ; CHECK: vsra.w.sx %v2, %v0, %s2, %vm1 %7 = icmp sgt i32 %5, 0 br i1 %7, label %9, label %8 @@ -30,7 +30,7 @@ define dso_local void @vsrawsx_vvsmvl(i32* %0, i32* %1, i64 %2, i32* %3, i32* %4 %23 = bitcast i32* %13 to i8* %24 = tail call <256 x double> @llvm.ve.vl.vldlsx.vssl(i64 4, i8* %23, i32 %17) %25 = bitcast i32* %10 to i8* - %26 = tail call <256 x double> @llvm.ve.vl.vsrawsx.vvsmvl(<256 x double> %19, i64 %2, <256 x i1> %22, <256 x double> %24, i32 %17) + %26 = tail call <256 x double> @llvm.ve.vl.vsrawsx.vvsmvl(<256 x double> %19, i32 %2, <256 x i1> %22, <256 x double> %24, i32 %17) tail call void @llvm.ve.vl.vstl.vssl(<256 x double> %26, i64 4, i8* %25, i32 %17) %27 = getelementptr inbounds i32, i32* %10, i64 256 %28 = getelementptr inbounds i32, i32* %11, i64 256 @@ -51,7 +51,7 @@ declare <256 x double> @llvm.ve.vl.vldlzx.vssl(i64, i8*, i32) #1 declare <256 x i1> @llvm.ve.vl.vfmkwgt.mvl(<256 x double>, i32) #2 ; Function Attrs: nounwind readnone -declare <256 x double> @llvm.ve.vl.vsrawsx.vvsmvl(<256 x double>, i64, <256 x i1>, <256 x double>, i32) #2 +declare <256 x double> @llvm.ve.vl.vsrawsx.vvsmvl(<256 x double>, i32, <256 x i1>, <256 x double>, i32) #2 ; Function Attrs: nounwind writeonly declare void @llvm.ve.vl.vstl.vssl(<256 x double>, i64, i8*, i32) #3 diff --git a/llvm/test/CodeGen/VE/gen-velintrin-vsrawsx_vvsmvl_imm.ll b/llvm/test/CodeGen/VE/gen-velintrin-vsrawsx_vvsmvl_imm.ll index 8d0991ae5f84..33e2ec7566ea 100644 --- a/llvm/test/CodeGen/VE/gen-velintrin-vsrawsx_vvsmvl_imm.ll +++ b/llvm/test/CodeGen/VE/gen-velintrin-vsrawsx_vvsmvl_imm.ll @@ -30,7 +30,7 @@ define dso_local void @vsrawsx_vvsmvl_imm(i32* %0, i32* %1, i32* %2, i32* %3, i3 %22 = bitcast i32* %12 to i8* %23 = tail call <256 x double> @llvm.ve.vl.vldlsx.vssl(i64 4, i8* %22, i32 %16) %24 = bitcast i32* %9 to i8* - %25 = tail call <256 x double> @llvm.ve.vl.vsrawsx.vvsmvl(<256 x double> %18, i64 3, <256 x i1> %21, <256 x double> %23, i32 %16) + %25 = tail call <256 x double> @llvm.ve.vl.vsrawsx.vvsmvl(<256 x double> %18, i32 3, <256 x i1> %21, <256 x double> %23, i32 %16) tail call void @llvm.ve.vl.vstl.vssl(<256 x double> %25, i64 4, i8* %24, i32 %16) %26 = getelementptr inbounds i32, i32* %9, i64 256 %27 = getelementptr inbounds i32, i32* %10, i64 256 @@ -51,7 +51,7 @@ declare <256 x double> @llvm.ve.vl.vldlzx.vssl(i64, i8*, i32) #1 declare <256 x i1> @llvm.ve.vl.vfmkwgt.mvl(<256 x double>, i32) #2 ; Function Attrs: nounwind readnone -declare <256 x double> @llvm.ve.vl.vsrawsx.vvsmvl(<256 x double>, i64, <256 x i1>, <256 x double>, i32) #2 +declare <256 x double> @llvm.ve.vl.vsrawsx.vvsmvl(<256 x double>, i32, <256 x i1>, <256 x double>, i32) #2 ; Function Attrs: nounwind writeonly declare void @llvm.ve.vl.vstl.vssl(<256 x double>, i64, i8*, i32) #3 diff --git a/llvm/test/CodeGen/VE/gen-velintrin-vsrawzx_vvsl.ll b/llvm/test/CodeGen/VE/gen-velintrin-vsrawzx_vvsl.ll index 5e424f01d521..3743e702e79c 100644 --- a/llvm/test/CodeGen/VE/gen-velintrin-vsrawzx_vvsl.ll +++ b/llvm/test/CodeGen/VE/gen-velintrin-vsrawzx_vvsl.ll @@ -5,7 +5,7 @@ target datalayout = "e-m:e-i64:64-n32:64-S128-v64:64:64-v128:64:64-v256:64:64-v5 target triple = "ve-unknown-linux-gnu" ; Function Attrs: nounwind -define dso_local void @vsrawzx_vvsl(i32* %0, i32* %1, i64 %2, i32 signext %3) local_unnamed_addr #0 { +define dso_local void @vsrawzx_vvsl(i32* %0, i32* %1, i32 %2, i32 signext %3) local_unnamed_addr #0 { ; CHECK: vsra.w.zx %v0, %v0, %s2 %5 = icmp sgt i32 %3, 0 br i1 %5, label %7, label %6 @@ -22,7 +22,7 @@ define dso_local void @vsrawzx_vvsl(i32* %0, i32* %1, i64 %2, i32 signext %3) lo %13 = select i1 %12, i32 %11, i32 256 %14 = bitcast i32* %9 to i8* %15 = tail call <256 x double> @llvm.ve.vl.vldlsx.vssl(i64 4, i8* %14, i32 %13) - %16 = tail call <256 x double> @llvm.ve.vl.vsrawzx.vvsl(<256 x double> %15, i64 %2, i32 %13) + %16 = tail call <256 x double> @llvm.ve.vl.vsrawzx.vvsl(<256 x double> %15, i32 %2, i32 %13) %17 = bitcast i32* %8 to i8* tail call void @llvm.ve.vl.vstl.vssl(<256 x double> %16, i64 4, i8* %17, i32 %13) %18 = getelementptr inbounds i32, i32* %8, i64 256 @@ -36,7 +36,7 @@ define dso_local void @vsrawzx_vvsl(i32* %0, i32* %1, i64 %2, i32 signext %3) lo declare <256 x double> @llvm.ve.vl.vldlsx.vssl(i64, i8*, i32) #1 ; Function Attrs: nounwind readnone -declare <256 x double> @llvm.ve.vl.vsrawzx.vvsl(<256 x double>, i64, i32) #2 +declare <256 x double> @llvm.ve.vl.vsrawzx.vvsl(<256 x double>, i32, i32) #2 ; Function Attrs: nounwind writeonly declare void @llvm.ve.vl.vstl.vssl(<256 x double>, i64, i8*, i32) #3 diff --git a/llvm/test/CodeGen/VE/gen-velintrin-vsrawzx_vvsl_imm.ll b/llvm/test/CodeGen/VE/gen-velintrin-vsrawzx_vvsl_imm.ll index 7eeeb77f54b1..b39c9f655789 100644 --- a/llvm/test/CodeGen/VE/gen-velintrin-vsrawzx_vvsl_imm.ll +++ b/llvm/test/CodeGen/VE/gen-velintrin-vsrawzx_vvsl_imm.ll @@ -22,7 +22,7 @@ define dso_local void @vsrawzx_vvsl_imm(i32* %0, i32* %1, i32 signext %2) local_ %12 = select i1 %11, i32 %10, i32 256 %13 = bitcast i32* %8 to i8* %14 = tail call <256 x double> @llvm.ve.vl.vldlsx.vssl(i64 4, i8* %13, i32 %12) - %15 = tail call <256 x double> @llvm.ve.vl.vsrawzx.vvsl(<256 x double> %14, i64 3, i32 %12) + %15 = tail call <256 x double> @llvm.ve.vl.vsrawzx.vvsl(<256 x double> %14, i32 3, i32 %12) %16 = bitcast i32* %7 to i8* tail call void @llvm.ve.vl.vstl.vssl(<256 x double> %15, i64 4, i8* %16, i32 %12) %17 = getelementptr inbounds i32, i32* %7, i64 256 @@ -36,7 +36,7 @@ define dso_local void @vsrawzx_vvsl_imm(i32* %0, i32* %1, i32 signext %2) local_ declare <256 x double> @llvm.ve.vl.vldlsx.vssl(i64, i8*, i32) #1 ; Function Attrs: nounwind readnone -declare <256 x double> @llvm.ve.vl.vsrawzx.vvsl(<256 x double>, i64, i32) #2 +declare <256 x double> @llvm.ve.vl.vsrawzx.vvsl(<256 x double>, i32, i32) #2 ; Function Attrs: nounwind writeonly declare void @llvm.ve.vl.vstl.vssl(<256 x double>, i64, i8*, i32) #3 diff --git a/llvm/test/CodeGen/VE/gen-velintrin-vsrawzx_vvsmvl.ll b/llvm/test/CodeGen/VE/gen-velintrin-vsrawzx_vvsmvl.ll index fa2af363af5f..3c090e4c8873 100644 --- a/llvm/test/CodeGen/VE/gen-velintrin-vsrawzx_vvsmvl.ll +++ b/llvm/test/CodeGen/VE/gen-velintrin-vsrawzx_vvsmvl.ll @@ -5,7 +5,7 @@ target datalayout = "e-m:e-i64:64-n32:64-S128-v64:64:64-v128:64:64-v256:64:64-v5 target triple = "ve-unknown-linux-gnu" ; Function Attrs: nounwind -define dso_local void @vsrawzx_vvsmvl(i32* %0, i32* %1, i64 %2, i32* %3, i32* %4, i32 signext %5) local_unnamed_addr #0 { +define dso_local void @vsrawzx_vvsmvl(i32* %0, i32* %1, i32 %2, i32* %3, i32* %4, i32 signext %5) local_unnamed_addr #0 { ; CHECK: vsra.w.zx %v2, %v0, %s2, %vm1 %7 = icmp sgt i32 %5, 0 br i1 %7, label %9, label %8 @@ -30,7 +30,7 @@ define dso_local void @vsrawzx_vvsmvl(i32* %0, i32* %1, i64 %2, i32* %3, i32* %4 %23 = bitcast i32* %13 to i8* %24 = tail call <256 x double> @llvm.ve.vl.vldlsx.vssl(i64 4, i8* %23, i32 %17) %25 = bitcast i32* %10 to i8* - %26 = tail call <256 x double> @llvm.ve.vl.vsrawzx.vvsmvl(<256 x double> %19, i64 %2, <256 x i1> %22, <256 x double> %24, i32 %17) + %26 = tail call <256 x double> @llvm.ve.vl.vsrawzx.vvsmvl(<256 x double> %19, i32 %2, <256 x i1> %22, <256 x double> %24, i32 %17) tail call void @llvm.ve.vl.vstl.vssl(<256 x double> %26, i64 4, i8* %25, i32 %17) %27 = getelementptr inbounds i32, i32* %10, i64 256 %28 = getelementptr inbounds i32, i32* %11, i64 256 @@ -51,7 +51,7 @@ declare <256 x double> @llvm.ve.vl.vldlzx.vssl(i64, i8*, i32) #1 declare <256 x i1> @llvm.ve.vl.vfmkwgt.mvl(<256 x double>, i32) #2 ; Function Attrs: nounwind readnone -declare <256 x double> @llvm.ve.vl.vsrawzx.vvsmvl(<256 x double>, i64, <256 x i1>, <256 x double>, i32) #2 +declare <256 x double> @llvm.ve.vl.vsrawzx.vvsmvl(<256 x double>, i32, <256 x i1>, <256 x double>, i32) #2 ; Function Attrs: nounwind writeonly declare void @llvm.ve.vl.vstl.vssl(<256 x double>, i64, i8*, i32) #3 diff --git a/llvm/test/CodeGen/VE/gen-velintrin-vsrawzx_vvsmvl_imm.ll b/llvm/test/CodeGen/VE/gen-velintrin-vsrawzx_vvsmvl_imm.ll index 56d3b62832d8..48337f1bb2e3 100644 --- a/llvm/test/CodeGen/VE/gen-velintrin-vsrawzx_vvsmvl_imm.ll +++ b/llvm/test/CodeGen/VE/gen-velintrin-vsrawzx_vvsmvl_imm.ll @@ -30,7 +30,7 @@ define dso_local void @vsrawzx_vvsmvl_imm(i32* %0, i32* %1, i32* %2, i32* %3, i3 %22 = bitcast i32* %12 to i8* %23 = tail call <256 x double> @llvm.ve.vl.vldlsx.vssl(i64 4, i8* %22, i32 %16) %24 = bitcast i32* %9 to i8* - %25 = tail call <256 x double> @llvm.ve.vl.vsrawzx.vvsmvl(<256 x double> %18, i64 3, <256 x i1> %21, <256 x double> %23, i32 %16) + %25 = tail call <256 x double> @llvm.ve.vl.vsrawzx.vvsmvl(<256 x double> %18, i32 3, <256 x i1> %21, <256 x double> %23, i32 %16) tail call void @llvm.ve.vl.vstl.vssl(<256 x double> %25, i64 4, i8* %24, i32 %16) %26 = getelementptr inbounds i32, i32* %9, i64 256 %27 = getelementptr inbounds i32, i32* %10, i64 256 @@ -51,7 +51,7 @@ declare <256 x double> @llvm.ve.vl.vldlzx.vssl(i64, i8*, i32) #1 declare <256 x i1> @llvm.ve.vl.vfmkwgt.mvl(<256 x double>, i32) #2 ; Function Attrs: nounwind readnone -declare <256 x double> @llvm.ve.vl.vsrawzx.vvsmvl(<256 x double>, i64, <256 x i1>, <256 x double>, i32) #2 +declare <256 x double> @llvm.ve.vl.vsrawzx.vvsmvl(<256 x double>, i32, <256 x i1>, <256 x double>, i32) #2 ; Function Attrs: nounwind writeonly declare void @llvm.ve.vl.vstl.vssl(<256 x double>, i64, i8*, i32) #3 From c8b71d2f4579a519fa6922a5b51b5a9f62853c7d Mon Sep 17 00:00:00 2001 From: Simon Moll Date: Wed, 21 Oct 2020 11:35:09 +0200 Subject: [PATCH 2/2] [ve] updated build_vec(_2) test (reg names, inst order) --- llvm/test/CodeGen/VE/build_vec.ll | 24 ++++++++++++------------ llvm/test/CodeGen/VE/build_vec_2.ll | 16 ++++++++-------- 2 files changed, 20 insertions(+), 20 deletions(-) diff --git a/llvm/test/CodeGen/VE/build_vec.ll b/llvm/test/CodeGen/VE/build_vec.ll index ed698f0a57d6..5e966fc9c989 100644 --- a/llvm/test/CodeGen/VE/build_vec.ll +++ b/llvm/test/CodeGen/VE/build_vec.ll @@ -936,11 +936,11 @@ entry: define i32 @vseqsrl_v4i32() { ; CHECK-LABEL: vseqsrl_v4i32: ; CHECK: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: or %s0, 1, (0)1 -; CHECK-NEXT: lea %s1, 4 -; CHECK-NEXT: lvl %s1 +; CHECK-NEXT: lea %s0, 4 +; CHECK-NEXT: lvl %s0 ; CHECK-NEXT: pvseq.lo %v0 -; CHECK-NEXT: pvsrl.lo %v0, %v0, %s0 +; CHECK-NEXT: or %s1, 1, (0)1 +; CHECK-NEXT: pvsrl.lo %v0, %v0, %s1 ; CHECK-NEXT: lea %s0, calc_v4i32@lo ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: lea.sl %s12, calc_v4i32@hi(, %s0) @@ -957,11 +957,11 @@ entry: define i32 @vseqsrl_v8i32() { ; CHECK-LABEL: vseqsrl_v8i32: ; CHECK: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: or %s0, 1, (0)1 -; CHECK-NEXT: lea %s1, 8 -; CHECK-NEXT: lvl %s1 +; CHECK-NEXT: lea %s0, 8 +; CHECK-NEXT: lvl %s0 ; CHECK-NEXT: pvseq.lo %v0 -; CHECK-NEXT: pvsrl.lo %v0, %v0, %s0 +; CHECK-NEXT: or %s1, 1, (0)1 +; CHECK-NEXT: pvsrl.lo %v0, %v0, %s1 ; CHECK-NEXT: lea %s0, calc_v8i32@lo ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: lea.sl %s12, calc_v8i32@hi(, %s0) @@ -978,11 +978,11 @@ entry: define i32 @vseqsrl_v256i32() { ; CHECK-LABEL: vseqsrl_v256i32: ; CHECK: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: or %s0, 1, (0)1 -; CHECK-NEXT: lea %s1, 256 -; CHECK-NEXT: lvl %s1 +; CHECK-NEXT: lea %s0, 256 +; CHECK-NEXT: lvl %s0 ; CHECK-NEXT: pvseq.lo %v0 -; CHECK-NEXT: pvsrl.lo %v0, %v0, %s0 +; CHECK-NEXT: or %s1, 1, (0)1 +; CHECK-NEXT: pvsrl.lo %v0, %v0, %s1 ; CHECK-NEXT: lea %s0, calc_v256i32@lo ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: lea.sl %s12, calc_v256i32@hi(, %s0) diff --git a/llvm/test/CodeGen/VE/build_vec_2.ll b/llvm/test/CodeGen/VE/build_vec_2.ll index 67f4e7cb8aeb..2d7ef20d694a 100644 --- a/llvm/test/CodeGen/VE/build_vec_2.ll +++ b/llvm/test/CodeGen/VE/build_vec_2.ll @@ -112,11 +112,11 @@ entry: define i32 @vseqsrl_v4i32() { ; CHECK-LABEL: vseqsrl_v4i32: ; CHECK: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: or %s0, 1, (0)1 -; CHECK-NEXT: lea %s1, 4 -; CHECK-NEXT: lvl %s1 +; CHECK-NEXT: lea %s0, 4 +; CHECK-NEXT: lvl %s0 ; CHECK-NEXT: pvseq.lo %v0 -; CHECK-NEXT: pvsrl.lo %v0, %v0, %s0 +; CHECK-NEXT: or %s1, 1, (0)1 +; CHECK-NEXT: pvsrl.lo %v0, %v0, %s1 ; CHECK-NEXT: lea %s0, calc_v4i32@lo ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: lea.sl %s12, calc_v4i32@hi(, %s0) @@ -133,11 +133,11 @@ entry: define i32 @vseqsrl_v8i32() { ; CHECK-LABEL: vseqsrl_v8i32: ; CHECK: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: or %s0, 1, (0)1 -; CHECK-NEXT: lea %s1, 8 -; CHECK-NEXT: lvl %s1 +; CHECK-NEXT: lea %s0, 8 +; CHECK-NEXT: lvl %s0 ; CHECK-NEXT: pvseq.lo %v0 -; CHECK-NEXT: pvsrl.lo %v0, %v0, %s0 +; CHECK-NEXT: or %s1, 1, (0)1 +; CHECK-NEXT: pvsrl.lo %v0, %v0, %s1 ; CHECK-NEXT: lea %s0, calc_v8i32@lo ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: lea.sl %s12, calc_v8i32@hi(, %s0)