From a34aedba4d397ffad64dfb94827581d1759b8797 Mon Sep 17 00:00:00 2001 From: Yen-Fu Chen Date: Thu, 22 Dec 2022 14:33:04 +0800 Subject: [PATCH 1/2] Fix missing csr_cycle increment After finishing emulating, all instructions must increase csr cycle, but we only do so for branch instructions. --- src/emulate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/emulate.c b/src/emulate.c index 352487f9..f4d482b2 100644 --- a/src/emulate.c +++ b/src/emulate.c @@ -266,9 +266,9 @@ enum { { \ rv->X[rv_reg_zero] = 0; \ code; \ + rv->csr_cycle++; \ if (__rv_insn_##inst##_canbranch) { \ /* can branch */ \ - rv->csr_cycle++; \ return true; \ } \ nextop: \ From d3fd742390dbae823fe6ab233717539a8b406c9c Mon Sep 17 00:00:00 2001 From: Yen-Fu Chen Date: Thu, 22 Dec 2022 14:05:22 +0800 Subject: [PATCH 2/2] Fix miss value fencei instrucition in branch list In the previous implementation, fencei was treated as a branch instruction, but it was assigned a missing value in the new branch list. As a result, emulator fails to pass Zifencei test. Close: #98 --- src/decode.h | 2 +- src/emulate.c | 8 ++++---- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/src/decode.h b/src/decode.h index 4a9c102f..ef237284 100644 --- a/src/decode.h +++ b/src/decode.h @@ -62,7 +62,7 @@ _(mret, 1) \ /* RV32 Zifencei Standard Extension */ \ IIF(RV32_HAS(Zifencei))( \ - _(fencei, 0) \ + _(fencei, 1) \ ) \ /* RV32 Zicsr Standard Extension */ \ IIF(RV32_HAS(Zicsr))( \ diff --git a/src/emulate.c b/src/emulate.c index f4d482b2..d0894c18 100644 --- a/src/emulate.c +++ b/src/emulate.c @@ -616,10 +616,10 @@ RVOP(hret, { RVOP(mret, { rv->PC = rv->csr_mepc; }) #if RV32_HAS(Zifencei) /* RV32 Zifencei Standard Extension */ -RVOP(fencei, - { - /* FIXME: fill real implementations */ - }) +RVOP(fencei, { + rv->PC += ir->insn_len; + /* FIXME: fill real implementations */ +}) #endif #if RV32_HAS(Zicsr) /* RV32 Zicsr Standard Extension */