diff --git a/src/soc/intel/alderlake/include/soc/gpio.h b/src/soc/intel/alderlake/include/soc/gpio.h
index 14338e9024..e6e23803ad 100644
--- a/src/soc/intel/alderlake/include/soc/gpio.h
+++ b/src/soc/intel/alderlake/include/soc/gpio.h
@@ -5,8 +5,13 @@
 
 #if CONFIG(SOC_INTEL_ALDERLAKE_PCH_S)
 #include <soc/gpio_defs_pch_s.h>
+#if CONFIG(SOC_INTEL_RAPTORLAKE)
+#define CROS_GPIO_NAME		"INTC1085"
+#define CROS_GPIO_DEVICE_NAME	"INTC1085:00"
+#else
 #define CROS_GPIO_NAME		"INTC1056"
 #define CROS_GPIO_DEVICE_NAME	"INTC1056:00"
+#endif
 #elif CONFIG(SOC_INTEL_ALDERLAKE_PCH_N)
 #include <soc/gpio_defs.h>
 #define CROS_GPIO_NAME		"INTC1057"
diff --git a/src/soc/intel/alderlake/include/soc/iomap.h b/src/soc/intel/alderlake/include/soc/iomap.h
index 59019d4cce..6188746555 100644
--- a/src/soc/intel/alderlake/include/soc/iomap.h
+++ b/src/soc/intel/alderlake/include/soc/iomap.h
@@ -20,8 +20,14 @@
 #define PCH_TRACE_HUB_BASE_SIZE	0x00800000
 #endif
 
+/* Hack to include SBREG in PCH_RESERVED region on ADL-S/RPL-S */
+#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_S)
+#define PCH_PRESERVED_BASE_ADDRESS	0xe0000000
+#define PCH_PRESERVED_BASE_SIZE		0x1e800000
+#else
 #define PCH_PRESERVED_BASE_ADDRESS	0xfc800000
 #define PCH_PRESERVED_BASE_SIZE		0x02000000
+#endif
 
 #define UART_BASE_SIZE		0x1000