diff --git a/py/rwmem/mappedregisterfile.py b/py/rwmem/mappedregisterfile.py index c84009f..cad73fa 100644 --- a/py/rwmem/mappedregisterfile.py +++ b/py/rwmem/mappedregisterfile.py @@ -8,15 +8,12 @@ __all__ = [ 'MappedRegister', 'MappedRegisterBlock', 'MappedRegisterFile' ] class MappedRegister: - __initialized = False - def __init__(self, map, reg: rwmem.Register, size, block_offset): self._map = map self._size = size self._reg = reg self._frozen = None self._block_offset = block_offset - self.__initialized = True def freeze(self): if not self._frozen is None: @@ -134,26 +131,8 @@ def __setitem__(self, idx, val): def __contains__(self, key): return key in self._reg - def __getattr__(self, key): - if key in self._reg: - return self.get_field_value(key) - else: - raise AttributeError('No field {0} found!'.format(key)) - - def __setattr__(self, key, value): - if not self.__initialized or key in dir(self): - super().__setattr__(key, value) - return - - if key not in self._reg: - raise AttributeError('No field {0} found!'.format(key)) - - self.set_field_value(key, value) - class MappedRegisterBlock(collections.abc.Mapping): - __initialized = False - def __init__(self, file, regblock: rwmem.RegisterBlock, offset: int | None = None, mode = rwmem.MapMode.ReadWrite): @@ -167,8 +146,6 @@ def __init__(self, file, regblock: rwmem.RegisterBlock, self._registers: dict[str, MappedRegister | None] = dict.fromkeys(regblock.keys()) - self.__initialized = True - def __enter__(self): return self @@ -197,31 +174,11 @@ def __iter__(self): def __len__(self): return len(self._registers) - def __getattr__(self, key): - if key in self: - return self[key] - else: - raise AttributeError(f'No MappedRegister {key} found!') - - def __setitem__(self, key, val): - reg = self.__getitem__(key) - reg.set_value(val) - - def __setattr__(self, key, value): - if not self.__initialized or key == '_map': - super().__setattr__(key, value) - return - - self.__setitem__(key, value) - class MappedRegisterFile(collections.abc.Mapping): - __initialized = False - def __init__(self, rf: rwmem.RegisterFile) -> None: self._rf = rf self._regblocks: dict[str, MappedRegisterBlock | None] = dict.fromkeys(rf.keys()) - self.__initialized = True def __getitem__(self, key: str): if key not in self._regblocks: @@ -244,18 +201,3 @@ def __iter__(self): def __len__(self): return len(self._regblocks) - - def __getattr__(self, key): - if key in self: - return self[key] - else: - raise AttributeError(f'No MappedRegisterBlock {key} found!') - - def __setitem__(self, key, val): - raise TypeError() - - def __setattr__(self, key, value): - if self.__initialized: - raise TypeError() - - super().__setattr__(key, value) diff --git a/py/tests/test_mmap_regs.py b/py/tests/test_mmap_regs.py index e421b53..e170d24 100755 --- a/py/tests/test_mmap_regs.py +++ b/py/tests/test_mmap_regs.py @@ -1,8 +1,5 @@ #!/usr/bin/python3 -# pylint can't handle the dynamic fields we use -# pylint: skip-file - import os import shutil import stat @@ -29,29 +26,25 @@ def tests(self): m = self.map self.assertTrue('REG1' in m) - self.assertTrue('REG11' in m.REG1) + self.assertTrue('REG11' in m['REG1']) self.assertEqual(m['REG1'].value, 0xf00dbaad) - self.assertEqual(m.REG1.value, 0xf00dbaad) - self.assertEqual(m.REG1[0:7], 0xad) - self.assertEqual(m.REG1[31:16], 0xf00d) + self.assertEqual(m['REG1'][0:7], 0xad) + self.assertEqual(m['REG1'][31:16], 0xf00d) self.assertEqual(m['REG1']['REG11'], 0xf00d) self.assertEqual(m['REG1']['REG12'], 0xbaad) - self.assertEqual(m.REG1.REG11, 0xf00d) - self.assertEqual(m.REG1.REG12, 0xbaad) - - self.assertEqual(m.REG2.value, 0xabbaaabb) - self.assertEqual(m.REG2.REG21, 0xab) - self.assertEqual(m.REG2.REG22, 0xba) - self.assertEqual(m.REG2.REG23, 0xaa) - self.assertEqual(m.REG2.REG24, 0xbb) + self.assertEqual(m['REG2'].value, 0xabbaaabb) + self.assertEqual(m['REG2']['REG21'], 0xab) + self.assertEqual(m['REG2']['REG22'], 0xba) + self.assertEqual(m['REG2']['REG23'], 0xaa) + self.assertEqual(m['REG2']['REG24'], 0xbb) - self.assertEqual(m.REG3.value, 0x00560078) - self.assertEqual(m.REG3.REG31, 0x56) - self.assertEqual(m.REG3.REG32, 0x78) + self.assertEqual(m['REG3'].value, 0x00560078) + self.assertEqual(m['REG3']['REG31'], 0x56) + self.assertEqual(m['REG3']['REG32'], 0x78) class WriteMmapRegsTests(unittest.TestCase): @@ -71,7 +64,7 @@ def tests(self): self.assertEqual(m['REG1'].value, 0xf00dbaad) - m['REG1'] = 0x12345678 + m['REG1'].set_value(0x12345678) m['REG1'][0:7] = 0xda m['REG1'][15:8] = 0x01 m['REG1']['REG11'] = 0xbade; @@ -81,20 +74,19 @@ def tests(self): m = self.map - m['REG1'] = 0xf00dbaad + m['REG1'].set_value(0xf00dbaad) self.assertEqual(m['REG1'].value, 0xf00dbaad) - m.REG1 = 0x12345678 - m.REG1[0:7] = 0xda - m.REG1[15:8] = 0x01 - m.REG1.REG11 = 0xbade; + m['REG1'].set_value(0x12345678) + m['REG1'][0:7] = 0xda + m['REG1'][15:8] = 0x01 + m['REG1']['REG11'] = 0xbade; - self.assertEqual(m.REG1.value, 0xbade01da) + self.assertEqual(m['REG1'].value, 0xbade01da) self.assertEqual(m._map.read(8, 4), 0xbade01da) - - m.REG3 = { 'REG31': 0x56, 'REG32': 0x78 } - self.assertEqual(m.REG3.value, 0x00560078) + m['REG3'].set_value({ 'REG31': 0x56, 'REG32': 0x78 }) + self.assertEqual(m['REG3'].value, 0x00560078) self.assertEqual(m._map.read(16, 4), 0x00560078) import difflib diff --git a/py/utils/test-dss.py b/py/utils/test-dss.py index 7c2350d..2577f88 100755 --- a/py/utils/test-dss.py +++ b/py/utils/test-dss.py @@ -127,7 +127,7 @@ def pr_old(): break vp = mrf[vp_name] - print(f'{vp_name} enable={vp.CONTROL.ENABLE}') + print(f'{vp_name} enable={vp['CONTROL']['ENABLE']}') ovr_name = f'OVR{vp_idx}' if not ovr_name in mrf: @@ -139,7 +139,7 @@ def pr_old(): for ovr_attr_idx in range(0, 4): ovr_attrs_name = f'ATTRIBUTES_{ovr_attr_idx}' reg = ovr[ovr_attrs_name] - print(f' {ovr_attrs_name} enable={reg.ENABLE} channelin={reg.CHANNELIN} posx={reg.POSX} posy={reg.POSY}') + print(f' {ovr_attrs_name} enable={reg['ENABLE']} channelin={reg['CHANNELIN']} posx={reg['POSX']} posy={reg['POSY']}') print("==") @@ -165,7 +165,7 @@ def pr(): import time -mrf.OVR2.ATTRIBUTES_0.CHANNELIN=0 +mrf['OVR2']['ATTRIBUTES_0']['CHANNELIN']=0 time.sleep(1) -mrf.OVR2.ATTRIBUTES_1.CHANNELIN=3 +mrf['OVR2']['ATTRIBUTES_1']['CHANNELIN']=3 #mrf.VP2.CONTROL.GOBIT=1