From ef6d74e9746a8e618dc9e31e98fa05a4f91b642c Mon Sep 17 00:00:00 2001 From: atrivedi-tsavoritesi Date: Mon, 6 Jan 2025 07:36:44 -0800 Subject: [PATCH] @FIR-446: Zephyr on SKYLP (#12) * @FIR-446: Zephyr on SKYLP This commit brings changes necessary to support SKYLP on Zephyr. It also makes changes necessary to support mulitple boards. In addition, the structure is customized for TSI SOCs. * Reverting print string so that sanity is not affected. --------- Co-authored-by: Riaz Khan --- boards/tsi/skylp/Kconfig | 5 + boards/tsi/skylp/Kconfig.defconfig | 21 ++++ boards/tsi/skylp/Kconfig.tsi_skylp | 5 + boards/tsi/skylp/board.yml | 10 ++ boards/tsi/skylp/tsi_skylp_m85-common.dtsi | 20 ++++ boards/tsi/skylp/tsi_skylp_m85.dts | 110 +++++++++++++++++++++ boards/tsi/skylp/tsi_skylp_m85.yaml | 12 +++ boards/tsi/skylp/tsi_skylp_m85_defconfig | 18 ++++ boards/tsi/skylp/tsi_skylp_txe.dts | 47 +++++++++ boards/tsi/skylp/tsi_skylp_txe.yaml | 16 +++ boards/tsi/skylp/tsi_skylp_txe_defconfig | 26 +++++ boards/tsi/skyp/Kconfig.defconfig | 2 +- boards/tsi/skyp/Kconfig.tsi | 7 -- boards/tsi/skyp/Kconfig.tsi_skyp | 8 ++ boards/tsi/skyp/board.yml | 2 +- boards/tsi/skyp/tsi_skyp_m85.yaml | 4 +- boards/tsi/skyp/tsi_skyp_txe.yaml | 2 +- soc/tsi/skylp_v1/CMakeLists.txt | 10 ++ soc/tsi/skylp_v1/Kconfig | 19 ++++ soc/tsi/skylp_v1/Kconfig.defconfig | 12 +++ soc/tsi/skylp_v1/Kconfig.soc | 27 +++++ soc/tsi/skylp_v1/soc.c | 23 +++++ soc/tsi/skylp_v1/soc.h | 16 +++ soc/tsi/soc.yml | 10 +- 24 files changed, 419 insertions(+), 13 deletions(-) create mode 100644 boards/tsi/skylp/Kconfig create mode 100644 boards/tsi/skylp/Kconfig.defconfig create mode 100644 boards/tsi/skylp/Kconfig.tsi_skylp create mode 100644 boards/tsi/skylp/board.yml create mode 100644 boards/tsi/skylp/tsi_skylp_m85-common.dtsi create mode 100644 boards/tsi/skylp/tsi_skylp_m85.dts create mode 100644 boards/tsi/skylp/tsi_skylp_m85.yaml create mode 100644 boards/tsi/skylp/tsi_skylp_m85_defconfig create mode 100644 boards/tsi/skylp/tsi_skylp_txe.dts create mode 100644 boards/tsi/skylp/tsi_skylp_txe.yaml create mode 100644 boards/tsi/skylp/tsi_skylp_txe_defconfig delete mode 100644 boards/tsi/skyp/Kconfig.tsi create mode 100644 boards/tsi/skyp/Kconfig.tsi_skyp create mode 100644 soc/tsi/skylp_v1/CMakeLists.txt create mode 100644 soc/tsi/skylp_v1/Kconfig create mode 100644 soc/tsi/skylp_v1/Kconfig.defconfig create mode 100644 soc/tsi/skylp_v1/Kconfig.soc create mode 100644 soc/tsi/skylp_v1/soc.c create mode 100644 soc/tsi/skylp_v1/soc.h diff --git a/boards/tsi/skylp/Kconfig b/boards/tsi/skylp/Kconfig new file mode 100644 index 000000000000..37f53d4116b6 --- /dev/null +++ b/boards/tsi/skylp/Kconfig @@ -0,0 +1,5 @@ +# Copyright (c) 2024 TSI +# SPDX-License-Identifier: Apache-2.0 + +# config BOARD_TSI +# select QEMU_TARGET diff --git a/boards/tsi/skylp/Kconfig.defconfig b/boards/tsi/skylp/Kconfig.defconfig new file mode 100644 index 000000000000..8dab7c6ba55c --- /dev/null +++ b/boards/tsi/skylp/Kconfig.defconfig @@ -0,0 +1,21 @@ +# Copyright (c) 2024 TSI +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_TSI_SKYLP + +# MPU-based null-pointer dereferencing detection cannot +# be applied as the (0x0 - 0x400) is unmapped but QEMU +# will still permit bus access. +choice NULL_POINTER_EXCEPTION_DETECTION + bool + default NULL_POINTER_EXCEPTION_DETECTION_NONE if QEMU_TARGET +endchoice + +if SERIAL + +config UART_INTERRUPT_DRIVEN + default n + +endif # SERIAL + +endif diff --git a/boards/tsi/skylp/Kconfig.tsi_skylp b/boards/tsi/skylp/Kconfig.tsi_skylp new file mode 100644 index 000000000000..79c09bcf44a2 --- /dev/null +++ b/boards/tsi/skylp/Kconfig.tsi_skylp @@ -0,0 +1,5 @@ +# Copyright (c) 2024 TSI +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_TSI_SKYLP + select SOC_SKYLP_M85 diff --git a/boards/tsi/skylp/board.yml b/boards/tsi/skylp/board.yml new file mode 100644 index 000000000000..74f48bc1bb7f --- /dev/null +++ b/boards/tsi/skylp/board.yml @@ -0,0 +1,10 @@ +board: + name: tsi_skylp + vendor: tsi + socs: + - name: skylp + variants: + - name: tensilica + cpucluster: txe + - name: cortex-m85 + cpucluster: m85 diff --git a/boards/tsi/skylp/tsi_skylp_m85-common.dtsi b/boards/tsi/skylp/tsi_skylp_m85-common.dtsi new file mode 100644 index 000000000000..ce567c12ce20 --- /dev/null +++ b/boards/tsi/skylp/tsi_skylp_m85-common.dtsi @@ -0,0 +1,20 @@ +/* + * Copyright (c) 2019-2021 Linaro Limited + * + * SPDX-License-Identifier: Apache-2.0 + */ + + sysclk: system-clock { + compatible = "fixed-clock"; + clock-frequency = <25000000>; + #clock-cells = <0>; +}; + +uart0: uart@14001000 { + compatible = "arm,cmsdk-uart"; + reg = <0x14001000 0x1000>; + interrupts = <34 3 33 3>; + interrupt-names = "tx", "rx"; + clocks = <&sysclk>; + current-speed = <115200>; +}; diff --git a/boards/tsi/skylp/tsi_skylp_m85.dts b/boards/tsi/skylp/tsi_skylp_m85.dts new file mode 100644 index 000000000000..d4925389adfa --- /dev/null +++ b/boards/tsi/skylp/tsi_skylp_m85.dts @@ -0,0 +1,110 @@ +/* + * Copyright (c) 2024 TSI + * Copyright 2022 Arm Limited and/or its affiliates + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include +#include + +/ { + compatible = "arm,mps3-an547"; + #address-cells = <1>; + #size-cells = <1>; + + chosen { + zephyr,console = &jtag_uart; + zephyr,shell-uart = &jtag_uart; + zephyr,sram = &sram; + zephyr,flash = &sram0; + }; + + jtag_uart: uart@86003000 { + compatible = "altr,jtag-uart"; + reg = <0x86003000 0x8>; + status = "enabled"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-m85"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + + mpu: mpu@e000ed90 { + compatible = "arm,armv8.1m-mpu"; + reg = <0xe000ed90 0x40>; + }; + }; + }; + + /* We utilize the secure addresses, if you subtract 0x10000000 + * you'll get the non-secure alias + */ + itcm: itcm@4000 { /* alias @ 0x4000 */ + compatible = "zephyr,memory-region"; + reg = <0x4000 DT_SIZE_K(16)>; + zephyr,memory-region = "ITCM"; + }; + + sram0: sram0@60000000 { /* alias @ 0x60000000 */ + compatible = "zephyr,memory-region"; + reg = <0x60000000 DT_SIZE_K(256)>; + zephyr,memory-region = "SRAM0"; + }; + + sram: sram@60040000 { /* alias @ 0x60040000 */ + compatible = "zephyr,memory-region", "mmio-sram"; + reg = <0x60040000 DT_SIZE_K(1792)>; + zephyr,memory-region = "SRAM"; + }; + + dtcm: dtcm@20000000 { /* alias @ 0x20000000 */ + compatible = "zephyr,memory-region"; + reg = <0x20000000 DT_SIZE_K(16)>; + zephyr,memory-region = "DTCM"; + }; + + isram: sram@60200000 {/* alias @ 0x60200000, lower 1MB of 2 MB SRAM1 */ + compatible = "zephyr,memory-region", "mmio-sram"; + reg = <0x60200000 DT_SIZE_M(1)>; + zephyr,memory-region = "ISRAM"; + }; + + /* Higher 1 MB of 2MB high SRAM */ + sram1: memory@60300000 { + device_type = "memory"; + compatible = "zephyr,memory-region"; + reg = <0x60300000 DT_SIZE_M(1)>; + zephyr,memory-region = "SRAM1"; + }; + + /*soc { + peripheral@71000000 { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x71000000 0x1effffff>; + + #include "tsi_skylp_m85-common.dtsi" + }; + };*/ +}; + +&jtag_uart { + status = "okay"; + current-speed = <9600>; +}; + +&nvic { + arm,num-irq-priority-bits = <3>; +}; diff --git a/boards/tsi/skylp/tsi_skylp_m85.yaml b/boards/tsi/skylp/tsi_skylp_m85.yaml new file mode 100644 index 000000000000..466c496dc352 --- /dev/null +++ b/boards/tsi/skylp/tsi_skylp_m85.yaml @@ -0,0 +1,12 @@ +identifier: tsi_skylp/m85 +name: TSI skylp +type: mcu +arch: arm +ram: 1792 +flash: 256 +simulation: qemu +toolchain: + - zephyr + - gnuarmemb + - xtools +vendor: arm diff --git a/boards/tsi/skylp/tsi_skylp_m85_defconfig b/boards/tsi/skylp/tsi_skylp_m85_defconfig new file mode 100644 index 000000000000..189b5ca59543 --- /dev/null +++ b/boards/tsi/skylp/tsi_skylp_m85_defconfig @@ -0,0 +1,18 @@ +# Copyright (c) 2024 TSI +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_RUNTIME_NMI=y +CONFIG_ARM_TRUSTZONE_M=n +CONFIG_ARM_MPU=y +CONFIG_QEMU_ICOUNT_SHIFT=7 + +# Serial +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y + +# Build a Secure firmware image +CONFIG_TRUSTED_EXECUTION_SECURE=n + +# Build the zephyr.hex and zephyrstrp.hex for FPGA +CONFIG_BUILD_OUTPUT_TSV_STRIPPED_HEX=y diff --git a/boards/tsi/skylp/tsi_skylp_txe.dts b/boards/tsi/skylp/tsi_skylp_txe.dts new file mode 100644 index 000000000000..1035391c2582 --- /dev/null +++ b/boards/tsi/skylp/tsi_skylp_txe.dts @@ -0,0 +1,47 @@ +/* + * Copyright 2021, 2023, 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include + +/ { + model = "NXP i.MX 8MPLUS Audio DSP"; + compatible = "nxp"; + + chosen { + //zephyr,sram = &sram0; + zephyr,sram = &sram_txe; + + zephyr,console = &uart4; + zephyr,shell-uart = &uart4; + }; + sram_txe: memory@60040000 { + device_type = "memory"; + compatible = "mmio-sram"; + reg = <0x60040000 DT_SIZE_K(512)>; + }; +}; + +&pinctrl { + uart4_default: uart4_default { + group0 { + pinmux = <&iomuxc_uart4_rxd_uart_rx_uart4_rx>, + <&iomuxc_uart4_txd_uart_tx_uart4_tx>; + bias-pull-up; + slew-rate = "slow"; + drive-strength = "x1"; + }; + }; +}; + +&uart4 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart4_default>; + pinctrl-names = "default"; +}; diff --git a/boards/tsi/skylp/tsi_skylp_txe.yaml b/boards/tsi/skylp/tsi_skylp_txe.yaml new file mode 100644 index 000000000000..7487e0db9faa --- /dev/null +++ b/boards/tsi/skylp/tsi_skylp_txe.yaml @@ -0,0 +1,16 @@ +identifier: tsi_skylp/txe +name: TSI TXE +type: mcu +arch: xtensa +toolchain: + - xcc + - xt-clang + - zephyr +supported: + - uart +testing: + ignore_tags: + - net + - bluetooth + - mcumgr +vendor: nxp diff --git a/boards/tsi/skylp/tsi_skylp_txe_defconfig b/boards/tsi/skylp/tsi_skylp_txe_defconfig new file mode 100644 index 000000000000..7395655e0e7b --- /dev/null +++ b/boards/tsi/skylp/tsi_skylp_txe_defconfig @@ -0,0 +1,26 @@ +# SPDX-License-Identifier: Apache-2.0 + +# size of stack for initialization and main thread +CONFIG_MAIN_STACK_SIZE=3072 + +# enable logger +CONFIG_LOG=y + +# no need for a "raw" binary zephyr/zephyr.bin in the build directory +CONFIG_BUILD_OUTPUT_BIN=y +CONFIG_BUILD_OUTPUT_HEX=y + +# enable uart driver +CONFIG_SERIAL=y + +# clock configuration +CONFIG_CLOCK_CONTROL=y + +# console (remote proc console by default) +CONFIG_CONSOLE=y + +# uart console (overrides remote proc console) +CONFIG_UART_CONSOLE=y + +# enable pin controller +CONFIG_PINCTRL=y diff --git a/boards/tsi/skyp/Kconfig.defconfig b/boards/tsi/skyp/Kconfig.defconfig index 5722cdf7d507..6dde04e050d5 100644 --- a/boards/tsi/skyp/Kconfig.defconfig +++ b/boards/tsi/skyp/Kconfig.defconfig @@ -1,7 +1,7 @@ # Copyright (c) 2024 TSI # SPDX-License-Identifier: Apache-2.0 -if BOARD_TSI +if BOARD_TSI_SKYP # MPU-based null-pointer dereferencing detection cannot # be applied as the (0x0 - 0x400) is unmapped but QEMU diff --git a/boards/tsi/skyp/Kconfig.tsi b/boards/tsi/skyp/Kconfig.tsi deleted file mode 100644 index eef039ebf52c..000000000000 --- a/boards/tsi/skyp/Kconfig.tsi +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright (c) 2024 TSI -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_TSI - select SOC_PART_NUMBER_MIMX8ML8DVNLZ - select SOC_SKYP_M85 if BOARD_TSI_SKYP_M85 - select SOC_MIMX8ML8_ADSP if BOARD_TSI_SKYP_TXE diff --git a/boards/tsi/skyp/Kconfig.tsi_skyp b/boards/tsi/skyp/Kconfig.tsi_skyp new file mode 100644 index 000000000000..44958a5def56 --- /dev/null +++ b/boards/tsi/skyp/Kconfig.tsi_skyp @@ -0,0 +1,8 @@ +# Copyright (c) 2024 TSI +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_TSI_SKYP + select SOC_SKYP_M85 +# select SOC_PART_NUMBER_MIMX8ML8DVNLZ +# select SOC_SKYP_M85 if BOARD_TSI_SKYP_M85 +# select SOC_MIMX8ML8_ADSP if BOARD_TSI_SKYP_TXE diff --git a/boards/tsi/skyp/board.yml b/boards/tsi/skyp/board.yml index 562658f4b485..8c13cf078e01 100644 --- a/boards/tsi/skyp/board.yml +++ b/boards/tsi/skyp/board.yml @@ -1,5 +1,5 @@ board: - name: tsi + name: tsi_skyp vendor: tsi socs: - name: skyp diff --git a/boards/tsi/skyp/tsi_skyp_m85.yaml b/boards/tsi/skyp/tsi_skyp_m85.yaml index 47b1d6abbd37..402ba01cd003 100644 --- a/boards/tsi/skyp/tsi_skyp_m85.yaml +++ b/boards/tsi/skyp/tsi_skyp_m85.yaml @@ -1,5 +1,5 @@ -identifier: tsi/skyp/m85 -name: TSI sky-p +identifier: tsi_skyp/m85 +name: TSI skyp type: mcu arch: arm ram: 1792 diff --git a/boards/tsi/skyp/tsi_skyp_txe.yaml b/boards/tsi/skyp/tsi_skyp_txe.yaml index 0a5a522caa8c..c147ca4ffeef 100644 --- a/boards/tsi/skyp/tsi_skyp_txe.yaml +++ b/boards/tsi/skyp/tsi_skyp_txe.yaml @@ -1,4 +1,4 @@ -identifier: tsi/skyp/txe +identifier: tsi_skyp/txe name: TSI DSP type: mcu arch: xtensa diff --git a/soc/tsi/skylp_v1/CMakeLists.txt b/soc/tsi/skylp_v1/CMakeLists.txt new file mode 100644 index 000000000000..7f8d6b55fba5 --- /dev/null +++ b/soc/tsi/skylp_v1/CMakeLists.txt @@ -0,0 +1,10 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +zephyr_sources( + soc.c + ) + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/tsi/skylp_v1/Kconfig b/soc/tsi/skylp_v1/Kconfig new file mode 100644 index 000000000000..6b60c82f2358 --- /dev/null +++ b/soc/tsi/skylp_v1/Kconfig @@ -0,0 +1,19 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_SKYLP_V1 + select ARM + +config SOC_SERIES_SKYLP_V1 + select CPU_CORTEX_M85 + select CPU_HAS_ARM_SAU + select CPU_HAS_ARM_MPU + select CPU_HAS_FPU + select ARMV8_M_DSP + select ARMV8_1_M_MVEI + select ARMV8_1_M_MVEF + select ARMV8_1_M_PMU + +config ARMV8_1_M_PMU_EVENTCNT + int + default 8 if SOC_SERIES_SKYLP_V1 diff --git a/soc/tsi/skylp_v1/Kconfig.defconfig b/soc/tsi/skylp_v1/Kconfig.defconfig new file mode 100644 index 000000000000..9bd0e6710260 --- /dev/null +++ b/soc/tsi/skylp_v1/Kconfig.defconfig @@ -0,0 +1,12 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_SKYLP_V1 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 25000000 + +config NUM_IRQS + default 128 + +endif # SOC_SERIES_SKYLP_V1 diff --git a/soc/tsi/skylp_v1/Kconfig.soc b/soc/tsi/skylp_v1/Kconfig.soc new file mode 100644 index 000000000000..73d8b4c1244a --- /dev/null +++ b/soc/tsi/skylp_v1/Kconfig.soc @@ -0,0 +1,27 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + + +config SOC_SERIES_SKYLP_V1 + bool + select SOC_FAMILY_ARM + help + Enable support for ARM MPS3 MCU Series + +config SOC_SKYLP + bool + select SOC_SERIES_SKYP_V1 + help + skylp + +config SOC_SKYLP_M85 + bool + select SOC_SKYLP + help + skylp_m85 + +config SOC_SERIES + default "skylp_v1" if SOC_SERIES_SKYLP_V1 + +config SOC + default "skylp" if SOC_SKYLP diff --git a/soc/tsi/skylp_v1/soc.c b/soc/tsi/skylp_v1/soc.c new file mode 100644 index 000000000000..1db1d7a4e6de --- /dev/null +++ b/soc/tsi/skylp_v1/soc.c @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2024 TSI + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + + +/* Setup GPIO drivers for accessing FPGAIO registers */ +#define FPGAIO_NODE(n) DT_INST(n, arm_mps3_fpgaio_gpio) +#define FPGAIO_INIT(n) \ + GPIO_MMIO32_INIT(FPGAIO_NODE(n), \ + DT_REG_ADDR(FPGAIO_NODE(n)), \ + BIT_MASK(DT_PROP(FPGAIO_NODE(n), ngpios))) + +/* We expect there to be 3 arm,mps3-fpgaio-gpio devices: + * led0, button, and misc + */ + +FPGAIO_INIT(2); diff --git a/soc/tsi/skylp_v1/soc.h b/soc/tsi/skylp_v1/soc.h new file mode 100644 index 000000000000..1b4a75d0e5ac --- /dev/null +++ b/soc/tsi/skylp_v1/soc.h @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2024 TSI + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file SoC configuration macros for the Renesas RA8M1 family MCU + */ + +#ifndef ZEPHYR_SOC_SKYP_SOC_H_ +#define ZEPHYR_SOC_SKYP_SOC_H_ + +#include + +#endif /* ZEPHYR_SOC_SKYP_SOC_H_ */ diff --git a/soc/tsi/soc.yml b/soc/tsi/soc.yml index a17404b1b2b0..c84ab2334313 100644 --- a/soc/tsi/soc.yml +++ b/soc/tsi/soc.yml @@ -1,5 +1,5 @@ family: - - name: tsi + - name: sky series: - name: skyp_v1 socs: @@ -7,3 +7,11 @@ family: cpuclusters: - name: m85 - name: txe + - name: sky + series: + - name: skylp_v1 + socs: + - name: skylp + cpuclusters: + - name: m85 + - name: txe