diff --git a/ArchImpl/CMakeLists.txt b/ArchImpl/CMakeLists.txt index c7ea595fab..0d2c701f2b 100644 --- a/ArchImpl/CMakeLists.txt +++ b/ArchImpl/CMakeLists.txt @@ -39,3 +39,4 @@ ADD_SUBDIRECTORY(OR1K) ADD_SUBDIRECTORY(RISCV) ADD_SUBDIRECTORY(RISCV64) ADD_SUBDIRECTORY(RV32IMACFD) +ADD_SUBDIRECTORY(RV64IMACFD) diff --git a/ArchImpl/OR1K/OR1KArch.cpp b/ArchImpl/OR1K/OR1KArch.cpp index 6f64ea7c06..f7c2ef9d71 100644 --- a/ArchImpl/OR1K/OR1KArch.cpp +++ b/ArchImpl/OR1K/OR1KArch.cpp @@ -358,6 +358,32 @@ void OR1KArch::initInstrSet(etiss::instr::ModedInstructionSet &mis) const { etiss_log(ERROR, "Failed to add instructions of the OR1K instruction set"); } + + mis.foreach( + [](etiss::instr::VariableInstructionSet &vis) { + vis.foreach( + [](etiss::instr::InstructionSet &is) { + is.getInvalid().addCallback( + [](etiss::instr::BitArray &ba, CodeSet &cs, etiss::instr::InstructionContext &ic) { + etiss_uint32 error_code = 0; + static etiss::instr::BitArrayRange R_error_code_0(31, 0); + error_code += R_error_code_0.read(ba) << 0; + + std::stringstream ss; + ss << "\t\t//trap_entry 32\n"; + ss << "\t\treturn " << std::to_string(error_code) << "U;"; + //#if DEBUG + ss << " // @0x" << std::hex << ic.current_address_ << std::dec << ": " << ba; + //#endif + ss << "\n"; + cs.append(CodePart::APPENDEDRETURNINGREQUIRED).code() = ss.str(); + return true; + }, + 0); + } + ); + } + ); } void OR1KArch::initCodeBlock(etiss::CodeBlock &cb) const diff --git a/ArchImpl/RISCV/RISCVArchSpecificImp.h b/ArchImpl/RISCV/RISCVArchSpecificImp.h index 00b0c4a23f..92f79fbd79 100755 --- a/ArchImpl/RISCV/RISCVArchSpecificImp.h +++ b/ArchImpl/RISCV/RISCVArchSpecificImp.h @@ -394,6 +394,29 @@ void RISCVArch::initInstrSet(etiss::instr::ModedInstructionSet &mis) const etiss::instr::VariableInstructionSet *vis = mis.get(1); using namespace etiss; using namespace etiss::instr; + + vis->foreach( + [](InstructionSet &is) { + is.getInvalid().addCallback( + [](BitArray &ba, CodeSet &cs, InstructionContext &ic) { + etiss_uint32 error_code = 0; + static BitArrayRange R_error_code_0(31, 0); + error_code += R_error_code_0.read(ba) << 0; + + std::stringstream ss; + ss << "\t\t//trap_entry 32\n"; + ss << "\t\treturn " << std::to_string(error_code) << "U;"; + //#if DEBUG + ss << " // @0x" << std::hex << ic.current_address_ << std::dec << ": " << ba; + //#endif + ss << "\n"; + cs.append(CodePart::APPENDEDRETURNINGREQUIRED).code() = ss.str(); + return true; + }, + 0); + } + ); + vis->length_updater_ = [](VariableInstructionSet &, InstructionContext &ic, BitArray &ba) { std::function updateRiscvInstrLength = [](InstructionContext &ic, etiss_uint32 opRd) { diff --git a/ArchImpl/RISCV64/RISCV64ArchSpecificImp.h b/ArchImpl/RISCV64/RISCV64ArchSpecificImp.h index ed283366da..a488e46139 100644 --- a/ArchImpl/RISCV64/RISCV64ArchSpecificImp.h +++ b/ArchImpl/RISCV64/RISCV64ArchSpecificImp.h @@ -418,6 +418,29 @@ void RISCV64Arch::initInstrSet(etiss::instr::ModedInstructionSet &mis) const using namespace etiss; using namespace etiss::instr; + + vis->foreach( + [](InstructionSet &is) { + is.getInvalid().addCallback( + [](BitArray &ba, CodeSet &cs, InstructionContext &ic) { + etiss_uint32 error_code = 0; + static BitArrayRange R_error_code_0(31, 0); + error_code += R_error_code_0.read(ba) << 0; + + std::stringstream ss; + ss << "\t\t//trap_entry 32\n"; + ss << "\t\treturn " << std::to_string(error_code) << "U;"; + //#if DEBUG + ss << " // @0x" << std::hex << ic.current_address_ << std::dec << ": " << ba; + //#endif + ss << "\n"; + cs.append(CodePart::APPENDEDRETURNINGREQUIRED).code() = ss.str(); + return true; + }, + 0); + } + ); + vis->length_updater_ = [](VariableInstructionSet &, InstructionContext &ic, BitArray &ba) { std::function updateRiscvInstrLength = [](InstructionContext &ic, etiss_uint32 opRd) { diff --git a/ArchImpl/RV32IMACFD/CMakeLists.txt b/ArchImpl/RV32IMACFD/CMakeLists.txt index 0938e4628f..54e8a034bb 100644 --- a/ArchImpl/RV32IMACFD/CMakeLists.txt +++ b/ArchImpl/RV32IMACFD/CMakeLists.txt @@ -1,19 +1,21 @@ -# Generated on Wed, 25 May 2022 18:09:21 +0200. +# Generated on Tue, 28 Nov 2023 09:45:19 +0100. # # This file contains the CMake build info for the RV32IMACFD core architecture. PROJECT(RV32IMACFD) +SET(CMAKE_BUILD_WITH_INSTALL_RPATH TRUE) +SET(CMAKE_INSTALL_RPATH "\$ORIGIN/../../include/jit/etiss/jit") + ADD_LIBRARY(${PROJECT_NAME} SHARED RV32IMACFDArch.cpp RV32IMACFDArchLib.cpp RV32IMACFDArchSpecificImp.cpp + RV32IMACFDFuncs.c RV32IMACFDInstr.cpp - RV32IMACFD_RISCVBaseInstr.cpp RV32IMACFD_RV32IInstr.cpp RV32IMACFD_RV32ICInstr.cpp RV32IMACFD_RV32MInstr.cpp - RV32IMACFD_ZicsrInstr.cpp RV32IMACFD_RV32FInstr.cpp RV32IMACFD_RV32FCInstr.cpp RV32IMACFD_RV32DInstr.cpp @@ -23,9 +25,15 @@ ADD_LIBRARY(${PROJECT_NAME} SHARED RV32IMACFD_tum_retInstr.cpp RV32IMACFD_RV32AInstr.cpp RV32IMACFD_tum_rvaInstr.cpp + RV32IMACFD_tum_semihostingInstr.cpp ) -FILE(COPY "${CMAKE_CURRENT_LIST_DIR}/${PROJECT_NAME}Funcs.h" DESTINATION "${ETISS_BINARY_DIR}/include/jit/Arch/${PROJECT_NAME}") +add_custom_command( + TARGET ${PROJECT_NAME} POST_BUILD + COMMAND ${CMAKE_COMMAND} -E copy + "${CMAKE_CURRENT_LIST_DIR}/${PROJECT_NAME}Funcs.h" + "${ETISS_BINARY_DIR}/include/jit/Arch/${PROJECT_NAME}" +) INSTALL(FILES "${CMAKE_CURRENT_LIST_DIR}/${PROJECT_NAME}Funcs.h" DESTINATION "include/jit/Arch/${PROJECT_NAME}") ETISSPluginArch(${PROJECT_NAME}) \ No newline at end of file diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD.h b/ArchImpl/RV32IMACFD/RV32IMACFD.h index 3cad50c017..538b4eb029 100644 --- a/ArchImpl/RV32IMACFD/RV32IMACFD.h +++ b/ArchImpl/RV32IMACFD/RV32IMACFD.h @@ -1,5 +1,5 @@ /** - * Generated on Tue, 01 Mar 2022 00:20:25 +0100. + * Generated on Tue, 28 Nov 2023 09:45:19 +0100. * * This file contains the registers for the RV32IMACFD core architecture. */ @@ -54,6 +54,9 @@ struct RV32IMACFD { etiss_uint8 PRIV; etiss_uint32 DPC; etiss_uint32 FCSR; + etiss_uint32 MSTATUS; + etiss_uint32 MIE; + etiss_uint32 MIP; etiss_uint32 *CSR[4096]; etiss_uint32 ins_CSR[4096]; etiss_uint64 F[32]; diff --git a/ArchImpl/RV32IMACFD/RV32IMACFDArch.cpp b/ArchImpl/RV32IMACFD/RV32IMACFDArch.cpp index 0a6e512baa..710bc07ae9 100644 --- a/ArchImpl/RV32IMACFD/RV32IMACFDArch.cpp +++ b/ArchImpl/RV32IMACFD/RV32IMACFDArch.cpp @@ -1,5 +1,5 @@ /** - * Generated on Tue, 01 Mar 2022 00:20:25 +0100. + * Generated on Tue, 28 Nov 2023 09:45:19 +0100. * * This file contains the architecture class for the RV32IMACFD core architecture. */ @@ -35,8 +35,6 @@ *********************************************************************************************************************************/ #include "RV32IMACFDArch.h" - -#define ETISS_ARCH_STATIC_FN_ONLY #include "RV32IMACFDFuncs.h" #define RV32IMACFD_DEBUG_CALL 0 @@ -67,6 +65,7 @@ void RV32IMACFDArch::resetCPU(ETISS_CPU * cpu,etiss::uint64 * startpointer) if (startpointer) cpu->instructionPointer = *startpointer & ~((etiss::uint64)0x1); else cpu->instructionPointer = 0x0; // reference to manual + cpu->nextPc = cpu->instructionPointer; cpu->mode = 1; cpu->cpuTime_ps = 0; cpu->cpuCycleTime_ps = 31250; @@ -122,6 +121,9 @@ void RV32IMACFDArch::resetCPU(ETISS_CPU * cpu,etiss::uint64 * startpointer) rv32imacfdcpu->PRIV = 0; rv32imacfdcpu->DPC = 0; rv32imacfdcpu->FCSR = 0; + rv32imacfdcpu->MSTATUS = 0; + rv32imacfdcpu->MIE = 0; + rv32imacfdcpu->MIP = 0; for (int i = 0; i < 32; ++i) { rv32imacfdcpu->F[i] = 0; } @@ -160,6 +162,9 @@ void RV32IMACFDArch::resetCPU(ETISS_CPU * cpu,etiss::uint64 * startpointer) rv32imacfdcpu->X[30] = &rv32imacfdcpu->T5; rv32imacfdcpu->X[31] = &rv32imacfdcpu->T6; rv32imacfdcpu->CSR[3] = &rv32imacfdcpu->FCSR; + rv32imacfdcpu->CSR[768] = &rv32imacfdcpu->MSTATUS; + rv32imacfdcpu->CSR[772] = &rv32imacfdcpu->MIE; + rv32imacfdcpu->CSR[836] = &rv32imacfdcpu->MIP; rv32imacfdcpu->PRIV = 3; rv32imacfdcpu->DPC = 0; @@ -207,7 +212,9 @@ void RV32IMACFDArch::initCodeBlock(etiss::CodeBlock & cb) const { cb.fileglobalCode().insert("#include \"Arch/RV32IMACFD/RV32IMACFD.h\"\n"); cb.fileglobalCode().insert("#include \"Arch/RV32IMACFD/RV32IMACFDFuncs.h\"\n"); - cb.functionglobalCode().insert("etiss_uint32 exception = 0;\n"); + cb.functionglobalCode().insert("cpu->exception = 0;\n"); + cb.functionglobalCode().insert("cpu->return_pending = 0;\n"); + cb.functionglobalCode().insert("etiss_uint32 mem_ret_code = 0;\n"); } etiss::plugin::gdb::GDBCore & RV32IMACFDArch::getGDBCore() diff --git a/ArchImpl/RV32IMACFD/RV32IMACFDArch.h b/ArchImpl/RV32IMACFD/RV32IMACFDArch.h index 0e6600425e..6ff28c4c5c 100644 --- a/ArchImpl/RV32IMACFD/RV32IMACFDArch.h +++ b/ArchImpl/RV32IMACFD/RV32IMACFDArch.h @@ -1,5 +1,5 @@ /** - * Generated on Thu, 24 Feb 2022 17:15:20 +0100. + * Generated on Tue, 28 Nov 2023 09:45:19 +0100. * * This file contains the architecture class for the RV32IMACFD core architecture. */ @@ -10,6 +10,7 @@ #include "etiss/CPUArch.h" #include "etiss/Instruction.h" #include "etiss/InterruptVector.h" +#include "etiss/InterruptEnable.h" #include "RV32IMACFD.h" #include "RV32IMACFDGDBCore.h" @@ -89,6 +90,8 @@ class RV32IMACFDArch : public etiss::CPUArch { */ virtual etiss::InterruptVector * createInterruptVector(ETISS_CPU * cpu); virtual void deleteInterruptVector(etiss::InterruptVector * vec, ETISS_CPU * cpu); + virtual etiss::InterruptEnable* createInterruptEnable(ETISS_CPU *cpu); + virtual void deleteInterruptEnable(etiss::InterruptEnable* en, ETISS_CPU* cpu); /** @brief get the GDBcore for RV32IMACFD architecture diff --git a/ArchImpl/RV32IMACFD/RV32IMACFDArchLib.cpp b/ArchImpl/RV32IMACFD/RV32IMACFDArchLib.cpp index 6f4070df85..be7a1cf73a 100644 --- a/ArchImpl/RV32IMACFD/RV32IMACFDArchLib.cpp +++ b/ArchImpl/RV32IMACFD/RV32IMACFDArchLib.cpp @@ -1,5 +1,5 @@ /** - * Generated on Thu, 24 Feb 2022 17:15:20 +0100. + * Generated on Tue, 28 Nov 2023 09:45:19 +0100. * * This file contains the library interface for the RV32IMACFD core architecture. */ diff --git a/ArchImpl/RV32IMACFD/RV32IMACFDArchSpecificImp.cpp b/ArchImpl/RV32IMACFD/RV32IMACFDArchSpecificImp.cpp index dc48e25ef6..5568acf9e2 100644 --- a/ArchImpl/RV32IMACFD/RV32IMACFDArchSpecificImp.cpp +++ b/ArchImpl/RV32IMACFD/RV32IMACFDArchSpecificImp.cpp @@ -12,7 +12,8 @@ #include "RV32IMACFDArch.h" #include "RV32IMACFDArchSpecificImp.h" -#include "Encoding.h" +#include "RV32IMACFDFuncs.h" + /** @brief This function will be called automatically in order to handling exceptions such as interrupt, system call, illegal instructions @@ -29,259 +30,9 @@ */ etiss::int32 RV32IMACFDArch::handleException(etiss::int32 cause, ETISS_CPU * cpu) { - etiss_uint32 handledCause = cause; - - std::function disableItr = [cpu]() { - if (likely((*((RV32IMACFD *)cpu)->CSR[CSR_MSTATUS]) & MSTATUS_MIE)) - { - // Push MIE, SIE, UIE to MPIE, SPIE, UPIE - etiss_uint32 irq_enable = ((*((RV32IMACFD *)cpu)->CSR[CSR_MSTATUS]) & MSTATUS_MIE) | - ((*((RV32IMACFD *)cpu)->CSR[CSR_MSTATUS]) & MSTATUS_UIE) | - ((*((RV32IMACFD *)cpu)->CSR[CSR_MSTATUS]) & MSTATUS_SIE); - (*((RV32IMACFD *)cpu)->CSR[CSR_MSTATUS]) = (irq_enable << 4) | ((*((RV32IMACFD *)cpu)->CSR[CSR_MSTATUS]) & 0xffffff00); - } - }; - - std::function handle = [cpu, cause](etiss_uint32 causeCode, - etiss_uint32 addr) { - std::stringstream msg; - - msg << "Exception is captured with cause code: 0x" << std::hex << causeCode; - msg << " Exception message: " << etiss::RETURNCODE::getErrorMessages()[cause] << std::endl; - - switch (causeCode & 0x80000000) - { - - // Exception - case 0x0: - // Check exception delegation - if (*((RV32IMACFD *)cpu)->CSR[CSR_MEDELEG] & (1 << (causeCode & 0x1f))) - { - // Pop MPIE to MIE - etiss::log(etiss::VERBOSE, "Exception is delegated to supervisor mode"); - (*((RV32IMACFD *)cpu)->CSR[CSR_MSTATUS]) ^= - (((*((RV32IMACFD *)cpu)->CSR[CSR_MSTATUS]) & MSTATUS_MPIE) >> 4) ^ ((*((RV32IMACFD *)cpu)->CSR[CSR_MSTATUS]) & MSTATUS_MIE); - *((RV32IMACFD *)cpu)->CSR[CSR_SCAUSE] = causeCode; - // Redo the instruction encoutered exception after handling - *((RV32IMACFD *)cpu)->CSR[CSR_SEPC] = static_cast(cpu->instructionPointer - 4); - *((RV32IMACFD *)cpu)->CSR[CSR_SSTATUS] ^= (*((RV32IMACFD *)cpu)->CSR[3088] << 8) ^ (*((RV32IMACFD *)cpu)->CSR[CSR_SSTATUS & MSTATUS_SPP]); - *((RV32IMACFD *)cpu)->CSR[3088] = PRV_S; - cpu->instructionPointer = *((RV32IMACFD *)cpu)->CSR[CSR_STVEC] & ~0x3; - } - else - { - *((RV32IMACFD *)cpu)->CSR[CSR_MCAUSE] = causeCode; - // Redo the instruction encoutered exception after handling - *((RV32IMACFD *)cpu)->CSR[CSR_MEPC] = static_cast(cpu->instructionPointer - 4); - (*((RV32IMACFD *)cpu)->CSR[CSR_MSTATUS]) ^= - (*((RV32IMACFD *)cpu)->CSR[3088] << 11) ^ ((*((RV32IMACFD *)cpu)->CSR[CSR_MSTATUS]) & MSTATUS_MPP); - *((RV32IMACFD *)cpu)->CSR[3088] = PRV_M; - // Customized handler address other than specified in RISC-V ISA manual - if (addr) - { - cpu->instructionPointer = addr; - break; - } - cpu->instructionPointer = *((RV32IMACFD *)cpu)->CSR[CSR_MTVEC] & ~0x3; - } - break; - - // Interrupt - case 0x80000000: - // Check exception delegation - if (*((RV32IMACFD *)cpu)->CSR[CSR_MIDELEG] & (1 << (causeCode & 0x1f))) - { - // Pop MPIE to MIE - etiss::log(etiss::VERBOSE, "Interrupt is delegated to supervisor mode"); - (*((RV32IMACFD *)cpu)->CSR[CSR_MSTATUS]) ^= - (((*((RV32IMACFD *)cpu)->CSR[CSR_MSTATUS]) & MSTATUS_MPIE) >> 4) ^ ((*((RV32IMACFD *)cpu)->CSR[CSR_MSTATUS]) & MSTATUS_MIE); - *((RV32IMACFD *)cpu)->CSR[CSR_SCAUSE] = causeCode; - // Return to instruction next interrupted one - *((RV32IMACFD *)cpu)->CSR[CSR_SEPC] = static_cast(cpu->instructionPointer); - *((RV32IMACFD *)cpu)->CSR[CSR_SSTATUS] ^= (*((RV32IMACFD *)cpu)->CSR[3088] << 8) ^ (*((RV32IMACFD *)cpu)->CSR[CSR_SSTATUS] & MSTATUS_SPP); - *((RV32IMACFD *)cpu)->CSR[3088] = PRV_S; - if (*((RV32IMACFD *)cpu)->CSR[CSR_STVEC] & 0x1) - cpu->instructionPointer = (*((RV32IMACFD *)cpu)->CSR[CSR_STVEC] & ~0x3) + causeCode * 4; - else - cpu->instructionPointer = *((RV32IMACFD *)cpu)->CSR[CSR_STVEC] & ~0x3; - } - else - { - *((RV32IMACFD *)cpu)->CSR[CSR_MCAUSE] = causeCode; - // Return to instruction next interrupted one - *((RV32IMACFD *)cpu)->CSR[CSR_MEPC] = static_cast(cpu->instructionPointer); - (*((RV32IMACFD *)cpu)->CSR[CSR_MSTATUS]) ^= - (*((RV32IMACFD *)cpu)->CSR[3088] << 11) ^ ((*((RV32IMACFD *)cpu)->CSR[CSR_MSTATUS]) & MSTATUS_MPP); - *((RV32IMACFD *)cpu)->CSR[3088] = PRV_M; - // Customized handler address other than specified in RISC-V ISA manual - if (addr) - { - cpu->instructionPointer = addr; - break; - } - if (*((RV32IMACFD *)cpu)->CSR[CSR_MTVEC] & 0x1) - cpu->instructionPointer = (*((RV32IMACFD *)cpu)->CSR[CSR_MTVEC] & ~0x3) + causeCode * 4; - else - cpu->instructionPointer = *((RV32IMACFD *)cpu)->CSR[CSR_MTVEC] & ~0x3; - } - break; - } - - msg << "Program is redirected to address: 0x" << std::hex << cpu->instructionPointer << std::endl; - etiss::log(etiss::VERBOSE, msg.str()); - return etiss::RETURNCODE::NOERROR; - }; - - switch (cause) - { - - case etiss::RETURNCODE::INTERRUPT: - if (!((*((RV32IMACFD *)cpu)->CSR[CSR_MSTATUS]) & MSTATUS_MIE)) - { - std::stringstream msg; - msg << "Interrupt handling is globally disabled. Interrupt line is still pending." << std::endl; - etiss::log(etiss::INFO, msg.str()); - handledCause = etiss::RETURNCODE::NOERROR; - break; - } - { - etiss_uint32 mip_tmp = (*(((RV32IMACFD *)cpu))->CSR[CSR_MIP]); - if (0 == mip_tmp) - { - handledCause = etiss::RETURNCODE::NOERROR; - break; - } - etiss_uint32 irqLine = 0; - for (size_t i = 0; i < sizeof(mip_tmp) * 8; ++i) - { - // Highest interrupt line with highest priority - if (unlikely((mip_tmp >> i) & 0x1)) - irqLine = i; - } - - if (!((*(((RV32IMACFD *)cpu))->CSR[CSR_MIE]) & (1 << irqLine))) - { - std::stringstream msg; - handledCause = etiss::RETURNCODE::NOERROR; - msg << "Interrupt line: " << irqLine << " is disabled. Interrupt is still pending." << std::endl; - etiss::log(etiss::INFO, msg.str()); - break; - } - - disableItr(); - - handledCause = handle(irqLine | 0x80000000, 0); - } - break; - - case etiss::RETURNCODE::RESET: - handledCause = handle(0, etiss::cfg().get("vp.entry_point", 0)); - break; - - case etiss::RETURNCODE::INSTR_PAGEFAULT: - disableItr(); - handledCause = handle(CAUSE_FETCH_PAGE_FAULT, 0); - break; - - case etiss::RETURNCODE::LOAD_PAGEFAULT: - - disableItr(); - handledCause = handle(CAUSE_LOAD_PAGE_FAULT, 0); - break; - - case etiss::RETURNCODE::STORE_PAGEFAULT: - - disableItr(); - handledCause = handle(CAUSE_STORE_PAGE_FAULT, 0); - break; - - case etiss::RETURNCODE::ILLEGALINSTRUCTION: - { - disableItr(); - std::stringstream msg; - msg << "Illegal instruction at address: 0x" << std::hex << cpu->instructionPointer << std::endl; - *((RV32IMACFD *)cpu)->CSR[CSR_MTVAL] = static_cast(cpu->instructionPointer); - // Point to next instruction - cpu->instructionPointer += 4; - etiss::log(etiss::WARNING, msg.str()); - handledCause = handle(CAUSE_ILLEGAL_INSTRUCTION, 0); - break; - } - - case etiss::RETURNCODE::DBUS_READ_ERROR: - - disableItr(); - handledCause = handle(CAUSE_LOAD_ACCESS, 0); - break; - - case etiss::RETURNCODE::DBUS_WRITE_ERROR: - - disableItr(); - handledCause = handle(CAUSE_STORE_ACCESS, 0); - break; - - case etiss::RETURNCODE::IBUS_READ_ERROR: - - disableItr(); - handledCause = handle(CAUSE_FETCH_ACCESS, 0); - break; - - case etiss::RETURNCODE::IBUS_WRITE_ERROR: - - disableItr(); - handledCause = handle(CAUSE_STORE_ACCESS, 0); - break; - - case etiss::RETURNCODE::BREAKPOINT: - - disableItr(); - handledCause = handle(CAUSE_BREAKPOINT, 0); - break; - - case etiss::RETURNCODE::SYSCALL: - - disableItr(); - switch (*((RV32IMACFD *)cpu)->CSR[3088]) - { - case PRV_U: - handledCause = handle(CAUSE_USER_ECALL, 0); - break; - case PRV_S: - handledCause = handle(CAUSE_SUPERVISOR_ECALL, 0); - break; - case PRV_M: - handledCause = handle(CAUSE_MACHINE_ECALL, 0); - break; - default: - etiss::log(etiss::ERROR, "System call type not supported for current architecture."); - } - - break; - - case etiss::RETURNCODE::ILLEGALJUMP: - { - disableItr(); - std::stringstream msg; - msg << "Illegal instruction access at address: 0x" << std::hex << cpu->instructionPointer << std::endl; - *((RV32IMACFD *)cpu)->CSR[CSR_MTVAL] = static_cast(cpu->instructionPointer); - // Point to next instruction - cpu->instructionPointer += 4; - etiss::log(etiss::WARNING, msg.str()); - handledCause = handle(CAUSE_FETCH_ACCESS, 0); - break; - } - - default: - { - std::stringstream msg; - msg << "Exception is not handled by architecture. Exception message: "; - msg << etiss::RETURNCODE::getErrorMessages()[cause] << std::endl; - etiss::log(etiss::INFO, msg.str()); - } - handledCause = cause; - break; - } - return handledCause; + RV32IMACFD_translate_exc_code(cpu, nullptr, nullptr, cause); + cpu->instructionPointer = cpu->nextPc; + return 0; } /** @@ -343,8 +94,104 @@ void RV32IMACFDArch::initInstrSet(etiss::instr::ModedInstructionSet & mis) const etiss::log(etiss::FATALERROR,"Failed to add instructions for RV32IMACFDISA"); etiss::instr::VariableInstructionSet *vis = mis.get(1); + using namespace etiss; using namespace etiss::instr; + + vis->get(32)->getInvalid().addCallback( + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint32 error_code = 0; +static BitArrayRange R_error_code_0(31, 0); +error_code += R_error_code_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//trap_entry 32\n"); + +// ----------------------------------------------------------------------------- +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, " + std::to_string(error_code) + "ULL);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); + + cp.code() = std::string("//trap_entry 32\n"); + +// ----------------------------------------------------------------------------- +cp.code() += "return cpu->exception;\n"; +// ----------------------------------------------------------------------------- + } + + return true; + }, + 0 + ); + + vis->get(16)->getInvalid().addCallback( + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint32 error_code = 0; +static BitArrayRange R_error_code_0(31, 0); +error_code += R_error_code_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//trap_entry 16\n"); + +// ----------------------------------------------------------------------------- +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, " + std::to_string(error_code) + "ULL);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); + + cp.code() = std::string("//trap_entry 16\n"); + +// ----------------------------------------------------------------------------- +cp.code() += "return cpu->exception;\n"; +// ----------------------------------------------------------------------------- + } + + return true; + }, + 0 + ); + vis->length_updater_ = [](VariableInstructionSet &, InstructionContext &ic, BitArray &ba) { std::function updateRV32IMACFDInstrLength = [](InstructionContext &ic, etiss_uint32 opRd) { @@ -495,20 +342,11 @@ etiss::InterruptVector * RV32IMACFDArch::createInterruptVector(ETISS_CPU * cpu) if (cpu == 0) return 0; - /************************************************************************** - * Implementation of interrupt vector * - ***************************************************************************/ - - // This is a default vector, implemented to avoid segfaults. Replace - // with actual implementation if necessary. - - RV32IMACFD* rvcpu = (RV32IMACFD *)cpu; - std::vector vec; std::vector mask; - vec.push_back(rvcpu->CSR[CSR_MIP]); - mask.push_back(rvcpu->CSR[CSR_MIE]); + vec.push_back(&((RV32IMACFD*)cpu)->MIP); + mask.push_back(&((RV32IMACFD*)cpu)->MIE); return new etiss::MappedInterruptVector(vec, mask); } @@ -517,3 +355,11 @@ void RV32IMACFDArch::deleteInterruptVector(etiss::InterruptVector * vec, ETISS_C { delete vec; } + +etiss::InterruptEnable* RV32IMACFDArch::createInterruptEnable(ETISS_CPU* cpu) { + return new etiss::MappedInterruptEnable(&((RV32IMACFD*)cpu)->MSTATUS, 15); +} + +void RV32IMACFDArch::deleteInterruptEnable(etiss::InterruptEnable* en, ETISS_CPU* cpu) { + delete en; +} diff --git a/ArchImpl/RV32IMACFD/RV32IMACFDArchSpecificImp.h b/ArchImpl/RV32IMACFD/RV32IMACFDArchSpecificImp.h index 18b89bed60..e9a4e1636b 100644 --- a/ArchImpl/RV32IMACFD/RV32IMACFDArchSpecificImp.h +++ b/ArchImpl/RV32IMACFD/RV32IMACFDArchSpecificImp.h @@ -1,5 +1,5 @@ /** - * Generated on Thu, 24 Feb 2022 17:15:20 +0100. + * Generated on Tue, 28 Nov 2023 09:45:19 +0100. * * This file contains the architecture specific header for the RV32IMACFD * core architecture. diff --git a/ArchImpl/RV32IMACFD/RV32IMACFDFuncs.c b/ArchImpl/RV32IMACFD/RV32IMACFDFuncs.c new file mode 100644 index 0000000000..3164715eaa --- /dev/null +++ b/ArchImpl/RV32IMACFD/RV32IMACFDFuncs.c @@ -0,0 +1,347 @@ +/** + * Generated on Tue, 28 Nov 2023 09:45:19 +0100. + * + * This file contains the function implementations for the RV32IMACFD core architecture. + */ + +#include "RV32IMACFDFuncs.h" + +etiss_uint8 RV32IMACFD_extension_enabled(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_int8 extension) +{ +{ // block +return (*((RV32IMACFD*)cpu)->CSR[769LL] >> (extension - 65ULL)) & 1ULL; +} // block +} + +etiss_uint8 RV32IMACFD_get_rm(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint8 rm) +{ +{ // block +if (rm == 7ULL) { // conditional +rm = ((((((RV32IMACFD*)cpu)->FCSR) >> (5ULL)) & 7)) & 0x7; +} // conditional +if (rm > 4ULL) { // conditional +RV32IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 2LL); +} // conditional +return rm; +} // block +} + +etiss_uint32 RV32IMACFD_sstatus_mask(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers) +{ +{ // block +etiss_uint32 mask = 0ULL; +if (RV32IMACFD_extension_enabled(cpu, system, plugin_pointers, 83ULL)) { // conditional +{ // block +mask = mask | 5767458ULL; +if (RV32IMACFD_extension_enabled(cpu, system, plugin_pointers, 86ULL)) { // conditional +mask = mask | 1536LL; +} // conditional +if (RV32IMACFD_extension_enabled(cpu, system, plugin_pointers, 70ULL)) { // conditional +mask = mask | 24576LL; +} // conditional +if (RV32IMACFD_extension_enabled(cpu, system, plugin_pointers, 88ULL)) { // conditional +mask = mask | 98304LL; +} // conditional +if ((RV32IMACFD_get_field(*((RV32IMACFD*)cpu)->CSR[384LL], 2147483648ULL))) { // conditional +mask = mask | 262144LL; +} // conditional +} // block +} // conditional +return mask; +} // block +} + +etiss_uint32 RV32IMACFD_mstatus_mask(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers) +{ +{ // block +etiss_uint32 mask = 6280ULL; +return mask | RV32IMACFD_sstatus_mask(cpu, system, plugin_pointers); +} // block +} + +etiss_uint32 RV32IMACFD_csr_read(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint32 csr) +{ +{ // block +if (csr == 1LL) { // conditional +return *((RV32IMACFD*)cpu)->CSR[3LL] & 31ULL; +} // conditional +if (csr == 2LL) { // conditional +return (*((RV32IMACFD*)cpu)->CSR[3LL] >> 5ULL) & 7ULL; +} // conditional +if (csr == 3072LL) { // conditional +return etiss_get_cycles(cpu, system, plugin_pointers); +} // conditional +if (csr == 3200LL) { // conditional +return etiss_get_cycles(cpu, system, plugin_pointers) >> 32ULL; +} // conditional +if (csr == 3073LL) { // conditional +return etiss_get_time(); +} // conditional +if (csr == 3201LL) { // conditional +return etiss_get_time() >> 32ULL; +} // conditional +if (csr == 3074LL) { // conditional +return etiss_get_instret(cpu, system, plugin_pointers); +} // conditional +if (csr == 3202LL) { // conditional +return etiss_get_instret(cpu, system, plugin_pointers) >> 32ULL; +} // conditional +if (csr == 768LL || csr == 256LL) { // conditional +return *((RV32IMACFD*)cpu)->CSR[768LL] | 8589934592ULL | 34359738368ULL; +} // conditional +if (csr == 769LL) { // conditional +return (((1ULL) << 30) | ((((*((RV32IMACFD*)cpu)->CSR[769LL]) >> (0ULL)) & 1073741823))); +} // conditional +return *((RV32IMACFD*)cpu)->CSR[csr]; +} // block +} + +void RV32IMACFD_csr_write(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint32 csr, etiss_uint32 val) +{ +{ // block +if (csr == 1LL) { // conditional +*((RV32IMACFD*)cpu)->CSR[3LL] = (*((RV32IMACFD*)cpu)->CSR[3LL] & 224ULL) | (val & 31ULL); +} // conditional + else if (csr == 2LL) { // conditional +*((RV32IMACFD*)cpu)->CSR[3LL] = ((val & 7ULL) << 5ULL) | (*((RV32IMACFD*)cpu)->CSR[3LL] & 31ULL); +} // conditional + else if (csr == 3LL) { // conditional +*((RV32IMACFD*)cpu)->CSR[3LL] = val & 255ULL; +} // conditional + else if (csr == 768LL) { // conditional +*((RV32IMACFD*)cpu)->CSR[768LL] = val & RV32IMACFD_mstatus_mask(cpu, system, plugin_pointers); +} // conditional + else if (csr == 256LL) { // conditional +*((RV32IMACFD*)cpu)->CSR[768LL] = val & RV32IMACFD_sstatus_mask(cpu, system, plugin_pointers); +} // conditional + else if (csr != 769LL) { // conditional +*((RV32IMACFD*)cpu)->CSR[csr] = val; +} // conditional +} // block +} + +etiss_uint64 RV32IMACFD_get_field(etiss_uint64 reg, etiss_uint64 mask) +{ +{ // block +if (!(mask)) { // conditional +return 0ULL; +} // conditional +return (reg & mask) / (mask & ~((mask << 1ULL))); +} // block +} + +etiss_uint64 RV32IMACFD_set_field(etiss_uint64 reg, etiss_uint64 mask, etiss_uint64 val) +{ +{ // block +return ((reg & ~(mask)) | ((val * (mask & ~((mask << 1ULL)))) & mask)); +} // block +} + +etiss_uint8 RV32IMACFD_ctz(etiss_uint64 val) +{ +{ // block +if (!(val)) { // conditional +return 0ULL; +} // conditional +etiss_uint8 res = 0ULL; +if ((val << 32ULL) == 0ULL) { // conditional +{ // block +res = res + 32ULL; +val = val >> 32ULL; +} // block +} // conditional +if ((val << 48ULL) == 0ULL) { // conditional +{ // block +res = res + 16ULL; +val = val >> 16ULL; +} // block +} // conditional +if ((val << 56ULL) == 0ULL) { // conditional +{ // block +res = res + 8ULL; +val = val >> 8ULL; +} // block +} // conditional +if ((val << 60ULL) == 0ULL) { // conditional +{ // block +res = res + 4ULL; +val = val >> 4ULL; +} // block +} // conditional +if ((val << 62ULL) == 0ULL) { // conditional +{ // block +res = res + 2ULL; +val = val >> 2ULL; +} // block +} // conditional +if ((val << 63ULL) == 0ULL) { // conditional +{ // block +res = res + 1ULL; +val = val >> 1ULL; +} // block +} // conditional +return res; +} // block +} + +void RV32IMACFD_raise(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_int32 irq, etiss_uint32 mcause) +{ +cpu->return_pending = 1; +cpu->exception = 0; +{ // block +etiss_uint32 epc = cpu->instructionPointer; +etiss_uint32 deleg = 0ULL; +etiss_uint32 vector = 0ULL; +etiss_uint32 bit = mcause; +etiss_int32 irq2 = (mcause & 2147483648ULL) != 0ULL; +if (irq2) { // conditional +{ // block +deleg = ((((RV32IMACFD*)cpu)->PRIV <= 1LL)) ? (*((RV32IMACFD*)cpu)->CSR[771LL]) : (0ULL); +bit = bit & 2147483647ULL; +} // block +} // conditional +else { // conditional +{ // block +deleg = ((((RV32IMACFD*)cpu)->PRIV <= 1LL)) ? (*((RV32IMACFD*)cpu)->CSR[770LL]) : (0ULL); +} // block +} // conditional +if (((RV32IMACFD*)cpu)->PRIV <= 1LL && (deleg >> bit) & 1ULL) { // conditional +{ // block +vector = ((*((RV32IMACFD*)cpu)->CSR[261LL] & 1ULL) && irq2) ? (bit * 4ULL) : (0ULL); +cpu->nextPc = (*((RV32IMACFD*)cpu)->CSR[261LL] & -2LL) + vector; +*((RV32IMACFD*)cpu)->CSR[321LL] = epc; +*((RV32IMACFD*)cpu)->CSR[322LL] = mcause; +etiss_uint32 s = RV32IMACFD_csr_read(cpu, system, plugin_pointers, 256LL); +s = RV32IMACFD_set_field(s, 32LL, RV32IMACFD_get_field(s, 2LL)); +s = RV32IMACFD_set_field(s, 256LL, ((RV32IMACFD*)cpu)->PRIV); +s = RV32IMACFD_set_field(s, 2LL, 0ULL); +RV32IMACFD_csr_write(cpu, system, plugin_pointers, 256LL, s); +((RV32IMACFD*)cpu)->PRIV = (1LL) & 0x7; +} // block +} // conditional +else { // conditional +{ // block +vector = ((*((RV32IMACFD*)cpu)->CSR[773LL] & 1ULL) && irq2) ? (bit * 4ULL) : (0ULL); +cpu->nextPc = (*((RV32IMACFD*)cpu)->CSR[773LL] & -2LL) + vector; +*((RV32IMACFD*)cpu)->CSR[833LL] = epc; +*((RV32IMACFD*)cpu)->CSR[834LL] = mcause; +etiss_uint32 s = RV32IMACFD_csr_read(cpu, system, plugin_pointers, 768LL); +s = RV32IMACFD_set_field(s, 128LL, RV32IMACFD_get_field(s, 8LL)); +s = RV32IMACFD_set_field(s, 6144LL, ((RV32IMACFD*)cpu)->PRIV); +s = RV32IMACFD_set_field(s, 8LL, 0ULL); +RV32IMACFD_csr_write(cpu, system, plugin_pointers, 768LL, s); +((RV32IMACFD*)cpu)->PRIV = (3LL) & 0x7; +} // block +} // conditional +} // block +} + +void RV32IMACFD_translate_exc_code(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_int32 cause) +{ +{ // block +etiss_uint32 code = 0ULL; +if (cause == -2147483648LL) { // conditional +return; +} // conditional + else if (cause == -5LL) { // conditional +code = 5LL; +} // conditional + else if (cause == -14LL) { // conditional +code = 13LL; +} // conditional + else if (cause == -6LL) { // conditional +code = 7LL; +} // conditional + else if (cause == -15LL) { // conditional +code = 15LL; +} // conditional + else if (cause == -7LL) { // conditional +code = 1LL; +} // conditional + else if (cause == -9LL) { // conditional +{ // block +code = RV32IMACFD_calc_irq_mcause(cpu, system, plugin_pointers); +if (!(code)) { // conditional +return; +} // conditional +} // block +} // conditional +else { // conditional +code = 2LL; +} // conditional +RV32IMACFD_raise(cpu, system, plugin_pointers, 0ULL, code); +} // block +} + +etiss_uint32 RV32IMACFD_calc_irq_mcause(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers) +{ +{ // block +etiss_uint32 pending_interrupts = *((RV32IMACFD*)cpu)->CSR[772LL] & *((RV32IMACFD*)cpu)->CSR[836LL]; +if (!(pending_interrupts)) { // conditional +return 0ULL; +} // conditional +etiss_uint32 mie = RV32IMACFD_get_field(*((RV32IMACFD*)cpu)->CSR[768LL], 8LL); +etiss_uint32 m_enabled = ((RV32IMACFD*)cpu)->PRIV < 3LL || (((RV32IMACFD*)cpu)->PRIV == 3LL && mie); +etiss_uint32 enabled_interrupts = pending_interrupts & ~(*((RV32IMACFD*)cpu)->CSR[771LL]) & -(m_enabled); +if (enabled_interrupts == 0ULL) { // conditional +{ // block +etiss_uint32 deleg = *((RV32IMACFD*)cpu)->CSR[771LL]; +etiss_uint32 sie = RV32IMACFD_get_field(RV32IMACFD_csr_read(cpu, system, plugin_pointers, 256LL), 2LL); +etiss_uint32 s_enabled = ((RV32IMACFD*)cpu)->PRIV < 1LL || (((RV32IMACFD*)cpu)->PRIV == 1LL && sie); +enabled_interrupts = pending_interrupts & deleg & -(s_enabled); +} // block +} // conditional +if (enabled_interrupts) { // conditional +{ // block +if (enabled_interrupts >> 12ULL) { // conditional +enabled_interrupts = enabled_interrupts >> 12ULL << 12ULL; +} // conditional + else if (enabled_interrupts & 2048LL) { // conditional +enabled_interrupts = 2048LL; +} // conditional + else if (enabled_interrupts & 8LL) { // conditional +enabled_interrupts = 8LL; +} // conditional + else if (enabled_interrupts & 128LL) { // conditional +enabled_interrupts = 128LL; +} // conditional + else if (enabled_interrupts & 512LL) { // conditional +enabled_interrupts = 512LL; +} // conditional + else if (enabled_interrupts & 2LL) { // conditional +enabled_interrupts = 2LL; +} // conditional + else if (enabled_interrupts & 32LL) { // conditional +enabled_interrupts = 32LL; +} // conditional + else if (enabled_interrupts & 8192LL) { // conditional +enabled_interrupts = 8192LL; +} // conditional + else if (enabled_interrupts & 1024LL) { // conditional +enabled_interrupts = 1024LL; +} // conditional + else if (enabled_interrupts & 4LL) { // conditional +enabled_interrupts = 4LL; +} // conditional + else if (enabled_interrupts & 64LL) { // conditional +enabled_interrupts = 64LL; +} // conditional +else { // conditional +return 0ULL; +} // conditional +return 2147483648ULL | RV32IMACFD_ctz(enabled_interrupts); +} // block +} // conditional +return 0ULL; +} // block +} + +void RV32IMACFD_check_irq(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers) +{ +{ // block +etiss_uint32 irq_mcause = RV32IMACFD_calc_irq_mcause(cpu, system, plugin_pointers); +if (irq_mcause) { // conditional +RV32IMACFD_raise(cpu, system, plugin_pointers, 1ULL, irq_mcause); +} // conditional +} // block +} diff --git a/ArchImpl/RV32IMACFD/RV32IMACFDFuncs.h b/ArchImpl/RV32IMACFD/RV32IMACFDFuncs.h index 4ddf6b2802..36a55fb202 100644 --- a/ArchImpl/RV32IMACFD/RV32IMACFDFuncs.h +++ b/ArchImpl/RV32IMACFD/RV32IMACFDFuncs.h @@ -1,195 +1,118 @@ /** - * Generated on Tue, 21 Jun 2022 11:35:14 +0200. + * Generated on Tue, 28 Nov 2023 09:45:19 +0100. * - * This file contains the function macros for the RV32IMACFD core architecture. + * This file contains the function prototypes for the RV32IMACFD core architecture. */ #ifndef __RV32IMACFD_FUNCS_H #define __RV32IMACFD_FUNCS_H -#ifndef ETISS_ARCH_STATIC_FN_ONLY -#include "Arch/RV32IMACFD/RV32IMACFD.h" +#ifdef __cplusplus +extern "C" { +#endif + +#include "RV32IMACFD.h" #include "etiss/jit/CPU.h" #include "etiss/jit/System.h" #include "etiss/jit/ReturnCode.h" -#endif -#ifndef ETISS_ARCH_STATIC_FN_ONLY -static inline void raise(etiss_int32 irq, etiss_int32 mcause); -#endif +void leave(etiss_int32 priv_lvl); -#ifndef ETISS_ARCH_STATIC_FN_ONLY -static inline void leave(etiss_int32 priv_lvl); -#endif +void wait(etiss_int32 flag); -#ifndef ETISS_ARCH_STATIC_FN_ONLY -static inline void wait(etiss_int32 flag); -#endif +etiss_uint8 RV32IMACFD_extension_enabled(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_int8 extension); -#ifndef ETISS_ARCH_STATIC_FN_ONLY -static inline etiss_uint32 fadd_s(etiss_uint32, etiss_uint32, etiss_uint8); -#endif +etiss_uint32 fadd_s(etiss_uint32, etiss_uint32, etiss_uint8); -#ifndef ETISS_ARCH_STATIC_FN_ONLY -static inline etiss_uint32 fsub_s(etiss_uint32, etiss_uint32, etiss_uint8); -#endif +etiss_uint32 fsub_s(etiss_uint32, etiss_uint32, etiss_uint8); -#ifndef ETISS_ARCH_STATIC_FN_ONLY -static inline etiss_uint32 fmul_s(etiss_uint32, etiss_uint32, etiss_uint8); -#endif +etiss_uint32 fmul_s(etiss_uint32, etiss_uint32, etiss_uint8); -#ifndef ETISS_ARCH_STATIC_FN_ONLY -static inline etiss_uint32 fdiv_s(etiss_uint32, etiss_uint32, etiss_uint8); -#endif +etiss_uint32 fdiv_s(etiss_uint32, etiss_uint32, etiss_uint8); -#ifndef ETISS_ARCH_STATIC_FN_ONLY -static inline etiss_uint32 fmadd_s(etiss_uint32, etiss_uint32, etiss_uint32, etiss_uint32, etiss_uint8); -#endif +etiss_uint32 fmadd_s(etiss_uint32, etiss_uint32, etiss_uint32, etiss_uint32, etiss_uint8); -#ifndef ETISS_ARCH_STATIC_FN_ONLY -static inline etiss_uint32 fsel_s(etiss_uint32, etiss_uint32, etiss_uint32); -#endif +etiss_uint32 fsel_s(etiss_uint32, etiss_uint32, etiss_uint32); -#ifndef ETISS_ARCH_STATIC_FN_ONLY -static inline etiss_uint32 fsqrt_s(etiss_uint32, etiss_uint8); -#endif +etiss_uint32 fsqrt_s(etiss_uint32, etiss_uint8); -#ifndef ETISS_ARCH_STATIC_FN_ONLY -static inline etiss_uint32 fcmp_s(etiss_uint32, etiss_uint32, etiss_uint32); -#endif +etiss_uint32 fcmp_s(etiss_uint32, etiss_uint32, etiss_uint32); -#ifndef ETISS_ARCH_STATIC_FN_ONLY -static inline etiss_uint32 fcvt_s(etiss_uint32, etiss_uint32, etiss_uint8); -#endif +etiss_uint32 fcvt_s(etiss_uint32, etiss_uint32, etiss_uint8); -#ifndef ETISS_ARCH_STATIC_FN_ONLY -static inline etiss_uint64 fcvt_32_64(etiss_uint32, etiss_uint32, etiss_uint8); -#endif +etiss_uint64 fcvt_32_64(etiss_uint32, etiss_uint32, etiss_uint8); -#ifndef ETISS_ARCH_STATIC_FN_ONLY -static inline etiss_uint32 fcvt_64_32(etiss_uint64, etiss_uint32, etiss_uint8); -#endif +etiss_uint32 fcvt_64_32(etiss_uint64, etiss_uint32, etiss_uint8); -#ifndef ETISS_ARCH_STATIC_FN_ONLY -static inline etiss_uint32 unbox_s(etiss_uint64); -#endif +etiss_uint32 unbox_s(etiss_uint64); -#ifndef ETISS_ARCH_STATIC_FN_ONLY -static inline etiss_uint32 fclass_s(etiss_uint32); -#endif +etiss_uint32 fclass_s(etiss_uint32); -#ifndef ETISS_ARCH_STATIC_FN_ONLY -static inline etiss_uint32 fget_flags(); -#endif +etiss_uint32 fget_flags(); -#ifndef ETISS_ARCH_STATIC_FN_ONLY -static inline etiss_uint64 fadd_d(etiss_uint64, etiss_uint64, etiss_uint8); -#endif +etiss_uint8 RV32IMACFD_get_rm(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint8 rm); -#ifndef ETISS_ARCH_STATIC_FN_ONLY -static inline etiss_uint64 fsub_d(etiss_uint64, etiss_uint64, etiss_uint8); -#endif +etiss_uint64 fadd_d(etiss_uint64, etiss_uint64, etiss_uint8); -#ifndef ETISS_ARCH_STATIC_FN_ONLY -static inline etiss_uint64 fmul_d(etiss_uint64, etiss_uint64, etiss_uint8); -#endif +etiss_uint64 fsub_d(etiss_uint64, etiss_uint64, etiss_uint8); -#ifndef ETISS_ARCH_STATIC_FN_ONLY -static inline etiss_uint64 fdiv_d(etiss_uint64, etiss_uint64, etiss_uint8); -#endif +etiss_uint64 fmul_d(etiss_uint64, etiss_uint64, etiss_uint8); -#ifndef ETISS_ARCH_STATIC_FN_ONLY -static inline etiss_uint64 fmadd_d(etiss_uint64, etiss_uint64, etiss_uint64, etiss_uint32, etiss_uint8); -#endif +etiss_uint64 fdiv_d(etiss_uint64, etiss_uint64, etiss_uint8); -#ifndef ETISS_ARCH_STATIC_FN_ONLY -static inline etiss_uint64 fsel_d(etiss_uint64, etiss_uint64, etiss_uint32); -#endif +etiss_uint64 fmadd_d(etiss_uint64, etiss_uint64, etiss_uint64, etiss_uint32, etiss_uint8); -#ifndef ETISS_ARCH_STATIC_FN_ONLY -static inline etiss_uint64 fsqrt_d(etiss_uint64, etiss_uint8); -#endif +etiss_uint64 fsel_d(etiss_uint64, etiss_uint64, etiss_uint32); -#ifndef ETISS_ARCH_STATIC_FN_ONLY -static inline etiss_uint64 fcmp_d(etiss_uint64, etiss_uint64, etiss_uint32); -#endif +etiss_uint64 fsqrt_d(etiss_uint64, etiss_uint8); -#ifndef ETISS_ARCH_STATIC_FN_ONLY -static inline etiss_uint64 fcvt_d(etiss_uint64, etiss_uint32, etiss_uint8); -#endif +etiss_uint64 fcmp_d(etiss_uint64, etiss_uint64, etiss_uint32); -#ifndef ETISS_ARCH_STATIC_FN_ONLY -static inline etiss_uint32 fconv_d2f(etiss_uint64, etiss_uint8); -#endif +etiss_uint64 fcvt_d(etiss_uint64, etiss_uint32, etiss_uint8); -#ifndef ETISS_ARCH_STATIC_FN_ONLY -static inline etiss_uint64 fconv_f2d(etiss_uint32, etiss_uint8); -#endif +etiss_uint32 fconv_d2f(etiss_uint64, etiss_uint8); -#ifndef ETISS_ARCH_STATIC_FN_ONLY -static inline etiss_uint64 unbox_d(etiss_uint64); -#endif +etiss_uint64 fconv_f2d(etiss_uint32, etiss_uint8); -#ifndef ETISS_ARCH_STATIC_FN_ONLY -static inline etiss_uint64 fclass_d(etiss_uint64); -#endif +etiss_uint64 unbox_d(etiss_uint64); -#ifndef ETISS_ARCH_STATIC_FN_ONLY -static inline etiss_uint64 etiss_get_cycles(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers); -#endif +etiss_uint64 fclass_d(etiss_uint64); -#ifndef ETISS_ARCH_STATIC_FN_ONLY -static inline etiss_uint64 etiss_get_time(); -#endif +etiss_uint64 etiss_get_cycles(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers); -#ifndef ETISS_ARCH_STATIC_FN_ONLY -static inline etiss_uint64 etiss_get_instret(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers); -#endif +etiss_uint64 etiss_get_time(); -#ifndef ETISS_ARCH_STATIC_FN_ONLY -static inline etiss_uint32 csr_read(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint32 csr) -{ -if (csr == 1U) { -return *((RV32IMACFD*)cpu)->CSR[3U] & 31U; -} -if (csr == 2U) { -return (*((RV32IMACFD*)cpu)->CSR[3U] >> 5U) & 7U; -} -if (csr == 3072U) { -return etiss_get_cycles(cpu, system, plugin_pointers); -} -if (csr == 3200U) { -return etiss_get_cycles(cpu, system, plugin_pointers) >> 32U; -} -if (csr == 3073U) { -return etiss_get_time(); -} -if (csr == 3201U) { -return etiss_get_time() >> 32U; -} -if (csr == 3074U) { -return etiss_get_instret(cpu, system, plugin_pointers); -} -if (csr == 3202U) { -return etiss_get_instret(cpu, system, plugin_pointers) >> 32U; -} -return *((RV32IMACFD*)cpu)->CSR[csr]; -} -#endif +etiss_uint64 etiss_get_instret(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers); -#ifndef ETISS_ARCH_STATIC_FN_ONLY -static inline void csr_write(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint32 csr, etiss_uint32 val) -{ -if (csr == 1U) { -*((RV32IMACFD*)cpu)->CSR[3] = (*((RV32IMACFD*)cpu)->CSR[3U] & 224U) | (val & 31U); -} else if (csr == 2U) { -*((RV32IMACFD*)cpu)->CSR[3] = ((val & 7U) << 5U) | (*((RV32IMACFD*)cpu)->CSR[3U] & 31U); -} else if (csr == 3U) { -*((RV32IMACFD*)cpu)->CSR[3] = val & 255U; -} else { -*((RV32IMACFD*)cpu)->CSR[csr] = val; -} +etiss_uint32 RV32IMACFD_sstatus_mask(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers); + +etiss_uint32 RV32IMACFD_mstatus_mask(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers); + +etiss_uint32 RV32IMACFD_csr_read(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint32 csr); + +void RV32IMACFD_csr_write(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint32 csr, etiss_uint32 val); + +etiss_uint64 RV32IMACFD_get_field(etiss_uint64 reg, etiss_uint64 mask); + +etiss_uint64 RV32IMACFD_set_field(etiss_uint64 reg, etiss_uint64 mask, etiss_uint64 val); + +etiss_uint8 RV32IMACFD_ctz(etiss_uint64 val); + +void RV32IMACFD_raise(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_int32 irq, etiss_uint32 mcause); + +void RV32IMACFD_translate_exc_code(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_int32 cause); + +etiss_uint32 RV32IMACFD_calc_irq_mcause(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers); + +void RV32IMACFD_check_irq(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers); + +etiss_uint8 etiss_semihost_enabled(); + +etiss_int64 etiss_semihost(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint32 XLEN, etiss_uint64 operation, etiss_uint64 parameter); + +#ifdef __cplusplus } #endif -#endif + +#endif \ No newline at end of file diff --git a/ArchImpl/RV32IMACFD/RV32IMACFDGDBCore.h b/ArchImpl/RV32IMACFD/RV32IMACFDGDBCore.h index 833db0470a..e90ad6f481 100644 --- a/ArchImpl/RV32IMACFD/RV32IMACFDGDBCore.h +++ b/ArchImpl/RV32IMACFD/RV32IMACFDGDBCore.h @@ -1,5 +1,5 @@ /** - * Generated on Thu, 24 Feb 2022 17:15:20 +0100. + * Generated on Tue, 28 Nov 2023 09:45:19 +0100. * * This file contains the GDBCore adapter for the RV32IMACFD core architecture. * diff --git a/ArchImpl/RV32IMACFD/RV32IMACFDInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFDInstr.cpp index bd9f697eb8..59dd686e5d 100644 --- a/ArchImpl/RV32IMACFD/RV32IMACFDInstr.cpp +++ b/ArchImpl/RV32IMACFD/RV32IMACFDInstr.cpp @@ -1,13 +1,11 @@ /** - * Generated on Thu, 24 Feb 2022 17:15:20 +0100. + * Generated on Tue, 28 Nov 2023 09:45:19 +0100. * * This file contains the instruction behavior models of the default * instruction set for the RV32IMACFD core architecture. */ #include "RV32IMACFDArch.h" - -#define ETISS_ARCH_STATIC_FN_ONLY #include "RV32IMACFDFuncs.h" using namespace etiss; diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RISCVBaseInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RISCVBaseInstr.cpp deleted file mode 100644 index e36c0f55a0..0000000000 --- a/ArchImpl/RV32IMACFD/RV32IMACFD_RISCVBaseInstr.cpp +++ /dev/null @@ -1,15 +0,0 @@ -/** - * Generated on Thu, 24 Feb 2022 17:15:20 +0100. - * - * This file contains the instruction behavior models of the RISCVBase - * instruction set for the RV32IMACFD core architecture. - */ - -#include "RV32IMACFDArch.h" - -#define ETISS_ARCH_STATIC_FN_ONLY -#include "RV32IMACFDFuncs.h" - -using namespace etiss; -using namespace etiss::instr; - diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32AInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32AInstr.cpp index b53b7e3496..5985fe8db7 100644 --- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32AInstr.cpp +++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32AInstr.cpp @@ -1,13 +1,11 @@ /** - * Generated on Mon, 09 May 2022 22:10:34 +0200. + * Generated on Tue, 28 Nov 2023 09:45:19 +0100. * * This file contains the instruction behavior models of the RV32A * instruction set for the RV32IMACFD core architecture. */ #include "RV32IMACFDArch.h" - -#define ETISS_ARCH_STATIC_FN_ONLY #include "RV32IMACFDFuncs.h" using namespace etiss; @@ -28,46 +26,78 @@ static InstructionDefinition amoswapw_rd_rs1_rs2_rl_aq ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; -etiss_uint32 rl = 0; +etiss_uint8 rl = 0; static BitArrayRange R_rl_0(25, 25); rl += R_rl_0.read(ba) << 0; -etiss_uint32 aq = 0; +etiss_uint8 aq = 0; static BitArrayRange R_aq_0(26, 26); aq += R_aq_0.read(ba) << 0; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//AMOSWAPW\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n"; +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "etiss_uint32 mem_val_0;\n"; +cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int32)(((etiss_int32)(mem_val_0)));\n"; +} // conditional +cp.code() += "etiss_uint32 mem_val_1;\n"; +cp.code() += "mem_val_1 = (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n"; +cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); - partInit.code() = std::string("//AMOSWAPW\n"); + cp.code() = std::string("//AMOSWAPW\n"); // ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n"; -if ((rd % 32U) != 0U) { -partInit.code() += "etiss_uint32 mem_val_0;\n"; -partInit.code() += "exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n"; -partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_int32)(((etiss_int32)(mem_val_0)));\n"; -} -partInit.code() += "etiss_uint32 mem_val_1 = (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]);\n"; -partInit.code() += "exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n"; - -partInit.code() += "if (exception) return exception;\n"; +cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n"; // ----------------------------------------------------------------------------- - - partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32); - partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 32); - partInit.getAffectedRegisters().add(reg_name[rd % 32], 32); - partInit.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -75,19 +105,19 @@ partInit.code() += "if (exception) return exception;\n"; [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; -etiss_uint32 rl = 0; +etiss_uint8 rl = 0; static BitArrayRange R_rl_0(25, 25); rl += R_rl_0.read(ba) << 0; -etiss_uint32 aq = 0; +etiss_uint8 aq = 0; static BitArrayRange R_aq_0(26, 26); aq += R_aq_0.read(ba) << 0; @@ -115,48 +145,80 @@ static InstructionDefinition amoaddw_rd_rs1_rs2_rl_aq ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; -etiss_uint32 rl = 0; +etiss_uint8 rl = 0; static BitArrayRange R_rl_0(25, 25); rl += R_rl_0.read(ba) << 0; -etiss_uint32 aq = 0; +etiss_uint8 aq = 0; static BitArrayRange R_aq_0(26, 26); aq += R_aq_0.read(ba) << 0; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//AMOADDW\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n"; +cp.code() += "etiss_uint32 mem_val_0;\n"; +cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "etiss_int32 res1 = mem_val_0;\n"; +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res1;\n"; +} // conditional +cp.code() += "etiss_uint32 res2 = res1 + *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n"; +cp.code() += "etiss_uint32 mem_val_1;\n"; +cp.code() += "mem_val_1 = res2;\n"; +cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); - partInit.code() = std::string("//AMOADDW\n"); + cp.code() = std::string("//AMOADDW\n"); // ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n"; -partInit.code() += "etiss_uint32 mem_val_0;\n"; -partInit.code() += "exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n"; -partInit.code() += "etiss_int32 res1 = mem_val_0;\n"; -if ((rd % 32U) != 0U) { -partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = res1;\n"; -} -partInit.code() += "etiss_uint32 res2 = res1 + *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "];\n"; -partInit.code() += "etiss_uint32 mem_val_1 = res2;\n"; -partInit.code() += "exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n"; - -partInit.code() += "if (exception) return exception;\n"; +cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n"; // ----------------------------------------------------------------------------- - - partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32); - partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 32); - partInit.getAffectedRegisters().add(reg_name[rd % 32], 32); - partInit.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -164,19 +226,19 @@ partInit.code() += "if (exception) return exception;\n"; [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; -etiss_uint32 rl = 0; +etiss_uint8 rl = 0; static BitArrayRange R_rl_0(25, 25); rl += R_rl_0.read(ba) << 0; -etiss_uint32 aq = 0; +etiss_uint8 aq = 0; static BitArrayRange R_aq_0(26, 26); aq += R_aq_0.read(ba) << 0; @@ -204,48 +266,80 @@ static InstructionDefinition amoxorw_rd_rs1_rs2_rl_aq ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; -etiss_uint32 rl = 0; +etiss_uint8 rl = 0; static BitArrayRange R_rl_0(25, 25); rl += R_rl_0.read(ba) << 0; -etiss_uint32 aq = 0; +etiss_uint8 aq = 0; static BitArrayRange R_aq_0(26, 26); aq += R_aq_0.read(ba) << 0; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//AMOXORW\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n"; +cp.code() += "etiss_uint32 mem_val_0;\n"; +cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "etiss_int32 res1 = mem_val_0;\n"; +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res1;\n"; +} // conditional +cp.code() += "etiss_uint32 res2 = res1 ^ *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n"; +cp.code() += "etiss_uint32 mem_val_1;\n"; +cp.code() += "mem_val_1 = res2;\n"; +cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); - partInit.code() = std::string("//AMOXORW\n"); + cp.code() = std::string("//AMOXORW\n"); // ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n"; -partInit.code() += "etiss_uint32 mem_val_0;\n"; -partInit.code() += "exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n"; -partInit.code() += "etiss_int32 res1 = mem_val_0;\n"; -if ((rd % 32U) != 0U) { -partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = res1;\n"; -} -partInit.code() += "etiss_uint32 res2 = res1 ^ *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "];\n"; -partInit.code() += "etiss_uint32 mem_val_1 = res2;\n"; -partInit.code() += "exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n"; - -partInit.code() += "if (exception) return exception;\n"; +cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n"; // ----------------------------------------------------------------------------- - - partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32); - partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 32); - partInit.getAffectedRegisters().add(reg_name[rd % 32], 32); - partInit.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -253,19 +347,19 @@ partInit.code() += "if (exception) return exception;\n"; [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; -etiss_uint32 rl = 0; +etiss_uint8 rl = 0; static BitArrayRange R_rl_0(25, 25); rl += R_rl_0.read(ba) << 0; -etiss_uint32 aq = 0; +etiss_uint8 aq = 0; static BitArrayRange R_aq_0(26, 26); aq += R_aq_0.read(ba) << 0; @@ -293,48 +387,80 @@ static InstructionDefinition amoandw_rd_rs1_rs2_rl_aq ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; -etiss_uint32 rl = 0; +etiss_uint8 rl = 0; static BitArrayRange R_rl_0(25, 25); rl += R_rl_0.read(ba) << 0; -etiss_uint32 aq = 0; +etiss_uint8 aq = 0; static BitArrayRange R_aq_0(26, 26); aq += R_aq_0.read(ba) << 0; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//AMOANDW\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n"; +cp.code() += "etiss_uint32 mem_val_0;\n"; +cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "etiss_int32 res1 = mem_val_0;\n"; +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res1;\n"; +} // conditional +cp.code() += "etiss_uint32 res2 = res1 & *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n"; +cp.code() += "etiss_uint32 mem_val_1;\n"; +cp.code() += "mem_val_1 = res2;\n"; +cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); - partInit.code() = std::string("//AMOANDW\n"); + cp.code() = std::string("//AMOANDW\n"); // ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n"; -partInit.code() += "etiss_uint32 mem_val_0;\n"; -partInit.code() += "exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n"; -partInit.code() += "etiss_int32 res1 = mem_val_0;\n"; -if ((rd % 32U) != 0U) { -partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = res1;\n"; -} -partInit.code() += "etiss_uint32 res2 = res1 & *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "];\n"; -partInit.code() += "etiss_uint32 mem_val_1 = res2;\n"; -partInit.code() += "exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n"; - -partInit.code() += "if (exception) return exception;\n"; +cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n"; // ----------------------------------------------------------------------------- - - partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32); - partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 32); - partInit.getAffectedRegisters().add(reg_name[rd % 32], 32); - partInit.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -342,19 +468,19 @@ partInit.code() += "if (exception) return exception;\n"; [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; -etiss_uint32 rl = 0; +etiss_uint8 rl = 0; static BitArrayRange R_rl_0(25, 25); rl += R_rl_0.read(ba) << 0; -etiss_uint32 aq = 0; +etiss_uint8 aq = 0; static BitArrayRange R_aq_0(26, 26); aq += R_aq_0.read(ba) << 0; @@ -382,48 +508,80 @@ static InstructionDefinition amoorw_rd_rs1_rs2_rl_aq ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; -etiss_uint32 rl = 0; +etiss_uint8 rl = 0; static BitArrayRange R_rl_0(25, 25); rl += R_rl_0.read(ba) << 0; -etiss_uint32 aq = 0; +etiss_uint8 aq = 0; static BitArrayRange R_aq_0(26, 26); aq += R_aq_0.read(ba) << 0; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//AMOORW\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n"; +cp.code() += "etiss_uint32 mem_val_0;\n"; +cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "etiss_int32 res1 = mem_val_0;\n"; +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res1;\n"; +} // conditional +cp.code() += "etiss_uint32 res2 = res1 | *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n"; +cp.code() += "etiss_uint32 mem_val_1;\n"; +cp.code() += "mem_val_1 = res2;\n"; +cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); - partInit.code() = std::string("//AMOORW\n"); + cp.code() = std::string("//AMOORW\n"); // ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n"; -partInit.code() += "etiss_uint32 mem_val_0;\n"; -partInit.code() += "exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n"; -partInit.code() += "etiss_int32 res1 = mem_val_0;\n"; -if ((rd % 32U) != 0U) { -partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = res1;\n"; -} -partInit.code() += "etiss_uint32 res2 = res1 | *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "];\n"; -partInit.code() += "etiss_uint32 mem_val_1 = res2;\n"; -partInit.code() += "exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n"; - -partInit.code() += "if (exception) return exception;\n"; +cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n"; // ----------------------------------------------------------------------------- - - partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32); - partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 32); - partInit.getAffectedRegisters().add(reg_name[rd % 32], 32); - partInit.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -431,19 +589,19 @@ partInit.code() += "if (exception) return exception;\n"; [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; -etiss_uint32 rl = 0; +etiss_uint8 rl = 0; static BitArrayRange R_rl_0(25, 25); rl += R_rl_0.read(ba) << 0; -etiss_uint32 aq = 0; +etiss_uint8 aq = 0; static BitArrayRange R_aq_0(26, 26); aq += R_aq_0.read(ba) << 0; @@ -471,48 +629,80 @@ static InstructionDefinition amominw_rd_rs1_rs2_rl_aq ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; -etiss_uint32 rl = 0; +etiss_uint8 rl = 0; static BitArrayRange R_rl_0(25, 25); rl += R_rl_0.read(ba) << 0; -etiss_uint32 aq = 0; +etiss_uint8 aq = 0; static BitArrayRange R_aq_0(26, 26); aq += R_aq_0.read(ba) << 0; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//AMOMINW\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n"; +cp.code() += "etiss_uint32 mem_val_0;\n"; +cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "etiss_int32 res1 = mem_val_0;\n"; +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res1;\n"; +} // conditional +cp.code() += "etiss_uint32 res2 = (res1 > (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL])) ? (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) : (res1);\n"; +cp.code() += "etiss_uint32 mem_val_1;\n"; +cp.code() += "mem_val_1 = res2;\n"; +cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); - partInit.code() = std::string("//AMOMINW\n"); + cp.code() = std::string("//AMOMINW\n"); // ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n"; -partInit.code() += "etiss_uint32 mem_val_0;\n"; -partInit.code() += "exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n"; -partInit.code() += "etiss_int32 res1 = mem_val_0;\n"; -if ((rd % 32U) != 0U) { -partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = res1;\n"; -} -partInit.code() += "etiss_uint32 res2 = (res1 > (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "])) ? (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]) : (res1);\n"; -partInit.code() += "etiss_uint32 mem_val_1 = res2;\n"; -partInit.code() += "exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n"; - -partInit.code() += "if (exception) return exception;\n"; +cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n"; // ----------------------------------------------------------------------------- - - partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32); - partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 32); - partInit.getAffectedRegisters().add(reg_name[rd % 32], 32); - partInit.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -520,19 +710,19 @@ partInit.code() += "if (exception) return exception;\n"; [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; -etiss_uint32 rl = 0; +etiss_uint8 rl = 0; static BitArrayRange R_rl_0(25, 25); rl += R_rl_0.read(ba) << 0; -etiss_uint32 aq = 0; +etiss_uint8 aq = 0; static BitArrayRange R_aq_0(26, 26); aq += R_aq_0.read(ba) << 0; @@ -560,48 +750,80 @@ static InstructionDefinition amomaxw_rd_rs1_rs2_rl_aq ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; -etiss_uint32 rl = 0; +etiss_uint8 rl = 0; static BitArrayRange R_rl_0(25, 25); rl += R_rl_0.read(ba) << 0; -etiss_uint32 aq = 0; +etiss_uint8 aq = 0; static BitArrayRange R_aq_0(26, 26); aq += R_aq_0.read(ba) << 0; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//AMOMAXW\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n"; +cp.code() += "etiss_uint32 mem_val_0;\n"; +cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "etiss_int32 res1 = mem_val_0;\n"; +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res1;\n"; +} // conditional +cp.code() += "etiss_uint32 res2 = (res1 < (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL])) ? (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) : (res1);\n"; +cp.code() += "etiss_uint32 mem_val_1;\n"; +cp.code() += "mem_val_1 = res2;\n"; +cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); - partInit.code() = std::string("//AMOMAXW\n"); + cp.code() = std::string("//AMOMAXW\n"); // ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n"; -partInit.code() += "etiss_uint32 mem_val_0;\n"; -partInit.code() += "exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n"; -partInit.code() += "etiss_int32 res1 = mem_val_0;\n"; -if ((rd % 32U) != 0U) { -partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = res1;\n"; -} -partInit.code() += "etiss_uint32 res2 = (res1 < (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "])) ? (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]) : (res1);\n"; -partInit.code() += "etiss_uint32 mem_val_1 = res2;\n"; -partInit.code() += "exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n"; - -partInit.code() += "if (exception) return exception;\n"; +cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n"; // ----------------------------------------------------------------------------- - - partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32); - partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 32); - partInit.getAffectedRegisters().add(reg_name[rd % 32], 32); - partInit.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -609,19 +831,19 @@ partInit.code() += "if (exception) return exception;\n"; [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; -etiss_uint32 rl = 0; +etiss_uint8 rl = 0; static BitArrayRange R_rl_0(25, 25); rl += R_rl_0.read(ba) << 0; -etiss_uint32 aq = 0; +etiss_uint8 aq = 0; static BitArrayRange R_aq_0(26, 26); aq += R_aq_0.read(ba) << 0; @@ -649,48 +871,80 @@ static InstructionDefinition amominuw_rd_rs1_rs2_rl_aq ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; -etiss_uint32 rl = 0; +etiss_uint8 rl = 0; static BitArrayRange R_rl_0(25, 25); rl += R_rl_0.read(ba) << 0; -etiss_uint32 aq = 0; +etiss_uint8 aq = 0; static BitArrayRange R_aq_0(26, 26); aq += R_aq_0.read(ba) << 0; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//AMOMINUW\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n"; +cp.code() += "etiss_uint32 mem_val_0;\n"; +cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "etiss_uint32 res1 = mem_val_0;\n"; +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int32)(res1);\n"; +} // conditional +cp.code() += "etiss_uint32 res2 = (res1 > (etiss_uint32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL])) ? (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) : (res1);\n"; +cp.code() += "etiss_uint32 mem_val_1;\n"; +cp.code() += "mem_val_1 = res2;\n"; +cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); - partInit.code() = std::string("//AMOMINUW\n"); + cp.code() = std::string("//AMOMINUW\n"); // ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n"; -partInit.code() += "etiss_uint32 mem_val_0;\n"; -partInit.code() += "exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n"; -partInit.code() += "etiss_uint32 res1 = mem_val_0;\n"; -if ((rd % 32U) != 0U) { -partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_int32)(res1);\n"; -} -partInit.code() += "etiss_uint32 res2 = (res1 > *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]) ? (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]) : (res1);\n"; -partInit.code() += "etiss_uint32 mem_val_1 = res2;\n"; -partInit.code() += "exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n"; - -partInit.code() += "if (exception) return exception;\n"; +cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n"; // ----------------------------------------------------------------------------- - - partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32); - partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 32); - partInit.getAffectedRegisters().add(reg_name[rd % 32], 32); - partInit.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -698,19 +952,19 @@ partInit.code() += "if (exception) return exception;\n"; [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; -etiss_uint32 rl = 0; +etiss_uint8 rl = 0; static BitArrayRange R_rl_0(25, 25); rl += R_rl_0.read(ba) << 0; -etiss_uint32 aq = 0; +etiss_uint8 aq = 0; static BitArrayRange R_aq_0(26, 26); aq += R_aq_0.read(ba) << 0; @@ -738,48 +992,80 @@ static InstructionDefinition amomaxuw_rd_rs1_rs2_rl_aq ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; -etiss_uint32 rl = 0; +etiss_uint8 rl = 0; static BitArrayRange R_rl_0(25, 25); rl += R_rl_0.read(ba) << 0; -etiss_uint32 aq = 0; +etiss_uint8 aq = 0; static BitArrayRange R_aq_0(26, 26); aq += R_aq_0.read(ba) << 0; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//AMOMAXUW\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n"; +cp.code() += "etiss_uint32 mem_val_0;\n"; +cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "etiss_uint32 res1 = mem_val_0;\n"; +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int32)(res1);\n"; +} // conditional +cp.code() += "etiss_uint32 res2 = (res1 < (etiss_uint32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL])) ? (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) : (res1);\n"; +cp.code() += "etiss_uint32 mem_val_1;\n"; +cp.code() += "mem_val_1 = res2;\n"; +cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); - partInit.code() = std::string("//AMOMAXUW\n"); + cp.code() = std::string("//AMOMAXUW\n"); // ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n"; -partInit.code() += "etiss_uint32 mem_val_0;\n"; -partInit.code() += "exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n"; -partInit.code() += "etiss_uint32 res1 = mem_val_0;\n"; -if ((rd % 32U) != 0U) { -partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_int32)(res1);\n"; -} -partInit.code() += "etiss_uint32 res2 = (res1 < *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]) ? (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]) : (res1);\n"; -partInit.code() += "etiss_uint32 mem_val_1 = res2;\n"; -partInit.code() += "exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n"; - -partInit.code() += "if (exception) return exception;\n"; +cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n"; // ----------------------------------------------------------------------------- - - partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32); - partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 32); - partInit.getAffectedRegisters().add(reg_name[rd % 32], 32); - partInit.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -787,19 +1073,19 @@ partInit.code() += "if (exception) return exception;\n"; [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; -etiss_uint32 rl = 0; +etiss_uint8 rl = 0; static BitArrayRange R_rl_0(25, 25); rl += R_rl_0.read(ba) << 0; -etiss_uint32 aq = 0; +etiss_uint8 aq = 0; static BitArrayRange R_aq_0(26, 26); aq += R_aq_0.read(ba) << 0; diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DCInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DCInstr.cpp index 8a625e65eb..4b201ed078 100644 --- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DCInstr.cpp +++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DCInstr.cpp @@ -1,13 +1,11 @@ /** - * Generated on Thu, 03 Mar 2022 12:13:52 +0100. + * Generated on Tue, 28 Nov 2023 09:45:19 +0100. * * This file contains the instruction behavior models of the RV32DC * instruction set for the RV32IMACFD core architecture. */ #include "RV32IMACFDArch.h" - -#define ETISS_ARCH_STATIC_FN_ONLY #include "RV32IMACFDFuncs.h" using namespace etiss; @@ -28,13 +26,13 @@ static InstructionDefinition cfld_rd_uimm_rs1 ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(4, 2); rd += R_rd_0.read(ba) << 0; -etiss_uint32 uimm = 0; +etiss_uint8 uimm = 0; static BitArrayRange R_uimm_6(6, 5); uimm += R_uimm_6.read(ba) << 6; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(9, 7); rs1 += R_rs1_0.read(ba) << 0; static BitArrayRange R_uimm_3(12, 10); @@ -42,22 +40,48 @@ uimm += R_uimm_3.read(ba) << 3; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//CFLD\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] + " + std::to_string(uimm) + "ULL;\n"; +cp.code() += "etiss_uint64 mem_val_0;\n"; +cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "etiss_uint64 res = (etiss_uint64)(mem_val_0);\n"; +cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd + 8ULL) + "ULL] = res;\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); - partInit.code() = std::string("//CFLD\n"); + cp.code() = std::string("//CFLD\n"); // ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 2U) + ";\n"; -partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "] + " + std::to_string(uimm) + ";\n"; -partInit.code() += "etiss_uint64 mem_val_0;\n"; -partInit.code() += "exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n"; -partInit.code() += "etiss_uint64 res = (etiss_uint64)(mem_val_0);\n"; -partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd + 8U) + "] = res;\n"; -partInit.code() += "if (exception) return exception;\n"; +cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n"; // ----------------------------------------------------------------------------- - - partInit.getRegisterDependencies().add(reg_name[rs1 + 8U], 32); - partInit.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -65,13 +89,13 @@ partInit.code() += "if (exception) return exception;\n"; [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(4, 2); rd += R_rd_0.read(ba) << 0; -etiss_uint32 uimm = 0; +etiss_uint8 uimm = 0; static BitArrayRange R_uimm_6(6, 5); uimm += R_uimm_6.read(ba) << 6; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(9, 7); rs1 += R_rs1_0.read(ba) << 0; static BitArrayRange R_uimm_3(12, 10); @@ -101,13 +125,13 @@ static InstructionDefinition cfsd_rs2_uimm_rs1 ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(4, 2); rs2 += R_rs2_0.read(ba) << 0; -etiss_uint32 uimm = 0; +etiss_uint8 uimm = 0; static BitArrayRange R_uimm_6(6, 5); uimm += R_uimm_6.read(ba) << 6; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(9, 7); rs1 += R_rs1_0.read(ba) << 0; static BitArrayRange R_uimm_3(12, 10); @@ -115,21 +139,47 @@ uimm += R_uimm_3.read(ba) << 3; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//CFSD\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] + " + std::to_string(uimm) + "ULL;\n"; +cp.code() += "etiss_uint64 mem_val_0;\n"; +cp.code() += "mem_val_0 = (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2 + 8ULL) + "ULL]);\n"; +cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); - partInit.code() = std::string("//CFSD\n"); + cp.code() = std::string("//CFSD\n"); // ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 2U) + ";\n"; -partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "] + " + std::to_string(uimm) + ";\n"; -partInit.code() += "etiss_uint64 mem_val_0 = (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2 + 8U) + "]);\n"; -partInit.code() += "exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n"; - -partInit.code() += "if (exception) return exception;\n"; +cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n"; // ----------------------------------------------------------------------------- - - partInit.getRegisterDependencies().add(reg_name[rs1 + 8U], 32); - partInit.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -137,13 +187,13 @@ partInit.code() += "if (exception) return exception;\n"; [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(4, 2); rs2 += R_rs2_0.read(ba) << 0; -etiss_uint32 uimm = 0; +etiss_uint8 uimm = 0; static BitArrayRange R_uimm_6(6, 5); uimm += R_uimm_6.read(ba) << 6; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(9, 7); rs1 += R_rs1_0.read(ba) << 0; static BitArrayRange R_uimm_3(12, 10); @@ -173,12 +223,12 @@ static InstructionDefinition cfldsp_uimm_rd ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 uimm = 0; +etiss_uint16 uimm = 0; static BitArrayRange R_uimm_6(4, 2); uimm += R_uimm_6.read(ba) << 6; static BitArrayRange R_uimm_3(6, 5); uimm += R_uimm_3.read(ba) << 3; -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; static BitArrayRange R_uimm_5(12, 12); @@ -186,22 +236,48 @@ uimm += R_uimm_5.read(ba) << 5; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//CFLDSP\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[2ULL] + " + std::to_string(uimm) + "ULL;\n"; +cp.code() += "etiss_uint64 mem_val_0;\n"; +cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "etiss_uint64 res = (etiss_uint64)(mem_val_0);\n"; +cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); - partInit.code() = std::string("//CFLDSP\n"); + cp.code() = std::string("//CFLDSP\n"); // ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 2U) + ";\n"; -partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(2U) + "] + " + std::to_string(uimm) + ";\n"; -partInit.code() += "etiss_uint64 mem_val_0;\n"; -partInit.code() += "exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n"; -partInit.code() += "etiss_uint64 res = (etiss_uint64)(mem_val_0);\n"; -partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n"; -partInit.code() += "if (exception) return exception;\n"; +cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n"; // ----------------------------------------------------------------------------- - - partInit.getRegisterDependencies().add(reg_name[2U], 32); - partInit.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -209,12 +285,12 @@ partInit.code() += "if (exception) return exception;\n"; [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 uimm = 0; +etiss_uint16 uimm = 0; static BitArrayRange R_uimm_6(4, 2); uimm += R_uimm_6.read(ba) << 6; static BitArrayRange R_uimm_3(6, 5); uimm += R_uimm_3.read(ba) << 3; -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; static BitArrayRange R_uimm_5(12, 12); @@ -244,10 +320,10 @@ static InstructionDefinition cfsdsp_rs2_uimm ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(6, 2); rs2 += R_rs2_0.read(ba) << 0; -etiss_uint32 uimm = 0; +etiss_uint16 uimm = 0; static BitArrayRange R_uimm_6(9, 7); uimm += R_uimm_6.read(ba) << 6; static BitArrayRange R_uimm_3(12, 10); @@ -255,21 +331,47 @@ uimm += R_uimm_3.read(ba) << 3; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//CFSDSP\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[2ULL] + " + std::to_string(uimm) + "ULL;\n"; +cp.code() += "etiss_uint64 mem_val_0;\n"; +cp.code() += "mem_val_0 = (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n"; +cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); - partInit.code() = std::string("//CFSDSP\n"); + cp.code() = std::string("//CFSDSP\n"); // ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 2U) + ";\n"; -partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(2U) + "] + " + std::to_string(uimm) + ";\n"; -partInit.code() += "etiss_uint64 mem_val_0 = (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]);\n"; -partInit.code() += "exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n"; - -partInit.code() += "if (exception) return exception;\n"; +cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n"; // ----------------------------------------------------------------------------- - - partInit.getRegisterDependencies().add(reg_name[2U], 32); - partInit.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -277,10 +379,10 @@ partInit.code() += "if (exception) return exception;\n"; [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(6, 2); rs2 += R_rs2_0.read(ba) << 0; -etiss_uint32 uimm = 0; +etiss_uint16 uimm = 0; static BitArrayRange R_uimm_6(9, 7); uimm += R_uimm_6.read(ba) << 6; static BitArrayRange R_uimm_3(12, 10); diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DInstr.cpp index 0b9a4c2882..694895002b 100644 --- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DInstr.cpp +++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DInstr.cpp @@ -1,13 +1,11 @@ /** - * Generated on Mon, 09 May 2022 21:45:21 +0200. + * Generated on Tue, 28 Nov 2023 09:45:19 +0100. * * This file contains the instruction behavior models of the RV32D * instruction set for the RV32IMACFD core architecture. */ #include "RV32IMACFDArch.h" - -#define ETISS_ARCH_STATIC_FN_ONLY #include "RV32IMACFDFuncs.h" using namespace etiss; @@ -28,34 +26,60 @@ static InstructionDefinition fld_rd_rs1_imm ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 imm = 0; +etiss_uint16 imm = 0; static BitArrayRange R_imm_0(31, 20); imm += R_imm_0.read(ba) << 0; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//FLD\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n"; +cp.code() += "etiss_uint64 mem_val_0;\n"; +cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "etiss_uint64 res = (etiss_uint64)(mem_val_0);\n"; +cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); - partInit.code() = std::string("//FLD\n"); + cp.code() = std::string("//FLD\n"); // ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n"; -partInit.code() += "etiss_uint64 mem_val_0;\n"; -partInit.code() += "exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n"; -partInit.code() += "etiss_uint64 res = (etiss_uint64)(mem_val_0);\n"; -partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n"; -partInit.code() += "if (exception) return exception;\n"; +cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n"; // ----------------------------------------------------------------------------- - - partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32); - partInit.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -63,13 +87,13 @@ partInit.code() += "if (exception) return exception;\n"; [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 imm = 0; +etiss_uint16 imm = 0; static BitArrayRange R_imm_0(31, 20); imm += R_imm_0.read(ba) << 0; @@ -97,13 +121,13 @@ static InstructionDefinition fsd_imm_rs1_rs2 ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 imm = 0; +etiss_uint16 imm = 0; static BitArrayRange R_imm_0(11, 7); imm += R_imm_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; static BitArrayRange R_imm_5(31, 25); @@ -111,21 +135,47 @@ imm += R_imm_5.read(ba) << 5; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//FSD\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n"; +cp.code() += "etiss_uint64 mem_val_0;\n"; +cp.code() += "mem_val_0 = (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n"; +cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); - partInit.code() = std::string("//FSD\n"); + cp.code() = std::string("//FSD\n"); // ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n"; -partInit.code() += "etiss_uint64 mem_val_0 = (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]);\n"; -partInit.code() += "exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n"; - -partInit.code() += "if (exception) return exception;\n"; +cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n"; // ----------------------------------------------------------------------------- - - partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32); - partInit.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -133,13 +183,13 @@ partInit.code() += "if (exception) return exception;\n"; [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 imm = 0; +etiss_uint16 imm = 0; static BitArrayRange R_imm_0(11, 7); imm += R_imm_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; static BitArrayRange R_imm_5(31, 25); @@ -169,37 +219,48 @@ static InstructionDefinition fmadd_d_rd_rm_rs1_rs2_rs3 ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rm = 0; +etiss_uint8 rm = 0; static BitArrayRange R_rm_0(14, 12); rm += R_rm_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; -etiss_uint32 rs3 = 0; +etiss_uint8 rs3 = 0; static BitArrayRange R_rs3_0(31, 27); rs3 += R_rs3_0.read(ba) << 0; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); - - partInit.code() = std::string("//FMADD_D\n"); - -// ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -partInit.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "]), 0U, (" + std::to_string(rm < 7U) + ") ? (" + std::to_string(rm) + ") : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n"; -partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n"; -partInit.code() += "etiss_uint32 flags = fget_flags();\n"; -partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32U) | (flags & 31U);\n"; -// ----------------------------------------------------------------------------- - - partInit.getAffectedRegisters().add("instructionPointer", 32); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//FMADD_D\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 0ULL, RV32IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n"; +cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n"; +cp.code() += "etiss_uint32 flags = fget_flags();\n"; +cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -207,19 +268,19 @@ partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32U) [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rm = 0; +etiss_uint8 rm = 0; static BitArrayRange R_rm_0(14, 12); rm += R_rm_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; -etiss_uint32 rs3 = 0; +etiss_uint8 rs3 = 0; static BitArrayRange R_rs3_0(31, 27); rs3 += R_rs3_0.read(ba) << 0; @@ -247,37 +308,48 @@ static InstructionDefinition fmsub_d_rd_rm_rs1_rs2_rs3 ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rm = 0; +etiss_uint8 rm = 0; static BitArrayRange R_rm_0(14, 12); rm += R_rm_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; -etiss_uint32 rs3 = 0; +etiss_uint8 rs3 = 0; static BitArrayRange R_rs3_0(31, 27); rs3 += R_rs3_0.read(ba) << 0; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); - - partInit.code() = std::string("//FMSUB_D\n"); - -// ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -partInit.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "]), 1U, (" + std::to_string(rm < 7U) + ") ? (" + std::to_string(rm) + ") : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n"; -partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n"; -partInit.code() += "etiss_uint32 flags = fget_flags();\n"; -partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32U) | (flags & 31U);\n"; -// ----------------------------------------------------------------------------- - - partInit.getAffectedRegisters().add("instructionPointer", 32); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//FMSUB_D\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 1ULL, RV32IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n"; +cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n"; +cp.code() += "etiss_uint32 flags = fget_flags();\n"; +cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -285,19 +357,19 @@ partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32U) [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rm = 0; +etiss_uint8 rm = 0; static BitArrayRange R_rm_0(14, 12); rm += R_rm_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; -etiss_uint32 rs3 = 0; +etiss_uint8 rs3 = 0; static BitArrayRange R_rs3_0(31, 27); rs3 += R_rs3_0.read(ba) << 0; @@ -325,37 +397,48 @@ static InstructionDefinition fnmadd_d_rd_rm_rs1_rs2_rs3 ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rm = 0; +etiss_uint8 rm = 0; static BitArrayRange R_rm_0(14, 12); rm += R_rm_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; -etiss_uint32 rs3 = 0; +etiss_uint8 rs3 = 0; static BitArrayRange R_rs3_0(31, 27); rs3 += R_rs3_0.read(ba) << 0; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); - - partInit.code() = std::string("//FNMADD_D\n"); - -// ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -partInit.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "]), 2U, (" + std::to_string(rm < 7U) + ") ? (" + std::to_string(rm) + ") : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n"; -partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n"; -partInit.code() += "etiss_uint32 flags = fget_flags();\n"; -partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32U) | (flags & 31U);\n"; -// ----------------------------------------------------------------------------- - - partInit.getAffectedRegisters().add("instructionPointer", 32); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//FNMADD_D\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 2ULL, RV32IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n"; +cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n"; +cp.code() += "etiss_uint32 flags = fget_flags();\n"; +cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -363,19 +446,19 @@ partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32U) [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rm = 0; +etiss_uint8 rm = 0; static BitArrayRange R_rm_0(14, 12); rm += R_rm_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; -etiss_uint32 rs3 = 0; +etiss_uint8 rs3 = 0; static BitArrayRange R_rs3_0(31, 27); rs3 += R_rs3_0.read(ba) << 0; @@ -403,37 +486,48 @@ static InstructionDefinition fnmsub_d_rd_rm_rs1_rs2_rs3 ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rm = 0; +etiss_uint8 rm = 0; static BitArrayRange R_rm_0(14, 12); rm += R_rm_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; -etiss_uint32 rs3 = 0; +etiss_uint8 rs3 = 0; static BitArrayRange R_rs3_0(31, 27); rs3 += R_rs3_0.read(ba) << 0; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); - - partInit.code() = std::string("//FNMSUB_D\n"); - -// ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -partInit.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "]), 3U, (" + std::to_string(rm < 7U) + ") ? (" + std::to_string(rm) + ") : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n"; -partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n"; -partInit.code() += "etiss_uint32 flags = fget_flags();\n"; -partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32U) | (flags & 31U);\n"; -// ----------------------------------------------------------------------------- - - partInit.getAffectedRegisters().add("instructionPointer", 32); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//FNMSUB_D\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 3ULL, RV32IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n"; +cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n"; +cp.code() += "etiss_uint32 flags = fget_flags();\n"; +cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -441,19 +535,19 @@ partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32U) [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rm = 0; +etiss_uint8 rm = 0; static BitArrayRange R_rm_0(14, 12); rm += R_rm_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; -etiss_uint32 rs3 = 0; +etiss_uint8 rs3 = 0; static BitArrayRange R_rs3_0(31, 27); rs3 += R_rs3_0.read(ba) << 0; @@ -481,34 +575,45 @@ static InstructionDefinition fadd_d_rd_rm_rs1_rs2 ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rm = 0; +etiss_uint8 rm = 0; static BitArrayRange R_rm_0(14, 12); rm += R_rm_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); - - partInit.code() = std::string("//FADD_D\n"); - -// ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -partInit.code() += "etiss_uint64 res = fadd_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]), (" + std::to_string(rm < 7U) + ") ? (" + std::to_string(rm) + ") : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n"; -partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n"; -partInit.code() += "etiss_uint32 flags = fget_flags();\n"; -partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32U) | (flags & 31U);\n"; -// ----------------------------------------------------------------------------- - - partInit.getAffectedRegisters().add("instructionPointer", 32); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//FADD_D\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint64 res = fadd_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), RV32IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n"; +cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n"; +cp.code() += "etiss_uint32 flags = fget_flags();\n"; +cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -516,16 +621,16 @@ partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32U) [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rm = 0; +etiss_uint8 rm = 0; static BitArrayRange R_rm_0(14, 12); rm += R_rm_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; @@ -553,34 +658,45 @@ static InstructionDefinition fsub_d_rd_rm_rs1_rs2 ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rm = 0; +etiss_uint8 rm = 0; static BitArrayRange R_rm_0(14, 12); rm += R_rm_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); - - partInit.code() = std::string("//FSUB_D\n"); - -// ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -partInit.code() += "etiss_uint64 res = fsub_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]), (" + std::to_string(rm < 7U) + ") ? (" + std::to_string(rm) + ") : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n"; -partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n"; -partInit.code() += "etiss_uint32 flags = fget_flags();\n"; -partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32U) | (flags & 31U);\n"; -// ----------------------------------------------------------------------------- - - partInit.getAffectedRegisters().add("instructionPointer", 32); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//FSUB_D\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint64 res = fsub_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), RV32IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n"; +cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n"; +cp.code() += "etiss_uint32 flags = fget_flags();\n"; +cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -588,16 +704,16 @@ partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32U) [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rm = 0; +etiss_uint8 rm = 0; static BitArrayRange R_rm_0(14, 12); rm += R_rm_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; @@ -625,34 +741,45 @@ static InstructionDefinition fmul_d_rd_rm_rs1_rs2 ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rm = 0; +etiss_uint8 rm = 0; static BitArrayRange R_rm_0(14, 12); rm += R_rm_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); - - partInit.code() = std::string("//FMUL_D\n"); - -// ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -partInit.code() += "etiss_uint64 res = fmul_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]), (" + std::to_string(rm < 7U) + ") ? (" + std::to_string(rm) + ") : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n"; -partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n"; -partInit.code() += "etiss_uint32 flags = fget_flags();\n"; -partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32U) | (flags & 31U);\n"; -// ----------------------------------------------------------------------------- - - partInit.getAffectedRegisters().add("instructionPointer", 32); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//FMUL_D\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint64 res = fmul_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), RV32IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n"; +cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n"; +cp.code() += "etiss_uint32 flags = fget_flags();\n"; +cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -660,16 +787,16 @@ partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32U) [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rm = 0; +etiss_uint8 rm = 0; static BitArrayRange R_rm_0(14, 12); rm += R_rm_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; @@ -697,34 +824,45 @@ static InstructionDefinition fdiv_d_rd_rm_rs1_rs2 ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rm = 0; +etiss_uint8 rm = 0; static BitArrayRange R_rm_0(14, 12); rm += R_rm_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); - - partInit.code() = std::string("//FDIV_D\n"); - -// ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -partInit.code() += "etiss_uint64 res = fdiv_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]), (" + std::to_string(rm < 7U) + ") ? (" + std::to_string(rm) + ") : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n"; -partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n"; -partInit.code() += "etiss_uint32 flags = fget_flags();\n"; -partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32U) | (flags & 31U);\n"; -// ----------------------------------------------------------------------------- - - partInit.getAffectedRegisters().add("instructionPointer", 32); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//FDIV_D\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint64 res = fdiv_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), RV32IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n"; +cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n"; +cp.code() += "etiss_uint32 flags = fget_flags();\n"; +cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -732,16 +870,16 @@ partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32U) [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rm = 0; +etiss_uint8 rm = 0; static BitArrayRange R_rm_0(14, 12); rm += R_rm_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; @@ -769,31 +907,42 @@ static InstructionDefinition fsqrt_d_rd_rm_rs1 ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rm = 0; +etiss_uint8 rm = 0; static BitArrayRange R_rm_0(14, 12); rm += R_rm_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); - - partInit.code() = std::string("//FSQRT_D\n"); - -// ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -partInit.code() += "etiss_uint64 res = fsqrt_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]), (" + std::to_string(rm < 7U) + ") ? (" + std::to_string(rm) + ") : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n"; -partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n"; -partInit.code() += "etiss_uint32 flags = fget_flags();\n"; -partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32U) | (flags & 31U);\n"; -// ----------------------------------------------------------------------------- - - partInit.getAffectedRegisters().add("instructionPointer", 32); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//FSQRT_D\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint64 res = fsqrt_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), RV32IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n"; +cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n"; +cp.code() += "etiss_uint32 flags = fget_flags();\n"; +cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -801,13 +950,13 @@ partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32U) [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rm = 0; +etiss_uint8 rm = 0; static BitArrayRange R_rm_0(14, 12); rm += R_rm_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; @@ -835,29 +984,40 @@ static InstructionDefinition fsgnj_d_rd_rs1_rs2 ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); - - partInit.code() = std::string("//FSGNJ_D\n"); - -// ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -partInit.code() += "etiss_uint64 res = ((((((((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]) >> (63U)) & 1)) << 63) | ((((((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]) >> (0U)) & 9223372036854775807)));\n"; -partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n"; -// ----------------------------------------------------------------------------- - - partInit.getAffectedRegisters().add("instructionPointer", 32); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//FSGNJ_D\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint64 res = ((((((((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]) >> (63ULL)) & 1)) << 63) | ((((((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]) >> (0ULL)) & 9223372036854775807)));\n"; +cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -865,13 +1025,13 @@ partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n"; [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; @@ -899,29 +1059,40 @@ static InstructionDefinition fsgnjn_d_rd_rs1_rs2 ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); - - partInit.code() = std::string("//FSGNJN_D\n"); - -// ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -partInit.code() += "etiss_uint64 res = (((~((((((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]) >> (63U)) & 1))) << 63) | ((((((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]) >> (0U)) & 9223372036854775807)));\n"; -partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n"; -// ----------------------------------------------------------------------------- - - partInit.getAffectedRegisters().add("instructionPointer", 32); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//FSGNJN_D\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint64 res = (((~((((((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]) >> (63ULL)) & 1))) << 63) | ((((((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]) >> (0ULL)) & 9223372036854775807)));\n"; +cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -929,13 +1100,13 @@ partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n"; [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; @@ -963,29 +1134,40 @@ static InstructionDefinition fsgnjx_d_rd_rs1_rs2 ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); - - partInit.code() = std::string("//FSGNJX_D\n"); - -// ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -partInit.code() += "etiss_uint64 res = (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]) ^ ((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]) & 9223372036854775808UL);\n"; -partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n"; -// ----------------------------------------------------------------------------- - - partInit.getAffectedRegisters().add("instructionPointer", 32); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//FSGNJX_D\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint64 res = (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]) ^ ((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]) & 9223372036854775808ULL);\n"; +cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -993,13 +1175,13 @@ partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n"; [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; @@ -1027,31 +1209,42 @@ static InstructionDefinition fmin_d_rd_rs1_rs2 ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); - - partInit.code() = std::string("//FMIN_D\n"); - -// ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -partInit.code() += "etiss_uint64 res = fsel_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]), 0U);\n"; -partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n"; -partInit.code() += "etiss_uint32 flags = fget_flags();\n"; -partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32U) | (flags & 31U);\n"; -// ----------------------------------------------------------------------------- - - partInit.getAffectedRegisters().add("instructionPointer", 32); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//FMIN_D\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint64 res = fsel_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), 0ULL);\n"; +cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n"; +cp.code() += "etiss_uint32 flags = fget_flags();\n"; +cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -1059,13 +1252,13 @@ partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32U) [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; @@ -1093,31 +1286,42 @@ static InstructionDefinition fmax_d_rd_rs1_rs2 ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); - - partInit.code() = std::string("//FMAX_D\n"); - -// ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -partInit.code() += "etiss_uint64 res = fsel_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]), 1U);\n"; -partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n"; -partInit.code() += "etiss_uint32 flags = fget_flags();\n"; -partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32U) | (flags & 31U);\n"; -// ----------------------------------------------------------------------------- - - partInit.getAffectedRegisters().add("instructionPointer", 32); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//FMAX_D\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint64 res = fsel_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), 1ULL);\n"; +cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n"; +cp.code() += "etiss_uint32 flags = fget_flags();\n"; +cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -1125,13 +1329,13 @@ partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32U) [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; @@ -1159,29 +1363,40 @@ static InstructionDefinition fcvt_s_d_rd_rm_rs1 ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rm = 0; +etiss_uint8 rm = 0; static BitArrayRange R_rm_0(14, 12); rm += R_rm_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); - - partInit.code() = std::string("//FCVT_S_D\n"); - -// ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -partInit.code() += "etiss_uint32 res = fconv_d2f(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "], " + std::to_string(rm) + ");\n"; -partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296UL + res;\n"; -// ----------------------------------------------------------------------------- - - partInit.getAffectedRegisters().add("instructionPointer", 32); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//FCVT_S_D\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint32 res = fconv_d2f(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL], " + std::to_string(rm) + "ULL);\n"; +cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL + res;\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -1189,13 +1404,13 @@ partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967 [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rm = 0; +etiss_uint8 rm = 0; static BitArrayRange R_rm_0(14, 12); rm += R_rm_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; @@ -1223,29 +1438,44 @@ static InstructionDefinition fcvt_d_s_rd_rm_rs1 ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rm = 0; +etiss_uint8 rm = 0; static BitArrayRange R_rm_0(14, 12); rm += R_rm_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); - - partInit.code() = std::string("//FCVT_D_S\n"); - -// ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -partInit.code() += "etiss_uint64 res = fconv_f2d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]), " + std::to_string(rm) + ");\n"; -partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n"; -// ----------------------------------------------------------------------------- - - partInit.getAffectedRegisters().add("instructionPointer", 32); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//FCVT_D_S\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint64 res = fconv_f2d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), " + std::to_string(rm) + "ULL);\n"; +{ // block +cp.code() += "{ // block\n"; +cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -1253,13 +1483,13 @@ partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n"; [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rm = 0; +etiss_uint8 rm = 0; static BitArrayRange R_rm_0(14, 12); rm += R_rm_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; @@ -1287,35 +1517,45 @@ static InstructionDefinition feq_d_rd_rs1_rs2 ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); - - partInit.code() = std::string("//FEQ_D\n"); - -// ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -partInit.code() += "etiss_uint64 res = 0U;\n"; -partInit.code() += "res = fcmp_d(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "], ((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "], 0U);\n"; -if ((rd % 32U) != 0U) { -partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = res;\n"; -} -partInit.code() += "etiss_uint32 flags = fget_flags();\n"; -partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32U) | (flags & 31U);\n"; -// ----------------------------------------------------------------------------- - - partInit.getAffectedRegisters().add(reg_name[rd % 32], 32); - partInit.getAffectedRegisters().add("instructionPointer", 32); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//FEQ_D\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint64 res = 0ULL;\n"; +cp.code() += "res = fcmp_d(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL], ((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL], 0ULL);\n"; +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res;\n"; +} // conditional +cp.code() += "etiss_uint32 flags = fget_flags();\n"; +cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -1323,13 +1563,13 @@ partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32U) [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; @@ -1357,35 +1597,45 @@ static InstructionDefinition flt_d_rd_rs1_rs2 ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); - - partInit.code() = std::string("//FLT_D\n"); - -// ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -partInit.code() += "etiss_uint64 res = 0U;\n"; -partInit.code() += "res = fcmp_d(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "], ((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "], 2U);\n"; -if ((rd % 32U) != 0U) { -partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = res;\n"; -} -partInit.code() += "etiss_uint32 flags = fget_flags();\n"; -partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32U) | (flags & 31U);\n"; -// ----------------------------------------------------------------------------- - - partInit.getAffectedRegisters().add(reg_name[rd % 32], 32); - partInit.getAffectedRegisters().add("instructionPointer", 32); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//FLT_D\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint64 res = 0ULL;\n"; +cp.code() += "res = fcmp_d(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL], ((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL], 2ULL);\n"; +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res;\n"; +} // conditional +cp.code() += "etiss_uint32 flags = fget_flags();\n"; +cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -1393,13 +1643,13 @@ partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32U) [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; @@ -1427,35 +1677,45 @@ static InstructionDefinition fle_d_rd_rs1_rs2 ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); - - partInit.code() = std::string("//FLE_D\n"); - -// ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -partInit.code() += "etiss_uint64 res = 0U;\n"; -partInit.code() += "res = fcmp_d(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "], ((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "], 1U);\n"; -if ((rd % 32U) != 0U) { -partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = res;\n"; -} -partInit.code() += "etiss_uint32 flags = fget_flags();\n"; -partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32U) | (flags & 31U);\n"; -// ----------------------------------------------------------------------------- - - partInit.getAffectedRegisters().add(reg_name[rd % 32], 32); - partInit.getAffectedRegisters().add("instructionPointer", 32); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//FLE_D\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint64 res = 0ULL;\n"; +cp.code() += "res = fcmp_d(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL], ((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL], 1ULL);\n"; +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res;\n"; +} // conditional +cp.code() += "etiss_uint32 flags = fget_flags();\n"; +cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -1463,13 +1723,13 @@ partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32U) [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; @@ -1497,26 +1757,36 @@ static InstructionDefinition fclass_d_rd_rs1 ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); - partInit.code() = std::string("//FCLASS_D\n"); + cp.code() = std::string("//FCLASS_D\n"); // ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = fclass_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]));\n"; +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = fclass_d((etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]));\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; // ----------------------------------------------------------------------------- - - partInit.getAffectedRegisters().add(reg_name[rd % 32], 32); - partInit.getAffectedRegisters().add("instructionPointer", 32); + cp.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -1524,10 +1794,10 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = fc [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; @@ -1555,35 +1825,45 @@ static InstructionDefinition fcvt_w_d_rd_rm_rs1 ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rm = 0; +etiss_uint8 rm = 0; static BitArrayRange R_rm_0(14, 12); rm += R_rm_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); - - partInit.code() = std::string("//FCVT_W_D\n"); - -// ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -partInit.code() += "etiss_int64 res = 0U;\n"; -partInit.code() += "res = fcvt_64_32(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "], 0U, " + std::to_string(rm) + ");\n"; -if ((rd % 32U) != 0U) { -partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = res;\n"; -} -partInit.code() += "etiss_uint32 flags = fget_flags();\n"; -partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32U) | (flags & 31U);\n"; -// ----------------------------------------------------------------------------- - - partInit.getAffectedRegisters().add(reg_name[rd % 32], 32); - partInit.getAffectedRegisters().add("instructionPointer", 32); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//FCVT_W_D\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_int32 res = 0ULL;\n"; +cp.code() += "res = fcvt_64_32(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL], 0ULL, " + std::to_string(rm) + "ULL);\n"; +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res;\n"; +} // conditional +cp.code() += "etiss_uint32 flags = fget_flags();\n"; +cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -1591,13 +1871,13 @@ partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32U) [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rm = 0; +etiss_uint8 rm = 0; static BitArrayRange R_rm_0(14, 12); rm += R_rm_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; @@ -1625,35 +1905,45 @@ static InstructionDefinition fcvt_wu_d_rd_rm_rs1 ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rm = 0; +etiss_uint8 rm = 0; static BitArrayRange R_rm_0(14, 12); rm += R_rm_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); - - partInit.code() = std::string("//FCVT_WU_D\n"); - -// ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -partInit.code() += "etiss_uint64 res = 0U;\n"; -partInit.code() += "res = fcvt_64_32(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "], 0U, " + std::to_string(rm) + ");\n"; -if ((rd % 32U) != 0U) { -partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = res;\n"; -} -partInit.code() += "etiss_uint32 flags = fget_flags();\n"; -partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32U) | (flags & 31U);\n"; -// ----------------------------------------------------------------------------- - - partInit.getAffectedRegisters().add(reg_name[rd % 32], 32); - partInit.getAffectedRegisters().add("instructionPointer", 32); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//FCVT_WU_D\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint32 res = 0ULL;\n"; +cp.code() += "res = fcvt_64_32(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL], 1ULL, " + std::to_string(rm) + "ULL);\n"; +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint64)((etiss_int32)(res));\n"; +} // conditional +cp.code() += "etiss_uint32 flags = fget_flags();\n"; +cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -1661,13 +1951,13 @@ partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32U) [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rm = 0; +etiss_uint8 rm = 0; static BitArrayRange R_rm_0(14, 12); rm += R_rm_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; @@ -1695,30 +1985,40 @@ static InstructionDefinition fcvt_d_w_rd_rm_rs1 ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rm = 0; +etiss_uint8 rm = 0; static BitArrayRange R_rm_0(14, 12); rm += R_rm_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); - - partInit.code() = std::string("//FCVT_D_W\n"); - -// ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -partInit.code() += "etiss_int64 res = fcvt_32_64((etiss_uint32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]), 2U, " + std::to_string(rm) + ");\n"; -partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n"; -// ----------------------------------------------------------------------------- - - partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32); - partInit.getAffectedRegisters().add("instructionPointer", 32); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//FCVT_D_W\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_int64 res = fcvt_32_64((etiss_uint32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]), 2ULL, " + std::to_string(rm) + "ULL);\n"; +cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -1726,13 +2026,13 @@ partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n"; [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rm = 0; +etiss_uint8 rm = 0; static BitArrayRange R_rm_0(14, 12); rm += R_rm_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; @@ -1760,30 +2060,40 @@ static InstructionDefinition fcvt_d_wu_rd_rm_rs1 ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rm = 0; +etiss_uint8 rm = 0; static BitArrayRange R_rm_0(14, 12); rm += R_rm_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); - - partInit.code() = std::string("//FCVT_D_WU\n"); - -// ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -partInit.code() += "etiss_uint64 res = fcvt_32_64((etiss_uint32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]), 3U, " + std::to_string(rm) + ");\n"; -partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n"; -// ----------------------------------------------------------------------------- - - partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32); - partInit.getAffectedRegisters().add("instructionPointer", 32); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//FCVT_D_WU\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint64 res = fcvt_32_64((etiss_uint32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]), 3ULL, " + std::to_string(rm) + "ULL);\n"; +cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -1791,13 +2101,13 @@ partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = res;\n"; [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rm = 0; +etiss_uint8 rm = 0; static BitArrayRange R_rm_0(14, 12); rm += R_rm_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FCInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FCInstr.cpp index 363ec9b47c..1ec5f74e3d 100644 --- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FCInstr.cpp +++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FCInstr.cpp @@ -1,13 +1,11 @@ /** - * Generated on Thu, 03 Mar 2022 21:04:49 +0100. + * Generated on Tue, 28 Nov 2023 09:45:19 +0100. * * This file contains the instruction behavior models of the RV32FC * instruction set for the RV32IMACFD core architecture. */ #include "RV32IMACFDArch.h" - -#define ETISS_ARCH_STATIC_FN_ONLY #include "RV32IMACFDFuncs.h" using namespace etiss; @@ -28,15 +26,15 @@ static InstructionDefinition cflw_rd_uimm_rs1 ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(4, 2); rd += R_rd_0.read(ba) << 0; -etiss_uint32 uimm = 0; +etiss_uint8 uimm = 0; static BitArrayRange R_uimm_6(5, 5); uimm += R_uimm_6.read(ba) << 6; static BitArrayRange R_uimm_2(6, 6); uimm += R_uimm_2.read(ba) << 2; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(9, 7); rs1 += R_rs1_0.read(ba) << 0; static BitArrayRange R_uimm_3(12, 10); @@ -44,22 +42,52 @@ uimm += R_uimm_3.read(ba) << 3; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//CFLW\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] + " + std::to_string(uimm) + "ULL;\n"; +cp.code() += "etiss_uint32 mem_val_0;\n"; +cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "etiss_uint32 res = (etiss_uint32)(mem_val_0);\n"; +{ // block +cp.code() += "{ // block\n"; +cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd + 8ULL) + "ULL] = -4294967296LL | res;\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); - partInit.code() = std::string("//CFLW\n"); + cp.code() = std::string("//CFLW\n"); // ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 2U) + ";\n"; -partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "] + " + std::to_string(uimm) + ";\n"; -partInit.code() += "etiss_uint32 mem_val_0;\n"; -partInit.code() += "exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n"; -partInit.code() += "etiss_uint32 res = (etiss_uint32)(mem_val_0);\n"; -partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd + 8U) + "] = -4294967296UL | res;\n"; -partInit.code() += "if (exception) return exception;\n"; +cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n"; // ----------------------------------------------------------------------------- - - partInit.getRegisterDependencies().add(reg_name[rs1 + 8U], 32); - partInit.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -67,15 +95,15 @@ partInit.code() += "if (exception) return exception;\n"; [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(4, 2); rd += R_rd_0.read(ba) << 0; -etiss_uint32 uimm = 0; +etiss_uint8 uimm = 0; static BitArrayRange R_uimm_6(5, 5); uimm += R_uimm_6.read(ba) << 6; static BitArrayRange R_uimm_2(6, 6); uimm += R_uimm_2.read(ba) << 2; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(9, 7); rs1 += R_rs1_0.read(ba) << 0; static BitArrayRange R_uimm_3(12, 10); @@ -105,15 +133,15 @@ static InstructionDefinition cfsw_rs2_uimm_rs1 ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(4, 2); rs2 += R_rs2_0.read(ba) << 0; -etiss_uint32 uimm = 0; +etiss_uint8 uimm = 0; static BitArrayRange R_uimm_6(5, 5); uimm += R_uimm_6.read(ba) << 6; static BitArrayRange R_uimm_2(6, 6); uimm += R_uimm_2.read(ba) << 2; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(9, 7); rs1 += R_rs1_0.read(ba) << 0; static BitArrayRange R_uimm_3(12, 10); @@ -121,21 +149,47 @@ uimm += R_uimm_3.read(ba) << 3; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//CFSW\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] + " + std::to_string(uimm) + "ULL;\n"; +cp.code() += "etiss_uint32 mem_val_0;\n"; +cp.code() += "mem_val_0 = (etiss_uint32)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2 + 8ULL) + "ULL]);\n"; +cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); - partInit.code() = std::string("//CFSW\n"); + cp.code() = std::string("//CFSW\n"); // ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 2U) + ";\n"; -partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "] + " + std::to_string(uimm) + ";\n"; -partInit.code() += "etiss_uint32 mem_val_0 = (etiss_uint32)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2 + 8U) + "]);\n"; -partInit.code() += "exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n"; - -partInit.code() += "if (exception) return exception;\n"; +cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n"; // ----------------------------------------------------------------------------- - - partInit.getRegisterDependencies().add(reg_name[rs1 + 8U], 32); - partInit.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -143,15 +197,15 @@ partInit.code() += "if (exception) return exception;\n"; [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(4, 2); rs2 += R_rs2_0.read(ba) << 0; -etiss_uint32 uimm = 0; +etiss_uint8 uimm = 0; static BitArrayRange R_uimm_6(5, 5); uimm += R_uimm_6.read(ba) << 6; static BitArrayRange R_uimm_2(6, 6); uimm += R_uimm_2.read(ba) << 2; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(9, 7); rs1 += R_rs1_0.read(ba) << 0; static BitArrayRange R_uimm_3(12, 10); @@ -181,12 +235,12 @@ static InstructionDefinition cflwsp_uimm_rd ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 uimm = 0; +etiss_uint8 uimm = 0; static BitArrayRange R_uimm_6(3, 2); uimm += R_uimm_6.read(ba) << 6; static BitArrayRange R_uimm_2(6, 4); uimm += R_uimm_2.read(ba) << 2; -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; static BitArrayRange R_uimm_5(12, 12); @@ -194,22 +248,52 @@ uimm += R_uimm_5.read(ba) << 5; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//CFLWSP\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[2ULL] + " + std::to_string(uimm) + "ULL;\n"; +cp.code() += "etiss_uint32 mem_val_0;\n"; +cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "etiss_uint32 res = (etiss_uint32)(mem_val_0);\n"; +{ // block +cp.code() += "{ // block\n"; +cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | res;\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); - partInit.code() = std::string("//CFLWSP\n"); + cp.code() = std::string("//CFLWSP\n"); // ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 2U) + ";\n"; -partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(2U) + "] + " + std::to_string(uimm) + ";\n"; -partInit.code() += "etiss_uint32 mem_val_0;\n"; -partInit.code() += "exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n"; -partInit.code() += "etiss_uint32 res = (etiss_uint32)(mem_val_0);\n"; -partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296UL | res;\n"; -partInit.code() += "if (exception) return exception;\n"; +cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n"; // ----------------------------------------------------------------------------- - - partInit.getRegisterDependencies().add(reg_name[2U], 32); - partInit.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -217,12 +301,12 @@ partInit.code() += "if (exception) return exception;\n"; [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 uimm = 0; +etiss_uint8 uimm = 0; static BitArrayRange R_uimm_6(3, 2); uimm += R_uimm_6.read(ba) << 6; static BitArrayRange R_uimm_2(6, 4); uimm += R_uimm_2.read(ba) << 2; -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; static BitArrayRange R_uimm_5(12, 12); @@ -252,10 +336,10 @@ static InstructionDefinition cfswsp_rs2_uimm ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(6, 2); rs2 += R_rs2_0.read(ba) << 0; -etiss_uint32 uimm = 0; +etiss_uint8 uimm = 0; static BitArrayRange R_uimm_6(8, 7); uimm += R_uimm_6.read(ba) << 6; static BitArrayRange R_uimm_2(12, 9); @@ -263,21 +347,47 @@ uimm += R_uimm_2.read(ba) << 2; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//CFSWSP\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[2ULL] + " + std::to_string(uimm) + "ULL;\n"; +cp.code() += "etiss_uint32 mem_val_0;\n"; +cp.code() += "mem_val_0 = (etiss_uint32)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n"; +cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); - partInit.code() = std::string("//CFSWSP\n"); + cp.code() = std::string("//CFSWSP\n"); // ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 2U) + ";\n"; -partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(2U) + "] + " + std::to_string(uimm) + ";\n"; -partInit.code() += "etiss_uint32 mem_val_0 = (etiss_uint32)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]);\n"; -partInit.code() += "exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n"; - -partInit.code() += "if (exception) return exception;\n"; +cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n"; // ----------------------------------------------------------------------------- - - partInit.getRegisterDependencies().add(reg_name[2U], 32); - partInit.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -285,10 +395,10 @@ partInit.code() += "if (exception) return exception;\n"; [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(6, 2); rs2 += R_rs2_0.read(ba) << 0; -etiss_uint32 uimm = 0; +etiss_uint8 uimm = 0; static BitArrayRange R_uimm_6(8, 7); uimm += R_uimm_6.read(ba) << 6; static BitArrayRange R_uimm_2(12, 9); diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FInstr.cpp index 419241809c..b1bce66baf 100644 --- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FInstr.cpp +++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FInstr.cpp @@ -1,13 +1,11 @@ /** - * Generated on Mon, 09 May 2022 21:04:41 +0200. + * Generated on Tue, 28 Nov 2023 09:45:19 +0100. * * This file contains the instruction behavior models of the RV32F * instruction set for the RV32IMACFD core architecture. */ #include "RV32IMACFDArch.h" - -#define ETISS_ARCH_STATIC_FN_ONLY #include "RV32IMACFDFuncs.h" using namespace etiss; @@ -28,34 +26,64 @@ static InstructionDefinition flw_rd_rs1_imm ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 imm = 0; +etiss_uint16 imm = 0; static BitArrayRange R_imm_0(31, 20); imm += R_imm_0.read(ba) << 0; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//FLW\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n"; +cp.code() += "etiss_uint32 mem_val_0;\n"; +cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "etiss_uint32 res = (etiss_uint32)(mem_val_0);\n"; +{ // block +cp.code() += "{ // block\n"; +cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); - partInit.code() = std::string("//FLW\n"); + cp.code() = std::string("//FLW\n"); // ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n"; -partInit.code() += "etiss_uint32 mem_val_0;\n"; -partInit.code() += "exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n"; -partInit.code() += "etiss_uint32 res = (etiss_uint32)(mem_val_0);\n"; -partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296UL | (etiss_uint64)(res);\n"; -partInit.code() += "if (exception) return exception;\n"; +cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n"; // ----------------------------------------------------------------------------- - - partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32); - partInit.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -63,13 +91,13 @@ partInit.code() += "if (exception) return exception;\n"; [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 imm = 0; +etiss_uint16 imm = 0; static BitArrayRange R_imm_0(31, 20); imm += R_imm_0.read(ba) << 0; @@ -97,13 +125,13 @@ static InstructionDefinition fsw_imm_rs1_rs2 ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 imm = 0; +etiss_uint16 imm = 0; static BitArrayRange R_imm_0(11, 7); imm += R_imm_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; static BitArrayRange R_imm_5(31, 25); @@ -111,21 +139,47 @@ imm += R_imm_5.read(ba) << 5; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//FSW\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n"; +cp.code() += "etiss_uint32 mem_val_0;\n"; +cp.code() += "mem_val_0 = (etiss_uint32)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n"; +cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); - partInit.code() = std::string("//FSW\n"); + cp.code() = std::string("//FSW\n"); // ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n"; -partInit.code() += "etiss_uint32 mem_val_0 = (etiss_uint32)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]);\n"; -partInit.code() += "exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n"; - -partInit.code() += "if (exception) return exception;\n"; +cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n"; // ----------------------------------------------------------------------------- - - partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32); - partInit.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -133,13 +187,13 @@ partInit.code() += "if (exception) return exception;\n"; [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 imm = 0; +etiss_uint16 imm = 0; static BitArrayRange R_imm_0(11, 7); imm += R_imm_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; static BitArrayRange R_imm_5(31, 25); @@ -169,37 +223,52 @@ static InstructionDefinition fmadd_s_rd_rm_rs1_rs2_rs3 ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rm = 0; +etiss_uint8 rm = 0; static BitArrayRange R_rm_0(14, 12); rm += R_rm_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; -etiss_uint32 rs3 = 0; +etiss_uint8 rs3 = 0; static BitArrayRange R_rs3_0(31, 27); rs3 += R_rs3_0.read(ba) << 0; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); - - partInit.code() = std::string("//FMADD_S\n"); - -// ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -partInit.code() += "etiss_uint32 res = fmadd_s(unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]), unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]), unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "]), 0U, (" + std::to_string(rm < 7U) + ") ? (" + std::to_string(rm) + ") : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n"; -partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296UL | (etiss_uint64)(res);\n"; -partInit.code() += "etiss_uint32 flags = fget_flags();\n"; -partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32U) | (flags & 31U);\n"; -// ----------------------------------------------------------------------------- - - partInit.getAffectedRegisters().add("instructionPointer", 32); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//FMADD_S\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint32 res = fmadd_s(unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 0ULL, RV32IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n"; +cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "etiss_uint32 flags = fget_flags();\n"; +cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -207,19 +276,19 @@ partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32U) [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rm = 0; +etiss_uint8 rm = 0; static BitArrayRange R_rm_0(14, 12); rm += R_rm_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; -etiss_uint32 rs3 = 0; +etiss_uint8 rs3 = 0; static BitArrayRange R_rs3_0(31, 27); rs3 += R_rs3_0.read(ba) << 0; @@ -247,37 +316,52 @@ static InstructionDefinition fmsub_s_rd_rm_rs1_rs2_rs3 ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rm = 0; +etiss_uint8 rm = 0; static BitArrayRange R_rm_0(14, 12); rm += R_rm_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; -etiss_uint32 rs3 = 0; +etiss_uint8 rs3 = 0; static BitArrayRange R_rs3_0(31, 27); rs3 += R_rs3_0.read(ba) << 0; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); - - partInit.code() = std::string("//FMSUB_S\n"); - -// ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -partInit.code() += "etiss_uint32 res = fmadd_s(unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]), unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]), unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "]), 1U, (" + std::to_string(rm < 7U) + ") ? (" + std::to_string(rm) + ") : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n"; -partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296UL | (etiss_uint64)(res);\n"; -partInit.code() += "etiss_uint32 flags = fget_flags();\n"; -partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32U) | (flags & 31U);\n"; -// ----------------------------------------------------------------------------- - - partInit.getAffectedRegisters().add("instructionPointer", 32); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//FMSUB_S\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint32 res = fmadd_s(unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 1ULL, RV32IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n"; +cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "etiss_uint32 flags = fget_flags();\n"; +cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -285,19 +369,19 @@ partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32U) [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rm = 0; +etiss_uint8 rm = 0; static BitArrayRange R_rm_0(14, 12); rm += R_rm_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; -etiss_uint32 rs3 = 0; +etiss_uint8 rs3 = 0; static BitArrayRange R_rs3_0(31, 27); rs3 += R_rs3_0.read(ba) << 0; @@ -325,40 +409,55 @@ static InstructionDefinition fnmadd_s_rd_rm_rs1_rs2_rs3 ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rm = 0; +etiss_uint8 rm = 0; static BitArrayRange R_rm_0(14, 12); rm += R_rm_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; -etiss_uint32 rs3 = 0; +etiss_uint8 rs3 = 0; static BitArrayRange R_rs3_0(31, 27); rs3 += R_rs3_0.read(ba) << 0; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); - - partInit.code() = std::string("//FNMADD_S\n"); - -// ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]);\n"; -partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]);\n"; -partInit.code() += "etiss_uint32 frs3 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "]);\n"; -partInit.code() += "etiss_uint32 res = fmadd_s(frs1, frs2, frs3, 2U, (" + std::to_string(rm < 7U) + ") ? (" + std::to_string(rm) + ") : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n"; -partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296UL | (etiss_uint64)(res);\n"; -partInit.code() += "etiss_uint32 flags = fget_flags();\n"; -partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32U) | (flags & 31U);\n"; -// ----------------------------------------------------------------------------- - - partInit.getAffectedRegisters().add("instructionPointer", 32); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//FNMADD_S\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n"; +cp.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n"; +cp.code() += "etiss_uint32 frs3 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]);\n"; +cp.code() += "etiss_uint32 res = fmadd_s(frs1, frs2, frs3, 2ULL, RV32IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n"; +cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "etiss_uint32 flags = fget_flags();\n"; +cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -366,19 +465,19 @@ partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32U) [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rm = 0; +etiss_uint8 rm = 0; static BitArrayRange R_rm_0(14, 12); rm += R_rm_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; -etiss_uint32 rs3 = 0; +etiss_uint8 rs3 = 0; static BitArrayRange R_rs3_0(31, 27); rs3 += R_rs3_0.read(ba) << 0; @@ -406,40 +505,55 @@ static InstructionDefinition fnmsub_s_rd_rm_rs1_rs2_rs3 ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rm = 0; +etiss_uint8 rm = 0; static BitArrayRange R_rm_0(14, 12); rm += R_rm_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; -etiss_uint32 rs3 = 0; +etiss_uint8 rs3 = 0; static BitArrayRange R_rs3_0(31, 27); rs3 += R_rs3_0.read(ba) << 0; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); - - partInit.code() = std::string("//FNMSUB_S\n"); - -// ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]);\n"; -partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]);\n"; -partInit.code() += "etiss_uint32 frs3 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "]);\n"; -partInit.code() += "etiss_uint32 res = fmadd_s(frs1, frs2, frs3, 3U, (" + std::to_string(rm < 7U) + ") ? (" + std::to_string(rm) + ") : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n"; -partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296UL | (etiss_uint64)(res);\n"; -partInit.code() += "etiss_uint32 flags = fget_flags();\n"; -partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32U) | (flags & 31U);\n"; -// ----------------------------------------------------------------------------- - - partInit.getAffectedRegisters().add("instructionPointer", 32); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//FNMSUB_S\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n"; +cp.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n"; +cp.code() += "etiss_uint32 frs3 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]);\n"; +cp.code() += "etiss_uint32 res = fmadd_s(frs1, frs2, frs3, 3ULL, RV32IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n"; +cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "etiss_uint32 flags = fget_flags();\n"; +cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -447,19 +561,19 @@ partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32U) [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rm = 0; +etiss_uint8 rm = 0; static BitArrayRange R_rm_0(14, 12); rm += R_rm_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; -etiss_uint32 rs3 = 0; +etiss_uint8 rs3 = 0; static BitArrayRange R_rs3_0(31, 27); rs3 += R_rs3_0.read(ba) << 0; @@ -487,36 +601,51 @@ static InstructionDefinition fadd_s_rd_rm_rs1_rs2 ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rm = 0; +etiss_uint8 rm = 0; static BitArrayRange R_rm_0(14, 12); rm += R_rm_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); - - partInit.code() = std::string("//FADD_S\n"); - -// ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]);\n"; -partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]);\n"; -partInit.code() += "etiss_uint32 res = fadd_s(frs1, frs2, (" + std::to_string(rm < 7U) + ") ? (" + std::to_string(rm) + ") : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n"; -partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296UL | (etiss_uint64)(res);\n"; -partInit.code() += "etiss_uint32 flags = fget_flags();\n"; -partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32U) | (flags & 31U);\n"; -// ----------------------------------------------------------------------------- - - partInit.getAffectedRegisters().add("instructionPointer", 32); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//FADD_S\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n"; +cp.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n"; +cp.code() += "etiss_uint32 res = fadd_s(frs1, frs2, RV32IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n"; +cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "etiss_uint32 flags = fget_flags();\n"; +cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -524,16 +653,16 @@ partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32U) [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rm = 0; +etiss_uint8 rm = 0; static BitArrayRange R_rm_0(14, 12); rm += R_rm_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; @@ -561,36 +690,51 @@ static InstructionDefinition fsub_s_rd_rm_rs1_rs2 ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rm = 0; +etiss_uint8 rm = 0; static BitArrayRange R_rm_0(14, 12); rm += R_rm_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); - - partInit.code() = std::string("//FSUB_S\n"); - -// ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]);\n"; -partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]);\n"; -partInit.code() += "etiss_uint32 res = fsub_s(frs1, frs2, (" + std::to_string(rm < 7U) + ") ? (" + std::to_string(rm) + ") : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n"; -partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296UL | (etiss_uint64)(res);\n"; -partInit.code() += "etiss_uint32 flags = fget_flags();\n"; -partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32U) | (flags & 31U);\n"; -// ----------------------------------------------------------------------------- - - partInit.getAffectedRegisters().add("instructionPointer", 32); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//FSUB_S\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n"; +cp.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n"; +cp.code() += "etiss_uint32 res = fsub_s(frs1, frs2, RV32IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n"; +cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "etiss_uint32 flags = fget_flags();\n"; +cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -598,16 +742,16 @@ partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32U) [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rm = 0; +etiss_uint8 rm = 0; static BitArrayRange R_rm_0(14, 12); rm += R_rm_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; @@ -635,36 +779,51 @@ static InstructionDefinition fmul_s_rd_rm_rs1_rs2 ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rm = 0; +etiss_uint8 rm = 0; static BitArrayRange R_rm_0(14, 12); rm += R_rm_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); - - partInit.code() = std::string("//FMUL_S\n"); - -// ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]);\n"; -partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]);\n"; -partInit.code() += "etiss_uint32 res = fmul_s(frs1, frs2, (" + std::to_string(rm < 7U) + ") ? (" + std::to_string(rm) + ") : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n"; -partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296UL | (etiss_uint64)(res);\n"; -partInit.code() += "etiss_uint32 flags = fget_flags();\n"; -partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32U) | (flags & 31U);\n"; -// ----------------------------------------------------------------------------- - - partInit.getAffectedRegisters().add("instructionPointer", 32); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//FMUL_S\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n"; +cp.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n"; +cp.code() += "etiss_uint32 res = fmul_s(frs1, frs2, RV32IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n"; +cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "etiss_uint32 flags = fget_flags();\n"; +cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -672,16 +831,16 @@ partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32U) [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rm = 0; +etiss_uint8 rm = 0; static BitArrayRange R_rm_0(14, 12); rm += R_rm_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; @@ -709,36 +868,51 @@ static InstructionDefinition fdiv_s_rd_rm_rs1_rs2 ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rm = 0; +etiss_uint8 rm = 0; static BitArrayRange R_rm_0(14, 12); rm += R_rm_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); - - partInit.code() = std::string("//FDIV_S\n"); - -// ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]);\n"; -partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]);\n"; -partInit.code() += "etiss_uint32 res = fdiv_s(frs1, frs2, (" + std::to_string(rm < 7U) + ") ? (" + std::to_string(rm) + ") : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n"; -partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296UL | (etiss_uint64)(res);\n"; -partInit.code() += "etiss_uint32 flags = fget_flags();\n"; -partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32U) | (flags & 31U);\n"; -// ----------------------------------------------------------------------------- - - partInit.getAffectedRegisters().add("instructionPointer", 32); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//FDIV_S\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n"; +cp.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n"; +cp.code() += "etiss_uint32 res = fdiv_s(frs1, frs2, RV32IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n"; +cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "etiss_uint32 flags = fget_flags();\n"; +cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -746,16 +920,16 @@ partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32U) [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rm = 0; +etiss_uint8 rm = 0; static BitArrayRange R_rm_0(14, 12); rm += R_rm_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; @@ -783,32 +957,47 @@ static InstructionDefinition fsqrt_s_rd_rm_rs1 ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rm = 0; +etiss_uint8 rm = 0; static BitArrayRange R_rm_0(14, 12); rm += R_rm_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); - - partInit.code() = std::string("//FSQRT_S\n"); - -// ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]);\n"; -partInit.code() += "etiss_uint32 res = fsqrt_s(frs1, (" + std::to_string(rm < 7U) + ") ? (" + std::to_string(rm) + ") : ((etiss_uint8)(((RV32IMACFD*)cpu)->FCSR)));\n"; -partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296UL | (etiss_uint64)(res);\n"; -partInit.code() += "etiss_uint32 flags = fget_flags();\n"; -partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32U) | (flags & 31U);\n"; -// ----------------------------------------------------------------------------- - - partInit.getAffectedRegisters().add("instructionPointer", 32); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//FSQRT_S\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n"; +cp.code() += "etiss_uint32 res = fsqrt_s(frs1, RV32IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n"; +cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "etiss_uint32 flags = fget_flags();\n"; +cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -816,13 +1005,13 @@ partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32U) [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rm = 0; +etiss_uint8 rm = 0; static BitArrayRange R_rm_0(14, 12); rm += R_rm_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; @@ -850,31 +1039,46 @@ static InstructionDefinition fsgnj_s_rd_rs1_rs2 ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); - - partInit.code() = std::string("//FSGNJ_S\n"); - -// ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]);\n"; -partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]);\n"; -partInit.code() += "etiss_uint32 res = ((((((frs2) >> (31U)) & 1)) << 31) | ((((frs1) >> (0U)) & 2147483647)));\n"; -partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296UL | (etiss_uint64)(res);\n"; -// ----------------------------------------------------------------------------- - - partInit.getAffectedRegisters().add("instructionPointer", 32); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//FSGNJ_S\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n"; +cp.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n"; +cp.code() += "etiss_uint32 res = ((((((frs2) >> (31ULL)) & 1)) << 31) | ((((frs1) >> (0ULL)) & 2147483647)));\n"; +cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -882,13 +1086,13 @@ partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967 [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; @@ -916,31 +1120,46 @@ static InstructionDefinition fsgnjn_s_rd_rs1_rs2 ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); - - partInit.code() = std::string("//FSGNJN_S\n"); - -// ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]);\n"; -partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]);\n"; -partInit.code() += "etiss_uint32 res = (((~((((frs2) >> (31U)) & 1))) << 31) | ((((frs1) >> (0U)) & 2147483647)));\n"; -partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296UL | (etiss_uint64)(res);\n"; -// ----------------------------------------------------------------------------- - - partInit.getAffectedRegisters().add("instructionPointer", 32); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//FSGNJN_S\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n"; +cp.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n"; +cp.code() += "etiss_uint32 res = (((~((((frs2) >> (31ULL)) & 1))) << 31) | ((((frs1) >> (0ULL)) & 2147483647)));\n"; +cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -948,13 +1167,13 @@ partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967 [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; @@ -982,31 +1201,46 @@ static InstructionDefinition fsgnjx_s_rd_rs1_rs2 ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); - - partInit.code() = std::string("//FSGNJX_S\n"); - -// ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]);\n"; -partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]);\n"; -partInit.code() += "etiss_uint32 res = frs1 ^ (frs2 & 2147483648U);\n"; -partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296UL | (etiss_uint64)(res);\n"; -// ----------------------------------------------------------------------------- - - partInit.getAffectedRegisters().add("instructionPointer", 32); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//FSGNJX_S\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n"; +cp.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n"; +cp.code() += "etiss_uint32 res = frs1 ^ (frs2 & 2147483648ULL);\n"; +cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -1014,13 +1248,13 @@ partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967 [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; @@ -1048,33 +1282,48 @@ static InstructionDefinition fmin_s_rd_rs1_rs2 ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); - - partInit.code() = std::string("//FMIN_S\n"); - -// ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]);\n"; -partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]);\n"; -partInit.code() += "etiss_uint32 res = fsel_s(frs1, frs2, 0U);\n"; -partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296UL | (etiss_uint64)(res);\n"; -partInit.code() += "etiss_uint32 flags = fget_flags();\n"; -partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32U) | (flags & 31U);\n"; -// ----------------------------------------------------------------------------- - - partInit.getAffectedRegisters().add("instructionPointer", 32); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//FMIN_S\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n"; +cp.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n"; +cp.code() += "etiss_uint32 res = fsel_s(frs1, frs2, 0ULL);\n"; +cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "etiss_uint32 flags = fget_flags();\n"; +cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -1082,13 +1331,13 @@ partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32U) [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; @@ -1116,33 +1365,48 @@ static InstructionDefinition fmax_s_rd_rs1_rs2 ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); - - partInit.code() = std::string("//FMAX_S\n"); - -// ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]);\n"; -partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]);\n"; -partInit.code() += "etiss_uint32 res = fsel_s(frs1, frs2, 1U);\n"; -partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296UL | (etiss_uint64)(res);\n"; -partInit.code() += "etiss_uint32 flags = fget_flags();\n"; -partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32U) | (flags & 31U);\n"; -// ----------------------------------------------------------------------------- - - partInit.getAffectedRegisters().add("instructionPointer", 32); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//FMAX_S\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n"; +cp.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n"; +cp.code() += "etiss_uint32 res = fsel_s(frs1, frs2, 1ULL);\n"; +cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "etiss_uint32 flags = fget_flags();\n"; +cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -1150,13 +1414,13 @@ partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32U) [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; @@ -1184,36 +1448,50 @@ static InstructionDefinition fcvt_w_s_rd_rm_rs1 ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rm = 0; +etiss_uint8 rm = 0; static BitArrayRange R_rm_0(14, 12); rm += R_rm_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); - - partInit.code() = std::string("//FCVT_W_S\n"); - -// ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -partInit.code() += "etiss_int32 res = 0U;\n"; -partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]);\n"; -partInit.code() += "res = fcvt_s(frs1, 0U, " + std::to_string(rm) + ");\n"; -if ((rd % 32U) != 0U) { -partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = res;\n"; -} -partInit.code() += "etiss_uint32 flags = fget_flags();\n"; -partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32U) | (flags & 31U);\n"; -// ----------------------------------------------------------------------------- - - partInit.getAffectedRegisters().add(reg_name[rd % 32], 32); - partInit.getAffectedRegisters().add("instructionPointer", 32); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//FCVT_W_S\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_int32 res = 0ULL;\n"; +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n"; +cp.code() += "res = fcvt_s(frs1, 0ULL, " + std::to_string(rm) + "ULL);\n"; +cp.code() += "} // block\n"; +} // block +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res;\n"; +} // conditional +cp.code() += "etiss_uint32 flags = fget_flags();\n"; +cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -1221,13 +1499,13 @@ partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32U) [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rm = 0; +etiss_uint8 rm = 0; static BitArrayRange R_rm_0(14, 12); rm += R_rm_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; @@ -1255,36 +1533,50 @@ static InstructionDefinition fcvt_wu_s_rd_rm_rs1 ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rm = 0; +etiss_uint8 rm = 0; static BitArrayRange R_rm_0(14, 12); rm += R_rm_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); - - partInit.code() = std::string("//FCVT_WU_S\n"); - -// ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -partInit.code() += "etiss_uint32 res = 0U;\n"; -partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]);\n"; -partInit.code() += "res = fcvt_s(frs1, 1U, " + std::to_string(rm) + ");\n"; -if ((rd % 32U) != 0U) { -partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = res;\n"; -} -partInit.code() += "etiss_uint32 flags = fget_flags();\n"; -partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32U) | (flags & 31U);\n"; -// ----------------------------------------------------------------------------- - - partInit.getAffectedRegisters().add(reg_name[rd % 32], 32); - partInit.getAffectedRegisters().add("instructionPointer", 32); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//FCVT_WU_S\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint32 res = 0ULL;\n"; +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n"; +cp.code() += "res = fcvt_s(frs1, 1ULL, " + std::to_string(rm) + "ULL);\n"; +cp.code() += "} // block\n"; +} // block +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint32)((etiss_int32)(res));\n"; +} // conditional +cp.code() += "etiss_uint32 flags = fget_flags();\n"; +cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -1292,13 +1584,13 @@ partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32U) [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rm = 0; +etiss_uint8 rm = 0; static BitArrayRange R_rm_0(14, 12); rm += R_rm_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; @@ -1326,37 +1618,51 @@ static InstructionDefinition feq_s_rd_rs1_rs2 ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); - - partInit.code() = std::string("//FEQ_S\n"); - -// ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -partInit.code() += "etiss_uint32 res = 0U;\n"; -partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]);\n"; -partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]);\n"; -partInit.code() += "res = fcmp_s(frs1, frs2, 0U);\n"; -if ((rd % 32U) != 0U) { -partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = res;\n"; -} -partInit.code() += "etiss_uint32 flags = fget_flags();\n"; -partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32U) | (flags & 31U);\n"; -// ----------------------------------------------------------------------------- - - partInit.getAffectedRegisters().add(reg_name[rd % 32], 32); - partInit.getAffectedRegisters().add("instructionPointer", 32); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//FEQ_S\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint32 res = 0ULL;\n"; +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n"; +cp.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n"; +cp.code() += "res = fcmp_s(frs1, frs2, 0ULL);\n"; +cp.code() += "} // block\n"; +} // block +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res;\n"; +} // conditional +cp.code() += "etiss_uint32 flags = fget_flags();\n"; +cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -1364,13 +1670,13 @@ partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32U) [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; @@ -1398,37 +1704,51 @@ static InstructionDefinition flt_s_rd_rs1_rs2 ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); - - partInit.code() = std::string("//FLT_S\n"); - -// ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -partInit.code() += "etiss_uint32 res = 0U;\n"; -partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]);\n"; -partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]);\n"; -partInit.code() += "res = fcmp_s(frs1, frs2, 2U);\n"; -if ((rd % 32U) != 0U) { -partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = res;\n"; -} -partInit.code() += "etiss_uint32 flags = fget_flags();\n"; -partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32U) | (flags & 31U);\n"; -// ----------------------------------------------------------------------------- - - partInit.getAffectedRegisters().add(reg_name[rd % 32], 32); - partInit.getAffectedRegisters().add("instructionPointer", 32); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//FLT_S\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint32 res = 0ULL;\n"; +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n"; +cp.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n"; +cp.code() += "res = fcmp_s(frs1, frs2, 2ULL);\n"; +cp.code() += "} // block\n"; +} // block +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res;\n"; +} // conditional +cp.code() += "etiss_uint32 flags = fget_flags();\n"; +cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -1436,13 +1756,13 @@ partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32U) [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; @@ -1470,37 +1790,51 @@ static InstructionDefinition fle_s_rd_rs1_rs2 ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); - - partInit.code() = std::string("//FLE_S\n"); - -// ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -partInit.code() += "etiss_uint32 res = 0U;\n"; -partInit.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]);\n"; -partInit.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "]);\n"; -partInit.code() += "res = fcmp_s(frs1, frs2, 1U);\n"; -if ((rd % 32U) != 0U) { -partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = res;\n"; -} -partInit.code() += "etiss_uint32 flags = fget_flags();\n"; -partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32U) | (flags & 31U);\n"; -// ----------------------------------------------------------------------------- - - partInit.getAffectedRegisters().add(reg_name[rd % 32], 32); - partInit.getAffectedRegisters().add("instructionPointer", 32); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//FLE_S\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint32 res = 0ULL;\n"; +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n"; +cp.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n"; +cp.code() += "res = fcmp_s(frs1, frs2, 1ULL);\n"; +cp.code() += "} // block\n"; +} // block +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res;\n"; +} // conditional +cp.code() += "etiss_uint32 flags = fget_flags();\n"; +cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -1508,13 +1842,13 @@ partInit.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32U) [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; @@ -1542,30 +1876,40 @@ static InstructionDefinition fclass_s_rd_rs1 ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); - - partInit.code() = std::string("//FCLASS_S\n"); - -// ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -partInit.code() += "etiss_uint32 res = 0U;\n"; -partInit.code() += "res = fclass_s(unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "]));\n"; -if ((rd % 32U) != 0U) { -partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = res;\n"; -} -// ----------------------------------------------------------------------------- - - partInit.getAffectedRegisters().add(reg_name[rd % 32], 32); - partInit.getAffectedRegisters().add("instructionPointer", 32); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//FCLASS_S\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint32 res = 0ULL;\n"; +cp.code() += "res = fclass_s(unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]));\n"; +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res;\n"; +} // conditional +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -1573,10 +1917,10 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = re [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; @@ -1604,30 +1948,44 @@ static InstructionDefinition fcvt_s_w_rd_rm_rs1 ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rm = 0; +etiss_uint8 rm = 0; static BitArrayRange R_rm_0(14, 12); rm += R_rm_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); - - partInit.code() = std::string("//FCVT_S_W\n"); - -// ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -partInit.code() += "etiss_uint32 res = fcvt_s((etiss_uint32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]), 2U, " + std::to_string(rm) + ");\n"; -partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296UL | (etiss_uint64)(res);\n"; -// ----------------------------------------------------------------------------- - - partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32); - partInit.getAffectedRegisters().add("instructionPointer", 32); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//FCVT_S_W\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint32 res = fcvt_s((etiss_uint32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]), 2ULL, " + std::to_string(rm) + "ULL);\n"; +cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -1635,13 +1993,13 @@ partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967 [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rm = 0; +etiss_uint8 rm = 0; static BitArrayRange R_rm_0(14, 12); rm += R_rm_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; @@ -1669,30 +2027,44 @@ static InstructionDefinition fcvt_s_wu_rd_rm_rs1 ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rm = 0; +etiss_uint8 rm = 0; static BitArrayRange R_rm_0(14, 12); rm += R_rm_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); - - partInit.code() = std::string("//FCVT_S_WU\n"); - -// ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -partInit.code() += "etiss_uint32 res = fcvt_s((etiss_uint32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]), 3U, " + std::to_string(rm) + ");\n"; -partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296UL | (etiss_uint64)(res);\n"; -// ----------------------------------------------------------------------------- - - partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32); - partInit.getAffectedRegisters().add("instructionPointer", 32); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//FCVT_S_WU\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint32 res = fcvt_s((etiss_uint32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]), 3ULL, " + std::to_string(rm) + "ULL);\n"; +cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -1700,13 +2072,13 @@ partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967 [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rm = 0; +etiss_uint8 rm = 0; static BitArrayRange R_rm_0(14, 12); rm += R_rm_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; @@ -1734,28 +2106,38 @@ static InstructionDefinition fmv_x_w_rd_rs1 ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); - - partInit.code() = std::string("//FMV_X_W\n"); - -// ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -if ((rd % 32U) != 0U) { -partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = ((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "];\n"; -} -// ----------------------------------------------------------------------------- - - partInit.getAffectedRegisters().add(reg_name[rd % 32], 32); - partInit.getAffectedRegisters().add("instructionPointer", 32); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//FMV_X_W\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint32)((etiss_int32)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]));\n"; +} // conditional +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -1763,10 +2145,10 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (( [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; @@ -1794,26 +2176,40 @@ static InstructionDefinition fmv_w_x_rd_rs1 ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); - - partInit.code() = std::string("//FMV_W_X\n"); - -// ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967296UL | (etiss_uint64)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]);\n"; -// ----------------------------------------------------------------------------- - - partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32); - partInit.getAffectedRegisters().add("instructionPointer", 32); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//FMV_W_X\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +{ // block +cp.code() += "{ // block\n"; +cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]);\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -1821,10 +2217,10 @@ partInit.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "] = -4294967 [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32ICInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32ICInstr.cpp index b9f4c33c8f..a3cad942da 100644 --- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32ICInstr.cpp +++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32ICInstr.cpp @@ -1,13 +1,11 @@ /** - * Generated on Mon, 09 May 2022 22:10:34 +0200. + * Generated on Tue, 28 Nov 2023 09:45:19 +0100. * * This file contains the instruction behavior models of the RV32IC * instruction set for the RV32IMACFD core architecture. */ #include "RV32IMACFDArch.h" - -#define ETISS_ARCH_STATIC_FN_ONLY #include "RV32IMACFDFuncs.h" using namespace etiss; @@ -28,10 +26,10 @@ static InstructionDefinition caddi4spn_rd_imm ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(4, 2); rd += R_rd_0.read(ba) << 0; -etiss_uint32 imm = 0; +etiss_uint16 imm = 0; static BitArrayRange R_imm_3(5, 5); imm += R_imm_3.read(ba) << 3; static BitArrayRange R_imm_2(6, 6); @@ -43,23 +41,42 @@ imm += R_imm_4.read(ba) << 4; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//CADDI4SPN\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +if (imm) { // conditional +cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[2ULL] + " + std::to_string(imm) + "ULL;\n"; +} // conditional +else { // conditional +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV32IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 2ULL);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +} // conditional +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); - partInit.code() = std::string("//CADDI4SPN\n"); + cp.code() = std::string("//CADDI4SPN\n"); // ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 2U) + ";\n"; -if (imm) { -partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(2U) + "] + " + std::to_string(imm) + ";\n"; -} else { -partInit.code() += "exception = ETISS_RETURNCODE_ILLEGALINSTRUCTION;\n"; -} -partInit.code() += "if (exception) return exception;\n"; +cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n"; // ----------------------------------------------------------------------------- - - partInit.getRegisterDependencies().add(reg_name[2U], 32); - partInit.getAffectedRegisters().add(reg_name[rd + 8U], 32); - partInit.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -67,10 +84,10 @@ partInit.code() += "if (exception) return exception;\n"; [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(4, 2); rd += R_rd_0.read(ba) << 0; -etiss_uint32 imm = 0; +etiss_uint16 imm = 0; static BitArrayRange R_imm_3(5, 5); imm += R_imm_3.read(ba) << 3; static BitArrayRange R_imm_2(6, 6); @@ -104,15 +121,15 @@ static InstructionDefinition clw_rd_uimm_rs1 ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(4, 2); rd += R_rd_0.read(ba) << 0; -etiss_uint32 uimm = 0; +etiss_uint8 uimm = 0; static BitArrayRange R_uimm_6(5, 5); uimm += R_uimm_6.read(ba) << 6; static BitArrayRange R_uimm_2(6, 6); uimm += R_uimm_2.read(ba) << 2; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(9, 7); rs1 += R_rs1_0.read(ba) << 0; static BitArrayRange R_uimm_3(12, 10); @@ -120,22 +137,47 @@ uimm += R_uimm_3.read(ba) << 3; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//CLW\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint32 load_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] + " + std::to_string(uimm) + "ULL;\n"; +cp.code() += "etiss_uint32 mem_val_0;\n"; +cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 4);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) + "ULL] = (etiss_int32)(mem_val_0);\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); - partInit.code() = std::string("//CLW\n"); + cp.code() = std::string("//CLW\n"); // ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 2U) + ";\n"; -partInit.code() += "etiss_uint32 load_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "] + " + std::to_string(uimm) + ";\n"; -partInit.code() += "etiss_uint32 mem_val_0;\n"; -partInit.code() += "exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 4);\n"; -partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "] = (etiss_int32)(mem_val_0);\n"; -partInit.code() += "if (exception) return exception;\n"; +cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n"; // ----------------------------------------------------------------------------- - - partInit.getRegisterDependencies().add(reg_name[rs1 + 8U], 32); - partInit.getAffectedRegisters().add(reg_name[rd + 8U], 32); - partInit.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -143,15 +185,15 @@ partInit.code() += "if (exception) return exception;\n"; [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(4, 2); rd += R_rd_0.read(ba) << 0; -etiss_uint32 uimm = 0; +etiss_uint8 uimm = 0; static BitArrayRange R_uimm_6(5, 5); uimm += R_uimm_6.read(ba) << 6; static BitArrayRange R_uimm_2(6, 6); uimm += R_uimm_2.read(ba) << 2; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(9, 7); rs1 += R_rs1_0.read(ba) << 0; static BitArrayRange R_uimm_3(12, 10); @@ -181,15 +223,15 @@ static InstructionDefinition csw_rs2_uimm_rs1 ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(4, 2); rs2 += R_rs2_0.read(ba) << 0; -etiss_uint32 uimm = 0; +etiss_uint8 uimm = 0; static BitArrayRange R_uimm_6(5, 5); uimm += R_uimm_6.read(ba) << 6; static BitArrayRange R_uimm_2(6, 6); uimm += R_uimm_2.read(ba) << 2; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(9, 7); rs1 += R_rs1_0.read(ba) << 0; static BitArrayRange R_uimm_3(12, 10); @@ -197,22 +239,47 @@ uimm += R_uimm_3.read(ba) << 3; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//CSW\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint32 load_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] + " + std::to_string(uimm) + "ULL;\n"; +cp.code() += "etiss_uint32 mem_val_0;\n"; +cp.code() += "mem_val_0 = (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 + 8ULL) + "ULL]);\n"; +cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 4);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); - partInit.code() = std::string("//CSW\n"); + cp.code() = std::string("//CSW\n"); // ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 2U) + ";\n"; -partInit.code() += "etiss_uint32 load_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "] + " + std::to_string(uimm) + ";\n"; -partInit.code() += "etiss_uint32 mem_val_0 = (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 + 8U) + "]);\n"; -partInit.code() += "exception |= (*(system->dwrite))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 4);\n"; - -partInit.code() += "if (exception) return exception;\n"; +cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n"; // ----------------------------------------------------------------------------- - - partInit.getRegisterDependencies().add(reg_name[rs1 + 8U], 32); - partInit.getRegisterDependencies().add(reg_name[rs2 + 8U], 32); - partInit.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -220,15 +287,15 @@ partInit.code() += "if (exception) return exception;\n"; [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(4, 2); rs2 += R_rs2_0.read(ba) << 0; -etiss_uint32 uimm = 0; +etiss_uint8 uimm = 0; static BitArrayRange R_uimm_6(5, 5); uimm += R_uimm_6.read(ba) << 6; static BitArrayRange R_uimm_2(6, 6); uimm += R_uimm_2.read(ba) << 2; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(9, 7); rs1 += R_rs1_0.read(ba) << 0; static BitArrayRange R_uimm_3(12, 10); @@ -258,10 +325,10 @@ static InstructionDefinition caddi_imm_rs1 ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 imm = 0; +etiss_uint8 imm = 0; static BitArrayRange R_imm_0(6, 2); imm += R_imm_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(11, 7); rs1 += R_rs1_0.read(ba) << 0; static BitArrayRange R_imm_5(12, 12); @@ -269,20 +336,25 @@ imm += R_imm_5.read(ba) << 5; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); - partInit.code() = std::string("//CADDI\n"); + cp.code() = std::string("//CADDI\n"); // ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 2U) + ";\n"; -if ((rs1 % 32U) != 0U) { -partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int8)((imm) << (2)) >> (2))) + ";\n"; -} +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +if ((rs1 % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int8)(((etiss_int8)imm) << (2)) >> (2))) + "LL;\n"; +} // conditional +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; // ----------------------------------------------------------------------------- - - partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32); - partInit.getAffectedRegisters().add(reg_name[rs1 % 32], 32); - partInit.getAffectedRegisters().add("instructionPointer", 32); + cp.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -290,10 +362,10 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32) + "] = * [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 imm = 0; +etiss_uint8 imm = 0; static BitArrayRange R_imm_0(6, 2); imm += R_imm_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(11, 7); rs1 += R_rs1_0.read(ba) << 0; static BitArrayRange R_imm_5(12, 12); @@ -323,7 +395,7 @@ static InstructionDefinition cnop_nzimm ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 nzimm = 0; +etiss_uint8 nzimm = 0; static BitArrayRange R_nzimm_0(6, 2); nzimm += R_nzimm_0.read(ba) << 0; static BitArrayRange R_nzimm_5(12, 12); @@ -331,15 +403,26 @@ nzimm += R_nzimm_5.read(ba) << 5; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); - partInit.code() = std::string("//CNOP\n"); + cp.code() = std::string("//CNOP\n"); // ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 2U) + ";\n"; +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; // ----------------------------------------------------------------------------- - - partInit.getAffectedRegisters().add("instructionPointer", 32); + cp.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -347,7 +430,7 @@ partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_addr [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 nzimm = 0; +etiss_uint8 nzimm = 0; static BitArrayRange R_nzimm_0(6, 2); nzimm += R_nzimm_0.read(ba) << 0; static BitArrayRange R_nzimm_5(12, 12); @@ -377,7 +460,7 @@ static InstructionDefinition cjal_imm ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 imm = 0; +etiss_uint16 imm = 0; static BitArrayRange R_imm_5(2, 2); imm += R_imm_5.read(ba) << 5; static BitArrayRange R_imm_1(5, 3); @@ -397,19 +480,37 @@ imm += R_imm_11.read(ba) << 11; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//CJAL\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "*((RV32IMACFD*)cpu)->X[1ULL] = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); - partInit.code() = std::string("//CJAL\n"); + cp.code() = std::string("//CJAL\n"); // ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 2U) + ";\n"; -partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(1U) + "] = " + std::to_string(ic.current_address_ + 2U) + ";\n"; -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (4)) >> (4))) + ";\n"; -partInit.code() += "return exception;\n"; +cp.code() += "return cpu->exception;\n"; // ----------------------------------------------------------------------------- - - partInit.getAffectedRegisters().add(reg_name[1U], 32); - partInit.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -417,7 +518,7 @@ partInit.code() += "return exception;\n"; [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 imm = 0; +etiss_uint16 imm = 0; static BitArrayRange R_imm_5(2, 2); imm += R_imm_5.read(ba) << 5; static BitArrayRange R_imm_1(5, 3); @@ -459,10 +560,10 @@ static InstructionDefinition cli_imm_rd ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 imm = 0; +etiss_uint8 imm = 0; static BitArrayRange R_imm_0(6, 2); imm += R_imm_0.read(ba) << 0; -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; static BitArrayRange R_imm_5(12, 12); @@ -470,19 +571,29 @@ imm += R_imm_5.read(ba) << 5; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); - - partInit.code() = std::string("//CLI\n"); - -// ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 2U) + ";\n"; -if ((rd % 32U) != 0U) { -partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = " + std::to_string(((etiss_int8)((imm) << (2)) >> (2))) + ";\n"; -} -// ----------------------------------------------------------------------------- - - partInit.getAffectedRegisters().add(reg_name[rd % 32], 32); - partInit.getAffectedRegisters().add("instructionPointer", 32); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//CLI\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = " + std::to_string(((etiss_int8)(((etiss_int8)imm) << (2)) >> (2))) + "LL;\n"; +} // conditional +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -490,10 +601,10 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = " [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 imm = 0; +etiss_uint8 imm = 0; static BitArrayRange R_imm_0(6, 2); imm += R_imm_0.read(ba) << 0; -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; static BitArrayRange R_imm_5(12, 12); @@ -526,7 +637,7 @@ static InstructionDefinition clui_imm_rd ( etiss_uint32 imm = 0; static BitArrayRange R_imm_12(6, 2); imm += R_imm_12.read(ba) << 12; -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; static BitArrayRange R_imm_17(12, 12); @@ -534,23 +645,46 @@ imm += R_imm_17.read(ba) << 17; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//CLUI\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +if (imm == 0ULL) { // conditional +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV32IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 2ULL);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +} // conditional +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = " + std::to_string(((etiss_int32)(((etiss_int32)imm) << (14)) >> (14))) + "LL;\n"; +} // conditional +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); - partInit.code() = std::string("//CLUI\n"); + cp.code() = std::string("//CLUI\n"); // ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 2U) + ";\n"; -if (imm == 0U) { -partInit.code() += "exception = ETISS_RETURNCODE_ILLEGALINSTRUCTION;\n"; -} -if ((rd % 32U) != 0U) { -partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = " + std::to_string(((etiss_int32)((imm) << (14)) >> (14))) + ";\n"; -} -partInit.code() += "if (exception) return exception;\n"; +cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n"; // ----------------------------------------------------------------------------- - - partInit.getAffectedRegisters().add(reg_name[rd % 32], 32); - partInit.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -561,7 +695,7 @@ partInit.code() += "if (exception) return exception;\n"; etiss_uint32 imm = 0; static BitArrayRange R_imm_12(6, 2); imm += R_imm_12.read(ba) << 12; -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; static BitArrayRange R_imm_17(12, 12); @@ -591,7 +725,7 @@ static InstructionDefinition caddi16sp_nzimm ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 nzimm = 0; +etiss_uint16 nzimm = 0; static BitArrayRange R_nzimm_5(2, 2); nzimm += R_nzimm_5.read(ba) << 5; static BitArrayRange R_nzimm_7(4, 3); @@ -605,23 +739,42 @@ nzimm += R_nzimm_9.read(ba) << 9; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//CADDI16SP\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +if (nzimm) { // conditional +cp.code() += "*((RV32IMACFD*)cpu)->X[2ULL] = *((RV32IMACFD*)cpu)->X[2ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)nzimm) << (6)) >> (6))) + "LL;\n"; +} // conditional +else { // conditional +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV32IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 2ULL);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +} // conditional +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); - partInit.code() = std::string("//CADDI16SP\n"); + cp.code() = std::string("//CADDI16SP\n"); // ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 2U) + ";\n"; -if (nzimm) { -partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(2U) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(2U) + "] + " + std::to_string(((etiss_int16)((nzimm) << (6)) >> (6))) + ";\n"; -} else { -partInit.code() += "exception = ETISS_RETURNCODE_ILLEGALINSTRUCTION;\n"; -} -partInit.code() += "if (exception) return exception;\n"; +cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n"; // ----------------------------------------------------------------------------- - - partInit.getRegisterDependencies().add(reg_name[2U], 32); - partInit.getAffectedRegisters().add(reg_name[2U], 32); - partInit.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -629,7 +782,7 @@ partInit.code() += "if (exception) return exception;\n"; [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 nzimm = 0; +etiss_uint16 nzimm = 0; static BitArrayRange R_nzimm_5(2, 2); nzimm += R_nzimm_5.read(ba) << 5; static BitArrayRange R_nzimm_7(4, 3); @@ -665,23 +818,43 @@ static InstructionDefinition __reserved_clui_rd ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//__reserved_clui\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV32IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 2ULL);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); - partInit.code() = std::string("//__reserved_clui\n"); + cp.code() = std::string("//__reserved_clui\n"); // ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 2U) + ";\n"; -partInit.code() += "exception = ETISS_RETURNCODE_ILLEGALINSTRUCTION;\n"; -partInit.code() += "if (exception) return exception;\n"; +cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n"; // ----------------------------------------------------------------------------- - - partInit.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -689,7 +862,7 @@ partInit.code() += "if (exception) return exception;\n"; [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; @@ -717,27 +890,36 @@ static InstructionDefinition csrli_shamt_rs1 ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 shamt = 0; +etiss_uint8 shamt = 0; static BitArrayRange R_shamt_0(6, 2); shamt += R_shamt_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(9, 7); rs1 += R_rs1_0.read(ba) << 0; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); - partInit.code() = std::string("//CSRLI\n"); + cp.code() = std::string("//CSRLI\n"); // ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 2U) + ";\n"; -partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "] >> " + std::to_string(shamt) + ";\n"; +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] >> " + std::to_string(shamt) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; // ----------------------------------------------------------------------------- - - partInit.getRegisterDependencies().add(reg_name[rs1 + 8U], 32); - partInit.getAffectedRegisters().add(reg_name[rs1 + 8U], 32); - partInit.getAffectedRegisters().add("instructionPointer", 32); + cp.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -745,10 +927,10 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "] = * [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 shamt = 0; +etiss_uint8 shamt = 0; static BitArrayRange R_shamt_0(6, 2); shamt += R_shamt_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(9, 7); rs1 += R_rs1_0.read(ba) << 0; @@ -776,33 +958,42 @@ static InstructionDefinition csrai_shamt_rs1 ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 shamt = 0; +etiss_uint8 shamt = 0; static BitArrayRange R_shamt_0(6, 2); shamt += R_shamt_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(9, 7); rs1 += R_rs1_0.read(ba) << 0; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); - - partInit.code() = std::string("//CSRAI\n"); - -// ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 2U) + ";\n"; -if (shamt) { -partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "] = ((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "])) >> " + std::to_string(shamt) + ";\n"; -} else { -if (0U) { -partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "] = ((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "])) >> 64U;\n"; -} -} -// ----------------------------------------------------------------------------- - - partInit.getRegisterDependencies().add(reg_name[rs1 + 8U], 32); - partInit.getAffectedRegisters().add(reg_name[rs1 + 8U], 32); - partInit.getAffectedRegisters().add("instructionPointer", 32); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//CSRAI\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +if (shamt) { // conditional +{ // block +cp.code() += "{ // block\n"; +cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] = ((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL])) >> " + std::to_string(shamt) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +} // conditional +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -810,10 +1001,10 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "] = ( [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 shamt = 0; +etiss_uint8 shamt = 0; static BitArrayRange R_shamt_0(6, 2); shamt += R_shamt_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(9, 7); rs1 += R_rs1_0.read(ba) << 0; @@ -841,10 +1032,10 @@ static InstructionDefinition candi_imm_rs1 ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 imm = 0; +etiss_uint8 imm = 0; static BitArrayRange R_imm_0(6, 2); imm += R_imm_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(9, 7); rs1 += R_rs1_0.read(ba) << 0; static BitArrayRange R_imm_5(12, 12); @@ -852,18 +1043,27 @@ imm += R_imm_5.read(ba) << 5; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); - partInit.code() = std::string("//CANDI\n"); + cp.code() = std::string("//CANDI\n"); // ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 2U) + ";\n"; -partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "] & " + std::to_string(((etiss_int8)((imm) << (2)) >> (2))) + ";\n"; +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] & " + std::to_string(((etiss_int8)(((etiss_int8)imm) << (2)) >> (2))) + "LL;\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; // ----------------------------------------------------------------------------- - - partInit.getRegisterDependencies().add(reg_name[rs1 + 8U], 32); - partInit.getAffectedRegisters().add(reg_name[rs1 + 8U], 32); - partInit.getAffectedRegisters().add("instructionPointer", 32); + cp.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -871,10 +1071,10 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "] = * [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 imm = 0; +etiss_uint8 imm = 0; static BitArrayRange R_imm_0(6, 2); imm += R_imm_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(9, 7); rs1 += R_rs1_0.read(ba) << 0; static BitArrayRange R_imm_5(12, 12); @@ -904,28 +1104,36 @@ static InstructionDefinition csub_rs2_rd ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(4, 2); rs2 += R_rs2_0.read(ba) << 0; -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(9, 7); rd += R_rd_0.read(ba) << 0; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); - partInit.code() = std::string("//CSUB\n"); + cp.code() = std::string("//CSUB\n"); // ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 2U) + ";\n"; -partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "] - *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 + 8U) + "];\n"; +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) + "ULL] - *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 + 8ULL) + "ULL];\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; // ----------------------------------------------------------------------------- - - partInit.getRegisterDependencies().add(reg_name[rd + 8U], 32); - partInit.getRegisterDependencies().add(reg_name[rs2 + 8U], 32); - partInit.getAffectedRegisters().add(reg_name[rd + 8U], 32); - partInit.getAffectedRegisters().add("instructionPointer", 32); + cp.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -933,10 +1141,10 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "] = *( [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(4, 2); rs2 += R_rs2_0.read(ba) << 0; -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(9, 7); rd += R_rd_0.read(ba) << 0; @@ -964,28 +1172,36 @@ static InstructionDefinition cxor_rs2_rd ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(4, 2); rs2 += R_rs2_0.read(ba) << 0; -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(9, 7); rd += R_rd_0.read(ba) << 0; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); - partInit.code() = std::string("//CXOR\n"); + cp.code() = std::string("//CXOR\n"); // ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 2U) + ";\n"; -partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "] ^ *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 + 8U) + "];\n"; +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) + "ULL] ^ *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 + 8ULL) + "ULL];\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; // ----------------------------------------------------------------------------- - - partInit.getRegisterDependencies().add(reg_name[rd + 8U], 32); - partInit.getRegisterDependencies().add(reg_name[rs2 + 8U], 32); - partInit.getAffectedRegisters().add(reg_name[rd + 8U], 32); - partInit.getAffectedRegisters().add("instructionPointer", 32); + cp.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -993,10 +1209,10 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "] = *( [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(4, 2); rs2 += R_rs2_0.read(ba) << 0; -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(9, 7); rd += R_rd_0.read(ba) << 0; @@ -1024,28 +1240,36 @@ static InstructionDefinition cor_rs2_rd ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(4, 2); rs2 += R_rs2_0.read(ba) << 0; -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(9, 7); rd += R_rd_0.read(ba) << 0; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); - partInit.code() = std::string("//COR\n"); + cp.code() = std::string("//COR\n"); // ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 2U) + ";\n"; -partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "] | *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 + 8U) + "];\n"; +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) + "ULL] | *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 + 8ULL) + "ULL];\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; // ----------------------------------------------------------------------------- - - partInit.getRegisterDependencies().add(reg_name[rd + 8U], 32); - partInit.getRegisterDependencies().add(reg_name[rs2 + 8U], 32); - partInit.getAffectedRegisters().add(reg_name[rd + 8U], 32); - partInit.getAffectedRegisters().add("instructionPointer", 32); + cp.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -1053,10 +1277,10 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "] = *( [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(4, 2); rs2 += R_rs2_0.read(ba) << 0; -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(9, 7); rd += R_rd_0.read(ba) << 0; @@ -1084,28 +1308,36 @@ static InstructionDefinition cand_rs2_rd ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(4, 2); rs2 += R_rs2_0.read(ba) << 0; -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(9, 7); rd += R_rd_0.read(ba) << 0; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); - partInit.code() = std::string("//CAND\n"); + cp.code() = std::string("//CAND\n"); // ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 2U) + ";\n"; -partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "] & *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 + 8U) + "];\n"; +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) + "ULL] & *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 + 8ULL) + "ULL];\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; // ----------------------------------------------------------------------------- - - partInit.getRegisterDependencies().add(reg_name[rd + 8U], 32); - partInit.getRegisterDependencies().add(reg_name[rs2 + 8U], 32); - partInit.getAffectedRegisters().add(reg_name[rd + 8U], 32); - partInit.getAffectedRegisters().add("instructionPointer", 32); + cp.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -1113,10 +1345,10 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8U) + "] = *( [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(4, 2); rs2 += R_rs2_0.read(ba) << 0; -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(9, 7); rd += R_rd_0.read(ba) << 0; @@ -1144,7 +1376,7 @@ static InstructionDefinition cj_imm ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 imm = 0; +etiss_uint16 imm = 0; static BitArrayRange R_imm_5(2, 2); imm += R_imm_5.read(ba) << 5; static BitArrayRange R_imm_1(5, 3); @@ -1164,17 +1396,32 @@ imm += R_imm_11.read(ba) << 11; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); - partInit.code() = std::string("//CJ\n"); + cp.code() = std::string("//CJ\n"); // ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 2U) + ";\n"; -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (4)) >> (4))) + ";\n"; -partInit.code() += "return exception;\n"; +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n"; +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; // ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); - partInit.getAffectedRegisters().add("instructionPointer", 32); + cp.code() = std::string("//CJ\n"); + +// ----------------------------------------------------------------------------- +cp.code() += "return cpu->exception;\n"; +// ----------------------------------------------------------------------------- + } return true; }, @@ -1182,7 +1429,7 @@ partInit.code() += "return exception;\n"; [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 imm = 0; +etiss_uint16 imm = 0; static BitArrayRange R_imm_5(2, 2); imm += R_imm_5.read(ba) << 5; static BitArrayRange R_imm_1(5, 3); @@ -1224,14 +1471,14 @@ static InstructionDefinition cbeqz_imm_rs1 ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 imm = 0; +etiss_uint16 imm = 0; static BitArrayRange R_imm_5(2, 2); imm += R_imm_5.read(ba) << 5; static BitArrayRange R_imm_1(4, 3); imm += R_imm_1.read(ba) << 1; static BitArrayRange R_imm_6(6, 5); imm += R_imm_6.read(ba) << 6; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(9, 7); rs1 += R_rs1_0.read(ba) << 0; static BitArrayRange R_imm_3(11, 10); @@ -1241,20 +1488,34 @@ imm += R_imm_8.read(ba) << 8; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); - partInit.code() = std::string("//CBEQZ\n"); + cp.code() = std::string("//CBEQZ\n"); // ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 2U) + ";\n"; -partInit.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "] == 0U) {\n"; -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (7)) >> (7))) + ";\n"; -partInit.code() += "}\n"; -partInit.code() += "if (cpu->instructionPointer != " + std::to_string(ic.current_address_ + 2) + ") return exception;\n"; +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] == 0ULL) { // conditional\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)(((etiss_int16)imm) << (7)) >> (7))) + "LL;\n"; +cp.code() += "} // conditional\n"; +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; // ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); - partInit.getRegisterDependencies().add(reg_name[rs1 + 8U], 32); - partInit.getAffectedRegisters().add("instructionPointer", 32); + cp.code() = std::string("//CBEQZ\n"); + +// ----------------------------------------------------------------------------- +cp.code() += "if (cpu->nextPc != " + std::to_string(ic.current_address_ + 2) + "ULL) return cpu->exception;\n"; +// ----------------------------------------------------------------------------- + } return true; }, @@ -1262,14 +1523,14 @@ partInit.code() += "if (cpu->instructionPointer != " + std::to_string(ic.current [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 imm = 0; +etiss_uint16 imm = 0; static BitArrayRange R_imm_5(2, 2); imm += R_imm_5.read(ba) << 5; static BitArrayRange R_imm_1(4, 3); imm += R_imm_1.read(ba) << 1; static BitArrayRange R_imm_6(6, 5); imm += R_imm_6.read(ba) << 6; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(9, 7); rs1 += R_rs1_0.read(ba) << 0; static BitArrayRange R_imm_3(11, 10); @@ -1301,14 +1562,14 @@ static InstructionDefinition cbnez_imm_rs1 ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 imm = 0; +etiss_uint16 imm = 0; static BitArrayRange R_imm_5(2, 2); imm += R_imm_5.read(ba) << 5; static BitArrayRange R_imm_1(4, 3); imm += R_imm_1.read(ba) << 1; static BitArrayRange R_imm_6(6, 5); imm += R_imm_6.read(ba) << 6; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(9, 7); rs1 += R_rs1_0.read(ba) << 0; static BitArrayRange R_imm_3(11, 10); @@ -1318,20 +1579,34 @@ imm += R_imm_8.read(ba) << 8; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); - partInit.code() = std::string("//CBNEZ\n"); + cp.code() = std::string("//CBNEZ\n"); // ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 2U) + ";\n"; -partInit.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8U) + "] != 0U) {\n"; -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (7)) >> (7))) + ";\n"; -partInit.code() += "}\n"; -partInit.code() += "if (cpu->instructionPointer != " + std::to_string(ic.current_address_ + 2) + ") return exception;\n"; +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] != 0ULL) { // conditional\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)(((etiss_int16)imm) << (7)) >> (7))) + "LL;\n"; +cp.code() += "} // conditional\n"; +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; // ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); - partInit.getRegisterDependencies().add(reg_name[rs1 + 8U], 32); - partInit.getAffectedRegisters().add("instructionPointer", 32); + cp.code() = std::string("//CBNEZ\n"); + +// ----------------------------------------------------------------------------- +cp.code() += "if (cpu->nextPc != " + std::to_string(ic.current_address_ + 2) + "ULL) return cpu->exception;\n"; +// ----------------------------------------------------------------------------- + } return true; }, @@ -1339,14 +1614,14 @@ partInit.code() += "if (cpu->instructionPointer != " + std::to_string(ic.current [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 imm = 0; +etiss_uint16 imm = 0; static BitArrayRange R_imm_5(2, 2); imm += R_imm_5.read(ba) << 5; static BitArrayRange R_imm_1(4, 3); imm += R_imm_1.read(ba) << 1; static BitArrayRange R_imm_6(6, 5); imm += R_imm_6.read(ba) << 6; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(9, 7); rs1 += R_rs1_0.read(ba) << 0; static BitArrayRange R_imm_3(11, 10); @@ -1378,29 +1653,34 @@ static InstructionDefinition cslli_nzuimm_rs1 ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 nzuimm = 0; +etiss_uint8 nzuimm = 0; static BitArrayRange R_nzuimm_0(6, 2); nzuimm += R_nzuimm_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(11, 7); rs1 += R_rs1_0.read(ba) << 0; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); - partInit.code() = std::string("//CSLLI\n"); + cp.code() = std::string("//CSLLI\n"); // ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 2U) + ";\n"; -if (nzuimm) { -partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] << " + std::to_string(nzuimm) + ";\n"; -} +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +if (nzuimm) { // conditional +cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] << " + std::to_string(nzuimm) + "ULL;\n"; +} // conditional +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; // ----------------------------------------------------------------------------- - - partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32); - partInit.getAffectedRegisters().add(reg_name[rs1 % 32], 32); - partInit.getAffectedRegisters().add("instructionPointer", 32); + cp.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -1408,10 +1688,10 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32) + "] = * [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 nzuimm = 0; +etiss_uint8 nzuimm = 0; static BitArrayRange R_nzuimm_0(6, 2); nzuimm += R_nzuimm_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(11, 7); rs1 += R_rs1_0.read(ba) << 0; @@ -1439,12 +1719,12 @@ static InstructionDefinition clwsp_uimm_rd ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 uimm = 0; +etiss_uint8 uimm = 0; static BitArrayRange R_uimm_6(3, 2); uimm += R_uimm_6.read(ba) << 6; static BitArrayRange R_uimm_2(6, 4); uimm += R_uimm_2.read(ba) << 2; -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; static BitArrayRange R_uimm_5(12, 12); @@ -1452,27 +1732,61 @@ uimm += R_uimm_5.read(ba) << 5; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//CLWSP\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +if (rd % 32ULL) { // conditional +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint32 mem_val_0;\n"; +cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, *((RV32IMACFD*)cpu)->X[2ULL] + " + std::to_string(uimm) + "ULL, (etiss_uint8*)&mem_val_0, 4);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "etiss_int32 res = mem_val_0;\n"; +cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int32)(res);\n"; +cp.code() += "} // block\n"; +} // block +} // conditional +else { // conditional +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV32IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 2ULL);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +} // conditional +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); - partInit.code() = std::string("//CLWSP\n"); + cp.code() = std::string("//CLWSP\n"); // ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 2U) + ";\n"; -partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(2U) + "] + " + std::to_string(uimm) + ";\n"; -partInit.code() += "etiss_uint32 mem_val_0;\n"; -partInit.code() += "exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n"; -partInit.code() += "etiss_int32 res = mem_val_0;\n"; -if (rd % 32U) { -partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = res;\n"; -} else { -partInit.code() += "exception = ETISS_RETURNCODE_ILLEGALINSTRUCTION;\n"; -} -partInit.code() += "if (exception) return exception;\n"; +cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n"; // ----------------------------------------------------------------------------- - - partInit.getRegisterDependencies().add(reg_name[2U], 32); - partInit.getAffectedRegisters().add(reg_name[rd % 32], 32); - partInit.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -1480,12 +1794,12 @@ partInit.code() += "if (exception) return exception;\n"; [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 uimm = 0; +etiss_uint8 uimm = 0; static BitArrayRange R_uimm_6(3, 2); uimm += R_uimm_6.read(ba) << 6; static BitArrayRange R_uimm_2(6, 4); uimm += R_uimm_2.read(ba) << 2; -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; static BitArrayRange R_uimm_5(12, 12); @@ -1515,29 +1829,34 @@ static InstructionDefinition cmv_rs2_rd ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(6, 2); rs2 += R_rs2_0.read(ba) << 0; -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); - partInit.code() = std::string("//CMV\n"); + cp.code() = std::string("//CMV\n"); // ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 2U) + ";\n"; -if ((rd % 32U) != 0U) { -partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "];\n"; -} +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n"; +} // conditional +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; // ----------------------------------------------------------------------------- - - partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 32); - partInit.getAffectedRegisters().add(reg_name[rd % 32], 32); - partInit.getAffectedRegisters().add("instructionPointer", 32); + cp.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -1545,10 +1864,10 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *( [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(6, 2); rs2 += R_rs2_0.read(ba) << 0; -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; @@ -1576,28 +1895,48 @@ static InstructionDefinition cjr_rs1 ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(11, 7); rs1 += R_rs1_0.read(ba) << 0; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//CJR\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +if (rs1) { // conditional +cp.code() += "cpu->nextPc = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] & -2LL;\n"; +} // conditional +else { // conditional +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV32IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 2ULL);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +} // conditional +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); - partInit.code() = std::string("//CJR\n"); + cp.code() = std::string("//CJR\n"); // ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 2U) + ";\n"; -if (rs1) { -partInit.code() += "cpu->instructionPointer = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] & -2U;\n"; -} else { -partInit.code() += "exception = ETISS_RETURNCODE_ILLEGALINSTRUCTION;\n"; -} -partInit.code() += "return exception;\n"; +cp.code() += "return cpu->exception;\n"; // ----------------------------------------------------------------------------- - - partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32); - partInit.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -1605,7 +1944,7 @@ partInit.code() += "return exception;\n"; [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(11, 7); rs1 += R_rs1_0.read(ba) << 0; @@ -1636,17 +1975,37 @@ static InstructionDefinition __reserved_cmv_ ( // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//__reserved_cmv\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV32IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 2ULL);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); - partInit.code() = std::string("//__reserved_cmv\n"); + cp.code() = std::string("//__reserved_cmv\n"); // ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 2U) + ";\n"; -partInit.code() += "exception = ETISS_RETURNCODE_ILLEGALINSTRUCTION;\n"; -partInit.code() += "if (exception) return exception;\n"; +cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n"; // ----------------------------------------------------------------------------- - - partInit.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -1679,30 +2038,34 @@ static InstructionDefinition cadd_rs2_rd ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(6, 2); rs2 += R_rs2_0.read(ba) << 0; -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); - partInit.code() = std::string("//CADD\n"); + cp.code() = std::string("//CADD\n"); // ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 2U) + ";\n"; -if ((rd % 32U) != 0U) { -partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32U) + "] + *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "];\n"; -} +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] + *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n"; +} // conditional +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; // ----------------------------------------------------------------------------- - - partInit.getRegisterDependencies().add(reg_name[rd % 32U], 32); - partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 32); - partInit.getAffectedRegisters().add(reg_name[rd % 32], 32); - partInit.getAffectedRegisters().add("instructionPointer", 32); + cp.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -1710,10 +2073,10 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *( [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(6, 2); rs2 += R_rs2_0.read(ba) << 0; -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; @@ -1741,27 +2104,44 @@ static InstructionDefinition cjalr_rs1 ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(11, 7); rs1 += R_rs1_0.read(ba) << 0; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//CJALR\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint32 new_pc = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n"; +cp.code() += "*((RV32IMACFD*)cpu)->X[1ULL] = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n"; +cp.code() += "cpu->nextPc = new_pc & -2LL;\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); - partInit.code() = std::string("//CJALR\n"); + cp.code() = std::string("//CJALR\n"); // ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 2U) + ";\n"; -partInit.code() += "etiss_uint32 new_pc = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n"; -partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(1U) + "] = " + std::to_string(ic.current_address_ + 2U) + ";\n"; -partInit.code() += "cpu->instructionPointer = new_pc & -2U;\n"; -partInit.code() += "return exception;\n"; +cp.code() += "return cpu->exception;\n"; // ----------------------------------------------------------------------------- - - partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32); - partInit.getAffectedRegisters().add(reg_name[1U], 32); - partInit.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -1769,7 +2149,7 @@ partInit.code() += "return exception;\n"; [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(11, 7); rs1 += R_rs1_0.read(ba) << 0; @@ -1800,17 +2180,37 @@ static InstructionDefinition cebreak_ ( // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//CEBREAK\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV32IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 3ULL);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); - partInit.code() = std::string("//CEBREAK\n"); + cp.code() = std::string("//CEBREAK\n"); // ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 2U) + ";\n"; -partInit.code() += "exception = ETISS_RETURNCODE_CPUFINISHED;\n"; -partInit.code() += "return exception;\n"; +cp.code() += "return cpu->exception;\n"; // ----------------------------------------------------------------------------- - - partInit.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -1843,10 +2243,10 @@ static InstructionDefinition cswsp_rs2_uimm ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(6, 2); rs2 += R_rs2_0.read(ba) << 0; -etiss_uint32 uimm = 0; +etiss_uint8 uimm = 0; static BitArrayRange R_uimm_6(8, 7); uimm += R_uimm_6.read(ba) << 6; static BitArrayRange R_uimm_2(12, 9); @@ -1854,22 +2254,47 @@ uimm += R_uimm_2.read(ba) << 2; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//CSWSP\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[2ULL] + " + std::to_string(uimm) + "ULL;\n"; +cp.code() += "etiss_uint32 mem_val_0;\n"; +cp.code() += "mem_val_0 = (etiss_uint32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n"; +cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); - partInit.code() = std::string("//CSWSP\n"); + cp.code() = std::string("//CSWSP\n"); // ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 2U) + ";\n"; -partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(2U) + "] + " + std::to_string(uimm) + ";\n"; -partInit.code() += "etiss_uint32 mem_val_0 = (etiss_uint32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]);\n"; -partInit.code() += "exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n"; - -partInit.code() += "if (exception) return exception;\n"; +cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n"; // ----------------------------------------------------------------------------- - - partInit.getRegisterDependencies().add(reg_name[2U], 32); - partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 32); - partInit.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -1877,10 +2302,10 @@ partInit.code() += "if (exception) return exception;\n"; [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(6, 2); rs2 += R_rs2_0.read(ba) << 0; -etiss_uint32 uimm = 0; +etiss_uint8 uimm = 0; static BitArrayRange R_uimm_6(8, 7); uimm += R_uimm_6.read(ba) << 6; static BitArrayRange R_uimm_2(12, 9); @@ -1913,17 +2338,37 @@ static InstructionDefinition dii_ ( // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//DII\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV32IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 2ULL);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); - partInit.code() = std::string("//DII\n"); + cp.code() = std::string("//DII\n"); // ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 2U) + ";\n"; -partInit.code() += "exception = ETISS_RETURNCODE_ILLEGALINSTRUCTION;\n"; -partInit.code() += "return exception;\n"; +cp.code() += "return cpu->exception;\n"; // ----------------------------------------------------------------------------- - - partInit.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32IInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32IInstr.cpp index de8acc1d26..26692b7a72 100644 --- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32IInstr.cpp +++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32IInstr.cpp @@ -1,13 +1,11 @@ /** - * Generated on Mon, 09 May 2022 21:04:41 +0200. + * Generated on Tue, 28 Nov 2023 09:45:19 +0100. * * This file contains the instruction behavior models of the RV32I * instruction set for the RV32IMACFD core architecture. */ #include "RV32IMACFDArch.h" - -#define ETISS_ARCH_STATIC_FN_ONLY #include "RV32IMACFDFuncs.h" using namespace etiss; @@ -28,7 +26,7 @@ static InstructionDefinition lui_rd_imm ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; etiss_uint32 imm = 0; @@ -37,19 +35,25 @@ imm += R_imm_12.read(ba) << 12; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); - partInit.code() = std::string("//LUI\n"); + cp.code() = std::string("//LUI\n"); // ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -if ((rd % 32U) != 0U) { -partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = " + std::to_string((etiss_int32)(imm)) + ";\n"; -} +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = " + std::to_string((etiss_uint32)(((etiss_int32)(imm)))) + "ULL;\n"; +} // conditional +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; // ----------------------------------------------------------------------------- - - partInit.getAffectedRegisters().add(reg_name[rd % 32], 32); - partInit.getAffectedRegisters().add("instructionPointer", 32); + cp.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -57,7 +61,7 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = " [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; etiss_uint32 imm = 0; @@ -88,7 +92,7 @@ static InstructionDefinition auipc_rd_imm ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; etiss_uint32 imm = 0; @@ -97,19 +101,25 @@ imm += R_imm_12.read(ba) << 12; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); - partInit.code() = std::string("//AUIPC\n"); + cp.code() = std::string("//AUIPC\n"); // ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -if ((rd % 32U) != 0U) { -partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = " + std::to_string(ic.current_address_ + (etiss_int32)(imm)) + ";\n"; -} +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = " + std::to_string(ic.current_address_ + (etiss_int32)(imm)) + "LL;\n"; +} // conditional +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; // ----------------------------------------------------------------------------- - - partInit.getAffectedRegisters().add(reg_name[rd % 32], 32); - partInit.getAffectedRegisters().add("instructionPointer", 32); + cp.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -117,7 +127,7 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = " [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; etiss_uint32 imm = 0; @@ -148,7 +158,7 @@ static InstructionDefinition jal_rd_imm ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; etiss_uint32 imm = 0; @@ -163,25 +173,57 @@ imm += R_imm_20.read(ba) << 20; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//JAL\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +if (imm % 2ULL) { // conditional +{ // block +cp.code() += "{ // block\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV32IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 0ULL);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // block\n"; +} // block +} // conditional +else { // conditional +{ // block +cp.code() += "{ // block\n"; +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n"; +} // conditional +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int32)(((etiss_int32)imm) << (11)) >> (11))) + "LL;\n"; +cp.code() += "} // block\n"; +} // block +} // conditional +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); - partInit.code() = std::string("//JAL\n"); + cp.code() = std::string("//JAL\n"); // ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -if (imm % 2U) { -partInit.code() += "exception = ETISS_RETURNCODE_IBUS_READ_ERROR;\n"; -} else { -if ((rd % 32U) != 0U) { -partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -} -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + ((etiss_int32)((imm) << (11)) >> (11))) + ";\n"; -} -partInit.code() += "return exception;\n"; +cp.code() += "return cpu->exception;\n"; // ----------------------------------------------------------------------------- - - partInit.getAffectedRegisters().add(reg_name[rd % 32], 32); - partInit.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -189,7 +231,7 @@ partInit.code() += "return exception;\n"; [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; etiss_uint32 imm = 0; @@ -226,40 +268,70 @@ static InstructionDefinition jalr_rd_rs1_imm ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 imm = 0; +etiss_uint16 imm = 0; static BitArrayRange R_imm_0(31, 20); imm += R_imm_0.read(ba) << 0; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//JALR\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint32 new_pc = (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL) & -2LL;\n"; +cp.code() += "if (new_pc % 2ULL) { // conditional\n"; +{ // block +cp.code() += "{ // block\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV32IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 0ULL);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // block\n"; +} // block +cp.code() += "} // conditional\n"; +cp.code() += "else { // conditional\n"; +{ // block +cp.code() += "{ // block\n"; +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n"; +} // conditional +cp.code() += "cpu->nextPc = new_pc & -2LL;\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "} // conditional\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); - partInit.code() = std::string("//JALR\n"); + cp.code() = std::string("//JALR\n"); // ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -partInit.code() += "etiss_uint32 new_pc = (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ") & -2U;\n"; -partInit.code() += "if (new_pc % 2U) {\n"; -partInit.code() += "exception = ETISS_RETURNCODE_IBUS_READ_ERROR;\n"; -partInit.code() += "}\n"; -partInit.code() += " else {\n"; -if ((rd % 32U) != 0U) { -partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -} -partInit.code() += "cpu->instructionPointer = new_pc & -2U;\n"; -partInit.code() += "}\n"; -partInit.code() += "return exception;\n"; +cp.code() += "return cpu->exception;\n"; // ----------------------------------------------------------------------------- - - partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32); - partInit.getAffectedRegisters().add(reg_name[rd % 32], 32); - partInit.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -267,13 +339,13 @@ partInit.code() += "return exception;\n"; [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 imm = 0; +etiss_uint16 imm = 0; static BitArrayRange R_imm_0(31, 20); imm += R_imm_0.read(ba) << 0; @@ -301,15 +373,15 @@ static InstructionDefinition beq_imm_rs1_rs2 ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 imm = 0; +etiss_uint16 imm = 0; static BitArrayRange R_imm_11(7, 7); imm += R_imm_11.read(ba) << 11; static BitArrayRange R_imm_1(11, 8); imm += R_imm_1.read(ba) << 1; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; static BitArrayRange R_imm_5(30, 25); @@ -319,25 +391,60 @@ imm += R_imm_12.read(ba) << 12; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//BEQ\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] == *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) { // conditional\n"; +{ // block +cp.code() += "{ // block\n"; +if (imm % 2ULL) { // conditional +{ // block +cp.code() += "{ // block\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV32IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 0ULL);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // block\n"; +} // block +} // conditional +else { // conditional +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)(((etiss_int16)imm) << (3)) >> (3))) + "LL;\n"; +cp.code() += "} // block\n"; +} // block +} // conditional +cp.code() += "} // block\n"; +} // block +cp.code() += "} // conditional\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); - partInit.code() = std::string("//BEQ\n"); + cp.code() = std::string("//BEQ\n"); // ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -partInit.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] == *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]) {\n"; -if (imm % 2U) { -partInit.code() += "exception = ETISS_RETURNCODE_IBUS_READ_ERROR;\n"; -} else { -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n"; -} -partInit.code() += "}\n"; -partInit.code() += "if (exception | cpu->instructionPointer != " + std::to_string(ic.current_address_ + 4) + ") return exception;\n"; +cp.code() += "if (cpu->return_pending | cpu->exception | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + "ULL) return cpu->exception;\n"; // ----------------------------------------------------------------------------- - - partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32); - partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 32); - partInit.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -345,15 +452,15 @@ partInit.code() += "if (exception | cpu->instructionPointer != " + std::to_strin [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 imm = 0; +etiss_uint16 imm = 0; static BitArrayRange R_imm_11(7, 7); imm += R_imm_11.read(ba) << 11; static BitArrayRange R_imm_1(11, 8); imm += R_imm_1.read(ba) << 1; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; static BitArrayRange R_imm_5(30, 25); @@ -385,15 +492,15 @@ static InstructionDefinition bne_imm_rs1_rs2 ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 imm = 0; +etiss_uint16 imm = 0; static BitArrayRange R_imm_11(7, 7); imm += R_imm_11.read(ba) << 11; static BitArrayRange R_imm_1(11, 8); imm += R_imm_1.read(ba) << 1; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; static BitArrayRange R_imm_5(30, 25); @@ -403,25 +510,60 @@ imm += R_imm_12.read(ba) << 12; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//BNE\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] != *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) { // conditional\n"; +{ // block +cp.code() += "{ // block\n"; +if (imm % 2ULL) { // conditional +{ // block +cp.code() += "{ // block\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV32IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 0ULL);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // block\n"; +} // block +} // conditional +else { // conditional +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)(((etiss_int16)imm) << (3)) >> (3))) + "LL;\n"; +cp.code() += "} // block\n"; +} // block +} // conditional +cp.code() += "} // block\n"; +} // block +cp.code() += "} // conditional\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); - partInit.code() = std::string("//BNE\n"); + cp.code() = std::string("//BNE\n"); // ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -partInit.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] != *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]) {\n"; -if (imm % 2U) { -partInit.code() += "exception = ETISS_RETURNCODE_IBUS_READ_ERROR;\n"; -} else { -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n"; -} -partInit.code() += "}\n"; -partInit.code() += "if (exception | cpu->instructionPointer != " + std::to_string(ic.current_address_ + 4) + ") return exception;\n"; +cp.code() += "if (cpu->return_pending | cpu->exception | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + "ULL) return cpu->exception;\n"; // ----------------------------------------------------------------------------- - - partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32); - partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 32); - partInit.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -429,15 +571,15 @@ partInit.code() += "if (exception | cpu->instructionPointer != " + std::to_strin [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 imm = 0; +etiss_uint16 imm = 0; static BitArrayRange R_imm_11(7, 7); imm += R_imm_11.read(ba) << 11; static BitArrayRange R_imm_1(11, 8); imm += R_imm_1.read(ba) << 1; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; static BitArrayRange R_imm_5(30, 25); @@ -469,15 +611,15 @@ static InstructionDefinition blt_imm_rs1_rs2 ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 imm = 0; +etiss_uint16 imm = 0; static BitArrayRange R_imm_11(7, 7); imm += R_imm_11.read(ba) << 11; static BitArrayRange R_imm_1(11, 8); imm += R_imm_1.read(ba) << 1; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; static BitArrayRange R_imm_5(30, 25); @@ -487,25 +629,60 @@ imm += R_imm_12.read(ba) << 12; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//BLT\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "if ((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) < (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL])) { // conditional\n"; +{ // block +cp.code() += "{ // block\n"; +if (imm % 2ULL) { // conditional +{ // block +cp.code() += "{ // block\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV32IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 0ULL);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // block\n"; +} // block +} // conditional +else { // conditional +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)(((etiss_int16)imm) << (3)) >> (3))) + "LL;\n"; +cp.code() += "} // block\n"; +} // block +} // conditional +cp.code() += "} // block\n"; +} // block +cp.code() += "} // conditional\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); - partInit.code() = std::string("//BLT\n"); + cp.code() = std::string("//BLT\n"); // ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -partInit.code() += "if ((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]) < (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "])) {\n"; -if (imm % 2U) { -partInit.code() += "exception = ETISS_RETURNCODE_IBUS_READ_ERROR;\n"; -} else { -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n"; -} -partInit.code() += "}\n"; -partInit.code() += "if (exception | cpu->instructionPointer != " + std::to_string(ic.current_address_ + 4) + ") return exception;\n"; +cp.code() += "if (cpu->return_pending | cpu->exception | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + "ULL) return cpu->exception;\n"; // ----------------------------------------------------------------------------- - - partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32); - partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 32); - partInit.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -513,15 +690,15 @@ partInit.code() += "if (exception | cpu->instructionPointer != " + std::to_strin [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 imm = 0; +etiss_uint16 imm = 0; static BitArrayRange R_imm_11(7, 7); imm += R_imm_11.read(ba) << 11; static BitArrayRange R_imm_1(11, 8); imm += R_imm_1.read(ba) << 1; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; static BitArrayRange R_imm_5(30, 25); @@ -553,15 +730,15 @@ static InstructionDefinition bge_imm_rs1_rs2 ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 imm = 0; +etiss_uint16 imm = 0; static BitArrayRange R_imm_11(7, 7); imm += R_imm_11.read(ba) << 11; static BitArrayRange R_imm_1(11, 8); imm += R_imm_1.read(ba) << 1; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; static BitArrayRange R_imm_5(30, 25); @@ -571,25 +748,60 @@ imm += R_imm_12.read(ba) << 12; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//BGE\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "if ((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) >= (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL])) { // conditional\n"; +{ // block +cp.code() += "{ // block\n"; +if (imm % 2ULL) { // conditional +{ // block +cp.code() += "{ // block\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV32IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 0ULL);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // block\n"; +} // block +} // conditional +else { // conditional +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)(((etiss_int16)imm) << (3)) >> (3))) + "LL;\n"; +cp.code() += "} // block\n"; +} // block +} // conditional +cp.code() += "} // block\n"; +} // block +cp.code() += "} // conditional\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); - partInit.code() = std::string("//BGE\n"); + cp.code() = std::string("//BGE\n"); // ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -partInit.code() += "if ((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]) >= (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "])) {\n"; -if (imm % 2U) { -partInit.code() += "exception = ETISS_RETURNCODE_IBUS_READ_ERROR;\n"; -} else { -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n"; -} -partInit.code() += "}\n"; -partInit.code() += "if (exception | cpu->instructionPointer != " + std::to_string(ic.current_address_ + 4) + ") return exception;\n"; +cp.code() += "if (cpu->return_pending | cpu->exception | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + "ULL) return cpu->exception;\n"; // ----------------------------------------------------------------------------- - - partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32); - partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 32); - partInit.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -597,15 +809,15 @@ partInit.code() += "if (exception | cpu->instructionPointer != " + std::to_strin [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 imm = 0; +etiss_uint16 imm = 0; static BitArrayRange R_imm_11(7, 7); imm += R_imm_11.read(ba) << 11; static BitArrayRange R_imm_1(11, 8); imm += R_imm_1.read(ba) << 1; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; static BitArrayRange R_imm_5(30, 25); @@ -637,15 +849,15 @@ static InstructionDefinition bltu_imm_rs1_rs2 ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 imm = 0; +etiss_uint16 imm = 0; static BitArrayRange R_imm_11(7, 7); imm += R_imm_11.read(ba) << 11; static BitArrayRange R_imm_1(11, 8); imm += R_imm_1.read(ba) << 1; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; static BitArrayRange R_imm_5(30, 25); @@ -655,25 +867,60 @@ imm += R_imm_12.read(ba) << 12; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//BLTU\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] < *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) { // conditional\n"; +{ // block +cp.code() += "{ // block\n"; +if (imm % 2ULL) { // conditional +{ // block +cp.code() += "{ // block\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV32IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 0ULL);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // block\n"; +} // block +} // conditional +else { // conditional +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)(((etiss_int16)imm) << (3)) >> (3))) + "LL;\n"; +cp.code() += "} // block\n"; +} // block +} // conditional +cp.code() += "} // block\n"; +} // block +cp.code() += "} // conditional\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); - partInit.code() = std::string("//BLTU\n"); + cp.code() = std::string("//BLTU\n"); // ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -partInit.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] < *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]) {\n"; -if (imm % 2U) { -partInit.code() += "exception = ETISS_RETURNCODE_IBUS_READ_ERROR;\n"; -} else { -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n"; -} -partInit.code() += "}\n"; -partInit.code() += "if (exception | cpu->instructionPointer != " + std::to_string(ic.current_address_ + 4) + ") return exception;\n"; +cp.code() += "if (cpu->return_pending | cpu->exception | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + "ULL) return cpu->exception;\n"; // ----------------------------------------------------------------------------- - - partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32); - partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 32); - partInit.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -681,15 +928,15 @@ partInit.code() += "if (exception | cpu->instructionPointer != " + std::to_strin [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 imm = 0; +etiss_uint16 imm = 0; static BitArrayRange R_imm_11(7, 7); imm += R_imm_11.read(ba) << 11; static BitArrayRange R_imm_1(11, 8); imm += R_imm_1.read(ba) << 1; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; static BitArrayRange R_imm_5(30, 25); @@ -721,15 +968,15 @@ static InstructionDefinition bgeu_imm_rs1_rs2 ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 imm = 0; +etiss_uint16 imm = 0; static BitArrayRange R_imm_11(7, 7); imm += R_imm_11.read(ba) << 11; static BitArrayRange R_imm_1(11, 8); imm += R_imm_1.read(ba) << 1; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; static BitArrayRange R_imm_5(30, 25); @@ -739,25 +986,60 @@ imm += R_imm_12.read(ba) << 12; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//BGEU\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] >= *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) { // conditional\n"; +{ // block +cp.code() += "{ // block\n"; +if (imm % 2ULL) { // conditional +{ // block +cp.code() += "{ // block\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV32IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 0ULL);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // block\n"; +} // block +} // conditional +else { // conditional +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)(((etiss_int16)imm) << (3)) >> (3))) + "LL;\n"; +cp.code() += "} // block\n"; +} // block +} // conditional +cp.code() += "} // block\n"; +} // block +cp.code() += "} // conditional\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); - partInit.code() = std::string("//BGEU\n"); + cp.code() = std::string("//BGEU\n"); // ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -partInit.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] >= *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]) {\n"; -if (imm % 2U) { -partInit.code() += "exception = ETISS_RETURNCODE_IBUS_READ_ERROR;\n"; -} else { -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + ((etiss_int16)((imm) << (3)) >> (3))) + ";\n"; -} -partInit.code() += "}\n"; -partInit.code() += "if (exception | cpu->instructionPointer != " + std::to_string(ic.current_address_ + 4) + ") return exception;\n"; +cp.code() += "if (cpu->return_pending | cpu->exception | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + "ULL) return cpu->exception;\n"; // ----------------------------------------------------------------------------- - - partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32); - partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 32); - partInit.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -765,15 +1047,15 @@ partInit.code() += "if (exception | cpu->instructionPointer != " + std::to_strin [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 imm = 0; +etiss_uint16 imm = 0; static BitArrayRange R_imm_11(7, 7); imm += R_imm_11.read(ba) << 11; static BitArrayRange R_imm_1(11, 8); imm += R_imm_1.read(ba) << 1; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; static BitArrayRange R_imm_5(30, 25); @@ -805,37 +1087,62 @@ static InstructionDefinition lb_rd_rs1_imm ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 imm = 0; +etiss_uint16 imm = 0; static BitArrayRange R_imm_0(31, 20); imm += R_imm_0.read(ba) << 0; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//LB\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint32 load_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n"; +cp.code() += "etiss_uint8 mem_val_0;\n"; +cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 1);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "etiss_int8 res = (etiss_int8)(mem_val_0);\n"; +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint32)(res);\n"; +} // conditional +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); - partInit.code() = std::string("//LB\n"); + cp.code() = std::string("//LB\n"); // ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -partInit.code() += "etiss_uint32 load_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n"; -partInit.code() += "etiss_uint8 mem_val_0;\n"; -partInit.code() += "exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 1);\n"; -partInit.code() += "etiss_int8 res = (etiss_int8)(mem_val_0);\n"; -if ((rd % 32U) != 0U) { -partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_int32)(res);\n"; -} -partInit.code() += "if (exception) return exception;\n"; +cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n"; // ----------------------------------------------------------------------------- - - partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32); - partInit.getAffectedRegisters().add(reg_name[rd % 32], 32); - partInit.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -843,13 +1150,13 @@ partInit.code() += "if (exception) return exception;\n"; [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 imm = 0; +etiss_uint16 imm = 0; static BitArrayRange R_imm_0(31, 20); imm += R_imm_0.read(ba) << 0; @@ -877,37 +1184,62 @@ static InstructionDefinition lh_rd_rs1_imm ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 imm = 0; +etiss_uint16 imm = 0; static BitArrayRange R_imm_0(31, 20); imm += R_imm_0.read(ba) << 0; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//LH\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint32 load_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n"; +cp.code() += "etiss_uint16 mem_val_0;\n"; +cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 2);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "etiss_int16 res = (etiss_int16)(mem_val_0);\n"; +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint32)(res);\n"; +} // conditional +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); - partInit.code() = std::string("//LH\n"); + cp.code() = std::string("//LH\n"); // ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -partInit.code() += "etiss_uint32 load_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n"; -partInit.code() += "etiss_uint16 mem_val_0;\n"; -partInit.code() += "exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 2);\n"; -partInit.code() += "etiss_int16 res = (etiss_int16)(mem_val_0);\n"; -if ((rd % 32U) != 0U) { -partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_int32)(res);\n"; -} -partInit.code() += "if (exception) return exception;\n"; +cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n"; // ----------------------------------------------------------------------------- - - partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32); - partInit.getAffectedRegisters().add(reg_name[rd % 32], 32); - partInit.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -915,13 +1247,13 @@ partInit.code() += "if (exception) return exception;\n"; [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 imm = 0; +etiss_uint16 imm = 0; static BitArrayRange R_imm_0(31, 20); imm += R_imm_0.read(ba) << 0; @@ -949,37 +1281,62 @@ static InstructionDefinition lw_rd_rs1_imm ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 imm = 0; +etiss_uint16 imm = 0; static BitArrayRange R_imm_0(31, 20); imm += R_imm_0.read(ba) << 0; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//LW\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint32 load_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n"; +cp.code() += "etiss_uint32 mem_val_0;\n"; +cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 4);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "etiss_int32 res = (etiss_int32)(mem_val_0);\n"; +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint32)(res);\n"; +} // conditional +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); - partInit.code() = std::string("//LW\n"); + cp.code() = std::string("//LW\n"); // ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -partInit.code() += "etiss_uint32 load_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n"; -partInit.code() += "etiss_uint32 mem_val_0;\n"; -partInit.code() += "exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 4);\n"; -partInit.code() += "etiss_int32 res = (etiss_int32)(mem_val_0);\n"; -if ((rd % 32U) != 0U) { -partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_int32)(res);\n"; -} -partInit.code() += "if (exception) return exception;\n"; +cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n"; // ----------------------------------------------------------------------------- - - partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32); - partInit.getAffectedRegisters().add(reg_name[rd % 32], 32); - partInit.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -987,13 +1344,13 @@ partInit.code() += "if (exception) return exception;\n"; [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 imm = 0; +etiss_uint16 imm = 0; static BitArrayRange R_imm_0(31, 20); imm += R_imm_0.read(ba) << 0; @@ -1021,37 +1378,62 @@ static InstructionDefinition lbu_rd_rs1_imm ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 imm = 0; +etiss_uint16 imm = 0; static BitArrayRange R_imm_0(31, 20); imm += R_imm_0.read(ba) << 0; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//LBU\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint32 load_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n"; +cp.code() += "etiss_uint8 mem_val_0;\n"; +cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 1);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "etiss_uint8 res = (etiss_uint8)(mem_val_0);\n"; +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint32)(res);\n"; +} // conditional +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); - partInit.code() = std::string("//LBU\n"); + cp.code() = std::string("//LBU\n"); // ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -partInit.code() += "etiss_uint32 load_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n"; -partInit.code() += "etiss_uint8 mem_val_0;\n"; -partInit.code() += "exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 1);\n"; -partInit.code() += "etiss_uint8 res = (etiss_uint8)(mem_val_0);\n"; -if ((rd % 32U) != 0U) { -partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_uint32)(res);\n"; -} -partInit.code() += "if (exception) return exception;\n"; +cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n"; // ----------------------------------------------------------------------------- - - partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32); - partInit.getAffectedRegisters().add(reg_name[rd % 32], 32); - partInit.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -1059,13 +1441,13 @@ partInit.code() += "if (exception) return exception;\n"; [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 imm = 0; +etiss_uint16 imm = 0; static BitArrayRange R_imm_0(31, 20); imm += R_imm_0.read(ba) << 0; @@ -1093,37 +1475,62 @@ static InstructionDefinition lhu_rd_rs1_imm ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 imm = 0; +etiss_uint16 imm = 0; static BitArrayRange R_imm_0(31, 20); imm += R_imm_0.read(ba) << 0; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//LHU\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint32 load_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n"; +cp.code() += "etiss_uint16 mem_val_0;\n"; +cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 2);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "etiss_uint16 res = (etiss_uint16)(mem_val_0);\n"; +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint32)(res);\n"; +} // conditional +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); - partInit.code() = std::string("//LHU\n"); + cp.code() = std::string("//LHU\n"); // ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -partInit.code() += "etiss_uint32 load_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n"; -partInit.code() += "etiss_uint16 mem_val_0;\n"; -partInit.code() += "exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 2);\n"; -partInit.code() += "etiss_uint16 res = (etiss_uint16)(mem_val_0);\n"; -if ((rd % 32U) != 0U) { -partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_uint32)(res);\n"; -} -partInit.code() += "if (exception) return exception;\n"; +cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n"; // ----------------------------------------------------------------------------- - - partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32); - partInit.getAffectedRegisters().add(reg_name[rd % 32], 32); - partInit.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -1131,13 +1538,13 @@ partInit.code() += "if (exception) return exception;\n"; [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 imm = 0; +etiss_uint16 imm = 0; static BitArrayRange R_imm_0(31, 20); imm += R_imm_0.read(ba) << 0; @@ -1165,13 +1572,13 @@ static InstructionDefinition sb_imm_rs1_rs2 ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 imm = 0; +etiss_uint16 imm = 0; static BitArrayRange R_imm_0(11, 7); imm += R_imm_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; static BitArrayRange R_imm_5(31, 25); @@ -1179,22 +1586,47 @@ imm += R_imm_5.read(ba) << 5; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); - partInit.code() = std::string("//SB\n"); + cp.code() = std::string("//SB\n"); // ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -partInit.code() += "etiss_uint32 store_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n"; -partInit.code() += "etiss_uint8 mem_val_0 = (etiss_int8)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]);\n"; -partInit.code() += "exception |= (*(system->dwrite))(system->handle, cpu, store_address, (etiss_uint8*)&mem_val_0, 1);\n"; - -partInit.code() += "if (exception) return exception;\n"; +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint32 store_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n"; +cp.code() += "etiss_uint8 mem_val_0;\n"; +cp.code() += "mem_val_0 = (etiss_int8)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n"; +cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, store_address, (etiss_uint8*)&mem_val_0, 1);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; // ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); + + cp.code() = std::string("//SB\n"); - partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32); - partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 32); - partInit.getAffectedRegisters().add("instructionPointer", 32); +// ----------------------------------------------------------------------------- +cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n"; +// ----------------------------------------------------------------------------- + } return true; }, @@ -1202,13 +1634,13 @@ partInit.code() += "if (exception) return exception;\n"; [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 imm = 0; +etiss_uint16 imm = 0; static BitArrayRange R_imm_0(11, 7); imm += R_imm_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; static BitArrayRange R_imm_5(31, 25); @@ -1238,13 +1670,13 @@ static InstructionDefinition sh_imm_rs1_rs2 ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 imm = 0; +etiss_uint16 imm = 0; static BitArrayRange R_imm_0(11, 7); imm += R_imm_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; static BitArrayRange R_imm_5(31, 25); @@ -1252,22 +1684,47 @@ imm += R_imm_5.read(ba) << 5; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); - partInit.code() = std::string("//SH\n"); + cp.code() = std::string("//SH\n"); // ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -partInit.code() += "etiss_uint32 store_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n"; -partInit.code() += "etiss_uint16 mem_val_0 = (etiss_int16)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]);\n"; -partInit.code() += "exception |= (*(system->dwrite))(system->handle, cpu, store_address, (etiss_uint8*)&mem_val_0, 2);\n"; - -partInit.code() += "if (exception) return exception;\n"; +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint32 store_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n"; +cp.code() += "etiss_uint16 mem_val_0;\n"; +cp.code() += "mem_val_0 = (etiss_int16)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n"; +cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, store_address, (etiss_uint8*)&mem_val_0, 2);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; // ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); - partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32); - partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 32); - partInit.getAffectedRegisters().add("instructionPointer", 32); + cp.code() = std::string("//SH\n"); + +// ----------------------------------------------------------------------------- +cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n"; +// ----------------------------------------------------------------------------- + } return true; }, @@ -1275,13 +1732,13 @@ partInit.code() += "if (exception) return exception;\n"; [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 imm = 0; +etiss_uint16 imm = 0; static BitArrayRange R_imm_0(11, 7); imm += R_imm_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; static BitArrayRange R_imm_5(31, 25); @@ -1311,13 +1768,13 @@ static InstructionDefinition sw_imm_rs1_rs2 ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 imm = 0; +etiss_uint16 imm = 0; static BitArrayRange R_imm_0(11, 7); imm += R_imm_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; static BitArrayRange R_imm_5(31, 25); @@ -1325,22 +1782,47 @@ imm += R_imm_5.read(ba) << 5; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); - partInit.code() = std::string("//SW\n"); + cp.code() = std::string("//SW\n"); // ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -partInit.code() += "etiss_uint32 store_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n"; -partInit.code() += "etiss_uint32 mem_val_0 = (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]);\n"; -partInit.code() += "exception |= (*(system->dwrite))(system->handle, cpu, store_address, (etiss_uint8*)&mem_val_0, 4);\n"; - -partInit.code() += "if (exception) return exception;\n"; +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint32 store_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n"; +cp.code() += "etiss_uint32 mem_val_0;\n"; +cp.code() += "mem_val_0 = (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n"; +cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, store_address, (etiss_uint8*)&mem_val_0, 4);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; // ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); - partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32); - partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 32); - partInit.getAffectedRegisters().add("instructionPointer", 32); + cp.code() = std::string("//SW\n"); + +// ----------------------------------------------------------------------------- +cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n"; +// ----------------------------------------------------------------------------- + } return true; }, @@ -1348,13 +1830,13 @@ partInit.code() += "if (exception) return exception;\n"; [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 imm = 0; +etiss_uint16 imm = 0; static BitArrayRange R_imm_0(11, 7); imm += R_imm_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; static BitArrayRange R_imm_5(31, 25); @@ -1384,32 +1866,37 @@ static InstructionDefinition addi_rd_rs1_imm ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 imm = 0; +etiss_uint16 imm = 0; static BitArrayRange R_imm_0(31, 20); imm += R_imm_0.read(ba) << 0; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); - partInit.code() = std::string("//ADDI\n"); + cp.code() = std::string("//ADDI\n"); // ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -if ((rd % 32U) != 0U) { -partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n"; -} +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n"; +} // conditional +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; // ----------------------------------------------------------------------------- - - partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32); - partInit.getAffectedRegisters().add(reg_name[rd % 32], 32); - partInit.getAffectedRegisters().add("instructionPointer", 32); + cp.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -1417,13 +1904,13 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *( [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 imm = 0; +etiss_uint16 imm = 0; static BitArrayRange R_imm_0(31, 20); imm += R_imm_0.read(ba) << 0; @@ -1451,32 +1938,37 @@ static InstructionDefinition slti_rd_rs1_imm ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 imm = 0; +etiss_uint16 imm = 0; static BitArrayRange R_imm_0(31, 20); imm += R_imm_0.read(ba) << 0; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); - partInit.code() = std::string("//SLTI\n"); + cp.code() = std::string("//SLTI\n"); // ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -if ((rd % 32U) != 0U) { -partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]) < " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ")) ? (1U) : (0U);\n"; -} +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) < " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL)) ? (1ULL) : (0ULL);\n"; +} // conditional +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; // ----------------------------------------------------------------------------- - - partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32); - partInit.getAffectedRegisters().add(reg_name[rd % 32], 32); - partInit.getAffectedRegisters().add("instructionPointer", 32); + cp.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -1484,13 +1976,13 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (( [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 imm = 0; +etiss_uint16 imm = 0; static BitArrayRange R_imm_0(31, 20); imm += R_imm_0.read(ba) << 0; @@ -1518,32 +2010,37 @@ static InstructionDefinition sltiu_rd_rs1_imm ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 imm = 0; +etiss_uint16 imm = 0; static BitArrayRange R_imm_0(31, 20); imm += R_imm_0.read(ba) << 0; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); - partInit.code() = std::string("//SLTIU\n"); + cp.code() = std::string("//SLTIU\n"); // ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -if ((rd % 32U) != 0U) { -partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = ((*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] < " + std::to_string((etiss_uint32)((((etiss_int16)((imm) << (4)) >> (4))))) + ")) ? (1U) : (0U);\n"; -} +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = ((*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] < " + std::to_string((etiss_uint32)((((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))))) + "ULL)) ? (1ULL) : (0ULL);\n"; +} // conditional +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; // ----------------------------------------------------------------------------- - - partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32); - partInit.getAffectedRegisters().add(reg_name[rd % 32], 32); - partInit.getAffectedRegisters().add("instructionPointer", 32); + cp.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -1551,13 +2048,13 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (( [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 imm = 0; +etiss_uint16 imm = 0; static BitArrayRange R_imm_0(31, 20); imm += R_imm_0.read(ba) << 0; @@ -1585,32 +2082,37 @@ static InstructionDefinition xori_rd_rs1_imm ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 imm = 0; +etiss_uint16 imm = 0; static BitArrayRange R_imm_0(31, 20); imm += R_imm_0.read(ba) << 0; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); - partInit.code() = std::string("//XORI\n"); + cp.code() = std::string("//XORI\n"); // ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -if ((rd % 32U) != 0U) { -partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] ^ " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n"; -} +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] ^ " + std::to_string((etiss_uint32)((((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))))) + "ULL;\n"; +} // conditional +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; // ----------------------------------------------------------------------------- - - partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32); - partInit.getAffectedRegisters().add(reg_name[rd % 32], 32); - partInit.getAffectedRegisters().add("instructionPointer", 32); + cp.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -1618,13 +2120,13 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *( [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 imm = 0; +etiss_uint16 imm = 0; static BitArrayRange R_imm_0(31, 20); imm += R_imm_0.read(ba) << 0; @@ -1652,32 +2154,37 @@ static InstructionDefinition ori_rd_rs1_imm ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 imm = 0; +etiss_uint16 imm = 0; static BitArrayRange R_imm_0(31, 20); imm += R_imm_0.read(ba) << 0; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); - partInit.code() = std::string("//ORI\n"); + cp.code() = std::string("//ORI\n"); // ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -if ((rd % 32U) != 0U) { -partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] | " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n"; -} +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] | " + std::to_string((etiss_uint32)((((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))))) + "ULL;\n"; +} // conditional +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; // ----------------------------------------------------------------------------- - - partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32); - partInit.getAffectedRegisters().add(reg_name[rd % 32], 32); - partInit.getAffectedRegisters().add("instructionPointer", 32); + cp.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -1685,13 +2192,13 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *( [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 imm = 0; +etiss_uint16 imm = 0; static BitArrayRange R_imm_0(31, 20); imm += R_imm_0.read(ba) << 0; @@ -1719,32 +2226,37 @@ static InstructionDefinition andi_rd_rs1_imm ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 imm = 0; +etiss_uint16 imm = 0; static BitArrayRange R_imm_0(31, 20); imm += R_imm_0.read(ba) << 0; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); - partInit.code() = std::string("//ANDI\n"); + cp.code() = std::string("//ANDI\n"); // ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -if ((rd % 32U) != 0U) { -partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] & " + std::to_string(((etiss_int16)((imm) << (4)) >> (4))) + ";\n"; -} +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] & " + std::to_string((etiss_uint32)((((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))))) + "ULL;\n"; +} // conditional +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; // ----------------------------------------------------------------------------- - - partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32); - partInit.getAffectedRegisters().add(reg_name[rd % 32], 32); - partInit.getAffectedRegisters().add("instructionPointer", 32); + cp.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -1752,13 +2264,13 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *( [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 imm = 0; +etiss_uint16 imm = 0; static BitArrayRange R_imm_0(31, 20); imm += R_imm_0.read(ba) << 0; @@ -1786,32 +2298,37 @@ static InstructionDefinition slli_rd_rs1_shamt ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 shamt = 0; +etiss_uint8 shamt = 0; static BitArrayRange R_shamt_0(24, 20); shamt += R_shamt_0.read(ba) << 0; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); - partInit.code() = std::string("//SLLI\n"); + cp.code() = std::string("//SLLI\n"); // ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -if ((rd % 32U) != 0U) { -partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] << " + std::to_string(shamt) + ";\n"; -} +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] << " + std::to_string(shamt) + "ULL;\n"; +} // conditional +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; // ----------------------------------------------------------------------------- - - partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32); - partInit.getAffectedRegisters().add(reg_name[rd % 32], 32); - partInit.getAffectedRegisters().add("instructionPointer", 32); + cp.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -1819,13 +2336,13 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *( [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 shamt = 0; +etiss_uint8 shamt = 0; static BitArrayRange R_shamt_0(24, 20); shamt += R_shamt_0.read(ba) << 0; @@ -1853,32 +2370,37 @@ static InstructionDefinition srli_rd_rs1_shamt ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 shamt = 0; +etiss_uint8 shamt = 0; static BitArrayRange R_shamt_0(24, 20); shamt += R_shamt_0.read(ba) << 0; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); - partInit.code() = std::string("//SRLI\n"); + cp.code() = std::string("//SRLI\n"); // ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -if ((rd % 32U) != 0U) { -partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] >> " + std::to_string(shamt) + ";\n"; -} +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] >> " + std::to_string(shamt) + "ULL;\n"; +} // conditional +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; // ----------------------------------------------------------------------------- - - partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32); - partInit.getAffectedRegisters().add(reg_name[rd % 32], 32); - partInit.getAffectedRegisters().add("instructionPointer", 32); + cp.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -1886,13 +2408,13 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *( [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 shamt = 0; +etiss_uint8 shamt = 0; static BitArrayRange R_shamt_0(24, 20); shamt += R_shamt_0.read(ba) << 0; @@ -1920,32 +2442,37 @@ static InstructionDefinition srai_rd_rs1_shamt ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 shamt = 0; +etiss_uint8 shamt = 0; static BitArrayRange R_shamt_0(24, 20); shamt += R_shamt_0.read(ba) << 0; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); - partInit.code() = std::string("//SRAI\n"); + cp.code() = std::string("//SRAI\n"); // ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -if ((rd % 32U) != 0U) { -partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]) >> " + std::to_string(shamt) + ";\n"; -} +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) >> " + std::to_string(shamt) + "ULL;\n"; +} // conditional +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; // ----------------------------------------------------------------------------- - - partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32); - partInit.getAffectedRegisters().add(reg_name[rd % 32], 32); - partInit.getAffectedRegisters().add("instructionPointer", 32); + cp.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -1953,13 +2480,13 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (e [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 shamt = 0; +etiss_uint8 shamt = 0; static BitArrayRange R_shamt_0(24, 20); shamt += R_shamt_0.read(ba) << 0; @@ -1987,33 +2514,37 @@ static InstructionDefinition add_rd_rs1_rs2 ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); - partInit.code() = std::string("//ADD\n"); + cp.code() = std::string("//ADD\n"); // ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -if ((rd % 32U) != 0U) { -partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] + *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "];\n"; -} +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n"; +} // conditional +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; // ----------------------------------------------------------------------------- - - partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32); - partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 32); - partInit.getAffectedRegisters().add(reg_name[rd % 32], 32); - partInit.getAffectedRegisters().add("instructionPointer", 32); + cp.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -2021,13 +2552,13 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *( [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; @@ -2055,33 +2586,37 @@ static InstructionDefinition sub_rd_rs1_rs2 ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); - partInit.code() = std::string("//SUB\n"); + cp.code() = std::string("//SUB\n"); // ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -if ((rd % 32U) != 0U) { -partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] - *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "];\n"; -} +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] - *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n"; +} // conditional +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; // ----------------------------------------------------------------------------- - - partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32); - partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 32); - partInit.getAffectedRegisters().add(reg_name[rd % 32], 32); - partInit.getAffectedRegisters().add("instructionPointer", 32); + cp.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -2089,13 +2624,13 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *( [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; @@ -2123,33 +2658,37 @@ static InstructionDefinition sll_rd_rs1_rs2 ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); - partInit.code() = std::string("//SLL\n"); + cp.code() = std::string("//SLL\n"); // ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -if ((rd % 32U) != 0U) { -partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] << (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "] & 31U);\n"; -} +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] << (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL] & 31ULL);\n"; +} // conditional +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; // ----------------------------------------------------------------------------- - - partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32); - partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 32); - partInit.getAffectedRegisters().add(reg_name[rd % 32], 32); - partInit.getAffectedRegisters().add("instructionPointer", 32); + cp.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -2157,13 +2696,13 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *( [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; @@ -2191,33 +2730,37 @@ static InstructionDefinition slt_rd_rs1_rs2 ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); - partInit.code() = std::string("//SLT\n"); + cp.code() = std::string("//SLT\n"); // ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -if ((rd % 32U) != 0U) { -partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = ((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]) < (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "])) ? (1U) : (0U);\n"; -} +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = ((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) < (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL])) ? (1ULL) : (0ULL);\n"; +} // conditional +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; // ----------------------------------------------------------------------------- - - partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32); - partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 32); - partInit.getAffectedRegisters().add(reg_name[rd % 32], 32); - partInit.getAffectedRegisters().add("instructionPointer", 32); + cp.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -2225,13 +2768,13 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (( [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; @@ -2259,33 +2802,37 @@ static InstructionDefinition sltu_rd_rs1_rs2 ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); - partInit.code() = std::string("//SLTU\n"); + cp.code() = std::string("//SLTU\n"); // ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -if ((rd % 32U) != 0U) { -partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = ((etiss_uint32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]) < (etiss_uint32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "])) ? (1U) : (0U);\n"; -} +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] < *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) ? (1ULL) : (0ULL);\n"; +} // conditional +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; // ----------------------------------------------------------------------------- - - partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32); - partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 32); - partInit.getAffectedRegisters().add(reg_name[rd % 32], 32); - partInit.getAffectedRegisters().add("instructionPointer", 32); + cp.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -2293,13 +2840,13 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (( [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; @@ -2327,33 +2874,37 @@ static InstructionDefinition xor_rd_rs1_rs2 ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); - partInit.code() = std::string("//XOR\n"); + cp.code() = std::string("//XOR\n"); // ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -if ((rd % 32U) != 0U) { -partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] ^ *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "];\n"; -} +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] ^ *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n"; +} // conditional +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; // ----------------------------------------------------------------------------- - - partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32); - partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 32); - partInit.getAffectedRegisters().add(reg_name[rd % 32], 32); - partInit.getAffectedRegisters().add("instructionPointer", 32); + cp.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -2361,13 +2912,13 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *( [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; @@ -2395,33 +2946,37 @@ static InstructionDefinition srl_rd_rs1_rs2 ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); - partInit.code() = std::string("//SRL\n"); + cp.code() = std::string("//SRL\n"); // ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -if ((rd % 32U) != 0U) { -partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] >> (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "] & 31U);\n"; -} +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] >> (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL] & 31ULL);\n"; +} // conditional +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; // ----------------------------------------------------------------------------- - - partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32); - partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 32); - partInit.getAffectedRegisters().add(reg_name[rd % 32], 32); - partInit.getAffectedRegisters().add("instructionPointer", 32); + cp.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -2429,13 +2984,13 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *( [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; @@ -2463,33 +3018,37 @@ static InstructionDefinition sra_rd_rs1_rs2 ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); - partInit.code() = std::string("//SRA\n"); + cp.code() = std::string("//SRA\n"); // ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -if ((rd % 32U) != 0U) { -partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]) >> (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "] & 31U);\n"; -} +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) >> (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL] & 31ULL);\n"; +} // conditional +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; // ----------------------------------------------------------------------------- - - partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32); - partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 32); - partInit.getAffectedRegisters().add(reg_name[rd % 32], 32); - partInit.getAffectedRegisters().add("instructionPointer", 32); + cp.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -2497,13 +3056,13 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (e [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; @@ -2531,33 +3090,37 @@ static InstructionDefinition or_rd_rs1_rs2 ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); - partInit.code() = std::string("//OR\n"); + cp.code() = std::string("//OR\n"); // ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -if ((rd % 32U) != 0U) { -partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] | *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "];\n"; -} +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] | *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n"; +} // conditional +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; // ----------------------------------------------------------------------------- - - partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32); - partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 32); - partInit.getAffectedRegisters().add(reg_name[rd % 32], 32); - partInit.getAffectedRegisters().add("instructionPointer", 32); + cp.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -2565,13 +3128,13 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *( [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; @@ -2599,33 +3162,37 @@ static InstructionDefinition and_rd_rs1_rs2 ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); - partInit.code() = std::string("//AND\n"); + cp.code() = std::string("//AND\n"); // ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -if ((rd % 32U) != 0U) { -partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] & *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "];\n"; -} +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] & *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n"; +} // conditional +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; // ----------------------------------------------------------------------------- - - partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32); - partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 32); - partInit.getAffectedRegisters().add(reg_name[rd % 32], 32); - partInit.getAffectedRegisters().add("instructionPointer", 32); + cp.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -2633,13 +3200,13 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *( [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; @@ -2667,34 +3234,41 @@ static InstructionDefinition fence_rd_rs1_succ_pred_fm ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 succ = 0; +etiss_uint8 succ = 0; static BitArrayRange R_succ_0(23, 20); succ += R_succ_0.read(ba) << 0; -etiss_uint32 pred = 0; +etiss_uint8 pred = 0; static BitArrayRange R_pred_0(27, 24); pred += R_pred_0.read(ba) << 0; -etiss_uint32 fm = 0; +etiss_uint8 fm = 0; static BitArrayRange R_fm_0(31, 28); fm += R_fm_0.read(ba) << 0; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); - partInit.code() = std::string("//FENCE\n"); + cp.code() = std::string("//FENCE\n"); // ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -partInit.code() += "((RV32IMACFD*)cpu)->FENCE[" + std::to_string(0) + "] = " + std::to_string(pred << 4U | succ) + ";\n"; +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "((RV32IMACFD*)cpu)->FENCE[0ULL] = " + std::to_string(pred << 4ULL | succ) + "ULL;\n"; +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; // ----------------------------------------------------------------------------- - - partInit.getAffectedRegisters().add("instructionPointer", 32); + cp.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -2702,19 +3276,19 @@ partInit.code() += "((RV32IMACFD*)cpu)->FENCE[" + std::to_string(0) + "] = " + s [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 succ = 0; +etiss_uint8 succ = 0; static BitArrayRange R_succ_0(23, 20); succ += R_succ_0.read(ba) << 0; -etiss_uint32 pred = 0; +etiss_uint8 pred = 0; static BitArrayRange R_pred_0(27, 24); pred += R_pred_0.read(ba) << 0; -etiss_uint32 fm = 0; +etiss_uint8 fm = 0; static BitArrayRange R_fm_0(31, 28); fm += R_fm_0.read(ba) << 0; @@ -2727,193 +3301,3 @@ ss << "fence" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std: return ss.str(); } ); - -// ECALL ----------------------------------------------------------------------- -static InstructionDefinition ecall_ ( - ISA32_RV32IMACFD, - "ecall", - (uint32_t) 0x000073, - (uint32_t) 0xffffffff, - [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) - { - -// ----------------------------------------------------------------------------- - -// ----------------------------------------------------------------------------- - -// ----------------------------------------------------------------------------- - -// ----------------------------------------------------------------------------- - - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); - - partInit.code() = std::string("//ECALL\n"); - -// ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -partInit.code() += "exception = ETISS_RETURNCODE_SYSCALL;\n"; -partInit.code() += "return exception;\n"; -// ----------------------------------------------------------------------------- - - partInit.getAffectedRegisters().add("instructionPointer", 32); - - return true; - }, - 0, - [] (BitArray & ba, Instruction & instr) - { -// ----------------------------------------------------------------------------- - -// ----------------------------------------------------------------------------- - - std::stringstream ss; -// ----------------------------------------------------------------------------- -ss << "ecall" << " # " << ba << (" []"); -// ----------------------------------------------------------------------------- - return ss.str(); - } -); - -// EBREAK ---------------------------------------------------------------------- -static InstructionDefinition ebreak_ ( - ISA32_RV32IMACFD, - "ebreak", - (uint32_t) 0x100073, - (uint32_t) 0xffffffff, - [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) - { - -// ----------------------------------------------------------------------------- - -// ----------------------------------------------------------------------------- - -// ----------------------------------------------------------------------------- - -// ----------------------------------------------------------------------------- - - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); - - partInit.code() = std::string("//EBREAK\n"); - -// ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -partInit.code() += "exception = ETISS_RETURNCODE_CPUFINISHED;\n"; -partInit.code() += "return exception;\n"; -// ----------------------------------------------------------------------------- - - partInit.getAffectedRegisters().add("instructionPointer", 32); - - return true; - }, - 0, - [] (BitArray & ba, Instruction & instr) - { -// ----------------------------------------------------------------------------- - -// ----------------------------------------------------------------------------- - - std::stringstream ss; -// ----------------------------------------------------------------------------- -ss << "ebreak" << " # " << ba << (" []"); -// ----------------------------------------------------------------------------- - return ss.str(); - } -); - -// WFI ------------------------------------------------------------------------- -static InstructionDefinition wfi_ ( - ISA32_RV32IMACFD, - "wfi", - (uint32_t) 0x10500073, - (uint32_t) 0xffffffff, - [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) - { - -// ----------------------------------------------------------------------------- - -// ----------------------------------------------------------------------------- - -// ----------------------------------------------------------------------------- - -// ----------------------------------------------------------------------------- - - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); - - partInit.code() = std::string("//WFI\n"); - -// ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -partInit.code() += "exception = ETISS_RETURNCODE_CPUFINISHED;\n"; -partInit.code() += "if (exception) return exception;\n"; -// ----------------------------------------------------------------------------- - - partInit.getAffectedRegisters().add("instructionPointer", 32); - - return true; - }, - 0, - [] (BitArray & ba, Instruction & instr) - { -// ----------------------------------------------------------------------------- - -// ----------------------------------------------------------------------------- - - std::stringstream ss; -// ----------------------------------------------------------------------------- -ss << "wfi" << " # " << ba << (" []"); -// ----------------------------------------------------------------------------- - return ss.str(); - } -); - -// DRET ------------------------------------------------------------------------ -static InstructionDefinition dret_ ( - ISA32_RV32IMACFD, - "dret", - (uint32_t) 0x7b200073, - (uint32_t) 0xffffffff, - [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) - { - -// ----------------------------------------------------------------------------- - -// ----------------------------------------------------------------------------- - -// ----------------------------------------------------------------------------- - -// ----------------------------------------------------------------------------- - - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); - - partInit.code() = std::string("//DRET\n"); - -// ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -partInit.code() += "if (((RV32IMACFD*)cpu)->PRIV < 4U) {\n"; -partInit.code() += "exception = ETISS_RETURNCODE_ILLEGALINSTRUCTION;\n"; -partInit.code() += "}\n"; -partInit.code() += " else {\n"; -partInit.code() += "cpu->instructionPointer = ((RV32IMACFD*)cpu)->DPC;\n"; -partInit.code() += "((RV32IMACFD*)cpu)->PRIV = (((RV32IMACFD*)cpu)->PRIV & 3U) & 0x7;\n"; -partInit.code() += "}\n"; -partInit.code() += "if (exception) return exception;\n"; -// ----------------------------------------------------------------------------- - - partInit.getAffectedRegisters().add("instructionPointer", 32); - - return true; - }, - 0, - [] (BitArray & ba, Instruction & instr) - { -// ----------------------------------------------------------------------------- - -// ----------------------------------------------------------------------------- - - std::stringstream ss; -// ----------------------------------------------------------------------------- -ss << "dret" << " # " << ba << (" []"); -// ----------------------------------------------------------------------------- - return ss.str(); - } -); diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32MInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32MInstr.cpp index eec12666b1..a432f45b19 100644 --- a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32MInstr.cpp +++ b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32MInstr.cpp @@ -1,13 +1,11 @@ /** - * Generated on Mon, 09 May 2022 21:04:41 +0200. + * Generated on Tue, 28 Nov 2023 09:45:19 +0100. * * This file contains the instruction behavior models of the RV32M * instruction set for the RV32IMACFD core architecture. */ #include "RV32IMACFDArch.h" - -#define ETISS_ARCH_STATIC_FN_ONLY #include "RV32IMACFDFuncs.h" using namespace etiss; @@ -28,34 +26,46 @@ static InstructionDefinition mul_rd_rs1_rs2 ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); - - partInit.code() = std::string("//MUL\n"); - -// ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -if ((rd % 32U) != 0U) { -partInit.code() += "etiss_int64 res = (etiss_int64)((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "])) * (etiss_int64)((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]));\n"; -partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_uint32)(res);\n"; -} -// ----------------------------------------------------------------------------- - - partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32); - partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 32); - partInit.getAffectedRegisters().add(reg_name[rd % 32], 32); - partInit.getAffectedRegisters().add("instructionPointer", 32); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//MUL\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +if ((rd % 32ULL) != 0ULL) { // conditional +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_int64 res = (etiss_int64)((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL])) * (etiss_int64)((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]));\n"; +cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint32)(res);\n"; +cp.code() += "} // block\n"; +} // block +} // conditional +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -63,13 +73,13 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (e [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; @@ -97,34 +107,46 @@ static InstructionDefinition mulh_rd_rs1_rs2 ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); - - partInit.code() = std::string("//MULH\n"); - -// ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -if ((rd % 32U) != 0U) { -partInit.code() += "etiss_int64 res = (etiss_int64)((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "])) * (etiss_int64)((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]));\n"; -partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_uint32)((res >> 32UL));\n"; -} -// ----------------------------------------------------------------------------- - - partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32); - partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 32); - partInit.getAffectedRegisters().add(reg_name[rd % 32], 32); - partInit.getAffectedRegisters().add("instructionPointer", 32); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//MULH\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +if ((rd % 32ULL) != 0ULL) { // conditional +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_int64 res = (etiss_int64)((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL])) * (etiss_int64)((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]));\n"; +cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint32)((res >> 32ULL));\n"; +cp.code() += "} // block\n"; +} // block +} // conditional +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -132,13 +154,13 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (e [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; @@ -166,34 +188,46 @@ static InstructionDefinition mulhsu_rd_rs1_rs2 ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); - - partInit.code() = std::string("//MULHSU\n"); - -// ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -if ((rd % 32U) != 0U) { -partInit.code() += "etiss_int64 res = (etiss_int64)((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "])) * (etiss_uint64)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]);\n"; -partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_uint32)((res >> 32UL));\n"; -} -// ----------------------------------------------------------------------------- - - partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32); - partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 32); - partInit.getAffectedRegisters().add(reg_name[rd % 32], 32); - partInit.getAffectedRegisters().add("instructionPointer", 32); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//MULHSU\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +if ((rd % 32ULL) != 0ULL) { // conditional +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_int64 res = (etiss_int64)((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL])) * (etiss_uint64)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n"; +cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint32)((res >> 32ULL));\n"; +cp.code() += "} // block\n"; +} // block +} // conditional +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -201,13 +235,13 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (e [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; @@ -235,34 +269,46 @@ static InstructionDefinition mulhu_rd_rs1_rs2 ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); - - partInit.code() = std::string("//MULHU\n"); - -// ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -if ((rd % 32U) != 0U) { -partInit.code() += "etiss_uint64 res = (etiss_uint64)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]) * (etiss_uint64)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]);\n"; -partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_uint32)((res >> 32UL));\n"; -} -// ----------------------------------------------------------------------------- - - partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32); - partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 32); - partInit.getAffectedRegisters().add(reg_name[rd % 32], 32); - partInit.getAffectedRegisters().add("instructionPointer", 32); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//MULHU\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +if ((rd % 32ULL) != 0ULL) { // conditional +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint64 res = (etiss_uint64)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) * (etiss_uint64)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n"; +cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint32)((res >> 32ULL));\n"; +cp.code() += "} // block\n"; +} // block +} // conditional +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -270,13 +316,13 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (e [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; @@ -304,44 +350,60 @@ static InstructionDefinition div_rd_rs1_rs2 ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); - - partInit.code() = std::string("//DIV\n"); - -// ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -if ((rd % 32U) != 0U) { -partInit.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "] != 0U) {\n"; -etiss_uint32 MMIN = 2147483648U; -partInit.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] == " + std::to_string(MMIN) + " && (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]) == -1U) {\n"; -partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = " + std::to_string(MMIN) + ";\n"; -partInit.code() += "}\n"; -partInit.code() += " else {\n"; -partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]) / (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]);\n"; -partInit.code() += "}\n"; -partInit.code() += "}\n"; -partInit.code() += " else {\n"; -partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = -1U;\n"; -partInit.code() += "}\n"; -} -// ----------------------------------------------------------------------------- - - partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32); - partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 32); - partInit.getAffectedRegisters().add(reg_name[rd % 32], 32); - partInit.getAffectedRegisters().add("instructionPointer", 32); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//DIV\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +if ((rd % 32ULL) != 0ULL) { // conditional +{ // block +cp.code() += "{ // block\n"; +cp.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL] != 0ULL) { // conditional\n"; +{ // block +cp.code() += "{ // block\n"; +etiss_uint32 MMIN = 2147483648ULL; +cp.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] == " + std::to_string(MMIN) + "ULL && (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) == -1LL) { // conditional\n"; +cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = " + std::to_string(MMIN) + "ULL;\n"; +cp.code() += "} // conditional\n"; +cp.code() += "else { // conditional\n"; +cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) / (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n"; +cp.code() += "} // conditional\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "} // conditional\n"; +cp.code() += "else { // conditional\n"; +cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = -1LL;\n"; +cp.code() += "} // conditional\n"; +cp.code() += "} // block\n"; +} // block +} // conditional +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -349,13 +411,13 @@ partInit.code() += "}\n"; [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; @@ -383,38 +445,50 @@ static InstructionDefinition divu_rd_rs1_rs2 ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); - - partInit.code() = std::string("//DIVU\n"); - -// ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -if ((rd % 32U) != 0U) { -partInit.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "] != 0U) {\n"; -partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] / *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "];\n"; -partInit.code() += "}\n"; -partInit.code() += " else {\n"; -partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = -1U;\n"; -partInit.code() += "}\n"; -} -// ----------------------------------------------------------------------------- - - partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32); - partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 32); - partInit.getAffectedRegisters().add(reg_name[rd % 32], 32); - partInit.getAffectedRegisters().add("instructionPointer", 32); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//DIVU\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +if ((rd % 32ULL) != 0ULL) { // conditional +{ // block +cp.code() += "{ // block\n"; +cp.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL] != 0ULL) { // conditional\n"; +cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] / *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n"; +cp.code() += "} // conditional\n"; +cp.code() += "else { // conditional\n"; +cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = -1LL;\n"; +cp.code() += "} // conditional\n"; +cp.code() += "} // block\n"; +} // block +} // conditional +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -422,13 +496,13 @@ partInit.code() += "}\n"; [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; @@ -456,44 +530,60 @@ static InstructionDefinition rem_rd_rs1_rs2 ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); - - partInit.code() = std::string("//REM\n"); - -// ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -if ((rd % 32U) != 0U) { -partInit.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "] != 0U) {\n"; -etiss_uint32 MMIN = 2147483648U; -partInit.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] == " + std::to_string(MMIN) + " && (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]) == -1U) {\n"; -partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = 0U;\n"; -partInit.code() += "}\n"; -partInit.code() += " else {\n"; -partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "]) % (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]);\n"; -partInit.code() += "}\n"; -partInit.code() += "}\n"; -partInit.code() += " else {\n"; -partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n"; -partInit.code() += "}\n"; -} -// ----------------------------------------------------------------------------- - - partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32); - partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 32); - partInit.getAffectedRegisters().add(reg_name[rd % 32], 32); - partInit.getAffectedRegisters().add("instructionPointer", 32); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//REM\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +if ((rd % 32ULL) != 0ULL) { // conditional +{ // block +cp.code() += "{ // block\n"; +cp.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL] != 0ULL) { // conditional\n"; +{ // block +cp.code() += "{ // block\n"; +etiss_uint32 MMIN = 2147483648ULL; +cp.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] == " + std::to_string(MMIN) + "ULL && (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) == -1LL) { // conditional\n"; +cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = 0ULL;\n"; +cp.code() += "} // conditional\n"; +cp.code() += "else { // conditional\n"; +cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) % (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n"; +cp.code() += "} // conditional\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "} // conditional\n"; +cp.code() += "else { // conditional\n"; +cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n"; +cp.code() += "} // conditional\n"; +cp.code() += "} // block\n"; +} // block +} // conditional +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -501,13 +591,13 @@ partInit.code() += "}\n"; [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; @@ -535,38 +625,50 @@ static InstructionDefinition remu_rd_rs1_rs2 ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); - - partInit.code() = std::string("//REMU\n"); - -// ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -if ((rd % 32U) != 0U) { -partInit.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "] != 0U) {\n"; -partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "] % *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "];\n"; -partInit.code() += "}\n"; -partInit.code() += " else {\n"; -partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n"; -partInit.code() += "}\n"; -} -// ----------------------------------------------------------------------------- - - partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32); - partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 32); - partInit.getAffectedRegisters().add(reg_name[rd % 32], 32); - partInit.getAffectedRegisters().add("instructionPointer", 32); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//REMU\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +if ((rd % 32ULL) != 0ULL) { // conditional +{ // block +cp.code() += "{ // block\n"; +cp.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL] != 0ULL) { // conditional\n"; +cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] % *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n"; +cp.code() += "} // conditional\n"; +cp.code() += "else { // conditional\n"; +cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n"; +cp.code() += "} // conditional\n"; +cp.code() += "} // block\n"; +} // block +} // conditional +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -574,13 +676,13 @@ partInit.code() += "}\n"; [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_ZicsrInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_ZicsrInstr.cpp deleted file mode 100644 index f81f0e19bb..0000000000 --- a/ArchImpl/RV32IMACFD/RV32IMACFD_ZicsrInstr.cpp +++ /dev/null @@ -1,15 +0,0 @@ -/** - * Generated on Thu, 24 Feb 2022 17:15:20 +0100. - * - * This file contains the instruction behavior models of the Zicsr - * instruction set for the RV32IMACFD core architecture. - */ - -#include "RV32IMACFDArch.h" - -#define ETISS_ARCH_STATIC_FN_ONLY -#include "RV32IMACFDFuncs.h" - -using namespace etiss; -using namespace etiss::instr; - diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_ZifenceiInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_ZifenceiInstr.cpp index 299183b2fa..7184a81933 100644 --- a/ArchImpl/RV32IMACFD/RV32IMACFD_ZifenceiInstr.cpp +++ b/ArchImpl/RV32IMACFD/RV32IMACFD_ZifenceiInstr.cpp @@ -1,13 +1,11 @@ /** - * Generated on Tue, 01 Mar 2022 12:43:46 +0100. + * Generated on Tue, 28 Nov 2023 09:45:19 +0100. * * This file contains the instruction behavior models of the Zifencei * instruction set for the RV32IMACFD core architecture. */ #include "RV32IMACFDArch.h" - -#define ETISS_ARCH_STATIC_FN_ONLY #include "RV32IMACFDFuncs.h" using namespace etiss; @@ -28,30 +26,45 @@ static InstructionDefinition fence_i_rd_rs1_imm ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 imm = 0; +etiss_uint16 imm = 0; static BitArrayRange R_imm_0(31, 20); imm += R_imm_0.read(ba) << 0; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); - partInit.code() = std::string("//FENCE_I\n"); + cp.code() = std::string("//FENCE_I\n"); // ----------------------------------------------------------------------------- -partInit.code() += "exception = ETISS_RETURNCODE_RELOADBLOCKS;\n"; -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -partInit.code() += "((RV32IMACFD*)cpu)->FENCE[" + std::to_string(1) + "] = " + std::to_string(imm) + ";\n"; -partInit.code() += "return exception;\n"; +cp.code() += "cpu->exception = ETISS_RETURNCODE_RELOADBLOCKS;\n"; +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "((RV32IMACFD*)cpu)->FENCE[1ULL] = " + std::to_string(imm) + "ULL;\n"; +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; // ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); - partInit.getAffectedRegisters().add("instructionPointer", 32); + cp.code() = std::string("//FENCE_I\n"); + +// ----------------------------------------------------------------------------- +cp.code() += "return cpu->exception;\n"; +// ----------------------------------------------------------------------------- + } return true; }, @@ -59,13 +72,13 @@ partInit.code() += "return exception;\n"; [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 imm = 0; +etiss_uint16 imm = 0; static BitArrayRange R_imm_0(31, 20); imm += R_imm_0.read(ba) << 0; diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_csrInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_csrInstr.cpp index 5da43a3bca..6353420428 100644 --- a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_csrInstr.cpp +++ b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_csrInstr.cpp @@ -1,13 +1,11 @@ /** - * Generated on Mon, 09 May 2022 21:04:41 +0200. + * Generated on Tue, 28 Nov 2023 09:45:19 +0100. * * This file contains the instruction behavior models of the tum_csr * instruction set for the RV32IMACFD core architecture. */ #include "RV32IMACFDArch.h" - -#define ETISS_ARCH_STATIC_FN_ONLY #include "RV32IMACFDFuncs.h" using namespace etiss; @@ -28,37 +26,55 @@ static InstructionDefinition csrrw_rd_rs1_csr ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 csr = 0; +etiss_uint16 csr = 0; static BitArrayRange R_csr_0(31, 20); csr += R_csr_0.read(ba) << 0; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); - - partInit.code() = std::string("//CSRRW\n"); - -// ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -partInit.code() += "etiss_uint32 xrs1 = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n"; -if ((rd % 32U) != 0U) { -partInit.code() += "etiss_uint32 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + ");\n"; -partInit.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + ", xrs1);"; -partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = xrd;\n"; -} else { -partInit.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + ", xrs1);"; -} -// ----------------------------------------------------------------------------- - - partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32); - partInit.getAffectedRegisters().add(reg_name[rd % 32], 32); - partInit.getAffectedRegisters().add("instructionPointer", 32); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//CSRRW\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint32 xrs1 = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n"; +if ((rd % 32ULL) != 0ULL) { // conditional +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint32 xrd = RV32IMACFD_csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL);\n"; +cp.code() += "RV32IMACFD_csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL, xrs1);\n"; +cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = xrd;\n"; +cp.code() += "} // block\n"; +} // block +} // conditional +else { // conditional +{ // block +cp.code() += "{ // block\n"; +cp.code() += "RV32IMACFD_csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL, xrs1);\n"; +cp.code() += "} // block\n"; +} // block +} // conditional +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -66,13 +82,13 @@ partInit.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(c [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 csr = 0; +etiss_uint16 csr = 0; static BitArrayRange R_csr_0(31, 20); csr += R_csr_0.read(ba) << 0; @@ -100,37 +116,46 @@ static InstructionDefinition csrrs_rd_rs1_csr ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 csr = 0; +etiss_uint16 csr = 0; static BitArrayRange R_csr_0(31, 20); csr += R_csr_0.read(ba) << 0; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); - - partInit.code() = std::string("//CSRRS\n"); - -// ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -partInit.code() += "etiss_uint32 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + ");\n"; -partInit.code() += "etiss_uint32 xrs1 = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n"; -if (rs1 != 0U) { -partInit.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + ", xrd | xrs1);"; -} -if ((rd % 32U) != 0U) { -partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = xrd;\n"; -} -// ----------------------------------------------------------------------------- - - partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32); - partInit.getAffectedRegisters().add(reg_name[rd % 32], 32); - partInit.getAffectedRegisters().add("instructionPointer", 32); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//CSRRS\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint32 xrd = RV32IMACFD_csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL);\n"; +cp.code() += "etiss_uint32 xrs1 = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n"; +if (rs1 != 0ULL) { // conditional +cp.code() += "RV32IMACFD_csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL, xrd | xrs1);\n"; +} // conditional +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = xrd;\n"; +} // conditional +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -138,13 +163,13 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = xr [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 csr = 0; +etiss_uint16 csr = 0; static BitArrayRange R_csr_0(31, 20); csr += R_csr_0.read(ba) << 0; @@ -172,37 +197,46 @@ static InstructionDefinition csrrc_rd_rs1_csr ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 csr = 0; +etiss_uint16 csr = 0; static BitArrayRange R_csr_0(31, 20); csr += R_csr_0.read(ba) << 0; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); - - partInit.code() = std::string("//CSRRC\n"); - -// ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -partInit.code() += "etiss_uint32 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + ");\n"; -partInit.code() += "etiss_uint32 xrs1 = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n"; -if (rs1 != 0U) { -partInit.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + ", xrd & ~(xrs1));"; -} -if ((rd % 32U) != 0U) { -partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = xrd;\n"; -} -// ----------------------------------------------------------------------------- - - partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32); - partInit.getAffectedRegisters().add(reg_name[rd % 32], 32); - partInit.getAffectedRegisters().add("instructionPointer", 32); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//CSRRC\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint32 xrd = RV32IMACFD_csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL);\n"; +cp.code() += "etiss_uint32 xrs1 = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n"; +if (rs1 != 0ULL) { // conditional +cp.code() += "RV32IMACFD_csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL, xrd & ~(xrs1));\n"; +} // conditional +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = xrd;\n"; +} // conditional +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -210,13 +244,13 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = xr [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 csr = 0; +etiss_uint16 csr = 0; static BitArrayRange R_csr_0(31, 20); csr += R_csr_0.read(ba) << 0; @@ -244,33 +278,43 @@ static InstructionDefinition csrrwi_rd_zimm_csr ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 zimm = 0; +etiss_uint8 zimm = 0; static BitArrayRange R_zimm_0(19, 15); zimm += R_zimm_0.read(ba) << 0; -etiss_uint32 csr = 0; +etiss_uint16 csr = 0; static BitArrayRange R_csr_0(31, 20); csr += R_csr_0.read(ba) << 0; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); - - partInit.code() = std::string("//CSRRWI\n"); - -// ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -partInit.code() += "etiss_uint32 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + ");\n"; -partInit.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + ", " + std::to_string((etiss_uint32)(zimm)) + ");"; -if ((rd % 32U) != 0U) { -partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = xrd;\n"; -} -// ----------------------------------------------------------------------------- - - partInit.getAffectedRegisters().add(reg_name[rd % 32], 32); - partInit.getAffectedRegisters().add("instructionPointer", 32); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//CSRRWI\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint32 xrd = RV32IMACFD_csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL);\n"; +cp.code() += "RV32IMACFD_csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL, " + std::to_string((etiss_uint32)(zimm)) + "ULL);\n"; +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = xrd;\n"; +} // conditional +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -278,13 +322,13 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = xr [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 zimm = 0; +etiss_uint8 zimm = 0; static BitArrayRange R_zimm_0(19, 15); zimm += R_zimm_0.read(ba) << 0; -etiss_uint32 csr = 0; +etiss_uint16 csr = 0; static BitArrayRange R_csr_0(31, 20); csr += R_csr_0.read(ba) << 0; @@ -312,35 +356,45 @@ static InstructionDefinition csrrsi_rd_zimm_csr ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 zimm = 0; +etiss_uint8 zimm = 0; static BitArrayRange R_zimm_0(19, 15); zimm += R_zimm_0.read(ba) << 0; -etiss_uint32 csr = 0; +etiss_uint16 csr = 0; static BitArrayRange R_csr_0(31, 20); csr += R_csr_0.read(ba) << 0; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); - - partInit.code() = std::string("//CSRRSI\n"); - -// ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -partInit.code() += "etiss_uint32 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + ");\n"; -if (zimm != 0U) { -partInit.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + ", xrd | " + std::to_string((etiss_uint32)(zimm)) + ");"; -} -if ((rd % 32U) != 0U) { -partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = xrd;\n"; -} -// ----------------------------------------------------------------------------- - - partInit.getAffectedRegisters().add(reg_name[rd % 32], 32); - partInit.getAffectedRegisters().add("instructionPointer", 32); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//CSRRSI\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint32 xrd = RV32IMACFD_csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL);\n"; +if (zimm != 0ULL) { // conditional +cp.code() += "RV32IMACFD_csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL, xrd | " + std::to_string((etiss_uint32)(zimm)) + "ULL);\n"; +} // conditional +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = xrd;\n"; +} // conditional +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -348,13 +402,13 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = xr [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 zimm = 0; +etiss_uint8 zimm = 0; static BitArrayRange R_zimm_0(19, 15); zimm += R_zimm_0.read(ba) << 0; -etiss_uint32 csr = 0; +etiss_uint16 csr = 0; static BitArrayRange R_csr_0(31, 20); csr += R_csr_0.read(ba) << 0; @@ -382,35 +436,45 @@ static InstructionDefinition csrrci_rd_zimm_csr ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 zimm = 0; +etiss_uint8 zimm = 0; static BitArrayRange R_zimm_0(19, 15); zimm += R_zimm_0.read(ba) << 0; -etiss_uint32 csr = 0; +etiss_uint16 csr = 0; static BitArrayRange R_csr_0(31, 20); csr += R_csr_0.read(ba) << 0; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); - - partInit.code() = std::string("//CSRRCI\n"); - -// ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -partInit.code() += "etiss_uint32 xrd = csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + ");\n"; -if (zimm != 0U) { -partInit.code() += "csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + ", xrd & " + std::to_string(~(((etiss_uint32)(zimm)))) + ");"; -} -if ((rd % 32U) != 0U) { -partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = xrd;\n"; -} -// ----------------------------------------------------------------------------- - - partInit.getAffectedRegisters().add(reg_name[rd % 32], 32); - partInit.getAffectedRegisters().add("instructionPointer", 32); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//CSRRCI\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint32 xrd = RV32IMACFD_csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL);\n"; +if (zimm != 0ULL) { // conditional +cp.code() += "RV32IMACFD_csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL, xrd & " + std::to_string(~(((etiss_uint32)(zimm)))) + "ULL);\n"; +} // conditional +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = xrd;\n"; +} // conditional +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -418,13 +482,13 @@ partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = xr [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 zimm = 0; +etiss_uint8 zimm = 0; static BitArrayRange R_zimm_0(19, 15); zimm += R_zimm_0.read(ba) << 0; -etiss_uint32 csr = 0; +etiss_uint16 csr = 0; static BitArrayRange R_csr_0(31, 20); csr += R_csr_0.read(ba) << 0; diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_retInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_retInstr.cpp index 32dfa2769b..3d2db2cc7e 100644 --- a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_retInstr.cpp +++ b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_retInstr.cpp @@ -1,24 +1,22 @@ /** - * Generated on Thu, 03 Mar 2022 12:13:52 +0100. + * Generated on Tue, 28 Nov 2023 09:45:19 +0100. * * This file contains the instruction behavior models of the tum_ret * instruction set for the RV32IMACFD core architecture. */ #include "RV32IMACFDArch.h" - -#define ETISS_ARCH_STATIC_FN_ONLY #include "RV32IMACFDFuncs.h" using namespace etiss; using namespace etiss::instr; -// URET ------------------------------------------------------------------------ -static InstructionDefinition uret_ ( +// ECALL ----------------------------------------------------------------------- +static InstructionDefinition ecall_ ( ISA32_RV32IMACFD, - "uret", - (uint32_t) 0x200073, + "ecall", + (uint32_t) 0x000073, (uint32_t) 0xffffffff, [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) { @@ -31,21 +29,41 @@ static InstructionDefinition uret_ ( // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); - partInit.code() = std::string("//URET\n"); + cp.code() = std::string("//ECALL\n"); // ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -partInit.code() += "*((RV32IMACFD*)cpu)->CSR[" + std::to_string(3088U) + "] = 0U;\n"; -partInit.code() += "*((RV32IMACFD*)cpu)->CSR[" + std::to_string(0U) + "] = *((RV32IMACFD*)cpu)->CSR[" + std::to_string(0U) + "] ^ ((*((RV32IMACFD*)cpu)->CSR[" + std::to_string(0U) + "] & 16U) >> 4U) ^ (*((RV32IMACFD*)cpu)->CSR[" + std::to_string(0U) + "] & 1U);\n"; -partInit.code() += "cpu->instructionPointer = *((RV32IMACFD*)cpu)->CSR[" + std::to_string(65U) + "];\n"; -partInit.code() += "*((RV32IMACFD*)cpu)->CSR[" + std::to_string(768U) + "] = *((RV32IMACFD*)cpu)->CSR[" + std::to_string(0U) + "];\n"; -partInit.code() += "*((RV32IMACFD*)cpu)->CSR[" + std::to_string(256U) + "] = *((RV32IMACFD*)cpu)->CSR[" + std::to_string(0U) + "];\n"; -partInit.code() += "return exception;\n"; +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV32IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 8LL + ((RV32IMACFD*)cpu)->PRIV);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; // ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); - partInit.getAffectedRegisters().add("instructionPointer", 32); + cp.code() = std::string("//ECALL\n"); + +// ----------------------------------------------------------------------------- +cp.code() += "return cpu->exception;\n"; +// ----------------------------------------------------------------------------- + } return true; }, @@ -58,17 +76,17 @@ partInit.code() += "return exception;\n"; std::stringstream ss; // ----------------------------------------------------------------------------- -ss << "uret" << " # " << ba << (" []"); +ss << "ecall" << " # " << ba << (" []"); // ----------------------------------------------------------------------------- return ss.str(); } ); -// SRET ------------------------------------------------------------------------ -static InstructionDefinition sret_ ( +// MRET ------------------------------------------------------------------------ +static InstructionDefinition mret_ ( ISA32_RV32IMACFD, - "sret", - (uint32_t) 0x10200073, + "mret", + (uint32_t) 0x30200073, (uint32_t) 0xffffffff, [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) { @@ -81,22 +99,54 @@ static InstructionDefinition sret_ ( // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); - partInit.code() = std::string("//SRET\n"); + cp.code() = std::string("//MRET\n"); // ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -partInit.code() += "*((RV32IMACFD*)cpu)->CSR[" + std::to_string(3088U) + "] = (*((RV32IMACFD*)cpu)->CSR[" + std::to_string(256U) + "] & 256U) >> 8U;\n"; -partInit.code() += "*((RV32IMACFD*)cpu)->CSR[" + std::to_string(256U) + "] = *((RV32IMACFD*)cpu)->CSR[" + std::to_string(256U) + "] ^ (*((RV32IMACFD*)cpu)->CSR[" + std::to_string(256U) + "] & 256U);\n"; -partInit.code() += "*((RV32IMACFD*)cpu)->CSR[" + std::to_string(256U) + "] = *((RV32IMACFD*)cpu)->CSR[" + std::to_string(256U) + "] ^ ((*((RV32IMACFD*)cpu)->CSR[" + std::to_string(256U) + "] & 32U) >> 4U) ^ (*((RV32IMACFD*)cpu)->CSR[" + std::to_string(256U) + "] & 2U);\n"; -partInit.code() += "cpu->instructionPointer = *((RV32IMACFD*)cpu)->CSR[" + std::to_string(321U) + "];\n"; -partInit.code() += "*((RV32IMACFD*)cpu)->CSR[" + std::to_string(768U) + "] = *((RV32IMACFD*)cpu)->CSR[" + std::to_string(256U) + "];\n"; -partInit.code() += "*((RV32IMACFD*)cpu)->CSR[" + std::to_string(0U) + "] = *((RV32IMACFD*)cpu)->CSR[" + std::to_string(256U) + "];\n"; -partInit.code() += "return exception;\n"; +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "if (((RV32IMACFD*)cpu)->PRIV < 3LL) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV32IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 2LL);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "cpu->nextPc = *((RV32IMACFD*)cpu)->CSR[833LL];\n"; +cp.code() += "etiss_uint32 s = RV32IMACFD_csr_read(cpu, system, plugin_pointers, 768LL);\n"; +cp.code() += "etiss_uint32 prev_prv = RV32IMACFD_get_field(s, 6144LL);\n"; +cp.code() += "if (prev_prv != 3LL) { // conditional\n"; +cp.code() += "s = RV32IMACFD_set_field(s, 131072LL, 0ULL);\n"; +cp.code() += "} // conditional\n"; +cp.code() += "s = RV32IMACFD_set_field(s, 8LL, RV32IMACFD_get_field(s, 128LL));\n"; +cp.code() += "s = RV32IMACFD_set_field(s, 128LL, 1ULL);\n"; +cp.code() += "s = RV32IMACFD_set_field(s, 6144LL, (RV32IMACFD_extension_enabled(cpu, system, plugin_pointers, 85ULL)) ? (0LL) : (3LL));\n"; +cp.code() += "RV32IMACFD_csr_write(cpu, system, plugin_pointers, 768LL, s);\n"; +cp.code() += "((RV32IMACFD*)cpu)->PRIV = (prev_prv) & 0x7;\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; // ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); - partInit.getAffectedRegisters().add("instructionPointer", 32); + cp.code() = std::string("//MRET\n"); + +// ----------------------------------------------------------------------------- +cp.code() += "return cpu->exception;\n"; +// ----------------------------------------------------------------------------- + } return true; }, @@ -109,17 +159,17 @@ partInit.code() += "return exception;\n"; std::stringstream ss; // ----------------------------------------------------------------------------- -ss << "sret" << " # " << ba << (" []"); +ss << "mret" << " # " << ba << (" []"); // ----------------------------------------------------------------------------- return ss.str(); } ); -// MRET ------------------------------------------------------------------------ -static InstructionDefinition mret_ ( +// WFI ------------------------------------------------------------------------- +static InstructionDefinition wfi_ ( ISA32_RV32IMACFD, - "mret", - (uint32_t) 0x30200073, + "wfi", + (uint32_t) 0x10500073, (uint32_t) 0xffffffff, [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) { @@ -132,22 +182,35 @@ static InstructionDefinition mret_ ( // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); - partInit.code() = std::string("//MRET\n"); + cp.code() = std::string("//WFI\n"); // ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -partInit.code() += "*((RV32IMACFD*)cpu)->CSR[" + std::to_string(3088U) + "] = (*((RV32IMACFD*)cpu)->CSR[" + std::to_string(768U) + "] & 6144U) >> 11U;\n"; -partInit.code() += "*((RV32IMACFD*)cpu)->CSR[" + std::to_string(768U) + "] = *((RV32IMACFD*)cpu)->CSR[" + std::to_string(768U) + "] ^ (*((RV32IMACFD*)cpu)->CSR[" + std::to_string(768U) + "] & 6144U);\n"; -partInit.code() += "*((RV32IMACFD*)cpu)->CSR[" + std::to_string(768U) + "] = *((RV32IMACFD*)cpu)->CSR[" + std::to_string(768U) + "] ^ ((*((RV32IMACFD*)cpu)->CSR[" + std::to_string(768U) + "] & 128U) >> 4U) ^ (*((RV32IMACFD*)cpu)->CSR[" + std::to_string(768U) + "] & 8U);\n"; -partInit.code() += "cpu->instructionPointer = *((RV32IMACFD*)cpu)->CSR[" + std::to_string(833U) + "];\n"; -partInit.code() += "*((RV32IMACFD*)cpu)->CSR[" + std::to_string(0U) + "] = *((RV32IMACFD*)cpu)->CSR[" + std::to_string(768U) + "];\n"; -partInit.code() += "*((RV32IMACFD*)cpu)->CSR[" + std::to_string(256U) + "] = *((RV32IMACFD*)cpu)->CSR[" + std::to_string(768U) + "];\n"; -partInit.code() += "return exception;\n"; +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; // ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); - partInit.getAffectedRegisters().add("instructionPointer", 32); + cp.code() = std::string("//WFI\n"); + +// ----------------------------------------------------------------------------- +cp.code() += "return cpu->exception;\n"; +// ----------------------------------------------------------------------------- + } return true; }, @@ -160,7 +223,87 @@ partInit.code() += "return exception;\n"; std::stringstream ss; // ----------------------------------------------------------------------------- -ss << "mret" << " # " << ba << (" []"); +ss << "wfi" << " # " << ba << (" []"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// SRET ------------------------------------------------------------------------ +static InstructionDefinition sret_ ( + ISA32_RV32IMACFD, + "sret", + (uint32_t) 0x10200073, + (uint32_t) 0xffffffff, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//SRET\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "if (((RV32IMACFD*)cpu)->PRIV < ((RV32IMACFD_get_field(RV32IMACFD_csr_read(cpu, system, plugin_pointers, 768LL), 4194304LL)) ? (3LL) : (1LL))) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV32IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 2LL);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "cpu->nextPc = *((RV32IMACFD*)cpu)->CSR[321LL];\n"; +cp.code() += "etiss_uint32 s = RV32IMACFD_csr_read(cpu, system, plugin_pointers, 256LL);\n"; +cp.code() += "etiss_uint32 prev_prv = RV32IMACFD_get_field(s, 256LL);\n"; +cp.code() += "s = RV32IMACFD_set_field(s, 2LL, RV32IMACFD_get_field(s, 32LL));\n"; +cp.code() += "s = RV32IMACFD_set_field(s, 32LL, 1ULL);\n"; +cp.code() += "s = RV32IMACFD_set_field(s, 256LL, 0LL);\n"; +cp.code() += "RV32IMACFD_csr_write(cpu, system, plugin_pointers, 768LL, s);\n"; +cp.code() += "((RV32IMACFD*)cpu)->PRIV = (prev_prv) & 0x7;\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); + + cp.code() = std::string("//SRET\n"); + +// ----------------------------------------------------------------------------- +cp.code() += "return cpu->exception;\n"; +// ----------------------------------------------------------------------------- + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "sret" << " # " << ba << (" []"); // ----------------------------------------------------------------------------- return ss.str(); } diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_rvaInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_rvaInstr.cpp index 7bcc8f67d3..279e076b1c 100644 --- a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_rvaInstr.cpp +++ b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_rvaInstr.cpp @@ -1,13 +1,11 @@ /** - * Generated on Mon, 09 May 2022 21:04:41 +0200. + * Generated on Tue, 28 Nov 2023 09:45:19 +0100. * * This file contains the instruction behavior models of the tum_rva * instruction set for the RV32IMACFD core architecture. */ #include "RV32IMACFDArch.h" - -#define ETISS_ARCH_STATIC_FN_ONLY #include "RV32IMACFDFuncs.h" using namespace etiss; @@ -28,41 +26,66 @@ static InstructionDefinition lrw_rd_rs1_rl_aq ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rl = 0; +etiss_uint8 rl = 0; static BitArrayRange R_rl_0(25, 25); rl += R_rl_0.read(ba) << 0; -etiss_uint32 aq = 0; +etiss_uint8 aq = 0; static BitArrayRange R_aq_0(26, 26); aq += R_aq_0.read(ba) << 0; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//LRW\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n"; +cp.code() += "etiss_uint32 mem_val_0;\n"; +cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "etiss_int32 res = (etiss_int32)(mem_val_0);\n"; +cp.code() += "((RV32IMACFD*)cpu)->RES_ADDR = offs;\n"; +if (rd) { // conditional +cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int32)(res);\n"; +} // conditional +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); - partInit.code() = std::string("//LRW\n"); + cp.code() = std::string("//LRW\n"); // ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n"; -partInit.code() += "etiss_uint32 mem_val_0;\n"; -partInit.code() += "exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n"; -partInit.code() += "etiss_int32 res = (etiss_int32)(mem_val_0);\n"; -partInit.code() += "((RV32IMACFD*)cpu)->RES_ADDR = offs;\n"; -if (rd) { -partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = (etiss_int32)(res);\n"; -} -partInit.code() += "if (exception) return exception;\n"; +cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n"; // ----------------------------------------------------------------------------- - - partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32); - partInit.getAffectedRegisters().add(reg_name[rd % 32], 32); - partInit.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -70,16 +93,16 @@ partInit.code() += "if (exception) return exception;\n"; [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rl = 0; +etiss_uint8 rl = 0; static BitArrayRange R_rl_0(25, 25); rl += R_rl_0.read(ba) << 0; -etiss_uint32 aq = 0; +etiss_uint8 aq = 0; static BitArrayRange R_aq_0(26, 26); aq += R_aq_0.read(ba) << 0; @@ -107,47 +130,71 @@ static InstructionDefinition scw_rd_rs1_rs2_rl_aq ( // ----------------------------------------------------------------------------- // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; -etiss_uint32 rl = 0; +etiss_uint8 rl = 0; static BitArrayRange R_rl_0(25, 25); rl += R_rl_0.read(ba) << 0; -etiss_uint32 aq = 0; +etiss_uint8 aq = 0; static BitArrayRange R_aq_0(26, 26); aq += R_aq_0.read(ba) << 0; // ----------------------------------------------------------------------------- - CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//SCW\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n"; +cp.code() += "if (((RV32IMACFD*)cpu)->RES_ADDR == offs) { // conditional\n"; +cp.code() += "etiss_uint32 mem_val_0;\n"; +cp.code() += "mem_val_0 = (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n"; +cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "} // conditional\n"; +if (rd) { // conditional +cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = ((RV32IMACFD*)cpu)->RES_ADDR != offs;\n"; +} // conditional +cp.code() += "((RV32IMACFD*)cpu)->RES_ADDR = -1LL;\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); - partInit.code() = std::string("//SCW\n"); + cp.code() = std::string("//SCW\n"); // ----------------------------------------------------------------------------- -partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4U) + ";\n"; -partInit.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32U) + "];\n"; -partInit.code() += "if (((RV32IMACFD*)cpu)->RES_ADDR == offs) {\n"; -partInit.code() += "etiss_uint32 mem_val_0 = (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32U) + "]);\n"; -partInit.code() += "exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n"; - -partInit.code() += "}\n"; -if (rd) { -partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = ((RV32IMACFD*)cpu)->RES_ADDR != offs;\n"; -} -partInit.code() += "((RV32IMACFD*)cpu)->RES_ADDR = -1U;\n"; -partInit.code() += "if (exception) return exception;\n"; +cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n"; // ----------------------------------------------------------------------------- - - partInit.getRegisterDependencies().add(reg_name[rs1 % 32U], 32); - partInit.getRegisterDependencies().add(reg_name[rs2 % 32U], 32); - partInit.getAffectedRegisters().add(reg_name[rd % 32], 32); - partInit.getAffectedRegisters().add("instructionPointer", 32); + } return true; }, @@ -155,19 +202,19 @@ partInit.code() += "if (exception) return exception;\n"; [] (BitArray & ba, Instruction & instr) { // ----------------------------------------------------------------------------- -etiss_uint32 rd = 0; +etiss_uint8 rd = 0; static BitArrayRange R_rd_0(11, 7); rd += R_rd_0.read(ba) << 0; -etiss_uint32 rs1 = 0; +etiss_uint8 rs1 = 0; static BitArrayRange R_rs1_0(19, 15); rs1 += R_rs1_0.read(ba) << 0; -etiss_uint32 rs2 = 0; +etiss_uint8 rs2 = 0; static BitArrayRange R_rs2_0(24, 20); rs2 += R_rs2_0.read(ba) << 0; -etiss_uint32 rl = 0; +etiss_uint8 rl = 0; static BitArrayRange R_rl_0(25, 25); rl += R_rl_0.read(ba) << 0; -etiss_uint32 aq = 0; +etiss_uint8 aq = 0; static BitArrayRange R_aq_0(26, 26); aq += R_aq_0.read(ba) << 0; diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_semihostingInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_semihostingInstr.cpp new file mode 100644 index 0000000000..601cc97f27 --- /dev/null +++ b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_semihostingInstr.cpp @@ -0,0 +1,149 @@ +/** + * Generated on Tue, 28 Nov 2023 09:45:19 +0100. + * + * This file contains the instruction behavior models of the tum_semihosting + * instruction set for the RV32IMACFD core architecture. + */ + +#include "RV32IMACFDArch.h" +#include "RV32IMACFDFuncs.h" + +using namespace etiss; +using namespace etiss::instr; + + +// EBREAK ---------------------------------------------------------------------- +static InstructionDefinition ebreak_ ( + ISA32_RV32IMACFD, + "ebreak", + (uint32_t) 0x100073, + (uint32_t) 0xffffffff, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//EBREAK\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "if (etiss_semihost_enabled()) { // conditional\n"; +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint32 mem_val_0;\n"; +cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, " + std::to_string(ic.current_address_ - 4ULL) + "ULL, (etiss_uint8*)&mem_val_0, 4);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "etiss_uint32 pre = (etiss_uint32)(mem_val_0);\n"; +cp.code() += "etiss_uint32 mem_val_1;\n"; +cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, " + std::to_string(ic.current_address_ + 0ULL) + "ULL, (etiss_uint8*)&mem_val_1, 4);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "etiss_uint32 ebreak = (etiss_uint32)(mem_val_1);\n"; +cp.code() += "etiss_uint32 mem_val_2;\n"; +cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, " + std::to_string(ic.current_address_ + 4ULL) + "ULL, (etiss_uint8*)&mem_val_2, 4);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "etiss_uint32 post = (etiss_uint32)(mem_val_2);\n"; +cp.code() += "if (pre == 32509971ULL && ebreak == 1048691ULL && post == 1081102355ULL) { // conditional\n"; +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint32 operation = *((RV32IMACFD*)cpu)->X[10ULL];\n"; +cp.code() += "etiss_uint32 parameter = *((RV32IMACFD*)cpu)->X[11ULL];\n"; +cp.code() += "*((RV32IMACFD*)cpu)->X[10ULL] = (etiss_int32)(etiss_semihost(cpu, system, plugin_pointers, 32ULL, operation, parameter));\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "} // conditional\n"; +cp.code() += "else { // conditional\n"; +{ // block +cp.code() += "{ // block\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV32IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 3LL);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // block\n"; +} // block +cp.code() += "} // conditional\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "} // conditional\n"; +cp.code() += "else { // conditional\n"; +{ // block +cp.code() += "{ // block\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV32IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 3LL);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // block\n"; +} // block +cp.code() += "} // conditional\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); + + cp.code() = std::string("//EBREAK\n"); + +// ----------------------------------------------------------------------------- +cp.code() += "if (cpu->return_pending | cpu->exception | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + "ULL) return cpu->exception;\n"; +// ----------------------------------------------------------------------------- + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "ebreak" << " # " << ba << (" []"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); diff --git a/ArchImpl/RV64IMACFD/CMakeLists.txt b/ArchImpl/RV64IMACFD/CMakeLists.txt new file mode 100644 index 0000000000..fb9c4ad8f5 --- /dev/null +++ b/ArchImpl/RV64IMACFD/CMakeLists.txt @@ -0,0 +1,46 @@ +# Generated on Tue, 28 Nov 2023 09:45:19 +0100. +# +# This file contains the CMake build info for the RV64IMACFD core architecture. + +PROJECT(RV64IMACFD) + +SET(CMAKE_BUILD_WITH_INSTALL_RPATH TRUE) +SET(CMAKE_INSTALL_RPATH "\$ORIGIN/../../include/jit/etiss/jit") + +ADD_LIBRARY(${PROJECT_NAME} SHARED + RV64IMACFDArch.cpp + RV64IMACFDArchLib.cpp + RV64IMACFDArchSpecificImp.cpp + RV64IMACFDFuncs.c + RV64IMACFDInstr.cpp + RV64IMACFD_RV32IInstr.cpp + RV64IMACFD_RV64IInstr.cpp + RV64IMACFD_RV32ICInstr.cpp + RV64IMACFD_RV64ICInstr.cpp + RV64IMACFD_RV32MInstr.cpp + RV64IMACFD_RV64MInstr.cpp + RV64IMACFD_RV32FInstr.cpp + RV64IMACFD_RV64FInstr.cpp + RV64IMACFD_RV32DInstr.cpp + RV64IMACFD_RV64DInstr.cpp + RV64IMACFD_RV32DCInstr.cpp + RV64IMACFD_RV32AInstr.cpp + RV64IMACFD_RV64AInstr.cpp + RV64IMACFD_ZifenceiInstr.cpp + RV64IMACFD_tum_csrInstr.cpp + RV64IMACFD_tum_retInstr.cpp + RV64IMACFD_tum_rvaInstr.cpp + RV64IMACFD_tum_rva64Instr.cpp + RV64IMACFD_tum_rvmInstr.cpp + RV64IMACFD_tum_semihostingInstr.cpp +) + +add_custom_command( + TARGET ${PROJECT_NAME} POST_BUILD + COMMAND ${CMAKE_COMMAND} -E copy + "${CMAKE_CURRENT_LIST_DIR}/${PROJECT_NAME}Funcs.h" + "${ETISS_BINARY_DIR}/include/jit/Arch/${PROJECT_NAME}" +) +INSTALL(FILES "${CMAKE_CURRENT_LIST_DIR}/${PROJECT_NAME}Funcs.h" DESTINATION "include/jit/Arch/${PROJECT_NAME}") + +ETISSPluginArch(${PROJECT_NAME}) \ No newline at end of file diff --git a/ArchImpl/RV64IMACFD/Encoding.h b/ArchImpl/RV64IMACFD/Encoding.h new file mode 100644 index 0000000000..d551ed5626 --- /dev/null +++ b/ArchImpl/RV64IMACFD/Encoding.h @@ -0,0 +1,203 @@ +/* + + @copyright + + 
+
+        Copyright 2018 Chair of Electronic Design Automation, TUM
+
+        This file is part of ETISS tool, see .
+
+        The initial version of this software has been created with the funding support by the German Federal
+        Ministry of Education and Research (BMBF) in the project EffektiV under grant 01IS13022.
+
+        Redistribution and use in source and binary forms, with or without modification, are permitted
+        provided that the following conditions are met:
+
+        1. Redistributions of source code must retain the above copyright notice, this list of conditions and
+        the following disclaimer.
+
+        2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions
+        and the following disclaimer in the documentation and/or other materials provided with the distribution.
+
+        3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse
+        or promote products derived from this software without specific prior written permission.
+
+        THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
+        WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+        PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY
+        DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+        PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+        HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+        NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+        POSSIBILITY OF SUCH DAMAGE.
+
+
+ + @author Chair of Electronic Design Automation, TUM + + @version 0.1 + +*/ + +#ifndef RISCV_CSR_ENCODING_H +#define RISCV_CSR_ENCODING_H + +#define MSTATUS_UIE 0x00000001 +#define MSTATUS_SIE 0x00000002 +#define MSTATUS_HIE 0x00000004 +#define MSTATUS_MIE 0x00000008 +#define MSTATUS_UPIE 0x00000010 +#define MSTATUS_SPIE 0x00000020 +#define MSTATUS_HPIE 0x00000040 +#define MSTATUS_MPIE 0x00000080 +#define MSTATUS_SPP 0x00000100 +#define MSTATUS_HPP 0x00000600 +#define MSTATUS_MPP 0x00001800 +#define MSTATUS_FS 0x00006000 +#define MSTATUS_XS 0x00018000 +#define MSTATUS_MPRV 0x00020000 +#define MSTATUS_SUM 0x00040000 +#define MSTATUS_MXR 0x00080000 +#define MSTATUS_TVM 0x00100000 +#define MSTATUS_TW 0x00200000 +#define MSTATUS_TSR 0x00400000 +#define MSTATUS32_SD 0x80000000 +#define MSTATUS_UXL 0x0000000300000000 +#define MSTATUS_SXL 0x0000000C00000000 +#define MSTATUS64_SD 0x8000000000000000 + +#define SSTATUS_UIE 0x00000001 +#define SSTATUS_SIE 0x00000002 +#define SSTATUS_UPIE 0x00000010 +#define SSTATUS_SPIE 0x00000020 +#define SSTATUS_SPP 0x00000100 +#define SSTATUS_FS 0x00006000 +#define SSTATUS_XS 0x00018000 +#define SSTATUS_SUM 0x00040000 +#define SSTATUS_MXR 0x00080000 +#define SSTATUS32_SD 0x80000000 +#define SSTATUS_UXL 0x0000000300000000 +#define SSTATUS64_SD 0x8000000000000000 + +#define MIP_SSIP (1 << IRQ_S_SOFT) +#define MIP_HSIP (1 << IRQ_H_SOFT) +#define MIP_MSIP (1 << IRQ_M_SOFT) +#define MIP_STIP (1 << IRQ_S_TIMER) +#define MIP_HTIP (1 << IRQ_H_TIMER) +#define MIP_MTIP (1 << IRQ_M_TIMER) +#define MIP_SEIP (1 << IRQ_S_EXT) +#define MIP_HEIP (1 << IRQ_H_EXT) +#define MIP_MEIP (1 << IRQ_M_EXT) + +#define SIP_SSIP MIP_SSIP +#define SIP_STIP MIP_STIP + +#define PRV_U 0 +#define PRV_S 1 +#define PRV_H 2 +#define PRV_M 3 + +#define PAGE_OFFSET 12 +#define OFFSET_MASK ((1 << PAGE_OFFSET) - 1) +#define PAGE_SIZE 1 << PAGE_OFFSET +#define LEVELS 3 +#define VPN_OFFSET 9 +#define PTESIZE 8 +#define SATP_PPN_MASK ((0x1ULL << 44ULL) - 1ULL) + +#define SATP32_MODE 0x80000000 +#define SATP32_ASID 0x7FC00000 +#define SATP32_PPN 0x003FFFFF +#define SATP64_MODE 0xF000000000000000 +#define SATP64_ASID 0x0FFFF00000000000 +#define SATP64_PPN 0x00000FFFFFFFFFFF + +#define SATP_MODE_OFF 0 +#define SATP_MODE_SV32 1 +#define SATP_MODE_SV39 8 +#define SATP_MODE_SV48 9 +#define SATP_MODE_SV57 10 +#define SATP_MODE_SV64 11 + +#define PMP_R 0x01 +#define PMP_W 0x02 +#define PMP_X 0x04 +#define PMP_A 0x18 +#define PMP_L 0x80 +#define PMP_SHIFT 2 + +#define PMP_TOR 0x08 +#define PMP_NA4 0x10 +#define PMP_NAPOT 0x18 + +#define IRQ_S_SOFT 1 +#define IRQ_H_SOFT 2 +#define IRQ_M_SOFT 3 +#define IRQ_S_TIMER 5 +#define IRQ_H_TIMER 6 +#define IRQ_M_TIMER 7 +#define IRQ_S_EXT 9 +#define IRQ_H_EXT 10 +#define IRQ_M_EXT 11 +#define IRQ_COP 12 +#define IRQ_HOST 13 + +#define DEFAULT_RSTVEC 0x00001000 +#define CLINT_BASE 0x02000000 +#define CLINT_SIZE 0x000c0000 +#define EXT_IO_BASE 0x40000000 +#define DRAM_BASE 0x80000000 + +// page table entry (PTE) fields +#define PTE_V 0x001 // Valid +#define PTE_R 0x002 // Read +#define PTE_W 0x004 // Write +#define PTE_X 0x008 // Execute +#define PTE_U 0x010 // User +#define PTE_G 0x020 // Global +#define PTE_A 0x040 // Accessed +#define PTE_D 0x080 // Dirty +#define PTE_SOFT 0x300 // Reserved for Software + +#define PTE_TABLE(PTE) (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V) + +#define CSR_SSTATUS 0x100 +#define CSR_SIE 0x104 +#define CSR_STVEC 0x105 +#define CSR_SCOUNTEREN 0x106 +#define CSR_SSCRATCH 0x140 +#define CSR_SEPC 0x141 +#define CSR_SCAUSE 0x142 +#define CSR_STVAL 0x143 +#define CSR_SIP 0x144 +#define CSR_SATP 0x180 +#define CSR_MSTATUS 0x300 +#define CSR_MISA 0x301 +#define CSR_MEDELEG 0x302 +#define CSR_MIDELEG 0x303 +#define CSR_MIE 0x304 +#define CSR_MTVEC 0x305 +#define CSR_MCOUNTEREN 0x306 +#define CSR_MSCRATCH 0x340 +#define CSR_MEPC 0x341 +#define CSR_MCAUSE 0x342 +#define CSR_MTVAL 0x343 +#define CSR_MIP 0x344 + +#define CAUSE_MISALIGNED_FETCH 0x0 +#define CAUSE_FETCH_ACCESS 0x1 +#define CAUSE_ILLEGAL_INSTRUCTION 0x2 +#define CAUSE_BREAKPOINT 0x3 +#define CAUSE_MISALIGNED_LOAD 0x4 +#define CAUSE_LOAD_ACCESS 0x5 +#define CAUSE_MISALIGNED_STORE 0x6 +#define CAUSE_STORE_ACCESS 0x7 +#define CAUSE_USER_ECALL 0x8 +#define CAUSE_SUPERVISOR_ECALL 0x9 +#define CAUSE_HYPERVISOR_ECALL 0xa +#define CAUSE_MACHINE_ECALL 0xb +#define CAUSE_FETCH_PAGE_FAULT 0xc +#define CAUSE_LOAD_PAGE_FAULT 0xd +#define CAUSE_STORE_PAGE_FAULT 0xf +#endif diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD.h b/ArchImpl/RV64IMACFD/RV64IMACFD.h new file mode 100644 index 0000000000..a2dc8d0d68 --- /dev/null +++ b/ArchImpl/RV64IMACFD/RV64IMACFD.h @@ -0,0 +1,71 @@ +/** + * Generated on Tue, 28 Nov 2023 09:45:19 +0100. + * + * This file contains the registers for the RV64IMACFD core architecture. + */ + +#ifndef ETISS_RV64IMACFDArch_RV64IMACFD_H_ +#define ETISS_RV64IMACFDArch_RV64IMACFD_H_ +#include +#include "etiss/jit/CPU.h" + +#ifdef __cplusplus +extern "C" { +#endif +#pragma pack(push, 1) +struct RV64IMACFD { + ETISS_CPU cpu; // original cpu struct must be defined as the first field of the new structure. this allows to cast X * to ETISS_CPU * and vice vers + etiss_uint64 ZERO; + etiss_uint64 RA; + etiss_uint64 SP; + etiss_uint64 GP; + etiss_uint64 TP; + etiss_uint64 T0; + etiss_uint64 T1; + etiss_uint64 T2; + etiss_uint64 S0; + etiss_uint64 S1; + etiss_uint64 A0; + etiss_uint64 A1; + etiss_uint64 A2; + etiss_uint64 A3; + etiss_uint64 A4; + etiss_uint64 A5; + etiss_uint64 A6; + etiss_uint64 A7; + etiss_uint64 S2; + etiss_uint64 S3; + etiss_uint64 S4; + etiss_uint64 S5; + etiss_uint64 S6; + etiss_uint64 S7; + etiss_uint64 S8; + etiss_uint64 S9; + etiss_uint64 S10; + etiss_uint64 S11; + etiss_uint64 T3; + etiss_uint64 T4; + etiss_uint64 T5; + etiss_uint64 T6; + etiss_uint64 *X[32]; + etiss_uint64 ins_X[32]; + etiss_uint64 FENCE[8]; + etiss_uint8 RES[8]; + etiss_uint8 PRIV; + etiss_uint64 DPC; + etiss_uint64 FCSR; + etiss_uint64 MSTATUS; + etiss_uint64 MIE; + etiss_uint64 MIP; + etiss_uint64 *CSR[4096]; + etiss_uint64 ins_CSR[4096]; + etiss_uint64 F[32]; + etiss_uint64 RES_ADDR; +}; + +#pragma pack(pop) // undo changes +typedef struct RV64IMACFD RV64IMACFD; // convenient use of X instead of struct X in generated C code +#ifdef __cplusplus +} // extern "C" +#endif +#endif diff --git a/ArchImpl/RV64IMACFD/RV64IMACFDArch.cpp b/ArchImpl/RV64IMACFD/RV64IMACFDArch.cpp new file mode 100644 index 0000000000..b1796a3f0a --- /dev/null +++ b/ArchImpl/RV64IMACFD/RV64IMACFDArch.cpp @@ -0,0 +1,266 @@ +/** + * Generated on Tue, 28 Nov 2023 09:45:19 +0100. + * + * This file contains the architecture class for the RV64IMACFD core architecture. + */ + +/********************************************************************************************************************************* + +* Modification guidelines: + + 1. The initial value of SP register should be initialized by ctr0.S/board.S. If not, it could be initialized + through utility class etiss::VirtualStruct::Field. + + 2. Debug mode print out all assignment results. GDB in 8 is prefered. + + 3. Manually copy the content in bracket ["return ETISS_RETURNCODE_CPUFINISHED; \n"] to terminating instruction, + otherwise the emulation can not be ended. + + 4. If subset of encoding error occurs, it means the format of the encoding in the input model was not appropriate + + 5. If the PC register points to wrong address, please notice that some assembly may cause branch operation + implicitly such as "MOV Rd Rn" in ARMv6-M + + 6. If a variable is the result of dynamic slicing such as, var_1 = var_2, the size would be + calculated during process (if possible), otherwise it is assumed to be the register size. Problems may occur when + var_1 encounters bit manipulation such as "~" due to bit expansion. To change the nml model with explicit slicing + e.g var_1 = val_2<3..0> or avoid bit manipulation for dynamic sliced variable. Otherwise, you have to manually + correct it. + + 7. Implementation dependent functionalities such as exception handling should be manully added. Corresponding interfaces + are provided in RV64IMACFDArchSpecificImp.h + + 8. RV64IMACFDGDBCore.h provides the GDBCore class to support gdb flavor debugging feature, modify iy if in need. + + *********************************************************************************************************************************/ + +#include "RV64IMACFDArch.h" +#include "RV64IMACFDFuncs.h" + +#define RV64IMACFD_DEBUG_CALL 0 +using namespace etiss ; +using namespace etiss::instr ; + +RV64IMACFDArch::RV64IMACFDArch():CPUArch("RV64IMACFD") +{ + headers_.insert("Arch/RV64IMACFD/RV64IMACFD.h"); +} + +const std::set & RV64IMACFDArch::getListenerSupportedRegisters() +{ + return listenerSupportedRegisters_; +} + +ETISS_CPU * RV64IMACFDArch::newCPU() +{ + ETISS_CPU * ret = (ETISS_CPU *) new RV64IMACFD() ; + resetCPU (ret, 0); + return ret; +} + +void RV64IMACFDArch::resetCPU(ETISS_CPU * cpu,etiss::uint64 * startpointer) +{ + memset (cpu, 0, sizeof(RV64IMACFD)); + RV64IMACFD * rv64imacfdcpu = (RV64IMACFD *) cpu; + + if (startpointer) cpu->instructionPointer = *startpointer & ~((etiss::uint64)0x1); + else cpu->instructionPointer = 0x0; // reference to manual + cpu->nextPc = cpu->instructionPointer; + cpu->mode = 1; + cpu->cpuTime_ps = 0; + cpu->cpuCycleTime_ps = 31250; + + + for (int i = 0; i < 32; ++i) { + rv64imacfdcpu->ins_X[i] = 0; + rv64imacfdcpu->X[i] = &rv64imacfdcpu->ins_X[i]; + } + for (int i = 0; i < 4096; ++i) { + rv64imacfdcpu->ins_CSR[i] = 0; + rv64imacfdcpu->CSR[i] = &rv64imacfdcpu->ins_CSR[i]; + } + + rv64imacfdcpu->ZERO = 0; + rv64imacfdcpu->RA = 0; + rv64imacfdcpu->SP = 0; + rv64imacfdcpu->GP = 0; + rv64imacfdcpu->TP = 0; + rv64imacfdcpu->T0 = 0; + rv64imacfdcpu->T1 = 0; + rv64imacfdcpu->T2 = 0; + rv64imacfdcpu->S0 = 0; + rv64imacfdcpu->S1 = 0; + rv64imacfdcpu->A0 = 0; + rv64imacfdcpu->A1 = 0; + rv64imacfdcpu->A2 = 0; + rv64imacfdcpu->A3 = 0; + rv64imacfdcpu->A4 = 0; + rv64imacfdcpu->A5 = 0; + rv64imacfdcpu->A6 = 0; + rv64imacfdcpu->A7 = 0; + rv64imacfdcpu->S2 = 0; + rv64imacfdcpu->S3 = 0; + rv64imacfdcpu->S4 = 0; + rv64imacfdcpu->S5 = 0; + rv64imacfdcpu->S6 = 0; + rv64imacfdcpu->S7 = 0; + rv64imacfdcpu->S8 = 0; + rv64imacfdcpu->S9 = 0; + rv64imacfdcpu->S10 = 0; + rv64imacfdcpu->S11 = 0; + rv64imacfdcpu->T3 = 0; + rv64imacfdcpu->T4 = 0; + rv64imacfdcpu->T5 = 0; + rv64imacfdcpu->T6 = 0; + for (int i = 0; i < 8; ++i) { + rv64imacfdcpu->FENCE[i] = 0; + } + for (int i = 0; i < 8; ++i) { + rv64imacfdcpu->RES[i] = 0; + } + rv64imacfdcpu->PRIV = 0; + rv64imacfdcpu->DPC = 0; + rv64imacfdcpu->FCSR = 0; + rv64imacfdcpu->MSTATUS = 0; + rv64imacfdcpu->MIE = 0; + rv64imacfdcpu->MIP = 0; + for (int i = 0; i < 32; ++i) { + rv64imacfdcpu->F[i] = 0; + } + rv64imacfdcpu->RES_ADDR = 0; + + rv64imacfdcpu->X[0] = &rv64imacfdcpu->ZERO; + rv64imacfdcpu->X[1] = &rv64imacfdcpu->RA; + rv64imacfdcpu->X[2] = &rv64imacfdcpu->SP; + rv64imacfdcpu->X[3] = &rv64imacfdcpu->GP; + rv64imacfdcpu->X[4] = &rv64imacfdcpu->TP; + rv64imacfdcpu->X[5] = &rv64imacfdcpu->T0; + rv64imacfdcpu->X[6] = &rv64imacfdcpu->T1; + rv64imacfdcpu->X[7] = &rv64imacfdcpu->T2; + rv64imacfdcpu->X[8] = &rv64imacfdcpu->S0; + rv64imacfdcpu->X[9] = &rv64imacfdcpu->S1; + rv64imacfdcpu->X[10] = &rv64imacfdcpu->A0; + rv64imacfdcpu->X[11] = &rv64imacfdcpu->A1; + rv64imacfdcpu->X[12] = &rv64imacfdcpu->A2; + rv64imacfdcpu->X[13] = &rv64imacfdcpu->A3; + rv64imacfdcpu->X[14] = &rv64imacfdcpu->A4; + rv64imacfdcpu->X[15] = &rv64imacfdcpu->A5; + rv64imacfdcpu->X[16] = &rv64imacfdcpu->A6; + rv64imacfdcpu->X[17] = &rv64imacfdcpu->A7; + rv64imacfdcpu->X[18] = &rv64imacfdcpu->S2; + rv64imacfdcpu->X[19] = &rv64imacfdcpu->S3; + rv64imacfdcpu->X[20] = &rv64imacfdcpu->S4; + rv64imacfdcpu->X[21] = &rv64imacfdcpu->S5; + rv64imacfdcpu->X[22] = &rv64imacfdcpu->S6; + rv64imacfdcpu->X[23] = &rv64imacfdcpu->S7; + rv64imacfdcpu->X[24] = &rv64imacfdcpu->S8; + rv64imacfdcpu->X[25] = &rv64imacfdcpu->S9; + rv64imacfdcpu->X[26] = &rv64imacfdcpu->S10; + rv64imacfdcpu->X[27] = &rv64imacfdcpu->S11; + rv64imacfdcpu->X[28] = &rv64imacfdcpu->T3; + rv64imacfdcpu->X[29] = &rv64imacfdcpu->T4; + rv64imacfdcpu->X[30] = &rv64imacfdcpu->T5; + rv64imacfdcpu->X[31] = &rv64imacfdcpu->T6; + rv64imacfdcpu->CSR[3] = &rv64imacfdcpu->FCSR; + rv64imacfdcpu->CSR[768] = &rv64imacfdcpu->MSTATUS; + rv64imacfdcpu->CSR[772] = &rv64imacfdcpu->MIE; + rv64imacfdcpu->CSR[836] = &rv64imacfdcpu->MIP; + + rv64imacfdcpu->PRIV = 3; + rv64imacfdcpu->DPC = 0; + *rv64imacfdcpu->CSR[0] = 11; + *rv64imacfdcpu->CSR[256] = 11; + *rv64imacfdcpu->CSR[768] = 11; + *rv64imacfdcpu->CSR[769] = 9223372036856090925; + *rv64imacfdcpu->CSR[3088] = 3; + *rv64imacfdcpu->CSR[772] = 4294966203; + *rv64imacfdcpu->CSR[260] = 4294964019; + *rv64imacfdcpu->CSR[4] = 4294963473; + rv64imacfdcpu->RES_ADDR = -1; +} + +void RV64IMACFDArch::deleteCPU(ETISS_CPU *cpu) +{ + delete (RV64IMACFD *) cpu ; +} + +/** + @return 8 (jump instruction + instruction of delay slot) +*/ +unsigned RV64IMACFDArch::getMaximumInstructionSizeInBytes() +{ + return 8; +} + +/** + @return 2 +*/ +unsigned RV64IMACFDArch::getInstructionSizeInBytes() +{ + return 2; +} + +/** + @brief required headers (RV64IMACFD.h) +*/ +const std::set & RV64IMACFDArch::getHeaders() const +{ + return headers_ ; +} + +void RV64IMACFDArch::initCodeBlock(etiss::CodeBlock & cb) const +{ + cb.fileglobalCode().insert("#include \"Arch/RV64IMACFD/RV64IMACFD.h\"\n"); + cb.fileglobalCode().insert("#include \"Arch/RV64IMACFD/RV64IMACFDFuncs.h\"\n"); + cb.functionglobalCode().insert("cpu->exception = 0;\n"); + cb.functionglobalCode().insert("cpu->return_pending = 0;\n"); + cb.functionglobalCode().insert("etiss_uint32 mem_ret_code = 0;\n"); +} + +etiss::plugin::gdb::GDBCore & RV64IMACFDArch::getGDBCore() +{ + return gdbcore_; +} + +const char * const reg_name[] = +{ + "X0", + "X1", + "X2", + "X3", + "X4", + "X5", + "X6", + "X7", + "X8", + "X9", + "X10", + "X11", + "X12", + "X13", + "X14", + "X15", + "X16", + "X17", + "X18", + "X19", + "X20", + "X21", + "X22", + "X23", + "X24", + "X25", + "X26", + "X27", + "X28", + "X29", + "X30", + "X31", +}; + +etiss::instr::InstructionGroup ISA16_RV64IMACFD("ISA16_RV64IMACFD", 16); +etiss::instr::InstructionClass ISA16_RV64IMACFDClass(1, "ISA16_RV64IMACFD", 16, ISA16_RV64IMACFD); +etiss::instr::InstructionGroup ISA32_RV64IMACFD("ISA32_RV64IMACFD", 32); +etiss::instr::InstructionClass ISA32_RV64IMACFDClass(1, "ISA32_RV64IMACFD", 32, ISA32_RV64IMACFD); + +etiss::instr::InstructionCollection RV64IMACFDISA("RV64IMACFDISA", ISA16_RV64IMACFDClass, ISA32_RV64IMACFDClass); \ No newline at end of file diff --git a/ArchImpl/RV64IMACFD/RV64IMACFDArch.h b/ArchImpl/RV64IMACFD/RV64IMACFDArch.h new file mode 100644 index 0000000000..3a025aeb06 --- /dev/null +++ b/ArchImpl/RV64IMACFD/RV64IMACFDArch.h @@ -0,0 +1,108 @@ +/** + * Generated on Tue, 28 Nov 2023 09:45:19 +0100. + * + * This file contains the architecture class for the RV64IMACFD core architecture. + */ + +#ifndef ETISS_RV64IMACFDArch_RV64IMACFDArch_H_ +#define ETISS_RV64IMACFDArch_RV64IMACFDArch_H_ + +#include "etiss/CPUArch.h" +#include "etiss/Instruction.h" +#include "etiss/InterruptVector.h" +#include "etiss/InterruptEnable.h" +#include "RV64IMACFD.h" +#include "RV64IMACFDGDBCore.h" + +#include + +extern const char * const reg_name[]; + +extern etiss::instr::InstructionGroup ISA16_RV64IMACFD; +extern etiss::instr::InstructionClass ISA16_RV64IMACFDClass; +extern etiss::instr::InstructionGroup ISA32_RV64IMACFD; +extern etiss::instr::InstructionClass ISA32_RV64IMACFDClass; + +extern etiss::instr::InstructionCollection RV64IMACFDISA; + +class RV64IMACFDArch : public etiss::CPUArch { + +public: + RV64IMACFDArch(); + + virtual const std::set & getListenerSupportedRegisters(); + + + virtual ETISS_CPU * newCPU(); + virtual void resetCPU(ETISS_CPU * cpu,etiss::uint64 * startpointer); + virtual void deleteCPU(ETISS_CPU *); + + /** + @brief get the VirtualStruct of the core to mitigate register access + + @see RV64IMACFDArchSpecificImp.h + */ + virtual std::shared_ptr getVirtualStruct(ETISS_CPU * cpu); + + /** + @return 8 (jump instruction + instruction of delay slot) + */ + virtual unsigned getMaximumInstructionSizeInBytes(); + + /** + @return 2 + */ + virtual unsigned getInstructionSizeInBytes(); + + /** + @brief required headers (RV64IMACFD.h) + */ + virtual const std::set & getHeaders() const; + + /** + @brief This function will be called automatically in order to handling architecure dependent exceptions such + as interrupt, system call, illegal instructions + + @see RV64IMACFDArchSpecificImp.h + */ + virtual etiss::int32 handleException(etiss::int32 code, ETISS_CPU * cpu); + + /** + @brief This function is called during CPUArch initialization + + @see RV64IMACFDArchSpecificImp.h + */ + virtual void initInstrSet(etiss::instr::ModedInstructionSet & ) const; + virtual void initCodeBlock(etiss::CodeBlock & cb) const; + + /** + @brief Target architecture may have inconsistent endianess. Data read from memory is buffered, and this function + is called to alter sequence of buffered data so that the inconsistent endianess is compensated. + + @see RV64IMACFDArchSpecificImp.h + */ + virtual void compensateEndianess(ETISS_CPU * cpu, etiss::instr::BitArray & ba) const ; + + /** + @brief If interrupt handling is expected, vector table could be provided to support interrupt triggering + + @see RV64IMACFDArchSpecificImp.h + */ + virtual etiss::InterruptVector * createInterruptVector(ETISS_CPU * cpu); + virtual void deleteInterruptVector(etiss::InterruptVector * vec, ETISS_CPU * cpu); + virtual etiss::InterruptEnable* createInterruptEnable(ETISS_CPU *cpu); + virtual void deleteInterruptEnable(etiss::InterruptEnable* en, ETISS_CPU* cpu); + + /** + @brief get the GDBcore for RV64IMACFD architecture + + @see RV64IMACFDGDBCore.h for implementation of GDBcore + */ + virtual etiss::plugin::gdb::GDBCore & getGDBCore(); + +private: + std::set listenerSupportedRegisters_; + std::set headers_; + RV64IMACFDGDBCore gdbcore_; +}; +#endif diff --git a/ArchImpl/RV64IMACFD/RV64IMACFDArchLib.cpp b/ArchImpl/RV64IMACFD/RV64IMACFDArchLib.cpp new file mode 100644 index 0000000000..3c7ce23eb8 --- /dev/null +++ b/ArchImpl/RV64IMACFD/RV64IMACFDArchLib.cpp @@ -0,0 +1,48 @@ +/** + * Generated on Tue, 28 Nov 2023 09:45:19 +0100. + * + * This file contains the library interface for the RV64IMACFD core architecture. + */ + +// define a name for this library. this will be used to avoid name clashes with other libraries. in this example the library is named "X". +// IMPORTANT this name MUST match the library name: e.g. X -> libX.so + +#define ETISS_LIBNAME RV64IMACFD +#include "etiss/helper/CPUArchLibrary.h" // defines the following functions +#include "RV64IMACFDArch.h" +extern "C" { + + ETISS_LIBRARYIF_VERSION_FUNC_IMPL + + ETISS_PLUGIN_EXPORT unsigned RV64IMACFD_countCPUArch() + { +//TODO + return 1; // number of cpu architectures provided + } + ETISS_PLUGIN_EXPORT const char * RV64IMACFD_nameCPUArch(unsigned index) + { +//TODO + switch (index) + { + case 0: + return "RV64IMACFD"; + default: + return ""; + } + } + ETISS_PLUGIN_EXPORT etiss::CPUArch* RV64IMACFD_createCPUArch(unsigned index,std::map options) + { +//TODO + switch (index) + { + case 0: + return new RV64IMACFDArch(); + default: + return 0; + } + } + ETISS_PLUGIN_EXPORT void RV64IMACFD_deleteCPUArch(etiss::CPUArch* arch) + { + delete arch; + } +} diff --git a/ArchImpl/RV64IMACFD/RV64IMACFDArchSpecificImp.cpp b/ArchImpl/RV64IMACFD/RV64IMACFDArchSpecificImp.cpp new file mode 100644 index 0000000000..7be16f264d --- /dev/null +++ b/ArchImpl/RV64IMACFD/RV64IMACFDArchSpecificImp.cpp @@ -0,0 +1,365 @@ +/** + * Generated on Fri, 03 Nov 2023 13:22:23 +0100. + * + * This file contains the architecture specific implementation for the RV64IMACFD + * core architecture. + * + * WARNING: This file contains user-added code, be mindful when overwriting this with + * generated code! + */ + +#include + +#include "RV64IMACFDArch.h" +#include "RV64IMACFDArchSpecificImp.h" +#include "RV64IMACFDFuncs.h" + +/** + @brief This function will be called automatically in order to handling exceptions such as interrupt, system call, illegal instructions + + @details Exception handling mechanism is implementation dependent for each cpu variant. Please add it to the following block if exception + handling is demanded. + Pesudo example: + switch(cause){ + case etiss::RETURNCODE::INTERRUPT: + . + . + . + break; + +*/ +etiss::int32 RV64IMACFDArch::handleException(etiss::int32 cause, ETISS_CPU * cpu) +{ + RV64IMACFD_translate_exc_code(cpu, nullptr, nullptr, cause); + cpu->instructionPointer = cpu->nextPc; + return 0; +} + +/** + @brief This function is called during CPUArch initialization + + @details Function pointer length_updater_ has to be replaced if multiple length instruction execution is supported. This + function enables dynamic instruction length update in order to guarantee correct binary translation + Pesudo example: + vis->length_updater_ = [](VariableInstructionSet & ,InstructionContext & ic, BitArray & ba) + { + switch(ba.byteCount()){ + case 4: + if ( INSTRUCTION_LENTH_NOT_EQUAL(4)){ + updateInstrLength(ic, ba); + ic.is_not_default_width_ = true; + . + . + . + } + break; + } + }; + +*/ +void RV64IMACFDArch::initInstrSet(etiss::instr::ModedInstructionSet & mis) const +{ + + { + /* Set default JIT Extensions. Read Parameters set from ETISS configuration and append with architecturally needed */ + std::string cfgPar = ""; + cfgPar = etiss::cfg().get("jit.external_headers", ";"); + etiss::cfg().set("jit.external_headers", cfgPar + "etiss/jit/libsoftfloat.h"); + + cfgPar = etiss::cfg().get("jit.external_libs", ";"); + etiss::cfg().set("jit.external_libs", cfgPar + "softfloat"); + + cfgPar = etiss::cfg().get("jit.external_header_paths", ";"); + etiss::cfg().set("jit.external_header_paths", cfgPar + "/etiss/jit"); + + cfgPar = etiss::cfg().get("jit.external_lib_paths", ";"); + etiss::cfg().set("jit.external_lib_paths", cfgPar + "/etiss/jit"); + + } + + if (false) { + // Pre-compilation of instruction set to view instruction tree. Could be disabled. + etiss::instr::ModedInstructionSet iset("RV64IMACFDISA"); + bool ok = true; + RV64IMACFDISA.addTo(iset,ok); + + iset.compile(); + + std::cout << iset.print() << std::endl; + } + + bool ok = true; + RV64IMACFDISA.addTo(mis,ok); + if (!ok) + etiss::log(etiss::FATALERROR,"Failed to add instructions for RV64IMACFDISA"); + + etiss::instr::VariableInstructionSet *vis = mis.get(1); + + using namespace etiss; + using namespace etiss::instr; + + vis->get(32)->getInvalid().addCallback( + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint32 error_code = 0; +static BitArrayRange R_error_code_0(31, 0); +error_code += R_error_code_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//trap_entry 32\n"); + +// ----------------------------------------------------------------------------- +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, " + std::to_string(error_code) + "ULL);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); + + cp.code() = std::string("//trap_entry 32\n"); + +// ----------------------------------------------------------------------------- +cp.code() += "return cpu->exception;\n"; +// ----------------------------------------------------------------------------- + } + + return true; + }, + 0 + ); + + vis->get(16)->getInvalid().addCallback( + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint32 error_code = 0; +static BitArrayRange R_error_code_0(31, 0); +error_code += R_error_code_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//trap_entry 16\n"); + +// ----------------------------------------------------------------------------- +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, " + std::to_string(error_code) + "ULL);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); + + cp.code() = std::string("//trap_entry 16\n"); + +// ----------------------------------------------------------------------------- +cp.code() += "return cpu->exception;\n"; +// ----------------------------------------------------------------------------- + } + + return true; + }, + 0 + ); + + vis->length_updater_ = [](VariableInstructionSet &, InstructionContext &ic, BitArray &ba) { + std::function updateRV64IMACFDInstrLength = + [](InstructionContext &ic, etiss_uint32 opRd) { + ic.instr_width_fully_evaluated_ = true; + ic.is_not_default_width_ = true; + if (opRd == 0x3f) + ic.instr_width_ = 64; + else if ((opRd & 0x3f) == 0x1f) + ic.instr_width_ = 48; + else if (((opRd & 0x1f) >= 0x3) && ((opRd & 0x1f) < 0x1f)) + ic.instr_width_ = 32; + else if(opRd == 0x7f) /* P-Extension instructions */ + ic.instr_width_ = 32; + else if ((opRd & 0x3) != 0x3) + ic.instr_width_ = 16; + else + // This might happen when code is followed by data. + ic.is_not_default_width_ = false; + }; + + BitArrayRange op(6, 0); + etiss_uint32 opRd = op.read(ba); + + /*BitArrayRange fullOp(ba.byteCount()*8-1,0); + etiss_uint32 fullOpRd = fullOp.read(ba); + + std::stringstream ss; + ss << "Byte count: " << ba.byteCount()<< std::endl; + ss << "opcode: 0x" <= 0x3) || ((opRd & 0x1f) < 0x1f)) || (opRd == 0)) + { + ic.is_not_default_width_ = false; + break; + } + else if(opRd == 0x7f) /* P-Extension instructions */ + { + updateRV64IMACFDInstrLength(ic, opRd); + break; + } + else + { + updateRV64IMACFDInstrLength(ic, opRd); + break; + } + case 6: + if (((opRd & 0x3f) == 0x1f) || (opRd == 0)) + { + ic.is_not_default_width_ = false; + break; + } + else + { + updateRV64IMACFDInstrLength(ic, opRd); + break; + } + case 8: + if ((opRd == 0x3f) || (opRd == 0)) + { + ic.is_not_default_width_ = false; + break; + } + else + { + updateRV64IMACFDInstrLength(ic, opRd); + break; + } + default: + // This might happen when code is followed by data. + ic.is_not_default_width_ = false; + } + }; + +} + +/** + @brief This function is called whenever a data is read from memory + + @details Target architecture may have inconsistent endianess. Data read from memory is buffered, and this function + is called to alter sequence of buffered data so that the inconsistent endianess is compensated. + Example for ARMv6M: + void * ptr = ba.internalBuffer(); + if (ba.byteCount() == 2) + { + *((uint32_t*)ptr) = ((uint16_t)(*((uint8_t*)ptr))) | ((uint16_t)(*(((uint8_t*)ptr)+1)) << 8); + } + else if (ba.byteCount() == 4) + { + *((uint32_t*)ptr) = ((((uint32_t)(*((uint8_t*)ptr))) | ((uint32_t)(*(((uint8_t*)ptr)+1)) << 8)) << 16) | ((uint32_t)(*(((uint8_t*)ptr)+2)) ) | ((uint32_t)(*(((uint8_t*)ptr)+3)) << 8); + } + else + { + etiss::log(etiss::FATALERROR,"Endianess cannot be handled",ba.byteCount()); + } + + @attention Default endianess: little-endian + +*/ +void RV64IMACFDArch::compensateEndianess(ETISS_CPU * cpu, etiss::instr::BitArray & ba) const +{ + /************************************************************************** + * Endianess compensation * + ***************************************************************************/ +} + +std::shared_ptr RV64IMACFDArch::getVirtualStruct(ETISS_CPU * cpu) +{ + auto ret = etiss::VirtualStruct::allocate( + cpu, + [] (etiss::VirtualStruct::Field*f) { + delete f; + } + ); + + for (uint32_t i = 0; i < 32; ++i){ + ret->addField(new RegField_RV64IMACFD(*ret,i)); + } + + ret->addField(new pcField_RV64IMACFD(*ret)); + return ret; +} + +/** + @brief If interrupt handling is expected, vector table could be provided to support interrupt triggering + + @details Interrupt vector table is used to inform the core whenever an edge/level triggered interrupt + incoming. The content of interrupt vector could be a special register or standalone interrupt + lines. +*/ +etiss::InterruptVector * RV64IMACFDArch::createInterruptVector(ETISS_CPU * cpu) +{ + if (cpu == 0) + return 0; + + std::vector vec; + std::vector mask; + + vec.push_back(&((RV64IMACFD*)cpu)->MIP); + mask.push_back(&((RV64IMACFD*)cpu)->MIE); + + return new etiss::MappedInterruptVector(vec, mask); +} + +void RV64IMACFDArch::deleteInterruptVector(etiss::InterruptVector * vec, ETISS_CPU * cpu) +{ + delete vec; +} + +etiss::InterruptEnable* RV64IMACFDArch::createInterruptEnable(ETISS_CPU* cpu) { + return new etiss::MappedInterruptEnable(&((RV64IMACFD*)cpu)->MSTATUS, 15); +} + +void RV64IMACFDArch::deleteInterruptEnable(etiss::InterruptEnable* en, ETISS_CPU* cpu) { + delete en; +} diff --git a/ArchImpl/RV64IMACFD/RV64IMACFDArchSpecificImp.h b/ArchImpl/RV64IMACFD/RV64IMACFDArchSpecificImp.h new file mode 100644 index 0000000000..f3a623cc27 --- /dev/null +++ b/ArchImpl/RV64IMACFD/RV64IMACFDArchSpecificImp.h @@ -0,0 +1,82 @@ +/** + * Generated on Tue, 28 Nov 2023 09:45:19 +0100. + * + * This file contains the architecture specific header for the RV64IMACFD + * core architecture. + * + * WARNING: This file contains user-added code, be mindful when overwriting this with + * generated code! + */ + +#ifndef ETISS_RV64IMACFDArch_RV64IMACFDARCHSPECIFICIMP_H_ +#define ETISS_RV64IMACFDArch_RV64IMACFDARCHSPECIFICIMP_H_ + +/** + @brief VirtualStruct for RV64IMACFD architecture to faciliate register acess + + @details VirtualStruct enables user to access certain register via their name without knowning ETISS hierarchy of a core. + Further fiels might be needed to enable gdbserver etc. + +*/ +class RegField_RV64IMACFD : public etiss::VirtualStruct::Field{ +private: + const unsigned gprid_; +public: + RegField_RV64IMACFD(etiss::VirtualStruct & parent,unsigned gprid) + : Field(parent, + std::string("X")+etiss::toString(gprid), + std::string("X")+etiss::toString(gprid), + R|W, + 8 + ), + gprid_(gprid) + {} + + RegField_RV64IMACFD(etiss::VirtualStruct & parent, std::string name, unsigned gprid) + : Field(parent, + name, + name, + R|W, + 8 + ), + gprid_(gprid) + {} + + virtual ~RegField_RV64IMACFD(){} + +protected: + virtual uint64_t _read() const { + return (uint64_t) *((RV64IMACFD*)parent_.structure_)->X[gprid_]; + } + + virtual void _write(uint64_t val) { + etiss::log(etiss::VERBOSE, "write to ETISS cpu state", name_, val); + *((RV64IMACFD*)parent_.structure_)->X[gprid_] = (etiss_uint64) val; + } +}; + +class pcField_RV64IMACFD : public etiss::VirtualStruct::Field{ +public: + pcField_RV64IMACFD(etiss::VirtualStruct & parent) + : Field(parent, + "instructionPointer", + "instructionPointer", + R|W, + 8 + ) + {} + + virtual ~pcField_RV64IMACFD(){} + +protected: + virtual uint64_t _read() const { + return (uint64_t) ((ETISS_CPU *)parent_.structure_)->instructionPointer; + } + + virtual void _write(uint64_t val) { + etiss::log(etiss::VERBOSE, "write to ETISS cpu state", name_, val); + ((ETISS_CPU *)parent_.structure_)->instructionPointer = (etiss_uint64) val; + } +}; + +#endif \ No newline at end of file diff --git a/ArchImpl/RV64IMACFD/RV64IMACFDFuncs.c b/ArchImpl/RV64IMACFD/RV64IMACFDFuncs.c new file mode 100644 index 0000000000..927e9a00f0 --- /dev/null +++ b/ArchImpl/RV64IMACFD/RV64IMACFDFuncs.c @@ -0,0 +1,371 @@ +/** + * Generated on Tue, 28 Nov 2023 09:45:19 +0100. + * + * This file contains the function implementations for the RV64IMACFD core architecture. + */ + +#include "RV64IMACFDFuncs.h" + +etiss_uint8 RV64IMACFD_extension_enabled(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_int8 extension) +{ +{ // block +return (*((RV64IMACFD*)cpu)->CSR[769LL] >> (extension - 65ULL)) & 1ULL; +} // block +} + +etiss_uint8 RV64IMACFD_get_rm(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint8 rm) +{ +{ // block +if (rm == 7ULL) { // conditional +rm = ((((((RV64IMACFD*)cpu)->FCSR) >> (5ULL)) & 7)) & 0x7; +} // conditional +if (rm > 4ULL) { // conditional +RV64IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 2LL); +} // conditional +return rm; +} // block +} + +etiss_uint64 RV64IMACFD_sstatus_mask(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers) +{ +{ // block +etiss_uint64 mask = 0ULL; +if (RV64IMACFD_extension_enabled(cpu, system, plugin_pointers, 83ULL)) { // conditional +{ // block +mask = mask | 5767458ULL; +if (RV64IMACFD_extension_enabled(cpu, system, plugin_pointers, 86ULL)) { // conditional +mask = mask | 1536LL; +} // conditional +if (RV64IMACFD_extension_enabled(cpu, system, plugin_pointers, 70ULL)) { // conditional +mask = mask | 24576LL; +} // conditional +if (RV64IMACFD_extension_enabled(cpu, system, plugin_pointers, 88ULL)) { // conditional +mask = mask | 98304LL; +} // conditional +if ((RV64IMACFD_get_field(*((RV64IMACFD*)cpu)->CSR[384LL], 17293822569102704640ULL))) { // conditional +mask = mask | 262144LL; +} // conditional +} // block +} // conditional +return mask; +} // block +} + +etiss_uint64 RV64IMACFD_mstatus_mask(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers) +{ +{ // block +etiss_uint64 mask = 6280ULL; +return mask | RV64IMACFD_sstatus_mask(cpu, system, plugin_pointers); +} // block +} + +etiss_uint64 RV64IMACFD_csr_read(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint32 csr) +{ +{ // block +if (csr == 1LL) { // conditional +return *((RV64IMACFD*)cpu)->CSR[3LL] & 31ULL; +} // conditional +if (csr == 2LL) { // conditional +return (*((RV64IMACFD*)cpu)->CSR[3LL] >> 5ULL) & 7ULL; +} // conditional +if (csr == 3072LL) { // conditional +return etiss_get_cycles(cpu, system, plugin_pointers); +} // conditional +if (csr == 3200LL) { // conditional +return etiss_get_cycles(cpu, system, plugin_pointers) >> 32ULL; +} // conditional +if (csr == 3073LL) { // conditional +return etiss_get_time(); +} // conditional +if (csr == 3201LL) { // conditional +return etiss_get_time() >> 32ULL; +} // conditional +if (csr == 3074LL) { // conditional +return etiss_get_instret(cpu, system, plugin_pointers); +} // conditional +if (csr == 3202LL) { // conditional +return etiss_get_instret(cpu, system, plugin_pointers) >> 32ULL; +} // conditional +if (csr == 768LL || csr == 256LL) { // conditional +return *((RV64IMACFD*)cpu)->CSR[768LL] | 8589934592ULL | 34359738368ULL; +} // conditional +if (csr == 769LL) { // conditional +return (((2ULL) << 62) | ((((*((RV64IMACFD*)cpu)->CSR[769LL]) >> (0ULL)) & 4611686018427387903))); +} // conditional +return *((RV64IMACFD*)cpu)->CSR[csr]; +} // block +} + +void RV64IMACFD_csr_write(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint32 csr, etiss_uint64 val) +{ +{ // block +if (csr == 1LL) { // conditional +*((RV64IMACFD*)cpu)->CSR[3LL] = (*((RV64IMACFD*)cpu)->CSR[3LL] & 224ULL) | (val & 31ULL); +} // conditional + else if (csr == 2LL) { // conditional +*((RV64IMACFD*)cpu)->CSR[3LL] = ((val & 7ULL) << 5ULL) | (*((RV64IMACFD*)cpu)->CSR[3LL] & 31ULL); +} // conditional + else if (csr == 3LL) { // conditional +*((RV64IMACFD*)cpu)->CSR[3LL] = val & 255ULL; +} // conditional + else if (csr == 768LL) { // conditional +*((RV64IMACFD*)cpu)->CSR[768LL] = val & RV64IMACFD_mstatus_mask(cpu, system, plugin_pointers); +} // conditional + else if (csr == 256LL) { // conditional +*((RV64IMACFD*)cpu)->CSR[768LL] = val & RV64IMACFD_sstatus_mask(cpu, system, plugin_pointers); +} // conditional + else if (csr != 769LL) { // conditional +*((RV64IMACFD*)cpu)->CSR[csr] = val; +} // conditional +} // block +} + +etiss_uint64 RV64IMACFD_get_field(etiss_uint64 reg, etiss_uint64 mask) +{ +{ // block +if (!(mask)) { // conditional +return 0ULL; +} // conditional +return (reg & mask) / (mask & ~((mask << 1ULL))); +} // block +} + +etiss_uint64 RV64IMACFD_set_field(etiss_uint64 reg, etiss_uint64 mask, etiss_uint64 val) +{ +{ // block +return ((reg & ~(mask)) | ((val * (mask & ~((mask << 1ULL)))) & mask)); +} // block +} + +etiss_uint8 RV64IMACFD_ctz(etiss_uint64 val) +{ +{ // block +if (!(val)) { // conditional +return 0ULL; +} // conditional +etiss_uint8 res = 0ULL; +if ((val << 32ULL) == 0ULL) { // conditional +{ // block +res = res + 32ULL; +val = val >> 32ULL; +} // block +} // conditional +if ((val << 48ULL) == 0ULL) { // conditional +{ // block +res = res + 16ULL; +val = val >> 16ULL; +} // block +} // conditional +if ((val << 56ULL) == 0ULL) { // conditional +{ // block +res = res + 8ULL; +val = val >> 8ULL; +} // block +} // conditional +if ((val << 60ULL) == 0ULL) { // conditional +{ // block +res = res + 4ULL; +val = val >> 4ULL; +} // block +} // conditional +if ((val << 62ULL) == 0ULL) { // conditional +{ // block +res = res + 2ULL; +val = val >> 2ULL; +} // block +} // conditional +if ((val << 63ULL) == 0ULL) { // conditional +{ // block +res = res + 1ULL; +val = val >> 1ULL; +} // block +} // conditional +return res; +} // block +} + +void RV64IMACFD_raise(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_int32 irq, etiss_uint64 mcause) +{ +cpu->return_pending = 1; +cpu->exception = 0; +{ // block +etiss_uint64 epc = cpu->instructionPointer; +etiss_uint64 deleg = 0ULL; +etiss_uint64 vector = 0ULL; +etiss_uint64 bit = mcause; +etiss_int32 irq2 = (mcause & 9223372036854775808ULL) != 0ULL; +if (irq2) { // conditional +{ // block +deleg = ((((RV64IMACFD*)cpu)->PRIV <= 1LL)) ? (*((RV64IMACFD*)cpu)->CSR[771LL]) : (0ULL); +bit = bit & 9223372036854775807ULL; +} // block +} // conditional +else { // conditional +{ // block +deleg = ((((RV64IMACFD*)cpu)->PRIV <= 1LL)) ? (*((RV64IMACFD*)cpu)->CSR[770LL]) : (0ULL); +} // block +} // conditional +if (((RV64IMACFD*)cpu)->PRIV <= 1LL && (deleg >> bit) & 1ULL) { // conditional +{ // block +vector = ((*((RV64IMACFD*)cpu)->CSR[261LL] & 1ULL) && irq2) ? (bit * 4ULL) : (0ULL); +cpu->nextPc = (*((RV64IMACFD*)cpu)->CSR[261LL] & -2LL) + vector; +*((RV64IMACFD*)cpu)->CSR[321LL] = epc; +*((RV64IMACFD*)cpu)->CSR[322LL] = mcause; +etiss_uint64 s = RV64IMACFD_csr_read(cpu, system, plugin_pointers, 256LL); +s = RV64IMACFD_set_field(s, 32LL, RV64IMACFD_get_field(s, 2LL)); +s = RV64IMACFD_set_field(s, 256LL, ((RV64IMACFD*)cpu)->PRIV); +s = RV64IMACFD_set_field(s, 2LL, 0ULL); +RV64IMACFD_csr_write(cpu, system, plugin_pointers, 256LL, s); +((RV64IMACFD*)cpu)->PRIV = (1LL) & 0x7; +} // block +} // conditional +else { // conditional +{ // block +vector = ((*((RV64IMACFD*)cpu)->CSR[773LL] & 1ULL) && irq2) ? (bit * 4ULL) : (0ULL); +cpu->nextPc = (*((RV64IMACFD*)cpu)->CSR[773LL] & -2LL) + vector; +*((RV64IMACFD*)cpu)->CSR[833LL] = epc; +*((RV64IMACFD*)cpu)->CSR[834LL] = mcause; +etiss_uint64 s = RV64IMACFD_csr_read(cpu, system, plugin_pointers, 768LL); +s = RV64IMACFD_set_field(s, 128LL, RV64IMACFD_get_field(s, 8LL)); +s = RV64IMACFD_set_field(s, 6144LL, ((RV64IMACFD*)cpu)->PRIV); +s = RV64IMACFD_set_field(s, 8LL, 0ULL); +RV64IMACFD_csr_write(cpu, system, plugin_pointers, 768LL, s); +((RV64IMACFD*)cpu)->PRIV = (3LL) & 0x7; +} // block +} // conditional +} // block +} + +void RV64IMACFD_translate_exc_code(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_int32 cause) +{ +{ // block +etiss_uint64 code = 0ULL; +if (cause == -2147483648LL) { // conditional +return; +} // conditional + else if (cause == -5LL) { // conditional +code = 5LL; +} // conditional + else if (cause == -14LL) { // conditional +code = 13LL; +} // conditional + else if (cause == -6LL) { // conditional +code = 7LL; +} // conditional + else if (cause == -15LL) { // conditional +code = 15LL; +} // conditional + else if (cause == -7LL) { // conditional +code = 1LL; +} // conditional + else if (cause == -9LL) { // conditional +{ // block +code = RV64IMACFD_calc_irq_mcause(cpu, system, plugin_pointers); +if (!(code)) { // conditional +return; +} // conditional +} // block +} // conditional +else { // conditional +code = 2LL; +} // conditional +RV64IMACFD_raise(cpu, system, plugin_pointers, 0ULL, code); +} // block +} + +etiss_uint64 RV64IMACFD_calc_irq_mcause(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers) +{ +{ // block +etiss_uint64 pending_interrupts = *((RV64IMACFD*)cpu)->CSR[772LL] & *((RV64IMACFD*)cpu)->CSR[836LL]; +if (!(pending_interrupts)) { // conditional +return 0ULL; +} // conditional +etiss_uint64 mie = RV64IMACFD_get_field(*((RV64IMACFD*)cpu)->CSR[768LL], 8LL); +etiss_uint64 m_enabled = ((RV64IMACFD*)cpu)->PRIV < 3LL || (((RV64IMACFD*)cpu)->PRIV == 3LL && mie); +etiss_uint64 enabled_interrupts = pending_interrupts & ~(*((RV64IMACFD*)cpu)->CSR[771LL]) & -(m_enabled); +if (enabled_interrupts == 0ULL) { // conditional +{ // block +etiss_uint64 deleg = *((RV64IMACFD*)cpu)->CSR[771LL]; +etiss_uint64 sie = RV64IMACFD_get_field(RV64IMACFD_csr_read(cpu, system, plugin_pointers, 256LL), 2LL); +etiss_uint64 s_enabled = ((RV64IMACFD*)cpu)->PRIV < 1LL || (((RV64IMACFD*)cpu)->PRIV == 1LL && sie); +enabled_interrupts = pending_interrupts & deleg & -(s_enabled); +} // block +} // conditional +if (enabled_interrupts) { // conditional +{ // block +if (enabled_interrupts >> 12ULL) { // conditional +enabled_interrupts = enabled_interrupts >> 12ULL << 12ULL; +} // conditional + else if (enabled_interrupts & 2048LL) { // conditional +enabled_interrupts = 2048LL; +} // conditional + else if (enabled_interrupts & 8LL) { // conditional +enabled_interrupts = 8LL; +} // conditional + else if (enabled_interrupts & 128LL) { // conditional +enabled_interrupts = 128LL; +} // conditional + else if (enabled_interrupts & 512LL) { // conditional +enabled_interrupts = 512LL; +} // conditional + else if (enabled_interrupts & 2LL) { // conditional +enabled_interrupts = 2LL; +} // conditional + else if (enabled_interrupts & 32LL) { // conditional +enabled_interrupts = 32LL; +} // conditional + else if (enabled_interrupts & 8192LL) { // conditional +enabled_interrupts = 8192LL; +} // conditional + else if (enabled_interrupts & 1024LL) { // conditional +enabled_interrupts = 1024LL; +} // conditional + else if (enabled_interrupts & 4LL) { // conditional +enabled_interrupts = 4LL; +} // conditional + else if (enabled_interrupts & 64LL) { // conditional +enabled_interrupts = 64LL; +} // conditional +else { // conditional +return 0ULL; +} // conditional +return 9223372036854775808ULL | RV64IMACFD_ctz(enabled_interrupts); +} // block +} // conditional +return 0ULL; +} // block +} + +void RV64IMACFD_check_irq(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers) +{ +{ // block +etiss_uint64 irq_mcause = RV64IMACFD_calc_irq_mcause(cpu, system, plugin_pointers); +if (irq_mcause) { // conditional +RV64IMACFD_raise(cpu, system, plugin_pointers, 1ULL, irq_mcause); +} // conditional +} // block +} + +etiss_int64 RV64IMACFD_mulh(etiss_int64 x, etiss_int64 y) +{ +{ // block +etiss_int128 res = (etiss_int128)(x) * (etiss_int128)(y); +return (etiss_int64)((res >> 64ULL)); +} // block +} + +etiss_int64 RV64IMACFD_mulhsu(etiss_int64 x, etiss_uint64 y) +{ +{ // block +etiss_int128 res = (etiss_int128)(x) * (etiss_uint128)(y); +return (etiss_int64)((res >> 64ULL)); +} // block +} + +etiss_uint64 RV64IMACFD_mulhu(etiss_uint64 x, etiss_uint64 y) +{ +{ // block +etiss_uint128 res = (etiss_uint128)(x) * (etiss_uint128)(y); +return (etiss_uint64)((res >> 64ULL)); +} // block +} diff --git a/ArchImpl/RV64IMACFD/RV64IMACFDFuncs.h b/ArchImpl/RV64IMACFD/RV64IMACFDFuncs.h new file mode 100644 index 0000000000..98d356fbcd --- /dev/null +++ b/ArchImpl/RV64IMACFD/RV64IMACFDFuncs.h @@ -0,0 +1,124 @@ +/** + * Generated on Tue, 28 Nov 2023 09:45:19 +0100. + * + * This file contains the function prototypes for the RV64IMACFD core architecture. + */ + +#ifndef __RV64IMACFD_FUNCS_H +#define __RV64IMACFD_FUNCS_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "RV64IMACFD.h" +#include "etiss/jit/CPU.h" +#include "etiss/jit/System.h" +#include "etiss/jit/ReturnCode.h" + + +void leave(etiss_int32 priv_lvl); + +void wait(etiss_int32 flag); + +etiss_uint8 RV64IMACFD_extension_enabled(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_int8 extension); + +etiss_uint32 fadd_s(etiss_uint32, etiss_uint32, etiss_uint8); + +etiss_uint32 fsub_s(etiss_uint32, etiss_uint32, etiss_uint8); + +etiss_uint32 fmul_s(etiss_uint32, etiss_uint32, etiss_uint8); + +etiss_uint32 fdiv_s(etiss_uint32, etiss_uint32, etiss_uint8); + +etiss_uint32 fmadd_s(etiss_uint32, etiss_uint32, etiss_uint32, etiss_uint32, etiss_uint8); + +etiss_uint32 fsel_s(etiss_uint32, etiss_uint32, etiss_uint32); + +etiss_uint32 fsqrt_s(etiss_uint32, etiss_uint8); + +etiss_uint32 fcmp_s(etiss_uint32, etiss_uint32, etiss_uint32); + +etiss_uint32 fcvt_s(etiss_uint32, etiss_uint32, etiss_uint8); + +etiss_uint64 fcvt_32_64(etiss_uint32, etiss_uint32, etiss_uint8); + +etiss_uint32 fcvt_64_32(etiss_uint64, etiss_uint32, etiss_uint8); + +etiss_uint32 unbox_s(etiss_uint64); + +etiss_uint32 fclass_s(etiss_uint32); + +etiss_uint32 fget_flags(); + +etiss_uint8 RV64IMACFD_get_rm(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint8 rm); + +etiss_uint64 fadd_d(etiss_uint64, etiss_uint64, etiss_uint8); + +etiss_uint64 fsub_d(etiss_uint64, etiss_uint64, etiss_uint8); + +etiss_uint64 fmul_d(etiss_uint64, etiss_uint64, etiss_uint8); + +etiss_uint64 fdiv_d(etiss_uint64, etiss_uint64, etiss_uint8); + +etiss_uint64 fmadd_d(etiss_uint64, etiss_uint64, etiss_uint64, etiss_uint32, etiss_uint8); + +etiss_uint64 fsel_d(etiss_uint64, etiss_uint64, etiss_uint32); + +etiss_uint64 fsqrt_d(etiss_uint64, etiss_uint8); + +etiss_uint64 fcmp_d(etiss_uint64, etiss_uint64, etiss_uint32); + +etiss_uint64 fcvt_d(etiss_uint64, etiss_uint32, etiss_uint8); + +etiss_uint32 fconv_d2f(etiss_uint64, etiss_uint8); + +etiss_uint64 fconv_f2d(etiss_uint32, etiss_uint8); + +etiss_uint64 unbox_d(etiss_uint64); + +etiss_uint64 fclass_d(etiss_uint64); + +etiss_uint64 etiss_get_cycles(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers); + +etiss_uint64 etiss_get_time(); + +etiss_uint64 etiss_get_instret(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers); + +etiss_uint64 RV64IMACFD_sstatus_mask(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers); + +etiss_uint64 RV64IMACFD_mstatus_mask(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers); + +etiss_uint64 RV64IMACFD_csr_read(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint32 csr); + +void RV64IMACFD_csr_write(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint32 csr, etiss_uint64 val); + +etiss_uint64 RV64IMACFD_get_field(etiss_uint64 reg, etiss_uint64 mask); + +etiss_uint64 RV64IMACFD_set_field(etiss_uint64 reg, etiss_uint64 mask, etiss_uint64 val); + +etiss_uint8 RV64IMACFD_ctz(etiss_uint64 val); + +void RV64IMACFD_raise(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_int32 irq, etiss_uint64 mcause); + +void RV64IMACFD_translate_exc_code(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_int32 cause); + +etiss_uint64 RV64IMACFD_calc_irq_mcause(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers); + +void RV64IMACFD_check_irq(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers); + +etiss_int64 RV64IMACFD_mulh(etiss_int64 x, etiss_int64 y); + +etiss_int64 RV64IMACFD_mulhsu(etiss_int64 x, etiss_uint64 y); + +etiss_uint64 RV64IMACFD_mulhu(etiss_uint64 x, etiss_uint64 y); + +etiss_uint8 etiss_semihost_enabled(); + +etiss_int64 etiss_semihost(ETISS_CPU * const cpu, ETISS_System * const system, void * const * const plugin_pointers, etiss_uint32 XLEN, etiss_uint64 operation, etiss_uint64 parameter); + +#ifdef __cplusplus +} +#endif + +#endif \ No newline at end of file diff --git a/ArchImpl/RV64IMACFD/RV64IMACFDGDBCore.h b/ArchImpl/RV64IMACFD/RV64IMACFDGDBCore.h new file mode 100644 index 0000000000..be39a0aacb --- /dev/null +++ b/ArchImpl/RV64IMACFD/RV64IMACFDGDBCore.h @@ -0,0 +1,70 @@ +/** + * Generated on Tue, 28 Nov 2023 09:45:19 +0100. + * + * This file contains the GDBCore adapter for the RV64IMACFD core architecture. + * + * WARNING: This file contains user-added code, be mindful when overwriting this with + * generated code! + */ + +#ifndef ETISS_RV64IMACFDArch_RV64IMACFDGDBCORE_H_ +#define ETISS_RV64IMACFDArch_RV64IMACFDGDBCORE_H_ + +#include "etiss/IntegratedLibrary/gdb/GDBCore.h" +#include + +/** + @brief This class is the brige between RV64IMACFD architecture and gdbserver + + @details Gdbserver integrated in ETISS calls GDBCore to read/write registers via virtualStrruct + The index in mapRegister() should strictly follow the RV64IMACFD gdb tool defined register + order. Because gdbserver will send raw register data sequentially in strict order over + RSP ->TCP/IP ->RSP protocal + + Check the order with gdb command: + $(gdb) info all-registers + which lists all registers supported and its order. + + By default only general purpose register and instruction pointer are supported. Further + Special Function Register/Control and Status Register could be added manually. Meanwhile + virtualStruct in RV64IMACFDArch.cpp should be modified as well as well + +*/ +class RV64IMACFDGDBCore : public etiss::plugin::gdb::GDBCore { +public: + std::string mapRegister(unsigned index){ + if (index < 32){ + std::stringstream ss; + ss << "X" << index; + return ss.str(); + } + switch (index){ + case 32: + return "instructionPointer"; + /************************************************************************** + * Further register should be added here to send data over gdbserver * + ***************************************************************************/ + } + return ""; + } + + unsigned mapRegister(std::string name){ + return INVALIDMAPPING; + } + + unsigned mappedRegisterCount(){ + // Modify according to sent register number + return 33; + } + + etiss::uint64 getInstructionPointer(ETISS_CPU * cpu){ + return cpu->instructionPointer; + } + + bool isLittleEndian(){ + // Modify according to RV64IMACFD manual + return true; + } +}; + +#endif diff --git a/ArchImpl/RV64IMACFD/RV64IMACFDInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFDInstr.cpp new file mode 100644 index 0000000000..49c27e824f --- /dev/null +++ b/ArchImpl/RV64IMACFD/RV64IMACFDInstr.cpp @@ -0,0 +1,13 @@ +/** + * Generated on Tue, 28 Nov 2023 09:45:19 +0100. + * + * This file contains the instruction behavior models of the default + * instruction set for the RV64IMACFD core architecture. + */ + +#include "RV64IMACFDArch.h" +#include "RV64IMACFDFuncs.h" + +using namespace etiss; +using namespace etiss::instr; + diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32AInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32AInstr.cpp new file mode 100644 index 0000000000..23e3ebdc0b --- /dev/null +++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32AInstr.cpp @@ -0,0 +1,1100 @@ +/** + * Generated on Tue, 28 Nov 2023 09:45:19 +0100. + * + * This file contains the instruction behavior models of the RV32A + * instruction set for the RV64IMACFD core architecture. + */ + +#include "RV64IMACFDArch.h" +#include "RV64IMACFDFuncs.h" + +using namespace etiss; +using namespace etiss::instr; + + +// AMOSWAPW -------------------------------------------------------------------- +static InstructionDefinition amoswapw_rd_rs1_rs2_rl_aq ( + ISA32_RV64IMACFD, + "amoswapw", + (uint32_t) 0x800202f, + (uint32_t) 0xf800707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; +etiss_uint8 rl = 0; +static BitArrayRange R_rl_0(25, 25); +rl += R_rl_0.read(ba) << 0; +etiss_uint8 aq = 0; +static BitArrayRange R_aq_0(26, 26); +aq += R_aq_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//AMOSWAPW\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n"; +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "etiss_uint32 mem_val_0;\n"; +cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int64)(((etiss_int32)(mem_val_0)));\n"; +} // conditional +cp.code() += "etiss_uint32 mem_val_1;\n"; +cp.code() += "mem_val_1 = (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n"; +cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); + + cp.code() = std::string("//AMOSWAPW\n"); + +// ----------------------------------------------------------------------------- +cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n"; +// ----------------------------------------------------------------------------- + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; +etiss_uint8 rl = 0; +static BitArrayRange R_rl_0(25, 25); +rl += R_rl_0.read(ba) << 0; +etiss_uint8 aq = 0; +static BitArrayRange R_aq_0(26, 26); +aq += R_aq_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "amoswapw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + " | rl=" + std::to_string(rl) + " | aq=" + std::to_string(aq) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// AMOADDW --------------------------------------------------------------------- +static InstructionDefinition amoaddw_rd_rs1_rs2_rl_aq ( + ISA32_RV64IMACFD, + "amoaddw", + (uint32_t) 0x00202f, + (uint32_t) 0xf800707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; +etiss_uint8 rl = 0; +static BitArrayRange R_rl_0(25, 25); +rl += R_rl_0.read(ba) << 0; +etiss_uint8 aq = 0; +static BitArrayRange R_aq_0(26, 26); +aq += R_aq_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//AMOADDW\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n"; +cp.code() += "etiss_uint32 mem_val_0;\n"; +cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "etiss_int32 res1 = mem_val_0;\n"; +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res1;\n"; +} // conditional +cp.code() += "etiss_uint32 res2 = res1 + *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n"; +cp.code() += "etiss_uint32 mem_val_1;\n"; +cp.code() += "mem_val_1 = res2;\n"; +cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); + + cp.code() = std::string("//AMOADDW\n"); + +// ----------------------------------------------------------------------------- +cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n"; +// ----------------------------------------------------------------------------- + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; +etiss_uint8 rl = 0; +static BitArrayRange R_rl_0(25, 25); +rl += R_rl_0.read(ba) << 0; +etiss_uint8 aq = 0; +static BitArrayRange R_aq_0(26, 26); +aq += R_aq_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "amoaddw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + " | rl=" + std::to_string(rl) + " | aq=" + std::to_string(aq) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// AMOXORW --------------------------------------------------------------------- +static InstructionDefinition amoxorw_rd_rs1_rs2_rl_aq ( + ISA32_RV64IMACFD, + "amoxorw", + (uint32_t) 0x2000202f, + (uint32_t) 0xf800707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; +etiss_uint8 rl = 0; +static BitArrayRange R_rl_0(25, 25); +rl += R_rl_0.read(ba) << 0; +etiss_uint8 aq = 0; +static BitArrayRange R_aq_0(26, 26); +aq += R_aq_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//AMOXORW\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n"; +cp.code() += "etiss_uint32 mem_val_0;\n"; +cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "etiss_int32 res1 = mem_val_0;\n"; +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res1;\n"; +} // conditional +cp.code() += "etiss_uint32 res2 = res1 ^ *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n"; +cp.code() += "etiss_uint32 mem_val_1;\n"; +cp.code() += "mem_val_1 = res2;\n"; +cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); + + cp.code() = std::string("//AMOXORW\n"); + +// ----------------------------------------------------------------------------- +cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n"; +// ----------------------------------------------------------------------------- + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; +etiss_uint8 rl = 0; +static BitArrayRange R_rl_0(25, 25); +rl += R_rl_0.read(ba) << 0; +etiss_uint8 aq = 0; +static BitArrayRange R_aq_0(26, 26); +aq += R_aq_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "amoxorw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + " | rl=" + std::to_string(rl) + " | aq=" + std::to_string(aq) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// AMOANDW --------------------------------------------------------------------- +static InstructionDefinition amoandw_rd_rs1_rs2_rl_aq ( + ISA32_RV64IMACFD, + "amoandw", + (uint32_t) 0x6000202f, + (uint32_t) 0xf800707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; +etiss_uint8 rl = 0; +static BitArrayRange R_rl_0(25, 25); +rl += R_rl_0.read(ba) << 0; +etiss_uint8 aq = 0; +static BitArrayRange R_aq_0(26, 26); +aq += R_aq_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//AMOANDW\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n"; +cp.code() += "etiss_uint32 mem_val_0;\n"; +cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "etiss_int32 res1 = mem_val_0;\n"; +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res1;\n"; +} // conditional +cp.code() += "etiss_uint32 res2 = res1 & *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n"; +cp.code() += "etiss_uint32 mem_val_1;\n"; +cp.code() += "mem_val_1 = res2;\n"; +cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); + + cp.code() = std::string("//AMOANDW\n"); + +// ----------------------------------------------------------------------------- +cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n"; +// ----------------------------------------------------------------------------- + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; +etiss_uint8 rl = 0; +static BitArrayRange R_rl_0(25, 25); +rl += R_rl_0.read(ba) << 0; +etiss_uint8 aq = 0; +static BitArrayRange R_aq_0(26, 26); +aq += R_aq_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "amoandw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + " | rl=" + std::to_string(rl) + " | aq=" + std::to_string(aq) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// AMOORW ---------------------------------------------------------------------- +static InstructionDefinition amoorw_rd_rs1_rs2_rl_aq ( + ISA32_RV64IMACFD, + "amoorw", + (uint32_t) 0x4000202f, + (uint32_t) 0xf800707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; +etiss_uint8 rl = 0; +static BitArrayRange R_rl_0(25, 25); +rl += R_rl_0.read(ba) << 0; +etiss_uint8 aq = 0; +static BitArrayRange R_aq_0(26, 26); +aq += R_aq_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//AMOORW\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n"; +cp.code() += "etiss_uint32 mem_val_0;\n"; +cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "etiss_int32 res1 = mem_val_0;\n"; +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res1;\n"; +} // conditional +cp.code() += "etiss_uint32 res2 = res1 | *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n"; +cp.code() += "etiss_uint32 mem_val_1;\n"; +cp.code() += "mem_val_1 = res2;\n"; +cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); + + cp.code() = std::string("//AMOORW\n"); + +// ----------------------------------------------------------------------------- +cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n"; +// ----------------------------------------------------------------------------- + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; +etiss_uint8 rl = 0; +static BitArrayRange R_rl_0(25, 25); +rl += R_rl_0.read(ba) << 0; +etiss_uint8 aq = 0; +static BitArrayRange R_aq_0(26, 26); +aq += R_aq_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "amoorw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + " | rl=" + std::to_string(rl) + " | aq=" + std::to_string(aq) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// AMOMINW --------------------------------------------------------------------- +static InstructionDefinition amominw_rd_rs1_rs2_rl_aq ( + ISA32_RV64IMACFD, + "amominw", + (uint32_t) 0x8000202f, + (uint32_t) 0xf800707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; +etiss_uint8 rl = 0; +static BitArrayRange R_rl_0(25, 25); +rl += R_rl_0.read(ba) << 0; +etiss_uint8 aq = 0; +static BitArrayRange R_aq_0(26, 26); +aq += R_aq_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//AMOMINW\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n"; +cp.code() += "etiss_uint32 mem_val_0;\n"; +cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "etiss_int32 res1 = mem_val_0;\n"; +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res1;\n"; +} // conditional +cp.code() += "etiss_uint32 res2 = (res1 > (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL])) ? (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) : (res1);\n"; +cp.code() += "etiss_uint32 mem_val_1;\n"; +cp.code() += "mem_val_1 = res2;\n"; +cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); + + cp.code() = std::string("//AMOMINW\n"); + +// ----------------------------------------------------------------------------- +cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n"; +// ----------------------------------------------------------------------------- + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; +etiss_uint8 rl = 0; +static BitArrayRange R_rl_0(25, 25); +rl += R_rl_0.read(ba) << 0; +etiss_uint8 aq = 0; +static BitArrayRange R_aq_0(26, 26); +aq += R_aq_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "amominw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + " | rl=" + std::to_string(rl) + " | aq=" + std::to_string(aq) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// AMOMAXW --------------------------------------------------------------------- +static InstructionDefinition amomaxw_rd_rs1_rs2_rl_aq ( + ISA32_RV64IMACFD, + "amomaxw", + (uint32_t) 0xa000202f, + (uint32_t) 0xf800707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; +etiss_uint8 rl = 0; +static BitArrayRange R_rl_0(25, 25); +rl += R_rl_0.read(ba) << 0; +etiss_uint8 aq = 0; +static BitArrayRange R_aq_0(26, 26); +aq += R_aq_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//AMOMAXW\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n"; +cp.code() += "etiss_uint32 mem_val_0;\n"; +cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "etiss_int32 res1 = mem_val_0;\n"; +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res1;\n"; +} // conditional +cp.code() += "etiss_uint32 res2 = (res1 < (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL])) ? (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) : (res1);\n"; +cp.code() += "etiss_uint32 mem_val_1;\n"; +cp.code() += "mem_val_1 = res2;\n"; +cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); + + cp.code() = std::string("//AMOMAXW\n"); + +// ----------------------------------------------------------------------------- +cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n"; +// ----------------------------------------------------------------------------- + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; +etiss_uint8 rl = 0; +static BitArrayRange R_rl_0(25, 25); +rl += R_rl_0.read(ba) << 0; +etiss_uint8 aq = 0; +static BitArrayRange R_aq_0(26, 26); +aq += R_aq_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "amomaxw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + " | rl=" + std::to_string(rl) + " | aq=" + std::to_string(aq) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// AMOMINUW -------------------------------------------------------------------- +static InstructionDefinition amominuw_rd_rs1_rs2_rl_aq ( + ISA32_RV64IMACFD, + "amominuw", + (uint32_t) 0xc000202f, + (uint32_t) 0xf800707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; +etiss_uint8 rl = 0; +static BitArrayRange R_rl_0(25, 25); +rl += R_rl_0.read(ba) << 0; +etiss_uint8 aq = 0; +static BitArrayRange R_aq_0(26, 26); +aq += R_aq_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//AMOMINUW\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n"; +cp.code() += "etiss_uint32 mem_val_0;\n"; +cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "etiss_uint32 res1 = mem_val_0;\n"; +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int32)(res1);\n"; +} // conditional +cp.code() += "etiss_uint32 res2 = (res1 > (etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL])) ? (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) : (res1);\n"; +cp.code() += "etiss_uint32 mem_val_1;\n"; +cp.code() += "mem_val_1 = res2;\n"; +cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); + + cp.code() = std::string("//AMOMINUW\n"); + +// ----------------------------------------------------------------------------- +cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n"; +// ----------------------------------------------------------------------------- + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; +etiss_uint8 rl = 0; +static BitArrayRange R_rl_0(25, 25); +rl += R_rl_0.read(ba) << 0; +etiss_uint8 aq = 0; +static BitArrayRange R_aq_0(26, 26); +aq += R_aq_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "amominuw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + " | rl=" + std::to_string(rl) + " | aq=" + std::to_string(aq) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// AMOMAXUW -------------------------------------------------------------------- +static InstructionDefinition amomaxuw_rd_rs1_rs2_rl_aq ( + ISA32_RV64IMACFD, + "amomaxuw", + (uint32_t) 0xe000202f, + (uint32_t) 0xf800707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; +etiss_uint8 rl = 0; +static BitArrayRange R_rl_0(25, 25); +rl += R_rl_0.read(ba) << 0; +etiss_uint8 aq = 0; +static BitArrayRange R_aq_0(26, 26); +aq += R_aq_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//AMOMAXUW\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n"; +cp.code() += "etiss_uint32 mem_val_0;\n"; +cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "etiss_uint32 res1 = mem_val_0;\n"; +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int32)(res1);\n"; +} // conditional +cp.code() += "etiss_uint32 res2 = (res1 < (etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL])) ? (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) : (res1);\n"; +cp.code() += "etiss_uint32 mem_val_1;\n"; +cp.code() += "mem_val_1 = res2;\n"; +cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); + + cp.code() = std::string("//AMOMAXUW\n"); + +// ----------------------------------------------------------------------------- +cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n"; +// ----------------------------------------------------------------------------- + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; +etiss_uint8 rl = 0; +static BitArrayRange R_rl_0(25, 25); +rl += R_rl_0.read(ba) << 0; +etiss_uint8 aq = 0; +static BitArrayRange R_aq_0(26, 26); +aq += R_aq_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "amomaxuw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + " | rl=" + std::to_string(rl) + " | aq=" + std::to_string(aq) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32DCInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32DCInstr.cpp new file mode 100644 index 0000000000..e0548e4ebd --- /dev/null +++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32DCInstr.cpp @@ -0,0 +1,399 @@ +/** + * Generated on Tue, 28 Nov 2023 09:45:19 +0100. + * + * This file contains the instruction behavior models of the RV32DC + * instruction set for the RV64IMACFD core architecture. + */ + +#include "RV64IMACFDArch.h" +#include "RV64IMACFDFuncs.h" + +using namespace etiss; +using namespace etiss::instr; + + +// CFLD ------------------------------------------------------------------------ +static InstructionDefinition cfld_rd_uimm_rs1 ( + ISA16_RV64IMACFD, + "cfld", + (uint16_t) 0x2000, + (uint16_t) 0xe003, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(4, 2); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 uimm = 0; +static BitArrayRange R_uimm_6(6, 5); +uimm += R_uimm_6.read(ba) << 6; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(9, 7); +rs1 += R_rs1_0.read(ba) << 0; +static BitArrayRange R_uimm_3(12, 10); +uimm += R_uimm_3.read(ba) << 3; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//CFLD\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] + " + std::to_string(uimm) + "ULL;\n"; +cp.code() += "etiss_uint64 mem_val_0;\n"; +cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "etiss_uint64 res = (etiss_uint64)(mem_val_0);\n"; +cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd + 8ULL) + "ULL] = res;\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); + + cp.code() = std::string("//CFLD\n"); + +// ----------------------------------------------------------------------------- +cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n"; +// ----------------------------------------------------------------------------- + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(4, 2); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 uimm = 0; +static BitArrayRange R_uimm_6(6, 5); +uimm += R_uimm_6.read(ba) << 6; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(9, 7); +rs1 += R_rs1_0.read(ba) << 0; +static BitArrayRange R_uimm_3(12, 10); +uimm += R_uimm_3.read(ba) << 3; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "cfld" << " # " << ba << (" [rd=" + std::to_string(rd) + " | uimm=" + std::to_string(uimm) + " | rs1=" + std::to_string(rs1) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// CFSD ------------------------------------------------------------------------ +static InstructionDefinition cfsd_rs2_uimm_rs1 ( + ISA16_RV64IMACFD, + "cfsd", + (uint16_t) 0xa000, + (uint16_t) 0xe003, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(4, 2); +rs2 += R_rs2_0.read(ba) << 0; +etiss_uint8 uimm = 0; +static BitArrayRange R_uimm_6(6, 5); +uimm += R_uimm_6.read(ba) << 6; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(9, 7); +rs1 += R_rs1_0.read(ba) << 0; +static BitArrayRange R_uimm_3(12, 10); +uimm += R_uimm_3.read(ba) << 3; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//CFSD\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] + " + std::to_string(uimm) + "ULL;\n"; +cp.code() += "etiss_uint64 mem_val_0;\n"; +cp.code() += "mem_val_0 = (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2 + 8ULL) + "ULL]);\n"; +cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); + + cp.code() = std::string("//CFSD\n"); + +// ----------------------------------------------------------------------------- +cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n"; +// ----------------------------------------------------------------------------- + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(4, 2); +rs2 += R_rs2_0.read(ba) << 0; +etiss_uint8 uimm = 0; +static BitArrayRange R_uimm_6(6, 5); +uimm += R_uimm_6.read(ba) << 6; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(9, 7); +rs1 += R_rs1_0.read(ba) << 0; +static BitArrayRange R_uimm_3(12, 10); +uimm += R_uimm_3.read(ba) << 3; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "cfsd" << " # " << ba << (" [rs2=" + std::to_string(rs2) + " | uimm=" + std::to_string(uimm) + " | rs1=" + std::to_string(rs1) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// CFLDSP ---------------------------------------------------------------------- +static InstructionDefinition cfldsp_uimm_rd ( + ISA16_RV64IMACFD, + "cfldsp", + (uint16_t) 0x2002, + (uint16_t) 0xe003, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint16 uimm = 0; +static BitArrayRange R_uimm_6(4, 2); +uimm += R_uimm_6.read(ba) << 6; +static BitArrayRange R_uimm_3(6, 5); +uimm += R_uimm_3.read(ba) << 3; +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +static BitArrayRange R_uimm_5(12, 12); +uimm += R_uimm_5.read(ba) << 5; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//CFLDSP\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[2ULL] + " + std::to_string(uimm) + "ULL;\n"; +cp.code() += "etiss_uint64 mem_val_0;\n"; +cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "etiss_uint64 res = (etiss_uint64)(mem_val_0);\n"; +cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); + + cp.code() = std::string("//CFLDSP\n"); + +// ----------------------------------------------------------------------------- +cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n"; +// ----------------------------------------------------------------------------- + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint16 uimm = 0; +static BitArrayRange R_uimm_6(4, 2); +uimm += R_uimm_6.read(ba) << 6; +static BitArrayRange R_uimm_3(6, 5); +uimm += R_uimm_3.read(ba) << 3; +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +static BitArrayRange R_uimm_5(12, 12); +uimm += R_uimm_5.read(ba) << 5; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "cfldsp" << " # " << ba << (" [uimm=" + std::to_string(uimm) + " | rd=" + std::to_string(rd) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// CFSDSP ---------------------------------------------------------------------- +static InstructionDefinition cfsdsp_rs2_uimm ( + ISA16_RV64IMACFD, + "cfsdsp", + (uint16_t) 0xa002, + (uint16_t) 0xe003, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(6, 2); +rs2 += R_rs2_0.read(ba) << 0; +etiss_uint16 uimm = 0; +static BitArrayRange R_uimm_6(9, 7); +uimm += R_uimm_6.read(ba) << 6; +static BitArrayRange R_uimm_3(12, 10); +uimm += R_uimm_3.read(ba) << 3; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//CFSDSP\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[2ULL] + " + std::to_string(uimm) + "ULL;\n"; +cp.code() += "etiss_uint64 mem_val_0;\n"; +cp.code() += "mem_val_0 = (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n"; +cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); + + cp.code() = std::string("//CFSDSP\n"); + +// ----------------------------------------------------------------------------- +cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n"; +// ----------------------------------------------------------------------------- + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(6, 2); +rs2 += R_rs2_0.read(ba) << 0; +etiss_uint16 uimm = 0; +static BitArrayRange R_uimm_6(9, 7); +uimm += R_uimm_6.read(ba) << 6; +static BitArrayRange R_uimm_3(12, 10); +uimm += R_uimm_3.read(ba) << 3; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "cfsdsp" << " # " << ba << (" [rs2=" + std::to_string(rs2) + " | uimm=" + std::to_string(uimm) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32DInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32DInstr.cpp new file mode 100644 index 0000000000..820fa7ad60 --- /dev/null +++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32DInstr.cpp @@ -0,0 +1,2122 @@ +/** + * Generated on Tue, 28 Nov 2023 09:45:19 +0100. + * + * This file contains the instruction behavior models of the RV32D + * instruction set for the RV64IMACFD core architecture. + */ + +#include "RV64IMACFDArch.h" +#include "RV64IMACFDFuncs.h" + +using namespace etiss; +using namespace etiss::instr; + + +// FLD ------------------------------------------------------------------------- +static InstructionDefinition fld_rd_rs1_imm ( + ISA32_RV64IMACFD, + "fld", + (uint32_t) 0x003007, + (uint32_t) 0x00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint16 imm = 0; +static BitArrayRange R_imm_0(31, 20); +imm += R_imm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//FLD\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n"; +cp.code() += "etiss_uint64 mem_val_0;\n"; +cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "etiss_uint64 res = (etiss_uint64)(mem_val_0);\n"; +cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); + + cp.code() = std::string("//FLD\n"); + +// ----------------------------------------------------------------------------- +cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n"; +// ----------------------------------------------------------------------------- + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint16 imm = 0; +static BitArrayRange R_imm_0(31, 20); +imm += R_imm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "fld" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | imm=" + std::to_string(imm) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// FSD ------------------------------------------------------------------------- +static InstructionDefinition fsd_imm_rs1_rs2 ( + ISA32_RV64IMACFD, + "fsd", + (uint32_t) 0x003027, + (uint32_t) 0x00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint16 imm = 0; +static BitArrayRange R_imm_0(11, 7); +imm += R_imm_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; +static BitArrayRange R_imm_5(31, 25); +imm += R_imm_5.read(ba) << 5; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//FSD\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n"; +cp.code() += "etiss_uint64 mem_val_0;\n"; +cp.code() += "mem_val_0 = (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n"; +cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); + + cp.code() = std::string("//FSD\n"); + +// ----------------------------------------------------------------------------- +cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n"; +// ----------------------------------------------------------------------------- + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint16 imm = 0; +static BitArrayRange R_imm_0(11, 7); +imm += R_imm_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; +static BitArrayRange R_imm_5(31, 25); +imm += R_imm_5.read(ba) << 5; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "fsd" << " # " << ba << (" [imm=" + std::to_string(imm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// FMADD_D --------------------------------------------------------------------- +static InstructionDefinition fmadd_d_rd_rm_rs1_rs2_rs3 ( + ISA32_RV64IMACFD, + "fmadd_d", + (uint32_t) 0x2000043, + (uint32_t) 0x600007f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rm = 0; +static BitArrayRange R_rm_0(14, 12); +rm += R_rm_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; +etiss_uint8 rs3 = 0; +static BitArrayRange R_rs3_0(31, 27); +rs3 += R_rs3_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//FMADD_D\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 0ULL, RV64IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n"; +cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n"; +cp.code() += "etiss_uint32 flags = fget_flags();\n"; +cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rm = 0; +static BitArrayRange R_rm_0(14, 12); +rm += R_rm_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; +etiss_uint8 rs3 = 0; +static BitArrayRange R_rs3_0(31, 27); +rs3 += R_rs3_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "fmadd_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + " | rs3=" + std::to_string(rs3) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// FMSUB_D --------------------------------------------------------------------- +static InstructionDefinition fmsub_d_rd_rm_rs1_rs2_rs3 ( + ISA32_RV64IMACFD, + "fmsub_d", + (uint32_t) 0x2000047, + (uint32_t) 0x600007f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rm = 0; +static BitArrayRange R_rm_0(14, 12); +rm += R_rm_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; +etiss_uint8 rs3 = 0; +static BitArrayRange R_rs3_0(31, 27); +rs3 += R_rs3_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//FMSUB_D\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 1ULL, RV64IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n"; +cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n"; +cp.code() += "etiss_uint32 flags = fget_flags();\n"; +cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rm = 0; +static BitArrayRange R_rm_0(14, 12); +rm += R_rm_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; +etiss_uint8 rs3 = 0; +static BitArrayRange R_rs3_0(31, 27); +rs3 += R_rs3_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "fmsub_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + " | rs3=" + std::to_string(rs3) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// FNMADD_D -------------------------------------------------------------------- +static InstructionDefinition fnmadd_d_rd_rm_rs1_rs2_rs3 ( + ISA32_RV64IMACFD, + "fnmadd_d", + (uint32_t) 0x200004f, + (uint32_t) 0x600007f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rm = 0; +static BitArrayRange R_rm_0(14, 12); +rm += R_rm_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; +etiss_uint8 rs3 = 0; +static BitArrayRange R_rs3_0(31, 27); +rs3 += R_rs3_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//FNMADD_D\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 2ULL, RV64IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n"; +cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n"; +cp.code() += "etiss_uint32 flags = fget_flags();\n"; +cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rm = 0; +static BitArrayRange R_rm_0(14, 12); +rm += R_rm_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; +etiss_uint8 rs3 = 0; +static BitArrayRange R_rs3_0(31, 27); +rs3 += R_rs3_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "fnmadd_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + " | rs3=" + std::to_string(rs3) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// FNMSUB_D -------------------------------------------------------------------- +static InstructionDefinition fnmsub_d_rd_rm_rs1_rs2_rs3 ( + ISA32_RV64IMACFD, + "fnmsub_d", + (uint32_t) 0x200004b, + (uint32_t) 0x600007f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rm = 0; +static BitArrayRange R_rm_0(14, 12); +rm += R_rm_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; +etiss_uint8 rs3 = 0; +static BitArrayRange R_rs3_0(31, 27); +rs3 += R_rs3_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//FNMSUB_D\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint64 res = fmadd_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 3ULL, RV64IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n"; +cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n"; +cp.code() += "etiss_uint32 flags = fget_flags();\n"; +cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rm = 0; +static BitArrayRange R_rm_0(14, 12); +rm += R_rm_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; +etiss_uint8 rs3 = 0; +static BitArrayRange R_rs3_0(31, 27); +rs3 += R_rs3_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "fnmsub_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + " | rs3=" + std::to_string(rs3) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// FADD_D ---------------------------------------------------------------------- +static InstructionDefinition fadd_d_rd_rm_rs1_rs2 ( + ISA32_RV64IMACFD, + "fadd_d", + (uint32_t) 0x2000053, + (uint32_t) 0xfe00007f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rm = 0; +static BitArrayRange R_rm_0(14, 12); +rm += R_rm_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//FADD_D\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint64 res = fadd_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), RV64IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n"; +cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n"; +cp.code() += "etiss_uint32 flags = fget_flags();\n"; +cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rm = 0; +static BitArrayRange R_rm_0(14, 12); +rm += R_rm_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "fadd_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// FSUB_D ---------------------------------------------------------------------- +static InstructionDefinition fsub_d_rd_rm_rs1_rs2 ( + ISA32_RV64IMACFD, + "fsub_d", + (uint32_t) 0xa000053, + (uint32_t) 0xfe00007f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rm = 0; +static BitArrayRange R_rm_0(14, 12); +rm += R_rm_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//FSUB_D\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint64 res = fsub_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), RV64IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n"; +cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n"; +cp.code() += "etiss_uint32 flags = fget_flags();\n"; +cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rm = 0; +static BitArrayRange R_rm_0(14, 12); +rm += R_rm_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "fsub_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// FMUL_D ---------------------------------------------------------------------- +static InstructionDefinition fmul_d_rd_rm_rs1_rs2 ( + ISA32_RV64IMACFD, + "fmul_d", + (uint32_t) 0x12000053, + (uint32_t) 0xfe00007f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rm = 0; +static BitArrayRange R_rm_0(14, 12); +rm += R_rm_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//FMUL_D\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint64 res = fmul_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), RV64IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n"; +cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n"; +cp.code() += "etiss_uint32 flags = fget_flags();\n"; +cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rm = 0; +static BitArrayRange R_rm_0(14, 12); +rm += R_rm_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "fmul_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// FDIV_D ---------------------------------------------------------------------- +static InstructionDefinition fdiv_d_rd_rm_rs1_rs2 ( + ISA32_RV64IMACFD, + "fdiv_d", + (uint32_t) 0x1a000053, + (uint32_t) 0xfe00007f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rm = 0; +static BitArrayRange R_rm_0(14, 12); +rm += R_rm_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//FDIV_D\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint64 res = fdiv_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), RV64IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n"; +cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n"; +cp.code() += "etiss_uint32 flags = fget_flags();\n"; +cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rm = 0; +static BitArrayRange R_rm_0(14, 12); +rm += R_rm_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "fdiv_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// FSQRT_D --------------------------------------------------------------------- +static InstructionDefinition fsqrt_d_rd_rm_rs1 ( + ISA32_RV64IMACFD, + "fsqrt_d", + (uint32_t) 0x5a000053, + (uint32_t) 0xfff0007f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rm = 0; +static BitArrayRange R_rm_0(14, 12); +rm += R_rm_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//FSQRT_D\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint64 res = fsqrt_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), RV64IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n"; +cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n"; +cp.code() += "etiss_uint32 flags = fget_flags();\n"; +cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rm = 0; +static BitArrayRange R_rm_0(14, 12); +rm += R_rm_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "fsqrt_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// FSGNJ_D --------------------------------------------------------------------- +static InstructionDefinition fsgnj_d_rd_rs1_rs2 ( + ISA32_RV64IMACFD, + "fsgnj_d", + (uint32_t) 0x22000053, + (uint32_t) 0xfe00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//FSGNJ_D\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint64 res = ((((((((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]) >> (63ULL)) & 1)) << 63) | ((((((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]) >> (0ULL)) & 9223372036854775807)));\n"; +cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "fsgnj_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// FSGNJN_D -------------------------------------------------------------------- +static InstructionDefinition fsgnjn_d_rd_rs1_rs2 ( + ISA32_RV64IMACFD, + "fsgnjn_d", + (uint32_t) 0x22001053, + (uint32_t) 0xfe00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//FSGNJN_D\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint64 res = (((~((((((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]) >> (63ULL)) & 1))) << 63) | ((((((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]) >> (0ULL)) & 9223372036854775807)));\n"; +cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "fsgnjn_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// FSGNJX_D -------------------------------------------------------------------- +static InstructionDefinition fsgnjx_d_rd_rs1_rs2 ( + ISA32_RV64IMACFD, + "fsgnjx_d", + (uint32_t) 0x22002053, + (uint32_t) 0xfe00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//FSGNJX_D\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint64 res = (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]) ^ ((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]) & 9223372036854775808ULL);\n"; +cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "fsgnjx_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// FMIN_D ---------------------------------------------------------------------- +static InstructionDefinition fmin_d_rd_rs1_rs2 ( + ISA32_RV64IMACFD, + "fmin_d", + (uint32_t) 0x2a000053, + (uint32_t) 0xfe00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//FMIN_D\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint64 res = fsel_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), 0ULL);\n"; +cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n"; +cp.code() += "etiss_uint32 flags = fget_flags();\n"; +cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "fmin_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// FMAX_D ---------------------------------------------------------------------- +static InstructionDefinition fmax_d_rd_rs1_rs2 ( + ISA32_RV64IMACFD, + "fmax_d", + (uint32_t) 0x2a001053, + (uint32_t) 0xfe00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//FMAX_D\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint64 res = fsel_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), 1ULL);\n"; +cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n"; +cp.code() += "etiss_uint32 flags = fget_flags();\n"; +cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "fmax_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// FCVT_S_D -------------------------------------------------------------------- +static InstructionDefinition fcvt_s_d_rd_rm_rs1 ( + ISA32_RV64IMACFD, + "fcvt_s_d", + (uint32_t) 0x40100053, + (uint32_t) 0xfff0007f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rm = 0; +static BitArrayRange R_rm_0(14, 12); +rm += R_rm_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//FCVT_S_D\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint32 res = fconv_d2f(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL], " + std::to_string(rm) + "ULL);\n"; +cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL + res;\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rm = 0; +static BitArrayRange R_rm_0(14, 12); +rm += R_rm_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "fcvt_s_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// FCVT_D_S -------------------------------------------------------------------- +static InstructionDefinition fcvt_d_s_rd_rm_rs1 ( + ISA32_RV64IMACFD, + "fcvt_d_s", + (uint32_t) 0x42000053, + (uint32_t) 0xfff0007f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rm = 0; +static BitArrayRange R_rm_0(14, 12); +rm += R_rm_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//FCVT_D_S\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint64 res = fconv_f2d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), " + std::to_string(rm) + "ULL);\n"; +{ // block +cp.code() += "{ // block\n"; +cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rm = 0; +static BitArrayRange R_rm_0(14, 12); +rm += R_rm_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "fcvt_d_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// FEQ_D ----------------------------------------------------------------------- +static InstructionDefinition feq_d_rd_rs1_rs2 ( + ISA32_RV64IMACFD, + "feq_d", + (uint32_t) 0xa2002053, + (uint32_t) 0xfe00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//FEQ_D\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint64 res = 0ULL;\n"; +cp.code() += "res = fcmp_d(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL], ((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL], 0ULL);\n"; +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res;\n"; +} // conditional +cp.code() += "etiss_uint32 flags = fget_flags();\n"; +cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "feq_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// FLT_D ----------------------------------------------------------------------- +static InstructionDefinition flt_d_rd_rs1_rs2 ( + ISA32_RV64IMACFD, + "flt_d", + (uint32_t) 0xa2001053, + (uint32_t) 0xfe00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//FLT_D\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint64 res = 0ULL;\n"; +cp.code() += "res = fcmp_d(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL], ((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL], 2ULL);\n"; +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res;\n"; +} // conditional +cp.code() += "etiss_uint32 flags = fget_flags();\n"; +cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "flt_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// FLE_D ----------------------------------------------------------------------- +static InstructionDefinition fle_d_rd_rs1_rs2 ( + ISA32_RV64IMACFD, + "fle_d", + (uint32_t) 0xa2000053, + (uint32_t) 0xfe00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//FLE_D\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint64 res = 0ULL;\n"; +cp.code() += "res = fcmp_d(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL], ((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL], 1ULL);\n"; +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res;\n"; +} // conditional +cp.code() += "etiss_uint32 flags = fget_flags();\n"; +cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "fle_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// FCLASS_D -------------------------------------------------------------------- +static InstructionDefinition fclass_d_rd_rs1 ( + ISA32_RV64IMACFD, + "fclass_d", + (uint32_t) 0xe2001053, + (uint32_t) 0xfff0707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//FCLASS_D\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = fclass_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]));\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "fclass_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// FCVT_W_D -------------------------------------------------------------------- +static InstructionDefinition fcvt_w_d_rd_rm_rs1 ( + ISA32_RV64IMACFD, + "fcvt_w_d", + (uint32_t) 0xc2000053, + (uint32_t) 0xfff0007f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rm = 0; +static BitArrayRange R_rm_0(14, 12); +rm += R_rm_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//FCVT_W_D\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_int32 res = 0ULL;\n"; +cp.code() += "res = fcvt_64_32(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL], 0ULL, " + std::to_string(rm) + "ULL);\n"; +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res;\n"; +} // conditional +cp.code() += "etiss_uint32 flags = fget_flags();\n"; +cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rm = 0; +static BitArrayRange R_rm_0(14, 12); +rm += R_rm_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "fcvt_w_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// FCVT_WU_D ------------------------------------------------------------------- +static InstructionDefinition fcvt_wu_d_rd_rm_rs1 ( + ISA32_RV64IMACFD, + "fcvt_wu_d", + (uint32_t) 0xc2100053, + (uint32_t) 0xfff0007f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rm = 0; +static BitArrayRange R_rm_0(14, 12); +rm += R_rm_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//FCVT_WU_D\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint32 res = 0ULL;\n"; +cp.code() += "res = fcvt_64_32(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL], 1ULL, " + std::to_string(rm) + "ULL);\n"; +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint64)((etiss_int32)(res));\n"; +} // conditional +cp.code() += "etiss_uint32 flags = fget_flags();\n"; +cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rm = 0; +static BitArrayRange R_rm_0(14, 12); +rm += R_rm_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "fcvt_wu_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// FCVT_D_W -------------------------------------------------------------------- +static InstructionDefinition fcvt_d_w_rd_rm_rs1 ( + ISA32_RV64IMACFD, + "fcvt_d_w", + (uint32_t) 0xd2000053, + (uint32_t) 0xfff0007f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rm = 0; +static BitArrayRange R_rm_0(14, 12); +rm += R_rm_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//FCVT_D_W\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_int64 res = fcvt_32_64((etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]), 2ULL, " + std::to_string(rm) + "ULL);\n"; +cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rm = 0; +static BitArrayRange R_rm_0(14, 12); +rm += R_rm_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "fcvt_d_w" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// FCVT_D_WU ------------------------------------------------------------------- +static InstructionDefinition fcvt_d_wu_rd_rm_rs1 ( + ISA32_RV64IMACFD, + "fcvt_d_wu", + (uint32_t) 0xd2100053, + (uint32_t) 0xfff0007f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rm = 0; +static BitArrayRange R_rm_0(14, 12); +rm += R_rm_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//FCVT_D_WU\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint64 res = fcvt_32_64((etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]), 3ULL, " + std::to_string(rm) + "ULL);\n"; +cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rm = 0; +static BitArrayRange R_rm_0(14, 12); +rm += R_rm_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "fcvt_d_wu" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32FInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32FInstr.cpp new file mode 100644 index 0000000000..e8b6879aba --- /dev/null +++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32FInstr.cpp @@ -0,0 +1,2235 @@ +/** + * Generated on Tue, 28 Nov 2023 09:45:19 +0100. + * + * This file contains the instruction behavior models of the RV32F + * instruction set for the RV64IMACFD core architecture. + */ + +#include "RV64IMACFDArch.h" +#include "RV64IMACFDFuncs.h" + +using namespace etiss; +using namespace etiss::instr; + + +// FLW ------------------------------------------------------------------------- +static InstructionDefinition flw_rd_rs1_imm ( + ISA32_RV64IMACFD, + "flw", + (uint32_t) 0x002007, + (uint32_t) 0x00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint16 imm = 0; +static BitArrayRange R_imm_0(31, 20); +imm += R_imm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//FLW\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n"; +cp.code() += "etiss_uint32 mem_val_0;\n"; +cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "etiss_uint32 res = (etiss_uint32)(mem_val_0);\n"; +{ // block +cp.code() += "{ // block\n"; +cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); + + cp.code() = std::string("//FLW\n"); + +// ----------------------------------------------------------------------------- +cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n"; +// ----------------------------------------------------------------------------- + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint16 imm = 0; +static BitArrayRange R_imm_0(31, 20); +imm += R_imm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "flw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | imm=" + std::to_string(imm) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// FSW ------------------------------------------------------------------------- +static InstructionDefinition fsw_imm_rs1_rs2 ( + ISA32_RV64IMACFD, + "fsw", + (uint32_t) 0x002027, + (uint32_t) 0x00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint16 imm = 0; +static BitArrayRange R_imm_0(11, 7); +imm += R_imm_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; +static BitArrayRange R_imm_5(31, 25); +imm += R_imm_5.read(ba) << 5; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//FSW\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n"; +cp.code() += "etiss_uint32 mem_val_0;\n"; +cp.code() += "mem_val_0 = (etiss_uint32)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n"; +cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); + + cp.code() = std::string("//FSW\n"); + +// ----------------------------------------------------------------------------- +cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n"; +// ----------------------------------------------------------------------------- + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint16 imm = 0; +static BitArrayRange R_imm_0(11, 7); +imm += R_imm_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; +static BitArrayRange R_imm_5(31, 25); +imm += R_imm_5.read(ba) << 5; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "fsw" << " # " << ba << (" [imm=" + std::to_string(imm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// FMADD_S --------------------------------------------------------------------- +static InstructionDefinition fmadd_s_rd_rm_rs1_rs2_rs3 ( + ISA32_RV64IMACFD, + "fmadd_s", + (uint32_t) 0x000043, + (uint32_t) 0x600007f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rm = 0; +static BitArrayRange R_rm_0(14, 12); +rm += R_rm_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; +etiss_uint8 rs3 = 0; +static BitArrayRange R_rs3_0(31, 27); +rs3 += R_rs3_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//FMADD_S\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint32 res = fmadd_s(unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 0ULL, RV64IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n"; +cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "etiss_uint32 flags = fget_flags();\n"; +cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rm = 0; +static BitArrayRange R_rm_0(14, 12); +rm += R_rm_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; +etiss_uint8 rs3 = 0; +static BitArrayRange R_rs3_0(31, 27); +rs3 += R_rs3_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "fmadd_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + " | rs3=" + std::to_string(rs3) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// FMSUB_S --------------------------------------------------------------------- +static InstructionDefinition fmsub_s_rd_rm_rs1_rs2_rs3 ( + ISA32_RV64IMACFD, + "fmsub_s", + (uint32_t) 0x000047, + (uint32_t) 0x600007f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rm = 0; +static BitArrayRange R_rm_0(14, 12); +rm += R_rm_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; +etiss_uint8 rs3 = 0; +static BitArrayRange R_rs3_0(31, 27); +rs3 += R_rs3_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//FMSUB_S\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint32 res = fmadd_s(unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 1ULL, RV64IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n"; +cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "etiss_uint32 flags = fget_flags();\n"; +cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rm = 0; +static BitArrayRange R_rm_0(14, 12); +rm += R_rm_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; +etiss_uint8 rs3 = 0; +static BitArrayRange R_rs3_0(31, 27); +rs3 += R_rs3_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "fmsub_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + " | rs3=" + std::to_string(rs3) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// FNMADD_S -------------------------------------------------------------------- +static InstructionDefinition fnmadd_s_rd_rm_rs1_rs2_rs3 ( + ISA32_RV64IMACFD, + "fnmadd_s", + (uint32_t) 0x00004f, + (uint32_t) 0x600007f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rm = 0; +static BitArrayRange R_rm_0(14, 12); +rm += R_rm_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; +etiss_uint8 rs3 = 0; +static BitArrayRange R_rs3_0(31, 27); +rs3 += R_rs3_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//FNMADD_S\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n"; +cp.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n"; +cp.code() += "etiss_uint32 frs3 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]);\n"; +cp.code() += "etiss_uint32 res = fmadd_s(frs1, frs2, frs3, 2ULL, RV64IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n"; +cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "etiss_uint32 flags = fget_flags();\n"; +cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rm = 0; +static BitArrayRange R_rm_0(14, 12); +rm += R_rm_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; +etiss_uint8 rs3 = 0; +static BitArrayRange R_rs3_0(31, 27); +rs3 += R_rs3_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "fnmadd_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + " | rs3=" + std::to_string(rs3) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// FNMSUB_S -------------------------------------------------------------------- +static InstructionDefinition fnmsub_s_rd_rm_rs1_rs2_rs3 ( + ISA32_RV64IMACFD, + "fnmsub_s", + (uint32_t) 0x00004b, + (uint32_t) 0x600007f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rm = 0; +static BitArrayRange R_rm_0(14, 12); +rm += R_rm_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; +etiss_uint8 rs3 = 0; +static BitArrayRange R_rs3_0(31, 27); +rs3 += R_rs3_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//FNMSUB_S\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n"; +cp.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n"; +cp.code() += "etiss_uint32 frs3 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]);\n"; +cp.code() += "etiss_uint32 res = fmadd_s(frs1, frs2, frs3, 3ULL, RV64IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n"; +cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "etiss_uint32 flags = fget_flags();\n"; +cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rm = 0; +static BitArrayRange R_rm_0(14, 12); +rm += R_rm_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; +etiss_uint8 rs3 = 0; +static BitArrayRange R_rs3_0(31, 27); +rs3 += R_rs3_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "fnmsub_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + " | rs3=" + std::to_string(rs3) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// FADD_S ---------------------------------------------------------------------- +static InstructionDefinition fadd_s_rd_rm_rs1_rs2 ( + ISA32_RV64IMACFD, + "fadd_s", + (uint32_t) 0x000053, + (uint32_t) 0xfe00007f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rm = 0; +static BitArrayRange R_rm_0(14, 12); +rm += R_rm_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//FADD_S\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n"; +cp.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n"; +cp.code() += "etiss_uint32 res = fadd_s(frs1, frs2, RV64IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n"; +cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "etiss_uint32 flags = fget_flags();\n"; +cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rm = 0; +static BitArrayRange R_rm_0(14, 12); +rm += R_rm_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "fadd_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// FSUB_S ---------------------------------------------------------------------- +static InstructionDefinition fsub_s_rd_rm_rs1_rs2 ( + ISA32_RV64IMACFD, + "fsub_s", + (uint32_t) 0x8000053, + (uint32_t) 0xfe00007f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rm = 0; +static BitArrayRange R_rm_0(14, 12); +rm += R_rm_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//FSUB_S\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n"; +cp.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n"; +cp.code() += "etiss_uint32 res = fsub_s(frs1, frs2, RV64IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n"; +cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "etiss_uint32 flags = fget_flags();\n"; +cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rm = 0; +static BitArrayRange R_rm_0(14, 12); +rm += R_rm_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "fsub_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// FMUL_S ---------------------------------------------------------------------- +static InstructionDefinition fmul_s_rd_rm_rs1_rs2 ( + ISA32_RV64IMACFD, + "fmul_s", + (uint32_t) 0x10000053, + (uint32_t) 0xfe00007f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rm = 0; +static BitArrayRange R_rm_0(14, 12); +rm += R_rm_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//FMUL_S\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n"; +cp.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n"; +cp.code() += "etiss_uint32 res = fmul_s(frs1, frs2, RV64IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n"; +cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "etiss_uint32 flags = fget_flags();\n"; +cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rm = 0; +static BitArrayRange R_rm_0(14, 12); +rm += R_rm_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "fmul_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// FDIV_S ---------------------------------------------------------------------- +static InstructionDefinition fdiv_s_rd_rm_rs1_rs2 ( + ISA32_RV64IMACFD, + "fdiv_s", + (uint32_t) 0x18000053, + (uint32_t) 0xfe00007f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rm = 0; +static BitArrayRange R_rm_0(14, 12); +rm += R_rm_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//FDIV_S\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n"; +cp.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n"; +cp.code() += "etiss_uint32 res = fdiv_s(frs1, frs2, RV64IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n"; +cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "etiss_uint32 flags = fget_flags();\n"; +cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rm = 0; +static BitArrayRange R_rm_0(14, 12); +rm += R_rm_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "fdiv_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// FSQRT_S --------------------------------------------------------------------- +static InstructionDefinition fsqrt_s_rd_rm_rs1 ( + ISA32_RV64IMACFD, + "fsqrt_s", + (uint32_t) 0x58000053, + (uint32_t) 0xfff0007f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rm = 0; +static BitArrayRange R_rm_0(14, 12); +rm += R_rm_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//FSQRT_S\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n"; +cp.code() += "etiss_uint32 res = fsqrt_s(frs1, RV64IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n"; +cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "etiss_uint32 flags = fget_flags();\n"; +cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rm = 0; +static BitArrayRange R_rm_0(14, 12); +rm += R_rm_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "fsqrt_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// FSGNJ_S --------------------------------------------------------------------- +static InstructionDefinition fsgnj_s_rd_rs1_rs2 ( + ISA32_RV64IMACFD, + "fsgnj_s", + (uint32_t) 0x20000053, + (uint32_t) 0xfe00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//FSGNJ_S\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n"; +cp.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n"; +cp.code() += "etiss_uint32 res = ((((((frs2) >> (31ULL)) & 1)) << 31) | ((((frs1) >> (0ULL)) & 2147483647)));\n"; +cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "fsgnj_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// FSGNJN_S -------------------------------------------------------------------- +static InstructionDefinition fsgnjn_s_rd_rs1_rs2 ( + ISA32_RV64IMACFD, + "fsgnjn_s", + (uint32_t) 0x20001053, + (uint32_t) 0xfe00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//FSGNJN_S\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n"; +cp.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n"; +cp.code() += "etiss_uint32 res = (((~((((frs2) >> (31ULL)) & 1))) << 31) | ((((frs1) >> (0ULL)) & 2147483647)));\n"; +cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "fsgnjn_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// FSGNJX_S -------------------------------------------------------------------- +static InstructionDefinition fsgnjx_s_rd_rs1_rs2 ( + ISA32_RV64IMACFD, + "fsgnjx_s", + (uint32_t) 0x20002053, + (uint32_t) 0xfe00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//FSGNJX_S\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n"; +cp.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n"; +cp.code() += "etiss_uint32 res = frs1 ^ (frs2 & 2147483648ULL);\n"; +cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "fsgnjx_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// FMIN_S ---------------------------------------------------------------------- +static InstructionDefinition fmin_s_rd_rs1_rs2 ( + ISA32_RV64IMACFD, + "fmin_s", + (uint32_t) 0x28000053, + (uint32_t) 0xfe00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//FMIN_S\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n"; +cp.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n"; +cp.code() += "etiss_uint32 res = fsel_s(frs1, frs2, 0ULL);\n"; +cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "etiss_uint32 flags = fget_flags();\n"; +cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "fmin_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// FMAX_S ---------------------------------------------------------------------- +static InstructionDefinition fmax_s_rd_rs1_rs2 ( + ISA32_RV64IMACFD, + "fmax_s", + (uint32_t) 0x28001053, + (uint32_t) 0xfe00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//FMAX_S\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n"; +cp.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n"; +cp.code() += "etiss_uint32 res = fsel_s(frs1, frs2, 1ULL);\n"; +cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "etiss_uint32 flags = fget_flags();\n"; +cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "fmax_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// FCVT_W_S -------------------------------------------------------------------- +static InstructionDefinition fcvt_w_s_rd_rm_rs1 ( + ISA32_RV64IMACFD, + "fcvt_w_s", + (uint32_t) 0xc0000053, + (uint32_t) 0xfff0007f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rm = 0; +static BitArrayRange R_rm_0(14, 12); +rm += R_rm_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//FCVT_W_S\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_int32 res = 0ULL;\n"; +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n"; +cp.code() += "res = fcvt_s(frs1, 0ULL, " + std::to_string(rm) + "ULL);\n"; +cp.code() += "} // block\n"; +} // block +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res;\n"; +} // conditional +cp.code() += "etiss_uint32 flags = fget_flags();\n"; +cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rm = 0; +static BitArrayRange R_rm_0(14, 12); +rm += R_rm_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "fcvt_w_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// FCVT_WU_S ------------------------------------------------------------------- +static InstructionDefinition fcvt_wu_s_rd_rm_rs1 ( + ISA32_RV64IMACFD, + "fcvt_wu_s", + (uint32_t) 0xc0100053, + (uint32_t) 0xfff0007f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rm = 0; +static BitArrayRange R_rm_0(14, 12); +rm += R_rm_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//FCVT_WU_S\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint32 res = 0ULL;\n"; +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n"; +cp.code() += "res = fcvt_s(frs1, 1ULL, " + std::to_string(rm) + "ULL);\n"; +cp.code() += "} // block\n"; +} // block +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint64)((etiss_int32)(res));\n"; +} // conditional +cp.code() += "etiss_uint32 flags = fget_flags();\n"; +cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rm = 0; +static BitArrayRange R_rm_0(14, 12); +rm += R_rm_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "fcvt_wu_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// FEQ_S ----------------------------------------------------------------------- +static InstructionDefinition feq_s_rd_rs1_rs2 ( + ISA32_RV64IMACFD, + "feq_s", + (uint32_t) 0xa0002053, + (uint32_t) 0xfe00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//FEQ_S\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint32 res = 0ULL;\n"; +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n"; +cp.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n"; +cp.code() += "res = fcmp_s(frs1, frs2, 0ULL);\n"; +cp.code() += "} // block\n"; +} // block +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res;\n"; +} // conditional +cp.code() += "etiss_uint32 flags = fget_flags();\n"; +cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "feq_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// FLT_S ----------------------------------------------------------------------- +static InstructionDefinition flt_s_rd_rs1_rs2 ( + ISA32_RV64IMACFD, + "flt_s", + (uint32_t) 0xa0001053, + (uint32_t) 0xfe00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//FLT_S\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint32 res = 0ULL;\n"; +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n"; +cp.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n"; +cp.code() += "res = fcmp_s(frs1, frs2, 2ULL);\n"; +cp.code() += "} // block\n"; +} // block +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res;\n"; +} // conditional +cp.code() += "etiss_uint32 flags = fget_flags();\n"; +cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "flt_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// FLE_S ----------------------------------------------------------------------- +static InstructionDefinition fle_s_rd_rs1_rs2 ( + ISA32_RV64IMACFD, + "fle_s", + (uint32_t) 0xa0000053, + (uint32_t) 0xfe00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//FLE_S\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint32 res = 0ULL;\n"; +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint32 frs1 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n"; +cp.code() += "etiss_uint32 frs2 = unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n"; +cp.code() += "res = fcmp_s(frs1, frs2, 1ULL);\n"; +cp.code() += "} // block\n"; +} // block +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res;\n"; +} // conditional +cp.code() += "etiss_uint32 flags = fget_flags();\n"; +cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "fle_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// FCLASS_S -------------------------------------------------------------------- +static InstructionDefinition fclass_s_rd_rs1 ( + ISA32_RV64IMACFD, + "fclass_s", + (uint32_t) 0xe0001053, + (uint32_t) 0xfff0707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//FCLASS_S\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint32 res = 0ULL;\n"; +cp.code() += "res = fclass_s(unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]));\n"; +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res;\n"; +} // conditional +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "fclass_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// FCVT_S_W -------------------------------------------------------------------- +static InstructionDefinition fcvt_s_w_rd_rm_rs1 ( + ISA32_RV64IMACFD, + "fcvt_s_w", + (uint32_t) 0xd0000053, + (uint32_t) 0xfff0007f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rm = 0; +static BitArrayRange R_rm_0(14, 12); +rm += R_rm_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//FCVT_S_W\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint32 res = fcvt_s((etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]), 2ULL, " + std::to_string(rm) + "ULL);\n"; +cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rm = 0; +static BitArrayRange R_rm_0(14, 12); +rm += R_rm_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "fcvt_s_w" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// FCVT_S_WU ------------------------------------------------------------------- +static InstructionDefinition fcvt_s_wu_rd_rm_rs1 ( + ISA32_RV64IMACFD, + "fcvt_s_wu", + (uint32_t) 0xd0100053, + (uint32_t) 0xfff0007f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rm = 0; +static BitArrayRange R_rm_0(14, 12); +rm += R_rm_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//FCVT_S_WU\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint32 res = fcvt_s((etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]), 3ULL, " + std::to_string(rm) + "ULL);\n"; +cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rm = 0; +static BitArrayRange R_rm_0(14, 12); +rm += R_rm_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "fcvt_s_wu" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// FMV_X_W --------------------------------------------------------------------- +static InstructionDefinition fmv_x_w_rd_rs1 ( + ISA32_RV64IMACFD, + "fmv_x_w", + (uint32_t) 0xe0000053, + (uint32_t) 0xfff0707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//FMV_X_W\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint64)((etiss_int32)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]));\n"; +} // conditional +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "fmv_x_w" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// FMV_W_X --------------------------------------------------------------------- +static InstructionDefinition fmv_w_x_rd_rs1 ( + ISA32_RV64IMACFD, + "fmv_w_x", + (uint32_t) 0xf0000053, + (uint32_t) 0xfff0707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//FMV_W_X\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +{ // block +cp.code() += "{ // block\n"; +cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]);\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "fmv_w_x" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32ICInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32ICInstr.cpp new file mode 100644 index 0000000000..645c92c559 --- /dev/null +++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32ICInstr.cpp @@ -0,0 +1,2288 @@ +/** + * Generated on Tue, 28 Nov 2023 09:45:19 +0100. + * + * This file contains the instruction behavior models of the RV32IC + * instruction set for the RV64IMACFD core architecture. + */ + +#include "RV64IMACFDArch.h" +#include "RV64IMACFDFuncs.h" + +using namespace etiss; +using namespace etiss::instr; + + +// CADDI4SPN ------------------------------------------------------------------- +static InstructionDefinition caddi4spn_rd_imm ( + ISA16_RV64IMACFD, + "caddi4spn", + (uint16_t) 0x00, + (uint16_t) 0xe003, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(4, 2); +rd += R_rd_0.read(ba) << 0; +etiss_uint16 imm = 0; +static BitArrayRange R_imm_3(5, 5); +imm += R_imm_3.read(ba) << 3; +static BitArrayRange R_imm_2(6, 6); +imm += R_imm_2.read(ba) << 2; +static BitArrayRange R_imm_6(10, 7); +imm += R_imm_6.read(ba) << 6; +static BitArrayRange R_imm_4(12, 11); +imm += R_imm_4.read(ba) << 4; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//CADDI4SPN\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +if (imm) { // conditional +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[2ULL] + " + std::to_string(imm) + "ULL;\n"; +} // conditional +else { // conditional +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV64IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 2ULL);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +} // conditional +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); + + cp.code() = std::string("//CADDI4SPN\n"); + +// ----------------------------------------------------------------------------- +cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n"; +// ----------------------------------------------------------------------------- + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(4, 2); +rd += R_rd_0.read(ba) << 0; +etiss_uint16 imm = 0; +static BitArrayRange R_imm_3(5, 5); +imm += R_imm_3.read(ba) << 3; +static BitArrayRange R_imm_2(6, 6); +imm += R_imm_2.read(ba) << 2; +static BitArrayRange R_imm_6(10, 7); +imm += R_imm_6.read(ba) << 6; +static BitArrayRange R_imm_4(12, 11); +imm += R_imm_4.read(ba) << 4; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "caddi4spn" << " # " << ba << (" [rd=" + std::to_string(rd) + " | imm=" + std::to_string(imm) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// CLW ------------------------------------------------------------------------- +static InstructionDefinition clw_rd_uimm_rs1 ( + ISA16_RV64IMACFD, + "clw", + (uint16_t) 0x4000, + (uint16_t) 0xe003, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(4, 2); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 uimm = 0; +static BitArrayRange R_uimm_6(5, 5); +uimm += R_uimm_6.read(ba) << 6; +static BitArrayRange R_uimm_2(6, 6); +uimm += R_uimm_2.read(ba) << 2; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(9, 7); +rs1 += R_rs1_0.read(ba) << 0; +static BitArrayRange R_uimm_3(12, 10); +uimm += R_uimm_3.read(ba) << 3; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//CLW\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint64 load_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] + " + std::to_string(uimm) + "ULL;\n"; +cp.code() += "etiss_uint32 mem_val_0;\n"; +cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 4);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) + "ULL] = (etiss_int32)(mem_val_0);\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); + + cp.code() = std::string("//CLW\n"); + +// ----------------------------------------------------------------------------- +cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n"; +// ----------------------------------------------------------------------------- + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(4, 2); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 uimm = 0; +static BitArrayRange R_uimm_6(5, 5); +uimm += R_uimm_6.read(ba) << 6; +static BitArrayRange R_uimm_2(6, 6); +uimm += R_uimm_2.read(ba) << 2; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(9, 7); +rs1 += R_rs1_0.read(ba) << 0; +static BitArrayRange R_uimm_3(12, 10); +uimm += R_uimm_3.read(ba) << 3; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "clw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | uimm=" + std::to_string(uimm) + " | rs1=" + std::to_string(rs1) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// CSW ------------------------------------------------------------------------- +static InstructionDefinition csw_rs2_uimm_rs1 ( + ISA16_RV64IMACFD, + "csw", + (uint16_t) 0xc000, + (uint16_t) 0xe003, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(4, 2); +rs2 += R_rs2_0.read(ba) << 0; +etiss_uint8 uimm = 0; +static BitArrayRange R_uimm_6(5, 5); +uimm += R_uimm_6.read(ba) << 6; +static BitArrayRange R_uimm_2(6, 6); +uimm += R_uimm_2.read(ba) << 2; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(9, 7); +rs1 += R_rs1_0.read(ba) << 0; +static BitArrayRange R_uimm_3(12, 10); +uimm += R_uimm_3.read(ba) << 3; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//CSW\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint64 load_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] + " + std::to_string(uimm) + "ULL;\n"; +cp.code() += "etiss_uint32 mem_val_0;\n"; +cp.code() += "mem_val_0 = (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 + 8ULL) + "ULL]);\n"; +cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 4);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); + + cp.code() = std::string("//CSW\n"); + +// ----------------------------------------------------------------------------- +cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n"; +// ----------------------------------------------------------------------------- + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(4, 2); +rs2 += R_rs2_0.read(ba) << 0; +etiss_uint8 uimm = 0; +static BitArrayRange R_uimm_6(5, 5); +uimm += R_uimm_6.read(ba) << 6; +static BitArrayRange R_uimm_2(6, 6); +uimm += R_uimm_2.read(ba) << 2; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(9, 7); +rs1 += R_rs1_0.read(ba) << 0; +static BitArrayRange R_uimm_3(12, 10); +uimm += R_uimm_3.read(ba) << 3; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "csw" << " # " << ba << (" [rs2=" + std::to_string(rs2) + " | uimm=" + std::to_string(uimm) + " | rs1=" + std::to_string(rs1) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// CADDI ----------------------------------------------------------------------- +static InstructionDefinition caddi_imm_rs1 ( + ISA16_RV64IMACFD, + "caddi", + (uint16_t) 0x01, + (uint16_t) 0xe003, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 imm = 0; +static BitArrayRange R_imm_0(6, 2); +imm += R_imm_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(11, 7); +rs1 += R_rs1_0.read(ba) << 0; +static BitArrayRange R_imm_5(12, 12); +imm += R_imm_5.read(ba) << 5; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//CADDI\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +if ((rs1 % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int8)(((etiss_int8)imm) << (2)) >> (2))) + "LL;\n"; +} // conditional +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 imm = 0; +static BitArrayRange R_imm_0(6, 2); +imm += R_imm_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(11, 7); +rs1 += R_rs1_0.read(ba) << 0; +static BitArrayRange R_imm_5(12, 12); +imm += R_imm_5.read(ba) << 5; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "caddi" << " # " << ba << (" [imm=" + std::to_string(imm) + " | rs1=" + std::to_string(rs1) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// CNOP ------------------------------------------------------------------------ +static InstructionDefinition cnop_nzimm ( + ISA16_RV64IMACFD, + "cnop", + (uint16_t) 0x01, + (uint16_t) 0xef83, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 nzimm = 0; +static BitArrayRange R_nzimm_0(6, 2); +nzimm += R_nzimm_0.read(ba) << 0; +static BitArrayRange R_nzimm_5(12, 12); +nzimm += R_nzimm_5.read(ba) << 5; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//CNOP\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 nzimm = 0; +static BitArrayRange R_nzimm_0(6, 2); +nzimm += R_nzimm_0.read(ba) << 0; +static BitArrayRange R_nzimm_5(12, 12); +nzimm += R_nzimm_5.read(ba) << 5; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "cnop" << " # " << ba << (" [nzimm=" + std::to_string(nzimm) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// CLI ------------------------------------------------------------------------- +static InstructionDefinition cli_imm_rd ( + ISA16_RV64IMACFD, + "cli", + (uint16_t) 0x4001, + (uint16_t) 0xe003, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 imm = 0; +static BitArrayRange R_imm_0(6, 2); +imm += R_imm_0.read(ba) << 0; +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +static BitArrayRange R_imm_5(12, 12); +imm += R_imm_5.read(ba) << 5; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//CLI\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = " + std::to_string(((etiss_int8)(((etiss_int8)imm) << (2)) >> (2))) + "LL;\n"; +} // conditional +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 imm = 0; +static BitArrayRange R_imm_0(6, 2); +imm += R_imm_0.read(ba) << 0; +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +static BitArrayRange R_imm_5(12, 12); +imm += R_imm_5.read(ba) << 5; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "cli" << " # " << ba << (" [imm=" + std::to_string(imm) + " | rd=" + std::to_string(rd) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// CLUI ------------------------------------------------------------------------ +static InstructionDefinition clui_imm_rd ( + ISA16_RV64IMACFD, + "clui", + (uint16_t) 0x6001, + (uint16_t) 0xe003, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint32 imm = 0; +static BitArrayRange R_imm_12(6, 2); +imm += R_imm_12.read(ba) << 12; +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +static BitArrayRange R_imm_17(12, 12); +imm += R_imm_17.read(ba) << 17; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//CLUI\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +if (imm == 0ULL) { // conditional +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV64IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 2ULL);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +} // conditional +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = " + std::to_string(((etiss_int32)(((etiss_int32)imm) << (14)) >> (14))) + "LL;\n"; +} // conditional +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); + + cp.code() = std::string("//CLUI\n"); + +// ----------------------------------------------------------------------------- +cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n"; +// ----------------------------------------------------------------------------- + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint32 imm = 0; +static BitArrayRange R_imm_12(6, 2); +imm += R_imm_12.read(ba) << 12; +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +static BitArrayRange R_imm_17(12, 12); +imm += R_imm_17.read(ba) << 17; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "clui" << " # " << ba << (" [imm=" + std::to_string(imm) + " | rd=" + std::to_string(rd) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// CADDI16SP ------------------------------------------------------------------- +static InstructionDefinition caddi16sp_nzimm ( + ISA16_RV64IMACFD, + "caddi16sp", + (uint16_t) 0x6101, + (uint16_t) 0xef83, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint16 nzimm = 0; +static BitArrayRange R_nzimm_5(2, 2); +nzimm += R_nzimm_5.read(ba) << 5; +static BitArrayRange R_nzimm_7(4, 3); +nzimm += R_nzimm_7.read(ba) << 7; +static BitArrayRange R_nzimm_6(5, 5); +nzimm += R_nzimm_6.read(ba) << 6; +static BitArrayRange R_nzimm_4(6, 6); +nzimm += R_nzimm_4.read(ba) << 4; +static BitArrayRange R_nzimm_9(12, 12); +nzimm += R_nzimm_9.read(ba) << 9; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//CADDI16SP\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +if (nzimm) { // conditional +cp.code() += "*((RV64IMACFD*)cpu)->X[2ULL] = *((RV64IMACFD*)cpu)->X[2ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)nzimm) << (6)) >> (6))) + "LL;\n"; +} // conditional +else { // conditional +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV64IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 2ULL);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +} // conditional +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); + + cp.code() = std::string("//CADDI16SP\n"); + +// ----------------------------------------------------------------------------- +cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n"; +// ----------------------------------------------------------------------------- + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint16 nzimm = 0; +static BitArrayRange R_nzimm_5(2, 2); +nzimm += R_nzimm_5.read(ba) << 5; +static BitArrayRange R_nzimm_7(4, 3); +nzimm += R_nzimm_7.read(ba) << 7; +static BitArrayRange R_nzimm_6(5, 5); +nzimm += R_nzimm_6.read(ba) << 6; +static BitArrayRange R_nzimm_4(6, 6); +nzimm += R_nzimm_4.read(ba) << 4; +static BitArrayRange R_nzimm_9(12, 12); +nzimm += R_nzimm_9.read(ba) << 9; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "caddi16sp" << " # " << ba << (" [nzimm=" + std::to_string(nzimm) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// __reserved_clui ------------------------------------------------------------- +static InstructionDefinition __reserved_clui_rd ( + ISA16_RV64IMACFD, + "__reserved_clui", + (uint16_t) 0x6001, + (uint16_t) 0xf07f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//__reserved_clui\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV64IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 2ULL);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); + + cp.code() = std::string("//__reserved_clui\n"); + +// ----------------------------------------------------------------------------- +cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n"; +// ----------------------------------------------------------------------------- + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "__reserved_clui" << " # " << ba << (" [rd=" + std::to_string(rd) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// CSRLI ----------------------------------------------------------------------- +static InstructionDefinition csrli_shamt_rs1 ( + ISA16_RV64IMACFD, + "csrli", + (uint16_t) 0x8001, + (uint16_t) 0xfc03, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 shamt = 0; +static BitArrayRange R_shamt_0(6, 2); +shamt += R_shamt_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(9, 7); +rs1 += R_rs1_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//CSRLI\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] >> " + std::to_string(shamt) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 shamt = 0; +static BitArrayRange R_shamt_0(6, 2); +shamt += R_shamt_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(9, 7); +rs1 += R_rs1_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "csrli" << " # " << ba << (" [shamt=" + std::to_string(shamt) + " | rs1=" + std::to_string(rs1) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// CSRAI ----------------------------------------------------------------------- +static InstructionDefinition csrai_shamt_rs1 ( + ISA16_RV64IMACFD, + "csrai", + (uint16_t) 0x8401, + (uint16_t) 0xfc03, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 shamt = 0; +static BitArrayRange R_shamt_0(6, 2); +shamt += R_shamt_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(9, 7); +rs1 += R_rs1_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//CSRAI\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +if (shamt) { // conditional +{ // block +cp.code() += "{ // block\n"; +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] = ((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL])) >> " + std::to_string(shamt) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +} // conditional +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 shamt = 0; +static BitArrayRange R_shamt_0(6, 2); +shamt += R_shamt_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(9, 7); +rs1 += R_rs1_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "csrai" << " # " << ba << (" [shamt=" + std::to_string(shamt) + " | rs1=" + std::to_string(rs1) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// CANDI ----------------------------------------------------------------------- +static InstructionDefinition candi_imm_rs1 ( + ISA16_RV64IMACFD, + "candi", + (uint16_t) 0x8801, + (uint16_t) 0xec03, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 imm = 0; +static BitArrayRange R_imm_0(6, 2); +imm += R_imm_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(9, 7); +rs1 += R_rs1_0.read(ba) << 0; +static BitArrayRange R_imm_5(12, 12); +imm += R_imm_5.read(ba) << 5; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//CANDI\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] & " + std::to_string(((etiss_int8)(((etiss_int8)imm) << (2)) >> (2))) + "LL;\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 imm = 0; +static BitArrayRange R_imm_0(6, 2); +imm += R_imm_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(9, 7); +rs1 += R_rs1_0.read(ba) << 0; +static BitArrayRange R_imm_5(12, 12); +imm += R_imm_5.read(ba) << 5; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "candi" << " # " << ba << (" [imm=" + std::to_string(imm) + " | rs1=" + std::to_string(rs1) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// CSUB ------------------------------------------------------------------------ +static InstructionDefinition csub_rs2_rd ( + ISA16_RV64IMACFD, + "csub", + (uint16_t) 0x8c01, + (uint16_t) 0xfc63, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(4, 2); +rs2 += R_rs2_0.read(ba) << 0; +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(9, 7); +rd += R_rd_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//CSUB\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) + "ULL] - *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 + 8ULL) + "ULL];\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(4, 2); +rs2 += R_rs2_0.read(ba) << 0; +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(9, 7); +rd += R_rd_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "csub" << " # " << ba << (" [rs2=" + std::to_string(rs2) + " | rd=" + std::to_string(rd) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// CXOR ------------------------------------------------------------------------ +static InstructionDefinition cxor_rs2_rd ( + ISA16_RV64IMACFD, + "cxor", + (uint16_t) 0x8c21, + (uint16_t) 0xfc63, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(4, 2); +rs2 += R_rs2_0.read(ba) << 0; +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(9, 7); +rd += R_rd_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//CXOR\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) + "ULL] ^ *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 + 8ULL) + "ULL];\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(4, 2); +rs2 += R_rs2_0.read(ba) << 0; +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(9, 7); +rd += R_rd_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "cxor" << " # " << ba << (" [rs2=" + std::to_string(rs2) + " | rd=" + std::to_string(rd) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// COR ------------------------------------------------------------------------- +static InstructionDefinition cor_rs2_rd ( + ISA16_RV64IMACFD, + "cor", + (uint16_t) 0x8c41, + (uint16_t) 0xfc63, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(4, 2); +rs2 += R_rs2_0.read(ba) << 0; +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(9, 7); +rd += R_rd_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//COR\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) + "ULL] | *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 + 8ULL) + "ULL];\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(4, 2); +rs2 += R_rs2_0.read(ba) << 0; +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(9, 7); +rd += R_rd_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "cor" << " # " << ba << (" [rs2=" + std::to_string(rs2) + " | rd=" + std::to_string(rd) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// CAND ------------------------------------------------------------------------ +static InstructionDefinition cand_rs2_rd ( + ISA16_RV64IMACFD, + "cand", + (uint16_t) 0x8c61, + (uint16_t) 0xfc63, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(4, 2); +rs2 += R_rs2_0.read(ba) << 0; +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(9, 7); +rd += R_rd_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//CAND\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) + "ULL] & *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 + 8ULL) + "ULL];\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(4, 2); +rs2 += R_rs2_0.read(ba) << 0; +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(9, 7); +rd += R_rd_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "cand" << " # " << ba << (" [rs2=" + std::to_string(rs2) + " | rd=" + std::to_string(rd) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// CJ -------------------------------------------------------------------------- +static InstructionDefinition cj_imm ( + ISA16_RV64IMACFD, + "cj", + (uint16_t) 0xa001, + (uint16_t) 0xe003, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint16 imm = 0; +static BitArrayRange R_imm_5(2, 2); +imm += R_imm_5.read(ba) << 5; +static BitArrayRange R_imm_1(5, 3); +imm += R_imm_1.read(ba) << 1; +static BitArrayRange R_imm_7(6, 6); +imm += R_imm_7.read(ba) << 7; +static BitArrayRange R_imm_6(7, 7); +imm += R_imm_6.read(ba) << 6; +static BitArrayRange R_imm_10(8, 8); +imm += R_imm_10.read(ba) << 10; +static BitArrayRange R_imm_8(10, 9); +imm += R_imm_8.read(ba) << 8; +static BitArrayRange R_imm_4(11, 11); +imm += R_imm_4.read(ba) << 4; +static BitArrayRange R_imm_11(12, 12); +imm += R_imm_11.read(ba) << 11; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//CJ\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n"; +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); + + cp.code() = std::string("//CJ\n"); + +// ----------------------------------------------------------------------------- +cp.code() += "return cpu->exception;\n"; +// ----------------------------------------------------------------------------- + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint16 imm = 0; +static BitArrayRange R_imm_5(2, 2); +imm += R_imm_5.read(ba) << 5; +static BitArrayRange R_imm_1(5, 3); +imm += R_imm_1.read(ba) << 1; +static BitArrayRange R_imm_7(6, 6); +imm += R_imm_7.read(ba) << 7; +static BitArrayRange R_imm_6(7, 7); +imm += R_imm_6.read(ba) << 6; +static BitArrayRange R_imm_10(8, 8); +imm += R_imm_10.read(ba) << 10; +static BitArrayRange R_imm_8(10, 9); +imm += R_imm_8.read(ba) << 8; +static BitArrayRange R_imm_4(11, 11); +imm += R_imm_4.read(ba) << 4; +static BitArrayRange R_imm_11(12, 12); +imm += R_imm_11.read(ba) << 11; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "cj" << " # " << ba << (" [imm=" + std::to_string(imm) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// CBEQZ ----------------------------------------------------------------------- +static InstructionDefinition cbeqz_imm_rs1 ( + ISA16_RV64IMACFD, + "cbeqz", + (uint16_t) 0xc001, + (uint16_t) 0xe003, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint16 imm = 0; +static BitArrayRange R_imm_5(2, 2); +imm += R_imm_5.read(ba) << 5; +static BitArrayRange R_imm_1(4, 3); +imm += R_imm_1.read(ba) << 1; +static BitArrayRange R_imm_6(6, 5); +imm += R_imm_6.read(ba) << 6; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(9, 7); +rs1 += R_rs1_0.read(ba) << 0; +static BitArrayRange R_imm_3(11, 10); +imm += R_imm_3.read(ba) << 3; +static BitArrayRange R_imm_8(12, 12); +imm += R_imm_8.read(ba) << 8; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//CBEQZ\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] == 0ULL) { // conditional\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)(((etiss_int16)imm) << (7)) >> (7))) + "LL;\n"; +cp.code() += "} // conditional\n"; +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); + + cp.code() = std::string("//CBEQZ\n"); + +// ----------------------------------------------------------------------------- +cp.code() += "if (cpu->nextPc != " + std::to_string(ic.current_address_ + 2) + "ULL) return cpu->exception;\n"; +// ----------------------------------------------------------------------------- + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint16 imm = 0; +static BitArrayRange R_imm_5(2, 2); +imm += R_imm_5.read(ba) << 5; +static BitArrayRange R_imm_1(4, 3); +imm += R_imm_1.read(ba) << 1; +static BitArrayRange R_imm_6(6, 5); +imm += R_imm_6.read(ba) << 6; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(9, 7); +rs1 += R_rs1_0.read(ba) << 0; +static BitArrayRange R_imm_3(11, 10); +imm += R_imm_3.read(ba) << 3; +static BitArrayRange R_imm_8(12, 12); +imm += R_imm_8.read(ba) << 8; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "cbeqz" << " # " << ba << (" [imm=" + std::to_string(imm) + " | rs1=" + std::to_string(rs1) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// CBNEZ ----------------------------------------------------------------------- +static InstructionDefinition cbnez_imm_rs1 ( + ISA16_RV64IMACFD, + "cbnez", + (uint16_t) 0xe001, + (uint16_t) 0xe003, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint16 imm = 0; +static BitArrayRange R_imm_5(2, 2); +imm += R_imm_5.read(ba) << 5; +static BitArrayRange R_imm_1(4, 3); +imm += R_imm_1.read(ba) << 1; +static BitArrayRange R_imm_6(6, 5); +imm += R_imm_6.read(ba) << 6; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(9, 7); +rs1 += R_rs1_0.read(ba) << 0; +static BitArrayRange R_imm_3(11, 10); +imm += R_imm_3.read(ba) << 3; +static BitArrayRange R_imm_8(12, 12); +imm += R_imm_8.read(ba) << 8; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//CBNEZ\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] != 0ULL) { // conditional\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)(((etiss_int16)imm) << (7)) >> (7))) + "LL;\n"; +cp.code() += "} // conditional\n"; +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); + + cp.code() = std::string("//CBNEZ\n"); + +// ----------------------------------------------------------------------------- +cp.code() += "if (cpu->nextPc != " + std::to_string(ic.current_address_ + 2) + "ULL) return cpu->exception;\n"; +// ----------------------------------------------------------------------------- + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint16 imm = 0; +static BitArrayRange R_imm_5(2, 2); +imm += R_imm_5.read(ba) << 5; +static BitArrayRange R_imm_1(4, 3); +imm += R_imm_1.read(ba) << 1; +static BitArrayRange R_imm_6(6, 5); +imm += R_imm_6.read(ba) << 6; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(9, 7); +rs1 += R_rs1_0.read(ba) << 0; +static BitArrayRange R_imm_3(11, 10); +imm += R_imm_3.read(ba) << 3; +static BitArrayRange R_imm_8(12, 12); +imm += R_imm_8.read(ba) << 8; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "cbnez" << " # " << ba << (" [imm=" + std::to_string(imm) + " | rs1=" + std::to_string(rs1) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// CSLLI ----------------------------------------------------------------------- +static InstructionDefinition cslli_nzuimm_rs1 ( + ISA16_RV64IMACFD, + "cslli", + (uint16_t) 0x02, + (uint16_t) 0xf003, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 nzuimm = 0; +static BitArrayRange R_nzuimm_0(6, 2); +nzuimm += R_nzuimm_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(11, 7); +rs1 += R_rs1_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//CSLLI\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +if (nzuimm) { // conditional +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] << " + std::to_string(nzuimm) + "ULL;\n"; +} // conditional +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 nzuimm = 0; +static BitArrayRange R_nzuimm_0(6, 2); +nzuimm += R_nzuimm_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(11, 7); +rs1 += R_rs1_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "cslli" << " # " << ba << (" [nzuimm=" + std::to_string(nzuimm) + " | rs1=" + std::to_string(rs1) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// CLWSP ----------------------------------------------------------------------- +static InstructionDefinition clwsp_uimm_rd ( + ISA16_RV64IMACFD, + "clwsp", + (uint16_t) 0x4002, + (uint16_t) 0xe003, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 uimm = 0; +static BitArrayRange R_uimm_6(3, 2); +uimm += R_uimm_6.read(ba) << 6; +static BitArrayRange R_uimm_2(6, 4); +uimm += R_uimm_2.read(ba) << 2; +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +static BitArrayRange R_uimm_5(12, 12); +uimm += R_uimm_5.read(ba) << 5; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//CLWSP\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +if (rd % 32ULL) { // conditional +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint32 mem_val_0;\n"; +cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, *((RV64IMACFD*)cpu)->X[2ULL] + " + std::to_string(uimm) + "ULL, (etiss_uint8*)&mem_val_0, 4);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "etiss_int32 res = mem_val_0;\n"; +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int64)(res);\n"; +cp.code() += "} // block\n"; +} // block +} // conditional +else { // conditional +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV64IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 2ULL);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +} // conditional +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); + + cp.code() = std::string("//CLWSP\n"); + +// ----------------------------------------------------------------------------- +cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n"; +// ----------------------------------------------------------------------------- + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 uimm = 0; +static BitArrayRange R_uimm_6(3, 2); +uimm += R_uimm_6.read(ba) << 6; +static BitArrayRange R_uimm_2(6, 4); +uimm += R_uimm_2.read(ba) << 2; +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +static BitArrayRange R_uimm_5(12, 12); +uimm += R_uimm_5.read(ba) << 5; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "clwsp" << " # " << ba << (" [uimm=" + std::to_string(uimm) + " | rd=" + std::to_string(rd) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// CMV ------------------------------------------------------------------------- +static InstructionDefinition cmv_rs2_rd ( + ISA16_RV64IMACFD, + "cmv", + (uint16_t) 0x8002, + (uint16_t) 0xf003, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(6, 2); +rs2 += R_rs2_0.read(ba) << 0; +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//CMV\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n"; +} // conditional +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(6, 2); +rs2 += R_rs2_0.read(ba) << 0; +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "cmv" << " # " << ba << (" [rs2=" + std::to_string(rs2) + " | rd=" + std::to_string(rd) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// CJR ------------------------------------------------------------------------- +static InstructionDefinition cjr_rs1 ( + ISA16_RV64IMACFD, + "cjr", + (uint16_t) 0x8002, + (uint16_t) 0xf07f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(11, 7); +rs1 += R_rs1_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//CJR\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +if (rs1) { // conditional +cp.code() += "cpu->nextPc = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] & -2LL;\n"; +} // conditional +else { // conditional +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV64IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 2ULL);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +} // conditional +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); + + cp.code() = std::string("//CJR\n"); + +// ----------------------------------------------------------------------------- +cp.code() += "return cpu->exception;\n"; +// ----------------------------------------------------------------------------- + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(11, 7); +rs1 += R_rs1_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "cjr" << " # " << ba << (" [rs1=" + std::to_string(rs1) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// __reserved_cmv -------------------------------------------------------------- +static InstructionDefinition __reserved_cmv_ ( + ISA16_RV64IMACFD, + "__reserved_cmv", + (uint16_t) 0x8002, + (uint16_t) 0xffff, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//__reserved_cmv\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV64IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 2ULL);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); + + cp.code() = std::string("//__reserved_cmv\n"); + +// ----------------------------------------------------------------------------- +cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n"; +// ----------------------------------------------------------------------------- + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "__reserved_cmv" << " # " << ba << (" []"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// CADD ------------------------------------------------------------------------ +static InstructionDefinition cadd_rs2_rd ( + ISA16_RV64IMACFD, + "cadd", + (uint16_t) 0x9002, + (uint16_t) 0xf003, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(6, 2); +rs2 += R_rs2_0.read(ba) << 0; +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//CADD\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] + *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n"; +} // conditional +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(6, 2); +rs2 += R_rs2_0.read(ba) << 0; +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "cadd" << " # " << ba << (" [rs2=" + std::to_string(rs2) + " | rd=" + std::to_string(rd) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// CJALR ----------------------------------------------------------------------- +static InstructionDefinition cjalr_rs1 ( + ISA16_RV64IMACFD, + "cjalr", + (uint16_t) 0x9002, + (uint16_t) 0xf07f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(11, 7); +rs1 += R_rs1_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//CJALR\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint64 new_pc = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n"; +cp.code() += "*((RV64IMACFD*)cpu)->X[1ULL] = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n"; +cp.code() += "cpu->nextPc = new_pc & -2LL;\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); + + cp.code() = std::string("//CJALR\n"); + +// ----------------------------------------------------------------------------- +cp.code() += "return cpu->exception;\n"; +// ----------------------------------------------------------------------------- + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(11, 7); +rs1 += R_rs1_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "cjalr" << " # " << ba << (" [rs1=" + std::to_string(rs1) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// CEBREAK --------------------------------------------------------------------- +static InstructionDefinition cebreak_ ( + ISA16_RV64IMACFD, + "cebreak", + (uint16_t) 0x9002, + (uint16_t) 0xffff, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//CEBREAK\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV64IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 3ULL);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); + + cp.code() = std::string("//CEBREAK\n"); + +// ----------------------------------------------------------------------------- +cp.code() += "return cpu->exception;\n"; +// ----------------------------------------------------------------------------- + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "cebreak" << " # " << ba << (" []"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// CSWSP ----------------------------------------------------------------------- +static InstructionDefinition cswsp_rs2_uimm ( + ISA16_RV64IMACFD, + "cswsp", + (uint16_t) 0xc002, + (uint16_t) 0xe003, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(6, 2); +rs2 += R_rs2_0.read(ba) << 0; +etiss_uint8 uimm = 0; +static BitArrayRange R_uimm_6(8, 7); +uimm += R_uimm_6.read(ba) << 6; +static BitArrayRange R_uimm_2(12, 9); +uimm += R_uimm_2.read(ba) << 2; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//CSWSP\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[2ULL] + " + std::to_string(uimm) + "ULL;\n"; +cp.code() += "etiss_uint32 mem_val_0;\n"; +cp.code() += "mem_val_0 = (etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n"; +cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); + + cp.code() = std::string("//CSWSP\n"); + +// ----------------------------------------------------------------------------- +cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n"; +// ----------------------------------------------------------------------------- + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(6, 2); +rs2 += R_rs2_0.read(ba) << 0; +etiss_uint8 uimm = 0; +static BitArrayRange R_uimm_6(8, 7); +uimm += R_uimm_6.read(ba) << 6; +static BitArrayRange R_uimm_2(12, 9); +uimm += R_uimm_2.read(ba) << 2; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "cswsp" << " # " << ba << (" [rs2=" + std::to_string(rs2) + " | uimm=" + std::to_string(uimm) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// DII ------------------------------------------------------------------------- +static InstructionDefinition dii_ ( + ISA16_RV64IMACFD, + "dii", + (uint16_t) 0x00, + (uint16_t) 0xffff, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//DII\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV64IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 2ULL);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); + + cp.code() = std::string("//DII\n"); + +// ----------------------------------------------------------------------------- +cp.code() += "return cpu->exception;\n"; +// ----------------------------------------------------------------------------- + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "dii" << " # " << ba << (" []"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32IInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32IInstr.cpp new file mode 100644 index 0000000000..8a365f76ae --- /dev/null +++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32IInstr.cpp @@ -0,0 +1,3303 @@ +/** + * Generated on Tue, 28 Nov 2023 09:45:19 +0100. + * + * This file contains the instruction behavior models of the RV32I + * instruction set for the RV64IMACFD core architecture. + */ + +#include "RV64IMACFDArch.h" +#include "RV64IMACFDFuncs.h" + +using namespace etiss; +using namespace etiss::instr; + + +// LUI ------------------------------------------------------------------------- +static InstructionDefinition lui_rd_imm ( + ISA32_RV64IMACFD, + "lui", + (uint32_t) 0x000037, + (uint32_t) 0x00007f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint32 imm = 0; +static BitArrayRange R_imm_12(31, 12); +imm += R_imm_12.read(ba) << 12; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//LUI\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = " + std::to_string((etiss_uint64)(((etiss_int32)(imm)))) + "ULL;\n"; +} // conditional +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint32 imm = 0; +static BitArrayRange R_imm_12(31, 12); +imm += R_imm_12.read(ba) << 12; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "lui" << " # " << ba << (" [rd=" + std::to_string(rd) + " | imm=" + std::to_string(imm) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// AUIPC ----------------------------------------------------------------------- +static InstructionDefinition auipc_rd_imm ( + ISA32_RV64IMACFD, + "auipc", + (uint32_t) 0x000017, + (uint32_t) 0x00007f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint32 imm = 0; +static BitArrayRange R_imm_12(31, 12); +imm += R_imm_12.read(ba) << 12; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//AUIPC\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = " + std::to_string(ic.current_address_ + (etiss_int32)(imm)) + "LL;\n"; +} // conditional +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint32 imm = 0; +static BitArrayRange R_imm_12(31, 12); +imm += R_imm_12.read(ba) << 12; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "auipc" << " # " << ba << (" [rd=" + std::to_string(rd) + " | imm=" + std::to_string(imm) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// JAL ------------------------------------------------------------------------- +static InstructionDefinition jal_rd_imm ( + ISA32_RV64IMACFD, + "jal", + (uint32_t) 0x00006f, + (uint32_t) 0x00007f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint32 imm = 0; +static BitArrayRange R_imm_12(19, 12); +imm += R_imm_12.read(ba) << 12; +static BitArrayRange R_imm_11(20, 20); +imm += R_imm_11.read(ba) << 11; +static BitArrayRange R_imm_1(30, 21); +imm += R_imm_1.read(ba) << 1; +static BitArrayRange R_imm_20(31, 31); +imm += R_imm_20.read(ba) << 20; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//JAL\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +if (imm % 2ULL) { // conditional +{ // block +cp.code() += "{ // block\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV64IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 0ULL);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // block\n"; +} // block +} // conditional +else { // conditional +{ // block +cp.code() += "{ // block\n"; +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n"; +} // conditional +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int32)(((etiss_int32)imm) << (11)) >> (11))) + "LL;\n"; +cp.code() += "} // block\n"; +} // block +} // conditional +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); + + cp.code() = std::string("//JAL\n"); + +// ----------------------------------------------------------------------------- +cp.code() += "return cpu->exception;\n"; +// ----------------------------------------------------------------------------- + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint32 imm = 0; +static BitArrayRange R_imm_12(19, 12); +imm += R_imm_12.read(ba) << 12; +static BitArrayRange R_imm_11(20, 20); +imm += R_imm_11.read(ba) << 11; +static BitArrayRange R_imm_1(30, 21); +imm += R_imm_1.read(ba) << 1; +static BitArrayRange R_imm_20(31, 31); +imm += R_imm_20.read(ba) << 20; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "jal" << " # " << ba << (" [rd=" + std::to_string(rd) + " | imm=" + std::to_string(imm) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// JALR ------------------------------------------------------------------------ +static InstructionDefinition jalr_rd_rs1_imm ( + ISA32_RV64IMACFD, + "jalr", + (uint32_t) 0x000067, + (uint32_t) 0x00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint16 imm = 0; +static BitArrayRange R_imm_0(31, 20); +imm += R_imm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//JALR\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint64 new_pc = (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL) & -2LL;\n"; +cp.code() += "if (new_pc % 2ULL) { // conditional\n"; +{ // block +cp.code() += "{ // block\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV64IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 0ULL);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // block\n"; +} // block +cp.code() += "} // conditional\n"; +cp.code() += "else { // conditional\n"; +{ // block +cp.code() += "{ // block\n"; +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n"; +} // conditional +cp.code() += "cpu->nextPc = new_pc & -2LL;\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "} // conditional\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); + + cp.code() = std::string("//JALR\n"); + +// ----------------------------------------------------------------------------- +cp.code() += "return cpu->exception;\n"; +// ----------------------------------------------------------------------------- + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint16 imm = 0; +static BitArrayRange R_imm_0(31, 20); +imm += R_imm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "jalr" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | imm=" + std::to_string(imm) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// BEQ ------------------------------------------------------------------------- +static InstructionDefinition beq_imm_rs1_rs2 ( + ISA32_RV64IMACFD, + "beq", + (uint32_t) 0x000063, + (uint32_t) 0x00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint16 imm = 0; +static BitArrayRange R_imm_11(7, 7); +imm += R_imm_11.read(ba) << 11; +static BitArrayRange R_imm_1(11, 8); +imm += R_imm_1.read(ba) << 1; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; +static BitArrayRange R_imm_5(30, 25); +imm += R_imm_5.read(ba) << 5; +static BitArrayRange R_imm_12(31, 31); +imm += R_imm_12.read(ba) << 12; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//BEQ\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] == *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) { // conditional\n"; +{ // block +cp.code() += "{ // block\n"; +if (imm % 2ULL) { // conditional +{ // block +cp.code() += "{ // block\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV64IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 0ULL);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // block\n"; +} // block +} // conditional +else { // conditional +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)(((etiss_int16)imm) << (3)) >> (3))) + "LL;\n"; +cp.code() += "} // block\n"; +} // block +} // conditional +cp.code() += "} // block\n"; +} // block +cp.code() += "} // conditional\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); + + cp.code() = std::string("//BEQ\n"); + +// ----------------------------------------------------------------------------- +cp.code() += "if (cpu->return_pending | cpu->exception | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + "ULL) return cpu->exception;\n"; +// ----------------------------------------------------------------------------- + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint16 imm = 0; +static BitArrayRange R_imm_11(7, 7); +imm += R_imm_11.read(ba) << 11; +static BitArrayRange R_imm_1(11, 8); +imm += R_imm_1.read(ba) << 1; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; +static BitArrayRange R_imm_5(30, 25); +imm += R_imm_5.read(ba) << 5; +static BitArrayRange R_imm_12(31, 31); +imm += R_imm_12.read(ba) << 12; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "beq" << " # " << ba << (" [imm=" + std::to_string(imm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// BNE ------------------------------------------------------------------------- +static InstructionDefinition bne_imm_rs1_rs2 ( + ISA32_RV64IMACFD, + "bne", + (uint32_t) 0x001063, + (uint32_t) 0x00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint16 imm = 0; +static BitArrayRange R_imm_11(7, 7); +imm += R_imm_11.read(ba) << 11; +static BitArrayRange R_imm_1(11, 8); +imm += R_imm_1.read(ba) << 1; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; +static BitArrayRange R_imm_5(30, 25); +imm += R_imm_5.read(ba) << 5; +static BitArrayRange R_imm_12(31, 31); +imm += R_imm_12.read(ba) << 12; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//BNE\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] != *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) { // conditional\n"; +{ // block +cp.code() += "{ // block\n"; +if (imm % 2ULL) { // conditional +{ // block +cp.code() += "{ // block\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV64IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 0ULL);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // block\n"; +} // block +} // conditional +else { // conditional +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)(((etiss_int16)imm) << (3)) >> (3))) + "LL;\n"; +cp.code() += "} // block\n"; +} // block +} // conditional +cp.code() += "} // block\n"; +} // block +cp.code() += "} // conditional\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); + + cp.code() = std::string("//BNE\n"); + +// ----------------------------------------------------------------------------- +cp.code() += "if (cpu->return_pending | cpu->exception | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + "ULL) return cpu->exception;\n"; +// ----------------------------------------------------------------------------- + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint16 imm = 0; +static BitArrayRange R_imm_11(7, 7); +imm += R_imm_11.read(ba) << 11; +static BitArrayRange R_imm_1(11, 8); +imm += R_imm_1.read(ba) << 1; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; +static BitArrayRange R_imm_5(30, 25); +imm += R_imm_5.read(ba) << 5; +static BitArrayRange R_imm_12(31, 31); +imm += R_imm_12.read(ba) << 12; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "bne" << " # " << ba << (" [imm=" + std::to_string(imm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// BLT ------------------------------------------------------------------------- +static InstructionDefinition blt_imm_rs1_rs2 ( + ISA32_RV64IMACFD, + "blt", + (uint32_t) 0x004063, + (uint32_t) 0x00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint16 imm = 0; +static BitArrayRange R_imm_11(7, 7); +imm += R_imm_11.read(ba) << 11; +static BitArrayRange R_imm_1(11, 8); +imm += R_imm_1.read(ba) << 1; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; +static BitArrayRange R_imm_5(30, 25); +imm += R_imm_5.read(ba) << 5; +static BitArrayRange R_imm_12(31, 31); +imm += R_imm_12.read(ba) << 12; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//BLT\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "if ((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) < (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL])) { // conditional\n"; +{ // block +cp.code() += "{ // block\n"; +if (imm % 2ULL) { // conditional +{ // block +cp.code() += "{ // block\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV64IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 0ULL);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // block\n"; +} // block +} // conditional +else { // conditional +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)(((etiss_int16)imm) << (3)) >> (3))) + "LL;\n"; +cp.code() += "} // block\n"; +} // block +} // conditional +cp.code() += "} // block\n"; +} // block +cp.code() += "} // conditional\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); + + cp.code() = std::string("//BLT\n"); + +// ----------------------------------------------------------------------------- +cp.code() += "if (cpu->return_pending | cpu->exception | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + "ULL) return cpu->exception;\n"; +// ----------------------------------------------------------------------------- + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint16 imm = 0; +static BitArrayRange R_imm_11(7, 7); +imm += R_imm_11.read(ba) << 11; +static BitArrayRange R_imm_1(11, 8); +imm += R_imm_1.read(ba) << 1; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; +static BitArrayRange R_imm_5(30, 25); +imm += R_imm_5.read(ba) << 5; +static BitArrayRange R_imm_12(31, 31); +imm += R_imm_12.read(ba) << 12; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "blt" << " # " << ba << (" [imm=" + std::to_string(imm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// BGE ------------------------------------------------------------------------- +static InstructionDefinition bge_imm_rs1_rs2 ( + ISA32_RV64IMACFD, + "bge", + (uint32_t) 0x005063, + (uint32_t) 0x00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint16 imm = 0; +static BitArrayRange R_imm_11(7, 7); +imm += R_imm_11.read(ba) << 11; +static BitArrayRange R_imm_1(11, 8); +imm += R_imm_1.read(ba) << 1; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; +static BitArrayRange R_imm_5(30, 25); +imm += R_imm_5.read(ba) << 5; +static BitArrayRange R_imm_12(31, 31); +imm += R_imm_12.read(ba) << 12; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//BGE\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "if ((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) >= (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL])) { // conditional\n"; +{ // block +cp.code() += "{ // block\n"; +if (imm % 2ULL) { // conditional +{ // block +cp.code() += "{ // block\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV64IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 0ULL);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // block\n"; +} // block +} // conditional +else { // conditional +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)(((etiss_int16)imm) << (3)) >> (3))) + "LL;\n"; +cp.code() += "} // block\n"; +} // block +} // conditional +cp.code() += "} // block\n"; +} // block +cp.code() += "} // conditional\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); + + cp.code() = std::string("//BGE\n"); + +// ----------------------------------------------------------------------------- +cp.code() += "if (cpu->return_pending | cpu->exception | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + "ULL) return cpu->exception;\n"; +// ----------------------------------------------------------------------------- + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint16 imm = 0; +static BitArrayRange R_imm_11(7, 7); +imm += R_imm_11.read(ba) << 11; +static BitArrayRange R_imm_1(11, 8); +imm += R_imm_1.read(ba) << 1; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; +static BitArrayRange R_imm_5(30, 25); +imm += R_imm_5.read(ba) << 5; +static BitArrayRange R_imm_12(31, 31); +imm += R_imm_12.read(ba) << 12; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "bge" << " # " << ba << (" [imm=" + std::to_string(imm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// BLTU ------------------------------------------------------------------------ +static InstructionDefinition bltu_imm_rs1_rs2 ( + ISA32_RV64IMACFD, + "bltu", + (uint32_t) 0x006063, + (uint32_t) 0x00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint16 imm = 0; +static BitArrayRange R_imm_11(7, 7); +imm += R_imm_11.read(ba) << 11; +static BitArrayRange R_imm_1(11, 8); +imm += R_imm_1.read(ba) << 1; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; +static BitArrayRange R_imm_5(30, 25); +imm += R_imm_5.read(ba) << 5; +static BitArrayRange R_imm_12(31, 31); +imm += R_imm_12.read(ba) << 12; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//BLTU\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] < *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) { // conditional\n"; +{ // block +cp.code() += "{ // block\n"; +if (imm % 2ULL) { // conditional +{ // block +cp.code() += "{ // block\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV64IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 0ULL);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // block\n"; +} // block +} // conditional +else { // conditional +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)(((etiss_int16)imm) << (3)) >> (3))) + "LL;\n"; +cp.code() += "} // block\n"; +} // block +} // conditional +cp.code() += "} // block\n"; +} // block +cp.code() += "} // conditional\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); + + cp.code() = std::string("//BLTU\n"); + +// ----------------------------------------------------------------------------- +cp.code() += "if (cpu->return_pending | cpu->exception | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + "ULL) return cpu->exception;\n"; +// ----------------------------------------------------------------------------- + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint16 imm = 0; +static BitArrayRange R_imm_11(7, 7); +imm += R_imm_11.read(ba) << 11; +static BitArrayRange R_imm_1(11, 8); +imm += R_imm_1.read(ba) << 1; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; +static BitArrayRange R_imm_5(30, 25); +imm += R_imm_5.read(ba) << 5; +static BitArrayRange R_imm_12(31, 31); +imm += R_imm_12.read(ba) << 12; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "bltu" << " # " << ba << (" [imm=" + std::to_string(imm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// BGEU ------------------------------------------------------------------------ +static InstructionDefinition bgeu_imm_rs1_rs2 ( + ISA32_RV64IMACFD, + "bgeu", + (uint32_t) 0x007063, + (uint32_t) 0x00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint16 imm = 0; +static BitArrayRange R_imm_11(7, 7); +imm += R_imm_11.read(ba) << 11; +static BitArrayRange R_imm_1(11, 8); +imm += R_imm_1.read(ba) << 1; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; +static BitArrayRange R_imm_5(30, 25); +imm += R_imm_5.read(ba) << 5; +static BitArrayRange R_imm_12(31, 31); +imm += R_imm_12.read(ba) << 12; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//BGEU\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] >= *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) { // conditional\n"; +{ // block +cp.code() += "{ // block\n"; +if (imm % 2ULL) { // conditional +{ // block +cp.code() += "{ // block\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV64IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 0ULL);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // block\n"; +} // block +} // conditional +else { // conditional +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)(((etiss_int16)imm) << (3)) >> (3))) + "LL;\n"; +cp.code() += "} // block\n"; +} // block +} // conditional +cp.code() += "} // block\n"; +} // block +cp.code() += "} // conditional\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); + + cp.code() = std::string("//BGEU\n"); + +// ----------------------------------------------------------------------------- +cp.code() += "if (cpu->return_pending | cpu->exception | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + "ULL) return cpu->exception;\n"; +// ----------------------------------------------------------------------------- + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint16 imm = 0; +static BitArrayRange R_imm_11(7, 7); +imm += R_imm_11.read(ba) << 11; +static BitArrayRange R_imm_1(11, 8); +imm += R_imm_1.read(ba) << 1; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; +static BitArrayRange R_imm_5(30, 25); +imm += R_imm_5.read(ba) << 5; +static BitArrayRange R_imm_12(31, 31); +imm += R_imm_12.read(ba) << 12; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "bgeu" << " # " << ba << (" [imm=" + std::to_string(imm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// LB -------------------------------------------------------------------------- +static InstructionDefinition lb_rd_rs1_imm ( + ISA32_RV64IMACFD, + "lb", + (uint32_t) 0x000003, + (uint32_t) 0x00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint16 imm = 0; +static BitArrayRange R_imm_0(31, 20); +imm += R_imm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//LB\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint64 load_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n"; +cp.code() += "etiss_uint8 mem_val_0;\n"; +cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 1);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "etiss_int8 res = (etiss_int8)(mem_val_0);\n"; +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint64)(res);\n"; +} // conditional +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); + + cp.code() = std::string("//LB\n"); + +// ----------------------------------------------------------------------------- +cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n"; +// ----------------------------------------------------------------------------- + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint16 imm = 0; +static BitArrayRange R_imm_0(31, 20); +imm += R_imm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "lb" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | imm=" + std::to_string(imm) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// LH -------------------------------------------------------------------------- +static InstructionDefinition lh_rd_rs1_imm ( + ISA32_RV64IMACFD, + "lh", + (uint32_t) 0x001003, + (uint32_t) 0x00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint16 imm = 0; +static BitArrayRange R_imm_0(31, 20); +imm += R_imm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//LH\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint64 load_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n"; +cp.code() += "etiss_uint16 mem_val_0;\n"; +cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 2);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "etiss_int16 res = (etiss_int16)(mem_val_0);\n"; +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint64)(res);\n"; +} // conditional +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); + + cp.code() = std::string("//LH\n"); + +// ----------------------------------------------------------------------------- +cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n"; +// ----------------------------------------------------------------------------- + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint16 imm = 0; +static BitArrayRange R_imm_0(31, 20); +imm += R_imm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "lh" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | imm=" + std::to_string(imm) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// LW -------------------------------------------------------------------------- +static InstructionDefinition lw_rd_rs1_imm ( + ISA32_RV64IMACFD, + "lw", + (uint32_t) 0x002003, + (uint32_t) 0x00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint16 imm = 0; +static BitArrayRange R_imm_0(31, 20); +imm += R_imm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//LW\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint64 load_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n"; +cp.code() += "etiss_uint32 mem_val_0;\n"; +cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 4);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "etiss_int32 res = (etiss_int32)(mem_val_0);\n"; +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint64)(res);\n"; +} // conditional +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); + + cp.code() = std::string("//LW\n"); + +// ----------------------------------------------------------------------------- +cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n"; +// ----------------------------------------------------------------------------- + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint16 imm = 0; +static BitArrayRange R_imm_0(31, 20); +imm += R_imm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "lw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | imm=" + std::to_string(imm) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// LBU ------------------------------------------------------------------------- +static InstructionDefinition lbu_rd_rs1_imm ( + ISA32_RV64IMACFD, + "lbu", + (uint32_t) 0x004003, + (uint32_t) 0x00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint16 imm = 0; +static BitArrayRange R_imm_0(31, 20); +imm += R_imm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//LBU\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint64 load_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n"; +cp.code() += "etiss_uint8 mem_val_0;\n"; +cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 1);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "etiss_uint8 res = (etiss_uint8)(mem_val_0);\n"; +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint64)(res);\n"; +} // conditional +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); + + cp.code() = std::string("//LBU\n"); + +// ----------------------------------------------------------------------------- +cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n"; +// ----------------------------------------------------------------------------- + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint16 imm = 0; +static BitArrayRange R_imm_0(31, 20); +imm += R_imm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "lbu" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | imm=" + std::to_string(imm) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// LHU ------------------------------------------------------------------------- +static InstructionDefinition lhu_rd_rs1_imm ( + ISA32_RV64IMACFD, + "lhu", + (uint32_t) 0x005003, + (uint32_t) 0x00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint16 imm = 0; +static BitArrayRange R_imm_0(31, 20); +imm += R_imm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//LHU\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint64 load_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n"; +cp.code() += "etiss_uint16 mem_val_0;\n"; +cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 2);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "etiss_uint16 res = (etiss_uint16)(mem_val_0);\n"; +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint64)(res);\n"; +} // conditional +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); + + cp.code() = std::string("//LHU\n"); + +// ----------------------------------------------------------------------------- +cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n"; +// ----------------------------------------------------------------------------- + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint16 imm = 0; +static BitArrayRange R_imm_0(31, 20); +imm += R_imm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "lhu" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | imm=" + std::to_string(imm) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// SB -------------------------------------------------------------------------- +static InstructionDefinition sb_imm_rs1_rs2 ( + ISA32_RV64IMACFD, + "sb", + (uint32_t) 0x000023, + (uint32_t) 0x00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint16 imm = 0; +static BitArrayRange R_imm_0(11, 7); +imm += R_imm_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; +static BitArrayRange R_imm_5(31, 25); +imm += R_imm_5.read(ba) << 5; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//SB\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint64 store_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n"; +cp.code() += "etiss_uint8 mem_val_0;\n"; +cp.code() += "mem_val_0 = (etiss_int8)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n"; +cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, store_address, (etiss_uint8*)&mem_val_0, 1);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); + + cp.code() = std::string("//SB\n"); + +// ----------------------------------------------------------------------------- +cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n"; +// ----------------------------------------------------------------------------- + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint16 imm = 0; +static BitArrayRange R_imm_0(11, 7); +imm += R_imm_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; +static BitArrayRange R_imm_5(31, 25); +imm += R_imm_5.read(ba) << 5; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "sb" << " # " << ba << (" [imm=" + std::to_string(imm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// SH -------------------------------------------------------------------------- +static InstructionDefinition sh_imm_rs1_rs2 ( + ISA32_RV64IMACFD, + "sh", + (uint32_t) 0x001023, + (uint32_t) 0x00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint16 imm = 0; +static BitArrayRange R_imm_0(11, 7); +imm += R_imm_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; +static BitArrayRange R_imm_5(31, 25); +imm += R_imm_5.read(ba) << 5; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//SH\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint64 store_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n"; +cp.code() += "etiss_uint16 mem_val_0;\n"; +cp.code() += "mem_val_0 = (etiss_int16)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n"; +cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, store_address, (etiss_uint8*)&mem_val_0, 2);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); + + cp.code() = std::string("//SH\n"); + +// ----------------------------------------------------------------------------- +cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n"; +// ----------------------------------------------------------------------------- + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint16 imm = 0; +static BitArrayRange R_imm_0(11, 7); +imm += R_imm_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; +static BitArrayRange R_imm_5(31, 25); +imm += R_imm_5.read(ba) << 5; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "sh" << " # " << ba << (" [imm=" + std::to_string(imm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// SW -------------------------------------------------------------------------- +static InstructionDefinition sw_imm_rs1_rs2 ( + ISA32_RV64IMACFD, + "sw", + (uint32_t) 0x002023, + (uint32_t) 0x00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint16 imm = 0; +static BitArrayRange R_imm_0(11, 7); +imm += R_imm_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; +static BitArrayRange R_imm_5(31, 25); +imm += R_imm_5.read(ba) << 5; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//SW\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint64 store_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n"; +cp.code() += "etiss_uint32 mem_val_0;\n"; +cp.code() += "mem_val_0 = (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n"; +cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, store_address, (etiss_uint8*)&mem_val_0, 4);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); + + cp.code() = std::string("//SW\n"); + +// ----------------------------------------------------------------------------- +cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n"; +// ----------------------------------------------------------------------------- + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint16 imm = 0; +static BitArrayRange R_imm_0(11, 7); +imm += R_imm_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; +static BitArrayRange R_imm_5(31, 25); +imm += R_imm_5.read(ba) << 5; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "sw" << " # " << ba << (" [imm=" + std::to_string(imm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// ADDI ------------------------------------------------------------------------ +static InstructionDefinition addi_rd_rs1_imm ( + ISA32_RV64IMACFD, + "addi", + (uint32_t) 0x000013, + (uint32_t) 0x00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint16 imm = 0; +static BitArrayRange R_imm_0(31, 20); +imm += R_imm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//ADDI\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n"; +} // conditional +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint16 imm = 0; +static BitArrayRange R_imm_0(31, 20); +imm += R_imm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "addi" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | imm=" + std::to_string(imm) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// SLTI ------------------------------------------------------------------------ +static InstructionDefinition slti_rd_rs1_imm ( + ISA32_RV64IMACFD, + "slti", + (uint32_t) 0x002013, + (uint32_t) 0x00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint16 imm = 0; +static BitArrayRange R_imm_0(31, 20); +imm += R_imm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//SLTI\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) < " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL)) ? (1ULL) : (0ULL);\n"; +} // conditional +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint16 imm = 0; +static BitArrayRange R_imm_0(31, 20); +imm += R_imm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "slti" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | imm=" + std::to_string(imm) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// SLTIU ----------------------------------------------------------------------- +static InstructionDefinition sltiu_rd_rs1_imm ( + ISA32_RV64IMACFD, + "sltiu", + (uint32_t) 0x003013, + (uint32_t) 0x00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint16 imm = 0; +static BitArrayRange R_imm_0(31, 20); +imm += R_imm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//SLTIU\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = ((*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] < " + std::to_string((etiss_uint64)((((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))))) + "ULL)) ? (1ULL) : (0ULL);\n"; +} // conditional +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint16 imm = 0; +static BitArrayRange R_imm_0(31, 20); +imm += R_imm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "sltiu" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | imm=" + std::to_string(imm) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// XORI ------------------------------------------------------------------------ +static InstructionDefinition xori_rd_rs1_imm ( + ISA32_RV64IMACFD, + "xori", + (uint32_t) 0x004013, + (uint32_t) 0x00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint16 imm = 0; +static BitArrayRange R_imm_0(31, 20); +imm += R_imm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//XORI\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] ^ " + std::to_string((etiss_uint64)((((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))))) + "ULL;\n"; +} // conditional +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint16 imm = 0; +static BitArrayRange R_imm_0(31, 20); +imm += R_imm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "xori" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | imm=" + std::to_string(imm) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// ORI ------------------------------------------------------------------------- +static InstructionDefinition ori_rd_rs1_imm ( + ISA32_RV64IMACFD, + "ori", + (uint32_t) 0x006013, + (uint32_t) 0x00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint16 imm = 0; +static BitArrayRange R_imm_0(31, 20); +imm += R_imm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//ORI\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] | " + std::to_string((etiss_uint64)((((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))))) + "ULL;\n"; +} // conditional +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint16 imm = 0; +static BitArrayRange R_imm_0(31, 20); +imm += R_imm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "ori" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | imm=" + std::to_string(imm) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// ANDI ------------------------------------------------------------------------ +static InstructionDefinition andi_rd_rs1_imm ( + ISA32_RV64IMACFD, + "andi", + (uint32_t) 0x007013, + (uint32_t) 0x00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint16 imm = 0; +static BitArrayRange R_imm_0(31, 20); +imm += R_imm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//ANDI\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] & " + std::to_string((etiss_uint64)((((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))))) + "ULL;\n"; +} // conditional +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint16 imm = 0; +static BitArrayRange R_imm_0(31, 20); +imm += R_imm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "andi" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | imm=" + std::to_string(imm) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// SLLI ------------------------------------------------------------------------ +static InstructionDefinition slli_rd_rs1_shamt ( + ISA32_RV64IMACFD, + "slli", + (uint32_t) 0x001013, + (uint32_t) 0xfe00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 shamt = 0; +static BitArrayRange R_shamt_0(24, 20); +shamt += R_shamt_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//SLLI\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] << " + std::to_string(shamt) + "ULL;\n"; +} // conditional +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 shamt = 0; +static BitArrayRange R_shamt_0(24, 20); +shamt += R_shamt_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "slli" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | shamt=" + std::to_string(shamt) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// SRLI ------------------------------------------------------------------------ +static InstructionDefinition srli_rd_rs1_shamt ( + ISA32_RV64IMACFD, + "srli", + (uint32_t) 0x005013, + (uint32_t) 0xfe00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 shamt = 0; +static BitArrayRange R_shamt_0(24, 20); +shamt += R_shamt_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//SRLI\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] >> " + std::to_string(shamt) + "ULL;\n"; +} // conditional +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 shamt = 0; +static BitArrayRange R_shamt_0(24, 20); +shamt += R_shamt_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "srli" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | shamt=" + std::to_string(shamt) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// SRAI ------------------------------------------------------------------------ +static InstructionDefinition srai_rd_rs1_shamt ( + ISA32_RV64IMACFD, + "srai", + (uint32_t) 0x40005013, + (uint32_t) 0xfe00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 shamt = 0; +static BitArrayRange R_shamt_0(24, 20); +shamt += R_shamt_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//SRAI\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) >> " + std::to_string(shamt) + "ULL;\n"; +} // conditional +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 shamt = 0; +static BitArrayRange R_shamt_0(24, 20); +shamt += R_shamt_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "srai" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | shamt=" + std::to_string(shamt) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// ADD ------------------------------------------------------------------------- +static InstructionDefinition add_rd_rs1_rs2 ( + ISA32_RV64IMACFD, + "add", + (uint32_t) 0x000033, + (uint32_t) 0xfe00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//ADD\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n"; +} // conditional +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "add" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// SUB ------------------------------------------------------------------------- +static InstructionDefinition sub_rd_rs1_rs2 ( + ISA32_RV64IMACFD, + "sub", + (uint32_t) 0x40000033, + (uint32_t) 0xfe00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//SUB\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] - *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n"; +} // conditional +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "sub" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// SLL ------------------------------------------------------------------------- +static InstructionDefinition sll_rd_rs1_rs2 ( + ISA32_RV64IMACFD, + "sll", + (uint32_t) 0x001033, + (uint32_t) 0xfe00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//SLL\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] << (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL] & 63ULL);\n"; +} // conditional +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "sll" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// SLT ------------------------------------------------------------------------- +static InstructionDefinition slt_rd_rs1_rs2 ( + ISA32_RV64IMACFD, + "slt", + (uint32_t) 0x002033, + (uint32_t) 0xfe00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//SLT\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = ((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) < (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL])) ? (1ULL) : (0ULL);\n"; +} // conditional +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "slt" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// SLTU ------------------------------------------------------------------------ +static InstructionDefinition sltu_rd_rs1_rs2 ( + ISA32_RV64IMACFD, + "sltu", + (uint32_t) 0x003033, + (uint32_t) 0xfe00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//SLTU\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] < *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) ? (1ULL) : (0ULL);\n"; +} // conditional +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "sltu" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// XOR ------------------------------------------------------------------------- +static InstructionDefinition xor_rd_rs1_rs2 ( + ISA32_RV64IMACFD, + "xor", + (uint32_t) 0x004033, + (uint32_t) 0xfe00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//XOR\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] ^ *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n"; +} // conditional +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "xor" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// SRL ------------------------------------------------------------------------- +static InstructionDefinition srl_rd_rs1_rs2 ( + ISA32_RV64IMACFD, + "srl", + (uint32_t) 0x005033, + (uint32_t) 0xfe00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//SRL\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] >> (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL] & 63ULL);\n"; +} // conditional +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "srl" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// SRA ------------------------------------------------------------------------- +static InstructionDefinition sra_rd_rs1_rs2 ( + ISA32_RV64IMACFD, + "sra", + (uint32_t) 0x40005033, + (uint32_t) 0xfe00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//SRA\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) >> (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL] & 63ULL);\n"; +} // conditional +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "sra" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// OR -------------------------------------------------------------------------- +static InstructionDefinition or_rd_rs1_rs2 ( + ISA32_RV64IMACFD, + "or", + (uint32_t) 0x006033, + (uint32_t) 0xfe00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//OR\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] | *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n"; +} // conditional +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "or" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// AND ------------------------------------------------------------------------- +static InstructionDefinition and_rd_rs1_rs2 ( + ISA32_RV64IMACFD, + "and", + (uint32_t) 0x007033, + (uint32_t) 0xfe00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//AND\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] & *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n"; +} // conditional +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "and" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// FENCE ----------------------------------------------------------------------- +static InstructionDefinition fence_rd_rs1_succ_pred_fm ( + ISA32_RV64IMACFD, + "fence", + (uint32_t) 0x00000f, + (uint32_t) 0x00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 succ = 0; +static BitArrayRange R_succ_0(23, 20); +succ += R_succ_0.read(ba) << 0; +etiss_uint8 pred = 0; +static BitArrayRange R_pred_0(27, 24); +pred += R_pred_0.read(ba) << 0; +etiss_uint8 fm = 0; +static BitArrayRange R_fm_0(31, 28); +fm += R_fm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//FENCE\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "((RV64IMACFD*)cpu)->FENCE[0ULL] = " + std::to_string(pred << 4ULL | succ) + "ULL;\n"; +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 succ = 0; +static BitArrayRange R_succ_0(23, 20); +succ += R_succ_0.read(ba) << 0; +etiss_uint8 pred = 0; +static BitArrayRange R_pred_0(27, 24); +pred += R_pred_0.read(ba) << 0; +etiss_uint8 fm = 0; +static BitArrayRange R_fm_0(31, 28); +fm += R_fm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "fence" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | succ=" + std::to_string(succ) + " | pred=" + std::to_string(pred) + " | fm=" + std::to_string(fm) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV32MInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32MInstr.cpp new file mode 100644 index 0000000000..eceb074ea4 --- /dev/null +++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV32MInstr.cpp @@ -0,0 +1,373 @@ +/** + * Generated on Tue, 28 Nov 2023 09:45:19 +0100. + * + * This file contains the instruction behavior models of the RV32M + * instruction set for the RV64IMACFD core architecture. + */ + +#include "RV64IMACFDArch.h" +#include "RV64IMACFDFuncs.h" + +using namespace etiss; +using namespace etiss::instr; + + +// DIV ------------------------------------------------------------------------- +static InstructionDefinition div_rd_rs1_rs2 ( + ISA32_RV64IMACFD, + "div", + (uint32_t) 0x2004033, + (uint32_t) 0xfe00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//DIV\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +if ((rd % 32ULL) != 0ULL) { // conditional +{ // block +cp.code() += "{ // block\n"; +cp.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL] != 0ULL) { // conditional\n"; +{ // block +cp.code() += "{ // block\n"; +etiss_uint64 MMIN = 9223372036854775808ULL; +cp.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] == " + std::to_string(MMIN) + "ULL && (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) == -1LL) { // conditional\n"; +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = " + std::to_string(MMIN) + "ULL;\n"; +cp.code() += "} // conditional\n"; +cp.code() += "else { // conditional\n"; +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) / (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n"; +cp.code() += "} // conditional\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "} // conditional\n"; +cp.code() += "else { // conditional\n"; +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = -1LL;\n"; +cp.code() += "} // conditional\n"; +cp.code() += "} // block\n"; +} // block +} // conditional +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "div" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// DIVU ------------------------------------------------------------------------ +static InstructionDefinition divu_rd_rs1_rs2 ( + ISA32_RV64IMACFD, + "divu", + (uint32_t) 0x2005033, + (uint32_t) 0xfe00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//DIVU\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +if ((rd % 32ULL) != 0ULL) { // conditional +{ // block +cp.code() += "{ // block\n"; +cp.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL] != 0ULL) { // conditional\n"; +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] / *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n"; +cp.code() += "} // conditional\n"; +cp.code() += "else { // conditional\n"; +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = -1LL;\n"; +cp.code() += "} // conditional\n"; +cp.code() += "} // block\n"; +} // block +} // conditional +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "divu" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// REM ------------------------------------------------------------------------- +static InstructionDefinition rem_rd_rs1_rs2 ( + ISA32_RV64IMACFD, + "rem", + (uint32_t) 0x2006033, + (uint32_t) 0xfe00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//REM\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +if ((rd % 32ULL) != 0ULL) { // conditional +{ // block +cp.code() += "{ // block\n"; +cp.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL] != 0ULL) { // conditional\n"; +{ // block +cp.code() += "{ // block\n"; +etiss_uint64 MMIN = 9223372036854775808ULL; +cp.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] == " + std::to_string(MMIN) + "ULL && (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) == -1LL) { // conditional\n"; +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = 0ULL;\n"; +cp.code() += "} // conditional\n"; +cp.code() += "else { // conditional\n"; +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) % (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n"; +cp.code() += "} // conditional\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "} // conditional\n"; +cp.code() += "else { // conditional\n"; +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n"; +cp.code() += "} // conditional\n"; +cp.code() += "} // block\n"; +} // block +} // conditional +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "rem" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// REMU ------------------------------------------------------------------------ +static InstructionDefinition remu_rd_rs1_rs2 ( + ISA32_RV64IMACFD, + "remu", + (uint32_t) 0x2007033, + (uint32_t) 0xfe00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//REMU\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +if ((rd % 32ULL) != 0ULL) { // conditional +{ // block +cp.code() += "{ // block\n"; +cp.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL] != 0ULL) { // conditional\n"; +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] % *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n"; +cp.code() += "} // conditional\n"; +cp.code() += "else { // conditional\n"; +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n"; +cp.code() += "} // conditional\n"; +cp.code() += "} // block\n"; +} // block +} // conditional +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "remu" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64AInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64AInstr.cpp new file mode 100644 index 0000000000..6cf1c75bf7 --- /dev/null +++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64AInstr.cpp @@ -0,0 +1,1100 @@ +/** + * Generated on Tue, 28 Nov 2023 09:45:19 +0100. + * + * This file contains the instruction behavior models of the RV64A + * instruction set for the RV64IMACFD core architecture. + */ + +#include "RV64IMACFDArch.h" +#include "RV64IMACFDFuncs.h" + +using namespace etiss; +using namespace etiss::instr; + + +// AMOSWAPD -------------------------------------------------------------------- +static InstructionDefinition amoswapd_rd_rs1_rs2_rl_aq ( + ISA32_RV64IMACFD, + "amoswapd", + (uint32_t) 0x800302f, + (uint32_t) 0xf800707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; +etiss_uint8 rl = 0; +static BitArrayRange R_rl_0(25, 25); +rl += R_rl_0.read(ba) << 0; +etiss_uint8 aq = 0; +static BitArrayRange R_aq_0(26, 26); +aq += R_aq_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//AMOSWAPD\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n"; +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "etiss_uint64 mem_val_0;\n"; +cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int64)(((etiss_int64)(mem_val_0)));\n"; +} // conditional +cp.code() += "etiss_uint64 mem_val_1;\n"; +cp.code() += "mem_val_1 = (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n"; +cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); + + cp.code() = std::string("//AMOSWAPD\n"); + +// ----------------------------------------------------------------------------- +cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n"; +// ----------------------------------------------------------------------------- + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; +etiss_uint8 rl = 0; +static BitArrayRange R_rl_0(25, 25); +rl += R_rl_0.read(ba) << 0; +etiss_uint8 aq = 0; +static BitArrayRange R_aq_0(26, 26); +aq += R_aq_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "amoswapd" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + " | rl=" + std::to_string(rl) + " | aq=" + std::to_string(aq) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// AMOADDD --------------------------------------------------------------------- +static InstructionDefinition amoaddd_rd_rs1_rs2_rl_aq ( + ISA32_RV64IMACFD, + "amoaddd", + (uint32_t) 0x00302f, + (uint32_t) 0xf800707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; +etiss_uint8 rl = 0; +static BitArrayRange R_rl_0(25, 25); +rl += R_rl_0.read(ba) << 0; +etiss_uint8 aq = 0; +static BitArrayRange R_aq_0(26, 26); +aq += R_aq_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//AMOADDD\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n"; +cp.code() += "etiss_uint64 mem_val_0;\n"; +cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "etiss_int64 res = mem_val_0;\n"; +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res;\n"; +} // conditional +cp.code() += "etiss_uint64 res2 = res + *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n"; +cp.code() += "etiss_uint64 mem_val_1;\n"; +cp.code() += "mem_val_1 = res2;\n"; +cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); + + cp.code() = std::string("//AMOADDD\n"); + +// ----------------------------------------------------------------------------- +cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n"; +// ----------------------------------------------------------------------------- + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; +etiss_uint8 rl = 0; +static BitArrayRange R_rl_0(25, 25); +rl += R_rl_0.read(ba) << 0; +etiss_uint8 aq = 0; +static BitArrayRange R_aq_0(26, 26); +aq += R_aq_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "amoaddd" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + " | rl=" + std::to_string(rl) + " | aq=" + std::to_string(aq) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// AMOXORD --------------------------------------------------------------------- +static InstructionDefinition amoxord_rd_rs1_rs2_rl_aq ( + ISA32_RV64IMACFD, + "amoxord", + (uint32_t) 0x2000302f, + (uint32_t) 0xf800707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; +etiss_uint8 rl = 0; +static BitArrayRange R_rl_0(25, 25); +rl += R_rl_0.read(ba) << 0; +etiss_uint8 aq = 0; +static BitArrayRange R_aq_0(26, 26); +aq += R_aq_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//AMOXORD\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n"; +cp.code() += "etiss_uint64 mem_val_0;\n"; +cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "etiss_int64 res = mem_val_0;\n"; +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res;\n"; +} // conditional +cp.code() += "etiss_uint64 res2 = res ^ *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n"; +cp.code() += "etiss_uint64 mem_val_1;\n"; +cp.code() += "mem_val_1 = res2;\n"; +cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); + + cp.code() = std::string("//AMOXORD\n"); + +// ----------------------------------------------------------------------------- +cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n"; +// ----------------------------------------------------------------------------- + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; +etiss_uint8 rl = 0; +static BitArrayRange R_rl_0(25, 25); +rl += R_rl_0.read(ba) << 0; +etiss_uint8 aq = 0; +static BitArrayRange R_aq_0(26, 26); +aq += R_aq_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "amoxord" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + " | rl=" + std::to_string(rl) + " | aq=" + std::to_string(aq) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// AMOANDD --------------------------------------------------------------------- +static InstructionDefinition amoandd_rd_rs1_rs2_rl_aq ( + ISA32_RV64IMACFD, + "amoandd", + (uint32_t) 0x6000302f, + (uint32_t) 0xf800707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; +etiss_uint8 rl = 0; +static BitArrayRange R_rl_0(25, 25); +rl += R_rl_0.read(ba) << 0; +etiss_uint8 aq = 0; +static BitArrayRange R_aq_0(26, 26); +aq += R_aq_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//AMOANDD\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n"; +cp.code() += "etiss_uint64 mem_val_0;\n"; +cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "etiss_int64 res = mem_val_0;\n"; +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res;\n"; +} // conditional +cp.code() += "etiss_uint64 res2 = res & *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n"; +cp.code() += "etiss_uint64 mem_val_1;\n"; +cp.code() += "mem_val_1 = res2;\n"; +cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); + + cp.code() = std::string("//AMOANDD\n"); + +// ----------------------------------------------------------------------------- +cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n"; +// ----------------------------------------------------------------------------- + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; +etiss_uint8 rl = 0; +static BitArrayRange R_rl_0(25, 25); +rl += R_rl_0.read(ba) << 0; +etiss_uint8 aq = 0; +static BitArrayRange R_aq_0(26, 26); +aq += R_aq_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "amoandd" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + " | rl=" + std::to_string(rl) + " | aq=" + std::to_string(aq) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// AMOORD ---------------------------------------------------------------------- +static InstructionDefinition amoord_rd_rs1_rs2_rl_aq ( + ISA32_RV64IMACFD, + "amoord", + (uint32_t) 0x4000302f, + (uint32_t) 0xf800707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; +etiss_uint8 rl = 0; +static BitArrayRange R_rl_0(25, 25); +rl += R_rl_0.read(ba) << 0; +etiss_uint8 aq = 0; +static BitArrayRange R_aq_0(26, 26); +aq += R_aq_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//AMOORD\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n"; +cp.code() += "etiss_uint64 mem_val_0;\n"; +cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "etiss_int64 res = mem_val_0;\n"; +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res;\n"; +} // conditional +cp.code() += "etiss_uint64 res2 = (((res) << 64) | (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]));\n"; +cp.code() += "etiss_uint64 mem_val_1;\n"; +cp.code() += "mem_val_1 = res2;\n"; +cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); + + cp.code() = std::string("//AMOORD\n"); + +// ----------------------------------------------------------------------------- +cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n"; +// ----------------------------------------------------------------------------- + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; +etiss_uint8 rl = 0; +static BitArrayRange R_rl_0(25, 25); +rl += R_rl_0.read(ba) << 0; +etiss_uint8 aq = 0; +static BitArrayRange R_aq_0(26, 26); +aq += R_aq_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "amoord" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + " | rl=" + std::to_string(rl) + " | aq=" + std::to_string(aq) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// AMOMIND --------------------------------------------------------------------- +static InstructionDefinition amomind_rd_rs1_rs2_rl_aq ( + ISA32_RV64IMACFD, + "amomind", + (uint32_t) 0x8000302f, + (uint32_t) 0xf800707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; +etiss_uint8 rl = 0; +static BitArrayRange R_rl_0(25, 25); +rl += R_rl_0.read(ba) << 0; +etiss_uint8 aq = 0; +static BitArrayRange R_aq_0(26, 26); +aq += R_aq_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//AMOMIND\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n"; +cp.code() += "etiss_uint64 mem_val_0;\n"; +cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "etiss_int64 res1 = mem_val_0;\n"; +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res1;\n"; +} // conditional +cp.code() += "etiss_uint64 res2 = (res1 > (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL])) ? (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) : (res1);\n"; +cp.code() += "etiss_uint64 mem_val_1;\n"; +cp.code() += "mem_val_1 = res2;\n"; +cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); + + cp.code() = std::string("//AMOMIND\n"); + +// ----------------------------------------------------------------------------- +cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n"; +// ----------------------------------------------------------------------------- + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; +etiss_uint8 rl = 0; +static BitArrayRange R_rl_0(25, 25); +rl += R_rl_0.read(ba) << 0; +etiss_uint8 aq = 0; +static BitArrayRange R_aq_0(26, 26); +aq += R_aq_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "amomind" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + " | rl=" + std::to_string(rl) + " | aq=" + std::to_string(aq) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// AMOMAXD --------------------------------------------------------------------- +static InstructionDefinition amomaxd_rd_rs1_rs2_rl_aq ( + ISA32_RV64IMACFD, + "amomaxd", + (uint32_t) 0xa000302f, + (uint32_t) 0xf800707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; +etiss_uint8 rl = 0; +static BitArrayRange R_rl_0(25, 25); +rl += R_rl_0.read(ba) << 0; +etiss_uint8 aq = 0; +static BitArrayRange R_aq_0(26, 26); +aq += R_aq_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//AMOMAXD\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n"; +cp.code() += "etiss_uint64 mem_val_0;\n"; +cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "etiss_int64 res = mem_val_0;\n"; +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res;\n"; +} // conditional +cp.code() += "etiss_uint64 res2 = (res < (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL])) ? (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) : (res);\n"; +cp.code() += "etiss_uint64 mem_val_1;\n"; +cp.code() += "mem_val_1 = res2;\n"; +cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); + + cp.code() = std::string("//AMOMAXD\n"); + +// ----------------------------------------------------------------------------- +cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n"; +// ----------------------------------------------------------------------------- + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; +etiss_uint8 rl = 0; +static BitArrayRange R_rl_0(25, 25); +rl += R_rl_0.read(ba) << 0; +etiss_uint8 aq = 0; +static BitArrayRange R_aq_0(26, 26); +aq += R_aq_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "amomaxd" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + " | rl=" + std::to_string(rl) + " | aq=" + std::to_string(aq) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// AMOMINUD -------------------------------------------------------------------- +static InstructionDefinition amominud_rd_rs1_rs2_rl_aq ( + ISA32_RV64IMACFD, + "amominud", + (uint32_t) 0xc000302f, + (uint32_t) 0xf800707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; +etiss_uint8 rl = 0; +static BitArrayRange R_rl_0(25, 25); +rl += R_rl_0.read(ba) << 0; +etiss_uint8 aq = 0; +static BitArrayRange R_aq_0(26, 26); +aq += R_aq_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//AMOMINUD\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n"; +cp.code() += "etiss_uint64 mem_val_0;\n"; +cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "etiss_uint64 res = mem_val_0;\n"; +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int64)(res);\n"; +} // conditional +cp.code() += "etiss_uint64 res2 = (res > *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) ? (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) : (res);\n"; +cp.code() += "etiss_uint64 mem_val_1;\n"; +cp.code() += "mem_val_1 = res2;\n"; +cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); + + cp.code() = std::string("//AMOMINUD\n"); + +// ----------------------------------------------------------------------------- +cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n"; +// ----------------------------------------------------------------------------- + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; +etiss_uint8 rl = 0; +static BitArrayRange R_rl_0(25, 25); +rl += R_rl_0.read(ba) << 0; +etiss_uint8 aq = 0; +static BitArrayRange R_aq_0(26, 26); +aq += R_aq_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "amominud" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + " | rl=" + std::to_string(rl) + " | aq=" + std::to_string(aq) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// AMOMAXUD -------------------------------------------------------------------- +static InstructionDefinition amomaxud_rd_rs1_rs2_rl_aq ( + ISA32_RV64IMACFD, + "amomaxud", + (uint32_t) 0xe000302f, + (uint32_t) 0xf800707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; +etiss_uint8 rl = 0; +static BitArrayRange R_rl_0(25, 25); +rl += R_rl_0.read(ba) << 0; +etiss_uint8 aq = 0; +static BitArrayRange R_aq_0(26, 26); +aq += R_aq_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//AMOMAXUD\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n"; +cp.code() += "etiss_uint64 mem_val_0;\n"; +cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "etiss_uint64 res1 = mem_val_0;\n"; +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int64)(res1);\n"; +} // conditional +cp.code() += "etiss_uint64 res2 = (res1 < *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) ? (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) : (res1);\n"; +cp.code() += "etiss_uint64 mem_val_1;\n"; +cp.code() += "mem_val_1 = res2;\n"; +cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); + + cp.code() = std::string("//AMOMAXUD\n"); + +// ----------------------------------------------------------------------------- +cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n"; +// ----------------------------------------------------------------------------- + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; +etiss_uint8 rl = 0; +static BitArrayRange R_rl_0(25, 25); +rl += R_rl_0.read(ba) << 0; +etiss_uint8 aq = 0; +static BitArrayRange R_aq_0(26, 26); +aq += R_aq_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "amomaxud" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + " | rl=" + std::to_string(rl) + " | aq=" + std::to_string(aq) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64DInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64DInstr.cpp new file mode 100644 index 0000000000..87e5e07efa --- /dev/null +++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64DInstr.cpp @@ -0,0 +1,451 @@ +/** + * Generated on Tue, 28 Nov 2023 09:45:19 +0100. + * + * This file contains the instruction behavior models of the RV64D + * instruction set for the RV64IMACFD core architecture. + */ + +#include "RV64IMACFDArch.h" +#include "RV64IMACFDFuncs.h" + +using namespace etiss; +using namespace etiss::instr; + + +// FCVT_L_D -------------------------------------------------------------------- +static InstructionDefinition fcvt_l_d_rd_rm_rs1 ( + ISA32_RV64IMACFD, + "fcvt_l_d", + (uint32_t) 0xc2200053, + (uint32_t) 0xfff0007f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rm = 0; +static BitArrayRange R_rm_0(14, 12); +rm += R_rm_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//FCVT_L_D\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = fcvt_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), 0ULL, " + std::to_string(rm) + "ULL);\n"; +cp.code() += "etiss_uint32 flags = fget_flags();\n"; +cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rm = 0; +static BitArrayRange R_rm_0(14, 12); +rm += R_rm_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "fcvt_l_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// FCVT_LU_D ------------------------------------------------------------------- +static InstructionDefinition fcvt_lu_d_rd_rm_rs1 ( + ISA32_RV64IMACFD, + "fcvt_lu_d", + (uint32_t) 0xc2300053, + (uint32_t) 0xfff0007f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rm = 0; +static BitArrayRange R_rm_0(14, 12); +rm += R_rm_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//FCVT_LU_D\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = fcvt_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), 1ULL, " + std::to_string(rm) + "ULL);\n"; +cp.code() += "etiss_uint32 flags = fget_flags();\n"; +cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rm = 0; +static BitArrayRange R_rm_0(14, 12); +rm += R_rm_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "fcvt_lu_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// FCVT_D_L -------------------------------------------------------------------- +static InstructionDefinition fcvt_d_l_rd_rm_rs1 ( + ISA32_RV64IMACFD, + "fcvt_d_l", + (uint32_t) 0xd2200053, + (uint32_t) 0xfff0007f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rm = 0; +static BitArrayRange R_rm_0(14, 12); +rm += R_rm_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//FCVT_D_L\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint64 res = fcvt_d(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL], 2ULL, " + std::to_string(rm) + "ULL);\n"; +cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rm = 0; +static BitArrayRange R_rm_0(14, 12); +rm += R_rm_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "fcvt_d_l" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// FCVT_D_LU ------------------------------------------------------------------- +static InstructionDefinition fcvt_d_lu_rd_rm_rs1 ( + ISA32_RV64IMACFD, + "fcvt_d_lu", + (uint32_t) 0xd2300053, + (uint32_t) 0xfff0007f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rm = 0; +static BitArrayRange R_rm_0(14, 12); +rm += R_rm_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//FCVT_D_LU\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint64 res = fcvt_d(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL], 3ULL, " + std::to_string(rm) + "ULL);\n"; +cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rm = 0; +static BitArrayRange R_rm_0(14, 12); +rm += R_rm_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "fcvt_d_lu" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// FMV_X_D --------------------------------------------------------------------- +static InstructionDefinition fmv_x_d_rd_rs1 ( + ISA32_RV64IMACFD, + "fmv_x_d", + (uint32_t) 0xe2000053, + (uint32_t) 0xfff0707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//FMV_X_D\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = ((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL];\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "fmv_x_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// FMV_D_X --------------------------------------------------------------------- +static InstructionDefinition fmv_d_x_rd_rs1 ( + ISA32_RV64IMACFD, + "fmv_d_x", + (uint32_t) 0xf2000053, + (uint32_t) 0xfff0707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//FMV_D_X\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "fmv_d_x" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64FInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64FInstr.cpp new file mode 100644 index 0000000000..9eb52e39db --- /dev/null +++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64FInstr.cpp @@ -0,0 +1,329 @@ +/** + * Generated on Tue, 28 Nov 2023 09:45:19 +0100. + * + * This file contains the instruction behavior models of the RV64F + * instruction set for the RV64IMACFD core architecture. + */ + +#include "RV64IMACFDArch.h" +#include "RV64IMACFDFuncs.h" + +using namespace etiss; +using namespace etiss::instr; + + +// FCVT_L_S -------------------------------------------------------------------- +static InstructionDefinition fcvt_l_s_rd_rm_rs1 ( + ISA32_RV64IMACFD, + "fcvt_l_s", + (uint32_t) 0xc0200053, + (uint32_t) 0xfff0007f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rm = 0; +static BitArrayRange R_rm_0(14, 12); +rm += R_rm_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//FCVT_L_S\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_int64 res = fcvt_32_64(unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), 0ULL, " + std::to_string(rm) + "ULL);\n"; +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res;\n"; +} // conditional +cp.code() += "etiss_uint32 flags = fget_flags();\n"; +cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rm = 0; +static BitArrayRange R_rm_0(14, 12); +rm += R_rm_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "fcvt_l_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// FCVT_LU_S ------------------------------------------------------------------- +static InstructionDefinition fcvt_lu_s_rd_rm_rs1 ( + ISA32_RV64IMACFD, + "fcvt_lu_s", + (uint32_t) 0xc0300053, + (uint32_t) 0xfff0007f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rm = 0; +static BitArrayRange R_rm_0(14, 12); +rm += R_rm_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//FCVT_LU_S\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint64 res = fcvt_32_64(unbox_s(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), 1ULL, " + std::to_string(rm) + "ULL);\n"; +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res;\n"; +} // conditional +cp.code() += "etiss_uint32 flags = fget_flags();\n"; +cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rm = 0; +static BitArrayRange R_rm_0(14, 12); +rm += R_rm_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "fcvt_lu_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// FCVT_S_L -------------------------------------------------------------------- +static InstructionDefinition fcvt_s_l_rd_rm_rs1 ( + ISA32_RV64IMACFD, + "fcvt_s_l", + (uint32_t) 0xd0200053, + (uint32_t) 0xfff0007f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rm = 0; +static BitArrayRange R_rm_0(14, 12); +rm += R_rm_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//FCVT_S_L\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint32 res = fcvt_64_32(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL], 2ULL, " + std::to_string(rm) + "ULL);\n"; +{ // block +cp.code() += "{ // block\n"; +cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rm = 0; +static BitArrayRange R_rm_0(14, 12); +rm += R_rm_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "fcvt_s_l" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// FCVT_S_LU ------------------------------------------------------------------- +static InstructionDefinition fcvt_s_lu_rd_rm_rs1 ( + ISA32_RV64IMACFD, + "fcvt_s_lu", + (uint32_t) 0xd0300053, + (uint32_t) 0xfff0007f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rm = 0; +static BitArrayRange R_rm_0(14, 12); +rm += R_rm_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//FCVT_S_LU\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint32 res = fcvt_64_32(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL], 3ULL, " + std::to_string(rm) + "ULL);\n"; +{ // block +cp.code() += "{ // block\n"; +cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rm = 0; +static BitArrayRange R_rm_0(14, 12); +rm += R_rm_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "fcvt_s_lu" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64ICInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64ICInstr.cpp new file mode 100644 index 0000000000..9e2d0d1304 --- /dev/null +++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64ICInstr.cpp @@ -0,0 +1,849 @@ +/** + * Generated on Tue, 28 Nov 2023 09:45:19 +0100. + * + * This file contains the instruction behavior models of the RV64IC + * instruction set for the RV64IMACFD core architecture. + */ + +#include "RV64IMACFDArch.h" +#include "RV64IMACFDFuncs.h" + +using namespace etiss; +using namespace etiss::instr; + + +// CADDIW ---------------------------------------------------------------------- +static InstructionDefinition caddiw_imm_rs1 ( + ISA16_RV64IMACFD, + "caddiw", + (uint16_t) 0x2001, + (uint16_t) 0xe003, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 imm = 0; +static BitArrayRange R_imm_0(6, 2); +imm += R_imm_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(11, 7); +rs1 += R_rs1_0.read(ba) << 0; +static BitArrayRange R_imm_5(12, 12); +imm += R_imm_5.read(ba) << 5; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//CADDIW\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +if ((rs1 % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] = (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) + " + std::to_string(((etiss_int8)(((etiss_int8)imm) << (2)) >> (2))) + "LL;\n"; +} // conditional +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 imm = 0; +static BitArrayRange R_imm_0(6, 2); +imm += R_imm_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(11, 7); +rs1 += R_rs1_0.read(ba) << 0; +static BitArrayRange R_imm_5(12, 12); +imm += R_imm_5.read(ba) << 5; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "caddiw" << " # " << ba << (" [imm=" + std::to_string(imm) + " | rs1=" + std::to_string(rs1) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// CSRLI ----------------------------------------------------------------------- +static InstructionDefinition csrli_nzuimm_rs1 ( + ISA16_RV64IMACFD, + "csrli", + (uint16_t) 0x8001, + (uint16_t) 0xec03, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 nzuimm = 0; +static BitArrayRange R_nzuimm_0(6, 2); +nzuimm += R_nzuimm_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(9, 7); +rs1 += R_rs1_0.read(ba) << 0; +static BitArrayRange R_nzuimm_5(12, 12); +nzuimm += R_nzuimm_5.read(ba) << 5; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//CSRLI\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] >> " + std::to_string(nzuimm) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 nzuimm = 0; +static BitArrayRange R_nzuimm_0(6, 2); +nzuimm += R_nzuimm_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(9, 7); +rs1 += R_rs1_0.read(ba) << 0; +static BitArrayRange R_nzuimm_5(12, 12); +nzuimm += R_nzuimm_5.read(ba) << 5; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "csrli" << " # " << ba << (" [nzuimm=" + std::to_string(nzuimm) + " | rs1=" + std::to_string(rs1) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// CSRAI ----------------------------------------------------------------------- +static InstructionDefinition csrai_shamt_rs1 ( + ISA16_RV64IMACFD, + "csrai", + (uint16_t) 0x8401, + (uint16_t) 0xec03, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 shamt = 0; +static BitArrayRange R_shamt_0(6, 2); +shamt += R_shamt_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(9, 7); +rs1 += R_rs1_0.read(ba) << 0; +static BitArrayRange R_shamt_5(12, 12); +shamt += R_shamt_5.read(ba) << 5; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//CSRAI\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] = ((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL])) >> " + std::to_string(shamt) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 shamt = 0; +static BitArrayRange R_shamt_0(6, 2); +shamt += R_shamt_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(9, 7); +rs1 += R_rs1_0.read(ba) << 0; +static BitArrayRange R_shamt_5(12, 12); +shamt += R_shamt_5.read(ba) << 5; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "csrai" << " # " << ba << (" [shamt=" + std::to_string(shamt) + " | rs1=" + std::to_string(rs1) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// CSLLI ----------------------------------------------------------------------- +static InstructionDefinition cslli_shamt_rs1 ( + ISA16_RV64IMACFD, + "cslli", + (uint16_t) 0x02, + (uint16_t) 0xe003, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 shamt = 0; +static BitArrayRange R_shamt_0(6, 2); +shamt += R_shamt_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(11, 7); +rs1 += R_rs1_0.read(ba) << 0; +static BitArrayRange R_shamt_5(12, 12); +shamt += R_shamt_5.read(ba) << 5; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//CSLLI\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +if (rs1 == 0ULL) { // conditional +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV64IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 2ULL);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +} // conditional +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1) + "ULL] << " + std::to_string(shamt) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); + + cp.code() = std::string("//CSLLI\n"); + +// ----------------------------------------------------------------------------- +cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n"; +// ----------------------------------------------------------------------------- + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 shamt = 0; +static BitArrayRange R_shamt_0(6, 2); +shamt += R_shamt_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(11, 7); +rs1 += R_rs1_0.read(ba) << 0; +static BitArrayRange R_shamt_5(12, 12); +shamt += R_shamt_5.read(ba) << 5; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "cslli" << " # " << ba << (" [shamt=" + std::to_string(shamt) + " | rs1=" + std::to_string(rs1) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// CLD ------------------------------------------------------------------------- +static InstructionDefinition cld_rd_uimm_rs1 ( + ISA16_RV64IMACFD, + "cld", + (uint16_t) 0x6000, + (uint16_t) 0xe003, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(4, 2); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 uimm = 0; +static BitArrayRange R_uimm_6(6, 5); +uimm += R_uimm_6.read(ba) << 6; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(9, 7); +rs1 += R_rs1_0.read(ba) << 0; +static BitArrayRange R_uimm_3(12, 10); +uimm += R_uimm_3.read(ba) << 3; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//CLD\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] + " + std::to_string(uimm) + "ULL;\n"; +cp.code() += "etiss_uint64 mem_val_0;\n"; +cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) + "ULL] = (etiss_int64)(mem_val_0);\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); + + cp.code() = std::string("//CLD\n"); + +// ----------------------------------------------------------------------------- +cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n"; +// ----------------------------------------------------------------------------- + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(4, 2); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 uimm = 0; +static BitArrayRange R_uimm_6(6, 5); +uimm += R_uimm_6.read(ba) << 6; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(9, 7); +rs1 += R_rs1_0.read(ba) << 0; +static BitArrayRange R_uimm_3(12, 10); +uimm += R_uimm_3.read(ba) << 3; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "cld" << " # " << ba << (" [rd=" + std::to_string(rd) + " | uimm=" + std::to_string(uimm) + " | rs1=" + std::to_string(rs1) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// CSD ------------------------------------------------------------------------- +static InstructionDefinition csd_rs2_uimm_rs1 ( + ISA16_RV64IMACFD, + "csd", + (uint16_t) 0xe000, + (uint16_t) 0xe003, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(4, 2); +rs2 += R_rs2_0.read(ba) << 0; +etiss_uint8 uimm = 0; +static BitArrayRange R_uimm_6(6, 5); +uimm += R_uimm_6.read(ba) << 6; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(9, 7); +rs1 += R_rs1_0.read(ba) << 0; +static BitArrayRange R_uimm_3(12, 10); +uimm += R_uimm_3.read(ba) << 3; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//CSD\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] + " + std::to_string(uimm) + "ULL;\n"; +cp.code() += "etiss_uint64 mem_val_0;\n"; +cp.code() += "mem_val_0 = (etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 + 8ULL) + "ULL]);\n"; +cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); + + cp.code() = std::string("//CSD\n"); + +// ----------------------------------------------------------------------------- +cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n"; +// ----------------------------------------------------------------------------- + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(4, 2); +rs2 += R_rs2_0.read(ba) << 0; +etiss_uint8 uimm = 0; +static BitArrayRange R_uimm_6(6, 5); +uimm += R_uimm_6.read(ba) << 6; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(9, 7); +rs1 += R_rs1_0.read(ba) << 0; +static BitArrayRange R_uimm_3(12, 10); +uimm += R_uimm_3.read(ba) << 3; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "csd" << " # " << ba << (" [rs2=" + std::to_string(rs2) + " | uimm=" + std::to_string(uimm) + " | rs1=" + std::to_string(rs1) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// CSUBW ----------------------------------------------------------------------- +static InstructionDefinition csubw_rs2_rd ( + ISA16_RV64IMACFD, + "csubw", + (uint16_t) 0x9c01, + (uint16_t) 0xfc63, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(4, 2); +rs2 += R_rs2_0.read(ba) << 0; +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(9, 7); +rd += R_rd_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//CSUBW\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint32 res = (etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) + "ULL]) - (etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 + 8ULL) + "ULL]);\n"; +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) + "ULL] = (etiss_uint64)((etiss_int32)(res));\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(4, 2); +rs2 += R_rs2_0.read(ba) << 0; +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(9, 7); +rd += R_rd_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "csubw" << " # " << ba << (" [rs2=" + std::to_string(rs2) + " | rd=" + std::to_string(rd) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// CADDW ----------------------------------------------------------------------- +static InstructionDefinition caddw_rs2_rd ( + ISA16_RV64IMACFD, + "caddw", + (uint16_t) 0x9c21, + (uint16_t) 0xfc63, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(4, 2); +rs2 += R_rs2_0.read(ba) << 0; +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(9, 7); +rd += R_rd_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//CADDW\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint32 res = (etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) + "ULL]) + (etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 + 8ULL) + "ULL]);\n"; +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) + "ULL] = (etiss_uint64)((etiss_int32)(res));\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(4, 2); +rs2 += R_rs2_0.read(ba) << 0; +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(9, 7); +rd += R_rd_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "caddw" << " # " << ba << (" [rs2=" + std::to_string(rs2) + " | rd=" + std::to_string(rd) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// CLDSP ----------------------------------------------------------------------- +static InstructionDefinition cldsp_uimm_rd ( + ISA16_RV64IMACFD, + "cldsp", + (uint16_t) 0x6002, + (uint16_t) 0xe003, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint16 uimm = 0; +static BitArrayRange R_uimm_6(4, 2); +uimm += R_uimm_6.read(ba) << 6; +static BitArrayRange R_uimm_3(6, 5); +uimm += R_uimm_3.read(ba) << 3; +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +static BitArrayRange R_uimm_5(12, 12); +uimm += R_uimm_5.read(ba) << 5; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//CLDSP\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[2ULL] + " + std::to_string(uimm) + "ULL;\n"; +cp.code() += "etiss_uint64 mem_val_0;\n"; +cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "etiss_int64 res = mem_val_0;\n"; +if (rd % 32ULL) { // conditional +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res;\n"; +} // conditional +else { // conditional +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV64IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 2ULL);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +} // conditional +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); + + cp.code() = std::string("//CLDSP\n"); + +// ----------------------------------------------------------------------------- +cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n"; +// ----------------------------------------------------------------------------- + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint16 uimm = 0; +static BitArrayRange R_uimm_6(4, 2); +uimm += R_uimm_6.read(ba) << 6; +static BitArrayRange R_uimm_3(6, 5); +uimm += R_uimm_3.read(ba) << 3; +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +static BitArrayRange R_uimm_5(12, 12); +uimm += R_uimm_5.read(ba) << 5; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "cldsp" << " # " << ba << (" [uimm=" + std::to_string(uimm) + " | rd=" + std::to_string(rd) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// CSDSP ----------------------------------------------------------------------- +static InstructionDefinition csdsp_rs2_uimm ( + ISA16_RV64IMACFD, + "csdsp", + (uint16_t) 0xe002, + (uint16_t) 0xe003, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(6, 2); +rs2 += R_rs2_0.read(ba) << 0; +etiss_uint16 uimm = 0; +static BitArrayRange R_uimm_6(9, 7); +uimm += R_uimm_6.read(ba) << 6; +static BitArrayRange R_uimm_3(12, 10); +uimm += R_uimm_3.read(ba) << 3; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//CSDSP\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[2ULL] + " + std::to_string(uimm) + "ULL;\n"; +cp.code() += "etiss_uint64 mem_val_0;\n"; +cp.code() += "mem_val_0 = (etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n"; +cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); + + cp.code() = std::string("//CSDSP\n"); + +// ----------------------------------------------------------------------------- +cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n"; +// ----------------------------------------------------------------------------- + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(6, 2); +rs2 += R_rs2_0.read(ba) << 0; +etiss_uint16 uimm = 0; +static BitArrayRange R_uimm_6(9, 7); +uimm += R_uimm_6.read(ba) << 6; +static BitArrayRange R_uimm_3(12, 10); +uimm += R_uimm_3.read(ba) << 3; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "csdsp" << " # " << ba << (" [rs2=" + std::to_string(rs2) + " | uimm=" + std::to_string(uimm) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64IInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64IInstr.cpp new file mode 100644 index 0000000000..1137b30d09 --- /dev/null +++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64IInstr.cpp @@ -0,0 +1,1253 @@ +/** + * Generated on Tue, 28 Nov 2023 09:45:19 +0100. + * + * This file contains the instruction behavior models of the RV64I + * instruction set for the RV64IMACFD core architecture. + */ + +#include "RV64IMACFDArch.h" +#include "RV64IMACFDFuncs.h" + +using namespace etiss; +using namespace etiss::instr; + + +// LWU ------------------------------------------------------------------------- +static InstructionDefinition lwu_rd_rs1_imm ( + ISA32_RV64IMACFD, + "lwu", + (uint32_t) 0x006003, + (uint32_t) 0x00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint16 imm = 0; +static BitArrayRange R_imm_0(31, 20); +imm += R_imm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//LWU\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n"; +cp.code() += "etiss_uint32 mem_val_0;\n"; +cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "etiss_uint32 res = (etiss_uint32)(mem_val_0);\n"; +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint64)(res);\n"; +} // conditional +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); + + cp.code() = std::string("//LWU\n"); + +// ----------------------------------------------------------------------------- +cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n"; +// ----------------------------------------------------------------------------- + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint16 imm = 0; +static BitArrayRange R_imm_0(31, 20); +imm += R_imm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "lwu" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | imm=" + std::to_string(imm) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// LD -------------------------------------------------------------------------- +static InstructionDefinition ld_rd_rs1_imm ( + ISA32_RV64IMACFD, + "ld", + (uint32_t) 0x003003, + (uint32_t) 0x00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint16 imm = 0; +static BitArrayRange R_imm_0(31, 20); +imm += R_imm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//LD\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n"; +cp.code() += "etiss_uint64 mem_val_0;\n"; +cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "etiss_int64 res = (etiss_int64)(mem_val_0);\n"; +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint64)(res);\n"; +} // conditional +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); + + cp.code() = std::string("//LD\n"); + +// ----------------------------------------------------------------------------- +cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n"; +// ----------------------------------------------------------------------------- + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint16 imm = 0; +static BitArrayRange R_imm_0(31, 20); +imm += R_imm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "ld" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | imm=" + std::to_string(imm) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// SD -------------------------------------------------------------------------- +static InstructionDefinition sd_imm_rs1_rs2 ( + ISA32_RV64IMACFD, + "sd", + (uint32_t) 0x003023, + (uint32_t) 0x00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint16 imm = 0; +static BitArrayRange R_imm_0(11, 7); +imm += R_imm_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; +static BitArrayRange R_imm_5(31, 25); +imm += R_imm_5.read(ba) << 5; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//SD\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n"; +cp.code() += "etiss_uint64 mem_val_0;\n"; +cp.code() += "mem_val_0 = (etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n"; +cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); + + cp.code() = std::string("//SD\n"); + +// ----------------------------------------------------------------------------- +cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n"; +// ----------------------------------------------------------------------------- + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint16 imm = 0; +static BitArrayRange R_imm_0(11, 7); +imm += R_imm_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; +static BitArrayRange R_imm_5(31, 25); +imm += R_imm_5.read(ba) << 5; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "sd" << " # " << ba << (" [imm=" + std::to_string(imm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// SLLI ------------------------------------------------------------------------ +static InstructionDefinition slli_rd_rs1_shamt ( + ISA32_RV64IMACFD, + "slli", + (uint32_t) 0x001013, + (uint32_t) 0xfc00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 shamt = 0; +static BitArrayRange R_shamt_0(25, 20); +shamt += R_shamt_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//SLLI\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] << " + std::to_string(shamt) + "ULL;\n"; +} // conditional +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 shamt = 0; +static BitArrayRange R_shamt_0(25, 20); +shamt += R_shamt_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "slli" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | shamt=" + std::to_string(shamt) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// SRLI ------------------------------------------------------------------------ +static InstructionDefinition srli_rd_rs1_shamt ( + ISA32_RV64IMACFD, + "srli", + (uint32_t) 0x005013, + (uint32_t) 0xfc00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 shamt = 0; +static BitArrayRange R_shamt_0(25, 20); +shamt += R_shamt_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//SRLI\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] >> " + std::to_string(shamt) + "ULL;\n"; +} // conditional +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 shamt = 0; +static BitArrayRange R_shamt_0(25, 20); +shamt += R_shamt_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "srli" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | shamt=" + std::to_string(shamt) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// SRAI ------------------------------------------------------------------------ +static InstructionDefinition srai_rd_rs1_shamt ( + ISA32_RV64IMACFD, + "srai", + (uint32_t) 0x40005013, + (uint32_t) 0xfc00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 shamt = 0; +static BitArrayRange R_shamt_0(25, 20); +shamt += R_shamt_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//SRAI\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = ((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL])) >> " + std::to_string(shamt) + "ULL;\n"; +} // conditional +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 shamt = 0; +static BitArrayRange R_shamt_0(25, 20); +shamt += R_shamt_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "srai" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | shamt=" + std::to_string(shamt) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// ADDIW ----------------------------------------------------------------------- +static InstructionDefinition addiw_rd_rs1_imm ( + ISA32_RV64IMACFD, + "addiw", + (uint32_t) 0x00001b, + (uint32_t) 0x00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint16 imm = 0; +static BitArrayRange R_imm_0(31, 20); +imm += R_imm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//ADDIW\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +if ((rd % 32ULL) != 0ULL) { // conditional +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_int32 res = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n"; +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int64)(res);\n"; +cp.code() += "} // block\n"; +} // block +} // conditional +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint16 imm = 0; +static BitArrayRange R_imm_0(31, 20); +imm += R_imm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "addiw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | imm=" + std::to_string(imm) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// SLLIW ----------------------------------------------------------------------- +static InstructionDefinition slliw_rd_rs1_shamt ( + ISA32_RV64IMACFD, + "slliw", + (uint32_t) 0x00101b, + (uint32_t) 0xfe00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 shamt = 0; +static BitArrayRange R_shamt_0(24, 20); +shamt += R_shamt_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//SLLIW\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +if ((rd % 32ULL) != 0ULL) { // conditional +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint32 sh_val = ((etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL])) << " + std::to_string(shamt) + "ULL;\n"; +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint64)((etiss_int32)(sh_val));\n"; +cp.code() += "} // block\n"; +} // block +} // conditional +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 shamt = 0; +static BitArrayRange R_shamt_0(24, 20); +shamt += R_shamt_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "slliw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | shamt=" + std::to_string(shamt) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// SRLIW ----------------------------------------------------------------------- +static InstructionDefinition srliw_rd_rs1_shamt ( + ISA32_RV64IMACFD, + "srliw", + (uint32_t) 0x00501b, + (uint32_t) 0xfe00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 shamt = 0; +static BitArrayRange R_shamt_0(24, 20); +shamt += R_shamt_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//SRLIW\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +if ((rd % 32ULL) != 0ULL) { // conditional +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint32 sh_val = ((etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL])) >> " + std::to_string(shamt) + "ULL;\n"; +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint64)((etiss_int32)(sh_val));\n"; +cp.code() += "} // block\n"; +} // block +} // conditional +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 shamt = 0; +static BitArrayRange R_shamt_0(24, 20); +shamt += R_shamt_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "srliw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | shamt=" + std::to_string(shamt) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// SRAIW ----------------------------------------------------------------------- +static InstructionDefinition sraiw_rd_rs1_shamt ( + ISA32_RV64IMACFD, + "sraiw", + (uint32_t) 0x4000501b, + (uint32_t) 0xfe00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 shamt = 0; +static BitArrayRange R_shamt_0(24, 20); +shamt += R_shamt_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//SRAIW\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +if ((rd % 32ULL) != 0ULL) { // conditional +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_int32 sh_val = ((etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL])) >> " + std::to_string(shamt) + "ULL;\n"; +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint64)(sh_val);\n"; +cp.code() += "} // block\n"; +} // block +} // conditional +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 shamt = 0; +static BitArrayRange R_shamt_0(24, 20); +shamt += R_shamt_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "sraiw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | shamt=" + std::to_string(shamt) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// ADDW ------------------------------------------------------------------------ +static InstructionDefinition addw_rd_rs1_rs2 ( + ISA32_RV64IMACFD, + "addw", + (uint32_t) 0x00003b, + (uint32_t) 0xfe00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//ADDW\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +if ((rd % 32ULL) != 0ULL) { // conditional +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_int32 res = (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) + (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n"; +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int64)(res);\n"; +cp.code() += "} // block\n"; +} // block +} // conditional +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "addw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// SUBW ------------------------------------------------------------------------ +static InstructionDefinition subw_rd_rs1_rs2 ( + ISA32_RV64IMACFD, + "subw", + (uint32_t) 0x4000003b, + (uint32_t) 0xfe00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//SUBW\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +if ((rd % 32ULL) != 0ULL) { // conditional +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_int32 res = (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) - (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n"; +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int64)(res);\n"; +cp.code() += "} // block\n"; +} // block +} // conditional +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "subw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// SLLW ------------------------------------------------------------------------ +static InstructionDefinition sllw_rd_rs1_rs2 ( + ISA32_RV64IMACFD, + "sllw", + (uint32_t) 0x00103b, + (uint32_t) 0xfe00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//SLLW\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +if ((rd % 32ULL) != 0ULL) { // conditional +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint32 count = (etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) & 31ULL;\n"; +cp.code() += "etiss_uint32 sh_val = ((etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL])) << count;\n"; +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint64)((etiss_int32)(sh_val));\n"; +cp.code() += "} // block\n"; +} // block +} // conditional +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "sllw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// SRLW ------------------------------------------------------------------------ +static InstructionDefinition srlw_rd_rs1_rs2 ( + ISA32_RV64IMACFD, + "srlw", + (uint32_t) 0x00503b, + (uint32_t) 0xfe00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//SRLW\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +if ((rd % 32ULL) != 0ULL) { // conditional +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint32 count = (etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) & 31ULL;\n"; +cp.code() += "etiss_uint32 sh_val = ((etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL])) >> count;\n"; +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint64)((etiss_int32)(sh_val));\n"; +cp.code() += "} // block\n"; +} // block +} // conditional +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "srlw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// SRAW ------------------------------------------------------------------------ +static InstructionDefinition sraw_rd_rs1_rs2 ( + ISA32_RV64IMACFD, + "sraw", + (uint32_t) 0x4000503b, + (uint32_t) 0xfe00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//SRAW\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +if ((rd % 32ULL) != 0ULL) { // conditional +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint32 count = (etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) & 31ULL;\n"; +cp.code() += "etiss_int32 sh_val = ((etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL])) >> count;\n"; +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int64)(sh_val);\n"; +cp.code() += "} // block\n"; +} // block +} // conditional +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "sraw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_RV64MInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64MInstr.cpp new file mode 100644 index 0000000000..996f9f6d13 --- /dev/null +++ b/ArchImpl/RV64IMACFD/RV64IMACFD_RV64MInstr.cpp @@ -0,0 +1,453 @@ +/** + * Generated on Tue, 28 Nov 2023 09:45:19 +0100. + * + * This file contains the instruction behavior models of the RV64M + * instruction set for the RV64IMACFD core architecture. + */ + +#include "RV64IMACFDArch.h" +#include "RV64IMACFDFuncs.h" + +using namespace etiss; +using namespace etiss::instr; + + +// MULW ------------------------------------------------------------------------ +static InstructionDefinition mulw_rd_rs1_rs2 ( + ISA32_RV64IMACFD, + "mulw", + (uint32_t) 0x200003b, + (uint32_t) 0xfe00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//MULW\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +if ((rd % 32ULL) != 0ULL) { // conditional +{ // block +cp.code() += "{ // block\n"; +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint64)((etiss_int32)(((etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) * (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]))));\n"; +cp.code() += "} // block\n"; +} // block +} // conditional +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "mulw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// DIVW ------------------------------------------------------------------------ +static InstructionDefinition divw_rd_rs1_rs2 ( + ISA32_RV64IMACFD, + "divw", + (uint32_t) 0x200403b, + (uint32_t) 0xfe00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//DIVW\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +if ((rd % 32ULL) != 0ULL) { // conditional +{ // block +cp.code() += "{ // block\n"; +cp.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL] != 0ULL) { // conditional\n"; +{ // block +cp.code() += "{ // block\n"; +etiss_int32 MMIN = 2147483648ULL; +cp.code() += "if ((etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) == " + std::to_string(MMIN) + "LL && (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) == -1LL) { // conditional\n"; +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = -2147483648LL;\n"; +cp.code() += "} // conditional\n"; +cp.code() += "else { // conditional\n"; +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int64)(((etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) / (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL])));\n"; +cp.code() += "} // conditional\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "} // conditional\n"; +cp.code() += "else { // conditional\n"; +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = -1LL;\n"; +cp.code() += "} // conditional\n"; +cp.code() += "} // block\n"; +} // block +} // conditional +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "divw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// DIVUW ----------------------------------------------------------------------- +static InstructionDefinition divuw_rd_rs1_rs2 ( + ISA32_RV64IMACFD, + "divuw", + (uint32_t) 0x200503b, + (uint32_t) 0xfe00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//DIVUW\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +if ((rd % 32ULL) != 0ULL) { // conditional +{ // block +cp.code() += "{ // block\n"; +cp.code() += "if ((etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) != 0ULL) { // conditional\n"; +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint64)((etiss_int32)(((etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) / (etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]))));\n"; +cp.code() += "} // conditional\n"; +cp.code() += "else { // conditional\n"; +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = -1LL;\n"; +cp.code() += "} // conditional\n"; +cp.code() += "} // block\n"; +} // block +} // conditional +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "divuw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// REMW ------------------------------------------------------------------------ +static InstructionDefinition remw_rd_rs1_rs2 ( + ISA32_RV64IMACFD, + "remw", + (uint32_t) 0x200603b, + (uint32_t) 0xfe00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//REMW\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +if ((rd % 32ULL) != 0ULL) { // conditional +{ // block +cp.code() += "{ // block\n"; +cp.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL] != 0ULL) { // conditional\n"; +{ // block +cp.code() += "{ // block\n"; +etiss_int32 MMIN = 2147483648ULL; +cp.code() += "if ((etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) == " + std::to_string(MMIN) + "LL && (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) == -1LL) { // conditional\n"; +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = 0ULL;\n"; +cp.code() += "} // conditional\n"; +cp.code() += "else { // conditional\n"; +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int64)(((etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) % (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL])));\n"; +cp.code() += "} // conditional\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "} // conditional\n"; +cp.code() += "else { // conditional\n"; +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int64)(((etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL])));\n"; +cp.code() += "} // conditional\n"; +cp.code() += "} // block\n"; +} // block +} // conditional +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "remw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// REMUW ----------------------------------------------------------------------- +static InstructionDefinition remuw_rd_rs1_rs2 ( + ISA32_RV64IMACFD, + "remuw", + (uint32_t) 0x200703b, + (uint32_t) 0xfe00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//REMUW\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +if ((rd % 32ULL) != 0ULL) { // conditional +{ // block +cp.code() += "{ // block\n"; +cp.code() += "if ((etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) != 0ULL) { // conditional\n"; +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint64)((etiss_int32)(((etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) % (etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]))));\n"; +cp.code() += "} // conditional\n"; +cp.code() += "else { // conditional\n"; +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint64)(((etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL])));\n"; +cp.code() += "} // conditional\n"; +cp.code() += "} // block\n"; +} // block +} // conditional +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "remuw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_ZifenceiInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_ZifenceiInstr.cpp new file mode 100644 index 0000000000..ac7eed9354 --- /dev/null +++ b/ArchImpl/RV64IMACFD/RV64IMACFD_ZifenceiInstr.cpp @@ -0,0 +1,93 @@ +/** + * Generated on Tue, 28 Nov 2023 09:45:19 +0100. + * + * This file contains the instruction behavior models of the Zifencei + * instruction set for the RV64IMACFD core architecture. + */ + +#include "RV64IMACFDArch.h" +#include "RV64IMACFDFuncs.h" + +using namespace etiss; +using namespace etiss::instr; + + +// FENCE_I --------------------------------------------------------------------- +static InstructionDefinition fence_i_rd_rs1_imm ( + ISA32_RV64IMACFD, + "fence_i", + (uint32_t) 0x00100f, + (uint32_t) 0x00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint16 imm = 0; +static BitArrayRange R_imm_0(31, 20); +imm += R_imm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//FENCE_I\n"); + +// ----------------------------------------------------------------------------- +cp.code() += "cpu->exception = ETISS_RETURNCODE_RELOADBLOCKS;\n"; +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "((RV64IMACFD*)cpu)->FENCE[1ULL] = " + std::to_string(imm) + "ULL;\n"; +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); + + cp.code() = std::string("//FENCE_I\n"); + +// ----------------------------------------------------------------------------- +cp.code() += "return cpu->exception;\n"; +// ----------------------------------------------------------------------------- + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint16 imm = 0; +static BitArrayRange R_imm_0(31, 20); +imm += R_imm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "fence_i" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | imm=" + std::to_string(imm) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_csrInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_csrInstr.cpp new file mode 100644 index 0000000000..a245b49a9d --- /dev/null +++ b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_csrInstr.cpp @@ -0,0 +1,503 @@ +/** + * Generated on Tue, 28 Nov 2023 09:45:19 +0100. + * + * This file contains the instruction behavior models of the tum_csr + * instruction set for the RV64IMACFD core architecture. + */ + +#include "RV64IMACFDArch.h" +#include "RV64IMACFDFuncs.h" + +using namespace etiss; +using namespace etiss::instr; + + +// CSRRW ----------------------------------------------------------------------- +static InstructionDefinition csrrw_rd_rs1_csr ( + ISA32_RV64IMACFD, + "csrrw", + (uint32_t) 0x001073, + (uint32_t) 0x00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint16 csr = 0; +static BitArrayRange R_csr_0(31, 20); +csr += R_csr_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//CSRRW\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint64 xrs1 = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n"; +if ((rd % 32ULL) != 0ULL) { // conditional +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint64 xrd = RV64IMACFD_csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL);\n"; +cp.code() += "RV64IMACFD_csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL, xrs1);\n"; +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = xrd;\n"; +cp.code() += "} // block\n"; +} // block +} // conditional +else { // conditional +{ // block +cp.code() += "{ // block\n"; +cp.code() += "RV64IMACFD_csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL, xrs1);\n"; +cp.code() += "} // block\n"; +} // block +} // conditional +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint16 csr = 0; +static BitArrayRange R_csr_0(31, 20); +csr += R_csr_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "csrrw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | csr=" + std::to_string(csr) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// CSRRS ----------------------------------------------------------------------- +static InstructionDefinition csrrs_rd_rs1_csr ( + ISA32_RV64IMACFD, + "csrrs", + (uint32_t) 0x002073, + (uint32_t) 0x00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint16 csr = 0; +static BitArrayRange R_csr_0(31, 20); +csr += R_csr_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//CSRRS\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint64 xrd = RV64IMACFD_csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL);\n"; +cp.code() += "etiss_uint64 xrs1 = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n"; +if (rs1 != 0ULL) { // conditional +cp.code() += "RV64IMACFD_csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL, xrd | xrs1);\n"; +} // conditional +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = xrd;\n"; +} // conditional +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint16 csr = 0; +static BitArrayRange R_csr_0(31, 20); +csr += R_csr_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "csrrs" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | csr=" + std::to_string(csr) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// CSRRC ----------------------------------------------------------------------- +static InstructionDefinition csrrc_rd_rs1_csr ( + ISA32_RV64IMACFD, + "csrrc", + (uint32_t) 0x003073, + (uint32_t) 0x00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint16 csr = 0; +static BitArrayRange R_csr_0(31, 20); +csr += R_csr_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//CSRRC\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint64 xrd = RV64IMACFD_csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL);\n"; +cp.code() += "etiss_uint64 xrs1 = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n"; +if (rs1 != 0ULL) { // conditional +cp.code() += "RV64IMACFD_csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL, xrd & ~(xrs1));\n"; +} // conditional +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = xrd;\n"; +} // conditional +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint16 csr = 0; +static BitArrayRange R_csr_0(31, 20); +csr += R_csr_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "csrrc" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | csr=" + std::to_string(csr) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// CSRRWI ---------------------------------------------------------------------- +static InstructionDefinition csrrwi_rd_zimm_csr ( + ISA32_RV64IMACFD, + "csrrwi", + (uint32_t) 0x005073, + (uint32_t) 0x00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 zimm = 0; +static BitArrayRange R_zimm_0(19, 15); +zimm += R_zimm_0.read(ba) << 0; +etiss_uint16 csr = 0; +static BitArrayRange R_csr_0(31, 20); +csr += R_csr_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//CSRRWI\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint64 xrd = RV64IMACFD_csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL);\n"; +cp.code() += "RV64IMACFD_csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL, " + std::to_string((etiss_uint64)(zimm)) + "ULL);\n"; +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = xrd;\n"; +} // conditional +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 zimm = 0; +static BitArrayRange R_zimm_0(19, 15); +zimm += R_zimm_0.read(ba) << 0; +etiss_uint16 csr = 0; +static BitArrayRange R_csr_0(31, 20); +csr += R_csr_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "csrrwi" << " # " << ba << (" [rd=" + std::to_string(rd) + " | zimm=" + std::to_string(zimm) + " | csr=" + std::to_string(csr) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// CSRRSI ---------------------------------------------------------------------- +static InstructionDefinition csrrsi_rd_zimm_csr ( + ISA32_RV64IMACFD, + "csrrsi", + (uint32_t) 0x006073, + (uint32_t) 0x00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 zimm = 0; +static BitArrayRange R_zimm_0(19, 15); +zimm += R_zimm_0.read(ba) << 0; +etiss_uint16 csr = 0; +static BitArrayRange R_csr_0(31, 20); +csr += R_csr_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//CSRRSI\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint64 xrd = RV64IMACFD_csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL);\n"; +if (zimm != 0ULL) { // conditional +cp.code() += "RV64IMACFD_csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL, xrd | " + std::to_string((etiss_uint64)(zimm)) + "ULL);\n"; +} // conditional +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = xrd;\n"; +} // conditional +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 zimm = 0; +static BitArrayRange R_zimm_0(19, 15); +zimm += R_zimm_0.read(ba) << 0; +etiss_uint16 csr = 0; +static BitArrayRange R_csr_0(31, 20); +csr += R_csr_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "csrrsi" << " # " << ba << (" [rd=" + std::to_string(rd) + " | zimm=" + std::to_string(zimm) + " | csr=" + std::to_string(csr) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// CSRRCI ---------------------------------------------------------------------- +static InstructionDefinition csrrci_rd_zimm_csr ( + ISA32_RV64IMACFD, + "csrrci", + (uint32_t) 0x007073, + (uint32_t) 0x00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 zimm = 0; +static BitArrayRange R_zimm_0(19, 15); +zimm += R_zimm_0.read(ba) << 0; +etiss_uint16 csr = 0; +static BitArrayRange R_csr_0(31, 20); +csr += R_csr_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//CSRRCI\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint64 xrd = RV64IMACFD_csr_read(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL);\n"; +if (zimm != 0ULL) { // conditional +cp.code() += "RV64IMACFD_csr_write(cpu, system, plugin_pointers, " + std::to_string(csr) + "ULL, xrd & " + std::to_string(~(((etiss_uint64)(zimm)))) + "ULL);\n"; +} // conditional +if ((rd % 32ULL) != 0ULL) { // conditional +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = xrd;\n"; +} // conditional +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 zimm = 0; +static BitArrayRange R_zimm_0(19, 15); +zimm += R_zimm_0.read(ba) << 0; +etiss_uint16 csr = 0; +static BitArrayRange R_csr_0(31, 20); +csr += R_csr_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "csrrci" << " # " << ba << (" [rd=" + std::to_string(rd) + " | zimm=" + std::to_string(zimm) + " | csr=" + std::to_string(csr) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_retInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_retInstr.cpp new file mode 100644 index 0000000000..c1813f9847 --- /dev/null +++ b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_retInstr.cpp @@ -0,0 +1,310 @@ +/** + * Generated on Tue, 28 Nov 2023 09:45:19 +0100. + * + * This file contains the instruction behavior models of the tum_ret + * instruction set for the RV64IMACFD core architecture. + */ + +#include "RV64IMACFDArch.h" +#include "RV64IMACFDFuncs.h" + +using namespace etiss; +using namespace etiss::instr; + + +// ECALL ----------------------------------------------------------------------- +static InstructionDefinition ecall_ ( + ISA32_RV64IMACFD, + "ecall", + (uint32_t) 0x000073, + (uint32_t) 0xffffffff, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//ECALL\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV64IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 8LL + ((RV64IMACFD*)cpu)->PRIV);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); + + cp.code() = std::string("//ECALL\n"); + +// ----------------------------------------------------------------------------- +cp.code() += "return cpu->exception;\n"; +// ----------------------------------------------------------------------------- + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "ecall" << " # " << ba << (" []"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// MRET ------------------------------------------------------------------------ +static InstructionDefinition mret_ ( + ISA32_RV64IMACFD, + "mret", + (uint32_t) 0x30200073, + (uint32_t) 0xffffffff, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//MRET\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "if (((RV64IMACFD*)cpu)->PRIV < 3LL) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV64IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 2LL);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "cpu->nextPc = *((RV64IMACFD*)cpu)->CSR[833LL];\n"; +cp.code() += "etiss_uint64 s = RV64IMACFD_csr_read(cpu, system, plugin_pointers, 768LL);\n"; +cp.code() += "etiss_uint64 prev_prv = RV64IMACFD_get_field(s, 6144LL);\n"; +cp.code() += "if (prev_prv != 3LL) { // conditional\n"; +cp.code() += "s = RV64IMACFD_set_field(s, 131072LL, 0ULL);\n"; +cp.code() += "} // conditional\n"; +cp.code() += "s = RV64IMACFD_set_field(s, 8LL, RV64IMACFD_get_field(s, 128LL));\n"; +cp.code() += "s = RV64IMACFD_set_field(s, 128LL, 1ULL);\n"; +cp.code() += "s = RV64IMACFD_set_field(s, 6144LL, (RV64IMACFD_extension_enabled(cpu, system, plugin_pointers, 85ULL)) ? (0LL) : (3LL));\n"; +cp.code() += "RV64IMACFD_csr_write(cpu, system, plugin_pointers, 768LL, s);\n"; +cp.code() += "((RV64IMACFD*)cpu)->PRIV = (prev_prv) & 0x7;\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); + + cp.code() = std::string("//MRET\n"); + +// ----------------------------------------------------------------------------- +cp.code() += "return cpu->exception;\n"; +// ----------------------------------------------------------------------------- + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "mret" << " # " << ba << (" []"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// WFI ------------------------------------------------------------------------- +static InstructionDefinition wfi_ ( + ISA32_RV64IMACFD, + "wfi", + (uint32_t) 0x10500073, + (uint32_t) 0xffffffff, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//WFI\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); + + cp.code() = std::string("//WFI\n"); + +// ----------------------------------------------------------------------------- +cp.code() += "return cpu->exception;\n"; +// ----------------------------------------------------------------------------- + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "wfi" << " # " << ba << (" []"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// SRET ------------------------------------------------------------------------ +static InstructionDefinition sret_ ( + ISA32_RV64IMACFD, + "sret", + (uint32_t) 0x10200073, + (uint32_t) 0xffffffff, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//SRET\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "if (((RV64IMACFD*)cpu)->PRIV < ((RV64IMACFD_get_field(RV64IMACFD_csr_read(cpu, system, plugin_pointers, 768LL), 4194304LL)) ? (3LL) : (1LL))) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV64IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 2LL);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "cpu->nextPc = *((RV64IMACFD*)cpu)->CSR[321LL];\n"; +cp.code() += "etiss_uint64 s = RV64IMACFD_csr_read(cpu, system, plugin_pointers, 256LL);\n"; +cp.code() += "etiss_uint64 prev_prv = RV64IMACFD_get_field(s, 256LL);\n"; +cp.code() += "s = RV64IMACFD_set_field(s, 2LL, RV64IMACFD_get_field(s, 32LL));\n"; +cp.code() += "s = RV64IMACFD_set_field(s, 32LL, 1ULL);\n"; +cp.code() += "s = RV64IMACFD_set_field(s, 256LL, 0LL);\n"; +cp.code() += "RV64IMACFD_csr_write(cpu, system, plugin_pointers, 768LL, s);\n"; +cp.code() += "((RV64IMACFD*)cpu)->PRIV = (prev_prv) & 0x7;\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); + + cp.code() = std::string("//SRET\n"); + +// ----------------------------------------------------------------------------- +cp.code() += "return cpu->exception;\n"; +// ----------------------------------------------------------------------------- + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "sret" << " # " << ba << (" []"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rva64Instr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rva64Instr.cpp new file mode 100644 index 0000000000..a363147790 --- /dev/null +++ b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rva64Instr.cpp @@ -0,0 +1,229 @@ +/** + * Generated on Tue, 28 Nov 2023 09:45:19 +0100. + * + * This file contains the instruction behavior models of the tum_rva64 + * instruction set for the RV64IMACFD core architecture. + */ + +#include "RV64IMACFDArch.h" +#include "RV64IMACFDFuncs.h" + +using namespace etiss; +using namespace etiss::instr; + + +// LRD ------------------------------------------------------------------------- +static InstructionDefinition lrd_rd_rs1_rl_aq ( + ISA32_RV64IMACFD, + "lrd", + (uint32_t) 0x1000302f, + (uint32_t) 0xf9f0707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rl = 0; +static BitArrayRange R_rl_0(25, 25); +rl += R_rl_0.read(ba) << 0; +etiss_uint8 aq = 0; +static BitArrayRange R_aq_0(26, 26); +aq += R_aq_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//LRD\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n"; +cp.code() += "etiss_uint64 mem_val_0;\n"; +cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "etiss_int64 res = (etiss_int64)(mem_val_0);\n"; +cp.code() += "((RV64IMACFD*)cpu)->RES_ADDR = offs;\n"; +if (rd) { // conditional +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int64)(res);\n"; +} // conditional +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); + + cp.code() = std::string("//LRD\n"); + +// ----------------------------------------------------------------------------- +cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n"; +// ----------------------------------------------------------------------------- + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rl = 0; +static BitArrayRange R_rl_0(25, 25); +rl += R_rl_0.read(ba) << 0; +etiss_uint8 aq = 0; +static BitArrayRange R_aq_0(26, 26); +aq += R_aq_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "lrd" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rl=" + std::to_string(rl) + " | aq=" + std::to_string(aq) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// SCD ------------------------------------------------------------------------- +static InstructionDefinition scd_rd_rs1_rs2_rl_aq ( + ISA32_RV64IMACFD, + "scd", + (uint32_t) 0x1800302f, + (uint32_t) 0xf800707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; +etiss_uint8 rl = 0; +static BitArrayRange R_rl_0(25, 25); +rl += R_rl_0.read(ba) << 0; +etiss_uint8 aq = 0; +static BitArrayRange R_aq_0(26, 26); +aq += R_aq_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//SCD\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n"; +cp.code() += "if (((RV64IMACFD*)cpu)->RES_ADDR == offs) { // conditional\n"; +cp.code() += "etiss_uint64 mem_val_0;\n"; +cp.code() += "mem_val_0 = (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n"; +cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "} // conditional\n"; +if (rd) { // conditional +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = ((RV64IMACFD*)cpu)->RES_ADDR != offs;\n"; +} // conditional +cp.code() += "((RV64IMACFD*)cpu)->RES_ADDR = -1LL;\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); + + cp.code() = std::string("//SCD\n"); + +// ----------------------------------------------------------------------------- +cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n"; +// ----------------------------------------------------------------------------- + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; +etiss_uint8 rl = 0; +static BitArrayRange R_rl_0(25, 25); +rl += R_rl_0.read(ba) << 0; +etiss_uint8 aq = 0; +static BitArrayRange R_aq_0(26, 26); +aq += R_aq_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "scd" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + " | rl=" + std::to_string(rl) + " | aq=" + std::to_string(aq) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rvaInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rvaInstr.cpp new file mode 100644 index 0000000000..9465934072 --- /dev/null +++ b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rvaInstr.cpp @@ -0,0 +1,229 @@ +/** + * Generated on Tue, 28 Nov 2023 09:45:19 +0100. + * + * This file contains the instruction behavior models of the tum_rva + * instruction set for the RV64IMACFD core architecture. + */ + +#include "RV64IMACFDArch.h" +#include "RV64IMACFDFuncs.h" + +using namespace etiss; +using namespace etiss::instr; + + +// LRW ------------------------------------------------------------------------- +static InstructionDefinition lrw_rd_rs1_rl_aq ( + ISA32_RV64IMACFD, + "lrw", + (uint32_t) 0x1000202f, + (uint32_t) 0xf9f0707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rl = 0; +static BitArrayRange R_rl_0(25, 25); +rl += R_rl_0.read(ba) << 0; +etiss_uint8 aq = 0; +static BitArrayRange R_aq_0(26, 26); +aq += R_aq_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//LRW\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n"; +cp.code() += "etiss_uint32 mem_val_0;\n"; +cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "etiss_int32 res = (etiss_int32)(mem_val_0);\n"; +cp.code() += "((RV64IMACFD*)cpu)->RES_ADDR = offs;\n"; +if (rd) { // conditional +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int64)(res);\n"; +} // conditional +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); + + cp.code() = std::string("//LRW\n"); + +// ----------------------------------------------------------------------------- +cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n"; +// ----------------------------------------------------------------------------- + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rl = 0; +static BitArrayRange R_rl_0(25, 25); +rl += R_rl_0.read(ba) << 0; +etiss_uint8 aq = 0; +static BitArrayRange R_aq_0(26, 26); +aq += R_aq_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "lrw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rl=" + std::to_string(rl) + " | aq=" + std::to_string(aq) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// SCW ------------------------------------------------------------------------- +static InstructionDefinition scw_rd_rs1_rs2_rl_aq ( + ISA32_RV64IMACFD, + "scw", + (uint32_t) 0x1800202f, + (uint32_t) 0xf800707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; +etiss_uint8 rl = 0; +static BitArrayRange R_rl_0(25, 25); +rl += R_rl_0.read(ba) << 0; +etiss_uint8 aq = 0; +static BitArrayRange R_aq_0(26, 26); +aq += R_aq_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//SCW\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n"; +cp.code() += "if (((RV64IMACFD*)cpu)->RES_ADDR == offs) { // conditional\n"; +cp.code() += "etiss_uint32 mem_val_0;\n"; +cp.code() += "mem_val_0 = (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n"; +cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "} // conditional\n"; +if (rd) { // conditional +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = ((RV64IMACFD*)cpu)->RES_ADDR != offs;\n"; +} // conditional +cp.code() += "((RV64IMACFD*)cpu)->RES_ADDR = -1LL;\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); + + cp.code() = std::string("//SCW\n"); + +// ----------------------------------------------------------------------------- +cp.code() += "if (cpu->return_pending | cpu->exception) return cpu->exception;\n"; +// ----------------------------------------------------------------------------- + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; +etiss_uint8 rl = 0; +static BitArrayRange R_rl_0(25, 25); +rl += R_rl_0.read(ba) << 0; +etiss_uint8 aq = 0; +static BitArrayRange R_aq_0(26, 26); +aq += R_aq_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "scw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + " | rl=" + std::to_string(rl) + " | aq=" + std::to_string(aq) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rvmInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rvmInstr.cpp new file mode 100644 index 0000000000..9079620b69 --- /dev/null +++ b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_rvmInstr.cpp @@ -0,0 +1,334 @@ +/** + * Generated on Tue, 28 Nov 2023 09:45:19 +0100. + * + * This file contains the instruction behavior models of the tum_rvm + * instruction set for the RV64IMACFD core architecture. + */ + +#include "RV64IMACFDArch.h" +#include "RV64IMACFDFuncs.h" + +using namespace etiss; +using namespace etiss::instr; + + +// MUL ------------------------------------------------------------------------- +static InstructionDefinition mul_rd_rs1_rs2 ( + ISA32_RV64IMACFD, + "mul", + (uint32_t) 0x2000033, + (uint32_t) 0xfe00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//MUL\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +if ((rd % 32ULL) != 0ULL) { // conditional +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_int64 res = (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) * (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n"; +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint64)(res);\n"; +cp.code() += "} // block\n"; +} // block +} // conditional +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "mul" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// MULH ------------------------------------------------------------------------ +static InstructionDefinition mulh_rd_rs1_rs2 ( + ISA32_RV64IMACFD, + "mulh", + (uint32_t) 0x2001033, + (uint32_t) 0xfe00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//MULH\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +if ((rd % 32ULL) != 0ULL) { // conditional +{ // block +cp.code() += "{ // block\n"; +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = RV64IMACFD_mulh((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]), (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]));\n"; +cp.code() += "} // block\n"; +} // block +} // conditional +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "mulh" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// MULHSU ---------------------------------------------------------------------- +static InstructionDefinition mulhsu_rd_rs1_rs2 ( + ISA32_RV64IMACFD, + "mulhsu", + (uint32_t) 0x2002033, + (uint32_t) 0xfe00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//MULHSU\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +if ((rd % 32ULL) != 0ULL) { // conditional +{ // block +cp.code() += "{ // block\n"; +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = RV64IMACFD_mulhsu((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]), *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n"; +cp.code() += "} // block\n"; +} // block +} // conditional +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "mulhsu" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// MULHU ----------------------------------------------------------------------- +static InstructionDefinition mulhu_rd_rs1_rs2 ( + ISA32_RV64IMACFD, + "mulhu", + (uint32_t) 0x2003033, + (uint32_t) 0xfe00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//MULHU\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +if ((rd % 32ULL) != 0ULL) { // conditional +{ // block +cp.code() += "{ // block\n"; +cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = RV64IMACFD_mulhu(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL], *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n"; +cp.code() += "} // block\n"; +} // block +} // conditional +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "mulhu" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_semihostingInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_semihostingInstr.cpp new file mode 100644 index 0000000000..0020b56c47 --- /dev/null +++ b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_semihostingInstr.cpp @@ -0,0 +1,149 @@ +/** + * Generated on Tue, 28 Nov 2023 09:45:19 +0100. + * + * This file contains the instruction behavior models of the tum_semihosting + * instruction set for the RV64IMACFD core architecture. + */ + +#include "RV64IMACFDArch.h" +#include "RV64IMACFDFuncs.h" + +using namespace etiss; +using namespace etiss::instr; + + +// EBREAK ---------------------------------------------------------------------- +static InstructionDefinition ebreak_ ( + ISA32_RV64IMACFD, + "ebreak", + (uint32_t) 0x100073, + (uint32_t) 0xffffffff, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//EBREAK\n"); + +// ----------------------------------------------------------------------------- +{ // block +cp.code() += "{ // block\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n"; +cp.code() += "} // block\n"; +} // block +{ // block +cp.code() += "{ // block\n"; +cp.code() += "if (etiss_semihost_enabled()) { // conditional\n"; +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint32 mem_val_0;\n"; +cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, " + std::to_string(ic.current_address_ - 4ULL) + "ULL, (etiss_uint8*)&mem_val_0, 4);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "etiss_uint32 pre = (etiss_uint32)(mem_val_0);\n"; +cp.code() += "etiss_uint32 mem_val_1;\n"; +cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, " + std::to_string(ic.current_address_ + 0ULL) + "ULL, (etiss_uint8*)&mem_val_1, 4);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "etiss_uint32 ebreak = (etiss_uint32)(mem_val_1);\n"; +cp.code() += "etiss_uint32 mem_val_2;\n"; +cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, " + std::to_string(ic.current_address_ + 4ULL) + "ULL, (etiss_uint8*)&mem_val_2, 4);\n"; +cp.code() += "if (cpu->exception) { // conditional\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // conditional\n"; +cp.code() += "etiss_uint32 post = (etiss_uint32)(mem_val_2);\n"; +cp.code() += "if (pre == 32509971ULL && ebreak == 1048691ULL && post == 1081102355ULL) { // conditional\n"; +{ // block +cp.code() += "{ // block\n"; +cp.code() += "etiss_uint64 operation = *((RV64IMACFD*)cpu)->X[10ULL];\n"; +cp.code() += "etiss_uint64 parameter = *((RV64IMACFD*)cpu)->X[11ULL];\n"; +cp.code() += "*((RV64IMACFD*)cpu)->X[10ULL] = (etiss_int64)(etiss_semihost(cpu, system, plugin_pointers, 64ULL, operation, parameter));\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "} // conditional\n"; +cp.code() += "else { // conditional\n"; +{ // block +cp.code() += "{ // block\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV64IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 3LL);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // block\n"; +} // block +cp.code() += "} // conditional\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "} // conditional\n"; +cp.code() += "else { // conditional\n"; +{ // block +cp.code() += "{ // block\n"; +{ // procedure +cp.code() += "{ // procedure\n"; +cp.code() += "RV64IMACFD_raise(cpu, system, plugin_pointers, 0ULL, 3LL);\n"; +cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n"; +cp.code() += "} // procedure\n"; +} // procedure +cp.code() += "} // block\n"; +} // block +cp.code() += "} // conditional\n"; +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); + + cp.code() = std::string("//EBREAK\n"); + +// ----------------------------------------------------------------------------- +cp.code() += "if (cpu->return_pending | cpu->exception | cpu->nextPc != " + std::to_string(ic.current_address_ + 4) + "ULL) return cpu->exception;\n"; +// ----------------------------------------------------------------------------- + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "ebreak" << " # " << ba << (" []"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); diff --git a/ArchImpl/RV64IMACFD/RV64IMACFD_tum_sfenceInstr.cpp b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_sfenceInstr.cpp new file mode 100644 index 0000000000..6cbe14b891 --- /dev/null +++ b/ArchImpl/RV64IMACFD/RV64IMACFD_tum_sfenceInstr.cpp @@ -0,0 +1,120 @@ +/** + * Generated on Wed, 13 Sep 2023 17:04:56 +0200. + * + * This file contains the instruction behavior models of the tum_sfence + * instruction set for the RV64IMACFD core architecture. + */ + +#include "RV64IMACFDArch.h" + +#define ETISS_ARCH_STATIC_FN_ONLY +extern "C" { +#include "RV64IMACFDFuncs.h" +} + +using namespace etiss; +using namespace etiss::instr; + + +// SFENCE_VMA ------------------------------------------------------------------ +static InstructionDefinition sfence_vma_rs1_rs2 ( + ISA32_RV64IMACFD, + "sfence_vma", + (uint32_t) 0x12000073, + (uint32_t) 0xfe007fff, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + { + CodePart & cp = cs.append(CodePart::INITIALREQUIRED); + + cp.code() = std::string("//SFENCE_VMA\n"); + +// ----------------------------------------------------------------------------- +cp.code() += "cpu->exception = ETISS_RETURNCODE_RELOADBLOCKS;\n"; +cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4ULL) + "ULL;\n"; +{ // block +cp.code() += "{ // block\n"; +cp.code() += "((RV64IMACFD*)cpu)->FENCE[2ULL] = " + std::to_string(rs1) + "ULL;\n"; +cp.code() += "((RV64IMACFD*)cpu)->FENCE[3ULL] = " + std::to_string(rs2) + "ULL;\n"; +cp.code() += "etiss_uint64 vaddr = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1) + "ULL];\n"; +cp.code() += "etiss_uint64 asid = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2) + "ULL];\n"; +if (rs1 == 0ULL) { // conditional +{ // block +cp.code() += "{ // block\n"; +if (rs2 == 0ULL) { // conditional +cp.code() += "evict_all(cpu, system, plugin_pointers);\n"; +} // conditional +else { // conditional +cp.code() += "evict_asid(cpu, system, plugin_pointers, asid);\n"; +} // conditional +cp.code() += "} // block\n"; +} // block +} // conditional +else { // conditional +{ // block +cp.code() += "{ // block\n"; +if (rs2 == 0ULL) { // conditional +cp.code() += "evict_addr(cpu, system, plugin_pointers, vaddr);\n"; +} // conditional +else { // conditional +cp.code() += "evict_addr_asid(cpu, system, plugin_pointers, vaddr, asid);\n"; +} // conditional +cp.code() += "} // block\n"; +} // block +} // conditional +cp.code() += "} // block\n"; +} // block +cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n"; +cp.code() += "cpu->instructionPointer = cpu->nextPc;\n"; +// ----------------------------------------------------------------------------- + cp.getRegisterDependencies().add(reg_name[rs1], 64); + cp.getRegisterDependencies().add(reg_name[rs2], 64); + cp.getAffectedRegisters().add("instructionPointer", 32); + } + { + CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED); + + cp.code() = std::string("//SFENCE_VMA\n"); + +// ----------------------------------------------------------------------------- +cp.code() += "return cpu->exception;\n"; +// ----------------------------------------------------------------------------- + } + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint8 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint8 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "sfence_vma" << " # " << ba << (" [rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); diff --git a/cmake/ETISSPlugin.cmake b/cmake/ETISSPlugin.cmake index a656bc1d8c..174015b04a 100644 --- a/cmake/ETISSPlugin.cmake +++ b/cmake/ETISSPlugin.cmake @@ -27,4 +27,6 @@ ENDMACRO() MACRO(ETISSPluginArch ProjName) ETISSPluginArchName(${ProjName} ${ProjName}) + get_property(jitlibs GLOBAL PROPERTY etiss_jitlibs) + TARGET_LINK_LIBRARIES(${PROJECT_NAME} PUBLIC "${jitlibs}") ENDMACRO() diff --git a/examples/SW/riscv/cmake/pulpino_tumeda/syscalls.c b/examples/SW/riscv/cmake/pulpino_tumeda/syscalls.c index 423b9e4a0c..5c5f7e75f2 100644 --- a/examples/SW/riscv/cmake/pulpino_tumeda/syscalls.c +++ b/examples/SW/riscv/cmake/pulpino_tumeda/syscalls.c @@ -115,7 +115,6 @@ void _exit_(int exit_status) #ifdef DEBUG_SYSTEM printf_fromisr("exit called with code: %i\n", exit_status); #endif - asm("ebreak"); while (1) ; } diff --git a/include/etiss/CPUArch.h b/include/etiss/CPUArch.h index 9c76a7ab41..da5c98df73 100644 --- a/include/etiss/CPUArch.h +++ b/include/etiss/CPUArch.h @@ -62,6 +62,7 @@ #include "etiss/Instruction.h" #include "etiss/IntegratedLibrary/gdb/GDBCore.h" #include "etiss/InterruptVector.h" +#include "etiss/InterruptEnable.h" #include "etiss/Plugin.h" #include "etiss/VirtualStruct.h" #include "etiss/jit/CPU.h" @@ -237,6 +238,10 @@ class CPUArch : public CPUArchRegListenerInterface, delete an allocated interrupt vector object */ virtual void deleteInterruptVector(etiss::InterruptVector *vec, ETISS_CPU *cpu); + + virtual etiss::InterruptEnable* createInterruptEnable(ETISS_CPU *cpu); + virtual void deleteInterruptEnable(etiss::InterruptEnable* en, ETISS_CPU* cpu); + /** returns arch dependent gdb functions. althought not required it is strongly recommended to implement this */ diff --git a/include/etiss/CPUCore.h b/include/etiss/CPUCore.h index 78709d38b4..e0257eca8f 100644 --- a/include/etiss/CPUCore.h +++ b/include/etiss/CPUCore.h @@ -59,6 +59,7 @@ #include "etiss/Translation.h" #include "etiss/System.h" #include "etiss/InterruptHandler.h" +#include "etiss/InterruptEnable.h" #include "etiss/Plugin.h" #include "etiss/jit/ReturnCode.h" #include "etiss/mm/MMU.h" @@ -186,6 +187,8 @@ class CPUCore : public VirtualStructSupport, public etiss::ToString */ inline etiss::InterruptVector *getInterruptVector() { return intwrapper_; } + inline etiss::InterruptEnable *getInterruptEnable() { return intenable_; } + /** * @brief Get the CPU architecture. * @@ -381,6 +384,7 @@ class CPUCore : public VirtualStructSupport, public etiss::ToString std::shared_ptr vcpu_; etiss::InterruptVector *intvector_; /// cpu interrupt vector derived from cpu_ and allocated by arch_ InterruptVectorWrapper *intwrapper_; /// wrapped interrupt vector to allow interrupt listening + etiss::InterruptEnable *intenable_; bool timer_enabled_; /// if true the a timer plugin allocated by arch_ will be added in CPUCore::execute std::shared_ptr jit_; /// JIT instance to use. may be 0 (etiss::getDefaultJIT() will be used in that case) diff --git a/include/etiss/InterruptEnable.h b/include/etiss/InterruptEnable.h new file mode 100644 index 0000000000..bcf4de3baf --- /dev/null +++ b/include/etiss/InterruptEnable.h @@ -0,0 +1,37 @@ +#ifndef ETISS_INCLUDE_INTERRUPTENABLE_H_ +#define ETISS_INCLUDE_INTERRUPTENABLE_H_ + +namespace etiss { + +class InterruptEnable +{ + public: + virtual ~InterruptEnable() {} + virtual bool isEnabled() { return true; } +}; + +template +class MappedInterruptEnable : public InterruptEnable +{ + public: + MappedInterruptEnable(t* enable_reg, t mask) : + enable_reg_(enable_reg), + mask_(mask) + { + + } + + virtual ~MappedInterruptEnable() {} + + bool isEnabled() override + { + return *enable_reg_ & mask_; + }; + + private: + t* enable_reg_; + t mask_; +}; + +} +#endif \ No newline at end of file diff --git a/include/etiss/InterruptHandler.h b/include/etiss/InterruptHandler.h index 7a4ce4a0a4..eb7327b255 100644 --- a/include/etiss/InterruptHandler.h +++ b/include/etiss/InterruptHandler.h @@ -55,6 +55,7 @@ #include "etiss/CPUArch.h" #include "etiss/InterruptVector.h" +#include "etiss/InterruptHandler.h" #include "etiss/LibraryInterface.h" #include "etiss/Plugin.h" #include "etiss/jit/types.h" @@ -84,7 +85,7 @@ enum InterruptType class InterruptHandler : public etiss::CoroutinePlugin { public: - InterruptHandler(etiss::InterruptVector *interruptVector, std::shared_ptr arch, + InterruptHandler(etiss::InterruptVector *interruptVector, etiss::InterruptEnable *interruptEnable, std::shared_ptr arch, InterruptType itype = EDGE_TRIGGERED, bool sync = true); virtual ~InterruptHandler(); /** @@ -104,6 +105,7 @@ class InterruptHandler : public etiss::CoroutinePlugin std::mutex mu_; const bool sync_; InterruptVector *const vector_; + InterruptEnable *const enable_; /** list: (time , (line ,state) ) */ std::list>> pending_; const std::shared_ptr cpuarch_; diff --git a/include/etiss/Translation.h b/include/etiss/Translation.h index 4fb82aa4f8..502f1e1b1c 100644 --- a/include/etiss/Translation.h +++ b/include/etiss/Translation.h @@ -209,6 +209,8 @@ class Translation etiss::int32 translateBlock(CodeBlock &cb); + void unloadBlocksAll(); + void unloadBlocks(etiss::uint64 startindex = 0, etiss::uint64 endindex = ((etiss::uint64)((etiss::int64)-1))); std::string disasm(uint8_t *buf, unsigned len, int &append); diff --git a/include_c/etiss/jit/CPU.h b/include_c/etiss/jit/CPU.h index 6fa4f17691..7572a99aa8 100644 --- a/include_c/etiss/jit/CPU.h +++ b/include_c/etiss/jit/CPU.h @@ -92,6 +92,8 @@ extern "C" instructionPointer; ///< pointer to next instruction. NOTE: not neccessarily the instruction address (e.g ///< instruction minimal size: 4; instruction pointer: 2 -> instruction address: 2*4) + etiss_uint64 nextPc; + etiss_uint64 cpuTime_ps; ///< simulation time of cpu etiss_uint64 resourceUsages[ETISS_MAX_RESOURCES]; ///exception = etiss::RETURNCODE::RELOADBLOCKS; + } } diff --git a/src/CPUCore.cpp b/src/CPUCore.cpp index 1aad4f0280..0861e1cce5 100644 --- a/src/CPUCore.cpp +++ b/src/CPUCore.cpp @@ -142,6 +142,7 @@ CPUCore::CPUCore(std::shared_ptr arch) , cpu_(arch->newCPU()) , vcpu_(arch->getVirtualStruct(cpu_)) , intvector_(arch->createInterruptVector(cpu_)) + , intenable_(arch->createInterruptEnable(cpu_)) , mmu_enabled_(false) { arch_->resetCPU(cpu_, 0); @@ -685,6 +686,7 @@ etiss::int32 CPUCore::execute(ETISS_System &_system) // start execution loop + bool exit_on_loop = etiss::cfg().get("etiss.exit_on_loop", false); float startTime = (float)clock() / CLOCKS_PER_SEC; // TESTING @@ -727,6 +729,11 @@ etiss::int32 CPUCore::execute(ETISS_System &_system) // cpu->instructionPointer)){ // Transalte virtual address to physical address if MMU is enabled uint64_t pma = cpu_->instructionPointer; + + // remember pc and cpu time to check for loop to self instructions + uint64_t old_pc = cpu_->instructionPointer; + uint64_t old_time = cpu_->cpuTime_ps; + if (mmu_enabled_) { if (mmu_->cache_flush_pending) @@ -785,6 +792,14 @@ etiss::int32 CPUCore::execute(ETISS_System &_system) // a variable of the plugin exception = (*(blptr->execBlock))(cpu_, system, plugins_handle_); + // exit simulator when a loop to self instruction is encountered + if (exit_on_loop && !exception && + old_time + cpu_->cpuCycleTime_ps == cpu_->cpuTime_ps && + old_pc == cpu_->instructionPointer) + { + exception = RETURNCODE::CPUFINISHED; + } + #if ETISS_CPUCORE_DBG_APPROXIMATE_INSTRUCTION_COUNTER instrcounter += blptr->end - oldinstrptr; // TESTING ///TODO handle early exception exit? ///BUG: diff --git a/src/ETISS.cpp b/src/ETISS.cpp index dbd5c02138..979401b12c 100644 --- a/src/ETISS.cpp +++ b/src/ETISS.cpp @@ -731,6 +731,7 @@ void etiss_initialize(const std::vector& args, bool forced = false) ("arch.or1k.ignore_sr_iee", po::value(), "Ignore exception on OpenRISC.") ("arch.or1k.if_stall_cycles", po::value(), "Add instruction stall cycles on OpenRISC.") ("arch.cpu_cycle_time_ps", po::value(), "Sets CPU cycles time on OpenRISC and ARM.") + ("arch.enable_semihosting", po::value(), "Enables semihosting operations") ("etiss.enable_dmi", po::value(), "Enables the Direct Memory Interface feature of SystemC to speed up memory accesses. This needs to be disabled for memory tracing.") ("etiss.log_pc", po::value(), "Enables logging of the program counter.") ("etiss.max_block_size", po::value(), "Sets maximum amount of instructions in a block.") diff --git a/src/Instruction.cpp b/src/Instruction.cpp index 57c8650c5c..bfe540ebfa 100644 --- a/src/Instruction.cpp +++ b/src/Instruction.cpp @@ -893,19 +893,8 @@ InstructionSet::InstructionSet(VariableInstructionSet &parent, unsigned width, c : parent_(parent), name_(name), width_(width), root_(nullptr), invalid(width, -1, -1, "INVALID") { - invalid.addCallback( - [](BitArray &ba, CodeSet &cs, InstructionContext &ic) { - std::stringstream ss; - ss << "\t\treturn ETISS_RETURNCODE_ILLEGALINSTRUCTION;"; - //#if DEBUG - ss << " // @0x" << std::hex << ic.current_address_ << std::dec << ": " << ba; - //#endif - ss << "\n"; - cs.append(CodePart::APPENDEDRETURNINGREQUIRED).code() = ss.str(); - return true; - }, - 0); } + InstructionSet::~InstructionSet() { delete root_; diff --git a/src/IntegratedLibrary/PrintInstruction.cpp b/src/IntegratedLibrary/PrintInstruction.cpp index b05b295de2..1e22ad61ff 100644 --- a/src/IntegratedLibrary/PrintInstruction.cpp +++ b/src/IntegratedLibrary/PrintInstruction.cpp @@ -110,6 +110,7 @@ extern "C" void PrintInstruction_print(const char *c, uint64_t addr) { std::cout << c; + std::cout.flush(); if (addr == 0x6cac) { // std::cout << "TCOUNT: " << std::dec << ++pi_6cac << "\n"; diff --git a/src/InterruptHandler.cpp b/src/InterruptHandler.cpp index e024d0fd52..c8e45ee58a 100644 --- a/src/InterruptHandler.cpp +++ b/src/InterruptHandler.cpp @@ -53,9 +53,9 @@ using namespace etiss; -InterruptHandler::InterruptHandler(etiss::InterruptVector *interruptVector, std::shared_ptr arch, +InterruptHandler::InterruptHandler(etiss::InterruptVector *interruptVector, etiss::InterruptEnable *interruptEnable, std::shared_ptr arch, InterruptType itype, bool sync) - : itype_(itype), sync_(sync), vector_(interruptVector), cpuarch_(arch) + : itype_(itype), sync_(sync), vector_(interruptVector), enable_(interruptEnable), cpuarch_(arch) { empty_ = true; } @@ -161,7 +161,12 @@ etiss::int32 InterruptHandler::execute() if (sync_) mu_.unlock(); - return (mayinterrupt && vector_->isActive()) ? etiss::RETURNCODE::INTERRUPT : etiss::RETURNCODE::NOERROR; + auto active = vector_->isActive(); + auto enabled = enable_->isEnabled(); + + // std::cout << "active: " << active << ", enabled: " << enabled << std::endl; + + return (mayinterrupt && active && enabled) ? etiss::RETURNCODE::INTERRUPT : etiss::RETURNCODE::NOERROR; } std::string InterruptHandler::_getPluginName() const diff --git a/src/SimpleMemSystem.cpp b/src/SimpleMemSystem.cpp index 5d1cd6c112..a631794607 100644 --- a/src/SimpleMemSystem.cpp +++ b/src/SimpleMemSystem.cpp @@ -175,7 +175,7 @@ void SimpleMemSystem::load_elf() if (reader.get_machine() == EM_RISCV) { if ((reader.get_class() == ELFCLASS64)) { - etiss::cfg().set("arch.cpu", "RISCV64"); // RISCV and OR1K work as well + etiss::cfg().set("arch.cpu", "RV64IMACFD"); // RISCV and OR1K work as well } else if ((reader.get_class() == ELFCLASS32)) { etiss::cfg().set("arch.cpu", "RV32IMACFD"); // add conditions diff --git a/src/Translation.cpp b/src/Translation.cpp index 999fb4d311..0af0974e5a 100644 --- a/src/Translation.cpp +++ b/src/Translation.cpp @@ -321,6 +321,7 @@ BlockLink *Translation::getBlock(BlockLink *prev, const etiss::uint64 &instructi block.fileglobalCode().insert("#include \"etiss/jit/CPU.h\"\n" "#include \"etiss/jit/System.h\"\n" "#include \"etiss/jit/libresources.h\"\n" + "#include \"etiss/jit/libsemihost.h\"\n" "#include \"etiss/jit/ReturnCode.h\"\n" "#include \"etiss/jit/libCSRCounters.h\"\n"); @@ -370,6 +371,7 @@ BlockLink *Translation::getBlock(BlockLink *prev, const etiss::uint64 &instructi std::set libs; //libs.insert("ETISS"); libs.insert("resources"); + libs.insert("semihost"); libs.insert("CSRCounters"); for(auto & it: jitExtLibraries()){ if(it != "") libs.insert(it); @@ -474,18 +476,19 @@ etiss::int32 Translation::translateBlock(CodeBlock &cb) context.is_not_default_width_ = false; context.instr_width_ = vis_->width_; + etiss::instr::BitArray errba(32, 0); + // read instruction etiss::int32 ret = (*system_.dbg_read)(system_.handle, cb.endaddress_, (etiss_uint8 *)mainba.internalBuffer(), mainba.byteCount()); // read instruction - if (ret == etiss::RETURNCODE::IBUS_READ_ERROR) + if (ret == etiss::RETURNCODE::IBUS_READ_ERROR || ret == etiss::RETURNCODE::DBUS_READ_ERROR) { std::cout << "Instruction bus read error while translating!" << std::endl; - CodeBlock::Line &line = cb.append(cb.endaddress_); // allocate codeSet for Instruction - line.getCodeSet().append(CodePart::PREINITIALDEBUGRETURNING).code() = - std::string("cpu->cpuTime_ps += " - "cpu->cpuCycleTime_ps;cpu->instructionPointer += ") + - std::to_string(mainba.byteCount()) + std::string(";return ETISS_RETURNCODE_IBUS_READ_ERROR;"); + errba = etiss::RETURNCODE::IBUS_READ_ERROR; // std::cout << "mainba.byteCount = " << mainba.byteCount() << std::endl; + auto instr = &vis_->getMain()->getInvalid(); + CodeBlock::Line &line = cb.append(cb.endaddress_); // allocate codeset for instruction + bool ok = instr->translate(errba, line.getCodeSet(), context); cb.endaddress_ += mainba.byteCount(); // update end address return etiss::RETURNCODE::NOERROR; } @@ -538,6 +541,7 @@ etiss::int32 Translation::translateBlock(CodeBlock &cb) etiss::instr::InstructionSet *instrSet = vis_->get(secba->width()); if (unlikely(!instrSet)) { + errba = etiss::RETURNCODE::ILLEGALINSTRUCTION; instr = &vis_->getMain()->getInvalid(); } else @@ -545,11 +549,12 @@ etiss::int32 Translation::translateBlock(CodeBlock &cb) instr = instrSet->resolve(*secba); if (unlikely(!instr)) { + errba = etiss::RETURNCODE::ILLEGALINSTRUCTION; instr = &instrSet->getInvalid(); } } CodeBlock::Line &line = cb.append(cb.endaddress_); // allocate codeset for instruction - bool ok = instr->translate(*secba, line.getCodeSet(), context); + bool ok = instr->translate(errba != etiss::instr::BitArray(32, 0) ? errba : *secba, line.getCodeSet(), context); if (unlikely(!ok)) { delete secba; @@ -564,10 +569,11 @@ etiss::int32 Translation::translateBlock(CodeBlock &cb) etiss::instr::Instruction *instr = instrSet->resolve(mainba); if (unlikely(instr == 0)) { + errba = etiss::RETURNCODE::ILLEGALINSTRUCTION; instr = &instrSet->getInvalid(); } CodeBlock::Line &line = cb.append(cb.endaddress_); // allocate codeset for instruction - bool ok = instr->translate(mainba, line.getCodeSet(), context); + bool ok = instr->translate(errba != etiss::instr::BitArray(32, 0) ? errba : mainba, line.getCodeSet(), context); if (unlikely(!ok)) { return etiss::RETURNCODE::GENERALERROR; @@ -581,8 +587,33 @@ etiss::int32 Translation::translateBlock(CodeBlock &cb) return etiss::RETURNCODE::NOERROR; } +void Translation::unloadBlocksAll() +{ + for (auto &entry:blockmap_) + { + entry.second.erase(std::remove_if(entry.second.begin(), entry.second.end(), + [](auto &bl) + { + bl->valid = false; + BlockLink::updateRef(bl->next, 0); + BlockLink::updateRef(bl->branch, 0); + BlockLink::decrRef(bl); // remove reference of map + return true; + }), + entry.second.end()); + } + blockmap_.clear(); +} + void Translation::unloadBlocks(etiss::uint64 startindex, etiss::uint64 endindex) { + // Hotfix: if everything needs to be deleted, new function unloadBlocksAll() + if (startindex == 0 && endindex == ((etiss::uint64)((etiss::int64)-1))) + { + unloadBlocksAll(); + return; + } + const etiss::uint64 startindexblock = startindex >> 9; const etiss::uint64 endindexblock = (endindex >> 9) + ((((endindex >> 9) << 9) == endindex) ? 0 : 1); for (etiss::uint64 block = startindexblock; block < endindexblock; block++) diff --git a/src/bare_etiss_processor/ETISS.ini b/src/bare_etiss_processor/ETISS.ini index 42feed3115..438d671619 100644 --- a/src/bare_etiss_processor/ETISS.ini +++ b/src/bare_etiss_processor/ETISS.ini @@ -77,6 +77,11 @@ etiss.load_integrated_libraries=true + ; Exit simulation if infinite loop-to-self is detected + ; default = false + + etiss.exit_on_loop=false + ;Causes the JIT Engines to compile in debug mode ; default = false diff --git a/src/bare_etiss_processor/main.cpp b/src/bare_etiss_processor/main.cpp index ba60edf0f5..895abd6b67 100644 --- a/src/bare_etiss_processor/main.cpp +++ b/src/bare_etiss_processor/main.cpp @@ -121,6 +121,10 @@ int main(int argc, const char *argv[]) std::cout << "=== Finished Setting up test system ===" << std::endl << std::endl; std::cout << "=== Setting up plug-ins ===" << std::endl; + + auto irq_handler = std::make_shared(cpu->getInterruptVector(), cpu->getInterruptEnable(), cpu->getArch(), etiss::LEVEL_TRIGGERED, false); + cpu->addPlugin(irq_handler); + initializer.loadIniPlugins(cpu); initializer.loadIniJIT(cpu); // here own developped plug-ins can be added with: diff --git a/src/jitlibs/CMakeLists.txt b/src/jitlibs/CMakeLists.txt index 0ab8415c91..292e2267ed 100644 --- a/src/jitlibs/CMakeLists.txt +++ b/src/jitlibs/CMakeLists.txt @@ -1,7 +1,9 @@ MACRO(InstallJitLib TARGET_NAME) + set_property(GLOBAL APPEND PROPERTY etiss_jitlibs ${TARGET_NAME}) INSTALL(TARGETS ${TARGET_NAME} DESTINATION include/jit/etiss/jit) ENDMACRO() ADD_SUBDIRECTORY(softfloat) ADD_SUBDIRECTORY(resources) -ADD_SUBDIRECTORY(CSRCounters) \ No newline at end of file +ADD_SUBDIRECTORY(semihost) +ADD_SUBDIRECTORY(CSRCounters) diff --git a/src/jitlibs/semihost/CMakeLists.txt b/src/jitlibs/semihost/CMakeLists.txt new file mode 100644 index 0000000000..9ae2fc0b01 --- /dev/null +++ b/src/jitlibs/semihost/CMakeLists.txt @@ -0,0 +1,25 @@ +PROJECT(semihost) + +IF(WIN32) + SET(CMAKE_WINDOWS_EXPORT_ALL_SYMBOLS ON) +ENDIF() + +ADD_LIBRARY(${PROJECT_NAME} SHARED + semihost.cpp +) + + +add_custom_command( + TARGET ${PROJECT_NAME} POST_BUILD VERBATIM + COMMAND ${CMAKE_COMMAND} -E make_directory ${ETISS_BINARY_DIR}/include/jit/etiss/jit/ + COMMAND ${CMAKE_COMMAND} -E copy "$" ${ETISS_BINARY_DIR}/include/jit/etiss/jit/ +) + + +TARGET_LINK_LIBRARIES(${PROJECT_NAME} PUBLIC ETISS) + +INSTALL(FILES + libsemihost.h + DESTINATION include/jit/etiss/jit +) +InstallJitLib(${PROJECT_NAME}) diff --git a/src/jitlibs/semihost/SemihostingCalls.h b/src/jitlibs/semihost/SemihostingCalls.h new file mode 100644 index 0000000000..5b705b8797 --- /dev/null +++ b/src/jitlibs/semihost/SemihostingCalls.h @@ -0,0 +1,32 @@ +#ifndef ETISS_INCLUDE_SEMIHOSTING_CALLS_H_ +#define ETISS_INCLUDE_SEMIHOSTING_CALLS_H_ + +// taken from +// https://github.com/ARM-software/abi-aa/releases/download/2022Q1/semihosting.pdf + +#define SYS_OPEN 0x01 +#define SYS_CLOSE 0x02 +#define SYS_WRITEC 0x03 +#define SYS_WRITE0 0x04 +#define SYS_WRITE 0x05 +#define SYS_READ 0x06 +#define SYS_READC 0x07 +#define SYS_ISERROR 0x08 +#define SYS_ISTTY 0x09 +#define SYS_SEEK 0x0A +#define SYS_FLEN 0x0C +#define SYS_TMPNAM 0x0D +#define SYS_REMOVE 0x0E +#define SYS_RENAME 0x0F +#define SYS_CLOCK 0x10 +#define SYS_TIME 0x11 +#define SYS_SYSTEM 0x12 +#define SYS_ERRNO 0x13 +#define SYS_GET_CMDLINE 0x15 +#define SYS_HEAPINFO 0x16 +#define SYS_EXIT 0x18 +#define SYS_EXIT_EXTENDED 0x20 +#define SYS_ELAPSED 0x30 +#define SYS_TICKFREQ 0x31 + +#endif diff --git a/src/jitlibs/semihost/libsemihost.h b/src/jitlibs/semihost/libsemihost.h new file mode 100644 index 0000000000..019a8bc614 --- /dev/null +++ b/src/jitlibs/semihost/libsemihost.h @@ -0,0 +1,17 @@ +#ifndef JITLIB_SEMIHOST_H +#define JITLIB_SEMIHOST_H + +#include +#include "etiss/jit/CPU.h" +#include "etiss/jit/System.h" + +/// Checks whether semihosting is enabled in the config +uint8_t etiss_semihost_enabled(); + +/// Executes the semihosting call based on the operation number. +/// For description of all semihosting calls see: +/// https://github.com/ARM-software/abi-aa/blob/main/semihosting/semihosting.rst +int64_t etiss_semihost(ETISS_CPU *const cpu, ETISS_System *const etissSystem, void *const *const _, uint32_t XLEN, + uint64_t operation, uint64_t parameter); + +#endif diff --git a/src/jitlibs/semihost/semihost.cpp b/src/jitlibs/semihost/semihost.cpp new file mode 100644 index 0000000000..964a897030 --- /dev/null +++ b/src/jitlibs/semihost/semihost.cpp @@ -0,0 +1,439 @@ +#include +#include "etiss/ETISS.h" + +#include "SemihostingCalls.h" + +extern "C" +{ +#include "libsemihost.h" +} + +// constant for SYS_ELAPSED and SYS_TICKFREQ +#define TICKER_FREQ 1000 // Hz + +// constants for SYS_OPEN +const char *SYS_OPEN_MODES_STRS[] = { "r", "rb", "r+", "r+b", "w", "wb", "w+", "w+b", "a", "ab", "a+", "a+b" }; +#define SYS_OPEN_MODES_TOTAL 12 // total number of modes +#define SYS_OPEN_MODES_IN_LIMIT 4 +#define SYS_OPEN_MODES_OUT_LIMIT 8 + +#define PS_PER_CS 10000000000 // 10 * 10^9 + +// if var is negative set semihosting errno and return -1 +#define CHECK_NEGATIVE_RETURN(var) \ + if ((var) < 0) \ + { \ + semihostingErrno = errno; \ + return -1; \ + } + +// For many semihosting calls parameter points to a data block, so this type of call is very common +#define FIELD(fieldNo) semihostReadStructField(etissSystem, XLEN / 8, parameter, fieldNo); + +// forward declaration for use in extern block: + +/// Executes the semihosting call based on the operation number. +/// For description of all semihosting calls see: +/// https://github.com/ARM-software/abi-aa/blob/main/semihosting/semihosting.rst +etiss_int64 semihostingCall(ETISS_CPU *const cpu, ETISS_System *const etissSystem, etiss_uint32 XLEN, + etiss_uint64 operationNumber, etiss_uint64 parameter); + +extern "C" +{ + uint8_t etiss_semihost_enabled() + { + return etiss::cfg().get("arch.enable_semihosting", false); + } + + int64_t etiss_semihost(ETISS_CPU *const cpu, ETISS_System *const etissSystem, void *const *const _, uint32_t XLEN, + uint64_t operation, uint64_t parameter) + { + return semihostingCall(cpu, etissSystem, XLEN, operation, parameter); + } +} + +/// Assumes there is an array of numBytes long integers at address. +/// Reads the filedNo-th field of this array an returns it as a uint64 +/// (0-indexed) +etiss_uint64 semihostReadStructField(ETISS_System *etissSystem, etiss_uint32 numBytes, etiss_uint64 address, + int fieldNo) +{ + if (numBytes == 8) + { + etiss_uint64 field = 0; + etissSystem->dbg_read(etissSystem->handle, address + 8 * fieldNo, (etiss_uint8 *)&field, 8); + return field; + } + else if (numBytes == 4) + { + etiss_uint32 field = 0; + etissSystem->dbg_read(etissSystem->handle, address + 4 * fieldNo, (etiss_uint8 *)&field, 4); + return field; + } + else if (numBytes == 2) + { + etiss_uint16 field = 0; + etissSystem->dbg_read(etissSystem->handle, address + 2 * fieldNo, (etiss_uint8 *)&field, 2); + return field; + } + else if (numBytes == 1) + { + etiss_uint8 field = 0; + etissSystem->dbg_read(etissSystem->handle, address + 1 * fieldNo, &field, 1); + return field; + } + + etiss::log(etiss::ERROR, "semihostReadStructField called with numBytes != 1, 2, 4 or 8"); + return 0; +} + +/// helper for reading a std::vector of bytes by address and length from an etiss system +std::vector semihostReadSystemMemory(ETISS_System *etissSystem, etiss_uint64 address, etiss_uint64 length) +{ + std::vector buffer; + buffer.resize(length); + etissSystem->dbg_read(etissSystem->handle, address, buffer.data(), length); + return buffer; +} + +/// helper for writing a std::vector of bytes to an etiss system +void semihostWriteSystemMemory(ETISS_System *etissSystem, etiss_uint64 address, std::vector data) +{ + etissSystem->dbg_write(etissSystem->handle, address, data.data(), data.size()); +} + +/// helper for reading a std::string by address and length from an etiss system +std::string semihostReadString(ETISS_System *etissSystem, etiss_uint64 address, etiss_uint64 length) +{ + std::vector buffer = semihostReadSystemMemory(etissSystem, address, length); + std::string str(buffer.begin(), buffer.end()); + return str; +} + +/// helper for writing a std::string to an etiss system +void semihostWriteString(ETISS_System *etissSystem, etiss_uint64 address, std::string str) +{ + etissSystem->dbg_write(etissSystem->handle, address, (etiss_uint8 *)str.c_str(), str.length() + 1); +} + +bool is_std_in_out_err(FILE *file) +{ + return file == stdin || file == stdout || file == stderr; +} + +etiss_int64 semihostingCall(ETISS_CPU *const cpu, ETISS_System *const etissSystem, etiss_uint32 XLEN, + etiss_uint64 operationNumber, etiss_uint64 parameter) +{ + // static variables to keep track of semihosting state + + /// openFiles maps target file descriptors (uint) to host + /// file descriptors (FILE *). + static std::map openFiles; + /// next target file descriptor to be allocated. + /// starts at 0 for first target fd (stdin) + static etiss_uint64 nextFd = 0; + /// Local errno variable to set in semihosting functions + /// and return using SYS_ERRNO + static etiss_int64 semihostingErrno; + + switch (operationNumber) + { + // share code between all operations that have the + // file descriptor as their first argument + case SYS_CLOSE: + case SYS_WRITE: + case SYS_READ: + case SYS_ISTTY: + case SYS_SEEK: + case SYS_FLEN: + { + etiss_uint64 fd = FIELD(0); + if (openFiles.count(fd) == 0) + { + std::stringstream ss; + ss << "Semihosting: invalid file descriptor " << fd << " for semihosting call 0x" << std::hex + << std::setfill('0') << std::setw(2) << operationNumber; + etiss::log(etiss::INFO, ss.str()); + semihostingErrno = EBADF; + return -1; + } + auto file = openFiles[fd]; + + switch (operationNumber) + { + case SYS_CLOSE: + { + std::stringstream ss; + ss << "Semihosting: SYS_CLOSE fd " << fd; + etiss::log(etiss::VERBOSE, ss.str()); + + openFiles.erase(fd); + // do not close stdin, stdout, stderr of host process + if (!is_std_in_out_err(file)) + fclose(file); + return 0; + } + case SYS_WRITE: + { + etiss_uint64 address = FIELD(1); + etiss_uint64 count = FIELD(2); + + std::stringstream ss; + ss << "Semihosting: SYS_WRITE fd " << fd; + etiss::log(etiss::VERBOSE, ss.str()); + + std::vector buffer = semihostReadSystemMemory(etissSystem, address, count); + + size_t num_written = fwrite(buffer.data(), 1, count, file); + return count - num_written; + } + case SYS_READ: + { + etiss_uint64 address = FIELD(1); + etiss_uint64 count = FIELD(2); + + std::stringstream ss; + ss << "Semihosting: SYS_READ fd " << fd << " count " << count; + etiss::log(etiss::VERBOSE, ss.str()); + + std::vector buffer; + buffer.resize(count); + + size_t num_read = 0; + if (file == stdin) + { + // when reading from stdin: mimic behaviour from read syscall + // and return on newline. + while (num_read < count) + { + char c = fgetc(file); + buffer[num_read] = c; + num_read++; + if (c == '\n') + break; + } + } + else + { + num_read = fread(buffer.data(), 1, count, file); + } + + buffer.resize(num_read); + semihostWriteSystemMemory(etissSystem, address, buffer); + + return (etiss_int64)count - num_read; + } + case SYS_ISTTY: + { + std::stringstream ss; + ss << "Semihosting: SYS_ISTTY fd " << fd; + etiss::log(etiss::VERBOSE, ss.str()); + + return is_std_in_out_err(file); + } + case SYS_SEEK: + { + etiss_uint64 position = FIELD(1); + + std::stringstream ss; + ss << "Semihosting: SYS_SEEK fd " << fd << ": " << position; + etiss::log(etiss::VERBOSE, ss.str()); + + int retval = fseek(file, position, SEEK_SET); + CHECK_NEGATIVE_RETURN(retval); + return 0; + } + case SYS_FLEN: + { + std::stringstream ss; + ss << "Semihosting: SYS_FLEN fd " << fd; + etiss::log(etiss::VERBOSE, ss.str()); + + size_t currentPos = ftell(file); + CHECK_NEGATIVE_RETURN(currentPos); + fseek(file, 0, SEEK_END); + size_t length = ftell(file); + fseek(file, currentPos, SEEK_SET); + return (etiss_int64)length; + } + } + } + case SYS_OPEN: + { + etiss_uint64 path_str_addr = FIELD(0); + etiss_uint64 mode = FIELD(1); + etiss_uint64 path_str_len = FIELD(2); + + std::string path_str = semihostReadString(etissSystem, path_str_addr, path_str_len); + + std::stringstream ss; + ss << "Semihosting: SYS_OPEN \"" << path_str << "\""; + etiss::log(etiss::VERBOSE, ss.str()); + + if (mode >= SYS_OPEN_MODES_TOTAL) + { + // invalid mode + semihostingErrno = EINVAL; + return -1; + } + + FILE *file = nullptr; + if (path_str == ":tt") + { + // special file path for opening stdin, stdout and stderr + // open stdin, stdout or stderr depending on mode argument + if (mode < SYS_OPEN_MODES_IN_LIMIT) // 0 <= mode <= 3 + file = stdin; + else if (mode < SYS_OPEN_MODES_OUT_LIMIT) // 4 <= mode <= 7 + file = stdout; + else // 8 <= mode <= 11 + file = stderr; + } + else + { + file = fopen(path_str.c_str(), SYS_OPEN_MODES_STRS[mode]); + if (file == nullptr) + { + semihostingErrno = errno; + return -1; + } + } + etiss_uint64 fd = nextFd++; + openFiles[fd] = file; + + return (etiss_int64)fd; + } + case SYS_WRITEC: + { + etiss_uint64 character = semihostReadStructField(etissSystem, 1, parameter, 0); + putchar(character); + return 0; + } + case SYS_WRITE0: + { + etiss_uint64 address = parameter; + while (1) + { + etiss_uint64 character = semihostReadStructField(etissSystem, 1, address, 0); + if (character == 0) + break; + putchar(character); + address++; + } + return 0; + } + case SYS_READC: + { + return getchar(); + } + case SYS_ISERROR: + { + etiss_uint64 value = FIELD(0); + return value != 0; + } + case SYS_TMPNAM: + { + etiss_uint64 buffer_address = FIELD(0); + etiss_uint64 identifier = FIELD(1); + etiss_uint64 buffer_len = FIELD(2); + + if (identifier > 255) + return -1; + + std::stringstream ss; + ss << "etiss-tmp/file-" << std::setfill('0') << std::setw(3) << identifier; + std::string filename = ss.str(); + + if (buffer_len <= filename.length() + 1) + return -1; + + semihostWriteString(etissSystem, buffer_address, filename); + return 0; + } + case SYS_REMOVE: + { + etiss_uint64 path_str_addr = FIELD(0); + etiss_uint64 path_str_len = FIELD(1); + + std::string path_str = semihostReadString(etissSystem, path_str_addr, path_str_len); + + std::stringstream ss; + ss << "Semihosting: SYS_REMOVE \"" << path_str << "\""; + etiss::log(etiss::VERBOSE, ss.str()); + + if (remove(path_str.c_str()) < 0) + { + semihostingErrno = errno; + return -1; + } + return 0; + } + case SYS_RENAME: + { + etiss_uint64 old_str_addr = FIELD(0); + etiss_uint64 old_str_len = FIELD(1); + etiss_uint64 new_str_addr = FIELD(2); + etiss_uint64 new_str_len = FIELD(3); + + std::string old_str = semihostReadString(etissSystem, old_str_addr, old_str_len); + std::string new_str = semihostReadString(etissSystem, new_str_addr, new_str_len); + + std::stringstream ss; + ss << "Semihosting: SYS_RENAME \"" << old_str << "\" to \"" << new_str << "\""; + etiss::log(etiss::VERBOSE, ss.str()); + + return rename(old_str.c_str(), new_str.c_str()); + } + case SYS_CLOCK: + { + // return centiseconds since some arbitrary start point + return cpu->cpuTime_ps / PS_PER_CS; + } + case SYS_TIME: + { + etiss::log(etiss::VERBOSE, "Semihosting: SYS_TIME"); + etiss_int64 seconds_since_epoch = (etiss_int64)std::time(0); + return seconds_since_epoch; + } + case SYS_ERRNO: + { + std::stringstream ss; + ss << "Semihosting: SYS_ERRNO (" << semihostingErrno << ")"; + etiss::log(etiss::VERBOSE, ss.str()); + return semihostingErrno; + } + case SYS_EXIT: + { + etiss::log(etiss::VERBOSE, "Semihosting: SYS_EXIT -> exit simulator"); + + cpu->exception = ETISS_RETURNCODE_CPUFINISHED; + cpu->return_pending = 1; + return 0; + } + case SYS_ELAPSED: + { + return cpu->cpuTime_ps / TICKER_FREQ; + } + case SYS_TICKFREQ: + { + return TICKER_FREQ; + } + case SYS_SYSTEM: + case SYS_GET_CMDLINE: + case SYS_HEAPINFO: + case SYS_EXIT_EXTENDED: + { + std::stringstream ss; + ss << "Semihosting: operation not implemented: " << operationNumber; + etiss::log(etiss::WARNING, ss.str()); + return 0; + } + default: + { + std::stringstream ss; + ss << "Semihosting: unknown operation number: " << operationNumber; + etiss::log(etiss::WARNING, ss.str()); + return 0; + } + } +} diff --git a/src/jitlibs/semihost/semihosting.md b/src/jitlibs/semihost/semihosting.md new file mode 100644 index 0000000000..e02d8d7018 --- /dev/null +++ b/src/jitlibs/semihost/semihosting.md @@ -0,0 +1,33 @@ +# Semihosting in ETISS + +This JitLib offers semihosting to features to architectures in ETISS. +The specific semihosting calls implemented by this library are used by Arm and RISC-V (https://github.com/ARM-software/abi-aa/blob/main/semihosting/semihosting.rst, https://github.com/riscv/riscv-semihosting-spec/blob/main/riscv-semihosting-spec.adoc). + +The JitLib provides the functions `etiss_semihost_enabled` and `etiss_semihost`. +The former returns the value of the config option `arch.enable_semihosting` and is called by the architectures prior to executing a semihosting call. +The latter is the actual semihosting implementation. +It is called with the values of the operation and parameter registers, executes the semihosting call, and returns the value of the return register. +For technical reasons also the bit-width of the architecture, the `ETISS_CPU` and the `ETISS_SYSTEM` are passed to this function. + +The JitLib keeps track of some minimal state, such as the open file descriptors. + +Semihosting can be used to exit from the simulator. +For this, the semihosting call `SYS_EXIT` is used. +Internally, it sets the exception variable of the CPU to `ETISS_RETURNCODE_CPUFINISHED` and `return_pending` to 1. + +# CoreDSL Implementation for RISC-V + +For RISC-V the instruction sequence +``` +slli x0, x0, 0x1f # 0x01f01013 Entry NOP +ebreak # 0x00100073 Break to debugger +srai x0, x0, 7 # 0x40705013 NOP encoding the semihosting call number 7 +``` +is used to execute the semihosting call. + +In the CoreDSL code we override the `ebreak` instruction. +It first checks whether semihosting is enabled and, if so, checks whether the instruction before and after match the required sequence. +If they match this JitLib will be called with the values of the `a0` and the `a1` registers as the operation and parameter arguments. +After this function return the return value is written to register `a0`. + +In case semihosting is disabled, or the instruction sequence does not match, the normal action for `ebreak` is executed: raising a breakpoint exception. diff --git a/src/mm/MMU.cpp b/src/mm/MMU.cpp index 04643cf335..b57de82c76 100644 --- a/src/mm/MMU.cpp +++ b/src/mm/MMU.cpp @@ -264,6 +264,8 @@ extern "C" "indirectly from ETISS_signalChangedRegisterValue()"); return; } - core->getMMU()->SignalMMU(mmu_signal_); + auto mmu = core->getMMU(); + if (mmu) + mmu->SignalMMU(mmu_signal_); } }